| blob | b9b55d955ea86b47f801a65bb199e8ac6df42a16 |
1 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
3 PR target/114232
4 * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
5 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
6 (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
7 (<plusminus:insn>v2qi3): Enable for optimize_size instead
8 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
9 (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
10 (<any_shift:insn>v2qi3): Enable for optimize_size instead
11 of optimize_function_for_size_p.
13 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
15 PR target/114200
16 PR target/114202
17 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
19 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
21 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
22 (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
23 offset handling.
24 (costs::add_stmt_cost): Also adjust cost for statements without
25 stmt_info.
26 * config/riscv/riscv-vector-costs.h: Define zero constant.
28 2024-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
30 PR target/113915
31 * config/arm/arm.md (NOCOND): Improve comment.
32 (arm_rev*) Add predicable.
33 * config/arm/arm.cc (arm_final_prescan_insn): Add check for
34 PREDICABLE_YES.
36 2024-03-06 Jeff Law <jlaw@ventanamicro.com>
38 PR target/113001
39 PR target/112871
40 * config/riscv/riscv.cc (expand_conditional_move): Do not swap
41 operands when the comparison operand is the same as the false
42 arm for a NE test.
44 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
46 * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
47 Eliminate common code and use generic code instead.
49 2024-03-06 Georg-Johann Lay <avr@gjlay.de>
51 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
52 rtx cost.
54 2024-03-06 Richard Biener <rguenther@suse.de>
56 PR tree-optimization/114239
57 * tree-vect-loop.cc (vect_get_vect_def): Remove.
58 (vect_create_epilog_for_reduction): The passed in stmt_info
59 should now be the live stmt that produces the scalar reduction
60 result. Revert PR114192 fix. Base reduction info off
61 info_for_reduction. Remove special handling of
62 early-break/peeled, restore original vector def gathering.
63 Make sure to pick the correct exit PHIs.
64 (vectorizable_live_operation): Pass in the proper stmt_info
65 for early break exits.
67 2024-03-06 Richard Sandiford <richard.sandiford@arm.com>
69 * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
70 out-of-class definitions of static constants.
72 2024-03-06 Richard Biener <rguenther@suse.de>
74 PR tree-optimization/114249
75 * tree-vect-slp.cc (vect_build_slp_instance): Move making
76 a BB reduction lane number even ...
77 (vect_slp_check_for_roots): ... here to avoid leaking
78 pattern defs.
80 2024-03-06 Richard Biener <rguenther@suse.de>
82 PR tree-optimization/114246
83 * tree-ssa-dse.cc (increment_start_addr): Strip useless
84 type conversions from the adjusted address.
86 2024-03-06 Jakub Jelinek <jakub@redhat.com>
88 PR rtl-optimization/114190
89 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
90 Call df_remove_problem for df_note before calling df_analyze.
92 2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
93 Indu Bhagat <indu.bhagat@oracle.com>
95 PR debug/114186
96 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
97 in the correct order of the dimensions.
98 (gen_ctf_subrange_type): Refactor out handling of
99 DW_TAG_subrange_type DIE to here.
101 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
103 PR sanitizer/97696
104 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
106 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
108 * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
109 and luti_strided.
110 * config/aarch64/aarch64-sme.md
111 (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
112 (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
113 (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
114 * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
115 (early_ra::maybe_convert_to_strided_access): Remove support for
116 strided LUTI2 and LUTI4.
118 2024-03-05 Richard Earnshaw <rearnsha@arm.com>
120 PR target/113510
121 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
122 low_register_operand.
124 2024-03-05 Georg-Johann Lay <avr@gjlay.de>
126 * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
127 in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
128 to "X = Y, X o= CST".
130 2024-03-05 Xi Ruoyao <xry111@xry111.site>
132 * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
133 s9 as an alias of r22.
135 2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
137 * config/avr/avr-protos.h (avr_out_insv): New proto.
138 * config/avr/avr.cc (avr_out_insv): New function.
139 (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
140 (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
141 * config/avr/avr.md (define_attr "adjust_len") Add insv.
142 (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
143 Add constraint alternative where the 3rd operand is a power
144 of 2, and the source register may differ from the destination.
145 (*insv.any_shift.<mode>_split): Call avr_out_insv to output
146 instructions. Set attr "length" to "insv".
147 * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
149 2024-03-05 Richard Biener <rguenther@suse.de>
151 PR tree-optimization/114231
152 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
153 processing a BB SLP root.
155 2024-03-05 Jakub Jelinek <jakub@redhat.com>
157 PR rtl-optimization/114211
158 * lower-subreg.cc (resolve_simple_move): For double-word
159 rotates by BITS_PER_WORD if there is overlap between source
160 and destination use a temporary.
162 2024-03-05 Jakub Jelinek <jakub@redhat.com>
164 PR middle-end/114157
165 * gimple-lower-bitint.cc: Include stor-layout.h.
166 (mergeable_op): Return true for BIT_FIELD_REF.
167 (struct bitint_large_huge): Declare handle_bit_field_ref method.
168 (bitint_large_huge::handle_bit_field_ref): New method.
169 (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
171 2024-03-05 Jakub Jelinek <jakub@redhat.com>
173 PR target/114116
174 * config/i386/i386.h (enum call_saved_registers_type): Add
175 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
176 * config/i386/i386-options.cc (ix86_set_func_type): Remove
177 has_no_callee_saved_registers variable, add no_callee_saved_registers
178 instead, initialize it depending on whether it is
179 no_callee_saved_registers function or not. Don't set it if
180 no_caller_saved_registers attribute is present. Adjust users.
181 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
182 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
183 TYPE_NO_CALLEE_SAVED_REGISTERS.
184 (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
186 2024-03-05 Pan Li <pan2.li@intel.com>
188 * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
189 mode_size related code.
191 2024-03-05 Patrick Palka <ppalka@redhat.com>
193 * doc/invoke.texi (-Wno-global-module): Document.
195 2024-03-04 David Faust <david.faust@oracle.com>
197 * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
198 * config/bpf/bpf.cc (bpf_expand_setmem): New.
199 * config/bpf/bpf.md (setmemdi): New define_expand.
201 2024-03-04 Jakub Jelinek <jakub@redhat.com>
203 PR rtl-optimization/113010
204 * combine.cc (simplify_comparison): Guard the
205 WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
206 and initialize inner_mode.
208 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
210 * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
211 VMLALDAVAXQ_U cases.
212 (VMLALDAVXQ): Remove iterator.
213 (VMLALDAVXQ_P): Likewise.
214 (VMLALDAVAXQ): Likewise.
215 * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
216 mode iterator attribute with V4BI mode.
217 * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
218 VMLALDAVAXQ_U): Remove unused unspecs.
220 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
222 * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
223 * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
224 attribute.
225 * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
226 vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
227 vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
228 vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
229 vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
230 vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
231 vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
232 vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
233 vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
234 vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
236 2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
238 * config/arm/arm.md (mve_unpredicated_insn): New attribute.
239 * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
240 (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
241 (MVE_VPT_PREDICABLE_INSN_P): Likewise.
242 * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
243 * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
244 (arm_vcx1q<a>v16qi): Likewise.
245 (arm_vcx1qav16qi): Likewise.
246 (arm_vcx1qv16qi): Likewise.
247 (arm_vcx2q<a>_p_v16qi): Likewise.
248 (arm_vcx2q<a>v16qi): Likewise.
249 (arm_vcx2qav16qi): Likewise.
250 (arm_vcx2qv16qi): Likewise.
251 (arm_vcx3q<a>_p_v16qi): Likewise.
252 (arm_vcx3q<a>v16qi): Likewise.
253 (arm_vcx3qav16qi): Likewise.
254 (arm_vcx3qv16qi): Likewise.
255 (@mve_<mve_insn>q_<supf><mode>): Likewise.
256 (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
257 (@mve_<mve_insn>q_<supf>v4si): Likewise.
258 (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
259 (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
260 (@mve_<mve_insn>q_f<mode>): Likewise.
261 (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
262 (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
263 (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
264 (@mve_<mve_insn>q_m_f<mode>): Likewise.
265 (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
266 (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
267 (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
268 (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
269 (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
270 (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
271 (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
272 (mve_v<absneg_str>q_f<mode>): Likewise.
273 (mve_<mve_addsubmul>q<mode>): Likewise.
274 (mve_<mve_addsubmul>q_f<mode>): Likewise.
275 (mve_vadciq_<supf>v4si): Likewise.
276 (mve_vadciq_m_<supf>v4si): Likewise.
277 (mve_vadcq_<supf>v4si): Likewise.
278 (mve_vadcq_m_<supf>v4si): Likewise.
279 (mve_vandq_<supf><mode>): Likewise.
280 (mve_vandq_f<mode>): Likewise.
281 (mve_vandq_m_<supf><mode>): Likewise.
282 (mve_vandq_m_f<mode>): Likewise.
283 (mve_vandq_s<mode>): Likewise.
284 (mve_vandq_u<mode>): Likewise.
285 (mve_vbicq_<supf><mode>): Likewise.
286 (mve_vbicq_f<mode>): Likewise.
287 (mve_vbicq_m_<supf><mode>): Likewise.
288 (mve_vbicq_m_f<mode>): Likewise.
289 (mve_vbicq_m_n_<supf><mode>): Likewise.
290 (mve_vbicq_n_<supf><mode>): Likewise.
291 (mve_vbicq_s<mode>): Likewise.
292 (mve_vbicq_u<mode>): Likewise.
293 (@mve_vclzq_s<mode>): Likewise.
294 (mve_vclzq_u<mode>): Likewise.
295 (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
296 (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
297 (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
298 (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
299 (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
300 (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
301 (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
302 (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
303 (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
304 (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
305 (mve_vcvtaq_<supf><mode>): Likewise.
306 (mve_vcvtaq_m_<supf><mode>): Likewise.
307 (mve_vcvtbq_f16_f32v8hf): Likewise.
308 (mve_vcvtbq_f32_f16v4sf): Likewise.
309 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
310 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
311 (mve_vcvtmq_<supf><mode>): Likewise.
312 (mve_vcvtmq_m_<supf><mode>): Likewise.
313 (mve_vcvtnq_<supf><mode>): Likewise.
314 (mve_vcvtnq_m_<supf><mode>): Likewise.
315 (mve_vcvtpq_<supf><mode>): Likewise.
316 (mve_vcvtpq_m_<supf><mode>): Likewise.
317 (mve_vcvtq_from_f_<supf><mode>): Likewise.
318 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
319 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
320 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
321 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
322 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
323 (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
324 (mve_vcvtq_to_f_<supf><mode>): Likewise.
325 (mve_vcvttq_f16_f32v8hf): Likewise.
326 (mve_vcvttq_f32_f16v4sf): Likewise.
327 (mve_vcvttq_m_f16_f32v8hf): Likewise.
328 (mve_vcvttq_m_f32_f16v4sf): Likewise.
329 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
330 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
331 (mve_veorq_s><mode>): Likewise.
332 (mve_veorq_u><mode>): Likewise.
333 (mve_veorq_f<mode>): Likewise.
334 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
335 (mve_vidupq_u<mode>_insn): Likewise.
336 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
337 (mve_viwdupq_wb_u<mode>_insn): Likewise.
338 (mve_vldrbq_<supf><mode>): Likewise.
339 (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
340 (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
341 (mve_vldrbq_z_<supf><mode>): Likewise.
342 (mve_vldrdq_gather_base_<supf>v2di): Likewise.
343 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
344 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
345 (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
346 (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
347 (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
348 (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
349 (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
350 (mve_vldrhq_<supf><mode>): Likewise.
351 (mve_vldrhq_fv8hf): Likewise.
352 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
353 (mve_vldrhq_gather_offset_fv8hf): Likewise.
354 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
355 (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
356 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
357 (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
358 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
359 (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
360 (mve_vldrhq_z_<supf><mode>): Likewise.
361 (mve_vldrhq_z_fv8hf): Likewise.
362 (mve_vldrwq_<supf>v4si): Likewise.
363 (mve_vldrwq_fv4sf): Likewise.
364 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
365 (mve_vldrwq_gather_base_fv4sf): Likewise.
366 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
367 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
368 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
369 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
370 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
371 (mve_vldrwq_gather_base_z_fv4sf): Likewise.
372 (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
373 (mve_vldrwq_gather_offset_fv4sf): Likewise.
374 (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
375 (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
376 (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
377 (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
378 (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
379 (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
380 (mve_vldrwq_z_<supf>v4si): Likewise.
381 (mve_vldrwq_z_fv4sf): Likewise.
382 (mve_vmvnq_s<mode>): Likewise.
383 (mve_vmvnq_u<mode>): Likewise.
384 (mve_vornq_<supf><mode>): Likewise.
385 (mve_vornq_f<mode>): Likewise.
386 (mve_vornq_m_<supf><mode>): Likewise.
387 (mve_vornq_m_f<mode>): Likewise.
388 (mve_vornq_s<mode>): Likewise.
389 (mve_vornq_u<mode>): Likewise.
390 (mve_vorrq_<supf><mode>): Likewise.
391 (mve_vorrq_f<mode>): Likewise.
392 (mve_vorrq_m_<supf><mode>): Likewise.
393 (mve_vorrq_m_f<mode>): Likewise.
394 (mve_vorrq_m_n_<supf><mode>): Likewise.
395 (mve_vorrq_n_<supf><mode>): Likewise.
396 (mve_vorrq_s<mode>): Likewise.
397 (mve_vorrq_s<mode>): Likewise.
398 (mve_vsbciq_<supf>v4si): Likewise.
399 (mve_vsbciq_m_<supf>v4si): Likewise.
400 (mve_vsbcq_<supf>v4si): Likewise.
401 (mve_vsbcq_m_<supf>v4si): Likewise.
402 (mve_vshlcq_<supf><mode>): Likewise.
403 (mve_vshlcq_m_<supf><mode>): Likewise.
404 (mve_vshrq_m_n_<supf><mode>): Likewise.
405 (mve_vshrq_n_<supf><mode>): Likewise.
406 (mve_vstrbq_<supf><mode>): Likewise.
407 (mve_vstrbq_p_<supf><mode>): Likewise.
408 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
409 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
410 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
411 (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
412 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
413 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
414 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
415 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
416 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
417 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
418 (mve_vstrhq_<supf><mode>): Likewise.
419 (mve_vstrhq_fv8hf): Likewise.
420 (mve_vstrhq_p_<supf><mode>): Likewise.
421 (mve_vstrhq_p_fv8hf): Likewise.
422 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
423 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
424 (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
425 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
426 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
427 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
428 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
429 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
430 (mve_vstrwq_<supf>v4si): Likewise.
431 (mve_vstrwq_fv4sf): Likewise.
432 (mve_vstrwq_p_<supf>v4si): Likewise.
433 (mve_vstrwq_p_fv4sf): Likewise.
434 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
435 (mve_vstrwq_scatter_base_fv4sf): Likewise.
436 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
437 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
438 (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
439 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
440 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
441 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
442 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
443 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
444 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
445 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
446 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
447 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
448 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
449 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
451 2024-03-04 Marek Polacek <polacek@redhat.com>
453 * doc/extend.texi: Update [[gnu::no_dangling]].
455 2024-03-04 Andrew Stubbs <ams@baylibre.com>
457 * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
458 * expr.cc (store_constructor): Likewise.
459 (do_store_flag): Likewise.
461 2024-03-04 Mark Wielaard <mark@klomp.org>
463 * common.opt.urls: Regenerate.
464 * config/avr/avr.opt.urls: Likewise.
465 * config/i386/i386.opt.urls: Likewise.
466 * config/pru/pru.opt.urls: Likewise.
467 * config/riscv/riscv.opt.urls: Likewise.
468 * config/rs6000/rs6000.opt.urls: Likewise.
470 2024-03-04 Richard Biener <rguenther@suse.de>
472 PR tree-optimization/114197
473 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
474 there are volatile bitfield accesses.
475 (pass_if_conversion::execute): Throw away result if the
476 if-converted and original loops are not nested as expected.
478 2024-03-04 Richard Biener <rguenther@suse.de>
480 PR tree-optimization/114164
481 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
482 the code generated for mask argument setup is not supported.
484 2024-03-04 Richard Biener <rguenther@suse.de>
486 PR tree-optimization/114203
487 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
488 adjustment before making the result defined at zero.
490 2024-03-04 Richard Biener <rguenther@suse.de>
492 PR tree-optimization/114192
493 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
494 appropriate def for the live out stmt in case of an alternate
495 exit.
497 2024-03-04 Jakub Jelinek <jakub@redhat.com>
499 PR middle-end/114209
500 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
501 unshare_expr when creating a MEM_REF from MEM_REF.
502 (bitint_large_huge::lower_stmt): Call unshare_expr.
504 2024-03-04 Jakub Jelinek <jakub@redhat.com>
506 PR target/114184
507 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
508 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
509 register.
511 2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
513 PR target/114187
514 * simplify-rtx.cc (simplify_context::simplify_subreg): Call
515 lowpart_subreg to perform type conversion, to avoid confusion
516 over the offset to use in the call to simplify_reg_subreg.
518 2024-03-03 Greg McGary <gkm@rivosinc.com>
520 PR rtl-optimization/113010
521 * combine.cc (simplify_comparison): Simplify a SUBREG on
522 WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
523 MEM load.
525 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
527 * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
528 Use bool in place of int for boolean logic (if possible).
529 Move declarations to definitions (if possible).
530 * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
531 * config/avr/avr-dimode.md: Same.
532 * config/avr/constraints.md: Same.
533 * config/avr/predicates.md: Same.
535 2024-03-03 Uros Bizjak <ubizjak@gmail.com>
537 PR target/113720
538 * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
539 (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
540 simplify insn RTX using UMUL_HIGHPART rtx_code.
541 (*umuldi3_highpart_const): Remove.
543 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
545 PR target/114100
546 * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
547 * config/avr/avr.cc (_reg_unused_after): Make static. And
548 add 3rd argument to skip the current insn.
549 (reg_unused_after): Adjust call of reg_unused_after.
550 (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
551 unneeded frame pointer adjustments.
553 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
555 PR target/92729
556 * config/avr/avr.md (define_attr "cc"): Remove.
557 * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
558 from prototype.
559 * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
560 its uses. Add insn argument.
561 (avr_out_plus_symbol): Remove pcc argument and its uses.
562 (avr_out_plus): Remove pcc argument and its uses.
563 Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
564 (avr_out_round): Adjust call of avr_out_plus.
566 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
568 * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
569 from r14-9273.
571 2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
573 PR target/101737
574 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
575 is not an insn, but e.g. a code label.
577 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
579 * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
580 * config/avr/avr.cc: Use them instead of magic numbers when it
581 means a register number.
583 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
585 * config/avr/avr.cc: Adjust some comments.
587 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
589 PR target/114100
590 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
591 the low part of the frame pointer with 8-bit stack pointer.
593 2024-03-01 Patrick Palka <ppalka@redhat.com>
595 PR c++/104919
596 PR c++/106009
597 * tree-inline.cc (remap_decl): Handle copy_decl returning the
598 original decl.
599 (remap_decls): Handle remap_decl returning the original decl.
600 (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
601 CONST_DECL.
603 2024-03-01 Jeff Law <jlaw@ventanamicro.com>
605 * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
606 type attribute.
607 (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
608 (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
609 (movhi_internal, movqi_internal): Likewise.
610 (movsf_softfloat, movsf_hardfloat): Likewise.
611 (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
612 (movdf_softfloat): Likewise.
614 2024-03-01 Marek Polacek <polacek@redhat.com>
616 PR c++/110358
617 PR c++/109642
618 * doc/extend.texi: Document gnu::no_dangling.
619 * doc/invoke.texi: Mention that gnu::no_dangling disables
620 -Wdangling-reference.
622 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
624 * config/avr/avr.opt: Overhaul help screen.
626 2024-03-01 Jakub Jelinek <jakub@redhat.com>
627 Tobias Burnus <tburnus@baylibre.com>
629 PR c++/110347
630 * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
631 lang_hooks.decls.omp_disregard_value_expr for
632 (first)private in target regions.
634 2024-03-01 Jakub Jelinek <jakub@redhat.com>
636 PR middle-end/114136
637 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
638 n_named_args initially before INIT_CUMULATIVE_ARGS to
639 structure_value_addr_parm rather than 0, after it don't modify
640 it if strict_argument_naming and clear only if
641 !pretend_outgoing_varargs_named.
643 2024-03-01 Jakub Jelinek <jakub@redhat.com>
645 PR debug/114015
646 * dwarf2out.cc (should_move_die_to_comdat): Return false for
647 aggregates without DW_AT_byte_size attribute or with non-constant
648 DW_AT_byte_size.
650 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
652 * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
653 valid values for level.
655 2024-03-01 Richard Biener <rguenther@suse.de>
657 PR middle-end/114070
658 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
659 Allow the folding if before lowering and the current IL
660 isn't supported with vcond_mask.
662 2024-03-01 xuli <xuli1@eswincomputing.com>
664 * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
665 attribute to riscv_attribute_table.
666 (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
667 (riscv_fntype_abi): Add riscv_vector_cc attribute check.
668 * doc/extend.texi: Add riscv_vector_cc attribute description.
670 2024-03-01 Pan Li <pan2.li@intel.com>
672 PR target/112817
673 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
674 RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
675 * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
676 (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
677 * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
678 comments for option replacement.
679 * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
680 riscv_autovec_preference to rvv_vector_bits.
681 (vls_mode_valid_p): Ditto.
682 (estimated_poly_value): Ditto.
683 * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
684 vector chunks and honor new option mrvv-vector-bits.
685 (riscv_override_options_internal): Update comments and rename the
686 vector chunks.
687 * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
688 internal option param=riscv-autovec-preference.
690 2024-03-01 Jakub Jelinek <jakub@redhat.com>
692 * function.cc (assign_parms): Only call assign_parms_setup_varargs
693 early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
695 2024-03-01 Jakub Jelinek <jakub@redhat.com>
697 PR middle-end/114156
698 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
699 rhs1 of a VCE to have no underlying variable if it is a load and
700 handle that case.
702 2024-02-29 David Malcolm <dmalcolm@redhat.com>
704 PR analyzer/114159
705 * function.cc (function_name): Make param const.
706 * function.h (function_name): Likewise.
708 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
710 PR target/114100
711 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
712 * config/avr/avr.opt (-mfuse-add=): New target option.
713 * common/config/avr/avr-common.cc (avr_option_optimization_table)
714 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
715 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
716 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
717 * config/avr/avr-protos.h (avr_split_tiny_move)
718 (make_avr_pass_fuse_add): New protos.
719 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
720 avr_split_tiny_move to split indirect memory accesses.
721 (gen_move_clobbercc): New define_expand helper.
722 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
723 (avr_pass_fuse_add): New class from rtl_opt_pass.
724 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
725 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
726 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
727 of PLUS addressing for AVR_TINY.
728 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
729 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
730 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
732 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
734 PR target/114132
735 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
736 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
737 (avr_function_arg): Set it.
738 (avr_frame_pointer_required_p): Use it instead of .nregs.
740 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
742 PR target/108174
743 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
744 static and mark with GTY.
746 2024-02-29 Xi Ruoyao <xry111@xry111.site>
748 * config/loongarch/loongarch.md
749 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
751 2024-02-29 Xi Ruoyao <xry111@xry111.site>
753 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
754 (crc): New define_int_attr.
755 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
756 into ...
757 (loongarch_<crc>_w_<size>_w): ... here.
759 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
761 PR target/114130
762 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
763 extend the expected value if needed.
765 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
767 * config.gcc (target_gtfiles): Change coreout to btfext-out.
768 (extra_objs): Change coreout to btfext-out.
769 * config/bpf/coreout.cc: Rename to btfext-out.cc.
770 * config/bpf/btfext-out.cc: Add.
771 * config/bpf/coreout.h: Rename to btfext-out.h.
772 * config/bpf/btfext-out.h: Add.
773 * config/bpf/core-builtins.cc: Change include.
774 * config/bpf/core-builtins.h: Change include.
775 * config/bpf/t-bpf: Accomodate renamed files.
777 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
779 PR target/113453
780 * config/bpf/bpf.cc (bpf_function_prologue): Define target
781 hook.
782 * config/bpf/coreout.cc (brf_ext_info_section)
783 (btf_ext_info): Move from coreout.h
784 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
785 (bpf_core_reloc): Rename to btf_ext_core_reloc.
786 (btf_ext): Add static variable.
787 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
788 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
789 (btf_ext_add_string, btf_funcinfo_type_callback)
790 (btf_add_func_info_for, btf_validate_funcinfo)
791 (btf_ext_info_len, output_btfext_func_info): Add function.
792 (output_btfext_header, bpf_core_reloc_add)
793 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
794 Change to support new structs.
795 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
796 Move and change in coreout.cc.
797 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
799 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
801 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
802 enabled by default for BPF.
803 (bpf_file_end): Call BTF deallocation.
804 (bpf_asm_init_sections): Correct condition.
805 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
806 deallocation.
807 (ctf_debuf_finish): Correct condition for calling
808 ctf_debug_finalize.
810 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
812 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
813 (traverse_btf_func_types): Define function.
814 * ctfc.h (funcs_traverse_callback): Typedef for function
815 prototype.
816 (traverse_btf_func_types): Add prototype.
818 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
820 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
822 2024-02-28 Richard Biener <rguenther@suse.de>
824 PR tree-optimization/113831
825 PR tree-optimization/108355
826 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
827 PR113831 fix.
829 2024-02-28 Richard Biener <rguenther@suse.de>
831 PR tree-optimization/114121
832 * tree-ssa-sccvn.h (vn_reference_s::offset,
833 vn_reference_s::max_size): New fields.
834 (vn_reference_insert_pieces): Adjust prototype.
835 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
836 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
837 size, allow using "don't know" state.
838 (vn_walk_cb_data::finish): Pass along offset/max_size.
839 (vn_reference_lookup_or_insert_for_pieces): Take offset and
840 max_size as argument and use it.
841 (vn_reference_lookup_3): Properly adjust offset and max_size
842 according to the adjusted ao_ref.
843 (vn_reference_lookup_pieces): Initialize offset and max_size.
844 (vn_reference_lookup): Likewise.
845 (vn_reference_lookup_call): Likewise.
846 (vn_reference_insert): Likewise.
847 (visit_reference_op_call): Likewise.
848 (vn_reference_insert_pieces): Take offset and max_size
849 as argument and use it.
851 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
853 PR tree-optimization/114075
854 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
855 point vectors
857 2024-02-28 Jakub Jelinek <jakub@redhat.com>
859 PR tree-optimization/114041
860 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
861 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
863 2024-02-28 Jakub Jelinek <jakub@redhat.com>
865 PR tree-optimization/113988
866 * stor-layout.h (bitwise_mode_for_size): Declare.
867 * stor-layout.cc (bitwise_mode_for_size): New function.
868 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
869 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
870 Use BITS_PER_UNIT instead of 8.
872 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
874 PR target/113871
875 * config/i386/mmx.md (V248FI): Add V2BF mode.
876 (V24FI_32): Ditto.
878 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
880 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
881 if either ref->offset is not byte aligned or ref->size is not known
882 to be equal to ref->max_size.
883 (maybe_trim_complex_store): Fix description.
884 (maybe_trim_constructor_store): Likewise.
885 (maybe_trim_partially_dead_store): Likewise.
887 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
889 * config/arm/mmintrin.h: Warn if this header is included without
890 defining __ENABLE_DEPRECATED_IWMMXT.
892 2024-02-27 Richard Biener <rguenther@suse.de>
894 PR tree-optimization/114074
895 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
896 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
897 Handle poly vs. non-poly multiplication correctly with respect
898 to undefined behavior on overflow.
900 2024-02-27 Jakub Jelinek <jakub@redhat.com>
902 PR rtl-optimization/114044
903 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
904 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
905 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
906 expand_PARITY): Declare.
907 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
908 expand_CTZ, expand_FFS, expand_PARITY): New functions.
909 (expand_POPCOUNT): Use expand_bitquery.
911 2024-02-27 Richard Biener <rguenther@suse.de>
913 PR tree-optimization/114081
914 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
915 Perform manual dominator update for prologue peeling.
916 (vect_do_peeling): Properly update dominators after adding the
917 prologue-around guard.
919 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
921 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
922 (mstrict-X): Tag as "Optimization".
924 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
926 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
927 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
929 2024-02-26 Jakub Jelinek <jakub@redhat.com>
930 H.J. Lu <hjl.tools@gmail.com>
932 PR rtl-optimization/113617
933 * varasm.cc (default_elf_select_rtx_section): For
934 references to private symbols in comdat sections
935 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
936 or .rodata.<comdat> comdat sections.
938 2024-02-26 Richard Biener <rguenther@suse.de>
940 PR tree-optimization/114099
941 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
942 Create and fill in a needed virtual LC PHI for the alternate
943 exits. Remove code dealing with that missing.
945 2024-02-26 Richard Biener <rguenther@suse.de>
947 PR tree-optimization/114068
948 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
949 New function.
950 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
951 on the main exit if needed. Remove band-aid for the case
952 it was missing.
954 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
956 PR target/114097
957 * config/i386/i386-options.cc (ix86_set_func_type): Check
958 interrupt instead of noreturn attribute.
960 2024-02-26 Jakub Jelinek <jakub@redhat.com>
962 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
963 !TARGET_64BIT.
965 2024-02-26 Jakub Jelinek <jakub@redhat.com>
967 PR tree-optimization/114090
968 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
969 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
970 types.
971 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
973 2024-02-26 Jakub Jelinek <jakub@redhat.com>
975 PR middle-end/114084
976 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
977 if all subtrees of var0 come from one of the op0 or op1 operands
978 and all subtrees of con0 come from the other one. Don't clear
979 variables which are never used afterwards.
981 2024-02-26 Richard Biener <rguenther@suse.de>
983 PR middle-end/114070
984 * genmatch.cc (parser::parse_c_expr): Do not record operand
985 lists but only mark operators used.
986 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
987 Properly guard the case of tcc_comparison changing the VEC_COND
988 value operand type.
990 2024-02-26 Jakub Jelinek <jakub@redhat.com>
992 PR target/114094
993 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
994 to printed instruction.
996 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
998 PR target/114098
999 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
1000 __builtin_ia32_ldtilecfg.
1001 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
1002 * config/i386/i386-builtin.def (BDESC): Add
1003 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
1004 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
1005 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
1006 * config/i386/i386.md (ldtilecfg): New pattern.
1007 (sttilecfg): Likewise.
1009 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
1011 PR tree-optimization/113205
1012 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
1013 the proposed layout if it does not allow a source partition with
1014 layout 2 to keep that layout.
1016 2024-02-24 Jakub Jelinek <jakub@redhat.com>
1018 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
1019 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
1020 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
1021 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
1022 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
1023 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
1024 macros.
1025 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
1026 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
1027 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
1028 HOST_WIDE_INT_UC macros.
1029 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
1030 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
1031 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
1032 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
1033 macros.
1034 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
1035 * config/i386/constraints.md (define_constraint "L"): Use
1036 HOST_WIDE_INT_C macro.
1037 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
1038 macro.
1039 (movl + movb peephole2): Likewise.
1040 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
1041 (const_32bit_mask): Likewise.
1043 2024-02-24 Jakub Jelinek <jakub@redhat.com>
1045 PR middle-end/114073
1046 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
1047 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
1048 types like vector or complex types.
1049 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
1050 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
1051 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
1053 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
1055 PR target/114028
1056 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
1057 Return false if inner mode is already Pmode.
1058 (rvv_builder::is_all_same_sequence): New function.
1059 (expand_vec_init): Emit broadcast if sequence is all same.
1061 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
1063 PR target/113613
1064 * config/aarch64/aarch64-early-ra.cc
1065 (early_ra::m_current_region): New member variable.
1066 (early_ra::m_fpr_recency): Likewise.
1067 (early_ra::start_new_region): Bump m_current_region.
1068 (early_ra::allocate_colors): Prefer less recently used registers
1069 in the event of a tie. Add a comment to explain why we prefer(ed)
1070 higher-numbered registers.
1071 (early_ra::find_oldest_color): Prefer less recently used registers
1072 here too.
1073 (early_ra::finalize_allocation): Update recency information for
1074 allocated registers.
1075 (early_ra::process_blocks): Initialize m_current_region and
1076 m_fpr_recency.
1078 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
1080 PR target/113295
1081 * config/aarch64/aarch64-early-ra.cc
1082 (early_ra::test_strictness): New enum.
1083 (early_ra::is_chain_candidate): Add a strictness parameter to
1084 control whether only correctness matters, or whether both correctness
1085 and heuristics should be used. Handle multiple levels of equivalence.
1086 (early_ra::find_related_start): Update call accordingly.
1087 (early_ra::strided_polarity_pref): Likewise.
1088 (early_ra::form_chains): Likewise.
1089 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
1090 correctness mode rather than trying to inline the test.
1092 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
1094 PR target/113295
1095 * config/aarch64/aarch64-early-ra.cc
1096 (early_ra::find_related_start): Account for definitions by shared
1097 registers when testing for a single register definition.
1098 (early_ra::accumulate_defs): New function.
1099 (early_ra::record_copy): If A shares B's register, fold A's
1100 definition information into B's. Fold A's use information into B's.
1102 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
1104 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
1105 if R_X86_64_CODE_6_GOTTPOFF is supported.
1106 * config.in: Regenerated.
1107 * configure: Likewise.
1108 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
1109 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
1111 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
1113 PR target/108120
1114 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
1115 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
1117 2024-02-23 Jakub Jelinek <jakub@redhat.com>
1119 PR rtl-optimization/114054
1120 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
1121 temp variable instead of target parameter for result.
1123 2024-02-23 Jakub Jelinek <jakub@redhat.com>
1125 PR tree-optimization/114040
1126 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
1127 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
1128 probability from likely to unlikely. When handling the true true
1129 store, first cast to limb_access_type and then to l's type.
1131 2024-02-23 Richard Biener <rguenther@suse.de>
1133 PR target/90785
1134 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
1136 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
1138 PR other/109668
1139 * config/riscv/arch-canonicalize: Move to python3
1140 * config/riscv/multilib-generator: Likewise
1142 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
1144 * doc/invoke.texi: Document -mcpu.
1146 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
1148 * configure: Regenerate.
1149 * configure.ac: Add parameter "--fatal-warnings" to assemble
1150 when checking whether the assemble support conditional branch
1151 relaxation.
1153 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1155 PR c/114007
1156 * doc/extend.texi: (__extension__): Remove comments about scope
1157 tokens vs. two colons.
1159 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
1161 PR tree-optimization/109804
1162 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
1163 DEMANGLE_COMPONENT_UNNAMED_TYPE.
1165 2024-02-22 Richard Biener <rguenther@suse.de>
1167 PR tree-optimization/114048
1168 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
1169 can also produce -1 off.
1171 2024-02-22 Richard Biener <rguenther@suse.de>
1173 PR tree-optimization/114027
1174 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
1175 condition reduction classification only for single-element
1176 chains.
1178 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1180 PR ipa/111960
1181 * profile-count.h (profile_count::dump): Remove overload with
1182 char * first argument.
1183 * profile-count.cc (profile_count::dump): Change overload with char *
1184 first argument which uses sprintf into the overfload with FILE *
1185 first argument and use fprintf instead. Remove overload which wrapped
1186 it.
1188 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1190 PR tree-optimization/113993
1191 * tree-call-cdce.cc (get_no_error_domain): Handle
1192 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
1193 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
1194 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1195 the as the F128 suffixed cases, otherwise as non-suffixed ones.
1196 Handle BUILT_IN_{EXP,POW}10L for
1197 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1198 as (-inf, 4932).
1200 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1202 PR tree-optimization/114038
1203 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
1204 loop exit condition if end is divisible by limb_prec.
1206 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
1208 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
1209 problem of mabi=, mno-flush-func, mexplicit-relocs;
1210 add missing leading - of mbranch-cost option.
1211 * config/mips/mips.opt.urls: Regenerate.
1213 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
1215 PR target/109987
1216 * config/rs6000/constraints.md (we): Update internal doc without
1217 referring to option -mpower9-vector.
1218 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
1219 special handlings.
1220 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
1221 OTHER_P8_VECTOR_MASKS): Merge to ...
1222 (OTHER_VSX_VECTOR_MASKS): ... here.
1223 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
1224 some error message handlings and explicit option mask adjustments on
1225 explicit option power{8,9}-vector conflicting with other options.
1226 (rs6000_print_isa_options): Update comments.
1227 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
1228 related array items and handlings.
1229 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
1230 special handlings.
1231 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
1232 WarnRemoved.
1233 * doc/extend.texi: Remove documentation referring to option
1234 -mpower8-vector.
1235 * doc/invoke.texi: Remove documentation for option
1236 -mpower{8,9}-vector and adjust some documentation referring to them.
1237 * doc/md.texi: Update documentation for constraint we.
1238 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
1240 2024-02-22 Pan Li <pan2.li@intel.com>
1242 PR target/114017
1243 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
1244 the version to 0.12.
1246 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1248 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
1250 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1251 Robin Dapp <rdapp.gcc@gmail.com>
1253 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1254 (generic_ooo_vec_load): Ditto
1255 (generic_ooo_vec_store): Ditto
1256 (generic_ooo_vec_loadstore_seg): Ditto
1257 (generic_ooo_vec_alu): Ditto
1258 (generic_ooo_vec_fcmp): Ditto
1259 (generic_ooo_vec_imul): Ditto
1260 (generic_ooo_vec_fadd): Ditto
1261 (generic_ooo_vec_fmul): Ditto
1262 (generic_ooo_crypto): Ditto
1263 (generic_ooo_perm): Ditto
1264 (generic_ooo_vec_reduction): Ditto
1265 (generic_ooo_vec_ordered_reduction): Ditto
1266 (generic_ooo_vec_idiv): Ditto
1267 (generic_ooo_vec_float_divsqrt): Ditto
1268 (generic_ooo_vec_mask): Ditto
1269 (generic_ooo_vec_vesetvl): Ditto
1270 (generic_ooo_vec_setrm): Ditto
1271 (generic_ooo_vec_readlen): Ditto
1272 * config/riscv/riscv.md: Include generic-vector-ooo
1273 * config/riscv/generic-vector-ooo.md: New file. To here
1275 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1277 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1278 (generic_ooo_branch): Ditto
1279 * config/riscv/generic.md (generic_sfb_alu): Ditto
1280 (generic_fmul_half): Ditto
1281 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1282 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
1283 (sifive_7_popcount): Ditto
1284 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
1285 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
1286 * config/riscv/vector.md: Change rdfrm to fmove
1287 * config/riscv/zc.md: Change pushpop to load/store
1289 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
1291 * doc/invoke.texi (Warning Options): Fix typos.
1293 2024-02-21 David Faust <david.faust@oracle.com>
1295 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
1296 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
1297 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
1299 2024-02-21 Martin Jambor <mjambor@suse.cz>
1301 PR ipa/113476
1302 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
1303 initializers in the contructor.
1304 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
1305 * ipa-cp.h: New file.
1306 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
1307 (ipcp_value_source): Move to ipa-cp.h.
1308 (ipcp_value_base): Likewise.
1309 (ipcp_value): Likewise.
1310 (ipcp_lattice): Likewise.
1311 (ipcp_agg_lattice): Likewise.
1312 (ipcp_bits_lattice): Likewise.
1313 (ipcp_vr_lattice): Likewise.
1314 (ipcp_param_lattices): Likewise.
1315 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
1316 (ipa_value_from_jfunc): Adjust a check for empty lattices.
1317 (ipa_context_from_jfunc): Likewise.
1318 (ipa_agg_value_from_jfunc): Likewise.
1319 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
1320 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
1321 just in contiguous memory.
1322 (ipcp_store_vr_results): Adjust a check for empty lattices.
1323 * auto-profile.cc: Include sreal.h and ipa-cp.h.
1324 * cgraph.cc: Likewise.
1325 * cgraphclones.cc: Likewise.
1326 * cgraphunit.cc: Likewise.
1327 * config/aarch64/aarch64.cc: Likewise.
1328 * config/i386/i386-builtins.cc: Likewise.
1329 * config/i386/i386-expand.cc: Likewise.
1330 * config/i386/i386-features.cc: Likewise.
1331 * config/i386/i386-options.cc: Likewise.
1332 * config/i386/i386.cc: Likewise.
1333 * config/rs6000/rs6000.cc: Likewise.
1334 * config/s390/s390.cc: Likewise.
1335 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
1336 files to be included in gtype-desc.cc.
1337 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
1338 * ipa-devirt.cc: Likewise.
1339 * ipa-fnsummary.cc: Likewise.
1340 * ipa-icf.cc: Likewise.
1341 * ipa-inline-analysis.cc: Likewise.
1342 * ipa-inline-transform.cc: Likewise.
1343 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
1344 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
1345 * ipa-param-manipulation.cc: Likewise.
1346 * ipa-predicate.cc: Likewise.
1347 * ipa-profile.cc: Likewise.
1348 * ipa-prop.cc: Likewise.
1349 (ipa_node_params_t::duplicate): Assert new lattices remain empty
1350 instead of setting them to NULL.
1351 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
1352 * ipa-split.cc: Likewise.
1353 * ipa-sra.cc: Likewise.
1354 * ipa-strub.cc: Likewise.
1355 * ipa-utils.cc: Likewise.
1356 * ipa.cc: Likewise.
1357 * toplev.cc: Likewise.
1358 * tree-ssa-ccp.cc: Likewise.
1359 * tree-ssa-sccvn.cc: Likewise.
1360 * tree-vrp.cc: Likewise.
1362 2024-02-21 Tamar Christina <tamar.christina@arm.com>
1364 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
1365 Armv8.7-a.
1367 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1369 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1370 Use aarch64_gen_compare_zero_and_branch rather than emitting
1371 a CBZ directly.
1373 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1375 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
1376 Remove duplicated call.
1378 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1380 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
1381 Check that each individual piece of state is shared in the same
1382 way, rather than using an aggregate check for PSTATE.ZA.
1384 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1386 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1387 In the code that commits a lazy save, only zero ZA if the function
1388 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
1390 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1392 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
1393 directly inserting the associated sequence
1394 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1395 ...here instead.
1397 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1399 PR target/113995
1400 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
1401 fold the SVE allocation into the initial allocation if the
1402 initial allocation includes a VG save.
1404 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1406 PR target/113220
1407 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
1408 contain jumps even if called after initial RTL expansion.
1409 * mode-switching.cc: Include cfgbuild.h.
1410 (optimize_mode_switching): Allow the sequence returned by the
1411 emit hook to contain internal jumps. Record which blocks
1412 contain such jumps and split the blocks at the end.
1413 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
1414 non-debug insns when scanning the sequence.
1416 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
1418 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
1419 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
1421 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
1423 * doc/invoke.texi (-mmcu): Add information about MCU specs.
1425 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
1427 * doc/invoke.texi (-minrt): Clarify that main
1428 must take no arguments.
1430 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
1432 * config/avr/builtins.def: Use function prototypes of given size
1433 and signedness.
1434 * config/avr/avr.cc (avr_init_builtins): Adjust types required
1435 by builtins.def.
1436 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
1438 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
1440 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
1441 instead of @table.
1443 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
1445 * config/bpf/bpf.opt: Add help information for -mcpu.
1447 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
1449 PR target/113805
1450 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
1451 New pass.
1452 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
1453 Declare.
1454 * config/aarch64/aarch64.md (is_call): New attribute.
1455 (*and<mode>3nr_compare0): Rename to...
1456 (@aarch64_and<mode>3nr_compare0): ...this.
1457 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
1458 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
1459 * config/aarch64/aarch64-speculation.cc: Update file comment to
1460 describe the new late pass.
1461 (aarch64_do_track_speculation): Handle is_call insns like other calls.
1462 (pass_track_speculation): Add an is_late member variable.
1463 (pass_track_speculation::gate): Run the late pass for streaming-
1464 compatible functions and the early pass for other functions.
1465 (make_pass_track_speculation): Update accordingly.
1466 (make_pass_late_track_speculation): New function.
1467 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
1468 function.
1469 (aarch64_guard_switch_pstate_sm): Use it.
1471 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
1473 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
1474 Register these builtins with a pointer to uint64_t rather than unsigned
1475 DI mode.
1477 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
1479 PR target/113615
1480 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
1481 Conditionalize on '!TARGET_RDNA2_PLUS'.
1482 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
1483 (gcn_expand_reduc_scalar):
1484 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
1486 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
1488 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
1489 '__gfx90a__' target CPU definition. Add some safeguards for the future.
1491 2024-02-19 Richard Biener <rguenther@suse.de>
1493 PR rtl-optimization/54052
1494 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
1495 local defs by LR_OUT.
1497 2024-02-19 Jakub Jelinek <jakub@redhat.com>
1499 PR tree-optimization/113967
1500 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
1501 in condition that @rpos is multiple of vector element size.
1503 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1505 PR target/113696
1506 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
1507 Suppress vsetvl fusion.
1509 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
1511 PR target/113912
1512 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
1513 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
1514 (ix86_emit_save_regs): Don't generate push2 if
1515 ix86_can_use_push2pop2 return false.
1516 (ix86_expand_epilogue): Don't generate pop2 if
1517 ix86_can_use_push2pop2 return false.
1519 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
1521 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
1522 Note on complete device support.
1524 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
1526 * doc/extend.texi (AVR Function Attributes): Fuse description
1527 of "signal" and "interrupt" attribute. Link pseudo instruction.
1529 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
1531 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
1532 symbol type conversions.
1533 (__cacop_d): Likewise.
1534 (__cpucfg): Likewise.
1535 (__asrtle_d): Likewise.
1536 (__asrtgt_d): Likewise.
1537 (__lddir_d): Likewise.
1538 (__ldpte_d): Likewise.
1539 (__crc_w_b_w): Likewise.
1540 (__crc_w_h_w): Likewise.
1541 (__crc_w_w_w): Likewise.
1542 (__crc_w_d_w): Likewise.
1543 (__crcc_w_b_w): Likewise.
1544 (__crcc_w_h_w): Likewise.
1545 (__crcc_w_w_w): Likewise.
1546 (__crcc_w_d_w): Likewise.
1547 (__csrrd_w): Likewise.
1548 (__csrwr_w): Likewise.
1549 (__csrxchg_w): Likewise.
1550 (__csrrd_d): Likewise.
1551 (__csrwr_d): Likewise.
1552 (__csrxchg_d): Likewise.
1553 (__iocsrrd_b): Likewise.
1554 (__iocsrrd_h): Likewise.
1555 (__iocsrrd_w): Likewise.
1556 (__iocsrrd_d): Likewise.
1557 (__iocsrwr_b): Likewise.
1558 (__iocsrwr_h): Likewise.
1559 (__iocsrwr_w): Likewise.
1560 (__iocsrwr_d): Likewise.
1561 (__frecipe_s): Likewise.
1562 (__frecipe_d): Likewise.
1563 (__frsqrte_s): Likewise.
1564 (__frsqrte_d): Likewise.
1566 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
1568 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
1569 function return value type to unsigned short.
1571 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
1573 * doc/sourcebuild.texi: add scan-assembler-bound
1575 2024-02-16 Jason Merrill <jason@redhat.com>
1577 * gdbhooks.py: Fix regex syntax.
1579 2024-02-16 Richard Biener <rguenther@suse.de>
1581 PR tree-optimization/113895
1582 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
1583 consistency checking when there are out-of-bound array
1584 accesses. Allow -1 off when from an array reference with
1585 constant index.
1587 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
1589 PR target/106543
1590 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
1591 pattern.
1593 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1595 * doc/sourcebuild.texi (Effective-Target Keywords, Other
1596 attribugs): Document linker_plugin.
1597 (Require Support): Document dg-require-linker-plugin.
1599 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
1601 PR target/109349
1602 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
1603 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
1604 (RISCV_MINOR_VERSION_BASE): Ditto.
1605 (RISCV_REVISION_VERSION_BASE): Ditto.
1606 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
1607 rather than magic number.
1608 * config/riscv/riscv.h (riscv_arch_help): New.
1609 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
1610 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
1611 --print-supported-extensions.
1612 * config/riscv/riscv.opt (march=help): New.
1613 (print-supported-extensions): New.
1614 (-print-supported-extensions): New.
1615 * doc/invoke.texi (RISC-V Options): Document -march=help.
1617 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
1619 PR target/113780
1620 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
1621 for indirect calls with 4 or more arguments in pac-enabled functions.
1623 2024-02-15 David Faust <david.faust@oracle.com>
1625 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
1626 use ldxb instead of ldxh.
1628 2024-02-15 Jakub Jelinek <jakub@redhat.com>
1630 PR middle-end/113921
1631 * cfgrtl.h (prepend_insn_to_edge): New declaration.
1632 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
1633 comment.
1634 (prepend_insn_to_edge): New function.
1635 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
1636 insert_insn_on_edge.
1638 2024-02-15 Richard Biener <rguenther@suse.de>
1640 PR tree-optimization/111156
1641 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
1642 at the pattern stmt if any.
1644 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
1646 PR target/113927
1647 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
1648 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
1649 * config/avr/avr.cc (avr_adiw_reg_p): New function.
1650 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
1651 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
1652 * config/avr/avr.md: Same.
1653 (attr "isa") <tiny, no_tiny>: Remove.
1654 <adiw, no_adiw>: Add.
1655 (define_insn, define_insn_and_split): When an alternative has
1656 constraint "w", then set attribute "isa" to "adiw".
1657 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
1658 Built-in define __AVR_HAVE_ADIW__.
1659 * doc/invoke.texi (AVR Options): Document it.
1661 2024-02-15 Andrew Stubbs <ams@baylibre.com>
1663 * config/gcn/gcn-valu.md
1664 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
1665 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
1666 details are supported on RDNA devices.
1668 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
1670 PR middle-end/113508
1671 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
1672 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
1673 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
1674 Add sentence about what the mode m is.
1676 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
1678 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
1679 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
1680 var.
1682 2024-02-15 Richard Biener <rguenther@suse.de>
1684 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
1685 stmts.
1687 2024-02-15 Jakub Jelinek <jakub@redhat.com>
1689 PR tree-optimization/113567
1690 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
1691 _BitInt multiplication, division or modulo with
1692 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
1693 force the affected inputs into a new SSA_NAME.
1695 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
1697 PR target/113871
1698 * config/i386/mmx.md (V248FI): New mode iterator.
1699 (V24FI_32): DItto.
1700 (vec_shl_<V248FI:mode>): New expander.
1701 (vec_shl_<V24FI_32:mode>): Ditto.
1702 (vec_shr_<V248FI:mode>): Ditto.
1703 (vec_shr_<V24FI_32:mode>): Ditto.
1704 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
1705 (vec_shr_<V248FI:mode>): Ditto.
1707 2024-02-14 Jan Hubicka <jh@suse.cz>
1709 PR tree-optimization/111054
1710 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
1712 2024-02-14 Tamar Christina <tamar.christina@arm.com>
1714 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
1716 2024-02-14 Richard Biener <rguenther@suse.de>
1718 PR tree-optimization/113910
1719 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
1720 the hashval_t hash.
1722 2024-02-14 Jakub Jelinek <jakub@redhat.com>
1724 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
1725 (pp_integer_with_precision): For unsigned ptrdiff_t printing
1726 with u, o or x print ptrdiff_t argument converted to
1727 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
1729 2024-02-14 Richard Biener <rguenther@suse.de>
1731 PR middle-end/113576
1732 * expr.cc (do_store_flag): For vector bool compares of vectors
1733 with padding zero that.
1734 * dojump.cc (do_compare_and_jump): Likewise.
1736 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
1738 * doc/install.texi (Prerequisites): Update gettext link.
1740 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
1742 PR target/113876
1743 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
1744 Return false if the incoming stack isn't 16-byte aligned.
1746 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
1748 PR middle-end/113904
1749 * omp-general.cc (struct omp_ts_info): Update for splitting of
1750 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1751 * omp-selectors.h (enum omp_tp_type): Replace
1752 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1754 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
1756 PR target/113742
1757 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
1758 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
1760 2024-02-13 Richard Biener <rguenther@suse.de>
1762 PR tree-optimization/113895
1763 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
1764 offset to discover constant array indices in bits, handle
1765 COMPONENT_REF to bitfields.
1767 2024-02-13 Richard Biener <rguenther@suse.de>
1769 PR tree-optimization/113831
1770 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
1771 typo in comment.
1773 2024-02-13 Richard Biener <rguenther@suse.de>
1775 PR tree-optimization/113902
1776 * tree-vect-loop.cc (move_early_exit_stmts): Track
1777 last_seen_vuse for VUSE updating.
1779 2024-02-13 Tamar Christina <tamar.christina@arm.com>
1781 PR tree-optimization/113734
1782 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
1783 an early break loop as partial.
1785 2024-02-13 Richard Biener <rguenther@suse.de>
1787 PR tree-optimization/113898
1788 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
1789 missing accumulated off adjustment.
1791 2024-02-13 Jakub Jelinek <jakub@redhat.com>
1793 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
1794 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
1795 it against UINT_MAX and ULONG_MAX.
1797 2024-02-13 David Malcolm <dmalcolm@redhat.com>
1799 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
1800 to...
1801 (emit_diagnostic_valist_meta): ...this.
1802 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
1803 (emit_diagnostic_valist_meta): ...this.
1805 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1807 PR tree-optimization/113849
1808 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
1809 fast path for widening casts where !m_upwards_2limb and lhs_type
1810 has precision which is a multiple of limb_prec.
1812 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1814 PR c++/113674
1815 * attribs.cc (extract_attribute_substring): Remove.
1816 (lookup_scoped_attribute_spec): Don't call it.
1818 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1820 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
1821 and cast to fmt_size_t instead of %lu and cast to unsigned long.
1823 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
1825 * Makefile.in: Add no-info dependency.
1826 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
1827 available.
1828 * configure: Regenerate.
1830 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
1832 PR target/113855
1833 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
1834 available to all sub-targets.
1835 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1836 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1838 2024-02-12 Richard Biener <rguenther@suse.de>
1840 PR tree-optimization/113831
1841 PR tree-optimization/108355
1842 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
1843 we see variable array indices and get_ref_base_and_extent
1844 can resolve those to constants fix up the ops to constants
1845 as well.
1846 (ao_ref_init_from_vn_reference): Use 'off' member for
1847 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
1848 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
1850 2024-02-12 Pan Li <pan2.li@intel.com>
1852 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
1853 Replace args to arguments for misspelled term.
1855 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
1857 PR target/112944
1858 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
1859 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
1860 when not linked with -mrodata-in-ram.
1862 2024-02-12 Richard Biener <rguenther@suse.de>
1864 PR tree-optimization/113863
1865 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1866 Record crossed virtual PHIs.
1867 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
1868 virtual PHIs.
1870 2024-02-10 Marek Polacek <polacek@redhat.com>
1872 DR 2237
1873 PR c++/107126
1874 PR c++/97202
1875 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
1877 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1879 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
1880 computation of idx for i == 4 of bitint_prec_huge.
1882 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1884 PR middle-end/110754
1885 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
1886 decls create PARM_DECL with pointer to original type, set
1887 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
1888 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
1889 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
1890 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
1891 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
1892 of the var as argument.
1894 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1896 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
1897 size_t and precision 4 for ptrdiff_t. Formatting fix.
1898 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
1899 Formatting fixes.
1900 (test_pp_format): Test t and z modifiers.
1901 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
1903 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1905 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
1906 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
1907 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
1908 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
1909 and casts to fmt_size_t instead of "%ld" and casts to long.
1910 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
1911 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
1912 instead of "%lu" and casts to unsigned long.
1913 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
1914 unsigned long.
1915 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
1916 and casts to fmt_size_t instead of "%ld" and casts to long.
1917 * cfgexpand.cc (dump_stack_var_partition): Use
1918 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
1919 and casts to unsigned long.
1920 * gengtype.cc (adjust_field_rtx_def): Likewise.
1921 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
1922 and casts to fmt_size_t instead of "%ld" and casts to long.
1923 * postreload-gcse.cc (dump_hash_table): Likewise.
1924 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
1925 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
1926 (ggc_internal_alloc, ggc_free): Likewise.
1927 * genpreds.cc (write_lookup_constraint_1): Likewise.
1928 (write_insn_constraint_len): Likewise.
1929 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
1930 and casts to fmt_size_t instead of "%ld" and casts to long.
1931 * varasm.cc (output_constant_pool_contents): Use
1932 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
1933 * var-tracking.cc (dump_var): Likewise.
1935 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1937 PR tree-optimization/113783
1938 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
1939 through VIEW_CONVERT_EXPR for final cast checks. Handle
1940 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
1941 INTEGER_TYPEs.
1942 (gimple_lower_bitint): Don't merge mergeable operations or other
1943 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
1944 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
1945 mode is BLKmode.
1947 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1949 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
1950 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
1951 HOST_SIZE_T_PRINT_HEX_PURE): Define.
1952 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
1953 fixes.
1955 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1957 PR middle-end/113415
1958 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
1959 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
1960 of hand written loop with emit_insn of copy_insn and emit original
1961 after_rtl_seq on the last edge.
1963 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1965 PR tree-optimization/113818
1966 * gimple-lower-bitint.cc (add_eh_edge): New function.
1967 (bitint_large_huge::handle_load,
1968 bitint_large_huge::lower_mergeable_stmt,
1969 bitint_large_huge::lower_muldiv_stmt): Use it.
1971 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1973 PR tree-optimization/113774
1974 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
1975 emit any comparison if m_first and low + 1 is equal to
1976 m_upwards_2limb, simplify condition for that. If not
1977 single_comparison, not m_first and we can prove that the idx <= low
1978 comparison will be always true, emit instead of idx <= low
1979 comparison low <= low such that cfg cleanup will optimize it at
1980 the end of the pass.
1982 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
1984 PR tree-optimization/113735
1985 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
1986 limit_check().
1988 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1990 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
1991 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
1993 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
1995 PR target/113711
1996 PR target/113733
1997 * config/i386/constraints.md: List all constraints with j prefix.
1998 (j>): Change auto-dec to auto-inc in documentation.
1999 (je): Changed to a memory constraint with APX NDD TLS operand
2000 check.
2001 (jM): New memory constraint for APX NDD instructions.
2002 (jO): Likewise.
2003 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
2004 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
2005 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
2006 (*add<mode>_1[SWI48]): Use je and jM.
2007 (addsi_1_zext): Use jM.
2008 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
2009 (*sub<mode>_1[SWI]): Use jM.
2010 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
2011 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
2012 (*and<dwi>3_doubleword): Likewise.
2013 (*anddi_1): Use jM.
2014 (*andsi_1_zext): Likewise.
2015 (*and<mode>_1[SWI24]): Likewise.
2016 (*<code><dwi>3_doubleword[any_or]): Use rjO
2017 (*code<mode>_1[any_or SWI248]): Use jM.
2018 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
2019 * config/i386/predicates.md (apx_ndd_memory_operand): New.
2020 (apx_ndd_add_memory_operand): Likewise.
2022 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2024 PR target/113824
2025 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
2026 * doc/avr-mmcu.texi: Rebuild.
2028 2024-02-08 Tamar Christina <tamar.christina@arm.com>
2030 PR tree-optimization/113808
2031 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
2032 value cross iterations.
2034 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2036 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
2037 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
2039 2024-02-08 Richard Biener <rguenther@suse.de>
2041 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2042 Revert last change to dr_may_alias_p.
2044 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2046 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
2047 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
2048 Remove spec asm_misc.
2049 * config/avr/specs.h: Same.
2051 2024-02-08 Pan Li <pan2.li@intel.com>
2053 PR target/113766
2054 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
2055 sure the c.arg_num is >= 2 before checking.
2056 (struct build_frm_base): Ditto.
2057 (struct narrow_alu_def): Ditto.
2059 2024-02-07 Richard Biener <rguenther@suse.de>
2061 PR tree-optimization/113796
2062 * tree-if-conv.cc (combine_blocks): Wipe range-info before
2063 replacing PHIs and inserting predicates.
2065 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
2066 Uros Bizjak <ubizjak@gmail.com>
2068 PR target/113690
2069 * config/i386/i386-features.cc (timode_convert_cst): New helper
2070 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
2071 CONST_VECTOR.
2072 (timode_scalar_chain::convert_op): Use timode_convert_cst.
2073 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
2074 Use timode_convert_cst.
2076 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
2078 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
2079 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
2080 (AARCH64_FL_DEBUGv8p9): Likewise.
2081 (AARCH64_FL_FGT2): Likewise.Likewise.
2082 (AARCH64_FL_ITE): Likewise.
2083 (AARCH64_FL_PFAR): Likewise.
2084 (AARCH64_FL_PMUv3_ICNTR): Likewise.
2085 (AARCH64_FL_PMUv3_SS): Likewise.
2086 (AARCH64_FL_PMUv3p9): Likewise.
2087 (AARCH64_FL_RASv2): Likewise.
2088 (AARCH64_FL_S1PIE): Likewise.
2089 (AARCH64_FL_S1POE): Likewise.
2090 (AARCH64_FL_S2PIE): Likewise.
2091 (AARCH64_FL_S2POE): Likewise.
2092 (AARCH64_FL_SCTLR2): Likewise.
2093 (AARCH64_FL_SEBEP): Likewise.
2094 (AARCH64_FL_SPE_FDS): Likewise.
2095 (AARCH64_FL_TCR2): Likewise.
2097 2024-02-07 Richard Biener <rguenther@suse.de>
2099 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2100 Only check whether reads are in-bound in places that are not safe.
2101 Fix dependence check. Add missing newline. Clarify comments.
2103 2024-02-07 Tamar Christina <tamar.christina@arm.com>
2105 PR tree-optimization/113750
2106 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
2107 for single predecessor when doing early break vect.
2108 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
2109 after labels.
2111 2024-02-07 Tamar Christina <tamar.christina@arm.com>
2113 PR tree-optimization/113731
2114 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
2115 method.
2116 * gimple-iterator.h (gsi_move_before): Default new param to
2117 GSI_SAME_STMT.
2118 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
2119 GSI_NEW_STMT.
2121 2024-02-07 Jakub Jelinek <jakub@redhat.com>
2123 PR tree-optimization/113756
2124 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
2125 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
2126 of lh_bits value and mask.
2128 2024-02-07 Jakub Jelinek <jakub@redhat.com>
2130 PR tree-optimization/113753
2131 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
2132 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
2133 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
2134 so that they start with r[half_blocks_needed] lowest bit. Fix up
2135 computation of top mask for SIGNED.
2137 2024-02-07 Pan Li <pan2.li@intel.com>
2139 PR target/113766
2140 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
2141 the signature of func.
2142 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
2143 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
2144 overloaded func with empty args error.
2146 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
2148 PR target/113689
2149 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
2150 R10_REG after sorry.
2152 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
2154 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
2155 Move before new caller, and add ".default" suffix.
2156 (get_suffixed_assembler_name): New.
2157 (make_resolver_func): Use get_suffixed_assembler_name.
2158 (aarch64_generate_version_dispatcher_body): Redo name mangling.
2160 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2162 PR target/113763
2163 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
2164 element from std::pair<unsigned int, char> to an unnamed struct.
2165 Adjust uses of tile range variable.
2167 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2169 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
2170 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
2172 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2174 PR sanitizer/110676
2175 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
2176 reset maxlen to sizetype maximum.
2178 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2180 PR tree-optimization/113736
2181 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
2182 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
2184 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2186 PR tree-optimization/113759
2187 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
2188 or from_unsignedN differs from properties of typeN, update typeN
2189 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
2190 uselessly convertible to typeN, convert it using fold_convert or
2191 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
2192 (convert_plusminus_to_widen): Likewise.
2194 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
2196 PR target/112577
2197 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
2198 vector structure modes correctly.
2200 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
2202 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
2203 warning.
2205 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
2207 PR target/113689
2208 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
2209 (x86_function_profiler): Call x86_64_select_profile_regnum to
2210 get a scratch register for large model profiling.
2212 2024-02-05 Richard Ball <richard.ball@arm.com>
2214 * config/arm/arm.cc (arm_output_mi_thunk): Emit
2215 insn for bti_c when bti is enabled.
2217 2024-02-05 Xi Ruoyao <xry111@xry111.site>
2219 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
2220 neg.
2222 2024-02-05 Xi Ruoyao <xry111@xry111.site>
2224 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
2225 (neg<mode>2): Change the mode iterator from MSA to IMSA because
2226 in FP arithmetic we cannot use (0 - x) for -x.
2227 (neg<mode>2): New define_insn to implement FP vector negation,
2228 using a bnegi instruction to negate the sign bit.
2230 2024-02-05 Richard Biener <rguenther@suse.de>
2232 PR tree-optimization/113707
2233 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
2234 checking the avail set treat out-of-region defines as
2235 available.
2237 2024-02-05 Richard Biener <rguenther@suse.de>
2239 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
2240 the default mode when building a pointer.
2242 2024-02-05 Jakub Jelinek <jakub@redhat.com>
2244 PR tree-optimization/113737
2245 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
2246 has just a single label, remove it and make single successor edge
2247 EDGE_FALLTHRU.
2249 2024-02-05 Jakub Jelinek <jakub@redhat.com>
2251 PR target/113059
2252 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
2253 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
2254 df_analyze call.
2256 2024-02-05 Richard Biener <rguenther@suse.de>
2258 PR target/113255
2259 * config/i386/i386-expand.cc
2260 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
2261 Use a new pseudo for the skipped number of bytes.
2263 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
2265 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
2266 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
2267 sifive-p670.
2269 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
2271 * config/riscv/riscv.md: Include sifive-p400.md.
2272 * config/riscv/sifive-p400.md: New file.
2273 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
2274 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
2275 Add sifive_p400.
2276 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
2277 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
2278 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
2280 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2282 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
2283 Add missing ":SI" to the match_operator.
2285 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2287 * config/xtensa/xtensa.md (SHI): New mode iterator.
2288 (2 split patterns related to constsynth):
2289 Change to also accept HImode operands.
2291 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
2293 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
2294 similarly.
2296 2024-02-04 Xi Ruoyao <xry111@xry111.site>
2298 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
2299 incorrect expand.
2300 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
2301 (elmsgnbit): Likewise.
2302 (neg<mode:FVEC>2): New define_insn.
2303 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
2304 are now instantiated in simd.md.
2306 2024-02-04 Xi Ruoyao <xry111@xry111.site>
2308 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
2309 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
2310 MAX_MACHINE_MODE.
2312 2024-02-04 Li Wei <liwei@loongson.cn>
2314 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
2315 (loongarch_expand_vselect_vconcat): Ditto.
2316 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
2317 all 128-bit constant permutation situations.
2318 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
2319 (loongarch_is_imm_set_shuffle): Renamed function name.
2320 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
2321 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
2322 extract-even and extract-odd permutations.
2323 (loongarch_is_odd_extraction): Delete.
2324 (loongarch_is_even_extraction): Ditto.
2325 (loongarch_expand_vec_perm_const): Adjust.
2327 2024-02-03 Jakub Jelinek <jakub@redhat.com>
2329 PR middle-end/113722
2330 * wide-int.cc (wi::bswap_large): Rename third argument from
2331 len to xlen and adjust use in safe_uhwi. Add len variable, set
2332 it to BLOCKS_NEEDED (precision) and use it for clearing of val
2333 and as canonize argument. Clear val using memset instead of
2334 a loop.
2336 2024-02-03 Jakub Jelinek <jakub@redhat.com>
2338 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
2339 mmi.preferred_base + mmi.size - sizeof (void *).
2341 2024-02-03 Xi Ruoyao <xry111@xry111.site>
2343 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
2344 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
2345 the ODR-violating locale declaration.
2347 2024-02-02 Tamar Christina <tamar.christina@arm.com>
2349 PR tree-optimization/113588
2350 PR tree-optimization/113467
2351 * tree-vect-data-refs.cc
2352 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
2353 (vect_analyze_early_break_dependences): Update comments.
2355 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
2357 PR target/59778
2358 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
2359 and PA_BUILTIN_SET_FPSR builtins.
2360 * (pa_builtins_icode): Declare.
2361 * (def_builtin, pa_fpu_init_builtins): New.
2362 * (pa_init_builtins): Initialize FPU builtins.
2363 * (pa_builtin_decl, pa_expand_builtin_1): New.
2364 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
2365 PA_BUILTIN_SET_FPSR builtins.
2366 * (pa_atomic_assign_expand_fenv): New.
2367 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
2368 UNSPECV constants.
2369 (get_fpsr, put_fpsr): New expanders.
2370 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
2371 insn patterns.
2373 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2375 PR target/113697
2376 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
2378 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
2380 * doc/extend.texi (Common Type Attributes): Fix typo in
2381 description of hardbool.
2383 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2385 PR tree-optimization/113692
2386 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
2387 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
2388 final_cast_p.
2390 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2392 PR middle-end/113699
2393 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
2394 uninitialized large/huge _BitInt SSA_NAME inputs.
2396 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2398 PR middle-end/113705
2399 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
2400 around wi::to_wide in order to compare value in prec precision.
2402 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
2404 Revert:
2405 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2407 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2409 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2411 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2413 2024-02-02 Pan Li <pan2.li@intel.com>
2415 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
2416 (riscv_pass_by_reference): Ditto.
2417 (riscv_fntype_abi): Ditto.
2419 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2421 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
2422 (pre_vsetvl::cleaup): Remove vsetvl_pre.
2423 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
2425 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
2427 * config/loongarch/larchintrin.h
2428 (__frecipe_s): Update function return type.
2429 (__frecipe_d): Ditto.
2430 (__frsqrte_s): Ditto.
2431 (__frsqrte_d): Ditto.
2433 2024-02-02 Li Wei <liwei@loongson.cn>
2435 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
2436 (loongarch_vector_costs::add_stmt_cost): Adjust.
2438 2024-02-02 Xi Ruoyao <xry111@xry111.site>
2440 * config/loongarch/loongarch.md (unspec): Add
2441 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
2442 (la_pcrel64_two_parts): New define_insn.
2443 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
2444 typo in the comment.
2445 (loongarch_call_tls_get_addr): If -mcmodel=extreme
2446 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
2447 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
2448 note to allow CSE addressing __tls_get_addr.
2449 (loongarch_legitimize_tls_address): If -mcmodel=extreme
2450 -mexplicit-relocs={always,auto}, address TLS IE symbols with
2451 la_pcrel64_two_parts.
2452 (loongarch_split_symbol): If -mcmodel=extreme
2453 -mexplicit-relocs={always,auto}, address symbols with
2454 la_pcrel64_two_parts.
2455 (loongarch_output_mi_thunk): Clean up unreachable code. If
2456 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
2457 thunks with la_pcrel64_two_parts.
2459 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2461 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
2462 Add support for call36.
2464 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2466 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
2467 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
2468 the macro instruction loading symbol address is not applicable.
2469 (loongarch_call_tls_get_addr): Adjust code.
2470 (loongarch_legitimize_tls_address): Likewise.
2472 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2474 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
2475 Add function declaration.
2476 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
2477 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
2478 is not allowed
2479 (loongarch_load_tls): Added macro support in extreme mode.
2480 (loongarch_call_tls_get_addr): Likewise.
2481 (loongarch_legitimize_tls_address): Likewise.
2482 (loongarch_force_address): Likewise.
2483 (loongarch_legitimize_move): Likewise.
2484 (loongarch_output_mi_thunk): Likewise.
2485 (loongarch_option_override_internal): Remove the code that detects
2486 explicit relocs status.
2487 (loongarch_handle_model_attribute): Likewise.
2488 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
2489 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
2490 (symbolic_off64_or_reg_operand): Likewise.
2492 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2494 * config/loongarch/loongarch.cc (loongarch_load_tls):
2495 Load all types of tls symbols through one function.
2496 (loongarch_got_load_tls_gd): Delete.
2497 (loongarch_got_load_tls_ld): Delete.
2498 (loongarch_got_load_tls_ie): Delete.
2499 (loongarch_got_load_tls_le): Delete.
2500 (loongarch_call_tls_get_addr): Modify the called function name.
2501 (loongarch_legitimize_tls_address): Likewise.
2502 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
2503 (@load_tls<mode>): New template.
2504 (@got_load_tls_ld<mode>): Delete.
2505 (@got_load_tls_le<mode>): Delete.
2506 (@got_load_tls_ie<mode>): Delete.
2508 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2510 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
2511 (loongarch_legitimize_address): Add logical transformation code.
2513 2024-02-01 Marek Polacek <polacek@redhat.com>
2515 * doc/invoke.texi: Update -Wdangling-reference documentation.
2517 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
2519 PR target/113701
2520 * config/i386/i386.md (*cmp<dwi>_doubleword):
2521 Do not force SUBREG pieces to pseudos.
2523 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
2525 * config/pa/pa.md (atomic_storedi_1): Fix bug in
2526 alternative 1.
2528 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
2530 * config/avr/avr.cc: Tabify.
2532 2024-02-01 Richard Ball <richard.ball@arm.com>
2534 PR tree-optimization/111268
2535 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
2536 Add variable-length check for vector input arguments
2537 to a function.
2539 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2541 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
2542 hard-code number of SGPR/VGPR/AVGPR registers.
2543 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
2544 SGPR/VGPR/AVGPR registers.
2546 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
2548 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
2549 attribute, and include sifive-p600.md.
2550 * config/riscv/generic-ooo.md: Update type attribute.
2551 * config/riscv/generic.md: Update type attribute.
2552 * config/riscv/sifive-7.md: Update type attribute.
2553 * config/riscv/sifive-p600.md: New file.
2554 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
2555 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
2556 Add sifive_p600.
2557 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
2558 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
2559 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
2561 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
2563 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
2564 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
2565 * config/riscv/riscv.opt: New macro for 7 new unprivileged
2566 extensions.
2567 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
2568 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
2570 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
2572 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
2573 -static-libasan. Add missing whitespace.
2575 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2577 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
2578 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
2579 Don't 'define_constants'.
2581 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2583 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
2585 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2587 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
2588 [TARGET_RDNA3]: Adjust.
2590 2024-02-01 Richard Biener <rguenther@suse.de>
2592 PR tree-optimization/113693
2593 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
2594 data when available.
2596 2024-02-01 Jakub Jelinek <jakub@redhat.com>
2597 Jason Merrill <jason@redhat.com>
2599 PR c++/113531
2600 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
2601 on variables which were promoted to TREE_STATIC.
2603 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
2604 Richard Biener <rguenther@suse.de>
2606 PR target/113560
2607 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
2608 information via tree_non_zero_bits to check if this operand
2609 is suitably extended for a widening (or highpart) multiplication.
2610 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
2611 isn't already of the claimed type.
2613 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2615 Revert:
2616 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2618 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2619 (generic_ooo_branch): ditto
2620 * config/riscv/generic.md (generic_sfb_alu): ditto
2621 (generic_fmul_half): ditto
2622 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2623 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
2624 (sifive_7_popcount): ditto
2625 * config/riscv/vector.md: change rdfrm to fmove
2626 * config/riscv/zc.md: change pushpop to load/store
2628 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2630 Revert:
2631 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2632 Robin Dapp <rdapp.gcc@gmail.com>
2634 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2635 (generic_ooo_vec_load): ditto
2636 (generic_ooo_vec_store): ditto
2637 (generic_ooo_vec_loadstore_seg): ditto
2638 (generic_ooo_vec_alu): ditto
2639 (generic_ooo_vec_fcmp): ditto
2640 (generic_ooo_vec_imul): ditto
2641 (generic_ooo_vec_fadd): ditto
2642 (generic_ooo_vec_fmul): ditto
2643 (generic_ooo_crypto): ditto
2644 (generic_ooo_perm): ditto
2645 (generic_ooo_vec_reduction): ditto
2646 (generic_ooo_vec_ordered_reduction): ditto
2647 (generic_ooo_vec_idiv): ditto
2648 (generic_ooo_vec_float_divsqrt): ditto
2649 (generic_ooo_vec_mask): ditto
2650 (generic_ooo_vec_vesetvl): ditto
2651 (generic_ooo_vec_setrm): ditto
2652 (generic_ooo_vec_readlen): ditto
2653 * config/riscv/riscv.md: include generic-vector-ooo
2654 * config/riscv/generic-vector-ooo.md: New file. to here
2656 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2658 Revert:
2659 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2661 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
2663 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2665 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
2667 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2668 Robin Dapp <rdapp.gcc@gmail.com>
2670 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2671 (generic_ooo_vec_load): ditto
2672 (generic_ooo_vec_store): ditto
2673 (generic_ooo_vec_loadstore_seg): ditto
2674 (generic_ooo_vec_alu): ditto
2675 (generic_ooo_vec_fcmp): ditto
2676 (generic_ooo_vec_imul): ditto
2677 (generic_ooo_vec_fadd): ditto
2678 (generic_ooo_vec_fmul): ditto
2679 (generic_ooo_crypto): ditto
2680 (generic_ooo_perm): ditto
2681 (generic_ooo_vec_reduction): ditto
2682 (generic_ooo_vec_ordered_reduction): ditto
2683 (generic_ooo_vec_idiv): ditto
2684 (generic_ooo_vec_float_divsqrt): ditto
2685 (generic_ooo_vec_mask): ditto
2686 (generic_ooo_vec_vesetvl): ditto
2687 (generic_ooo_vec_setrm): ditto
2688 (generic_ooo_vec_readlen): ditto
2689 * config/riscv/riscv.md: include generic-vector-ooo
2690 * config/riscv/generic-vector-ooo.md: New file. to here
2692 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2694 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2695 (generic_ooo_branch): ditto
2696 * config/riscv/generic.md (generic_sfb_alu): ditto
2697 (generic_fmul_half): ditto
2698 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2699 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
2700 (sifive_7_popcount): ditto
2701 * config/riscv/vector.md: change rdfrm to fmove
2702 * config/riscv/zc.md: change pushpop to load/store
2704 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
2706 PR target/113657
2707 * config/aarch64/aarch64-simd.md (split for movv8di):
2708 For strict aligned mode, use DImode instead of TImode.
2710 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
2712 PR middle-end/113607
2713 * match.pd: Make sure else values match when folding a
2714 vec_cond into a conditional operation.
2716 2024-01-31 Marek Polacek <polacek@redhat.com>
2718 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
2720 2024-01-31 Tamar Christina <tamar.christina@arm.com>
2721 Matthew Malcomson <matthew.malcomson@arm.com>
2723 PR sanitizer/112644
2724 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
2725 memcmp.
2726 * builtins.cc (expand_builtin): Include HWASAN when checking for
2727 builtin inlining.
2729 2024-01-31 Richard Biener <rguenther@suse.de>
2731 PR middle-end/110176
2732 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
2733 to match INTEGER_CST only without outstanding conversion.
2735 2024-01-31 Alex Coplan <alex.coplan@arm.com>
2737 PR target/111677
2738 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
2739 V16QImode for the full 16-byte FPR saves in the vector PCS case.
2741 2024-01-31 Richard Biener <rguenther@suse.de>
2743 PR tree-optimization/111444
2744 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
2745 vn_reference_lookup_2 when optimistically skipping may-defs.
2747 2024-01-31 Richard Biener <rguenther@suse.de>
2749 PR tree-optimization/113630
2750 * tree-ssa-pre.cc (compute_avail): Avoid registering a
2751 reference with a representation with not matching base
2752 access size.
2754 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2756 PR rtl-optimization/113656
2757 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
2758 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
2760 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2762 PR debug/113637
2763 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
2764 with BLKmode are larger than DWARF2_ADDR_SIZE.
2766 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2768 PR tree-optimization/113639
2769 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
2770 For VIEW_CONVERT_EXPR set rhs1 to its operand.
2772 2024-01-31 Richard Biener <rguenther@suse.de>
2774 PR tree-optimization/113670
2775 * tree-vect-data-refs.cc (vect_check_gather_scatter):
2776 Make sure we can take the address of the reference base.
2778 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
2780 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
2781 ATA5835, ATtiny64AUTO, ATA5700M322.
2782 * doc/avr-mmcu.texi: Rebuild.
2784 2024-01-31 Alexandre Oliva <oliva@adacore.com>
2786 PR debug/113394
2787 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
2788 caller.
2790 2024-01-31 Alexandre Oliva <oliva@adacore.com>
2792 PR middle-end/112917
2793 PR middle-end/113100
2794 * builtins.cc (expand_builtin_stack_address): Use
2795 STACK_ADDRESS_OFFSET.
2796 * doc/extend.texi (__builtin_stack_address): Adjust.
2797 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
2798 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
2799 * doc/tm.texi: Rebuilt.
2801 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2803 PR target/113495
2804 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
2805 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
2806 (pre_vsetvl::compute_transparent): New function.
2807 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
2809 2024-01-30 Fangrui Song <maskray@google.com>
2811 PR target/105576
2812 * config/i386/constraints.md: Define constraint "Ws".
2813 * doc/md.texi: Document it.
2815 2024-01-30 Marek Polacek <polacek@redhat.com>
2817 PR c++/110358
2818 PR c++/109640
2819 * doc/invoke.texi: Update -Wdangling-reference description.
2821 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2823 * config/xtensa/constraints.md (R, T, U):
2824 Change define_constraint to define_memory_constraint.
2825 * config/xtensa/predicates.md (move_operand): Don't check that a
2826 constant pool operand size is a multiple of UNITS_PER_WORD.
2827 * config/xtensa/xtensa.cc
2828 (xtensa_lra_p, TARGET_LRA_P): Remove.
2829 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
2830 clause as it can no longer be true.
2831 (fixup_subreg_mem): Drop function.
2832 (xtensa_output_integer_literal_parts): Consider 16-bit wide
2833 constants.
2834 (xtensa_legitimate_constant_p): Add short-circuit path for
2835 integer load instructions. Don't check that mode size is
2836 at least UNITS_PER_WORD.
2837 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
2838 rather reload_in_progress and reload_completed.
2839 (doloop_end): Drop operand 2.
2840 (movhi_internal): Add alternative loading constant from a
2841 literal pool.
2842 (define_split for DI register_operand): Don't limit to
2843 !TARGET_AUTO_LITPOOLS.
2844 * config/xtensa/xtensa.opt (mlra): Change to no effect.
2846 2024-01-30 Pan Li <pan2.li@intel.com>
2848 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
2849 calculate the gpr count required by vls mode.
2850 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
2851 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
2852 for vls mode.
2853 (riscv_get_arg_info): Add vls mode handling.
2854 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
2856 2024-01-30 Richard Biener <rguenther@suse.de>
2858 PR tree-optimization/113659
2859 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2860 Handle main exit without virtual use.
2862 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
2864 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
2866 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
2868 PR libgcc/113403
2869 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
2870 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
2871 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
2872 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
2873 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
2874 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
2876 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
2878 PR target/113623
2879 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
2880 Mark all registers that occur in addresses as needing a GPR.
2882 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
2884 PR target/113636
2885 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
2886 the containing insn as an extra parameter. Reset debug instructions
2887 if they reference a register that is no longer used by real insns.
2888 (early_ra::apply_allocation): Update calls accordingly.
2890 2024-01-30 Jakub Jelinek <jakub@redhat.com>
2892 PR tree-optimization/113603
2893 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
2894 count_nonzero_bytes call refetch si using get_strinfo in case it
2895 has been unshared in the meantime.
2897 2024-01-30 Jakub Jelinek <jakub@redhat.com>
2899 PR middle-end/101195
2900 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
2901 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
2903 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
2905 * config/riscv/thead.cc (th_print_operand_address): Change %ld
2906 to %lld.
2908 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
2909 Manolis Tsamis <manolis.tsamis@vrull.eu>
2910 Philipp Tomsich <philipp.tomsich@vrull.eu>
2912 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
2913 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
2914 Likewise.
2915 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
2916 Call on framework moved later.
2918 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
2920 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
2921 instruction in naked function epilogues.
2923 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
2925 PR target/113655
2926 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
2927 gcc_cv_as_mips_explicit_relocs.
2928 * configure: Regnerated.
2930 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
2932 PR target/108933
2933 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
2934 Correct generated RTL.
2935 (arm_rev16si2_alt1): Correctly handle conditional execution.
2936 (arm_rev16si2_alt2): Likewise.
2938 2024-01-29 Richard Biener <rguenther@suse.de>
2940 PR middle-end/113622
2941 * expr.cc (expand_assignment): Spill hard registers if
2942 we index them with a variable offset.
2944 2024-01-29 Richard Biener <rguenther@suse.de>
2946 PR middle-end/113622
2947 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
2948 Also allow DECL_HARD_REGISTER variables.
2950 2024-01-29 Alex Coplan <alex.coplan@arm.com>
2952 PR target/113616
2953 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
2954 Use iterate_safely when iterating over debug uses.
2955 (fixup_debug_uses): Likewise.
2956 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
2957 over nondebug insns instead of manually maintaining the next insn.
2958 * iterator-utils.h (class safe_iterator): New.
2959 (iterate_safely): New.
2961 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
2963 PR target/38534
2964 * config/i386/i386-options.cc (ix86_set_func_type): Save
2965 callee-saved registers in noreturn functions for -O0/-Og.
2967 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2969 PR target/113615
2970 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
2971 define for !TARGET_RDNA2_PLUS.
2973 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
2975 PR target/113281
2976 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
2977 workaround for right shifts.
2978 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
2979 (vect_determine_precisions_from_range): Be more selective about
2980 which codes can be narrowed based on their input and output ranges.
2981 For shifts, require at least one more bit of precision than the
2982 maximum shift amount.
2984 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2986 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
2988 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2990 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
2991 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
2992 LLVM 13.0.1+.
2994 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2996 PR other/111966
2997 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
2998 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
2999 (SET_SRAM_ECC_UNSET): ... this.
3000 (copy_early_debug_info): Remove gfx900 special case, now handled as
3001 part of the generic handling.
3002 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
3004 2024-01-29 Jakub Jelinek <jakub@redhat.com>
3006 PR tree-optimization/110603
3007 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
3008 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
3009 overwritten anyway). Avoid creating invalid range with minlen
3010 larger than maxlen. Formatting fix.
3012 2024-01-29 Richard Biener <rguenther@suse.de>
3014 PR debug/103047
3015 * tree-inline.cc (initialize_inlined_parameters): Reverse
3016 the decl chain of inlined parameters.
3018 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
3020 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
3021 alignment of CFString constants by setting DECL_USER_ALIGN.
3023 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
3024 Jakub Jelinek <jakub@redhat.com>
3026 PR libgcc/113402
3027 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
3028 and BUILT_IN_GCC_NESTED_PTR_DELETED.
3029 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
3030 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
3031 rename the library fallbacks to __gcc_nested_func_ptr_created and
3032 __gcc_nested_func_ptr_deleted.
3033 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
3034 and __gcc_nested_func_ptr_deleted.
3035 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
3036 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
3037 * tree.cc (build_common_builtin_nodes): Build the
3038 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
3039 builtins only for non-explicit.
3041 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
3043 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
3045 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
3047 PR target/38534
3048 * config/i386/i386-options.cc (ix86_set_func_type): Don't
3049 save and restore callee saved registers for a noreturn function
3050 with nothrow or compiled with -fno-exceptions.
3052 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
3054 PR target/103503
3055 PR target/113312
3056 * config/i386/i386-expand.cc (ix86_expand_call): Replace
3057 no_caller_saved_registers check with call_saved_registers check.
3058 Clobber all registers that are not used by the callee with
3059 no_callee_saved_registers attribute.
3060 * config/i386/i386-options.cc (ix86_set_func_type): Set
3061 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
3062 noreturn function. Disallow no_callee_saved_registers with
3063 interrupt or no_caller_saved_registers attributes together.
3064 (ix86_set_current_function): Replace no_caller_saved_registers
3065 check with call_saved_registers check.
3066 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
3067 (ix86_handle_call_saved_registers_attribute): This.
3068 (ix86_gnu_attributes): Add
3069 ix86_handle_call_saved_registers_attribute.
3070 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
3071 no_caller_saved_registers check with call_saved_registers check.
3072 (ix86_function_ok_for_sibcall): Don't allow callee with
3073 no_callee_saved_registers attribute when the calling function
3074 has callee-saved registers.
3075 (ix86_comp_type_attributes): Also check
3076 no_callee_saved_registers.
3077 (ix86_epilogue_uses): Replace no_caller_saved_registers check
3078 with call_saved_registers check.
3079 (ix86_hard_regno_scratch_ok): Likewise.
3080 (ix86_save_reg): Replace no_caller_saved_registers check with
3081 call_saved_registers check. Don't save any registers for
3082 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
3083 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
3084 no_callee_saved_registers attribute is called.
3085 (find_drap_reg): Replace no_caller_saved_registers check with
3086 call_saved_registers check.
3087 * config/i386/i386.h (call_saved_registers_type): New enum.
3088 (machine_function): Replace no_caller_saved_registers with
3089 call_saved_registers.
3090 * doc/extend.texi: Document no_callee_saved_registers attribute.
3092 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3094 PR tree-optimization/113614
3095 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
3096 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
3097 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
3099 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3101 PR tree-optimization/113568
3102 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
3103 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
3104 in the widening extension checks.
3106 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3108 * gimple-lower-bitint.cc (gimple_lower_bitint): For
3109 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
3111 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
3113 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
3114 the warning for an attribute-always_inline without inline declaration.
3116 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
3118 PR other/113575
3119 * genopinit.cc (main): Split init_all_optabs into functions
3120 of 1000 patterns each.
3122 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
3124 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
3125 TM_MULTILIB_CONFIG.
3126 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
3127 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
3128 -march/-mtune.
3130 2024-01-26 Andrew Stubbs <ams@baylibre.com>
3132 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
3133 * config/gcn/gcn-valu.md (all_convert): New iterator.
3134 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
3135 define_expand, and rename the old one to ...
3136 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
3137 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
3138 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
3139 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
3140 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
3141 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
3142 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
3143 (<u>mulqihi3_scalar): Likewise.
3145 2024-01-26 Richard Biener <rguenther@suse.de>
3147 PR tree-optimization/113602
3148 * tree-data-ref.cc (dr_analyze_innermost): Fail when
3149 the base object isn't addressable.
3151 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
3153 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
3154 "--amdhsa-code-object-version=" argument.
3155 (ASM_SPEC): Use it; replace previous version of it.
3157 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3159 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
3160 (pre_vsetvl::emit_vsetvl): Ditto.
3162 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
3164 * config/loongarch/lasx.md (vec_extract<mode>_0):
3165 New define_insn_and_split patten.
3167 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
3169 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
3171 2024-01-26 Li Wei <liwei@loongson.cn>
3173 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
3175 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3177 PR target/113469
3178 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
3180 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
3182 PR target/100212
3183 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
3184 undefined shift after the call to exact_log2.
3186 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
3188 PR target/100204
3189 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
3190 before taking the negative of it.
3192 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
3194 PR target/113526
3195 * lra-constraints.cc (curr_insn_transform): Change class even for
3196 spilled pseudo successfully matched with with NO_REGS.
3198 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
3200 PR target/113601
3201 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
3203 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
3205 PR target/112987
3206 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
3207 (aarch64_expand_epilogue): Use the new function.
3208 (aarch64_split_compare_and_swap): Likewise.
3209 (aarch64_split_atomic_op): Likewise.
3211 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
3213 PR middle-end/112971
3214 * fold-const.cc (simplify_const_binop): New function for binop
3215 simplification of two constant vectors when element-wise
3216 handling is not necessary.
3217 (const_binop): Call new function.
3219 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
3221 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
3222 * config/riscv/constraints.md: Likewise.
3223 * config/riscv/corev.def: Likewise.
3224 * config/riscv/corev.md: Likewise.
3225 * config/riscv/predicates.md: Likewise.
3226 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
3227 * config/riscv/riscv-ftypes.def: Likewise.
3228 * config/riscv/riscv.opt: Likewise.
3229 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
3230 * doc/extend.texi: Add XCVbitmanip builtin documentation.
3231 * doc/sourcebuild.texi: Likewise.
3233 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
3235 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
3237 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
3239 PR target/113538
3240 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
3241 (riscv_fntype_abi): Ditto.
3242 * config/riscv/riscv.opt: Ditto.
3244 2024-01-25 Jakub Jelinek <jakub@redhat.com>
3246 PR middle-end/113574
3247 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
3248 count against TYPE_PRECISION rather than TYPE_SIZE.
3250 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3252 PR target/113572
3253 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
3254 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
3256 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3258 PR target/113550
3259 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
3260 whether each split instruction is a load that clobbers the source
3261 address. Emit that instruction last if so.
3263 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3265 PR target/113485
3266 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
3267 pattern.
3268 (<optab><Vnarrowq><mode>2): Use it instead of generating a
3269 paradoxical subreg for the input.
3271 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3273 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
3274 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
3275 predecessors dump information.
3277 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3279 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
3280 redundant full available computation.
3281 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3283 2024-01-25 Jakub Jelinek <jakub@redhat.com>
3285 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
3286 * doc/rtl.texi (CONST_VECTOR): Likewise.
3288 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3290 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
3291 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
3292 (pass_vsetvl::execute): Ditto.
3293 * config/riscv/riscv.opt: Ditto.
3295 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
3297 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
3298 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
3300 2024-01-25 Richard Biener <rguenther@suse.de>
3302 PR tree-optimization/113576
3303 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
3304 exits with may_be_zero niters when its the last one.
3306 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
3308 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3309 For symbols of type tls, non-zero Offset is not generated.
3311 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
3313 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
3314 P9 with m32 and mpowerpc64.
3316 2024-01-25 liuhongt <hongtao.liu@intel.com>
3318 * config/i386/i386-options.cc (ix86_option_override_internal):
3319 Enable -mlam=u57 by default when compiled with
3320 -fsanitize=hwaddress.
3322 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
3324 * common/config/riscv/riscv-common.cc (riscv_implied_info):
3325 Remove {"ztso", "a"}.
3327 2024-01-24 Martin Jambor <mjambor@suse.cz>
3329 PR ipa/108007
3330 PR ipa/112616
3331 * cgraph.h (cgraph_edge): Add a parameter to
3332 redirect_call_stmt_to_callee.
3333 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
3334 parameter to modify_call.
3335 (ipa_release_ssas_in_hash): Declare.
3336 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
3337 parameter killed_ssas, pass it to padjs->modify_call.
3338 * ipa-param-manipulation.cc (purge_all_uses): New function.
3339 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
3340 Instead of substituting uses, invoke purge_all_uses. If
3341 hash of killed SSAs has not been provided, create a temporary one
3342 and release SSAs that have been added to it.
3343 (compare_ssa_versions): New function.
3344 (ipa_release_ssas_in_hash): Likewise.
3345 * tree-inline.cc (redirect_all_calls): Create
3346 id->killed_new_ssa_names earlier, pass it to edge redirection,
3347 adjust a comment.
3348 (copy_body): Release SSAs in id->killed_new_ssa_names.
3350 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
3352 PR target/113486
3353 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
3354 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
3356 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
3358 PR target/113095
3359 * config/riscv/sfb.md: New splitters to rewrite single bit
3360 sign extension as the condition to SFB instructions.
3362 2024-01-24 Jan Hubicka <jh@suse.cz>
3364 PR middle-end/88345
3365 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
3366 (fmin-function-alignment): New parameter.
3367 * doc/invoke.texi: (-fmin-function-alignment): Document.
3368 (-falign-functions,-falign-loops,-falign-labels): Mention that
3369 aglinments are ignored in cold code.
3370 * varasm.cc (assemble_start_function): Handle min-function-alignment.
3372 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3374 PR target/109636
3375 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
3376 mulv2di3): Remove.
3377 * config/aarch64/iterators.md (VQDIV): Remove.
3378 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
3379 SVE_I_SIMD_DI): New.
3380 (VPRED, sve_lane_con): Add V4SI and V2DI.
3381 * config/aarch64/aarch64-sve.md (<optab><mode>3,
3382 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
3383 (mul<mode>3): New, split from <optab><mode>3.
3384 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
3385 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
3386 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
3387 SVE_FULL_HSDI_SIMD_DI.
3389 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3391 PR tree-optimization/113552
3392 * config/aarch64/aarch64.cc
3393 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
3395 2024-01-24 Martin Jambor <mjambor@suse.cz>
3397 PR ipa/113490
3398 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
3399 count is equal or greater than the limit. Use the limit from the
3400 callee.
3402 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
3404 * configure.ac: Detect the explicit relocs support for
3405 mips, and define C macro MIPS_EXPLICIT_RELOCS.
3406 * config.in: Regenerated.
3407 * configure: Regenerated.
3408 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
3409 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
3410 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
3411 !TARGET_EXPLICIT_RELOCS instead of just set it.
3412 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
3413 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
3414 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
3415 and define -m(no-)explicit-relocs as aliases.
3417 2024-01-24 Alex Coplan <alex.coplan@arm.com>
3419 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
3420 to 1.
3421 (-mlate-ldp-fusion): Likewise.
3423 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3425 * tree-vect-loop.cc (vect_get_vect_def,
3426 vect_create_epilog_for_reduction): Rename main_exit_p to
3427 last_val_reduc_p.
3429 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3431 PR tree-optimization/113364
3432 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
3433 early exits then we must reduce from the first offset for all of them.
3435 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3437 PR target/113495
3438 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
3439 (get_regno): Ditto.
3440 (get_bb_index): Ditto.
3441 (pre_vsetvl::compute_avl_def_data): Ditto.
3442 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
3443 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3445 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
3446 Richard Sandiford <richard.sandiford@arm.com>
3448 PR target/100942
3449 * ccmp.cc (ccmp_candidate_p): Add outer argument.
3450 Allow if the outer is true and the lhs is used more
3451 than once.
3452 (expand_ccmp_expr): Update call to ccmp_candidate_p.
3453 * expr.h (expand_expr_real_gassign): Declare.
3454 * expr.cc (expand_expr_real_gassign): New function, split out from...
3455 (expand_expr_real_1): ...here.
3456 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
3458 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3460 PR target/113089
3461 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
3462 (fixup_debug_use): New.
3463 (fixup_debug_uses_trailing_add): New.
3464 (fixup_debug_uses): New. Use it ...
3465 (ldp_bb_info::fuse_pair): ... here.
3466 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
3467 fix up debug uses of the base register that are affected by
3468 folding in the trailing add insn.
3470 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3472 PR target/113089
3473 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
3474 Update trailing nondebug uses of the base register in the case
3475 of cancelling writeback.
3477 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3479 PR target/113089
3480 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
3481 (debug_insn_use_iterator): New.
3482 (set_info::first_debug_insn_use): New.
3483 (set_info::debug_insn_uses): New.
3484 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
3485 (set_info::first_debug_insn_use): New.
3486 (set_info::debug_insn_uses): New.
3488 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3490 PR target/113356
3491 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
3492 Don't record hazards against the opposite insn in the pair.
3494 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3496 PR target/113070
3497 * config/aarch64/aarch64-ldp-fusion.cc
3498 (struct stp_change_builder): New.
3499 (decide_stp_strategy): Reanme to ...
3500 (try_repurpose_store): ... this.
3501 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
3502 construct stp changes. Fix up uses when inserting new stp insns.
3504 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3506 PR target/113070
3507 * rtl-ssa.h: Include hash-set.h.
3508 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
3509 new_sets parameter and use it to keep track of new user-created sets.
3510 (function_info::apply_changes_to_insn): Also call add_def on new sets.
3511 (function_info::change_insns): Add hash_set to keep track of new
3512 user-created defs. Plumb it through.
3513 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
3514 apply_changes_to_insn.
3516 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3518 PR target/113070
3519 * rtl-ssa/accesses.cc (function_info::create_use): New.
3520 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
3521 Ensure new uses end up referring to permanent defs.
3522 * rtl-ssa/functions.h (function_info::create_use): Declare.
3524 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3526 PR target/113070
3527 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
3528 to finalize_new_accesses from the backwards placement loop, run it
3529 forwards in a separate loop.
3531 2024-01-23 Richard Biener <rguenther@suse.de>
3533 PR tree-optimization/113552
3534 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
3535 floor_log2 instead of exact_log2 on the number of calls.
3537 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
3538 Jakub Jelinek <jakub@redhat.com>
3540 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
3541 decl.
3543 2024-01-23 Richard Biener <rguenther@suse.de>
3545 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3546 Separate single and multi-exit case when creating PHIs between
3547 the main and epilogue.
3549 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
3551 PR target/112989
3552 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
3553 MODE_single variants of functions that don't take tuple arguments.
3555 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3557 PR target/113114
3558 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
3559 Don't assert recog success, just punt if the writeback pair
3560 isn't recognized.
3562 2024-01-23 Jakub Jelinek <jakub@redhat.com>
3564 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
3565 ATTRIBUTE_UNUSED to decl.
3567 2024-01-23 Richard Biener <rguenther@suse.de>
3569 PR debug/107058
3570 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
3571 handle unexpected but bogus DIE contexts when not checking
3572 enabled.
3574 2024-01-23 Jakub Jelinek <jakub@redhat.com>
3576 PR tree-optimization/113462
3577 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
3578 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
3579 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
3580 sizes between 129 and 8192 bytes.
3582 2024-01-23 Xi Ruoyao <xry111@xry111.site>
3584 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3585 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
3586 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
3587 (loongarch_call_tls_get_addr): Do not split symbols of
3588 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
3589 EXPLICIT_RELOCS_AUTO.
3591 2024-01-23 Richard Biener <rguenther@suse.de>
3593 * alias.cc (known_base_value_p): Remove.
3594 (find_base_value): Remove PLUS/MINUS handling
3595 when both operands are not CONST_INT_P.
3597 2024-01-23 Richard Biener <rguenther@suse.de>
3599 PR rtl-optimization/113255
3600 * alias.cc (find_base_term): Remove PLUS/MINUS handling
3601 when both operands are not CONST_INT_P.
3603 2024-01-23 Richard Biener <rguenther@suse.de>
3605 PR debug/112718
3606 * dwarf2out.cc (dwarf2out_finish): Reset all type units
3607 for the fat part of an LTO compile.
3609 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
3611 * doc/sourcebuild.texi: Add attributes for keywords.
3613 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
3615 PR c++/90463
3616 * doc/invoke.texi (Warning Options): Correct lists of options
3617 enabled by -Wall and -Wextra by checking against common.opt
3618 and c-family/c.opt.
3620 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
3622 PR target/113030
3623 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
3624 instead of cpu_optaliases.
3625 (check_arch): Use arch_opt_alias instead of arch_optaliases.
3627 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3629 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
3630 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
3631 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
3633 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3635 PR target/109092
3636 * config/riscv/riscv.md: Use reg instead of subreg.
3638 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
3640 PR other/111966
3641 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
3642 to match the compiler default.
3643 (simple_object_copy_lto_debug_sections): Never unlink the outfile
3644 on error as the caller does so.
3645 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
3646 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
3648 2024-01-22 Richard Biener <rguenther@suse.de>
3650 PR tree-optimization/113373
3651 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3652 Create LC PHIs in the exit blocks where necessary.
3653 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
3654 to handle missing LC PHIs.
3655 (find_connected_edge): Remove.
3656 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
3658 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3660 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
3662 2024-01-22 xuli <xuli1@eswincomputing.com>
3664 PR target/113420
3665 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
3666 (registered_function::overloaded_hash):refactor.
3667 (resolve_overloaded_builtin):avoid internal ICE.
3669 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
3671 PR target/82420
3672 PR target/111279
3673 * calls.cc (emit_library_call_value_1): Pass valid TYPE
3674 to emit_push_insn.
3675 * expr.cc (emit_push_insn): Likewise.
3677 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
3679 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
3680 correcction version of last change.
3682 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
3684 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
3685 fix bugs in signature.
3687 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
3688 Richard Biener <rguenther@suse.de>
3690 PR rtl-optimization/111267
3691 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
3692 profitable_p method to likely_profitable_p.
3693 (try_fwprop_subst_node): Update call to likely_profitable_p.
3694 Only bail-out early when !prop.likely_profitable_p for instructions
3695 that are not single sets. When comparing costs, bail-out if the
3696 cost is unchanged and !prop.likely_profitable_p.
3698 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
3700 PR c++/90464
3701 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
3702 isn't enabled by -Wunused unless -Wextra is provided, and that
3703 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
3704 -Wunused doesn't enable -Wunused-* options documented as behaving
3705 otherwise, and list them explicitly.
3707 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
3709 PR c/109708
3710 * doc/invoke.texi (Warning Options): Fix broken example and
3711 clean up/reorganize the others. Also describe what the short-form
3712 options mean.
3714 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
3716 PR c/102998
3717 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
3718 (Warning Options): Correct/edit discussion of -Warray-parameter
3719 to make the first example less confusing, and fill in missing info.
3721 2024-01-20 Jakub Jelinek <jakub@redhat.com>
3723 PR tree-optimization/113462
3724 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
3725 Handle rhs1 INTEGER_CST like SSA_NAME.
3727 2024-01-20 Jakub Jelinek <jakub@redhat.com>
3729 PR tree-optimization/113491
3730 * tree-switch-conversion.cc (switch_conversion::build_constructors):
3731 If elt.index has precision higher than sizetype, fold_convert it to
3732 sizetype.
3733 (switch_conversion::array_value_type): Return type if type is
3734 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
3735 (switch_conversion::build_arrays): Use unsigned_type_for rather than
3736 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
3737 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
3738 higher than sizetype, use sizetype as tidx type and fold_convert the
3739 subtraction to sizetype.
3741 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3743 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
3744 (riscv_vector_mode_supported_any_target_p): Ditto.
3746 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
3748 PR target/110934
3749 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
3750 (TARGET_ZERO_CALL_USED_REGS): Define.
3752 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
3754 PR target/108640
3755 * config/m68k/m68k.cc (output_andsi3): Use QImode for
3756 address adjusted for 1-byte RMW access.
3757 (output_iorsi3): Likewise.
3758 (output_xorsi3): Likewise.
3760 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3762 * doc/invoke.texi (RISC-V Options): Add list of supported
3763 extensions.
3765 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3767 PR target/113495
3768 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
3769 (RVV_VUNDEF): Ditto.
3770 * config/riscv/riscv-vsetvl.cc: Add timevar.
3772 2024-01-19 Richard Biener <rguenther@suse.de>
3774 PR debug/113488
3775 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
3776 an early DIE but there should be, do not pretend there is.
3778 2024-01-19 Richard Biener <rguenther@suse.de>
3780 PR tree-optimization/113494
3781 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3782 Handle endless loop on exit. Handle re-allocated PHI.
3784 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3786 PR tree-optimization/113464
3787 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
3788 optimize loads into GIMPLE_ASM stmts.
3790 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3792 PR tree-optimization/113463
3793 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
3794 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
3795 lhs.
3797 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3799 PR tree-optimization/113459
3800 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
3801 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
3802 of SCALAR_INT_TYPE_MODE if type has BLKmode.
3803 (vn_reference_lookup_3): Likewise. Formatting fix.
3805 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3806 Richard Biener <rguenther@suse.de>
3808 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
3809 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
3810 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
3811 but adjust_address also for BLKmode mode and MEM op0.
3813 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
3815 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
3816 extensions.
3818 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3820 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
3822 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3824 * common/config/riscv/riscv-common.cc
3825 (riscv_subset_list::parse_std_ext): Remove.
3826 (riscv_subset_list::parse_multiletter_ext): Remove.
3827 * config/riscv/riscv-subset.h
3828 (riscv_subset_list::parse_std_ext): Remove.
3829 (riscv_subset_list::parse_multiletter_ext): Remove.
3831 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3833 * common/config/riscv/riscv-common.cc
3834 (riscv_subset_list::parse_single_std_ext): New parameter.
3835 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3836 (riscv_subset_list::parse_single_ext): Ditto.
3837 (riscv_subset_list::parse): Relax the order for the input of ISA
3838 string.
3839 * config/riscv/riscv-subset.h
3840 (riscv_subset_list::parse_single_std_ext): New parameter.
3841 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3842 (riscv_subset_list::parse_single_ext): Ditto.
3844 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3846 * common/config/riscv/riscv-common.cc
3847 (riscv_subset_list::parse_base_ext): New.
3848 (riscv_subset_list::parse): Extract part of logic into
3849 riscv_subset_list::parse_base_ext.
3850 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
3851 New.
3853 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3855 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
3856 sorry message.
3858 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
3860 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
3861 UNSPEC_CLMUL_VC.
3863 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
3865 PR c/110029
3866 * doc/extend.texi (Common Variable Attributes): Explain what
3867 happens when multiple variables with cleanups are in the same scope.
3869 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3871 PR ipa/108470
3872 * doc/extend.texi (Common Function Attributes): Document that
3873 noinline also disables some interprocedural optimizations and
3874 improve flow to the part about using inline asm instead to
3875 disable calls from being optimized away completely. Remove the
3876 sentence that says noipa is mainly for internal compiler testing.
3878 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
3880 PR tree-optimization/69807
3881 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
3883 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
3885 PR target/108521
3886 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
3887 from x86 Windows Options.
3889 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3891 PR c/107942
3892 * doc/extend.texi (C Extensions): Add new section to menu.
3893 (Function Attributes): Move dangling index entries to....
3894 (Const and Volatile Functions): New section.
3896 2024-01-18 David Malcolm <dmalcolm@redhat.com>
3898 PR middle-end/112684
3899 * toplev.cc (toplev::main): Don't ICE in
3900 -fdiagnostics-generate-patch when exiting after options,
3901 since no edit context will have been created.
3903 2024-01-18 Richard Biener <rguenther@suse.de>
3905 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
3906 operands vector.
3908 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3910 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
3911 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
3913 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3914 Jin Ma <jinma@linux.alibaba.com>
3915 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3916 Christoph Müllner <christoph.muellner@vrull.eu>
3918 * config/riscv/thead.cc
3919 (th_asm_output_opcode): Rewrite some instructions.
3921 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3922 Jin Ma <jinma@linux.alibaba.com>
3923 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3924 Christoph Müllner <christoph.muellner@vrull.eu>
3926 * config/riscv/riscv.md (none,thv,rvv): New attribute.
3927 (no,yes): Add an attribute to disable alternative
3928 for xtheadvector or RVV1.0.
3929 * config/riscv/vector.md:
3930 Disable alternatives that destination register overlaps
3931 source register group for xtheadvector.
3933 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3934 Jin Ma <jinma@linux.alibaba.com>
3935 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3936 Christoph Müllner <christoph.muellner@vrull.eu>
3938 * config/riscv/riscv-vector-builtins-bases.cc
3939 (class th_loadstore_width): Define new builtin bases.
3940 (class th_extract): Define new builtin bases.
3941 (BASE): Define new builtin bases.
3942 * config/riscv/riscv-vector-builtins-bases.h:
3943 Define new builtin class.
3944 * config/riscv/riscv-vector-builtins-shapes.cc
3945 (struct th_loadstore_width_def): Define new builtin shapes.
3946 (struct th_indexed_loadstore_width_def):
3947 Define new builtin shapes.
3948 (struct th_extract_def): Define new builtin shapes.
3949 (SHAPE): Define new builtin shapes.
3950 * config/riscv/riscv-vector-builtins-shapes.h:
3951 Define new builtin shapes.
3952 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
3953 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
3954 * config/riscv/riscv-vector-builtins.h
3955 (enum required_ext): Add new XTheadVector member.
3956 (struct function_group_info): Likewise.
3957 * config/riscv/t-riscv:
3958 Add thead-vector-builtins-functions.def
3959 * config/riscv/thead-vector.md
3960 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
3961 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
3962 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
3963 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
3964 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
3965 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
3966 (@pred_th_extract<mode>): Likewise.
3967 (*pred_th_extract<mode>): Likewise.
3968 * config/riscv/thead-vector-builtins-functions.def: New file.
3970 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3971 Jin Ma <jinma@linux.alibaba.com>
3972 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3973 Christoph Müllner <christoph.muellner@vrull.eu>
3975 * config.gcc: Add files for XTheadVector intrinsics.
3976 * config/riscv/autovec.md: Guard XTheadVector.
3977 * config/riscv/predicates.md: Disable immediate vl
3978 for XTheadVector.
3979 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
3980 Add pragma for XTheadVector.
3981 * config/riscv/riscv-string.cc (riscv_expand_block_move):
3982 Guard XTheadVector.
3983 * config/riscv/riscv-v.cc (vls_mode_valid_p):
3984 Avoid autovec.
3985 * config/riscv/riscv-vector-builtins-bases.cc:
3986 Do not normalize vsetvl instructions for XTheadVector.
3987 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
3988 New check type function.
3989 (build_one): Adjust for XTheadVector.
3990 * config/riscv/riscv-vector-switch.def (ENTRY):
3991 Disable fractional mode for the XTheadVector extension.
3992 (TUPLE_ENTRY): Likewise.
3993 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
3994 Guard XTheadVector.
3995 (riscv_preferred_simd_mode): Likewsie.
3996 (riscv_autovectorize_vector_modes): Likewise.
3997 (riscv_vector_mode_supported_any_target_p): Likewise.
3998 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
3999 * config/riscv/thead.cc (th_asm_output_opcode):
4000 Rewrite vsetvl instructions.
4001 * config/riscv/vector.md:
4002 Include thead-vector.md and change fractional LMUL
4003 into 1 for vbool.
4004 * config/riscv/riscv_th_vector.h: New file.
4005 * config/riscv/thead-vector.md: New file.
4007 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4008 Jin Ma <jinma@linux.alibaba.com>
4009 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4010 Christoph Müllner <christoph.muellner@vrull.eu>
4012 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
4013 Add new function to add assembler insn code prefix/suffix.
4014 (th_asm_output_opcode):
4015 Add Thead function to add assembler insn code prefix/suffix.
4016 * config/riscv/riscv.cc (riscv_asm_output_opcode):
4017 Implement function to add assembler insn code prefix/suffix.
4018 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
4019 Add new function to add assembler insn code prefix/suffix.
4020 * config/riscv/thead.cc (th_asm_output_opcode):
4021 Implement Thead function to add assembler insn code
4022 prefix/suffix.
4024 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4025 Jin Ma <jinma@linux.alibaba.com>
4026 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4027 Christoph Müllner <christoph.muellner@vrull.eu>
4029 * common/config/riscv/riscv-common.cc
4030 (riscv_subset_list::parse): Add new vendor extension.
4031 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
4032 Add test marco.
4033 * config/riscv/riscv.opt: Add new mask.
4035 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4037 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
4038 to be conditional on macosx-version-min.
4040 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4042 * config/darwin.cc (darwin_objc1_section): Use the correct
4043 meta-data version for constant strings.
4044 (machopic_select_section): Assert if we fail to handle CFString
4045 sections as Obejctive-C meta-data or drectly.
4047 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4049 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
4050 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
4051 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
4052 versions when the object format is Mach-O.
4054 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4056 PR target/105522
4057 * config/darwin.cc (machopic_select_section): Handle C and C++
4058 CFStrings.
4059 (darwin_rename_builtins): Move this out of the CFString code.
4060 (darwin_libc_has_function): Likewise.
4061 (darwin_build_constant_cfstring): Create an anonymous var to
4062 hold each CFString.
4063 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
4064 CFstrings.
4066 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
4068 PR bootstrap/113445
4069 * haifa-sched.cc (dep_list_size): Make global.
4070 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
4071 * sched-int.h (dep_list_size): Declare.
4073 2024-01-18 Martin Jambor <mjambor@suse.cz>
4075 PR tree-optimization/110422
4076 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
4077 gotos.
4079 2024-01-18 Richard Biener <rguenther@suse.de>
4081 PR tree-optimization/113475
4082 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
4083 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
4084 (phi_analyzer::~phi_analyzer): Deallocate and free collected
4085 phi_grous.
4086 (phi_analyzer::process_phi): Record allocated phi_groups.
4088 2024-01-18 Richard Biener <rguenther@suse.de>
4090 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
4091 storage for gvec_oprnds elements.
4093 2024-01-18 Richard Biener <rguenther@suse.de>
4095 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
4096 prefer all later exits we can handle.
4097 (vect_analyze_loop_form): Free the allocated loop body.
4098 Adjust comments.
4100 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4102 * config/avr/avr-log.cc: Tabify.
4104 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4106 * config/riscv/autovec.md: Support vi variant.
4108 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4110 * config/avr/avr-devices.cc: Tabify.
4112 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4114 * config/avr/avr-c.cc: Tabify.
4116 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4118 * config/avr/driver-avr.cc: Tabify.
4120 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4122 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
4124 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4126 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
4128 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4130 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
4131 minline-strcmp, minline-strncmp, minline-strlen,
4132 -param=riscv-vector-abi): Remove Bool keywords.
4134 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4136 PR target/113122
4137 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
4138 support. Add missing space after , in emitted assembly in some
4139 cases. Formatting fixes.
4141 2024-01-18 Xi Ruoyao <xry111@xry111.site>
4143 * config/loongarch/loongarch.md (movsi_internal): Remove
4144 constraint z.
4146 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4148 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
4149 in the diagnostic, and capitalize the device name.
4150 (print_mcu): Generate specs such that:
4151 <*check_rodata_in_ram>: New.
4152 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
4153 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
4154 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
4156 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4158 PR other/113399
4159 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
4160 Common and Optimization.
4162 2024-01-18 Richard Biener <rguenther@suse.de>
4164 PR tree-optimization/113431
4165 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
4166 When there is an invariant load we might not preserve
4167 scalar order.
4169 2024-01-18 Richard Biener <rguenther@suse.de>
4171 PR tree-optimization/113374
4172 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
4173 * tree-vect-loop.cc (move_early_exit_stmts): Update
4174 virtual LC PHIs.
4175 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4176 Refactor. Preserve virtual LC PHIs on all exits.
4178 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
4180 * config/loongarch/loongarch.cc (loongarch_split_symbol):
4181 Assign the '/u' attribute to the mem.
4183 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4185 PR middle-end/110847
4186 * doc/invoke.texi (Option Summary): Document negative forms of
4187 -Wtsan and -Wxor-used-as-pow.
4188 (Warning Options): Likewise.
4190 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4192 PR target/113429
4193 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
4195 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4197 * doc/extend.texi (Common Function Attributes): Re-alphabetize
4198 the table.
4199 (Common Variable Attributes): Likewise.
4200 (Common Type Attributes): Likewise.
4202 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4204 PR middle-end/111659
4205 * doc/extend.texi (Common Variable Attributes): Fix long lines
4206 in documentation of strict_flex_array + other minor copy-editing.
4207 Add a cross-reference to -Wstrict-flex-arrays.
4208 * doc/invoke.texi (Option Summary): Fix whitespace in tables
4209 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
4210 (C Dialect Options): Combine the docs for the two
4211 -fstrict-flex-arrays forms into a single entry. Note this option
4212 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
4213 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
4214 Minor copy-editing. Add cross references to the strict_flex_array
4215 attribute and -fstrict-flex-arrays option. Add note that this
4216 option depends on -ftree-vrp.
4218 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
4220 PR target/113221
4221 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
4222 only allow REG operands instead of allowing all.
4224 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
4226 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
4227 Remove redundant checks in else condition for readablity.
4228 (earliest_fuse_vsetvl_info) Print iteration count in debug
4229 prints.
4230 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
4231 dump details in certain cases.
4233 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
4235 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
4236 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
4237 * config/riscv/riscv-vsetvl.cc
4238 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
4239 (pass_vsetvl::execute): Use vsetvl_strategy.
4241 2024-01-17 Jan Hubicka <jh@suse.cz>
4243 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
4244 accidental hack reseting offset.
4246 2024-01-17 Jan Hubicka <jh@suse.cz>
4248 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
4249 handling of X86_TUNE_AVOID_512FMA_CHAINS.
4251 2024-01-17 Jan Hubicka <jh@suse.cz>
4252 Jakub Jelinek <jakub@redhat.com>
4254 PR tree-optimization/110852
4255 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
4256 binary operations
4257 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
4258 PRED_COMBINED_VALUE_PREDICTIONS_PHI
4259 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
4260 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
4262 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4264 PR tree-optimization/113421
4265 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
4266 comment.
4267 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
4268 formatting. Start at vop rather than cvop even if stmt is a store
4269 and needs_operand_addr.
4271 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4273 PR middle-end/113410
4274 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
4275 If access_nelts is integral with larger precision than sizetype,
4276 fold_convert it to sizetype.
4278 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4280 PR tree-optimization/113408
4281 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
4282 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
4283 to handle_cast.
4285 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4287 PR middle-end/113406
4288 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
4289 regardless of whether is_gimple_reg_type (restype) or not.
4291 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4293 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
4294 funcions -> functions, and use were instead of was.
4295 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
4296 and guaranteee -> guarantee.
4297 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
4299 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4301 PR middle-end/113409
4302 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
4303 INTEGER_TYPE.
4304 (omp_extract_for_data): Use build_bitint_type rather than
4305 build_nonstandard_integer_type if either iter_type or loop->v type
4306 is BITINT_TYPE.
4307 * omp-expand.cc (expand_omp_for_generic,
4308 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
4309 BITINT_TYPE like INTEGER_TYPE.
4311 2024-01-17 Richard Biener <rguenther@suse.de>
4313 PR tree-optimization/113371
4314 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
4315 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4316 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
4317 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4319 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
4321 PR rtl-optimization/96388
4322 PR rtl-optimization/111554
4323 * sched-deps.cc (find_inc): Avoid exponential behavior.
4325 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4327 PR c/111693
4328 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
4329 from C++ Language Options to Warning Options. Add entry for
4330 -Wuse-after-free.
4331 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
4332 from here....
4333 (Warning Options): ...to here. Minor copy-editing to fix typo
4334 and grammar.
4336 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
4338 * config/mips/mips.cc (mips_compute_frame_info): If another
4339 register is used as global_pointer, mark $GP live false.
4341 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4343 PR target/112973
4344 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
4345 give the section a light copy-editing pass.
4347 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
4349 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
4350 * config/aarch64/aarch64-tune.md: Regenerated.
4351 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
4353 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
4355 PR target/112573
4356 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
4357 badly formed CONST expressions.
4359 2024-01-16 Daniel Cederman <cederman@gaisler.com>
4361 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
4363 2024-01-16 Daniel Cederman <cederman@gaisler.com>
4365 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
4366 * config/sparc/sync.md (membar_storeload): Turn into named insn
4367 and add GR712RC errata workaround.
4368 (membar_v8): Add GR712RC errata workaround.
4370 2024-01-16 Andreas Larsson <andreas@gaisler.com>
4372 * config/sparc/sync.md (*membar_storeload_leon3): Remove
4373 (*membar_storeload): Enable for LEON
4375 2024-01-16 Jakub Jelinek <jakub@redhat.com>
4377 PR tree-optimization/113372
4378 PR middle-end/90348
4379 PR middle-end/110115
4380 PR middle-end/111422
4381 * cfgexpand.cc (add_scope_conflicts_2): New function.
4382 (add_scope_conflicts_1): Use it.
4384 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
4386 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
4387 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
4388 * doc/avr-mmcu.texi: Regenerate.
4390 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
4392 PR tree-optimization/113091
4393 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
4394 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
4395 scalar use with new function.
4396 (vect_bb_slp_mark_live_stmts): New function as entry to existing
4397 overriden functions with same name.
4398 (vect_slp_analyze_operations): Call new entry function to mark
4399 live statements.
4401 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4403 PR target/113404
4404 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
4405 for RVV in big-endian mode.
4407 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
4409 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
4410 (riscv_pass_in_vector_p): Delete.
4411 (riscv_init_cumulative_args): Delete the checking.
4412 (riscv_get_arg_info): Delete the checking.
4413 (riscv_function_value): Delete the checking.
4414 * config/riscv/riscv.h: Delete the member for checking.
4416 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
4418 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
4420 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
4422 * config.gcc: Include riscv_bitmanip.h.
4423 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
4424 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
4425 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
4426 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
4427 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
4428 * config/riscv/riscv-ftypes.def (2): New ftypes.
4429 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
4430 (RISCV_BUILTIN_NO_PREFIX): Likewise.
4431 * config/riscv/riscv_bitmanip.h: New file.
4433 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
4435 * config.gcc: Include riscv_crypto.h.
4436 * config/riscv/riscv_crypto.h: New file.
4438 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
4440 PR middle-end/113354
4441 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
4442 in the insn if the corresponding operand does not require hard
4443 register anymore.
4445 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
4447 PR target/107201
4448 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
4449 * config/avr/driver-avr.cc (avr_no_devlib): New function.
4450 (avr_devicespecs_file): Use it to remove -nodevicelib from the
4451 options for cores only.
4452 * config/avr/avr-arch.h (avr_get_parch): New prototype.
4453 * config/avr/avr-devices.cc (avr_get_parch): New function.
4455 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4457 PR target/113247
4458 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
4459 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
4460 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
4462 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4464 PR target/113281
4465 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
4466 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
4467 * config/riscv/riscv-vector-costs.h: New function.
4469 2024-01-15 Richard Biener <rguenther@suse.de>
4471 PR tree-optimization/113385
4472 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4473 First redirect, then split the exit edge.
4475 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4477 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
4478 Remove m_num_vector_iterations.
4479 * config/riscv/riscv-vector-costs.h: Ditto.
4481 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
4483 PR target/113156
4484 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
4485 (-mbranch-cost): Set "Optimization" flag.
4487 2024-01-15 Jakub Jelinek <jakub@redhat.com>
4489 PR tree-optimization/113370
4490 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
4491 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
4492 set it to just prec % limb_prec.
4494 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4496 PR target/113393
4497 * config/riscv/vector.md: Fix ternary attributes.
4499 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
4501 PR target/112944
4502 * configure.ac [target=avr]: Check availability of emulations
4503 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
4504 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
4505 * configure: Regenerate.
4506 * config.in: Regenerate.
4507 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
4508 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
4509 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
4510 * config/avr/avr-arch.h (enum avr_device_specific_features):
4511 Add AVR_ISA_FLMAP.
4512 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
4513 AVR_ISA_FLMAP.
4514 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
4515 (avr_set_core_architecture): Set avr_arch_index.
4516 (have_avrxmega2_flmap, have_avrxmega4_flmap)
4517 (have_avrxmega3_rodata_in_flash): Set new static const bool according
4518 to configure results.
4519 (avr_rodata_in_flash_p): New function using them.
4520 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
4521 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
4522 (avr_asm_named_section): Track avr_has_rodata_p.
4523 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
4524 and not avr_rodata_in_flash_p ().
4525 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
4526 (LINK_SPEC): Add %(link_rodata_in_ram).
4527 (LINK_ARCH_SPEC): Remove.
4528 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
4529 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
4530 const bool according to configure results.
4531 (diagnose_mrodata_in_ram): New function.
4532 (print_mcu): Generate specs with the following changes:
4533 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
4534 need to extend avr/specs.h each time we add a new bell or whistle.
4535 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
4536 -m[no-]rodata-in-ram.
4537 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
4538 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
4539 <*cpp>: Add %(cpp_rodata_in_ram).
4540 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
4541 requested.
4542 <*self_spec>: Add -mflmap or %<mflmap as needed.
4544 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
4546 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
4547 not the GPR iterator. Adjust pattern name and mode attribute
4548 accordingly.
4550 2024-01-13 Jakub Jelinek <jakub@redhat.com>
4552 PR tree-optimization/113361
4553 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
4554 Fix up determination of the type for > limb_prec constants.
4556 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
4558 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
4559 Add web-link to the avr-gcc wiki.
4561 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
4563 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
4564 documentation for a version without argument, which is not supported.
4566 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4568 * config/arm/arm_neon.h
4569 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
4570 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
4571 (vld1_f16_x4, vld1_f32_x4): New.
4572 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
4573 (vld1_bf16_x4): New.
4574 (vld1q_types_x4): Updated to use vld1q_x4
4575 from arm_neon_builtins.def
4576 * config/arm/arm_neon_builtins.def
4577 (vld1_x4): Updated entries.
4578 (vld1q_x4): New entries, but comes from the old vld1_x4
4579 * config/arm/neon.md
4580 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
4582 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4584 * config/arm/arm_neon.h
4585 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
4586 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
4587 (vld1_f16_x3, vld1_f32_x3): New.
4588 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
4589 (vld1_bf16_x3): New.
4590 (vld1q_types_x3): Updated to use vld1q_x3 from
4591 arm_neon_builtins.def
4592 * config/arm/arm_neon_builtins.def
4593 (vld1_x3): Updated entries.
4594 (vld1q_x3): New entries, but comes from the old vld1_x2
4595 * config/arm/neon.md
4596 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
4598 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4600 * config/arm/arm_neon.h
4601 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
4602 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
4603 (vld1_f16_x2, vld1_f32_x2): New.
4604 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
4605 (vld1_bf16_x2): New.
4606 (vld1q_types_x2): Updated to use vld1q_x2 from
4607 arm_neon_builtins.def
4608 * config/arm/arm_neon_builtins.def
4609 (vld1_x2): Updated entries.
4610 (vld1q_x2): New entries, but comes from the old vld1_x2
4611 * config/arm/neon.md
4612 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
4613 neon_vld1_x2<mode>.
4615 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4617 * config/arm/arm_neon.h
4618 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
4619 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
4620 (vst1q_f16_x4, vst1q_f32_x4): New.
4621 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
4622 (vst1q_bf16_x4): New.
4623 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
4624 * config/arm/neon.md
4625 (neon_vst1q_x4<mode>): New.
4626 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
4627 * config/arm/unspecs.md
4628 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
4630 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4632 * config/arm/arm_neon.h
4633 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
4634 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
4635 (vst1q_f16_x3, vst1q_f32_x3): New.
4636 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
4637 (vst1q_bf16_x3): New.
4638 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
4639 * config/arm/neon.md
4640 (neon_vst1q_x3<mode>): New.
4641 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
4642 * config/arm/unspecs.md
4643 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
4645 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4647 * config/arm/arm_neon.h
4648 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
4649 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
4650 (vst1q_f16_x2, vst1q_f32_x2): New.
4651 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
4652 (vst1q_bf16_x2): New.
4653 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
4654 * config/arm/neon.md
4655 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
4656 neon_vst1_x2<mode>.
4657 * config/arm/iterators.md
4658 (VMEMX2): New mode iterator.
4659 (VMEMX2_q): New mode attribute.
4661 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4663 * config/arm/arm_neon.h
4664 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
4665 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
4666 (vst1_f16_x4, vst1_f32_x4): New.
4667 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
4668 (vst1_bf16_x4): New.
4669 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
4670 * config/arm/neon.md (vst1_x4<mode>): New.
4672 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4674 * config/arm/arm_neon.h
4675 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
4676 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
4677 (vst1_f16_x3, vst1_f32_x3): New.
4678 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
4679 (vst1_bf16_x3): New.
4680 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
4681 * config/arm/neon.md (vst1_x3<mode>): New.
4683 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4685 * config/arm/arm_neon.h
4686 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
4687 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
4688 (vst1_f16_x2, vst1_f32_x2): New.
4689 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
4690 (vst1_bf16_x2): New.
4691 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
4692 * config/arm/neon.md (vst1_x2<mode>): New.
4694 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4696 * config/arm/arm_neon.h
4697 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
4698 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
4699 (vld1q_f16_x4, vld1q_f32_x4): New.
4700 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
4701 (vld1q_bf16_x4): New.
4702 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
4703 * config/arm/neon.md
4704 (neon_vld1_x4<mode>): New.
4705 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
4706 * config/arm/unspecs.md
4707 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
4709 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4711 * config/arm/arm_neon.h
4712 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
4713 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
4714 (vld1q_f16_x3, vld1q_f32_x3): New.
4715 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
4716 (vld1q_bf16_x3): New.
4717 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
4718 * config/arm/neon.md
4719 (neon_vld1_x3<mode>): New.
4720 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
4721 * config/arm/unspecs.md
4722 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
4724 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4726 * config/arm/arm_neon.h
4727 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
4728 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
4729 (vld1q_f16_x2, vld1q_f32_x2): New.
4730 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
4731 (vld1q_bf16_x2): New.
4732 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
4733 * config/arm/neon.md (vld1_x2<mode>): New.
4735 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4737 PR tree-optimization/113287
4738 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
4740 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4742 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
4743 * tree-vect-loop.cc (vect_transform_loop): Likewise.
4745 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4747 PR tree-optimization/113178
4748 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
4749 alternate exits.
4751 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4753 PR tree-optimization/113237
4754 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
4755 existing LCSSA variable for exit when all exits are early break.
4757 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4759 PR tree-optimization/113137
4760 PR tree-optimization/113136
4761 PR tree-optimization/113172
4762 PR tree-optimization/113178
4763 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4764 Maintain PHIs on inverted loops.
4765 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
4766 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
4767 latch.
4768 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
4770 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4772 PR tree-optimization/113135
4773 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
4774 dependency analysis.
4776 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
4778 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
4779 diagnostics class member name for abort of error.
4781 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
4783 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
4784 format string to %s argument.
4786 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
4787 Jakub Jelinek <jakub@redhat.com>
4789 PR middle-end/113182
4790 * varasm.cc (process_pending_assemble_externals,
4791 assemble_external_libcall): Use targetm.strip_name_encoding
4792 before calling get_identifier.
4794 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4796 PR target/113196
4797 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
4798 New member variable.
4799 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
4800 Declare.
4801 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
4802 * config/aarch64/aarch64-simd.md
4803 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
4804 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
4805 zip2 for zero-extends to...
4806 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
4807 instruction. Fix big-endian handling.
4808 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
4809 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
4810 zip1 for zero-extends to...
4811 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
4812 Fix big-endian handling.
4813 (*aarch64_zip1_uxtl): New pattern.
4814 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
4815 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
4816 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
4817 (aarch64_gen_shareable_zero): Use it.
4818 (aarch64_split_simd_shift_p): New function.
4820 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4822 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
4823 (function_beg_insn): New macro.
4824 * function.cc (expand_function_start): Initialize function_beg_insn.
4826 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4828 PR target/112989
4829 * config/aarch64/aarch64-sve-builtins.h
4830 (function_builder::m_overload_names): Replace with...
4831 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
4832 new global.
4833 (add_overloaded_function): Update accordingly, using get_identifier
4834 to get a GGC-friendly record of the name.
4836 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4838 PR target/112989
4839 * config/aarch64/aarch64-sve-builtins.def: Don't include
4840 aarch64-sve-builtins-sme.def.
4841 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
4842 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
4843 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
4844 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
4845 requires AARCH64_FL_SME2.
4846 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
4847 AARCH64_FL_SME adjustment here.
4848 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
4849 include SME intrinsics.
4850 (sme_function_groups): New array.
4851 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
4852 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
4854 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4856 PR target/113281
4857 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
4858 (struct cpu_vector_cost): Add regmove struct.
4859 (get_vector_costs): Export as global.
4860 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
4861 (costs::add_stmt_cost): Ditto.
4862 * config/riscv/riscv.cc (get_common_costs): Export global function.
4864 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4866 PR tree-optimization/113334
4867 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
4868 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
4869 to determine if number should be extended by all ones rather than zero
4870 extended.
4872 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4874 PR tree-optimization/113330
4875 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
4876 too large size.
4878 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4880 PR tree-optimization/113323
4881 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
4882 check for lhs being large/huge _BitInt not in m_names.
4884 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4886 PR tree-optimization/113316
4887 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
4888 uninitialized large/huge _BitInt arguments to calls.
4890 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4892 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
4893 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
4894 CEIL (TYPE_PRECISION (t), limb_prec).
4895 (bitint_large_huge::handle_cast): Likewise.
4897 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
4899 PR sanitizer/113284
4900 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
4901 Use assemble_function_label_final () for Power ELF V1 ABI.
4902 * output.h (assemble_function_label_final): New function.
4903 * varasm.cc (assemble_function_label_raw): Use
4904 assemble_function_label_final ().
4905 (assemble_function_label_final): New function.
4907 2024-01-12 Richard Biener <rguenther@suse.de>
4909 PR middle-end/113344
4910 * match.pd ((double)float CMP (double)float -> float CMP float):
4911 Perform result type check only for vectors.
4912 * fold-const.cc (fold_binary_loc): Likewise.
4914 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
4916 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
4917 (usdot_prod<mode>): Ditto.
4918 (sdot_prod<mode>): Ditto.
4919 (udot_prod<mode>): Ditto.
4921 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
4923 PR target/113288
4924 * config/i386/i386-c.cc (ix86_target_macros_internal):
4925 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
4927 2024-01-12 Richard Biener <rguenther@suse.de>
4929 PR target/112280
4930 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
4931 Do not generate code when d.testing_p.
4933 2024-01-12 liuhongt <hongtao.liu@intel.com>
4935 PR target/113039
4936 * doc/invoke.texi (fcf-protection=): Update documents.
4938 2024-01-12 Pan Li <pan2.li@intel.com>
4940 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
4941 comments of predicate func riscv_v_ext_mode_p.
4943 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
4945 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
4946 Modify ABI-name length of vfloat16m8_t
4948 2024-01-12 Li Wei <liwei@loongson.cn>
4950 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
4951 Adjust.
4953 2024-01-12 Li Wei <liwei@loongson.cn>
4955 * config/loongarch/loongarch.md (add<mode>3): Removed.
4956 (*addsi3): New.
4957 (addsi3): Ditto.
4958 (adddi3): Ditto.
4959 (*addsi3_extended): Removed.
4960 (addsi3_extended): New.
4962 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
4964 * config/riscv/thead.md: Add limits for splits.
4966 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
4968 PR middle-end/113322
4969 * expr.cc (do_store_flag): Don't try single bit tests with
4970 comparison on vector types.
4972 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
4974 PR tree-optimization/113301
4975 * match.pd (`1/x`): Delay signed case until late.
4977 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
4979 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
4980 and -msp8 to...
4981 (AVR Internal Options): ...this new @subsubsection.
4983 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
4985 PR rtl-optimization/112918
4986 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
4987 (in_class_p): Restrict condition for narrowing class in case of
4988 allow_all_reload_class_changes_p.
4989 (process_alt_operands): Try to match operand without and with
4990 narrowing reg class. Discourage narrowing the class. Finish insn
4991 matching only if there is no class narrowing.
4992 (curr_insn_transform): Pass true to in_class_p for reg operand win.
4994 2024-01-11 Richard Biener <rguenther@suse.de>
4996 PR tree-optimization/112505
4997 * tree-vect-loop.cc (vectorizable_induction): Reject
4998 bit-precision induction.
5000 2024-01-11 Richard Biener <rguenther@suse.de>
5002 PR tree-optimization/113126
5003 * match.pd ((double)float CMP (double)float -> float CMP float):
5004 Make sure the boolean type is the same.
5005 * fold-const.cc (fold_binary_loc): Likewise.
5007 2024-01-11 Richard Biener <rguenther@suse.de>
5009 PR tree-optimization/112636
5010 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
5011 estimate_numbers_of_iterations before querying
5012 get_max_loop_iterations_int.
5013 (pass_ch::execute): Initialize SCEV and loops appropriately.
5015 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
5017 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
5018 Reduced Tiny.
5019 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
5020 * doc/extend.texi (AVR Variable Attributes): Improve documentation
5021 of io, io_low and address attributes.
5022 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
5023 * doc/avr-mmcu.texi: Rebuild.
5025 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
5027 PR target/113233
5028 * config/loongarch/genopts/loongarch.opt.in: Mark options with
5029 the "Save" property.
5030 * config/loongarch/loongarch.opt: Same.
5031 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
5032 according to la_target.
5033 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
5034 RESTORE} for the la_target structure; Rename option conditions
5035 to have the same "la_" prefix.
5036 * config/loongarch/loongarch.h: Same.
5038 2024-01-11 Pan Li <pan2.li@intel.com>
5040 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
5041 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
5043 2024-01-11 Alex Coplan <alex.coplan@arm.com>
5045 PR target/113077
5046 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
5047 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
5048 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
5049 synthesize these if needed. Update caller ...
5050 (ldp_bb_info::fuse_pair): ... here.
5051 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
5052 and either insn is frame-related.
5053 (find_trailing_add): Punt on frame-related insns.
5054 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
5055 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
5057 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
5059 * config/mips/mips.cc (mips_start_function_definition):
5060 Add ATTRIBUTE_UNUSED.
5062 2024-01-11 Richard Biener <rguenther@suse.de>
5064 PR middle-end/112740
5065 * expr.cc (store_constructor): Check the integer vector
5066 mask has a single bit per element before using sign-extension
5067 to expand an uniform vector.
5069 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5071 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
5072 preempt VLS on unknown NITERS loop.
5074 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
5076 * doc/invoke.texi: Add -mevex512.
5078 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
5080 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
5081 (*nor<mode>3): Likewise.
5082 (nor<mode>3): Likewise.
5083 (*negsi2_extended): New template.
5084 (*<optab>si3_internal): Likewise.
5085 (*one_cmplsi2_internal): Likewise.
5086 (*norsi3_internal): Likewise.
5087 (*<optab>nsi_internal): Likewise.
5088 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
5089 modified bit operation to make the optimization work.
5091 2024-01-11 liuhongt <hongtao.liu@intel.com>
5093 PR target/104401
5094 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
5096 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5098 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
5099 (get_vector_costs): Ditto.
5100 (riscv_builtin_vectorization_cost): Ditto.
5102 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5104 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
5106 2024-01-10 Antoni Boucher <bouanto@zoho.com>
5108 PR jit/111396
5109 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
5110 ipa_free_size_summary.
5111 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
5112 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
5113 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
5114 * ipa-prop.h (ipa_prop_cc_finalize): New function.
5115 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
5116 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
5117 ipa_sra_cc_finalize): New functions.
5118 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
5119 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
5120 ipa_sra_cc_finalize
5121 Include ipa-utils.h.
5123 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
5125 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
5126 (th_int_get_save_adjustment): Likewise.
5127 (th_int_adjust_cfi_prologue): Likewise.
5128 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
5129 (TH_INT_INTERRUPT): New macro.
5130 (riscv_expand_prologue): Add the processing of XTheadInt.
5131 (riscv_expand_epilogue): Likewise.
5132 * config/riscv/riscv.h (BITSET_P): Moved to here.
5133 * config/riscv/riscv.md: New unspec.
5134 * config/riscv/thead.cc (th_int_get_mask): New function.
5135 (th_int_get_save_adjustment): Likewise.
5136 (th_int_adjust_cfi_prologue): Likewise.
5137 * config/riscv/thead.md (th_int_push): New pattern.
5138 (th_int_pop): new pattern.
5140 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5142 PR tree-optimization/112468
5143 * doc/sourcebuild.texi: Document ifn_copysign.
5144 * match.pd: Only apply transformation if target supports the IFN.
5146 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
5148 PR tree-optimization/112581
5149 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
5150 mark_ssa_maybe_undefs.
5151 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
5152 variables can not be reassociated.
5153 (init_range_entry): Check for uninitialized variables too.
5154 (init_reassoc): Call mark_ssa_maybe_undefs.
5156 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
5158 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
5159 Also handle sign extension.
5161 2024-01-10 Alex Coplan <alex.coplan@arm.com>
5163 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
5164 to 0.
5165 (-mlate-ldp-fusion): Likewise.
5167 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5169 PR tree-optimization/113287
5170 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
5171 instead of using BRANCH_EDGE to determine true edge.
5173 2024-01-10 Richard Biener <rguenther@suse.de>
5175 PR tree-optimization/113078
5176 * tree-vect-loop.cc (check_reduction_path): Canonicalize
5177 .COND_SUB to .COND_ADD.
5179 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5181 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
5182 Handle prefix mappings before calling find_opt.
5183 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
5184 "-fno-"-prefixed command-line option.
5185 * opts-common.cc (get_option_prefix_remapping): New.
5186 * opts.h (get_option_prefix_remapping): New decl.
5188 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5190 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
5191 m_urlifier to pp_output_formatted_text.
5192 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
5193 (obstack_append_string): New overload, taking a length.
5194 (urlify_quoted_string): Pass in an obstack ptr, rather than using
5195 that of the pp's buffer. Generalize to handle trailing text in
5196 the buffer beyond the run of quoted text.
5197 (class quoting_info): New.
5198 (on_begin_quote): New.
5199 (on_end_quote): New.
5200 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
5201 it to calls to on_begin_quote and on_end_quote.
5202 (struct auto_obstack): New.
5203 (quoting_info::handle_phase_3): New.
5204 (pp_output_formatted_text): Add urlifier param. Use it if there
5205 is deferred urlification. Delete m_quotes.
5206 (selftest::pp_printf_with_urlifier): Pass urlifier to
5207 pp_output_formatted_text.
5208 (selftest::test_urlification): Update results for the existing
5209 case of quoted text stradding chunks; add more such test cases.
5210 * pretty-print.h (class quoting_info): New forward decl.
5211 (chunk_info::m_quotes): New field.
5212 (pp_output_formatted_text): Add optional urlifier param.
5214 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5216 * pretty-print.cc (selftest::test_pp_format): Add selftest
5217 coverage for numbered args.
5219 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5221 PR tree-optimization/113144
5222 PR tree-optimization/113145
5223 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5224 Update all BB that the original exits dominated.
5226 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
5228 * dwarf2out.cc (modified_type_die): Extend the support of reverse
5229 storage order to enumeration types if -gstrict-dwarf is not passed.
5230 (gen_enumeration_type_die): Add REVERSE parameter and generate the
5231 DIE immediately after the existing one if it is true.
5232 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
5233 call to gen_enumeration_type_die.
5234 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
5235 first recursive call as well as the call to gen_tagged_type_die.
5236 (gen_type_die): Add REVERSE parameter and pass it in the call to
5237 gen_type_die_with_usage.
5239 2024-01-10 Jakub Jelinek <jakub@redhat.com>
5241 PR tree-optimization/113120
5242 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
5243 with root->size TYPE_PRECISION don't build anything new.
5244 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
5245 rather than build_nonstandard_integer_type.
5247 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
5249 * config/i386/i386.opt: Adjust document.
5250 * doc/invoke.texi: Add description for
5251 -mapx-inline-asm-use-gpr32.
5253 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5255 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
5256 (avg<v_double_trunc>3_floor): New pattern.
5257 (<u>avg<v_double_trunc>3_ceil): Remove.
5258 (avg<v_double_trunc>3_ceil): New pattern.
5259 (uavg<mode>3_floor): Ditto.
5260 (uavg<mode>3_ceil): Ditto.
5261 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
5262 (enum insn_type): Ditto.
5263 * config/riscv/riscv-v.cc: Ditto.
5264 * config/riscv/vector-iterators.md (ashiftrt): Remove.
5265 (ASHIFTRT): Ditto.
5266 * config/riscv/vector.md: Add VLS modes.
5268 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5270 PR target/111480
5271 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
5272 (vczlsbb_char): New int attribute.
5273 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
5274 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
5275 (*vctzlsbb_zext_<mode>): Rename to ...
5276 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
5277 cover vclzlsbb.
5279 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5281 PR target/112606
5282 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
5283 of the last argument from altivec_register_operand to any_operand. If
5284 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
5285 otherwise if it doesn't satisfy altivec_register_operand, force it to
5286 REG using copy_to_mode_reg.
5288 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5290 PR middle-end/113100
5291 * builtins.cc (expand_builtin_stack_address): Guard stack point
5292 adjustment with SPARC_STACK_BOUNDARY_HACK.
5294 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5296 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
5297 argument string definitions.
5298 * config/loongarch/loongarch-str.h: Same.
5299 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
5300 as aliases to -mexplicit-relocs={always,none}
5301 * config/loongarch/loongarch.opt: Regenerate.
5302 * config/loongarch/loongarch.cc: Same.
5304 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5306 * config/loongarch/loongarch-def.h: Define constants with
5307 enums instead of Macros.
5309 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5311 * config/loongarch/genopts/loongarch-strings: Rename.
5312 * config/loongarch/genopts/loongarch.opt.in: Same.
5313 * config/loongarch/loongarch-cpu.cc: Same.
5314 * config/loongarch/loongarch-def.cc: Same.
5315 * config/loongarch/loongarch-def.h: Same.
5316 * config/loongarch/loongarch-opts.cc: Same.
5317 * config/loongarch/loongarch-opts.h: Same.
5318 * config/loongarch/loongarch-str.h: Same.
5319 * config/loongarch/loongarch.opt: Same.
5321 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5323 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
5324 variable with the common la_ prefix.
5325 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
5326 flags as saved using TargetVariable.
5327 * config/loongarch/loongarch.opt: Same.
5328 * config/loongarch/loongarch-def.h: Define evolution_set to
5329 mark changes to the -march default.
5330 * config/loongarch/loongarch-driver.cc: Same.
5331 * config/loongarch/loongarch-opts.cc: Same.
5332 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
5333 conditions around the la_target structure.
5334 * config/loongarch/loongarch.cc: Same.
5335 * config/loongarch/loongarch.md: Same.
5336 * config/loongarch/loongarch-builtins.cc: Same.
5337 * config/loongarch/loongarch-c.cc: Same.
5338 * config/loongarch/lasx.md: Same.
5339 * config/loongarch/lsx.md: Same.
5340 * config/loongarch/sync.md: Same.
5342 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
5344 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
5345 no less.
5347 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
5349 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
5351 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5353 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
5354 restart_loop.
5355 (vectorizable_live_operation): Likewise.
5357 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5359 PR tree-optimization/113199
5360 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
5361 BIT_FIELD_REF.
5363 2024-01-09 Jakub Jelinek <jakub@redhat.com>
5365 PR target/113270
5366 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
5367 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
5368 GTY(()) declaration before the definition, drop GTY(()) drom the
5369 definition.
5371 2024-01-09 Richard Biener <rguenther@suse.de>
5373 PR tree-optimization/113026
5374 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
5375 redundant and wrong niter bound setting. Move niter
5376 bound adjustment down.
5378 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5380 PR middle-end/113163
5381 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
5382 Reject non-linear inductions that aren't supported.
5384 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
5386 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
5387 left shift implementation strategies.
5388 (arc_shift_info): Type for each entry of the shift strategy table.
5389 (arc_shift_context_idx): Return a integer value for each code
5390 generation context, used as an index
5391 (arc_ashl_alg): Table indexed by context and shifted bit count.
5392 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
5393 left shift implementation.
5394 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
5395 provide accurate costs, when optimizing for speed or size.
5397 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5399 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
5401 2024-01-09 Julian Brown <julian@codesourcery.com>
5403 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
5404 processed out before gimplification.
5405 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
5406 * tree.def (OMP_ARRAY_SECTION): New tree code.
5408 2024-01-09 Jakub Jelinek <jakub@redhat.com>
5410 PR tree-optimization/113210
5411 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
5412 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
5413 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
5414 minus 1.
5416 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
5418 PR rtl-optimization/113140
5419 * reorg.cc (fill_slots_from_thread): If we are to branch after the
5420 last instruction of the function, create an end label.
5422 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
5423 Hongtao Liu <hongtao.liu@intel.com>
5425 PR target/112992
5426 * config/i386/i386-expand.cc
5427 (ix86_convert_const_wide_int_to_broadcast): Allow call to
5428 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
5429 (ix86_broadcast_from_constant): Revert recent change; Return a
5430 suitable MEMREF independently of mode/target combinations.
5431 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
5432 to decide whether expansion is possible/preferrable. Only try
5433 forcing DImode constants to memory (and trying again) if calling
5434 ix86_expand_vector_init_duplicate fails with an DImode immediate
5435 constant.
5436 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
5437 V4SImode for suitable immediate constants.
5438 <case E_V4DImode>: Try using V8SImode for suitable constants.
5439 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
5440 <case E_V2HImode>: Likewise.
5441 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
5442 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
5443 <label widen>: Handle CONT_INTs via simplify_binary_operation.
5444 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
5445 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
5446 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
5447 (ix86_expand_vector_init): Move try using a broadcast for all_same
5448 with ix86_expand_vector_init_duplicate before using constant pool.
5450 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
5452 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
5454 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
5456 * config/arm/arm-cpus.in (cortex-m52): New cpu.
5457 * config/arm/arm-tables.opt: Regenerate.
5458 * config/arm/arm-tune.md: Regenerate.
5460 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
5462 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
5463 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
5464 (@vec_concatz<mode>): New insn pattern.
5465 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
5466 Handle VALS containing two vectors.
5468 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5470 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
5471 (vundefined): Ditto.
5473 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
5475 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5476 Add new function_base for crypto vector.
5477 (class bitmanip): Ditto.
5478 (class b_reverse):Ditto.
5479 (class vwsll): Ditto.
5480 (class clmul): Ditto.
5481 (class vg_nhab): Ditto.
5482 (class crypto_vv):Ditto.
5483 (class crypto_vi):Ditto.
5484 (class vaeskf2_vsm3c):Ditto.
5485 (class vsm3me): Ditto.
5486 (BASE): Add BASE declaration for crypto vector.
5487 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5488 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5489 Add crypto vector intrinsic definition.
5490 (vbrev): Ditto.
5491 (vclz): Ditto.
5492 (vctz): Ditto.
5493 (vwsll): Ditto.
5494 (vandn): Ditto.
5495 (vbrev8): Ditto.
5496 (vrev8): Ditto.
5497 (vrol): Ditto.
5498 (vror): Ditto.
5499 (vclmul): Ditto.
5500 (vclmulh): Ditto.
5501 (vghsh): Ditto.
5502 (vgmul): Ditto.
5503 (vaesef): Ditto.
5504 (vaesem): Ditto.
5505 (vaesdf): Ditto.
5506 (vaesdm): Ditto.
5507 (vaesz): Ditto.
5508 (vaeskf1): Ditto.
5509 (vaeskf2): Ditto.
5510 (vsha2ms): Ditto.
5511 (vsha2ch): Ditto.
5512 (vsha2cl): Ditto.
5513 (vsm4k): Ditto.
5514 (vsm4r): Ditto.
5515 (vsm3me): Ditto.
5516 (vsm3c): Ditto.
5517 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5518 Add new function_shape for crypto vector.
5519 (struct crypto_vi_def): Ditto.
5520 (struct crypto_vv_no_op_type_def): Ditto.
5521 (SHAPE): Add SHAPE declaration of crypto vector.
5522 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5523 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5524 Add new data type for crypto vector.
5525 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5526 (vuint32mf2_t): Ditto.
5527 (vuint32m1_t): Ditto.
5528 (vuint32m2_t): Ditto.
5529 (vuint32m4_t): Ditto.
5530 (vuint32m8_t): Ditto.
5531 (vuint64m1_t): Ditto.
5532 (vuint64m2_t): Ditto.
5533 (vuint64m4_t): Ditto.
5534 (vuint64m8_t): Ditto.
5535 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5536 Add new data struct for crypto vector.
5537 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5538 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5539 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5541 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
5543 PR sanitizer/113251
5544 * varasm.cc (assemble_function_label_raw): Do not call
5545 asan_function_start () without the current function.
5547 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
5549 PR target/113225
5550 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
5551 extern and kernel_helper attributed function decls.
5553 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
5555 * btfout.cc (output_btf_strs): Changed.
5557 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
5559 * config/gcn/mkoffload.cc (main): Handle gfx1100
5560 when setting the default XNACK.
5562 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
5564 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
5565 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
5566 (ASM_SPEC): Handle gfx1100.
5567 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
5568 (enum gcn_isa): Add ISA_RDNA3.
5569 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
5570 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5571 * config/gcn/gcn.cc (gcn_option_override,
5572 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
5573 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
5574 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5575 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
5576 with gfx1100.
5577 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
5578 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
5579 __gfx1100__.
5580 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5581 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
5582 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
5583 (isa_has_combined_avgprs, main): Handle gfx1100.
5584 * config/gcn/t-omp-device (isa): Add gfx1100.
5586 2024-01-08 Richard Biener <rguenther@suse.de>
5588 * doc/invoke.texi (-mmovbe): Clarify.
5590 2024-01-08 Richard Biener <rguenther@suse.de>
5592 PR tree-optimization/113026
5593 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
5594 Avoid an epilog in more cases.
5595 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
5596 epilogues niter upper bounds and estimates.
5598 2024-01-08 Jakub Jelinek <jakub@redhat.com>
5600 PR tree-optimization/113228
5601 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
5603 2024-01-08 Jakub Jelinek <jakub@redhat.com>
5605 PR tree-optimization/113120
5606 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
5607 large _BitInt zero INTEGER_CST PHI argument.
5609 2024-01-08 Jakub Jelinek <jakub@redhat.com>
5611 PR tree-optimization/113119
5612 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
5613 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
5614 is before REALPART_EXPR.
5616 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
5618 PR target/112952
5619 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
5620 range when diagnosing attribute "io" and "io_low" are out of range.
5621 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
5622 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
5623 in contexts other than static storage.
5624 (avr_asm_output_aligned_decl_common): Move output of decls with
5625 attribute "address", "io", and "io_low" to...
5626 (avr_output_addr_attrib): ...this new function.
5627 (avr_asm_asm_output_aligned_bss): Remove output for decls with
5628 attribute "address", "io", and "io_low".
5629 (avr_encode_section_info): Rectify handling of decls with attribute
5630 "address", "io", and "io_low".
5632 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
5634 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
5635 (elf_flags): Remove XNACK from the default value.
5636 (main): Set a default XNACK according to the arch.
5638 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
5640 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
5641 (process_asm): Don't count avgprs.
5643 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
5645 * config/i386/i386.opt: Add supported sub-features.
5646 * doc/extend.texi: Add description for target attribute.
5648 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
5650 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
5652 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
5653 Uros Bizjak <ubizjak@gmail.com>
5655 PR target/113231
5656 * config/i386/i386-features.cc (compute_convert_gain): Include
5657 the overhead of explicit load and store (movd) instructions when
5658 converting non-store scalar operations with memory destinations.
5659 Various indentation whitespace fixes.
5661 2024-01-07 Tamar Christina <tamar.christina@arm.com>
5663 * config/arm/neon.md (cbranch<mode>4): New.
5665 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5667 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
5669 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
5671 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
5673 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5675 PR target/113248
5676 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
5677 Update the MAX_SEW.
5679 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5681 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
5682 (variable_vectorized_p): Teach loop invariant.
5683 (has_unexpected_spills_p): Ditto.
5685 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5687 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
5688 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
5689 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
5691 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
5693 PR target/113104
5694 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
5695 (aarch64-vect-compare-costs): ...this.
5696 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
5697 Replace with...
5698 (-param=aarch64-vect-compare-costs=): ...this new param.
5699 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
5700 Don't disable it when vectorizing for Advanced SIMD only.
5701 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
5702 whenever aarch64_vect_compare_costs is true.
5704 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
5706 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
5707 Modify the method of determining the memory offset of [x]vld/[x]vst.
5708 (lasx_mxst_<lasxfmt_f>): Likewise.
5709 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
5710 (loongarch_address_insns): Likewise.
5711 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
5712 (lsx_st_<lsxfmt_f>): Likewise.
5713 * config/loongarch/predicates.md (aq10b_operand): Likewise.
5714 (aq10h_operand): Likewise.
5715 (aq10w_operand): Likewise.
5716 (aq10d_operand): Likewise.
5718 2024-01-05 Alex Coplan <alex.coplan@arm.com>
5720 PR target/113217
5721 * config/aarch64/aarch64-ldp-fusion.cc
5722 (ldp_bb_info::try_fuse_pair): If the second access can throw,
5723 narrow the move range to exactly that insn.
5725 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
5727 * asan.cc (asan_function_start): Drop switch_to_section ().
5728 (asan_emit_stack_protection): Set .LASANPC alignment.
5729 * config/i386/i386.cc: Use assemble_function_label_raw ()
5730 instead of ASM_OUTPUT_LABEL ().
5731 * config/s390/s390.cc (s390_asm_output_function_label):
5732 Likewise.
5733 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
5734 * final.cc (final_start_function_1): Drop
5735 asan_function_start ().
5736 * output.h (assemble_function_label_raw): New function.
5737 * varasm.cc (assemble_function_label_raw): Likewise.
5739 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
5741 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
5742 Use ASM_OUTPUT_FUNCTION_LABEL ().
5743 * config/alpha/alpha.cc (alpha_start_function): Likewise.
5744 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5745 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
5746 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5747 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5748 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
5749 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5750 * config/ia64/ia64.cc (ia64_start_function): Likewise.
5751 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
5752 Likewise.
5753 * config/microblaze/microblaze.cc (microblaze_function_prologue):
5754 Likewise.
5755 * config/mips/mips.cc (mips_start_unique_function): Return the
5756 tree.
5757 (mips_start_function_definition): Use
5758 ASM_OUTPUT_FUNCTION_LABEL ().
5759 (mips_finish_stub): Pass the tree to
5760 mips_start_function_definition ().
5761 (mips16_build_function_stub): Likewise.
5762 (mips16_build_call_stub): Likewise.
5763 (mips_output_function_prologue): Likewise.
5764 * config/pa/pa.cc (pa_output_function_label): Use
5765 ASM_OUTPUT_FUNCTION_LABEL ().
5766 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
5767 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5768 Likewise.
5769 (rs6000_xcoff_declare_function_name): Likewise.
5771 2024-01-05 Jakub Jelinek <jakub@redhat.com>
5773 PR tree-optimization/113201
5774 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
5775 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
5777 2024-01-05 Jakub Jelinek <jakub@redhat.com>
5779 PR tree-optimization/90693
5780 * tree-ssa-math-opts.cc (match_single_bit_test): If
5781 tree_expr_nonzero_p (arg), remember it in the second argument to
5782 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
5783 arg ^ (arg - 1) > arg - 1.
5784 * internal-fn.cc (expand_POPCOUNT): If second argument to
5785 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
5786 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
5788 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
5790 * config/riscv/riscv-v.cc (expand_load_store):
5791 Remove `value`.
5792 (expand_cond_len_op): Ditto.
5793 (expand_gather_scatter): Ditto.
5794 (expand_lanes_load_store): Ditto.
5795 (expand_fold_extract_last): Ditto.
5797 2024-01-05 Pan Li <pan2.li@intel.com>
5799 Revert:
5800 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
5802 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5803 Add new function_base for crypto vector.
5804 (class bitmanip): Ditto.
5805 (class b_reverse):Ditto.
5806 (class vwsll): Ditto.
5807 (class clmul): Ditto.
5808 (class vg_nhab): Ditto.
5809 (class crypto_vv):Ditto.
5810 (class crypto_vi):Ditto.
5811 (class vaeskf2_vsm3c):Ditto.
5812 (class vsm3me): Ditto.
5813 (BASE): Add BASE declaration for crypto vector.
5814 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5815 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5816 Add crypto vector intrinsic definition.
5817 (vbrev): Ditto.
5818 (vclz): Ditto.
5819 (vctz): Ditto.
5820 (vwsll): Ditto.
5821 (vandn): Ditto.
5822 (vbrev8): Ditto.
5823 (vrev8): Ditto.
5824 (vrol): Ditto.
5825 (vror): Ditto.
5826 (vclmul): Ditto.
5827 (vclmulh): Ditto.
5828 (vghsh): Ditto.
5829 (vgmul): Ditto.
5830 (vaesef): Ditto.
5831 (vaesem): Ditto.
5832 (vaesdf): Ditto.
5833 (vaesdm): Ditto.
5834 (vaesz): Ditto.
5835 (vaeskf1): Ditto.
5836 (vaeskf2): Ditto.
5837 (vsha2ms): Ditto.
5838 (vsha2ch): Ditto.
5839 (vsha2cl): Ditto.
5840 (vsm4k): Ditto.
5841 (vsm4r): Ditto.
5842 (vsm3me): Ditto.
5843 (vsm3c): Ditto.
5844 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5845 Add new function_shape for crypto vector.
5846 (struct crypto_vi_def): Ditto.
5847 (struct crypto_vv_no_op_type_def): Ditto.
5848 (SHAPE): Add SHAPE declaration of crypto vector.
5849 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5850 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5851 Add new data type for crypto vector.
5852 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5853 (vuint32mf2_t): Ditto.
5854 (vuint32m1_t): Ditto.
5855 (vuint32m2_t): Ditto.
5856 (vuint32m4_t): Ditto.
5857 (vuint32m8_t): Ditto.
5858 (vuint64m1_t): Ditto.
5859 (vuint64m2_t): Ditto.
5860 (vuint64m4_t): Ditto.
5861 (vuint64m8_t): Ditto.
5862 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5863 Add new data struct for crypto vector.
5864 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5865 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5866 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5868 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
5870 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5871 Add new function_base for crypto vector.
5872 (class bitmanip): Ditto.
5873 (class b_reverse):Ditto.
5874 (class vwsll): Ditto.
5875 (class clmul): Ditto.
5876 (class vg_nhab): Ditto.
5877 (class crypto_vv):Ditto.
5878 (class crypto_vi):Ditto.
5879 (class vaeskf2_vsm3c):Ditto.
5880 (class vsm3me): Ditto.
5881 (BASE): Add BASE declaration for crypto vector.
5882 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5883 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5884 Add crypto vector intrinsic definition.
5885 (vbrev): Ditto.
5886 (vclz): Ditto.
5887 (vctz): Ditto.
5888 (vwsll): Ditto.
5889 (vandn): Ditto.
5890 (vbrev8): Ditto.
5891 (vrev8): Ditto.
5892 (vrol): Ditto.
5893 (vror): Ditto.
5894 (vclmul): Ditto.
5895 (vclmulh): Ditto.
5896 (vghsh): Ditto.
5897 (vgmul): Ditto.
5898 (vaesef): Ditto.
5899 (vaesem): Ditto.
5900 (vaesdf): Ditto.
5901 (vaesdm): Ditto.
5902 (vaesz): Ditto.
5903 (vaeskf1): Ditto.
5904 (vaeskf2): Ditto.
5905 (vsha2ms): Ditto.
5906 (vsha2ch): Ditto.
5907 (vsha2cl): Ditto.
5908 (vsm4k): Ditto.
5909 (vsm4r): Ditto.
5910 (vsm3me): Ditto.
5911 (vsm3c): Ditto.
5912 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5913 Add new function_shape for crypto vector.
5914 (struct crypto_vi_def): Ditto.
5915 (struct crypto_vv_no_op_type_def): Ditto.
5916 (SHAPE): Add SHAPE declaration of crypto vector.
5917 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5918 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5919 Add new data type for crypto vector.
5920 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5921 (vuint32mf2_t): Ditto.
5922 (vuint32m1_t): Ditto.
5923 (vuint32m2_t): Ditto.
5924 (vuint32m4_t): Ditto.
5925 (vuint32m8_t): Ditto.
5926 (vuint64m1_t): Ditto.
5927 (vuint64m2_t): Ditto.
5928 (vuint64m4_t): Ditto.
5929 (vuint64m8_t): Ditto.
5930 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5931 Add new data struct for crypto vector.
5932 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5933 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5934 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5936 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5938 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5940 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
5942 PR tree-optimization/113186
5943 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
5944 Match `^` with the `==` for 1bit integral types.
5945 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
5946 integral types.
5948 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5950 * toplev.cc (general_init): Pass lang_mask to urlifier.
5952 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5954 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
5955 param.
5956 (diagnostic_context::make_option_url): Update for lang_mask param.
5957 * gcc-urlifier.cc: Include "opts.h" and "options.h".
5958 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
5959 (gcc_urlifier::m_lang_mask): New field.
5960 (doc_urls): Make static.
5961 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
5962 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
5963 Look for an option by name before trying a binary search in
5964 doc_urls.
5965 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
5966 (gcc_urlifier::get_url_suffix_for_option): New.
5967 (make_gcc_urlifier): Add lang_mask param.
5968 (selftest::gcc_urlifier_cc_tests): Update for above changes.
5969 Verify that a URL is found for "-fpack-struct".
5970 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
5971 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
5972 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
5973 to make_gcc_urlifier.
5974 * opts-diagnostic.h (get_option_url): Add lang_mask param.
5975 * opts.cc (get_option_html_page): Remove special-casing for
5976 analyzer and LTO.
5977 (get_option_url_suffix): New.
5978 (get_option_url): Reimplement.
5979 (selftest::test_get_option_html_page): Rename to...
5980 (selftest::test_get_option_url_suffix): ...this and update for
5981 above changes.
5982 (selftest::opts_cc_tests): Update for renaming.
5983 * opts.h: Include "rich-location.h".
5984 (get_option_url_suffix): New decl.
5986 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5988 * Makefile.in (ALL_OPT_URL_FILES): New.
5989 (GCC_OBJS): Add options-urls.o.
5990 (OBJS): Likewise.
5991 (OBJS-libcommon): Likewise.
5992 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
5993 inputs to opt-gather.awk.
5994 (options-urls.cc): New Makefile target.
5995 * opt-functions.awk (url_suffix): New function.
5996 (lang_url_suffix): New function.
5997 * options-urls-cc-gen.awk: New file.
5998 * opts.h (get_opt_url_suffix): New decl.
6000 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6002 * params.opt.urls: New file, autogenerated by
6003 regenerate-opt-urls.py.
6005 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6007 * common.opt.urls: New file, autogenerated by
6008 regenerate-opt-urls.py.
6009 * config/aarch64/aarch64.opt.urls: Likewise.
6010 * config/alpha/alpha.opt.urls: Likewise.
6011 * config/alpha/elf.opt.urls: Likewise.
6012 * config/arc/arc-tables.opt.urls: Likewise.
6013 * config/arc/arc.opt.urls: Likewise.
6014 * config/arm/arm-tables.opt.urls: Likewise.
6015 * config/arm/arm.opt.urls: Likewise.
6016 * config/arm/vxworks.opt.urls: Likewise.
6017 * config/avr/avr.opt.urls: Likewise.
6018 * config/bpf/bpf.opt.urls: Likewise.
6019 * config/c6x/c6x-tables.opt.urls: Likewise.
6020 * config/c6x/c6x.opt.urls: Likewise.
6021 * config/cris/cris.opt.urls: Likewise.
6022 * config/cris/elf.opt.urls: Likewise.
6023 * config/csky/csky.opt.urls: Likewise.
6024 * config/csky/csky_tables.opt.urls: Likewise.
6025 * config/darwin.opt.urls: Likewise.
6026 * config/dragonfly.opt.urls: Likewise.
6027 * config/epiphany/epiphany.opt.urls: Likewise.
6028 * config/fr30/fr30.opt.urls: Likewise.
6029 * config/freebsd.opt.urls: Likewise.
6030 * config/frv/frv.opt.urls: Likewise.
6031 * config/ft32/ft32.opt.urls: Likewise.
6032 * config/fused-madd.opt.urls: Likewise.
6033 * config/g.opt.urls: Likewise.
6034 * config/gcn/gcn.opt.urls: Likewise.
6035 * config/gnu-user.opt.urls: Likewise.
6036 * config/h8300/h8300.opt.urls: Likewise.
6037 * config/hpux11.opt.urls: Likewise.
6038 * config/i386/cygming.opt.urls: Likewise.
6039 * config/i386/cygwin.opt.urls: Likewise.
6040 * config/i386/djgpp.opt.urls: Likewise.
6041 * config/i386/i386.opt.urls: Likewise.
6042 * config/i386/mingw-w64.opt.urls: Likewise.
6043 * config/i386/mingw.opt.urls: Likewise.
6044 * config/i386/nto.opt.urls: Likewise.
6045 * config/ia64/ia64.opt.urls: Likewise.
6046 * config/ia64/ilp32.opt.urls: Likewise.
6047 * config/ia64/vms.opt.urls: Likewise.
6048 * config/iq2000/iq2000.opt.urls: Likewise.
6049 * config/linux-android.opt.urls: Likewise.
6050 * config/linux.opt.urls: Likewise.
6051 * config/lm32/lm32.opt.urls: Likewise.
6052 * config/loongarch/loongarch.opt.urls: Likewise.
6053 * config/lynx.opt.urls: Likewise.
6054 * config/m32c/m32c.opt.urls: Likewise.
6055 * config/m32r/m32r.opt.urls: Likewise.
6056 * config/m68k/ieee.opt.urls: Likewise.
6057 * config/m68k/m68k-tables.opt.urls: Likewise.
6058 * config/m68k/m68k.opt.urls: Likewise.
6059 * config/m68k/uclinux.opt.urls: Likewise.
6060 * config/mcore/mcore.opt.urls: Likewise.
6061 * config/microblaze/microblaze.opt.urls: Likewise.
6062 * config/mips/mips-tables.opt.urls: Likewise.
6063 * config/mips/mips.opt.urls: Likewise.
6064 * config/mips/sde.opt.urls: Likewise.
6065 * config/mmix/mmix.opt.urls: Likewise.
6066 * config/mn10300/mn10300.opt.urls: Likewise.
6067 * config/moxie/moxie.opt.urls: Likewise.
6068 * config/msp430/msp430.opt.urls: Likewise.
6069 * config/nds32/nds32-elf.opt.urls: Likewise.
6070 * config/nds32/nds32-linux.opt.urls: Likewise.
6071 * config/nds32/nds32.opt.urls: Likewise.
6072 * config/netbsd-elf.opt.urls: Likewise.
6073 * config/netbsd.opt.urls: Likewise.
6074 * config/nios2/elf.opt.urls: Likewise.
6075 * config/nios2/nios2.opt.urls: Likewise.
6076 * config/nvptx/nvptx-gen.opt.urls: Likewise.
6077 * config/nvptx/nvptx.opt.urls: Likewise.
6078 * config/openbsd.opt.urls: Likewise.
6079 * config/or1k/elf.opt.urls: Likewise.
6080 * config/or1k/or1k.opt.urls: Likewise.
6081 * config/pa/pa-hpux.opt.urls: Likewise.
6082 * config/pa/pa-hpux1010.opt.urls: Likewise.
6083 * config/pa/pa-hpux1111.opt.urls: Likewise.
6084 * config/pa/pa-hpux1131.opt.urls: Likewise.
6085 * config/pa/pa.opt.urls: Likewise.
6086 * config/pa/pa64-hpux.opt.urls: Likewise.
6087 * config/pdp11/pdp11.opt.urls: Likewise.
6088 * config/pru/pru.opt.urls: Likewise.
6089 * config/riscv/riscv.opt.urls: Likewise.
6090 * config/rl78/rl78.opt.urls: Likewise.
6091 * config/rpath.opt.urls: Likewise.
6092 * config/rs6000/476.opt.urls: Likewise.
6093 * config/rs6000/aix64.opt.urls: Likewise.
6094 * config/rs6000/darwin.opt.urls: Likewise.
6095 * config/rs6000/linux64.opt.urls: Likewise.
6096 * config/rs6000/rs6000-tables.opt.urls: Likewise.
6097 * config/rs6000/rs6000.opt.urls: Likewise.
6098 * config/rs6000/sysv4.opt.urls: Likewise.
6099 * config/rtems.opt.urls: Likewise.
6100 * config/rx/elf.opt.urls: Likewise.
6101 * config/rx/rx.opt.urls: Likewise.
6102 * config/s390/s390.opt.urls: Likewise.
6103 * config/s390/tpf.opt.urls: Likewise.
6104 * config/sh/sh.opt.urls: Likewise.
6105 * config/sh/superh.opt.urls: Likewise.
6106 * config/sol2.opt.urls: Likewise.
6107 * config/sparc/long-double-switch.opt.urls: Likewise.
6108 * config/sparc/sparc.opt.urls: Likewise.
6109 * config/stormy16/stormy16.opt.urls: Likewise.
6110 * config/v850/v850.opt.urls: Likewise.
6111 * config/vax/elf.opt.urls: Likewise.
6112 * config/vax/vax.opt.urls: Likewise.
6113 * config/visium/visium.opt.urls: Likewise.
6114 * config/vms/vms.opt.urls: Likewise.
6115 * config/vxworks-smp.opt.urls: Likewise.
6116 * config/vxworks.opt.urls: Likewise.
6117 * config/xtensa/elf.opt.urls: Likewise.
6118 * config/xtensa/uclinux.opt.urls: Likewise.
6119 * config/xtensa/xtensa.opt.urls: Likewise.
6120 * config/bfin/bfin.opt.urls: New file.
6122 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6124 * Makefile.in (OPT_URLS_HTML_DEPS): New.
6125 (regenerate-opt-urls): New target.
6126 (regenerate-opt-urls-unit-test): New target.
6127 * doc/options.texi (Option properties): Add UrlSuffix and
6128 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
6129 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
6130 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
6131 and Makefile.in's OPT_URLS_HTML_DEPS.
6132 (Anatomy of a Target Back End): Add
6133 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
6134 * regenerate-opt-urls.py: New file.
6136 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6138 * diagnostic-format-sarif.cc
6139 (sarif_builder::make_logical_location_object): Convert to...
6140 (make_sarif_logical_location_object): ...this.
6141 (sarif_builder::set_any_logical_locs_arr): Update for above
6142 change.
6143 (sarif_builder::make_thread_flow_location_object): Call
6144 maybe_add_sarif_properties on each diagnostic_event.
6145 * diagnostic-format-sarif.h (class logical_location): New forward
6146 decl.
6147 (make_sarif_logical_location_object): New decl.
6148 * diagnostic-path.h (class sarif_object): New forward decl.
6149 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
6151 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
6152 Patrick Lin <patrick@andestech.com>
6153 Rufus Chen <rufus@andestech.com>
6154 Monk Chiang <monk.chiang@sifive.com>
6156 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
6157 with Nan-boxing value.
6158 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
6160 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
6161 Jeff Law <jlaw@ventanamicro.com>
6163 PR rtl-optimization/104914
6164 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
6165 a sign or zero extension is only required if the modified field
6166 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
6167 targets, don't refer to the temporarily incorrectly extended value
6168 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
6170 2024-01-04 Pan Li <pan2.li@intel.com>
6172 Revert:
6173 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6175 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6177 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6179 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6181 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
6183 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
6184 offset of fcsr.
6186 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6188 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
6189 (compute_nregs_for_mode): Refine LMUL.
6190 (max_number_of_live_regs): Ditto.
6191 (compute_estimated_lmul): Ditto.
6192 (has_unexpected_spills_p): Ditto.
6194 2024-01-04 Li Wei <liwei@loongson.cn>
6196 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
6197 Remove useless forward declaration.
6198 (loongarch_is_even_extraction): Remove useless forward declaration.
6199 (loongarch_try_expand_lsx_vshuf_const): Removed.
6200 (loongarch_expand_vec_perm_const_1): Merged.
6201 (loongarch_is_double_duplicate): Removed.
6202 (loongarch_is_center_extraction): Ditto.
6203 (loongarch_is_reversing_permutation): Ditto.
6204 (loongarch_is_di_misalign_extract): Ditto.
6205 (loongarch_is_si_misalign_extract): Ditto.
6206 (loongarch_is_lasx_lowpart_extract): Ditto.
6207 (loongarch_is_op_reverse_perm): Ditto.
6208 (loongarch_is_single_op_perm): Ditto.
6209 (loongarch_is_divisible_perm): Ditto.
6210 (loongarch_is_triple_stride_extract): Ditto.
6211 (loongarch_expand_vec_perm_const_2): Merged.
6212 (loongarch_expand_vec_perm_const): New.
6213 (loongarch_vectorize_vec_perm_const): Adjust.
6215 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
6217 * omp-general.cc: Fix comment typos and misplaced/confusing
6218 comments. Delete redundant include of omp-general.h.
6220 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6222 PR rtl-optimization/104914
6223 * config/mips/mips.md (insqisi_extended): New patterns.
6224 (inshisi_extended): Ditto.
6226 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6228 * config/mips/mips.cc (mips_insn_cost): New function.
6230 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6232 * config/mips/mips.md (perf_ratio): New attribute.
6234 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6236 PR target/113206
6237 PR target/113209
6238 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
6239 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
6240 blocks belong to infinite loop.
6241 (pre_vsetvl::emit_vsetvl): Remove fake edges.
6242 * config/riscv/t-riscv: Add a new include file.
6244 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6246 * config/riscv/vector.md: Fix indent.
6248 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
6250 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
6251 OMP_CLAUSE__SIMDUID_.
6252 * tree.cc (omp_clause_num_ops): Update position of entry for
6253 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
6254 (omp_clause_code_name): Likewise.
6256 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
6258 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
6259 printing of FUNC_MAP/IND_FUNC_MAP labels.
6261 2024-01-03 Jakub Jelinek <jakub@redhat.com>
6263 * gcc.cc (process_command): Update copyright notice dates.
6264 * gcov-dump.cc (print_version): Ditto.
6265 * gcov.cc (print_version): Ditto.
6266 * gcov-tool.cc (print_version): Ditto.
6267 * gengtype.cc (create_file): Ditto.
6268 * doc/cpp.texi: Bump @copying's copyright year.
6269 * doc/cppinternals.texi: Ditto.
6270 * doc/gcc.texi: Ditto.
6271 * doc/gccint.texi: Ditto.
6272 * doc/gcov.texi: Ditto.
6273 * doc/install.texi: Ditto.
6274 * doc/invoke.texi: Ditto.
6276 2024-01-03 Xi Ruoyao <xry111@xry111.site>
6278 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
6279 (fmin<mode>3): Likewise.
6280 (reduc_fmax_scal_<mode>3): New define_expand.
6281 (reduc_fmin_scal_<mode>3): Likewise.
6283 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6285 PR target/113112
6286 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
6287 (max_number_of_live_regs): Ditto.
6288 (has_unexpected_spills_p): Ditto.
6290 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
6291 Jin Ma <jinma@linux.alibaba.com>
6292 Xianmiao Qu <cooper.qu@linux.alibaba.com>
6293 Christoph Müllner <christoph.muellner@vrull.eu>
6295 * config/riscv/vector.md:
6296 Use vector_length_operand for vsetvl patterns.
6298 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6300 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
6301 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
6303 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
6305 * config/aarch64/aarch64-tuning-flags.def
6306 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
6307 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
6308 * config/aarch64/aarch64.cc
6309 (aarch64_override_options_internal): Set
6310 param_fully_pipelined_fma according to tuning option.
6311 * config/aarch64/tuning_models/ampere1.h: Add
6312 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
6313 * config/aarch64/tuning_models/ampere1a.h: Likewise.
6314 * config/aarch64/tuning_models/ampere1b.h: Likewise.
6316 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
6318 * config/riscv/vector-crypto.md: Modify copyright year.
6320 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6322 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
6324 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
6326 * config.in: Regenerate.
6327 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
6328 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
6329 Added TLS Le Relax support.
6330 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
6331 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
6332 * configure: Regenerate.
6333 * configure.ac: Check if binutils supports TLS le relax.
6335 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
6337 * config/riscv/iterators.md: Add rotate insn name.
6338 * config/riscv/riscv.md: Add new insns name for crypto vector.
6339 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
6340 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
6341 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
6343 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6345 PR target/113112
6346 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
6347 pointer type liveness count.
6348 \f
6349 Copyright (C) 2024 Free Software Foundation, Inc.
6351 Copying and distribution of this file, with or without modification,
6352 are permitted in any medium without royalty provided the copyright
6353 notice and this notice are preserved.