| blob | 547919c8042662e36cc93cd003d0f313d90751a7 |
1 /* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
2 Copyright (C) 1991 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22 /* Sometimes the directive `riscos' is check. This does not imply that this
23 tm file can be used unchanged to build a GCC for RISC OS.
24 (Since in fact, it can't.) */
38 \f
39 /* Translation to find startup files. On RISCiX boxes, gcrt0.o is in
40 /usr/lib. */
41 #define STARTFILE_SPEC \
42 "%{pg:/usr/lib/gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
44 #ifdef riscos
46 #else
48 #endif
49 \f
50 /* Run-time Target Specification. */
51 #define TARGET_VERSION \
54 /* Run-time compilation parameters selecting different hardware subsets.
55 On the ARM, misuse it in a different way. */
58 /* Nonzero if the function prologue (and epilogue) should obey
59 the ARM Procedure Call Standard. */
60 #define TARGET_APCS (target_flags & 1)
62 /* Nonzero if the function prologue should output the function name to enable
63 the post mortem debugger to print a backtrace (very useful on RISCOS,
64 unused on RISCiX). Specifying this flag also enables -mapcs.
65 XXX Must still be implemented in the prologue. */
66 #define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
68 /* Nonzero if floating point instructions are emulated by the FPE, in which
69 case instruction scheduling becomes very uninteresting. */
70 #define TARGET_FPE (target_flags & 4)
72 #define TARGET_SWITCHES \
73 { \
78 }
80 #define TARGET_DEFAULT 0
82 #define TARGET_MEM_FUNCTIONS 1
84 /* OVERRIDE_OPTIONS takes care of the following:
85 - if -mpoke-function-name, then -mapcs.
86 - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
87 - if floating point is done by emulation, forget about instruction
88 scheduling. Note that this only saves compilation time; it doesn't
89 matter for the final code. */
90 #ifdef riscos
91 #define TARGET_WHEN_DEBUGING 3
92 #else
93 #define TARGET_WHEN_DEBUGING 1
94 #endif
96 #define OVERRIDE_OPTIONS \
97 { \
98 if (write_symbols != NO_DEBUG) \
99 target_flags |= TARGET_WHEN_DEBUGING; \
100 else if (TARGET_POKE_FUNCTION_NAME) \
101 target_flags |= 1; \
102 if (TARGET_FPE) \
103 flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
104 }
106 /* Omitting the frame pointer is a very good idea on the ARM, especially if
107 not TARGET_APCS, in which case all that pushing on function entry isn't
108 mandatory anymore. */
109 #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
110 { \
111 if (OPTIMIZE) \
112 flag_omit_frame_pointer = 1; \
113 }
114 \f
115 /* Target machine storage Layout. */
117 /* Define this if most significant bit is lowest numbered
118 in instructions that operate on numbered bit-fields. */
119 #define BITS_BIG_ENDIAN 0
121 /* Define this if most significant byte of a word is the lowest numbered. */
122 #define BYTES_BIG_ENDIAN 0
124 /* Define this if most significant word of a multiword number is the lowest
125 numbered. */
126 #define WORDS_BIG_ENDIAN 0
128 /* Number of bits in an addressible storage unit */
129 #define BITS_PER_UNIT 8
131 #define BITS_PER_WORD 32
133 #define UNITS_PER_WORD 4
135 #define POINTER_SIZE 32
137 #define PARM_BOUNDARY 32
139 #define STACK_BOUNDARY 32
141 #define FUNCTION_BOUNDARY 32
143 #define EMPTY_FIELD_BOUNDARY 32
145 #define BIGGEST_ALIGNMENT 32
147 #define STRICT_ALIGNMENT 1
149 /* Define number of bits in most basic integer type.
150 (If undefined, default is BITS_PER_WORD). */
151 /* #define INT_TYPE_SIZE */
152 \f
153 /* Standard register usage. */
155 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
156 (S - saved over call).
158 r0 * argument word/integer result
159 r1-r3 argument word
161 r4-r8 S register variable
162 r9 S (rfp) register variable (real frame pointer)
164 r10 F S (sl) stack limit (not currently used)
165 r11 F S (fp) argument pointer
166 r12 (ip) temp workspace
167 r13 F S (sp) lower end of current stack frame
168 r14 (lr) link address/workspace
169 r15 F (pc) program counter
171 f0 floating point result
172 f1-f3 floating point scratch
174 f4-f7 S floating point variable
176 *: See CONDITIONAL_REGISTER_USAGE */
178 /* The number of hard registers is 16 ARM + 8 FPU. */
179 #define FIRST_PSEUDO_REGISTER 24
181 /* 1 for registers that have pervasive standard uses
182 and are not available for the register allocator. */
183 #define FIXED_REGISTERS \
184 { \
185 0,0,0,0,0,0,0,0, \
186 0,0,1,1,0,1,0,1, \
187 0,0,0,0,0,0,0,0 \
188 }
190 /* 1 for registers not available across function calls.
191 These must include the FIXED_REGISTERS and also any
192 registers that can be used without being saved.
193 The latter must include the registers where values are returned
194 and the register where structure-value addresses are passed.
195 Aside from that, you can include as many other registers as you like. */
196 #define CALL_USED_REGISTERS \
197 { \
198 1,1,1,1,0,0,0,0, \
199 0,0,1,1,1,1,1,1, \
200 1,1,1,1,0,0,0,0 \
201 }
203 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
204 trampled. This effectively reduces the number of available registers by 1.
205 XXX It is a hack, I know.
206 XXX Is this still needed? */
207 #define CONDITIONAL_REGISTER_USAGE \
208 { \
209 if (obey_regdecls) \
210 fixed_regs[0] = 1; \
211 }
213 /* Return number of consecutive hard regs needed starting at reg REGNO
214 to hold something of mode MODE.
215 This is ordinarily the length in words of a value of mode MODE
216 but can be less for certain modes in special long registers.
218 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
219 mode. */
220 #define HARD_REGNO_NREGS(REGNO, MODE) \
221 ((REGNO) >= 16 ? 1 \
222 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
224 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
225 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
226 regs holding FP. */
227 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
228 ((REGNO) < 16 || GET_MODE_CLASS (MODE) == MODE_FLOAT)
230 /* Value is 1 if it is a good idea to tie two pseudo registers
231 when one has mode MODE1 and one has mode MODE2.
232 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
233 for any hard reg, then this must be 0 for correct output. */
234 #define MODES_TIEABLE_P(MODE1, MODE2) \
235 (((MODE1) == SFmode || (MODE1) == DFmode) \
236 == ((MODE2) == SFmode || (MODE2) == DFmode))
238 /* Specify the registers used for certain standard purposes.
239 The values of these macros are register numbers. */
241 /* Define this if the program counter is overloaded on a register. */
242 #define PC_REGNUM 15
244 /* Register to use for pushing function arguments. */
245 #define STACK_POINTER_REGNUM 13
247 /* Base register for access to local variables of the function. */
248 #define FRAME_POINTER_REGNUM 9
250 /* Value should be nonzero if functions must have frame pointers.
251 Zero means the frame pointer need not be set up (and parms may be accessed
252 via the stack pointer) in functions that seem suitable. */
253 #define FRAME_POINTER_REQUIRED 0
255 /* Base register for access to arguments of the function. */
256 #define ARG_POINTER_REGNUM 11
258 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
259 as an invisible last argument (possible since varargs don't exist in
260 Pascal), so the following is not true. */
261 #define STATIC_CHAIN_REGNUM 8
263 /* Register in which address to store a structure value
264 is passed to a function. */
265 #define STRUCT_VALUE_REGNUM 0
267 /* The order in which register should be allocated. It is good to use ip
268 since no saving is required (though calls clobber it). It is quite good to
269 use lr since other calls may clobber it anyway. */
270 #define REG_ALLOC_ORDER \
271 { \
272 0, 1, 2, 3, 12, 14, 4, 5, \
273 6, 7, 8, 10, 9, 11, 13, 15, \
274 16, 17, 18, 19, 20, 21, 22, 23 \
275 }
276 \f
277 /* Register and constant classes. */
279 /* Register classes: all ARM regs or all FPU regs---simple! */
280 enum reg_class
281 {
282 NO_REGS,
283 FPU_REGS,
284 GENERAL_REGS,
285 ALL_REGS,
286 LIM_REG_CLASSES
287 };
289 #define N_REG_CLASSES (int) LIM_REG_CLASSES
291 /* Give names of register classes as strings for dump file. */
292 #define REG_CLASS_NAMES \
293 { \
298 }
300 /* Define which registers fit in which classes.
301 This is an initializer for a vector of HARD_REG_SET
302 of length N_REG_CLASSES. */
303 #define REG_CLASS_CONTENTS \
304 { \
309 }
311 /* The same information, inverted:
312 Return the class number of the smallest class containing
313 reg number REGNO. This could be a conditional expression
314 or could index an array. */
315 #define REGNO_REG_CLASS(REGNO) \
316 ((REGNO) < 16 ? GENERAL_REGS : FPU_REGS)
318 /* The class value for index registers, and the one for base regs. */
319 #define INDEX_REG_CLASS GENERAL_REGS
320 #define BASE_REG_CLASS GENERAL_REGS
322 /* Get reg_class from a letter such as appears in the machine description.
323 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
324 #define REG_CLASS_FROM_LETTER(C) \
327 /* The letters I, J, K, L and M in a register constraint string
328 can be used to stand for particular ranges of immediate operands.
329 This macro defines what the ranges are.
330 C is the letter, and VALUE is a constant value.
331 Return 1 if VALUE is in the range specified by C.
332 I: immediate arithmetic operand (i.e. 8 bits shifted as requried).
333 J: valid indexing constants. */
334 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
338 /* Constaint letter 'G' for the FPU immediate constants. */
339 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
342 /* Given an rtx X being reloaded into a reg required to be
343 in class CLASS, return the class of reg to actually use.
344 In general this is just CLASS; but on some machines
345 in some cases it is preferable to use a more restrictive class. */
346 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
348 /* Return the maximum number of consecutive registers
349 needed to represent mode MODE in a register of class CLASS.
350 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
351 #define CLASS_MAX_NREGS(CLASS, MODE) \
352 ((CLASS) == FPU_REGS ? 1 \
353 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
355 /* Moves between FPU_REGS and GENERAL_REGS are two insns. */
356 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
357 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
358 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
359 ? 4 : 2)
360 \f
361 /* Stack layout; function entry, exit and calling. */
363 /* Define this if pushing a word on the stack
364 makes the stack pointer a smaller address. */
365 #define STACK_GROWS_DOWNWARD 1
367 /* Define this if the nominal address of the stack frame
368 is at the high-address end of the local variables;
369 that is, each additional local variable allocated
370 goes at a more negative offset in the frame. */
371 #define FRAME_GROWS_DOWNWARD 1
373 /* Offset within stack frame to start allocating local variables at.
374 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
375 first local allocated. Otherwise, it is the offset to the BEGINNING
376 of the first local allocated. */
377 #define STARTING_FRAME_OFFSET 0
379 /* If we generate an insn to push BYTES bytes,
380 this says how many the stack pointer really advances by. */
381 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
383 /* Offset of first parameter from the argument pointer register value. */
384 #define FIRST_PARM_OFFSET(FNDECL) 4
386 /* Value is the number of byte of arguments automatically
387 popped when returning from a subroutine call.
388 FUNTYPE is the data type of the function (as a tree),
389 or for a library call it is an identifier node for the subroutine name.
390 SIZE is the number of bytes of arguments passed on the stack.
392 On the ARM, the caller does not pop any of its arguments that were passed
393 on the stack. */
394 #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
396 /* Define how to find the value returned by a function.
397 VALTYPE is the data type of the value (as a tree).
398 If the precise function being called is known, FUNC is its FUNCTION_DECL;
399 otherwise, FUNC is 0. */
400 #define FUNCTION_VALUE(VALTYPE, FUNC) \
401 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
402 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
403 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
405 /* Define how to find the value returned by a library function
406 assuming the value has mode MODE. */
407 #define LIBCALL_VALUE(MODE) \
408 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
409 ? gen_rtx (REG, MODE, 16) \
410 : gen_rtx (REG, MODE, 0))
412 /* 1 if N is a possible register number for a function value.
413 On the ARM, only r0 and f0 can return results. */
414 #define FUNCTION_VALUE_REGNO_P(REGNO) \
415 ((REGNO) == 0 || (REGNO) == 16)
417 /* Define where to put the arguments to a function.
418 Value is zero to push the argument on the stack,
419 or a hard register in which to store the argument.
421 MODE is the argument's machine mode.
422 TYPE is the data type of the argument (as a tree).
423 This is null for libcalls where that information may
424 not be available.
425 CUM is a variable of type CUMULATIVE_ARGS which gives info about
426 the preceding args and about the function being called.
427 NAMED is nonzero if this argument is a named parameter
428 (otherwise it is an extra parameter matching an ellipsis).
430 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
431 other arguments are passed on the stack. If (NAMED == 0) (which happens
432 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
433 passed in the stack (function_prologue will indeed make it pass in the
434 stack if necessary). */
435 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
436 ((NAMED) \
437 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
438 : 0)
440 /* For an arg passed partly in registers and partly in memory,
441 this is the number of registers used.
442 For args passed entirely in registers or entirely in memory, zero. */
443 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
444 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
445 ? GET_MODE_SIZE (MODE) \
446 : int_size_in_bytes (TYPE)) \
447 ? 4 - (CUM) / 4 : 0)
449 /* A C type for declaring a variable that is used as the first argument of
450 `FUNCTION_ARG' and other related values. For some target machines, the
451 type `int' suffices and can hold the number of bytes of argument so far.
453 On the ARM, this is the number of bytes of arguments scanned so far. */
454 #define CUMULATIVE_ARGS int
456 /* Initialize a variable CUM of type CUMULATIVE_ARGS
457 for a call to a function whose data type is FNTYPE.
458 For a library call, FNTYPE is 0.
459 On the ARM, the offset starts at 0. */
460 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
461 ((CUM) = (((FNTYPE) && aggregate_value_p (FNTYPE)) ? 4 : 0))
463 /* Update the data in CUM to advance over an argument
464 of mode MODE and data type TYPE.
465 (TYPE is null for libcalls where that information may not be available.) */
466 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
467 (CUM) += ((MODE) != BLKmode \
468 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
469 : (int_size_in_bytes (TYPE) + 3) & ~3) \
471 /* 1 if N is a possible register number for function argument passing.
472 On the ARM, r0-r3 are used to pass args. */
473 #define FUNCTION_ARG_REGNO_P(REGNO) \
474 ((REGNO) >= 0 && (REGNO) <= 3)
476 /* Perform any actions needed for a function that is receiving a variable
477 number of arguments. CUM is as above. MODE and TYPE are the mode and type
478 of the current parameter. PRETEND_SIZE is a variable that should be set to
479 the amount of stack that must be pushed by the prolog to pretend that our
480 caller pushed it.
482 Normally, this macro will push all remaining incoming registers on the
483 stack and set PRETEND_SIZE to the length of the registers pushed.
485 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
486 named arg and all anonymous args onto the stack.
487 XXX I know the prologue shouldn't be pushing registers, but it is faster
488 that way. */
489 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
490 { \
491 extern int current_function_anonymous_args; \
492 current_function_anonymous_args = 1; \
493 if ((CUM) < 16) \
494 (PRETEND_SIZE) = 16 - (CUM); \
495 }
497 /* Generate assembly output for the start of a function. */
498 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
499 output_prologue ((STREAM), (SIZE))
501 /* Call the function profiler with a given profile label. The Acorn compiler
502 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
503 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
504 to mind about this! */
505 #define FUNCTION_PROFILER(STREAM,LABELNO) \
506 { \
510 arm_increase_location (12); \
511 }
513 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
514 the stack pointer does not matter. The value is tested only in
515 functions that have frame pointers.
516 No definition is equivalent to always zero.
518 On the ARM, the function epilogue recovers the stack pointer from the
519 frame. */
520 #define EXIT_IGNORE_STACK 1
522 /* Generate the assembly code for function exit. */
523 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
524 output_epilogue ((STREAM), (SIZE))
526 /* Determine if the epilogue should be output as RTL.
527 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
528 /* #define USE_RETURN_INSN use_return_insn () */
530 /* Store in the variable DEPTH the initial difference between the frame
531 pointer reg contents and the stack pointer reg contents, as of the start of
532 the function body. This depends on the layout of the fixed parts of the
533 stack frame and on how registers are saved. */
534 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
535 (DEPTH) = (get_frame_size () + 3) & ~3;
537 /* Output assembler code for a block containing the constant parts
538 of a trampoline, leaving space for the variable parts.
540 On the ARM, (if r8 is the static chain regnum, and remembering that
541 referencing pc adds an offset of 8) the trampoline looks like:
542 ldr r8, [pc, #0]
543 ldr pc, [pc]
544 .word static chain value
545 .word function's address */
546 #define TRAMPOLINE_TEMPLATE(FILE) \
547 { \
552 }
554 /* Length in units of the trampoline for entering a nested function. */
555 #define TRAMPOLINE_SIZE 16
557 /* Alignment required for a trampoline in units. */
558 #define TRAMPOLINE_ALIGN 4
560 /* Emit RTL insns to initialize the variable parts of a trampoline.
561 FNADDR is an RTX for the address of the function's pure code.
562 CXT is an RTX for the static chain value for the function. */
563 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
564 { \
565 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
566 (CXT)); \
567 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
568 (FNADDR)); \
569 }
571 /* Call the function profiler with a given profile label. The Acorn compiler
572 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
573 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
574 to mind about this! */
575 #define FUNCTION_PROFILER(STREAM,LABELNO) \
576 { \
580 arm_increase_location (12); \
581 }
582 \f
583 /* Addressing modes, and classification of registers for them. */
585 #define HAVE_POST_INCREMENT 1
586 #define HAVE_PRE_INCREMENT 1
587 #define HAVE_POST_DECREMENT 1
588 #define HAVE_PRE_DECREMENT 1
590 /* Macros to check register numbers against specific register classes. */
592 /* These assume that REGNO is a hard or pseudo reg number.
593 They give nonzero only if REGNO is a hard reg of the suitable class
594 or a pseudo reg currently allocated to a suitable hard reg.
595 Since they use reg_renumber, they are safe only once reg_renumber
596 has been allocated, which happens in local-alloc.c.
598 On the ARM, don't allow the pc to be used. */
599 #define REGNO_OK_FOR_BASE_P(REGNO) \
600 ((REGNO) < 15 || (unsigned) reg_renumber[(REGNO)] < 15)
601 #define REGNO_OK_FOR_INDEX_P(REGNO) \
602 REGNO_OK_FOR_BASE_P(REGNO)
604 /* Maximum number of registers that can appear in a valid memory address.
605 The addressing mode [ra,rb, <shift> rc] uses the greatest number of
606 registers. */
607 #define MAX_REGS_PER_ADDRESS 3
609 /* Recognize any constant value that is a valid address. */
610 /* XXX We can address any constant, eventually... */
611 #if 0
612 #define CONSTANT_ADDRESS_P(X) \
613 ( GET_CODE(X) == LABEL_REF \
614 || GET_CODE(X) == SYMBOL_REF \
615 || GET_CODE(X) == CONST_INT \
616 || GET_CODE(X) == CONST )
617 #endif
619 #define CONSTANT_ADDRESS_P(X) \
620 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
622 /* Nonzero if the constant value X is a legitimate general operand.
623 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
625 On the ARM, allow any integer (invalid ones are removed later by insn
626 patterns), nice doubles and symbol_refs which refer to the function's
627 constant pool XXX. */
628 #define LEGITIMATE_CONSTANT_P(X) \
629 (GET_CODE (X) == CONST_INT \
630 || (GET_CODE (X) == CONST_DOUBLE \
631 && const_double_rtx_ok_for_fpu (X)))
632 #if 0
634 #endif
636 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
637 and check its validity for a certain class.
638 We have two alternate definitions for each of them.
639 The usual definition accepts all pseudo regs; the other rejects
640 them unless they have been allocated suitable hard regs.
641 The symbol REG_OK_STRICT causes the latter definition to be used. */
642 #ifndef REG_OK_STRICT
643 /* Nonzero if X is a hard reg that can be used as a base reg
644 or if it is a pseudo reg. */
645 #define REG_OK_FOR_BASE_P(X) \
646 (REGNO (X) < 16 || REGNO (X) >= 24)
647 /* Nonzero if X is a hard reg that can be used as an index
648 or if it is a pseudo reg. */
649 #define REG_OK_FOR_INDEX_P(X) \
650 REG_OK_FOR_BASE_P(X)
651 #define REG_OK_FOR_PRE_POST_P(X) \
652 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
653 #else
654 /* Nonzero if X is a hard reg that can be used as a base reg. */
655 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
656 /* Nonzero if X is a hard reg that can be used as an index. */
657 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
658 #define REG_OK_FOR_PRE_POST_P(X) \
659 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16)
660 #endif
661 \f
662 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
663 that is a valid memory address for an instruction.
664 The MODE argument is the machine mode for the MEM expression
665 that wants to use this address.
667 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
668 #define BASE_REGISTER_RTX_P(X) \
669 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
671 #define INDEX_REGISTER_RTX_P(X) \
672 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
674 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
675 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
676 only be small constants. */
677 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
678 do \
679 { \
680 int range; \
681 \
682 if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
683 range = 1024; \
684 else \
685 { \
686 if (INDEX_REGISTER_RTX_P (INDEX)) \
687 goto LABEL; \
688 if (GET_MODE_SIZE (MODE) <= 4 && GET_CODE (INDEX) == MULT) \
689 { \
690 rtx xiop0 = XEXP (INDEX, 0); \
691 rtx xiop1 = XEXP (INDEX, 1); \
692 if (INDEX_REGISTER_RTX_P (xiop0) && power_of_two_operand (xiop1, SImode)) \
693 goto LABEL; \
694 if (INDEX_REGISTER_RTX_P (xiop1) && power_of_two_operand (xiop0, SImode)) \
695 goto LABEL; \
696 } \
697 range = 4096; \
698 } \
699 \
700 if (GET_CODE (INDEX) == CONST_INT && abs (INTVAL (INDEX)) < range) \
701 goto LABEL; \
702 } while (0)
704 /* Jump to LABEL if X is a valid address RTX. This must also take
705 REG_OK_STRICT into account when deciding about valid registers, but it uses
706 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
707 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
708 Allow REG-only and AUTINC-REG if handling TImode. Other symbol refs must
709 be forced though a static cell to ensure addressability. */
710 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
711 { \
712 if (BASE_REGISTER_RTX_P (X)) \
713 goto LABEL; \
714 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
715 && GET_CODE (XEXP (X, 0)) == REG \
716 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
717 goto LABEL; \
718 else if ((MODE) == TImode) \
719 ; \
720 else if (GET_CODE (X) == PLUS) \
721 { \
722 rtx xop0 = XEXP(X,0); \
723 rtx xop1 = XEXP(X,1); \
724 \
725 if (BASE_REGISTER_RTX_P (xop0)) \
726 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
727 else if (BASE_REGISTER_RTX_P (xop1)) \
728 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
729 } \
730 else if (GET_CODE (X) == MINUS) \
731 { \
732 rtx xop0 = XEXP (X,0); \
733 rtx xop1 = XEXP (X,1); \
734 \
735 if (BASE_REGISTER_RTX_P (xop0)) \
736 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
737 } \
738 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
739 && GET_CODE (X) == SYMBOL_REF \
740 && CONSTANT_POOL_ADDRESS_P (X)) \
741 goto LABEL; \
742 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
743 && GET_CODE (XEXP (X, 0)) == REG \
744 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
745 goto LABEL; \
746 }
747 \f
748 /* Try machine-dependent ways of modifying an illegitimate address
749 to be legitimate. If we find one, return the new, valid address.
750 This macro is used in only one place: `memory_address' in explow.c.
752 OLDX is the address as it was before break_out_memory_refs was called.
753 In some cases it is useful to look at this to decide what needs to be done.
755 MODE and WIN are passed so that this macro can use
756 GO_IF_LEGITIMATE_ADDRESS.
758 It is always safe for this macro to do nothing. It exists to recognize
759 opportunities to optimize the output.
761 On the ARM, try to convert [REG, #BIGCONST]
762 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
763 where VALIDCONST == 0 in case of TImode. */
764 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
765 { \
766 if (GET_CODE (X) == PLUS) \
767 { \
768 rtx xop0 = XEXP (X, 0); \
769 rtx xop1 = XEXP (X, 1); \
770 \
771 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
772 { \
773 int n = INTVAL (xop1); \
774 int low_n = ((MODE) == TImode ? 0 \
775 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
776 rtx base_reg = gen_reg_rtx (SImode); \
777 rtx val = force_operand (gen_rtx (PLUS, SImode, xop0, \
778 gen_rtx (CONST_INT, \
779 VOIDmode, n - low_n)), \
780 0); \
781 emit_move_insn (base_reg, val); \
782 (X) = (low_n == 0 ? base_reg \
783 : gen_rtx (PLUS, SImode, base_reg, \
784 gen_rtx (CONST_INT, VOIDmode, low_n))); \
785 } \
786 else if (BASE_REGISTER_RTX_P (xop1) && GET_CODE (xop0) == CONST_INT) \
787 { \
788 int n = INTVAL (xop0); \
789 int low_n = ((MODE) == TImode ? 0 \
790 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
791 rtx base_reg = gen_reg_rtx (SImode); \
792 rtx val = force_operand (gen_rtx (PLUS, SImode, xop1, \
793 gen_rtx (CONST_INT, \
794 VOIDmode, n - low_n)), \
795 0); \
796 emit_move_insn (base_reg, val); \
797 (X) = (low_n == 0 ? base_reg \
798 : gen_rtx (PLUS, SImode, base_reg, \
799 gen_rtx (CONST_INT, VOIDmode, low_n))); \
800 } \
801 } \
802 if (memory_address_p (MODE, X)) \
803 goto win; \
804 }
806 /* Go to LABEL if ADDR (a legitimate address expression)
807 has an effect that depends on the machine mode it is used for. */
808 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
809 { \
810 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
811 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
812 goto LABEL; \
813 }
814 \f
815 /* Specify the machine mode that this machine uses
816 for the index in the tablejump instruction. */
817 #define CASE_VECTOR_MODE SImode
819 /* Define this if the tablejump instruction expects the table
820 to contain offsets from the address of the table.
821 Do not define this if the table should contain absolute addresses. */
822 /* #define CASE_VECTOR_PC_RELATIVE */
824 /* Specify the tree operation to be used to convert reals to integers. */
825 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
827 /* This is the kind of divide that is easiest to do in the general case. */
828 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
830 /* 'char' is signed by default on RISCiX, unsigned on RISCOS. */
831 #ifdef riscos
832 #define DEFAULT_SIGNED_CHAR 0
833 #else
834 #define DEFAULT_SIGNED_CHAR 1
835 #endif
837 /* Don't cse the address of the function being compiled. */
838 #define NO_RECURSIVE_FUNCTION_CSE 1
840 /* Max number of bytes we can move from memory to memory
841 in one reasonably fast instruction.
842 On the ARM, there are no instructions which move memory to memory! */
843 #define MOVE_MAX 0
845 /* Define if normal loads of shorter-than-word items from memory clears
846 the rest of the bigs in the register.
847 On the ARM, movhi does a garbage extend. */
848 /* #define BYTE_LOADS_ZERO_EXTEND */
850 /* Define this if zero-extension is slow (more than one real instruction).
851 On the ARM, it is more than one instruction only if not fetching from
852 memory. */
853 /* #define SLOW_ZERO_EXTEND */
855 /* Nonzero if access to memory by bytes is slow and undesirable. */
856 #define SLOW_BYTE_ACCESS 0
858 /* Immediate shift counts are truncated by the output routines (or was it
859 the assembler?). Shift counts in a register are truncated by ARM. Note
860 that the native compiler puts too large (> 32) immediate shift counts
861 into a register and shifts by the register, letting the ARM decide what
862 to do instead of doing that itself. */
863 #define SHIFT_COUNT_TRUNCATED 1
865 /* We have the vprintf function. */
866 #define HAVE_VPRINTF 1
868 /* XX This is not true, is it? */
869 /* All integers have the same format so truncation is easy. */
870 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
872 /* Calling from registers is a massive pain. */
873 #define NO_FUNCTION_CSE 1
875 /* Chars and shorts should be passed as ints. */
876 #define PROMOTE_PROTOTYPES 1
878 /* There is no support for s<cond> insns at present */
879 #define STORE_FLAG_VALUE 0
881 /* The machine modes of pointers and functions */
882 #define Pmode SImode
883 #define FUNCTION_MODE Pmode
885 /* The structure type of the machine dependent info field of insns
886 No uses for this yet. */
887 /* #define INSN_MACHINE_INFO struct machine_info */
889 /* The relative costs of various types of constants. Note that cse.c defines
890 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
891 #define CONST_COSTS(RTX, CODE) \
892 case CONST_INT: \
893 if (const_ok_for_arm (INTVAL (RTX))) \
894 return (2); \
895 else \
896 return (5); \
897 \
898 case CONST: \
899 case LABEL_REF: \
900 case SYMBOL_REF: \
901 return (6); \
902 \
903 case CONST_DOUBLE: \
904 if (const_double_rtx_ok_for_fpu (RTX)) \
905 return(2); \
906 else \
907 return(7);
908 \f
909 /* Condition code information. */
911 /* Store in cc_status the expressions
912 that the condition codes will describe
913 after execution of an instruction whose pattern is EXP.
914 Do not alter them if the instruction would not alter the cc's. */
916 /* On the ARM nothing sets the condition code implicitly---apart from DImode
917 operations excluding moves---but we have to watch for registers in the
918 condition code value being clobbered. This clobbering includes (alas)
919 function calls. XXX They could just be considered to clobber regs 0-3 and
920 10-15 with extra work. */
921 #define NOTICE_UPDATE_CC(EXP, INSN) \
922 { \
923 if (GET_MODE (EXP) == DImode \
924 && GET_CODE (EXP) == SET \
925 && GET_CODE (SET_SRC (EXP)) != REG \
926 && GET_CODE (SET_SRC (EXP)) != MEM \
927 && GET_CODE (SET_SRC (EXP)) != CONST_INT) \
928 CC_STATUS_INIT; \
929 else if (GET_CODE (EXP) == SET) \
930 { \
931 rtx dest = SET_DEST (EXP); \
932 if (dest == cc0_rtx) \
933 { \
934 cc_status.flags = 0; \
935 cc_status.value1 = SET_DEST (EXP); \
936 cc_status.value2 = SET_SRC (EXP); \
937 } \
938 if (BASE_REGISTER_RTX_P (dest)) \
939 { \
940 if (cc_status.value1 \
941 && reg_overlap_mentioned_p (dest, cc_status.value1)) \
942 cc_status.value1 = 0; \
943 if (cc_status.value2 \
944 && reg_overlap_mentioned_p (dest, cc_status.value2)) \
945 cc_status.value2 = 0; \
946 } \
947 } \
948 else if (GET_CODE (INSN) != JUMP_INSN && GET_CODE (EXP) == PARALLEL) \
949 { \
950 CC_STATUS_INIT; \
951 } \
952 }
953 \f
954 /* Assembler output control */
956 /* The text to go at the start of the assembler file */
957 #define ASM_FILE_START(STREAM) \
958 { \
959 extern char *version_string; \
960 \
968 }
973 /* Switch to the text or data segment. */
977 /* The assembler's names for the registers. RFP need not always be used as
978 the Real framepointer; it can also be used as a normal general register.
979 Note that the name `fp' is horribly misleading since `fp' is in fact only
980 the argument-and-return-context pointer. */
981 #define REGISTER_NAMES \
982 { \
986 }
988 /* DBX register number for a given compiler register number */
989 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
991 /* Generate DBX debugging information. */
992 #define DBX_DEBUGGING_INFO 1
994 /* Acorn dbx moans about continuation chars, so don't use any. */
995 #define DBX_CONTIN_LENGTH 0
997 /* Output a label definition. */
998 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
999 arm_asm_output_label ((STREAM), (NAME))
1001 /* Output a function label definition. */
1002 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1003 ASM_OUTPUT_LABEL(STREAM, NAME)
1005 /* Output a globalising directive for a label. */
1006 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1008 assemble_name (STREAM, NAME), \
1011 /* Output a reference to a label. */
1012 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1015 /* Make an internal label into a string. */
1016 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1019 /* Output an internal label definition. */
1020 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1021 do \
1022 { \
1023 char *s = (char *) alloca (11 + strlen (PREFIX)); \
1024 extern int arm_target_label, arm_ccfsm_state; \
1025 \
1026 if (arm_ccfsm_state == 3 && arm_target_label == (NUM)) \
1027 arm_ccfsm_state = 0; \
1030 arm_asm_output_label (STREAM, s); \
1031 } while (0)
1033 /* Nothing special is done about jump tables */
1034 /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1035 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1037 /* Construct a private name. */
1038 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1039 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1042 /* Output a push or a pop instruction (only used when profiling). */
1043 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1044 (arm_increase_location (4) \
1047 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1048 (arm_increase_location (4) \
1051 /* Output a relative address. Not needed since jump tables are absolute
1052 but we must define it anyway. */
1053 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1056 /* Output an element of a dispatch table. */
1057 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1058 (arm_increase_location (4) \
1061 /* Output various types of constants. */
1062 #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1063 (arm_increase_location (sizeof (double)) \
1066 #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1067 (arm_increase_location (sizeof (float)) \
1070 #define ASM_OUTPUT_INT(STREAM, EXP) \
1072 output_addr_const (STREAM, (EXP)), \
1073 arm_increase_location (4), \
1076 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1078 output_addr_const (STREAM, (EXP)), \
1079 arm_increase_location (2), \
1082 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1084 output_addr_const (STREAM, (EXP)), \
1085 arm_increase_location (1), \
1088 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1090 arm_increase_location (1))
1092 #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
1093 output_ascii_pseudo_op ((STREAM), (PTR), (LEN))
1095 /* Output a gap. In fact we fill it with nulls. */
1096 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1097 (arm_increase_location (NBYTES), \
1100 /* Align output to a power of two. Horrible /bin/as. */
1101 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1102 do \
1103 { \
1104 register int amount = 1 << (POWER); \
1105 extern int arm_text_location; \
1106 \
1107 if (amount == 2) \
1109 else \
1111 \
1112 if (in_text_section ()) \
1113 arm_text_location = ((arm_text_location + amount - 1) \
1114 & ~(amount - 1)); \
1115 } while (0)
1117 /* Output a common block */
1118 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1120 assemble_name ((STREAM), (NAME)), \
1123 /* Output a local common block. /bin/as can't do this, so hack a `.space' into
1124 the bss segment. Note that this is *bad* practice. */
1125 #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1126 output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1128 /* Output a source filename for the debugger. RISCiX dbx insists that the
1129 ``desc'' field is set to compiler version number >= 315 (sic). */
1130 #if 0
1131 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM,NAME) \
1133 #endif
1135 /* Output a source line for the debugger. */
1136 /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1138 /* Output a #ident directive. */
1139 #define ASM_OUTPUT_IDENT(STREAM,STRING) \
1142 /* The assembler's parentheses characters. */
1146 /* Target characters. */
1147 #define TARGET_BELL 007
1148 #define TARGET_BS 010
1149 #define TARGET_TAB 011
1150 #define TARGET_NEWLINE 012
1151 #define TARGET_VT 013
1152 #define TARGET_FF 014
1153 #define TARGET_CR 015
1154 \f
1155 /* FINAL_PRESCAN_INSN is used to take a look at the insns, in order to delete
1156 small-distance conditional branches and have ASM_OUTPUT_OPCODE make the
1157 instructions conditional. Suffixes like s (affect flags) and b (bytewise
1158 load/store) need to stay suffixes, so the possible condition code comes
1159 before these suffixes. */
1160 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1161 { \
1162 extern int arm_ccfsm_state, arm_current_cc; \
1163 extern char *arm_condition_codes[]; \
1164 int i; \
1165 \
1167 if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) \
1168 { \
1170 arm_ccfsm_state += 2; \
1171 } \
1172 else if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) \
1173 { \
1175 putc (*(PTR), STREAM); \
1178 putc (*(PTR), STREAM); \
1179 } \
1180 }
1182 /* Only perform branch elimination (by making instructions conditional) if
1183 we're optimising. Otherwise it's of no use anyway. */
1184 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1185 if (optimize) \
1186 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1188 /* Output an operand of an instruction. If X is a REG and CODE is `M', output
1189 a ldm/stm style multi-reg. */
1190 #define PRINT_OPERAND(STREAM, X, CODE) \
1191 { \
1193 fputs (reg_names[REGNO (X) + 1], (STREAM)); \
1194 else if (GET_CODE (X) == REG) \
1195 { \
1197 fputs (reg_names[REGNO (X)], (STREAM)); \
1198 else \
1200 reg_names[REGNO (X)], \
1201 reg_names[REGNO (X) - 1 \
1202 + ((GET_MODE_SIZE (GET_MODE (X)) \
1203 + GET_MODE_SIZE (SImode) - 1) \
1204 / GET_MODE_SIZE (SImode))]); \
1205 } \
1206 else if (GET_CODE (X) == MEM) \
1207 { \
1208 extern int output_memory_reference_mode; \
1209 output_memory_reference_mode = GET_MODE (X); \
1210 output_address (XEXP (X, 0)); \
1211 } \
1212 else if (GET_CODE(X) == CONST_DOUBLE) \
1213 { \
1214 union real_extract u; \
1215 u.i[0] = CONST_DOUBLE_LOW (X); \
1216 u.i[1] = CONST_DOUBLE_HIGH (X); \
1218 } \
1219 else if (GET_CODE (X) == NEG) \
1220 { \
1222 output_operand ((X), 0); \
1223 } \
1224 else \
1225 { \
1227 output_addr_const(STREAM, X); \
1228 } \
1229 }
1231 /* Output the address of an operand. */
1232 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1233 { \
1234 int is_minus = GET_CODE (X) == MINUS; \
1235 \
1236 if (GET_CODE (X) == REG) \
1238 else if (GET_CODE (X) == PLUS || is_minus) \
1239 { \
1240 rtx base = XEXP (X, 0); \
1241 rtx index = XEXP (X, 1); \
1242 char *base_reg_name; \
1243 int offset = 0; \
1244 int shift; \
1245 if (GET_CODE (base) != REG) \
1246 { \
1248 rtx temp = base; \
1249 base = index; \
1250 index = temp; \
1251 } \
1252 base_reg_name = reg_names[REGNO (base)]; \
1253 switch (GET_CODE (index)) \
1254 { \
1255 case CONST_INT: \
1256 offset = INTVAL (index); \
1257 if (is_minus) \
1258 offset = -offset; \
1260 break; \
1261 \
1262 case REG: \
1265 break; \
1266 \
1267 case MULT: \
1268 if (GET_CODE (XEXP (index,0)) == CONST_INT) \
1269 { \
1270 shift = int_log2 (INTVAL (XEXP (index, 0))); \
1271 index = XEXP (index, 1); \
1272 } \
1273 else if (GET_CODE(XEXP(index,1)) == CONST_INT) \
1274 { \
1275 shift = int_log2 (INTVAL (XEXP (index, 1))); \
1276 index = XEXP (index, 0); \
1277 } \
1278 else \
1279 abort(); \
1282 shift); \
1283 break; \
1284 \
1285 default: \
1286 abort(); \
1287 } \
1288 } \
1289 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1290 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1291 { \
1292 extern int output_memory_reference_mode; \
1293 \
1294 if (GET_CODE (XEXP (X, 0)) != REG) \
1295 abort (); \
1296 \
1297 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1300 GET_MODE_SIZE (output_memory_reference_mode)); \
1301 else \
1304 GET_MODE_SIZE (output_memory_reference_mode)); \
1305 } \
1306 else output_addr_const(STREAM, X); \
1307 }
1309 /* EOF arm.h */