| blob | c8c3a680d823db8fc28579f16f994ba07c48395d |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 (FIRST_SPE_HIGH_REGNO 117)
60 (LAST_SPE_HIGH_REGNO 148)
61 ])
63 ;;
64 ;; UNSPEC usage
65 ;;
67 (define_c_enum "unspec"
68 [UNSPEC_FRSP ; frsp for POWER machines
69 UNSPEC_PROBE_STACK ; probe stack memory reference
70 UNSPEC_TOCPTR ; address of a word pointing to the TOC
71 UNSPEC_TOC ; address of the TOC (more-or-less)
72 UNSPEC_MOVSI_GOT
73 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
74 UNSPEC_FCTIWZ
75 UNSPEC_FRIM
76 UNSPEC_FRIN
77 UNSPEC_FRIP
78 UNSPEC_FRIZ
79 UNSPEC_LD_MPIC ; load_macho_picbase
80 UNSPEC_RELD_MPIC ; re-load_macho_picbase
81 UNSPEC_MPIC_CORRECT ; macho_correct_pic
82 UNSPEC_TLSGD
83 UNSPEC_TLSLD
84 UNSPEC_MOVESI_FROM_CR
85 UNSPEC_MOVESI_TO_CR
86 UNSPEC_TLSDTPREL
87 UNSPEC_TLSDTPRELHA
88 UNSPEC_TLSDTPRELLO
89 UNSPEC_TLSGOTDTPREL
90 UNSPEC_TLSTPREL
91 UNSPEC_TLSTPRELHA
92 UNSPEC_TLSTPRELLO
93 UNSPEC_TLSGOTTPREL
94 UNSPEC_TLSTLS
95 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
96 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
97 UNSPEC_STFIWX
98 UNSPEC_POPCNTB
99 UNSPEC_FRES
100 UNSPEC_SP_SET
101 UNSPEC_SP_TEST
102 UNSPEC_SYNC
103 UNSPEC_LWSYNC
104 UNSPEC_SYNC_OP
105 UNSPEC_ATOMIC
106 UNSPEC_CMPXCHG
107 UNSPEC_XCHG
108 UNSPEC_AND
109 UNSPEC_DLMZB
110 UNSPEC_DLMZB_CR
111 UNSPEC_DLMZB_STRLEN
112 UNSPEC_RSQRT
113 UNSPEC_TOCREL
114 UNSPEC_MACHOPIC_OFFSET
115 UNSPEC_BPERM
116 UNSPEC_COPYSIGN
117 UNSPEC_PARITY
118 UNSPEC_FCTIW
119 UNSPEC_FCTID
120 UNSPEC_LFIWAX
121 UNSPEC_LFIWZX
122 UNSPEC_FCTIWUZ
123 UNSPEC_GRP_END_NOP
124 UNSPEC_P8V_FMRGOW
125 UNSPEC_P8V_MTVSRWZ
126 UNSPEC_P8V_RELOAD_FROM_GPR
127 UNSPEC_P8V_MTVSRD
128 UNSPEC_P8V_XXPERMDI
129 UNSPEC_P8V_RELOAD_FROM_VSX
130 UNSPEC_ADDG6S
131 UNSPEC_CDTBCD
132 UNSPEC_CBCDTD
133 UNSPEC_DIVE
134 UNSPEC_DIVEO
135 UNSPEC_DIVEU
136 UNSPEC_DIVEUO
137 UNSPEC_UNPACK_128BIT
138 UNSPEC_PACK_128BIT
139 UNSPEC_LSQ
140 UNSPEC_FUSION_GPR
141 ])
143 ;;
144 ;; UNSPEC_VOLATILE usage
145 ;;
147 (define_c_enum "unspecv"
148 [UNSPECV_BLOCK
149 UNSPECV_LL ; load-locked
150 UNSPECV_SC ; store-conditional
151 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
152 UNSPECV_EH_RR ; eh_reg_restore
153 UNSPECV_ISYNC ; isync instruction
154 UNSPECV_MFTB ; move from time base
155 UNSPECV_NLGR ; non-local goto receiver
156 UNSPECV_MFFS ; Move from FPSCR
157 UNSPECV_MTFSF ; Move to FPSCR Fields
158 ])
160 \f
161 ;; Define an insn type attribute. This is used in function unit delay
162 ;; computations.
163 (define_attr "type"
164 "integer,two,three,
165 add,logical,shift,insert,
166 mul,halfmul,div,
167 exts,cntlz,popcnt,isel,
168 load,store,fpload,fpstore,vecload,vecstore,
169 cmp,
170 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
171 compare,
172 cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
173 fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
174 brinc,
175 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
176 vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
177 htm"
178 (const_string "integer"))
180 ;; What data size does this instruction work on?
181 ;; This is used for insert, mul.
182 (define_attr "size" "8,16,32,64" (const_string "32"))
184 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
185 ;; This is used for add, logical, shift, exts, mul.
186 (define_attr "dot" "no,yes" (const_string "no"))
188 ;; Does this instruction sign-extend its result?
189 ;; This is used for load insns.
190 (define_attr "sign_extend" "no,yes" (const_string "no"))
192 ;; Does this instruction use indexed (that is, reg+reg) addressing?
193 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
194 ;; it is automatically set based on that. If a load or store instruction
195 ;; has fewer than two operands it needs to set this attribute manually
196 ;; or the compiler will crash.
197 (define_attr "indexed" "no,yes"
198 (if_then_else (ior (match_operand 0 "indexed_address_mem")
199 (match_operand 1 "indexed_address_mem"))
200 (const_string "yes")
201 (const_string "no")))
203 ;; Does this instruction use update addressing?
204 ;; This is used for load and store insns. See the comments for "indexed".
205 (define_attr "update" "no,yes"
206 (if_then_else (ior (match_operand 0 "update_address_mem")
207 (match_operand 1 "update_address_mem"))
208 (const_string "yes")
209 (const_string "no")))
211 ;; Is this instruction using operands[2] as shift amount, and can that be a
212 ;; register?
213 ;; This is used for shift insns.
214 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
216 ;; Is this instruction using a shift amount from a register?
217 ;; This is used for shift insns.
218 (define_attr "var_shift" "no,yes"
219 (if_then_else (and (eq_attr "type" "shift")
220 (eq_attr "maybe_var_shift" "yes"))
221 (if_then_else (match_operand 2 "gpc_reg_operand")
222 (const_string "yes")
223 (const_string "no"))
224 (const_string "no")))
226 ;; Define floating point instruction sub-types for use with Xfpu.md
227 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
229 ;; Length (in bytes).
230 ; '(pc)' in the following doesn't include the instruction itself; it is
231 ; calculated as if the instruction had zero size.
232 (define_attr "length" ""
233 (if_then_else (eq_attr "type" "branch")
234 (if_then_else (and (ge (minus (match_dup 0) (pc))
235 (const_int -32768))
236 (lt (minus (match_dup 0) (pc))
237 (const_int 32764)))
238 (const_int 4)
239 (const_int 8))
240 (const_int 4)))
242 ;; Processor type -- this attribute must exactly match the processor_type
243 ;; enumeration in rs6000-opts.h.
244 (define_attr "cpu"
245 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
246 ppc750,ppc7400,ppc7450,
247 ppc403,ppc405,ppc440,ppc476,
248 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
249 power4,power5,power6,power7,power8,
250 rs64a,mpccore,cell,ppca2,titan"
251 (const (symbol_ref "rs6000_cpu_attr")))
254 ;; If this instruction is microcoded on the CELL processor
255 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
256 (define_attr "cell_micro" "not,conditional,always"
257 (if_then_else (ior (eq_attr "type" "compare")
258 (and (eq_attr "type" "shift,exts,mul")
259 (eq_attr "dot" "yes"))
260 (and (eq_attr "type" "load")
261 (eq_attr "sign_extend" "yes"))
262 (and (eq_attr "type" "shift")
263 (eq_attr "var_shift" "yes")))
264 (const_string "always")
265 (const_string "not")))
267 (automata_option "ndfa")
269 (include "rs64.md")
270 (include "mpc.md")
271 (include "40x.md")
272 (include "440.md")
273 (include "476.md")
274 (include "601.md")
275 (include "603.md")
276 (include "6xx.md")
277 (include "7xx.md")
278 (include "7450.md")
279 (include "8540.md")
280 (include "e300c2c3.md")
281 (include "e500mc.md")
282 (include "e500mc64.md")
283 (include "e5500.md")
284 (include "e6500.md")
285 (include "power4.md")
286 (include "power5.md")
287 (include "power6.md")
288 (include "power7.md")
289 (include "power8.md")
290 (include "cell.md")
291 (include "xfpu.md")
292 (include "a2.md")
293 (include "titan.md")
295 (include "predicates.md")
296 (include "constraints.md")
298 (include "darwin.md")
300 \f
301 ;; Mode iterators
303 ; This mode iterator allows :GPR to be used to indicate the allowable size
304 ; of whole values in GPRs.
305 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
307 ; Any supported integer mode.
308 (define_mode_iterator INT [QI HI SI DI TI PTI])
310 ; Any supported integer mode that fits in one register.
311 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
313 ; Everything we can extend QImode to.
314 (define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")])
316 ; Everything we can extend HImode to.
317 (define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")])
319 ; Everything we can extend SImode to.
320 (define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")])
322 ; QImode or HImode for small atomic ops
323 (define_mode_iterator QHI [QI HI])
325 ; HImode or SImode for sign extended fusion ops
326 (define_mode_iterator HSI [HI SI])
328 ; SImode or DImode, even if DImode doesn't fit in GPRs.
329 (define_mode_iterator SDI [SI DI])
331 ; The size of a pointer. Also, the size of the value that a record-condition
332 ; (one with a '.') will compare; and the size used for arithmetic carries.
333 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
335 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
336 ; PTImode is GPR only)
337 (define_mode_iterator TI2 [TI PTI])
339 ; Any hardware-supported floating-point mode
340 (define_mode_iterator FP [
341 (SF "TARGET_HARD_FLOAT
342 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
343 (DF "TARGET_HARD_FLOAT
344 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
345 (TF "!TARGET_IEEEQUAD
346 && TARGET_HARD_FLOAT
347 && (TARGET_FPRS || TARGET_E500_DOUBLE)
348 && TARGET_LONG_DOUBLE_128")
349 (DD "TARGET_DFP")
350 (TD "TARGET_DFP")])
352 ; Any fma capable floating-point mode.
353 (define_mode_iterator FMA_F [
354 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
355 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
356 || VECTOR_UNIT_VSX_P (DFmode)")
357 (V2SF "TARGET_PAIRED_FLOAT")
358 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
359 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
360 ])
362 ; Floating point move iterators to combine binary and decimal moves
363 (define_mode_iterator FMOVE32 [SF SD])
364 (define_mode_iterator FMOVE64 [DF DD])
365 (define_mode_iterator FMOVE64X [DI DF DD])
366 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
367 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
369 ; Iterators for 128 bit types for direct move
370 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
371 (V16QI "")
372 (V8HI "")
373 (V4SI "")
374 (V4SF "")
375 (V2DI "")
376 (V2DF "")
377 (V1TI "")])
379 ; Whether a floating point move is ok, don't allow SD without hardware FP
380 (define_mode_attr fmove_ok [(SF "")
381 (DF "")
382 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
383 (DD "")])
385 ; Convert REAL_VALUE to the appropriate bits
386 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
387 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
388 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
389 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
391 ; Definitions for load to 32-bit fpr register
392 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
393 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
394 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
395 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
397 ; Definitions for store from 32-bit fpr register
398 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
399 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
400 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
401 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
403 ; Definitions for 32-bit fpr direct move
404 ; At present, the decimal modes are not allowed in the traditional altivec
405 ; registers, so restrict the constraints to just the traditional FPRs.
406 (define_mode_attr f32_dm [(SF "wn") (SD "wh")])
408 ; Definitions for 32-bit VSX
409 (define_mode_attr f32_vsx [(SF "ww") (SD "wn")])
411 ; Definitions for 32-bit use of altivec registers
412 (define_mode_attr f32_av [(SF "wu") (SD "wn")])
414 ; Definitions for 64-bit VSX
415 (define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
417 ; Definitions for 64-bit direct move
418 (define_mode_attr f64_dm [(DF "wk") (DD "wh")])
420 ; Definitions for 64-bit use of altivec registers
421 (define_mode_attr f64_av [(DF "wv") (DD "wn")])
423 ; These modes do not fit in integer registers in 32-bit mode.
424 ; but on e500v2, the gpr are 64 bit registers
425 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
427 ; Iterator for reciprocal estimate instructions
428 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
430 ; Iterator for just SF/DF
431 (define_mode_iterator SFDF [SF DF])
433 ; SF/DF suffix for traditional floating instructions
434 (define_mode_attr Ftrad [(SF "s") (DF "")])
436 ; SF/DF suffix for VSX instructions
437 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
439 ; SF/DF constraint for arithmetic on traditional floating point registers
440 (define_mode_attr Ff [(SF "f") (DF "d")])
442 ; SF/DF constraint for arithmetic on VSX registers
443 (define_mode_attr Fv [(SF "wy") (DF "ws")])
445 ; SF/DF constraint for arithmetic on altivec registers
446 (define_mode_attr Fa [(SF "wu") (DF "wv")])
448 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
449 (define_mode_attr Fs [(SF "s") (DF "d")])
451 ; FRE/FRES support
452 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
453 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
455 ; Conditional returns.
456 (define_code_iterator any_return [return simple_return])
457 (define_code_attr return_pred [(return "direct_return ()")
458 (simple_return "1")])
459 (define_code_attr return_str [(return "") (simple_return "simple_")])
461 ; Logical operators.
462 (define_code_iterator iorxor [ior xor])
464 ; Signed/unsigned variants of ops.
465 (define_code_iterator any_extend [sign_extend zero_extend])
466 (define_code_attr u [(sign_extend "") (zero_extend "u")])
467 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
469 ; Various instructions that come in SI and DI forms.
470 ; A generic w/d attribute, for things like cmpw/cmpd.
471 (define_mode_attr wd [(QI "b")
472 (HI "h")
473 (SI "w")
474 (DI "d")
475 (V16QI "b")
476 (V8HI "h")
477 (V4SI "w")
478 (V2DI "d")])
480 ;; How many bits in this mode?
481 (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
483 ; DImode bits
484 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
486 ;; ISEL/ISEL64 target selection
487 (define_mode_attr sel [(SI "") (DI "64")])
489 ;; Bitmask for shift instructions
490 (define_mode_attr hH [(SI "h") (DI "H")])
492 ;; A mode twice the size of the given mode
493 (define_mode_attr dmode [(SI "di") (DI "ti")])
494 (define_mode_attr DMODE [(SI "DI") (DI "TI")])
496 ;; Suffix for reload patterns
497 (define_mode_attr ptrsize [(SI "32bit")
498 (DI "64bit")])
500 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
501 (DI "TARGET_64BIT")])
503 (define_mode_attr mptrsize [(SI "si")
504 (DI "di")])
506 (define_mode_attr ptrload [(SI "lwz")
507 (DI "ld")])
509 (define_mode_attr ptrm [(SI "m")
510 (DI "Y")])
512 (define_mode_attr rreg [(SF "f")
513 (DF "ws")
514 (TF "f")
515 (TD "f")
516 (V4SF "wf")
517 (V2DF "wd")])
519 (define_mode_attr rreg2 [(SF "f")
520 (DF "d")])
522 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
523 (DF "TARGET_FCFID")])
525 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
526 (DF "TARGET_E500_DOUBLE")])
528 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
529 (DF "TARGET_DOUBLE_FLOAT")])
531 ;; Mode iterator for logical operations on 128-bit types
532 (define_mode_iterator BOOL_128 [TI
533 PTI
534 (V16QI "TARGET_ALTIVEC")
535 (V8HI "TARGET_ALTIVEC")
536 (V4SI "TARGET_ALTIVEC")
537 (V4SF "TARGET_ALTIVEC")
538 (V2DI "TARGET_ALTIVEC")
539 (V2DF "TARGET_ALTIVEC")
540 (V1TI "TARGET_ALTIVEC")])
542 ;; For the GPRs we use 3 constraints for register outputs, two that are the
543 ;; same as the output register, and a third where the output register is an
544 ;; early clobber, so we don't have to deal with register overlaps. For the
545 ;; vector types, we prefer to use the vector registers. For TI mode, allow
546 ;; either.
548 ;; Mode attribute for boolean operation register constraints for output
549 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v")
550 (PTI "&r,r,r")
551 (V16QI "wa,v,&?r,?r,?r")
552 (V8HI "wa,v,&?r,?r,?r")
553 (V4SI "wa,v,&?r,?r,?r")
554 (V4SF "wa,v,&?r,?r,?r")
555 (V2DI "wa,v,&?r,?r,?r")
556 (V2DF "wa,v,&?r,?r,?r")
557 (V1TI "wa,v,&?r,?r,?r")])
559 ;; Mode attribute for boolean operation register constraints for operand1
560 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v")
561 (PTI "r,0,r")
562 (V16QI "wa,v,r,0,r")
563 (V8HI "wa,v,r,0,r")
564 (V4SI "wa,v,r,0,r")
565 (V4SF "wa,v,r,0,r")
566 (V2DI "wa,v,r,0,r")
567 (V2DF "wa,v,r,0,r")
568 (V1TI "wa,v,r,0,r")])
570 ;; Mode attribute for boolean operation register constraints for operand2
571 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v")
572 (PTI "r,r,0")
573 (V16QI "wa,v,r,r,0")
574 (V8HI "wa,v,r,r,0")
575 (V4SI "wa,v,r,r,0")
576 (V4SF "wa,v,r,r,0")
577 (V2DI "wa,v,r,r,0")
578 (V2DF "wa,v,r,r,0")
579 (V1TI "wa,v,r,r,0")])
581 ;; Mode attribute for boolean operation register constraints for operand1
582 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
583 ;; is used for operand1 or operand2
584 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v")
585 (PTI "r,0,0")
586 (V16QI "wa,v,r,0,0")
587 (V8HI "wa,v,r,0,0")
588 (V4SI "wa,v,r,0,0")
589 (V4SF "wa,v,r,0,0")
590 (V2DI "wa,v,r,0,0")
591 (V2DF "wa,v,r,0,0")
592 (V1TI "wa,v,r,0,0")])
594 ;; Reload iterator for creating the function to allocate a base register to
595 ;; supplement addressing modes.
596 (define_mode_iterator RELOAD [V16QI V8HI V4SI V2DI V4SF V2DF V1TI
597 SF SD SI DF DD DI TI PTI])
599 \f
600 ;; Start with fixed-point load and store insns. Here we put only the more
601 ;; complex forms. Basic data transfer is done later.
603 (define_insn "zero_extendqi<mode>2"
604 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
605 (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
606 ""
607 "@
608 lbz%U1%X1 %0,%1
609 rlwinm %0,%1,0,0xff"
610 [(set_attr "type" "load,shift")])
612 (define_insn_and_split "*zero_extendqi<mode>2_dot"
613 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
614 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
615 (const_int 0)))
616 (clobber (match_scratch:EXTQI 0 "=r,r"))]
617 "rs6000_gen_cell_microcode"
618 "@
619 andi. %0,%1,0xff
620 #"
621 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
622 [(set (match_dup 0)
623 (zero_extend:EXTQI (match_dup 1)))
624 (set (match_dup 2)
625 (compare:CC (match_dup 0)
626 (const_int 0)))]
627 ""
628 [(set_attr "type" "logical")
629 (set_attr "dot" "yes")
630 (set_attr "length" "4,8")])
632 (define_insn_and_split "*zero_extendqi<mode>2_dot2"
633 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
634 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
635 (const_int 0)))
636 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
637 (zero_extend:EXTQI (match_dup 1)))]
638 "rs6000_gen_cell_microcode"
639 "@
640 andi. %0,%1,0xff
641 #"
642 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
643 [(set (match_dup 0)
644 (zero_extend:EXTQI (match_dup 1)))
645 (set (match_dup 2)
646 (compare:CC (match_dup 0)
647 (const_int 0)))]
648 ""
649 [(set_attr "type" "logical")
650 (set_attr "dot" "yes")
651 (set_attr "length" "4,8")])
654 (define_insn "zero_extendhi<mode>2"
655 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
656 (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
657 ""
658 "@
659 lhz%U1%X1 %0,%1
660 rlwinm %0,%1,0,0xffff"
661 [(set_attr "type" "load,shift")])
663 (define_insn_and_split "*zero_extendhi<mode>2_dot"
664 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
665 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
666 (const_int 0)))
667 (clobber (match_scratch:EXTHI 0 "=r,r"))]
668 "rs6000_gen_cell_microcode"
669 "@
670 andi. %0,%1,0xffff
671 #"
672 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
673 [(set (match_dup 0)
674 (zero_extend:EXTHI (match_dup 1)))
675 (set (match_dup 2)
676 (compare:CC (match_dup 0)
677 (const_int 0)))]
678 ""
679 [(set_attr "type" "logical")
680 (set_attr "dot" "yes")
681 (set_attr "length" "4,8")])
683 (define_insn_and_split "*zero_extendhi<mode>2_dot2"
684 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
685 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
686 (const_int 0)))
687 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
688 (zero_extend:EXTHI (match_dup 1)))]
689 "rs6000_gen_cell_microcode"
690 "@
691 andi. %0,%1,0xffff
692 #"
693 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
694 [(set (match_dup 0)
695 (zero_extend:EXTHI (match_dup 1)))
696 (set (match_dup 2)
697 (compare:CC (match_dup 0)
698 (const_int 0)))]
699 ""
700 [(set_attr "type" "logical")
701 (set_attr "dot" "yes")
702 (set_attr "length" "4,8")])
705 (define_insn "zero_extendsi<mode>2"
706 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
707 (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
708 ""
709 "@
710 lwz%U1%X1 %0,%1
711 rldicl %0,%1,0,32
712 mtvsrwz %x0,%1
713 lfiwzx %0,%y1
714 lxsiwzx %x0,%y1"
715 [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
717 (define_insn_and_split "*zero_extendsi<mode>2_dot"
718 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
719 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
720 (const_int 0)))
721 (clobber (match_scratch:EXTSI 0 "=r,r"))]
722 "rs6000_gen_cell_microcode"
723 "@
724 rldicl. %0,%1,0,32
725 #"
726 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
727 [(set (match_dup 0)
728 (zero_extend:DI (match_dup 1)))
729 (set (match_dup 2)
730 (compare:CC (match_dup 0)
731 (const_int 0)))]
732 ""
733 [(set_attr "type" "shift")
734 (set_attr "dot" "yes")
735 (set_attr "length" "4,8")])
737 (define_insn_and_split "*zero_extendsi<mode>2_dot2"
738 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
739 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
740 (const_int 0)))
741 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
742 (zero_extend:EXTSI (match_dup 1)))]
743 "rs6000_gen_cell_microcode"
744 "@
745 rldicl. %0,%1,0,32
746 #"
747 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
748 [(set (match_dup 0)
749 (zero_extend:EXTSI (match_dup 1)))
750 (set (match_dup 2)
751 (compare:CC (match_dup 0)
752 (const_int 0)))]
753 ""
754 [(set_attr "type" "shift")
755 (set_attr "dot" "yes")
756 (set_attr "length" "4,8")])
759 (define_insn "extendqi<mode>2"
760 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
761 (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
762 ""
763 "extsb %0,%1"
764 [(set_attr "type" "exts")])
766 (define_insn_and_split "*extendqi<mode>2_dot"
767 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
768 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
769 (const_int 0)))
770 (clobber (match_scratch:EXTQI 0 "=r,r"))]
771 "rs6000_gen_cell_microcode"
772 "@
773 extsb. %0,%1
774 #"
775 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
776 [(set (match_dup 0)
777 (sign_extend:EXTQI (match_dup 1)))
778 (set (match_dup 2)
779 (compare:CC (match_dup 0)
780 (const_int 0)))]
781 ""
782 [(set_attr "type" "exts")
783 (set_attr "dot" "yes")
784 (set_attr "length" "4,8")])
786 (define_insn_and_split "*extendqi<mode>2_dot2"
787 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
788 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
789 (const_int 0)))
790 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
791 (sign_extend:EXTQI (match_dup 1)))]
792 "rs6000_gen_cell_microcode"
793 "@
794 extsb. %0,%1
795 #"
796 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
797 [(set (match_dup 0)
798 (sign_extend:EXTQI (match_dup 1)))
799 (set (match_dup 2)
800 (compare:CC (match_dup 0)
801 (const_int 0)))]
802 ""
803 [(set_attr "type" "exts")
804 (set_attr "dot" "yes")
805 (set_attr "length" "4,8")])
808 (define_expand "extendhi<mode>2"
809 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "")
810 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "")))]
811 ""
812 "")
814 (define_insn "*extendhi<mode>2"
815 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
816 (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
817 "rs6000_gen_cell_microcode"
818 "@
819 lha%U1%X1 %0,%1
820 extsh %0,%1"
821 [(set_attr "type" "load,exts")
822 (set_attr "sign_extend" "yes")])
824 (define_insn "*extendhi<mode>2_noload"
825 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
826 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
827 "!rs6000_gen_cell_microcode"
828 "extsh %0,%1"
829 [(set_attr "type" "exts")])
831 (define_insn_and_split "*extendhi<mode>2_dot"
832 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
833 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
834 (const_int 0)))
835 (clobber (match_scratch:EXTHI 0 "=r,r"))]
836 "rs6000_gen_cell_microcode"
837 "@
838 extsh. %0,%1
839 #"
840 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
841 [(set (match_dup 0)
842 (sign_extend:EXTHI (match_dup 1)))
843 (set (match_dup 2)
844 (compare:CC (match_dup 0)
845 (const_int 0)))]
846 ""
847 [(set_attr "type" "exts")
848 (set_attr "dot" "yes")
849 (set_attr "length" "4,8")])
851 (define_insn_and_split "*extendhi<mode>2_dot2"
852 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
853 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
854 (const_int 0)))
855 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
856 (sign_extend:EXTHI (match_dup 1)))]
857 "rs6000_gen_cell_microcode"
858 "@
859 extsh. %0,%1
860 #"
861 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
862 [(set (match_dup 0)
863 (sign_extend:EXTHI (match_dup 1)))
864 (set (match_dup 2)
865 (compare:CC (match_dup 0)
866 (const_int 0)))]
867 ""
868 [(set_attr "type" "exts")
869 (set_attr "dot" "yes")
870 (set_attr "length" "4,8")])
873 (define_insn "extendsi<mode>2"
874 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
875 (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
876 ""
877 "@
878 lwa%U1%X1 %0,%1
879 extsw %0,%1
880 mtvsrwa %x0,%1
881 lfiwax %0,%y1
882 lxsiwax %x0,%y1"
883 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
884 (set_attr "sign_extend" "yes")])
886 (define_insn_and_split "*extendsi<mode>2_dot"
887 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
888 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
889 (const_int 0)))
890 (clobber (match_scratch:EXTSI 0 "=r,r"))]
891 "rs6000_gen_cell_microcode"
892 "@
893 extsw. %0,%1
894 #"
895 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
896 [(set (match_dup 0)
897 (sign_extend:EXTSI (match_dup 1)))
898 (set (match_dup 2)
899 (compare:CC (match_dup 0)
900 (const_int 0)))]
901 ""
902 [(set_attr "type" "exts")
903 (set_attr "dot" "yes")
904 (set_attr "length" "4,8")])
906 (define_insn_and_split "*extendsi<mode>2_dot2"
907 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
908 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
909 (const_int 0)))
910 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
911 (sign_extend:EXTSI (match_dup 1)))]
912 "rs6000_gen_cell_microcode"
913 "@
914 extsw. %0,%1
915 #"
916 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
917 [(set (match_dup 0)
918 (sign_extend:EXTSI (match_dup 1)))
919 (set (match_dup 2)
920 (compare:CC (match_dup 0)
921 (const_int 0)))]
922 ""
923 [(set_attr "type" "exts")
924 (set_attr "dot" "yes")
925 (set_attr "length" "4,8")])
926 \f
927 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
929 (define_insn "*macchwc"
930 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
931 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
932 (match_operand:SI 2 "gpc_reg_operand" "r")
933 (const_int 16))
934 (sign_extend:SI
935 (match_operand:HI 1 "gpc_reg_operand" "r")))
936 (match_operand:SI 4 "gpc_reg_operand" "0"))
937 (const_int 0)))
938 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
939 (plus:SI (mult:SI (ashiftrt:SI
940 (match_dup 2)
941 (const_int 16))
942 (sign_extend:SI
943 (match_dup 1)))
944 (match_dup 4)))]
945 "TARGET_MULHW"
946 "macchw. %0,%1,%2"
947 [(set_attr "type" "halfmul")])
949 (define_insn "*macchw"
950 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
951 (plus:SI (mult:SI (ashiftrt:SI
952 (match_operand:SI 2 "gpc_reg_operand" "r")
953 (const_int 16))
954 (sign_extend:SI
955 (match_operand:HI 1 "gpc_reg_operand" "r")))
956 (match_operand:SI 3 "gpc_reg_operand" "0")))]
957 "TARGET_MULHW"
958 "macchw %0,%1,%2"
959 [(set_attr "type" "halfmul")])
961 (define_insn "*macchwuc"
962 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
963 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
964 (match_operand:SI 2 "gpc_reg_operand" "r")
965 (const_int 16))
966 (zero_extend:SI
967 (match_operand:HI 1 "gpc_reg_operand" "r")))
968 (match_operand:SI 4 "gpc_reg_operand" "0"))
969 (const_int 0)))
970 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
971 (plus:SI (mult:SI (lshiftrt:SI
972 (match_dup 2)
973 (const_int 16))
974 (zero_extend:SI
975 (match_dup 1)))
976 (match_dup 4)))]
977 "TARGET_MULHW"
978 "macchwu. %0,%1,%2"
979 [(set_attr "type" "halfmul")])
981 (define_insn "*macchwu"
982 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
983 (plus:SI (mult:SI (lshiftrt:SI
984 (match_operand:SI 2 "gpc_reg_operand" "r")
985 (const_int 16))
986 (zero_extend:SI
987 (match_operand:HI 1 "gpc_reg_operand" "r")))
988 (match_operand:SI 3 "gpc_reg_operand" "0")))]
989 "TARGET_MULHW"
990 "macchwu %0,%1,%2"
991 [(set_attr "type" "halfmul")])
993 (define_insn "*machhwc"
994 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
995 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
996 (match_operand:SI 1 "gpc_reg_operand" "%r")
997 (const_int 16))
998 (ashiftrt:SI
999 (match_operand:SI 2 "gpc_reg_operand" "r")
1000 (const_int 16)))
1001 (match_operand:SI 4 "gpc_reg_operand" "0"))
1002 (const_int 0)))
1003 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1004 (plus:SI (mult:SI (ashiftrt:SI
1005 (match_dup 1)
1006 (const_int 16))
1007 (ashiftrt:SI
1008 (match_dup 2)
1009 (const_int 16)))
1010 (match_dup 4)))]
1011 "TARGET_MULHW"
1012 "machhw. %0,%1,%2"
1013 [(set_attr "type" "halfmul")])
1015 (define_insn "*machhw"
1016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1017 (plus:SI (mult:SI (ashiftrt:SI
1018 (match_operand:SI 1 "gpc_reg_operand" "%r")
1019 (const_int 16))
1020 (ashiftrt:SI
1021 (match_operand:SI 2 "gpc_reg_operand" "r")
1022 (const_int 16)))
1023 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1024 "TARGET_MULHW"
1025 "machhw %0,%1,%2"
1026 [(set_attr "type" "halfmul")])
1028 (define_insn "*machhwuc"
1029 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1030 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1031 (match_operand:SI 1 "gpc_reg_operand" "%r")
1032 (const_int 16))
1033 (lshiftrt:SI
1034 (match_operand:SI 2 "gpc_reg_operand" "r")
1035 (const_int 16)))
1036 (match_operand:SI 4 "gpc_reg_operand" "0"))
1037 (const_int 0)))
1038 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1039 (plus:SI (mult:SI (lshiftrt:SI
1040 (match_dup 1)
1041 (const_int 16))
1042 (lshiftrt:SI
1043 (match_dup 2)
1044 (const_int 16)))
1045 (match_dup 4)))]
1046 "TARGET_MULHW"
1047 "machhwu. %0,%1,%2"
1048 [(set_attr "type" "halfmul")])
1050 (define_insn "*machhwu"
1051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1052 (plus:SI (mult:SI (lshiftrt:SI
1053 (match_operand:SI 1 "gpc_reg_operand" "%r")
1054 (const_int 16))
1055 (lshiftrt:SI
1056 (match_operand:SI 2 "gpc_reg_operand" "r")
1057 (const_int 16)))
1058 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1059 "TARGET_MULHW"
1060 "machhwu %0,%1,%2"
1061 [(set_attr "type" "halfmul")])
1063 (define_insn "*maclhwc"
1064 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1065 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1066 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1067 (sign_extend:SI
1068 (match_operand:HI 2 "gpc_reg_operand" "r")))
1069 (match_operand:SI 4 "gpc_reg_operand" "0"))
1070 (const_int 0)))
1071 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1072 (plus:SI (mult:SI (sign_extend:SI
1073 (match_dup 1))
1074 (sign_extend:SI
1075 (match_dup 2)))
1076 (match_dup 4)))]
1077 "TARGET_MULHW"
1078 "maclhw. %0,%1,%2"
1079 [(set_attr "type" "halfmul")])
1081 (define_insn "*maclhw"
1082 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1083 (plus:SI (mult:SI (sign_extend:SI
1084 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1085 (sign_extend:SI
1086 (match_operand:HI 2 "gpc_reg_operand" "r")))
1087 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1088 "TARGET_MULHW"
1089 "maclhw %0,%1,%2"
1090 [(set_attr "type" "halfmul")])
1092 (define_insn "*maclhwuc"
1093 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1094 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1095 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1096 (zero_extend:SI
1097 (match_operand:HI 2 "gpc_reg_operand" "r")))
1098 (match_operand:SI 4 "gpc_reg_operand" "0"))
1099 (const_int 0)))
1100 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (plus:SI (mult:SI (zero_extend:SI
1102 (match_dup 1))
1103 (zero_extend:SI
1104 (match_dup 2)))
1105 (match_dup 4)))]
1106 "TARGET_MULHW"
1107 "maclhwu. %0,%1,%2"
1108 [(set_attr "type" "halfmul")])
1110 (define_insn "*maclhwu"
1111 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1112 (plus:SI (mult:SI (zero_extend:SI
1113 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1114 (zero_extend:SI
1115 (match_operand:HI 2 "gpc_reg_operand" "r")))
1116 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1117 "TARGET_MULHW"
1118 "maclhwu %0,%1,%2"
1119 [(set_attr "type" "halfmul")])
1121 (define_insn "*nmacchwc"
1122 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1123 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1124 (mult:SI (ashiftrt:SI
1125 (match_operand:SI 2 "gpc_reg_operand" "r")
1126 (const_int 16))
1127 (sign_extend:SI
1128 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1129 (const_int 0)))
1130 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1131 (minus:SI (match_dup 4)
1132 (mult:SI (ashiftrt:SI
1133 (match_dup 2)
1134 (const_int 16))
1135 (sign_extend:SI
1136 (match_dup 1)))))]
1137 "TARGET_MULHW"
1138 "nmacchw. %0,%1,%2"
1139 [(set_attr "type" "halfmul")])
1141 (define_insn "*nmacchw"
1142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1143 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1144 (mult:SI (ashiftrt:SI
1145 (match_operand:SI 2 "gpc_reg_operand" "r")
1146 (const_int 16))
1147 (sign_extend:SI
1148 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1149 "TARGET_MULHW"
1150 "nmacchw %0,%1,%2"
1151 [(set_attr "type" "halfmul")])
1153 (define_insn "*nmachhwc"
1154 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1155 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1156 (mult:SI (ashiftrt:SI
1157 (match_operand:SI 1 "gpc_reg_operand" "%r")
1158 (const_int 16))
1159 (ashiftrt:SI
1160 (match_operand:SI 2 "gpc_reg_operand" "r")
1161 (const_int 16))))
1162 (const_int 0)))
1163 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1164 (minus:SI (match_dup 4)
1165 (mult:SI (ashiftrt:SI
1166 (match_dup 1)
1167 (const_int 16))
1168 (ashiftrt:SI
1169 (match_dup 2)
1170 (const_int 16)))))]
1171 "TARGET_MULHW"
1172 "nmachhw. %0,%1,%2"
1173 [(set_attr "type" "halfmul")])
1175 (define_insn "*nmachhw"
1176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1177 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1178 (mult:SI (ashiftrt:SI
1179 (match_operand:SI 1 "gpc_reg_operand" "%r")
1180 (const_int 16))
1181 (ashiftrt:SI
1182 (match_operand:SI 2 "gpc_reg_operand" "r")
1183 (const_int 16)))))]
1184 "TARGET_MULHW"
1185 "nmachhw %0,%1,%2"
1186 [(set_attr "type" "halfmul")])
1188 (define_insn "*nmaclhwc"
1189 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1190 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1191 (mult:SI (sign_extend:SI
1192 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1193 (sign_extend:SI
1194 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1195 (const_int 0)))
1196 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1197 (minus:SI (match_dup 4)
1198 (mult:SI (sign_extend:SI
1199 (match_dup 1))
1200 (sign_extend:SI
1201 (match_dup 2)))))]
1202 "TARGET_MULHW"
1203 "nmaclhw. %0,%1,%2"
1204 [(set_attr "type" "halfmul")])
1206 (define_insn "*nmaclhw"
1207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1208 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1209 (mult:SI (sign_extend:SI
1210 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1211 (sign_extend:SI
1212 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1213 "TARGET_MULHW"
1214 "nmaclhw %0,%1,%2"
1215 [(set_attr "type" "halfmul")])
1217 (define_insn "*mulchwc"
1218 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1219 (compare:CC (mult:SI (ashiftrt:SI
1220 (match_operand:SI 2 "gpc_reg_operand" "r")
1221 (const_int 16))
1222 (sign_extend:SI
1223 (match_operand:HI 1 "gpc_reg_operand" "r")))
1224 (const_int 0)))
1225 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1226 (mult:SI (ashiftrt:SI
1227 (match_dup 2)
1228 (const_int 16))
1229 (sign_extend:SI
1230 (match_dup 1))))]
1231 "TARGET_MULHW"
1232 "mulchw. %0,%1,%2"
1233 [(set_attr "type" "halfmul")])
1235 (define_insn "*mulchw"
1236 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1237 (mult:SI (ashiftrt:SI
1238 (match_operand:SI 2 "gpc_reg_operand" "r")
1239 (const_int 16))
1240 (sign_extend:SI
1241 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1242 "TARGET_MULHW"
1243 "mulchw %0,%1,%2"
1244 [(set_attr "type" "halfmul")])
1246 (define_insn "*mulchwuc"
1247 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1248 (compare:CC (mult:SI (lshiftrt:SI
1249 (match_operand:SI 2 "gpc_reg_operand" "r")
1250 (const_int 16))
1251 (zero_extend:SI
1252 (match_operand:HI 1 "gpc_reg_operand" "r")))
1253 (const_int 0)))
1254 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1255 (mult:SI (lshiftrt:SI
1256 (match_dup 2)
1257 (const_int 16))
1258 (zero_extend:SI
1259 (match_dup 1))))]
1260 "TARGET_MULHW"
1261 "mulchwu. %0,%1,%2"
1262 [(set_attr "type" "halfmul")])
1264 (define_insn "*mulchwu"
1265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1266 (mult:SI (lshiftrt:SI
1267 (match_operand:SI 2 "gpc_reg_operand" "r")
1268 (const_int 16))
1269 (zero_extend:SI
1270 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1271 "TARGET_MULHW"
1272 "mulchwu %0,%1,%2"
1273 [(set_attr "type" "halfmul")])
1275 (define_insn "*mulhhwc"
1276 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1277 (compare:CC (mult:SI (ashiftrt:SI
1278 (match_operand:SI 1 "gpc_reg_operand" "%r")
1279 (const_int 16))
1280 (ashiftrt:SI
1281 (match_operand:SI 2 "gpc_reg_operand" "r")
1282 (const_int 16)))
1283 (const_int 0)))
1284 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1285 (mult:SI (ashiftrt:SI
1286 (match_dup 1)
1287 (const_int 16))
1288 (ashiftrt:SI
1289 (match_dup 2)
1290 (const_int 16))))]
1291 "TARGET_MULHW"
1292 "mulhhw. %0,%1,%2"
1293 [(set_attr "type" "halfmul")])
1295 (define_insn "*mulhhw"
1296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1297 (mult:SI (ashiftrt:SI
1298 (match_operand:SI 1 "gpc_reg_operand" "%r")
1299 (const_int 16))
1300 (ashiftrt:SI
1301 (match_operand:SI 2 "gpc_reg_operand" "r")
1302 (const_int 16))))]
1303 "TARGET_MULHW"
1304 "mulhhw %0,%1,%2"
1305 [(set_attr "type" "halfmul")])
1307 (define_insn "*mulhhwuc"
1308 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1309 (compare:CC (mult:SI (lshiftrt:SI
1310 (match_operand:SI 1 "gpc_reg_operand" "%r")
1311 (const_int 16))
1312 (lshiftrt:SI
1313 (match_operand:SI 2 "gpc_reg_operand" "r")
1314 (const_int 16)))
1315 (const_int 0)))
1316 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1317 (mult:SI (lshiftrt:SI
1318 (match_dup 1)
1319 (const_int 16))
1320 (lshiftrt:SI
1321 (match_dup 2)
1322 (const_int 16))))]
1323 "TARGET_MULHW"
1324 "mulhhwu. %0,%1,%2"
1325 [(set_attr "type" "halfmul")])
1327 (define_insn "*mulhhwu"
1328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1329 (mult:SI (lshiftrt:SI
1330 (match_operand:SI 1 "gpc_reg_operand" "%r")
1331 (const_int 16))
1332 (lshiftrt:SI
1333 (match_operand:SI 2 "gpc_reg_operand" "r")
1334 (const_int 16))))]
1335 "TARGET_MULHW"
1336 "mulhhwu %0,%1,%2"
1337 [(set_attr "type" "halfmul")])
1339 (define_insn "*mullhwc"
1340 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1341 (compare:CC (mult:SI (sign_extend:SI
1342 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1343 (sign_extend:SI
1344 (match_operand:HI 2 "gpc_reg_operand" "r")))
1345 (const_int 0)))
1346 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1347 (mult:SI (sign_extend:SI
1348 (match_dup 1))
1349 (sign_extend:SI
1350 (match_dup 2))))]
1351 "TARGET_MULHW"
1352 "mullhw. %0,%1,%2"
1353 [(set_attr "type" "halfmul")])
1355 (define_insn "*mullhw"
1356 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1357 (mult:SI (sign_extend:SI
1358 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1359 (sign_extend:SI
1360 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1361 "TARGET_MULHW"
1362 "mullhw %0,%1,%2"
1363 [(set_attr "type" "halfmul")])
1365 (define_insn "*mullhwuc"
1366 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1367 (compare:CC (mult:SI (zero_extend:SI
1368 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1369 (zero_extend:SI
1370 (match_operand:HI 2 "gpc_reg_operand" "r")))
1371 (const_int 0)))
1372 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1373 (mult:SI (zero_extend:SI
1374 (match_dup 1))
1375 (zero_extend:SI
1376 (match_dup 2))))]
1377 "TARGET_MULHW"
1378 "mullhwu. %0,%1,%2"
1379 [(set_attr "type" "halfmul")])
1381 (define_insn "*mullhwu"
1382 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1383 (mult:SI (zero_extend:SI
1384 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1385 (zero_extend:SI
1386 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1387 "TARGET_MULHW"
1388 "mullhwu %0,%1,%2"
1389 [(set_attr "type" "halfmul")])
1390 \f
1391 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1392 (define_insn "dlmzb"
1393 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1394 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1395 (match_operand:SI 2 "gpc_reg_operand" "r")]
1396 UNSPEC_DLMZB_CR))
1397 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1398 (unspec:SI [(match_dup 1)
1399 (match_dup 2)]
1400 UNSPEC_DLMZB))]
1401 "TARGET_DLMZB"
1402 "dlmzb. %0,%1,%2")
1404 (define_expand "strlensi"
1405 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1406 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1407 (match_operand:QI 2 "const_int_operand" "")
1408 (match_operand 3 "const_int_operand" "")]
1409 UNSPEC_DLMZB_STRLEN))
1410 (clobber (match_scratch:CC 4 "=x"))]
1411 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1412 {
1413 rtx result = operands[0];
1414 rtx src = operands[1];
1415 rtx search_char = operands[2];
1416 rtx align = operands[3];
1417 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1418 rtx loop_label, end_label, mem, cr0, cond;
1419 if (search_char != const0_rtx
1420 || GET_CODE (align) != CONST_INT
1421 || INTVAL (align) < 8)
1422 FAIL;
1423 word1 = gen_reg_rtx (SImode);
1424 word2 = gen_reg_rtx (SImode);
1425 scratch_dlmzb = gen_reg_rtx (SImode);
1426 scratch_string = gen_reg_rtx (Pmode);
1427 loop_label = gen_label_rtx ();
1428 end_label = gen_label_rtx ();
1429 addr = force_reg (Pmode, XEXP (src, 0));
1430 emit_move_insn (scratch_string, addr);
1431 emit_label (loop_label);
1432 mem = change_address (src, SImode, scratch_string);
1433 emit_move_insn (word1, mem);
1434 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1435 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1436 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1437 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1438 emit_jump_insn (gen_rtx_SET (VOIDmode,
1439 pc_rtx,
1440 gen_rtx_IF_THEN_ELSE (VOIDmode,
1441 cond,
1442 gen_rtx_LABEL_REF
1443 (VOIDmode,
1444 end_label),
1445 pc_rtx)));
1446 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1447 emit_jump_insn (gen_rtx_SET (VOIDmode,
1448 pc_rtx,
1449 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1450 emit_barrier ();
1451 emit_label (end_label);
1452 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1453 emit_insn (gen_subsi3 (result, scratch_string, addr));
1454 emit_insn (gen_addsi3 (result, result, constm1_rtx));
1455 DONE;
1456 })
1457 \f
1458 ;; Fixed-point arithmetic insns.
1460 (define_expand "add<mode>3"
1461 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1462 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1463 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1464 ""
1465 {
1466 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1467 {
1468 if (non_short_cint_operand (operands[2], DImode))
1469 FAIL;
1470 }
1471 else if (GET_CODE (operands[2]) == CONST_INT
1472 && ! add_operand (operands[2], <MODE>mode))
1473 {
1474 rtx tmp = ((!can_create_pseudo_p ()
1475 || rtx_equal_p (operands[0], operands[1]))
1476 ? operands[0] : gen_reg_rtx (<MODE>mode));
1478 HOST_WIDE_INT val = INTVAL (operands[2]);
1479 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1480 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1482 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1483 FAIL;
1485 /* The ordering here is important for the prolog expander.
1486 When space is allocated from the stack, adding 'low' first may
1487 produce a temporary deallocation (which would be bad). */
1488 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1489 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1490 DONE;
1491 }
1492 })
1494 ;; Discourage ai/addic because of carry but provide it in an alternative
1495 ;; allowing register zero as source.
1496 (define_insn "*add<mode>3_internal1"
1497 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1498 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1499 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1500 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1501 "@
1502 add %0,%1,%2
1503 addi %0,%1,%2
1504 addic %0,%1,%2
1505 addis %0,%1,%v2"
1506 [(set_attr "type" "add")])
1508 (define_insn "addsi3_high"
1509 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1510 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1511 (high:SI (match_operand 2 "" ""))))]
1512 "TARGET_MACHO && !TARGET_64BIT"
1513 "addis %0,%1,ha16(%2)"
1514 [(set_attr "type" "add")])
1516 (define_insn "*add<mode>3_internal2"
1517 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1518 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1519 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1520 (const_int 0)))
1521 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1522 ""
1523 "@
1524 add. %3,%1,%2
1525 addic. %3,%1,%2
1526 #
1527 #"
1528 [(set_attr "type" "add,compare,compare,compare")
1529 (set_attr "dot" "yes")
1530 (set_attr "length" "4,4,8,8")])
1532 (define_split
1533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1534 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1535 (match_operand:GPR 2 "reg_or_short_operand" ""))
1536 (const_int 0)))
1537 (clobber (match_scratch:GPR 3 ""))]
1538 "reload_completed"
1539 [(set (match_dup 3)
1540 (plus:GPR (match_dup 1)
1541 (match_dup 2)))
1542 (set (match_dup 0)
1543 (compare:CC (match_dup 3)
1544 (const_int 0)))]
1545 "")
1547 (define_insn "*add<mode>3_internal3"
1548 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1549 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1550 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1551 (const_int 0)))
1552 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1553 (plus:P (match_dup 1)
1554 (match_dup 2)))]
1555 ""
1556 "@
1557 add. %0,%1,%2
1558 addic. %0,%1,%2
1559 #
1560 #"
1561 [(set_attr "type" "add,compare,compare,compare")
1562 (set_attr "dot" "yes")
1563 (set_attr "length" "4,4,8,8")])
1565 (define_split
1566 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1567 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1568 (match_operand:P 2 "reg_or_short_operand" ""))
1569 (const_int 0)))
1570 (set (match_operand:P 0 "gpc_reg_operand" "")
1571 (plus:P (match_dup 1) (match_dup 2)))]
1572 "reload_completed"
1573 [(set (match_dup 0)
1574 (plus:P (match_dup 1)
1575 (match_dup 2)))
1576 (set (match_dup 3)
1577 (compare:CC (match_dup 0)
1578 (const_int 0)))]
1579 "")
1581 ;; Split an add that we can't do in one insn into two insns, each of which
1582 ;; does one 16-bit part. This is used by combine. Note that the low-order
1583 ;; add should be last in case the result gets used in an address.
1585 (define_split
1586 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1587 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1588 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1589 ""
1590 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1591 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1592 {
1593 HOST_WIDE_INT val = INTVAL (operands[2]);
1594 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1595 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1597 operands[4] = GEN_INT (low);
1598 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1599 operands[3] = GEN_INT (rest);
1600 else if (can_create_pseudo_p ())
1601 {
1602 operands[3] = gen_reg_rtx (DImode);
1603 emit_move_insn (operands[3], operands[2]);
1604 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1605 DONE;
1606 }
1607 else
1608 FAIL;
1609 })
1611 (define_expand "one_cmpl<mode>2"
1612 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1613 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1614 ""
1615 {
1616 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1617 {
1618 rs6000_split_logical (operands, NOT, false, false, false);
1619 DONE;
1620 }
1621 })
1623 (define_insn "*one_cmpl<mode>2"
1624 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1625 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1626 ""
1627 "not %0,%1")
1629 (define_insn_and_split "*one_cmpl<mode>2_dot"
1630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1631 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1632 (const_int 0)))
1633 (clobber (match_scratch:GPR 0 "=r,r"))]
1634 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1635 "@
1636 not. %0,%1
1637 #"
1638 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1639 [(set (match_dup 0)
1640 (not:GPR (match_dup 1)))
1641 (set (match_dup 2)
1642 (compare:CC (match_dup 0)
1643 (const_int 0)))]
1644 ""
1645 [(set_attr "type" "logical")
1646 (set_attr "dot" "yes")
1647 (set_attr "length" "4,8")])
1649 (define_insn_and_split "*one_cmpl<mode>2_dot2"
1650 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1651 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1652 (const_int 0)))
1653 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1654 (not:GPR (match_dup 1)))]
1655 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1656 "@
1657 not. %0,%1
1658 #"
1659 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1660 [(set (match_dup 0)
1661 (not:GPR (match_dup 1)))
1662 (set (match_dup 2)
1663 (compare:CC (match_dup 0)
1664 (const_int 0)))]
1665 ""
1666 [(set_attr "type" "logical")
1667 (set_attr "dot" "yes")
1668 (set_attr "length" "4,8")])
1671 (define_expand "sub<mode>3"
1672 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1673 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1674 (match_operand:SDI 2 "gpc_reg_operand" "")))]
1675 ""
1676 {
1677 if (short_cint_operand (operands[1], <MODE>mode)
1678 && !(<MODE>mode == DImode && !TARGET_POWERPC64))
1679 {
1680 emit_insn (gen_subf<mode>3_imm (operands[0], operands[2], operands[1]));
1681 DONE;
1682 }
1683 })
1685 (define_insn "*subf<mode>3"
1686 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1687 (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r")
1688 (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1689 ""
1690 "subf %0,%1,%2"
1691 [(set_attr "type" "add")])
1693 (define_insn_and_split "*subf<mode>3_dot"
1694 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1695 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
1696 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1697 (const_int 0)))
1698 (clobber (match_scratch:GPR 0 "=r,r"))]
1699 "<MODE>mode == Pmode"
1700 "@
1701 subf. %0,%1,%2
1702 #"
1703 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1704 [(set (match_dup 0)
1705 (minus:GPR (match_dup 2)
1706 (match_dup 1)))
1707 (set (match_dup 3)
1708 (compare:CC (match_dup 0)
1709 (const_int 0)))]
1710 ""
1711 [(set_attr "type" "add")
1712 (set_attr "dot" "yes")
1713 (set_attr "length" "4,8")])
1715 (define_insn_and_split "*subf<mode>3_dot2"
1716 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1717 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
1718 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1719 (const_int 0)))
1720 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1721 (minus:GPR (match_dup 2)
1722 (match_dup 1)))]
1723 "<MODE>mode == Pmode"
1724 "@
1725 subf. %0,%1,%2
1726 #"
1727 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1728 [(set (match_dup 0)
1729 (minus:GPR (match_dup 2)
1730 (match_dup 1)))
1731 (set (match_dup 3)
1732 (compare:CC (match_dup 0)
1733 (const_int 0)))]
1734 ""
1735 [(set_attr "type" "add")
1736 (set_attr "dot" "yes")
1737 (set_attr "length" "4,8")])
1739 (define_insn "subf<mode>3_imm"
1740 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1741 (minus:GPR (match_operand:GPR 2 "short_cint_operand" "I")
1742 (match_operand:GPR 1 "gpc_reg_operand" "r")))
1743 (clobber (reg:GPR CA_REGNO))]
1744 ""
1745 "subfic %0,%1,%2"
1746 [(set_attr "type" "add")])
1749 (define_expand "neg<mode>2"
1750 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1751 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1752 ""
1753 "")
1755 (define_insn "*neg<mode>2"
1756 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1757 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1758 ""
1759 "neg %0,%1"
1760 [(set_attr "type" "add")])
1762 (define_insn_and_split "*neg<mode>2_dot"
1763 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1764 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1765 (const_int 0)))
1766 (clobber (match_scratch:GPR 0 "=r,r"))]
1767 "<MODE>mode == Pmode"
1768 "@
1769 neg. %0,%1
1770 #"
1771 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1772 [(set (match_dup 0)
1773 (neg:GPR (match_dup 1)))
1774 (set (match_dup 2)
1775 (compare:CC (match_dup 0)
1776 (const_int 0)))]
1777 ""
1778 [(set_attr "type" "add")
1779 (set_attr "dot" "yes")
1780 (set_attr "length" "4,8")])
1782 (define_insn_and_split "*neg<mode>2_dot2"
1783 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1784 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1785 (const_int 0)))
1786 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1787 (neg:GPR (match_dup 1)))]
1788 "<MODE>mode == Pmode"
1789 "@
1790 neg. %0,%1
1791 #"
1792 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1793 [(set (match_dup 0)
1794 (neg:GPR (match_dup 1)))
1795 (set (match_dup 2)
1796 (compare:CC (match_dup 0)
1797 (const_int 0)))]
1798 ""
1799 [(set_attr "type" "add")
1800 (set_attr "dot" "yes")
1801 (set_attr "length" "4,8")])
1804 (define_insn "clz<mode>2"
1805 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1806 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1807 ""
1808 "cntlz<wd> %0,%1"
1809 [(set_attr "type" "cntlz")])
1811 (define_expand "ctz<mode>2"
1812 [(set (match_dup 2)
1813 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1814 (set (match_dup 3)
1815 (and:GPR (match_dup 1)
1816 (match_dup 2)))
1817 (set (match_dup 4)
1818 (clz:GPR (match_dup 3)))
1819 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1820 (minus:GPR (match_dup 5)
1821 (match_dup 4)))
1822 (clobber (reg:GPR CA_REGNO))])]
1823 ""
1824 {
1825 operands[2] = gen_reg_rtx (<MODE>mode);
1826 operands[3] = gen_reg_rtx (<MODE>mode);
1827 operands[4] = gen_reg_rtx (<MODE>mode);
1828 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1829 })
1831 (define_expand "ffs<mode>2"
1832 [(set (match_dup 2)
1833 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1834 (set (match_dup 3)
1835 (and:GPR (match_dup 1)
1836 (match_dup 2)))
1837 (set (match_dup 4)
1838 (clz:GPR (match_dup 3)))
1839 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1840 (minus:GPR (match_dup 5)
1841 (match_dup 4)))
1842 (clobber (reg:GPR CA_REGNO))])]
1843 ""
1844 {
1845 operands[2] = gen_reg_rtx (<MODE>mode);
1846 operands[3] = gen_reg_rtx (<MODE>mode);
1847 operands[4] = gen_reg_rtx (<MODE>mode);
1848 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1849 })
1852 (define_expand "popcount<mode>2"
1853 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1854 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1855 "TARGET_POPCNTB || TARGET_POPCNTD"
1856 {
1857 rs6000_emit_popcount (operands[0], operands[1]);
1858 DONE;
1859 })
1861 (define_insn "popcntb<mode>2"
1862 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1863 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1864 UNSPEC_POPCNTB))]
1865 "TARGET_POPCNTB"
1866 "popcntb %0,%1"
1867 [(set_attr "type" "popcnt")])
1869 (define_insn "popcntd<mode>2"
1870 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1871 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1872 "TARGET_POPCNTD"
1873 "popcnt<wd> %0,%1"
1874 [(set_attr "type" "popcnt")])
1877 (define_expand "parity<mode>2"
1878 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1879 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1880 "TARGET_POPCNTB"
1881 {
1882 rs6000_emit_parity (operands[0], operands[1]);
1883 DONE;
1884 })
1886 (define_insn "parity<mode>2_cmpb"
1887 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1888 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
1889 "TARGET_CMPB && TARGET_POPCNTB"
1890 "prty<wd> %0,%1"
1891 [(set_attr "type" "popcnt")])
1894 ;; Since the hardware zeros the upper part of the register, save generating the
1895 ;; AND immediate if we are converting to unsigned
1896 (define_insn "*bswaphi2_extenddi"
1897 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1898 (zero_extend:DI
1899 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1900 "TARGET_POWERPC64"
1901 "lhbrx %0,%y1"
1902 [(set_attr "length" "4")
1903 (set_attr "type" "load")])
1905 (define_insn "*bswaphi2_extendsi"
1906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1907 (zero_extend:SI
1908 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1909 ""
1910 "lhbrx %0,%y1"
1911 [(set_attr "length" "4")
1912 (set_attr "type" "load")])
1914 (define_expand "bswaphi2"
1915 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1916 (bswap:HI
1917 (match_operand:HI 1 "reg_or_mem_operand" "")))
1918 (clobber (match_scratch:SI 2 ""))])]
1919 ""
1920 {
1921 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1922 operands[1] = force_reg (HImode, operands[1]);
1923 })
1925 (define_insn "bswaphi2_internal"
1926 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
1927 (bswap:HI
1928 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
1929 (clobber (match_scratch:SI 2 "=X,X,&r"))]
1930 ""
1931 "@
1932 lhbrx %0,%y1
1933 sthbrx %1,%y0
1934 #"
1935 [(set_attr "length" "4,4,12")
1936 (set_attr "type" "load,store,*")])
1938 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
1939 ;; correct for -mlittle as well as -mbig.
1940 (define_split
1941 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1942 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
1943 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
1944 "reload_completed"
1945 [(set (match_dup 3)
1946 (zero_extract:SI (match_dup 4)
1947 (const_int 8)
1948 (const_int 16)))
1949 (set (match_dup 2)
1950 (and:SI (ashift:SI (match_dup 4)
1951 (const_int 8))
1952 (const_int 65280))) ;; 0xff00
1953 (set (match_dup 3)
1954 (ior:SI (match_dup 3)
1955 (match_dup 2)))]
1956 "
1957 {
1958 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
1959 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
1960 }")
1962 (define_insn "*bswapsi2_extenddi"
1963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1964 (zero_extend:DI
1965 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
1966 "TARGET_POWERPC64"
1967 "lwbrx %0,%y1"
1968 [(set_attr "length" "4")
1969 (set_attr "type" "load")])
1971 (define_expand "bswapsi2"
1972 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
1973 (bswap:SI
1974 (match_operand:SI 1 "reg_or_mem_operand" "")))]
1975 ""
1976 {
1977 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1978 operands[1] = force_reg (SImode, operands[1]);
1979 })
1981 (define_insn "*bswapsi2_internal"
1982 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
1983 (bswap:SI
1984 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
1985 ""
1986 "@
1987 lwbrx %0,%y1
1988 stwbrx %1,%y0
1989 #"
1990 [(set_attr "length" "4,4,12")
1991 (set_attr "type" "load,store,*")])
1993 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
1994 ;; zero_extract insns do not change for -mlittle.
1995 (define_split
1996 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1997 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1998 "reload_completed"
1999 [(set (match_dup 0)
2000 (rotate:SI (match_dup 1) (const_int 8)))
2001 (set (zero_extract:SI (match_dup 0)
2002 (const_int 8)
2003 (const_int 0))
2004 (match_dup 1))
2005 (set (zero_extract:SI (match_dup 0)
2006 (const_int 8)
2007 (const_int 16))
2008 (rotate:SI (match_dup 1)
2009 (const_int 16)))]
2010 "")
2012 (define_expand "bswapdi2"
2013 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2014 (bswap:DI
2015 (match_operand:DI 1 "reg_or_mem_operand" "")))
2016 (clobber (match_scratch:DI 2 ""))
2017 (clobber (match_scratch:DI 3 ""))
2018 (clobber (match_scratch:DI 4 ""))])]
2019 ""
2020 {
2021 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2022 operands[1] = force_reg (DImode, operands[1]);
2024 if (!TARGET_POWERPC64)
2025 {
2026 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2027 that uses 64-bit registers needs the same scratch registers as 64-bit
2028 mode. */
2029 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2030 DONE;
2031 }
2032 })
2034 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2035 (define_insn "*bswapdi2_ldbrx"
2036 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2037 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2038 (clobber (match_scratch:DI 2 "=X,X,&r"))
2039 (clobber (match_scratch:DI 3 "=X,X,&r"))
2040 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2041 "TARGET_POWERPC64 && TARGET_LDBRX
2042 && (REG_P (operands[0]) || REG_P (operands[1]))"
2043 "@
2044 ldbrx %0,%y1
2045 stdbrx %1,%y0
2046 #"
2047 [(set_attr "length" "4,4,36")
2048 (set_attr "type" "load,store,*")])
2050 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2051 (define_insn "*bswapdi2_64bit"
2052 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2053 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2054 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2055 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2056 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2057 "TARGET_POWERPC64 && !TARGET_LDBRX
2058 && (REG_P (operands[0]) || REG_P (operands[1]))
2059 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2060 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2061 "#"
2062 [(set_attr "length" "16,12,36")])
2064 (define_split
2065 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2066 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2067 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2068 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2069 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2070 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2071 [(const_int 0)]
2072 "
2073 {
2074 rtx dest = operands[0];
2075 rtx src = operands[1];
2076 rtx op2 = operands[2];
2077 rtx op3 = operands[3];
2078 rtx op4 = operands[4];
2079 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2080 BYTES_BIG_ENDIAN ? 4 : 0);
2081 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2082 BYTES_BIG_ENDIAN ? 4 : 0);
2083 rtx addr1;
2084 rtx addr2;
2085 rtx word_high;
2086 rtx word_low;
2088 addr1 = XEXP (src, 0);
2089 if (GET_CODE (addr1) == PLUS)
2090 {
2091 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2092 if (TARGET_AVOID_XFORM)
2093 {
2094 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2095 addr2 = op2;
2096 }
2097 else
2098 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2099 }
2100 else if (TARGET_AVOID_XFORM)
2101 {
2102 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2103 addr2 = op2;
2104 }
2105 else
2106 {
2107 emit_move_insn (op2, GEN_INT (4));
2108 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2109 }
2111 if (BYTES_BIG_ENDIAN)
2112 {
2113 word_high = change_address (src, SImode, addr1);
2114 word_low = change_address (src, SImode, addr2);
2115 }
2116 else
2117 {
2118 word_high = change_address (src, SImode, addr2);
2119 word_low = change_address (src, SImode, addr1);
2120 }
2122 emit_insn (gen_bswapsi2 (op3_32, word_low));
2123 emit_insn (gen_bswapsi2 (op4_32, word_high));
2124 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2125 emit_insn (gen_iordi3 (dest, dest, op4));
2126 DONE;
2127 }")
2129 (define_split
2130 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2131 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2132 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2133 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2134 (clobber (match_operand:DI 4 "" ""))]
2135 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2136 [(const_int 0)]
2137 "
2138 {
2139 rtx dest = operands[0];
2140 rtx src = operands[1];
2141 rtx op2 = operands[2];
2142 rtx op3 = operands[3];
2143 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2144 BYTES_BIG_ENDIAN ? 4 : 0);
2145 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2146 BYTES_BIG_ENDIAN ? 4 : 0);
2147 rtx addr1;
2148 rtx addr2;
2149 rtx word_high;
2150 rtx word_low;
2152 addr1 = XEXP (dest, 0);
2153 if (GET_CODE (addr1) == PLUS)
2154 {
2155 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2156 if (TARGET_AVOID_XFORM)
2157 {
2158 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2159 addr2 = op2;
2160 }
2161 else
2162 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2163 }
2164 else if (TARGET_AVOID_XFORM)
2165 {
2166 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2167 addr2 = op2;
2168 }
2169 else
2170 {
2171 emit_move_insn (op2, GEN_INT (4));
2172 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2173 }
2175 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2176 if (BYTES_BIG_ENDIAN)
2177 {
2178 word_high = change_address (dest, SImode, addr1);
2179 word_low = change_address (dest, SImode, addr2);
2180 }
2181 else
2182 {
2183 word_high = change_address (dest, SImode, addr2);
2184 word_low = change_address (dest, SImode, addr1);
2185 }
2186 emit_insn (gen_bswapsi2 (word_high, src_si));
2187 emit_insn (gen_bswapsi2 (word_low, op3_si));
2188 DONE;
2189 }")
2191 (define_split
2192 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2193 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2194 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2195 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2196 (clobber (match_operand:DI 4 "" ""))]
2197 "TARGET_POWERPC64 && reload_completed"
2198 [(const_int 0)]
2199 "
2200 {
2201 rtx dest = operands[0];
2202 rtx src = operands[1];
2203 rtx op2 = operands[2];
2204 rtx op3 = operands[3];
2205 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2206 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2207 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2208 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2209 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2211 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2212 emit_insn (gen_bswapsi2 (dest_si, src_si));
2213 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2214 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2215 emit_insn (gen_iordi3 (dest, dest, op3));
2216 DONE;
2217 }")
2219 (define_insn "bswapdi2_32bit"
2220 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2221 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2222 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2223 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2224 "#"
2225 [(set_attr "length" "16,12,36")])
2227 (define_split
2228 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2229 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2230 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2231 "!TARGET_POWERPC64 && reload_completed"
2232 [(const_int 0)]
2233 "
2234 {
2235 rtx dest = operands[0];
2236 rtx src = operands[1];
2237 rtx op2 = operands[2];
2238 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2239 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2240 rtx addr1;
2241 rtx addr2;
2242 rtx word1;
2243 rtx word2;
2245 addr1 = XEXP (src, 0);
2246 if (GET_CODE (addr1) == PLUS)
2247 {
2248 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2249 if (TARGET_AVOID_XFORM)
2250 {
2251 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2252 addr2 = op2;
2253 }
2254 else
2255 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2256 }
2257 else if (TARGET_AVOID_XFORM)
2258 {
2259 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2260 addr2 = op2;
2261 }
2262 else
2263 {
2264 emit_move_insn (op2, GEN_INT (4));
2265 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2266 }
2268 word1 = change_address (src, SImode, addr1);
2269 word2 = change_address (src, SImode, addr2);
2271 emit_insn (gen_bswapsi2 (dest2, word1));
2272 emit_insn (gen_bswapsi2 (dest1, word2));
2273 DONE;
2274 }")
2276 (define_split
2277 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2278 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2279 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2280 "!TARGET_POWERPC64 && reload_completed"
2281 [(const_int 0)]
2282 "
2283 {
2284 rtx dest = operands[0];
2285 rtx src = operands[1];
2286 rtx op2 = operands[2];
2287 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2288 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2289 rtx addr1;
2290 rtx addr2;
2291 rtx word1;
2292 rtx word2;
2294 addr1 = XEXP (dest, 0);
2295 if (GET_CODE (addr1) == PLUS)
2296 {
2297 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2298 if (TARGET_AVOID_XFORM)
2299 {
2300 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2301 addr2 = op2;
2302 }
2303 else
2304 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2305 }
2306 else if (TARGET_AVOID_XFORM)
2307 {
2308 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2309 addr2 = op2;
2310 }
2311 else
2312 {
2313 emit_move_insn (op2, GEN_INT (4));
2314 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2315 }
2317 word1 = change_address (dest, SImode, addr1);
2318 word2 = change_address (dest, SImode, addr2);
2320 emit_insn (gen_bswapsi2 (word2, src1));
2321 emit_insn (gen_bswapsi2 (word1, src2));
2322 DONE;
2323 }")
2325 (define_split
2326 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2327 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2328 (clobber (match_operand:SI 2 "" ""))]
2329 "!TARGET_POWERPC64 && reload_completed"
2330 [(const_int 0)]
2331 "
2332 {
2333 rtx dest = operands[0];
2334 rtx src = operands[1];
2335 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2336 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2337 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2338 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2340 emit_insn (gen_bswapsi2 (dest1, src2));
2341 emit_insn (gen_bswapsi2 (dest2, src1));
2342 DONE;
2343 }")
2346 (define_insn "mul<mode>3"
2347 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2348 (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2349 (match_operand:GPR 2 "reg_or_short_operand" "r,I")))]
2350 ""
2351 "@
2352 mull<wd> %0,%1,%2
2353 mulli %0,%1,%2"
2354 [(set_attr "type" "mul")
2355 (set (attr "size")
2356 (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
2357 (const_string "8")
2358 (match_operand:GPR 2 "short_cint_operand" "")
2359 (const_string "16")]
2360 (const_string "<bits>")))])
2362 (define_insn_and_split "*mul<mode>3_dot"
2363 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2364 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2365 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2366 (const_int 0)))
2367 (clobber (match_scratch:GPR 0 "=r,r"))]
2368 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2369 "@
2370 mull<wd>. %0,%1,%2
2371 #"
2372 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2373 [(set (match_dup 0)
2374 (mult:GPR (match_dup 1)
2375 (match_dup 2)))
2376 (set (match_dup 3)
2377 (compare:CC (match_dup 0)
2378 (const_int 0)))]
2379 ""
2380 [(set_attr "type" "mul")
2381 (set_attr "size" "<bits>")
2382 (set_attr "dot" "yes")
2383 (set_attr "length" "4,8")])
2385 (define_insn_and_split "*mul<mode>3_dot2"
2386 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2387 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2388 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2389 (const_int 0)))
2390 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2391 (mult:GPR (match_dup 1)
2392 (match_dup 2)))]
2393 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2394 "@
2395 mull<wd>. %0,%1,%2
2396 #"
2397 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2398 [(set (match_dup 0)
2399 (mult:GPR (match_dup 1)
2400 (match_dup 2)))
2401 (set (match_dup 3)
2402 (compare:CC (match_dup 0)
2403 (const_int 0)))]
2404 ""
2405 [(set_attr "type" "mul")
2406 (set_attr "size" "<bits>")
2407 (set_attr "dot" "yes")
2408 (set_attr "length" "4,8")])
2411 (define_expand "<su>mul<mode>3_highpart"
2412 [(set (match_operand:GPR 0 "gpc_reg_operand")
2413 (subreg:GPR
2414 (mult:<DMODE> (any_extend:<DMODE>
2415 (match_operand:GPR 1 "gpc_reg_operand"))
2416 (any_extend:<DMODE>
2417 (match_operand:GPR 2 "gpc_reg_operand")))
2418 0))]
2419 ""
2420 {
2421 if (<MODE>mode == SImode && TARGET_POWERPC64)
2422 {
2423 emit_insn (gen_<su>mulsi3_highpart_64 (operands[0], operands[1],
2424 operands[2]));
2425 DONE;
2426 }
2428 if (!WORDS_BIG_ENDIAN)
2429 {
2430 emit_insn (gen_<su>mul<mode>3_highpart_le (operands[0], operands[1],
2431 operands[2]));
2432 DONE;
2433 }
2434 })
2436 (define_insn "*<su>mul<mode>3_highpart"
2437 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2438 (subreg:GPR
2439 (mult:<DMODE> (any_extend:<DMODE>
2440 (match_operand:GPR 1 "gpc_reg_operand" "r"))
2441 (any_extend:<DMODE>
2442 (match_operand:GPR 2 "gpc_reg_operand" "r")))
2443 0))]
2444 "WORDS_BIG_ENDIAN && !(<MODE>mode == SImode && TARGET_POWERPC64)"
2445 "mulh<wd><u> %0,%1,%2"
2446 [(set_attr "type" "mul")
2447 (set_attr "size" "<bits>")])
2449 (define_insn "<su>mulsi3_highpart_le"
2450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2451 (subreg:SI
2452 (mult:DI (any_extend:DI
2453 (match_operand:SI 1 "gpc_reg_operand" "r"))
2454 (any_extend:DI
2455 (match_operand:SI 2 "gpc_reg_operand" "r")))
2456 4))]
2457 "!WORDS_BIG_ENDIAN && !TARGET_POWERPC64"
2458 "mulhw<u> %0,%1,%2"
2459 [(set_attr "type" "mul")])
2461 (define_insn "<su>muldi3_highpart_le"
2462 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2463 (subreg:DI
2464 (mult:TI (any_extend:TI
2465 (match_operand:DI 1 "gpc_reg_operand" "r"))
2466 (any_extend:TI
2467 (match_operand:DI 2 "gpc_reg_operand" "r")))
2468 8))]
2469 "!WORDS_BIG_ENDIAN && TARGET_POWERPC64"
2470 "mulhd<u> %0,%1,%2"
2471 [(set_attr "type" "mul")
2472 (set_attr "size" "64")])
2474 (define_insn "<su>mulsi3_highpart_64"
2475 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2476 (truncate:SI
2477 (lshiftrt:DI
2478 (mult:DI (any_extend:DI
2479 (match_operand:SI 1 "gpc_reg_operand" "r"))
2480 (any_extend:DI
2481 (match_operand:SI 2 "gpc_reg_operand" "r")))
2482 (const_int 32))))]
2483 "TARGET_POWERPC64"
2484 "mulhw<u> %0,%1,%2"
2485 [(set_attr "type" "mul")])
2487 (define_expand "<u>mul<mode><dmode>3"
2488 [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
2489 (mult:<DMODE> (any_extend:<DMODE>
2490 (match_operand:GPR 1 "gpc_reg_operand"))
2491 (any_extend:<DMODE>
2492 (match_operand:GPR 2 "gpc_reg_operand"))))]
2493 "!(<MODE>mode == SImode && TARGET_POWERPC64)"
2494 {
2495 rtx l = gen_reg_rtx (<MODE>mode);
2496 rtx h = gen_reg_rtx (<MODE>mode);
2497 emit_insn (gen_mul<mode>3 (l, operands[1], operands[2]));
2498 emit_insn (gen_<su>mul<mode>3_highpart (h, operands[1], operands[2]));
2499 emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
2500 emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
2501 DONE;
2502 })
2505 (define_insn "udiv<mode>3"
2506 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2507 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2508 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2509 ""
2510 "div<wd>u %0,%1,%2"
2511 [(set_attr "type" "div")
2512 (set_attr "size" "<bits>")])
2515 ;; For powers of two we can do sra[wd]i/addze for divide and then adjust for
2516 ;; modulus. If it isn't a power of two, force operands into register and do
2517 ;; a normal divide.
2518 (define_expand "div<mode>3"
2519 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2520 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2521 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2522 ""
2523 {
2524 if (CONST_INT_P (operands[2])
2525 && INTVAL (operands[2]) > 0
2526 && exact_log2 (INTVAL (operands[2])) >= 0)
2527 {
2528 emit_insn (gen_div<mode>3_sra (operands[0], operands[1], operands[2]));
2529 DONE;
2530 }
2532 operands[2] = force_reg (<MODE>mode, operands[2]);
2533 })
2535 (define_insn "*div<mode>3"
2536 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2537 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2538 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2539 ""
2540 "div<wd> %0,%1,%2"
2541 [(set_attr "type" "div")
2542 (set_attr "size" "<bits>")])
2544 (define_insn "div<mode>3_sra"
2545 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2546 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2547 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))
2548 (clobber (reg:GPR CA_REGNO))]
2549 ""
2550 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2551 [(set_attr "type" "two")
2552 (set_attr "length" "8")])
2554 (define_insn_and_split "*div<mode>3_sra_dot"
2555 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2556 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2557 (match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
2558 (const_int 0)))
2559 (clobber (match_scratch:GPR 0 "=r,r"))
2560 (clobber (reg:GPR CA_REGNO))]
2561 "<MODE>mode == Pmode"
2562 "@
2563 sra<wd>i %0,%1,%p2\;addze. %0,%0
2564 #"
2565 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2566 [(parallel [(set (match_dup 0)
2567 (div:GPR (match_dup 1)
2568 (match_dup 2)))
2569 (clobber (reg:GPR CA_REGNO))])
2570 (set (match_dup 3)
2571 (compare:CC (match_dup 0)
2572 (const_int 0)))]
2573 ""
2574 [(set_attr "type" "two")
2575 (set_attr "length" "8,12")
2576 (set_attr "cell_micro" "not")])
2578 (define_insn_and_split "*div<mode>3_sra_dot2"
2579 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2580 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2581 (match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
2582 (const_int 0)))
2583 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2584 (div:GPR (match_dup 1)
2585 (match_dup 2)))
2586 (clobber (reg:GPR CA_REGNO))]
2587 "<MODE>mode == Pmode"
2588 "@
2589 sra<wd>i %0,%1,%p2\;addze. %0,%0
2590 #"
2591 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2592 [(parallel [(set (match_dup 0)
2593 (div:GPR (match_dup 1)
2594 (match_dup 2)))
2595 (clobber (reg:GPR CA_REGNO))])
2596 (set (match_dup 3)
2597 (compare:CC (match_dup 0)
2598 (const_int 0)))]
2599 ""
2600 [(set_attr "type" "two")
2601 (set_attr "length" "8,12")
2602 (set_attr "cell_micro" "not")])
2604 (define_expand "mod<mode>3"
2605 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2606 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2607 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2608 ""
2609 {
2610 int i;
2611 rtx temp1;
2612 rtx temp2;
2614 if (GET_CODE (operands[2]) != CONST_INT
2615 || INTVAL (operands[2]) <= 0
2616 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2617 FAIL;
2619 temp1 = gen_reg_rtx (<MODE>mode);
2620 temp2 = gen_reg_rtx (<MODE>mode);
2622 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2623 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2624 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2625 DONE;
2626 })
2627 \f
2628 ;; Logical instructions
2629 ;; The logical instructions are mostly combined by using match_operator,
2630 ;; but the plain AND insns are somewhat different because there is no
2631 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2632 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2634 (define_expand "and<mode>3"
2635 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2636 (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2637 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2638 ""
2639 {
2640 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2641 {
2642 rs6000_split_logical (operands, AND, false, false, false);
2643 DONE;
2644 }
2646 if (logical_const_operand (operands[2], <MODE>mode)
2647 && !any_mask_operand (operands[2], <MODE>mode))
2648 {
2649 emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
2650 DONE;
2651 }
2653 if ((<MODE>mode == DImode && !and64_2_operand (operands[2], <MODE>mode))
2654 || (<MODE>mode != DImode && !and_operand (operands[2], <MODE>mode)))
2655 operands[2] = force_reg (<MODE>mode, operands[2]);
2656 })
2659 (define_insn "and<mode>3_imm"
2660 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2661 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
2662 (match_operand:GPR 2 "logical_const_operand" "n")))
2663 (clobber (match_scratch:CC 3 "=x"))]
2664 "rs6000_gen_cell_microcode
2665 && !any_mask_operand (operands[2], <MODE>mode)"
2666 "andi%e2. %0,%1,%u2"
2667 [(set_attr "type" "logical")
2668 (set_attr "dot" "yes")])
2670 (define_insn_and_split "*and<mode>3_imm_dot"
2671 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2672 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2673 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2674 (const_int 0)))
2675 (clobber (match_scratch:GPR 0 "=r,r"))
2676 (clobber (match_scratch:CC 4 "=X,x"))]
2677 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2678 && rs6000_gen_cell_microcode
2679 && !any_mask_operand (operands[2], <MODE>mode)"
2680 "@
2681 andi%e2. %0,%1,%u2
2682 #"
2683 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2684 [(parallel [(set (match_dup 0)
2685 (and:GPR (match_dup 1)
2686 (match_dup 2)))
2687 (clobber (match_dup 4))])
2688 (set (match_dup 3)
2689 (compare:CC (match_dup 0)
2690 (const_int 0)))]
2691 ""
2692 [(set_attr "type" "logical")
2693 (set_attr "dot" "yes")
2694 (set_attr "length" "4,8")])
2696 (define_insn_and_split "*and<mode>3_imm_dot2"
2697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2698 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2699 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2700 (const_int 0)))
2701 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2702 (and:GPR (match_dup 1)
2703 (match_dup 2)))
2704 (clobber (match_scratch:CC 4 "=X,x"))]
2705 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2706 && rs6000_gen_cell_microcode
2707 && !any_mask_operand (operands[2], <MODE>mode)"
2708 "@
2709 andi%e2. %0,%1,%u2
2710 #"
2711 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2712 [(parallel [(set (match_dup 0)
2713 (and:GPR (match_dup 1)
2714 (match_dup 2)))
2715 (clobber (match_dup 4))])
2716 (set (match_dup 3)
2717 (compare:CC (match_dup 0)
2718 (const_int 0)))]
2719 ""
2720 [(set_attr "type" "logical")
2721 (set_attr "dot" "yes")
2722 (set_attr "length" "4,8")])
2724 (define_insn_and_split "*and<mode>3_imm_mask_dot"
2725 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2726 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2727 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2728 (const_int 0)))
2729 (clobber (match_scratch:GPR 0 "=r,r"))]
2730 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2731 && rs6000_gen_cell_microcode
2732 && any_mask_operand (operands[2], <MODE>mode)"
2733 "@
2734 andi%e2. %0,%1,%u2
2735 #"
2736 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2737 [(set (match_dup 0)
2738 (and:GPR (match_dup 1)
2739 (match_dup 2)))
2740 (set (match_dup 3)
2741 (compare:CC (match_dup 0)
2742 (const_int 0)))]
2743 ""
2744 [(set_attr "type" "logical")
2745 (set_attr "dot" "yes")
2746 (set_attr "length" "4,8")])
2748 (define_insn_and_split "*and<mode>3_imm_mask_dot2"
2749 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2750 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2751 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2752 (const_int 0)))
2753 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2754 (and:GPR (match_dup 1)
2755 (match_dup 2)))]
2756 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2757 && rs6000_gen_cell_microcode
2758 && any_mask_operand (operands[2], <MODE>mode)"
2759 "@
2760 andi%e2. %0,%1,%u2
2761 #"
2762 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2763 [(set (match_dup 0)
2764 (and:GPR (match_dup 1)
2765 (match_dup 2)))
2766 (set (match_dup 3)
2767 (compare:CC (match_dup 0)
2768 (const_int 0)))]
2769 ""
2770 [(set_attr "type" "logical")
2771 (set_attr "dot" "yes")
2772 (set_attr "length" "4,8")])
2775 (define_insn "*and<mode>3_mask"
2776 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2777 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2778 (match_operand:GPR 2 "any_mask_operand" "S,T")))]
2779 ""
2780 "@
2781 rldic%B2 %0,%1,0,%S2
2782 rlwinm %0,%1,0,%m2,%M2"
2783 [(set_attr "type" "shift")])
2785 (define_insn_and_split "*and<mode>3_mask_dot"
2786 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2787 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2788 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2789 (const_int 0)))
2790 (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
2791 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2792 && rs6000_gen_cell_microcode
2793 && !logical_const_operand (operands[2], <MODE>mode)"
2794 "@
2795 rldic%B2. %0,%1,0,%S2
2796 rlwinm. %0,%1,0,%m2,%M2
2797 #
2798 #"
2799 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2800 [(set (match_dup 0)
2801 (and:GPR (match_dup 1)
2802 (match_dup 2)))
2803 (set (match_dup 3)
2804 (compare:CC (match_dup 0)
2805 (const_int 0)))]
2806 ""
2807 [(set_attr "type" "shift")
2808 (set_attr "dot" "yes")
2809 (set_attr "length" "4,4,8,8")])
2811 (define_insn_and_split "*and<mode>3_mask_dot2"
2812 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2813 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2814 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2815 (const_int 0)))
2816 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
2817 (and:GPR (match_dup 1)
2818 (match_dup 2)))]
2819 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2820 && rs6000_gen_cell_microcode
2821 && !logical_const_operand (operands[2], <MODE>mode)"
2822 "@
2823 rldic%B2. %0,%1,0,%S2
2824 rlwinm. %0,%1,0,%m2,%M2
2825 #
2826 #"
2827 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2828 [(set (match_dup 0)
2829 (and:GPR (match_dup 1)
2830 (match_dup 2)))
2831 (set (match_dup 3)
2832 (compare:CC (match_dup 0)
2833 (const_int 0)))]
2834 ""
2835 [(set_attr "type" "shift")
2836 (set_attr "dot" "yes")
2837 (set_attr "length" "4,4,8,8")])
2841 (define_insn "andsi3_internal0_nomc"
2842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2843 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2844 (match_operand:SI 2 "and_operand" "?r,T")))]
2845 "!rs6000_gen_cell_microcode"
2846 "@
2847 and %0,%1,%2
2848 rlwinm %0,%1,0,%m2,%M2"
2849 [(set_attr "type" "logical,shift")])
2852 ;; Handle the PowerPC64 rlwinm corner case
2854 (define_insn_and_split "*andsi3_internal6"
2855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2856 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2857 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2858 "TARGET_POWERPC64"
2859 "#"
2860 "TARGET_POWERPC64"
2861 [(set (match_dup 0)
2862 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2863 (match_dup 4)))
2864 (set (match_dup 0)
2865 (rotate:SI (match_dup 0) (match_dup 5)))]
2866 "
2867 {
2868 int mb = extract_MB (operands[2]);
2869 int me = extract_ME (operands[2]);
2870 operands[3] = GEN_INT (me + 1);
2871 operands[5] = GEN_INT (32 - (me + 1));
2872 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2873 }"
2874 [(set_attr "length" "8")])
2877 (define_expand "<code><mode>3"
2878 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2879 (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2880 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2881 ""
2882 {
2883 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2884 {
2885 rs6000_split_logical (operands, <CODE>, false, false, false);
2886 DONE;
2887 }
2889 if (non_logical_cint_operand (operands[2], <MODE>mode))
2890 {
2891 rtx tmp = ((!can_create_pseudo_p ()
2892 || rtx_equal_p (operands[0], operands[1]))
2893 ? operands[0] : gen_reg_rtx (<MODE>mode));
2895 HOST_WIDE_INT value = INTVAL (operands[2]);
2896 HOST_WIDE_INT lo = value & 0xffff;
2897 HOST_WIDE_INT hi = value - lo;
2899 emit_insn (gen_<code><mode>3 (tmp, operands[1], GEN_INT (hi)));
2900 emit_insn (gen_<code><mode>3 (operands[0], tmp, GEN_INT (lo)));
2901 DONE;
2902 }
2904 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
2905 operands[2] = force_reg (<MODE>mode, operands[2]);
2906 })
2908 (define_split
2909 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2910 (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2911 (match_operand:GPR 2 "non_logical_cint_operand" "")))]
2912 ""
2913 [(set (match_dup 3)
2914 (iorxor:GPR (match_dup 1)
2915 (match_dup 4)))
2916 (set (match_dup 0)
2917 (iorxor:GPR (match_dup 3)
2918 (match_dup 5)))]
2919 {
2920 operands[3] = ((!can_create_pseudo_p ()
2921 || rtx_equal_p (operands[0], operands[1]))
2922 ? operands[0] : gen_reg_rtx (<MODE>mode));
2924 HOST_WIDE_INT value = INTVAL (operands[2]);
2925 HOST_WIDE_INT lo = value & 0xffff;
2926 HOST_WIDE_INT hi = value - lo;
2928 operands[4] = GEN_INT (hi);
2929 operands[5] = GEN_INT (lo);
2930 })
2932 (define_insn "*bool<mode>3_imm"
2933 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2934 (match_operator:GPR 3 "boolean_or_operator"
2935 [(match_operand:GPR 1 "gpc_reg_operand" "%r")
2936 (match_operand:GPR 2 "logical_const_operand" "n")]))]
2937 ""
2938 "%q3i%e2 %0,%1,%u2"
2939 [(set_attr "type" "logical")])
2941 (define_insn "*bool<mode>3"
2942 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2943 (match_operator:GPR 3 "boolean_operator"
2944 [(match_operand:GPR 1 "gpc_reg_operand" "r")
2945 (match_operand:GPR 2 "gpc_reg_operand" "r")]))]
2946 ""
2947 "%q3 %0,%1,%2"
2948 [(set_attr "type" "logical")])
2950 (define_insn_and_split "*bool<mode>3_dot"
2951 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2952 (compare:CC (match_operator:GPR 3 "boolean_operator"
2953 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
2954 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
2955 (const_int 0)))
2956 (clobber (match_scratch:GPR 0 "=r,r"))]
2957 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2958 "@
2959 %q3. %0,%1,%2
2960 #"
2961 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
2962 [(set (match_dup 0)
2963 (match_dup 3))
2964 (set (match_dup 4)
2965 (compare:CC (match_dup 0)
2966 (const_int 0)))]
2967 ""
2968 [(set_attr "type" "logical")
2969 (set_attr "dot" "yes")
2970 (set_attr "length" "4,8")])
2972 (define_insn_and_split "*bool<mode>3_dot2"
2973 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2974 (compare:CC (match_operator:GPR 3 "boolean_operator"
2975 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
2976 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
2977 (const_int 0)))
2978 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2979 (match_dup 3))]
2980 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2981 "@
2982 %q3. %0,%1,%2
2983 #"
2984 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
2985 [(set (match_dup 0)
2986 (match_dup 3))
2987 (set (match_dup 4)
2988 (compare:CC (match_dup 0)
2989 (const_int 0)))]
2990 ""
2991 [(set_attr "type" "logical")
2992 (set_attr "dot" "yes")
2993 (set_attr "length" "4,8")])
2996 (define_insn "*boolc<mode>3"
2997 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2998 (match_operator:GPR 3 "boolean_operator"
2999 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))
3000 (match_operand:GPR 1 "gpc_reg_operand" "r")]))]
3001 ""
3002 "%q3 %0,%1,%2"
3003 [(set_attr "type" "logical")])
3005 (define_insn_and_split "*boolc<mode>3_dot"
3006 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3007 (compare:CC (match_operator:GPR 3 "boolean_operator"
3008 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3009 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3010 (const_int 0)))
3011 (clobber (match_scratch:GPR 0 "=r,r"))]
3012 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3013 "@
3014 %q3. %0,%1,%2
3015 #"
3016 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3017 [(set (match_dup 0)
3018 (match_dup 3))
3019 (set (match_dup 4)
3020 (compare:CC (match_dup 0)
3021 (const_int 0)))]
3022 ""
3023 [(set_attr "type" "logical")
3024 (set_attr "dot" "yes")
3025 (set_attr "length" "4,8")])
3027 (define_insn_and_split "*boolc<mode>3_dot2"
3028 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3029 (compare:CC (match_operator:GPR 3 "boolean_operator"
3030 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3031 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3032 (const_int 0)))
3033 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3034 (match_dup 3))]
3035 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3036 "@
3037 %q3. %0,%1,%2
3038 #"
3039 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3040 [(set (match_dup 0)
3041 (match_dup 3))
3042 (set (match_dup 4)
3043 (compare:CC (match_dup 0)
3044 (const_int 0)))]
3045 ""
3046 [(set_attr "type" "logical")
3047 (set_attr "dot" "yes")
3048 (set_attr "length" "4,8")])
3051 (define_insn "*boolcc<mode>3"
3052 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3053 (match_operator:GPR 3 "boolean_operator"
3054 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
3055 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))]
3056 ""
3057 "%q3 %0,%1,%2"
3058 [(set_attr "type" "logical")])
3060 (define_insn_and_split "*boolcc<mode>3_dot"
3061 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3062 (compare:CC (match_operator:GPR 3 "boolean_operator"
3063 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3064 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3065 (const_int 0)))
3066 (clobber (match_scratch:GPR 0 "=r,r"))]
3067 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3068 "@
3069 %q3. %0,%1,%2
3070 #"
3071 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3072 [(set (match_dup 0)
3073 (match_dup 3))
3074 (set (match_dup 4)
3075 (compare:CC (match_dup 0)
3076 (const_int 0)))]
3077 ""
3078 [(set_attr "type" "logical")
3079 (set_attr "dot" "yes")
3080 (set_attr "length" "4,8")])
3082 (define_insn_and_split "*boolcc<mode>3_dot2"
3083 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3084 (compare:CC (match_operator:GPR 3 "boolean_operator"
3085 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3086 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3087 (const_int 0)))
3088 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3089 (match_dup 3))]
3090 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3091 "@
3092 %q3. %0,%1,%2
3093 #"
3094 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3095 [(set (match_dup 0)
3096 (match_dup 3))
3097 (set (match_dup 4)
3098 (compare:CC (match_dup 0)
3099 (const_int 0)))]
3100 ""
3101 [(set_attr "type" "logical")
3102 (set_attr "dot" "yes")
3103 (set_attr "length" "4,8")])
3106 ;; TODO: Should have dots of this as well.
3107 (define_insn "*eqv<mode>3"
3108 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3109 (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3110 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
3111 ""
3112 "eqv %0,%1,%2"
3113 [(set_attr "type" "logical")])
3114 \f
3115 ;; Rotate and shift insns, in all their variants. These support shifts,
3116 ;; field inserts and extracts, and various combinations thereof.
3117 (define_expand "insv"
3118 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3119 (match_operand:SI 1 "const_int_operand" "")
3120 (match_operand:SI 2 "const_int_operand" ""))
3121 (match_operand 3 "gpc_reg_operand" ""))]
3122 ""
3123 "
3124 {
3125 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3126 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3127 compiler if the address of the structure is taken later. Likewise, do
3128 not handle invalid E500 subregs. */
3129 if (GET_CODE (operands[0]) == SUBREG
3130 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3131 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3132 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3133 FAIL;
3135 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3136 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3137 operands[3]));
3138 else
3139 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3140 operands[3]));
3141 DONE;
3142 }")
3144 (define_insn "insvsi_internal"
3145 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3146 (match_operand:SI 1 "const_int_operand" "i")
3147 (match_operand:SI 2 "const_int_operand" "i"))
3148 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3149 ""
3150 "*
3151 {
3152 int start = INTVAL (operands[2]) & 31;
3153 int size = INTVAL (operands[1]) & 31;
3155 operands[4] = GEN_INT (32 - start - size);
3156 operands[1] = GEN_INT (start + size - 1);
3157 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3158 }"
3159 [(set_attr "type" "insert")])
3161 (define_insn "*insvsi_internal1"
3162 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3163 (match_operand:SI 1 "const_int_operand" "i")
3164 (match_operand:SI 2 "const_int_operand" "i"))
3165 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3166 (match_operand:SI 4 "const_int_operand" "i")))]
3167 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3168 "*
3169 {
3170 int shift = INTVAL (operands[4]) & 31;
3171 int start = INTVAL (operands[2]) & 31;
3172 int size = INTVAL (operands[1]) & 31;
3174 operands[4] = GEN_INT (shift - start - size);
3175 operands[1] = GEN_INT (start + size - 1);
3176 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3177 }"
3178 [(set_attr "type" "insert")])
3180 (define_insn "*insvsi_internal2"
3181 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3182 (match_operand:SI 1 "const_int_operand" "i")
3183 (match_operand:SI 2 "const_int_operand" "i"))
3184 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3185 (match_operand:SI 4 "const_int_operand" "i")))]
3186 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3187 "*
3188 {
3189 int shift = INTVAL (operands[4]) & 31;
3190 int start = INTVAL (operands[2]) & 31;
3191 int size = INTVAL (operands[1]) & 31;
3193 operands[4] = GEN_INT (32 - shift - start - size);
3194 operands[1] = GEN_INT (start + size - 1);
3195 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3196 }"
3197 [(set_attr "type" "insert")])
3199 (define_insn "*insvsi_internal3"
3200 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3201 (match_operand:SI 1 "const_int_operand" "i")
3202 (match_operand:SI 2 "const_int_operand" "i"))
3203 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3204 (match_operand:SI 4 "const_int_operand" "i")))]
3205 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3206 "*
3207 {
3208 int shift = INTVAL (operands[4]) & 31;
3209 int start = INTVAL (operands[2]) & 31;
3210 int size = INTVAL (operands[1]) & 31;
3212 operands[4] = GEN_INT (32 - shift - start - size);
3213 operands[1] = GEN_INT (start + size - 1);
3214 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3215 }"
3216 [(set_attr "type" "insert")])
3218 (define_insn "*insvsi_internal4"
3219 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3220 (match_operand:SI 1 "const_int_operand" "i")
3221 (match_operand:SI 2 "const_int_operand" "i"))
3222 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3223 (match_operand:SI 4 "const_int_operand" "i")
3224 (match_operand:SI 5 "const_int_operand" "i")))]
3225 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3226 "*
3227 {
3228 int extract_start = INTVAL (operands[5]) & 31;
3229 int extract_size = INTVAL (operands[4]) & 31;
3230 int insert_start = INTVAL (operands[2]) & 31;
3231 int insert_size = INTVAL (operands[1]) & 31;
3233 /* Align extract field with insert field */
3234 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3235 operands[1] = GEN_INT (insert_start + insert_size - 1);
3236 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3237 }"
3238 [(set_attr "type" "insert")])
3240 ;; combine patterns for rlwimi
3241 (define_insn "*insvsi_internal5"
3242 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3243 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3244 (match_operand:SI 1 "mask_operand" "i"))
3245 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3246 (match_operand:SI 2 "const_int_operand" "i"))
3247 (match_operand:SI 5 "mask_operand" "i"))))]
3248 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3249 "*
3250 {
3251 int me = extract_ME(operands[5]);
3252 int mb = extract_MB(operands[5]);
3253 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3254 operands[2] = GEN_INT(mb);
3255 operands[1] = GEN_INT(me);
3256 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3257 }"
3258 [(set_attr "type" "insert")])
3260 (define_insn "*insvsi_internal6"
3261 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3262 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3263 (match_operand:SI 2 "const_int_operand" "i"))
3264 (match_operand:SI 5 "mask_operand" "i"))
3265 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3266 (match_operand:SI 1 "mask_operand" "i"))))]
3267 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3268 "*
3269 {
3270 int me = extract_ME(operands[5]);
3271 int mb = extract_MB(operands[5]);
3272 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3273 operands[2] = GEN_INT(mb);
3274 operands[1] = GEN_INT(me);
3275 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3276 }"
3277 [(set_attr "type" "insert")])
3279 (define_insn "insvdi_internal"
3280 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3281 (match_operand:SI 1 "const_int_operand" "i")
3282 (match_operand:SI 2 "const_int_operand" "i"))
3283 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3284 "TARGET_POWERPC64"
3285 "*
3286 {
3287 int start = INTVAL (operands[2]) & 63;
3288 int size = INTVAL (operands[1]) & 63;
3290 operands[1] = GEN_INT (64 - start - size);
3291 return \"rldimi %0,%3,%H1,%H2\";
3292 }"
3293 [(set_attr "type" "insert")
3294 (set_attr "size" "64")])
3296 (define_insn "*insvdi_internal2"
3297 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3298 (match_operand:SI 1 "const_int_operand" "i")
3299 (match_operand:SI 2 "const_int_operand" "i"))
3300 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3301 (match_operand:SI 4 "const_int_operand" "i")))]
3302 "TARGET_POWERPC64
3303 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3304 "*
3305 {
3306 int shift = INTVAL (operands[4]) & 63;
3307 int start = (INTVAL (operands[2]) & 63) - 32;
3308 int size = INTVAL (operands[1]) & 63;
3310 operands[4] = GEN_INT (64 - shift - start - size);
3311 operands[2] = GEN_INT (start);
3312 operands[1] = GEN_INT (start + size - 1);
3313 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3314 }")
3316 (define_insn "*insvdi_internal3"
3317 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3318 (match_operand:SI 1 "const_int_operand" "i")
3319 (match_operand:SI 2 "const_int_operand" "i"))
3320 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3321 (match_operand:SI 4 "const_int_operand" "i")))]
3322 "TARGET_POWERPC64
3323 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3324 "*
3325 {
3326 int shift = INTVAL (operands[4]) & 63;
3327 int start = (INTVAL (operands[2]) & 63) - 32;
3328 int size = INTVAL (operands[1]) & 63;
3330 operands[4] = GEN_INT (64 - shift - start - size);
3331 operands[2] = GEN_INT (start);
3332 operands[1] = GEN_INT (start + size - 1);
3333 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3334 }")
3336 (define_expand "extzv"
3337 [(set (match_operand 0 "gpc_reg_operand" "")
3338 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3339 (match_operand:SI 2 "const_int_operand" "")
3340 (match_operand:SI 3 "const_int_operand" "")))]
3341 ""
3342 "
3343 {
3344 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3345 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3346 compiler if the address of the structure is taken later. */
3347 if (GET_CODE (operands[0]) == SUBREG
3348 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3349 FAIL;
3351 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3352 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3353 operands[3]));
3354 else
3355 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3356 operands[3]));
3357 DONE;
3358 }")
3360 (define_insn "extzvsi_internal"
3361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3362 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3363 (match_operand:SI 2 "const_int_operand" "i")
3364 (match_operand:SI 3 "const_int_operand" "i")))]
3365 ""
3366 "*
3367 {
3368 int start = INTVAL (operands[3]) & 31;
3369 int size = INTVAL (operands[2]) & 31;
3371 if (start + size >= 32)
3372 operands[3] = const0_rtx;
3373 else
3374 operands[3] = GEN_INT (start + size);
3375 return \"rlwinm %0,%1,%3,%s2,31\";
3376 }"
3377 [(set_attr "type" "shift")])
3379 (define_insn "*extzvsi_internal1"
3380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3381 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3382 (match_operand:SI 2 "const_int_operand" "i,i")
3383 (match_operand:SI 3 "const_int_operand" "i,i"))
3384 (const_int 0)))
3385 (clobber (match_scratch:SI 4 "=r,r"))]
3386 ""
3387 "*
3388 {
3389 int start = INTVAL (operands[3]) & 31;
3390 int size = INTVAL (operands[2]) & 31;
3392 /* Force split for non-cc0 compare. */
3393 if (which_alternative == 1)
3394 return \"#\";
3396 /* If the bit-field being tested fits in the upper or lower half of a
3397 word, it is possible to use andiu. or andil. to test it. This is
3398 useful because the condition register set-use delay is smaller for
3399 andi[ul]. than for rlinm. This doesn't work when the starting bit
3400 position is 0 because the LT and GT bits may be set wrong. */
3402 if ((start > 0 && start + size <= 16) || start >= 16)
3403 {
3404 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3405 - (1 << (16 - (start & 15) - size))));
3406 if (start < 16)
3407 return \"andis. %4,%1,%3\";
3408 else
3409 return \"andi. %4,%1,%3\";
3410 }
3412 if (start + size >= 32)
3413 operands[3] = const0_rtx;
3414 else
3415 operands[3] = GEN_INT (start + size);
3416 return \"rlwinm. %4,%1,%3,%s2,31\";
3417 }"
3418 [(set_attr "type" "shift")
3419 (set_attr "dot" "yes")
3420 (set_attr "length" "4,8")])
3422 (define_split
3423 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3424 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3425 (match_operand:SI 2 "const_int_operand" "")
3426 (match_operand:SI 3 "const_int_operand" ""))
3427 (const_int 0)))
3428 (clobber (match_scratch:SI 4 ""))]
3429 "reload_completed"
3430 [(set (match_dup 4)
3431 (zero_extract:SI (match_dup 1) (match_dup 2)
3432 (match_dup 3)))
3433 (set (match_dup 0)
3434 (compare:CC (match_dup 4)
3435 (const_int 0)))]
3436 "")
3438 (define_insn "*extzvsi_internal2"
3439 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3440 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3441 (match_operand:SI 2 "const_int_operand" "i,i")
3442 (match_operand:SI 3 "const_int_operand" "i,i"))
3443 (const_int 0)))
3444 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3445 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3446 ""
3447 "*
3448 {
3449 int start = INTVAL (operands[3]) & 31;
3450 int size = INTVAL (operands[2]) & 31;
3452 /* Force split for non-cc0 compare. */
3453 if (which_alternative == 1)
3454 return \"#\";
3456 /* Since we are using the output value, we can't ignore any need for
3457 a shift. The bit-field must end at the LSB. */
3458 if (start >= 16 && start + size == 32)
3459 {
3460 operands[3] = GEN_INT ((1 << size) - 1);
3461 return \"andi. %0,%1,%3\";
3462 }
3464 if (start + size >= 32)
3465 operands[3] = const0_rtx;
3466 else
3467 operands[3] = GEN_INT (start + size);
3468 return \"rlwinm. %0,%1,%3,%s2,31\";
3469 }"
3470 [(set_attr "type" "shift")
3471 (set_attr "dot" "yes")
3472 (set_attr "length" "4,8")])
3474 (define_split
3475 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3476 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3477 (match_operand:SI 2 "const_int_operand" "")
3478 (match_operand:SI 3 "const_int_operand" ""))
3479 (const_int 0)))
3480 (set (match_operand:SI 0 "gpc_reg_operand" "")
3481 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3482 "reload_completed"
3483 [(set (match_dup 0)
3484 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3485 (set (match_dup 4)
3486 (compare:CC (match_dup 0)
3487 (const_int 0)))]
3488 "")
3490 (define_insn "extzvdi_internal"
3491 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3492 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3493 (match_operand:SI 2 "const_int_operand" "i")
3494 (match_operand:SI 3 "const_int_operand" "i")))]
3495 "TARGET_POWERPC64"
3496 "*
3497 {
3498 int start = INTVAL (operands[3]) & 63;
3499 int size = INTVAL (operands[2]) & 63;
3501 if (start + size >= 64)
3502 operands[3] = const0_rtx;
3503 else
3504 operands[3] = GEN_INT (start + size);
3505 operands[2] = GEN_INT (64 - size);
3506 return \"rldicl %0,%1,%3,%2\";
3507 }"
3508 [(set_attr "type" "shift")])
3510 (define_insn "*extzvdi_internal1"
3511 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3512 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3513 (match_operand:SI 2 "const_int_operand" "i")
3514 (match_operand:SI 3 "const_int_operand" "i"))
3515 (const_int 0)))
3516 (clobber (match_scratch:DI 4 "=r"))]
3517 "TARGET_64BIT && rs6000_gen_cell_microcode"
3518 "*
3519 {
3520 int start = INTVAL (operands[3]) & 63;
3521 int size = INTVAL (operands[2]) & 63;
3523 if (start + size >= 64)
3524 operands[3] = const0_rtx;
3525 else
3526 operands[3] = GEN_INT (start + size);
3527 operands[2] = GEN_INT (64 - size);
3528 return \"rldicl. %4,%1,%3,%2\";
3529 }"
3530 [(set_attr "type" "shift")
3531 (set_attr "dot" "yes")])
3533 (define_insn "*extzvdi_internal2"
3534 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3535 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3536 (match_operand:SI 2 "const_int_operand" "i")
3537 (match_operand:SI 3 "const_int_operand" "i"))
3538 (const_int 0)))
3539 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3540 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3541 "TARGET_64BIT && rs6000_gen_cell_microcode"
3542 "*
3543 {
3544 int start = INTVAL (operands[3]) & 63;
3545 int size = INTVAL (operands[2]) & 63;
3547 if (start + size >= 64)
3548 operands[3] = const0_rtx;
3549 else
3550 operands[3] = GEN_INT (start + size);
3551 operands[2] = GEN_INT (64 - size);
3552 return \"rldicl. %0,%1,%3,%2\";
3553 }"
3554 [(set_attr "type" "shift")
3555 (set_attr "dot" "yes")])
3558 (define_insn "rotl<mode>3"
3559 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3560 (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3561 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3562 ""
3563 "rotl<wd>%I2 %0,%1,%<hH>2"
3564 [(set_attr "type" "shift")
3565 (set_attr "maybe_var_shift" "yes")])
3567 (define_insn "*rotlsi3_64"
3568 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3569 (zero_extend:DI
3570 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3571 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3572 "TARGET_POWERPC64"
3573 "rotlw%I2 %0,%1,%h2"
3574 [(set_attr "type" "shift")
3575 (set_attr "maybe_var_shift" "yes")])
3577 (define_insn_and_split "*rotl<mode>3_dot"
3578 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3579 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3580 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3581 (const_int 0)))
3582 (clobber (match_scratch:GPR 0 "=r,r"))]
3583 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3584 "@
3585 rotl<wd>%I2. %0,%1,%<hH>2
3586 #"
3587 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3588 [(set (match_dup 0)
3589 (rotate:GPR (match_dup 1)
3590 (match_dup 2)))
3591 (set (match_dup 3)
3592 (compare:CC (match_dup 0)
3593 (const_int 0)))]
3594 ""
3595 [(set_attr "type" "shift")
3596 (set_attr "maybe_var_shift" "yes")
3597 (set_attr "dot" "yes")
3598 (set_attr "length" "4,8")])
3600 (define_insn_and_split "*rotl<mode>3_dot2"
3601 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3602 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3603 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3604 (const_int 0)))
3605 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3606 (rotate:GPR (match_dup 1)
3607 (match_dup 2)))]
3608 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3609 "@
3610 rotl<wd>%I2. %0,%1,%<hH>2
3611 #"
3612 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3613 [(set (match_dup 0)
3614 (rotate:GPR (match_dup 1)
3615 (match_dup 2)))
3616 (set (match_dup 3)
3617 (compare:CC (match_dup 0)
3618 (const_int 0)))]
3619 ""
3620 [(set_attr "type" "shift")
3621 (set_attr "maybe_var_shift" "yes")
3622 (set_attr "dot" "yes")
3623 (set_attr "length" "4,8")])
3626 (define_insn "*rotlsi3_internal4"
3627 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3628 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3629 (match_operand:SI 2 "reg_or_cint_operand" "rn"))
3630 (match_operand:SI 3 "mask_operand" "n")))]
3631 ""
3632 "rlw%I2nm %0,%1,%h2,%m3,%M3"
3633 [(set_attr "type" "shift")
3634 (set_attr "maybe_var_shift" "yes")])
3636 (define_insn "*rotlsi3_internal5"
3637 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3638 (compare:CC (and:SI
3639 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3640 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3641 (match_operand:SI 3 "mask_operand" "n,n"))
3642 (const_int 0)))
3643 (clobber (match_scratch:SI 4 "=r,r"))]
3644 ""
3645 "@
3646 rlw%I2nm. %4,%1,%h2,%m3,%M3
3647 #"
3648 [(set_attr "type" "shift")
3649 (set_attr "maybe_var_shift" "yes")
3650 (set_attr "dot" "yes")
3651 (set_attr "length" "4,8")])
3653 (define_split
3654 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3655 (compare:CC (and:SI
3656 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3657 (match_operand:SI 2 "reg_or_cint_operand" ""))
3658 (match_operand:SI 3 "mask_operand" ""))
3659 (const_int 0)))
3660 (clobber (match_scratch:SI 4 ""))]
3661 "reload_completed"
3662 [(set (match_dup 4)
3663 (and:SI (rotate:SI (match_dup 1)
3664 (match_dup 2))
3665 (match_dup 3)))
3666 (set (match_dup 0)
3667 (compare:CC (match_dup 4)
3668 (const_int 0)))]
3669 "")
3671 (define_insn "*rotlsi3_internal6"
3672 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3673 (compare:CC (and:SI
3674 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3675 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3676 (match_operand:SI 3 "mask_operand" "n,n"))
3677 (const_int 0)))
3678 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3679 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3680 ""
3681 "@
3682 rlw%I2nm. %0,%1,%h2,%m3,%M3
3683 #"
3684 [(set_attr "type" "shift")
3685 (set_attr "maybe_var_shift" "yes")
3686 (set_attr "dot" "yes")
3687 (set_attr "length" "4,8")])
3689 (define_split
3690 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3691 (compare:CC (and:SI
3692 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3693 (match_operand:SI 2 "reg_or_cint_operand" ""))
3694 (match_operand:SI 3 "mask_operand" ""))
3695 (const_int 0)))
3696 (set (match_operand:SI 0 "gpc_reg_operand" "")
3697 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3698 "reload_completed"
3699 [(set (match_dup 0)
3700 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3701 (set (match_dup 4)
3702 (compare:CC (match_dup 0)
3703 (const_int 0)))]
3704 "")
3706 (define_insn "*rotlsi3_internal7le"
3707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3708 (zero_extend:SI
3709 (subreg:QI
3710 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3711 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3712 "!BYTES_BIG_ENDIAN"
3713 "rlw%I2nm %0,%1,%h2,0xff"
3714 [(set (attr "cell_micro")
3715 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3716 (const_string "not")
3717 (const_string "always")))
3718 (set_attr "type" "shift")])
3720 (define_insn "*rotlsi3_internal7be"
3721 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3722 (zero_extend:SI
3723 (subreg:QI
3724 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3725 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3726 "BYTES_BIG_ENDIAN"
3727 "rlw%I2nm %0,%1,%h2,0xff"
3728 [(set (attr "cell_micro")
3729 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3730 (const_string "not")
3731 (const_string "always")))
3732 (set_attr "type" "shift")])
3734 (define_insn "*rotlsi3_internal8le"
3735 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3736 (compare:CC (zero_extend:SI
3737 (subreg:QI
3738 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3739 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3740 (const_int 0)))
3741 (clobber (match_scratch:SI 3 "=r,r"))]
3742 "!BYTES_BIG_ENDIAN"
3743 "@
3744 rlw%I2nm. %3,%1,%h2,0xff
3745 #"
3746 [(set_attr "type" "shift")
3747 (set_attr "maybe_var_shift" "yes")
3748 (set_attr "dot" "yes")
3749 (set_attr "length" "4,8")])
3751 (define_insn "*rotlsi3_internal8be"
3752 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3753 (compare:CC (zero_extend:SI
3754 (subreg:QI
3755 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3756 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3757 (const_int 0)))
3758 (clobber (match_scratch:SI 3 "=r,r"))]
3759 "BYTES_BIG_ENDIAN"
3760 "@
3761 rlw%I2nm. %3,%1,%h2,0xff
3762 #"
3763 [(set_attr "type" "shift")
3764 (set_attr "maybe_var_shift" "yes")
3765 (set_attr "dot" "yes")
3766 (set_attr "length" "4,8")])
3768 (define_split
3769 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3770 (compare:CC (zero_extend:SI
3771 (subreg:QI
3772 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3773 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3774 (const_int 0)))
3775 (clobber (match_scratch:SI 3 ""))]
3776 "!BYTES_BIG_ENDIAN && reload_completed"
3777 [(set (match_dup 3)
3778 (zero_extend:SI (subreg:QI
3779 (rotate:SI (match_dup 1)
3780 (match_dup 2)) 0)))
3781 (set (match_dup 0)
3782 (compare:CC (match_dup 3)
3783 (const_int 0)))]
3784 "")
3786 (define_split
3787 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3788 (compare:CC (zero_extend:SI
3789 (subreg:QI
3790 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3791 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3792 (const_int 0)))
3793 (clobber (match_scratch:SI 3 ""))]
3794 "BYTES_BIG_ENDIAN && reload_completed"
3795 [(set (match_dup 3)
3796 (zero_extend:SI (subreg:QI
3797 (rotate:SI (match_dup 1)
3798 (match_dup 2)) 3)))
3799 (set (match_dup 0)
3800 (compare:CC (match_dup 3)
3801 (const_int 0)))]
3802 "")
3804 (define_insn "*rotlsi3_internal9le"
3805 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3806 (compare:CC (zero_extend:SI
3807 (subreg:QI
3808 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3809 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3810 (const_int 0)))
3811 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3812 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3813 "!BYTES_BIG_ENDIAN"
3814 "@
3815 rlw%I2nm. %0,%1,%h2,0xff
3816 #"
3817 [(set_attr "type" "shift")
3818 (set_attr "maybe_var_shift" "yes")
3819 (set_attr "dot" "yes")
3820 (set_attr "length" "4,8")])
3822 (define_insn "*rotlsi3_internal9be"
3823 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3824 (compare:CC (zero_extend:SI
3825 (subreg:QI
3826 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3827 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3828 (const_int 0)))
3829 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3830 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3831 "BYTES_BIG_ENDIAN"
3832 "@
3833 rlw%I2nm. %0,%1,%h2,0xff
3834 #"
3835 [(set_attr "type" "shift")
3836 (set_attr "maybe_var_shift" "yes")
3837 (set_attr "dot" "yes")
3838 (set_attr "length" "4,8")])
3840 (define_split
3841 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3842 (compare:CC (zero_extend:SI
3843 (subreg:QI
3844 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3845 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3846 (const_int 0)))
3847 (set (match_operand:SI 0 "gpc_reg_operand" "")
3848 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3849 "!BYTES_BIG_ENDIAN && reload_completed"
3850 [(set (match_dup 0)
3851 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3852 (set (match_dup 3)
3853 (compare:CC (match_dup 0)
3854 (const_int 0)))]
3855 "")
3857 (define_split
3858 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3859 (compare:CC (zero_extend:SI
3860 (subreg:QI
3861 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3862 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3863 (const_int 0)))
3864 (set (match_operand:SI 0 "gpc_reg_operand" "")
3865 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3866 "BYTES_BIG_ENDIAN && reload_completed"
3867 [(set (match_dup 0)
3868 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
3869 (set (match_dup 3)
3870 (compare:CC (match_dup 0)
3871 (const_int 0)))]
3872 "")
3874 (define_insn "*rotlsi3_internal10le"
3875 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3876 (zero_extend:SI
3877 (subreg:HI
3878 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3879 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))]
3880 "!BYTES_BIG_ENDIAN"
3881 "rlw%I2nm %0,%1,%h2,0xffff"
3882 [(set_attr "type" "shift")
3883 (set_attr "maybe_var_shift" "yes")])
3885 (define_insn "*rotlsi3_internal10be"
3886 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3887 (zero_extend:SI
3888 (subreg:HI
3889 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3890 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))]
3891 "BYTES_BIG_ENDIAN"
3892 "rlw%I2nm %0,%1,%h2,0xffff"
3893 [(set_attr "type" "shift")
3894 (set_attr "maybe_var_shift" "yes")])
3896 (define_insn "*rotlsi3_internal11le"
3897 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3898 (compare:CC (zero_extend:SI
3899 (subreg:HI
3900 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3901 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3902 (const_int 0)))
3903 (clobber (match_scratch:SI 3 "=r,r"))]
3904 "!BYTES_BIG_ENDIAN"
3905 "@
3906 rlw%I2nm. %3,%1,%h2,0xffff
3907 #"
3908 [(set_attr "type" "shift")
3909 (set_attr "maybe_var_shift" "yes")
3910 (set_attr "dot" "yes")
3911 (set_attr "length" "4,8")])
3913 (define_insn "*rotlsi3_internal11be"
3914 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3915 (compare:CC (zero_extend:SI
3916 (subreg:HI
3917 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3918 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
3919 (const_int 0)))
3920 (clobber (match_scratch:SI 3 "=r,r"))]
3921 "BYTES_BIG_ENDIAN"
3922 "@
3923 rlw%I2nm. %3,%1,%h2,0xffff
3924 #"
3925 [(set_attr "type" "shift")
3926 (set_attr "maybe_var_shift" "yes")
3927 (set_attr "dot" "yes")
3928 (set_attr "length" "4,8")])
3930 (define_split
3931 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3932 (compare:CC (zero_extend:SI
3933 (subreg:HI
3934 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3935 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3936 (const_int 0)))
3937 (clobber (match_scratch:SI 3 ""))]
3938 "!BYTES_BIG_ENDIAN && reload_completed"
3939 [(set (match_dup 3)
3940 (zero_extend:SI (subreg:HI
3941 (rotate:SI (match_dup 1)
3942 (match_dup 2)) 0)))
3943 (set (match_dup 0)
3944 (compare:CC (match_dup 3)
3945 (const_int 0)))]
3946 "")
3948 (define_split
3949 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3950 (compare:CC (zero_extend:SI
3951 (subreg:HI
3952 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3953 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
3954 (const_int 0)))
3955 (clobber (match_scratch:SI 3 ""))]
3956 "BYTES_BIG_ENDIAN && reload_completed"
3957 [(set (match_dup 3)
3958 (zero_extend:SI (subreg:HI
3959 (rotate:SI (match_dup 1)
3960 (match_dup 2)) 2)))
3961 (set (match_dup 0)
3962 (compare:CC (match_dup 3)
3963 (const_int 0)))]
3964 "")
3966 (define_insn "*rotlsi3_internal12le"
3967 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3968 (compare:CC (zero_extend:SI
3969 (subreg:HI
3970 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3971 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3972 (const_int 0)))
3973 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3974 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3975 "!BYTES_BIG_ENDIAN"
3976 "@
3977 rlw%I2nm. %0,%1,%h2,0xffff
3978 #"
3979 [(set_attr "type" "shift")
3980 (set_attr "maybe_var_shift" "yes")
3981 (set_attr "dot" "yes")
3982 (set_attr "length" "4,8")])
3984 (define_insn "*rotlsi3_internal12be"
3985 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3986 (compare:CC (zero_extend:SI
3987 (subreg:HI
3988 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3989 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
3990 (const_int 0)))
3991 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3992 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
3993 "BYTES_BIG_ENDIAN"
3994 "@
3995 rlw%I2nm. %0,%1,%h2,0xffff
3996 #"
3997 [(set_attr "type" "shift")
3998 (set_attr "maybe_var_shift" "yes")
3999 (set_attr "dot" "yes")
4000 (set_attr "length" "4,8")])
4002 (define_split
4003 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4004 (compare:CC (zero_extend:SI
4005 (subreg:HI
4006 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4007 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4008 (const_int 0)))
4009 (set (match_operand:SI 0 "gpc_reg_operand" "")
4010 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4011 "!BYTES_BIG_ENDIAN && reload_completed"
4012 [(set (match_dup 0)
4013 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4014 (set (match_dup 3)
4015 (compare:CC (match_dup 0)
4016 (const_int 0)))]
4017 "")
4019 (define_split
4020 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4021 (compare:CC (zero_extend:SI
4022 (subreg:HI
4023 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4024 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4025 (const_int 0)))
4026 (set (match_operand:SI 0 "gpc_reg_operand" "")
4027 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4028 "BYTES_BIG_ENDIAN && reload_completed"
4029 [(set (match_dup 0)
4030 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4031 (set (match_dup 3)
4032 (compare:CC (match_dup 0)
4033 (const_int 0)))]
4034 "")
4037 (define_insn "ashl<mode>3"
4038 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4039 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4040 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4041 ""
4042 "sl<wd>%I2 %0,%1,%<hH>2"
4043 [(set_attr "type" "shift")
4044 (set_attr "maybe_var_shift" "yes")])
4046 (define_insn "*ashlsi3_64"
4047 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4048 (zero_extend:DI
4049 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4050 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4051 "TARGET_POWERPC64"
4052 "slw%I2 %0,%1,%h2"
4053 [(set_attr "type" "shift")
4054 (set_attr "maybe_var_shift" "yes")])
4056 (define_insn_and_split "*ashl<mode>3_dot"
4057 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4058 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4059 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4060 (const_int 0)))
4061 (clobber (match_scratch:GPR 0 "=r,r"))]
4062 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4063 "@
4064 sl<wd>%I2. %0,%1,%<hH>2
4065 #"
4066 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4067 [(set (match_dup 0)
4068 (ashift:GPR (match_dup 1)
4069 (match_dup 2)))
4070 (set (match_dup 3)
4071 (compare:CC (match_dup 0)
4072 (const_int 0)))]
4073 ""
4074 [(set_attr "type" "shift")
4075 (set_attr "maybe_var_shift" "yes")
4076 (set_attr "dot" "yes")
4077 (set_attr "length" "4,8")])
4079 (define_insn_and_split "*ashl<mode>3_dot2"
4080 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4081 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4082 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4083 (const_int 0)))
4084 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4085 (ashift:GPR (match_dup 1)
4086 (match_dup 2)))]
4087 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4088 "@
4089 sl<wd>%I2. %0,%1,%<hH>2
4090 #"
4091 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4092 [(set (match_dup 0)
4093 (ashift:GPR (match_dup 1)
4094 (match_dup 2)))
4095 (set (match_dup 3)
4096 (compare:CC (match_dup 0)
4097 (const_int 0)))]
4098 ""
4099 [(set_attr "type" "shift")
4100 (set_attr "maybe_var_shift" "yes")
4101 (set_attr "dot" "yes")
4102 (set_attr "length" "4,8")])
4105 (define_insn "rlwinm"
4106 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4107 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4108 (match_operand:SI 2 "const_int_operand" "i"))
4109 (match_operand:SI 3 "mask_operand" "n")))]
4110 "includes_lshift_p (operands[2], operands[3])"
4111 "rlwinm %0,%1,%h2,%m3,%M3"
4112 [(set_attr "type" "shift")])
4114 (define_insn ""
4115 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4116 (compare:CC
4117 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4118 (match_operand:SI 2 "const_int_operand" "i,i"))
4119 (match_operand:SI 3 "mask_operand" "n,n"))
4120 (const_int 0)))
4121 (clobber (match_scratch:SI 4 "=r,r"))]
4122 "includes_lshift_p (operands[2], operands[3])"
4123 "@
4124 rlwinm. %4,%1,%h2,%m3,%M3
4125 #"
4126 [(set_attr "type" "shift")
4127 (set_attr "dot" "yes")
4128 (set_attr "length" "4,8")])
4130 (define_split
4131 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4132 (compare:CC
4133 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4134 (match_operand:SI 2 "const_int_operand" ""))
4135 (match_operand:SI 3 "mask_operand" ""))
4136 (const_int 0)))
4137 (clobber (match_scratch:SI 4 ""))]
4138 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4139 [(set (match_dup 4)
4140 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4141 (match_dup 3)))
4142 (set (match_dup 0)
4143 (compare:CC (match_dup 4)
4144 (const_int 0)))]
4145 "")
4147 (define_insn ""
4148 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4149 (compare:CC
4150 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4151 (match_operand:SI 2 "const_int_operand" "i,i"))
4152 (match_operand:SI 3 "mask_operand" "n,n"))
4153 (const_int 0)))
4154 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4155 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4156 "includes_lshift_p (operands[2], operands[3])"
4157 "@
4158 rlwinm. %0,%1,%h2,%m3,%M3
4159 #"
4160 [(set_attr "type" "shift")
4161 (set_attr "dot" "yes")
4162 (set_attr "length" "4,8")])
4164 (define_split
4165 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4166 (compare:CC
4167 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4168 (match_operand:SI 2 "const_int_operand" ""))
4169 (match_operand:SI 3 "mask_operand" ""))
4170 (const_int 0)))
4171 (set (match_operand:SI 0 "gpc_reg_operand" "")
4172 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4173 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4174 [(set (match_dup 0)
4175 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4176 (set (match_dup 4)
4177 (compare:CC (match_dup 0)
4178 (const_int 0)))]
4179 "")
4182 (define_insn "lshr<mode>3"
4183 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4184 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4185 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4186 ""
4187 "sr<wd>%I2 %0,%1,%<hH>2"
4188 [(set_attr "type" "shift")
4189 (set_attr "maybe_var_shift" "yes")])
4191 (define_insn "*lshrsi3_64"
4192 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4193 (zero_extend:DI
4194 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4195 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4196 "TARGET_POWERPC64"
4197 "srw%I2 %0,%1,%h2"
4198 [(set_attr "type" "shift")
4199 (set_attr "maybe_var_shift" "yes")])
4201 (define_insn_and_split "*lshr<mode>3_dot"
4202 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4203 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4204 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4205 (const_int 0)))
4206 (clobber (match_scratch:GPR 0 "=r,r"))]
4207 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4208 "@
4209 sr<wd>%I2. %0,%1,%<hH>2
4210 #"
4211 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4212 [(set (match_dup 0)
4213 (lshiftrt:GPR (match_dup 1)
4214 (match_dup 2)))
4215 (set (match_dup 3)
4216 (compare:CC (match_dup 0)
4217 (const_int 0)))]
4218 ""
4219 [(set_attr "type" "shift")
4220 (set_attr "maybe_var_shift" "yes")
4221 (set_attr "dot" "yes")
4222 (set_attr "length" "4,8")])
4224 (define_insn_and_split "*lshr<mode>3_dot2"
4225 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4226 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4227 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4228 (const_int 0)))
4229 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4230 (lshiftrt:GPR (match_dup 1)
4231 (match_dup 2)))]
4232 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4233 "@
4234 sr<wd>%I2. %0,%1,%<hH>2
4235 #"
4236 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4237 [(set (match_dup 0)
4238 (lshiftrt:GPR (match_dup 1)
4239 (match_dup 2)))
4240 (set (match_dup 3)
4241 (compare:CC (match_dup 0)
4242 (const_int 0)))]
4243 ""
4244 [(set_attr "type" "shift")
4245 (set_attr "maybe_var_shift" "yes")
4246 (set_attr "dot" "yes")
4247 (set_attr "length" "4,8")])
4250 (define_insn ""
4251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4252 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4253 (match_operand:SI 2 "const_int_operand" "i"))
4254 (match_operand:SI 3 "mask_operand" "n")))]
4255 "includes_rshift_p (operands[2], operands[3])"
4256 "rlwinm %0,%1,%s2,%m3,%M3"
4257 [(set_attr "type" "shift")])
4259 (define_insn ""
4260 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4261 (compare:CC
4262 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4263 (match_operand:SI 2 "const_int_operand" "i,i"))
4264 (match_operand:SI 3 "mask_operand" "n,n"))
4265 (const_int 0)))
4266 (clobber (match_scratch:SI 4 "=r,r"))]
4267 "includes_rshift_p (operands[2], operands[3])"
4268 "@
4269 rlwinm. %4,%1,%s2,%m3,%M3
4270 #"
4271 [(set_attr "type" "shift")
4272 (set_attr "dot" "yes")
4273 (set_attr "length" "4,8")])
4275 (define_split
4276 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4277 (compare:CC
4278 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4279 (match_operand:SI 2 "const_int_operand" ""))
4280 (match_operand:SI 3 "mask_operand" ""))
4281 (const_int 0)))
4282 (clobber (match_scratch:SI 4 ""))]
4283 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4284 [(set (match_dup 4)
4285 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4286 (match_dup 3)))
4287 (set (match_dup 0)
4288 (compare:CC (match_dup 4)
4289 (const_int 0)))]
4290 "")
4292 (define_insn ""
4293 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4294 (compare:CC
4295 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4296 (match_operand:SI 2 "const_int_operand" "i,i"))
4297 (match_operand:SI 3 "mask_operand" "n,n"))
4298 (const_int 0)))
4299 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4300 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4301 "includes_rshift_p (operands[2], operands[3])"
4302 "@
4303 rlwinm. %0,%1,%s2,%m3,%M3
4304 #"
4305 [(set_attr "type" "shift")
4306 (set_attr "dot" "yes")
4307 (set_attr "length" "4,8")])
4309 (define_split
4310 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4311 (compare:CC
4312 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4313 (match_operand:SI 2 "const_int_operand" ""))
4314 (match_operand:SI 3 "mask_operand" ""))
4315 (const_int 0)))
4316 (set (match_operand:SI 0 "gpc_reg_operand" "")
4317 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4318 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4319 [(set (match_dup 0)
4320 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4321 (set (match_dup 4)
4322 (compare:CC (match_dup 0)
4323 (const_int 0)))]
4324 "")
4326 (define_insn "*lshiftrt_internal1le"
4327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4328 (zero_extend:SI
4329 (subreg:QI
4330 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4331 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4332 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4333 "rlwinm %0,%1,%s2,0xff"
4334 [(set_attr "type" "shift")])
4336 (define_insn "*lshiftrt_internal1be"
4337 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4338 (zero_extend:SI
4339 (subreg:QI
4340 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4341 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4342 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4343 "rlwinm %0,%1,%s2,0xff"
4344 [(set_attr "type" "shift")])
4346 (define_insn "*lshiftrt_internal2le"
4347 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4348 (compare:CC
4349 (zero_extend:SI
4350 (subreg:QI
4351 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4352 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4353 (const_int 0)))
4354 (clobber (match_scratch:SI 3 "=r,r"))]
4355 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4356 "@
4357 rlwinm. %3,%1,%s2,0xff
4358 #"
4359 [(set_attr "type" "shift")
4360 (set_attr "dot" "yes")
4361 (set_attr "length" "4,8")])
4363 (define_insn "*lshiftrt_internal2be"
4364 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4365 (compare:CC
4366 (zero_extend:SI
4367 (subreg:QI
4368 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4369 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4370 (const_int 0)))
4371 (clobber (match_scratch:SI 3 "=r,r"))]
4372 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4373 "@
4374 rlwinm. %3,%1,%s2,0xff
4375 #"
4376 [(set_attr "type" "shift")
4377 (set_attr "dot" "yes")
4378 (set_attr "length" "4,8")])
4380 (define_split
4381 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4382 (compare:CC
4383 (zero_extend:SI
4384 (subreg:QI
4385 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4386 (match_operand:SI 2 "const_int_operand" "")) 0))
4387 (const_int 0)))
4388 (clobber (match_scratch:SI 3 ""))]
4389 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4390 [(set (match_dup 3)
4391 (zero_extend:SI (subreg:QI
4392 (lshiftrt:SI (match_dup 1)
4393 (match_dup 2)) 0)))
4394 (set (match_dup 0)
4395 (compare:CC (match_dup 3)
4396 (const_int 0)))]
4397 "")
4399 (define_split
4400 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4401 (compare:CC
4402 (zero_extend:SI
4403 (subreg:QI
4404 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4405 (match_operand:SI 2 "const_int_operand" "")) 3))
4406 (const_int 0)))
4407 (clobber (match_scratch:SI 3 ""))]
4408 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4409 [(set (match_dup 3)
4410 (zero_extend:SI (subreg:QI
4411 (lshiftrt:SI (match_dup 1)
4412 (match_dup 2)) 3)))
4413 (set (match_dup 0)
4414 (compare:CC (match_dup 3)
4415 (const_int 0)))]
4416 "")
4418 (define_insn "*lshiftrt_internal3le"
4419 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4420 (compare:CC
4421 (zero_extend:SI
4422 (subreg:QI
4423 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4424 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4425 (const_int 0)))
4426 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4427 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4428 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4429 "@
4430 rlwinm. %0,%1,%s2,0xff
4431 #"
4432 [(set_attr "type" "shift")
4433 (set_attr "dot" "yes")
4434 (set_attr "length" "4,8")])
4436 (define_insn "*lshiftrt_internal3be"
4437 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4438 (compare:CC
4439 (zero_extend:SI
4440 (subreg:QI
4441 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4442 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4443 (const_int 0)))
4444 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4445 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4446 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4447 "@
4448 rlwinm. %0,%1,%s2,0xff
4449 #"
4450 [(set_attr "type" "shift")
4451 (set_attr "dot" "yes")
4452 (set_attr "length" "4,8")])
4454 (define_split
4455 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4456 (compare:CC
4457 (zero_extend:SI
4458 (subreg:QI
4459 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4460 (match_operand:SI 2 "const_int_operand" "")) 0))
4461 (const_int 0)))
4462 (set (match_operand:SI 0 "gpc_reg_operand" "")
4463 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4464 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4465 [(set (match_dup 0)
4466 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4467 (set (match_dup 3)
4468 (compare:CC (match_dup 0)
4469 (const_int 0)))]
4470 "")
4472 (define_split
4473 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4474 (compare:CC
4475 (zero_extend:SI
4476 (subreg:QI
4477 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4478 (match_operand:SI 2 "const_int_operand" "")) 3))
4479 (const_int 0)))
4480 (set (match_operand:SI 0 "gpc_reg_operand" "")
4481 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4482 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4483 [(set (match_dup 0)
4484 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4485 (set (match_dup 3)
4486 (compare:CC (match_dup 0)
4487 (const_int 0)))]
4488 "")
4490 (define_insn "*lshiftrt_internal4le"
4491 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4492 (zero_extend:SI
4493 (subreg:HI
4494 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4495 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4496 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4497 "rlwinm %0,%1,%s2,0xffff"
4498 [(set_attr "type" "shift")])
4500 (define_insn "*lshiftrt_internal4be"
4501 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4502 (zero_extend:SI
4503 (subreg:HI
4504 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4505 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4506 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4507 "rlwinm %0,%1,%s2,0xffff"
4508 [(set_attr "type" "shift")])
4510 (define_insn "*lshiftrt_internal5le"
4511 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4512 (compare:CC
4513 (zero_extend:SI
4514 (subreg:HI
4515 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4516 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4517 (const_int 0)))
4518 (clobber (match_scratch:SI 3 "=r,r"))]
4519 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4520 "@
4521 rlwinm. %3,%1,%s2,0xffff
4522 #"
4523 [(set_attr "type" "shift")
4524 (set_attr "dot" "yes")
4525 (set_attr "length" "4,8")])
4527 (define_insn "*lshiftrt_internal5be"
4528 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4529 (compare:CC
4530 (zero_extend:SI
4531 (subreg:HI
4532 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4533 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4534 (const_int 0)))
4535 (clobber (match_scratch:SI 3 "=r,r"))]
4536 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4537 "@
4538 rlwinm. %3,%1,%s2,0xffff
4539 #"
4540 [(set_attr "type" "shift")
4541 (set_attr "dot" "yes")
4542 (set_attr "length" "4,8")])
4544 (define_split
4545 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4546 (compare:CC
4547 (zero_extend:SI
4548 (subreg:HI
4549 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4550 (match_operand:SI 2 "const_int_operand" "")) 0))
4551 (const_int 0)))
4552 (clobber (match_scratch:SI 3 ""))]
4553 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4554 [(set (match_dup 3)
4555 (zero_extend:SI (subreg:HI
4556 (lshiftrt:SI (match_dup 1)
4557 (match_dup 2)) 0)))
4558 (set (match_dup 0)
4559 (compare:CC (match_dup 3)
4560 (const_int 0)))]
4561 "")
4563 (define_split
4564 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4565 (compare:CC
4566 (zero_extend:SI
4567 (subreg:HI
4568 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4569 (match_operand:SI 2 "const_int_operand" "")) 2))
4570 (const_int 0)))
4571 (clobber (match_scratch:SI 3 ""))]
4572 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4573 [(set (match_dup 3)
4574 (zero_extend:SI (subreg:HI
4575 (lshiftrt:SI (match_dup 1)
4576 (match_dup 2)) 2)))
4577 (set (match_dup 0)
4578 (compare:CC (match_dup 3)
4579 (const_int 0)))]
4580 "")
4582 (define_insn "*lshiftrt_internal5le"
4583 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4584 (compare:CC
4585 (zero_extend:SI
4586 (subreg:HI
4587 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4588 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4589 (const_int 0)))
4590 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4591 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4592 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4593 "@
4594 rlwinm. %0,%1,%s2,0xffff
4595 #"
4596 [(set_attr "type" "shift")
4597 (set_attr "dot" "yes")
4598 (set_attr "length" "4,8")])
4600 (define_insn "*lshiftrt_internal5be"
4601 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4602 (compare:CC
4603 (zero_extend:SI
4604 (subreg:HI
4605 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4606 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4607 (const_int 0)))
4608 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4609 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4610 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4611 "@
4612 rlwinm. %0,%1,%s2,0xffff
4613 #"
4614 [(set_attr "type" "shift")
4615 (set_attr "dot" "yes")
4616 (set_attr "length" "4,8")])
4618 (define_split
4619 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4620 (compare:CC
4621 (zero_extend:SI
4622 (subreg:HI
4623 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4624 (match_operand:SI 2 "const_int_operand" "")) 0))
4625 (const_int 0)))
4626 (set (match_operand:SI 0 "gpc_reg_operand" "")
4627 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4628 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4629 [(set (match_dup 0)
4630 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4631 (set (match_dup 3)
4632 (compare:CC (match_dup 0)
4633 (const_int 0)))]
4634 "")
4636 (define_split
4637 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4638 (compare:CC
4639 (zero_extend:SI
4640 (subreg:HI
4641 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4642 (match_operand:SI 2 "const_int_operand" "")) 2))
4643 (const_int 0)))
4644 (set (match_operand:SI 0 "gpc_reg_operand" "")
4645 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4646 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4647 [(set (match_dup 0)
4648 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4649 (set (match_dup 3)
4650 (compare:CC (match_dup 0)
4651 (const_int 0)))]
4652 "")
4655 (define_expand "ashr<mode>3"
4656 [(parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4657 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
4658 (match_operand:SI 2 "reg_or_cint_operand" "")))
4659 (clobber (reg:GPR CA_REGNO))])]
4660 ""
4661 {
4662 /* The generic code does not generate optimal code for the low word
4663 (it should be a rlwimi and a rot). Until we have target code to
4664 solve this generically, keep this expander. */
4666 if (<MODE>mode == DImode && !TARGET_POWERPC64)
4667 {
4668 if (CONST_INT_P (operands[2]))
4669 {
4670 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
4671 DONE;
4672 }
4673 else
4674 FAIL;
4675 }
4676 })
4678 (define_insn "*ashr<mode>3"
4679 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4680 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4681 (match_operand:SI 2 "reg_or_cint_operand" "rn")))
4682 (clobber (reg:GPR CA_REGNO))]
4683 ""
4684 "sra<wd>%I2 %0,%1,%<hH>2"
4685 [(set_attr "type" "shift")
4686 (set_attr "maybe_var_shift" "yes")])
4688 (define_insn "*ashrsi3_64"
4689 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4690 (sign_extend:DI
4691 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4692 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))
4693 (clobber (reg:SI CA_REGNO))]
4694 "TARGET_POWERPC64"
4695 "sraw%I2 %0,%1,%h2"
4696 [(set_attr "type" "shift")
4697 (set_attr "maybe_var_shift" "yes")])
4699 (define_insn_and_split "*ashr<mode>3_dot"
4700 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4701 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4702 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4703 (const_int 0)))
4704 (clobber (match_scratch:GPR 0 "=r,r"))
4705 (clobber (reg:GPR CA_REGNO))]
4706 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4707 "@
4708 sra<wd>%I2. %0,%1,%<hH>2
4709 #"
4710 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4711 [(parallel [(set (match_dup 0)
4712 (ashiftrt:GPR (match_dup 1)
4713 (match_dup 2)))
4714 (clobber (reg:GPR CA_REGNO))])
4715 (set (match_dup 3)
4716 (compare:CC (match_dup 0)
4717 (const_int 0)))]
4718 ""
4719 [(set_attr "type" "shift")
4720 (set_attr "maybe_var_shift" "yes")
4721 (set_attr "dot" "yes")
4722 (set_attr "length" "4,8")])
4724 (define_insn_and_split "*ashr<mode>3_dot2"
4725 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4726 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4727 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4728 (const_int 0)))
4729 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4730 (ashiftrt:GPR (match_dup 1)
4731 (match_dup 2)))
4732 (clobber (reg:GPR CA_REGNO))]
4733 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4734 "@
4735 sra<wd>%I2. %0,%1,%<hH>2
4736 #"
4737 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4738 [(parallel [(set (match_dup 0)
4739 (ashiftrt:GPR (match_dup 1)
4740 (match_dup 2)))
4741 (clobber (reg:GPR CA_REGNO))])
4742 (set (match_dup 3)
4743 (compare:CC (match_dup 0)
4744 (const_int 0)))]
4745 ""
4746 [(set_attr "type" "shift")
4747 (set_attr "maybe_var_shift" "yes")
4748 (set_attr "dot" "yes")
4749 (set_attr "length" "4,8")])
4750 \f
4751 ;; Builtins to replace a division to generate FRE reciprocal estimate
4752 ;; instructions and the necessary fixup instructions
4753 (define_expand "recip<mode>3"
4754 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4755 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4756 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4757 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4758 {
4759 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4760 DONE;
4761 })
4763 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4764 ;; hardware division. This is only done before register allocation and with
4765 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4766 (define_split
4767 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4768 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4769 (match_operand 2 "gpc_reg_operand" "")))]
4770 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4771 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4772 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4773 [(const_int 0)]
4774 {
4775 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4776 DONE;
4777 })
4779 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4780 ;; appropriate fixup.
4781 (define_expand "rsqrt<mode>2"
4782 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4783 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4784 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4785 {
4786 rs6000_emit_swrsqrt (operands[0], operands[1]);
4787 DONE;
4788 })
4789 \f
4790 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
4791 ;; modes here, and also add in conditional vsx/power8-vector support to access
4792 ;; values in the traditional Altivec registers if the appropriate
4793 ;; -mupper-regs-{df,sf} option is enabled.
4795 (define_expand "abs<mode>2"
4796 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4797 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4798 "TARGET_<MODE>_INSN"
4799 "")
4801 (define_insn "*abs<mode>2_fpr"
4802 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4803 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4804 "TARGET_<MODE>_FPR"
4805 "@
4806 fabs %0,%1
4807 xsabsdp %x0,%x1"
4808 [(set_attr "type" "fp")
4809 (set_attr "fp_type" "fp_addsub_<Fs>")])
4811 (define_insn "*nabs<mode>2_fpr"
4812 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4813 (neg:SFDF
4814 (abs:SFDF
4815 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
4816 "TARGET_<MODE>_FPR"
4817 "@
4818 fnabs %0,%1
4819 xsnabsdp %x0,%x1"
4820 [(set_attr "type" "fp")
4821 (set_attr "fp_type" "fp_addsub_<Fs>")])
4823 (define_expand "neg<mode>2"
4824 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4825 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4826 "TARGET_<MODE>_INSN"
4827 "")
4829 (define_insn "*neg<mode>2_fpr"
4830 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4831 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4832 "TARGET_<MODE>_FPR"
4833 "@
4834 fneg %0,%1
4835 xsnegdp %x0,%x1"
4836 [(set_attr "type" "fp")
4837 (set_attr "fp_type" "fp_addsub_<Fs>")])
4839 (define_expand "add<mode>3"
4840 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4841 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4842 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4843 "TARGET_<MODE>_INSN"
4844 "")
4846 (define_insn "*add<mode>3_fpr"
4847 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4848 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4849 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4850 "TARGET_<MODE>_FPR"
4851 "@
4852 fadd<Ftrad> %0,%1,%2
4853 xsadd<Fvsx> %x0,%x1,%x2"
4854 [(set_attr "type" "fp")
4855 (set_attr "fp_type" "fp_addsub_<Fs>")])
4857 (define_expand "sub<mode>3"
4858 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4859 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4860 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4861 "TARGET_<MODE>_INSN"
4862 "")
4864 (define_insn "*sub<mode>3_fpr"
4865 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4866 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4867 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4868 "TARGET_<MODE>_FPR"
4869 "@
4870 fsub<Ftrad> %0,%1,%2
4871 xssub<Fvsx> %x0,%x1,%x2"
4872 [(set_attr "type" "fp")
4873 (set_attr "fp_type" "fp_addsub_<Fs>")])
4875 (define_expand "mul<mode>3"
4876 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4877 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4878 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4879 "TARGET_<MODE>_INSN"
4880 "")
4882 (define_insn "*mul<mode>3_fpr"
4883 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4884 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4885 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4886 "TARGET_<MODE>_FPR"
4887 "@
4888 fmul<Ftrad> %0,%1,%2
4889 xsmul<Fvsx> %x0,%x1,%x2"
4890 [(set_attr "type" "dmul")
4891 (set_attr "fp_type" "fp_mul_<Fs>")])
4893 (define_expand "div<mode>3"
4894 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4895 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4896 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4897 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
4898 "")
4900 (define_insn "*div<mode>3_fpr"
4901 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4902 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4903 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4904 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
4905 "@
4906 fdiv<Ftrad> %0,%1,%2
4907 xsdiv<Fvsx> %x0,%x1,%x2"
4908 [(set_attr "type" "<Fs>div")
4909 (set_attr "fp_type" "fp_div_<Fs>")])
4911 (define_insn "sqrt<mode>2"
4912 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4913 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4914 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
4915 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
4916 "@
4917 fsqrt<Ftrad> %0,%1
4918 xssqrt<Fvsx> %x0,%x1"
4919 [(set_attr "type" "<Fs>sqrt")
4920 (set_attr "fp_type" "fp_sqrt_<Fs>")])
4922 ;; Floating point reciprocal approximation
4923 (define_insn "fre<Fs>"
4924 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4925 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4926 UNSPEC_FRES))]
4927 "TARGET_<FFRE>"
4928 "@
4929 fre<Ftrad> %0,%1
4930 xsre<Fvsx> %x0,%x1"
4931 [(set_attr "type" "fp")])
4933 (define_insn "*rsqrt<mode>2"
4934 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4935 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4936 UNSPEC_RSQRT))]
4937 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4938 "@
4939 frsqrte<Ftrad> %0,%1
4940 xsrsqrte<Fvsx> %x0,%x1"
4941 [(set_attr "type" "fp")])
4943 ;; Floating point comparisons
4944 (define_insn "*cmp<mode>_fpr"
4945 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
4946 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4947 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4948 "TARGET_<MODE>_FPR"
4949 "@
4950 fcmpu %0,%1,%2
4951 xscmpudp %0,%x1,%x2"
4952 [(set_attr "type" "fpcompare")])
4954 ;; Floating point conversions
4955 (define_expand "extendsfdf2"
4956 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4957 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4958 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4959 "")
4961 (define_insn_and_split "*extendsfdf2_fpr"
4962 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu")
4963 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
4964 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4965 "@
4966 #
4967 fmr %0,%1
4968 lfs%U1%X1 %0,%1
4969 #
4970 xxlor %x0,%x1,%x1
4971 lxsspx %x0,%y1"
4972 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4973 [(const_int 0)]
4974 {
4975 emit_note (NOTE_INSN_DELETED);
4976 DONE;
4977 }
4978 [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
4980 (define_expand "truncdfsf2"
4981 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4982 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4983 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4984 "")
4986 (define_insn "*truncdfsf2_fpr"
4987 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4988 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4989 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4990 "frsp %0,%1"
4991 [(set_attr "type" "fp")])
4993 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
4994 ;; builtins.c and optabs.c that are not correct for IBM long double
4995 ;; when little-endian.
4996 (define_expand "signbittf2"
4997 [(set (match_dup 2)
4998 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
4999 (set (match_dup 3)
5000 (subreg:DI (match_dup 2) 0))
5001 (set (match_dup 4)
5002 (match_dup 5))
5003 (set (match_operand:SI 0 "gpc_reg_operand" "")
5004 (match_dup 6))]
5005 "!TARGET_IEEEQUAD
5006 && TARGET_HARD_FLOAT
5007 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5008 && TARGET_LONG_DOUBLE_128"
5009 {
5010 operands[2] = gen_reg_rtx (DFmode);
5011 operands[3] = gen_reg_rtx (DImode);
5012 if (TARGET_POWERPC64)
5013 {
5014 operands[4] = gen_reg_rtx (DImode);
5015 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5016 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5017 WORDS_BIG_ENDIAN ? 4 : 0);
5018 }
5019 else
5020 {
5021 operands[4] = gen_reg_rtx (SImode);
5022 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5023 WORDS_BIG_ENDIAN ? 0 : 4);
5024 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5025 }
5026 })
5028 (define_expand "copysign<mode>3"
5029 [(set (match_dup 3)
5030 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5031 (set (match_dup 4)
5032 (neg:SFDF (abs:SFDF (match_dup 1))))
5033 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5034 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5035 (match_dup 5))
5036 (match_dup 3)
5037 (match_dup 4)))]
5038 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5039 && ((TARGET_PPC_GFXOPT
5040 && !HONOR_NANS (<MODE>mode)
5041 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5042 || TARGET_CMPB
5043 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5044 {
5045 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5046 {
5047 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5048 operands[2]));
5049 DONE;
5050 }
5052 operands[3] = gen_reg_rtx (<MODE>mode);
5053 operands[4] = gen_reg_rtx (<MODE>mode);
5054 operands[5] = CONST0_RTX (<MODE>mode);
5055 })
5057 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5058 ;; compiler from optimizing -0.0
5059 (define_insn "copysign<mode>3_fcpsgn"
5060 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5061 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5062 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5063 UNSPEC_COPYSIGN))]
5064 "TARGET_<MODE>_FPR && TARGET_CMPB"
5065 "@
5066 fcpsgn %0,%2,%1
5067 xscpsgndp %x0,%x2,%x1"
5068 [(set_attr "type" "fp")])
5070 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5071 ;; fsel instruction and some auxiliary computations. Then we just have a
5072 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5073 ;; combine.
5074 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5075 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5076 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5077 ;; define_splits to make them if made by combine. On VSX machines we have the
5078 ;; min/max instructions.
5079 ;;
5080 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5081 ;; to allow either DF/SF to use only traditional registers.
5083 (define_expand "smax<mode>3"
5084 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5085 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5086 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5087 (match_dup 1)
5088 (match_dup 2)))]
5089 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5090 {
5091 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5092 DONE;
5093 })
5095 (define_insn "*smax<mode>3_vsx"
5096 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5097 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5098 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5099 "TARGET_<MODE>_FPR && TARGET_VSX"
5100 "xsmaxdp %x0,%x1,%x2"
5101 [(set_attr "type" "fp")])
5103 (define_expand "smin<mode>3"
5104 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5105 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5106 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5107 (match_dup 2)
5108 (match_dup 1)))]
5109 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5110 {
5111 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5112 DONE;
5113 })
5115 (define_insn "*smin<mode>3_vsx"
5116 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5117 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5118 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5119 "TARGET_<MODE>_FPR && TARGET_VSX"
5120 "xsmindp %x0,%x1,%x2"
5121 [(set_attr "type" "fp")])
5123 (define_split
5124 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5125 (match_operator:SFDF 3 "min_max_operator"
5126 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5127 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5128 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5129 && !TARGET_VSX"
5130 [(const_int 0)]
5131 {
5132 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5133 operands[2]);
5134 DONE;
5135 })
5137 (define_split
5138 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5139 (match_operator:SF 3 "min_max_operator"
5140 [(match_operand:SF 1 "gpc_reg_operand" "")
5141 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5142 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5143 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5144 [(const_int 0)]
5145 "
5146 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5147 operands[1], operands[2]);
5148 DONE;
5149 }")
5151 (define_expand "mov<mode>cc"
5152 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5153 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5154 (match_operand:GPR 2 "gpc_reg_operand" "")
5155 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5156 "TARGET_ISEL<sel>"
5157 "
5158 {
5159 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5160 DONE;
5161 else
5162 FAIL;
5163 }")
5165 ;; We use the BASE_REGS for the isel input operands because, if rA is
5166 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5167 ;; because we may switch the operands and rB may end up being rA.
5168 ;;
5169 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5170 ;; leave out the mode in operand 4 and use one pattern, but reload can
5171 ;; change the mode underneath our feet and then gets confused trying
5172 ;; to reload the value.
5173 (define_insn "isel_signed_<mode>"
5174 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5175 (if_then_else:GPR
5176 (match_operator 1 "scc_comparison_operator"
5177 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5178 (const_int 0)])
5179 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5180 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5181 "TARGET_ISEL<sel>"
5182 "*
5183 { return output_isel (operands); }"
5184 [(set_attr "type" "isel")
5185 (set_attr "length" "4")])
5187 (define_insn "isel_unsigned_<mode>"
5188 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5189 (if_then_else:GPR
5190 (match_operator 1 "scc_comparison_operator"
5191 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5192 (const_int 0)])
5193 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5194 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5195 "TARGET_ISEL<sel>"
5196 "*
5197 { return output_isel (operands); }"
5198 [(set_attr "type" "isel")
5199 (set_attr "length" "4")])
5201 ;; These patterns can be useful for combine; they let combine know that
5202 ;; isel can handle reversed comparisons so long as the operands are
5203 ;; registers.
5205 (define_insn "*isel_reversed_signed_<mode>"
5206 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5207 (if_then_else:GPR
5208 (match_operator 1 "scc_rev_comparison_operator"
5209 [(match_operand:CC 4 "cc_reg_operand" "y")
5210 (const_int 0)])
5211 (match_operand:GPR 2 "gpc_reg_operand" "b")
5212 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5213 "TARGET_ISEL<sel>"
5214 "*
5215 { return output_isel (operands); }"
5216 [(set_attr "type" "isel")
5217 (set_attr "length" "4")])
5219 (define_insn "*isel_reversed_unsigned_<mode>"
5220 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5221 (if_then_else:GPR
5222 (match_operator 1 "scc_rev_comparison_operator"
5223 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5224 (const_int 0)])
5225 (match_operand:GPR 2 "gpc_reg_operand" "b")
5226 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5227 "TARGET_ISEL<sel>"
5228 "*
5229 { return output_isel (operands); }"
5230 [(set_attr "type" "isel")
5231 (set_attr "length" "4")])
5233 (define_expand "movsfcc"
5234 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5235 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5236 (match_operand:SF 2 "gpc_reg_operand" "")
5237 (match_operand:SF 3 "gpc_reg_operand" "")))]
5238 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5239 "
5240 {
5241 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5242 DONE;
5243 else
5244 FAIL;
5245 }")
5247 (define_insn "*fselsfsf4"
5248 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5249 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5250 (match_operand:SF 4 "zero_fp_constant" "F"))
5251 (match_operand:SF 2 "gpc_reg_operand" "f")
5252 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5253 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5254 "fsel %0,%1,%2,%3"
5255 [(set_attr "type" "fp")])
5257 (define_insn "*fseldfsf4"
5258 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5259 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5260 (match_operand:DF 4 "zero_fp_constant" "F"))
5261 (match_operand:SF 2 "gpc_reg_operand" "f")
5262 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5263 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5264 "fsel %0,%1,%2,%3"
5265 [(set_attr "type" "fp")])
5267 ;; The conditional move instructions allow us to perform max and min
5268 ;; operations even when
5270 (define_split
5271 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5272 (match_operator:DF 3 "min_max_operator"
5273 [(match_operand:DF 1 "gpc_reg_operand" "")
5274 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5275 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5276 && !flag_trapping_math"
5277 [(const_int 0)]
5278 "
5279 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5280 operands[1], operands[2]);
5281 DONE;
5282 }")
5284 (define_expand "movdfcc"
5285 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5286 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5287 (match_operand:DF 2 "gpc_reg_operand" "")
5288 (match_operand:DF 3 "gpc_reg_operand" "")))]
5289 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5290 "
5291 {
5292 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5293 DONE;
5294 else
5295 FAIL;
5296 }")
5298 (define_insn "*fseldfdf4"
5299 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5300 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5301 (match_operand:DF 4 "zero_fp_constant" "F"))
5302 (match_operand:DF 2 "gpc_reg_operand" "d")
5303 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5304 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5305 "fsel %0,%1,%2,%3"
5306 [(set_attr "type" "fp")])
5308 (define_insn "*fselsfdf4"
5309 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5310 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5311 (match_operand:SF 4 "zero_fp_constant" "F"))
5312 (match_operand:DF 2 "gpc_reg_operand" "d")
5313 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5314 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5315 "fsel %0,%1,%2,%3"
5316 [(set_attr "type" "fp")])
5317 \f
5318 ;; Conversions to and from floating-point.
5320 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5321 ; don't want to support putting SImode in FPR registers.
5322 (define_insn "lfiwax"
5323 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5324 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5325 UNSPEC_LFIWAX))]
5326 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5327 "@
5328 lfiwax %0,%y1
5329 lxsiwax %x0,%y1
5330 mtvsrwa %x0,%1"
5331 [(set_attr "type" "fpload,fpload,mffgpr")])
5333 ; This split must be run before register allocation because it allocates the
5334 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5335 ; it earlier to allow for the combiner to merge insns together where it might
5336 ; not be needed and also in case the insns are deleted as dead code.
5338 (define_insn_and_split "floatsi<mode>2_lfiwax"
5339 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
5340 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5341 (clobber (match_scratch:DI 2 "=wj"))]
5342 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5343 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5344 "#"
5345 ""
5346 [(pc)]
5347 "
5348 {
5349 rtx dest = operands[0];
5350 rtx src = operands[1];
5351 rtx tmp;
5353 if (!MEM_P (src) && TARGET_POWERPC64
5354 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5355 tmp = convert_to_mode (DImode, src, false);
5356 else
5357 {
5358 tmp = operands[2];
5359 if (GET_CODE (tmp) == SCRATCH)
5360 tmp = gen_reg_rtx (DImode);
5361 if (MEM_P (src))
5362 {
5363 src = rs6000_address_for_fpconvert (src);
5364 emit_insn (gen_lfiwax (tmp, src));
5365 }
5366 else
5367 {
5368 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5369 emit_move_insn (stack, src);
5370 emit_insn (gen_lfiwax (tmp, stack));
5371 }
5372 }
5373 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5374 DONE;
5375 }"
5376 [(set_attr "length" "12")
5377 (set_attr "type" "fpload")])
5379 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5380 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fa>")
5381 (float:SFDF
5382 (sign_extend:DI
5383 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5384 (clobber (match_scratch:DI 2 "=0,d"))]
5385 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5386 && <SI_CONVERT_FP>"
5387 "#"
5388 ""
5389 [(pc)]
5390 "
5391 {
5392 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5393 if (GET_CODE (operands[2]) == SCRATCH)
5394 operands[2] = gen_reg_rtx (DImode);
5395 emit_insn (gen_lfiwax (operands[2], operands[1]));
5396 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5397 DONE;
5398 }"
5399 [(set_attr "length" "8")
5400 (set_attr "type" "fpload")])
5402 (define_insn "lfiwzx"
5403 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5404 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5405 UNSPEC_LFIWZX))]
5406 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5407 "@
5408 lfiwzx %0,%y1
5409 lxsiwzx %x0,%y1
5410 mtvsrwz %x0,%1"
5411 [(set_attr "type" "fpload,fpload,mftgpr")])
5413 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5414 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
5415 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5416 (clobber (match_scratch:DI 2 "=wj"))]
5417 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5418 && <SI_CONVERT_FP>"
5419 "#"
5420 ""
5421 [(pc)]
5422 "
5423 {
5424 rtx dest = operands[0];
5425 rtx src = operands[1];
5426 rtx tmp;
5428 if (!MEM_P (src) && TARGET_POWERPC64
5429 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5430 tmp = convert_to_mode (DImode, src, true);
5431 else
5432 {
5433 tmp = operands[2];
5434 if (GET_CODE (tmp) == SCRATCH)
5435 tmp = gen_reg_rtx (DImode);
5436 if (MEM_P (src))
5437 {
5438 src = rs6000_address_for_fpconvert (src);
5439 emit_insn (gen_lfiwzx (tmp, src));
5440 }
5441 else
5442 {
5443 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5444 emit_move_insn (stack, src);
5445 emit_insn (gen_lfiwzx (tmp, stack));
5446 }
5447 }
5448 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5449 DONE;
5450 }"
5451 [(set_attr "length" "12")
5452 (set_attr "type" "fpload")])
5454 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5455 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fa>")
5456 (unsigned_float:SFDF
5457 (zero_extend:DI
5458 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5459 (clobber (match_scratch:DI 2 "=0,d"))]
5460 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5461 && <SI_CONVERT_FP>"
5462 "#"
5463 ""
5464 [(pc)]
5465 "
5466 {
5467 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5468 if (GET_CODE (operands[2]) == SCRATCH)
5469 operands[2] = gen_reg_rtx (DImode);
5470 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5471 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5472 DONE;
5473 }"
5474 [(set_attr "length" "8")
5475 (set_attr "type" "fpload")])
5477 ; For each of these conversions, there is a define_expand, a define_insn
5478 ; with a '#' template, and a define_split (with C code). The idea is
5479 ; to allow constant folding with the template of the define_insn,
5480 ; then to have the insns split later (between sched1 and final).
5482 (define_expand "floatsidf2"
5483 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5484 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5485 (use (match_dup 2))
5486 (use (match_dup 3))
5487 (clobber (match_dup 4))
5488 (clobber (match_dup 5))
5489 (clobber (match_dup 6))])]
5490 "TARGET_HARD_FLOAT
5491 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5492 "
5493 {
5494 if (TARGET_E500_DOUBLE)
5495 {
5496 if (!REG_P (operands[1]))
5497 operands[1] = force_reg (SImode, operands[1]);
5498 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5499 DONE;
5500 }
5501 else if (TARGET_LFIWAX && TARGET_FCFID)
5502 {
5503 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5504 DONE;
5505 }
5506 else if (TARGET_FCFID)
5507 {
5508 rtx dreg = operands[1];
5509 if (!REG_P (dreg))
5510 dreg = force_reg (SImode, dreg);
5511 dreg = convert_to_mode (DImode, dreg, false);
5512 emit_insn (gen_floatdidf2 (operands[0], dreg));
5513 DONE;
5514 }
5516 if (!REG_P (operands[1]))
5517 operands[1] = force_reg (SImode, operands[1]);
5518 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5519 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5520 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5521 operands[5] = gen_reg_rtx (DFmode);
5522 operands[6] = gen_reg_rtx (SImode);
5523 }")
5525 (define_insn_and_split "*floatsidf2_internal"
5526 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5527 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5528 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5529 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5530 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5531 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5532 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5533 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5534 "#"
5535 ""
5536 [(pc)]
5537 "
5538 {
5539 rtx lowword, highword;
5540 gcc_assert (MEM_P (operands[4]));
5541 highword = adjust_address (operands[4], SImode, 0);
5542 lowword = adjust_address (operands[4], SImode, 4);
5543 if (! WORDS_BIG_ENDIAN)
5544 {
5545 rtx tmp;
5546 tmp = highword; highword = lowword; lowword = tmp;
5547 }
5549 emit_insn (gen_xorsi3 (operands[6], operands[1],
5550 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5551 emit_move_insn (lowword, operands[6]);
5552 emit_move_insn (highword, operands[2]);
5553 emit_move_insn (operands[5], operands[4]);
5554 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5555 DONE;
5556 }"
5557 [(set_attr "length" "24")
5558 (set_attr "type" "fp")])
5560 ;; If we don't have a direct conversion to single precision, don't enable this
5561 ;; conversion for 32-bit without fast math, because we don't have the insn to
5562 ;; generate the fixup swizzle to avoid double rounding problems.
5563 (define_expand "floatunssisf2"
5564 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5565 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5566 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5567 && (!TARGET_FPRS
5568 || (TARGET_FPRS
5569 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5570 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5571 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5572 "
5573 {
5574 if (!TARGET_FPRS)
5575 {
5576 if (!REG_P (operands[1]))
5577 operands[1] = force_reg (SImode, operands[1]);
5578 }
5579 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5580 {
5581 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5582 DONE;
5583 }
5584 else
5585 {
5586 rtx dreg = operands[1];
5587 if (!REG_P (dreg))
5588 dreg = force_reg (SImode, dreg);
5589 dreg = convert_to_mode (DImode, dreg, true);
5590 emit_insn (gen_floatdisf2 (operands[0], dreg));
5591 DONE;
5592 }
5593 }")
5595 (define_expand "floatunssidf2"
5596 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5597 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5598 (use (match_dup 2))
5599 (use (match_dup 3))
5600 (clobber (match_dup 4))
5601 (clobber (match_dup 5))])]
5602 "TARGET_HARD_FLOAT
5603 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5604 "
5605 {
5606 if (TARGET_E500_DOUBLE)
5607 {
5608 if (!REG_P (operands[1]))
5609 operands[1] = force_reg (SImode, operands[1]);
5610 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5611 DONE;
5612 }
5613 else if (TARGET_LFIWZX && TARGET_FCFID)
5614 {
5615 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5616 DONE;
5617 }
5618 else if (TARGET_FCFID)
5619 {
5620 rtx dreg = operands[1];
5621 if (!REG_P (dreg))
5622 dreg = force_reg (SImode, dreg);
5623 dreg = convert_to_mode (DImode, dreg, true);
5624 emit_insn (gen_floatdidf2 (operands[0], dreg));
5625 DONE;
5626 }
5628 if (!REG_P (operands[1]))
5629 operands[1] = force_reg (SImode, operands[1]);
5630 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5631 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5632 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5633 operands[5] = gen_reg_rtx (DFmode);
5634 }")
5636 (define_insn_and_split "*floatunssidf2_internal"
5637 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5638 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5639 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5640 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5641 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5642 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5643 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5644 && !(TARGET_FCFID && TARGET_POWERPC64)"
5645 "#"
5646 ""
5647 [(pc)]
5648 "
5649 {
5650 rtx lowword, highword;
5651 gcc_assert (MEM_P (operands[4]));
5652 highword = adjust_address (operands[4], SImode, 0);
5653 lowword = adjust_address (operands[4], SImode, 4);
5654 if (! WORDS_BIG_ENDIAN)
5655 {
5656 rtx tmp;
5657 tmp = highword; highword = lowword; lowword = tmp;
5658 }
5660 emit_move_insn (lowword, operands[1]);
5661 emit_move_insn (highword, operands[2]);
5662 emit_move_insn (operands[5], operands[4]);
5663 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5664 DONE;
5665 }"
5666 [(set_attr "length" "20")
5667 (set_attr "type" "fp")])
5669 (define_expand "fix_trunc<mode>si2"
5670 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5671 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5672 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5673 "
5674 {
5675 if (!<E500_CONVERT>)
5676 {
5677 rtx tmp, stack;
5679 if (TARGET_STFIWX)
5680 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5681 else
5682 {
5683 tmp = gen_reg_rtx (DImode);
5684 stack = rs6000_allocate_stack_temp (DImode, true, false);
5685 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5686 tmp, stack));
5687 }
5688 DONE;
5689 }
5690 }")
5692 ; Like the convert to float patterns, this insn must be split before
5693 ; register allocation so that it can allocate the memory slot if it
5694 ; needed
5695 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5696 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5697 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5698 (clobber (match_scratch:DI 2 "=d"))]
5699 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5700 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5701 && TARGET_STFIWX && can_create_pseudo_p ()"
5702 "#"
5703 ""
5704 [(pc)]
5705 {
5706 rtx dest = operands[0];
5707 rtx src = operands[1];
5708 rtx tmp = operands[2];
5710 if (GET_CODE (tmp) == SCRATCH)
5711 tmp = gen_reg_rtx (DImode);
5713 emit_insn (gen_fctiwz_<mode> (tmp, src));
5714 if (MEM_P (dest))
5715 {
5716 dest = rs6000_address_for_fpconvert (dest);
5717 emit_insn (gen_stfiwx (dest, tmp));
5718 DONE;
5719 }
5720 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5721 {
5722 dest = gen_lowpart (DImode, dest);
5723 emit_move_insn (dest, tmp);
5724 DONE;
5725 }
5726 else
5727 {
5728 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5729 emit_insn (gen_stfiwx (stack, tmp));
5730 emit_move_insn (dest, stack);
5731 DONE;
5732 }
5733 }
5734 [(set_attr "length" "12")
5735 (set_attr "type" "fp")])
5737 (define_insn_and_split "fix_trunc<mode>si2_internal"
5738 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5739 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5740 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5741 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5742 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5743 "#"
5744 ""
5745 [(pc)]
5746 "
5747 {
5748 rtx lowword;
5749 gcc_assert (MEM_P (operands[3]));
5750 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5752 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5753 emit_move_insn (operands[3], operands[2]);
5754 emit_move_insn (operands[0], lowword);
5755 DONE;
5756 }"
5757 [(set_attr "length" "16")
5758 (set_attr "type" "fp")])
5760 (define_expand "fix_trunc<mode>di2"
5761 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5762 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5763 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5764 && TARGET_FCFID"
5765 "")
5767 (define_insn "*fix_trunc<mode>di2_fctidz"
5768 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5769 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fa>")))]
5770 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5771 && TARGET_FCFID"
5772 "@
5773 fctidz %0,%1
5774 xscvdpsxds %x0,%x1"
5775 [(set_attr "type" "fp")])
5777 (define_expand "fixuns_trunc<mode>si2"
5778 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5779 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5780 "TARGET_HARD_FLOAT
5781 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5782 || <E500_CONVERT>)"
5783 "
5784 {
5785 if (!<E500_CONVERT>)
5786 {
5787 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5788 DONE;
5789 }
5790 }")
5792 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5793 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5794 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5795 (clobber (match_scratch:DI 2 "=d"))]
5796 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5797 && TARGET_STFIWX && can_create_pseudo_p ()"
5798 "#"
5799 ""
5800 [(pc)]
5801 {
5802 rtx dest = operands[0];
5803 rtx src = operands[1];
5804 rtx tmp = operands[2];
5806 if (GET_CODE (tmp) == SCRATCH)
5807 tmp = gen_reg_rtx (DImode);
5809 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5810 if (MEM_P (dest))
5811 {
5812 dest = rs6000_address_for_fpconvert (dest);
5813 emit_insn (gen_stfiwx (dest, tmp));
5814 DONE;
5815 }
5816 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5817 {
5818 dest = gen_lowpart (DImode, dest);
5819 emit_move_insn (dest, tmp);
5820 DONE;
5821 }
5822 else
5823 {
5824 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5825 emit_insn (gen_stfiwx (stack, tmp));
5826 emit_move_insn (dest, stack);
5827 DONE;
5828 }
5829 }
5830 [(set_attr "length" "12")
5831 (set_attr "type" "fp")])
5833 (define_expand "fixuns_trunc<mode>di2"
5834 [(set (match_operand:DI 0 "register_operand" "")
5835 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5836 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5837 "")
5839 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5840 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5841 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fa>")))]
5842 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5843 && TARGET_FCTIDUZ"
5844 "@
5845 fctiduz %0,%1
5846 xscvdpuxds %x0,%x1"
5847 [(set_attr "type" "fp")])
5849 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5850 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5851 ; because the first makes it clear that operand 0 is not live
5852 ; before the instruction.
5853 (define_insn "fctiwz_<mode>"
5854 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5855 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
5856 UNSPEC_FCTIWZ))]
5857 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5858 "@
5859 fctiwz %0,%1
5860 xscvdpsxws %x0,%x1"
5861 [(set_attr "type" "fp")])
5863 (define_insn "fctiwuz_<mode>"
5864 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5865 (unspec:DI [(unsigned_fix:SI
5866 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
5867 UNSPEC_FCTIWUZ))]
5868 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5869 "@
5870 fctiwuz %0,%1
5871 xscvdpuxws %x0,%x1"
5872 [(set_attr "type" "fp")])
5874 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5875 ;; since the friz instruction does not truncate the value if the floating
5876 ;; point value is < LONG_MIN or > LONG_MAX.
5877 (define_insn "*friz"
5878 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
5879 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
5880 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5881 && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
5882 "@
5883 friz %0,%1
5884 xsrdpiz %x0,%x1"
5885 [(set_attr "type" "fp")])
5887 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5888 ;; load to properly sign extend the value, but at least doing a store, load
5889 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5890 ;; if we have 32-bit memory ops
5891 (define_insn_and_split "*round32<mode>2_fprs"
5892 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5893 (float:SFDF
5894 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5895 (clobber (match_scratch:DI 2 "=d"))
5896 (clobber (match_scratch:DI 3 "=d"))]
5897 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5898 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5899 && can_create_pseudo_p ()"
5900 "#"
5901 ""
5902 [(pc)]
5903 {
5904 rtx dest = operands[0];
5905 rtx src = operands[1];
5906 rtx tmp1 = operands[2];
5907 rtx tmp2 = operands[3];
5908 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5910 if (GET_CODE (tmp1) == SCRATCH)
5911 tmp1 = gen_reg_rtx (DImode);
5912 if (GET_CODE (tmp2) == SCRATCH)
5913 tmp2 = gen_reg_rtx (DImode);
5915 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5916 emit_insn (gen_stfiwx (stack, tmp1));
5917 emit_insn (gen_lfiwax (tmp2, stack));
5918 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5919 DONE;
5920 }
5921 [(set_attr "type" "fpload")
5922 (set_attr "length" "16")])
5924 (define_insn_and_split "*roundu32<mode>2_fprs"
5925 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5926 (unsigned_float:SFDF
5927 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5928 (clobber (match_scratch:DI 2 "=d"))
5929 (clobber (match_scratch:DI 3 "=d"))]
5930 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5931 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
5932 && can_create_pseudo_p ()"
5933 "#"
5934 ""
5935 [(pc)]
5936 {
5937 rtx dest = operands[0];
5938 rtx src = operands[1];
5939 rtx tmp1 = operands[2];
5940 rtx tmp2 = operands[3];
5941 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5943 if (GET_CODE (tmp1) == SCRATCH)
5944 tmp1 = gen_reg_rtx (DImode);
5945 if (GET_CODE (tmp2) == SCRATCH)
5946 tmp2 = gen_reg_rtx (DImode);
5948 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
5949 emit_insn (gen_stfiwx (stack, tmp1));
5950 emit_insn (gen_lfiwzx (tmp2, stack));
5951 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5952 DONE;
5953 }
5954 [(set_attr "type" "fpload")
5955 (set_attr "length" "16")])
5957 ;; No VSX equivalent to fctid
5958 (define_insn "lrint<mode>di2"
5959 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5960 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5961 UNSPEC_FCTID))]
5962 "TARGET_<MODE>_FPR && TARGET_FPRND"
5963 "fctid %0,%1"
5964 [(set_attr "type" "fp")])
5966 (define_insn "btrunc<mode>2"
5967 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5968 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5969 UNSPEC_FRIZ))]
5970 "TARGET_<MODE>_FPR && TARGET_FPRND"
5971 "@
5972 friz %0,%1
5973 xsrdpiz %x0,%x1"
5974 [(set_attr "type" "fp")
5975 (set_attr "fp_type" "fp_addsub_<Fs>")])
5977 (define_insn "ceil<mode>2"
5978 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5979 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5980 UNSPEC_FRIP))]
5981 "TARGET_<MODE>_FPR && TARGET_FPRND"
5982 "@
5983 frip %0,%1
5984 xsrdpip %x0,%x1"
5985 [(set_attr "type" "fp")
5986 (set_attr "fp_type" "fp_addsub_<Fs>")])
5988 (define_insn "floor<mode>2"
5989 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5990 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5991 UNSPEC_FRIM))]
5992 "TARGET_<MODE>_FPR && TARGET_FPRND"
5993 "@
5994 frim %0,%1
5995 xsrdpim %x0,%x1"
5996 [(set_attr "type" "fp")
5997 (set_attr "fp_type" "fp_addsub_<Fs>")])
5999 ;; No VSX equivalent to frin
6000 (define_insn "round<mode>2"
6001 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6002 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6003 UNSPEC_FRIN))]
6004 "TARGET_<MODE>_FPR && TARGET_FPRND"
6005 "frin %0,%1"
6006 [(set_attr "type" "fp")
6007 (set_attr "fp_type" "fp_addsub_<Fs>")])
6009 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6010 (define_insn "stfiwx"
6011 [(set (match_operand:SI 0 "memory_operand" "=Z")
6012 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6013 UNSPEC_STFIWX))]
6014 "TARGET_PPC_GFXOPT"
6015 "stfiwx %1,%y0"
6016 [(set_attr "type" "fpstore")])
6018 ;; If we don't have a direct conversion to single precision, don't enable this
6019 ;; conversion for 32-bit without fast math, because we don't have the insn to
6020 ;; generate the fixup swizzle to avoid double rounding problems.
6021 (define_expand "floatsisf2"
6022 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6023 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6024 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6025 && (!TARGET_FPRS
6026 || (TARGET_FPRS
6027 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6028 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6029 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6030 "
6031 {
6032 if (!TARGET_FPRS)
6033 {
6034 if (!REG_P (operands[1]))
6035 operands[1] = force_reg (SImode, operands[1]);
6036 }
6037 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6038 {
6039 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6040 DONE;
6041 }
6042 else if (TARGET_FCFID && TARGET_LFIWAX)
6043 {
6044 rtx dfreg = gen_reg_rtx (DFmode);
6045 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6046 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6047 DONE;
6048 }
6049 else
6050 {
6051 rtx dreg = operands[1];
6052 if (!REG_P (dreg))
6053 dreg = force_reg (SImode, dreg);
6054 dreg = convert_to_mode (DImode, dreg, false);
6055 emit_insn (gen_floatdisf2 (operands[0], dreg));
6056 DONE;
6057 }
6058 }")
6060 (define_expand "floatdidf2"
6061 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6062 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6063 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6064 "")
6066 (define_insn "*floatdidf2_fpr"
6067 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6068 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6069 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6070 "@
6071 fcfid %0,%1
6072 xscvsxddp %x0,%x1"
6073 [(set_attr "type" "fp")])
6075 ; Allow the combiner to merge source memory operands to the conversion so that
6076 ; the optimizer/register allocator doesn't try to load the value too early in a
6077 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6078 ; hit. We will split after reload to avoid the trip through the GPRs
6080 (define_insn_and_split "*floatdidf2_mem"
6081 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6082 (float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
6083 (clobber (match_scratch:DI 2 "=d,wi"))]
6084 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6085 "#"
6086 "&& reload_completed"
6087 [(set (match_dup 2) (match_dup 1))
6088 (set (match_dup 0) (float:DF (match_dup 2)))]
6089 ""
6090 [(set_attr "length" "8")
6091 (set_attr "type" "fpload")])
6093 (define_expand "floatunsdidf2"
6094 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6095 (unsigned_float:DF
6096 (match_operand:DI 1 "gpc_reg_operand" "")))]
6097 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
6098 "")
6100 (define_insn "*floatunsdidf2_fcfidu"
6101 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6102 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6103 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
6104 "@
6105 fcfidu %0,%1
6106 xscvuxddp %x0,%x1"
6107 [(set_attr "type" "fp")
6108 (set_attr "length" "4")])
6110 (define_insn_and_split "*floatunsdidf2_mem"
6111 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
6112 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
6113 (clobber (match_scratch:DI 2 "=d,wi"))]
6114 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6115 "#"
6116 "&& reload_completed"
6117 [(set (match_dup 2) (match_dup 1))
6118 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6119 ""
6120 [(set_attr "length" "8")
6121 (set_attr "type" "fpload")])
6123 (define_expand "floatdisf2"
6124 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6125 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6126 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6127 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6128 "
6129 {
6130 if (!TARGET_FCFIDS)
6131 {
6132 rtx val = operands[1];
6133 if (!flag_unsafe_math_optimizations)
6134 {
6135 rtx label = gen_label_rtx ();
6136 val = gen_reg_rtx (DImode);
6137 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6138 emit_label (label);
6139 }
6140 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6141 DONE;
6142 }
6143 }")
6145 (define_insn "floatdisf2_fcfids"
6146 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
6147 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6148 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6149 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6150 "@
6151 fcfids %0,%1
6152 xscvsxdsp %x0,%x1"
6153 [(set_attr "type" "fp")])
6155 (define_insn_and_split "*floatdisf2_mem"
6156 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
6157 (float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
6158 (clobber (match_scratch:DI 2 "=d,d,wi"))]
6159 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6160 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6161 "#"
6162 "&& reload_completed"
6163 [(pc)]
6164 "
6165 {
6166 emit_move_insn (operands[2], operands[1]);
6167 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6168 DONE;
6169 }"
6170 [(set_attr "length" "8")])
6172 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6173 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6174 ;; from double rounding.
6175 ;; Instead of creating a new cpu type for two FP operations, just use fp
6176 (define_insn_and_split "floatdisf2_internal1"
6177 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6178 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6179 (clobber (match_scratch:DF 2 "=d"))]
6180 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6181 && !TARGET_FCFIDS"
6182 "#"
6183 "&& reload_completed"
6184 [(set (match_dup 2)
6185 (float:DF (match_dup 1)))
6186 (set (match_dup 0)
6187 (float_truncate:SF (match_dup 2)))]
6188 ""
6189 [(set_attr "length" "8")
6190 (set_attr "type" "fp")])
6192 ;; Twiddles bits to avoid double rounding.
6193 ;; Bits that might be truncated when converting to DFmode are replaced
6194 ;; by a bit that won't be lost at that stage, but is below the SFmode
6195 ;; rounding position.
6196 (define_expand "floatdisf2_internal2"
6197 [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6198 (const_int 53)))
6199 (clobber (reg:DI CA_REGNO))])
6200 (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6201 (const_int 2047)))
6202 (set (match_dup 3) (plus:DI (match_dup 3)
6203 (const_int 1)))
6204 (set (match_dup 0) (plus:DI (match_dup 0)
6205 (const_int 2047)))
6206 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6207 (const_int 2)))
6208 (set (match_dup 0) (ior:DI (match_dup 0)
6209 (match_dup 1)))
6210 (set (match_dup 0) (and:DI (match_dup 0)
6211 (const_int -2048)))
6212 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6213 (label_ref (match_operand:DI 2 "" ""))
6214 (pc)))
6215 (set (match_dup 0) (match_dup 1))]
6216 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6217 && !TARGET_FCFIDS"
6218 "
6219 {
6220 operands[3] = gen_reg_rtx (DImode);
6221 operands[4] = gen_reg_rtx (CCUNSmode);
6222 }")
6224 (define_expand "floatunsdisf2"
6225 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6226 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6227 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6228 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6229 "")
6231 (define_insn "floatunsdisf2_fcfidus"
6232 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wu")
6233 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
6234 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6235 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6236 "@
6237 fcfidus %0,%1
6238 xscvuxdsp %x0,%x1"
6239 [(set_attr "type" "fp")])
6241 (define_insn_and_split "*floatunsdisf2_mem"
6242 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
6243 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
6244 (clobber (match_scratch:DI 2 "=d,d,wi"))]
6245 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6246 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6247 "#"
6248 "&& reload_completed"
6249 [(pc)]
6250 "
6251 {
6252 emit_move_insn (operands[2], operands[1]);
6253 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6254 DONE;
6255 }"
6256 [(set_attr "length" "8")
6257 (set_attr "type" "fpload")])
6258 \f
6259 ;; Define the TImode operations that can be done in a small number
6260 ;; of instructions. The & constraints are to prevent the register
6261 ;; allocator from allocating registers that overlap with the inputs
6262 ;; (for example, having an input in 7,8 and an output in 6,7). We
6263 ;; also allow for the output being the same as one of the inputs.
6265 (define_insn "addti3"
6266 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
6267 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
6268 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
6269 "TARGET_64BIT"
6270 {
6271 if (WORDS_BIG_ENDIAN)
6272 return (GET_CODE (operands[2])) != CONST_INT
6273 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6274 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6275 else
6276 return (GET_CODE (operands[2])) != CONST_INT
6277 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6278 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6279 }
6280 [(set_attr "type" "two")
6281 (set_attr "length" "8")])
6283 (define_insn "subti3"
6284 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6285 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
6286 (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6287 "TARGET_64BIT"
6288 {
6289 if (WORDS_BIG_ENDIAN)
6290 return (GET_CODE (operands[1]) != CONST_INT)
6291 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6292 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6293 else
6294 return (GET_CODE (operands[1]) != CONST_INT)
6295 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6296 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6297 }
6298 [(set_attr "type" "two")
6299 (set_attr "length" "8")])
6302 ;; Define the DImode operations that can be done in a small number
6303 ;; of instructions. The & constraints are to prevent the register
6304 ;; allocator from allocating registers that overlap with the inputs
6305 ;; (for example, having an input in 7,8 and an output in 6,7). We
6306 ;; also allow for the output being the same as one of the inputs.
6308 (define_insn "*adddi3_noppc64"
6309 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6310 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6311 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6312 "! TARGET_POWERPC64"
6313 "*
6314 {
6315 if (WORDS_BIG_ENDIAN)
6316 return (GET_CODE (operands[2])) != CONST_INT
6317 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6318 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6319 else
6320 return (GET_CODE (operands[2])) != CONST_INT
6321 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6322 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6323 }"
6324 [(set_attr "type" "two")
6325 (set_attr "length" "8")])
6327 (define_insn "*subdi3_noppc64"
6328 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6329 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6330 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6331 "! TARGET_POWERPC64"
6332 "*
6333 {
6334 if (WORDS_BIG_ENDIAN)
6335 return (GET_CODE (operands[1]) != CONST_INT)
6336 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6337 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6338 else
6339 return (GET_CODE (operands[1]) != CONST_INT)
6340 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6341 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6342 }"
6343 [(set_attr "type" "two")
6344 (set_attr "length" "8")])
6346 (define_insn "*negdi2_noppc64"
6347 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6348 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6349 "! TARGET_POWERPC64"
6350 "*
6351 {
6352 return (WORDS_BIG_ENDIAN)
6353 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6354 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6355 }"
6356 [(set_attr "type" "two")
6357 (set_attr "length" "8")])
6360 ;; Shift by a variable amount is too complex to be worth open-coding. We
6361 ;; just handle shifts by constants.
6362 (define_insn "ashrdi3_no_power"
6363 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6364 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6365 (match_operand:SI 2 "const_int_operand" "M,i")))
6366 (clobber (reg:SI CA_REGNO))]
6367 "!TARGET_POWERPC64"
6368 {
6369 switch (which_alternative)
6370 {
6371 default:
6372 gcc_unreachable ();
6373 case 0:
6374 if (WORDS_BIG_ENDIAN)
6375 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6376 else
6377 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6378 case 1:
6379 if (WORDS_BIG_ENDIAN)
6380 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6381 else
6382 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6383 }
6384 }
6385 [(set_attr "type" "two,three")
6386 (set_attr "length" "8,12")])
6388 (define_insn "*ashrdisi3_noppc64be"
6389 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6390 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6391 (const_int 32)) 4))]
6392 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6393 "*
6394 {
6395 if (REGNO (operands[0]) == REGNO (operands[1]))
6396 return \"\";
6397 else
6398 return \"mr %0,%1\";
6399 }"
6400 [(set_attr "length" "4")])
6402 \f
6403 ;; PowerPC64 DImode operations.
6405 (define_insn "*rotldi3_internal4"
6406 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6407 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6408 (match_operand:DI 2 "reg_or_cint_operand" "rn"))
6409 (match_operand:DI 3 "mask64_operand" "n")))]
6410 "TARGET_POWERPC64"
6411 "rld%I2c%B3 %0,%1,%H2,%S3"
6412 [(set_attr "type" "shift")
6413 (set_attr "maybe_var_shift" "yes")])
6415 (define_insn "*rotldi3_internal5"
6416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6417 (compare:CC (and:DI
6418 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6419 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6420 (match_operand:DI 3 "mask64_operand" "n,n"))
6421 (const_int 0)))
6422 (clobber (match_scratch:DI 4 "=r,r"))]
6423 "TARGET_64BIT"
6424 "@
6425 rld%I2c%B3. %4,%1,%H2,%S3
6426 #"
6427 [(set_attr "type" "shift")
6428 (set_attr "maybe_var_shift" "yes")
6429 (set_attr "dot" "yes")
6430 (set_attr "length" "4,8")])
6432 (define_split
6433 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6434 (compare:CC (and:DI
6435 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6436 (match_operand:DI 2 "reg_or_cint_operand" ""))
6437 (match_operand:DI 3 "mask64_operand" ""))
6438 (const_int 0)))
6439 (clobber (match_scratch:DI 4 ""))]
6440 "TARGET_POWERPC64 && reload_completed"
6441 [(set (match_dup 4)
6442 (and:DI (rotate:DI (match_dup 1)
6443 (match_dup 2))
6444 (match_dup 3)))
6445 (set (match_dup 0)
6446 (compare:CC (match_dup 4)
6447 (const_int 0)))]
6448 "")
6450 (define_insn "*rotldi3_internal6"
6451 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6452 (compare:CC (and:DI
6453 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6454 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6455 (match_operand:DI 3 "mask64_operand" "n,n"))
6456 (const_int 0)))
6457 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6458 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6459 "TARGET_64BIT"
6460 "@
6461 rld%I2c%B3. %0,%1,%H2,%S3
6462 #"
6463 [(set_attr "type" "shift")
6464 (set_attr "maybe_var_shift" "yes")
6465 (set_attr "dot" "yes")
6466 (set_attr "length" "4,8")])
6468 (define_split
6469 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6470 (compare:CC (and:DI
6471 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6472 (match_operand:DI 2 "reg_or_cint_operand" ""))
6473 (match_operand:DI 3 "mask64_operand" ""))
6474 (const_int 0)))
6475 (set (match_operand:DI 0 "gpc_reg_operand" "")
6476 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6477 "TARGET_POWERPC64 && reload_completed"
6478 [(set (match_dup 0)
6479 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6480 (set (match_dup 4)
6481 (compare:CC (match_dup 0)
6482 (const_int 0)))]
6483 "")
6485 (define_insn "*rotldi3_internal7le"
6486 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6487 (zero_extend:DI
6488 (subreg:QI
6489 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6490 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6491 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6492 "rld%I2cl %0,%1,%H2,56"
6493 [(set_attr "type" "shift")
6494 (set_attr "maybe_var_shift" "yes")])
6496 (define_insn "*rotldi3_internal7be"
6497 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6498 (zero_extend:DI
6499 (subreg:QI
6500 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6501 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
6502 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6503 "rld%I2cl %0,%1,%H2,56"
6504 [(set_attr "type" "shift")
6505 (set_attr "maybe_var_shift" "yes")])
6507 (define_insn "*rotldi3_internal8le"
6508 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6509 (compare:CC (zero_extend:DI
6510 (subreg:QI
6511 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6512 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6513 (const_int 0)))
6514 (clobber (match_scratch:DI 3 "=r,r"))]
6515 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6516 "@
6517 rld%I2cl. %3,%1,%H2,56
6518 #"
6519 [(set_attr "type" "shift")
6520 (set_attr "maybe_var_shift" "yes")
6521 (set_attr "dot" "yes")
6522 (set_attr "length" "4,8")])
6524 (define_insn "*rotldi3_internal8be"
6525 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6526 (compare:CC (zero_extend:DI
6527 (subreg:QI
6528 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6529 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6530 (const_int 0)))
6531 (clobber (match_scratch:DI 3 "=r,r"))]
6532 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6533 "@
6534 rld%I2cl. %3,%1,%H2,56
6535 #"
6536 [(set_attr "type" "shift")
6537 (set_attr "maybe_var_shift" "yes")
6538 (set_attr "dot" "yes")
6539 (set_attr "length" "4,8")])
6541 (define_split
6542 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6543 (compare:CC (zero_extend:DI
6544 (subreg:QI
6545 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6546 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6547 (const_int 0)))
6548 (clobber (match_scratch:DI 3 ""))]
6549 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6550 [(set (match_dup 3)
6551 (zero_extend:DI (subreg:QI
6552 (rotate:DI (match_dup 1)
6553 (match_dup 2)) 0)))
6554 (set (match_dup 0)
6555 (compare:CC (match_dup 3)
6556 (const_int 0)))]
6557 "")
6559 (define_split
6560 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6561 (compare:CC (zero_extend:DI
6562 (subreg:QI
6563 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6564 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6565 (const_int 0)))
6566 (clobber (match_scratch:DI 3 ""))]
6567 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6568 [(set (match_dup 3)
6569 (zero_extend:DI (subreg:QI
6570 (rotate:DI (match_dup 1)
6571 (match_dup 2)) 7)))
6572 (set (match_dup 0)
6573 (compare:CC (match_dup 3)
6574 (const_int 0)))]
6575 "")
6577 (define_insn "*rotldi3_internal9le"
6578 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6579 (compare:CC (zero_extend:DI
6580 (subreg:QI
6581 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6582 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6583 (const_int 0)))
6584 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6585 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6586 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6587 "@
6588 rld%I2cl. %0,%1,%H2,56
6589 #"
6590 [(set_attr "type" "shift")
6591 (set_attr "maybe_var_shift" "yes")
6592 (set_attr "dot" "yes")
6593 (set_attr "length" "4,8")])
6595 (define_insn "*rotldi3_internal9be"
6596 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6597 (compare:CC (zero_extend:DI
6598 (subreg:QI
6599 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6600 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6601 (const_int 0)))
6602 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6603 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6604 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6605 "@
6606 rld%I2cl. %0,%1,%H2,56
6607 #"
6608 [(set_attr "type" "shift")
6609 (set_attr "maybe_var_shift" "yes")
6610 (set_attr "dot" "yes")
6611 (set_attr "length" "4,8")])
6613 (define_split
6614 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6615 (compare:CC (zero_extend:DI
6616 (subreg:QI
6617 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6618 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6619 (const_int 0)))
6620 (set (match_operand:DI 0 "gpc_reg_operand" "")
6621 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6622 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6623 [(set (match_dup 0)
6624 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6625 (set (match_dup 3)
6626 (compare:CC (match_dup 0)
6627 (const_int 0)))]
6628 "")
6630 (define_split
6631 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6632 (compare:CC (zero_extend:DI
6633 (subreg:QI
6634 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6635 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6636 (const_int 0)))
6637 (set (match_operand:DI 0 "gpc_reg_operand" "")
6638 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6639 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6640 [(set (match_dup 0)
6641 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
6642 (set (match_dup 3)
6643 (compare:CC (match_dup 0)
6644 (const_int 0)))]
6645 "")
6647 (define_insn "*rotldi3_internal10le"
6648 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6649 (zero_extend:DI
6650 (subreg:HI
6651 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6652 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6653 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6654 "rld%I2cl %0,%1,%H2,48"
6655 [(set_attr "type" "shift")
6656 (set_attr "maybe_var_shift" "yes")])
6658 (define_insn "*rotldi3_internal10be"
6659 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6660 (zero_extend:DI
6661 (subreg:HI
6662 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6663 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
6664 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6665 "rld%I2cl %0,%1,%H2,48"
6666 [(set_attr "type" "shift")
6667 (set_attr "maybe_var_shift" "yes")])
6669 (define_insn "*rotldi3_internal11le"
6670 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6671 (compare:CC (zero_extend:DI
6672 (subreg:HI
6673 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6674 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6675 (const_int 0)))
6676 (clobber (match_scratch:DI 3 "=r,r"))]
6677 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6678 "@
6679 rld%I2cl. %3,%1,%H2,48
6680 #"
6681 [(set_attr "type" "shift")
6682 (set_attr "maybe_var_shift" "yes")
6683 (set_attr "dot" "yes")
6684 (set_attr "length" "4,8")])
6686 (define_insn "*rotldi3_internal11be"
6687 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6688 (compare:CC (zero_extend:DI
6689 (subreg:HI
6690 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6691 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6692 (const_int 0)))
6693 (clobber (match_scratch:DI 3 "=r,r"))]
6694 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6695 "@
6696 rld%I2cl. %3,%1,%H2,48
6697 #"
6698 [(set_attr "type" "shift")
6699 (set_attr "maybe_var_shift" "yes")
6700 (set_attr "dot" "yes")
6701 (set_attr "length" "4,8")])
6703 (define_split
6704 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6705 (compare:CC (zero_extend:DI
6706 (subreg:HI
6707 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6708 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6709 (const_int 0)))
6710 (clobber (match_scratch:DI 3 ""))]
6711 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6712 [(set (match_dup 3)
6713 (zero_extend:DI (subreg:HI
6714 (rotate:DI (match_dup 1)
6715 (match_dup 2)) 0)))
6716 (set (match_dup 0)
6717 (compare:CC (match_dup 3)
6718 (const_int 0)))]
6719 "")
6721 (define_split
6722 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6723 (compare:CC (zero_extend:DI
6724 (subreg:HI
6725 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6726 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6727 (const_int 0)))
6728 (clobber (match_scratch:DI 3 ""))]
6729 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6730 [(set (match_dup 3)
6731 (zero_extend:DI (subreg:HI
6732 (rotate:DI (match_dup 1)
6733 (match_dup 2)) 6)))
6734 (set (match_dup 0)
6735 (compare:CC (match_dup 3)
6736 (const_int 0)))]
6737 "")
6739 (define_insn "*rotldi3_internal12le"
6740 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6741 (compare:CC (zero_extend:DI
6742 (subreg:HI
6743 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6744 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6745 (const_int 0)))
6746 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6747 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6748 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6749 "@
6750 rld%I2cl. %0,%1,%H2,48
6751 #"
6752 [(set_attr "type" "shift")
6753 (set_attr "maybe_var_shift" "yes")
6754 (set_attr "dot" "yes")
6755 (set_attr "length" "4,8")])
6757 (define_insn "*rotldi3_internal12be"
6758 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6759 (compare:CC (zero_extend:DI
6760 (subreg:HI
6761 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6762 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6763 (const_int 0)))
6764 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6765 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6766 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6767 "@
6768 rld%I2cl. %0,%1,%H2,48
6769 #"
6770 [(set_attr "type" "shift")
6771 (set_attr "maybe_var_shift" "yes")
6772 (set_attr "dot" "yes")
6773 (set_attr "length" "4,8")])
6775 (define_split
6776 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6777 (compare:CC (zero_extend:DI
6778 (subreg:HI
6779 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6780 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6781 (const_int 0)))
6782 (set (match_operand:DI 0 "gpc_reg_operand" "")
6783 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6784 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6785 [(set (match_dup 0)
6786 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6787 (set (match_dup 3)
6788 (compare:CC (match_dup 0)
6789 (const_int 0)))]
6790 "")
6792 (define_split
6793 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6794 (compare:CC (zero_extend:DI
6795 (subreg:HI
6796 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6797 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6798 (const_int 0)))
6799 (set (match_operand:DI 0 "gpc_reg_operand" "")
6800 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6801 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6802 [(set (match_dup 0)
6803 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
6804 (set (match_dup 3)
6805 (compare:CC (match_dup 0)
6806 (const_int 0)))]
6807 "")
6809 (define_insn "*rotldi3_internal13le"
6810 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6811 (zero_extend:DI
6812 (subreg:SI
6813 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6814 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6815 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6816 "rld%I2cl %0,%1,%H2,32"
6817 [(set_attr "type" "shift")
6818 (set_attr "maybe_var_shift" "yes")])
6820 (define_insn "*rotldi3_internal13be"
6821 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6822 (zero_extend:DI
6823 (subreg:SI
6824 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6825 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
6826 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6827 "rld%I2cl %0,%1,%H2,32"
6828 [(set_attr "type" "shift")
6829 (set_attr "maybe_var_shift" "yes")])
6831 (define_insn "*rotldi3_internal14le"
6832 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6833 (compare:CC (zero_extend:DI
6834 (subreg:SI
6835 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6836 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6837 (const_int 0)))
6838 (clobber (match_scratch:DI 3 "=r,r"))]
6839 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6840 "@
6841 rld%I2cl. %3,%1,%H2,32
6842 #"
6843 [(set_attr "type" "shift")
6844 (set_attr "maybe_var_shift" "yes")
6845 (set_attr "dot" "yes")
6846 (set_attr "length" "4,8")])
6848 (define_insn "*rotldi3_internal14be"
6849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6850 (compare:CC (zero_extend:DI
6851 (subreg:SI
6852 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6853 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6854 (const_int 0)))
6855 (clobber (match_scratch:DI 3 "=r,r"))]
6856 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6857 "@
6858 rld%I2cl. %3,%1,%H2,32
6859 #"
6860 [(set_attr "type" "shift")
6861 (set_attr "maybe_var_shift" "yes")
6862 (set_attr "dot" "yes")
6863 (set_attr "length" "4,8")])
6865 (define_split
6866 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6867 (compare:CC (zero_extend:DI
6868 (subreg:SI
6869 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6870 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6871 (const_int 0)))
6872 (clobber (match_scratch:DI 3 ""))]
6873 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6874 [(set (match_dup 3)
6875 (zero_extend:DI (subreg:SI
6876 (rotate:DI (match_dup 1)
6877 (match_dup 2)) 0)))
6878 (set (match_dup 0)
6879 (compare:CC (match_dup 3)
6880 (const_int 0)))]
6881 "")
6883 (define_split
6884 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6885 (compare:CC (zero_extend:DI
6886 (subreg:SI
6887 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6888 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6889 (const_int 0)))
6890 (clobber (match_scratch:DI 3 ""))]
6891 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6892 [(set (match_dup 3)
6893 (zero_extend:DI (subreg:SI
6894 (rotate:DI (match_dup 1)
6895 (match_dup 2)) 4)))
6896 (set (match_dup 0)
6897 (compare:CC (match_dup 3)
6898 (const_int 0)))]
6899 "")
6901 (define_insn "*rotldi3_internal15le"
6902 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6903 (compare:CC (zero_extend:DI
6904 (subreg:SI
6905 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6906 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6907 (const_int 0)))
6908 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6909 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6910 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6911 "@
6912 rld%I2cl. %0,%1,%H2,32
6913 #"
6914 [(set_attr "type" "shift")
6915 (set_attr "maybe_var_shift" "yes")
6916 (set_attr "dot" "yes")
6917 (set_attr "length" "4,8")])
6919 (define_insn "*rotldi3_internal15be"
6920 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6921 (compare:CC (zero_extend:DI
6922 (subreg:SI
6923 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6924 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6925 (const_int 0)))
6926 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6927 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6928 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6929 "@
6930 rld%I2cl. %0,%1,%H2,32
6931 #"
6932 [(set_attr "type" "shift")
6933 (set_attr "maybe_var_shift" "yes")
6934 (set_attr "dot" "yes")
6935 (set_attr "length" "4,8")])
6937 (define_split
6938 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6939 (compare:CC (zero_extend:DI
6940 (subreg:SI
6941 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6942 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6943 (const_int 0)))
6944 (set (match_operand:DI 0 "gpc_reg_operand" "")
6945 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6946 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6947 [(set (match_dup 0)
6948 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6949 (set (match_dup 3)
6950 (compare:CC (match_dup 0)
6951 (const_int 0)))]
6952 "")
6954 (define_split
6955 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6956 (compare:CC (zero_extend:DI
6957 (subreg:SI
6958 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6959 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6960 (const_int 0)))
6961 (set (match_operand:DI 0 "gpc_reg_operand" "")
6962 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6963 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6964 [(set (match_dup 0)
6965 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
6966 (set (match_dup 3)
6967 (compare:CC (match_dup 0)
6968 (const_int 0)))]
6969 "")
6971 (define_insn "*ashldi3_internal4"
6972 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6973 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6974 (match_operand:SI 2 "const_int_operand" "i"))
6975 (match_operand:DI 3 "const_int_operand" "n")))]
6976 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6977 "rldic %0,%1,%H2,%W3"
6978 [(set_attr "type" "shift")])
6980 (define_insn "ashldi3_internal5"
6981 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6982 (compare:CC
6983 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6984 (match_operand:SI 2 "const_int_operand" "i,i"))
6985 (match_operand:DI 3 "const_int_operand" "n,n"))
6986 (const_int 0)))
6987 (clobber (match_scratch:DI 4 "=r,r"))]
6988 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6989 "@
6990 rldic. %4,%1,%H2,%W3
6991 #"
6992 [(set_attr "type" "shift")
6993 (set_attr "dot" "yes")
6994 (set_attr "length" "4,8")])
6996 (define_split
6997 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6998 (compare:CC
6999 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7000 (match_operand:SI 2 "const_int_operand" ""))
7001 (match_operand:DI 3 "const_int_operand" ""))
7002 (const_int 0)))
7003 (clobber (match_scratch:DI 4 ""))]
7004 "TARGET_POWERPC64 && reload_completed
7005 && includes_rldic_lshift_p (operands[2], operands[3])"
7006 [(set (match_dup 4)
7007 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7008 (match_dup 3)))
7009 (set (match_dup 0)
7010 (compare:CC (match_dup 4)
7011 (const_int 0)))]
7012 "")
7014 (define_insn "*ashldi3_internal6"
7015 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7016 (compare:CC
7017 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7018 (match_operand:SI 2 "const_int_operand" "i,i"))
7019 (match_operand:DI 3 "const_int_operand" "n,n"))
7020 (const_int 0)))
7021 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7022 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7023 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7024 "@
7025 rldic. %0,%1,%H2,%W3
7026 #"
7027 [(set_attr "type" "shift")
7028 (set_attr "dot" "yes")
7029 (set_attr "length" "4,8")])
7031 (define_split
7032 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7033 (compare:CC
7034 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7035 (match_operand:SI 2 "const_int_operand" ""))
7036 (match_operand:DI 3 "const_int_operand" ""))
7037 (const_int 0)))
7038 (set (match_operand:DI 0 "gpc_reg_operand" "")
7039 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7040 "TARGET_POWERPC64 && reload_completed
7041 && includes_rldic_lshift_p (operands[2], operands[3])"
7042 [(set (match_dup 0)
7043 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7044 (match_dup 3)))
7045 (set (match_dup 4)
7046 (compare:CC (match_dup 0)
7047 (const_int 0)))]
7048 "")
7050 (define_insn "*ashldi3_internal7"
7051 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7052 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7053 (match_operand:SI 2 "const_int_operand" "i"))
7054 (match_operand:DI 3 "mask64_operand" "n")))]
7055 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7056 "rldicr %0,%1,%H2,%S3"
7057 [(set_attr "type" "shift")])
7059 (define_insn "ashldi3_internal8"
7060 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7061 (compare:CC
7062 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7063 (match_operand:SI 2 "const_int_operand" "i,i"))
7064 (match_operand:DI 3 "mask64_operand" "n,n"))
7065 (const_int 0)))
7066 (clobber (match_scratch:DI 4 "=r,r"))]
7067 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7068 "@
7069 rldicr. %4,%1,%H2,%S3
7070 #"
7071 [(set_attr "type" "shift")
7072 (set_attr "dot" "yes")
7073 (set_attr "length" "4,8")])
7075 (define_split
7076 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7077 (compare:CC
7078 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7079 (match_operand:SI 2 "const_int_operand" ""))
7080 (match_operand:DI 3 "mask64_operand" ""))
7081 (const_int 0)))
7082 (clobber (match_scratch:DI 4 ""))]
7083 "TARGET_POWERPC64 && reload_completed
7084 && includes_rldicr_lshift_p (operands[2], operands[3])"
7085 [(set (match_dup 4)
7086 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7087 (match_dup 3)))
7088 (set (match_dup 0)
7089 (compare:CC (match_dup 4)
7090 (const_int 0)))]
7091 "")
7093 (define_insn "*ashldi3_internal9"
7094 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7095 (compare:CC
7096 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7097 (match_operand:SI 2 "const_int_operand" "i,i"))
7098 (match_operand:DI 3 "mask64_operand" "n,n"))
7099 (const_int 0)))
7100 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7101 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7102 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7103 "@
7104 rldicr. %0,%1,%H2,%S3
7105 #"
7106 [(set_attr "type" "shift")
7107 (set_attr "dot" "yes")
7108 (set_attr "length" "4,8")])
7110 (define_split
7111 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7112 (compare:CC
7113 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7114 (match_operand:SI 2 "const_int_operand" ""))
7115 (match_operand:DI 3 "mask64_operand" ""))
7116 (const_int 0)))
7117 (set (match_operand:DI 0 "gpc_reg_operand" "")
7118 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7119 "TARGET_POWERPC64 && reload_completed
7120 && includes_rldicr_lshift_p (operands[2], operands[3])"
7121 [(set (match_dup 0)
7122 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7123 (match_dup 3)))
7124 (set (match_dup 4)
7125 (compare:CC (match_dup 0)
7126 (const_int 0)))]
7127 "")
7130 (define_insn_and_split "*anddi3_2rld"
7131 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7132 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
7133 (match_operand:DI 2 "and_2rld_operand" "n")))]
7134 "TARGET_POWERPC64"
7135 "#"
7136 ""
7137 [(set (match_dup 0)
7138 (and:DI (rotate:DI (match_dup 1)
7139 (match_dup 4))
7140 (match_dup 5)))
7141 (set (match_dup 0)
7142 (and:DI (rotate:DI (match_dup 0)
7143 (match_dup 6))
7144 (match_dup 7)))]
7145 {
7146 build_mask64_2_operands (operands[2], &operands[4]);
7147 }
7148 [(set_attr "length" "8")])
7150 (define_insn_and_split "*anddi3_2rld_dot"
7151 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7152 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7153 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7154 (const_int 0)))
7155 (clobber (match_scratch:DI 0 "=r,r"))]
7156 "TARGET_64BIT && rs6000_gen_cell_microcode"
7157 "@
7158 #
7159 #"
7160 "&& reload_completed"
7161 [(set (match_dup 0)
7162 (and:DI (rotate:DI (match_dup 1)
7163 (match_dup 4))
7164 (match_dup 5)))
7165 (parallel [(set (match_dup 3)
7166 (compare:CC (and:DI (rotate:DI (match_dup 0)
7167 (match_dup 6))
7168 (match_dup 7))
7169 (const_int 0)))
7170 (clobber (match_dup 0))])]
7171 {
7172 build_mask64_2_operands (operands[2], &operands[4]);
7173 }
7174 [(set_attr "type" "compare")
7175 (set_attr "dot" "yes")
7176 (set_attr "length" "8,12")])
7178 (define_insn_and_split "*anddi3_2rld_dot2"
7179 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7180 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7181 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7182 (const_int 0)))
7183 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7184 (and:DI (match_dup 1)
7185 (match_dup 2)))]
7186 "TARGET_64BIT && rs6000_gen_cell_microcode"
7187 "@
7188 #
7189 #"
7190 "&& reload_completed"
7191 [(set (match_dup 0)
7192 (and:DI (rotate:DI (match_dup 1)
7193 (match_dup 4))
7194 (match_dup 5)))
7195 (parallel [(set (match_dup 3)
7196 (compare:CC (and:DI (rotate:DI (match_dup 0)
7197 (match_dup 6))
7198 (match_dup 7))
7199 (const_int 0)))
7200 (set (match_dup 0)
7201 (and:DI (rotate:DI (match_dup 0)
7202 (match_dup 6))
7203 (match_dup 7)))])]
7204 {
7205 build_mask64_2_operands (operands[2], &operands[4]);
7206 }
7207 [(set_attr "type" "compare")
7208 (set_attr "dot" "yes")
7209 (set_attr "length" "8,12")])
7210 \f
7211 ;; 128-bit logical operations expanders
7213 (define_expand "and<mode>3"
7214 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7215 (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7216 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7217 ""
7218 "")
7220 (define_expand "ior<mode>3"
7221 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7222 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7223 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7224 ""
7225 "")
7227 (define_expand "xor<mode>3"
7228 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7229 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7230 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7231 ""
7232 "")
7234 (define_expand "one_cmpl<mode>2"
7235 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7236 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7237 ""
7238 "")
7240 (define_expand "nor<mode>3"
7241 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7242 (and:BOOL_128
7243 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7244 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7245 ""
7246 "")
7248 (define_expand "andc<mode>3"
7249 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7250 (and:BOOL_128
7251 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7252 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7253 ""
7254 "")
7256 ;; Power8 vector logical instructions.
7257 (define_expand "eqv<mode>3"
7258 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7259 (not:BOOL_128
7260 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7261 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7262 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7263 "")
7265 ;; Rewrite nand into canonical form
7266 (define_expand "nand<mode>3"
7267 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7268 (ior:BOOL_128
7269 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7270 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7271 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7272 "")
7274 ;; The canonical form is to have the negated element first, so we need to
7275 ;; reverse arguments.
7276 (define_expand "orc<mode>3"
7277 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7278 (ior:BOOL_128
7279 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7280 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7281 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7282 "")
7284 ;; 128-bit logical operations insns and split operations
7285 (define_insn_and_split "*and<mode>3_internal"
7286 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7287 (and:BOOL_128
7288 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7289 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
7290 ""
7291 {
7292 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7293 return "xxland %x0,%x1,%x2";
7295 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7296 return "vand %0,%1,%2";
7298 return "#";
7299 }
7300 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7301 [(const_int 0)]
7302 {
7303 rs6000_split_logical (operands, AND, false, false, false);
7304 DONE;
7305 }
7306 [(set (attr "type")
7307 (if_then_else
7308 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7309 (const_string "vecsimple")
7310 (const_string "integer")))
7311 (set (attr "length")
7312 (if_then_else
7313 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7314 (const_string "4")
7315 (if_then_else
7316 (match_test "TARGET_POWERPC64")
7317 (const_string "8")
7318 (const_string "16"))))])
7320 ;; 128-bit IOR/XOR
7321 (define_insn_and_split "*bool<mode>3_internal"
7322 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7323 (match_operator:BOOL_128 3 "boolean_or_operator"
7324 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7325 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7326 ""
7327 {
7328 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7329 return "xxl%q3 %x0,%x1,%x2";
7331 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7332 return "v%q3 %0,%1,%2";
7334 return "#";
7335 }
7336 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7337 [(const_int 0)]
7338 {
7339 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
7340 DONE;
7341 }
7342 [(set (attr "type")
7343 (if_then_else
7344 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7345 (const_string "vecsimple")
7346 (const_string "integer")))
7347 (set (attr "length")
7348 (if_then_else
7349 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7350 (const_string "4")
7351 (if_then_else
7352 (match_test "TARGET_POWERPC64")
7353 (const_string "8")
7354 (const_string "16"))))])
7356 ;; 128-bit ANDC/ORC
7357 (define_insn_and_split "*boolc<mode>3_internal1"
7358 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7359 (match_operator:BOOL_128 3 "boolean_operator"
7360 [(not:BOOL_128
7361 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
7362 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7363 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7364 {
7365 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7366 return "xxl%q3 %x0,%x1,%x2";
7368 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7369 return "v%q3 %0,%1,%2";
7371 return "#";
7372 }
7373 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7374 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7375 [(const_int 0)]
7376 {
7377 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7378 DONE;
7379 }
7380 [(set (attr "type")
7381 (if_then_else
7382 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7383 (const_string "vecsimple")
7384 (const_string "integer")))
7385 (set (attr "length")
7386 (if_then_else
7387 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7388 (const_string "4")
7389 (if_then_else
7390 (match_test "TARGET_POWERPC64")
7391 (const_string "8")
7392 (const_string "16"))))])
7394 (define_insn_and_split "*boolc<mode>3_internal2"
7395 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7396 (match_operator:TI2 3 "boolean_operator"
7397 [(not:TI2
7398 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7399 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
7400 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7401 "#"
7402 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7403 [(const_int 0)]
7404 {
7405 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7406 DONE;
7407 }
7408 [(set_attr "type" "integer")
7409 (set (attr "length")
7410 (if_then_else
7411 (match_test "TARGET_POWERPC64")
7412 (const_string "8")
7413 (const_string "16")))])
7415 ;; 128-bit NAND/NOR
7416 (define_insn_and_split "*boolcc<mode>3_internal1"
7417 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7418 (match_operator:BOOL_128 3 "boolean_operator"
7419 [(not:BOOL_128
7420 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
7421 (not:BOOL_128
7422 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
7423 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7424 {
7425 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7426 return "xxl%q3 %x0,%x1,%x2";
7428 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7429 return "v%q3 %0,%1,%2";
7431 return "#";
7432 }
7433 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7434 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7435 [(const_int 0)]
7436 {
7437 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7438 DONE;
7439 }
7440 [(set (attr "type")
7441 (if_then_else
7442 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7443 (const_string "vecsimple")
7444 (const_string "integer")))
7445 (set (attr "length")
7446 (if_then_else
7447 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7448 (const_string "4")
7449 (if_then_else
7450 (match_test "TARGET_POWERPC64")
7451 (const_string "8")
7452 (const_string "16"))))])
7454 (define_insn_and_split "*boolcc<mode>3_internal2"
7455 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7456 (match_operator:TI2 3 "boolean_operator"
7457 [(not:TI2
7458 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7459 (not:TI2
7460 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
7461 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7462 "#"
7463 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7464 [(const_int 0)]
7465 {
7466 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7467 DONE;
7468 }
7469 [(set_attr "type" "integer")
7470 (set (attr "length")
7471 (if_then_else
7472 (match_test "TARGET_POWERPC64")
7473 (const_string "8")
7474 (const_string "16")))])
7477 ;; 128-bit EQV
7478 (define_insn_and_split "*eqv<mode>3_internal1"
7479 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7480 (not:BOOL_128
7481 (xor:BOOL_128
7482 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
7483 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
7484 "TARGET_P8_VECTOR"
7485 {
7486 if (vsx_register_operand (operands[0], <MODE>mode))
7487 return "xxleqv %x0,%x1,%x2";
7489 return "#";
7490 }
7491 "TARGET_P8_VECTOR && reload_completed
7492 && int_reg_operand (operands[0], <MODE>mode)"
7493 [(const_int 0)]
7494 {
7495 rs6000_split_logical (operands, XOR, true, false, false);
7496 DONE;
7497 }
7498 [(set (attr "type")
7499 (if_then_else
7500 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7501 (const_string "vecsimple")
7502 (const_string "integer")))
7503 (set (attr "length")
7504 (if_then_else
7505 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7506 (const_string "4")
7507 (if_then_else
7508 (match_test "TARGET_POWERPC64")
7509 (const_string "8")
7510 (const_string "16"))))])
7512 (define_insn_and_split "*eqv<mode>3_internal2"
7513 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7514 (not:TI2
7515 (xor:TI2
7516 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
7517 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
7518 "!TARGET_P8_VECTOR"
7519 "#"
7520 "reload_completed && !TARGET_P8_VECTOR"
7521 [(const_int 0)]
7522 {
7523 rs6000_split_logical (operands, XOR, true, false, false);
7524 DONE;
7525 }
7526 [(set_attr "type" "integer")
7527 (set (attr "length")
7528 (if_then_else
7529 (match_test "TARGET_POWERPC64")
7530 (const_string "8")
7531 (const_string "16")))])
7533 ;; 128-bit one's complement
7534 (define_insn_and_split "*one_cmpl<mode>3_internal"
7535 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7536 (not:BOOL_128
7537 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
7538 ""
7539 {
7540 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7541 return "xxlnor %x0,%x1,%x1";
7543 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7544 return "vnor %0,%1,%1";
7546 return "#";
7547 }
7548 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7549 [(const_int 0)]
7550 {
7551 rs6000_split_logical (operands, NOT, false, false, false);
7552 DONE;
7553 }
7554 [(set (attr "type")
7555 (if_then_else
7556 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7557 (const_string "vecsimple")
7558 (const_string "integer")))
7559 (set (attr "length")
7560 (if_then_else
7561 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7562 (const_string "4")
7563 (if_then_else
7564 (match_test "TARGET_POWERPC64")
7565 (const_string "8")
7566 (const_string "16"))))])
7568 \f
7569 ;; Now define ways of moving data around.
7571 ;; Set up a register with a value from the GOT table
7573 (define_expand "movsi_got"
7574 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7575 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7576 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7577 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7578 "
7579 {
7580 if (GET_CODE (operands[1]) == CONST)
7581 {
7582 rtx offset = const0_rtx;
7583 HOST_WIDE_INT value;
7585 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7586 value = INTVAL (offset);
7587 if (value != 0)
7588 {
7589 rtx tmp = (!can_create_pseudo_p ()
7590 ? operands[0]
7591 : gen_reg_rtx (Pmode));
7592 emit_insn (gen_movsi_got (tmp, operands[1]));
7593 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7594 DONE;
7595 }
7596 }
7598 operands[2] = rs6000_got_register (operands[1]);
7599 }")
7601 (define_insn "*movsi_got_internal"
7602 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7603 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7604 (match_operand:SI 2 "gpc_reg_operand" "b")]
7605 UNSPEC_MOVSI_GOT))]
7606 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7607 "lwz %0,%a1@got(%2)"
7608 [(set_attr "type" "load")])
7610 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7611 ;; didn't get allocated to a hard register.
7612 (define_split
7613 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7614 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7615 (match_operand:SI 2 "memory_operand" "")]
7616 UNSPEC_MOVSI_GOT))]
7617 "DEFAULT_ABI == ABI_V4
7618 && flag_pic == 1
7619 && (reload_in_progress || reload_completed)"
7620 [(set (match_dup 0) (match_dup 2))
7621 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7622 UNSPEC_MOVSI_GOT))]
7623 "")
7625 ;; For SI, we special-case integers that can't be loaded in one insn. We
7626 ;; do the load 16-bits at a time. We could do this by loading from memory,
7627 ;; and this is even supposed to be faster, but it is simpler not to get
7628 ;; integers in the TOC.
7629 (define_insn "movsi_low"
7630 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7631 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7632 (match_operand 2 "" ""))))]
7633 "TARGET_MACHO && ! TARGET_64BIT"
7634 "lwz %0,lo16(%2)(%1)"
7635 [(set_attr "type" "load")
7636 (set_attr "length" "4")])
7638 (define_insn "*movsi_internal1"
7639 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7640 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7641 "!TARGET_SINGLE_FPU &&
7642 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7643 "@
7644 mr %0,%1
7645 la %0,%a1
7646 lwz%U1%X1 %0,%1
7647 stw%U0%X0 %1,%0
7648 li %0,%1
7649 lis %0,%v1
7650 #
7651 mf%1 %0
7652 mt%0 %1
7653 mt%0 %1
7654 nop"
7655 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7656 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7658 (define_insn "*movsi_internal1_single"
7659 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7660 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7661 "TARGET_SINGLE_FPU &&
7662 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7663 "@
7664 mr %0,%1
7665 la %0,%a1
7666 lwz%U1%X1 %0,%1
7667 stw%U0%X0 %1,%0
7668 li %0,%1
7669 lis %0,%v1
7670 #
7671 mf%1 %0
7672 mt%0 %1
7673 mt%0 %1
7674 nop
7675 stfs%U0%X0 %1,%0
7676 lfs%U1%X1 %0,%1"
7677 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
7678 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7680 ;; Split a load of a large constant into the appropriate two-insn
7681 ;; sequence.
7683 (define_split
7684 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7685 (match_operand:SI 1 "const_int_operand" ""))]
7686 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7687 && (INTVAL (operands[1]) & 0xffff) != 0"
7688 [(set (match_dup 0)
7689 (match_dup 2))
7690 (set (match_dup 0)
7691 (ior:SI (match_dup 0)
7692 (match_dup 3)))]
7693 "
7694 {
7695 if (rs6000_emit_set_const (operands[0], operands[1]))
7696 DONE;
7697 else
7698 FAIL;
7699 }")
7701 (define_insn "*mov<mode>_internal2"
7702 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7703 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7704 (const_int 0)))
7705 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7706 ""
7707 "@
7708 cmp<wd>i %2,%0,0
7709 mr. %0,%1
7710 #"
7711 [(set_attr "type" "cmp,logical,cmp")
7712 (set_attr "dot" "yes")
7713 (set_attr "length" "4,4,8")])
7715 (define_split
7716 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7717 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7718 (const_int 0)))
7719 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7720 "reload_completed"
7721 [(set (match_dup 0) (match_dup 1))
7722 (set (match_dup 2)
7723 (compare:CC (match_dup 0)
7724 (const_int 0)))]
7725 "")
7726 \f
7727 (define_insn "*movhi_internal"
7728 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7729 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7730 "gpc_reg_operand (operands[0], HImode)
7731 || gpc_reg_operand (operands[1], HImode)"
7732 "@
7733 mr %0,%1
7734 lhz%U1%X1 %0,%1
7735 sth%U0%X0 %1,%0
7736 li %0,%w1
7737 mf%1 %0
7738 mt%0 %1
7739 nop"
7740 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7742 (define_expand "mov<mode>"
7743 [(set (match_operand:INT 0 "general_operand" "")
7744 (match_operand:INT 1 "any_operand" ""))]
7745 ""
7746 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7748 (define_insn "*movqi_internal"
7749 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7750 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7751 "gpc_reg_operand (operands[0], QImode)
7752 || gpc_reg_operand (operands[1], QImode)"
7753 "@
7754 mr %0,%1
7755 lbz%U1%X1 %0,%1
7756 stb%U0%X0 %1,%0
7757 li %0,%1
7758 mf%1 %0
7759 mt%0 %1
7760 nop"
7761 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7762 \f
7763 ;; Here is how to move condition codes around. When we store CC data in
7764 ;; an integer register or memory, we store just the high-order 4 bits.
7765 ;; This lets us not shift in the most common case of CR0.
7766 (define_expand "movcc"
7767 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7768 (match_operand:CC 1 "nonimmediate_operand" ""))]
7769 ""
7770 "")
7772 (define_insn "*movcc_internal1"
7773 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7774 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7775 "register_operand (operands[0], CCmode)
7776 || register_operand (operands[1], CCmode)"
7777 "@
7778 mcrf %0,%1
7779 mtcrf 128,%1
7780 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7781 crxor %0,%0,%0
7782 mfcr %0%Q1
7783 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7784 mr %0,%1
7785 li %0,%1
7786 mf%1 %0
7787 mt%0 %1
7788 lwz%U1%X1 %0,%1
7789 stw%U0%X0 %1,%0"
7790 [(set (attr "type")
7791 (cond [(eq_attr "alternative" "0,3")
7792 (const_string "cr_logical")
7793 (eq_attr "alternative" "1,2")
7794 (const_string "mtcr")
7795 (eq_attr "alternative" "6,7")
7796 (const_string "integer")
7797 (eq_attr "alternative" "8")
7798 (const_string "mfjmpr")
7799 (eq_attr "alternative" "9")
7800 (const_string "mtjmpr")
7801 (eq_attr "alternative" "10")
7802 (const_string "load")
7803 (eq_attr "alternative" "11")
7804 (const_string "store")
7805 (match_test "TARGET_MFCRF")
7806 (const_string "mfcrf")
7807 ]
7808 (const_string "mfcr")))
7809 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
7810 \f
7811 ;; For floating-point, we normally deal with the floating-point registers
7812 ;; unless -msoft-float is used. The sole exception is that parameter passing
7813 ;; can produce floating-point values in fixed-point registers. Unless the
7814 ;; value is a simple constant or already in memory, we deal with this by
7815 ;; allocating memory and copying the value explicitly via that memory location.
7817 ;; Move 32-bit binary/decimal floating point
7818 (define_expand "mov<mode>"
7819 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
7820 (match_operand:FMOVE32 1 "any_operand" ""))]
7821 "<fmove_ok>"
7822 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7824 (define_split
7825 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
7826 (match_operand:FMOVE32 1 "const_double_operand" ""))]
7827 "reload_completed
7828 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7829 || (GET_CODE (operands[0]) == SUBREG
7830 && GET_CODE (SUBREG_REG (operands[0])) == REG
7831 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7832 [(set (match_dup 2) (match_dup 3))]
7833 "
7834 {
7835 long l;
7836 REAL_VALUE_TYPE rv;
7838 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7839 <real_value_to_target> (rv, l);
7841 if (! TARGET_POWERPC64)
7842 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
7843 else
7844 operands[2] = gen_lowpart (SImode, operands[0]);
7846 operands[3] = gen_int_mode (l, SImode);
7847 }")
7849 (define_insn "mov<mode>_hardfloat"
7850 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
7851 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r,h,0,G,Fn"))]
7852 "(gpc_reg_operand (operands[0], <MODE>mode)
7853 || gpc_reg_operand (operands[1], <MODE>mode))
7854 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
7855 "@
7856 mr %0,%1
7857 lwz%U1%X1 %0,%1
7858 stw%U0%X0 %1,%0
7859 fmr %0,%1
7860 xxlor %x0,%x1,%x1
7861 xxlxor %x0,%x0,%x0
7862 <f32_li>
7863 <f32_si>
7864 <f32_lv>
7865 <f32_sv>
7866 mtvsrwz %x0,%1
7867 mfvsrwz %0,%x1
7868 mt%0 %1
7869 mf%1 %0
7870 nop
7871 #
7872 #"
7873 [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
7874 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
7876 (define_insn "*mov<mode>_softfloat"
7877 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
7878 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
7879 "(gpc_reg_operand (operands[0], <MODE>mode)
7880 || gpc_reg_operand (operands[1], <MODE>mode))
7881 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7882 "@
7883 mr %0,%1
7884 mt%0 %1
7885 mf%1 %0
7886 lwz%U1%X1 %0,%1
7887 stw%U0%X0 %1,%0
7888 li %0,%1
7889 lis %0,%v1
7890 #
7891 #
7892 nop"
7893 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
7894 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
7896 \f
7897 ;; Move 64-bit binary/decimal floating point
7898 (define_expand "mov<mode>"
7899 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
7900 (match_operand:FMOVE64 1 "any_operand" ""))]
7901 ""
7902 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7904 (define_split
7905 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7906 (match_operand:FMOVE64 1 "const_int_operand" ""))]
7907 "! TARGET_POWERPC64 && reload_completed
7908 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7909 || (GET_CODE (operands[0]) == SUBREG
7910 && GET_CODE (SUBREG_REG (operands[0])) == REG
7911 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7912 [(set (match_dup 2) (match_dup 4))
7913 (set (match_dup 3) (match_dup 1))]
7914 "
7915 {
7916 int endian = (WORDS_BIG_ENDIAN == 0);
7917 HOST_WIDE_INT value = INTVAL (operands[1]);
7919 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7920 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7921 operands[4] = GEN_INT (value >> 32);
7922 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7923 }")
7925 (define_split
7926 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7927 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7928 "! TARGET_POWERPC64 && reload_completed
7929 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7930 || (GET_CODE (operands[0]) == SUBREG
7931 && GET_CODE (SUBREG_REG (operands[0])) == REG
7932 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7933 [(set (match_dup 2) (match_dup 4))
7934 (set (match_dup 3) (match_dup 5))]
7935 "
7936 {
7937 int endian = (WORDS_BIG_ENDIAN == 0);
7938 long l[2];
7939 REAL_VALUE_TYPE rv;
7941 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7942 <real_value_to_target> (rv, l);
7944 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7945 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7946 operands[4] = gen_int_mode (l[endian], SImode);
7947 operands[5] = gen_int_mode (l[1 - endian], SImode);
7948 }")
7950 (define_split
7951 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7952 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7953 "TARGET_POWERPC64 && reload_completed
7954 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7955 || (GET_CODE (operands[0]) == SUBREG
7956 && GET_CODE (SUBREG_REG (operands[0])) == REG
7957 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7958 [(set (match_dup 2) (match_dup 3))]
7959 "
7960 {
7961 int endian = (WORDS_BIG_ENDIAN == 0);
7962 long l[2];
7963 REAL_VALUE_TYPE rv;
7964 HOST_WIDE_INT val;
7966 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7967 <real_value_to_target> (rv, l);
7969 operands[2] = gen_lowpart (DImode, operands[0]);
7970 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7971 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7972 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7974 operands[3] = gen_int_mode (val, DImode);
7975 }")
7977 ;; Don't have reload use general registers to load a constant. It is
7978 ;; less efficient than loading the constant into an FP register, since
7979 ;; it will probably be used there.
7981 ;; The move constraints are ordered to prefer floating point registers before
7982 ;; general purpose registers to avoid doing a store and a load to get the value
7983 ;; into a floating point register when it is needed for a floating point
7984 ;; operation. Prefer traditional floating point registers over VSX registers,
7985 ;; since the D-form version of the memory instructions does not need a GPR for
7986 ;; reloading.
7988 (define_insn "*mov<mode>_hardfloat32"
7989 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,!r,!r,!r")
7990 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,G,H,F"))]
7991 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7992 && (gpc_reg_operand (operands[0], <MODE>mode)
7993 || gpc_reg_operand (operands[1], <MODE>mode))"
7994 "@
7995 stfd%U0%X0 %1,%0
7996 lfd%U1%X1 %0,%1
7997 fmr %0,%1
7998 lxsd%U1x %x0,%y1
7999 stxsd%U0x %x1,%y0
8000 xxlor %x0,%x1,%x1
8001 xxlxor %x0,%x0,%x0
8002 #
8003 #
8004 #
8005 #
8006 #
8007 #"
8008 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
8009 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
8011 (define_insn "*mov<mode>_softfloat32"
8012 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8013 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
8014 "! TARGET_POWERPC64
8015 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8016 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
8017 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
8018 && (gpc_reg_operand (operands[0], <MODE>mode)
8019 || gpc_reg_operand (operands[1], <MODE>mode))"
8020 "#"
8021 [(set_attr "type" "store,load,two,*,*,*")
8022 (set_attr "length" "8,8,8,8,12,16")])
8024 ; ld/std require word-aligned displacements -> 'Y' constraint.
8025 ; List Y->r and r->Y before r->r for reload.
8026 (define_insn "*mov<mode>_hardfloat64"
8027 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,<f64_dm>")
8028 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,r,h,0,G,H,F,wg,r,<f64_dm>,r"))]
8029 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8030 && (gpc_reg_operand (operands[0], <MODE>mode)
8031 || gpc_reg_operand (operands[1], <MODE>mode))"
8032 "@
8033 stfd%U0%X0 %1,%0
8034 lfd%U1%X1 %0,%1
8035 fmr %0,%1
8036 lxsd%U1x %x0,%y1
8037 stxsd%U0x %x1,%y0
8038 xxlor %x0,%x1,%x1
8039 xxlxor %x0,%x0,%x0
8040 std%U0%X0 %1,%0
8041 ld%U1%X1 %0,%1
8042 mr %0,%1
8043 mt%0 %1
8044 mf%1 %0
8045 nop
8046 #
8047 #
8048 #
8049 mftgpr %0,%1
8050 mffgpr %0,%1
8051 mfvsrd %0,%x1
8052 mtvsrd %x0,%1"
8053 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
8054 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
8056 (define_insn "*mov<mode>_softfloat64"
8057 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8058 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8059 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8060 && (gpc_reg_operand (operands[0], <MODE>mode)
8061 || gpc_reg_operand (operands[1], <MODE>mode))"
8062 "@
8063 std%U0%X0 %1,%0
8064 ld%U1%X1 %0,%1
8065 mr %0,%1
8066 mt%0 %1
8067 mf%1 %0
8068 #
8069 #
8070 #
8071 nop"
8072 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8073 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8074 \f
8075 (define_expand "mov<mode>"
8076 [(set (match_operand:FMOVE128 0 "general_operand" "")
8077 (match_operand:FMOVE128 1 "any_operand" ""))]
8078 ""
8079 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8081 ;; It's important to list Y->r and r->Y before r->r because otherwise
8082 ;; reload, given m->r, will try to pick r->r and reload it, which
8083 ;; doesn't make progress.
8085 ;; We can't split little endian direct moves of TDmode, because the words are
8086 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
8087 ;; problematical. Don't allow direct move for this case.
8089 (define_insn_and_split "*mov<mode>_64bit_dm"
8090 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
8091 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
8092 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8093 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
8094 && (gpc_reg_operand (operands[0], <MODE>mode)
8095 || gpc_reg_operand (operands[1], <MODE>mode))"
8096 "#"
8097 "&& reload_completed"
8098 [(pc)]
8099 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8100 [(set_attr "length" "8,8,8,12,12,8,8,8")])
8102 (define_insn_and_split "*movtd_64bit_nodm"
8103 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8104 (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
8105 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
8106 && (gpc_reg_operand (operands[0], TDmode)
8107 || gpc_reg_operand (operands[1], TDmode))"
8108 "#"
8109 "&& reload_completed"
8110 [(pc)]
8111 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8112 [(set_attr "length" "8,8,8,12,12,8")])
8114 (define_insn_and_split "*mov<mode>_32bit"
8115 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8116 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
8117 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
8118 && (gpc_reg_operand (operands[0], <MODE>mode)
8119 || gpc_reg_operand (operands[1], <MODE>mode))"
8120 "#"
8121 "&& reload_completed"
8122 [(pc)]
8123 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8124 [(set_attr "length" "8,8,8,20,20,16")])
8126 (define_insn_and_split "*mov<mode>_softfloat"
8127 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8128 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
8129 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
8130 && (gpc_reg_operand (operands[0], <MODE>mode)
8131 || gpc_reg_operand (operands[1], <MODE>mode))"
8132 "#"
8133 "&& reload_completed"
8134 [(pc)]
8135 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8136 [(set_attr "length" "20,20,16")])
8138 ;; If we are using -ffast-math, easy_fp_constant assumes all constants are
8139 ;; 'easy' in order to allow for reciprocal estimation. Make sure the constant
8140 ;; is in the constant pool before reload occurs. This simplifies accessing
8141 ;; scalars in the traditional Altivec registers.
8143 (define_split
8144 [(set (match_operand:SFDF 0 "register_operand" "")
8145 (match_operand:SFDF 1 "memory_fp_constant" ""))]
8146 "TARGET_<MODE>_FPR && flag_unsafe_math_optimizations
8147 && !reload_in_progress && !reload_completed && !lra_in_progress"
8148 [(set (match_dup 0) (match_dup 2))]
8149 {
8150 operands[2] = validize_mem (force_const_mem (<MODE>mode, operands[1]));
8151 })
8153 (define_expand "extenddftf2"
8154 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8155 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8156 "!TARGET_IEEEQUAD
8157 && TARGET_HARD_FLOAT
8158 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8159 && TARGET_LONG_DOUBLE_128"
8160 {
8161 if (TARGET_E500_DOUBLE)
8162 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8163 else
8164 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8165 DONE;
8166 })
8168 (define_expand "extenddftf2_fprs"
8169 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8170 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8171 (use (match_dup 2))])]
8172 "!TARGET_IEEEQUAD
8173 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8174 && TARGET_LONG_DOUBLE_128"
8175 {
8176 operands[2] = CONST0_RTX (DFmode);
8177 /* Generate GOT reference early for SVR4 PIC. */
8178 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8179 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8180 })
8182 (define_insn_and_split "*extenddftf2_internal"
8183 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8184 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8185 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8186 "!TARGET_IEEEQUAD
8187 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8188 && TARGET_LONG_DOUBLE_128"
8189 "#"
8190 "&& reload_completed"
8191 [(pc)]
8192 {
8193 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8194 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8195 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8196 operands[1]);
8197 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8198 operands[2]);
8199 DONE;
8200 })
8202 (define_expand "extendsftf2"
8203 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8204 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8205 "!TARGET_IEEEQUAD
8206 && TARGET_HARD_FLOAT
8207 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8208 && TARGET_LONG_DOUBLE_128"
8209 {
8210 rtx tmp = gen_reg_rtx (DFmode);
8211 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8212 emit_insn (gen_extenddftf2 (operands[0], tmp));
8213 DONE;
8214 })
8216 (define_expand "trunctfdf2"
8217 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8218 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8219 "!TARGET_IEEEQUAD
8220 && TARGET_HARD_FLOAT
8221 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8222 && TARGET_LONG_DOUBLE_128"
8223 "")
8225 (define_insn_and_split "trunctfdf2_internal1"
8226 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8227 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8228 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8229 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8230 "@
8231 #
8232 fmr %0,%1"
8233 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8234 [(const_int 0)]
8235 {
8236 emit_note (NOTE_INSN_DELETED);
8237 DONE;
8238 }
8239 [(set_attr "type" "fp")])
8241 (define_insn "trunctfdf2_internal2"
8242 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8243 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8244 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8245 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8246 && TARGET_LONG_DOUBLE_128"
8247 "fadd %0,%1,%L1"
8248 [(set_attr "type" "fp")
8249 (set_attr "fp_type" "fp_addsub_d")])
8251 (define_expand "trunctfsf2"
8252 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8253 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8254 "!TARGET_IEEEQUAD
8255 && TARGET_HARD_FLOAT
8256 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8257 && TARGET_LONG_DOUBLE_128"
8258 {
8259 if (TARGET_E500_DOUBLE)
8260 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8261 else
8262 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8263 DONE;
8264 })
8266 (define_insn_and_split "trunctfsf2_fprs"
8267 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8268 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8269 (clobber (match_scratch:DF 2 "=d"))]
8270 "!TARGET_IEEEQUAD
8271 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8272 && TARGET_LONG_DOUBLE_128"
8273 "#"
8274 "&& reload_completed"
8275 [(set (match_dup 2)
8276 (float_truncate:DF (match_dup 1)))
8277 (set (match_dup 0)
8278 (float_truncate:SF (match_dup 2)))]
8279 "")
8281 (define_expand "floatsitf2"
8282 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8283 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8284 "!TARGET_IEEEQUAD
8285 && TARGET_HARD_FLOAT
8286 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8287 && TARGET_LONG_DOUBLE_128"
8288 {
8289 rtx tmp = gen_reg_rtx (DFmode);
8290 expand_float (tmp, operands[1], false);
8291 emit_insn (gen_extenddftf2 (operands[0], tmp));
8292 DONE;
8293 })
8295 ; fadd, but rounding towards zero.
8296 ; This is probably not the optimal code sequence.
8297 (define_insn "fix_trunc_helper"
8298 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8299 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8300 UNSPEC_FIX_TRUNC_TF))
8301 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8302 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8303 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8304 [(set_attr "type" "fp")
8305 (set_attr "length" "20")])
8307 (define_expand "fix_trunctfsi2"
8308 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8309 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8310 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8311 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8312 {
8313 if (TARGET_E500_DOUBLE)
8314 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8315 else
8316 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8317 DONE;
8318 })
8320 (define_expand "fix_trunctfsi2_fprs"
8321 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8322 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8323 (clobber (match_dup 2))
8324 (clobber (match_dup 3))
8325 (clobber (match_dup 4))
8326 (clobber (match_dup 5))])]
8327 "!TARGET_IEEEQUAD
8328 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8329 {
8330 operands[2] = gen_reg_rtx (DFmode);
8331 operands[3] = gen_reg_rtx (DFmode);
8332 operands[4] = gen_reg_rtx (DImode);
8333 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8334 })
8336 (define_insn_and_split "*fix_trunctfsi2_internal"
8337 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8338 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8339 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8340 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8341 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8342 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8343 "!TARGET_IEEEQUAD
8344 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8345 "#"
8346 ""
8347 [(pc)]
8348 {
8349 rtx lowword;
8350 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8352 gcc_assert (MEM_P (operands[5]));
8353 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8355 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8356 emit_move_insn (operands[5], operands[4]);
8357 emit_move_insn (operands[0], lowword);
8358 DONE;
8359 })
8361 (define_expand "negtf2"
8362 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8363 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8364 "!TARGET_IEEEQUAD
8365 && TARGET_HARD_FLOAT
8366 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8367 && TARGET_LONG_DOUBLE_128"
8368 "")
8370 (define_insn "negtf2_internal"
8371 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8372 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8373 "!TARGET_IEEEQUAD
8374 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8375 "*
8376 {
8377 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8378 return \"fneg %L0,%L1\;fneg %0,%1\";
8379 else
8380 return \"fneg %0,%1\;fneg %L0,%L1\";
8381 }"
8382 [(set_attr "type" "fp")
8383 (set_attr "length" "8")])
8385 (define_expand "abstf2"
8386 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8387 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8388 "!TARGET_IEEEQUAD
8389 && TARGET_HARD_FLOAT
8390 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8391 && TARGET_LONG_DOUBLE_128"
8392 "
8393 {
8394 rtx label = gen_label_rtx ();
8395 if (TARGET_E500_DOUBLE)
8396 {
8397 if (flag_finite_math_only && !flag_trapping_math)
8398 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8399 else
8400 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8401 }
8402 else
8403 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8404 emit_label (label);
8405 DONE;
8406 }")
8408 (define_expand "abstf2_internal"
8409 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8410 (match_operand:TF 1 "gpc_reg_operand" ""))
8411 (set (match_dup 3) (match_dup 5))
8412 (set (match_dup 5) (abs:DF (match_dup 5)))
8413 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8414 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8415 (label_ref (match_operand 2 "" ""))
8416 (pc)))
8417 (set (match_dup 6) (neg:DF (match_dup 6)))]
8418 "!TARGET_IEEEQUAD
8419 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8420 && TARGET_LONG_DOUBLE_128"
8421 "
8422 {
8423 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8424 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8425 operands[3] = gen_reg_rtx (DFmode);
8426 operands[4] = gen_reg_rtx (CCFPmode);
8427 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8428 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8429 }")
8430 \f
8431 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
8432 ;; must have 3 arguments, and scratch register constraint must be a single
8433 ;; constraint.
8435 ;; Reload patterns to support gpr load/store with misaligned mem.
8436 ;; and multiple gpr load/store at offset >= 0xfffc
8437 (define_expand "reload_<mode>_store"
8438 [(parallel [(match_operand 0 "memory_operand" "=m")
8439 (match_operand 1 "gpc_reg_operand" "r")
8440 (match_operand:GPR 2 "register_operand" "=&b")])]
8441 ""
8442 {
8443 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8444 DONE;
8445 })
8447 (define_expand "reload_<mode>_load"
8448 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8449 (match_operand 1 "memory_operand" "m")
8450 (match_operand:GPR 2 "register_operand" "=b")])]
8451 ""
8452 {
8453 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8454 DONE;
8455 })
8457 \f
8458 ;; Reload patterns for various types using the vector registers. We may need
8459 ;; an additional base register to convert the reg+offset addressing to reg+reg
8460 ;; for vector registers and reg+reg or (reg+reg)&(-16) addressing to just an
8461 ;; index register for gpr registers.
8462 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_store"
8463 [(parallel [(match_operand:RELOAD 0 "memory_operand" "m")
8464 (match_operand:RELOAD 1 "gpc_reg_operand" "wa")
8465 (match_operand:P 2 "register_operand" "=b")])]
8466 "<P:tptrsize>"
8467 {
8468 rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
8469 DONE;
8470 })
8472 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_load"
8473 [(parallel [(match_operand:RELOAD 0 "gpc_reg_operand" "wa")
8474 (match_operand:RELOAD 1 "memory_operand" "m")
8475 (match_operand:P 2 "register_operand" "=b")])]
8476 "<P:tptrsize>"
8477 {
8478 rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
8479 DONE;
8480 })
8483 ;; Reload sometimes tries to move the address to a GPR, and can generate
8484 ;; invalid RTL for addresses involving AND -16. Allow addresses involving
8485 ;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
8487 (define_insn_and_split "*vec_reload_and_plus_<mptrsize>"
8488 [(set (match_operand:P 0 "gpc_reg_operand" "=b")
8489 (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
8490 (match_operand:P 2 "reg_or_cint_operand" "rI"))
8491 (const_int -16)))]
8492 "TARGET_ALTIVEC && (reload_in_progress || reload_completed)"
8493 "#"
8494 "&& reload_completed"
8495 [(set (match_dup 0)
8496 (plus:P (match_dup 1)
8497 (match_dup 2)))
8498 (set (match_dup 0)
8499 (and:P (match_dup 0)
8500 (const_int -16)))])
8501 \f
8502 ;; Power8 merge instructions to allow direct move to/from floating point
8503 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
8504 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
8505 ;; value, since it is allocated in reload and not all of the flow information
8506 ;; is setup for it. We have two patterns to do the two moves between gprs and
8507 ;; fprs. There isn't a dependancy between the two, but we could potentially
8508 ;; schedule other instructions between the two instructions. TFmode is
8509 ;; currently limited to traditional FPR registers. If/when this is changed, we
8510 ;; will need to revist %L to make sure it works with VSX registers, or add an
8511 ;; %x version of %L.
8513 (define_insn "p8_fmrgow_<mode>"
8514 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
8515 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
8516 UNSPEC_P8V_FMRGOW))]
8517 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8518 "fmrgow %0,%1,%L1"
8519 [(set_attr "type" "vecperm")])
8521 (define_insn "p8_mtvsrwz_1"
8522 [(set (match_operand:TF 0 "register_operand" "=d")
8523 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
8524 UNSPEC_P8V_MTVSRWZ))]
8525 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8526 "mtvsrwz %x0,%1"
8527 [(set_attr "type" "mftgpr")])
8529 (define_insn "p8_mtvsrwz_2"
8530 [(set (match_operand:TF 0 "register_operand" "+d")
8531 (unspec:TF [(match_dup 0)
8532 (match_operand:SI 1 "register_operand" "r")]
8533 UNSPEC_P8V_MTVSRWZ))]
8534 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8535 "mtvsrwz %L0,%1"
8536 [(set_attr "type" "mftgpr")])
8538 (define_insn_and_split "reload_fpr_from_gpr<mode>"
8539 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
8540 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
8541 UNSPEC_P8V_RELOAD_FROM_GPR))
8542 (clobber (match_operand:TF 2 "register_operand" "=d"))]
8543 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8544 "#"
8545 "&& reload_completed"
8546 [(const_int 0)]
8547 {
8548 rtx dest = operands[0];
8549 rtx src = operands[1];
8550 rtx tmp = operands[2];
8551 rtx gpr_hi_reg = gen_highpart (SImode, src);
8552 rtx gpr_lo_reg = gen_lowpart (SImode, src);
8554 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
8555 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
8556 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
8557 DONE;
8558 }
8559 [(set_attr "length" "12")
8560 (set_attr "type" "three")])
8562 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
8563 (define_insn "p8_mtvsrd_1"
8564 [(set (match_operand:TF 0 "register_operand" "=ws")
8565 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
8566 UNSPEC_P8V_MTVSRD))]
8567 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8568 "mtvsrd %0,%1"
8569 [(set_attr "type" "mftgpr")])
8571 (define_insn "p8_mtvsrd_2"
8572 [(set (match_operand:TF 0 "register_operand" "+ws")
8573 (unspec:TF [(match_dup 0)
8574 (match_operand:DI 1 "register_operand" "r")]
8575 UNSPEC_P8V_MTVSRD))]
8576 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8577 "mtvsrd %L0,%1"
8578 [(set_attr "type" "mftgpr")])
8580 (define_insn "p8_xxpermdi_<mode>"
8581 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8582 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
8583 UNSPEC_P8V_XXPERMDI))]
8584 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8585 "xxpermdi %x0,%1,%L1,0"
8586 [(set_attr "type" "vecperm")])
8588 (define_insn_and_split "reload_vsx_from_gpr<mode>"
8589 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8590 (unspec:FMOVE128_GPR
8591 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
8592 UNSPEC_P8V_RELOAD_FROM_GPR))
8593 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
8594 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8595 "#"
8596 "&& reload_completed"
8597 [(const_int 0)]
8598 {
8599 rtx dest = operands[0];
8600 rtx src = operands[1];
8601 rtx tmp = operands[2];
8602 rtx gpr_hi_reg = gen_highpart (DImode, src);
8603 rtx gpr_lo_reg = gen_lowpart (DImode, src);
8605 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
8606 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
8607 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
8608 }
8609 [(set_attr "length" "12")
8610 (set_attr "type" "three")])
8612 (define_split
8613 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
8614 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
8615 "reload_completed
8616 && (int_reg_operand (operands[0], <MODE>mode)
8617 || int_reg_operand (operands[1], <MODE>mode))"
8618 [(pc)]
8619 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8621 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
8622 ;; type is stored internally as double precision in the VSX registers, we have
8623 ;; to convert it from the vector format.
8625 (define_insn_and_split "reload_vsx_from_gprsf"
8626 [(set (match_operand:SF 0 "register_operand" "=wa")
8627 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
8628 UNSPEC_P8V_RELOAD_FROM_GPR))
8629 (clobber (match_operand:DI 2 "register_operand" "=r"))]
8630 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8631 "#"
8632 "&& reload_completed"
8633 [(const_int 0)]
8634 {
8635 rtx op0 = operands[0];
8636 rtx op1 = operands[1];
8637 rtx op2 = operands[2];
8638 /* Also use the destination register to hold the unconverted DImode value.
8639 This is conceptually a separate value from OP0, so we use gen_rtx_REG
8640 rather than simplify_gen_subreg. */
8641 rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
8642 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
8644 /* Move SF value to upper 32-bits for xscvspdpn. */
8645 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
8646 emit_move_insn (op0_di, op2);
8647 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
8648 DONE;
8649 }
8650 [(set_attr "length" "8")
8651 (set_attr "type" "two")])
8653 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
8654 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
8655 ;; and then doing a move of that.
8656 (define_insn "p8_mfvsrd_3_<mode>"
8657 [(set (match_operand:DF 0 "register_operand" "=r")
8658 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8659 UNSPEC_P8V_RELOAD_FROM_VSX))]
8660 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8661 "mfvsrd %0,%x1"
8662 [(set_attr "type" "mftgpr")])
8664 (define_insn_and_split "reload_gpr_from_vsx<mode>"
8665 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
8666 (unspec:FMOVE128_GPR
8667 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8668 UNSPEC_P8V_RELOAD_FROM_VSX))
8669 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
8670 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8671 "#"
8672 "&& reload_completed"
8673 [(const_int 0)]
8674 {
8675 rtx dest = operands[0];
8676 rtx src = operands[1];
8677 rtx tmp = operands[2];
8678 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
8679 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
8681 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
8682 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
8683 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
8684 }
8685 [(set_attr "length" "12")
8686 (set_attr "type" "three")])
8688 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
8689 ;; type is stored internally as double precision, we have to convert it to the
8690 ;; vector format.
8692 (define_insn_and_split "reload_gpr_from_vsxsf"
8693 [(set (match_operand:SF 0 "register_operand" "=r")
8694 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
8695 UNSPEC_P8V_RELOAD_FROM_VSX))
8696 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
8697 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8698 "#"
8699 "&& reload_completed"
8700 [(const_int 0)]
8701 {
8702 rtx op0 = operands[0];
8703 rtx op1 = operands[1];
8704 rtx op2 = operands[2];
8705 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
8707 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
8708 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
8709 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
8710 DONE;
8711 }
8712 [(set_attr "length" "12")
8713 (set_attr "type" "three")])
8715 (define_insn "p8_mfvsrd_4_disf"
8716 [(set (match_operand:DI 0 "register_operand" "=r")
8717 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
8718 UNSPEC_P8V_RELOAD_FROM_VSX))]
8719 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8720 "mfvsrd %0,%x1"
8721 [(set_attr "type" "mftgpr")])
8723 \f
8724 ;; Next come the multi-word integer load and store and the load and store
8725 ;; multiple insns.
8727 ;; List r->r after r->Y, otherwise reload will try to reload a
8728 ;; non-offsettable address by using r->r which won't make progress.
8729 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8730 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8731 (define_insn "*movdi_internal32"
8732 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
8733 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
8734 "! TARGET_POWERPC64
8735 && (gpc_reg_operand (operands[0], DImode)
8736 || gpc_reg_operand (operands[1], DImode))"
8737 "@
8738 #
8739 #
8740 #
8741 stfd%U0%X0 %1,%0
8742 lfd%U1%X1 %0,%1
8743 fmr %0,%1
8744 #"
8745 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
8747 (define_split
8748 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8749 (match_operand:DI 1 "const_int_operand" ""))]
8750 "! TARGET_POWERPC64 && reload_completed
8751 && gpr_or_gpr_p (operands[0], operands[1])
8752 && !direct_move_p (operands[0], operands[1])"
8753 [(set (match_dup 2) (match_dup 4))
8754 (set (match_dup 3) (match_dup 1))]
8755 "
8756 {
8757 HOST_WIDE_INT value = INTVAL (operands[1]);
8758 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8759 DImode);
8760 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8761 DImode);
8762 operands[4] = GEN_INT (value >> 32);
8763 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8764 }")
8766 (define_split
8767 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8768 (match_operand:DIFD 1 "input_operand" ""))]
8769 "reload_completed && !TARGET_POWERPC64
8770 && gpr_or_gpr_p (operands[0], operands[1])
8771 && !direct_move_p (operands[0], operands[1])"
8772 [(pc)]
8773 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8775 (define_insn "*movdi_internal64"
8776 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
8777 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
8778 "TARGET_POWERPC64
8779 && (gpc_reg_operand (operands[0], DImode)
8780 || gpc_reg_operand (operands[1], DImode))"
8781 "@
8782 std%U0%X0 %1,%0
8783 ld%U1%X1 %0,%1
8784 mr %0,%1
8785 li %0,%1
8786 lis %0,%v1
8787 #
8788 stfd%U0%X0 %1,%0
8789 lfd%U1%X1 %0,%1
8790 fmr %0,%1
8791 mf%1 %0
8792 mt%0 %1
8793 nop
8794 mftgpr %0,%1
8795 mffgpr %0,%1
8796 mfvsrd %0,%x1
8797 mtvsrd %x0,%1
8798 xxlxor %x0,%x0,%x0"
8799 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple")
8800 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
8802 ;; Generate all one-bits and clear left or right.
8803 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8804 (define_split
8805 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8806 (match_operand:DI 1 "mask64_operand" ""))]
8807 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8808 [(set (match_dup 0) (const_int -1))
8809 (set (match_dup 0)
8810 (and:DI (rotate:DI (match_dup 0)
8811 (const_int 0))
8812 (match_dup 1)))]
8813 "")
8815 ;; Split a load of a large constant into the appropriate five-instruction
8816 ;; sequence. Handle anything in a constant number of insns.
8817 ;; When non-easy constants can go in the TOC, this should use
8818 ;; easy_fp_constant predicate.
8819 (define_split
8820 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8821 (match_operand:DI 1 "const_int_operand" ""))]
8822 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8823 [(set (match_dup 0) (match_dup 2))
8824 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8825 "
8826 {
8827 if (rs6000_emit_set_const (operands[0], operands[1]))
8828 DONE;
8829 else
8830 FAIL;
8831 }")
8833 (define_split
8834 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8835 (match_operand:DI 1 "const_scalar_int_operand" ""))]
8836 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8837 [(set (match_dup 0) (match_dup 2))
8838 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8839 "
8840 {
8841 if (rs6000_emit_set_const (operands[0], operands[1]))
8842 DONE;
8843 else
8844 FAIL;
8845 }")
8846 \f
8847 ;; TImode/PTImode is similar, except that we usually want to compute the
8848 ;; address into a register and use lsi/stsi (the exception is during reload).
8850 (define_insn "*mov<mode>_string"
8851 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8852 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
8853 "! TARGET_POWERPC64
8854 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
8855 && (gpc_reg_operand (operands[0], <MODE>mode)
8856 || gpc_reg_operand (operands[1], <MODE>mode))"
8857 "*
8858 {
8859 switch (which_alternative)
8860 {
8861 default:
8862 gcc_unreachable ();
8863 case 0:
8864 if (TARGET_STRING)
8865 return \"stswi %1,%P0,16\";
8866 case 1:
8867 return \"#\";
8868 case 2:
8869 /* If the address is not used in the output, we can use lsi. Otherwise,
8870 fall through to generating four loads. */
8871 if (TARGET_STRING
8872 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8873 return \"lswi %0,%P1,16\";
8874 /* ... fall through ... */
8875 case 3:
8876 case 4:
8877 case 5:
8878 return \"#\";
8879 }
8880 }"
8881 [(set_attr "type" "store,store,load,load,*,*")
8882 (set_attr "update" "yes")
8883 (set_attr "indexed" "yes")
8884 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8885 (const_string "always")
8886 (const_string "conditional")))])
8888 (define_insn "*mov<mode>_ppc64"
8889 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
8890 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
8891 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
8892 && (gpc_reg_operand (operands[0], <MODE>mode)
8893 || gpc_reg_operand (operands[1], <MODE>mode)))"
8894 {
8895 return rs6000_output_move_128bit (operands);
8896 }
8897 [(set_attr "type" "store,store,load,load,*,*")
8898 (set_attr "length" "8")])
8900 (define_split
8901 [(set (match_operand:TI2 0 "int_reg_operand" "")
8902 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
8903 "TARGET_POWERPC64
8904 && (VECTOR_MEM_NONE_P (<MODE>mode)
8905 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
8906 [(set (match_dup 2) (match_dup 4))
8907 (set (match_dup 3) (match_dup 5))]
8908 "
8909 {
8910 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8911 <MODE>mode);
8912 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8913 <MODE>mode);
8914 if (CONST_WIDE_INT_P (operands[1]))
8915 {
8916 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
8917 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
8918 }
8919 else if (CONST_INT_P (operands[1]))
8920 {
8921 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8922 operands[5] = operands[1];
8923 }
8924 else
8925 FAIL;
8926 }")
8928 (define_split
8929 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
8930 (match_operand:TI2 1 "input_operand" ""))]
8931 "reload_completed
8932 && gpr_or_gpr_p (operands[0], operands[1])
8933 && !direct_move_p (operands[0], operands[1])
8934 && !quad_load_store_p (operands[0], operands[1])"
8935 [(pc)]
8936 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8937 \f
8938 (define_expand "load_multiple"
8939 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8940 (match_operand:SI 1 "" ""))
8941 (use (match_operand:SI 2 "" ""))])]
8942 "TARGET_STRING && !TARGET_POWERPC64"
8943 "
8944 {
8945 int regno;
8946 int count;
8947 rtx op1;
8948 int i;
8950 /* Support only loading a constant number of fixed-point registers from
8951 memory and only bother with this if more than two; the machine
8952 doesn't support more than eight. */
8953 if (GET_CODE (operands[2]) != CONST_INT
8954 || INTVAL (operands[2]) <= 2
8955 || INTVAL (operands[2]) > 8
8956 || GET_CODE (operands[1]) != MEM
8957 || GET_CODE (operands[0]) != REG
8958 || REGNO (operands[0]) >= 32)
8959 FAIL;
8961 count = INTVAL (operands[2]);
8962 regno = REGNO (operands[0]);
8964 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8965 op1 = replace_equiv_address (operands[1],
8966 force_reg (SImode, XEXP (operands[1], 0)));
8968 for (i = 0; i < count; i++)
8969 XVECEXP (operands[3], 0, i)
8970 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8971 adjust_address_nv (op1, SImode, i * 4));
8972 }")
8974 (define_insn "*ldmsi8"
8975 [(match_parallel 0 "load_multiple_operation"
8976 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8977 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8978 (set (match_operand:SI 3 "gpc_reg_operand" "")
8979 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8980 (set (match_operand:SI 4 "gpc_reg_operand" "")
8981 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8982 (set (match_operand:SI 5 "gpc_reg_operand" "")
8983 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8984 (set (match_operand:SI 6 "gpc_reg_operand" "")
8985 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8986 (set (match_operand:SI 7 "gpc_reg_operand" "")
8987 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8988 (set (match_operand:SI 8 "gpc_reg_operand" "")
8989 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8990 (set (match_operand:SI 9 "gpc_reg_operand" "")
8991 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8992 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8993 "*
8994 { return rs6000_output_load_multiple (operands); }"
8995 [(set_attr "type" "load")
8996 (set_attr "update" "yes")
8997 (set_attr "indexed" "yes")
8998 (set_attr "length" "32")])
9000 (define_insn "*ldmsi7"
9001 [(match_parallel 0 "load_multiple_operation"
9002 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9003 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9004 (set (match_operand:SI 3 "gpc_reg_operand" "")
9005 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9006 (set (match_operand:SI 4 "gpc_reg_operand" "")
9007 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9008 (set (match_operand:SI 5 "gpc_reg_operand" "")
9009 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9010 (set (match_operand:SI 6 "gpc_reg_operand" "")
9011 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9012 (set (match_operand:SI 7 "gpc_reg_operand" "")
9013 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9014 (set (match_operand:SI 8 "gpc_reg_operand" "")
9015 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9016 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9017 "*
9018 { return rs6000_output_load_multiple (operands); }"
9019 [(set_attr "type" "load")
9020 (set_attr "update" "yes")
9021 (set_attr "indexed" "yes")
9022 (set_attr "length" "32")])
9024 (define_insn "*ldmsi6"
9025 [(match_parallel 0 "load_multiple_operation"
9026 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9027 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9028 (set (match_operand:SI 3 "gpc_reg_operand" "")
9029 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9030 (set (match_operand:SI 4 "gpc_reg_operand" "")
9031 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9032 (set (match_operand:SI 5 "gpc_reg_operand" "")
9033 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9034 (set (match_operand:SI 6 "gpc_reg_operand" "")
9035 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9036 (set (match_operand:SI 7 "gpc_reg_operand" "")
9037 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9038 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9039 "*
9040 { return rs6000_output_load_multiple (operands); }"
9041 [(set_attr "type" "load")
9042 (set_attr "update" "yes")
9043 (set_attr "indexed" "yes")
9044 (set_attr "length" "32")])
9046 (define_insn "*ldmsi5"
9047 [(match_parallel 0 "load_multiple_operation"
9048 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9049 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9050 (set (match_operand:SI 3 "gpc_reg_operand" "")
9051 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9052 (set (match_operand:SI 4 "gpc_reg_operand" "")
9053 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9054 (set (match_operand:SI 5 "gpc_reg_operand" "")
9055 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9056 (set (match_operand:SI 6 "gpc_reg_operand" "")
9057 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9058 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9059 "*
9060 { return rs6000_output_load_multiple (operands); }"
9061 [(set_attr "type" "load")
9062 (set_attr "update" "yes")
9063 (set_attr "indexed" "yes")
9064 (set_attr "length" "32")])
9066 (define_insn "*ldmsi4"
9067 [(match_parallel 0 "load_multiple_operation"
9068 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9069 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9070 (set (match_operand:SI 3 "gpc_reg_operand" "")
9071 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9072 (set (match_operand:SI 4 "gpc_reg_operand" "")
9073 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9074 (set (match_operand:SI 5 "gpc_reg_operand" "")
9075 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9076 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9077 "*
9078 { return rs6000_output_load_multiple (operands); }"
9079 [(set_attr "type" "load")
9080 (set_attr "update" "yes")
9081 (set_attr "indexed" "yes")
9082 (set_attr "length" "32")])
9084 (define_insn "*ldmsi3"
9085 [(match_parallel 0 "load_multiple_operation"
9086 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9087 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9088 (set (match_operand:SI 3 "gpc_reg_operand" "")
9089 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9090 (set (match_operand:SI 4 "gpc_reg_operand" "")
9091 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9092 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9093 "*
9094 { return rs6000_output_load_multiple (operands); }"
9095 [(set_attr "type" "load")
9096 (set_attr "update" "yes")
9097 (set_attr "indexed" "yes")
9098 (set_attr "length" "32")])
9100 (define_expand "store_multiple"
9101 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9102 (match_operand:SI 1 "" ""))
9103 (clobber (scratch:SI))
9104 (use (match_operand:SI 2 "" ""))])]
9105 "TARGET_STRING && !TARGET_POWERPC64"
9106 "
9107 {
9108 int regno;
9109 int count;
9110 rtx to;
9111 rtx op0;
9112 int i;
9114 /* Support only storing a constant number of fixed-point registers to
9115 memory and only bother with this if more than two; the machine
9116 doesn't support more than eight. */
9117 if (GET_CODE (operands[2]) != CONST_INT
9118 || INTVAL (operands[2]) <= 2
9119 || INTVAL (operands[2]) > 8
9120 || GET_CODE (operands[0]) != MEM
9121 || GET_CODE (operands[1]) != REG
9122 || REGNO (operands[1]) >= 32)
9123 FAIL;
9125 count = INTVAL (operands[2]);
9126 regno = REGNO (operands[1]);
9128 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9129 to = force_reg (SImode, XEXP (operands[0], 0));
9130 op0 = replace_equiv_address (operands[0], to);
9132 XVECEXP (operands[3], 0, 0)
9133 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9134 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9135 gen_rtx_SCRATCH (SImode));
9137 for (i = 1; i < count; i++)
9138 XVECEXP (operands[3], 0, i + 1)
9139 = gen_rtx_SET (VOIDmode,
9140 adjust_address_nv (op0, SImode, i * 4),
9141 gen_rtx_REG (SImode, regno + i));
9142 }")
9144 (define_insn "*stmsi8"
9145 [(match_parallel 0 "store_multiple_operation"
9146 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9147 (match_operand:SI 2 "gpc_reg_operand" "r"))
9148 (clobber (match_scratch:SI 3 "=X"))
9149 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9150 (match_operand:SI 4 "gpc_reg_operand" "r"))
9151 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9152 (match_operand:SI 5 "gpc_reg_operand" "r"))
9153 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9154 (match_operand:SI 6 "gpc_reg_operand" "r"))
9155 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9156 (match_operand:SI 7 "gpc_reg_operand" "r"))
9157 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9158 (match_operand:SI 8 "gpc_reg_operand" "r"))
9159 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9160 (match_operand:SI 9 "gpc_reg_operand" "r"))
9161 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9162 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9163 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9164 "stswi %2,%1,%O0"
9165 [(set_attr "type" "store")
9166 (set_attr "update" "yes")
9167 (set_attr "indexed" "yes")
9168 (set_attr "cell_micro" "always")])
9170 (define_insn "*stmsi7"
9171 [(match_parallel 0 "store_multiple_operation"
9172 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9173 (match_operand:SI 2 "gpc_reg_operand" "r"))
9174 (clobber (match_scratch:SI 3 "=X"))
9175 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9176 (match_operand:SI 4 "gpc_reg_operand" "r"))
9177 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9178 (match_operand:SI 5 "gpc_reg_operand" "r"))
9179 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9180 (match_operand:SI 6 "gpc_reg_operand" "r"))
9181 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9182 (match_operand:SI 7 "gpc_reg_operand" "r"))
9183 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9184 (match_operand:SI 8 "gpc_reg_operand" "r"))
9185 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9186 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9187 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9188 "stswi %2,%1,%O0"
9189 [(set_attr "type" "store")
9190 (set_attr "update" "yes")
9191 (set_attr "indexed" "yes")
9192 (set_attr "cell_micro" "always")])
9194 (define_insn "*stmsi6"
9195 [(match_parallel 0 "store_multiple_operation"
9196 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9197 (match_operand:SI 2 "gpc_reg_operand" "r"))
9198 (clobber (match_scratch:SI 3 "=X"))
9199 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9200 (match_operand:SI 4 "gpc_reg_operand" "r"))
9201 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9202 (match_operand:SI 5 "gpc_reg_operand" "r"))
9203 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9204 (match_operand:SI 6 "gpc_reg_operand" "r"))
9205 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9206 (match_operand:SI 7 "gpc_reg_operand" "r"))
9207 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9208 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9209 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9210 "stswi %2,%1,%O0"
9211 [(set_attr "type" "store")
9212 (set_attr "update" "yes")
9213 (set_attr "indexed" "yes")
9214 (set_attr "cell_micro" "always")])
9216 (define_insn "*stmsi5"
9217 [(match_parallel 0 "store_multiple_operation"
9218 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9219 (match_operand:SI 2 "gpc_reg_operand" "r"))
9220 (clobber (match_scratch:SI 3 "=X"))
9221 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9222 (match_operand:SI 4 "gpc_reg_operand" "r"))
9223 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9224 (match_operand:SI 5 "gpc_reg_operand" "r"))
9225 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9226 (match_operand:SI 6 "gpc_reg_operand" "r"))
9227 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9228 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9229 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9230 "stswi %2,%1,%O0"
9231 [(set_attr "type" "store")
9232 (set_attr "update" "yes")
9233 (set_attr "indexed" "yes")
9234 (set_attr "cell_micro" "always")])
9236 (define_insn "*stmsi4"
9237 [(match_parallel 0 "store_multiple_operation"
9238 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9239 (match_operand:SI 2 "gpc_reg_operand" "r"))
9240 (clobber (match_scratch:SI 3 "=X"))
9241 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9242 (match_operand:SI 4 "gpc_reg_operand" "r"))
9243 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9244 (match_operand:SI 5 "gpc_reg_operand" "r"))
9245 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9246 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9247 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9248 "stswi %2,%1,%O0"
9249 [(set_attr "type" "store")
9250 (set_attr "update" "yes")
9251 (set_attr "indexed" "yes")
9252 (set_attr "cell_micro" "always")])
9254 (define_insn "*stmsi3"
9255 [(match_parallel 0 "store_multiple_operation"
9256 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9257 (match_operand:SI 2 "gpc_reg_operand" "r"))
9258 (clobber (match_scratch:SI 3 "=X"))
9259 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9260 (match_operand:SI 4 "gpc_reg_operand" "r"))
9261 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9262 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9263 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9264 "stswi %2,%1,%O0"
9265 [(set_attr "type" "store")
9266 (set_attr "update" "yes")
9267 (set_attr "indexed" "yes")
9268 (set_attr "cell_micro" "always")])
9269 \f
9270 (define_expand "setmemsi"
9271 [(parallel [(set (match_operand:BLK 0 "" "")
9272 (match_operand 2 "const_int_operand" ""))
9273 (use (match_operand:SI 1 "" ""))
9274 (use (match_operand:SI 3 "" ""))])]
9275 ""
9276 "
9277 {
9278 /* If value to set is not zero, use the library routine. */
9279 if (operands[2] != const0_rtx)
9280 FAIL;
9282 if (expand_block_clear (operands))
9283 DONE;
9284 else
9285 FAIL;
9286 }")
9288 ;; String/block move insn.
9289 ;; Argument 0 is the destination
9290 ;; Argument 1 is the source
9291 ;; Argument 2 is the length
9292 ;; Argument 3 is the alignment
9294 (define_expand "movmemsi"
9295 [(parallel [(set (match_operand:BLK 0 "" "")
9296 (match_operand:BLK 1 "" ""))
9297 (use (match_operand:SI 2 "" ""))
9298 (use (match_operand:SI 3 "" ""))])]
9299 ""
9300 "
9301 {
9302 if (expand_block_move (operands))
9303 DONE;
9304 else
9305 FAIL;
9306 }")
9308 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9309 ;; register allocator doesn't have a clue about allocating 8 word registers.
9310 ;; rD/rS = r5 is preferred, efficient form.
9311 (define_expand "movmemsi_8reg"
9312 [(parallel [(set (match_operand 0 "" "")
9313 (match_operand 1 "" ""))
9314 (use (match_operand 2 "" ""))
9315 (use (match_operand 3 "" ""))
9316 (clobber (reg:SI 5))
9317 (clobber (reg:SI 6))
9318 (clobber (reg:SI 7))
9319 (clobber (reg:SI 8))
9320 (clobber (reg:SI 9))
9321 (clobber (reg:SI 10))
9322 (clobber (reg:SI 11))
9323 (clobber (reg:SI 12))
9324 (clobber (match_scratch:SI 4 ""))])]
9325 "TARGET_STRING"
9326 "")
9328 (define_insn ""
9329 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9330 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9331 (use (match_operand:SI 2 "immediate_operand" "i"))
9332 (use (match_operand:SI 3 "immediate_operand" "i"))
9333 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9334 (clobber (reg:SI 6))
9335 (clobber (reg:SI 7))
9336 (clobber (reg:SI 8))
9337 (clobber (reg:SI 9))
9338 (clobber (reg:SI 10))
9339 (clobber (reg:SI 11))
9340 (clobber (reg:SI 12))
9341 (clobber (match_scratch:SI 5 "=X"))]
9342 "TARGET_STRING
9343 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9344 || INTVAL (operands[2]) == 0)
9345 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9346 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9347 && REGNO (operands[4]) == 5"
9348 "lswi %4,%1,%2\;stswi %4,%0,%2"
9349 [(set_attr "type" "store")
9350 (set_attr "update" "yes")
9351 (set_attr "indexed" "yes")
9352 (set_attr "cell_micro" "always")
9353 (set_attr "length" "8")])
9355 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9356 ;; register allocator doesn't have a clue about allocating 6 word registers.
9357 ;; rD/rS = r5 is preferred, efficient form.
9358 (define_expand "movmemsi_6reg"
9359 [(parallel [(set (match_operand 0 "" "")
9360 (match_operand 1 "" ""))
9361 (use (match_operand 2 "" ""))
9362 (use (match_operand 3 "" ""))
9363 (clobber (reg:SI 5))
9364 (clobber (reg:SI 6))
9365 (clobber (reg:SI 7))
9366 (clobber (reg:SI 8))
9367 (clobber (reg:SI 9))
9368 (clobber (reg:SI 10))
9369 (clobber (match_scratch:SI 4 ""))])]
9370 "TARGET_STRING"
9371 "")
9373 (define_insn ""
9374 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9375 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9376 (use (match_operand:SI 2 "immediate_operand" "i"))
9377 (use (match_operand:SI 3 "immediate_operand" "i"))
9378 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9379 (clobber (reg:SI 6))
9380 (clobber (reg:SI 7))
9381 (clobber (reg:SI 8))
9382 (clobber (reg:SI 9))
9383 (clobber (reg:SI 10))
9384 (clobber (match_scratch:SI 5 "=X"))]
9385 "TARGET_STRING
9386 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9387 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9388 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9389 && REGNO (operands[4]) == 5"
9390 "lswi %4,%1,%2\;stswi %4,%0,%2"
9391 [(set_attr "type" "store")
9392 (set_attr "update" "yes")
9393 (set_attr "indexed" "yes")
9394 (set_attr "cell_micro" "always")
9395 (set_attr "length" "8")])
9397 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9398 ;; problems with TImode.
9399 ;; rD/rS = r5 is preferred, efficient form.
9400 (define_expand "movmemsi_4reg"
9401 [(parallel [(set (match_operand 0 "" "")
9402 (match_operand 1 "" ""))
9403 (use (match_operand 2 "" ""))
9404 (use (match_operand 3 "" ""))
9405 (clobber (reg:SI 5))
9406 (clobber (reg:SI 6))
9407 (clobber (reg:SI 7))
9408 (clobber (reg:SI 8))
9409 (clobber (match_scratch:SI 4 ""))])]
9410 "TARGET_STRING"
9411 "")
9413 (define_insn ""
9414 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9415 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9416 (use (match_operand:SI 2 "immediate_operand" "i"))
9417 (use (match_operand:SI 3 "immediate_operand" "i"))
9418 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9419 (clobber (reg:SI 6))
9420 (clobber (reg:SI 7))
9421 (clobber (reg:SI 8))
9422 (clobber (match_scratch:SI 5 "=X"))]
9423 "TARGET_STRING
9424 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9425 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9426 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9427 && REGNO (operands[4]) == 5"
9428 "lswi %4,%1,%2\;stswi %4,%0,%2"
9429 [(set_attr "type" "store")
9430 (set_attr "update" "yes")
9431 (set_attr "indexed" "yes")
9432 (set_attr "cell_micro" "always")
9433 (set_attr "length" "8")])
9435 ;; Move up to 8 bytes at a time.
9436 (define_expand "movmemsi_2reg"
9437 [(parallel [(set (match_operand 0 "" "")
9438 (match_operand 1 "" ""))
9439 (use (match_operand 2 "" ""))
9440 (use (match_operand 3 "" ""))
9441 (clobber (match_scratch:DI 4 ""))
9442 (clobber (match_scratch:SI 5 ""))])]
9443 "TARGET_STRING && ! TARGET_POWERPC64"
9444 "")
9446 (define_insn ""
9447 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9448 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9449 (use (match_operand:SI 2 "immediate_operand" "i"))
9450 (use (match_operand:SI 3 "immediate_operand" "i"))
9451 (clobber (match_scratch:DI 4 "=&r"))
9452 (clobber (match_scratch:SI 5 "=X"))]
9453 "TARGET_STRING && ! TARGET_POWERPC64
9454 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9455 "lswi %4,%1,%2\;stswi %4,%0,%2"
9456 [(set_attr "type" "store")
9457 (set_attr "update" "yes")
9458 (set_attr "indexed" "yes")
9459 (set_attr "cell_micro" "always")
9460 (set_attr "length" "8")])
9462 ;; Move up to 4 bytes at a time.
9463 (define_expand "movmemsi_1reg"
9464 [(parallel [(set (match_operand 0 "" "")
9465 (match_operand 1 "" ""))
9466 (use (match_operand 2 "" ""))
9467 (use (match_operand 3 "" ""))
9468 (clobber (match_scratch:SI 4 ""))
9469 (clobber (match_scratch:SI 5 ""))])]
9470 "TARGET_STRING"
9471 "")
9473 (define_insn ""
9474 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9475 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9476 (use (match_operand:SI 2 "immediate_operand" "i"))
9477 (use (match_operand:SI 3 "immediate_operand" "i"))
9478 (clobber (match_scratch:SI 4 "=&r"))
9479 (clobber (match_scratch:SI 5 "=X"))]
9480 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9481 "lswi %4,%1,%2\;stswi %4,%0,%2"
9482 [(set_attr "type" "store")
9483 (set_attr "update" "yes")
9484 (set_attr "indexed" "yes")
9485 (set_attr "cell_micro" "always")
9486 (set_attr "length" "8")])
9487 \f
9488 ;; Define insns that do load or store with update. Some of these we can
9489 ;; get by using pre-decrement or pre-increment, but the hardware can also
9490 ;; do cases where the increment is not the size of the object.
9491 ;;
9492 ;; In all these cases, we use operands 0 and 1 for the register being
9493 ;; incremented because those are the operands that local-alloc will
9494 ;; tie and these are the pair most likely to be tieable (and the ones
9495 ;; that will benefit the most).
9497 (define_insn "*movdi_update1"
9498 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9499 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9500 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9501 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9502 (plus:DI (match_dup 1) (match_dup 2)))]
9503 "TARGET_POWERPC64 && TARGET_UPDATE
9504 && (!avoiding_indexed_address_p (DImode)
9505 || !gpc_reg_operand (operands[2], DImode))"
9506 "@
9507 ldux %3,%0,%2
9508 ldu %3,%2(%0)"
9509 [(set_attr "type" "load")
9510 (set_attr "update" "yes")
9511 (set_attr "indexed" "yes,no")])
9513 (define_insn "movdi_<mode>_update"
9514 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9515 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9516 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9517 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9518 (plus:P (match_dup 1) (match_dup 2)))]
9519 "TARGET_POWERPC64 && TARGET_UPDATE
9520 && (!avoiding_indexed_address_p (Pmode)
9521 || !gpc_reg_operand (operands[2], Pmode)
9522 || (REG_P (operands[0])
9523 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9524 "@
9525 stdux %3,%0,%2
9526 stdu %3,%2(%0)"
9527 [(set_attr "type" "store")
9528 (set_attr "update" "yes")
9529 (set_attr "indexed" "yes,no")])
9531 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9532 ;; needed for stack allocation, even if the user passes -mno-update.
9533 (define_insn "movdi_<mode>_update_stack"
9534 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9535 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9536 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9537 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9538 (plus:P (match_dup 1) (match_dup 2)))]
9539 "TARGET_POWERPC64"
9540 "@
9541 stdux %3,%0,%2
9542 stdu %3,%2(%0)"
9543 [(set_attr "type" "store")
9544 (set_attr "update" "yes")
9545 (set_attr "indexed" "yes,no")])
9547 (define_insn "*movsi_update1"
9548 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9549 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9550 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9551 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9552 (plus:SI (match_dup 1) (match_dup 2)))]
9553 "TARGET_UPDATE
9554 && (!avoiding_indexed_address_p (SImode)
9555 || !gpc_reg_operand (operands[2], SImode))"
9556 "@
9557 lwzux %3,%0,%2
9558 lwzu %3,%2(%0)"
9559 [(set_attr "type" "load")
9560 (set_attr "update" "yes")
9561 (set_attr "indexed" "yes,no")])
9563 (define_insn "*movsi_update2"
9564 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9565 (sign_extend:DI
9566 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9567 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9568 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9569 (plus:DI (match_dup 1) (match_dup 2)))]
9570 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9571 && !avoiding_indexed_address_p (DImode)"
9572 "lwaux %3,%0,%2"
9573 [(set_attr "type" "load")
9574 (set_attr "sign_extend" "yes")
9575 (set_attr "update" "yes")
9576 (set_attr "indexed" "yes")])
9578 (define_insn "movsi_update"
9579 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9580 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9581 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9582 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9583 (plus:SI (match_dup 1) (match_dup 2)))]
9584 "TARGET_UPDATE
9585 && (!avoiding_indexed_address_p (SImode)
9586 || !gpc_reg_operand (operands[2], SImode)
9587 || (REG_P (operands[0])
9588 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9589 "@
9590 stwux %3,%0,%2
9591 stwu %3,%2(%0)"
9592 [(set_attr "type" "store")
9593 (set_attr "update" "yes")
9594 (set_attr "indexed" "yes,no")])
9596 ;; This is an unconditional pattern; needed for stack allocation, even
9597 ;; if the user passes -mno-update.
9598 (define_insn "movsi_update_stack"
9599 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9600 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9601 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9602 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9603 (plus:SI (match_dup 1) (match_dup 2)))]
9604 ""
9605 "@
9606 stwux %3,%0,%2
9607 stwu %3,%2(%0)"
9608 [(set_attr "type" "store")
9609 (set_attr "update" "yes")
9610 (set_attr "indexed" "yes,no")])
9612 (define_insn "*movhi_update1"
9613 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9614 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9615 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9616 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9617 (plus:SI (match_dup 1) (match_dup 2)))]
9618 "TARGET_UPDATE
9619 && (!avoiding_indexed_address_p (SImode)
9620 || !gpc_reg_operand (operands[2], SImode))"
9621 "@
9622 lhzux %3,%0,%2
9623 lhzu %3,%2(%0)"
9624 [(set_attr "type" "load")
9625 (set_attr "update" "yes")
9626 (set_attr "indexed" "yes,no")])
9628 (define_insn "*movhi_update2"
9629 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9630 (zero_extend:SI
9631 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9632 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9633 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9634 (plus:SI (match_dup 1) (match_dup 2)))]
9635 "TARGET_UPDATE
9636 && (!avoiding_indexed_address_p (SImode)
9637 || !gpc_reg_operand (operands[2], SImode))"
9638 "@
9639 lhzux %3,%0,%2
9640 lhzu %3,%2(%0)"
9641 [(set_attr "type" "load")
9642 (set_attr "update" "yes")
9643 (set_attr "indexed" "yes,no")])
9645 (define_insn "*movhi_update3"
9646 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9647 (sign_extend:SI
9648 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9649 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9650 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9651 (plus:SI (match_dup 1) (match_dup 2)))]
9652 "TARGET_UPDATE && rs6000_gen_cell_microcode
9653 && (!avoiding_indexed_address_p (SImode)
9654 || !gpc_reg_operand (operands[2], SImode))"
9655 "@
9656 lhaux %3,%0,%2
9657 lhau %3,%2(%0)"
9658 [(set_attr "type" "load")
9659 (set_attr "sign_extend" "yes")
9660 (set_attr "update" "yes")
9661 (set_attr "indexed" "yes,no")])
9663 (define_insn "*movhi_update4"
9664 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9665 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9666 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9667 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9668 (plus:SI (match_dup 1) (match_dup 2)))]
9669 "TARGET_UPDATE
9670 && (!avoiding_indexed_address_p (SImode)
9671 || !gpc_reg_operand (operands[2], SImode))"
9672 "@
9673 sthux %3,%0,%2
9674 sthu %3,%2(%0)"
9675 [(set_attr "type" "store")
9676 (set_attr "update" "yes")
9677 (set_attr "indexed" "yes,no")])
9679 (define_insn "*movqi_update1"
9680 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9681 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9682 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9683 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9684 (plus:SI (match_dup 1) (match_dup 2)))]
9685 "TARGET_UPDATE
9686 && (!avoiding_indexed_address_p (SImode)
9687 || !gpc_reg_operand (operands[2], SImode))"
9688 "@
9689 lbzux %3,%0,%2
9690 lbzu %3,%2(%0)"
9691 [(set_attr "type" "load")
9692 (set_attr "update" "yes")
9693 (set_attr "indexed" "yes,no")])
9695 (define_insn "*movqi_update2"
9696 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9697 (zero_extend:SI
9698 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9699 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9700 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9701 (plus:SI (match_dup 1) (match_dup 2)))]
9702 "TARGET_UPDATE
9703 && (!avoiding_indexed_address_p (SImode)
9704 || !gpc_reg_operand (operands[2], SImode))"
9705 "@
9706 lbzux %3,%0,%2
9707 lbzu %3,%2(%0)"
9708 [(set_attr "type" "load")
9709 (set_attr "update" "yes")
9710 (set_attr "indexed" "yes,no")])
9712 (define_insn "*movqi_update3"
9713 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9714 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9715 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9716 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9717 (plus:SI (match_dup 1) (match_dup 2)))]
9718 "TARGET_UPDATE
9719 && (!avoiding_indexed_address_p (SImode)
9720 || !gpc_reg_operand (operands[2], SImode))"
9721 "@
9722 stbux %3,%0,%2
9723 stbu %3,%2(%0)"
9724 [(set_attr "type" "store")
9725 (set_attr "update" "yes")
9726 (set_attr "indexed" "yes,no")])
9728 (define_insn "*movsf_update1"
9729 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9730 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9731 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9732 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9733 (plus:SI (match_dup 1) (match_dup 2)))]
9734 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9735 && (!avoiding_indexed_address_p (SImode)
9736 || !gpc_reg_operand (operands[2], SImode))"
9737 "@
9738 lfsux %3,%0,%2
9739 lfsu %3,%2(%0)"
9740 [(set_attr "type" "fpload")
9741 (set_attr "update" "yes")
9742 (set_attr "indexed" "yes,no")])
9744 (define_insn "*movsf_update2"
9745 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9746 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9747 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9748 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9749 (plus:SI (match_dup 1) (match_dup 2)))]
9750 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9751 && (!avoiding_indexed_address_p (SImode)
9752 || !gpc_reg_operand (operands[2], SImode))"
9753 "@
9754 stfsux %3,%0,%2
9755 stfsu %3,%2(%0)"
9756 [(set_attr "type" "fpstore")
9757 (set_attr "update" "yes")
9758 (set_attr "indexed" "yes,no")])
9760 (define_insn "*movsf_update3"
9761 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9762 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9763 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9764 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9765 (plus:SI (match_dup 1) (match_dup 2)))]
9766 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9767 && (!avoiding_indexed_address_p (SImode)
9768 || !gpc_reg_operand (operands[2], SImode))"
9769 "@
9770 lwzux %3,%0,%2
9771 lwzu %3,%2(%0)"
9772 [(set_attr "type" "load")
9773 (set_attr "update" "yes")
9774 (set_attr "indexed" "yes,no")])
9776 (define_insn "*movsf_update4"
9777 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9778 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9779 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9780 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9781 (plus:SI (match_dup 1) (match_dup 2)))]
9782 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9783 && (!avoiding_indexed_address_p (SImode)
9784 || !gpc_reg_operand (operands[2], SImode))"
9785 "@
9786 stwux %3,%0,%2
9787 stwu %3,%2(%0)"
9788 [(set_attr "type" "store")
9789 (set_attr "update" "yes")
9790 (set_attr "indexed" "yes,no")])
9792 (define_insn "*movdf_update1"
9793 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9794 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9795 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9796 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9797 (plus:SI (match_dup 1) (match_dup 2)))]
9798 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9799 && (!avoiding_indexed_address_p (SImode)
9800 || !gpc_reg_operand (operands[2], SImode))"
9801 "@
9802 lfdux %3,%0,%2
9803 lfdu %3,%2(%0)"
9804 [(set_attr "type" "fpload")
9805 (set_attr "update" "yes")
9806 (set_attr "indexed" "yes,no")])
9808 (define_insn "*movdf_update2"
9809 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9810 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9811 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9812 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9813 (plus:SI (match_dup 1) (match_dup 2)))]
9814 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9815 && (!avoiding_indexed_address_p (SImode)
9816 || !gpc_reg_operand (operands[2], SImode))"
9817 "@
9818 stfdux %3,%0,%2
9819 stfdu %3,%2(%0)"
9820 [(set_attr "type" "fpstore")
9821 (set_attr "update" "yes")
9822 (set_attr "indexed" "yes,no")])
9825 ;; After inserting conditional returns we can sometimes have
9826 ;; unnecessary register moves. Unfortunately we cannot have a
9827 ;; modeless peephole here, because some single SImode sets have early
9828 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9829 ;; sequences, using get_attr_length here will smash the operands
9830 ;; array. Neither is there an early_cobbler_p predicate.
9831 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9832 ;; Also this optimization interferes with scalars going into
9833 ;; altivec registers (the code does reloading through the FPRs).
9834 (define_peephole2
9835 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9836 (match_operand:DF 1 "any_operand" ""))
9837 (set (match_operand:DF 2 "gpc_reg_operand" "")
9838 (match_dup 0))]
9839 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9840 && !TARGET_UPPER_REGS_DF
9841 && peep2_reg_dead_p (2, operands[0])"
9842 [(set (match_dup 2) (match_dup 1))])
9844 (define_peephole2
9845 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9846 (match_operand:SF 1 "any_operand" ""))
9847 (set (match_operand:SF 2 "gpc_reg_operand" "")
9848 (match_dup 0))]
9849 "!TARGET_UPPER_REGS_SF
9850 && peep2_reg_dead_p (2, operands[0])"
9851 [(set (match_dup 2) (match_dup 1))])
9853 \f
9854 ;; TLS support.
9856 ;; Mode attributes for different ABIs.
9857 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9858 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9859 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9860 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9862 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9863 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9864 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9865 (match_operand 4 "" "g")))
9866 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9867 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9868 UNSPEC_TLSGD)
9869 (clobber (reg:SI LR_REGNO))]
9870 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9871 {
9872 if (TARGET_CMODEL != CMODEL_SMALL)
9873 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9874 "bl %z3\;nop";
9875 else
9876 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9877 }
9878 "&& TARGET_TLS_MARKERS"
9879 [(set (match_dup 0)
9880 (unspec:TLSmode [(match_dup 1)
9881 (match_dup 2)]
9882 UNSPEC_TLSGD))
9883 (parallel [(set (match_dup 0)
9884 (call (mem:TLSmode (match_dup 3))
9885 (match_dup 4)))
9886 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9887 (clobber (reg:SI LR_REGNO))])]
9888 ""
9889 [(set_attr "type" "two")
9890 (set (attr "length")
9891 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9892 (const_int 16)
9893 (const_int 12)))])
9895 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9896 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9897 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9898 (match_operand 4 "" "g")))
9899 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9900 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9901 UNSPEC_TLSGD)
9902 (clobber (reg:SI LR_REGNO))]
9903 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9904 {
9905 if (flag_pic)
9906 {
9907 if (TARGET_SECURE_PLT && flag_pic == 2)
9908 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9909 else
9910 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9911 }
9912 else
9913 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9914 }
9915 "&& TARGET_TLS_MARKERS"
9916 [(set (match_dup 0)
9917 (unspec:TLSmode [(match_dup 1)
9918 (match_dup 2)]
9919 UNSPEC_TLSGD))
9920 (parallel [(set (match_dup 0)
9921 (call (mem:TLSmode (match_dup 3))
9922 (match_dup 4)))
9923 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9924 (clobber (reg:SI LR_REGNO))])]
9925 ""
9926 [(set_attr "type" "two")
9927 (set_attr "length" "8")])
9929 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9930 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9931 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9932 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9933 UNSPEC_TLSGD))]
9934 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9935 "addi %0,%1,%2@got@tlsgd"
9936 "&& TARGET_CMODEL != CMODEL_SMALL"
9937 [(set (match_dup 3)
9938 (high:TLSmode
9939 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9940 (set (match_dup 0)
9941 (lo_sum:TLSmode (match_dup 3)
9942 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
9943 "
9944 {
9945 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9946 }"
9947 [(set (attr "length")
9948 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9949 (const_int 8)
9950 (const_int 4)))])
9952 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9953 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9954 (high:TLSmode
9955 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9956 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9957 UNSPEC_TLSGD)))]
9958 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9959 "addis %0,%1,%2@got@tlsgd@ha"
9960 [(set_attr "length" "4")])
9962 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9963 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9964 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9965 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
9966 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9967 UNSPEC_TLSGD)))]
9968 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9969 "addi %0,%1,%2@got@tlsgd@l"
9970 [(set_attr "length" "4")])
9972 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9973 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9974 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9975 (match_operand 2 "" "g")))
9976 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9977 UNSPEC_TLSGD)
9978 (clobber (reg:SI LR_REGNO))]
9979 "HAVE_AS_TLS && TARGET_TLS_MARKERS
9980 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9981 "bl %z1(%3@tlsgd)\;nop"
9982 [(set_attr "type" "branch")
9983 (set_attr "length" "8")])
9985 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9986 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9987 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9988 (match_operand 2 "" "g")))
9989 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9990 UNSPEC_TLSGD)
9991 (clobber (reg:SI LR_REGNO))]
9992 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9993 {
9994 if (flag_pic)
9995 {
9996 if (TARGET_SECURE_PLT && flag_pic == 2)
9997 return "bl %z1+32768(%3@tlsgd)@plt";
9998 return "bl %z1(%3@tlsgd)@plt";
9999 }
10000 return "bl %z1(%3@tlsgd)";
10001 }
10002 [(set_attr "type" "branch")
10003 (set_attr "length" "4")])
10005 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10006 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10007 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10008 (match_operand 3 "" "g")))
10009 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10010 UNSPEC_TLSLD)
10011 (clobber (reg:SI LR_REGNO))]
10012 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10013 {
10014 if (TARGET_CMODEL != CMODEL_SMALL)
10015 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
10016 "bl %z2\;nop";
10017 else
10018 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
10019 }
10020 "&& TARGET_TLS_MARKERS"
10021 [(set (match_dup 0)
10022 (unspec:TLSmode [(match_dup 1)]
10023 UNSPEC_TLSLD))
10024 (parallel [(set (match_dup 0)
10025 (call (mem:TLSmode (match_dup 2))
10026 (match_dup 3)))
10027 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10028 (clobber (reg:SI LR_REGNO))])]
10029 ""
10030 [(set_attr "type" "two")
10031 (set (attr "length")
10032 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10033 (const_int 16)
10034 (const_int 12)))])
10036 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10037 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10038 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10039 (match_operand 3 "" "g")))
10040 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10041 UNSPEC_TLSLD)
10042 (clobber (reg:SI LR_REGNO))]
10043 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10044 {
10045 if (flag_pic)
10046 {
10047 if (TARGET_SECURE_PLT && flag_pic == 2)
10048 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10049 else
10050 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10051 }
10052 else
10053 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10054 }
10055 "&& TARGET_TLS_MARKERS"
10056 [(set (match_dup 0)
10057 (unspec:TLSmode [(match_dup 1)]
10058 UNSPEC_TLSLD))
10059 (parallel [(set (match_dup 0)
10060 (call (mem:TLSmode (match_dup 2))
10061 (match_dup 3)))
10062 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10063 (clobber (reg:SI LR_REGNO))])]
10064 ""
10065 [(set_attr "length" "8")])
10067 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10068 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10069 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10070 UNSPEC_TLSLD))]
10071 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10072 "addi %0,%1,%&@got@tlsld"
10073 "&& TARGET_CMODEL != CMODEL_SMALL"
10074 [(set (match_dup 2)
10075 (high:TLSmode
10076 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10077 (set (match_dup 0)
10078 (lo_sum:TLSmode (match_dup 2)
10079 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
10080 "
10081 {
10082 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10083 }"
10084 [(set (attr "length")
10085 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10086 (const_int 8)
10087 (const_int 4)))])
10089 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10090 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10091 (high:TLSmode
10092 (unspec:TLSmode [(const_int 0)
10093 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10094 UNSPEC_TLSLD)))]
10095 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10096 "addis %0,%1,%&@got@tlsld@ha"
10097 [(set_attr "length" "4")])
10099 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10100 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10101 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10102 (unspec:TLSmode [(const_int 0)
10103 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
10104 UNSPEC_TLSLD)))]
10105 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10106 "addi %0,%1,%&@got@tlsld@l"
10107 [(set_attr "length" "4")])
10109 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10110 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10111 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10112 (match_operand 2 "" "g")))
10113 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10114 (clobber (reg:SI LR_REGNO))]
10115 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10116 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10117 "bl %z1(%&@tlsld)\;nop"
10118 [(set_attr "type" "branch")
10119 (set_attr "length" "8")])
10121 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10122 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10123 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10124 (match_operand 2 "" "g")))
10125 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10126 (clobber (reg:SI LR_REGNO))]
10127 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10128 {
10129 if (flag_pic)
10130 {
10131 if (TARGET_SECURE_PLT && flag_pic == 2)
10132 return "bl %z1+32768(%&@tlsld)@plt";
10133 return "bl %z1(%&@tlsld)@plt";
10134 }
10135 return "bl %z1(%&@tlsld)";
10136 }
10137 [(set_attr "type" "branch")
10138 (set_attr "length" "4")])
10140 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10141 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10142 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10143 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10144 UNSPEC_TLSDTPREL))]
10145 "HAVE_AS_TLS"
10146 "addi %0,%1,%2@dtprel")
10148 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10149 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10150 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10151 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10152 UNSPEC_TLSDTPRELHA))]
10153 "HAVE_AS_TLS"
10154 "addis %0,%1,%2@dtprel@ha")
10156 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10157 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10158 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10159 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10160 UNSPEC_TLSDTPRELLO))]
10161 "HAVE_AS_TLS"
10162 "addi %0,%1,%2@dtprel@l")
10164 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10165 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10166 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10167 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10168 UNSPEC_TLSGOTDTPREL))]
10169 "HAVE_AS_TLS"
10170 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10171 "&& TARGET_CMODEL != CMODEL_SMALL"
10172 [(set (match_dup 3)
10173 (high:TLSmode
10174 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10175 (set (match_dup 0)
10176 (lo_sum:TLSmode (match_dup 3)
10177 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10178 "
10179 {
10180 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10181 }"
10182 [(set (attr "length")
10183 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10184 (const_int 8)
10185 (const_int 4)))])
10187 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10188 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10189 (high:TLSmode
10190 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10191 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10192 UNSPEC_TLSGOTDTPREL)))]
10193 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10194 "addis %0,%1,%2@got@dtprel@ha"
10195 [(set_attr "length" "4")])
10197 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10198 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10199 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10200 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10201 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10202 UNSPEC_TLSGOTDTPREL)))]
10203 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10204 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10205 [(set_attr "length" "4")])
10207 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10208 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10209 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10210 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10211 UNSPEC_TLSTPREL))]
10212 "HAVE_AS_TLS"
10213 "addi %0,%1,%2@tprel")
10215 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10216 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10217 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10218 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10219 UNSPEC_TLSTPRELHA))]
10220 "HAVE_AS_TLS"
10221 "addis %0,%1,%2@tprel@ha")
10223 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10224 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10225 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10226 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10227 UNSPEC_TLSTPRELLO))]
10228 "HAVE_AS_TLS"
10229 "addi %0,%1,%2@tprel@l")
10231 ;; "b" output constraint here and on tls_tls input to support linker tls
10232 ;; optimization. The linker may edit the instructions emitted by a
10233 ;; tls_got_tprel/tls_tls pair to addis,addi.
10234 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10235 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10236 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10237 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10238 UNSPEC_TLSGOTTPREL))]
10239 "HAVE_AS_TLS"
10240 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10241 "&& TARGET_CMODEL != CMODEL_SMALL"
10242 [(set (match_dup 3)
10243 (high:TLSmode
10244 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10245 (set (match_dup 0)
10246 (lo_sum:TLSmode (match_dup 3)
10247 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10248 "
10249 {
10250 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10251 }"
10252 [(set (attr "length")
10253 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10254 (const_int 8)
10255 (const_int 4)))])
10257 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10258 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10259 (high:TLSmode
10260 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10261 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10262 UNSPEC_TLSGOTTPREL)))]
10263 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10264 "addis %0,%1,%2@got@tprel@ha"
10265 [(set_attr "length" "4")])
10267 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10268 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10269 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10270 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10271 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10272 UNSPEC_TLSGOTTPREL)))]
10273 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10274 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
10275 [(set_attr "length" "4")])
10277 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10278 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10279 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10280 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10281 UNSPEC_TLSTLS))]
10282 "TARGET_ELF && HAVE_AS_TLS"
10283 "add %0,%1,%2@tls")
10285 (define_expand "tls_get_tpointer"
10286 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10287 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
10288 "TARGET_XCOFF && HAVE_AS_TLS"
10289 "
10290 {
10291 emit_insn (gen_tls_get_tpointer_internal ());
10292 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
10293 DONE;
10294 }")
10296 (define_insn "tls_get_tpointer_internal"
10297 [(set (reg:SI 3)
10298 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
10299 (clobber (reg:SI LR_REGNO))]
10300 "TARGET_XCOFF && HAVE_AS_TLS"
10301 "bla __get_tpointer")
10303 (define_expand "tls_get_addr<mode>"
10304 [(set (match_operand:P 0 "gpc_reg_operand" "")
10305 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
10306 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
10307 "TARGET_XCOFF && HAVE_AS_TLS"
10308 "
10309 {
10310 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
10311 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
10312 emit_insn (gen_tls_get_addr_internal<mode> ());
10313 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
10314 DONE;
10315 }")
10317 (define_insn "tls_get_addr_internal<mode>"
10318 [(set (reg:P 3)
10319 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
10320 (clobber (reg:P 0))
10321 (clobber (reg:P 4))
10322 (clobber (reg:P 5))
10323 (clobber (reg:P 11))
10324 (clobber (reg:CC CR0_REGNO))
10325 (clobber (reg:P LR_REGNO))]
10326 "TARGET_XCOFF && HAVE_AS_TLS"
10327 "bla __tls_get_addr")
10328 \f
10329 ;; Next come insns related to the calling sequence.
10330 ;;
10331 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10332 ;; We move the back-chain and decrement the stack pointer.
10334 (define_expand "allocate_stack"
10335 [(set (match_operand 0 "gpc_reg_operand" "")
10336 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10337 (set (reg 1)
10338 (minus (reg 1) (match_dup 1)))]
10339 ""
10340 "
10341 { rtx chain = gen_reg_rtx (Pmode);
10342 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10343 rtx neg_op0;
10344 rtx insn, par, set, mem;
10346 emit_move_insn (chain, stack_bot);
10348 /* Check stack bounds if necessary. */
10349 if (crtl->limit_stack)
10350 {
10351 rtx available;
10352 available = expand_binop (Pmode, sub_optab,
10353 stack_pointer_rtx, stack_limit_rtx,
10354 NULL_RTX, 1, OPTAB_WIDEN);
10355 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10356 }
10358 if (GET_CODE (operands[1]) != CONST_INT
10359 || INTVAL (operands[1]) < -32767
10360 || INTVAL (operands[1]) > 32768)
10361 {
10362 neg_op0 = gen_reg_rtx (Pmode);
10363 if (TARGET_32BIT)
10364 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10365 else
10366 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10367 }
10368 else
10369 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10371 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10372 : gen_movdi_di_update_stack))
10373 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10374 chain));
10375 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10376 it now and set the alias set/attributes. The above gen_*_update
10377 calls will generate a PARALLEL with the MEM set being the first
10378 operation. */
10379 par = PATTERN (insn);
10380 gcc_assert (GET_CODE (par) == PARALLEL);
10381 set = XVECEXP (par, 0, 0);
10382 gcc_assert (GET_CODE (set) == SET);
10383 mem = SET_DEST (set);
10384 gcc_assert (MEM_P (mem));
10385 MEM_NOTRAP_P (mem) = 1;
10386 set_mem_alias_set (mem, get_frame_alias_set ());
10388 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10389 DONE;
10390 }")
10392 ;; These patterns say how to save and restore the stack pointer. We need not
10393 ;; save the stack pointer at function level since we are careful to
10394 ;; preserve the backchain. At block level, we have to restore the backchain
10395 ;; when we restore the stack pointer.
10396 ;;
10397 ;; For nonlocal gotos, we must save both the stack pointer and its
10398 ;; backchain and restore both. Note that in the nonlocal case, the
10399 ;; save area is a memory location.
10401 (define_expand "save_stack_function"
10402 [(match_operand 0 "any_operand" "")
10403 (match_operand 1 "any_operand" "")]
10404 ""
10405 "DONE;")
10407 (define_expand "restore_stack_function"
10408 [(match_operand 0 "any_operand" "")
10409 (match_operand 1 "any_operand" "")]
10410 ""
10411 "DONE;")
10413 ;; Adjust stack pointer (op0) to a new value (op1).
10414 ;; First copy old stack backchain to new location, and ensure that the
10415 ;; scheduler won't reorder the sp assignment before the backchain write.
10416 (define_expand "restore_stack_block"
10417 [(set (match_dup 2) (match_dup 3))
10418 (set (match_dup 4) (match_dup 2))
10419 (match_dup 5)
10420 (set (match_operand 0 "register_operand" "")
10421 (match_operand 1 "register_operand" ""))]
10422 ""
10423 "
10424 {
10425 rtvec p;
10427 operands[1] = force_reg (Pmode, operands[1]);
10428 operands[2] = gen_reg_rtx (Pmode);
10429 operands[3] = gen_frame_mem (Pmode, operands[0]);
10430 operands[4] = gen_frame_mem (Pmode, operands[1]);
10431 p = rtvec_alloc (1);
10432 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10433 gen_frame_mem (BLKmode, operands[0]),
10434 const0_rtx);
10435 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10436 }")
10438 (define_expand "save_stack_nonlocal"
10439 [(set (match_dup 3) (match_dup 4))
10440 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10441 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10442 ""
10443 "
10444 {
10445 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10447 /* Copy the backchain to the first word, sp to the second. */
10448 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10449 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10450 operands[3] = gen_reg_rtx (Pmode);
10451 operands[4] = gen_frame_mem (Pmode, operands[1]);
10452 }")
10454 (define_expand "restore_stack_nonlocal"
10455 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10456 (set (match_dup 3) (match_dup 4))
10457 (set (match_dup 5) (match_dup 2))
10458 (match_dup 6)
10459 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10460 ""
10461 "
10462 {
10463 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10464 rtvec p;
10466 /* Restore the backchain from the first word, sp from the second. */
10467 operands[2] = gen_reg_rtx (Pmode);
10468 operands[3] = gen_reg_rtx (Pmode);
10469 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10470 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10471 operands[5] = gen_frame_mem (Pmode, operands[3]);
10472 p = rtvec_alloc (1);
10473 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10474 gen_frame_mem (BLKmode, operands[0]),
10475 const0_rtx);
10476 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10477 }")
10478 \f
10479 ;; TOC register handling.
10481 ;; Code to initialize the TOC register...
10483 (define_insn "load_toc_aix_si"
10484 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10485 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10486 (use (reg:SI 2))])]
10487 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
10488 "*
10489 {
10490 char buf[30];
10491 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10492 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10493 operands[2] = gen_rtx_REG (Pmode, 2);
10494 return \"lwz %0,%1(%2)\";
10495 }"
10496 [(set_attr "type" "load")
10497 (set_attr "update" "no")
10498 (set_attr "indexed" "no")])
10500 (define_insn "load_toc_aix_di"
10501 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10502 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10503 (use (reg:DI 2))])]
10504 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
10505 "*
10506 {
10507 char buf[30];
10508 #ifdef TARGET_RELOCATABLE
10509 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10510 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10511 #else
10512 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10513 #endif
10514 if (TARGET_ELF)
10515 strcat (buf, \"@toc\");
10516 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10517 operands[2] = gen_rtx_REG (Pmode, 2);
10518 return \"ld %0,%1(%2)\";
10519 }"
10520 [(set_attr "type" "load")
10521 (set_attr "update" "no")
10522 (set_attr "indexed" "no")])
10524 (define_insn "load_toc_v4_pic_si"
10525 [(set (reg:SI LR_REGNO)
10526 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10527 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10528 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10529 [(set_attr "type" "branch")
10530 (set_attr "length" "4")])
10532 (define_expand "load_toc_v4_PIC_1"
10533 [(parallel [(set (reg:SI LR_REGNO)
10534 (match_operand:SI 0 "immediate_operand" "s"))
10535 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10536 "TARGET_ELF && DEFAULT_ABI == ABI_V4
10537 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10538 "")
10540 (define_insn "load_toc_v4_PIC_1_normal"
10541 [(set (reg:SI LR_REGNO)
10542 (match_operand:SI 0 "immediate_operand" "s"))
10543 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10544 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10545 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10546 "bcl 20,31,%0\\n%0:"
10547 [(set_attr "type" "branch")
10548 (set_attr "length" "4")])
10550 (define_insn "load_toc_v4_PIC_1_476"
10551 [(set (reg:SI LR_REGNO)
10552 (match_operand:SI 0 "immediate_operand" "s"))
10553 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10554 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10555 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10556 "*
10557 {
10558 char name[32];
10559 static char templ[32];
10561 get_ppc476_thunk_name (name);
10562 sprintf (templ, \"bl %s\\n%%0:\", name);
10563 return templ;
10564 }"
10565 [(set_attr "type" "branch")
10566 (set_attr "length" "4")])
10568 (define_expand "load_toc_v4_PIC_1b"
10569 [(parallel [(set (reg:SI LR_REGNO)
10570 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10571 (label_ref (match_operand 1 "" ""))]
10572 UNSPEC_TOCPTR))
10573 (match_dup 1)])]
10574 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10575 "")
10577 (define_insn "load_toc_v4_PIC_1b_normal"
10578 [(set (reg:SI LR_REGNO)
10579 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10580 (label_ref (match_operand 1 "" ""))]
10581 UNSPEC_TOCPTR))
10582 (match_dup 1)]
10583 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10584 "bcl 20,31,$+8\;.long %0-$"
10585 [(set_attr "type" "branch")
10586 (set_attr "length" "8")])
10588 (define_insn "load_toc_v4_PIC_1b_476"
10589 [(set (reg:SI LR_REGNO)
10590 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10591 (label_ref (match_operand 1 "" ""))]
10592 UNSPEC_TOCPTR))
10593 (match_dup 1)]
10594 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10595 "*
10596 {
10597 char name[32];
10598 static char templ[32];
10600 get_ppc476_thunk_name (name);
10601 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10602 return templ;
10603 }"
10604 [(set_attr "type" "branch")
10605 (set_attr "length" "16")])
10607 (define_insn "load_toc_v4_PIC_2"
10608 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10609 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10610 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10611 (match_operand:SI 3 "immediate_operand" "s")))))]
10612 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10613 "lwz %0,%2-%3(%1)"
10614 [(set_attr "type" "load")])
10616 (define_insn "load_toc_v4_PIC_3b"
10617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10618 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10619 (high:SI
10620 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10621 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10622 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10623 "addis %0,%1,%2-%3@ha")
10625 (define_insn "load_toc_v4_PIC_3c"
10626 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10627 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10628 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10629 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10630 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10631 "addi %0,%1,%2-%3@l")
10633 ;; If the TOC is shared over a translation unit, as happens with all
10634 ;; the kinds of PIC that we support, we need to restore the TOC
10635 ;; pointer only when jumping over units of translation.
10636 ;; On Darwin, we need to reload the picbase.
10638 (define_expand "builtin_setjmp_receiver"
10639 [(use (label_ref (match_operand 0 "" "")))]
10640 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10641 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10642 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10643 "
10644 {
10645 #if TARGET_MACHO
10646 if (DEFAULT_ABI == ABI_DARWIN)
10647 {
10648 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10649 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10650 rtx tmplabrtx;
10651 char tmplab[20];
10653 crtl->uses_pic_offset_table = 1;
10654 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10655 CODE_LABEL_NUMBER (operands[0]));
10656 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10658 emit_insn (gen_load_macho_picbase (tmplabrtx));
10659 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10660 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10661 }
10662 else
10663 #endif
10664 rs6000_emit_load_toc_table (FALSE);
10665 DONE;
10666 }")
10668 ;; Largetoc support
10669 (define_insn "*largetoc_high"
10670 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10671 (high:DI
10672 (unspec [(match_operand:DI 1 "" "")
10673 (match_operand:DI 2 "gpc_reg_operand" "b")]
10674 UNSPEC_TOCREL)))]
10675 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10676 "addis %0,%2,%1@toc@ha")
10678 (define_insn "*largetoc_high_aix<mode>"
10679 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10680 (high:P
10681 (unspec [(match_operand:P 1 "" "")
10682 (match_operand:P 2 "gpc_reg_operand" "b")]
10683 UNSPEC_TOCREL)))]
10684 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10685 "addis %0,%1@u(%2)")
10687 (define_insn "*largetoc_high_plus"
10688 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10689 (high:DI
10690 (plus:DI
10691 (unspec [(match_operand:DI 1 "" "")
10692 (match_operand:DI 2 "gpc_reg_operand" "b")]
10693 UNSPEC_TOCREL)
10694 (match_operand:DI 3 "add_cint_operand" "n"))))]
10695 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10696 "addis %0,%2,%1+%3@toc@ha")
10698 (define_insn "*largetoc_high_plus_aix<mode>"
10699 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10700 (high:P
10701 (plus:P
10702 (unspec [(match_operand:P 1 "" "")
10703 (match_operand:P 2 "gpc_reg_operand" "b")]
10704 UNSPEC_TOCREL)
10705 (match_operand:P 3 "add_cint_operand" "n"))))]
10706 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10707 "addis %0,%1+%3@u(%2)")
10709 (define_insn "*largetoc_low"
10710 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10711 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
10712 (match_operand:DI 2 "" "")))]
10713 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10714 "@
10715 addi %0,%1,%2@l
10716 addic %0,%1,%2@l")
10718 (define_insn "*largetoc_low_aix<mode>"
10719 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
10720 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
10721 (match_operand:P 2 "" "")))]
10722 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10723 "la %0,%2@l(%1)")
10725 (define_insn_and_split "*tocref<mode>"
10726 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10727 (match_operand:P 1 "small_toc_ref" "R"))]
10728 "TARGET_TOC"
10729 "la %0,%a1"
10730 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10731 [(set (match_dup 0) (high:P (match_dup 1)))
10732 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10734 ;; Elf specific ways of loading addresses for non-PIC code.
10735 ;; The output of this could be r0, but we make a very strong
10736 ;; preference for a base register because it will usually
10737 ;; be needed there.
10738 (define_insn "elf_high"
10739 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10740 (high:SI (match_operand 1 "" "")))]
10741 "TARGET_ELF && ! TARGET_64BIT"
10742 "lis %0,%1@ha")
10744 (define_insn "elf_low"
10745 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10746 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10747 (match_operand 2 "" "")))]
10748 "TARGET_ELF && ! TARGET_64BIT"
10749 "@
10750 la %0,%2@l(%1)
10751 addic %0,%1,%K2")
10752 \f
10753 ;; Call and call_value insns
10754 (define_expand "call"
10755 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10756 (match_operand 1 "" ""))
10757 (use (match_operand 2 "" ""))
10758 (clobber (reg:SI LR_REGNO))])]
10759 ""
10760 "
10761 {
10762 #if TARGET_MACHO
10763 if (MACHOPIC_INDIRECT)
10764 operands[0] = machopic_indirect_call_target (operands[0]);
10765 #endif
10767 gcc_assert (GET_CODE (operands[0]) == MEM);
10768 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10770 operands[0] = XEXP (operands[0], 0);
10772 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10773 {
10774 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
10775 DONE;
10776 }
10778 if (GET_CODE (operands[0]) != SYMBOL_REF
10779 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10780 {
10781 if (INTVAL (operands[2]) & CALL_LONG)
10782 operands[0] = rs6000_longcall_ref (operands[0]);
10784 switch (DEFAULT_ABI)
10785 {
10786 case ABI_V4:
10787 case ABI_DARWIN:
10788 operands[0] = force_reg (Pmode, operands[0]);
10789 break;
10791 default:
10792 gcc_unreachable ();
10793 }
10794 }
10795 }")
10797 (define_expand "call_value"
10798 [(parallel [(set (match_operand 0 "" "")
10799 (call (mem:SI (match_operand 1 "address_operand" ""))
10800 (match_operand 2 "" "")))
10801 (use (match_operand 3 "" ""))
10802 (clobber (reg:SI LR_REGNO))])]
10803 ""
10804 "
10805 {
10806 #if TARGET_MACHO
10807 if (MACHOPIC_INDIRECT)
10808 operands[1] = machopic_indirect_call_target (operands[1]);
10809 #endif
10811 gcc_assert (GET_CODE (operands[1]) == MEM);
10812 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10814 operands[1] = XEXP (operands[1], 0);
10816 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10817 {
10818 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
10819 DONE;
10820 }
10822 if (GET_CODE (operands[1]) != SYMBOL_REF
10823 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10824 {
10825 if (INTVAL (operands[3]) & CALL_LONG)
10826 operands[1] = rs6000_longcall_ref (operands[1]);
10828 switch (DEFAULT_ABI)
10829 {
10830 case ABI_V4:
10831 case ABI_DARWIN:
10832 operands[1] = force_reg (Pmode, operands[1]);
10833 break;
10835 default:
10836 gcc_unreachable ();
10837 }
10838 }
10839 }")
10841 ;; Call to function in current module. No TOC pointer reload needed.
10842 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10843 ;; either the function was not prototyped, or it was prototyped as a
10844 ;; variable argument function. It is > 0 if FP registers were passed
10845 ;; and < 0 if they were not.
10847 (define_insn "*call_local32"
10848 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10849 (match_operand 1 "" "g,g"))
10850 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10851 (clobber (reg:SI LR_REGNO))]
10852 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10853 "*
10854 {
10855 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10856 output_asm_insn (\"crxor 6,6,6\", operands);
10858 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10859 output_asm_insn (\"creqv 6,6,6\", operands);
10861 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10862 }"
10863 [(set_attr "type" "branch")
10864 (set_attr "length" "4,8")])
10866 (define_insn "*call_local64"
10867 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10868 (match_operand 1 "" "g,g"))
10869 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10870 (clobber (reg:SI LR_REGNO))]
10871 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10872 "*
10873 {
10874 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10875 output_asm_insn (\"crxor 6,6,6\", operands);
10877 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10878 output_asm_insn (\"creqv 6,6,6\", operands);
10880 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10881 }"
10882 [(set_attr "type" "branch")
10883 (set_attr "length" "4,8")])
10885 (define_insn "*call_value_local32"
10886 [(set (match_operand 0 "" "")
10887 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10888 (match_operand 2 "" "g,g")))
10889 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10890 (clobber (reg:SI LR_REGNO))]
10891 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10892 "*
10893 {
10894 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10895 output_asm_insn (\"crxor 6,6,6\", operands);
10897 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10898 output_asm_insn (\"creqv 6,6,6\", operands);
10900 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10901 }"
10902 [(set_attr "type" "branch")
10903 (set_attr "length" "4,8")])
10906 (define_insn "*call_value_local64"
10907 [(set (match_operand 0 "" "")
10908 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10909 (match_operand 2 "" "g,g")))
10910 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10911 (clobber (reg:SI LR_REGNO))]
10912 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10913 "*
10914 {
10915 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10916 output_asm_insn (\"crxor 6,6,6\", operands);
10918 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10919 output_asm_insn (\"creqv 6,6,6\", operands);
10921 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10922 }"
10923 [(set_attr "type" "branch")
10924 (set_attr "length" "4,8")])
10927 ;; A function pointer under System V is just a normal pointer
10928 ;; operands[0] is the function pointer
10929 ;; operands[1] is the stack size to clean up
10930 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10931 ;; which indicates how to set cr1
10933 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10934 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10935 (match_operand 1 "" "g,g,g,g"))
10936 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10937 (clobber (reg:SI LR_REGNO))]
10938 "DEFAULT_ABI == ABI_V4
10939 || DEFAULT_ABI == ABI_DARWIN"
10940 {
10941 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10942 output_asm_insn ("crxor 6,6,6", operands);
10944 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10945 output_asm_insn ("creqv 6,6,6", operands);
10947 return "b%T0l";
10948 }
10949 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10950 (set_attr "length" "4,4,8,8")])
10952 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10953 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10954 (match_operand 1 "" "g,g"))
10955 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10956 (clobber (reg:SI LR_REGNO))]
10957 "(DEFAULT_ABI == ABI_DARWIN
10958 || (DEFAULT_ABI == ABI_V4
10959 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10960 {
10961 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10962 output_asm_insn ("crxor 6,6,6", operands);
10964 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10965 output_asm_insn ("creqv 6,6,6", operands);
10967 #if TARGET_MACHO
10968 return output_call(insn, operands, 0, 2);
10969 #else
10970 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10971 {
10972 gcc_assert (!TARGET_SECURE_PLT);
10973 return "bl %z0@plt";
10974 }
10975 else
10976 return "bl %z0";
10977 #endif
10978 }
10979 "DEFAULT_ABI == ABI_V4
10980 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10981 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10982 [(parallel [(call (mem:SI (match_dup 0))
10983 (match_dup 1))
10984 (use (match_dup 2))
10985 (use (match_dup 3))
10986 (clobber (reg:SI LR_REGNO))])]
10987 {
10988 operands[3] = pic_offset_table_rtx;
10989 }
10990 [(set_attr "type" "branch,branch")
10991 (set_attr "length" "4,8")])
10993 (define_insn "*call_nonlocal_sysv_secure<mode>"
10994 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10995 (match_operand 1 "" "g,g"))
10996 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10997 (use (match_operand:SI 3 "register_operand" "r,r"))
10998 (clobber (reg:SI LR_REGNO))]
10999 "(DEFAULT_ABI == ABI_V4
11000 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11001 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11002 {
11003 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11004 output_asm_insn ("crxor 6,6,6", operands);
11006 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11007 output_asm_insn ("creqv 6,6,6", operands);
11009 if (flag_pic == 2)
11010 /* The magic 32768 offset here and in the other sysv call insns
11011 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11012 See sysv4.h:toc_section. */
11013 return "bl %z0+32768@plt";
11014 else
11015 return "bl %z0@plt";
11016 }
11017 [(set_attr "type" "branch,branch")
11018 (set_attr "length" "4,8")])
11020 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11021 [(set (match_operand 0 "" "")
11022 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11023 (match_operand 2 "" "g,g,g,g")))
11024 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11025 (clobber (reg:SI LR_REGNO))]
11026 "DEFAULT_ABI == ABI_V4
11027 || DEFAULT_ABI == ABI_DARWIN"
11028 {
11029 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11030 output_asm_insn ("crxor 6,6,6", operands);
11032 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11033 output_asm_insn ("creqv 6,6,6", operands);
11035 return "b%T1l";
11036 }
11037 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11038 (set_attr "length" "4,4,8,8")])
11040 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11041 [(set (match_operand 0 "" "")
11042 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11043 (match_operand 2 "" "g,g")))
11044 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11045 (clobber (reg:SI LR_REGNO))]
11046 "(DEFAULT_ABI == ABI_DARWIN
11047 || (DEFAULT_ABI == ABI_V4
11048 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11049 {
11050 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11051 output_asm_insn ("crxor 6,6,6", operands);
11053 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11054 output_asm_insn ("creqv 6,6,6", operands);
11056 #if TARGET_MACHO
11057 return output_call(insn, operands, 1, 3);
11058 #else
11059 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11060 {
11061 gcc_assert (!TARGET_SECURE_PLT);
11062 return "bl %z1@plt";
11063 }
11064 else
11065 return "bl %z1";
11066 #endif
11067 }
11068 "DEFAULT_ABI == ABI_V4
11069 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11070 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11071 [(parallel [(set (match_dup 0)
11072 (call (mem:SI (match_dup 1))
11073 (match_dup 2)))
11074 (use (match_dup 3))
11075 (use (match_dup 4))
11076 (clobber (reg:SI LR_REGNO))])]
11077 {
11078 operands[4] = pic_offset_table_rtx;
11079 }
11080 [(set_attr "type" "branch,branch")
11081 (set_attr "length" "4,8")])
11083 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11084 [(set (match_operand 0 "" "")
11085 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11086 (match_operand 2 "" "g,g")))
11087 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11088 (use (match_operand:SI 4 "register_operand" "r,r"))
11089 (clobber (reg:SI LR_REGNO))]
11090 "(DEFAULT_ABI == ABI_V4
11091 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11092 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11093 {
11094 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11095 output_asm_insn ("crxor 6,6,6", operands);
11097 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11098 output_asm_insn ("creqv 6,6,6", operands);
11100 if (flag_pic == 2)
11101 return "bl %z1+32768@plt";
11102 else
11103 return "bl %z1@plt";
11104 }
11105 [(set_attr "type" "branch,branch")
11106 (set_attr "length" "4,8")])
11109 ;; Call to AIX abi function in the same module.
11111 (define_insn "*call_local_aix<mode>"
11112 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
11113 (match_operand 1 "" "g"))
11114 (clobber (reg:P LR_REGNO))]
11115 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11116 "bl %z0"
11117 [(set_attr "type" "branch")
11118 (set_attr "length" "4")])
11120 (define_insn "*call_value_local_aix<mode>"
11121 [(set (match_operand 0 "" "")
11122 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
11123 (match_operand 2 "" "g")))
11124 (clobber (reg:P LR_REGNO))]
11125 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11126 "bl %z1"
11127 [(set_attr "type" "branch")
11128 (set_attr "length" "4")])
11130 ;; Call to AIX abi function which may be in another module.
11131 ;; Restore the TOC pointer (r2) after the call.
11133 (define_insn "*call_nonlocal_aix<mode>"
11134 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
11135 (match_operand 1 "" "g"))
11136 (clobber (reg:P LR_REGNO))]
11137 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11138 "bl %z0\;nop"
11139 [(set_attr "type" "branch")
11140 (set_attr "length" "8")])
11142 (define_insn "*call_value_nonlocal_aix<mode>"
11143 [(set (match_operand 0 "" "")
11144 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
11145 (match_operand 2 "" "g")))
11146 (clobber (reg:P LR_REGNO))]
11147 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11148 "bl %z1\;nop"
11149 [(set_attr "type" "branch")
11150 (set_attr "length" "8")])
11152 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11153 ;; Operand0 is the addresss of the function to call
11154 ;; Operand2 is the location in the function descriptor to load r2 from
11155 ;; Operand3 is the stack location to hold the current TOC pointer
11157 (define_insn "*call_indirect_aix<mode>"
11158 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11159 (match_operand 1 "" "g,g"))
11160 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11161 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11162 (clobber (reg:P LR_REGNO))]
11163 "DEFAULT_ABI == ABI_AIX"
11164 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11165 [(set_attr "type" "jmpreg")
11166 (set_attr "length" "12")])
11168 (define_insn "*call_value_indirect_aix<mode>"
11169 [(set (match_operand 0 "" "")
11170 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11171 (match_operand 2 "" "g,g")))
11172 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11173 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11174 (clobber (reg:P LR_REGNO))]
11175 "DEFAULT_ABI == ABI_AIX"
11176 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11177 [(set_attr "type" "jmpreg")
11178 (set_attr "length" "12")])
11180 ;; Call to indirect functions with the ELFv2 ABI.
11181 ;; Operand0 is the addresss of the function to call
11182 ;; Operand2 is the stack location to hold the current TOC pointer
11184 (define_insn "*call_indirect_elfv2<mode>"
11185 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11186 (match_operand 1 "" "g,g"))
11187 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11188 (clobber (reg:P LR_REGNO))]
11189 "DEFAULT_ABI == ABI_ELFv2"
11190 "b%T0l\;<ptrload> 2,%2"
11191 [(set_attr "type" "jmpreg")
11192 (set_attr "length" "8")])
11194 (define_insn "*call_value_indirect_elfv2<mode>"
11195 [(set (match_operand 0 "" "")
11196 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11197 (match_operand 2 "" "g,g")))
11198 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11199 (clobber (reg:P LR_REGNO))]
11200 "DEFAULT_ABI == ABI_ELFv2"
11201 "b%T1l\;<ptrload> 2,%3"
11202 [(set_attr "type" "jmpreg")
11203 (set_attr "length" "8")])
11206 ;; Call subroutine returning any type.
11207 (define_expand "untyped_call"
11208 [(parallel [(call (match_operand 0 "" "")
11209 (const_int 0))
11210 (match_operand 1 "" "")
11211 (match_operand 2 "" "")])]
11212 ""
11213 "
11214 {
11215 int i;
11217 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11219 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11220 {
11221 rtx set = XVECEXP (operands[2], 0, i);
11222 emit_move_insn (SET_DEST (set), SET_SRC (set));
11223 }
11225 /* The optimizer does not know that the call sets the function value
11226 registers we stored in the result block. We avoid problems by
11227 claiming that all hard registers are used and clobbered at this
11228 point. */
11229 emit_insn (gen_blockage ());
11231 DONE;
11232 }")
11234 ;; sibling call patterns
11235 (define_expand "sibcall"
11236 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11237 (match_operand 1 "" ""))
11238 (use (match_operand 2 "" ""))
11239 (use (reg:SI LR_REGNO))
11240 (simple_return)])]
11241 ""
11242 "
11243 {
11244 #if TARGET_MACHO
11245 if (MACHOPIC_INDIRECT)
11246 operands[0] = machopic_indirect_call_target (operands[0]);
11247 #endif
11249 gcc_assert (GET_CODE (operands[0]) == MEM);
11250 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11252 operands[0] = XEXP (operands[0], 0);
11254 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11255 {
11256 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11257 DONE;
11258 }
11259 }")
11261 (define_expand "sibcall_value"
11262 [(parallel [(set (match_operand 0 "register_operand" "")
11263 (call (mem:SI (match_operand 1 "address_operand" ""))
11264 (match_operand 2 "" "")))
11265 (use (match_operand 3 "" ""))
11266 (use (reg:SI LR_REGNO))
11267 (simple_return)])]
11268 ""
11269 "
11270 {
11271 #if TARGET_MACHO
11272 if (MACHOPIC_INDIRECT)
11273 operands[1] = machopic_indirect_call_target (operands[1]);
11274 #endif
11276 gcc_assert (GET_CODE (operands[1]) == MEM);
11277 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11279 operands[1] = XEXP (operands[1], 0);
11281 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11282 {
11283 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
11284 DONE;
11285 }
11286 }")
11288 ;; this and similar patterns must be marked as using LR, otherwise
11289 ;; dataflow will try to delete the store into it. This is true
11290 ;; even when the actual reg to jump to is in CTR, when LR was
11291 ;; saved and restored around the PIC-setting BCL.
11292 (define_insn "*sibcall_local32"
11293 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11294 (match_operand 1 "" "g,g"))
11295 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11296 (use (reg:SI LR_REGNO))
11297 (simple_return)]
11298 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11299 "*
11300 {
11301 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11302 output_asm_insn (\"crxor 6,6,6\", operands);
11304 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11305 output_asm_insn (\"creqv 6,6,6\", operands);
11307 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11308 }"
11309 [(set_attr "type" "branch")
11310 (set_attr "length" "4,8")])
11312 (define_insn "*sibcall_local64"
11313 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11314 (match_operand 1 "" "g,g"))
11315 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11316 (use (reg:SI LR_REGNO))
11317 (simple_return)]
11318 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11319 "*
11320 {
11321 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11322 output_asm_insn (\"crxor 6,6,6\", operands);
11324 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11325 output_asm_insn (\"creqv 6,6,6\", operands);
11327 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11328 }"
11329 [(set_attr "type" "branch")
11330 (set_attr "length" "4,8")])
11332 (define_insn "*sibcall_value_local32"
11333 [(set (match_operand 0 "" "")
11334 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11335 (match_operand 2 "" "g,g")))
11336 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11337 (use (reg:SI LR_REGNO))
11338 (simple_return)]
11339 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11340 "*
11341 {
11342 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11343 output_asm_insn (\"crxor 6,6,6\", operands);
11345 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11346 output_asm_insn (\"creqv 6,6,6\", operands);
11348 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11349 }"
11350 [(set_attr "type" "branch")
11351 (set_attr "length" "4,8")])
11353 (define_insn "*sibcall_value_local64"
11354 [(set (match_operand 0 "" "")
11355 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11356 (match_operand 2 "" "g,g")))
11357 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11358 (use (reg:SI LR_REGNO))
11359 (simple_return)]
11360 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11361 "*
11362 {
11363 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11364 output_asm_insn (\"crxor 6,6,6\", operands);
11366 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11367 output_asm_insn (\"creqv 6,6,6\", operands);
11369 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11370 }"
11371 [(set_attr "type" "branch")
11372 (set_attr "length" "4,8")])
11374 (define_insn "*sibcall_nonlocal_sysv<mode>"
11375 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11376 (match_operand 1 "" ""))
11377 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11378 (use (reg:SI LR_REGNO))
11379 (simple_return)]
11380 "(DEFAULT_ABI == ABI_DARWIN
11381 || DEFAULT_ABI == ABI_V4)
11382 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11383 "*
11384 {
11385 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11386 output_asm_insn (\"crxor 6,6,6\", operands);
11388 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11389 output_asm_insn (\"creqv 6,6,6\", operands);
11391 if (which_alternative >= 2)
11392 return \"b%T0\";
11393 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11394 {
11395 gcc_assert (!TARGET_SECURE_PLT);
11396 return \"b %z0@plt\";
11397 }
11398 else
11399 return \"b %z0\";
11400 }"
11401 [(set_attr "type" "branch")
11402 (set_attr "length" "4,8,4,8")])
11404 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11405 [(set (match_operand 0 "" "")
11406 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11407 (match_operand 2 "" "")))
11408 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11409 (use (reg:SI LR_REGNO))
11410 (simple_return)]
11411 "(DEFAULT_ABI == ABI_DARWIN
11412 || DEFAULT_ABI == ABI_V4)
11413 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11414 "*
11415 {
11416 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11417 output_asm_insn (\"crxor 6,6,6\", operands);
11419 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11420 output_asm_insn (\"creqv 6,6,6\", operands);
11422 if (which_alternative >= 2)
11423 return \"b%T1\";
11424 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11425 {
11426 gcc_assert (!TARGET_SECURE_PLT);
11427 return \"b %z1@plt\";
11428 }
11429 else
11430 return \"b %z1\";
11431 }"
11432 [(set_attr "type" "branch")
11433 (set_attr "length" "4,8,4,8")])
11435 ;; AIX ABI sibling call patterns.
11437 (define_insn "*sibcall_aix<mode>"
11438 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11439 (match_operand 1 "" "g,g"))
11440 (simple_return)]
11441 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11442 "@
11443 b %z0
11444 b%T0"
11445 [(set_attr "type" "branch")
11446 (set_attr "length" "4")])
11448 (define_insn "*sibcall_value_aix<mode>"
11449 [(set (match_operand 0 "" "")
11450 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11451 (match_operand 2 "" "g,g")))
11452 (simple_return)]
11453 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11454 "@
11455 b %z1
11456 b%T1"
11457 [(set_attr "type" "branch")
11458 (set_attr "length" "4")])
11460 (define_expand "sibcall_epilogue"
11461 [(use (const_int 0))]
11462 ""
11463 {
11464 if (!TARGET_SCHED_PROLOG)
11465 emit_insn (gen_blockage ());
11466 rs6000_emit_epilogue (TRUE);
11467 DONE;
11468 })
11470 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11471 ;; all of memory. This blocks insns from being moved across this point.
11473 (define_insn "blockage"
11474 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11475 ""
11476 "")
11478 (define_expand "probe_stack"
11479 [(set (match_operand 0 "memory_operand" "=m")
11480 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11481 ""
11482 {
11483 if (TARGET_64BIT)
11484 emit_insn (gen_probe_stack_di (operands[0]));
11485 else
11486 emit_insn (gen_probe_stack_si (operands[0]));
11487 DONE;
11488 })
11490 (define_insn "probe_stack_<mode>"
11491 [(set (match_operand:P 0 "memory_operand" "=m")
11492 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
11493 ""
11494 {
11495 operands[1] = gen_rtx_REG (Pmode, 0);
11496 return "st<wd>%U0%X0 %1,%0";
11497 }
11498 [(set_attr "type" "store")
11499 (set (attr "update")
11500 (if_then_else (match_operand 0 "update_address_mem")
11501 (const_string "yes")
11502 (const_string "no")))
11503 (set (attr "indexed")
11504 (if_then_else (match_operand 0 "indexed_address_mem")
11505 (const_string "yes")
11506 (const_string "no")))
11507 (set_attr "length" "4")])
11509 (define_insn "probe_stack_range<P:mode>"
11510 [(set (match_operand:P 0 "register_operand" "=r")
11511 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11512 (match_operand:P 2 "register_operand" "r")]
11513 UNSPECV_PROBE_STACK_RANGE))]
11514 ""
11515 "* return output_probe_stack_range (operands[0], operands[2]);"
11516 [(set_attr "type" "three")])
11517 \f
11518 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11519 ;; signed & unsigned, and one type of branch.
11520 ;;
11521 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11522 ;; insns, and branches.
11524 (define_expand "cbranch<mode>4"
11525 [(use (match_operator 0 "rs6000_cbranch_operator"
11526 [(match_operand:GPR 1 "gpc_reg_operand" "")
11527 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11528 (use (match_operand 3 ""))]
11529 ""
11530 "
11531 {
11532 /* Take care of the possibility that operands[2] might be negative but
11533 this might be a logical operation. That insn doesn't exist. */
11534 if (GET_CODE (operands[2]) == CONST_INT
11535 && INTVAL (operands[2]) < 0)
11536 {
11537 operands[2] = force_reg (<MODE>mode, operands[2]);
11538 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11539 GET_MODE (operands[0]),
11540 operands[1], operands[2]);
11541 }
11543 rs6000_emit_cbranch (<MODE>mode, operands);
11544 DONE;
11545 }")
11547 (define_expand "cbranch<mode>4"
11548 [(use (match_operator 0 "rs6000_cbranch_operator"
11549 [(match_operand:FP 1 "gpc_reg_operand" "")
11550 (match_operand:FP 2 "gpc_reg_operand" "")]))
11551 (use (match_operand 3 ""))]
11552 ""
11553 "
11554 {
11555 rs6000_emit_cbranch (<MODE>mode, operands);
11556 DONE;
11557 }")
11559 (define_expand "cstore<mode>4"
11560 [(use (match_operator 1 "rs6000_cbranch_operator"
11561 [(match_operand:GPR 2 "gpc_reg_operand" "")
11562 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11563 (clobber (match_operand:SI 0 "register_operand"))]
11564 ""
11565 "
11566 {
11567 /* Take care of the possibility that operands[3] might be negative but
11568 this might be a logical operation. That insn doesn't exist. */
11569 if (GET_CODE (operands[3]) == CONST_INT
11570 && INTVAL (operands[3]) < 0)
11571 {
11572 operands[3] = force_reg (<MODE>mode, operands[3]);
11573 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11574 GET_MODE (operands[1]),
11575 operands[2], operands[3]);
11576 }
11578 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11579 For SEQ, likewise, except that comparisons with zero should be done
11580 with an scc insns. However, due to the order that combine see the
11581 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11582 the cases we don't want to handle or are best handled by portable
11583 code. */
11584 if (GET_CODE (operands[1]) == NE)
11585 FAIL;
11586 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11587 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11588 && operands[3] == const0_rtx)
11589 FAIL;
11590 rs6000_emit_sCOND (<MODE>mode, operands);
11591 DONE;
11592 }")
11594 (define_expand "cstore<mode>4"
11595 [(use (match_operator 1 "rs6000_cbranch_operator"
11596 [(match_operand:FP 2 "gpc_reg_operand" "")
11597 (match_operand:FP 3 "gpc_reg_operand" "")]))
11598 (clobber (match_operand:SI 0 "register_operand"))]
11599 ""
11600 "
11601 {
11602 rs6000_emit_sCOND (<MODE>mode, operands);
11603 DONE;
11604 }")
11607 (define_expand "stack_protect_set"
11608 [(match_operand 0 "memory_operand" "")
11609 (match_operand 1 "memory_operand" "")]
11610 ""
11611 {
11612 #ifdef TARGET_THREAD_SSP_OFFSET
11613 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11614 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11615 operands[1] = gen_rtx_MEM (Pmode, addr);
11616 #endif
11617 if (TARGET_64BIT)
11618 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11619 else
11620 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11621 DONE;
11622 })
11624 (define_insn "stack_protect_setsi"
11625 [(set (match_operand:SI 0 "memory_operand" "=m")
11626 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11627 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11628 "TARGET_32BIT"
11629 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11630 [(set_attr "type" "three")
11631 (set_attr "length" "12")])
11633 (define_insn "stack_protect_setdi"
11634 [(set (match_operand:DI 0 "memory_operand" "=Y")
11635 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11636 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11637 "TARGET_64BIT"
11638 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11639 [(set_attr "type" "three")
11640 (set_attr "length" "12")])
11642 (define_expand "stack_protect_test"
11643 [(match_operand 0 "memory_operand" "")
11644 (match_operand 1 "memory_operand" "")
11645 (match_operand 2 "" "")]
11646 ""
11647 {
11648 rtx test, op0, op1;
11649 #ifdef TARGET_THREAD_SSP_OFFSET
11650 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11651 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11652 operands[1] = gen_rtx_MEM (Pmode, addr);
11653 #endif
11654 op0 = operands[0];
11655 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11656 test = gen_rtx_EQ (VOIDmode, op0, op1);
11657 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11658 DONE;
11659 })
11661 (define_insn "stack_protect_testsi"
11662 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11663 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11664 (match_operand:SI 2 "memory_operand" "m,m")]
11665 UNSPEC_SP_TEST))
11666 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11667 (clobber (match_scratch:SI 3 "=&r,&r"))]
11668 "TARGET_32BIT"
11669 "@
11670 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11671 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11672 [(set_attr "length" "16,20")])
11674 (define_insn "stack_protect_testdi"
11675 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11676 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11677 (match_operand:DI 2 "memory_operand" "Y,Y")]
11678 UNSPEC_SP_TEST))
11679 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11680 (clobber (match_scratch:DI 3 "=&r,&r"))]
11681 "TARGET_64BIT"
11682 "@
11683 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11684 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11685 [(set_attr "length" "16,20")])
11687 \f
11688 ;; Here are the actual compare insns.
11689 (define_insn "*cmp<mode>_internal1"
11690 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11691 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11692 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11693 ""
11694 "cmp<wd>%I2 %0,%1,%2"
11695 [(set_attr "type" "cmp")])
11697 ;; If we are comparing a register for equality with a large constant,
11698 ;; we can do this with an XOR followed by a compare. But this is profitable
11699 ;; only if the large constant is only used for the comparison (and in this
11700 ;; case we already have a register to reuse as scratch).
11701 ;;
11702 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11703 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11705 (define_peephole2
11706 [(set (match_operand:SI 0 "register_operand")
11707 (match_operand:SI 1 "logical_const_operand" ""))
11708 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11709 [(match_dup 0)
11710 (match_operand:SI 2 "logical_const_operand" "")]))
11711 (set (match_operand:CC 4 "cc_reg_operand" "")
11712 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11713 (match_dup 0)))
11714 (set (pc)
11715 (if_then_else (match_operator 6 "equality_operator"
11716 [(match_dup 4) (const_int 0)])
11717 (match_operand 7 "" "")
11718 (match_operand 8 "" "")))]
11719 "peep2_reg_dead_p (3, operands[0])
11720 && peep2_reg_dead_p (4, operands[4])"
11721 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11722 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11723 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11725 {
11726 /* Get the constant we are comparing against, and see what it looks like
11727 when sign-extended from 16 to 32 bits. Then see what constant we could
11728 XOR with SEXTC to get the sign-extended value. */
11729 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11730 SImode,
11731 operands[1], operands[2]);
11732 HOST_WIDE_INT c = INTVAL (cnst);
11733 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11734 HOST_WIDE_INT xorv = c ^ sextc;
11736 operands[9] = GEN_INT (xorv);
11737 operands[10] = GEN_INT (sextc);
11738 })
11740 (define_insn "*cmpsi_internal2"
11741 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11742 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11743 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11744 ""
11745 "cmplw%I2 %0,%1,%b2"
11746 [(set_attr "type" "cmp")])
11748 (define_insn "*cmpdi_internal2"
11749 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11750 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11751 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11752 ""
11753 "cmpld%I2 %0,%1,%b2"
11754 [(set_attr "type" "cmp")])
11756 ;; The following two insns don't exist as single insns, but if we provide
11757 ;; them, we can swap an add and compare, which will enable us to overlap more
11758 ;; of the required delay between a compare and branch. We generate code for
11759 ;; them by splitting.
11761 (define_insn ""
11762 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11763 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11764 (match_operand:SI 2 "short_cint_operand" "i")))
11765 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11766 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11767 ""
11768 "#"
11769 [(set_attr "length" "8")])
11771 (define_insn ""
11772 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11773 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11774 (match_operand:SI 2 "u_short_cint_operand" "i")))
11775 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11776 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11777 ""
11778 "#"
11779 [(set_attr "length" "8")])
11781 (define_split
11782 [(set (match_operand:CC 3 "cc_reg_operand" "")
11783 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11784 (match_operand:SI 2 "short_cint_operand" "")))
11785 (set (match_operand:SI 0 "gpc_reg_operand" "")
11786 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11787 ""
11788 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11789 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11791 (define_split
11792 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11793 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11794 (match_operand:SI 2 "u_short_cint_operand" "")))
11795 (set (match_operand:SI 0 "gpc_reg_operand" "")
11796 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11797 ""
11798 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11799 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11801 ;; Only need to compare second words if first words equal
11802 (define_insn "*cmptf_internal1"
11803 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11804 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11805 (match_operand:TF 2 "gpc_reg_operand" "d")))]
11806 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11807 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11808 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11809 [(set_attr "type" "fpcompare")
11810 (set_attr "length" "12")])
11812 (define_insn_and_split "*cmptf_internal2"
11813 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11814 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11815 (match_operand:TF 2 "gpc_reg_operand" "d")))
11816 (clobber (match_scratch:DF 3 "=d"))
11817 (clobber (match_scratch:DF 4 "=d"))
11818 (clobber (match_scratch:DF 5 "=d"))
11819 (clobber (match_scratch:DF 6 "=d"))
11820 (clobber (match_scratch:DF 7 "=d"))
11821 (clobber (match_scratch:DF 8 "=d"))
11822 (clobber (match_scratch:DF 9 "=d"))
11823 (clobber (match_scratch:DF 10 "=d"))
11824 (clobber (match_scratch:GPR 11 "=b"))]
11825 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11826 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11827 "#"
11828 "&& reload_completed"
11829 [(set (match_dup 3) (match_dup 14))
11830 (set (match_dup 4) (match_dup 15))
11831 (set (match_dup 9) (abs:DF (match_dup 5)))
11832 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11833 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11834 (label_ref (match_dup 12))
11835 (pc)))
11836 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11837 (set (pc) (label_ref (match_dup 13)))
11838 (match_dup 12)
11839 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11840 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11841 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11842 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11843 (match_dup 13)]
11844 {
11845 REAL_VALUE_TYPE rv;
11846 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
11847 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
11849 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11850 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11851 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11852 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11853 operands[12] = gen_label_rtx ();
11854 operands[13] = gen_label_rtx ();
11855 real_inf (&rv);
11856 operands[14] = force_const_mem (DFmode,
11857 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11858 operands[15] = force_const_mem (DFmode,
11859 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11860 DFmode));
11861 if (TARGET_TOC)
11862 {
11863 rtx tocref;
11864 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11865 operands[14] = gen_const_mem (DFmode, tocref);
11866 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11867 operands[15] = gen_const_mem (DFmode, tocref);
11868 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11869 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11870 }
11871 })
11872 \f
11873 ;; Now we have the scc insns. We can do some combinations because of the
11874 ;; way the machine works.
11875 ;;
11876 ;; Note that this is probably faster if we can put an insn between the
11877 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11878 ;; cases the insns below which don't use an intermediate CR field will
11879 ;; be used instead.
11880 (define_insn ""
11881 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11882 (match_operator:SI 1 "scc_comparison_operator"
11883 [(match_operand 2 "cc_reg_operand" "y")
11884 (const_int 0)]))]
11885 ""
11886 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11887 [(set (attr "type")
11888 (cond [(match_test "TARGET_MFCRF")
11889 (const_string "mfcrf")
11890 ]
11891 (const_string "mfcr")))
11892 (set_attr "length" "8")])
11894 ;; Same as above, but get the GT bit.
11895 (define_insn "move_from_CR_gt_bit"
11896 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11897 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11898 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11899 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11900 [(set_attr "type" "mfcr")
11901 (set_attr "length" "8")])
11903 ;; Same as above, but get the OV/ORDERED bit.
11904 (define_insn "move_from_CR_ov_bit"
11905 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11906 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
11907 UNSPEC_MV_CR_OV))]
11908 "TARGET_ISEL"
11909 "mfcr %0\;rlwinm %0,%0,%t1,1"
11910 [(set_attr "type" "mfcr")
11911 (set_attr "length" "8")])
11913 (define_insn ""
11914 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11915 (match_operator:DI 1 "scc_comparison_operator"
11916 [(match_operand 2 "cc_reg_operand" "y")
11917 (const_int 0)]))]
11918 "TARGET_POWERPC64"
11919 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11920 [(set (attr "type")
11921 (cond [(match_test "TARGET_MFCRF")
11922 (const_string "mfcrf")
11923 ]
11924 (const_string "mfcr")))
11925 (set_attr "length" "8")])
11927 (define_insn ""
11928 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11929 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11930 [(match_operand 2 "cc_reg_operand" "y,y")
11931 (const_int 0)])
11932 (const_int 0)))
11933 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11934 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11935 "TARGET_32BIT"
11936 "@
11937 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11938 #"
11939 [(set_attr "type" "shift")
11940 (set_attr "dot" "yes")
11941 (set_attr "length" "8,16")])
11943 (define_split
11944 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11945 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11946 [(match_operand 2 "cc_reg_operand" "")
11947 (const_int 0)])
11948 (const_int 0)))
11949 (set (match_operand:SI 3 "gpc_reg_operand" "")
11950 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11951 "TARGET_32BIT && reload_completed"
11952 [(set (match_dup 3)
11953 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11954 (set (match_dup 0)
11955 (compare:CC (match_dup 3)
11956 (const_int 0)))]
11957 "")
11959 (define_insn ""
11960 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11961 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11962 [(match_operand 2 "cc_reg_operand" "y")
11963 (const_int 0)])
11964 (match_operand:SI 3 "const_int_operand" "n")))]
11965 ""
11966 "*
11967 {
11968 int is_bit = ccr_bit (operands[1], 1);
11969 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11970 int count;
11972 if (is_bit >= put_bit)
11973 count = is_bit - put_bit;
11974 else
11975 count = 32 - (put_bit - is_bit);
11977 operands[4] = GEN_INT (count);
11978 operands[5] = GEN_INT (put_bit);
11980 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11981 }"
11982 [(set (attr "type")
11983 (cond [(match_test "TARGET_MFCRF")
11984 (const_string "mfcrf")
11985 ]
11986 (const_string "mfcr")))
11987 (set_attr "length" "8")])
11989 (define_insn ""
11990 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11991 (compare:CC
11992 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11993 [(match_operand 2 "cc_reg_operand" "y,y")
11994 (const_int 0)])
11995 (match_operand:SI 3 "const_int_operand" "n,n"))
11996 (const_int 0)))
11997 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11998 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11999 (match_dup 3)))]
12000 ""
12001 "*
12002 {
12003 int is_bit = ccr_bit (operands[1], 1);
12004 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12005 int count;
12007 /* Force split for non-cc0 compare. */
12008 if (which_alternative == 1)
12009 return \"#\";
12011 if (is_bit >= put_bit)
12012 count = is_bit - put_bit;
12013 else
12014 count = 32 - (put_bit - is_bit);
12016 operands[5] = GEN_INT (count);
12017 operands[6] = GEN_INT (put_bit);
12019 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
12020 }"
12021 [(set_attr "type" "shift")
12022 (set_attr "dot" "yes")
12023 (set_attr "length" "8,16")])
12025 (define_split
12026 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12027 (compare:CC
12028 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12029 [(match_operand 2 "cc_reg_operand" "")
12030 (const_int 0)])
12031 (match_operand:SI 3 "const_int_operand" ""))
12032 (const_int 0)))
12033 (set (match_operand:SI 4 "gpc_reg_operand" "")
12034 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12035 (match_dup 3)))]
12036 "reload_completed"
12037 [(set (match_dup 4)
12038 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12039 (match_dup 3)))
12040 (set (match_dup 0)
12041 (compare:CC (match_dup 4)
12042 (const_int 0)))]
12043 "")
12045 ;; There is a 3 cycle delay between consecutive mfcr instructions
12046 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12048 (define_peephole
12049 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12050 (match_operator:SI 1 "scc_comparison_operator"
12051 [(match_operand 2 "cc_reg_operand" "y")
12052 (const_int 0)]))
12053 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12054 (match_operator:SI 4 "scc_comparison_operator"
12055 [(match_operand 5 "cc_reg_operand" "y")
12056 (const_int 0)]))]
12057 "REGNO (operands[2]) != REGNO (operands[5])"
12058 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12059 [(set_attr "type" "mfcr")
12060 (set_attr "length" "12")])
12062 (define_peephole
12063 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12064 (match_operator:DI 1 "scc_comparison_operator"
12065 [(match_operand 2 "cc_reg_operand" "y")
12066 (const_int 0)]))
12067 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12068 (match_operator:DI 4 "scc_comparison_operator"
12069 [(match_operand 5 "cc_reg_operand" "y")
12070 (const_int 0)]))]
12071 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12072 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12073 [(set_attr "type" "mfcr")
12074 (set_attr "length" "12")])
12076 ;; There are some scc insns that can be done directly, without a compare.
12077 ;; These are faster because they don't involve the communications between
12078 ;; the FXU and branch units. In fact, we will be replacing all of the
12079 ;; integer scc insns here or in the portable methods in emit_store_flag.
12080 ;;
12081 ;; Also support (neg (scc ..)) since that construct is used to replace
12082 ;; branches, (plus (scc ..) ..) since that construct is common and
12083 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12084 ;; cases where it is no more expensive than (neg (scc ..)).
12086 ;; Have reload force a constant into a register for the simple insns that
12087 ;; otherwise won't accept constants. We do this because it is faster than
12088 ;; the cmp/mfcr sequence we would otherwise generate.
12090 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12091 (DI "rKJI")])
12093 (define_insn_and_split "*eq<mode>"
12094 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12095 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12096 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12097 ""
12098 "#"
12099 ""
12100 [(set (match_dup 0)
12101 (clz:GPR (match_dup 3)))
12102 (set (match_dup 0)
12103 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12104 {
12105 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12106 {
12107 /* Use output operand as intermediate. */
12108 operands[3] = operands[0];
12110 if (logical_operand (operands[2], <MODE>mode))
12111 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12112 gen_rtx_XOR (<MODE>mode,
12113 operands[1], operands[2])));
12114 else
12115 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12116 gen_rtx_PLUS (<MODE>mode, operands[1],
12117 negate_rtx (<MODE>mode,
12118 operands[2]))));
12119 }
12120 else
12121 operands[3] = operands[1];
12123 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12124 })
12126 (define_insn_and_split "*eq<mode>_compare"
12127 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12128 (compare:CC
12129 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12130 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12131 (const_int 0)))
12132 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12133 (eq:P (match_dup 1) (match_dup 2)))]
12134 "optimize_size"
12135 "#"
12136 "optimize_size"
12137 [(set (match_dup 0)
12138 (clz:P (match_dup 4)))
12139 (parallel [(set (match_dup 3)
12140 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12141 (const_int 0)))
12142 (set (match_dup 0)
12143 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12144 {
12145 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12146 {
12147 /* Use output operand as intermediate. */
12148 operands[4] = operands[0];
12150 if (logical_operand (operands[2], <MODE>mode))
12151 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12152 gen_rtx_XOR (<MODE>mode,
12153 operands[1], operands[2])));
12154 else
12155 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12156 gen_rtx_PLUS (<MODE>mode, operands[1],
12157 negate_rtx (<MODE>mode,
12158 operands[2]))));
12159 }
12160 else
12161 operands[4] = operands[1];
12163 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12164 })
12166 ;; We have insns of the form shown by the first define_insn below. If
12167 ;; there is something inside the comparison operation, we must split it.
12168 (define_split
12169 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12170 (plus:SI (match_operator 1 "comparison_operator"
12171 [(match_operand:SI 2 "" "")
12172 (match_operand:SI 3
12173 "reg_or_cint_operand" "")])
12174 (match_operand:SI 4 "gpc_reg_operand" "")))
12175 (clobber (match_operand:SI 5 "register_operand" ""))]
12176 "! gpc_reg_operand (operands[2], SImode)"
12177 [(set (match_dup 5) (match_dup 2))
12178 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
12179 (match_dup 4)))])
12181 (define_insn "*plus_eqsi"
12182 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12183 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12184 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12185 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12186 "TARGET_32BIT"
12187 "@
12188 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
12189 subfic %0,%1,0\;addze %0,%3
12190 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
12191 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
12192 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
12193 [(set_attr "type" "three,two,three,three,three")
12194 (set_attr "length" "12,8,12,12,12")])
12196 (define_insn "*compare_plus_eqsi"
12197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12198 (compare:CC
12199 (plus:SI
12200 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12201 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12202 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12203 (const_int 0)))
12204 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12205 "TARGET_32BIT && optimize_size"
12206 "@
12207 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12208 subfic %4,%1,0\;addze. %4,%3
12209 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
12210 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
12211 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12212 #
12213 #
12214 #
12215 #
12216 #"
12217 [(set_attr "type" "compare")
12218 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12220 (define_split
12221 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12222 (compare:CC
12223 (plus:SI
12224 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12225 (match_operand:SI 2 "scc_eq_operand" ""))
12226 (match_operand:SI 3 "gpc_reg_operand" ""))
12227 (const_int 0)))
12228 (clobber (match_scratch:SI 4 ""))]
12229 "TARGET_32BIT && optimize_size && reload_completed"
12230 [(set (match_dup 4)
12231 (plus:SI (eq:SI (match_dup 1)
12232 (match_dup 2))
12233 (match_dup 3)))
12234 (set (match_dup 0)
12235 (compare:CC (match_dup 4)
12236 (const_int 0)))]
12237 "")
12239 (define_insn "*plus_eqsi_compare"
12240 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12241 (compare:CC
12242 (plus:SI
12243 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12244 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12245 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12246 (const_int 0)))
12247 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12248 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12249 "TARGET_32BIT && optimize_size"
12250 "@
12251 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12252 subfic %0,%1,0\;addze. %0,%3
12253 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
12254 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
12255 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12256 #
12257 #
12258 #
12259 #
12260 #"
12261 [(set_attr "type" "compare")
12262 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12264 (define_split
12265 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12266 (compare:CC
12267 (plus:SI
12268 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12269 (match_operand:SI 2 "scc_eq_operand" ""))
12270 (match_operand:SI 3 "gpc_reg_operand" ""))
12271 (const_int 0)))
12272 (set (match_operand:SI 0 "gpc_reg_operand" "")
12273 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12274 "TARGET_32BIT && optimize_size && reload_completed"
12275 [(set (match_dup 0)
12276 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12277 (set (match_dup 4)
12278 (compare:CC (match_dup 0)
12279 (const_int 0)))]
12280 "")
12282 (define_insn "*neg_eq0<mode>"
12283 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12284 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12285 (const_int 0))))]
12286 ""
12287 "addic %0,%1,-1\;subfe %0,%0,%0"
12288 [(set_attr "type" "two")
12289 (set_attr "length" "8")])
12291 (define_insn_and_split "*neg_eq<mode>"
12292 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12293 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12294 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12295 ""
12296 "#"
12297 ""
12298 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12299 {
12300 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12301 {
12302 /* Use output operand as intermediate. */
12303 operands[3] = operands[0];
12305 if (logical_operand (operands[2], <MODE>mode))
12306 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12307 gen_rtx_XOR (<MODE>mode,
12308 operands[1], operands[2])));
12309 else
12310 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12311 gen_rtx_PLUS (<MODE>mode, operands[1],
12312 negate_rtx (<MODE>mode,
12313 operands[2]))));
12314 }
12315 else
12316 operands[3] = operands[1];
12317 })
12319 (define_insn "*ne0_<mode>"
12320 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12321 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12322 (const_int 0)))
12323 (clobber (match_scratch:P 2 "=&r"))]
12324 "!(TARGET_32BIT && TARGET_ISEL)"
12325 "addic %2,%1,-1\;subfe %0,%2,%1"
12326 [(set_attr "type" "two")
12327 (set_attr "length" "8")])
12329 (define_insn "*plus_ne0_<mode>"
12330 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12331 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12332 (const_int 0))
12333 (match_operand:P 2 "gpc_reg_operand" "r")))
12334 (clobber (match_scratch:P 3 "=&r"))]
12335 ""
12336 "addic %3,%1,-1\;addze %0,%2"
12337 [(set_attr "type" "two")
12338 (set_attr "length" "8")])
12340 (define_insn "*compare_plus_ne0_<mode>"
12341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12342 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12343 (const_int 0))
12344 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12345 (const_int 0)))
12346 (clobber (match_scratch:P 3 "=&r,&r"))
12347 (clobber (match_scratch:P 4 "=X,&r"))]
12348 ""
12349 "@
12350 addic %3,%1,-1\;addze. %3,%2
12351 #"
12352 [(set_attr "type" "compare")
12353 (set_attr "length" "8,12")])
12355 (define_split
12356 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12357 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12358 (const_int 0))
12359 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12360 (clobber (match_scratch:P 3 ""))
12361 (clobber (match_scratch:P 4 ""))]
12362 "reload_completed"
12363 [(parallel [(set (match_dup 3)
12364 (plus:P (ne:P (match_dup 1)
12365 (const_int 0))
12366 (match_dup 2)))
12367 (clobber (match_dup 4))])
12368 (set (match_dup 0)
12369 (compare:CC (match_dup 3)
12370 (const_int 0)))]
12371 "")
12373 ; For combine.
12374 (define_insn "*compare_plus_ne0_<mode>_1"
12375 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12376 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12377 (const_int 0))
12378 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
12379 (clobber (match_scratch:P 3 "=&r,&r"))
12380 (clobber (match_scratch:P 4 "=X,&r"))]
12381 ""
12382 "@
12383 addic %3,%1,-1\;addze. %3,%2
12384 #"
12385 [(set_attr "type" "compare")
12386 (set_attr "length" "8,12")])
12388 (define_split
12389 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
12390 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12391 (const_int 0))
12392 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12393 (clobber (match_scratch:P 3 ""))
12394 (clobber (match_scratch:P 4 ""))]
12395 "reload_completed"
12396 [(parallel [(set (match_dup 3)
12397 (plus:P (ne:P (match_dup 1)
12398 (const_int 0))
12399 (match_dup 2)))
12400 (clobber (match_dup 4))])
12401 (set (match_dup 0)
12402 (compare:CC (match_dup 3)
12403 (const_int 0)))]
12404 "")
12406 (define_insn "*plus_ne0_<mode>_compare"
12407 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12408 (compare:CC
12409 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12410 (const_int 0))
12411 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12412 (const_int 0)))
12413 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12414 (plus:P (ne:P (match_dup 1)
12415 (const_int 0))
12416 (match_dup 2)))
12417 (clobber (match_scratch:P 3 "=&r,&r"))]
12418 ""
12419 "@
12420 addic %3,%1,-1\;addze. %0,%2
12421 #"
12422 [(set_attr "type" "compare")
12423 (set_attr "length" "8,12")])
12425 (define_split
12426 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12427 (compare:CC
12428 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
12429 (const_int 0))
12430 (match_operand:P 2 "gpc_reg_operand" ""))
12431 (const_int 0)))
12432 (set (match_operand:P 0 "gpc_reg_operand" "")
12433 (plus:P (ne:P (match_dup 1)
12434 (const_int 0))
12435 (match_dup 2)))
12436 (clobber (match_scratch:P 3 ""))]
12437 "reload_completed"
12438 [(parallel [(set (match_dup 0)
12439 (plus:P (ne:P (match_dup 1)
12440 (const_int 0))
12441 (match_dup 2)))
12442 (clobber (match_dup 3))])
12443 (set (match_dup 4)
12444 (compare:CC (match_dup 0)
12445 (const_int 0)))]
12446 "")
12448 (define_insn "*leu<mode>"
12449 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12450 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12451 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12452 ""
12453 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12454 [(set_attr "type" "three")
12455 (set_attr "length" "12")])
12457 (define_insn "*leu<mode>_compare"
12458 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12459 (compare:CC
12460 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12461 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12462 (const_int 0)))
12463 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12464 (leu:P (match_dup 1) (match_dup 2)))]
12465 ""
12466 "@
12467 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12468 #"
12469 [(set_attr "type" "compare")
12470 (set_attr "length" "12,16")])
12472 (define_split
12473 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12474 (compare:CC
12475 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12476 (match_operand:P 2 "reg_or_short_operand" ""))
12477 (const_int 0)))
12478 (set (match_operand:P 0 "gpc_reg_operand" "")
12479 (leu:P (match_dup 1) (match_dup 2)))]
12480 "reload_completed"
12481 [(set (match_dup 0)
12482 (leu:P (match_dup 1) (match_dup 2)))
12483 (set (match_dup 3)
12484 (compare:CC (match_dup 0)
12485 (const_int 0)))]
12486 "")
12488 (define_insn "*plus_leu<mode>"
12489 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12490 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12491 (match_operand:P 2 "reg_or_short_operand" "rI"))
12492 (match_operand:P 3 "gpc_reg_operand" "r")))]
12493 ""
12494 "subf%I2c %0,%1,%2\;addze %0,%3"
12495 [(set_attr "type" "two")
12496 (set_attr "length" "8")])
12498 (define_insn ""
12499 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12500 (compare:CC
12501 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12502 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12503 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12504 (const_int 0)))
12505 (clobber (match_scratch:SI 4 "=&r,&r"))]
12506 "TARGET_32BIT"
12507 "@
12508 subf%I2c %4,%1,%2\;addze. %4,%3
12509 #"
12510 [(set_attr "type" "compare")
12511 (set_attr "length" "8,12")])
12513 (define_split
12514 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12515 (compare:CC
12516 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12517 (match_operand:SI 2 "reg_or_short_operand" ""))
12518 (match_operand:SI 3 "gpc_reg_operand" ""))
12519 (const_int 0)))
12520 (clobber (match_scratch:SI 4 ""))]
12521 "TARGET_32BIT && reload_completed"
12522 [(set (match_dup 4)
12523 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12524 (match_dup 3)))
12525 (set (match_dup 0)
12526 (compare:CC (match_dup 4)
12527 (const_int 0)))]
12528 "")
12530 (define_insn ""
12531 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12532 (compare:CC
12533 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12534 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12535 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12536 (const_int 0)))
12537 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12538 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12539 "TARGET_32BIT"
12540 "@
12541 subf%I2c %0,%1,%2\;addze. %0,%3
12542 #"
12543 [(set_attr "type" "compare")
12544 (set_attr "length" "8,12")])
12546 (define_split
12547 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12548 (compare:CC
12549 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12550 (match_operand:SI 2 "reg_or_short_operand" ""))
12551 (match_operand:SI 3 "gpc_reg_operand" ""))
12552 (const_int 0)))
12553 (set (match_operand:SI 0 "gpc_reg_operand" "")
12554 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12555 "TARGET_32BIT && reload_completed"
12556 [(set (match_dup 0)
12557 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12558 (set (match_dup 4)
12559 (compare:CC (match_dup 0)
12560 (const_int 0)))]
12561 "")
12563 (define_insn "*neg_leu<mode>"
12564 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12565 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12566 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12567 ""
12568 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
12569 [(set_attr "type" "three")
12570 (set_attr "length" "12")])
12572 (define_insn "*and_neg_leu<mode>"
12573 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12574 (and:P (neg:P
12575 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12576 (match_operand:P 2 "reg_or_short_operand" "rI")))
12577 (match_operand:P 3 "gpc_reg_operand" "r")))]
12578 ""
12579 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
12580 [(set_attr "type" "three")
12581 (set_attr "length" "12")])
12583 (define_insn ""
12584 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12585 (compare:CC
12586 (and:SI (neg:SI
12587 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12588 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12589 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12590 (const_int 0)))
12591 (clobber (match_scratch:SI 4 "=&r,&r"))]
12592 "TARGET_32BIT"
12593 "@
12594 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
12595 #"
12596 [(set_attr "type" "compare")
12597 (set_attr "length" "12,16")])
12599 (define_split
12600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12601 (compare:CC
12602 (and:SI (neg:SI
12603 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12604 (match_operand:SI 2 "reg_or_short_operand" "")))
12605 (match_operand:SI 3 "gpc_reg_operand" ""))
12606 (const_int 0)))
12607 (clobber (match_scratch:SI 4 ""))]
12608 "TARGET_32BIT && reload_completed"
12609 [(set (match_dup 4)
12610 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12611 (match_dup 3)))
12612 (set (match_dup 0)
12613 (compare:CC (match_dup 4)
12614 (const_int 0)))]
12615 "")
12617 (define_insn ""
12618 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12619 (compare:CC
12620 (and:SI (neg:SI
12621 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12622 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12623 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12624 (const_int 0)))
12625 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12626 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12627 "TARGET_32BIT"
12628 "@
12629 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
12630 #"
12631 [(set_attr "type" "compare")
12632 (set_attr "length" "12,16")])
12634 (define_split
12635 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12636 (compare:CC
12637 (and:SI (neg:SI
12638 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12639 (match_operand:SI 2 "reg_or_short_operand" "")))
12640 (match_operand:SI 3 "gpc_reg_operand" ""))
12641 (const_int 0)))
12642 (set (match_operand:SI 0 "gpc_reg_operand" "")
12643 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12644 "TARGET_32BIT && reload_completed"
12645 [(set (match_dup 0)
12646 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12647 (match_dup 3)))
12648 (set (match_dup 4)
12649 (compare:CC (match_dup 0)
12650 (const_int 0)))]
12651 "")
12653 (define_insn_and_split "*ltu<mode>"
12654 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12655 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12656 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12657 ""
12658 "#"
12659 ""
12660 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12661 (set (match_dup 0) (neg:P (match_dup 0)))]
12662 "")
12664 (define_insn_and_split "*ltu<mode>_compare"
12665 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12666 (compare:CC
12667 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12668 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12669 (const_int 0)))
12670 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12671 (ltu:P (match_dup 1) (match_dup 2)))]
12672 ""
12673 "#"
12674 ""
12675 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12676 (parallel [(set (match_dup 3)
12677 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12678 (set (match_dup 0) (neg:P (match_dup 0)))])]
12679 "")
12681 (define_insn_and_split "*plus_ltu<mode>"
12682 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12683 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12684 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12685 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12686 ""
12687 "#"
12688 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12689 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12690 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12691 "")
12693 (define_insn_and_split "*plus_ltu<mode>_1"
12694 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12695 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12696 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12697 (match_operand:P 3 "short_cint_operand" "I,I")))]
12698 ""
12699 "#"
12700 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12701 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12702 (parallel [(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))
12703 (clobber (reg:P CA_REGNO))])]
12704 "")
12706 (define_insn_and_split "*plus_ltu<mode>_compare"
12707 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12708 (compare:CC
12709 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12710 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12711 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12712 (const_int 0)))
12713 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12714 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12715 ""
12716 "#"
12717 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12718 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12719 (parallel [(set (match_dup 4)
12720 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12721 (const_int 0)))
12722 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12723 "")
12725 (define_insn "*neg_ltu<mode>"
12726 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12727 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12728 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12729 ""
12730 "@
12731 subfc %0,%2,%1\;subfe %0,%0,%0
12732 addic %0,%1,%n2\;subfe %0,%0,%0"
12733 [(set_attr "type" "two")
12734 (set_attr "length" "8")])
12736 (define_insn "*geu<mode>"
12737 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12738 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12739 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12740 ""
12741 "@
12742 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12743 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12744 [(set_attr "type" "three")
12745 (set_attr "length" "12")])
12747 (define_insn "*geu<mode>_compare"
12748 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12749 (compare:CC
12750 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12751 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12752 (const_int 0)))
12753 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12754 (geu:P (match_dup 1) (match_dup 2)))]
12755 ""
12756 "@
12757 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12758 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12759 #
12760 #"
12761 [(set_attr "type" "compare")
12762 (set_attr "length" "12,12,16,16")])
12764 (define_split
12765 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12766 (compare:CC
12767 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12768 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12769 (const_int 0)))
12770 (set (match_operand:P 0 "gpc_reg_operand" "")
12771 (geu:P (match_dup 1) (match_dup 2)))]
12772 "reload_completed"
12773 [(set (match_dup 0)
12774 (geu:P (match_dup 1) (match_dup 2)))
12775 (set (match_dup 3)
12776 (compare:CC (match_dup 0)
12777 (const_int 0)))]
12778 "")
12780 (define_insn "*plus_geu<mode>"
12781 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12782 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12783 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12784 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12785 ""
12786 "@
12787 subfc %0,%2,%1\;addze %0,%3
12788 addic %0,%1,%n2\;addze %0,%3"
12789 [(set_attr "type" "two")
12790 (set_attr "length" "8")])
12792 (define_insn ""
12793 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12794 (compare:CC
12795 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12796 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12797 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12798 (const_int 0)))
12799 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12800 "TARGET_32BIT"
12801 "@
12802 subfc %4,%2,%1\;addze. %4,%3
12803 addic %4,%1,%n2\;addze. %4,%3
12804 #
12805 #"
12806 [(set_attr "type" "compare")
12807 (set_attr "length" "8,8,12,12")])
12809 (define_split
12810 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12811 (compare:CC
12812 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12813 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12814 (match_operand:SI 3 "gpc_reg_operand" ""))
12815 (const_int 0)))
12816 (clobber (match_scratch:SI 4 ""))]
12817 "TARGET_32BIT && reload_completed"
12818 [(set (match_dup 4)
12819 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12820 (match_dup 3)))
12821 (set (match_dup 0)
12822 (compare:CC (match_dup 4)
12823 (const_int 0)))]
12824 "")
12826 (define_insn ""
12827 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12828 (compare:CC
12829 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12830 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12831 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12832 (const_int 0)))
12833 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12834 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12835 "TARGET_32BIT"
12836 "@
12837 subfc %0,%2,%1\;addze. %0,%3
12838 addic %0,%1,%n2\;addze. %0,%3
12839 #
12840 #"
12841 [(set_attr "type" "compare")
12842 (set_attr "length" "8,8,12,12")])
12844 (define_split
12845 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12846 (compare:CC
12847 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12848 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12849 (match_operand:SI 3 "gpc_reg_operand" ""))
12850 (const_int 0)))
12851 (set (match_operand:SI 0 "gpc_reg_operand" "")
12852 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12853 "TARGET_32BIT && reload_completed"
12854 [(set (match_dup 0)
12855 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12856 (set (match_dup 4)
12857 (compare:CC (match_dup 0)
12858 (const_int 0)))]
12859 "")
12861 (define_insn "*neg_geu<mode>"
12862 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12863 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12864 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12865 ""
12866 "@
12867 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
12868 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
12869 [(set_attr "type" "three")
12870 (set_attr "length" "12")])
12872 (define_insn "*and_neg_geu<mode>"
12873 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12874 (and:P (neg:P
12875 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12876 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12877 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12878 ""
12879 "@
12880 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
12881 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
12882 [(set_attr "type" "three")
12883 (set_attr "length" "12")])
12885 (define_insn ""
12886 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12887 (compare:CC
12888 (and:SI (neg:SI
12889 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12890 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12891 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12892 (const_int 0)))
12893 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12894 "TARGET_32BIT"
12895 "@
12896 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
12897 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
12898 #
12899 #"
12900 [(set_attr "type" "compare")
12901 (set_attr "length" "12,12,16,16")])
12903 (define_split
12904 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12905 (compare:CC
12906 (and:SI (neg:SI
12907 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12908 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12909 (match_operand:SI 3 "gpc_reg_operand" ""))
12910 (const_int 0)))
12911 (clobber (match_scratch:SI 4 ""))]
12912 "TARGET_32BIT && reload_completed"
12913 [(set (match_dup 4)
12914 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12915 (match_dup 3)))
12916 (set (match_dup 0)
12917 (compare:CC (match_dup 4)
12918 (const_int 0)))]
12919 "")
12921 (define_insn ""
12922 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12923 (compare:CC
12924 (and:SI (neg:SI
12925 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12926 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12927 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12928 (const_int 0)))
12929 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12930 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12931 "TARGET_32BIT"
12932 "@
12933 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
12934 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
12935 #
12936 #"
12937 [(set_attr "type" "compare")
12938 (set_attr "length" "12,12,16,16")])
12940 (define_split
12941 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12942 (compare:CC
12943 (and:SI (neg:SI
12944 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12945 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12946 (match_operand:SI 3 "gpc_reg_operand" ""))
12947 (const_int 0)))
12948 (set (match_operand:SI 0 "gpc_reg_operand" "")
12949 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12950 "TARGET_32BIT && reload_completed"
12951 [(set (match_dup 0)
12952 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12953 (set (match_dup 4)
12954 (compare:CC (match_dup 0)
12955 (const_int 0)))]
12956 "")
12958 (define_insn "*plus_gt0<mode>"
12959 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12960 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12961 (const_int 0))
12962 (match_operand:P 2 "gpc_reg_operand" "r")))]
12963 ""
12964 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12965 [(set_attr "type" "three")
12966 (set_attr "length" "12")])
12968 (define_insn ""
12969 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12970 (compare:CC
12971 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12972 (const_int 0))
12973 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12974 (const_int 0)))
12975 (clobber (match_scratch:SI 3 "=&r,&r"))]
12976 "TARGET_32BIT"
12977 "@
12978 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12979 #"
12980 [(set_attr "type" "compare")
12981 (set_attr "length" "12,16")])
12983 (define_split
12984 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12985 (compare:CC
12986 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12987 (const_int 0))
12988 (match_operand:SI 2 "gpc_reg_operand" ""))
12989 (const_int 0)))
12990 (clobber (match_scratch:SI 3 ""))]
12991 "TARGET_32BIT && reload_completed"
12992 [(set (match_dup 3)
12993 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12994 (match_dup 2)))
12995 (set (match_dup 0)
12996 (compare:CC (match_dup 3)
12997 (const_int 0)))]
12998 "")
13000 (define_insn ""
13001 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13002 (compare:CC
13003 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13004 (const_int 0))
13005 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13006 (const_int 0)))
13007 (clobber (match_scratch:DI 3 "=&r,&r"))]
13008 "TARGET_64BIT"
13009 "@
13010 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13011 #"
13012 [(set_attr "type" "compare")
13013 (set_attr "length" "12,16")])
13015 (define_split
13016 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13017 (compare:CC
13018 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13019 (const_int 0))
13020 (match_operand:DI 2 "gpc_reg_operand" ""))
13021 (const_int 0)))
13022 (clobber (match_scratch:DI 3 ""))]
13023 "TARGET_64BIT && reload_completed"
13024 [(set (match_dup 3)
13025 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13026 (match_dup 2)))
13027 (set (match_dup 0)
13028 (compare:CC (match_dup 3)
13029 (const_int 0)))]
13030 "")
13032 (define_insn ""
13033 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13034 (compare:CC
13035 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13036 (const_int 0))
13037 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13038 (const_int 0)))
13039 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13040 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13041 "TARGET_32BIT"
13042 "@
13043 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13044 #"
13045 [(set_attr "type" "compare")
13046 (set_attr "length" "12,16")])
13048 (define_split
13049 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13050 (compare:CC
13051 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13052 (const_int 0))
13053 (match_operand:SI 2 "gpc_reg_operand" ""))
13054 (const_int 0)))
13055 (set (match_operand:SI 0 "gpc_reg_operand" "")
13056 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13057 "TARGET_32BIT && reload_completed"
13058 [(set (match_dup 0)
13059 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13060 (set (match_dup 3)
13061 (compare:CC (match_dup 0)
13062 (const_int 0)))]
13063 "")
13065 (define_insn ""
13066 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13067 (compare:CC
13068 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13069 (const_int 0))
13070 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13071 (const_int 0)))
13072 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13073 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13074 "TARGET_64BIT"
13075 "@
13076 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13077 #"
13078 [(set_attr "type" "compare")
13079 (set_attr "length" "12,16")])
13081 (define_split
13082 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13083 (compare:CC
13084 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13085 (const_int 0))
13086 (match_operand:DI 2 "gpc_reg_operand" ""))
13087 (const_int 0)))
13088 (set (match_operand:DI 0 "gpc_reg_operand" "")
13089 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13090 "TARGET_64BIT && reload_completed"
13091 [(set (match_dup 0)
13092 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13093 (set (match_dup 3)
13094 (compare:CC (match_dup 0)
13095 (const_int 0)))]
13096 "")
13098 (define_insn_and_split "*gtu<mode>"
13099 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13100 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13101 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13102 ""
13103 "#"
13104 ""
13105 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13106 (set (match_dup 0) (neg:P (match_dup 0)))]
13107 "")
13109 (define_insn_and_split "*gtu<mode>_compare"
13110 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13111 (compare:CC
13112 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13113 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13114 (const_int 0)))
13115 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13116 (gtu:P (match_dup 1) (match_dup 2)))]
13117 ""
13118 "#"
13119 ""
13120 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13121 (parallel [(set (match_dup 3)
13122 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13123 (set (match_dup 0) (neg:P (match_dup 0)))])]
13124 "")
13126 (define_insn_and_split "*plus_gtu<mode>"
13127 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13128 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13129 (match_operand:P 2 "reg_or_short_operand" "rI"))
13130 (match_operand:P 3 "gpc_reg_operand" "r")))]
13131 ""
13132 "#"
13133 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13134 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13135 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13136 "")
13138 (define_insn_and_split "*plus_gtu<mode>_1"
13139 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13140 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13141 (match_operand:P 2 "reg_or_short_operand" "rI"))
13142 (match_operand:P 3 "short_cint_operand" "I")))]
13143 ""
13144 "#"
13145 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13146 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13147 (parallel [(set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))
13148 (clobber (reg:P CA_REGNO))])]
13149 "")
13151 (define_insn_and_split "*plus_gtu<mode>_compare"
13152 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13153 (compare:CC
13154 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13155 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13156 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13157 (const_int 0)))
13158 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13159 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13160 ""
13161 "#"
13162 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13163 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13164 (parallel [(set (match_dup 4)
13165 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13166 (const_int 0)))
13167 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13168 "")
13170 (define_insn "*neg_gtu<mode>"
13171 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13172 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13173 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13174 ""
13175 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13176 [(set_attr "type" "two")
13177 (set_attr "length" "8")])
13179 \f
13180 ;; Define both directions of branch and return. If we need a reload
13181 ;; register, we'd rather use CR0 since it is much easier to copy a
13182 ;; register CC value to there.
13184 (define_insn ""
13185 [(set (pc)
13186 (if_then_else (match_operator 1 "branch_comparison_operator"
13187 [(match_operand 2
13188 "cc_reg_operand" "y")
13189 (const_int 0)])
13190 (label_ref (match_operand 0 "" ""))
13191 (pc)))]
13192 ""
13193 "*
13194 {
13195 return output_cbranch (operands[1], \"%l0\", 0, insn);
13196 }"
13197 [(set_attr "type" "branch")])
13199 (define_insn ""
13200 [(set (pc)
13201 (if_then_else (match_operator 0 "branch_comparison_operator"
13202 [(match_operand 1
13203 "cc_reg_operand" "y")
13204 (const_int 0)])
13205 (any_return)
13206 (pc)))]
13207 "<return_pred>"
13208 "*
13209 {
13210 return output_cbranch (operands[0], NULL, 0, insn);
13211 }"
13212 [(set_attr "type" "jmpreg")
13213 (set_attr "length" "4")])
13215 (define_insn ""
13216 [(set (pc)
13217 (if_then_else (match_operator 1 "branch_comparison_operator"
13218 [(match_operand 2
13219 "cc_reg_operand" "y")
13220 (const_int 0)])
13221 (pc)
13222 (label_ref (match_operand 0 "" ""))))]
13223 ""
13224 "*
13225 {
13226 return output_cbranch (operands[1], \"%l0\", 1, insn);
13227 }"
13228 [(set_attr "type" "branch")])
13230 (define_insn ""
13231 [(set (pc)
13232 (if_then_else (match_operator 0 "branch_comparison_operator"
13233 [(match_operand 1
13234 "cc_reg_operand" "y")
13235 (const_int 0)])
13236 (pc)
13237 (any_return)))]
13238 "<return_pred>"
13239 "*
13240 {
13241 return output_cbranch (operands[0], NULL, 1, insn);
13242 }"
13243 [(set_attr "type" "jmpreg")
13244 (set_attr "length" "4")])
13246 ;; Logic on condition register values.
13248 ; This pattern matches things like
13249 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13250 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13251 ; (const_int 1)))
13252 ; which are generated by the branch logic.
13253 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13255 (define_insn "*cceq_ior_compare"
13256 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13257 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13258 [(match_operator:SI 2
13259 "branch_positive_comparison_operator"
13260 [(match_operand 3
13261 "cc_reg_operand" "y,y")
13262 (const_int 0)])
13263 (match_operator:SI 4
13264 "branch_positive_comparison_operator"
13265 [(match_operand 5
13266 "cc_reg_operand" "0,y")
13267 (const_int 0)])])
13268 (const_int 1)))]
13269 ""
13270 "cr%q1 %E0,%j2,%j4"
13271 [(set_attr "type" "cr_logical,delayed_cr")])
13273 ; Why is the constant -1 here, but 1 in the previous pattern?
13274 ; Because ~1 has all but the low bit set.
13275 (define_insn ""
13276 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13277 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13278 [(not:SI (match_operator:SI 2
13279 "branch_positive_comparison_operator"
13280 [(match_operand 3
13281 "cc_reg_operand" "y,y")
13282 (const_int 0)]))
13283 (match_operator:SI 4
13284 "branch_positive_comparison_operator"
13285 [(match_operand 5
13286 "cc_reg_operand" "0,y")
13287 (const_int 0)])])
13288 (const_int -1)))]
13289 ""
13290 "cr%q1 %E0,%j2,%j4"
13291 [(set_attr "type" "cr_logical,delayed_cr")])
13293 (define_insn "*cceq_rev_compare"
13294 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13295 (compare:CCEQ (match_operator:SI 1
13296 "branch_positive_comparison_operator"
13297 [(match_operand 2
13298 "cc_reg_operand" "0,y")
13299 (const_int 0)])
13300 (const_int 0)))]
13301 ""
13302 "crnot %E0,%j1"
13303 [(set_attr "type" "cr_logical,delayed_cr")])
13305 ;; If we are comparing the result of two comparisons, this can be done
13306 ;; using creqv or crxor.
13308 (define_insn_and_split ""
13309 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13310 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13311 [(match_operand 2 "cc_reg_operand" "y")
13312 (const_int 0)])
13313 (match_operator 3 "branch_comparison_operator"
13314 [(match_operand 4 "cc_reg_operand" "y")
13315 (const_int 0)])))]
13316 ""
13317 "#"
13318 ""
13319 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13320 (match_dup 5)))]
13321 "
13322 {
13323 int positive_1, positive_2;
13325 positive_1 = branch_positive_comparison_operator (operands[1],
13326 GET_MODE (operands[1]));
13327 positive_2 = branch_positive_comparison_operator (operands[3],
13328 GET_MODE (operands[3]));
13330 if (! positive_1)
13331 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13332 GET_CODE (operands[1])),
13333 SImode,
13334 operands[2], const0_rtx);
13335 else if (GET_MODE (operands[1]) != SImode)
13336 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13337 operands[2], const0_rtx);
13339 if (! positive_2)
13340 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13341 GET_CODE (operands[3])),
13342 SImode,
13343 operands[4], const0_rtx);
13344 else if (GET_MODE (operands[3]) != SImode)
13345 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13346 operands[4], const0_rtx);
13348 if (positive_1 == positive_2)
13349 {
13350 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13351 operands[5] = constm1_rtx;
13352 }
13353 else
13354 {
13355 operands[5] = const1_rtx;
13356 }
13357 }")
13359 ;; Unconditional branch and return.
13361 (define_insn "jump"
13362 [(set (pc)
13363 (label_ref (match_operand 0 "" "")))]
13364 ""
13365 "b %l0"
13366 [(set_attr "type" "branch")])
13368 (define_insn "<return_str>return"
13369 [(any_return)]
13370 "<return_pred>"
13371 "blr"
13372 [(set_attr "type" "jmpreg")])
13374 (define_expand "indirect_jump"
13375 [(set (pc) (match_operand 0 "register_operand" ""))])
13377 (define_insn "*indirect_jump<mode>"
13378 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13379 ""
13380 "@
13381 bctr
13382 blr"
13383 [(set_attr "type" "jmpreg")])
13385 ;; Table jump for switch statements:
13386 (define_expand "tablejump"
13387 [(use (match_operand 0 "" ""))
13388 (use (label_ref (match_operand 1 "" "")))]
13389 ""
13390 "
13391 {
13392 if (TARGET_32BIT)
13393 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13394 else
13395 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13396 DONE;
13397 }")
13399 (define_expand "tablejumpsi"
13400 [(set (match_dup 3)
13401 (plus:SI (match_operand:SI 0 "" "")
13402 (match_dup 2)))
13403 (parallel [(set (pc) (match_dup 3))
13404 (use (label_ref (match_operand 1 "" "")))])]
13405 "TARGET_32BIT"
13406 "
13407 { operands[0] = force_reg (SImode, operands[0]);
13408 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13409 operands[3] = gen_reg_rtx (SImode);
13410 }")
13412 (define_expand "tablejumpdi"
13413 [(set (match_dup 4)
13414 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13415 (set (match_dup 3)
13416 (plus:DI (match_dup 4)
13417 (match_dup 2)))
13418 (parallel [(set (pc) (match_dup 3))
13419 (use (label_ref (match_operand 1 "" "")))])]
13420 "TARGET_64BIT"
13421 "
13422 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13423 operands[3] = gen_reg_rtx (DImode);
13424 operands[4] = gen_reg_rtx (DImode);
13425 }")
13427 (define_insn "*tablejump<mode>_internal1"
13428 [(set (pc)
13429 (match_operand:P 0 "register_operand" "c,*l"))
13430 (use (label_ref (match_operand 1 "" "")))]
13431 ""
13432 "@
13433 bctr
13434 blr"
13435 [(set_attr "type" "jmpreg")])
13437 (define_insn "nop"
13438 [(const_int 0)]
13439 ""
13440 "nop")
13442 (define_insn "group_ending_nop"
13443 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13444 ""
13445 "*
13446 {
13447 if (rs6000_cpu_attr == CPU_POWER6)
13448 return \"ori 1,1,0\";
13449 return \"ori 2,2,0\";
13450 }")
13451 \f
13452 ;; Define the subtract-one-and-jump insns, starting with the template
13453 ;; so loop.c knows what to generate.
13455 (define_expand "doloop_end"
13456 [(use (match_operand 0 "" "")) ; loop pseudo
13457 (use (match_operand 1 "" ""))] ; label
13458 ""
13459 "
13460 {
13461 if (TARGET_64BIT)
13462 {
13463 if (GET_MODE (operands[0]) != DImode)
13464 FAIL;
13465 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
13466 }
13467 else
13468 {
13469 if (GET_MODE (operands[0]) != SImode)
13470 FAIL;
13471 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
13472 }
13473 DONE;
13474 }")
13476 (define_expand "ctr<mode>"
13477 [(parallel [(set (pc)
13478 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13479 (const_int 1))
13480 (label_ref (match_operand 1 "" ""))
13481 (pc)))
13482 (set (match_dup 0)
13483 (plus:P (match_dup 0)
13484 (const_int -1)))
13485 (clobber (match_scratch:CC 2 ""))
13486 (clobber (match_scratch:P 3 ""))])]
13487 ""
13488 "")
13490 ;; We need to be able to do this for any operand, including MEM, or we
13491 ;; will cause reload to blow up since we don't allow output reloads on
13492 ;; JUMP_INSNs.
13493 ;; For the length attribute to be calculated correctly, the
13494 ;; label MUST be operand 0.
13496 (define_insn "*ctr<mode>_internal1"
13497 [(set (pc)
13498 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13499 (const_int 1))
13500 (label_ref (match_operand 0 "" ""))
13501 (pc)))
13502 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13503 (plus:P (match_dup 1)
13504 (const_int -1)))
13505 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13506 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13507 ""
13508 "*
13509 {
13510 if (which_alternative != 0)
13511 return \"#\";
13512 else if (get_attr_length (insn) == 4)
13513 return \"bdnz %l0\";
13514 else
13515 return \"bdz $+8\;b %l0\";
13516 }"
13517 [(set_attr "type" "branch")
13518 (set_attr "length" "*,12,16,16")])
13520 (define_insn "*ctr<mode>_internal2"
13521 [(set (pc)
13522 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13523 (const_int 1))
13524 (pc)
13525 (label_ref (match_operand 0 "" ""))))
13526 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13527 (plus:P (match_dup 1)
13528 (const_int -1)))
13529 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13530 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13531 ""
13532 "*
13533 {
13534 if (which_alternative != 0)
13535 return \"#\";
13536 else if (get_attr_length (insn) == 4)
13537 return \"bdz %l0\";
13538 else
13539 return \"bdnz $+8\;b %l0\";
13540 }"
13541 [(set_attr "type" "branch")
13542 (set_attr "length" "*,12,16,16")])
13544 ;; Similar but use EQ
13546 (define_insn "*ctr<mode>_internal5"
13547 [(set (pc)
13548 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13549 (const_int 1))
13550 (label_ref (match_operand 0 "" ""))
13551 (pc)))
13552 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13553 (plus:P (match_dup 1)
13554 (const_int -1)))
13555 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13556 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13557 ""
13558 "*
13559 {
13560 if (which_alternative != 0)
13561 return \"#\";
13562 else if (get_attr_length (insn) == 4)
13563 return \"bdz %l0\";
13564 else
13565 return \"bdnz $+8\;b %l0\";
13566 }"
13567 [(set_attr "type" "branch")
13568 (set_attr "length" "*,12,16,16")])
13570 (define_insn "*ctr<mode>_internal6"
13571 [(set (pc)
13572 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13573 (const_int 1))
13574 (pc)
13575 (label_ref (match_operand 0 "" ""))))
13576 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13577 (plus:P (match_dup 1)
13578 (const_int -1)))
13579 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13580 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13581 ""
13582 "*
13583 {
13584 if (which_alternative != 0)
13585 return \"#\";
13586 else if (get_attr_length (insn) == 4)
13587 return \"bdnz %l0\";
13588 else
13589 return \"bdz $+8\;b %l0\";
13590 }"
13591 [(set_attr "type" "branch")
13592 (set_attr "length" "*,12,16,16")])
13594 ;; Now the splitters if we could not allocate the CTR register
13596 (define_split
13597 [(set (pc)
13598 (if_then_else (match_operator 2 "comparison_operator"
13599 [(match_operand:P 1 "gpc_reg_operand" "")
13600 (const_int 1)])
13601 (match_operand 5 "" "")
13602 (match_operand 6 "" "")))
13603 (set (match_operand:P 0 "gpc_reg_operand" "")
13604 (plus:P (match_dup 1) (const_int -1)))
13605 (clobber (match_scratch:CC 3 ""))
13606 (clobber (match_scratch:P 4 ""))]
13607 "reload_completed"
13608 [(parallel [(set (match_dup 3)
13609 (compare:CC (plus:P (match_dup 1)
13610 (const_int -1))
13611 (const_int 0)))
13612 (set (match_dup 0)
13613 (plus:P (match_dup 1)
13614 (const_int -1)))])
13615 (set (pc) (if_then_else (match_dup 7)
13616 (match_dup 5)
13617 (match_dup 6)))]
13618 "
13619 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13620 operands[3], const0_rtx); }")
13622 (define_split
13623 [(set (pc)
13624 (if_then_else (match_operator 2 "comparison_operator"
13625 [(match_operand:P 1 "gpc_reg_operand" "")
13626 (const_int 1)])
13627 (match_operand 5 "" "")
13628 (match_operand 6 "" "")))
13629 (set (match_operand:P 0 "nonimmediate_operand" "")
13630 (plus:P (match_dup 1) (const_int -1)))
13631 (clobber (match_scratch:CC 3 ""))
13632 (clobber (match_scratch:P 4 ""))]
13633 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13634 [(parallel [(set (match_dup 3)
13635 (compare:CC (plus:P (match_dup 1)
13636 (const_int -1))
13637 (const_int 0)))
13638 (set (match_dup 4)
13639 (plus:P (match_dup 1)
13640 (const_int -1)))])
13641 (set (match_dup 0)
13642 (match_dup 4))
13643 (set (pc) (if_then_else (match_dup 7)
13644 (match_dup 5)
13645 (match_dup 6)))]
13646 "
13647 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13648 operands[3], const0_rtx); }")
13649 \f
13650 (define_insn "trap"
13651 [(trap_if (const_int 1) (const_int 0))]
13652 ""
13653 "trap"
13654 [(set_attr "type" "trap")])
13656 (define_expand "ctrap<mode>4"
13657 [(trap_if (match_operator 0 "ordered_comparison_operator"
13658 [(match_operand:GPR 1 "register_operand")
13659 (match_operand:GPR 2 "reg_or_short_operand")])
13660 (match_operand 3 "zero_constant" ""))]
13661 ""
13662 "")
13664 (define_insn ""
13665 [(trap_if (match_operator 0 "ordered_comparison_operator"
13666 [(match_operand:GPR 1 "register_operand" "r")
13667 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13668 (const_int 0))]
13669 ""
13670 "t<wd>%V0%I2 %1,%2"
13671 [(set_attr "type" "trap")])
13672 \f
13673 ;; Insns related to generating the function prologue and epilogue.
13675 (define_expand "prologue"
13676 [(use (const_int 0))]
13677 ""
13678 {
13679 rs6000_emit_prologue ();
13680 if (!TARGET_SCHED_PROLOG)
13681 emit_insn (gen_blockage ());
13682 DONE;
13683 })
13685 (define_insn "*movesi_from_cr_one"
13686 [(match_parallel 0 "mfcr_operation"
13687 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13688 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13689 (match_operand 3 "immediate_operand" "n")]
13690 UNSPEC_MOVESI_FROM_CR))])]
13691 "TARGET_MFCRF"
13692 "*
13693 {
13694 int mask = 0;
13695 int i;
13696 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13697 {
13698 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13699 operands[4] = GEN_INT (mask);
13700 output_asm_insn (\"mfcr %1,%4\", operands);
13701 }
13702 return \"\";
13703 }"
13704 [(set_attr "type" "mfcrf")])
13706 (define_insn "movesi_from_cr"
13707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13708 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13709 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13710 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13711 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13712 UNSPEC_MOVESI_FROM_CR))]
13713 ""
13714 "mfcr %0"
13715 [(set_attr "type" "mfcr")])
13717 (define_insn "*crsave"
13718 [(match_parallel 0 "crsave_operation"
13719 [(set (match_operand:SI 1 "memory_operand" "=m")
13720 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13721 ""
13722 "stw %2,%1"
13723 [(set_attr "type" "store")])
13725 (define_insn "*stmw"
13726 [(match_parallel 0 "stmw_operation"
13727 [(set (match_operand:SI 1 "memory_operand" "=m")
13728 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13729 "TARGET_MULTIPLE"
13730 "stmw %2,%1"
13731 [(set_attr "type" "store")
13732 (set_attr "update" "yes")
13733 (set_attr "indexed" "yes")])
13735 ; The following comment applies to:
13736 ; save_gpregs_*
13737 ; save_fpregs_*
13738 ; restore_gpregs*
13739 ; return_and_restore_gpregs*
13740 ; return_and_restore_fpregs*
13741 ; return_and_restore_fpregs_aix*
13742 ;
13743 ; The out-of-line save / restore functions expects one input argument.
13744 ; Since those are not standard call_insn's, we must avoid using
13745 ; MATCH_OPERAND for that argument. That way the register rename
13746 ; optimization will not try to rename this register.
13747 ; Each pattern is repeated for each possible register number used in
13748 ; various ABIs (r11, r1, and for some functions r12)
13750 (define_insn "*save_gpregs_<mode>_r11"
13751 [(match_parallel 0 "any_parallel_operand"
13752 [(clobber (reg:P 65))
13753 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13754 (use (reg:P 11))
13755 (set (match_operand:P 2 "memory_operand" "=m")
13756 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13757 ""
13758 "bl %1"
13759 [(set_attr "type" "branch")
13760 (set_attr "length" "4")])
13762 (define_insn "*save_gpregs_<mode>_r12"
13763 [(match_parallel 0 "any_parallel_operand"
13764 [(clobber (reg:P 65))
13765 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13766 (use (reg:P 12))
13767 (set (match_operand:P 2 "memory_operand" "=m")
13768 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13769 ""
13770 "bl %1"
13771 [(set_attr "type" "branch")
13772 (set_attr "length" "4")])
13774 (define_insn "*save_gpregs_<mode>_r1"
13775 [(match_parallel 0 "any_parallel_operand"
13776 [(clobber (reg:P 65))
13777 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13778 (use (reg:P 1))
13779 (set (match_operand:P 2 "memory_operand" "=m")
13780 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13781 ""
13782 "bl %1"
13783 [(set_attr "type" "branch")
13784 (set_attr "length" "4")])
13786 (define_insn "*save_fpregs_<mode>_r11"
13787 [(match_parallel 0 "any_parallel_operand"
13788 [(clobber (reg:P 65))
13789 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13790 (use (reg:P 11))
13791 (set (match_operand:DF 2 "memory_operand" "=m")
13792 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13793 ""
13794 "bl %1"
13795 [(set_attr "type" "branch")
13796 (set_attr "length" "4")])
13798 (define_insn "*save_fpregs_<mode>_r12"
13799 [(match_parallel 0 "any_parallel_operand"
13800 [(clobber (reg:P 65))
13801 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13802 (use (reg:P 12))
13803 (set (match_operand:DF 2 "memory_operand" "=m")
13804 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13805 ""
13806 "bl %1"
13807 [(set_attr "type" "branch")
13808 (set_attr "length" "4")])
13810 (define_insn "*save_fpregs_<mode>_r1"
13811 [(match_parallel 0 "any_parallel_operand"
13812 [(clobber (reg:P 65))
13813 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13814 (use (reg:P 1))
13815 (set (match_operand:DF 2 "memory_operand" "=m")
13816 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13817 ""
13818 "bl %1"
13819 [(set_attr "type" "branch")
13820 (set_attr "length" "4")])
13822 ; This is to explain that changes to the stack pointer should
13823 ; not be moved over loads from or stores to stack memory.
13824 (define_insn "stack_tie"
13825 [(match_parallel 0 "tie_operand"
13826 [(set (mem:BLK (reg 1)) (const_int 0))])]
13827 ""
13828 ""
13829 [(set_attr "length" "0")])
13831 (define_expand "epilogue"
13832 [(use (const_int 0))]
13833 ""
13834 {
13835 if (!TARGET_SCHED_PROLOG)
13836 emit_insn (gen_blockage ());
13837 rs6000_emit_epilogue (FALSE);
13838 DONE;
13839 })
13841 ; On some processors, doing the mtcrf one CC register at a time is
13842 ; faster (like on the 604e). On others, doing them all at once is
13843 ; faster; for instance, on the 601 and 750.
13845 (define_expand "movsi_to_cr_one"
13846 [(set (match_operand:CC 0 "cc_reg_operand" "")
13847 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13848 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13849 ""
13850 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13852 (define_insn "*movsi_to_cr"
13853 [(match_parallel 0 "mtcrf_operation"
13854 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13855 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13856 (match_operand 3 "immediate_operand" "n")]
13857 UNSPEC_MOVESI_TO_CR))])]
13858 ""
13859 "*
13860 {
13861 int mask = 0;
13862 int i;
13863 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13864 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13865 operands[4] = GEN_INT (mask);
13866 return \"mtcrf %4,%2\";
13867 }"
13868 [(set_attr "type" "mtcr")])
13870 (define_insn "*mtcrfsi"
13871 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13872 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13873 (match_operand 2 "immediate_operand" "n")]
13874 UNSPEC_MOVESI_TO_CR))]
13875 "GET_CODE (operands[0]) == REG
13876 && CR_REGNO_P (REGNO (operands[0]))
13877 && GET_CODE (operands[2]) == CONST_INT
13878 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13879 "mtcrf %R0,%1"
13880 [(set_attr "type" "mtcr")])
13882 ; The load-multiple instructions have similar properties.
13883 ; Note that "load_multiple" is a name known to the machine-independent
13884 ; code that actually corresponds to the PowerPC load-string.
13886 (define_insn "*lmw"
13887 [(match_parallel 0 "lmw_operation"
13888 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13889 (match_operand:SI 2 "memory_operand" "m"))])]
13890 "TARGET_MULTIPLE"
13891 "lmw %1,%2"
13892 [(set_attr "type" "load")
13893 (set_attr "update" "yes")
13894 (set_attr "indexed" "yes")
13895 (set_attr "cell_micro" "always")])
13897 (define_insn "*return_internal_<mode>"
13898 [(simple_return)
13899 (use (match_operand:P 0 "register_operand" "lc"))]
13900 ""
13901 "b%T0"
13902 [(set_attr "type" "jmpreg")])
13904 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13905 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13907 ; The following comment applies to:
13908 ; save_gpregs_*
13909 ; save_fpregs_*
13910 ; restore_gpregs*
13911 ; return_and_restore_gpregs*
13912 ; return_and_restore_fpregs*
13913 ; return_and_restore_fpregs_aix*
13914 ;
13915 ; The out-of-line save / restore functions expects one input argument.
13916 ; Since those are not standard call_insn's, we must avoid using
13917 ; MATCH_OPERAND for that argument. That way the register rename
13918 ; optimization will not try to rename this register.
13919 ; Each pattern is repeated for each possible register number used in
13920 ; various ABIs (r11, r1, and for some functions r12)
13922 (define_insn "*restore_gpregs_<mode>_r11"
13923 [(match_parallel 0 "any_parallel_operand"
13924 [(clobber (match_operand:P 1 "register_operand" "=l"))
13925 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13926 (use (reg:P 11))
13927 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13928 (match_operand:P 4 "memory_operand" "m"))])]
13929 ""
13930 "bl %2"
13931 [(set_attr "type" "branch")
13932 (set_attr "length" "4")])
13934 (define_insn "*restore_gpregs_<mode>_r12"
13935 [(match_parallel 0 "any_parallel_operand"
13936 [(clobber (match_operand:P 1 "register_operand" "=l"))
13937 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13938 (use (reg:P 12))
13939 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13940 (match_operand:P 4 "memory_operand" "m"))])]
13941 ""
13942 "bl %2"
13943 [(set_attr "type" "branch")
13944 (set_attr "length" "4")])
13946 (define_insn "*restore_gpregs_<mode>_r1"
13947 [(match_parallel 0 "any_parallel_operand"
13948 [(clobber (match_operand:P 1 "register_operand" "=l"))
13949 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13950 (use (reg:P 1))
13951 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13952 (match_operand:P 4 "memory_operand" "m"))])]
13953 ""
13954 "bl %2"
13955 [(set_attr "type" "branch")
13956 (set_attr "length" "4")])
13958 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13959 [(match_parallel 0 "any_parallel_operand"
13960 [(return)
13961 (clobber (match_operand:P 1 "register_operand" "=l"))
13962 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13963 (use (reg:P 11))
13964 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13965 (match_operand:P 4 "memory_operand" "m"))])]
13966 ""
13967 "b %2"
13968 [(set_attr "type" "branch")
13969 (set_attr "length" "4")])
13971 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13972 [(match_parallel 0 "any_parallel_operand"
13973 [(return)
13974 (clobber (match_operand:P 1 "register_operand" "=l"))
13975 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13976 (use (reg:P 12))
13977 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13978 (match_operand:P 4 "memory_operand" "m"))])]
13979 ""
13980 "b %2"
13981 [(set_attr "type" "branch")
13982 (set_attr "length" "4")])
13984 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13985 [(match_parallel 0 "any_parallel_operand"
13986 [(return)
13987 (clobber (match_operand:P 1 "register_operand" "=l"))
13988 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13989 (use (reg:P 1))
13990 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13991 (match_operand:P 4 "memory_operand" "m"))])]
13992 ""
13993 "b %2"
13994 [(set_attr "type" "branch")
13995 (set_attr "length" "4")])
13997 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13998 [(match_parallel 0 "any_parallel_operand"
13999 [(return)
14000 (clobber (match_operand:P 1 "register_operand" "=l"))
14001 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14002 (use (reg:P 11))
14003 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14004 (match_operand:DF 4 "memory_operand" "m"))])]
14005 ""
14006 "b %2"
14007 [(set_attr "type" "branch")
14008 (set_attr "length" "4")])
14010 (define_insn "*return_and_restore_fpregs_<mode>_r12"
14011 [(match_parallel 0 "any_parallel_operand"
14012 [(return)
14013 (clobber (match_operand:P 1 "register_operand" "=l"))
14014 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14015 (use (reg:P 12))
14016 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14017 (match_operand:DF 4 "memory_operand" "m"))])]
14018 ""
14019 "b %2"
14020 [(set_attr "type" "branch")
14021 (set_attr "length" "4")])
14023 (define_insn "*return_and_restore_fpregs_<mode>_r1"
14024 [(match_parallel 0 "any_parallel_operand"
14025 [(return)
14026 (clobber (match_operand:P 1 "register_operand" "=l"))
14027 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14028 (use (reg:P 1))
14029 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14030 (match_operand:DF 4 "memory_operand" "m"))])]
14031 ""
14032 "b %2"
14033 [(set_attr "type" "branch")
14034 (set_attr "length" "4")])
14036 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
14037 [(match_parallel 0 "any_parallel_operand"
14038 [(return)
14039 (use (match_operand:P 1 "register_operand" "l"))
14040 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14041 (use (reg:P 11))
14042 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14043 (match_operand:DF 4 "memory_operand" "m"))])]
14044 ""
14045 "b %2"
14046 [(set_attr "type" "branch")
14047 (set_attr "length" "4")])
14049 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
14050 [(match_parallel 0 "any_parallel_operand"
14051 [(return)
14052 (use (match_operand:P 1 "register_operand" "l"))
14053 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14054 (use (reg:P 1))
14055 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14056 (match_operand:DF 4 "memory_operand" "m"))])]
14057 ""
14058 "b %2"
14059 [(set_attr "type" "branch")
14060 (set_attr "length" "4")])
14062 ; This is used in compiling the unwind routines.
14063 (define_expand "eh_return"
14064 [(use (match_operand 0 "general_operand" ""))]
14065 ""
14066 "
14067 {
14068 if (TARGET_32BIT)
14069 emit_insn (gen_eh_set_lr_si (operands[0]));
14070 else
14071 emit_insn (gen_eh_set_lr_di (operands[0]));
14072 DONE;
14073 }")
14075 ; We can't expand this before we know where the link register is stored.
14076 (define_insn "eh_set_lr_<mode>"
14077 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14078 UNSPECV_EH_RR)
14079 (clobber (match_scratch:P 1 "=&b"))]
14080 ""
14081 "#")
14083 (define_split
14084 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14085 (clobber (match_scratch 1 ""))]
14086 "reload_completed"
14087 [(const_int 0)]
14088 "
14089 {
14090 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14091 DONE;
14092 }")
14094 (define_insn "prefetch"
14095 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14096 (match_operand:SI 1 "const_int_operand" "n")
14097 (match_operand:SI 2 "const_int_operand" "n"))]
14098 ""
14099 "*
14100 {
14101 if (GET_CODE (operands[0]) == REG)
14102 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14103 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14104 }"
14105 [(set_attr "type" "load")])
14106 \f
14107 (define_insn "bpermd_<mode>"
14108 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14109 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14110 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14111 "TARGET_POPCNTD"
14112 "bpermd %0,%1,%2"
14113 [(set_attr "type" "popcnt")])
14115 \f
14116 ;; Builtin fma support. Handle
14117 ;; Note that the conditions for expansion are in the FMA_F iterator.
14119 (define_expand "fma<mode>4"
14120 [(set (match_operand:FMA_F 0 "register_operand" "")
14121 (fma:FMA_F
14122 (match_operand:FMA_F 1 "register_operand" "")
14123 (match_operand:FMA_F 2 "register_operand" "")
14124 (match_operand:FMA_F 3 "register_operand" "")))]
14125 ""
14126 "")
14128 (define_insn "*fma<mode>4_fpr"
14129 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14130 (fma:SFDF
14131 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
14132 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14133 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
14134 "TARGET_<MODE>_FPR"
14135 "@
14136 fmadd<Ftrad> %0,%1,%2,%3
14137 xsmadda<Fvsx> %x0,%x1,%x2
14138 xsmaddm<Fvsx> %x0,%x1,%x3"
14139 [(set_attr "type" "fp")
14140 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14142 ; Altivec only has fma and nfms.
14143 (define_expand "fms<mode>4"
14144 [(set (match_operand:FMA_F 0 "register_operand" "")
14145 (fma:FMA_F
14146 (match_operand:FMA_F 1 "register_operand" "")
14147 (match_operand:FMA_F 2 "register_operand" "")
14148 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14149 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14150 "")
14152 (define_insn "*fms<mode>4_fpr"
14153 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14154 (fma:SFDF
14155 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14156 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14157 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14158 "TARGET_<MODE>_FPR"
14159 "@
14160 fmsub<Ftrad> %0,%1,%2,%3
14161 xsmsuba<Fvsx> %x0,%x1,%x2
14162 xsmsubm<Fvsx> %x0,%x1,%x3"
14163 [(set_attr "type" "fp")
14164 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14166 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14167 (define_expand "fnma<mode>4"
14168 [(set (match_operand:FMA_F 0 "register_operand" "")
14169 (neg:FMA_F
14170 (fma:FMA_F
14171 (match_operand:FMA_F 1 "register_operand" "")
14172 (match_operand:FMA_F 2 "register_operand" "")
14173 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14174 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14175 "")
14177 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14178 (define_expand "fnms<mode>4"
14179 [(set (match_operand:FMA_F 0 "register_operand" "")
14180 (neg:FMA_F
14181 (fma:FMA_F
14182 (match_operand:FMA_F 1 "register_operand" "")
14183 (match_operand:FMA_F 2 "register_operand" "")
14184 (match_operand:FMA_F 3 "register_operand" ""))))]
14185 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14186 "")
14188 ; Not an official optab name, but used from builtins.
14189 (define_expand "nfma<mode>4"
14190 [(set (match_operand:FMA_F 0 "register_operand" "")
14191 (neg:FMA_F
14192 (fma:FMA_F
14193 (match_operand:FMA_F 1 "register_operand" "")
14194 (match_operand:FMA_F 2 "register_operand" "")
14195 (match_operand:FMA_F 3 "register_operand" ""))))]
14196 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14197 "")
14199 (define_insn "*nfma<mode>4_fpr"
14200 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14201 (neg:SFDF
14202 (fma:SFDF
14203 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14204 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14205 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14206 "TARGET_<MODE>_FPR"
14207 "@
14208 fnmadd<Ftrad> %0,%1,%2,%3
14209 xsnmadda<Fvsx> %x0,%x1,%x2
14210 xsnmaddm<Fvsx> %x0,%x1,%x3"
14211 [(set_attr "type" "fp")
14212 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14214 ; Not an official optab name, but used from builtins.
14215 (define_expand "nfms<mode>4"
14216 [(set (match_operand:FMA_F 0 "register_operand" "")
14217 (neg:FMA_F
14218 (fma:FMA_F
14219 (match_operand:FMA_F 1 "register_operand" "")
14220 (match_operand:FMA_F 2 "register_operand" "")
14221 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14222 ""
14223 "")
14225 (define_insn "*nfmssf4_fpr"
14226 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14227 (neg:SFDF
14228 (fma:SFDF
14229 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14230 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14231 (neg:SFDF
14232 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
14233 "TARGET_<MODE>_FPR"
14234 "@
14235 fnmsub<Ftrad> %0,%1,%2,%3
14236 xsnmsuba<Fvsx> %x0,%x1,%x2
14237 xsnmsubm<Fvsx> %x0,%x1,%x3"
14238 [(set_attr "type" "fp")
14239 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14241 \f
14242 (define_expand "rs6000_get_timebase"
14243 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
14244 ""
14245 {
14246 if (TARGET_POWERPC64)
14247 emit_insn (gen_rs6000_mftb_di (operands[0]));
14248 else
14249 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
14250 DONE;
14251 })
14253 (define_insn "rs6000_get_timebase_ppc32"
14254 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
14255 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
14256 (clobber (match_scratch:SI 1 "=r"))
14257 (clobber (match_scratch:CC 2 "=y"))]
14258 "!TARGET_POWERPC64"
14259 {
14260 if (WORDS_BIG_ENDIAN)
14261 if (TARGET_MFCRF)
14262 {
14263 return "mfspr %0,269\;"
14264 "mfspr %L0,268\;"
14265 "mfspr %1,269\;"
14266 "cmpw %2,%0,%1\;"
14267 "bne- %2,$-16";
14268 }
14269 else
14270 {
14271 return "mftbu %0\;"
14272 "mftb %L0\;"
14273 "mftbu %1\;"
14274 "cmpw %2,%0,%1\;"
14275 "bne- %2,$-16";
14276 }
14277 else
14278 if (TARGET_MFCRF)
14279 {
14280 return "mfspr %L0,269\;"
14281 "mfspr %0,268\;"
14282 "mfspr %1,269\;"
14283 "cmpw %2,%L0,%1\;"
14284 "bne- %2,$-16";
14285 }
14286 else
14287 {
14288 return "mftbu %L0\;"
14289 "mftb %0\;"
14290 "mftbu %1\;"
14291 "cmpw %2,%L0,%1\;"
14292 "bne- %2,$-16";
14293 }
14294 }
14295 [(set_attr "length" "20")])
14297 (define_insn "rs6000_mftb_<mode>"
14298 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
14299 (unspec_volatile:GPR [(const_int 0)] UNSPECV_MFTB))]
14300 ""
14301 {
14302 if (TARGET_MFCRF)
14303 return "mfspr %0,268";
14304 else
14305 return "mftb %0";
14306 })
14308 \f
14309 (define_insn "rs6000_mffs"
14310 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
14311 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
14312 "TARGET_HARD_FLOAT && TARGET_FPRS"
14313 "mffs %0")
14315 (define_insn "rs6000_mtfsf"
14316 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
14317 (match_operand:DF 1 "gpc_reg_operand" "d")]
14318 UNSPECV_MTFSF)]
14319 "TARGET_HARD_FLOAT && TARGET_FPRS"
14320 "mtfsf %0,%1")
14322 \f
14323 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
14324 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
14325 ;; register that is being loaded. The fused ops must be physically adjacent.
14327 ;; Find cases where the addis that feeds into a load instruction is either used
14328 ;; once or is the same as the target register, and replace it with the fusion
14329 ;; insn
14331 (define_peephole2
14332 [(set (match_operand:P 0 "base_reg_operand" "")
14333 (match_operand:P 1 "fusion_gpr_addis" ""))
14334 (set (match_operand:INT1 2 "base_reg_operand" "")
14335 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
14336 "TARGET_P8_FUSION
14337 && fusion_gpr_load_p (operands[0], operands[1], operands[2],
14338 operands[3])"
14339 [(const_int 0)]
14340 {
14341 expand_fusion_gpr_load (operands);
14342 DONE;
14343 })
14345 ;; Fusion insn, created by the define_peephole2 above (and eventually by
14346 ;; reload)
14348 (define_insn "fusion_gpr_load_<mode>"
14349 [(set (match_operand:INT1 0 "base_reg_operand" "=&b")
14350 (unspec:INT1 [(match_operand:INT1 1 "fusion_gpr_mem_combo" "")]
14351 UNSPEC_FUSION_GPR))]
14352 "TARGET_P8_FUSION"
14353 {
14354 return emit_fusion_gpr_load (operands[0], operands[1]);
14355 }
14356 [(set_attr "type" "load")
14357 (set_attr "length" "8")])
14359 \f
14360 ;; Miscellaneous ISA 2.06 (power7) instructions
14361 (define_insn "addg6s"
14362 [(set (match_operand:SI 0 "register_operand" "=r")
14363 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
14364 (match_operand:SI 2 "register_operand" "r")]
14365 UNSPEC_ADDG6S))]
14366 "TARGET_POPCNTD"
14367 "addg6s %0,%1,%2"
14368 [(set_attr "type" "integer")
14369 (set_attr "length" "4")])
14371 (define_insn "cdtbcd"
14372 [(set (match_operand:SI 0 "register_operand" "=r")
14373 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14374 UNSPEC_CDTBCD))]
14375 "TARGET_POPCNTD"
14376 "cdtbcd %0,%1"
14377 [(set_attr "type" "integer")
14378 (set_attr "length" "4")])
14380 (define_insn "cbcdtd"
14381 [(set (match_operand:SI 0 "register_operand" "=r")
14382 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14383 UNSPEC_CBCDTD))]
14384 "TARGET_POPCNTD"
14385 "cbcdtd %0,%1"
14386 [(set_attr "type" "integer")
14387 (set_attr "length" "4")])
14389 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
14390 UNSPEC_DIVEO
14391 UNSPEC_DIVEU
14392 UNSPEC_DIVEUO])
14394 (define_int_attr div_extend [(UNSPEC_DIVE "e")
14395 (UNSPEC_DIVEO "eo")
14396 (UNSPEC_DIVEU "eu")
14397 (UNSPEC_DIVEUO "euo")])
14399 (define_insn "div<div_extend>_<mode>"
14400 [(set (match_operand:GPR 0 "register_operand" "=r")
14401 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
14402 (match_operand:GPR 2 "register_operand" "r")]
14403 UNSPEC_DIV_EXTEND))]
14404 "TARGET_POPCNTD"
14405 "div<wd><div_extend> %0,%1,%2"
14406 [(set_attr "type" "div")
14407 (set_attr "size" "<bits>")])
14409 \f
14410 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
14412 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
14413 (define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
14415 (define_expand "unpack<mode>"
14416 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
14417 (unspec:<FP128_64>
14418 [(match_operand:FMOVE128 1 "register_operand" "")
14419 (match_operand:QI 2 "const_0_to_1_operand" "")]
14420 UNSPEC_UNPACK_128BIT))]
14421 ""
14422 "")
14424 (define_insn_and_split "unpack<mode>_dm"
14425 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
14426 (unspec:<FP128_64>
14427 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
14428 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
14429 UNSPEC_UNPACK_128BIT))]
14430 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
14431 "#"
14432 "&& reload_completed"
14433 [(set (match_dup 0) (match_dup 3))]
14434 {
14435 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14437 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14438 {
14439 emit_note (NOTE_INSN_DELETED);
14440 DONE;
14441 }
14443 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14444 }
14445 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
14446 (set_attr "length" "4")])
14448 (define_insn_and_split "unpack<mode>_nodm"
14449 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
14450 (unspec:<FP128_64>
14451 [(match_operand:FMOVE128 1 "register_operand" "d,d")
14452 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
14453 UNSPEC_UNPACK_128BIT))]
14454 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
14455 "#"
14456 "&& reload_completed"
14457 [(set (match_dup 0) (match_dup 3))]
14458 {
14459 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14461 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14462 {
14463 emit_note (NOTE_INSN_DELETED);
14464 DONE;
14465 }
14467 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14468 }
14469 [(set_attr "type" "fp,fpstore")
14470 (set_attr "length" "4")])
14472 (define_insn_and_split "pack<mode>"
14473 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
14474 (unspec:FMOVE128
14475 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
14476 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
14477 UNSPEC_PACK_128BIT))]
14478 ""
14479 "@
14480 fmr %L0,%2
14481 #"
14482 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
14483 [(set (match_dup 3) (match_dup 1))
14484 (set (match_dup 4) (match_dup 2))]
14485 {
14486 unsigned dest_hi = REGNO (operands[0]);
14487 unsigned dest_lo = dest_hi + 1;
14489 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
14490 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
14492 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
14493 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
14494 }
14495 [(set_attr "type" "fp,fp")
14496 (set_attr "length" "4,8")])
14498 (define_insn "unpackv1ti"
14499 [(set (match_operand:DI 0 "register_operand" "=d,d")
14500 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
14501 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
14502 UNSPEC_UNPACK_128BIT))]
14503 "TARGET_VSX"
14504 {
14505 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
14506 return ASM_COMMENT_START " xxpermdi to same register";
14508 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
14509 return "xxpermdi %x0,%x1,%x1,%3";
14510 }
14511 [(set_attr "type" "vecperm")
14512 (set_attr "length" "4")])
14514 (define_insn "packv1ti"
14515 [(set (match_operand:V1TI 0 "register_operand" "=wa")
14516 (unspec:V1TI
14517 [(match_operand:DI 1 "register_operand" "d")
14518 (match_operand:DI 2 "register_operand" "d")]
14519 UNSPEC_PACK_128BIT))]
14520 "TARGET_VSX"
14521 "xxpermdi %x0,%x1,%x2,0"
14522 [(set_attr "type" "vecperm")
14523 (set_attr "length" "4")])
14525 \f
14527 (include "sync.md")
14528 (include "vector.md")
14529 (include "vsx.md")
14530 (include "altivec.md")
14531 (include "spe.md")
14532 (include "dfp.md")
14533 (include "paired.md")
14534 (include "crypto.md")
14535 (include "htm.md")