1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx
*reg_last_reload_reg
;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload
;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload
;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx
*reg_equiv_constant
;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx
*reg_equiv_invariant
;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx
*reg_equiv_memory_loc
;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx
,gc
) *reg_equiv_memory_loc_vec
;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx
*reg_equiv_address
;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx
*reg_equiv_alt_mem_list
;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width
;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size
;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber
;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid
;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead
;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
163 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs
;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global
;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET
*pseudo_previous_regs
;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET
*pseudo_forbidden_regs
;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs
;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg
;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels
;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok
;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok
;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos
;
261 /* Used for communication between order_regs_for_reload and count_pseudo.
262 Used to avoid counting one pseudo twice. */
263 static regset_head pseudos_counted
;
265 /* First uid used by insns created by reload in this function.
266 Used in find_equiv_reg. */
267 int reload_first_uid
;
269 /* Flag set by local-alloc or global-alloc if anything is live in
270 a call-clobbered reg across calls. */
271 int caller_save_needed
;
273 /* Set to 1 while reload_as_needed is operating.
274 Required by some machines to handle any generated moves differently. */
275 int reload_in_progress
= 0;
277 /* These arrays record the insn_code of insns that may be needed to
278 perform input and output reloads of special objects. They provide a
279 place to pass a scratch register. */
280 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
281 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
283 /* This obstack is used for allocation of rtl during register elimination.
284 The allocated storage can be freed once find_reloads has processed the
286 static struct obstack reload_obstack
;
288 /* Points to the beginning of the reload_obstack. All insn_chain structures
289 are allocated first. */
290 static char *reload_startobj
;
292 /* The point after all insn_chain structures. Used to quickly deallocate
293 memory allocated in copy_reloads during calculate_needs_all_insns. */
294 static char *reload_firstobj
;
296 /* This points before all local rtl generated by register elimination.
297 Used to quickly free all memory after processing one insn. */
298 static char *reload_insn_firstobj
;
300 /* List of insn_chain instructions, one for every insn that reload needs to
302 struct insn_chain
*reload_insn_chain
;
304 /* List of all insns needing reloads. */
305 static struct insn_chain
*insns_need_reload
;
307 /* This structure is used to record information about register eliminations.
308 Each array entry describes one possible way of eliminating a register
309 in favor of another. If there is more than one way of eliminating a
310 particular register, the most preferred should be specified first. */
314 int from
; /* Register number to be eliminated. */
315 int to
; /* Register number used as replacement. */
316 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
317 int can_eliminate
; /* Nonzero if this elimination can be done. */
318 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
319 insns made by reload. */
320 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
321 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
322 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
323 rtx from_rtx
; /* REG rtx for the register to be eliminated.
324 We cannot simply compare the number since
325 we might then spuriously replace a hard
326 register corresponding to a pseudo
327 assigned to the reg to be eliminated. */
328 rtx to_rtx
; /* REG rtx for the replacement. */
331 static struct elim_table
*reg_eliminate
= 0;
333 /* This is an intermediate structure to initialize the table. It has
334 exactly the members provided by ELIMINABLE_REGS. */
335 static const struct elim_table_1
339 } reg_eliminate_1
[] =
341 /* If a set of eliminable registers was specified, define the table from it.
342 Otherwise, default to the normal case of the frame pointer being
343 replaced by the stack pointer. */
345 #ifdef ELIMINABLE_REGS
348 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
351 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
353 /* Record the number of pending eliminations that have an offset not equal
354 to their initial offset. If nonzero, we use a new copy of each
355 replacement result in any insns encountered. */
356 int num_not_at_initial_offset
;
358 /* Count the number of registers that we may be able to eliminate. */
359 static int num_eliminable
;
360 /* And the number of registers that are equivalent to a constant that
361 can be eliminated to frame_pointer / arg_pointer + constant. */
362 static int num_eliminable_invariants
;
364 /* For each label, we record the offset of each elimination. If we reach
365 a label by more than one path and an offset differs, we cannot do the
366 elimination. This information is indexed by the difference of the
367 number of the label and the first label number. We can't offset the
368 pointer itself as this can cause problems on machines with segmented
369 memory. The first table is an array of flags that records whether we
370 have yet encountered a label and the second table is an array of arrays,
371 one entry in the latter array for each elimination. */
373 static int first_label_num
;
374 static char *offsets_known_at
;
375 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
377 /* Number of labels in the current function. */
379 static int num_labels
;
381 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
382 static void maybe_fix_stack_asms (void);
383 static void copy_reloads (struct insn_chain
*);
384 static void calculate_needs_all_insns (int);
385 static int find_reg (struct insn_chain
*, int);
386 static void find_reload_regs (struct insn_chain
*);
387 static void select_reload_regs (void);
388 static void delete_caller_save_insns (void);
390 static void spill_failure (rtx
, enum reg_class
);
391 static void count_spilled_pseudo (int, int, int);
392 static void delete_dead_insn (rtx
);
393 static void alter_reg (int, int, bool);
394 static void set_label_offsets (rtx
, rtx
, int);
395 static void check_eliminable_occurrences (rtx
);
396 static void elimination_effects (rtx
, enum machine_mode
);
397 static int eliminate_regs_in_insn (rtx
, int);
398 static void update_eliminable_offsets (void);
399 static void mark_not_eliminable (rtx
, rtx
, void *);
400 static void set_initial_elim_offsets (void);
401 static bool verify_initial_elim_offsets (void);
402 static void set_initial_label_offsets (void);
403 static void set_offsets_for_label (rtx
);
404 static void init_elim_table (void);
405 static void update_eliminables (HARD_REG_SET
*);
406 static void spill_hard_reg (unsigned int, int);
407 static int finish_spills (int);
408 static void scan_paradoxical_subregs (rtx
);
409 static void count_pseudo (int);
410 static void order_regs_for_reload (struct insn_chain
*);
411 static void reload_as_needed (int);
412 static void forget_old_reloads_1 (rtx
, rtx
, void *);
413 static void forget_marked_reloads (regset
);
414 static int reload_reg_class_lower (const void *, const void *);
415 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
417 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
419 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
420 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
422 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
424 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type
);
425 static int allocate_reload_reg (struct insn_chain
*, int, int);
426 static int conflicts_with_override (rtx
);
427 static void failed_reload (rtx
, int);
428 static int set_reload_reg (int, int);
429 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
430 static void choose_reload_regs (struct insn_chain
*);
431 static void merge_assigned_reloads (rtx
);
432 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
434 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
436 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
437 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
438 static bool inherit_piecemeal_p (int, int);
439 static void emit_reload_insns (struct insn_chain
*);
440 static void delete_output_reload (rtx
, int, int);
441 static void delete_address_reloads (rtx
, rtx
);
442 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
443 static rtx
inc_for_reload (rtx
, rtx
, rtx
, int);
445 static void add_auto_inc_notes (rtx
, rtx
);
447 static void copy_eh_notes (rtx
, rtx
);
448 static int reloads_conflict (int, int);
449 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
450 static rtx
emit_insn_if_valid_for_reload (rtx
);
452 /* Initialize the reload pass once per compilation. */
459 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
460 Set spill_indirect_levels to the number of levels such addressing is
461 permitted, zero if it is not permitted at all. */
464 = gen_rtx_MEM (Pmode
,
467 LAST_VIRTUAL_REGISTER
+ 1),
469 spill_indirect_levels
= 0;
471 while (memory_address_p (QImode
, tem
))
473 spill_indirect_levels
++;
474 tem
= gen_rtx_MEM (Pmode
, tem
);
477 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
479 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
480 indirect_symref_ok
= memory_address_p (QImode
, tem
);
482 /* See if reg+reg is a valid (and offsettable) address. */
484 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
486 tem
= gen_rtx_PLUS (Pmode
,
487 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
488 gen_rtx_REG (Pmode
, i
));
490 /* This way, we make sure that reg+reg is an offsettable address. */
491 tem
= plus_constant (tem
, 4);
493 if (memory_address_p (QImode
, tem
))
495 double_reg_address_ok
= 1;
500 /* Initialize obstack for our rtl allocation. */
501 gcc_obstack_init (&reload_obstack
);
502 reload_startobj
= obstack_alloc (&reload_obstack
, 0);
504 INIT_REG_SET (&spilled_pseudos
);
505 INIT_REG_SET (&pseudos_counted
);
508 /* List of insn chains that are currently unused. */
509 static struct insn_chain
*unused_insn_chains
= 0;
511 /* Allocate an empty insn_chain structure. */
513 new_insn_chain (void)
515 struct insn_chain
*c
;
517 if (unused_insn_chains
== 0)
519 c
= obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
520 INIT_REG_SET (&c
->live_throughout
);
521 INIT_REG_SET (&c
->dead_or_set
);
525 c
= unused_insn_chains
;
526 unused_insn_chains
= c
->next
;
528 c
->is_caller_save_insn
= 0;
529 c
->need_operand_change
= 0;
535 /* Small utility function to set all regs in hard reg set TO which are
536 allocated to pseudos in regset FROM. */
539 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
542 reg_set_iterator rsi
;
544 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
546 int r
= reg_renumber
[regno
];
551 /* reload_combine uses the information from
552 BASIC_BLOCK->global_live_at_start, which might still
553 contain registers that have not actually been allocated
554 since they have an equivalence. */
555 gcc_assert (reload_completed
);
559 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (regno
)];
561 SET_HARD_REG_BIT (*to
, r
+ nregs
);
566 /* Replace all pseudos found in LOC with their corresponding
570 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
583 unsigned int regno
= REGNO (x
);
585 if (regno
< FIRST_PSEUDO_REGISTER
)
588 x
= eliminate_regs (x
, mem_mode
, usage
);
592 replace_pseudos_in (loc
, mem_mode
, usage
);
596 if (reg_equiv_constant
[regno
])
597 *loc
= reg_equiv_constant
[regno
];
598 else if (reg_equiv_mem
[regno
])
599 *loc
= reg_equiv_mem
[regno
];
600 else if (reg_equiv_address
[regno
])
601 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
604 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
605 || REGNO (regno_reg_rtx
[regno
]) != regno
);
606 *loc
= regno_reg_rtx
[regno
];
611 else if (code
== MEM
)
613 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
617 /* Process each of our operands recursively. */
618 fmt
= GET_RTX_FORMAT (code
);
619 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
621 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
622 else if (*fmt
== 'E')
623 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
624 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
628 /* Global variables used by reload and its subroutines. */
630 /* Set during calculate_needs if an insn needs register elimination. */
631 static int something_needs_elimination
;
632 /* Set during calculate_needs if an insn needs an operand changed. */
633 static int something_needs_operands_changed
;
635 /* Nonzero means we couldn't get enough spill regs. */
638 /* The function is used to sort pseudos according their usage
639 frequencies (putting most frequently ones first). */
641 pseudo_reg_compare (const void *v1p
, const void *v2p
)
643 int regno1
= *(int *) v1p
;
644 int regno2
= *(int *) v2p
;
647 if ((diff
= REG_FREQ (regno2
) - REG_FREQ (regno1
)) != 0)
649 return regno1
- regno2
;
652 /* Main entry point for the reload pass.
654 FIRST is the first insn of the function being compiled.
656 GLOBAL nonzero means we were called from global_alloc
657 and should attempt to reallocate any pseudoregs that we
658 displace from hard regs we will use for reloads.
659 If GLOBAL is zero, we do not have enough information to do that,
660 so any pseudo reg that is spilled must go to the stack.
662 Return value is nonzero if reload failed
663 and we must not do any more for this function. */
666 reload (rtx first
, int global
)
670 struct elim_table
*ep
;
673 /* Make sure even insns with volatile mem refs are recognizable. */
678 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
680 /* Make sure that the last insn in the chain
681 is not something that needs reloading. */
682 emit_note (NOTE_INSN_DELETED
);
684 /* Enable find_equiv_reg to distinguish insns made by reload. */
685 reload_first_uid
= get_max_uid ();
687 #ifdef SECONDARY_MEMORY_NEEDED
688 /* Initialize the secondary memory table. */
689 clear_secondary_mem ();
692 /* We don't have a stack slot for any spill reg yet. */
693 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
694 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
696 /* Initialize the save area information for caller-save, in case some
700 /* Compute which hard registers are now in use
701 as homes for pseudo registers.
702 This is done here rather than (eg) in global_alloc
703 because this point is reached even if not optimizing. */
704 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
707 /* A function that receives a nonlocal goto must save all call-saved
709 if (current_function_has_nonlocal_label
)
710 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
711 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
712 regs_ever_live
[i
] = 1;
714 /* Find all the pseudo registers that didn't get hard regs
715 but do have known equivalent constants or memory slots.
716 These include parameters (known equivalent to parameter slots)
717 and cse'd or loop-moved constant memory addresses.
719 Record constant equivalents in reg_equiv_constant
720 so they will be substituted by find_reloads.
721 Record memory equivalents in reg_mem_equiv so they can
722 be substituted eventually by altering the REG-rtx's. */
724 reg_equiv_constant
= XCNEWVEC (rtx
, max_regno
);
725 reg_equiv_invariant
= XCNEWVEC (rtx
, max_regno
);
726 reg_equiv_mem
= XCNEWVEC (rtx
, max_regno
);
727 reg_equiv_alt_mem_list
= XCNEWVEC (rtx
, max_regno
);
728 reg_equiv_address
= XCNEWVEC (rtx
, max_regno
);
729 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
730 reg_old_renumber
= XCNEWVEC (short, max_regno
);
731 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
732 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
733 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
735 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
737 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
738 to. Also find all paradoxical subregs and find largest such for
741 num_eliminable_invariants
= 0;
742 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
744 rtx set
= single_set (insn
);
746 /* We may introduce USEs that we want to remove at the end, so
747 we'll mark them with QImode. Make sure there are no
748 previously-marked insns left by say regmove. */
749 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
750 && GET_MODE (insn
) != VOIDmode
)
751 PUT_MODE (insn
, VOIDmode
);
754 scan_paradoxical_subregs (PATTERN (insn
));
756 if (set
!= 0 && REG_P (SET_DEST (set
)))
758 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
764 i
= REGNO (SET_DEST (set
));
767 if (i
<= LAST_VIRTUAL_REGISTER
)
770 if (! function_invariant_p (x
)
772 /* A function invariant is often CONSTANT_P but may
773 include a register. We promise to only pass
774 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
776 && LEGITIMATE_PIC_OPERAND_P (x
)))
778 /* It can happen that a REG_EQUIV note contains a MEM
779 that is not a legitimate memory operand. As later
780 stages of reload assume that all addresses found
781 in the reg_equiv_* arrays were originally legitimate,
782 we ignore such REG_EQUIV notes. */
783 if (memory_operand (x
, VOIDmode
))
785 /* Always unshare the equivalence, so we can
786 substitute into this insn without touching the
788 reg_equiv_memory_loc
[i
] = copy_rtx (x
);
790 else if (function_invariant_p (x
))
792 if (GET_CODE (x
) == PLUS
)
794 /* This is PLUS of frame pointer and a constant,
795 and might be shared. Unshare it. */
796 reg_equiv_invariant
[i
] = copy_rtx (x
);
797 num_eliminable_invariants
++;
799 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
801 reg_equiv_invariant
[i
] = x
;
802 num_eliminable_invariants
++;
804 else if (LEGITIMATE_CONSTANT_P (x
))
805 reg_equiv_constant
[i
] = x
;
808 reg_equiv_memory_loc
[i
]
809 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
810 if (! reg_equiv_memory_loc
[i
])
811 reg_equiv_init
[i
] = NULL_RTX
;
816 reg_equiv_init
[i
] = NULL_RTX
;
821 reg_equiv_init
[i
] = NULL_RTX
;
826 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
827 if (reg_equiv_init
[i
])
829 fprintf (dump_file
, "init_insns for %u: ", i
);
830 print_inline_rtx (dump_file
, reg_equiv_init
[i
], 20);
831 fprintf (dump_file
, "\n");
836 first_label_num
= get_first_label_num ();
837 num_labels
= max_label_num () - first_label_num
;
839 /* Allocate the tables used to store offset information at labels. */
840 /* We used to use alloca here, but the size of what it would try to
841 allocate would occasionally cause it to exceed the stack limit and
842 cause a core dump. */
843 offsets_known_at
= XNEWVEC (char, num_labels
);
844 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
849 /* Alter each pseudo-reg rtx to contain its hard reg number.
850 Assign stack slots to the pseudos that lack hard regs or
851 equivalents. Do not touch virtual registers. */
853 pseudo_regs
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
854 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
855 pseudo_regs
[n
++] = i
;
858 qsort (pseudo_regs
, n
, sizeof (int), pseudo_reg_compare
);
859 if (frame_pointer_needed
|| ! flag_ira
)
860 for (i
= 0; i
< n
; i
++)
861 alter_reg (pseudo_regs
[i
], -1, false);
863 for (i
= n
- 1; i
>= 0; i
--)
864 alter_reg (pseudo_regs
[i
], -1, false);
868 /* If we have some registers we think can be eliminated, scan all insns to
869 see if there is an insn that sets one of these registers to something
870 other than itself plus a constant. If so, the register cannot be
871 eliminated. Doing this scan here eliminates an extra pass through the
872 main reload loop in the most common case where register elimination
874 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
876 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
878 maybe_fix_stack_asms ();
880 insns_need_reload
= 0;
881 something_needs_elimination
= 0;
883 /* Initialize to -1, which means take the first spill register. */
886 /* Spill any hard regs that we know we can't eliminate. */
887 CLEAR_HARD_REG_SET (used_spill_regs
);
888 /* There can be multiple ways to eliminate a register;
889 they should be listed adjacently.
890 Elimination for any register fails only if all possible ways fail. */
891 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
894 int can_eliminate
= 0;
897 can_eliminate
|= ep
->can_eliminate
;
900 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
902 spill_hard_reg (from
, 1);
905 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
906 if (frame_pointer_needed
)
907 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
909 finish_spills (global
);
911 /* From now on, we may need to generate moves differently. We may also
912 allow modifications of insns which cause them to not be recognized.
913 Any such modifications will be cleaned up during reload itself. */
914 reload_in_progress
= 1;
916 /* This loop scans the entire function each go-round
917 and repeats until one repetition spills no additional hard regs. */
920 int something_changed
;
923 HOST_WIDE_INT starting_frame_size
;
925 /* Round size of stack frame to stack_alignment_needed. This must be done
926 here because the stack size may be a part of the offset computation
927 for register elimination, and there might have been new stack slots
928 created in the last iteration of this loop. */
929 if (cfun
->stack_alignment_needed
)
930 assign_stack_local (BLKmode
, 0, cfun
->stack_alignment_needed
);
932 starting_frame_size
= get_frame_size ();
934 set_initial_elim_offsets ();
935 set_initial_label_offsets ();
937 /* For each pseudo register that has an equivalent location defined,
938 try to eliminate any eliminable registers (such as the frame pointer)
939 assuming initial offsets for the replacement register, which
942 If the resulting location is directly addressable, substitute
943 the MEM we just got directly for the old REG.
945 If it is not addressable but is a constant or the sum of a hard reg
946 and constant, it is probably not addressable because the constant is
947 out of range, in that case record the address; we will generate
948 hairy code to compute the address in a register each time it is
949 needed. Similarly if it is a hard register, but one that is not
950 valid as an address register.
952 If the location is not addressable, but does not have one of the
953 above forms, assign a stack slot. We have to do this to avoid the
954 potential of producing lots of reloads if, e.g., a location involves
955 a pseudo that didn't get a hard register and has an equivalent memory
956 location that also involves a pseudo that didn't get a hard register.
958 Perhaps at some point we will improve reload_when_needed handling
959 so this problem goes away. But that's very hairy. */
961 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
962 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
964 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
966 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
968 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
969 else if (CONSTANT_P (XEXP (x
, 0))
970 || (REG_P (XEXP (x
, 0))
971 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
972 || (GET_CODE (XEXP (x
, 0)) == PLUS
973 && REG_P (XEXP (XEXP (x
, 0), 0))
974 && (REGNO (XEXP (XEXP (x
, 0), 0))
975 < FIRST_PSEUDO_REGISTER
)
976 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
977 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
980 /* Make a new stack slot. Then indicate that something
981 changed so we go back and recompute offsets for
982 eliminable registers because the allocation of memory
983 below might change some offset. reg_equiv_{mem,address}
984 will be set up for this pseudo on the next pass around
986 reg_equiv_memory_loc
[i
] = 0;
987 reg_equiv_init
[i
] = 0;
988 alter_reg (i
, -1, true);
992 if (caller_save_needed
)
995 /* If we allocated another stack slot, redo elimination bookkeeping. */
996 if (starting_frame_size
!= get_frame_size ())
999 if (caller_save_needed
)
1001 save_call_clobbered_regs ();
1002 /* That might have allocated new insn_chain structures. */
1003 reload_firstobj
= obstack_alloc (&reload_obstack
, 0);
1006 calculate_needs_all_insns (global
);
1008 CLEAR_REG_SET (&spilled_pseudos
);
1011 something_changed
= 0;
1013 /* If we allocated any new memory locations, make another pass
1014 since it might have changed elimination offsets. */
1015 if (starting_frame_size
!= get_frame_size ())
1016 something_changed
= 1;
1018 /* Even if the frame size remained the same, we might still have
1019 changed elimination offsets, e.g. if find_reloads called
1020 force_const_mem requiring the back end to allocate a constant
1021 pool base register that needs to be saved on the stack. */
1022 else if (!verify_initial_elim_offsets ())
1023 something_changed
= 1;
1026 HARD_REG_SET to_spill
;
1027 CLEAR_HARD_REG_SET (to_spill
);
1028 update_eliminables (&to_spill
);
1029 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
1031 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1032 if (TEST_HARD_REG_BIT (to_spill
, i
))
1034 spill_hard_reg (i
, 1);
1037 /* Regardless of the state of spills, if we previously had
1038 a register that we thought we could eliminate, but now can
1039 not eliminate, we must run another pass.
1041 Consider pseudos which have an entry in reg_equiv_* which
1042 reference an eliminable register. We must make another pass
1043 to update reg_equiv_* so that we do not substitute in the
1044 old value from when we thought the elimination could be
1046 something_changed
= 1;
1050 select_reload_regs ();
1054 if (insns_need_reload
!= 0 || did_spill
)
1055 something_changed
|= finish_spills (global
);
1057 if (! something_changed
)
1060 if (caller_save_needed
)
1061 delete_caller_save_insns ();
1063 obstack_free (&reload_obstack
, reload_firstobj
);
1066 /* If global-alloc was run, notify it of any register eliminations we have
1069 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1070 if (ep
->can_eliminate
)
1071 mark_elimination (ep
->from
, ep
->to
);
1073 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1074 If that insn didn't set the register (i.e., it copied the register to
1075 memory), just delete that insn instead of the equivalencing insn plus
1076 anything now dead. If we call delete_dead_insn on that insn, we may
1077 delete the insn that actually sets the register if the register dies
1078 there and that is incorrect. */
1080 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1082 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1085 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1087 rtx equiv_insn
= XEXP (list
, 0);
1089 /* If we already deleted the insn or if it may trap, we can't
1090 delete it. The latter case shouldn't happen, but can
1091 if an insn has a variable address, gets a REG_EH_REGION
1092 note added to it, and then gets converted into a load
1093 from a constant address. */
1094 if (NOTE_P (equiv_insn
)
1095 || can_throw_internal (equiv_insn
))
1097 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1098 delete_dead_insn (equiv_insn
);
1100 SET_INSN_DELETED (equiv_insn
);
1105 /* Use the reload registers where necessary
1106 by generating move instructions to move the must-be-register
1107 values into or out of the reload registers. */
1109 if (insns_need_reload
!= 0 || something_needs_elimination
1110 || something_needs_operands_changed
)
1112 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1114 reload_as_needed (global
);
1116 gcc_assert (old_frame_size
== get_frame_size ());
1118 gcc_assert (verify_initial_elim_offsets ());
1121 /* If we were able to eliminate the frame pointer, show that it is no
1122 longer live at the start of any basic block. If it ls live by
1123 virtue of being in a pseudo, that pseudo will be marked live
1124 and hence the frame pointer will be known to be live via that
1127 if (! frame_pointer_needed
)
1129 CLEAR_REGNO_REG_SET (bb
->il
.rtl
->global_live_at_start
,
1130 HARD_FRAME_POINTER_REGNUM
);
1132 /* Come here (with failure set nonzero) if we can't get enough spill
1136 CLEAR_REG_SET (&spilled_pseudos
);
1137 reload_in_progress
= 0;
1139 /* Now eliminate all pseudo regs by modifying them into
1140 their equivalent memory references.
1141 The REG-rtx's for the pseudos are modified in place,
1142 so all insns that used to refer to them now refer to memory.
1144 For a reg that has a reg_equiv_address, all those insns
1145 were changed by reloading so that no insns refer to it any longer;
1146 but the DECL_RTL of a variable decl may refer to it,
1147 and if so this causes the debugging info to mention the variable. */
1149 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1153 if (reg_equiv_mem
[i
])
1154 addr
= XEXP (reg_equiv_mem
[i
], 0);
1156 if (reg_equiv_address
[i
])
1157 addr
= reg_equiv_address
[i
];
1161 if (reg_renumber
[i
] < 0)
1163 rtx reg
= regno_reg_rtx
[i
];
1165 REG_USERVAR_P (reg
) = 0;
1166 PUT_CODE (reg
, MEM
);
1167 XEXP (reg
, 0) = addr
;
1168 if (reg_equiv_memory_loc
[i
])
1169 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc
[i
]);
1172 MEM_IN_STRUCT_P (reg
) = MEM_SCALAR_P (reg
) = 0;
1173 MEM_ATTRS (reg
) = 0;
1175 MEM_NOTRAP_P (reg
) = 1;
1177 else if (reg_equiv_mem
[i
])
1178 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1182 /* We must set reload_completed now since the cleanup_subreg_operands call
1183 below will re-recognize each insn and reload may have generated insns
1184 which are only valid during and after reload. */
1185 reload_completed
= 1;
1187 /* Make a pass over all the insns and delete all USEs which we inserted
1188 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1189 notes. Delete all CLOBBER insns, except those that refer to the return
1190 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1191 from misarranging variable-array code, and simplify (subreg (reg))
1192 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1193 are no longer useful or accurate. Strip and regenerate REG_INC notes
1194 that may have been moved around. */
1196 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1201 /* Clean up invalid ASMs so that they don't confuse later passes.
1203 if (asm_noperands (PATTERN (insn
)) >= 0)
1205 extract_insn (insn
);
1206 if (!constrain_operands (1))
1208 error_for_asm (insn
,
1209 "%<asm%> operand has impossible constraints");
1217 HARD_REG_SET used_function_regs
;
1219 get_call_invalidated_used_regs (insn
, &used_function_regs
, false);
1220 IOR_HARD_REG_SET (cfun
->emit
->call_used_regs
, used_function_regs
);
1221 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1222 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1225 if ((GET_CODE (PATTERN (insn
)) == USE
1226 /* We mark with QImode USEs introduced by reload itself. */
1227 && (GET_MODE (insn
) == QImode
1228 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1229 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1230 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1231 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1232 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1233 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1234 != stack_pointer_rtx
))
1235 && (!REG_P (XEXP (PATTERN (insn
), 0))
1236 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1242 /* Some CLOBBERs may survive until here and still reference unassigned
1243 pseudos with const equivalent, which may in turn cause ICE in later
1244 passes if the reference remains in place. */
1245 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1246 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1247 VOIDmode
, PATTERN (insn
));
1249 /* Discard obvious no-ops, even without -O. This optimization
1250 is fast and doesn't interfere with debugging. */
1251 if (NONJUMP_INSN_P (insn
)
1252 && GET_CODE (PATTERN (insn
)) == SET
1253 && REG_P (SET_SRC (PATTERN (insn
)))
1254 && REG_P (SET_DEST (PATTERN (insn
)))
1255 && (REGNO (SET_SRC (PATTERN (insn
)))
1256 == REGNO (SET_DEST (PATTERN (insn
)))))
1262 pnote
= ®_NOTES (insn
);
1265 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1266 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1267 || REG_NOTE_KIND (*pnote
) == REG_INC
1268 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1269 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1270 *pnote
= XEXP (*pnote
, 1);
1272 pnote
= &XEXP (*pnote
, 1);
1276 add_auto_inc_notes (insn
, PATTERN (insn
));
1279 /* And simplify (subreg (reg)) if it appears as an operand. */
1280 cleanup_subreg_operands (insn
);
1283 /* If we are doing stack checking, give a warning if this function's
1284 frame size is larger than we expect. */
1285 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1287 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1288 static int verbose_warned
= 0;
1290 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1291 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1292 size
+= UNITS_PER_WORD
;
1294 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1296 warning (0, "frame size too large for reliable stack checking");
1297 if (! verbose_warned
)
1299 warning (0, "try reducing the number of local variables");
1305 /* Indicate that we no longer have known memory locations or constants. */
1306 if (reg_equiv_constant
)
1307 free (reg_equiv_constant
);
1308 if (reg_equiv_invariant
)
1309 free (reg_equiv_invariant
);
1310 reg_equiv_constant
= 0;
1311 reg_equiv_invariant
= 0;
1312 VEC_free (rtx
, gc
, reg_equiv_memory_loc_vec
);
1313 reg_equiv_memory_loc
= 0;
1315 if (offsets_known_at
)
1316 free (offsets_known_at
);
1320 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1321 if (reg_equiv_alt_mem_list
[i
])
1322 free_EXPR_LIST_list (®_equiv_alt_mem_list
[i
]);
1323 free (reg_equiv_alt_mem_list
);
1325 free (reg_equiv_mem
);
1327 free (reg_equiv_address
);
1328 free (reg_max_ref_width
);
1329 free (reg_old_renumber
);
1330 free (pseudo_previous_regs
);
1331 free (pseudo_forbidden_regs
);
1333 CLEAR_HARD_REG_SET (used_spill_regs
);
1334 for (i
= 0; i
< n_spills
; i
++)
1335 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1337 /* Free all the insn_chain structures at once. */
1338 obstack_free (&reload_obstack
, reload_startobj
);
1339 unused_insn_chains
= 0;
1340 fixup_abnormal_edges ();
1342 /* Replacing pseudos with their memory equivalents might have
1343 created shared rtx. Subsequent passes would get confused
1344 by this, so unshare everything here. */
1345 unshare_all_rtl_again (first
);
1347 #ifdef STACK_BOUNDARY
1348 /* init_emit has set the alignment of the hard frame pointer
1349 to STACK_BOUNDARY. It is very likely no longer valid if
1350 the hard frame pointer was used for register allocation. */
1351 if (!frame_pointer_needed
)
1352 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1358 /* Yet another special case. Unfortunately, reg-stack forces people to
1359 write incorrect clobbers in asm statements. These clobbers must not
1360 cause the register to appear in bad_spill_regs, otherwise we'll call
1361 fatal_insn later. We clear the corresponding regnos in the live
1362 register sets to avoid this.
1363 The whole thing is rather sick, I'm afraid. */
1366 maybe_fix_stack_asms (void)
1369 const char *constraints
[MAX_RECOG_OPERANDS
];
1370 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1371 struct insn_chain
*chain
;
1373 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1376 HARD_REG_SET clobbered
, allowed
;
1379 if (! INSN_P (chain
->insn
)
1380 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1382 pat
= PATTERN (chain
->insn
);
1383 if (GET_CODE (pat
) != PARALLEL
)
1386 CLEAR_HARD_REG_SET (clobbered
);
1387 CLEAR_HARD_REG_SET (allowed
);
1389 /* First, make a mask of all stack regs that are clobbered. */
1390 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1392 rtx t
= XVECEXP (pat
, 0, i
);
1393 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1394 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1397 /* Get the operand values and constraints out of the insn. */
1398 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1399 constraints
, operand_mode
);
1401 /* For every operand, see what registers are allowed. */
1402 for (i
= 0; i
< noperands
; i
++)
1404 const char *p
= constraints
[i
];
1405 /* For every alternative, we compute the class of registers allowed
1406 for reloading in CLS, and merge its contents into the reg set
1408 int cls
= (int) NO_REGS
;
1414 if (c
== '\0' || c
== ',' || c
== '#')
1416 /* End of one alternative - mark the regs in the current
1417 class, and reset the class. */
1418 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1424 } while (c
!= '\0' && c
!= ',');
1432 case '=': case '+': case '*': case '%': case '?': case '!':
1433 case '0': case '1': case '2': case '3': case '4': case 'm':
1434 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1435 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1436 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1441 cls
= (int) reg_class_subunion
[cls
]
1442 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1447 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1451 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1452 cls
= (int) reg_class_subunion
[cls
]
1453 [(int) base_reg_class (VOIDmode
, ADDRESS
, SCRATCH
)];
1455 cls
= (int) reg_class_subunion
[cls
]
1456 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1458 p
+= CONSTRAINT_LEN (c
, p
);
1461 /* Those of the registers which are clobbered, but allowed by the
1462 constraints, must be usable as reload registers. So clear them
1463 out of the life information. */
1464 AND_HARD_REG_SET (allowed
, clobbered
);
1465 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1466 if (TEST_HARD_REG_BIT (allowed
, i
))
1468 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1469 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1476 /* Copy the global variables n_reloads and rld into the corresponding elts
1479 copy_reloads (struct insn_chain
*chain
)
1481 chain
->n_reloads
= n_reloads
;
1482 chain
->rld
= obstack_alloc (&reload_obstack
,
1483 n_reloads
* sizeof (struct reload
));
1484 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1485 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1488 /* Walk the chain of insns, and determine for each whether it needs reloads
1489 and/or eliminations. Build the corresponding insns_need_reload list, and
1490 set something_needs_elimination as appropriate. */
1492 calculate_needs_all_insns (int global
)
1494 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1495 struct insn_chain
*chain
, *next
= 0;
1497 something_needs_elimination
= 0;
1499 reload_insn_firstobj
= obstack_alloc (&reload_obstack
, 0);
1500 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1502 rtx insn
= chain
->insn
;
1506 /* Clear out the shortcuts. */
1507 chain
->n_reloads
= 0;
1508 chain
->need_elim
= 0;
1509 chain
->need_reload
= 0;
1510 chain
->need_operand_change
= 0;
1512 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1513 include REG_LABEL), we need to see what effects this has on the
1514 known offsets at labels. */
1516 if (LABEL_P (insn
) || JUMP_P (insn
)
1517 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1518 set_label_offsets (insn
, insn
, 0);
1522 rtx old_body
= PATTERN (insn
);
1523 int old_code
= INSN_CODE (insn
);
1524 rtx old_notes
= REG_NOTES (insn
);
1525 int did_elimination
= 0;
1526 int operands_changed
= 0;
1527 rtx set
= single_set (insn
);
1529 /* Skip insns that only set an equivalence. */
1530 if (set
&& REG_P (SET_DEST (set
))
1531 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1532 && (reg_equiv_constant
[REGNO (SET_DEST (set
))]
1533 || (reg_equiv_invariant
[REGNO (SET_DEST (set
))]))
1534 && reg_equiv_init
[REGNO (SET_DEST (set
))])
1537 /* If needed, eliminate any eliminable registers. */
1538 if (num_eliminable
|| num_eliminable_invariants
)
1539 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1541 /* Analyze the instruction. */
1542 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1543 global
, spill_reg_order
);
1545 /* If a no-op set needs more than one reload, this is likely
1546 to be something that needs input address reloads. We
1547 can't get rid of this cleanly later, and it is of no use
1548 anyway, so discard it now.
1549 We only do this when expensive_optimizations is enabled,
1550 since this complements reload inheritance / output
1551 reload deletion, and it can make debugging harder. */
1552 if (flag_expensive_optimizations
&& n_reloads
> 1)
1554 rtx set
= single_set (insn
);
1557 ((SET_SRC (set
) == SET_DEST (set
)
1558 && REG_P (SET_SRC (set
))
1559 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1560 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1561 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1562 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1563 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))] != NULL
1564 && reg_equiv_memory_loc
[REGNO (SET_DEST (set
))] != NULL
1565 && rtx_equal_p (reg_equiv_memory_loc
1566 [REGNO (SET_SRC (set
))],
1567 reg_equiv_memory_loc
1568 [REGNO (SET_DEST (set
))]))))
1571 /* Delete it from the reload chain. */
1573 chain
->prev
->next
= next
;
1575 reload_insn_chain
= next
;
1577 next
->prev
= chain
->prev
;
1578 chain
->next
= unused_insn_chains
;
1579 unused_insn_chains
= chain
;
1584 update_eliminable_offsets ();
1586 /* Remember for later shortcuts which insns had any reloads or
1587 register eliminations. */
1588 chain
->need_elim
= did_elimination
;
1589 chain
->need_reload
= n_reloads
> 0;
1590 chain
->need_operand_change
= operands_changed
;
1592 /* Discard any register replacements done. */
1593 if (did_elimination
)
1595 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1596 PATTERN (insn
) = old_body
;
1597 INSN_CODE (insn
) = old_code
;
1598 REG_NOTES (insn
) = old_notes
;
1599 something_needs_elimination
= 1;
1602 something_needs_operands_changed
|= operands_changed
;
1606 copy_reloads (chain
);
1607 *pprev_reload
= chain
;
1608 pprev_reload
= &chain
->next_need_reload
;
1615 /* Comparison function for qsort to decide which of two reloads
1616 should be handled first. *P1 and *P2 are the reload numbers. */
1619 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1621 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1624 /* Consider required reloads before optional ones. */
1625 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1629 /* Count all solitary classes before non-solitary ones. */
1630 t
= ((reg_class_size
[(int) rld
[r2
].class] == 1)
1631 - (reg_class_size
[(int) rld
[r1
].class] == 1));
1635 /* Aside from solitaires, consider all multi-reg groups first. */
1636 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1640 /* Consider reloads in order of increasing reg-class number. */
1641 t
= (int) rld
[r1
].class - (int) rld
[r2
].class;
1645 /* If reloads are equally urgent, sort by reload number,
1646 so that the results of qsort leave nothing to chance. */
1650 /* The cost of spilling each hard reg. */
1651 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1653 /* When spilling multiple hard registers, we use SPILL_COST for the first
1654 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1655 only the first hard reg for a multi-reg pseudo. */
1656 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1658 /* Update the spill cost arrays, considering that pseudo REG is live. */
1661 count_pseudo (int reg
)
1663 int freq
= REG_FREQ (reg
);
1664 int r
= reg_renumber
[reg
];
1667 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1668 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1671 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1673 gcc_assert (r
>= 0);
1675 spill_add_cost
[r
] += freq
;
1677 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1679 spill_cost
[r
+ nregs
] += freq
;
1682 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1683 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1686 order_regs_for_reload (struct insn_chain
*chain
)
1689 HARD_REG_SET used_by_pseudos
;
1690 HARD_REG_SET used_by_pseudos2
;
1691 reg_set_iterator rsi
;
1693 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1695 memset (spill_cost
, 0, sizeof spill_cost
);
1696 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1698 /* Count number of uses of each hard reg by pseudo regs allocated to it
1699 and then order them by decreasing use. First exclude hard registers
1700 that are live in or across this insn. */
1702 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1703 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1704 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1705 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1707 /* Now find out which pseudos are allocated to it, and update
1709 CLEAR_REG_SET (&pseudos_counted
);
1711 EXECUTE_IF_SET_IN_REG_SET
1712 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1716 EXECUTE_IF_SET_IN_REG_SET
1717 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1721 CLEAR_REG_SET (&pseudos_counted
);
1724 /* Vector of reload-numbers showing the order in which the reloads should
1726 static short reload_order
[MAX_RELOADS
];
1728 /* This is used to keep track of the spill regs used in one insn. */
1729 static HARD_REG_SET used_spill_regs_local
;
1731 /* We decided to spill hard register SPILLED, which has a size of
1732 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1733 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1734 update SPILL_COST/SPILL_ADD_COST. */
1737 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1739 int freq
= REG_FREQ (reg
);
1740 int r
= reg_renumber
[reg
];
1741 int nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1743 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1744 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1747 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1749 spill_add_cost
[r
] -= freq
;
1751 spill_cost
[r
+ nregs
] -= freq
;
1754 /* Find reload register to use for reload number ORDER. */
1757 find_reg (struct insn_chain
*chain
, int order
)
1759 int rnum
= reload_order
[order
];
1760 struct reload
*rl
= rld
+ rnum
;
1761 int best_cost
= INT_MAX
;
1765 HARD_REG_SET not_usable
;
1766 HARD_REG_SET used_by_other_reload
;
1767 reg_set_iterator rsi
;
1769 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1770 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1771 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->class]);
1773 CLEAR_HARD_REG_SET (used_by_other_reload
);
1774 for (k
= 0; k
< order
; k
++)
1776 int other
= reload_order
[k
];
1778 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1779 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1780 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1783 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1785 unsigned int regno
= i
;
1787 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1788 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1789 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1791 int this_cost
= spill_cost
[regno
];
1793 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1795 for (j
= 1; j
< this_nregs
; j
++)
1797 this_cost
+= spill_add_cost
[regno
+ j
];
1798 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1799 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1804 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1806 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1808 if (this_cost
< best_cost
1809 /* Among registers with equal cost, prefer caller-saved ones, or
1810 use REG_ALLOC_ORDER if it is defined. */
1811 || (this_cost
== best_cost
1812 #ifdef REG_ALLOC_ORDER
1813 && (inv_reg_alloc_order
[regno
]
1814 < inv_reg_alloc_order
[best_reg
])
1816 && call_used_regs
[regno
]
1817 && ! call_used_regs
[best_reg
]
1822 best_cost
= this_cost
;
1830 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1832 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1833 rl
->regno
= best_reg
;
1835 EXECUTE_IF_SET_IN_REG_SET
1836 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1838 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1841 EXECUTE_IF_SET_IN_REG_SET
1842 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1844 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1847 for (i
= 0; i
< rl
->nregs
; i
++)
1849 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1850 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1851 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1856 /* Find more reload regs to satisfy the remaining need of an insn, which
1858 Do it by ascending class number, since otherwise a reg
1859 might be spilled for a big class and might fail to count
1860 for a smaller class even though it belongs to that class. */
1863 find_reload_regs (struct insn_chain
*chain
)
1867 /* In order to be certain of getting the registers we need,
1868 we must sort the reloads into order of increasing register class.
1869 Then our grabbing of reload registers will parallel the process
1870 that provided the reload registers. */
1871 for (i
= 0; i
< chain
->n_reloads
; i
++)
1873 /* Show whether this reload already has a hard reg. */
1874 if (chain
->rld
[i
].reg_rtx
)
1876 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1877 chain
->rld
[i
].regno
= regno
;
1879 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
1882 chain
->rld
[i
].regno
= -1;
1883 reload_order
[i
] = i
;
1886 n_reloads
= chain
->n_reloads
;
1887 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1889 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1892 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1894 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1896 /* Compute the order of preference for hard registers to spill. */
1898 order_regs_for_reload (chain
);
1900 for (i
= 0; i
< n_reloads
; i
++)
1902 int r
= reload_order
[i
];
1904 /* Ignore reloads that got marked inoperative. */
1905 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1906 && ! rld
[r
].optional
1907 && rld
[r
].regno
== -1)
1908 if (! find_reg (chain
, i
))
1911 fprintf (dump_file
, "reload failure for reload %d\n", r
);
1912 spill_failure (chain
->insn
, rld
[r
].class);
1918 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
1919 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
1921 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1925 select_reload_regs (void)
1927 struct insn_chain
*chain
;
1929 /* Try to satisfy the needs for each insn. */
1930 for (chain
= insns_need_reload
; chain
!= 0;
1931 chain
= chain
->next_need_reload
)
1932 find_reload_regs (chain
);
1935 /* Delete all insns that were inserted by emit_caller_save_insns during
1938 delete_caller_save_insns (void)
1940 struct insn_chain
*c
= reload_insn_chain
;
1944 while (c
!= 0 && c
->is_caller_save_insn
)
1946 struct insn_chain
*next
= c
->next
;
1949 if (c
== reload_insn_chain
)
1950 reload_insn_chain
= next
;
1954 next
->prev
= c
->prev
;
1956 c
->prev
->next
= next
;
1957 c
->next
= unused_insn_chains
;
1958 unused_insn_chains
= c
;
1966 /* Handle the failure to find a register to spill.
1967 INSN should be one of the insns which needed this particular spill reg. */
1970 spill_failure (rtx insn
, enum reg_class
class)
1972 if (asm_noperands (PATTERN (insn
)) >= 0)
1973 error_for_asm (insn
, "can't find a register in class %qs while "
1974 "reloading %<asm%>",
1975 reg_class_names
[class]);
1978 error ("unable to find a register to spill in class %qs",
1979 reg_class_names
[class]);
1983 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
1984 debug_reload_to_stream (dump_file
);
1986 fatal_insn ("this is the insn:", insn
);
1990 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1991 data that is dead in INSN. */
1994 delete_dead_insn (rtx insn
)
1996 rtx prev
= prev_real_insn (insn
);
1999 /* If the previous insn sets a register that dies in our insn, delete it
2001 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2002 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2003 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2004 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2005 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2006 delete_dead_insn (prev
);
2008 SET_INSN_DELETED (insn
);
2011 /* Modify the home of pseudo-reg I.
2012 The new home is present in reg_renumber[I].
2014 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2015 or it may be -1, meaning there is none or it is not relevant.
2016 This is used so that all pseudos spilled from a given hard reg
2017 can share one stack slot. */
2020 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2022 /* When outputting an inline function, this can happen
2023 for a reg that isn't actually used. */
2024 if (regno_reg_rtx
[i
] == 0)
2027 /* If the reg got changed to a MEM at rtl-generation time,
2029 if (!REG_P (regno_reg_rtx
[i
]))
2032 /* Modify the reg-rtx to contain the new hard reg
2033 number or else to contain its pseudo reg number. */
2034 REGNO (regno_reg_rtx
[i
])
2035 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
2037 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2038 allocate a stack slot for it. */
2040 if (reg_renumber
[i
] < 0
2041 && REG_N_REFS (i
) > 0
2042 && reg_equiv_constant
[i
] == 0
2043 && (reg_equiv_invariant
[i
] == 0 || reg_equiv_init
[i
] == 0)
2044 && reg_equiv_memory_loc
[i
] == 0)
2047 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2048 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2049 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2050 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2051 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2053 bool shared_p
= false;
2056 x
= (dont_share_p
|| ! flag_ira
2057 ? NULL_RTX
: reuse_stack_slot (i
, inherent_size
, total_size
));
2060 /* Each pseudo reg has an inherent size which comes from its own mode,
2061 and a total size which provides room for paradoxical subregs
2062 which refer to the pseudo reg in wider modes.
2064 We can use a slot already allocated if it provides both
2065 enough inherent space and enough total space.
2066 Otherwise, we allocate a new slot, making sure that it has no less
2067 inherent space, and no less total space, then the previous slot. */
2068 else if (from_reg
== -1 || (! dont_share_p
&& flag_ira
))
2070 /* No known place to spill from => no slot to reuse. */
2071 x
= assign_stack_local (mode
, total_size
,
2072 min_align
> inherent_align
2073 || total_size
> inherent_size
? -1 : 0);
2074 if (BYTES_BIG_ENDIAN
)
2075 /* Cancel the big-endian correction done in assign_stack_local.
2076 Get the address of the beginning of the slot.
2077 This is so we can do a big-endian correction unconditionally
2079 adjust
= inherent_size
- total_size
;
2081 /* Nothing can alias this slot except this pseudo. */
2082 set_mem_alias_set (x
, new_alias_set ());
2084 if (! dont_share_p
&& flag_ira
)
2085 mark_new_stack_slot (x
, i
, total_size
);
2088 /* Reuse a stack slot if possible. */
2089 else if (spill_stack_slot
[from_reg
] != 0
2090 && spill_stack_slot_width
[from_reg
] >= total_size
2091 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2093 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2094 x
= spill_stack_slot
[from_reg
];
2096 /* Allocate a bigger slot. */
2099 /* Compute maximum size needed, both for inherent size
2100 and for total size. */
2103 if (spill_stack_slot
[from_reg
])
2105 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2107 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2108 if (spill_stack_slot_width
[from_reg
] > total_size
)
2109 total_size
= spill_stack_slot_width
[from_reg
];
2110 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2111 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2114 /* Make a slot with that size. */
2115 x
= assign_stack_local (mode
, total_size
,
2116 min_align
> inherent_align
2117 || total_size
> inherent_size
? -1 : 0);
2120 /* All pseudos mapped to this slot can alias each other. */
2121 if (spill_stack_slot
[from_reg
])
2122 set_mem_alias_set (x
, MEM_ALIAS_SET (spill_stack_slot
[from_reg
]));
2124 set_mem_alias_set (x
, new_alias_set ());
2126 if (BYTES_BIG_ENDIAN
)
2128 /* Cancel the big-endian correction done in assign_stack_local.
2129 Get the address of the beginning of the slot.
2130 This is so we can do a big-endian correction unconditionally
2132 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2135 = adjust_address_nv (x
, mode_for_size (total_size
2141 spill_stack_slot
[from_reg
] = stack_slot
;
2142 spill_stack_slot_width
[from_reg
] = total_size
;
2145 /* On a big endian machine, the "address" of the slot
2146 is the address of the low part that fits its inherent mode. */
2147 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2148 adjust
+= (total_size
- inherent_size
);
2150 /* If we have any adjustment to make, or if the stack slot is the
2151 wrong mode, make a new stack slot. */
2152 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2154 /* If we have a decl for the original register, set it for the
2155 memory. If this is a shared MEM, make a copy. */
2159 set_mem_attrs_from_reg (x
, regno_reg_rtx
[i
]);
2161 else if (REG_EXPR (regno_reg_rtx
[i
])
2162 && DECL_P (REG_EXPR (regno_reg_rtx
[i
])))
2164 rtx decl
= DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx
[i
]));
2166 /* We can do this only for the DECLs home pseudo, not for
2167 any copies of it, since otherwise when the stack slot
2168 is reused, nonoverlapping_memrefs_p might think they
2170 if (decl
&& REG_P (decl
) && REGNO (decl
) == (unsigned) i
)
2172 if (from_reg
!= -1 && spill_stack_slot
[from_reg
] == x
)
2175 set_mem_attrs_from_reg (x
, regno_reg_rtx
[i
]);
2179 /* Save the stack slot for later. */
2180 reg_equiv_memory_loc
[i
] = x
;
2184 /* Mark the slots in regs_ever_live for the hard regs
2185 used by pseudo-reg number REGNO. */
2188 mark_home_live (int regno
)
2192 i
= reg_renumber
[regno
];
2195 lim
= i
+ hard_regno_nregs
[i
][PSEUDO_REGNO_MODE (regno
)];
2197 regs_ever_live
[i
++] = 1;
2200 /* This function handles the tracking of elimination offsets around branches.
2202 X is a piece of RTL being scanned.
2204 INSN is the insn that it came from, if any.
2206 INITIAL_P is nonzero if we are to set the offset to be the initial
2207 offset and zero if we are setting the offset of the label to be the
2211 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2213 enum rtx_code code
= GET_CODE (x
);
2216 struct elim_table
*p
;
2221 if (LABEL_REF_NONLOCAL_P (x
))
2226 /* ... fall through ... */
2229 /* If we know nothing about this label, set the desired offsets. Note
2230 that this sets the offset at a label to be the offset before a label
2231 if we don't know anything about the label. This is not correct for
2232 the label after a BARRIER, but is the best guess we can make. If
2233 we guessed wrong, we will suppress an elimination that might have
2234 been possible had we been able to guess correctly. */
2236 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2238 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2239 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2240 = (initial_p
? reg_eliminate
[i
].initial_offset
2241 : reg_eliminate
[i
].offset
);
2242 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2245 /* Otherwise, if this is the definition of a label and it is
2246 preceded by a BARRIER, set our offsets to the known offset of
2250 && (tem
= prev_nonnote_insn (insn
)) != 0
2252 set_offsets_for_label (insn
);
2254 /* If neither of the above cases is true, compare each offset
2255 with those previously recorded and suppress any eliminations
2256 where the offsets disagree. */
2258 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2259 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2260 != (initial_p
? reg_eliminate
[i
].initial_offset
2261 : reg_eliminate
[i
].offset
))
2262 reg_eliminate
[i
].can_eliminate
= 0;
2267 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2269 /* ... fall through ... */
2273 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2274 and hence must have all eliminations at their initial offsets. */
2275 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2276 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2277 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2283 /* Each of the labels in the parallel or address vector must be
2284 at their initial offsets. We want the first field for PARALLEL
2285 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2287 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2288 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2293 /* We only care about setting PC. If the source is not RETURN,
2294 IF_THEN_ELSE, or a label, disable any eliminations not at
2295 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2296 isn't one of those possibilities. For branches to a label,
2297 call ourselves recursively.
2299 Note that this can disable elimination unnecessarily when we have
2300 a non-local goto since it will look like a non-constant jump to
2301 someplace in the current function. This isn't a significant
2302 problem since such jumps will normally be when all elimination
2303 pairs are back to their initial offsets. */
2305 if (SET_DEST (x
) != pc_rtx
)
2308 switch (GET_CODE (SET_SRC (x
)))
2315 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2319 tem
= XEXP (SET_SRC (x
), 1);
2320 if (GET_CODE (tem
) == LABEL_REF
)
2321 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2322 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2325 tem
= XEXP (SET_SRC (x
), 2);
2326 if (GET_CODE (tem
) == LABEL_REF
)
2327 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2328 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2336 /* If we reach here, all eliminations must be at their initial
2337 offset because we are doing a jump to a variable address. */
2338 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2339 if (p
->offset
!= p
->initial_offset
)
2340 p
->can_eliminate
= 0;
2348 /* Scan X and replace any eliminable registers (such as fp) with a
2349 replacement (such as sp), plus an offset.
2351 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2352 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2353 MEM, we are allowed to replace a sum of a register and the constant zero
2354 with the register, which we cannot do outside a MEM. In addition, we need
2355 to record the fact that a register is referenced outside a MEM.
2357 If INSN is an insn, it is the insn containing X. If we replace a REG
2358 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2359 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2360 the REG is being modified.
2362 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2363 That's used when we eliminate in expressions stored in notes.
2364 This means, do not set ref_outside_mem even if the reference
2367 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2368 replacements done assuming all offsets are at their initial values. If
2369 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2370 encounter, return the actual location so that find_reloads will do
2371 the proper thing. */
2374 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2375 bool may_use_invariant
)
2377 enum rtx_code code
= GET_CODE (x
);
2378 struct elim_table
*ep
;
2385 if (! current_function_decl
)
2407 /* First handle the case where we encounter a bare register that
2408 is eliminable. Replace it with a PLUS. */
2409 if (regno
< FIRST_PSEUDO_REGISTER
)
2411 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2413 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2414 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2417 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2418 && reg_equiv_invariant
&& reg_equiv_invariant
[regno
])
2420 if (may_use_invariant
)
2421 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant
[regno
]),
2422 mem_mode
, insn
, true);
2423 /* There exists at least one use of REGNO that cannot be
2424 eliminated. Prevent the defining insn from being deleted. */
2425 reg_equiv_init
[regno
] = NULL_RTX
;
2426 alter_reg (regno
, -1, true);
2430 /* You might think handling MINUS in a manner similar to PLUS is a
2431 good idea. It is not. It has been tried multiple times and every
2432 time the change has had to have been reverted.
2434 Other parts of reload know a PLUS is special (gen_reload for example)
2435 and require special code to handle code a reloaded PLUS operand.
2437 Also consider backends where the flags register is clobbered by a
2438 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2439 lea instruction comes to mind). If we try to reload a MINUS, we
2440 may kill the flags register that was holding a useful value.
2442 So, please before trying to handle MINUS, consider reload as a
2443 whole instead of this little section as well as the backend issues. */
2445 /* If this is the sum of an eliminable register and a constant, rework
2447 if (REG_P (XEXP (x
, 0))
2448 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2449 && CONSTANT_P (XEXP (x
, 1)))
2451 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2453 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2455 /* The only time we want to replace a PLUS with a REG (this
2456 occurs when the constant operand of the PLUS is the negative
2457 of the offset) is when we are inside a MEM. We won't want
2458 to do so at other times because that would change the
2459 structure of the insn in a way that reload can't handle.
2460 We special-case the commonest situation in
2461 eliminate_regs_in_insn, so just replace a PLUS with a
2462 PLUS here, unless inside a MEM. */
2463 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2464 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2467 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2468 plus_constant (XEXP (x
, 1),
2469 ep
->previous_offset
));
2472 /* If the register is not eliminable, we are done since the other
2473 operand is a constant. */
2477 /* If this is part of an address, we want to bring any constant to the
2478 outermost PLUS. We will do this by doing register replacement in
2479 our operands and seeing if a constant shows up in one of them.
2481 Note that there is no risk of modifying the structure of the insn,
2482 since we only get called for its operands, thus we are either
2483 modifying the address inside a MEM, or something like an address
2484 operand of a load-address insn. */
2487 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true);
2488 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true);
2490 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2492 /* If one side is a PLUS and the other side is a pseudo that
2493 didn't get a hard register but has a reg_equiv_constant,
2494 we must replace the constant here since it may no longer
2495 be in the position of any operand. */
2496 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2497 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2498 && reg_renumber
[REGNO (new1
)] < 0
2499 && reg_equiv_constant
!= 0
2500 && reg_equiv_constant
[REGNO (new1
)] != 0)
2501 new1
= reg_equiv_constant
[REGNO (new1
)];
2502 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2503 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2504 && reg_renumber
[REGNO (new0
)] < 0
2505 && reg_equiv_constant
[REGNO (new0
)] != 0)
2506 new0
= reg_equiv_constant
[REGNO (new0
)];
2508 new = form_sum (new0
, new1
);
2510 /* As above, if we are not inside a MEM we do not want to
2511 turn a PLUS into something else. We might try to do so here
2512 for an addition of 0 if we aren't optimizing. */
2513 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2514 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2522 /* If this is the product of an eliminable register and a
2523 constant, apply the distribute law and move the constant out
2524 so that we have (plus (mult ..) ..). This is needed in order
2525 to keep load-address insns valid. This case is pathological.
2526 We ignore the possibility of overflow here. */
2527 if (REG_P (XEXP (x
, 0))
2528 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2529 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2530 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2532 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2535 /* Refs inside notes don't count for this purpose. */
2536 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2537 || GET_CODE (insn
) == INSN_LIST
)))
2538 ep
->ref_outside_mem
= 1;
2541 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2542 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2545 /* ... fall through ... */
2549 /* See comments before PLUS about handling MINUS. */
2551 case DIV
: case UDIV
:
2552 case MOD
: case UMOD
:
2553 case AND
: case IOR
: case XOR
:
2554 case ROTATERT
: case ROTATE
:
2555 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2557 case GE
: case GT
: case GEU
: case GTU
:
2558 case LE
: case LT
: case LEU
: case LTU
:
2560 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false);
2561 rtx new1
= XEXP (x
, 1)
2562 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false) : 0;
2564 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2565 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2570 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2573 new = eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true);
2574 if (new != XEXP (x
, 0))
2576 /* If this is a REG_DEAD note, it is not valid anymore.
2577 Using the eliminated version could result in creating a
2578 REG_DEAD note for the stack or frame pointer. */
2579 if (GET_MODE (x
) == REG_DEAD
)
2581 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true)
2584 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2588 /* ... fall through ... */
2591 /* Now do eliminations in the rest of the chain. If this was
2592 an EXPR_LIST, this might result in allocating more memory than is
2593 strictly needed, but it simplifies the code. */
2596 new = eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true);
2597 if (new != XEXP (x
, 1))
2599 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2607 case STRICT_LOW_PART
:
2609 case SIGN_EXTEND
: case ZERO_EXTEND
:
2610 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2611 case FLOAT
: case FIX
:
2612 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2621 new = eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false);
2622 if (new != XEXP (x
, 0))
2623 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2627 /* Similar to above processing, but preserve SUBREG_BYTE.
2628 Convert (subreg (mem)) to (mem) if not paradoxical.
2629 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2630 pseudo didn't get a hard reg, we must replace this with the
2631 eliminated version of the memory location because push_reload
2632 may do the replacement in certain circumstances. */
2633 if (REG_P (SUBREG_REG (x
))
2634 && (GET_MODE_SIZE (GET_MODE (x
))
2635 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2636 && reg_equiv_memory_loc
!= 0
2637 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2639 new = SUBREG_REG (x
);
2642 new = eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false);
2644 if (new != SUBREG_REG (x
))
2646 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2647 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2650 && ((x_size
< new_size
2651 #ifdef WORD_REGISTER_OPERATIONS
2652 /* On these machines, combine can create rtl of the form
2653 (set (subreg:m1 (reg:m2 R) 0) ...)
2654 where m1 < m2, and expects something interesting to
2655 happen to the entire word. Moreover, it will use the
2656 (reg:m2 R) later, expecting all bits to be preserved.
2657 So if the number of words is the same, preserve the
2658 subreg so that push_reload can see it. */
2659 && ! ((x_size
- 1) / UNITS_PER_WORD
2660 == (new_size
-1 ) / UNITS_PER_WORD
)
2663 || x_size
== new_size
)
2665 return adjust_address_nv (new, GET_MODE (x
), SUBREG_BYTE (x
));
2667 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_BYTE (x
));
2673 /* Our only special processing is to pass the mode of the MEM to our
2674 recursive call and copy the flags. While we are here, handle this
2675 case more efficiently. */
2677 replace_equiv_address_nv (x
,
2678 eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
),
2682 /* Handle insn_list USE that a call to a pure function may generate. */
2683 new = eliminate_regs_1 (XEXP (x
, 0), 0, insn
, false);
2684 if (new != XEXP (x
, 0))
2685 return gen_rtx_USE (GET_MODE (x
), new);
2697 /* Process each of our operands recursively. If any have changed, make a
2699 fmt
= GET_RTX_FORMAT (code
);
2700 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2704 new = eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false);
2705 if (new != XEXP (x
, i
) && ! copied
)
2707 x
= shallow_copy_rtx (x
);
2712 else if (*fmt
== 'E')
2715 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2717 new = eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false);
2718 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
2720 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2724 x
= shallow_copy_rtx (x
);
2727 XVEC (x
, i
) = new_v
;
2730 XVECEXP (x
, i
, j
) = new;
2739 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2741 return eliminate_regs_1 (x
, mem_mode
, insn
, false);
2744 /* Scan rtx X for modifications of elimination target registers. Update
2745 the table of eliminables to reflect the changed state. MEM_MODE is
2746 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2749 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2751 enum rtx_code code
= GET_CODE (x
);
2752 struct elim_table
*ep
;
2776 /* First handle the case where we encounter a bare register that
2777 is eliminable. Replace it with a PLUS. */
2778 if (regno
< FIRST_PSEUDO_REGISTER
)
2780 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2782 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2785 ep
->ref_outside_mem
= 1;
2790 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2791 && reg_equiv_constant
[regno
]
2792 && ! function_invariant_p (reg_equiv_constant
[regno
]))
2793 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2802 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2803 if (ep
->to_rtx
== XEXP (x
, 0))
2805 int size
= GET_MODE_SIZE (mem_mode
);
2807 /* If more bytes than MEM_MODE are pushed, account for them. */
2808 #ifdef PUSH_ROUNDING
2809 if (ep
->to_rtx
== stack_pointer_rtx
)
2810 size
= PUSH_ROUNDING (size
);
2812 if (code
== PRE_DEC
|| code
== POST_DEC
)
2814 else if (code
== PRE_INC
|| code
== POST_INC
)
2816 else if ((code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2817 && GET_CODE (XEXP (x
, 1)) == PLUS
2818 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
2819 && CONSTANT_P (XEXP (XEXP (x
, 1), 1)))
2820 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
2823 /* These two aren't unary operators. */
2824 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
2827 /* Fall through to generic unary operation case. */
2828 case STRICT_LOW_PART
:
2830 case SIGN_EXTEND
: case ZERO_EXTEND
:
2831 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2832 case FLOAT
: case FIX
:
2833 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2842 elimination_effects (XEXP (x
, 0), mem_mode
);
2846 if (REG_P (SUBREG_REG (x
))
2847 && (GET_MODE_SIZE (GET_MODE (x
))
2848 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2849 && reg_equiv_memory_loc
!= 0
2850 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2853 elimination_effects (SUBREG_REG (x
), mem_mode
);
2857 /* If using a register that is the source of an eliminate we still
2858 think can be performed, note it cannot be performed since we don't
2859 know how this register is used. */
2860 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2861 if (ep
->from_rtx
== XEXP (x
, 0))
2862 ep
->can_eliminate
= 0;
2864 elimination_effects (XEXP (x
, 0), mem_mode
);
2868 /* If clobbering a register that is the replacement register for an
2869 elimination we still think can be performed, note that it cannot
2870 be performed. Otherwise, we need not be concerned about it. */
2871 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2872 if (ep
->to_rtx
== XEXP (x
, 0))
2873 ep
->can_eliminate
= 0;
2875 elimination_effects (XEXP (x
, 0), mem_mode
);
2879 /* Check for setting a register that we know about. */
2880 if (REG_P (SET_DEST (x
)))
2882 /* See if this is setting the replacement register for an
2885 If DEST is the hard frame pointer, we do nothing because we
2886 assume that all assignments to the frame pointer are for
2887 non-local gotos and are being done at a time when they are valid
2888 and do not disturb anything else. Some machines want to
2889 eliminate a fake argument pointer (or even a fake frame pointer)
2890 with either the real frame or the stack pointer. Assignments to
2891 the hard frame pointer must not prevent this elimination. */
2893 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2895 if (ep
->to_rtx
== SET_DEST (x
)
2896 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2898 /* If it is being incremented, adjust the offset. Otherwise,
2899 this elimination can't be done. */
2900 rtx src
= SET_SRC (x
);
2902 if (GET_CODE (src
) == PLUS
2903 && XEXP (src
, 0) == SET_DEST (x
)
2904 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2905 ep
->offset
-= INTVAL (XEXP (src
, 1));
2907 ep
->can_eliminate
= 0;
2911 elimination_effects (SET_DEST (x
), 0);
2912 elimination_effects (SET_SRC (x
), 0);
2916 /* Our only special processing is to pass the mode of the MEM to our
2918 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
2925 fmt
= GET_RTX_FORMAT (code
);
2926 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2929 elimination_effects (XEXP (x
, i
), mem_mode
);
2930 else if (*fmt
== 'E')
2931 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2932 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
2936 /* Descend through rtx X and verify that no references to eliminable registers
2937 remain. If any do remain, mark the involved register as not
2941 check_eliminable_occurrences (rtx x
)
2950 code
= GET_CODE (x
);
2952 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2954 struct elim_table
*ep
;
2956 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2957 if (ep
->from_rtx
== x
)
2958 ep
->can_eliminate
= 0;
2962 fmt
= GET_RTX_FORMAT (code
);
2963 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2966 check_eliminable_occurrences (XEXP (x
, i
));
2967 else if (*fmt
== 'E')
2970 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2971 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
2976 /* Scan INSN and eliminate all eliminable registers in it.
2978 If REPLACE is nonzero, do the replacement destructively. Also
2979 delete the insn as dead it if it is setting an eliminable register.
2981 If REPLACE is zero, do all our allocations in reload_obstack.
2983 If no eliminations were done and this insn doesn't require any elimination
2984 processing (these are not identical conditions: it might be updating sp,
2985 but not referencing fp; this needs to be seen during reload_as_needed so
2986 that the offset between fp and sp can be taken into consideration), zero
2987 is returned. Otherwise, 1 is returned. */
2990 eliminate_regs_in_insn (rtx insn
, int replace
)
2992 int icode
= recog_memoized (insn
);
2993 rtx old_body
= PATTERN (insn
);
2994 int insn_is_asm
= asm_noperands (old_body
) >= 0;
2995 rtx old_set
= single_set (insn
);
2999 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3000 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3001 struct elim_table
*ep
;
3002 rtx plus_src
, plus_cst_src
;
3004 if (! insn_is_asm
&& icode
< 0)
3006 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
3007 || GET_CODE (PATTERN (insn
)) == CLOBBER
3008 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
3009 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3010 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3014 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3015 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3017 /* Check for setting an eliminable register. */
3018 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3019 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3021 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3022 /* If this is setting the frame pointer register to the
3023 hardware frame pointer register and this is an elimination
3024 that will be done (tested above), this insn is really
3025 adjusting the frame pointer downward to compensate for
3026 the adjustment done before a nonlocal goto. */
3027 if (ep
->from
== FRAME_POINTER_REGNUM
3028 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3030 rtx base
= SET_SRC (old_set
);
3031 rtx base_insn
= insn
;
3032 HOST_WIDE_INT offset
= 0;
3034 while (base
!= ep
->to_rtx
)
3036 rtx prev_insn
, prev_set
;
3038 if (GET_CODE (base
) == PLUS
3039 && GET_CODE (XEXP (base
, 1)) == CONST_INT
)
3041 offset
+= INTVAL (XEXP (base
, 1));
3042 base
= XEXP (base
, 0);
3044 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3045 && (prev_set
= single_set (prev_insn
)) != 0
3046 && rtx_equal_p (SET_DEST (prev_set
), base
))
3048 base
= SET_SRC (prev_set
);
3049 base_insn
= prev_insn
;
3055 if (base
== ep
->to_rtx
)
3058 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3060 new_body
= old_body
;
3063 new_body
= copy_insn (old_body
);
3064 if (REG_NOTES (insn
))
3065 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3067 PATTERN (insn
) = new_body
;
3068 old_set
= single_set (insn
);
3070 /* First see if this insn remains valid when we
3071 make the change. If not, keep the INSN_CODE
3072 the same and let reload fit it up. */
3073 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3074 validate_change (insn
, &SET_DEST (old_set
),
3076 if (! apply_change_group ())
3078 SET_SRC (old_set
) = src
;
3079 SET_DEST (old_set
) = ep
->to_rtx
;
3088 /* In this case this insn isn't serving a useful purpose. We
3089 will delete it in reload_as_needed once we know that this
3090 elimination is, in fact, being done.
3092 If REPLACE isn't set, we can't delete this insn, but needn't
3093 process it since it won't be used unless something changes. */
3096 delete_dead_insn (insn
);
3104 /* We allow one special case which happens to work on all machines we
3105 currently support: a single set with the source or a REG_EQUAL
3106 note being a PLUS of an eliminable register and a constant. */
3107 plus_src
= plus_cst_src
= 0;
3108 if (old_set
&& REG_P (SET_DEST (old_set
)))
3110 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3111 plus_src
= SET_SRC (old_set
);
3112 /* First see if the source is of the form (plus (...) CST). */
3114 && GET_CODE (XEXP (plus_src
, 1)) == CONST_INT
)
3115 plus_cst_src
= plus_src
;
3116 else if (REG_P (SET_SRC (old_set
))
3119 /* Otherwise, see if we have a REG_EQUAL note of the form
3120 (plus (...) CST). */
3122 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3124 if (REG_NOTE_KIND (links
) == REG_EQUAL
3125 && GET_CODE (XEXP (links
, 0)) == PLUS
3126 && GET_CODE (XEXP (XEXP (links
, 0), 1)) == CONST_INT
)
3128 plus_cst_src
= XEXP (links
, 0);
3134 /* Check that the first operand of the PLUS is a hard reg or
3135 the lowpart subreg of one. */
3138 rtx reg
= XEXP (plus_cst_src
, 0);
3139 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3140 reg
= SUBREG_REG (reg
);
3142 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3148 rtx reg
= XEXP (plus_cst_src
, 0);
3149 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3151 if (GET_CODE (reg
) == SUBREG
)
3152 reg
= SUBREG_REG (reg
);
3154 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3155 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3157 rtx to_rtx
= ep
->to_rtx
;
3158 offset
+= ep
->offset
;
3160 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3161 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3166 /* We assume here that if we need a PARALLEL with
3167 CLOBBERs for this assignment, we can do with the
3168 MATCH_SCRATCHes that add_clobbers allocates.
3169 There's not much we can do if that doesn't work. */
3170 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3174 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, &num_clobbers
);
3177 rtvec vec
= rtvec_alloc (num_clobbers
+ 1);
3179 vec
->elem
[0] = PATTERN (insn
);
3180 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
3181 add_clobbers (PATTERN (insn
), INSN_CODE (insn
));
3183 gcc_assert (INSN_CODE (insn
) >= 0);
3185 /* If we have a nonzero offset, and the source is already
3186 a simple REG, the following transformation would
3187 increase the cost of the insn by replacing a simple REG
3188 with (plus (reg sp) CST). So try only when we already
3189 had a PLUS before. */
3192 new_body
= old_body
;
3195 new_body
= copy_insn (old_body
);
3196 if (REG_NOTES (insn
))
3197 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3199 PATTERN (insn
) = new_body
;
3200 old_set
= single_set (insn
);
3202 XEXP (SET_SRC (old_set
), 0) = to_rtx
;
3203 XEXP (SET_SRC (old_set
), 1) = GEN_INT (offset
);
3209 /* This can't have an effect on elimination offsets, so skip right
3215 /* Determine the effects of this insn on elimination offsets. */
3216 elimination_effects (old_body
, 0);
3218 /* Eliminate all eliminable registers occurring in operands that
3219 can be handled by reload. */
3220 extract_insn (insn
);
3221 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3223 orig_operand
[i
] = recog_data
.operand
[i
];
3224 substed_operand
[i
] = recog_data
.operand
[i
];
3226 /* For an asm statement, every operand is eliminable. */
3227 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3229 bool is_set_src
, in_plus
;
3231 /* Check for setting a register that we know about. */
3232 if (recog_data
.operand_type
[i
] != OP_IN
3233 && REG_P (orig_operand
[i
]))
3235 /* If we are assigning to a register that can be eliminated, it
3236 must be as part of a PARALLEL, since the code above handles
3237 single SETs. We must indicate that we can no longer
3238 eliminate this reg. */
3239 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3241 if (ep
->from_rtx
== orig_operand
[i
])
3242 ep
->can_eliminate
= 0;
3245 /* Companion to the above plus substitution, we can allow
3246 invariants as the source of a plain move. */
3248 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3252 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3253 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3257 = eliminate_regs_1 (recog_data
.operand
[i
], 0,
3258 replace
? insn
: NULL_RTX
,
3259 is_set_src
|| in_plus
);
3260 if (substed_operand
[i
] != orig_operand
[i
])
3262 /* Terminate the search in check_eliminable_occurrences at
3264 *recog_data
.operand_loc
[i
] = 0;
3266 /* If an output operand changed from a REG to a MEM and INSN is an
3267 insn, write a CLOBBER insn. */
3268 if (recog_data
.operand_type
[i
] != OP_IN
3269 && REG_P (orig_operand
[i
])
3270 && MEM_P (substed_operand
[i
])
3272 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, orig_operand
[i
]),
3277 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3278 *recog_data
.dup_loc
[i
]
3279 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3281 /* If any eliminable remain, they aren't eliminable anymore. */
3282 check_eliminable_occurrences (old_body
);
3284 /* Substitute the operands; the new values are in the substed_operand
3286 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3287 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3288 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3289 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3291 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3292 re-recognize the insn. We do this in case we had a simple addition
3293 but now can do this as a load-address. This saves an insn in this
3295 If re-recognition fails, the old insn code number will still be used,
3296 and some register operands may have changed into PLUS expressions.
3297 These will be handled by find_reloads by loading them into a register
3302 /* If we aren't replacing things permanently and we changed something,
3303 make another copy to ensure that all the RTL is new. Otherwise
3304 things can go wrong if find_reload swaps commutative operands
3305 and one is inside RTL that has been copied while the other is not. */
3306 new_body
= old_body
;
3309 new_body
= copy_insn (old_body
);
3310 if (REG_NOTES (insn
))
3311 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3313 PATTERN (insn
) = new_body
;
3315 /* If we had a move insn but now we don't, rerecognize it. This will
3316 cause spurious re-recognition if the old move had a PARALLEL since
3317 the new one still will, but we can't call single_set without
3318 having put NEW_BODY into the insn and the re-recognition won't
3319 hurt in this rare case. */
3320 /* ??? Why this huge if statement - why don't we just rerecognize the
3324 && ((REG_P (SET_SRC (old_set
))
3325 && (GET_CODE (new_body
) != SET
3326 || !REG_P (SET_SRC (new_body
))))
3327 /* If this was a load from or store to memory, compare
3328 the MEM in recog_data.operand to the one in the insn.
3329 If they are not equal, then rerecognize the insn. */
3331 && ((MEM_P (SET_SRC (old_set
))
3332 && SET_SRC (old_set
) != recog_data
.operand
[1])
3333 || (MEM_P (SET_DEST (old_set
))
3334 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3335 /* If this was an add insn before, rerecognize. */
3336 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3338 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3340 INSN_CODE (insn
) = new_icode
;
3344 /* Restore the old body. If there were any changes to it, we made a copy
3345 of it while the changes were still in place, so we'll correctly return
3346 a modified insn below. */
3349 /* Restore the old body. */
3350 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3351 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3352 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3353 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3356 /* Update all elimination pairs to reflect the status after the current
3357 insn. The changes we make were determined by the earlier call to
3358 elimination_effects.
3360 We also detect cases where register elimination cannot be done,
3361 namely, if a register would be both changed and referenced outside a MEM
3362 in the resulting insn since such an insn is often undefined and, even if
3363 not, we cannot know what meaning will be given to it. Note that it is
3364 valid to have a register used in an address in an insn that changes it
3365 (presumably with a pre- or post-increment or decrement).
3367 If anything changes, return nonzero. */
3369 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3371 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3372 ep
->can_eliminate
= 0;
3374 ep
->ref_outside_mem
= 0;
3376 if (ep
->previous_offset
!= ep
->offset
)
3381 /* If we changed something, perform elimination in REG_NOTES. This is
3382 needed even when REPLACE is zero because a REG_DEAD note might refer
3383 to a register that we eliminate and could cause a different number
3384 of spill registers to be needed in the final reload pass than in
3386 if (val
&& REG_NOTES (insn
) != 0)
3388 = eliminate_regs_1 (REG_NOTES (insn
), 0, REG_NOTES (insn
), true);
3393 /* Loop through all elimination pairs.
3394 Recalculate the number not at initial offset.
3396 Compute the maximum offset (minimum offset if the stack does not
3397 grow downward) for each elimination pair. */
3400 update_eliminable_offsets (void)
3402 struct elim_table
*ep
;
3404 num_not_at_initial_offset
= 0;
3405 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3407 ep
->previous_offset
= ep
->offset
;
3408 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3409 num_not_at_initial_offset
++;
3413 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3414 replacement we currently believe is valid, mark it as not eliminable if X
3415 modifies DEST in any way other than by adding a constant integer to it.
3417 If DEST is the frame pointer, we do nothing because we assume that
3418 all assignments to the hard frame pointer are nonlocal gotos and are being
3419 done at a time when they are valid and do not disturb anything else.
3420 Some machines want to eliminate a fake argument pointer with either the
3421 frame or stack pointer. Assignments to the hard frame pointer must not
3422 prevent this elimination.
3424 Called via note_stores from reload before starting its passes to scan
3425 the insns of the function. */
3428 mark_not_eliminable (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
3432 /* A SUBREG of a hard register here is just changing its mode. We should
3433 not see a SUBREG of an eliminable hard register, but check just in
3435 if (GET_CODE (dest
) == SUBREG
)
3436 dest
= SUBREG_REG (dest
);
3438 if (dest
== hard_frame_pointer_rtx
)
3441 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3442 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3443 && (GET_CODE (x
) != SET
3444 || GET_CODE (SET_SRC (x
)) != PLUS
3445 || XEXP (SET_SRC (x
), 0) != dest
3446 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3448 reg_eliminate
[i
].can_eliminate_previous
3449 = reg_eliminate
[i
].can_eliminate
= 0;
3454 /* Verify that the initial elimination offsets did not change since the
3455 last call to set_initial_elim_offsets. This is used to catch cases
3456 where something illegal happened during reload_as_needed that could
3457 cause incorrect code to be generated if we did not check for it. */
3460 verify_initial_elim_offsets (void)
3464 if (!num_eliminable
)
3467 #ifdef ELIMINABLE_REGS
3469 struct elim_table
*ep
;
3471 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3473 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3474 if (t
!= ep
->initial_offset
)
3479 INITIAL_FRAME_POINTER_OFFSET (t
);
3480 if (t
!= reg_eliminate
[0].initial_offset
)
3487 /* Reset all offsets on eliminable registers to their initial values. */
3490 set_initial_elim_offsets (void)
3492 struct elim_table
*ep
= reg_eliminate
;
3494 #ifdef ELIMINABLE_REGS
3495 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3497 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3498 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3501 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3502 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3505 num_not_at_initial_offset
= 0;
3508 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3511 set_initial_eh_label_offset (rtx label
)
3513 set_label_offsets (label
, NULL_RTX
, 1);
3516 /* Initialize the known label offsets.
3517 Set a known offset for each forced label to be at the initial offset
3518 of each elimination. We do this because we assume that all
3519 computed jumps occur from a location where each elimination is
3520 at its initial offset.
3521 For all other labels, show that we don't know the offsets. */
3524 set_initial_label_offsets (void)
3527 memset (offsets_known_at
, 0, num_labels
);
3529 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3531 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3533 for_each_eh_label (set_initial_eh_label_offset
);
3536 /* Set all elimination offsets to the known values for the code label given
3540 set_offsets_for_label (rtx insn
)
3543 int label_nr
= CODE_LABEL_NUMBER (insn
);
3544 struct elim_table
*ep
;
3546 num_not_at_initial_offset
= 0;
3547 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3549 ep
->offset
= ep
->previous_offset
3550 = offsets_at
[label_nr
- first_label_num
][i
];
3551 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3552 num_not_at_initial_offset
++;
3556 /* See if anything that happened changes which eliminations are valid.
3557 For example, on the SPARC, whether or not the frame pointer can
3558 be eliminated can depend on what registers have been used. We need
3559 not check some conditions again (such as flag_omit_frame_pointer)
3560 since they can't have changed. */
3563 update_eliminables (HARD_REG_SET
*pset
)
3565 int previous_frame_pointer_needed
= frame_pointer_needed
;
3566 struct elim_table
*ep
;
3568 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3569 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3570 #ifdef ELIMINABLE_REGS
3571 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3574 ep
->can_eliminate
= 0;
3576 /* Look for the case where we have discovered that we can't replace
3577 register A with register B and that means that we will now be
3578 trying to replace register A with register C. This means we can
3579 no longer replace register C with register B and we need to disable
3580 such an elimination, if it exists. This occurs often with A == ap,
3581 B == sp, and C == fp. */
3583 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3585 struct elim_table
*op
;
3588 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3590 /* Find the current elimination for ep->from, if there is a
3592 for (op
= reg_eliminate
;
3593 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3594 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3600 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3602 for (op
= reg_eliminate
;
3603 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3604 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3605 op
->can_eliminate
= 0;
3609 /* See if any registers that we thought we could eliminate the previous
3610 time are no longer eliminable. If so, something has changed and we
3611 must spill the register. Also, recompute the number of eliminable
3612 registers and see if the frame pointer is needed; it is if there is
3613 no elimination of the frame pointer that we can perform. */
3615 frame_pointer_needed
= 1;
3616 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3618 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3619 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3620 frame_pointer_needed
= 0;
3622 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3624 ep
->can_eliminate_previous
= 0;
3625 SET_HARD_REG_BIT (*pset
, ep
->from
);
3630 /* If we didn't need a frame pointer last time, but we do now, spill
3631 the hard frame pointer. */
3632 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3633 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3636 /* Initialize the table of registers to eliminate. */
3639 init_elim_table (void)
3641 struct elim_table
*ep
;
3642 #ifdef ELIMINABLE_REGS
3643 const struct elim_table_1
*ep1
;
3647 reg_eliminate
= xcalloc (sizeof (struct elim_table
), NUM_ELIMINABLE_REGS
);
3649 /* Does this function require a frame pointer? */
3651 frame_pointer_needed
= (! flag_omit_frame_pointer
3652 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3653 and restore sp for alloca. So we can't eliminate
3654 the frame pointer in that case. At some point,
3655 we should improve this by emitting the
3656 sp-adjusting insns for this case. */
3657 || (current_function_calls_alloca
3658 && EXIT_IGNORE_STACK
)
3659 || current_function_accesses_prior_frames
3660 || FRAME_POINTER_REQUIRED
);
3664 #ifdef ELIMINABLE_REGS
3665 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3666 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3668 ep
->from
= ep1
->from
;
3670 ep
->can_eliminate
= ep
->can_eliminate_previous
3671 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3672 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3675 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3676 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3677 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3678 = ! frame_pointer_needed
;
3681 /* Count the number of eliminable registers and build the FROM and TO
3682 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3683 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3684 We depend on this. */
3685 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3687 num_eliminable
+= ep
->can_eliminate
;
3688 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3689 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3693 /* Kick all pseudos out of hard register REGNO.
3695 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3696 because we found we can't eliminate some register. In the case, no pseudos
3697 are allowed to be in the register, even if they are only in a block that
3698 doesn't require spill registers, unlike the case when we are spilling this
3699 hard reg to produce another spill register.
3701 Return nonzero if any pseudos needed to be kicked out. */
3704 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
3710 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3711 regs_ever_live
[regno
] = 1;
3714 /* Spill every pseudo reg that was allocated to this reg
3715 or to something that overlaps this reg. */
3717 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3718 if (reg_renumber
[i
] >= 0
3719 && (unsigned int) reg_renumber
[i
] <= regno
3720 && ((unsigned int) reg_renumber
[i
]
3721 + hard_regno_nregs
[(unsigned int) reg_renumber
[i
]]
3722 [PSEUDO_REGNO_MODE (i
)]
3724 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3727 /* After find_reload_regs has been run for all insn that need reloads,
3728 and/or spill_hard_regs was called, this function is used to actually
3729 spill pseudo registers and try to reallocate them. It also sets up the
3730 spill_regs array for use by choose_reload_regs. */
3733 finish_spills (int global
)
3735 struct insn_chain
*chain
;
3736 int something_changed
= 0;
3738 reg_set_iterator rsi
;
3740 /* Build the spill_regs array for the function. */
3741 /* If there are some registers still to eliminate and one of the spill regs
3742 wasn't ever used before, additional stack space may have to be
3743 allocated to store this register. Thus, we may have changed the offset
3744 between the stack and frame pointers, so mark that something has changed.
3746 One might think that we need only set VAL to 1 if this is a call-used
3747 register. However, the set of registers that must be saved by the
3748 prologue is not identical to the call-used set. For example, the
3749 register used by the call insn for the return PC is a call-used register,
3750 but must be saved by the prologue. */
3753 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3754 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3756 spill_reg_order
[i
] = n_spills
;
3757 spill_regs
[n_spills
++] = i
;
3758 if (num_eliminable
&& ! regs_ever_live
[i
])
3759 something_changed
= 1;
3760 regs_ever_live
[i
] = 1;
3763 spill_reg_order
[i
] = -1;
3765 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3767 /* Record the current hard register the pseudo is allocated to in
3768 pseudo_previous_regs so we avoid reallocating it to the same
3769 hard reg in a later pass. */
3770 gcc_assert (reg_renumber
[i
] >= 0);
3772 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3773 /* Mark it as no longer having a hard register home. */
3774 reg_renumber
[i
] = -1;
3776 mark_allocation_change (i
);
3777 /* We will need to scan everything again. */
3778 something_changed
= 1;
3781 /* Retry global register allocation if possible. */
3784 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
3785 /* For every insn that needs reloads, set the registers used as spill
3786 regs in pseudo_forbidden_regs for every pseudo live across the
3788 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3790 EXECUTE_IF_SET_IN_REG_SET
3791 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3793 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3794 chain
->used_spill_regs
);
3796 EXECUTE_IF_SET_IN_REG_SET
3797 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
3799 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
3800 chain
->used_spill_regs
);
3804 /* Retry allocating the spilled pseudos. For each reg, merge the
3805 various reg sets that indicate which hard regs can't be used,
3806 and call retry_global_alloc.
3807 We change spill_pseudos here to only contain pseudos that did not
3808 get a new hard register. */
3809 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
3810 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3812 HARD_REG_SET forbidden
;
3814 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3815 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3816 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3819 /* We might migrate pseudo to another hard register on
3820 previous iteration. So check this. */
3821 if (reg_renumber
[i
] < 0)
3823 retry_ira_color (i
, forbidden
);
3824 if (reg_renumber
[i
] >= 0)
3825 something_changed
= 1;
3829 retry_global_alloc (i
, forbidden
);
3830 if (reg_renumber
[i
] >= 0)
3831 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
3835 /* Fix up the register information in the insn chain.
3836 This involves deleting those of the spilled pseudos which did not get
3837 a new hard register home from the live_{before,after} sets. */
3838 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3840 HARD_REG_SET used_by_pseudos
;
3841 HARD_REG_SET used_by_pseudos2
;
3843 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
3844 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
3846 /* Mark any unallocated hard regs as available for spills. That
3847 makes inheritance work somewhat better. */
3848 if (chain
->need_reload
)
3850 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
3851 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
3852 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3854 /* Save the old value for the sanity test below. */
3855 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3857 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
3858 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
3859 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3860 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3862 /* Make sure we only enlarge the set. */
3863 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3869 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3870 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
3872 int regno
= reg_renumber
[i
];
3873 if (reg_old_renumber
[i
] == regno
)
3876 alter_reg (i
, reg_old_renumber
[i
], false);
3877 reg_old_renumber
[i
] = regno
;
3881 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
3883 fprintf (dump_file
, " Register %d now in %d.\n\n",
3884 i
, reg_renumber
[i
]);
3888 return something_changed
;
3891 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3894 scan_paradoxical_subregs (rtx x
)
3898 enum rtx_code code
= GET_CODE (x
);
3908 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
3916 if (REG_P (SUBREG_REG (x
))
3917 && (GET_MODE_SIZE (GET_MODE (x
))
3918 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
3919 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3920 = GET_MODE_SIZE (GET_MODE (x
));
3927 fmt
= GET_RTX_FORMAT (code
);
3928 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3931 scan_paradoxical_subregs (XEXP (x
, i
));
3932 else if (fmt
[i
] == 'E')
3935 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3936 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3941 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3942 examine all of the reload insns between PREV and NEXT exclusive, and
3943 annotate all that may trap. */
3946 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
3948 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3949 unsigned int trap_count
;
3955 if (may_trap_p (PATTERN (insn
)))
3959 remove_note (insn
, note
);
3963 for (i
= NEXT_INSN (prev
); i
!= next
; i
= NEXT_INSN (i
))
3964 if (INSN_P (i
) && i
!= insn
&& may_trap_p (PATTERN (i
)))
3968 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (note
, 0), REG_NOTES (i
));
3972 /* Reload pseudo-registers into hard regs around each insn as needed.
3973 Additional register load insns are output before the insn that needs it
3974 and perhaps store insns after insns that modify the reloaded pseudo reg.
3976 reg_last_reload_reg and reg_reloaded_contents keep track of
3977 which registers are already available in reload registers.
3978 We update these for the reloads that we perform,
3979 as the insns are scanned. */
3982 reload_as_needed (int live_known
)
3984 struct insn_chain
*chain
;
3985 #if defined (AUTO_INC_DEC)
3990 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
3991 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
3992 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
3993 INIT_REG_SET (®_has_output_reload
);
3994 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
3995 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
3997 set_initial_elim_offsets ();
3999 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4002 rtx insn
= chain
->insn
;
4003 rtx old_next
= NEXT_INSN (insn
);
4005 /* If we pass a label, copy the offsets from the label information
4006 into the current offsets of each elimination. */
4008 set_offsets_for_label (insn
);
4010 else if (INSN_P (insn
))
4012 regset_head regs_to_forget
;
4013 INIT_REG_SET (®s_to_forget
);
4014 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4016 /* If this is a USE and CLOBBER of a MEM, ensure that any
4017 references to eliminable registers have been removed. */
4019 if ((GET_CODE (PATTERN (insn
)) == USE
4020 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4021 && MEM_P (XEXP (PATTERN (insn
), 0)))
4022 XEXP (XEXP (PATTERN (insn
), 0), 0)
4023 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4024 GET_MODE (XEXP (PATTERN (insn
), 0)),
4027 /* If we need to do register elimination processing, do so.
4028 This might delete the insn, in which case we are done. */
4029 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4031 eliminate_regs_in_insn (insn
, 1);
4034 update_eliminable_offsets ();
4035 CLEAR_REG_SET (®s_to_forget
);
4040 /* If need_elim is nonzero but need_reload is zero, one might think
4041 that we could simply set n_reloads to 0. However, find_reloads
4042 could have done some manipulation of the insn (such as swapping
4043 commutative operands), and these manipulations are lost during
4044 the first pass for every insn that needs register elimination.
4045 So the actions of find_reloads must be redone here. */
4047 if (! chain
->need_elim
&& ! chain
->need_reload
4048 && ! chain
->need_operand_change
)
4050 /* First find the pseudo regs that must be reloaded for this insn.
4051 This info is returned in the tables reload_... (see reload.h).
4052 Also modify the body of INSN by substituting RELOAD
4053 rtx's for those pseudo regs. */
4056 CLEAR_REG_SET (®_has_output_reload
);
4057 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4059 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4065 rtx next
= NEXT_INSN (insn
);
4068 prev
= PREV_INSN (insn
);
4070 /* Now compute which reload regs to reload them into. Perhaps
4071 reusing reload regs from previous insns, or else output
4072 load insns to reload them. Maybe output store insns too.
4073 Record the choices of reload reg in reload_reg_rtx. */
4074 choose_reload_regs (chain
);
4076 /* Merge any reloads that we didn't combine for fear of
4077 increasing the number of spill registers needed but now
4078 discover can be safely merged. */
4079 if (SMALL_REGISTER_CLASSES
)
4080 merge_assigned_reloads (insn
);
4082 /* Generate the insns to reload operands into or out of
4083 their reload regs. */
4084 emit_reload_insns (chain
);
4086 /* Substitute the chosen reload regs from reload_reg_rtx
4087 into the insn's body (or perhaps into the bodies of other
4088 load and store insn that we just made for reloading
4089 and that we moved the structure into). */
4090 subst_reloads (insn
);
4092 /* Adjust the exception region notes for loads and stores. */
4093 if (flag_non_call_exceptions
&& !CALL_P (insn
))
4094 fixup_eh_region_note (insn
, prev
, next
);
4096 /* If this was an ASM, make sure that all the reload insns
4097 we have generated are valid. If not, give an error
4099 if (asm_noperands (PATTERN (insn
)) >= 0)
4100 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4101 if (p
!= insn
&& INSN_P (p
)
4102 && GET_CODE (PATTERN (p
)) != USE
4103 && (recog_memoized (p
) < 0
4104 || (extract_insn (p
), ! constrain_operands (1))))
4106 error_for_asm (insn
,
4107 "%<asm%> operand requires "
4108 "impossible reload");
4113 if (num_eliminable
&& chain
->need_elim
)
4114 update_eliminable_offsets ();
4116 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4117 is no longer validly lying around to save a future reload.
4118 Note that this does not detect pseudos that were reloaded
4119 for this insn in order to be stored in
4120 (obeying register constraints). That is correct; such reload
4121 registers ARE still valid. */
4122 forget_marked_reloads (®s_to_forget
);
4123 CLEAR_REG_SET (®s_to_forget
);
4125 /* There may have been CLOBBER insns placed after INSN. So scan
4126 between INSN and NEXT and use them to forget old reloads. */
4127 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4128 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4129 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4132 /* Likewise for regs altered by auto-increment in this insn.
4133 REG_INC notes have been changed by reloading:
4134 find_reloads_address_1 records substitutions for them,
4135 which have been performed by subst_reloads above. */
4136 for (i
= n_reloads
- 1; i
>= 0; i
--)
4138 rtx in_reg
= rld
[i
].in_reg
;
4141 enum rtx_code code
= GET_CODE (in_reg
);
4142 /* PRE_INC / PRE_DEC will have the reload register ending up
4143 with the same value as the stack slot, but that doesn't
4144 hold true for POST_INC / POST_DEC. Either we have to
4145 convert the memory access to a true POST_INC / POST_DEC,
4146 or we can't use the reload register for inheritance. */
4147 if ((code
== POST_INC
|| code
== POST_DEC
)
4148 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4149 REGNO (rld
[i
].reg_rtx
))
4150 /* Make sure it is the inc/dec pseudo, and not
4151 some other (e.g. output operand) pseudo. */
4152 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4153 == REGNO (XEXP (in_reg
, 0))))
4156 rtx reload_reg
= rld
[i
].reg_rtx
;
4157 enum machine_mode mode
= GET_MODE (reload_reg
);
4161 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4163 /* We really want to ignore REG_INC notes here, so
4164 use PATTERN (p) as argument to reg_set_p . */
4165 if (reg_set_p (reload_reg
, PATTERN (p
)))
4167 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4172 n
= validate_replace_rtx (reload_reg
,
4173 gen_rtx_fmt_e (code
,
4178 /* We must also verify that the constraints
4179 are met after the replacement. */
4182 n
= constrain_operands (1);
4186 /* If the constraints were not met, then
4187 undo the replacement. */
4190 validate_replace_rtx (gen_rtx_fmt_e (code
,
4203 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4205 /* Mark this as having an output reload so that the
4206 REG_INC processing code below won't invalidate
4207 the reload for inheritance. */
4208 SET_HARD_REG_BIT (reg_is_output_reload
,
4209 REGNO (reload_reg
));
4210 SET_REGNO_REG_SET (®_has_output_reload
,
4211 REGNO (XEXP (in_reg
, 0)));
4214 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4217 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4218 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4219 REGNO (rld
[i
].reg_rtx
))
4220 /* Make sure it is the inc/dec pseudo, and not
4221 some other (e.g. output operand) pseudo. */
4222 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4223 == REGNO (XEXP (in_reg
, 0))))
4225 SET_HARD_REG_BIT (reg_is_output_reload
,
4226 REGNO (rld
[i
].reg_rtx
));
4227 SET_REGNO_REG_SET (®_has_output_reload
,
4228 REGNO (XEXP (in_reg
, 0)));
4232 /* If a pseudo that got a hard register is auto-incremented,
4233 we must purge records of copying it into pseudos without
4235 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4236 if (REG_NOTE_KIND (x
) == REG_INC
)
4238 /* See if this pseudo reg was reloaded in this insn.
4239 If so, its last-reload info is still valid
4240 because it is based on this insn's reload. */
4241 for (i
= 0; i
< n_reloads
; i
++)
4242 if (rld
[i
].out
== XEXP (x
, 0))
4246 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4250 /* A reload reg's contents are unknown after a label. */
4252 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4254 /* Don't assume a reload reg is still good after a call insn
4255 if it is a call-used reg, or if it contains a value that will
4256 be partially clobbered by the call. */
4257 else if (CALL_P (insn
))
4259 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4260 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4265 free (reg_last_reload_reg
);
4266 CLEAR_REG_SET (®_has_output_reload
);
4269 /* Discard all record of any value reloaded from X,
4270 or reloaded in X from someplace else;
4271 unless X is an output reload reg of the current insn.
4273 X may be a hard reg (the reload reg)
4274 or it may be a pseudo reg that was reloaded from.
4276 When DATA is non-NULL just mark the registers in regset
4277 to be forgotten later. */
4280 forget_old_reloads_1 (rtx x
, rtx ignored ATTRIBUTE_UNUSED
,
4285 regset regs
= (regset
) data
;
4287 /* note_stores does give us subregs of hard regs,
4288 subreg_regno_offset requires a hard reg. */
4289 while (GET_CODE (x
) == SUBREG
)
4291 /* We ignore the subreg offset when calculating the regno,
4292 because we are using the entire underlying hard register
4302 if (regno
>= FIRST_PSEUDO_REGISTER
)
4308 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4309 /* Storing into a spilled-reg invalidates its contents.
4310 This can happen if a block-local pseudo is allocated to that reg
4311 and it wasn't spilled because this block's total need is 0.
4312 Then some insn might have an optional reload and use this reg. */
4314 for (i
= 0; i
< nr
; i
++)
4315 /* But don't do this if the reg actually serves as an output
4316 reload reg in the current instruction. */
4318 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4320 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4321 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, regno
+ i
);
4322 spill_reg_store
[regno
+ i
] = 0;
4328 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4331 /* Since value of X has changed,
4332 forget any value previously copied from it. */
4335 /* But don't forget a copy if this is the output reload
4336 that establishes the copy's validity. */
4338 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4339 reg_last_reload_reg
[regno
+ nr
] = 0;
4343 /* Forget the reloads marked in regset by previous function. */
4345 forget_marked_reloads (regset regs
)
4348 reg_set_iterator rsi
;
4349 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4351 if (reg
< FIRST_PSEUDO_REGISTER
4352 /* But don't do this if the reg actually serves as an output
4353 reload reg in the current instruction. */
4355 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4357 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4358 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, reg
);
4359 spill_reg_store
[reg
] = 0;
4362 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4363 reg_last_reload_reg
[reg
] = 0;
4367 /* The following HARD_REG_SETs indicate when each hard register is
4368 used for a reload of various parts of the current insn. */
4370 /* If reg is unavailable for all reloads. */
4371 static HARD_REG_SET reload_reg_unavailable
;
4372 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4373 static HARD_REG_SET reload_reg_used
;
4374 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4375 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4376 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4377 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4378 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4379 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4380 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4381 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4382 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4383 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4384 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4385 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4386 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4387 static HARD_REG_SET reload_reg_used_in_op_addr
;
4388 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4389 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4390 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4391 static HARD_REG_SET reload_reg_used_in_insn
;
4392 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4393 static HARD_REG_SET reload_reg_used_in_other_addr
;
4395 /* If reg is in use as a reload reg for any sort of reload. */
4396 static HARD_REG_SET reload_reg_used_at_all
;
4398 /* If reg is use as an inherited reload. We just mark the first register
4400 static HARD_REG_SET reload_reg_used_for_inherit
;
4402 /* Records which hard regs are used in any way, either as explicit use or
4403 by being allocated to a pseudo during any point of the current insn. */
4404 static HARD_REG_SET reg_used_in_insn
;
4406 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4407 TYPE. MODE is used to indicate how many consecutive regs are
4411 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4412 enum machine_mode mode
)
4414 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4417 for (i
= regno
; i
< nregs
+ regno
; i
++)
4422 SET_HARD_REG_BIT (reload_reg_used
, i
);
4425 case RELOAD_FOR_INPUT_ADDRESS
:
4426 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4429 case RELOAD_FOR_INPADDR_ADDRESS
:
4430 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4433 case RELOAD_FOR_OUTPUT_ADDRESS
:
4434 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4437 case RELOAD_FOR_OUTADDR_ADDRESS
:
4438 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4441 case RELOAD_FOR_OPERAND_ADDRESS
:
4442 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4445 case RELOAD_FOR_OPADDR_ADDR
:
4446 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4449 case RELOAD_FOR_OTHER_ADDRESS
:
4450 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4453 case RELOAD_FOR_INPUT
:
4454 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4457 case RELOAD_FOR_OUTPUT
:
4458 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4461 case RELOAD_FOR_INSN
:
4462 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4466 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4470 /* Similarly, but show REGNO is no longer in use for a reload. */
4473 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
4474 enum reload_type type
, enum machine_mode mode
)
4476 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
4477 unsigned int start_regno
, end_regno
, r
;
4479 /* A complication is that for some reload types, inheritance might
4480 allow multiple reloads of the same types to share a reload register.
4481 We set check_opnum if we have to check only reloads with the same
4482 operand number, and check_any if we have to check all reloads. */
4483 int check_opnum
= 0;
4485 HARD_REG_SET
*used_in_set
;
4490 used_in_set
= &reload_reg_used
;
4493 case RELOAD_FOR_INPUT_ADDRESS
:
4494 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4497 case RELOAD_FOR_INPADDR_ADDRESS
:
4499 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4502 case RELOAD_FOR_OUTPUT_ADDRESS
:
4503 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4506 case RELOAD_FOR_OUTADDR_ADDRESS
:
4508 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4511 case RELOAD_FOR_OPERAND_ADDRESS
:
4512 used_in_set
= &reload_reg_used_in_op_addr
;
4515 case RELOAD_FOR_OPADDR_ADDR
:
4517 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4520 case RELOAD_FOR_OTHER_ADDRESS
:
4521 used_in_set
= &reload_reg_used_in_other_addr
;
4525 case RELOAD_FOR_INPUT
:
4526 used_in_set
= &reload_reg_used_in_input
[opnum
];
4529 case RELOAD_FOR_OUTPUT
:
4530 used_in_set
= &reload_reg_used_in_output
[opnum
];
4533 case RELOAD_FOR_INSN
:
4534 used_in_set
= &reload_reg_used_in_insn
;
4539 /* We resolve conflicts with remaining reloads of the same type by
4540 excluding the intervals of reload registers by them from the
4541 interval of freed reload registers. Since we only keep track of
4542 one set of interval bounds, we might have to exclude somewhat
4543 more than what would be necessary if we used a HARD_REG_SET here.
4544 But this should only happen very infrequently, so there should
4545 be no reason to worry about it. */
4547 start_regno
= regno
;
4548 end_regno
= regno
+ nregs
;
4549 if (check_opnum
|| check_any
)
4551 for (i
= n_reloads
- 1; i
>= 0; i
--)
4553 if (rld
[i
].when_needed
== type
4554 && (check_any
|| rld
[i
].opnum
== opnum
)
4557 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4558 unsigned int conflict_end
4560 + hard_regno_nregs
[conflict_start
][rld
[i
].mode
]);
4562 /* If there is an overlap with the first to-be-freed register,
4563 adjust the interval start. */
4564 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4565 start_regno
= conflict_end
;
4566 /* Otherwise, if there is a conflict with one of the other
4567 to-be-freed registers, adjust the interval end. */
4568 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4569 end_regno
= conflict_start
;
4574 for (r
= start_regno
; r
< end_regno
; r
++)
4575 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
4578 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4579 specified by OPNUM and TYPE. */
4582 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
4586 /* In use for a RELOAD_OTHER means it's not available for anything. */
4587 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4588 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4594 /* In use for anything means we can't use it for RELOAD_OTHER. */
4595 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4596 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4597 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4598 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4601 for (i
= 0; i
< reload_n_operands
; i
++)
4602 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4603 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4604 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4605 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4606 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4607 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4612 case RELOAD_FOR_INPUT
:
4613 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4614 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4617 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4620 /* If it is used for some other input, can't use it. */
4621 for (i
= 0; i
< reload_n_operands
; i
++)
4622 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4625 /* If it is used in a later operand's address, can't use it. */
4626 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4627 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4628 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4633 case RELOAD_FOR_INPUT_ADDRESS
:
4634 /* Can't use a register if it is used for an input address for this
4635 operand or used as an input in an earlier one. */
4636 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4637 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4640 for (i
= 0; i
< opnum
; i
++)
4641 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4646 case RELOAD_FOR_INPADDR_ADDRESS
:
4647 /* Can't use a register if it is used for an input address
4648 for this operand or used as an input in an earlier
4650 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4653 for (i
= 0; i
< opnum
; i
++)
4654 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4659 case RELOAD_FOR_OUTPUT_ADDRESS
:
4660 /* Can't use a register if it is used for an output address for this
4661 operand or used as an output in this or a later operand. Note
4662 that multiple output operands are emitted in reverse order, so
4663 the conflicting ones are those with lower indices. */
4664 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4667 for (i
= 0; i
<= opnum
; i
++)
4668 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4673 case RELOAD_FOR_OUTADDR_ADDRESS
:
4674 /* Can't use a register if it is used for an output address
4675 for this operand or used as an output in this or a
4676 later operand. Note that multiple output operands are
4677 emitted in reverse order, so the conflicting ones are
4678 those with lower indices. */
4679 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4682 for (i
= 0; i
<= opnum
; i
++)
4683 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4688 case RELOAD_FOR_OPERAND_ADDRESS
:
4689 for (i
= 0; i
< reload_n_operands
; i
++)
4690 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4693 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4694 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4696 case RELOAD_FOR_OPADDR_ADDR
:
4697 for (i
= 0; i
< reload_n_operands
; i
++)
4698 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4701 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4703 case RELOAD_FOR_OUTPUT
:
4704 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4705 outputs, or an operand address for this or an earlier output.
4706 Note that multiple output operands are emitted in reverse order,
4707 so the conflicting ones are those with higher indices. */
4708 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4711 for (i
= 0; i
< reload_n_operands
; i
++)
4712 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4715 for (i
= opnum
; i
< reload_n_operands
; i
++)
4716 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4717 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4722 case RELOAD_FOR_INSN
:
4723 for (i
= 0; i
< reload_n_operands
; i
++)
4724 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4725 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4728 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4729 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4731 case RELOAD_FOR_OTHER_ADDRESS
:
4732 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4739 /* Return 1 if the value in reload reg REGNO, as used by a reload
4740 needed for the part of the insn specified by OPNUM and TYPE,
4741 is still available in REGNO at the end of the insn.
4743 We can assume that the reload reg was already tested for availability
4744 at the time it is needed, and we should not check this again,
4745 in case the reg has already been marked in use. */
4748 reload_reg_reaches_end_p (unsigned int regno
, int opnum
, enum reload_type type
)
4755 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4756 its value must reach the end. */
4759 /* If this use is for part of the insn,
4760 its value reaches if no subsequent part uses the same register.
4761 Just like the above function, don't try to do this with lots
4764 case RELOAD_FOR_OTHER_ADDRESS
:
4765 /* Here we check for everything else, since these don't conflict
4766 with anything else and everything comes later. */
4768 for (i
= 0; i
< reload_n_operands
; i
++)
4769 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4770 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4771 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4772 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4773 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4774 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4777 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4778 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4779 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4780 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4782 case RELOAD_FOR_INPUT_ADDRESS
:
4783 case RELOAD_FOR_INPADDR_ADDRESS
:
4784 /* Similar, except that we check only for this and subsequent inputs
4785 and the address of only subsequent inputs and we do not need
4786 to check for RELOAD_OTHER objects since they are known not to
4789 for (i
= opnum
; i
< reload_n_operands
; i
++)
4790 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4793 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4794 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4795 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4798 for (i
= 0; i
< reload_n_operands
; i
++)
4799 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4800 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4801 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4804 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4807 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4808 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4809 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4811 case RELOAD_FOR_INPUT
:
4812 /* Similar to input address, except we start at the next operand for
4813 both input and input address and we do not check for
4814 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4817 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4818 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4819 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4820 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4823 /* ... fall through ... */
4825 case RELOAD_FOR_OPERAND_ADDRESS
:
4826 /* Check outputs and their addresses. */
4828 for (i
= 0; i
< reload_n_operands
; i
++)
4829 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4830 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4831 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4834 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4836 case RELOAD_FOR_OPADDR_ADDR
:
4837 for (i
= 0; i
< reload_n_operands
; i
++)
4838 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4839 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4840 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4843 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4844 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4845 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4847 case RELOAD_FOR_INSN
:
4848 /* These conflict with other outputs with RELOAD_OTHER. So
4849 we need only check for output addresses. */
4851 opnum
= reload_n_operands
;
4853 /* ... fall through ... */
4855 case RELOAD_FOR_OUTPUT
:
4856 case RELOAD_FOR_OUTPUT_ADDRESS
:
4857 case RELOAD_FOR_OUTADDR_ADDRESS
:
4858 /* We already know these can't conflict with a later output. So the
4859 only thing to check are later output addresses.
4860 Note that multiple output operands are emitted in reverse order,
4861 so the conflicting ones are those with lower indices. */
4862 for (i
= 0; i
< opnum
; i
++)
4863 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4864 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4875 /* Returns whether R1 and R2 are uniquely chained: the value of one
4876 is used by the other, and that value is not used by any other
4877 reload for this insn. This is used to partially undo the decision
4878 made in find_reloads when in the case of multiple
4879 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4880 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4881 reloads. This code tries to avoid the conflict created by that
4882 change. It might be cleaner to explicitly keep track of which
4883 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4884 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4885 this after the fact. */
4887 reloads_unique_chain_p (int r1
, int r2
)
4891 /* We only check input reloads. */
4892 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
4895 /* Avoid anything with output reloads. */
4896 if (rld
[r1
].out
|| rld
[r2
].out
)
4899 /* "chained" means one reload is a component of the other reload,
4900 not the same as the other reload. */
4901 if (rld
[r1
].opnum
!= rld
[r2
].opnum
4902 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
4903 || rld
[r1
].optional
|| rld
[r2
].optional
4904 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
4905 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
4908 for (i
= 0; i
< n_reloads
; i
++)
4909 /* Look for input reloads that aren't our two */
4910 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
4912 /* If our reload is mentioned at all, it isn't a simple chain. */
4913 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
4919 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4922 This function uses the same algorithm as reload_reg_free_p above. */
4925 reloads_conflict (int r1
, int r2
)
4927 enum reload_type r1_type
= rld
[r1
].when_needed
;
4928 enum reload_type r2_type
= rld
[r2
].when_needed
;
4929 int r1_opnum
= rld
[r1
].opnum
;
4930 int r2_opnum
= rld
[r2
].opnum
;
4932 /* RELOAD_OTHER conflicts with everything. */
4933 if (r2_type
== RELOAD_OTHER
)
4936 /* Otherwise, check conflicts differently for each type. */
4940 case RELOAD_FOR_INPUT
:
4941 return (r2_type
== RELOAD_FOR_INSN
4942 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
4943 || r2_type
== RELOAD_FOR_OPADDR_ADDR
4944 || r2_type
== RELOAD_FOR_INPUT
4945 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
4946 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
4947 && r2_opnum
> r1_opnum
));
4949 case RELOAD_FOR_INPUT_ADDRESS
:
4950 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
4951 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4953 case RELOAD_FOR_INPADDR_ADDRESS
:
4954 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
4955 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4957 case RELOAD_FOR_OUTPUT_ADDRESS
:
4958 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
4959 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4961 case RELOAD_FOR_OUTADDR_ADDRESS
:
4962 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
4963 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4965 case RELOAD_FOR_OPERAND_ADDRESS
:
4966 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
4967 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
4968 && !reloads_unique_chain_p (r1
, r2
)));
4970 case RELOAD_FOR_OPADDR_ADDR
:
4971 return (r2_type
== RELOAD_FOR_INPUT
4972 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
4974 case RELOAD_FOR_OUTPUT
:
4975 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
4976 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
4977 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
4978 && r2_opnum
>= r1_opnum
));
4980 case RELOAD_FOR_INSN
:
4981 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
4982 || r2_type
== RELOAD_FOR_INSN
4983 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4985 case RELOAD_FOR_OTHER_ADDRESS
:
4986 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
4996 /* Indexed by reload number, 1 if incoming value
4997 inherited from previous insns. */
4998 static char reload_inherited
[MAX_RELOADS
];
5000 /* For an inherited reload, this is the insn the reload was inherited from,
5001 if we know it. Otherwise, this is 0. */
5002 static rtx reload_inheritance_insn
[MAX_RELOADS
];
5004 /* If nonzero, this is a place to get the value of the reload,
5005 rather than using reload_in. */
5006 static rtx reload_override_in
[MAX_RELOADS
];
5008 /* For each reload, the hard register number of the register used,
5009 or -1 if we did not need a register for this reload. */
5010 static int reload_spill_index
[MAX_RELOADS
];
5012 /* Subroutine of free_for_value_p, used to check a single register.
5013 START_REGNO is the starting regno of the full reload register
5014 (possibly comprising multiple hard registers) that we are considering. */
5017 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5018 enum reload_type type
, rtx value
, rtx out
,
5019 int reloadnum
, int ignore_address_reloads
)
5022 /* Set if we see an input reload that must not share its reload register
5023 with any new earlyclobber, but might otherwise share the reload
5024 register with an output or input-output reload. */
5025 int check_earlyclobber
= 0;
5029 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5032 if (out
== const0_rtx
)
5038 /* We use some pseudo 'time' value to check if the lifetimes of the
5039 new register use would overlap with the one of a previous reload
5040 that is not read-only or uses a different value.
5041 The 'time' used doesn't have to be linear in any shape or form, just
5043 Some reload types use different 'buckets' for each operand.
5044 So there are MAX_RECOG_OPERANDS different time values for each
5046 We compute TIME1 as the time when the register for the prospective
5047 new reload ceases to be live, and TIME2 for each existing
5048 reload as the time when that the reload register of that reload
5050 Where there is little to be gained by exact lifetime calculations,
5051 we just make conservative assumptions, i.e. a longer lifetime;
5052 this is done in the 'default:' cases. */
5055 case RELOAD_FOR_OTHER_ADDRESS
:
5056 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5057 time1
= copy
? 0 : 1;
5060 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5062 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5063 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5064 respectively, to the time values for these, we get distinct time
5065 values. To get distinct time values for each operand, we have to
5066 multiply opnum by at least three. We round that up to four because
5067 multiply by four is often cheaper. */
5068 case RELOAD_FOR_INPADDR_ADDRESS
:
5069 time1
= opnum
* 4 + 2;
5071 case RELOAD_FOR_INPUT_ADDRESS
:
5072 time1
= opnum
* 4 + 3;
5074 case RELOAD_FOR_INPUT
:
5075 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5076 executes (inclusive). */
5077 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5079 case RELOAD_FOR_OPADDR_ADDR
:
5081 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5082 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5084 case RELOAD_FOR_OPERAND_ADDRESS
:
5085 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5087 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5089 case RELOAD_FOR_OUTADDR_ADDRESS
:
5090 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5092 case RELOAD_FOR_OUTPUT_ADDRESS
:
5093 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5096 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5099 for (i
= 0; i
< n_reloads
; i
++)
5101 rtx reg
= rld
[i
].reg_rtx
;
5102 if (reg
&& REG_P (reg
)
5103 && ((unsigned) regno
- true_regnum (reg
)
5104 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5107 rtx other_input
= rld
[i
].in
;
5109 /* If the other reload loads the same input value, that
5110 will not cause a conflict only if it's loading it into
5111 the same register. */
5112 if (true_regnum (reg
) != start_regno
)
5113 other_input
= NULL_RTX
;
5114 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5115 || rld
[i
].out
|| out
)
5118 switch (rld
[i
].when_needed
)
5120 case RELOAD_FOR_OTHER_ADDRESS
:
5123 case RELOAD_FOR_INPADDR_ADDRESS
:
5124 /* find_reloads makes sure that a
5125 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5126 by at most one - the first -
5127 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5128 address reload is inherited, the address address reload
5129 goes away, so we can ignore this conflict. */
5130 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5131 && ignore_address_reloads
5132 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5133 Then the address address is still needed to store
5134 back the new address. */
5135 && ! rld
[reloadnum
].out
)
5137 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5138 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5140 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5141 && ignore_address_reloads
5142 /* Unless we are reloading an auto_inc expression. */
5143 && ! rld
[reloadnum
].out
)
5145 time2
= rld
[i
].opnum
* 4 + 2;
5147 case RELOAD_FOR_INPUT_ADDRESS
:
5148 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5149 && ignore_address_reloads
5150 && ! rld
[reloadnum
].out
)
5152 time2
= rld
[i
].opnum
* 4 + 3;
5154 case RELOAD_FOR_INPUT
:
5155 time2
= rld
[i
].opnum
* 4 + 4;
5156 check_earlyclobber
= 1;
5158 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5159 == MAX_RECOG_OPERAND * 4 */
5160 case RELOAD_FOR_OPADDR_ADDR
:
5161 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5162 && ignore_address_reloads
5163 && ! rld
[reloadnum
].out
)
5165 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5167 case RELOAD_FOR_OPERAND_ADDRESS
:
5168 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5169 check_earlyclobber
= 1;
5171 case RELOAD_FOR_INSN
:
5172 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5174 case RELOAD_FOR_OUTPUT
:
5175 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5176 instruction is executed. */
5177 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5179 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5180 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5182 case RELOAD_FOR_OUTADDR_ADDRESS
:
5183 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5184 && ignore_address_reloads
5185 && ! rld
[reloadnum
].out
)
5187 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5189 case RELOAD_FOR_OUTPUT_ADDRESS
:
5190 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5193 /* If there is no conflict in the input part, handle this
5194 like an output reload. */
5195 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5197 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5198 /* Earlyclobbered outputs must conflict with inputs. */
5199 if (earlyclobber_operand_p (rld
[i
].out
))
5200 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5205 /* RELOAD_OTHER might be live beyond instruction execution,
5206 but this is not obvious when we set time2 = 1. So check
5207 here if there might be a problem with the new reload
5208 clobbering the register used by the RELOAD_OTHER. */
5216 && (! rld
[i
].in
|| rld
[i
].out
5217 || ! rtx_equal_p (other_input
, value
)))
5218 || (out
&& rld
[reloadnum
].out_reg
5219 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5225 /* Earlyclobbered outputs must conflict with inputs. */
5226 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
5232 /* Return 1 if the value in reload reg REGNO, as used by a reload
5233 needed for the part of the insn specified by OPNUM and TYPE,
5234 may be used to load VALUE into it.
5236 MODE is the mode in which the register is used, this is needed to
5237 determine how many hard regs to test.
5239 Other read-only reloads with the same value do not conflict
5240 unless OUT is nonzero and these other reloads have to live while
5241 output reloads live.
5242 If OUT is CONST0_RTX, this is a special case: it means that the
5243 test should not be for using register REGNO as reload register, but
5244 for copying from register REGNO into the reload register.
5246 RELOADNUM is the number of the reload we want to load this value for;
5247 a reload does not conflict with itself.
5249 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5250 reloads that load an address for the very reload we are considering.
5252 The caller has to make sure that there is no conflict with the return
5256 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
5257 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
5258 int ignore_address_reloads
)
5260 int nregs
= hard_regno_nregs
[regno
][mode
];
5262 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
5263 value
, out
, reloadnum
,
5264 ignore_address_reloads
))
5269 /* Return nonzero if the rtx X is invariant over the current function. */
5270 /* ??? Actually, the places where we use this expect exactly what is
5271 tested here, and not everything that is function invariant. In
5272 particular, the frame pointer and arg pointer are special cased;
5273 pic_offset_table_rtx is not, and we must not spill these things to
5277 function_invariant_p (rtx x
)
5281 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
5283 if (GET_CODE (x
) == PLUS
5284 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
5285 && CONSTANT_P (XEXP (x
, 1)))
5290 /* Determine whether the reload reg X overlaps any rtx'es used for
5291 overriding inheritance. Return nonzero if so. */
5294 conflicts_with_override (rtx x
)
5297 for (i
= 0; i
< n_reloads
; i
++)
5298 if (reload_override_in
[i
]
5299 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
5304 /* Give an error message saying we failed to find a reload for INSN,
5305 and clear out reload R. */
5307 failed_reload (rtx insn
, int r
)
5309 if (asm_noperands (PATTERN (insn
)) < 0)
5310 /* It's the compiler's fault. */
5311 fatal_insn ("could not find a spill register", insn
);
5313 /* It's the user's fault; the operand's mode and constraint
5314 don't match. Disable this reload so we don't crash in final. */
5315 error_for_asm (insn
,
5316 "%<asm%> operand constraint incompatible with operand size");
5320 rld
[r
].optional
= 1;
5321 rld
[r
].secondary_p
= 1;
5324 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5325 for reload R. If it's valid, get an rtx for it. Return nonzero if
5328 set_reload_reg (int i
, int r
)
5331 rtx reg
= spill_reg_rtx
[i
];
5333 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
5334 spill_reg_rtx
[i
] = reg
5335 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
5337 regno
= true_regnum (reg
);
5339 /* Detect when the reload reg can't hold the reload mode.
5340 This used to be one `if', but Sequent compiler can't handle that. */
5341 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5343 enum machine_mode test_mode
= VOIDmode
;
5345 test_mode
= GET_MODE (rld
[r
].in
);
5346 /* If rld[r].in has VOIDmode, it means we will load it
5347 in whatever mode the reload reg has: to wit, rld[r].mode.
5348 We have already tested that for validity. */
5349 /* Aside from that, we need to test that the expressions
5350 to reload from or into have modes which are valid for this
5351 reload register. Otherwise the reload insns would be invalid. */
5352 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
5353 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5354 if (! (rld
[r
].out
!= 0
5355 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
5357 /* The reg is OK. */
5360 /* Mark as in use for this insn the reload regs we use
5362 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
5363 rld
[r
].when_needed
, rld
[r
].mode
);
5365 rld
[r
].reg_rtx
= reg
;
5366 reload_spill_index
[r
] = spill_regs
[i
];
5373 /* Find a spill register to use as a reload register for reload R.
5374 LAST_RELOAD is nonzero if this is the last reload for the insn being
5377 Set rld[R].reg_rtx to the register allocated.
5379 We return 1 if successful, or 0 if we couldn't find a spill reg and
5380 we didn't change anything. */
5383 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
5388 /* If we put this reload ahead, thinking it is a group,
5389 then insist on finding a group. Otherwise we can grab a
5390 reg that some other reload needs.
5391 (That can happen when we have a 68000 DATA_OR_FP_REG
5392 which is a group of data regs or one fp reg.)
5393 We need not be so restrictive if there are no more reloads
5396 ??? Really it would be nicer to have smarter handling
5397 for that kind of reg class, where a problem like this is normal.
5398 Perhaps those classes should be avoided for reloading
5399 by use of more alternatives. */
5401 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
5403 /* If we want a single register and haven't yet found one,
5404 take any reg in the right class and not in use.
5405 If we want a consecutive group, here is where we look for it.
5407 We use two passes so we can first look for reload regs to
5408 reuse, which are already in use for other reloads in this insn,
5409 and only then use additional registers.
5410 I think that maximizing reuse is needed to make sure we don't
5411 run out of reload regs. Suppose we have three reloads, and
5412 reloads A and B can share regs. These need two regs.
5413 Suppose A and B are given different regs.
5414 That leaves none for C. */
5415 for (pass
= 0; pass
< 2; pass
++)
5417 /* I is the index in spill_regs.
5418 We advance it round-robin between insns to use all spill regs
5419 equally, so that inherited reloads have a chance
5420 of leapfrogging each other. */
5424 for (count
= 0; count
< n_spills
; count
++)
5426 int class = (int) rld
[r
].class;
5432 regnum
= spill_regs
[i
];
5434 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
5437 /* We check reload_reg_used to make sure we
5438 don't clobber the return register. */
5439 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5440 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
5441 rld
[r
].when_needed
, rld
[r
].in
,
5443 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5444 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
5445 /* Look first for regs to share, then for unshared. But
5446 don't share regs used for inherited reloads; they are
5447 the ones we want to preserve. */
5449 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5451 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5454 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
5455 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5456 (on 68000) got us two FP regs. If NR is 1,
5457 we would reject both of them. */
5460 /* If we need only one reg, we have already won. */
5463 /* But reject a single reg if we demand a group. */
5468 /* Otherwise check that as many consecutive regs as we need
5469 are available here. */
5472 int regno
= regnum
+ nr
- 1;
5473 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5474 && spill_reg_order
[regno
] >= 0
5475 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5476 rld
[r
].when_needed
)))
5485 /* If we found something on pass 1, omit pass 2. */
5486 if (count
< n_spills
)
5490 /* We should have found a spill register by now. */
5491 if (count
>= n_spills
)
5494 /* I is the index in SPILL_REG_RTX of the reload register we are to
5495 allocate. Get an rtx for it and find its register number. */
5497 return set_reload_reg (i
, r
);
5500 /* Initialize all the tables needed to allocate reload registers.
5501 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5502 is the array we use to restore the reg_rtx field for every reload. */
5505 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
5509 for (i
= 0; i
< n_reloads
; i
++)
5510 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5512 memset (reload_inherited
, 0, MAX_RELOADS
);
5513 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
5514 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
5516 CLEAR_HARD_REG_SET (reload_reg_used
);
5517 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5518 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5519 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5520 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5521 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5523 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5526 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5527 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5528 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5529 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5530 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5531 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5534 for (i
= 0; i
< reload_n_operands
; i
++)
5536 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5537 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5538 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5539 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5540 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5541 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5544 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5546 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5548 for (i
= 0; i
< n_reloads
; i
++)
5549 /* If we have already decided to use a certain register,
5550 don't use it in another way. */
5552 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5553 rld
[i
].when_needed
, rld
[i
].mode
);
5556 /* Assign hard reg targets for the pseudo-registers we must reload
5557 into hard regs for this insn.
5558 Also output the instructions to copy them in and out of the hard regs.
5560 For machines with register classes, we are responsible for
5561 finding a reload reg in the proper class. */
5564 choose_reload_regs (struct insn_chain
*chain
)
5566 rtx insn
= chain
->insn
;
5568 unsigned int max_group_size
= 1;
5569 enum reg_class group_class
= NO_REGS
;
5570 int pass
, win
, inheritance
;
5572 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5574 /* In order to be certain of getting the registers we need,
5575 we must sort the reloads into order of increasing register class.
5576 Then our grabbing of reload registers will parallel the process
5577 that provided the reload registers.
5579 Also note whether any of the reloads wants a consecutive group of regs.
5580 If so, record the maximum size of the group desired and what
5581 register class contains all the groups needed by this insn. */
5583 for (j
= 0; j
< n_reloads
; j
++)
5585 reload_order
[j
] = j
;
5586 reload_spill_index
[j
] = -1;
5588 if (rld
[j
].nregs
> 1)
5590 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5592 = reg_class_superunion
[(int) rld
[j
].class][(int) group_class
];
5595 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5599 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5601 /* If -O, try first with inheritance, then turning it off.
5602 If not -O, don't do inheritance.
5603 Using inheritance when not optimizing leads to paradoxes
5604 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5605 because one side of the comparison might be inherited. */
5607 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5609 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5611 /* Process the reloads in order of preference just found.
5612 Beyond this point, subregs can be found in reload_reg_rtx.
5614 This used to look for an existing reloaded home for all of the
5615 reloads, and only then perform any new reloads. But that could lose
5616 if the reloads were done out of reg-class order because a later
5617 reload with a looser constraint might have an old home in a register
5618 needed by an earlier reload with a tighter constraint.
5620 To solve this, we make two passes over the reloads, in the order
5621 described above. In the first pass we try to inherit a reload
5622 from a previous insn. If there is a later reload that needs a
5623 class that is a proper subset of the class being processed, we must
5624 also allocate a spill register during the first pass.
5626 Then make a second pass over the reloads to allocate any reloads
5627 that haven't been given registers yet. */
5629 for (j
= 0; j
< n_reloads
; j
++)
5631 int r
= reload_order
[j
];
5632 rtx search_equiv
= NULL_RTX
;
5634 /* Ignore reloads that got marked inoperative. */
5635 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5636 && ! rld
[r
].secondary_p
)
5639 /* If find_reloads chose to use reload_in or reload_out as a reload
5640 register, we don't need to chose one. Otherwise, try even if it
5641 found one since we might save an insn if we find the value lying
5643 Try also when reload_in is a pseudo without a hard reg. */
5644 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5645 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5646 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5647 && !MEM_P (rld
[r
].in
)
5648 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5651 #if 0 /* No longer needed for correct operation.
5652 It might give better code, or might not; worth an experiment? */
5653 /* If this is an optional reload, we can't inherit from earlier insns
5654 until we are sure that any non-optional reloads have been allocated.
5655 The following code takes advantage of the fact that optional reloads
5656 are at the end of reload_order. */
5657 if (rld
[r
].optional
!= 0)
5658 for (i
= 0; i
< j
; i
++)
5659 if ((rld
[reload_order
[i
]].out
!= 0
5660 || rld
[reload_order
[i
]].in
!= 0
5661 || rld
[reload_order
[i
]].secondary_p
)
5662 && ! rld
[reload_order
[i
]].optional
5663 && rld
[reload_order
[i
]].reg_rtx
== 0)
5664 allocate_reload_reg (chain
, reload_order
[i
], 0);
5667 /* First see if this pseudo is already available as reloaded
5668 for a previous insn. We cannot try to inherit for reloads
5669 that are smaller than the maximum number of registers needed
5670 for groups unless the register we would allocate cannot be used
5673 We could check here to see if this is a secondary reload for
5674 an object that is already in a register of the desired class.
5675 This would avoid the need for the secondary reload register.
5676 But this is complex because we can't easily determine what
5677 objects might want to be loaded via this reload. So let a
5678 register be allocated here. In `emit_reload_insns' we suppress
5679 one of the loads in the case described above. */
5685 enum machine_mode mode
= VOIDmode
;
5689 else if (REG_P (rld
[r
].in
))
5691 regno
= REGNO (rld
[r
].in
);
5692 mode
= GET_MODE (rld
[r
].in
);
5694 else if (REG_P (rld
[r
].in_reg
))
5696 regno
= REGNO (rld
[r
].in_reg
);
5697 mode
= GET_MODE (rld
[r
].in_reg
);
5699 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
5700 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
5702 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
5703 if (regno
< FIRST_PSEUDO_REGISTER
)
5704 regno
= subreg_regno (rld
[r
].in_reg
);
5706 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
5707 mode
= GET_MODE (rld
[r
].in_reg
);
5710 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
5711 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
5713 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
5714 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
5715 rld
[r
].out
= rld
[r
].in
;
5719 /* This won't work, since REGNO can be a pseudo reg number.
5720 Also, it takes much more hair to keep track of all the things
5721 that can invalidate an inherited reload of part of a pseudoreg. */
5722 else if (GET_CODE (rld
[r
].in
) == SUBREG
5723 && REG_P (SUBREG_REG (rld
[r
].in
)))
5724 regno
= subreg_regno (rld
[r
].in
);
5727 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5729 enum reg_class
class = rld
[r
].class, last_class
;
5730 rtx last_reg
= reg_last_reload_reg
[regno
];
5731 enum machine_mode need_mode
;
5733 i
= REGNO (last_reg
);
5734 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
5735 last_class
= REGNO_REG_CLASS (i
);
5741 = smallest_mode_for_size (GET_MODE_BITSIZE (mode
)
5742 + byte
* BITS_PER_UNIT
,
5743 GET_MODE_CLASS (mode
));
5745 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
5746 >= GET_MODE_SIZE (need_mode
))
5747 #ifdef CANNOT_CHANGE_MODE_CLASS
5748 /* Verify that the register in "i" can be obtained
5750 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg
),
5751 GET_MODE (last_reg
),
5754 && reg_reloaded_contents
[i
] == regno
5755 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5756 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
5757 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5758 /* Even if we can't use this register as a reload
5759 register, we might use it for reload_override_in,
5760 if copying it to the desired class is cheap
5762 || ((REGISTER_MOVE_COST (mode
, last_class
, class)
5763 < MEMORY_MOVE_COST (mode
, class, 1))
5764 && (secondary_reload_class (1, class, mode
,
5767 #ifdef SECONDARY_MEMORY_NEEDED
5768 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5773 && (rld
[r
].nregs
== max_group_size
5774 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5776 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
5777 rld
[r
].when_needed
, rld
[r
].in
,
5780 /* If a group is needed, verify that all the subsequent
5781 registers still have their values intact. */
5782 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
5785 for (k
= 1; k
< nr
; k
++)
5786 if (reg_reloaded_contents
[i
+ k
] != regno
5787 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5795 last_reg
= (GET_MODE (last_reg
) == mode
5796 ? last_reg
: gen_rtx_REG (mode
, i
));
5799 for (k
= 0; k
< nr
; k
++)
5800 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5803 /* We found a register that contains the
5804 value we need. If this register is the
5805 same as an `earlyclobber' operand of the
5806 current insn, just mark it as a place to
5807 reload from since we can't use it as the
5808 reload register itself. */
5810 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5811 if (reg_overlap_mentioned_for_reload_p
5812 (reg_last_reload_reg
[regno
],
5813 reload_earlyclobbers
[i1
]))
5816 if (i1
!= n_earlyclobbers
5817 || ! (free_for_value_p (i
, rld
[r
].mode
,
5819 rld
[r
].when_needed
, rld
[r
].in
,
5821 /* Don't use it if we'd clobber a pseudo reg. */
5822 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5824 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5825 /* Don't clobber the frame pointer. */
5826 || (i
== HARD_FRAME_POINTER_REGNUM
5827 && frame_pointer_needed
5829 /* Don't really use the inherited spill reg
5830 if we need it wider than we've got it. */
5831 || (GET_MODE_SIZE (rld
[r
].mode
)
5832 > GET_MODE_SIZE (mode
))
5835 /* If find_reloads chose reload_out as reload
5836 register, stay with it - that leaves the
5837 inherited register for subsequent reloads. */
5838 || (rld
[r
].out
&& rld
[r
].reg_rtx
5839 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
5841 if (! rld
[r
].optional
)
5843 reload_override_in
[r
] = last_reg
;
5844 reload_inheritance_insn
[r
]
5845 = reg_reloaded_insn
[i
];
5851 /* We can use this as a reload reg. */
5852 /* Mark the register as in use for this part of
5854 mark_reload_reg_in_use (i
,
5858 rld
[r
].reg_rtx
= last_reg
;
5859 reload_inherited
[r
] = 1;
5860 reload_inheritance_insn
[r
]
5861 = reg_reloaded_insn
[i
];
5862 reload_spill_index
[r
] = i
;
5863 for (k
= 0; k
< nr
; k
++)
5864 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5872 /* Here's another way to see if the value is already lying around. */
5875 && ! reload_inherited
[r
]
5877 && (CONSTANT_P (rld
[r
].in
)
5878 || GET_CODE (rld
[r
].in
) == PLUS
5879 || REG_P (rld
[r
].in
)
5880 || MEM_P (rld
[r
].in
))
5881 && (rld
[r
].nregs
== max_group_size
5882 || ! reg_classes_intersect_p (rld
[r
].class, group_class
)))
5883 search_equiv
= rld
[r
].in
;
5884 /* If this is an output reload from a simple move insn, look
5885 if an equivalence for the input is available. */
5886 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
5888 rtx set
= single_set (insn
);
5891 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
5892 && CONSTANT_P (SET_SRC (set
)))
5893 search_equiv
= SET_SRC (set
);
5899 = find_equiv_reg (search_equiv
, insn
, rld
[r
].class,
5900 -1, NULL
, 0, rld
[r
].mode
);
5906 regno
= REGNO (equiv
);
5909 /* This must be a SUBREG of a hard register.
5910 Make a new REG since this might be used in an
5911 address and not all machines support SUBREGs
5913 gcc_assert (GET_CODE (equiv
) == SUBREG
);
5914 regno
= subreg_regno (equiv
);
5915 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
5916 /* If we choose EQUIV as the reload register, but the
5917 loop below decides to cancel the inheritance, we'll
5918 end up reloading EQUIV in rld[r].mode, not the mode
5919 it had originally. That isn't safe when EQUIV isn't
5920 available as a spill register since its value might
5921 still be live at this point. */
5922 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
5923 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
5928 /* If we found a spill reg, reject it unless it is free
5929 and of the desired class. */
5933 int bad_for_class
= 0;
5934 int max_regno
= regno
+ rld
[r
].nregs
;
5936 for (i
= regno
; i
< max_regno
; i
++)
5938 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5940 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5945 && ! free_for_value_p (regno
, rld
[r
].mode
,
5946 rld
[r
].opnum
, rld
[r
].when_needed
,
5947 rld
[r
].in
, rld
[r
].out
, r
, 1))
5952 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5955 /* We found a register that contains the value we need.
5956 If this register is the same as an `earlyclobber' operand
5957 of the current insn, just mark it as a place to reload from
5958 since we can't use it as the reload register itself. */
5961 for (i
= 0; i
< n_earlyclobbers
; i
++)
5962 if (reg_overlap_mentioned_for_reload_p (equiv
,
5963 reload_earlyclobbers
[i
]))
5965 if (! rld
[r
].optional
)
5966 reload_override_in
[r
] = equiv
;
5971 /* If the equiv register we have found is explicitly clobbered
5972 in the current insn, it depends on the reload type if we
5973 can use it, use it for reload_override_in, or not at all.
5974 In particular, we then can't use EQUIV for a
5975 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5979 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
5980 switch (rld
[r
].when_needed
)
5982 case RELOAD_FOR_OTHER_ADDRESS
:
5983 case RELOAD_FOR_INPADDR_ADDRESS
:
5984 case RELOAD_FOR_INPUT_ADDRESS
:
5985 case RELOAD_FOR_OPADDR_ADDR
:
5988 case RELOAD_FOR_INPUT
:
5989 case RELOAD_FOR_OPERAND_ADDRESS
:
5990 if (! rld
[r
].optional
)
5991 reload_override_in
[r
] = equiv
;
5997 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
5998 switch (rld
[r
].when_needed
)
6000 case RELOAD_FOR_OTHER_ADDRESS
:
6001 case RELOAD_FOR_INPADDR_ADDRESS
:
6002 case RELOAD_FOR_INPUT_ADDRESS
:
6003 case RELOAD_FOR_OPADDR_ADDR
:
6004 case RELOAD_FOR_OPERAND_ADDRESS
:
6005 case RELOAD_FOR_INPUT
:
6008 if (! rld
[r
].optional
)
6009 reload_override_in
[r
] = equiv
;
6017 /* If we found an equivalent reg, say no code need be generated
6018 to load it, and use it as our reload reg. */
6020 && (regno
!= HARD_FRAME_POINTER_REGNUM
6021 || !frame_pointer_needed
))
6023 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6025 rld
[r
].reg_rtx
= equiv
;
6026 reload_inherited
[r
] = 1;
6028 /* If reg_reloaded_valid is not set for this register,
6029 there might be a stale spill_reg_store lying around.
6030 We must clear it, since otherwise emit_reload_insns
6031 might delete the store. */
6032 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6033 spill_reg_store
[regno
] = NULL_RTX
;
6034 /* If any of the hard registers in EQUIV are spill
6035 registers, mark them as in use for this insn. */
6036 for (k
= 0; k
< nr
; k
++)
6038 i
= spill_reg_order
[regno
+ k
];
6041 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6044 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6051 /* If we found a register to use already, or if this is an optional
6052 reload, we are done. */
6053 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6057 /* No longer needed for correct operation. Might or might
6058 not give better code on the average. Want to experiment? */
6060 /* See if there is a later reload that has a class different from our
6061 class that intersects our class or that requires less register
6062 than our reload. If so, we must allocate a register to this
6063 reload now, since that reload might inherit a previous reload
6064 and take the only available register in our class. Don't do this
6065 for optional reloads since they will force all previous reloads
6066 to be allocated. Also don't do this for reloads that have been
6069 for (i
= j
+ 1; i
< n_reloads
; i
++)
6071 int s
= reload_order
[i
];
6073 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6074 && ! rld
[s
].secondary_p
)
6078 if ((rld
[s
].class != rld
[r
].class
6079 && reg_classes_intersect_p (rld
[r
].class,
6081 || rld
[s
].nregs
< rld
[r
].nregs
)
6088 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6092 /* Now allocate reload registers for anything non-optional that
6093 didn't get one yet. */
6094 for (j
= 0; j
< n_reloads
; j
++)
6096 int r
= reload_order
[j
];
6098 /* Ignore reloads that got marked inoperative. */
6099 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6102 /* Skip reloads that already have a register allocated or are
6104 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6107 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6111 /* If that loop got all the way, we have won. */
6118 /* Loop around and try without any inheritance. */
6123 /* First undo everything done by the failed attempt
6124 to allocate with inheritance. */
6125 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6127 /* Some sanity tests to verify that the reloads found in the first
6128 pass are identical to the ones we have now. */
6129 gcc_assert (chain
->n_reloads
== n_reloads
);
6131 for (i
= 0; i
< n_reloads
; i
++)
6133 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6135 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6136 for (j
= 0; j
< n_spills
; j
++)
6137 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6138 if (! set_reload_reg (j
, i
))
6139 failed_reload (chain
->insn
, i
);
6143 /* If we thought we could inherit a reload, because it seemed that
6144 nothing else wanted the same reload register earlier in the insn,
6145 verify that assumption, now that all reloads have been assigned.
6146 Likewise for reloads where reload_override_in has been set. */
6148 /* If doing expensive optimizations, do one preliminary pass that doesn't
6149 cancel any inheritance, but removes reloads that have been needed only
6150 for reloads that we know can be inherited. */
6151 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6153 for (j
= 0; j
< n_reloads
; j
++)
6155 int r
= reload_order
[j
];
6157 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6158 check_reg
= rld
[r
].reg_rtx
;
6159 else if (reload_override_in
[r
]
6160 && (REG_P (reload_override_in
[r
])
6161 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6162 check_reg
= reload_override_in
[r
];
6165 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6166 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6167 (reload_inherited
[r
]
6168 ? rld
[r
].out
: const0_rtx
),
6173 reload_inherited
[r
] = 0;
6174 reload_override_in
[r
] = 0;
6176 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6177 reload_override_in, then we do not need its related
6178 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6179 likewise for other reload types.
6180 We handle this by removing a reload when its only replacement
6181 is mentioned in reload_in of the reload we are going to inherit.
6182 A special case are auto_inc expressions; even if the input is
6183 inherited, we still need the address for the output. We can
6184 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6185 If we succeeded removing some reload and we are doing a preliminary
6186 pass just to remove such reloads, make another pass, since the
6187 removal of one reload might allow us to inherit another one. */
6189 && rld
[r
].out
!= rld
[r
].in
6190 && remove_address_replacements (rld
[r
].in
) && pass
)
6195 /* Now that reload_override_in is known valid,
6196 actually override reload_in. */
6197 for (j
= 0; j
< n_reloads
; j
++)
6198 if (reload_override_in
[j
])
6199 rld
[j
].in
= reload_override_in
[j
];
6201 /* If this reload won't be done because it has been canceled or is
6202 optional and not inherited, clear reload_reg_rtx so other
6203 routines (such as subst_reloads) don't get confused. */
6204 for (j
= 0; j
< n_reloads
; j
++)
6205 if (rld
[j
].reg_rtx
!= 0
6206 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
6207 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
6208 && ! rld
[j
].secondary_p
)))
6210 int regno
= true_regnum (rld
[j
].reg_rtx
);
6212 if (spill_reg_order
[regno
] >= 0)
6213 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
6214 rld
[j
].when_needed
, rld
[j
].mode
);
6216 reload_spill_index
[j
] = -1;
6219 /* Record which pseudos and which spill regs have output reloads. */
6220 for (j
= 0; j
< n_reloads
; j
++)
6222 int r
= reload_order
[j
];
6224 i
= reload_spill_index
[r
];
6226 /* I is nonneg if this reload uses a register.
6227 If rld[r].reg_rtx is 0, this is an optional reload
6228 that we opted to ignore. */
6229 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
6230 && rld
[r
].reg_rtx
!= 0)
6232 int nregno
= REGNO (rld
[r
].out_reg
);
6235 if (nregno
< FIRST_PSEUDO_REGISTER
)
6236 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
6239 SET_REGNO_REG_SET (®_has_output_reload
,
6244 nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6246 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6249 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
6250 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
6251 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
6256 /* Deallocate the reload register for reload R. This is called from
6257 remove_address_replacements. */
6260 deallocate_reload_reg (int r
)
6264 if (! rld
[r
].reg_rtx
)
6266 regno
= true_regnum (rld
[r
].reg_rtx
);
6268 if (spill_reg_order
[regno
] >= 0)
6269 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
6271 reload_spill_index
[r
] = -1;
6274 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6275 reloads of the same item for fear that we might not have enough reload
6276 registers. However, normally they will get the same reload register
6277 and hence actually need not be loaded twice.
6279 Here we check for the most common case of this phenomenon: when we have
6280 a number of reloads for the same object, each of which were allocated
6281 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6282 reload, and is not modified in the insn itself. If we find such,
6283 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6284 This will not increase the number of spill registers needed and will
6285 prevent redundant code. */
6288 merge_assigned_reloads (rtx insn
)
6292 /* Scan all the reloads looking for ones that only load values and
6293 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6294 assigned and not modified by INSN. */
6296 for (i
= 0; i
< n_reloads
; i
++)
6298 int conflicting_input
= 0;
6299 int max_input_address_opnum
= -1;
6300 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6302 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
6303 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
6304 || reg_set_p (rld
[i
].reg_rtx
, insn
))
6307 /* Look at all other reloads. Ensure that the only use of this
6308 reload_reg_rtx is in a reload that just loads the same value
6309 as we do. Note that any secondary reloads must be of the identical
6310 class since the values, modes, and result registers are the
6311 same, so we need not do anything with any secondary reloads. */
6313 for (j
= 0; j
< n_reloads
; j
++)
6315 if (i
== j
|| rld
[j
].reg_rtx
== 0
6316 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
6320 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6321 && rld
[j
].opnum
> max_input_address_opnum
)
6322 max_input_address_opnum
= rld
[j
].opnum
;
6324 /* If the reload regs aren't exactly the same (e.g, different modes)
6325 or if the values are different, we can't merge this reload.
6326 But if it is an input reload, we might still merge
6327 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6329 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6330 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
6331 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
6333 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
6334 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
6335 || rld
[i
].opnum
> rld
[j
].opnum
)
6336 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
6338 conflicting_input
= 1;
6339 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
6340 min_conflicting_input_opnum
= rld
[j
].opnum
;
6344 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6345 we, in fact, found any matching reloads. */
6348 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6350 gcc_assert (rld
[i
].when_needed
!= RELOAD_FOR_OUTPUT
);
6352 for (j
= 0; j
< n_reloads
; j
++)
6353 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
6354 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6355 && (! conflicting_input
6356 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6357 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
6359 rld
[i
].when_needed
= RELOAD_OTHER
;
6361 reload_spill_index
[j
] = -1;
6362 transfer_replacements (i
, j
);
6365 /* If this is now RELOAD_OTHER, look for any reloads that load
6366 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6367 if they were for inputs, RELOAD_OTHER for outputs. Note that
6368 this test is equivalent to looking for reloads for this operand
6370 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6371 share registers with a RELOAD_FOR_INPUT, so we can not change it
6372 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6373 do not modify RELOAD_FOR_OUTPUT. */
6375 if (rld
[i
].when_needed
== RELOAD_OTHER
)
6376 for (j
= 0; j
< n_reloads
; j
++)
6378 && rld
[j
].when_needed
!= RELOAD_OTHER
6379 && rld
[j
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
6380 && rld
[j
].when_needed
!= RELOAD_FOR_OUTPUT_ADDRESS
6381 && (! conflicting_input
6382 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6383 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6384 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
6390 = ((rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6391 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6392 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6394 /* Check to see if we accidentally converted two
6395 reloads that use the same reload register with
6396 different inputs to the same type. If so, the
6397 resulting code won't work. */
6399 for (k
= 0; k
< j
; k
++)
6400 gcc_assert (rld
[k
].in
== 0 || rld
[k
].reg_rtx
== 0
6401 || rld
[k
].when_needed
!= rld
[j
].when_needed
6402 || !rtx_equal_p (rld
[k
].reg_rtx
,
6404 || rtx_equal_p (rld
[k
].in
,
6411 /* These arrays are filled by emit_reload_insns and its subroutines. */
6412 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6413 static rtx other_input_address_reload_insns
= 0;
6414 static rtx other_input_reload_insns
= 0;
6415 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6416 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6417 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6418 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6419 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6420 static rtx operand_reload_insns
= 0;
6421 static rtx other_operand_reload_insns
= 0;
6422 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6424 /* Values to be put in spill_reg_store are put here first. */
6425 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6426 static HARD_REG_SET reg_reloaded_died
;
6428 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6429 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6430 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6431 adjusted register, and return true. Otherwise, return false. */
6433 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
6434 enum reg_class new_class
,
6435 enum machine_mode new_mode
)
6440 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
6442 unsigned regno
= REGNO (reg
);
6444 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
6446 if (GET_MODE (reg
) != new_mode
)
6448 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
6450 if (hard_regno_nregs
[regno
][new_mode
]
6451 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
6453 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
6461 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6462 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6463 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6464 adjusted register, and return true. Otherwise, return false. */
6466 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
6467 enum insn_code icode
)
6470 enum reg_class new_class
= scratch_reload_class (icode
);
6471 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
6473 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
6474 new_class
, new_mode
);
6477 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6478 has the number J. OLD contains the value to be used as input. */
6481 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6484 rtx insn
= chain
->insn
;
6485 rtx reloadreg
= rl
->reg_rtx
;
6486 rtx oldequiv_reg
= 0;
6489 enum machine_mode mode
;
6492 /* Determine the mode to reload in.
6493 This is very tricky because we have three to choose from.
6494 There is the mode the insn operand wants (rl->inmode).
6495 There is the mode of the reload register RELOADREG.
6496 There is the intrinsic mode of the operand, which we could find
6497 by stripping some SUBREGs.
6498 It turns out that RELOADREG's mode is irrelevant:
6499 we can change that arbitrarily.
6501 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6502 then the reload reg may not support QImode moves, so use SImode.
6503 If foo is in memory due to spilling a pseudo reg, this is safe,
6504 because the QImode value is in the least significant part of a
6505 slot big enough for a SImode. If foo is some other sort of
6506 memory reference, then it is impossible to reload this case,
6507 so previous passes had better make sure this never happens.
6509 Then consider a one-word union which has SImode and one of its
6510 members is a float, being fetched as (SUBREG:SF union:SI).
6511 We must fetch that as SFmode because we could be loading into
6512 a float-only register. In this case OLD's mode is correct.
6514 Consider an immediate integer: it has VOIDmode. Here we need
6515 to get a mode from something else.
6517 In some cases, there is a fourth mode, the operand's
6518 containing mode. If the insn specifies a containing mode for
6519 this operand, it overrides all others.
6521 I am not sure whether the algorithm here is always right,
6522 but it does the right things in those cases. */
6524 mode
= GET_MODE (old
);
6525 if (mode
== VOIDmode
)
6528 /* delete_output_reload is only invoked properly if old contains
6529 the original pseudo register. Since this is replaced with a
6530 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6531 find the pseudo in RELOAD_IN_REG. */
6532 if (reload_override_in
[j
]
6533 && REG_P (rl
->in_reg
))
6540 else if (REG_P (oldequiv
))
6541 oldequiv_reg
= oldequiv
;
6542 else if (GET_CODE (oldequiv
) == SUBREG
)
6543 oldequiv_reg
= SUBREG_REG (oldequiv
);
6545 /* If we are reloading from a register that was recently stored in
6546 with an output-reload, see if we can prove there was
6547 actually no need to store the old value in it. */
6549 if (optimize
&& REG_P (oldequiv
)
6550 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6551 && spill_reg_store
[REGNO (oldequiv
)]
6553 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6554 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6556 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6558 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6559 then load RELOADREG from OLDEQUIV. Note that we cannot use
6560 gen_lowpart_common since it can do the wrong thing when
6561 RELOADREG has a multi-word mode. Note that RELOADREG
6562 must always be a REG here. */
6564 if (GET_MODE (reloadreg
) != mode
)
6565 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6566 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6567 oldequiv
= SUBREG_REG (oldequiv
);
6568 if (GET_MODE (oldequiv
) != VOIDmode
6569 && mode
!= GET_MODE (oldequiv
))
6570 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
6572 /* Switch to the right place to emit the reload insns. */
6573 switch (rl
->when_needed
)
6576 where
= &other_input_reload_insns
;
6578 case RELOAD_FOR_INPUT
:
6579 where
= &input_reload_insns
[rl
->opnum
];
6581 case RELOAD_FOR_INPUT_ADDRESS
:
6582 where
= &input_address_reload_insns
[rl
->opnum
];
6584 case RELOAD_FOR_INPADDR_ADDRESS
:
6585 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6587 case RELOAD_FOR_OUTPUT_ADDRESS
:
6588 where
= &output_address_reload_insns
[rl
->opnum
];
6590 case RELOAD_FOR_OUTADDR_ADDRESS
:
6591 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6593 case RELOAD_FOR_OPERAND_ADDRESS
:
6594 where
= &operand_reload_insns
;
6596 case RELOAD_FOR_OPADDR_ADDR
:
6597 where
= &other_operand_reload_insns
;
6599 case RELOAD_FOR_OTHER_ADDRESS
:
6600 where
= &other_input_address_reload_insns
;
6606 push_to_sequence (*where
);
6608 /* Auto-increment addresses must be reloaded in a special way. */
6609 if (rl
->out
&& ! rl
->out_reg
)
6611 /* We are not going to bother supporting the case where a
6612 incremented register can't be copied directly from
6613 OLDEQUIV since this seems highly unlikely. */
6614 gcc_assert (rl
->secondary_in_reload
< 0);
6616 if (reload_inherited
[j
])
6617 oldequiv
= reloadreg
;
6619 old
= XEXP (rl
->in_reg
, 0);
6621 if (optimize
&& REG_P (oldequiv
)
6622 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6623 && spill_reg_store
[REGNO (oldequiv
)]
6625 && (dead_or_set_p (insn
,
6626 spill_reg_stored_to
[REGNO (oldequiv
)])
6627 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6629 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6631 /* Prevent normal processing of this reload. */
6633 /* Output a special code sequence for this case. */
6634 new_spill_reg_store
[REGNO (reloadreg
)]
6635 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6639 /* If we are reloading a pseudo-register that was set by the previous
6640 insn, see if we can get rid of that pseudo-register entirely
6641 by redirecting the previous insn into our reload register. */
6643 else if (optimize
&& REG_P (old
)
6644 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6645 && dead_or_set_p (insn
, old
)
6646 /* This is unsafe if some other reload
6647 uses the same reg first. */
6648 && ! conflicts_with_override (reloadreg
)
6649 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
6650 rl
->when_needed
, old
, rl
->out
, j
, 0))
6652 rtx temp
= PREV_INSN (insn
);
6653 while (temp
&& NOTE_P (temp
))
6654 temp
= PREV_INSN (temp
);
6656 && NONJUMP_INSN_P (temp
)
6657 && GET_CODE (PATTERN (temp
)) == SET
6658 && SET_DEST (PATTERN (temp
)) == old
6659 /* Make sure we can access insn_operand_constraint. */
6660 && asm_noperands (PATTERN (temp
)) < 0
6661 /* This is unsafe if operand occurs more than once in current
6662 insn. Perhaps some occurrences aren't reloaded. */
6663 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
6665 rtx old
= SET_DEST (PATTERN (temp
));
6666 /* Store into the reload register instead of the pseudo. */
6667 SET_DEST (PATTERN (temp
)) = reloadreg
;
6669 /* Verify that resulting insn is valid. */
6670 extract_insn (temp
);
6671 if (constrain_operands (1))
6673 /* If the previous insn is an output reload, the source is
6674 a reload register, and its spill_reg_store entry will
6675 contain the previous destination. This is now
6677 if (REG_P (SET_SRC (PATTERN (temp
)))
6678 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6680 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6681 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6684 /* If these are the only uses of the pseudo reg,
6685 pretend for GDB it lives in the reload reg we used. */
6686 if (REG_N_DEATHS (REGNO (old
)) == 1
6687 && REG_N_SETS (REGNO (old
)) == 1)
6689 reg_renumber
[REGNO (old
)] = REGNO (rl
->reg_rtx
);
6691 mark_allocation_change (REGNO (old
));
6692 alter_reg (REGNO (old
), -1, false);
6698 SET_DEST (PATTERN (temp
)) = old
;
6703 /* We can't do that, so output an insn to load RELOADREG. */
6705 /* If we have a secondary reload, pick up the secondary register
6706 and icode, if any. If OLDEQUIV and OLD are different or
6707 if this is an in-out reload, recompute whether or not we
6708 still need a secondary register and what the icode should
6709 be. If we still need a secondary register and the class or
6710 icode is different, go back to reloading from OLD if using
6711 OLDEQUIV means that we got the wrong type of register. We
6712 cannot have different class or icode due to an in-out reload
6713 because we don't make such reloads when both the input and
6714 output need secondary reload registers. */
6716 if (! special
&& rl
->secondary_in_reload
>= 0)
6718 rtx second_reload_reg
= 0;
6719 rtx third_reload_reg
= 0;
6720 int secondary_reload
= rl
->secondary_in_reload
;
6721 rtx real_oldequiv
= oldequiv
;
6724 enum insn_code icode
;
6725 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
6727 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6728 and similarly for OLD.
6729 See comments in get_secondary_reload in reload.c. */
6730 /* If it is a pseudo that cannot be replaced with its
6731 equivalent MEM, we must fall back to reload_in, which
6732 will have all the necessary substitutions registered.
6733 Likewise for a pseudo that can't be replaced with its
6734 equivalent constant.
6736 Take extra care for subregs of such pseudos. Note that
6737 we cannot use reg_equiv_mem in this case because it is
6738 not in the right mode. */
6741 if (GET_CODE (tmp
) == SUBREG
)
6742 tmp
= SUBREG_REG (tmp
);
6744 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6745 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6746 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6748 if (! reg_equiv_mem
[REGNO (tmp
)]
6749 || num_not_at_initial_offset
6750 || GET_CODE (oldequiv
) == SUBREG
)
6751 real_oldequiv
= rl
->in
;
6753 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
6757 if (GET_CODE (tmp
) == SUBREG
)
6758 tmp
= SUBREG_REG (tmp
);
6760 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6761 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6762 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6764 if (! reg_equiv_mem
[REGNO (tmp
)]
6765 || num_not_at_initial_offset
6766 || GET_CODE (old
) == SUBREG
)
6769 real_old
= reg_equiv_mem
[REGNO (tmp
)];
6772 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
6773 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
6775 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
6777 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
6778 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
6779 /* We'd have to add more code for quartary reloads. */
6780 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
6782 icode
= rl
->secondary_in_icode
;
6784 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6785 || (rl
->in
!= 0 && rl
->out
!= 0))
6787 secondary_reload_info sri
, sri2
;
6788 enum reg_class new_class
, new_t_class
;
6790 sri
.icode
= CODE_FOR_nothing
;
6791 sri
.prev_sri
= NULL
;
6792 new_class
= targetm
.secondary_reload (1, real_oldequiv
, rl
->class,
6795 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
6796 second_reload_reg
= 0;
6797 else if (new_class
== NO_REGS
)
6799 if (reload_adjust_reg_for_icode (&second_reload_reg
,
6800 third_reload_reg
, sri
.icode
))
6801 icode
= sri
.icode
, third_reload_reg
= 0;
6803 oldequiv
= old
, real_oldequiv
= real_old
;
6805 else if (sri
.icode
!= CODE_FOR_nothing
)
6806 /* We currently lack a way to express this in reloads. */
6810 sri2
.icode
= CODE_FOR_nothing
;
6811 sri2
.prev_sri
= &sri
;
6812 new_t_class
= targetm
.secondary_reload (1, real_oldequiv
,
6813 new_class
, mode
, &sri
);
6814 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
6816 if (reload_adjust_reg_for_temp (&second_reload_reg
,
6819 third_reload_reg
= 0, tertiary_icode
= sri2
.icode
;
6821 oldequiv
= old
, real_oldequiv
= real_old
;
6823 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
6825 rtx intermediate
= second_reload_reg
;
6827 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
6829 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
6832 second_reload_reg
= intermediate
;
6833 tertiary_icode
= sri2
.icode
;
6836 oldequiv
= old
, real_oldequiv
= real_old
;
6838 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
6840 rtx intermediate
= second_reload_reg
;
6842 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
6844 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
6847 second_reload_reg
= intermediate
;
6848 tertiary_icode
= sri2
.icode
;
6851 oldequiv
= old
, real_oldequiv
= real_old
;
6854 /* This could be handled more intelligently too. */
6855 oldequiv
= old
, real_oldequiv
= real_old
;
6859 /* If we still need a secondary reload register, check
6860 to see if it is being used as a scratch or intermediate
6861 register and generate code appropriately. If we need
6862 a scratch register, use REAL_OLDEQUIV since the form of
6863 the insn may depend on the actual address if it is
6866 if (second_reload_reg
)
6868 if (icode
!= CODE_FOR_nothing
)
6870 /* We'd have to add extra code to handle this case. */
6871 gcc_assert (!third_reload_reg
);
6873 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6874 second_reload_reg
));
6879 /* See if we need a scratch register to load the
6880 intermediate register (a tertiary reload). */
6881 if (tertiary_icode
!= CODE_FOR_nothing
)
6883 emit_insn ((GEN_FCN (tertiary_icode
)
6884 (second_reload_reg
, real_oldequiv
,
6885 third_reload_reg
)));
6887 else if (third_reload_reg
)
6889 gen_reload (third_reload_reg
, real_oldequiv
,
6892 gen_reload (second_reload_reg
, third_reload_reg
,
6897 gen_reload (second_reload_reg
, real_oldequiv
,
6901 oldequiv
= second_reload_reg
;
6906 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6908 rtx real_oldequiv
= oldequiv
;
6910 if ((REG_P (oldequiv
)
6911 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6912 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6913 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6914 || (GET_CODE (oldequiv
) == SUBREG
6915 && REG_P (SUBREG_REG (oldequiv
))
6916 && (REGNO (SUBREG_REG (oldequiv
))
6917 >= FIRST_PSEUDO_REGISTER
)
6918 && ((reg_equiv_memory_loc
6919 [REGNO (SUBREG_REG (oldequiv
))] != 0)
6920 || (reg_equiv_constant
6921 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6922 || (CONSTANT_P (oldequiv
)
6923 && (PREFERRED_RELOAD_CLASS (oldequiv
,
6924 REGNO_REG_CLASS (REGNO (reloadreg
)))
6926 real_oldequiv
= rl
->in
;
6927 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
6931 if (flag_non_call_exceptions
)
6932 copy_eh_notes (insn
, get_insns ());
6934 /* End this sequence. */
6935 *where
= get_insns ();
6938 /* Update reload_override_in so that delete_address_reloads_1
6939 can see the actual register usage. */
6941 reload_override_in
[j
] = oldequiv
;
6944 /* Generate insns to for the output reload RL, which is for the insn described
6945 by CHAIN and has the number J. */
6947 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
6950 rtx reloadreg
= rl
->reg_rtx
;
6951 rtx insn
= chain
->insn
;
6954 enum machine_mode mode
= GET_MODE (old
);
6957 if (rl
->when_needed
== RELOAD_OTHER
)
6960 push_to_sequence (output_reload_insns
[rl
->opnum
]);
6962 /* Determine the mode to reload in.
6963 See comments above (for input reloading). */
6965 if (mode
== VOIDmode
)
6967 /* VOIDmode should never happen for an output. */
6968 if (asm_noperands (PATTERN (insn
)) < 0)
6969 /* It's the compiler's fault. */
6970 fatal_insn ("VOIDmode on an output", insn
);
6971 error_for_asm (insn
, "output operand is constant in %<asm%>");
6972 /* Prevent crash--use something we know is valid. */
6974 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6977 if (GET_MODE (reloadreg
) != mode
)
6978 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
6980 /* If we need two reload regs, set RELOADREG to the intermediate
6981 one, since it will be stored into OLD. We might need a secondary
6982 register only for an input reload, so check again here. */
6984 if (rl
->secondary_out_reload
>= 0)
6987 int secondary_reload
= rl
->secondary_out_reload
;
6988 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
6990 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6991 && reg_equiv_mem
[REGNO (old
)] != 0)
6992 real_old
= reg_equiv_mem
[REGNO (old
)];
6994 if (secondary_reload_class (0, rl
->class, mode
, real_old
) != NO_REGS
)
6996 rtx second_reloadreg
= reloadreg
;
6997 reloadreg
= rld
[secondary_reload
].reg_rtx
;
6999 /* See if RELOADREG is to be used as a scratch register
7000 or as an intermediate register. */
7001 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7003 /* We'd have to add extra code to handle this case. */
7004 gcc_assert (tertiary_reload
< 0);
7006 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7007 (real_old
, second_reloadreg
, reloadreg
)));
7012 /* See if we need both a scratch and intermediate reload
7015 enum insn_code tertiary_icode
7016 = rld
[secondary_reload
].secondary_out_icode
;
7018 /* We'd have to add more code for quartary reloads. */
7019 gcc_assert (tertiary_reload
< 0
7020 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7022 if (GET_MODE (reloadreg
) != mode
)
7023 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7025 if (tertiary_icode
!= CODE_FOR_nothing
)
7027 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7030 /* Copy primary reload reg to secondary reload reg.
7031 (Note that these have been swapped above, then
7032 secondary reload reg to OLD using our insn.) */
7034 /* If REAL_OLD is a paradoxical SUBREG, remove it
7035 and try to put the opposite SUBREG on
7037 if (GET_CODE (real_old
) == SUBREG
7038 && (GET_MODE_SIZE (GET_MODE (real_old
))
7039 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
7040 && 0 != (tem
= gen_lowpart_common
7041 (GET_MODE (SUBREG_REG (real_old
)),
7043 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
7045 gen_reload (reloadreg
, second_reloadreg
,
7046 rl
->opnum
, rl
->when_needed
);
7047 emit_insn ((GEN_FCN (tertiary_icode
)
7048 (real_old
, reloadreg
, third_reloadreg
)));
7054 /* Copy between the reload regs here and then to
7057 gen_reload (reloadreg
, second_reloadreg
,
7058 rl
->opnum
, rl
->when_needed
);
7059 if (tertiary_reload
>= 0)
7061 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7063 gen_reload (third_reloadreg
, reloadreg
,
7064 rl
->opnum
, rl
->when_needed
);
7065 reloadreg
= third_reloadreg
;
7072 /* Output the last reload insn. */
7077 /* Don't output the last reload if OLD is not the dest of
7078 INSN and is in the src and is clobbered by INSN. */
7079 if (! flag_expensive_optimizations
7081 || !(set
= single_set (insn
))
7082 || rtx_equal_p (old
, SET_DEST (set
))
7083 || !reg_mentioned_p (old
, SET_SRC (set
))
7084 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7085 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7086 gen_reload (old
, reloadreg
, rl
->opnum
,
7090 /* Look at all insns we emitted, just to be safe. */
7091 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7094 rtx pat
= PATTERN (p
);
7096 /* If this output reload doesn't come from a spill reg,
7097 clear any memory of reloaded copies of the pseudo reg.
7098 If this output reload comes from a spill reg,
7099 reg_has_output_reload will make this do nothing. */
7100 note_stores (pat
, forget_old_reloads_1
, NULL
);
7102 if (reg_mentioned_p (rl
->reg_rtx
, pat
))
7104 rtx set
= single_set (insn
);
7105 if (reload_spill_index
[j
] < 0
7107 && SET_SRC (set
) == rl
->reg_rtx
)
7109 int src
= REGNO (SET_SRC (set
));
7111 reload_spill_index
[j
] = src
;
7112 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7113 if (find_regno_note (insn
, REG_DEAD
, src
))
7114 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7116 if (REGNO (rl
->reg_rtx
) < FIRST_PSEUDO_REGISTER
)
7118 int s
= rl
->secondary_out_reload
;
7119 set
= single_set (p
);
7120 /* If this reload copies only to the secondary reload
7121 register, the secondary reload does the actual
7123 if (s
>= 0 && set
== NULL_RTX
)
7124 /* We can't tell what function the secondary reload
7125 has and where the actual store to the pseudo is
7126 made; leave new_spill_reg_store alone. */
7129 && SET_SRC (set
) == rl
->reg_rtx
7130 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7132 /* Usually the next instruction will be the
7133 secondary reload insn; if we can confirm
7134 that it is, setting new_spill_reg_store to
7135 that insn will allow an extra optimization. */
7136 rtx s_reg
= rld
[s
].reg_rtx
;
7137 rtx next
= NEXT_INSN (p
);
7138 rld
[s
].out
= rl
->out
;
7139 rld
[s
].out_reg
= rl
->out_reg
;
7140 set
= single_set (next
);
7141 if (set
&& SET_SRC (set
) == s_reg
7142 && ! new_spill_reg_store
[REGNO (s_reg
)])
7144 SET_HARD_REG_BIT (reg_is_output_reload
,
7146 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7150 new_spill_reg_store
[REGNO (rl
->reg_rtx
)] = p
;
7155 if (rl
->when_needed
== RELOAD_OTHER
)
7157 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7158 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7161 output_reload_insns
[rl
->opnum
] = get_insns ();
7163 if (flag_non_call_exceptions
)
7164 copy_eh_notes (insn
, get_insns ());
7169 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7170 and has the number J. */
7172 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7174 rtx insn
= chain
->insn
;
7175 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7176 ? rl
->in_reg
: rl
->in
);
7179 /* AUTO_INC reloads need to be handled even if inherited. We got an
7180 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7181 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7182 && ! rtx_equal_p (rl
->reg_rtx
, old
)
7183 && rl
->reg_rtx
!= 0)
7184 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7186 /* When inheriting a wider reload, we have a MEM in rl->in,
7187 e.g. inheriting a SImode output reload for
7188 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7189 if (optimize
&& reload_inherited
[j
] && rl
->in
7191 && MEM_P (rl
->in_reg
)
7192 && reload_spill_index
[j
] >= 0
7193 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7194 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7196 /* If we are reloading a register that was recently stored in with an
7197 output-reload, see if we can prove there was
7198 actually no need to store the old value in it. */
7201 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7202 that there may be multiple uses of the previous output reload.
7203 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7204 && rl
->when_needed
== RELOAD_FOR_INPUT
7205 && (reload_inherited
[j
] || reload_override_in
[j
])
7207 && REG_P (rl
->reg_rtx
)
7208 && spill_reg_store
[REGNO (rl
->reg_rtx
)] != 0
7210 /* There doesn't seem to be any reason to restrict this to pseudos
7211 and doing so loses in the case where we are copying from a
7212 register of the wrong class. */
7213 && (REGNO (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
7214 >= FIRST_PSEUDO_REGISTER
)
7216 /* The insn might have already some references to stackslots
7217 replaced by MEMs, while reload_out_reg still names the
7219 && (dead_or_set_p (insn
,
7220 spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
7221 || rtx_equal_p (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)],
7223 delete_output_reload (insn
, j
, REGNO (rl
->reg_rtx
));
7226 /* Do output reloading for reload RL, which is for the insn described by
7227 CHAIN and has the number J.
7228 ??? At some point we need to support handling output reloads of
7229 JUMP_INSNs or insns that set cc0. */
7231 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7234 rtx insn
= chain
->insn
;
7235 /* If this is an output reload that stores something that is
7236 not loaded in this same reload, see if we can eliminate a previous
7238 rtx pseudo
= rl
->out_reg
;
7243 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7244 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7245 && reg_last_reload_reg
[REGNO (pseudo
)])
7247 int pseudo_no
= REGNO (pseudo
);
7248 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7250 /* We don't need to test full validity of last_regno for
7251 inherit here; we only want to know if the store actually
7252 matches the pseudo. */
7253 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7254 && reg_reloaded_contents
[last_regno
] == pseudo_no
7255 && spill_reg_store
[last_regno
]
7256 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7257 delete_output_reload (insn
, j
, last_regno
);
7262 || rl
->reg_rtx
== old
7263 || rl
->reg_rtx
== 0)
7266 /* An output operand that dies right away does need a reload,
7267 but need not be copied from it. Show the new location in the
7269 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7270 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7272 XEXP (note
, 0) = rl
->reg_rtx
;
7275 /* Likewise for a SUBREG of an operand that dies. */
7276 else if (GET_CODE (old
) == SUBREG
7277 && REG_P (SUBREG_REG (old
))
7278 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7281 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
7285 else if (GET_CODE (old
) == SCRATCH
)
7286 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7287 but we don't want to make an output reload. */
7290 /* If is a JUMP_INSN, we can't support output reloads yet. */
7291 gcc_assert (NONJUMP_INSN_P (insn
));
7293 emit_output_reload_insns (chain
, rld
+ j
, j
);
7296 /* Reload number R reloads from or to a group of hard registers starting at
7297 register REGNO. Return true if it can be treated for inheritance purposes
7298 like a group of reloads, each one reloading a single hard register.
7299 The caller has already checked that the spill register and REGNO use
7300 the same number of registers to store the reload value. */
7303 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED
, int regno ATTRIBUTE_UNUSED
)
7305 #ifdef CANNOT_CHANGE_MODE_CLASS
7306 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index
[r
],
7307 GET_MODE (rld
[r
].reg_rtx
),
7308 reg_raw_mode
[reload_spill_index
[r
]])
7309 && !REG_CANNOT_CHANGE_MODE_P (regno
,
7310 GET_MODE (rld
[r
].reg_rtx
),
7311 reg_raw_mode
[regno
]));
7317 /* Output insns to reload values in and out of the chosen reload regs. */
7320 emit_reload_insns (struct insn_chain
*chain
)
7322 rtx insn
= chain
->insn
;
7326 CLEAR_HARD_REG_SET (reg_reloaded_died
);
7328 for (j
= 0; j
< reload_n_operands
; j
++)
7329 input_reload_insns
[j
] = input_address_reload_insns
[j
]
7330 = inpaddr_address_reload_insns
[j
]
7331 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
7332 = outaddr_address_reload_insns
[j
]
7333 = other_output_reload_insns
[j
] = 0;
7334 other_input_address_reload_insns
= 0;
7335 other_input_reload_insns
= 0;
7336 operand_reload_insns
= 0;
7337 other_operand_reload_insns
= 0;
7339 /* Dump reloads into the dump file. */
7342 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
7343 debug_reload_to_stream (dump_file
);
7346 /* Now output the instructions to copy the data into and out of the
7347 reload registers. Do these in the order that the reloads were reported,
7348 since reloads of base and index registers precede reloads of operands
7349 and the operands may need the base and index registers reloaded. */
7351 for (j
= 0; j
< n_reloads
; j
++)
7354 && REGNO (rld
[j
].reg_rtx
) < FIRST_PSEUDO_REGISTER
)
7355 new_spill_reg_store
[REGNO (rld
[j
].reg_rtx
)] = 0;
7357 do_input_reload (chain
, rld
+ j
, j
);
7358 do_output_reload (chain
, rld
+ j
, j
);
7361 /* Now write all the insns we made for reloads in the order expected by
7362 the allocation functions. Prior to the insn being reloaded, we write
7363 the following reloads:
7365 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7367 RELOAD_OTHER reloads.
7369 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7370 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7371 RELOAD_FOR_INPUT reload for the operand.
7373 RELOAD_FOR_OPADDR_ADDRS reloads.
7375 RELOAD_FOR_OPERAND_ADDRESS reloads.
7377 After the insn being reloaded, we write the following:
7379 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7380 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7381 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7382 reloads for the operand. The RELOAD_OTHER output reloads are
7383 output in descending order by reload number. */
7385 emit_insn_before (other_input_address_reload_insns
, insn
);
7386 emit_insn_before (other_input_reload_insns
, insn
);
7388 for (j
= 0; j
< reload_n_operands
; j
++)
7390 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
7391 emit_insn_before (input_address_reload_insns
[j
], insn
);
7392 emit_insn_before (input_reload_insns
[j
], insn
);
7395 emit_insn_before (other_operand_reload_insns
, insn
);
7396 emit_insn_before (operand_reload_insns
, insn
);
7398 for (j
= 0; j
< reload_n_operands
; j
++)
7400 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
7401 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
7402 x
= emit_insn_after (output_reload_insns
[j
], x
);
7403 emit_insn_after (other_output_reload_insns
[j
], x
);
7406 /* For all the spill regs newly reloaded in this instruction,
7407 record what they were reloaded from, so subsequent instructions
7408 can inherit the reloads.
7410 Update spill_reg_store for the reloads of this insn.
7411 Copy the elements that were updated in the loop above. */
7413 for (j
= 0; j
< n_reloads
; j
++)
7415 int r
= reload_order
[j
];
7416 int i
= reload_spill_index
[r
];
7418 /* If this is a non-inherited input reload from a pseudo, we must
7419 clear any memory of a previous store to the same pseudo. Only do
7420 something if there will not be an output reload for the pseudo
7422 if (rld
[r
].in_reg
!= 0
7423 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7425 rtx reg
= rld
[r
].in_reg
;
7427 if (GET_CODE (reg
) == SUBREG
)
7428 reg
= SUBREG_REG (reg
);
7431 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7432 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
7434 int nregno
= REGNO (reg
);
7436 if (reg_last_reload_reg
[nregno
])
7438 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7440 if (reg_reloaded_contents
[last_regno
] == nregno
)
7441 spill_reg_store
[last_regno
] = 0;
7446 /* I is nonneg if this reload used a register.
7447 If rld[r].reg_rtx is 0, this is an optional reload
7448 that we opted to ignore. */
7450 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
7452 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
7454 int part_reaches_end
= 0;
7455 int all_reaches_end
= 1;
7457 /* For a multi register reload, we need to check if all or part
7458 of the value lives to the end. */
7459 for (k
= 0; k
< nr
; k
++)
7461 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
7462 rld
[r
].when_needed
))
7463 part_reaches_end
= 1;
7465 all_reaches_end
= 0;
7468 /* Ignore reloads that don't reach the end of the insn in
7470 if (all_reaches_end
)
7472 /* First, clear out memory of what used to be in this spill reg.
7473 If consecutive registers are used, clear them all. */
7475 for (k
= 0; k
< nr
; k
++)
7477 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7478 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7481 /* Maybe the spill reg contains a copy of reload_out. */
7483 && (REG_P (rld
[r
].out
)
7487 || REG_P (rld
[r
].out_reg
)))
7489 rtx out
= (REG_P (rld
[r
].out
)
7493 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
7494 int nregno
= REGNO (out
);
7495 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7496 : hard_regno_nregs
[nregno
]
7497 [GET_MODE (rld
[r
].reg_rtx
)]);
7500 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7501 spill_reg_stored_to
[i
] = out
;
7502 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7504 piecemeal
= (nregno
< FIRST_PSEUDO_REGISTER
7506 && inherit_piecemeal_p (r
, nregno
));
7508 /* If NREGNO is a hard register, it may occupy more than
7509 one register. If it does, say what is in the
7510 rest of the registers assuming that both registers
7511 agree on how many words the object takes. If not,
7512 invalidate the subsequent registers. */
7514 if (nregno
< FIRST_PSEUDO_REGISTER
)
7515 for (k
= 1; k
< nnr
; k
++)
7516 reg_last_reload_reg
[nregno
+ k
]
7518 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7521 /* Now do the inverse operation. */
7522 for (k
= 0; k
< nr
; k
++)
7524 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7525 reg_reloaded_contents
[i
+ k
]
7526 = (nregno
>= FIRST_PSEUDO_REGISTER
|| !piecemeal
7529 reg_reloaded_insn
[i
+ k
] = insn
;
7530 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7531 if (HARD_REGNO_CALL_PART_CLOBBERED (i
+ k
, GET_MODE (out
)))
7532 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7536 /* Maybe the spill reg contains a copy of reload_in. Only do
7537 something if there will not be an output reload for
7538 the register being reloaded. */
7539 else if (rld
[r
].out_reg
== 0
7541 && ((REG_P (rld
[r
].in
)
7542 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
7543 && !REGNO_REG_SET_P (®_has_output_reload
,
7545 || (REG_P (rld
[r
].in_reg
)
7546 && !REGNO_REG_SET_P (®_has_output_reload
,
7547 REGNO (rld
[r
].in_reg
))))
7548 && ! reg_set_p (rld
[r
].reg_rtx
, PATTERN (insn
)))
7555 if (REG_P (rld
[r
].in
)
7556 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
7558 else if (REG_P (rld
[r
].in_reg
))
7561 in
= XEXP (rld
[r
].in_reg
, 0);
7562 nregno
= REGNO (in
);
7564 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7565 : hard_regno_nregs
[nregno
]
7566 [GET_MODE (rld
[r
].reg_rtx
)]);
7568 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7570 piecemeal
= (nregno
< FIRST_PSEUDO_REGISTER
7572 && inherit_piecemeal_p (r
, nregno
));
7574 if (nregno
< FIRST_PSEUDO_REGISTER
)
7575 for (k
= 1; k
< nnr
; k
++)
7576 reg_last_reload_reg
[nregno
+ k
]
7578 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7581 /* Unless we inherited this reload, show we haven't
7582 recently done a store.
7583 Previous stores of inherited auto_inc expressions
7584 also have to be discarded. */
7585 if (! reload_inherited
[r
]
7586 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
7587 spill_reg_store
[i
] = 0;
7589 for (k
= 0; k
< nr
; k
++)
7591 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7592 reg_reloaded_contents
[i
+ k
]
7593 = (nregno
>= FIRST_PSEUDO_REGISTER
|| !piecemeal
7596 reg_reloaded_insn
[i
+ k
] = insn
;
7597 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7598 if (HARD_REGNO_CALL_PART_CLOBBERED (i
+ k
, GET_MODE (in
)))
7599 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
, i
+ k
);
7604 /* However, if part of the reload reaches the end, then we must
7605 invalidate the old info for the part that survives to the end. */
7606 else if (part_reaches_end
)
7608 for (k
= 0; k
< nr
; k
++)
7609 if (reload_reg_reaches_end_p (i
+ k
,
7611 rld
[r
].when_needed
))
7612 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7616 /* The following if-statement was #if 0'd in 1.34 (or before...).
7617 It's reenabled in 1.35 because supposedly nothing else
7618 deals with this problem. */
7620 /* If a register gets output-reloaded from a non-spill register,
7621 that invalidates any previous reloaded copy of it.
7622 But forget_old_reloads_1 won't get to see it, because
7623 it thinks only about the original insn. So invalidate it here.
7624 Also do the same thing for RELOAD_OTHER constraints where the
7625 output is discarded. */
7627 && ((rld
[r
].out
!= 0
7628 && (REG_P (rld
[r
].out
)
7629 || (MEM_P (rld
[r
].out
)
7630 && REG_P (rld
[r
].out_reg
))))
7631 || (rld
[r
].out
== 0 && rld
[r
].out_reg
7632 && REG_P (rld
[r
].out_reg
))))
7634 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
7635 ? rld
[r
].out
: rld
[r
].out_reg
);
7636 int nregno
= REGNO (out
);
7637 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7639 rtx src_reg
, store_insn
= NULL_RTX
;
7641 reg_last_reload_reg
[nregno
] = 0;
7643 /* If we can find a hard register that is stored, record
7644 the storing insn so that we may delete this insn with
7645 delete_output_reload. */
7646 src_reg
= rld
[r
].reg_rtx
;
7648 /* If this is an optional reload, try to find the source reg
7649 from an input reload. */
7652 rtx set
= single_set (insn
);
7653 if (set
&& SET_DEST (set
) == rld
[r
].out
)
7657 src_reg
= SET_SRC (set
);
7659 for (k
= 0; k
< n_reloads
; k
++)
7661 if (rld
[k
].in
== src_reg
)
7663 src_reg
= rld
[k
].reg_rtx
;
7670 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7671 if (src_reg
&& REG_P (src_reg
)
7672 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7674 int src_regno
= REGNO (src_reg
);
7675 int nr
= hard_regno_nregs
[src_regno
][rld
[r
].mode
];
7676 /* The place where to find a death note varies with
7677 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7678 necessarily checked exactly in the code that moves
7679 notes, so just check both locations. */
7680 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7681 if (! note
&& store_insn
)
7682 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7685 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7686 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7687 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7688 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7689 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7690 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7691 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ nr
,
7692 GET_MODE (src_reg
)))
7693 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
7695 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7697 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7699 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7701 reg_last_reload_reg
[nregno
] = src_reg
;
7702 /* We have to set reg_has_output_reload here, or else
7703 forget_old_reloads_1 will clear reg_last_reload_reg
7705 SET_REGNO_REG_SET (®_has_output_reload
,
7711 int num_regs
= hard_regno_nregs
[nregno
][GET_MODE (out
)];
7713 while (num_regs
-- > 0)
7714 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7718 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7721 /* Go through the motions to emit INSN and test if it is strictly valid.
7722 Return the emitted insn if valid, else return NULL. */
7725 emit_insn_if_valid_for_reload (rtx insn
)
7727 rtx last
= get_last_insn ();
7730 insn
= emit_insn (insn
);
7731 code
= recog_memoized (insn
);
7735 extract_insn (insn
);
7736 /* We want constrain operands to treat this insn strictly in its
7737 validity determination, i.e., the way it would after reload has
7739 if (constrain_operands (1))
7743 delete_insns_since (last
);
7747 /* Emit code to perform a reload from IN (which may be a reload register) to
7748 OUT (which may also be a reload register). IN or OUT is from operand
7749 OPNUM with reload type TYPE.
7751 Returns first insn emitted. */
7754 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
7756 rtx last
= get_last_insn ();
7759 /* If IN is a paradoxical SUBREG, remove it and try to put the
7760 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7761 if (GET_CODE (in
) == SUBREG
7762 && (GET_MODE_SIZE (GET_MODE (in
))
7763 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7764 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7765 in
= SUBREG_REG (in
), out
= tem
;
7766 else if (GET_CODE (out
) == SUBREG
7767 && (GET_MODE_SIZE (GET_MODE (out
))
7768 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7769 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7770 out
= SUBREG_REG (out
), in
= tem
;
7772 /* How to do this reload can get quite tricky. Normally, we are being
7773 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7774 register that didn't get a hard register. In that case we can just
7775 call emit_move_insn.
7777 We can also be asked to reload a PLUS that adds a register or a MEM to
7778 another register, constant or MEM. This can occur during frame pointer
7779 elimination and while reloading addresses. This case is handled by
7780 trying to emit a single insn to perform the add. If it is not valid,
7781 we use a two insn sequence.
7783 Or we can be asked to reload an unary operand that was a fragment of
7784 an addressing mode, into a register. If it isn't recognized as-is,
7785 we try making the unop operand and the reload-register the same:
7786 (set reg:X (unop:X expr:Y))
7787 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7789 Finally, we could be called to handle an 'o' constraint by putting
7790 an address into a register. In that case, we first try to do this
7791 with a named pattern of "reload_load_address". If no such pattern
7792 exists, we just emit a SET insn and hope for the best (it will normally
7793 be valid on machines that use 'o').
7795 This entire process is made complex because reload will never
7796 process the insns we generate here and so we must ensure that
7797 they will fit their constraints and also by the fact that parts of
7798 IN might be being reloaded separately and replaced with spill registers.
7799 Because of this, we are, in some sense, just guessing the right approach
7800 here. The one listed above seems to work.
7802 ??? At some point, this whole thing needs to be rethought. */
7804 if (GET_CODE (in
) == PLUS
7805 && (REG_P (XEXP (in
, 0))
7806 || GET_CODE (XEXP (in
, 0)) == SUBREG
7807 || MEM_P (XEXP (in
, 0)))
7808 && (REG_P (XEXP (in
, 1))
7809 || GET_CODE (XEXP (in
, 1)) == SUBREG
7810 || CONSTANT_P (XEXP (in
, 1))
7811 || MEM_P (XEXP (in
, 1))))
7813 /* We need to compute the sum of a register or a MEM and another
7814 register, constant, or MEM, and put it into the reload
7815 register. The best possible way of doing this is if the machine
7816 has a three-operand ADD insn that accepts the required operands.
7818 The simplest approach is to try to generate such an insn and see if it
7819 is recognized and matches its constraints. If so, it can be used.
7821 It might be better not to actually emit the insn unless it is valid,
7822 but we need to pass the insn as an operand to `recog' and
7823 `extract_insn' and it is simpler to emit and then delete the insn if
7824 not valid than to dummy things up. */
7826 rtx op0
, op1
, tem
, insn
;
7829 op0
= find_replacement (&XEXP (in
, 0));
7830 op1
= find_replacement (&XEXP (in
, 1));
7832 /* Since constraint checking is strict, commutativity won't be
7833 checked, so we need to do that here to avoid spurious failure
7834 if the add instruction is two-address and the second operand
7835 of the add is the same as the reload reg, which is frequently
7836 the case. If the insn would be A = B + A, rearrange it so
7837 it will be A = A + B as constrain_operands expects. */
7839 if (REG_P (XEXP (in
, 1))
7840 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7841 tem
= op0
, op0
= op1
, op1
= tem
;
7843 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7844 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7846 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
7850 /* If that failed, we must use a conservative two-insn sequence.
7852 Use a move to copy one operand into the reload register. Prefer
7853 to reload a constant, MEM or pseudo since the move patterns can
7854 handle an arbitrary operand. If OP1 is not a constant, MEM or
7855 pseudo and OP1 is not a valid operand for an add instruction, then
7858 After reloading one of the operands into the reload register, add
7859 the reload register to the output register.
7861 If there is another way to do this for a specific machine, a
7862 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7865 code
= (int) add_optab
->handlers
[(int) GET_MODE (out
)].insn_code
;
7867 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
7869 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
7870 || (code
!= CODE_FOR_nothing
7871 && ! ((*insn_data
[code
].operand
[2].predicate
)
7872 (op1
, insn_data
[code
].operand
[2].mode
))))
7873 tem
= op0
, op0
= op1
, op1
= tem
;
7875 gen_reload (out
, op0
, opnum
, type
);
7877 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7878 This fixes a problem on the 32K where the stack pointer cannot
7879 be used as an operand of an add insn. */
7881 if (rtx_equal_p (op0
, op1
))
7884 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
7887 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7889 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7893 /* If that failed, copy the address register to the reload register.
7894 Then add the constant to the reload register. */
7896 gen_reload (out
, op1
, opnum
, type
);
7897 insn
= emit_insn (gen_add2_insn (out
, op0
));
7898 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7901 #ifdef SECONDARY_MEMORY_NEEDED
7902 /* If we need a memory location to do the move, do it that way. */
7903 else if ((REG_P (in
) || GET_CODE (in
) == SUBREG
)
7904 && reg_or_subregno (in
) < FIRST_PSEUDO_REGISTER
7905 && (REG_P (out
) || GET_CODE (out
) == SUBREG
)
7906 && reg_or_subregno (out
) < FIRST_PSEUDO_REGISTER
7907 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in
)),
7908 REGNO_REG_CLASS (reg_or_subregno (out
)),
7911 /* Get the memory to use and rewrite both registers to its mode. */
7912 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7914 if (GET_MODE (loc
) != GET_MODE (out
))
7915 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7917 if (GET_MODE (loc
) != GET_MODE (in
))
7918 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7920 gen_reload (loc
, in
, opnum
, type
);
7921 gen_reload (out
, loc
, opnum
, type
);
7924 else if (REG_P (out
) && UNARY_P (in
))
7931 op1
= find_replacement (&XEXP (in
, 0));
7932 if (op1
!= XEXP (in
, 0))
7933 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
7935 /* First, try a plain SET. */
7936 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
7940 /* If that failed, move the inner operand to the reload
7941 register, and try the same unop with the inner expression
7942 replaced with the reload register. */
7944 if (GET_MODE (op1
) != GET_MODE (out
))
7945 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
7949 gen_reload (out_moded
, op1
, opnum
, type
);
7952 = gen_rtx_SET (VOIDmode
, out
,
7953 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
7955 insn
= emit_insn_if_valid_for_reload (insn
);
7959 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7963 fatal_insn ("Failure trying to reload:", set
);
7965 /* If IN is a simple operand, use gen_move_insn. */
7966 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
7968 tem
= emit_insn (gen_move_insn (out
, in
));
7969 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
7970 mark_jump_label (in
, tem
, 0);
7973 #ifdef HAVE_reload_load_address
7974 else if (HAVE_reload_load_address
)
7975 emit_insn (gen_reload_load_address (out
, in
));
7978 /* Otherwise, just write (set OUT IN) and hope for the best. */
7980 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7982 /* Return the first insn emitted.
7983 We can not just return get_last_insn, because there may have
7984 been multiple instructions emitted. Also note that gen_move_insn may
7985 emit more than one insn itself, so we can not assume that there is one
7986 insn emitted per emit_insn_before call. */
7988 return last
? NEXT_INSN (last
) : get_insns ();
7991 /* Delete a previously made output-reload whose result we now believe
7992 is not needed. First we double-check.
7994 INSN is the insn now being processed.
7995 LAST_RELOAD_REG is the hard register number for which we want to delete
7996 the last output reload.
7997 J is the reload-number that originally used REG. The caller has made
7998 certain that reload J doesn't use REG any longer for input. */
8001 delete_output_reload (rtx insn
, int j
, int last_reload_reg
)
8003 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8004 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8007 int n_inherited
= 0;
8011 /* It is possible that this reload has been only used to set another reload
8012 we eliminated earlier and thus deleted this instruction too. */
8013 if (INSN_DELETED_P (output_reload_insn
))
8016 /* Get the raw pseudo-register referred to. */
8018 while (GET_CODE (reg
) == SUBREG
)
8019 reg
= SUBREG_REG (reg
);
8020 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
8022 /* This is unsafe if the operand occurs more often in the current
8023 insn than it is inherited. */
8024 for (k
= n_reloads
- 1; k
>= 0; k
--)
8026 rtx reg2
= rld
[k
].in
;
8029 if (MEM_P (reg2
) || reload_override_in
[k
])
8030 reg2
= rld
[k
].in_reg
;
8032 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8033 reg2
= XEXP (rld
[k
].in_reg
, 0);
8035 while (GET_CODE (reg2
) == SUBREG
)
8036 reg2
= SUBREG_REG (reg2
);
8037 if (rtx_equal_p (reg2
, reg
))
8039 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8042 reg2
= rld
[k
].out_reg
;
8045 while (GET_CODE (reg2
) == SUBREG
)
8046 reg2
= XEXP (reg2
, 0);
8047 if (rtx_equal_p (reg2
, reg
))
8054 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8055 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8056 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8059 n_occurrences
+= count_occurrences (PATTERN (insn
),
8060 eliminate_regs (substed
, 0,
8062 for (i1
= reg_equiv_alt_mem_list
[REGNO (reg
)]; i1
; i1
= XEXP (i1
, 1))
8064 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8065 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8067 if (n_occurrences
> n_inherited
)
8070 /* If the pseudo-reg we are reloading is no longer referenced
8071 anywhere between the store into it and here,
8072 and we're within the same basic block, then the value can only
8073 pass through the reload reg and end up here.
8074 Otherwise, give up--return. */
8075 for (i1
= NEXT_INSN (output_reload_insn
);
8076 i1
!= insn
; i1
= NEXT_INSN (i1
))
8078 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8080 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8081 && reg_mentioned_p (reg
, PATTERN (i1
)))
8083 /* If this is USE in front of INSN, we only have to check that
8084 there are no more references than accounted for by inheritance. */
8085 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8087 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8088 i1
= NEXT_INSN (i1
);
8090 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8096 /* We will be deleting the insn. Remove the spill reg information. */
8097 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8099 spill_reg_store
[last_reload_reg
+ k
] = 0;
8100 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8103 /* The caller has already checked that REG dies or is set in INSN.
8104 It has also checked that we are optimizing, and thus some
8105 inaccuracies in the debugging information are acceptable.
8106 So we could just delete output_reload_insn. But in some cases
8107 we can improve the debugging information without sacrificing
8108 optimization - maybe even improving the code: See if the pseudo
8109 reg has been completely replaced with reload regs. If so, delete
8110 the store insn and forget we had a stack slot for the pseudo. */
8111 if (rld
[j
].out
!= rld
[j
].in
8112 && REG_N_DEATHS (REGNO (reg
)) == 1
8113 && REG_N_SETS (REGNO (reg
)) == 1
8114 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
8115 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8119 /* We know that it was used only between here and the beginning of
8120 the current basic block. (We also know that the last use before
8121 INSN was the output reload we are thinking of deleting, but never
8122 mind that.) Search that range; see if any ref remains. */
8123 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8125 rtx set
= single_set (i2
);
8127 /* Uses which just store in the pseudo don't count,
8128 since if they are the only uses, they are dead. */
8129 if (set
!= 0 && SET_DEST (set
) == reg
)
8134 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8135 && reg_mentioned_p (reg
, PATTERN (i2
)))
8137 /* Some other ref remains; just delete the output reload we
8139 delete_address_reloads (output_reload_insn
, insn
);
8140 delete_insn (output_reload_insn
);
8145 /* Delete the now-dead stores into this pseudo. Note that this
8146 loop also takes care of deleting output_reload_insn. */
8147 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8149 rtx set
= single_set (i2
);
8151 if (set
!= 0 && SET_DEST (set
) == reg
)
8153 delete_address_reloads (i2
, insn
);
8161 /* For the debugging info, say the pseudo lives in this reload reg. */
8162 reg_renumber
[REGNO (reg
)] = REGNO (rld
[j
].reg_rtx
);
8164 mark_allocation_change (REGNO (reg
));
8165 alter_reg (REGNO (reg
), -1, false);
8169 delete_address_reloads (output_reload_insn
, insn
);
8170 delete_insn (output_reload_insn
);
8174 /* We are going to delete DEAD_INSN. Recursively delete loads of
8175 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8176 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8178 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
8180 rtx set
= single_set (dead_insn
);
8181 rtx set2
, dst
, prev
, next
;
8184 rtx dst
= SET_DEST (set
);
8186 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8188 /* If we deleted the store from a reloaded post_{in,de}c expression,
8189 we can delete the matching adds. */
8190 prev
= PREV_INSN (dead_insn
);
8191 next
= NEXT_INSN (dead_insn
);
8192 if (! prev
|| ! next
)
8194 set
= single_set (next
);
8195 set2
= single_set (prev
);
8197 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8198 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
8199 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
8201 dst
= SET_DEST (set
);
8202 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8203 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8204 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8205 || (INTVAL (XEXP (SET_SRC (set
), 1))
8206 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8208 delete_related_insns (prev
);
8209 delete_related_insns (next
);
8212 /* Subfunction of delete_address_reloads: process registers found in X. */
8214 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
8216 rtx prev
, set
, dst
, i2
;
8218 enum rtx_code code
= GET_CODE (x
);
8222 const char *fmt
= GET_RTX_FORMAT (code
);
8223 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8226 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8227 else if (fmt
[i
] == 'E')
8229 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8230 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8237 if (spill_reg_order
[REGNO (x
)] < 0)
8240 /* Scan backwards for the insn that sets x. This might be a way back due
8242 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8244 code
= GET_CODE (prev
);
8245 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8249 if (reg_set_p (x
, PATTERN (prev
)))
8251 if (reg_referenced_p (x
, PATTERN (prev
)))
8254 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8256 /* Check that PREV only sets the reload register. */
8257 set
= single_set (prev
);
8260 dst
= SET_DEST (set
);
8262 || ! rtx_equal_p (dst
, x
))
8264 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8266 /* Check if DST was used in a later insn -
8267 it might have been inherited. */
8268 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8274 if (reg_referenced_p (dst
, PATTERN (i2
)))
8276 /* If there is a reference to the register in the current insn,
8277 it might be loaded in a non-inherited reload. If no other
8278 reload uses it, that means the register is set before
8280 if (i2
== current_insn
)
8282 for (j
= n_reloads
- 1; j
>= 0; j
--)
8283 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8284 || reload_override_in
[j
] == dst
)
8286 for (j
= n_reloads
- 1; j
>= 0; j
--)
8287 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
8296 /* If DST is still live at CURRENT_INSN, check if it is used for
8297 any reload. Note that even if CURRENT_INSN sets DST, we still
8298 have to check the reloads. */
8299 if (i2
== current_insn
)
8301 for (j
= n_reloads
- 1; j
>= 0; j
--)
8302 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8303 || reload_override_in
[j
] == dst
)
8305 /* ??? We can't finish the loop here, because dst might be
8306 allocated to a pseudo in this block if no reload in this
8307 block needs any of the classes containing DST - see
8308 spill_hard_reg. There is no easy way to tell this, so we
8309 have to scan till the end of the basic block. */
8311 if (reg_set_p (dst
, PATTERN (i2
)))
8315 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
8316 reg_reloaded_contents
[REGNO (dst
)] = -1;
8320 /* Output reload-insns to reload VALUE into RELOADREG.
8321 VALUE is an autoincrement or autodecrement RTX whose operand
8322 is a register or memory location;
8323 so reloading involves incrementing that location.
8324 IN is either identical to VALUE, or some cheaper place to reload from.
8326 INC_AMOUNT is the number to increment or decrement by (always positive).
8327 This cannot be deduced from VALUE.
8329 Return the instruction that stores into RELOADREG. */
8332 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
8334 /* REG or MEM to be copied and incremented. */
8335 rtx incloc
= find_replacement (&XEXP (value
, 0));
8336 /* Nonzero if increment after copying. */
8337 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
8338 || GET_CODE (value
) == POST_MODIFY
);
8344 rtx real_in
= in
== value
? incloc
: in
;
8346 /* No hard register is equivalent to this register after
8347 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8348 we could inc/dec that register as well (maybe even using it for
8349 the source), but I'm not sure it's worth worrying about. */
8351 reg_last_reload_reg
[REGNO (incloc
)] = 0;
8353 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
8355 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
8356 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
8360 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
8361 inc_amount
= -inc_amount
;
8363 inc
= GEN_INT (inc_amount
);
8366 /* If this is post-increment, first copy the location to the reload reg. */
8367 if (post
&& real_in
!= reloadreg
)
8368 emit_insn (gen_move_insn (reloadreg
, real_in
));
8372 /* See if we can directly increment INCLOC. Use a method similar to
8373 that in gen_reload. */
8375 last
= get_last_insn ();
8376 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
8377 gen_rtx_PLUS (GET_MODE (incloc
),
8380 code
= recog_memoized (add_insn
);
8383 extract_insn (add_insn
);
8384 if (constrain_operands (1))
8386 /* If this is a pre-increment and we have incremented the value
8387 where it lives, copy the incremented value to RELOADREG to
8388 be used as an address. */
8391 emit_insn (gen_move_insn (reloadreg
, incloc
));
8396 delete_insns_since (last
);
8399 /* If couldn't do the increment directly, must increment in RELOADREG.
8400 The way we do this depends on whether this is pre- or post-increment.
8401 For pre-increment, copy INCLOC to the reload register, increment it
8402 there, then save back. */
8406 if (in
!= reloadreg
)
8407 emit_insn (gen_move_insn (reloadreg
, real_in
));
8408 emit_insn (gen_add2_insn (reloadreg
, inc
));
8409 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8414 Because this might be a jump insn or a compare, and because RELOADREG
8415 may not be available after the insn in an input reload, we must do
8416 the incrementation before the insn being reloaded for.
8418 We have already copied IN to RELOADREG. Increment the copy in
8419 RELOADREG, save that back, then decrement RELOADREG so it has
8420 the original value. */
8422 emit_insn (gen_add2_insn (reloadreg
, inc
));
8423 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8424 if (GET_CODE (inc
) == CONST_INT
)
8425 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-INTVAL (inc
))));
8427 emit_insn (gen_sub2_insn (reloadreg
, inc
));
8435 add_auto_inc_notes (rtx insn
, rtx x
)
8437 enum rtx_code code
= GET_CODE (x
);
8441 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
8444 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
8448 /* Scan all the operand sub-expressions. */
8449 fmt
= GET_RTX_FORMAT (code
);
8450 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8453 add_auto_inc_notes (insn
, XEXP (x
, i
));
8454 else if (fmt
[i
] == 'E')
8455 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8456 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
8461 /* Copy EH notes from an insn to its reloads. */
8463 copy_eh_notes (rtx insn
, rtx x
)
8465 rtx eh_note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
8468 for (; x
!= 0; x
= NEXT_INSN (x
))
8470 if (may_trap_p (PATTERN (x
)))
8472 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (eh_note
, 0),
8478 /* This is used by reload pass, that does emit some instructions after
8479 abnormal calls moving basic block end, but in fact it wants to emit
8480 them on the edge. Looks for abnormal call edges, find backward the
8481 proper call and fix the damage.
8483 Similar handle instructions throwing exceptions internally. */
8485 fixup_abnormal_edges (void)
8487 bool inserted
= false;
8495 /* Look for cases we are interested in - calls or instructions causing
8497 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8499 if (e
->flags
& EDGE_ABNORMAL_CALL
)
8501 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
8502 == (EDGE_ABNORMAL
| EDGE_EH
))
8505 if (e
&& !CALL_P (BB_END (bb
))
8506 && !can_throw_internal (BB_END (bb
)))
8510 /* Get past the new insns generated. Allow notes, as the insns
8511 may be already deleted. */
8513 while ((NONJUMP_INSN_P (insn
) || NOTE_P (insn
))
8514 && !can_throw_internal (insn
)
8515 && insn
!= BB_HEAD (bb
))
8516 insn
= PREV_INSN (insn
);
8518 if (CALL_P (insn
) || can_throw_internal (insn
))
8522 stop
= NEXT_INSN (BB_END (bb
));
8524 insn
= NEXT_INSN (insn
);
8526 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
8527 if (e
->flags
& EDGE_FALLTHRU
)
8530 while (insn
&& insn
!= stop
)
8532 next
= NEXT_INSN (insn
);
8537 /* Sometimes there's still the return value USE.
8538 If it's placed after a trapping call (i.e. that
8539 call is the last insn anyway), we have no fallthru
8540 edge. Simply delete this use and don't try to insert
8541 on the non-existent edge. */
8542 if (GET_CODE (PATTERN (insn
)) != USE
)
8544 /* We're not deleting it, we're moving it. */
8545 INSN_DELETED_P (insn
) = 0;
8546 PREV_INSN (insn
) = NULL_RTX
;
8547 NEXT_INSN (insn
) = NULL_RTX
;
8549 insert_insn_on_edge (insn
, e
);
8557 /* It may be that we don't find any such trapping insn. In this
8558 case we discovered quite late that the insn that had been
8559 marked as can_throw_internal in fact couldn't trap at all.
8560 So we should in fact delete the EH edges out of the block. */
8562 purge_dead_edges (bb
);
8566 /* We've possibly turned single trapping insn into multiple ones. */
8567 if (flag_non_call_exceptions
)
8570 blocks
= sbitmap_alloc (last_basic_block
);
8571 sbitmap_ones (blocks
);
8572 find_many_sub_basic_blocks (blocks
);
8576 commit_edge_insertions ();
8578 #ifdef ENABLE_CHECKING
8579 /* Verify that we didn't turn one trapping insn into many, and that
8580 we found and corrected all of the problems wrt fixups on the
8582 verify_flow_info ();