1 /* Integrated Register Allocator entry point.
2 Copyright (C) 2006, 2007
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
23 /* The integrated register allocator (IRA) is called integrated
24 because register coalescing and register live range splitting are
25 done on-the-fly during coloring. Register coalescing is done by
26 hard register preferencing during hard register assigning. The
27 live range splitting is a byproduct of the regional register
30 The regional allocation is top-down process. The first we do
31 allocation for all function then we improve it for loops then their
32 subloops and so on. To reduce register shuffling, the same
33 mechanism of hard register prefrencing is used. This approach
34 works as good as Callahan-Koblentz algorithm but it is simpler.
35 We use Chaitin-Briggs coloring for each loop (or function) with
36 optional biased coloring. If pseudo-registers got different
37 location on loop borders we rename them inside the loop and
38 generate pseudo-register move insns. Some optimizations (like
39 removing redundant stores, moving register shuffling to less
40 frequent points, and code duplication reducing) to minimize effect
41 of register shuffling is done
43 If we don't improve register allocation for loops we get classic
44 Chaitin-Briggs coloring (only instead of separate pass of
45 coalescing, we use hard register preferencing).
47 Optionally we implements Chow's priority coloring only for all
48 function. It is quite analogous to the current gcc global register
49 allocator only we use more sophisticated hard register
52 Literature is worth to read for better understanding the code:
54 o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
55 Graph Coloring Register Allocation.
57 o David Callahan, Brian Koblenz. Register allocation via
58 hierarchical graph coloring
60 o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
61 Coloring Register Allocation: A Study of the Chaitin-Briggs and
62 Callahan-Koblenz Algorithms.
64 o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
65 Register Allocation Based on Graph Fusion.
72 #include "coretypes.h"
81 #include "hard-reg-set.h"
82 #include "basic-block.h"
87 #include "tree-pass.h"
91 #include "integrate.h"
96 static void setup_inner_mode (void);
97 static void setup_reg_mode_hard_regset (void);
98 static void setup_class_subset_and_move_costs (void);
99 static void setup_class_hard_regs (void);
100 static void setup_available_class_regs (void);
101 static void setup_alloc_regs (int);
102 static void setup_reg_subclasses (void);
103 #ifdef IRA_COVER_CLASSES
104 static void setup_cover_classes (void);
105 static void setup_class_translate (void);
107 static void print_class_cover (FILE *);
108 static void find_reg_class_closure (void);
109 static void setup_reg_class_nregs (void);
110 static void setup_prohibited_class_mode_regs (void);
111 static void setup_eliminable_regset (void);
112 static void find_reg_equiv_invariant_const (void);
113 static void setup_reg_renumber (int, int);
114 static int setup_pseudo_assignment_from_reg_renumber (void);
115 static void calculate_allocation_cost (void);
116 #ifdef ENABLE_IRA_CHECKING
117 static void check_allocation (void);
119 static void fix_reg_equiv_init (void);
120 #ifdef ENABLE_IRA_CHECKING
121 static void print_redundant_copies (void);
123 static void setup_preferred_alternate_classes (void);
125 static bool gate_ira (void);
126 static unsigned int rest_of_handle_ira (void);
128 /* Dump file for IRA. */
131 /* The number of elements in the following array. */
132 int spilled_reg_stack_slots_num
;
134 /* The following array contains description of spilled registers stack
135 slots have been used in the current function so far. */
136 struct spilled_reg_stack_slot
*spilled_reg_stack_slots
;
138 /* The following variable values are correspondingly overall cost of
139 the allocation, cost of hard register usage for the pseudos, cost
140 of memory usage for the pseudos, cost of loads, stores and register
141 move insns generated for register live range splitting. */
143 int reg_cost
, mem_cost
;
144 int load_cost
, store_cost
, shuffle_cost
;
145 int move_loops_num
, additional_jumps_num
;
147 /* A mode whose value is immediately contained in given mode
149 unsigned char mode_inner_mode
[NUM_MACHINE_MODES
];
151 /* The following array is a map hard regs X modes -> number registers
152 for store value of given mode starting with given hard
154 HARD_REG_SET reg_mode_hard_regset
[FIRST_PSEUDO_REGISTER
] [NUM_MACHINE_MODES
];
156 /* The following two variables are array analog of macros
157 MEMORY_MOVE_COST and REGISTER_MOVE_COST. */
158 int memory_move_cost
[MAX_MACHINE_MODE
] [N_REG_CLASSES
] [2];
159 int register_move_cost
[MAX_MACHINE_MODE
] [N_REG_CLASSES
] [N_REG_CLASSES
];
161 /* Nonzero value of element of the following array means that the
162 1st class is a subset of the 2nd class. */
163 int class_subset_p
[N_REG_CLASSES
] [N_REG_CLASSES
];
165 /* Temporary hard reg set used for different calculation. */
166 static HARD_REG_SET temp_hard_regset
;
170 /* The function sets up mode_inner_mode array. */
172 setup_inner_mode (void)
175 enum machine_mode wider
;
177 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
178 mode_inner_mode
[i
] = VOIDmode
;
179 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
181 wider
= GET_MODE_WIDER_MODE (i
);
182 if (wider
!= VOIDmode
)
184 ira_assert (mode_inner_mode
[wider
] == VOIDmode
);
185 mode_inner_mode
[wider
] = i
;
192 /* The function sets up map REG_MODE_HARD_REGSET. */
194 setup_reg_mode_hard_regset (void)
196 int i
, m
, hard_regno
;
198 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
199 for (hard_regno
= 0; hard_regno
< FIRST_PSEUDO_REGISTER
; hard_regno
++)
201 CLEAR_HARD_REG_SET (reg_mode_hard_regset
[hard_regno
] [m
]);
202 for (i
= hard_regno_nregs
[hard_regno
] [m
] - 1; i
>= 0; i
--)
203 if (hard_regno
+ i
< FIRST_PSEUDO_REGISTER
)
204 SET_HARD_REG_BIT (reg_mode_hard_regset
[hard_regno
] [m
],
211 /* The function sets up MEMORY_MOVE_COST, REGISTER_MOVE_COST and
214 setup_class_subset_and_move_costs (void)
217 enum machine_mode mode
;
219 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
221 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
223 memory_move_cost
[mode
] [cl
] [0] = MEMORY_MOVE_COST (mode
, cl
, 0);
224 memory_move_cost
[mode
] [cl
] [1] = MEMORY_MOVE_COST (mode
, cl
, 1);
227 for (cl2
= (int) N_REG_CLASSES
- 1; cl2
>= 0; cl2
--)
229 if (cl
!= NO_REGS
&& cl2
!= NO_REGS
)
230 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
231 register_move_cost
[mode
] [cl
] [cl2
]
232 = REGISTER_MOVE_COST (mode
, cl
, cl2
);
233 GO_IF_HARD_REG_SUBSET (reg_class_contents
[cl
],
234 reg_class_contents
[cl2
],
236 class_subset_p
[cl
] [cl2
] = FALSE
;
240 class_subset_p
[cl
] [cl2
] = TRUE
;
247 /* Hard registers can not be used for the register allocator for all
248 functions of the current compile unit. */
249 static HARD_REG_SET no_unit_alloc_regs
;
251 /* Hard registers which can be used for the allocation of given
252 register class. The order is defined by the allocation order. */
253 short class_hard_regs
[N_REG_CLASSES
] [FIRST_PSEUDO_REGISTER
];
255 /* The size of the above array for given register class. */
256 int class_hard_regs_num
[N_REG_CLASSES
];
258 /* Index (in class_hard_regs) for given register class and hard
259 register (in general case a hard register can belong to several
260 register classes). */
261 short class_hard_reg_index
[N_REG_CLASSES
] [FIRST_PSEUDO_REGISTER
];
263 /* The function sets up the three arrays declared above. */
265 setup_class_hard_regs (void)
267 int cl
, i
, hard_regno
, n
;
268 HARD_REG_SET processed_hard_reg_set
;
270 ira_assert (SHRT_MAX
>= FIRST_PSEUDO_REGISTER
);
271 /* We could call ORDER_REGS_FOR_LOCAL_ALLOC here (it is usually
272 putting hard callee-used hard registers first). But our
273 heuristics work better. */
274 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
276 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
277 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
278 CLEAR_HARD_REG_SET (processed_hard_reg_set
);
279 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
281 #ifdef REG_ALLOC_ORDER
282 hard_regno
= reg_alloc_order
[i
];
286 if (TEST_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
))
288 SET_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
);
289 if (! TEST_HARD_REG_BIT (temp_hard_regset
, hard_regno
))
290 class_hard_reg_index
[cl
] [hard_regno
] = -1;
293 class_hard_reg_index
[cl
] [hard_regno
] = n
;
294 class_hard_regs
[cl
] [n
++] = hard_regno
;
297 class_hard_regs_num
[cl
] = n
;
301 /* Number of class hard registers available for the register
302 allocation for given classes. */
303 int available_class_regs
[N_REG_CLASSES
];
305 /* Function setting up AVAILABLE_CLASS_REGS. */
307 setup_available_class_regs (void)
311 memset (available_class_regs
, 0, sizeof (available_class_regs
));
312 for (i
= 0; i
< N_REG_CLASSES
; i
++)
314 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
315 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
316 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
317 if (TEST_HARD_REG_BIT (temp_hard_regset
, j
))
318 available_class_regs
[i
]++;
322 /* The function setting up different global variables defining hard
323 registers for the allocation. It depends on USE_HARD_FRAME_P whose
324 nonzero value means that we can use hard frame pointer for the
327 setup_alloc_regs (int use_hard_frame_p
)
329 COPY_HARD_REG_SET (no_unit_alloc_regs
, fixed_reg_set
);
330 if (! use_hard_frame_p
)
331 SET_HARD_REG_BIT (no_unit_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
332 setup_class_hard_regs ();
333 setup_available_class_regs ();
338 /* Define the following macro if allocation through malloc if
340 /*#define IRA_NO_OBSTACK*/
342 #ifndef IRA_NO_OBSTACK
343 /* Obstack used for storing all dynamic data (except bitmaps) of the
345 static struct obstack ira_obstack
;
348 /* Obstack used for storing all bitmaps of the IRA. */
349 static struct bitmap_obstack ira_bitmap_obstack
;
351 /* The function allocates memory of size LEN for IRA data. */
353 ira_allocate (size_t len
)
357 #ifndef IRA_NO_OBSTACK
358 res
= obstack_alloc (&ira_obstack
, len
);
365 /* The function free memory ADDR allocated for IRA data. */
367 ira_free (void *addr ATTRIBUTE_UNUSED
)
369 #ifndef IRA_NO_OBSTACK
377 /* The function allocates bitmap for IRA. */
379 ira_allocate_bitmap (void)
381 return BITMAP_ALLOC (&ira_bitmap_obstack
);
384 /* The function frees bitmap B allocated for IRA. */
386 ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED
)
391 /* The function allocates regset for IRA. */
393 ira_allocate_regset (void)
395 return ALLOC_REG_SET (&ira_bitmap_obstack
);
398 /* The function frees regset R allocated for IRA. */
400 ira_free_regset (regset r ATTRIBUTE_UNUSED
)
407 /* The function returns nonzero if hard registers starting with
408 HARD_REGNO and containing value of MODE are not in set
411 hard_reg_not_in_set_p (int hard_regno
, enum machine_mode mode
,
412 HARD_REG_SET hard_regset
)
416 ira_assert (hard_regno
>= 0);
417 for (i
= hard_regno_nregs
[hard_regno
] [mode
] - 1; i
>= 0; i
--)
418 if (TEST_HARD_REG_BIT (hard_regset
, hard_regno
+ i
))
425 /* The function outputs information about allocation of all pseudos
428 print_disposition (FILE *f
)
434 fprintf (f
, "Disposition:");
435 max_regno
= max_reg_num ();
436 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
437 for (p
= regno_pseudo_map
[i
]; p
!= NULL
; p
= PSEUDO_NEXT_REGNO_PSEUDO (p
))
442 fprintf (f
, " %4d:r%-4d", PSEUDO_NUM (p
), PSEUDO_REGNO (p
));
443 if ((bb
= PSEUDO_LOOP_TREE_NODE (p
)->bb
) != NULL
)
444 fprintf (f
, "b%-3d", bb
->index
);
446 fprintf (f
, "l%-3d", PSEUDO_LOOP_TREE_NODE (p
)->loop
->num
);
447 if (PSEUDO_HARD_REGNO (p
) >= 0)
448 fprintf (f
, " %3d", PSEUDO_HARD_REGNO (p
));
455 /* The function outputs information about allocation of all pseudos
458 debug_disposition (void)
460 print_disposition (stderr
);
465 /* For each reg class, table listing all the classes contained in it
466 (excluding the class itself. Fixed registers are excluded from the
468 static enum reg_class alloc_reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
470 /* The function initializes the tables of subclasses of each reg
473 setup_reg_subclasses (void)
477 for (i
= 0; i
< N_REG_CLASSES
; i
++)
478 for (j
= 0; j
< N_REG_CLASSES
; j
++)
479 alloc_reg_class_subclasses
[i
] [j
] = LIM_REG_CLASSES
;
481 for (i
= 0; i
< N_REG_CLASSES
; i
++)
483 if (i
== (int) NO_REGS
)
486 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
487 AND_COMPL_HARD_REG_SET (temp_hard_regset
, fixed_reg_set
);
488 GO_IF_HARD_REG_EQUAL (temp_hard_regset
, zero_hard_reg_set
, cont
);
493 for (j
= 0; j
< N_REG_CLASSES
; j
++)
498 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
],
499 reg_class_contents
[j
], subclass
);
502 p
= &alloc_reg_class_subclasses
[j
] [0];
503 while (*p
!= LIM_REG_CLASSES
) p
++;
504 *p
= (enum reg_class
) i
;
511 /* The value is size of the subsequent array. */
512 int reg_class_cover_size
;
514 /* The array containing cover classes whose hard registers are used
515 for the allocation -- see also comments for macro
516 IRA_COVER_CLASSES. */
517 enum reg_class reg_class_cover
[N_REG_CLASSES
];
520 #ifdef IRA_COVER_CLASSES
522 /* The function checks IRA_COVER_CLASSES and sets the two global
523 variables defined above. */
525 setup_cover_classes (void)
529 static enum reg_class classes
[] = IRA_COVER_CLASSES
;
531 reg_class_cover_size
= 0;
532 for (i
= 0; (cl
= classes
[i
]) != LIM_REG_CLASSES
; i
++)
534 for (j
= 0; j
< i
; j
++)
535 if (reg_classes_intersect_p (cl
, classes
[j
]))
537 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
538 AND_COMPL_HARD_REG_SET (temp_hard_regset
, fixed_reg_set
);
539 GO_IF_HARD_REG_EQUAL (temp_hard_regset
, zero_hard_reg_set
, cont
);
540 reg_class_cover
[reg_class_cover_size
++] = cl
;
547 /* Map of register classes to corresponding cover class containing the
548 given class. If given class is not a subset of a cover class, we
549 translate it into the cheapest cover class. */
550 enum reg_class class_translate
[N_REG_CLASSES
];
552 #ifdef IRA_COVER_CLASSES
554 /* The function sets up array CLASS_TRANSLATE. */
556 setup_class_translate (void)
558 enum reg_class cl
, cover_class
, best_class
, *cl_ptr
;
559 enum machine_mode mode
;
560 int i
, cost
, min_cost
, best_cost
;
562 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
563 class_translate
[cl
] = NO_REGS
;
564 for (i
= 0; i
< reg_class_cover_size
; i
++)
566 cover_class
= reg_class_cover
[i
];
567 for (cl_ptr
= &alloc_reg_class_subclasses
[cover_class
] [0];
568 (cl
= *cl_ptr
) != LIM_REG_CLASSES
;
571 if (class_translate
[cl
] == NO_REGS
)
572 class_translate
[cl
] = cover_class
;
573 #ifdef ENABLE_IRA_CHECKING
576 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
577 AND_COMPL_HARD_REG_SET (temp_hard_regset
, fixed_reg_set
);
578 GO_IF_HARD_REG_SUBSET (temp_hard_regset
, zero_hard_reg_set
, ok
);
585 class_translate
[cover_class
] = cover_class
;
587 /* For classes which are not fully covered by a cover class (in
588 other words covered by more one cover class), use the cheapest
590 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
592 if (cl
== NO_REGS
|| class_translate
[cl
] != NO_REGS
)
594 best_class
= NO_REGS
;
596 for (i
= 0; i
< reg_class_cover_size
; i
++)
598 cover_class
= reg_class_cover
[i
];
599 COPY_HARD_REG_SET (temp_hard_regset
,
600 reg_class_contents
[cover_class
]);
601 AND_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
602 GO_IF_HARD_REG_EQUAL (temp_hard_regset
, zero_hard_reg_set
,
605 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
607 cost
= (memory_move_cost
[mode
] [cl
] [0]
608 + memory_move_cost
[mode
] [cl
] [1]);
612 if (best_class
== NO_REGS
|| best_cost
> min_cost
)
614 best_class
= cover_class
;
615 best_cost
= min_cost
;
620 class_translate
[cl
] = best_class
;
625 /* The function outputs all cover classes and the translation map into
628 print_class_cover (FILE *f
)
630 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
633 fprintf (f
, "Class cover:\n");
634 for (i
= 0; i
< reg_class_cover_size
; i
++)
635 fprintf (f
, " %s", reg_class_names
[reg_class_cover
[i
]]);
636 fprintf (f
, "\nClass translation:\n");
637 for (i
= 0; i
< N_REG_CLASSES
; i
++)
638 fprintf (f
, " %s -> %s\n", reg_class_names
[i
],
639 reg_class_names
[class_translate
[i
]]);
642 /* The function outputs all cover classes and the translation map into
645 debug_class_cover (void)
647 print_class_cover (stderr
);
650 /* Function setting up different arrays concerning class subsets and
653 find_reg_class_closure (void)
655 setup_reg_subclasses ();
656 #ifdef IRA_COVER_CLASSES
657 setup_cover_classes ();
658 setup_class_translate ();
664 /* Map: register class x machine mode -> number of hard registers of
665 given class needed to store value of given mode. If the number is
666 different, the size will be negative. */
667 int reg_class_nregs
[N_REG_CLASSES
] [MAX_MACHINE_MODE
];
669 /* Maximal value of the previous array elements. */
672 /* Function forming REG_CLASS_NREGS map. */
674 setup_reg_class_nregs (void)
680 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
681 for (m
= 0; m
< MAX_MACHINE_MODE
; m
++)
683 reg_class_nregs
[cl
] [m
] = CLASS_MAX_NREGS (cl
, m
);
684 if (max_nregs
< reg_class_nregs
[cl
] [m
])
685 max_nregs
= reg_class_nregs
[cl
] [m
];
691 /* Array whose values are hard regset of hard registers of given
692 register class whose HARD_REGNO_MODE_OK values are zero. */
693 HARD_REG_SET prohibited_class_mode_regs
[N_REG_CLASSES
] [NUM_MACHINE_MODES
];
695 /* The function setting up PROHIBITED_CLASS_MODE_REGS. */
697 setup_prohibited_class_mode_regs (void)
699 int i
, j
, k
, hard_regno
;
702 for (i
= 0; i
< reg_class_cover_size
; i
++)
704 cl
= reg_class_cover
[i
];
705 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
707 CLEAR_HARD_REG_SET (prohibited_class_mode_regs
[cl
] [j
]);
708 for (k
= class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
710 hard_regno
= class_hard_regs
[cl
] [k
];
711 if (! HARD_REGNO_MODE_OK (hard_regno
, j
))
712 SET_HARD_REG_BIT (prohibited_class_mode_regs
[cl
] [j
],
721 /* Hard regsets whose all bits are correspondingly zero or one. */
722 HARD_REG_SET zero_hard_reg_set
;
723 HARD_REG_SET one_hard_reg_set
;
725 /* Function called once during compiler work. It sets up different
726 arrays whose values don't depend on the compiled function. */
730 CLEAR_HARD_REG_SET (zero_hard_reg_set
);
731 SET_HARD_REG_SET (one_hard_reg_set
);
733 setup_reg_mode_hard_regset ();
734 setup_class_subset_and_move_costs ();
735 setup_alloc_regs (flag_omit_frame_pointer
!= 0);
736 find_reg_class_closure ();
737 setup_reg_class_nregs ();
738 setup_prohibited_class_mode_regs ();
739 init_ira_costs_once ();
744 /* Function specific hard registers excluded from the allocation. */
745 HARD_REG_SET no_alloc_regs
;
747 /* The function sets up ELIMINABLE_REGSET, NO_ALLOC_REGS, and
750 setup_eliminable_regset (void)
753 #ifdef ELIMINABLE_REGS
754 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
757 = (! flag_omit_frame_pointer
758 || (current_function_calls_alloca
&& EXIT_IGNORE_STACK
)
759 || FRAME_POINTER_REQUIRED
);
761 COPY_HARD_REG_SET (no_alloc_regs
, no_unit_alloc_regs
);
762 CLEAR_HARD_REG_SET (eliminable_regset
);
763 /* Build the regset of all eliminable registers and show we can't
764 use those that we already know won't be eliminated. */
765 #ifdef ELIMINABLE_REGS
766 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
769 = (! CAN_ELIMINATE (eliminables
[i
].from
, eliminables
[i
].to
)
770 || (eliminables
[i
].to
== STACK_POINTER_REGNUM
&& need_fp
));
772 if (! regs_asm_clobbered
[eliminables
[i
].from
])
774 SET_HARD_REG_BIT (eliminable_regset
, eliminables
[i
].from
);
777 SET_HARD_REG_BIT (no_alloc_regs
, eliminables
[i
].from
);
779 else if (cannot_elim
)
780 error ("%s cannot be used in asm here",
781 reg_names
[eliminables
[i
].from
]);
783 regs_ever_live
[eliminables
[i
].from
] = 1;
785 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
786 if (! regs_asm_clobbered
[HARD_FRAME_POINTER_REGNUM
])
788 SET_HARD_REG_BIT (eliminable_regset
, HARD_FRAME_POINTER_REGNUM
);
790 SET_HARD_REG_BIT (no_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
793 error ("%s cannot be used in asm here",
794 reg_names
[HARD_FRAME_POINTER_REGNUM
]);
796 regs_ever_live
[HARD_FRAME_POINTER_REGNUM
] = 1;
800 if (! regs_asm_clobbered
[FRAME_POINTER_REGNUM
])
802 SET_HARD_REG_BIT (eliminable_regset
, FRAME_POINTER_REGNUM
);
804 SET_HARD_REG_BIT (no_alloc_regs
, FRAME_POINTER_REGNUM
);
807 error ("%s cannot be used in asm here", reg_names
[FRAME_POINTER_REGNUM
]);
809 regs_ever_live
[FRAME_POINTER_REGNUM
] = 1;
815 /* The element value is nonzero if the corresponding regno value is
817 int *reg_equiv_invariant_p
;
819 /* The element value is equiv constant or NULL_RTX. */
820 rtx
*reg_equiv_const
;
822 /* The function sets up the two array declaraed above. */
824 find_reg_equiv_invariant_const (void)
827 rtx list
, insn
, note
, constant
, x
;
829 for (i
= FIRST_PSEUDO_REGISTER
; i
< reg_equiv_init_size
; i
++)
833 for (list
= reg_equiv_init
[i
]; list
!= NULL_RTX
; list
= XEXP (list
, 1))
835 insn
= XEXP (list
, 0);
836 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
838 if (note
== NULL_RTX
)
843 if (! function_invariant_p (x
)
845 /* A function invariant is often CONSTANT_P but may
846 include a register. We promise to only pass CONSTANT_P
847 objects to LEGITIMATE_PIC_OPERAND_P. */
848 || (CONSTANT_P (x
) && LEGITIMATE_PIC_OPERAND_P (x
)))
850 /* It can happen that a REG_EQUIV note contains a MEM that
851 is not a legitimate memory operand. As later stages of
852 reload assume that all addresses found in the
853 reg_equiv_* arrays were originally legitimate, we
854 ignore such REG_EQUIV notes. */
855 if (memory_operand (x
, VOIDmode
))
857 else if (function_invariant_p (x
))
859 if (GET_CODE (x
) == PLUS
860 || x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
867 reg_equiv_invariant_p
[i
] = invariant_p
;
868 reg_equiv_const
[i
] = constant
;
874 /* The function sets up REG_RENUMBER and CALLER_SAVE_NEEDED used by
875 reload from the allocation found by IRA. If AFTER_EMIT_P, the
876 function is called after emitting the move insns, otherwise if
877 AFTER_CALL_P, the function is called right after splitting pseudos
880 setup_reg_renumber (int after_emit_p
, int after_call_p
)
885 caller_save_needed
= 0;
886 for (i
= 0; i
< pseudos_num
; i
++)
889 if (PSEUDO_CAP_MEMBER (p
) != NULL
)
892 if (! PSEUDO_ASSIGNED_P (p
))
893 PSEUDO_ASSIGNED_P (p
) = TRUE
;
894 ira_assert (PSEUDO_ASSIGNED_P (p
));
895 hard_regno
= PSEUDO_HARD_REGNO (p
);
896 reg_renumber
[after_emit_p
897 ? (int) REGNO (PSEUDO_REG (p
)) : PSEUDO_REGNO (p
)]
898 = (hard_regno
< 0 ? -1 : hard_regno
);
899 if (hard_regno
>= 0 && PSEUDO_CALLS_CROSSED_NUM (p
) != 0
900 && ! hard_reg_not_in_set_p (hard_regno
, PSEUDO_MODE (p
),
904 ((! after_call_p
&& flag_caller_saves
)
905 || (flag_caller_saves
&& ! flag_ira_split_around_calls
));
906 caller_save_needed
= 1;
911 /* The function sets up pseudo assignment from reg_renumber. If the
912 cover class of a pseudo does not correspond to the hard register,
913 return TRUE and mark the pseudo as unassigned. */
915 setup_pseudo_assignment_from_reg_renumber (void)
921 for (i
= 0; i
< pseudos_num
; i
++)
924 hard_regno
= PSEUDO_HARD_REGNO (p
) = reg_renumber
[PSEUDO_REGNO (p
)];
925 ira_assert (! PSEUDO_ASSIGNED_P (p
));
927 && hard_reg_not_in_set_p (hard_regno
, PSEUDO_MODE (p
),
929 [PSEUDO_COVER_CLASS (p
)]))
932 PSEUDO_ASSIGNED_P (p
) = TRUE
;
937 /* The function evaluates overall allocation cost and costs for using
938 registers and memory for pseudos. */
941 calculate_allocation_cost (void)
943 int i
, hard_regno
, cost
;
946 overall_cost
= reg_cost
= mem_cost
= 0;
947 for (i
= 0; i
< pseudos_num
; i
++)
950 hard_regno
= PSEUDO_HARD_REGNO (p
);
951 ira_assert (hard_regno
< 0
952 || ! hard_reg_not_in_set_p
953 (hard_regno
, PSEUDO_MODE (p
),
954 reg_class_contents
[PSEUDO_COVER_CLASS (p
)]));
957 cost
= PSEUDO_MEMORY_COST (p
);
962 cost
= (PSEUDO_HARD_REG_COSTS (p
)
963 [class_hard_reg_index
964 [PSEUDO_COVER_CLASS (p
)] [hard_regno
]]);
967 overall_cost
+= cost
;
970 if (ira_dump_file
!= NULL
)
972 fprintf (ira_dump_file
,
973 "+++Costs: overall %d, reg %d, mem %d, ld %d, st %d, move %d\n",
974 overall_cost
, reg_cost
, mem_cost
,
975 load_cost
, store_cost
, shuffle_cost
);
976 fprintf (ira_dump_file
, "+++ move loops %d, new jumps %d\n",
977 move_loops_num
, additional_jumps_num
);
982 #ifdef ENABLE_IRA_CHECKING
983 /* The function checks correctness of the allocation. */
985 check_allocation (void)
987 pseudo_t p
, conflict_p
, *pseudo_vec
;
988 int i
, hard_regno
, conflict_hard_regno
, j
, nregs
, conflict_nregs
;
990 for (i
= 0; i
< pseudos_num
; i
++)
993 if (PSEUDO_CAP_MEMBER (p
) != NULL
994 || (hard_regno
= PSEUDO_HARD_REGNO (p
)) < 0)
996 nregs
= hard_regno_nregs
[hard_regno
] [PSEUDO_MODE (p
)];
997 pseudo_vec
= PSEUDO_CONFLICT_PSEUDO_VEC (p
);
998 for (j
= 0; (conflict_p
= pseudo_vec
[j
]) != NULL
; j
++)
999 if ((conflict_hard_regno
= PSEUDO_HARD_REGNO (conflict_p
)) >= 0)
1003 [conflict_hard_regno
] [PSEUDO_MODE (conflict_p
)]);
1004 if ((conflict_hard_regno
<= hard_regno
1005 && hard_regno
< conflict_hard_regno
+ conflict_nregs
)
1006 || (hard_regno
<= conflict_hard_regno
1007 && conflict_hard_regno
< hard_regno
+ nregs
))
1009 fprintf (stderr
, "bad allocation for %d and %d\n",
1010 PSEUDO_REGNO (p
), PSEUDO_REGNO (conflict_p
));
1018 /* The function fixes values of array REG_EQUIV_INIT after live range
1019 splitting done by IRA. */
1021 fix_reg_equiv_init (void)
1023 int max_regno
= max_reg_num ();
1025 rtx x
, prev
, next
, insn
, set
;
1028 if (reg_equiv_init_size
< max_regno
)
1030 reg_equiv_init
= ggc_realloc (reg_equiv_init
, max_regno
* sizeof (rtx
));
1031 while (reg_equiv_init_size
< max_regno
)
1032 reg_equiv_init
[reg_equiv_init_size
++] = NULL_RTX
;
1033 for (i
= FIRST_PSEUDO_REGISTER
; i
< reg_equiv_init_size
; i
++)
1034 for (prev
= NULL_RTX
, x
= reg_equiv_init
[i
]; x
!= NULL_RTX
; x
= next
)
1038 set
= single_set (insn
);
1039 ira_assert (set
!= NULL_RTX
1040 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))));
1041 if (REG_P (SET_DEST (set
))
1042 && ((int) REGNO (SET_DEST (set
)) == i
1043 || (int) ORIGINAL_REGNO (SET_DEST (set
)) == i
))
1044 new_regno
= REGNO (SET_DEST (set
));
1045 else if (REG_P (SET_SRC (set
))
1046 && ((int) REGNO (SET_SRC (set
)) == i
1047 || (int) ORIGINAL_REGNO (SET_SRC (set
)) == i
))
1048 new_regno
= REGNO (SET_SRC (set
));
1055 if (prev
== NULL_RTX
)
1056 reg_equiv_init
[i
] = next
;
1058 XEXP (prev
, 1) = next
;
1059 XEXP (x
, 1) = reg_equiv_init
[new_regno
];
1060 reg_equiv_init
[new_regno
] = x
;
1066 #ifdef ENABLE_IRA_CHECKING
1067 /* The function prints redundant memory memory copies. */
1069 print_redundant_copies (void)
1073 struct pseudo_copy
*cp
, *next_cp
;
1075 for (i
= 0; i
< pseudos_num
; i
++)
1078 if (PSEUDO_CAP_MEMBER (p
) != NULL
)
1081 hard_regno
= PSEUDO_HARD_REGNO (p
);
1082 if (hard_regno
>= 0)
1084 for (cp
= PSEUDO_COPIES (p
); cp
!= NULL
; cp
= next_cp
)
1086 next_cp
= cp
->next_first_pseudo_copy
;
1089 next_cp
= cp
->next_second_pseudo_copy
;
1090 if (ira_dump_file
!= NULL
&& cp
->move_insn
!= NULL_RTX
1091 && PSEUDO_HARD_REGNO (cp
->first
) == hard_regno
)
1092 fprintf (ira_dump_file
, "move %d(freq %d):%d\n",
1093 INSN_UID (cp
->move_insn
), cp
->freq
, hard_regno
);
1099 /* Setup preferred and alternative classes for pseudo-registers for
1102 setup_preferred_alternate_classes (void)
1105 enum reg_class cover_class
;
1108 for (i
= 0; i
< pseudos_num
; i
++)
1111 cover_class
= PSEUDO_COVER_CLASS (p
);
1112 if (cover_class
== NO_REGS
)
1113 cover_class
= GENERAL_REGS
;
1114 setup_reg_classes (PSEUDO_REGNO (p
), cover_class
, NO_REGS
);
1120 /* The value of max_regn_num () correspondingly before the allocator
1121 and before splitting pseudos around calls. */
1122 int ira_max_regno_before
;
1123 int ira_max_regno_call_before
;
1125 /* Flags for each regno (existing before the splitting pseudos around
1126 calls) about that the corresponding register crossed a call. */
1127 char *original_regno_call_crossed_p
;
1129 /* This is the main entry of IRA. */
1133 int i
, overall_cost_before
, loops_p
;
1141 rebuild_p
= update_equiv_regs ();
1143 #ifndef IRA_NO_OBSTACK
1144 gcc_obstack_init (&ira_obstack
);
1146 bitmap_obstack_initialize (&ira_bitmap_obstack
);
1148 ira_max_regno_call_before
= ira_max_regno_before
= max_reg_num ();
1149 reg_equiv_invariant_p
= ira_allocate (max_reg_num () * sizeof (int));
1150 memset (reg_equiv_invariant_p
, 0, max_reg_num () * sizeof (int));
1151 reg_equiv_const
= ira_allocate (max_reg_num () * sizeof (rtx
));
1152 memset (reg_equiv_const
, 0, max_reg_num () * sizeof (rtx
));
1153 find_reg_equiv_invariant_const ();
1156 rebuild_jump_labels (get_insns ());
1157 purge_all_dead_edges ();
1158 delete_unreachable_blocks ();
1160 setup_eliminable_regset ();
1162 overall_cost
= reg_cost
= mem_cost
= 0;
1163 load_cost
= store_cost
= shuffle_cost
= 0;
1164 move_loops_num
= additional_jumps_num
= 0;
1165 loops_p
= ira_build (flag_ira_algorithm
== IRA_ALGORITHM_REGIONAL
1166 || flag_ira_algorithm
== IRA_ALGORITHM_MIXED
);
1171 max_regno
= max_reg_num ();
1173 /* Allocate the reg_renumber array. */
1174 allocate_reg_info (max_regno
, FALSE
, TRUE
);
1176 setup_reg_renumber (TRUE
, FALSE
);
1181 /* Even if new registers are not created rebuild IRA internal
1182 representation to use correct regno pseudo map. */
1185 if (setup_pseudo_assignment_from_reg_renumber ())
1187 reassign_conflict_pseudos (max_regno
, FALSE
);
1188 setup_reg_renumber (FALSE
, FALSE
);
1192 original_regno_call_crossed_p
= ira_allocate (max_regno
* sizeof (char));
1194 for (i
= 0; i
< pseudos_num
; i
++)
1197 ira_assert (PSEUDO_CAP_MEMBER (p
) == NULL
);
1198 original_regno_call_crossed_p
[PSEUDO_REGNO (p
)]
1199 = PSEUDO_CALLS_CROSSED_NUM (p
) != 0;
1201 ira_max_regno_call_before
= max_reg_num ();
1202 if (flag_caller_saves
&& flag_ira_split_around_calls
)
1205 if (split_around_calls ())
1208 max_regno
= max_reg_num ();
1209 /* Allocate the reg_renumber array. */
1210 allocate_reg_info (max_regno
, FALSE
, TRUE
);
1212 setup_pseudo_assignment_from_reg_renumber ();
1213 reassign_conflict_pseudos ((flag_ira_assign_after_call_split
1214 ? ira_max_regno_call_before
1215 : max_reg_num ()), TRUE
);
1216 setup_reg_renumber (FALSE
, TRUE
);
1221 calculate_allocation_cost ();
1223 #ifdef ENABLE_IRA_CHECKING
1224 check_allocation ();
1227 max_regno
= max_reg_num ();
1228 delete_trivially_dead_insns (get_insns (), max_regno
);
1229 /* The allocator makes live register information inaccurate. */
1230 life_analysis (PROP_DEATH_NOTES
| PROP_LOG_LINKS
| PROP_REG_INFO
);
1231 max_regno
= max_reg_num ();
1233 /* Determine if the current function is a leaf before running IRA
1234 since this can impact optimizations done by the prologue and
1235 epilogue thus changing register elimination offsets. */
1236 current_function_is_leaf
= leaf_function_p ();
1238 /* Allocate the reg_renumber array. */
1239 allocate_reg_info (max_regno
, FALSE
, TRUE
);
1241 /* And the reg_equiv_memory_loc array. */
1242 VEC_safe_grow (rtx
, gc
, reg_equiv_memory_loc_vec
, max_regno
);
1243 memset (VEC_address (rtx
, reg_equiv_memory_loc_vec
), 0,
1244 sizeof (rtx
) * max_regno
);
1245 reg_equiv_memory_loc
= VEC_address (rtx
, reg_equiv_memory_loc_vec
);
1247 allocate_initial_values (reg_equiv_memory_loc
);
1249 fix_reg_equiv_init ();
1251 setup_preferred_alternate_classes ();
1253 #ifdef ENABLE_IRA_CHECKING
1254 print_redundant_copies ();
1257 overall_cost_before
= overall_cost
;
1259 spilled_reg_stack_slots_num
= 0;
1260 spilled_reg_stack_slots
1261 = ira_allocate (max_regno
* sizeof (struct spilled_reg_stack_slot
));
1263 build_insn_chain (get_insns ());
1264 reload_completed
= ! reload (get_insns (), 1);
1266 ira_free (spilled_reg_stack_slots
);
1268 if (ira_dump_file
!= NULL
&& overall_cost_before
!= overall_cost
)
1269 fprintf (ira_dump_file
, "+++Overall after reload %d\n", overall_cost
);
1273 cleanup_cfg (CLEANUP_EXPENSIVE
);
1275 ira_free (original_regno_call_crossed_p
);
1276 ira_free (reg_equiv_invariant_p
);
1277 ira_free (reg_equiv_const
);
1279 bitmap_obstack_release (&ira_bitmap_obstack
);
1280 #ifndef IRA_NO_OBSTACK
1281 obstack_free (&ira_obstack
, NULL
);
1284 reload_completed
= 1;
1292 return flag_ira
!= 0;
1295 /* Run the integrated register allocator. */
1297 rest_of_handle_ira (void)
1303 struct tree_opt_pass pass_ira
=
1306 gate_ira
, /* gate */
1307 rest_of_handle_ira
, /* execute */
1310 0, /* static_pass_number */
1312 0, /* properties_required */
1313 0, /* properties_provided */
1314 0, /* properties_destroyed */
1315 0, /* todo_flags_start */
1317 TODO_ggc_collect
, /* todo_flags_finish */