| blob | 4393283f75005db27576ec30e06f4ab19bd6dff0 |
1 2024-04-03 Mark Wielaard <mark@klomp.org>
3 * config/i386/i386.opt.urls: Regenerate.
5 2024-04-03 H.J. Lu <hjl.tools@gmail.com>
7 PR tree-optimization/114115
8 * cgraph.h (symtab_node): Add check_ifunc_callee_symtab_nodes.
9 (cgraph_node): Add called_by_ifunc_resolver.
10 * cgraphunit.cc (symbol_table::compile): Call
11 symtab_node::check_ifunc_callee_symtab_nodes.
12 * symtab.cc (check_ifunc_resolver): New.
13 (ifunc_ref_map): Likewise.
14 (is_caller_ifunc_resolver): Likewise.
15 (symtab_node::check_ifunc_callee_symtab_nodes): Likewise.
16 * tree-profile.cc (gimple_gen_ic_func_profiler): Disable indirect
17 call profiling for IFUNC resolvers and their callees.
19 2024-04-03 Tobias Burnus <tburnus@baylibre.com>
21 * lto-wrapper.cc (compile_offload_image): Prefix 'offload_args'
22 suffix by the target name.
24 2024-04-03 Tobias Burnus <tburnus@baylibre.com>
26 * doc/install.texi (amdgcn-*-amdhsa): Update Newlib recommendation
27 and update wording for LLVM 18 release.
29 2024-04-03 Tobias Burnus <tburnus@baylibre.com>
31 PR other/111966
32 * config/gcn/mkoffload.cc (get_arch): New; moved -march= flag
33 handling from ...
34 (main): ... here; call it to handle --with-arch config option
35 and -march= commandline.
37 2024-04-03 Jakub Jelinek <jakub@redhat.com>
39 PR middle-end/114552
40 * expr.cc (emit_push_insn): Only use store_constructor for
41 immediate_const_ctor_p if int_expr_size matches size.
43 2024-04-03 Richard Biener <rguenther@suse.de>
45 PR tree-optimization/114557
46 PR tree-optimization/114480
47 * tree-phinodes.cc (release_phi_node): Return PHIs from
48 allocation buckets not covered by free_phinodes to GC.
49 (remove_phi_node): Release the PHI LHS before freeing the
50 PHI node.
51 * tree-vect-loop.cc (vectorizable_live_operation): Get PHI lhs
52 before releasing it.
54 2024-04-03 Jiahao Xu <xujiahao@loongson.cn>
56 * config/loongarch/lasx.md: Remove unused code.
57 * config/loongarch/loongarch-protos.h
58 (loongarch_split_lsx_copy_d): Remove.
59 (loongarch_split_lsx_insert_d): Ditto.
60 (loongarch_split_lsx_fill_d): Ditto.
61 * config/loongarch/loongarch.cc
62 (loongarch_split_lsx_copy_d): Ditto.
63 (loongarch_split_lsx_insert_d): Ditto.
64 (loongarch_split_lsx_fill_d): Ditto.
65 * config/loongarch/lsx.md (lsx_vpickve2gr_du): Remove splitter.
66 (lsx_vpickve2gr_<lsxfmt_f>): Ditto.
67 (abs<mode>2): Remove expander.
68 (vabs<mode>2): Rename 2 abs<mode>2.
70 2024-04-02 Christophe Lyon <christophe.lyon@linaro.org>
72 * config/aarch64/aarch64-option-extensions.def: Fix comment.
74 2024-04-02 Tom Tromey <tromey@adacore.com>
76 * dwarf2out.cc (print_dw_val) <dw_val_class_loc>: Don't
77 print newline when not recursing.
79 2024-04-02 Iain Sandoe <iain@sandoe.co.uk>
81 * config/darwin.cc (darwin_override_options): Update the
82 clang major version value in the dsymutil check.
84 2024-04-02 Iain Sandoe <iain@sandoe.co.uk>
86 * config/darwin.cc (darwin_override_options): Reduce the debug
87 level to 2 if dsymutil cannot handle .macinfo sections.
89 2024-04-02 Yang Yujie <yangyujie@loongson.cn>
91 * config/loongarch/t-loongarch: Add loongarch-def-arrays.h
92 to OPTION_H_EXTRA.
94 2024-04-02 mengqinggang <mengqinggang@loongson.cn>
95 Lulu Cheng <chenglulu@loongson.cn>
96 Xi Ruoyao <xry111@xry111.site>
98 * config.gcc: Add --with-tls option to change TLS flavor.
99 * config/loongarch/genopts/loongarch.opt.in: Add -mtls-dialect to
100 configure TLS flavor.
101 * config/loongarch/loongarch-def.h (struct loongarch_target): Add
102 tls_dialect.
103 * config/loongarch/loongarch-driver.cc (la_driver_init): Add tls
104 flavor.
105 * config/loongarch/loongarch-opts.cc (loongarch_init_target): Add
106 tls_dialect.
107 (loongarch_config_target): Ditto.
108 (loongarch_update_gcc_opt_status): Ditto.
109 * config/loongarch/loongarch-opts.h (loongarch_init_target): Ditto.
110 (TARGET_TLS_DESC): New define.
111 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Add TLS
112 DESC instructions sequence length.
113 (loongarch_legitimize_tls_address): New TLS DESC instruction sequence.
114 (loongarch_option_override_internal): Add la_opt_tls_dialect.
115 (loongarch_option_restore): Add la_target.tls_dialect.
116 * config/loongarch/loongarch.md (@got_load_tls_desc<mode>): Normal
117 code model for TLS DESC.
118 (got_load_tls_desc_off64): Extreme cmode model for TLS DESC.
119 * config/loongarch/loongarch.opt: Regenerate.
120 * config/loongarch/loongarch.opt.urls: Ditto.
121 * doc/invoke.texi: Add a description of the compilation option
122 '-mtls-dialect={trad,desc}'.
124 2024-04-02 Lulu Cheng <chenglulu@loongson.cn>
126 * config/loongarch/loongarch.opt.urls: Regenerate.
128 2024-04-01 Yang Yujie <yangyujie@loongson.cn>
130 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]recip as
131 aliases to -mrecip={all,none}, respectively.
132 * config/loongarch/loongarch.opt: Regenerate.
133 * config/loongarch/loongarch-def.h (ABI_FPU_64): Rename to...
134 (ABI_FPU64_P): ...this.
135 (ABI_FPU_32): Rename to...
136 (ABI_FPU32_P): ...this.
137 (ABI_FPU_NONE): Rename to...
138 (ABI_NOFPU_P): ...this.
139 (ABI_LP64_P): Define.
140 * config/loongarch/loongarch.cc (loongarch_init_print_operand_punct):
141 Merged into loongarch_global_init.
142 (loongarch_cpu_option_override): Renamed to
143 loongarch_target_option_override.
144 (loongarch_option_override_internal): Move the work after
145 loongarch_config_target into loongarch_target_option_override.
146 (loongarch_global_init): Define.
147 (INIT_TARGET_FLAG): Move to loongarch-opts.cc.
148 (loongarch_option_override): Call loongarch_global_init
149 separately.
150 * config/loongarch/loongarch-opts.cc (loongarch_parse_mrecip_scheme):
151 Split the parsing of -mrecip=<string> from
152 loongarch_option_override_internal.
153 (loongarch_generate_mrecip_scheme): Define. Split from
154 loongarch_option_override_internal.
155 (loongarch_target_option_override): Define. Renamed from
156 loongarch_cpu_option_override.
157 (loongarch_init_misc_options): Define. Split from
158 loongarch_option_override_internal.
159 (INIT_TARGET_FLAG): Move from loongarch.cc.
160 * config/loongarch/loongarch-opts.h (loongarch_target_option_override):
161 New prototype.
162 (loongarch_parse_mrecip_scheme): New prototype.
163 (loongarch_init_misc_options): New prototype.
164 (TARGET_ABI_LP64): Simplify with ABI_LP64_P.
165 * config/loongarch/loongarch.h (TARGET_RECIP_DIV): Simplify.
166 Do not reference specific CPU architecture (LA664).
167 (TARGET_RECIP_SQRT): Same.
168 (TARGET_RECIP_RSQRT): Same.
169 (TARGET_RECIP_VEC_DIV): Same.
170 (TARGET_RECIP_VEC_SQRT): Same.
171 (TARGET_RECIP_VEC_RSQRT): Same.
173 2024-04-01 Lulu Cheng <chenglulu@loongson.cn>
175 * doc/invoke.texi: Add descriptions for the compilation
176 options.
178 2024-03-31 Jeff Law <jlaw@ventanamicro.com>
180 * config/riscv/xiangshan.md (xiangshan_jump): Add branch, jalr, ret
181 and sfb_alu.
183 2024-03-31 Pan Li <pan2.li@intel.com>
185 * config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
186 the term built-in over builtin.
188 2024-03-31 Pan Li <pan2.li@intel.com>
190 * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
191 Remove unused var decl.
193 2024-03-30 Xi Ruoyao <xry111@xry111.site>
195 PR target/114175
196 * config/mips/mips.cc (mips_setup_incoming_varargs): Only skip
197 mips_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
198 functions if arg.type is NULL.
200 2024-03-29 Andrew Pinski <quic_apinski@quicinc.com>
202 * lto-compress.cc (lto_end_uncompression): Use
203 fatal_error instead of internal_error when ZSTD
204 is not enabled.
206 2024-03-28 Jeff Law <jlaw@ventanamicro.com>
208 * config/h8300/extensions.md (zero_extendqihi*): Add output
209 template for reg->reg case where the regs don't match.
211 2024-03-28 Gaius Mulley <(no_default)>
213 PR modula2/114517
214 * doc/gm2.texi: Mention gm2 treats a # in the first column
215 as a preprocessor directive unless -fno-cpp is supplied.
217 2024-03-28 Jakub Jelinek <jakub@redhat.com>
219 * predict.cc (estimate_bb_frequencies): Fix comment typo,
220 scalling -> scaling.
222 2024-03-28 Jakub Jelinek <jakub@redhat.com>
224 PR tree-optimization/112303
225 * profile-count.h (profile_count::operator+): Perform
226 addition in uint64_t variable and set m_val to MIN of that
227 val and max_count.
228 (profile_count::operator+=): Likewise.
229 (profile_count::operator-=): Formatting fix.
230 (profile_count::apply_probability): Use safe_scale_64bit
231 even in the int overload.
233 2024-03-28 Jan Hubicka <jh@suse.cz>
235 PR middle-end/113907
236 * ipa-icf.cc (sem_function::init): Hash PHI operands
237 (sem_function::compare_phi_node): Add argument about preserving order
239 2024-03-28 Richard Biener <rguenther@suse.de>
241 PR middle-end/114480
242 * cfganal.cc (compute_idf): Use simpler bitmap iteration,
243 touch work_set only when phi_insertion_points changed.
245 2024-03-28 Palmer Dabbelt <palmer@rivosinc.com>
247 * config/riscv/riscv.h (REGISTER_NAMES): Add vxsat.
249 2024-03-27 Segher Boessenkool <segher@kernel.crashing.org>
251 PR rtl-optimization/101523
252 * combine.cc (try_combine): Don't do a 2-insn combination if
253 it does not in fact change I2.
255 2024-03-27 Jakub Jelinek <jakub@redhat.com>
257 * doc/invoke.texi (Spec Files): Use @var{S} instead of S,
258 @var{X} instead of X etc. for other placeholders.
260 2024-03-27 Richard Biener <rguenther@suse.de>
262 PR tree-optimization/114057
263 * tree-vect-slp.cc (vect_bb_slp_mark_live_stmts): Mark
264 BB reduction remain defs as scalar uses.
266 2024-03-27 Victor Do Nascimento <victor.donascimento@arm.com>
268 * config/aarch64/aarch64-option-extensions.def (rcpc3):
269 Fix FEATURE_STRING field to "lrcpc3".
271 2024-03-27 Victor Do Nascimento <victor.donascimento@arm.com>
273 * config/aarch64/aarch64-option-extensions.def: Add LSE128
274 AARCH64_OPT_EXTENSION, adding it as a dependency for the D128
275 feature.
276 * doc/invoke.texi (AArch64 Options): Document +lse128.
278 2024-03-26 Richard Sandiford <richard.sandiford@arm.com>
280 * config/aarch64/aarch64-feature-deps.h: Use constexpr for
281 out-of-line statics.
283 2024-03-26 Cupertino Miranda <cupertino.miranda@oracle.com>
285 PR target/114431
286 * btfout.cc (get_name_for_datasec_entry): Add function.
287 (btf_asm_datasec_entry): Print label when possible.
289 2024-03-26 Richard Ball <richard.ball@arm.com>
291 PR target/114272
292 * config/aarch64/aarch64-cores.def (AARCH64_CORE):
293 Change SCHEDULER_IDENT from cortexa55 to cortexa53
294 for Cortex-A510 and Cortex-A520.
296 2024-03-26 Jakub Jelinek <jakub@redhat.com>
298 PR middle-end/111151
299 * fold-const.cc (extract_muldiv_1) <case MAX_EXPR>: Punt for
300 MULT_EXPR altogether, or for MAX_EXPR if c is -1.
302 2024-03-26 Jakub Jelinek <jakub@redhat.com>
304 PR sanitizer/111736
305 * tsan.cc (instrument_expr): Punt on non-generic address space
306 accesses.
308 2024-03-26 Richard Biener <rguenther@suse.de>
310 PR tree-optimization/114471
311 * tree-vect-stmts.cc (vectorizable_operation): Verify operand
312 types are compatible with the result type.
314 2024-03-26 Richard Biener <rguenther@suse.de>
316 PR tree-optimization/114464
317 * tree-vect-loop.cc (vectorizable_recurr): Verify the latch
318 vector type is compatible with what we chose for the recurrence.
320 2024-03-26 Jakub Jelinek <jakub@redhat.com>
322 * cfgloopmanip.cc (update_loop_exit_probability_scale_dom_bbs):
323 Fix comment typo - multple -> multiple.
324 * config/i386/x86-tune.def (X86_TUNE_ACCUMULATE_OUTGOING_ARGS):
325 Likewise.
327 2024-03-26 YunQiang Su <syq@gcc.gnu.org>
329 * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Predefine
330 __mips_strict_alignment if STRICT_ALIGNMENT.
332 2024-03-25 Richard Biener <rguenther@suse.de>
334 * config.gcc (amdgcn): Add gfx1036 entries.
335 * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
336 (gcn_local_sym_hash): Likewise.
337 * config/gcn/gcn-opts.h (enum processor_type): Likewise.
338 (TARGET_GFX1036): New macro.
339 * config/gcn/gcn.cc (gcn_option_override): Handle gfx1036.
340 (gcn_omp_device_kind_arch_isa): Likewise.
341 (output_file_start): Likewise.
342 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1036__.
343 (TARGET_CPU_CPP_BUILTINS): Rename __gfx1030 to __gfx1030__.
344 * config/gcn/gcn.opt: Add gfx1036.
345 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1036): New.
346 (main): Handle gfx1036.
347 * config/gcn/t-omp-device: Add gfx1036 isa.
348 * doc/install.texi (amdgcn): Add gfx1036.
349 * doc/invoke.texi (-march): Likewise.
351 2024-03-25 Pan Li <pan2.li@intel.com>
353 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
354 when V is disabled and init the RVV types and intrinic APIs.
355 * config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
356 error if V ext is disabled.
357 * config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
358 Ditto.
359 (riscv_arguments_is_vector_type_p): Ditto.
360 (riscv_vector_cc_function_p): Ditto.
361 * config/riscv/riscv_vector.h: Remove error if V is disable.
363 2024-03-23 John David Anglin <danglin@gcc.gnu.org>
365 * config/pa/pa.cc (pa_output_global_address): Handle
366 UNSPEC_DLTIND14R addresses.
367 * config/pa/pa.h (PRINT_OPERAND_ADDRESS): Output "RT'" for
368 UNSPEC_DLTIND14R address.
370 2024-03-23 Jakub Jelinek <jakub@redhat.com>
372 PR tree-optimization/114433
373 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): For
374 m_bitfld_load check save_first rather than m_first.
376 2024-03-23 Jakub Jelinek <jakub@redhat.com>
378 PR tree-optimization/114425
379 * gimple-lower-bitint.cc (build_bitint_stmt_ssa_conflicts): Handle
380 _Complex large/huge _BitInt types like the large/huge _BitInt types.
382 2024-03-23 Jakub Jelinek <jakub@redhat.com>
384 PR middle-end/111683
385 * tree-predcom.cc (pcom_worker::suitable_component_p): If has_write
386 and comp_step is RS_NONZERO, return false if any reference in the
387 component doesn't have DR_STEP a multiple of access size.
389 2024-03-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
391 * config/xtensa/xtensa.md: Add new split pattern described above.
393 2024-03-22 Georg-Johann Lay <avr@gjlay.de>
395 * config/avr/avr.cc (avr_set_current_function): Adjust diagnostic
396 for deprecated SIGNAL and INTERRUPT usage without respective header.
398 2024-03-22 Andrew Stubbs <ams@baylibre.com>
400 * config/gcn/gcn.md (*memory_barrier): Split into RDNA and !RDNA.
401 (atomic_load<mode>): Adjust RDNA cache settings.
402 (atomic_store<mode>): Likewise.
403 (atomic_exchange<mode>): Likewise.
405 2024-03-22 Andrew Stubbs <ams@baylibre.com>
407 * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on
408 RDNA devices.
410 2024-03-22 Andrew Stubbs <ams@baylibre.com>
412 * config.gcc (amdgcn): Add gfx1103 entries.
413 * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
414 (gcn_local_sym_hash): Likewise.
415 * config/gcn/gcn-opts.h (enum processor_type): Likewise.
416 (TARGET_GFX1103): New macro.
417 * config/gcn/gcn.cc (gcn_option_override): Handle gfx1103.
418 (gcn_omp_device_kind_arch_isa): Likewise.
419 (output_file_start): Likewise.
420 (gcn_hsa_declare_function_name): Use TARGET_RDNA3, not just gfx1100.
421 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1103__.
422 * config/gcn/gcn.opt: Add gfx1103.
423 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1103): New.
424 (main): Handle gfx1103.
425 * config/gcn/t-omp-device: Add gfx1103 isa.
426 * doc/install.texi (amdgcn): Add gfx1103.
427 * doc/invoke.texi (-march): Likewise.
429 2024-03-22 Andrew Stubbs <ams@baylibre.com>
431 * dojump.cc (do_compare_rtx_and_jump): Clear excess bits in vector
432 bitmasks.
433 (do_compare_and_jump): Remove now-redundant similar code.
434 * internal-fn.cc (expand_fn_using_insn): Clear excess bits in vector
435 bitmasks.
436 (add_mask_and_len_args): Likewise.
438 2024-03-22 Pan Li <pan2.li@intel.com>
440 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
441 macro __riscv_v_fixed_vlen when zvl.
442 * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
443 New static func to take care of the RVV types decorated by
444 the attributes.
446 2024-03-22 Andrew Pinski <quic_apinski@quicinc.com>
448 PR c/109619
449 * builtins.cc (fold_builtin_1): Use error_operand_p
450 instead of checking against ERROR_MARK.
451 (fold_builtin_2): Likewise.
452 (fold_builtin_3): Likewise.
454 2024-03-22 Jakub Jelinek <jakub@redhat.com>
456 PR sanitizer/111736
457 * ubsan.cc (ubsan_expand_null_ifn, instrument_mem_ref): Avoid
458 SANITIZE_NULL instrumentation for non-generic address spaces
459 for which targetm.addr_space.zero_address_valid (as) is true.
461 2024-03-22 Jakub Jelinek <jakub@redhat.com>
463 PR tree-optimization/114405
464 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
465 Set rprec to limb_prec rather than 0 if tprec is divisible by
466 limb_prec. In the last bf_cur handling, set rprec to (tprec + bo_bit)
467 % limb_prec rather than tprec % limb_prec and use just rprec instead
468 of rprec + bo_bit. For build_bit_field_ref offset, divide
469 (tprec + bo_bit) by limb_prec rather than just tprec.
471 2024-03-22 Christoph Müllner <christoph.muellner@vrull.eu>
473 PR target/114194
474 * config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC.
475 Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR.
477 2024-03-22 Jeff Law <jlaw@ventanamicro.com>
479 * config/riscv/riscv.cc (riscv_expand_prologue): Add missing stack
480 tie for scalable and final stack adjustment if needed.
481 Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
483 2024-03-22 Pan Li <pan2.li@intel.com>
485 PR target/114352
486 * common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
487 New struct for func decl and target name.
488 (struct riscv_func_target_hasher): New hasher for hash table mapping
489 from the fn_decl to fn_target_name.
490 (riscv_func_decl_hash): New func to compute the hash for fn_decl.
491 (riscv_func_target_hasher::hash): New func to impl hash interface.
492 (riscv_func_target_hasher::equal): New func to impl equal interface.
493 (riscv_cmdline_subset_list): New static var for cmdline subset list.
494 (riscv_func_target_table_lazy_init): New func to lazy init the func
495 target hash table.
496 (riscv_func_target_get): New func to get target name from hash table.
497 (riscv_func_target_put): New func to put target name into hash table.
498 (riscv_func_target_remove_and_destory): New func to remove target
499 info from the hash table and destory it.
500 (riscv_parse_arch_string): Set the static var cmdline_subset_list.
501 * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static
502 var for cmdline subset list.
503 (riscv_func_target_get): New func decl.
504 (riscv_func_target_put): Ditto.
505 (riscv_func_target_remove_and_destory): Ditto.
506 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
507 Take cmdline_subset_list instead of current_subset_list when clone.
508 (riscv_process_target_attr): Record the func target info to hash table.
509 (riscv_option_valid_attribute_p): Add new arg tree fndel.
510 * config/riscv/riscv.cc (riscv_declare_function_name): Consume the
511 func target info and print the arch message.
513 2024-03-22 Pan Li <pan2.li@intel.com>
515 PR target/114352
516 * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
517 Replace implied, combine and check to func finalize.
518 (riscv_subset_list::finalize): New func impl to take care of
519 implied, combine ext and related checks.
520 * config/riscv/riscv-subset.h: Add func decl for finalize.
521 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
522 Finalize the ext before return succeed.
523 * config/riscv/riscv.cc (riscv_set_current_function): Reinit the
524 machine mode before when set cur function.
526 2024-03-21 Andrew Stubbs <ams@baylibre.com>
528 * config/gcn/gcn.cc (gcn_expand_builtin_1): Comment correction.
530 2024-03-21 Andrew Stubbs <ams@baylibre.com>
532 * config/gcn/gcn-hsa.h (ASM_SPEC): Pass -mattr=+cumode.
534 2024-03-21 Andrew Stubbs <ams@baylibre.com>
536 * config/gcn/gcn-run.cc (main): Add an hsa_memory_free calls for each
537 device_malloc call.
539 2024-03-21 liuhongt <hongtao.liu@intel.com>
541 PR tree-optimization/114396
542 * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Pass utype
543 and true to wi::from_mpz.
545 2024-03-21 Richard Biener <rguenther@suse.de>
547 PR tree-optimization/111736
548 * asan.cc (instrument_derefs): Do not instrument accesses
549 to non-generic address-spaces.
551 2024-03-21 Richard Biener <rguenther@suse.de>
553 PR tree-optimization/113727
554 * tree-sra.cc (analyze_access_subtree): Do not allow
555 replacements in subtrees when grp_partial_lhs.
557 2024-03-21 liuhongt <hongtao.liu@intel.com>
559 PR middle-end/114347
560 * doc/invoke.texi: Document -fexcess-precision=16.
562 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
564 * config/bpf/core-builtins.cc (bpf_core_get_index): Check if
565 field contains a DECL_NAME.
567 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
569 * config/bpf/btfext-out.cc (cpf_core_reloc_add): Correct for new code.
570 Add assert to validate the string is set.
571 * config/bpf/core-builtins.cc (cr_final): Make string struct
572 field as const.
573 (process_enum_value): Correct for field type change.
574 (process_type): Set access string to "0".
576 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
578 * config/bpf/core-builtins.cc (core_field_info): Add
579 support for POINTER_PLUS_EXPR in the root of the field expression.
580 (bpf_core_get_index): Likewise.
581 (pack_field_expr): Make the BTF type to point to the structure
582 related node, instead of its pointer type.
583 (make_core_safe_access_index): Correct to new code.
585 2024-03-20 Xi Ruoyao <xry111@xry111.site>
587 PR target/114407
588 * config/loongarch/loongarch-opts.cc (loongarch_config_target):
589 Fix typo in diagnostic message, enabing -> enabling.
591 2024-03-20 Jakub Jelinek <jakub@redhat.com>
593 PR target/114175
594 * config/visium/visium.cc (visium_setup_incoming_varargs): Only skip
595 TARGET_FUNCTION_ARG_ADVANCE for TYPE_NO_NAMED_ARGS_STDARG_P functions
596 if arg.type is NULL.
598 2024-03-20 Jakub Jelinek <jakub@redhat.com>
600 PR target/114175
601 * config/nios2/nios2.cc (nios2_setup_incoming_varargs): Only skip
602 nios2_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
603 if arg.type is NULL.
605 2024-03-20 Jakub Jelinek <jakub@redhat.com>
607 PR target/114175
608 * config/nds32/nds32.cc (nds32_setup_incoming_varargs): Only skip
609 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
610 if arg.type is NULL.
612 2024-03-20 Jakub Jelinek <jakub@redhat.com>
614 PR target/114175
615 * config/m32r/m32r.cc (m32r_setup_incoming_varargs): Only skip
616 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
617 if arg.type is NULL.
619 2024-03-20 Jakub Jelinek <jakub@redhat.com>
621 PR target/114175
622 * config/ft32/ft32.cc (ft32_setup_incoming_varargs): Only skip
623 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
624 if arg.type is NULL.
626 2024-03-20 Jakub Jelinek <jakub@redhat.com>
628 PR target/114175
629 * config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): Only
630 skip function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
631 if arg.type is NULL.
633 2024-03-20 Jakub Jelinek <jakub@redhat.com>
635 PR target/114175
636 * config/csky/csky.cc (csky_setup_incoming_varargs): Only skip
637 csky_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
638 if arg.type is NULL.
640 2024-03-20 Yury Khrustalev <yury.khrustalev@arm.com>
642 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
644 2024-03-20 Jakub Jelinek <jakub@redhat.com>
646 PR tree-optimization/114365
647 * gimple-lower-bitint.cc (bitint_large_huge::handle_load): When adding
648 a PHI node, set iv2 to its result afterwards.
650 2024-03-20 Jakub Jelinek <jakub@redhat.com>
652 * tree-ssa-loop-ch.cc (update_profile_after_ch): Fix comment typo:
653 probabbility -> probability.
654 (ch_base::copy_headers): Fix comment typo: itrations -> iterations.
656 2024-03-20 Jakub Jelinek <jakub@redhat.com>
658 PR bootstrap/114369
659 * system.h (vec_step): Define to vec_step_ when compiling
660 with clang on PowerPC.
662 2024-03-20 demin.han <demin.han@starfivetech.com>
664 PR target/112651
665 * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
666 (enum rvv_max_lmul_enum): Ditto
667 (TARGET_MAX_LMUL): Ditto
668 * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
669 * config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
670 (costs::better_main_loop_than_p): Ditto
671 * config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul
673 2024-03-20 Richard Biener <rguenther@suse.de>
675 PR middle-end/113396
676 * tree-dfa.cc (get_ref_base_and_extent): Use index range
677 bounds only if they fit within the address-range constraints
678 of offset_int.
680 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
682 * config/loongarch/loongarch.cc
683 (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and
684 UNITS_PER_FPREG macros.
685 (loongarch_hard_regno_nregs): Ditto.
686 (loongarch_class_max_nregs): Ditto.
687 (loongarch_get_separate_components): Ditto.
688 (loongarch_process_components): Ditto.
689 * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
690 (UNITS_PER_HWFPVALUE): Ditto.
691 (UNITS_PER_FPVALUE): Ditto.
693 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
695 * config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking
696 of loongarch_expand_vec_cmp()'s return value.
697 (vec_cmpu<ILASX:mode><mode256_i>): Ditto.
698 * config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto.
699 (vec_cmpu<ILSX:mode><mode_i>): Ditto.
700 * config/loongarch/loongarch-protos.h
701 (loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return
702 type from bool to void.
703 * config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
705 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
707 * config/loongarch/loongarch-protos.h
708 (loongarch_cfun_has_cprestore_slot_p): Delete.
709 (loongarch_adjust_insn_length): Delete.
710 (current_section_name): Delete.
711 (loongarch_split_symbol_type): Delete.
712 * config/loongarch/loongarch.cc
713 (loongarch_case_values_threshold): Delete.
714 (loongarch_spill_class): Delete.
715 (TARGET_OPTAB_SUPPORTED_P): Delete.
716 (TARGET_CASE_VALUES_THRESHOLD): Delete.
717 (TARGET_SPILL_CLASS): Delete.
719 2024-03-20 Lewis Hyatt <lhyatt@gmail.com>
721 PR c++/111918
722 * diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
723 * diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
724 Make use of DK_ANY to indicate a diagnostic was initially enabled.
725 (diagnostic_context::diagnostic_enabled): Do not change the type of
726 a diagnostic if the saved classification is type DK_ANY.
728 2024-03-19 Martin Jambor <mjambor@suse.cz>
730 PR ipa/108802
731 PR ipa/114254
732 * ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
733 at COMPONENT_REFs directly from a PARM_DECL, also recognize loads from
734 a pointer parameter.
735 (ipa_analyze_indirect_call_uses): Also recognize loads from a pointer
736 parameter, also recognize the case when pfn pointer is loaded in its
737 own BB.
739 2024-03-19 Vladimir N. Makarov <vmakarov@redhat.com>
741 PR target/99829
742 * lra-constraints.cc (lra_constraints): Prevent removing insn
743 with reverse equivalence to memory if the memory was reloaded.
745 2024-03-19 David Malcolm <dmalcolm@redhat.com>
747 PR middle-end/114348
748 * diagnostic-format-json.cc
749 (json_stderr_output_format::machine_readable_stderr_p): New.
750 (json_file_output_format::machine_readable_stderr_p): New.
751 * diagnostic-format-sarif.cc
752 (sarif_stream_output_format::machine_readable_stderr_p): New.
753 (sarif_file_output_format::machine_readable_stderr_p): New.
754 * diagnostic.cc (diagnostic_context::action_after_output): Move
755 "fnotice" to before "finish" call, so that we still have the
756 diagnostic_context.
757 (fnotice): Bail out if the user requested one of the
758 machine-readable diagnostic output formats on stderr.
759 * diagnostic.h
760 (diagnostic_output_format::machine_readable_stderr_p): New pure
761 virtual function.
762 (diagnostic_text_output_format::machine_readable_stderr_p): New.
763 (diagnostic_context::get_output_format): New accessor.
765 2024-03-19 Edwin Lu <ewlu@rivosinc.com>
767 PR target/114175
768 * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
769 riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
770 if arg.type is NULL
772 2024-03-19 Jonathan Wakely <jwakely@redhat.com>
774 * doc/install.texi (Prerequisites): Document use of autogen for
775 libstdc++.
777 2024-03-19 Richard Biener <rguenther@suse.de>
779 PR tree-optimization/114151
780 PR tree-optimization/114269
781 PR tree-optimization/114322
782 PR tree-optimization/114074
783 * tree-chrec.cc (chrec_fold_multiply): Restrict the use of
784 unsigned arithmetic when actual overflow on constant operands
785 is observed.
787 2024-03-19 Jakub Jelinek <jakub@redhat.com>
789 PR target/114175
790 * config/arc/arc.cc (arc_setup_incoming_varargs): Only skip
791 arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
792 if arg.type is NULL.
794 2024-03-19 Xi Ruoyao <xry111@xry111.site>
796 PR target/114175
797 * config/loongarch/loongarch.cc
798 (loongarch_setup_incoming_varargs): Only skip
799 loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
800 functions if arg.type is NULL.
802 2024-03-19 Christophe Lyon <christophe.lyon@linaro.org>
804 PR target/114323
805 * config/arm/arm-mve-builtins.cc
806 (function_instance::reads_global_state_p): Take CP_READ_MEMORY
807 into account.
809 2024-03-19 Jakub Jelinek <jakub@redhat.com>
811 PR target/114175
812 * config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
813 function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
814 if arg.type is NULL.
816 2024-03-19 Jakub Jelinek <jakub@redhat.com>
818 PR target/114175
819 * config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
820 rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P functions
821 if arg.type is NULL.
823 2024-03-19 Richard Biener <rguenther@suse.de>
825 PR tree-optimization/114375
826 * tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
827 load permutation for masked loads but reject it when any
828 such is necessary.
829 * tree-vect-stmts.cc (vectorizable_load): Reject masked
830 VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
831 supported.
833 2024-03-19 Mary Bennett <mary.bennett@embecosm.com>
835 * common/config/riscv/riscv-common.cc: Create XCVbi extension
836 support.
837 * config/riscv/riscv.opt: Likewise.
838 * config/riscv/corev.md: Implement cv_branch<mode> pattern
839 for cv.beqimm and cv.bneimm.
840 * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
841 branch instruction pattern.
842 * config/riscv/constraints.md: Implement constraints
843 cv_bi_s5 - signed 5-bit immediate.
844 * config/riscv/predicates.md: Implement predicate
845 const_int5s_operand - signed 5 bit immediate.
846 * doc/sourcebuild.texi: Add XCVbi documentation.
848 2024-03-19 Chen Jiawei <jiawei@iscas.ac.cn>
850 * config/riscv/riscv-cores.def (RISCV_TUNE): New def.
851 (RISCV_CORE): Ditto.
852 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
853 option.
854 * config/riscv/riscv.cc: New def.
855 * config/riscv/riscv.md: New include.
856 * config/riscv/xiangshan.md: New file.
858 2024-03-18 David Malcolm <dmalcolm@redhat.com>
860 PR analyzer/110902
861 PR analyzer/110928
862 PR analyzer/111305
863 PR analyzer/111441
864 * selftest.h (ASSERT_NE_AT): New macro.
866 2024-03-18 Uros Bizjak <ubizjak@gmail.com>
868 PR target/111822
869 * config/i386/i386-features.cc (smode_convert_cst): New function
870 to handle SImode, DImode and TImode immediates, generalized from
871 timode_convert_cst.
872 (timode_convert_cst): Remove.
873 (scalar_chain::convert_op): Unify from
874 general_scalar_chain::convert_op and timode_scalar_chain::convert_op.
875 (general_scalar_chain::convert_op): Remove.
876 (timode_scalar_chain::convert_op): Remove.
877 (timode_scalar_chain::convert_insn): Update the call to
878 renamed timode_convert_cst.
879 * config/i386/i386-features.h (class scalar_chain):
880 Redeclare convert_op as protected class member.
881 (class general_calar_chain): Remove convert_op.
882 (class timode_scalar_chain): Ditto.
884 2024-03-18 Jan Hubicka <jh@suse.cz>
886 * config/i386/zn4zn5.md: Add file missed in the previous commit.
888 2024-03-18 Jan Hubicka <jh@suse.cz>
889 Karthiban Anbazhagan <Karthiban.Anbazhagan@amd.com>
891 * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
892 * common/config/i386/i386-common.cc (processor_names): Add znver5.
893 (processor_alias_table): Likewise.
894 * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
895 family.
896 (processor_subtypes): Add znver5.
897 * config.gcc (x86_64-*-* |...): Likewise.
898 * config/i386/driver-i386.cc (host_detect_local_cpu): Let
899 march=native detect znver5 cpu's.
900 * config/i386/i386-c.cc (ix86_target_macros_internal): Add
901 znver5.
902 * config/i386/i386-options.cc (m_ZNVER5): New definition
903 (processor_cost_table): Add znver5.
904 * config/i386/i386.cc (ix86_reassociation_width): Likewise.
905 * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
906 (PTA_ZNVER5): New definition.
907 * config/i386/i386.md (define_attr "cpu"): Add znver5.
908 (Scheduling descriptions) Add znver5.md.
909 * config/i386/x86-tune-costs.h (znver5_cost): New definition.
910 * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
911 (ix86_adjust_cost): Likewise.
912 * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
913 (avx512_store_by_pieces): Add m_ZNVER5.
914 * doc/extend.texi: Add znver5.
915 * doc/invoke.texi: Likewise.
916 * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler.
918 2024-03-18 Georg-Johann Lay <avr@gjlay.de>
920 * config/avr/constraints.md (CX2, CX3, CX4): New constraints.
921 * config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
922 * config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
923 * config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
924 (xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
925 (xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
927 2024-03-18 liuhongt <hongtao.liu@intel.com>
929 PR target/114334
930 * config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
931 (MODEF248): New mode iterator.
932 (ssevecmodesuffix): Hanlde BF and HF.
933 * config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
934 (<code><mode>3): Ditto.
936 2024-03-18 John David Anglin <danglin@gcc.gnu.org>
938 PR rtl-optimization/112415
939 * config/pa/pa.cc (pa_emit_move_sequence): Revise condition
940 for symbolic memory operands.
941 (pa_legitimate_address_p): Revise LO_SUM condition.
942 * config/pa/pa.h (INT14_OK_STRICT): Revise define. Move
943 comment about GNU linker to predicates.md.
944 * config/pa/predicates.md (floating_point_store_memory_operand):
945 Revise condition for symbolic memory operands. Update
946 comment.
948 2024-03-17 John David Anglin <danglin@gcc.gnu.org>
950 * config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.
952 2024-03-16 Jakub Jelinek <jakub@redhat.com>
954 PR target/114175
955 * config/i386/i386.cc (ix86_setup_incoming_varargs): Only skip
956 ix86_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
957 if arg.type is NULL.
959 2024-03-16 Jakub Jelinek <jakub@redhat.com>
961 PR tree-optimization/114329
962 * gimple-lower-bitint.cc (struct bitint_large_huge): Declare
963 build_bit_field_ref method.
964 (bitint_large_huge::build_bit_field_ref): New method.
965 (bitint_large_huge::lower_mergeable_stmt): Use it.
967 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
969 * config/riscv/riscv.opt.urls: Regenerated.
970 * config/rs6000/sysv4.opt.urls: Likewise.
971 * config/xtensa/xtensa.opt.urls: Likewise.
973 2024-03-15 Jakub Jelinek <jakub@redhat.com>
975 * lower-subreg.cc (resolve_simple_move): Fix comment typo,
976 betwee -> between.
977 * edit-context.cc (class line_event): Fix comment typo,
978 betweeen -> between.
980 2024-03-15 Jakub Jelinek <jakub@redhat.com>
982 PR target/114339
983 * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp) <case LE>: Fix
984 a pasto, compare code against LE rather than GE.
986 2024-03-15 Joe Ramsay <Joe.Ramsay@arm.com>
988 * match.pd: Fix truncation pattern for -fno-signed-zeroes
990 2024-03-15 Jakub Jelinek <jakub@redhat.com>
992 PR middle-end/114332
993 * expr.cc (expand_expr_real_1): EXTEND_BITINT also CALL_EXPR results.
995 2024-03-15 Jakub Jelinek <jakub@redhat.com>
997 PR tree-optimization/113466
998 * gimple-lower-bitint.cc (bitint_large_huge): Add m_returns_twice_calls
999 member.
1000 (bitint_large_huge::bitint_large_huge): Initialize it.
1001 (bitint_large_huge::~bitint_large_huge): Release it.
1002 (bitint_large_huge::lower_call): Remember ECF_RETURNS_TWICE call stmts
1003 before which at least one statement has been inserted.
1004 (gimple_lower_bitint): Move argument loads before ECF_RETURNS_TWICE
1005 calls to a different block and add corresponding PHIs.
1007 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
1009 * config/mips/mips.opt: Support -mstrict-align, and use
1010 TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
1011 as alias.
1012 * config/mips/mips.h: Use TARGET_STRICT_ALIGN.
1013 * config/mips/mips.opt.urls: Regenerate.
1014 * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
1016 2024-03-15 Tejas Belagod <tejas.belagod@arm.com>
1018 PR middle-end/114108
1019 * tree-vect-patterns.cc (vect_recog_abd_pattern): Call
1020 vect_convert_output with the correct vecitype.
1022 2024-03-15 Chenghui Pan <panchenghui@loongson.cn>
1024 * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
1025 Remove masking of operand 3.
1027 2024-03-14 Jason Merrill <jason@redhat.com>
1029 * tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
1030 comments.
1032 2024-03-14 John David Anglin <danglin@gcc.gnu.org>
1034 PR target/114288
1035 * config/pa/pa.cc (pa_legitimate_address_p): Don't allow
1036 14-bit displacements before reload for modes that may use
1037 a floating-point load or store.
1039 2024-03-14 David Faust <david.faust@oracle.com>
1041 * config/bpf/bpf.h (INT8_TYPE): Change to signed char.
1043 2024-03-14 Max Filippov <jcmvbkbc@gmail.com>
1045 * config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
1046 patterns ahead of the l32i.n and s32i.n.
1048 2024-03-14 Jakub Jelinek <jakub@redhat.com>
1050 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.
1052 2024-03-14 Jakub Jelinek <jakub@redhat.com>
1054 PR middle-end/113907
1055 * ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
1056 SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
1057 functions.
1059 2024-03-14 Xi Ruoyao <xry111@xry111.site>
1061 * config/loongarch/loongarch.md (any_ge): Remove.
1062 (sge<u>_<X:mode><GPR:mode>): Remove.
1064 2024-03-14 Jakub Jelinek <jakub@redhat.com>
1066 PR target/114310
1067 * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
1068 TImode force newval into a register.
1070 2024-03-14 Chung-Lin Tang <cltang@baylibre.com>
1072 * tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
1073 (OMP_CLAUSE__CACHE__READONLY): New macro.
1074 * tree-core.h (struct GTY(()) tree_base): Adjust comments for new
1075 uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
1076 OMP_CLAUSE__CACHE__READONLY.
1077 * tree-pretty-print.cc (dump_omp_clause): Add support for printing
1078 OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.
1080 2024-03-14 Andreas Krebbel <krebbel@linux.ibm.com>
1082 * config/s390/s390.cc (s390_encode_section_info): Adjust the check
1083 for misaligned symbols.
1084 * config/s390/s390.opt: Improve documentation.
1086 2024-03-14 Jakub Jelinek <jakub@redhat.com>
1088 * gimple-iterator.cc (edge_before_returns_twice_call): Copy all
1089 flags and probability from ad_edge to e edge. If CDI_DOMINATORS
1090 are computed, recompute immediate dominator of other_edge->src
1091 and other_edge->dest.
1092 (gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
1093 for the returns_twice call case to the gsi_for_stmt (stmt) to deal
1094 with update it for bb splitting.
1096 2024-03-14 liuhongt <hongtao.liu@intel.com>
1098 * config/i386/i386-features.cc
1099 (general_scalar_chain::convert_op): Handle REG_EH_REGION note.
1100 (convert_scalars_to_vector): Ditto.
1101 * config/i386/i386-features.h (class scalar_chain): New
1102 memeber control_flow_insns.
1104 2024-03-13 Jakub Jelinek <jakub@redhat.com>
1106 PR middle-end/114319
1107 * gimple-ssa-store-merging.cc
1108 (imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
1109 allow matching __builtin_bswap64 if there is bswapsi2 optab.
1111 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1113 * config/s390/s390.cc (s390_secondary_reload): Guard
1114 SYMBOL_FLAG_NOTALIGN2_P.
1116 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1118 * config/s390/s390-builtin-types.def: Update to reflect latest
1119 changes.
1120 * config/s390/s390-builtins.def: Streamline vector builtins with
1121 LLVM.
1123 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1125 * config/s390/s390-builtins.def (vec_permi): Deprecate.
1126 (vec_ctd): Deprecate.
1127 (vec_ctd_s64): Deprecate.
1128 (vec_ctd_u64): Deprecate.
1129 (vec_ctsl): Deprecate.
1130 (vec_ctul): Deprecate.
1131 (vec_ld2f): Deprecate.
1132 (vec_st2f): Deprecate.
1133 (vec_insert): Deprecate overloads with bool vectors.
1135 2024-03-13 Jakub Jelinek <jakub@redhat.com>
1137 PR middle-end/114313
1138 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
1139 TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
1140 (bitint_large_huge::handle_load): Pass NULL_TREE rather than
1141 rhs_type to limb_access for the bitfield load cases.
1142 (bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
1143 lhs_type to limb_access if nlhs is non-NULL.
1145 2024-03-13 Jakub Jelinek <jakub@redhat.com>
1147 PR sanitizer/112709
1148 * asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
1149 build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
1150 gsi_safe_insert_before instead of gsi_insert_before.
1152 2024-03-13 Jakub Jelinek <jakub@redhat.com>
1154 PR sanitizer/112709
1155 * gimple-iterator.h (gsi_safe_insert_before,
1156 gsi_safe_insert_seq_before): Declare.
1157 * gimple-iterator.cc: Include gimplify.h.
1158 (edge_before_returns_twice_call, adjust_before_returns_twice_call,
1159 gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
1160 * ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
1161 instrument_nonnull_arg, instrument_nonnull_return): Use
1162 gsi_safe_insert_before instead of gsi_insert_before.
1163 (maybe_instrument_pointer_overflow): Use force_gimple_operand,
1164 gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
1165 instead of force_gimple_operand_gsi.
1166 (instrument_object_size): Likewise. Use gsi_safe_insert_before
1167 instead of gsi_insert_before.
1169 2024-03-12 Richard Biener <rguenther@suse.de>
1171 PR tree-optimization/114121
1172 * tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
1173 converted operand properly.
1174 (chrec_fold_multiply): Likewise. Handle missed recursion.
1176 2024-03-12 Jakub Jelinek <jakub@redhat.com>
1178 PR sanitizer/112709
1179 * asan.cc (has_stmt_been_instrumented_p): Don't instrument call
1180 stores on the caller side unless it is a call to a builtin or
1181 internal function or function doesn't return by hidden reference.
1182 (maybe_instrument_call): Likewise.
1183 (instrument_derefs): Instrument stores to RESULT_DECL if
1184 returning by hidden reference.
1186 2024-03-12 Jakub Jelinek <jakub@redhat.com>
1188 PR tree-optimization/114293
1189 * tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
1190 max is smaller than min, set max to ~(size_t)0.
1192 2024-03-12 Pan Li <pan2.li@intel.com>
1194 * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
1195 code style greater than 80 chars.
1196 (riscv_cpu_cpp_builtins): Fix useless empty line, indent
1197 with 3 space(s) and argument unalignment.
1199 2024-03-12 Richard Biener <rguenther@suse.de>
1201 PR tree-optimization/114297
1202 * tree-vect-loop.cc (vectorizable_live_operation): Pass in the
1203 live stmts SLP node to vect_create_epilog_for_reduction.
1205 2024-03-12 Andrew Pinski <quic_apinski@quicinc.com>
1207 PR driver/114314
1208 * common.opt (fmultiflags): Add RejectNegative.
1210 2024-03-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
1212 * config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
1213 * config/aarch64/aarch64.opt: Likewise.
1214 * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
1215 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
1216 (aarch64_expand_epilogue): Likewise.
1217 (aarch64_post_cfi_startproc): Likewise.
1218 (aarch64_handle_no_branch_protection): Copy and rename.
1219 (aarch64_handle_standard_branch_protection): Likewise.
1220 (aarch64_handle_pac_ret_protection): Likewise.
1221 (aarch64_handle_pac_ret_leaf): Likewise.
1222 (aarch64_handle_pac_ret_b_key): Likewise.
1223 (aarch64_handle_bti_protection): Likewise.
1224 (aarch64_override_options): Update branch protection validation.
1225 (aarch64_handle_attr_branch_protection): Likewise.
1226 * config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
1227 Pass branch protection type description as argument.
1228 (struct aarch_branch_protect_type): Move from aarch-common.h.
1229 * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
1230 Remove.
1231 (aarch_handle_standard_branch_protection): Remove.
1232 (aarch_handle_pac_ret_protection): Remove.
1233 (aarch_handle_pac_ret_leaf): Remove.
1234 (aarch_handle_pac_ret_b_key): Remove.
1235 (aarch_handle_bti_protection): Remove.
1236 (aarch_validate_mbranch_protection): Pass branch protection type
1237 description as argument.
1238 * config/arm/aarch-common.h (enum aarch_key_type): Remove.
1239 (struct aarch_branch_protect_type): Remove.
1240 * config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
1241 * config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
1242 (arm_handle_standard_branch_protection): Likewise.
1243 (arm_handle_pac_ret_protection): Likewise.
1244 (arm_handle_pac_ret_leaf): Likewise.
1245 (arm_handle_bti_protection): Likewise.
1246 (arm_configure_build_target): Update branch protection validation.
1247 * config/arm/arm.opt: Remove aarch_ra_sign_key.
1249 2024-03-11 Richard Biener <rguenther@suse.de>
1251 PR middle-end/114299
1252 * gimplify.cc (internal_get_tmp_var): When gimplification
1253 of VAL failed, return a decl.
1255 2024-03-11 Jakub Jelinek <jakub@redhat.com>
1257 PR tree-optimization/114278
1258 * tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
1259 longer addressable, set DECL_NOT_GIMPLE_REG_P on them.
1261 2024-03-11 Eric Botcazou <ebotcazou@adacore.com>
1263 PR debug/113519
1264 PR debug/113777
1265 * dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
1266 generate the DIE with the same parent as in the regular case.
1268 2024-03-11 Andrew Pinski <quic_apinski@quicinc.com>
1270 PR middle-end/95351
1271 * fold-const.cc (merge_truthop_with_opposite_arm): Use
1272 the type of the operands of the comparison and not the type
1273 of the comparison.
1275 2024-03-10 jlaw <jeffreyalaw@gmail.com>
1277 PR tree-optimization/110199
1278 * tree-ssa-scopedtables.cc
1279 (avail_exprs_stack::simplify_binary_operation): Generalize handling
1280 of MIN_EXPR/MAX_EXPR to allow additional simplifications. Canonicalize
1281 comparison operands for other cases.
1283 2024-03-10 Pan Li <pan2.li@intel.com>
1285 * tree-vect-stmts.cc (vectorizable_store): Enable the assert
1286 during transform process.
1287 (vectorizable_load): Ditto.
1289 2024-03-10 jlaw <jeffreyalaw@gmail.com>
1291 PR target/102250
1292 * doc/install.texi: Document need for python when building
1293 RISC-V compilers.
1295 2024-03-10 jlaw <jeffreyalaw@gmail.com>
1297 PR target/111362
1298 * mode-switching.cc (optimize_mode_switching): Only process
1299 NONDEBUG insns.
1301 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
1303 * config/avr/avr.md: Fix typos in comment, indentation glitches
1304 and some other nits.
1306 2024-03-09 Jakub Jelinek <jakub@redhat.com>
1308 PR target/114284
1309 * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
1310 src containing MEMs unless prop.likely_profitable_p ().
1312 2024-03-09 Xi Ruoyao <xry111@xry111.site>
1314 * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
1315 Support 'Q' for R_LARCH_RELAX for TLS IE.
1316 (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
1317 IE.
1318 * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
1320 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
1322 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
1323 usum_widenqihi and add_zero_extend1.
1324 [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
1325 sub+sign_extend.
1326 * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
1327 Compute exact insn lengths.
1328 (*usum_widenqihi3): Allow input operands to commute.
1330 2024-03-09 Jakub Jelinek <jakub@redhat.com>
1332 * config/i386/i386.opt.urls: Regenerate.
1334 2024-03-09 Lulu Cheng <chenglulu@loongson.cn>
1336 * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
1337 In loongarch64, a sign extension operation is added when
1338 operands[2] is a register operand and the mode is SImode.
1340 2024-03-08 Martin Jambor <mjambor@suse.cz>
1342 PR ipa/113757
1343 * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
1344 id->killed_new_ssa_names.
1346 2024-03-08 Vladimir N. Makarov <vmakarov@redhat.com>
1348 PR target/113790
1349 * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
1350 for non-reload pseudo too.
1352 2024-03-08 David Faust <david.faust@oracle.com>
1354 * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
1355 not attempt inline expansion if size is above threshold.
1356 * config/bpf/bpf.opt (-minline-memops-threshold): New option.
1357 * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
1358 Document.
1360 2024-03-08 Richard Biener <rguenther@suse.de>
1362 PR tree-optimization/114269
1363 PR tree-optimization/114074
1364 * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
1365 in the third CASE_CONVERT case as well.
1366 (chrec_fold_multiply): Handle sign-conversions from unsigned
1367 by performing the operation in the unsigned type.
1369 2024-03-08 Georg-Johann Lay <avr@gjlay.de>
1371 * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
1372 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
1374 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1376 * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
1377 asm_noperands < 0 means it is not asm goto too.
1379 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1381 PR target/38534
1382 * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
1383 option.
1384 * config/i386/i386-options.cc (ix86_set_func_type): Don't use
1385 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
1386 ix86_noreturn_no_callee_saved_registers is enabled.
1387 * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
1389 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1391 PR debug/113918
1392 * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
1393 on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
1395 2024-03-08 demin.han <demin.han@starfivetech.com>
1397 PR target/114264
1398 * config/riscv/riscv-vector-costs.cc: Fix ICE
1400 2024-03-08 Haochen Gui <guihaoc@gcc.gnu.org>
1402 * fwprop.cc (forward_propagate_into): Return false for volatile set
1403 source rtx.
1405 2024-03-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
1407 PR target/113618
1408 * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
1409 (aarch64_expand_cpymem): Emit single load/store only.
1410 (aarch64_set_one_block): Emit single stores only.
1412 2024-03-07 Robin Dapp <rdapp@ventanamicro.com>
1414 PR middle-end/114196
1415 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
1416 vectorization guards.
1418 2024-03-07 Jonathan Wakely <jwakely@redhat.com>
1420 * doc/cppopts.texi: Remove incorrect claim about -dD not
1421 outputting predefined macros.
1423 2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
1425 PR target/113950
1426 * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
1427 and simplify else if with else.
1429 2024-03-07 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
1431 * system.h: Include safe-ctype.h after C++ standard headers.
1433 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1435 PR rtl-optimization/110079
1436 * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
1437 asm goto.
1439 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1441 PR middle-end/105533
1442 * expmed.cc (choose_mult_variant): Only try the val - 1 variant
1443 if val is not HOST_WIDE_INT_MIN or if mode has exactly
1444 HOST_BITS_PER_WIDE_INT precision. Avoid triggering UB while computing
1445 val - 1.
1447 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1449 PR middle-end/105533
1450 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
1451 Multiple op->off by BITS_PER_UNIT instead of shifting it left by
1452 LOG2_BITS_PER_UNIT.
1454 2024-03-07 Yang Yujie <yangyujie@loongson.cn>
1456 * config.gcc: Add a case for loongarch*-*-linux-musl*.
1457 * config/loongarch/linux.h: Disable the multilib-compatible
1458 treatment for *musl* targets.
1459 * config/loongarch/musl.h: New file.
1461 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1463 PR tree-optimization/114009
1464 * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
1465 argument even for GENERIC, not just for GIMPLE.
1466 * match.pd (a * !a -> 0): New simplifications.
1468 2024-03-07 demin.han <demin.han@starfivetech.com>
1470 * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
1471 * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
1472 (expand_vec_cmp_float): Adapt arguments
1474 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
1476 PR target/114232
1477 * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
1478 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
1479 (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1480 (<plusminus:insn>v2qi3): Enable for optimize_size instead
1481 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
1482 (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1483 (<any_shift:insn>v2qi3): Enable for optimize_size instead
1484 of optimize_function_for_size_p.
1486 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
1488 PR target/114200
1489 PR target/114202
1490 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
1492 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
1494 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
1495 (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
1496 offset handling.
1497 (costs::add_stmt_cost): Also adjust cost for statements without
1498 stmt_info.
1499 * config/riscv/riscv-vector-costs.h: Define zero constant.
1501 2024-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
1503 PR target/113915
1504 * config/arm/arm.md (NOCOND): Improve comment.
1505 (arm_rev*) Add predicable.
1506 * config/arm/arm.cc (arm_final_prescan_insn): Add check for
1507 PREDICABLE_YES.
1509 2024-03-06 Jeff Law <jlaw@ventanamicro.com>
1511 PR target/113001
1512 PR target/112871
1513 * config/riscv/riscv.cc (expand_conditional_move): Do not swap
1514 operands when the comparison operand is the same as the false
1515 arm for a NE test.
1517 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
1519 * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
1520 Eliminate common code and use generic code instead.
1522 2024-03-06 Georg-Johann Lay <avr@gjlay.de>
1524 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
1525 rtx cost.
1527 2024-03-06 Richard Biener <rguenther@suse.de>
1529 PR tree-optimization/114239
1530 * tree-vect-loop.cc (vect_get_vect_def): Remove.
1531 (vect_create_epilog_for_reduction): The passed in stmt_info
1532 should now be the live stmt that produces the scalar reduction
1533 result. Revert PR114192 fix. Base reduction info off
1534 info_for_reduction. Remove special handling of
1535 early-break/peeled, restore original vector def gathering.
1536 Make sure to pick the correct exit PHIs.
1537 (vectorizable_live_operation): Pass in the proper stmt_info
1538 for early break exits.
1540 2024-03-06 Richard Sandiford <richard.sandiford@arm.com>
1542 * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
1543 out-of-class definitions of static constants.
1545 2024-03-06 Richard Biener <rguenther@suse.de>
1547 PR tree-optimization/114249
1548 * tree-vect-slp.cc (vect_build_slp_instance): Move making
1549 a BB reduction lane number even ...
1550 (vect_slp_check_for_roots): ... here to avoid leaking
1551 pattern defs.
1553 2024-03-06 Richard Biener <rguenther@suse.de>
1555 PR tree-optimization/114246
1556 * tree-ssa-dse.cc (increment_start_addr): Strip useless
1557 type conversions from the adjusted address.
1559 2024-03-06 Jakub Jelinek <jakub@redhat.com>
1561 PR rtl-optimization/114190
1562 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
1563 Call df_remove_problem for df_note before calling df_analyze.
1565 2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
1566 Indu Bhagat <indu.bhagat@oracle.com>
1568 PR debug/114186
1569 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
1570 in the correct order of the dimensions.
1571 (gen_ctf_subrange_type): Refactor out handling of
1572 DW_TAG_subrange_type DIE to here.
1574 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1576 PR sanitizer/97696
1577 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
1579 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1581 * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
1582 and luti_strided.
1583 * config/aarch64/aarch64-sme.md
1584 (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
1585 (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
1586 (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
1587 * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
1588 (early_ra::maybe_convert_to_strided_access): Remove support for
1589 strided LUTI2 and LUTI4.
1591 2024-03-05 Richard Earnshaw <rearnsha@arm.com>
1593 PR target/113510
1594 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
1595 low_register_operand.
1597 2024-03-05 Georg-Johann Lay <avr@gjlay.de>
1599 * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
1600 in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
1601 to "X = Y, X o= CST".
1603 2024-03-05 Xi Ruoyao <xry111@xry111.site>
1605 * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
1606 s9 as an alias of r22.
1608 2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
1610 * config/avr/avr-protos.h (avr_out_insv): New proto.
1611 * config/avr/avr.cc (avr_out_insv): New function.
1612 (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
1613 (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
1614 * config/avr/avr.md (define_attr "adjust_len") Add insv.
1615 (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
1616 Add constraint alternative where the 3rd operand is a power
1617 of 2, and the source register may differ from the destination.
1618 (*insv.any_shift.<mode>_split): Call avr_out_insv to output
1619 instructions. Set attr "length" to "insv".
1620 * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
1622 2024-03-05 Richard Biener <rguenther@suse.de>
1624 PR tree-optimization/114231
1625 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
1626 processing a BB SLP root.
1628 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1630 PR rtl-optimization/114211
1631 * lower-subreg.cc (resolve_simple_move): For double-word
1632 rotates by BITS_PER_WORD if there is overlap between source
1633 and destination use a temporary.
1635 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1637 PR middle-end/114157
1638 * gimple-lower-bitint.cc: Include stor-layout.h.
1639 (mergeable_op): Return true for BIT_FIELD_REF.
1640 (struct bitint_large_huge): Declare handle_bit_field_ref method.
1641 (bitint_large_huge::handle_bit_field_ref): New method.
1642 (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
1644 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1646 PR target/114116
1647 * config/i386/i386.h (enum call_saved_registers_type): Add
1648 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
1649 * config/i386/i386-options.cc (ix86_set_func_type): Remove
1650 has_no_callee_saved_registers variable, add no_callee_saved_registers
1651 instead, initialize it depending on whether it is
1652 no_callee_saved_registers function or not. Don't set it if
1653 no_caller_saved_registers attribute is present. Adjust users.
1654 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
1655 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
1656 TYPE_NO_CALLEE_SAVED_REGISTERS.
1657 (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
1659 2024-03-05 Pan Li <pan2.li@intel.com>
1661 * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
1662 mode_size related code.
1664 2024-03-05 Patrick Palka <ppalka@redhat.com>
1666 * doc/invoke.texi (-Wno-global-module): Document.
1668 2024-03-04 David Faust <david.faust@oracle.com>
1670 * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
1671 * config/bpf/bpf.cc (bpf_expand_setmem): New.
1672 * config/bpf/bpf.md (setmemdi): New define_expand.
1674 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1676 PR rtl-optimization/113010
1677 * combine.cc (simplify_comparison): Guard the
1678 WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
1679 and initialize inner_mode.
1681 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1683 * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1684 VMLALDAVAXQ_U cases.
1685 (VMLALDAVXQ): Remove iterator.
1686 (VMLALDAVXQ_P): Likewise.
1687 (VMLALDAVAXQ): Likewise.
1688 * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
1689 mode iterator attribute with V4BI mode.
1690 * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1691 VMLALDAVAXQ_U): Remove unused unspecs.
1693 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1695 * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
1696 * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
1697 attribute.
1698 * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
1699 vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
1700 vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
1701 vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
1702 vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
1703 vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
1704 vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
1705 vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
1706 vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
1707 vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
1709 2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1711 * config/arm/arm.md (mve_unpredicated_insn): New attribute.
1712 * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
1713 (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
1714 (MVE_VPT_PREDICABLE_INSN_P): Likewise.
1715 * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
1716 * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
1717 (arm_vcx1q<a>v16qi): Likewise.
1718 (arm_vcx1qav16qi): Likewise.
1719 (arm_vcx1qv16qi): Likewise.
1720 (arm_vcx2q<a>_p_v16qi): Likewise.
1721 (arm_vcx2q<a>v16qi): Likewise.
1722 (arm_vcx2qav16qi): Likewise.
1723 (arm_vcx2qv16qi): Likewise.
1724 (arm_vcx3q<a>_p_v16qi): Likewise.
1725 (arm_vcx3q<a>v16qi): Likewise.
1726 (arm_vcx3qav16qi): Likewise.
1727 (arm_vcx3qv16qi): Likewise.
1728 (@mve_<mve_insn>q_<supf><mode>): Likewise.
1729 (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
1730 (@mve_<mve_insn>q_<supf>v4si): Likewise.
1731 (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
1732 (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
1733 (@mve_<mve_insn>q_f<mode>): Likewise.
1734 (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
1735 (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
1736 (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
1737 (@mve_<mve_insn>q_m_f<mode>): Likewise.
1738 (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
1739 (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
1740 (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
1741 (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
1742 (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
1743 (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
1744 (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
1745 (mve_v<absneg_str>q_f<mode>): Likewise.
1746 (mve_<mve_addsubmul>q<mode>): Likewise.
1747 (mve_<mve_addsubmul>q_f<mode>): Likewise.
1748 (mve_vadciq_<supf>v4si): Likewise.
1749 (mve_vadciq_m_<supf>v4si): Likewise.
1750 (mve_vadcq_<supf>v4si): Likewise.
1751 (mve_vadcq_m_<supf>v4si): Likewise.
1752 (mve_vandq_<supf><mode>): Likewise.
1753 (mve_vandq_f<mode>): Likewise.
1754 (mve_vandq_m_<supf><mode>): Likewise.
1755 (mve_vandq_m_f<mode>): Likewise.
1756 (mve_vandq_s<mode>): Likewise.
1757 (mve_vandq_u<mode>): Likewise.
1758 (mve_vbicq_<supf><mode>): Likewise.
1759 (mve_vbicq_f<mode>): Likewise.
1760 (mve_vbicq_m_<supf><mode>): Likewise.
1761 (mve_vbicq_m_f<mode>): Likewise.
1762 (mve_vbicq_m_n_<supf><mode>): Likewise.
1763 (mve_vbicq_n_<supf><mode>): Likewise.
1764 (mve_vbicq_s<mode>): Likewise.
1765 (mve_vbicq_u<mode>): Likewise.
1766 (@mve_vclzq_s<mode>): Likewise.
1767 (mve_vclzq_u<mode>): Likewise.
1768 (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
1769 (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
1770 (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
1771 (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
1772 (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
1773 (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
1774 (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
1775 (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
1776 (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
1777 (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
1778 (mve_vcvtaq_<supf><mode>): Likewise.
1779 (mve_vcvtaq_m_<supf><mode>): Likewise.
1780 (mve_vcvtbq_f16_f32v8hf): Likewise.
1781 (mve_vcvtbq_f32_f16v4sf): Likewise.
1782 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
1783 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
1784 (mve_vcvtmq_<supf><mode>): Likewise.
1785 (mve_vcvtmq_m_<supf><mode>): Likewise.
1786 (mve_vcvtnq_<supf><mode>): Likewise.
1787 (mve_vcvtnq_m_<supf><mode>): Likewise.
1788 (mve_vcvtpq_<supf><mode>): Likewise.
1789 (mve_vcvtpq_m_<supf><mode>): Likewise.
1790 (mve_vcvtq_from_f_<supf><mode>): Likewise.
1791 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
1792 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
1793 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
1794 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
1795 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
1796 (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
1797 (mve_vcvtq_to_f_<supf><mode>): Likewise.
1798 (mve_vcvttq_f16_f32v8hf): Likewise.
1799 (mve_vcvttq_f32_f16v4sf): Likewise.
1800 (mve_vcvttq_m_f16_f32v8hf): Likewise.
1801 (mve_vcvttq_m_f32_f16v4sf): Likewise.
1802 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
1803 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
1804 (mve_veorq_s><mode>): Likewise.
1805 (mve_veorq_u><mode>): Likewise.
1806 (mve_veorq_f<mode>): Likewise.
1807 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
1808 (mve_vidupq_u<mode>_insn): Likewise.
1809 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
1810 (mve_viwdupq_wb_u<mode>_insn): Likewise.
1811 (mve_vldrbq_<supf><mode>): Likewise.
1812 (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
1813 (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
1814 (mve_vldrbq_z_<supf><mode>): Likewise.
1815 (mve_vldrdq_gather_base_<supf>v2di): Likewise.
1816 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
1817 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
1818 (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
1819 (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
1820 (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
1821 (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
1822 (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
1823 (mve_vldrhq_<supf><mode>): Likewise.
1824 (mve_vldrhq_fv8hf): Likewise.
1825 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
1826 (mve_vldrhq_gather_offset_fv8hf): Likewise.
1827 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
1828 (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
1829 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
1830 (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
1831 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
1832 (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
1833 (mve_vldrhq_z_<supf><mode>): Likewise.
1834 (mve_vldrhq_z_fv8hf): Likewise.
1835 (mve_vldrwq_<supf>v4si): Likewise.
1836 (mve_vldrwq_fv4sf): Likewise.
1837 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
1838 (mve_vldrwq_gather_base_fv4sf): Likewise.
1839 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
1840 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
1841 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
1842 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
1843 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
1844 (mve_vldrwq_gather_base_z_fv4sf): Likewise.
1845 (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
1846 (mve_vldrwq_gather_offset_fv4sf): Likewise.
1847 (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
1848 (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
1849 (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
1850 (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
1851 (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
1852 (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
1853 (mve_vldrwq_z_<supf>v4si): Likewise.
1854 (mve_vldrwq_z_fv4sf): Likewise.
1855 (mve_vmvnq_s<mode>): Likewise.
1856 (mve_vmvnq_u<mode>): Likewise.
1857 (mve_vornq_<supf><mode>): Likewise.
1858 (mve_vornq_f<mode>): Likewise.
1859 (mve_vornq_m_<supf><mode>): Likewise.
1860 (mve_vornq_m_f<mode>): Likewise.
1861 (mve_vornq_s<mode>): Likewise.
1862 (mve_vornq_u<mode>): Likewise.
1863 (mve_vorrq_<supf><mode>): Likewise.
1864 (mve_vorrq_f<mode>): Likewise.
1865 (mve_vorrq_m_<supf><mode>): Likewise.
1866 (mve_vorrq_m_f<mode>): Likewise.
1867 (mve_vorrq_m_n_<supf><mode>): Likewise.
1868 (mve_vorrq_n_<supf><mode>): Likewise.
1869 (mve_vorrq_s<mode>): Likewise.
1870 (mve_vorrq_s<mode>): Likewise.
1871 (mve_vsbciq_<supf>v4si): Likewise.
1872 (mve_vsbciq_m_<supf>v4si): Likewise.
1873 (mve_vsbcq_<supf>v4si): Likewise.
1874 (mve_vsbcq_m_<supf>v4si): Likewise.
1875 (mve_vshlcq_<supf><mode>): Likewise.
1876 (mve_vshlcq_m_<supf><mode>): Likewise.
1877 (mve_vshrq_m_n_<supf><mode>): Likewise.
1878 (mve_vshrq_n_<supf><mode>): Likewise.
1879 (mve_vstrbq_<supf><mode>): Likewise.
1880 (mve_vstrbq_p_<supf><mode>): Likewise.
1881 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
1882 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
1883 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
1884 (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
1885 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
1886 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
1887 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
1888 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
1889 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
1890 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
1891 (mve_vstrhq_<supf><mode>): Likewise.
1892 (mve_vstrhq_fv8hf): Likewise.
1893 (mve_vstrhq_p_<supf><mode>): Likewise.
1894 (mve_vstrhq_p_fv8hf): Likewise.
1895 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
1896 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
1897 (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
1898 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
1899 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
1900 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
1901 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
1902 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
1903 (mve_vstrwq_<supf>v4si): Likewise.
1904 (mve_vstrwq_fv4sf): Likewise.
1905 (mve_vstrwq_p_<supf>v4si): Likewise.
1906 (mve_vstrwq_p_fv4sf): Likewise.
1907 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
1908 (mve_vstrwq_scatter_base_fv4sf): Likewise.
1909 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
1910 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
1911 (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
1912 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
1913 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
1914 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
1915 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
1916 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
1917 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
1918 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
1919 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
1920 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
1921 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
1922 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
1924 2024-03-04 Marek Polacek <polacek@redhat.com>
1926 * doc/extend.texi: Update [[gnu::no_dangling]].
1928 2024-03-04 Andrew Stubbs <ams@baylibre.com>
1930 * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
1931 * expr.cc (store_constructor): Likewise.
1932 (do_store_flag): Likewise.
1934 2024-03-04 Mark Wielaard <mark@klomp.org>
1936 * common.opt.urls: Regenerate.
1937 * config/avr/avr.opt.urls: Likewise.
1938 * config/i386/i386.opt.urls: Likewise.
1939 * config/pru/pru.opt.urls: Likewise.
1940 * config/riscv/riscv.opt.urls: Likewise.
1941 * config/rs6000/rs6000.opt.urls: Likewise.
1943 2024-03-04 Richard Biener <rguenther@suse.de>
1945 PR tree-optimization/114197
1946 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
1947 there are volatile bitfield accesses.
1948 (pass_if_conversion::execute): Throw away result if the
1949 if-converted and original loops are not nested as expected.
1951 2024-03-04 Richard Biener <rguenther@suse.de>
1953 PR tree-optimization/114164
1954 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
1955 the code generated for mask argument setup is not supported.
1957 2024-03-04 Richard Biener <rguenther@suse.de>
1959 PR tree-optimization/114203
1960 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
1961 adjustment before making the result defined at zero.
1963 2024-03-04 Richard Biener <rguenther@suse.de>
1965 PR tree-optimization/114192
1966 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
1967 appropriate def for the live out stmt in case of an alternate
1968 exit.
1970 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1972 PR middle-end/114209
1973 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
1974 unshare_expr when creating a MEM_REF from MEM_REF.
1975 (bitint_large_huge::lower_stmt): Call unshare_expr.
1977 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1979 PR target/114184
1980 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
1981 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
1982 register.
1984 2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
1986 PR target/114187
1987 * simplify-rtx.cc (simplify_context::simplify_subreg): Call
1988 lowpart_subreg to perform type conversion, to avoid confusion
1989 over the offset to use in the call to simplify_reg_subreg.
1991 2024-03-03 Greg McGary <gkm@rivosinc.com>
1993 PR rtl-optimization/113010
1994 * combine.cc (simplify_comparison): Simplify a SUBREG on
1995 WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
1996 MEM load.
1998 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
2000 * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
2001 Use bool in place of int for boolean logic (if possible).
2002 Move declarations to definitions (if possible).
2003 * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
2004 * config/avr/avr-dimode.md: Same.
2005 * config/avr/constraints.md: Same.
2006 * config/avr/predicates.md: Same.
2008 2024-03-03 Uros Bizjak <ubizjak@gmail.com>
2010 PR target/113720
2011 * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
2012 (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
2013 simplify insn RTX using UMUL_HIGHPART rtx_code.
2014 (*umuldi3_highpart_const): Remove.
2016 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
2018 PR target/114100
2019 * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
2020 * config/avr/avr.cc (_reg_unused_after): Make static. And
2021 add 3rd argument to skip the current insn.
2022 (reg_unused_after): Adjust call of reg_unused_after.
2023 (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
2024 unneeded frame pointer adjustments.
2026 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
2028 PR target/92729
2029 * config/avr/avr.md (define_attr "cc"): Remove.
2030 * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
2031 from prototype.
2032 * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
2033 its uses. Add insn argument.
2034 (avr_out_plus_symbol): Remove pcc argument and its uses.
2035 (avr_out_plus): Remove pcc argument and its uses.
2036 Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
2037 (avr_out_round): Adjust call of avr_out_plus.
2039 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
2041 * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
2042 from r14-9273.
2044 2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
2046 PR target/101737
2047 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
2048 is not an insn, but e.g. a code label.
2050 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
2052 * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
2053 * config/avr/avr.cc: Use them instead of magic numbers when it
2054 means a register number.
2056 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
2058 * config/avr/avr.cc: Adjust some comments.
2060 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
2062 PR target/114100
2063 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
2064 the low part of the frame pointer with 8-bit stack pointer.
2066 2024-03-01 Patrick Palka <ppalka@redhat.com>
2068 PR c++/104919
2069 PR c++/106009
2070 * tree-inline.cc (remap_decl): Handle copy_decl returning the
2071 original decl.
2072 (remap_decls): Handle remap_decl returning the original decl.
2073 (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
2074 CONST_DECL.
2076 2024-03-01 Jeff Law <jlaw@ventanamicro.com>
2078 * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
2079 type attribute.
2080 (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
2081 (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
2082 (movhi_internal, movqi_internal): Likewise.
2083 (movsf_softfloat, movsf_hardfloat): Likewise.
2084 (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
2085 (movdf_softfloat): Likewise.
2087 2024-03-01 Marek Polacek <polacek@redhat.com>
2089 PR c++/110358
2090 PR c++/109642
2091 * doc/extend.texi: Document gnu::no_dangling.
2092 * doc/invoke.texi: Mention that gnu::no_dangling disables
2093 -Wdangling-reference.
2095 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
2097 * config/avr/avr.opt: Overhaul help screen.
2099 2024-03-01 Jakub Jelinek <jakub@redhat.com>
2100 Tobias Burnus <tburnus@baylibre.com>
2102 PR c++/110347
2103 * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
2104 lang_hooks.decls.omp_disregard_value_expr for
2105 (first)private in target regions.
2107 2024-03-01 Jakub Jelinek <jakub@redhat.com>
2109 PR middle-end/114136
2110 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
2111 n_named_args initially before INIT_CUMULATIVE_ARGS to
2112 structure_value_addr_parm rather than 0, after it don't modify
2113 it if strict_argument_naming and clear only if
2114 !pretend_outgoing_varargs_named.
2116 2024-03-01 Jakub Jelinek <jakub@redhat.com>
2118 PR debug/114015
2119 * dwarf2out.cc (should_move_die_to_comdat): Return false for
2120 aggregates without DW_AT_byte_size attribute or with non-constant
2121 DW_AT_byte_size.
2123 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
2125 * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
2126 valid values for level.
2128 2024-03-01 Richard Biener <rguenther@suse.de>
2130 PR middle-end/114070
2131 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
2132 Allow the folding if before lowering and the current IL
2133 isn't supported with vcond_mask.
2135 2024-03-01 xuli <xuli1@eswincomputing.com>
2137 * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
2138 attribute to riscv_attribute_table.
2139 (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
2140 (riscv_fntype_abi): Add riscv_vector_cc attribute check.
2141 * doc/extend.texi: Add riscv_vector_cc attribute description.
2143 2024-03-01 Pan Li <pan2.li@intel.com>
2145 PR target/112817
2146 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
2147 RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
2148 * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
2149 (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
2150 * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
2151 comments for option replacement.
2152 * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
2153 riscv_autovec_preference to rvv_vector_bits.
2154 (vls_mode_valid_p): Ditto.
2155 (estimated_poly_value): Ditto.
2156 * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
2157 vector chunks and honor new option mrvv-vector-bits.
2158 (riscv_override_options_internal): Update comments and rename the
2159 vector chunks.
2160 * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
2161 internal option param=riscv-autovec-preference.
2163 2024-03-01 Jakub Jelinek <jakub@redhat.com>
2165 * function.cc (assign_parms): Only call assign_parms_setup_varargs
2166 early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
2168 2024-03-01 Jakub Jelinek <jakub@redhat.com>
2170 PR middle-end/114156
2171 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
2172 rhs1 of a VCE to have no underlying variable if it is a load and
2173 handle that case.
2175 2024-02-29 David Malcolm <dmalcolm@redhat.com>
2177 PR analyzer/114159
2178 * function.cc (function_name): Make param const.
2179 * function.h (function_name): Likewise.
2181 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
2183 PR target/114100
2184 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
2185 * config/avr/avr.opt (-mfuse-add=): New target option.
2186 * common/config/avr/avr-common.cc (avr_option_optimization_table)
2187 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
2188 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
2189 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
2190 * config/avr/avr-protos.h (avr_split_tiny_move)
2191 (make_avr_pass_fuse_add): New protos.
2192 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
2193 avr_split_tiny_move to split indirect memory accesses.
2194 (gen_move_clobbercc): New define_expand helper.
2195 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
2196 (avr_pass_fuse_add): New class from rtl_opt_pass.
2197 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
2198 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
2199 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
2200 of PLUS addressing for AVR_TINY.
2201 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
2202 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
2203 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
2205 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
2207 PR target/114132
2208 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
2209 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
2210 (avr_function_arg): Set it.
2211 (avr_frame_pointer_required_p): Use it instead of .nregs.
2213 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
2215 PR target/108174
2216 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
2217 static and mark with GTY.
2219 2024-02-29 Xi Ruoyao <xry111@xry111.site>
2221 * config/loongarch/loongarch.md
2222 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
2224 2024-02-29 Xi Ruoyao <xry111@xry111.site>
2226 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
2227 (crc): New define_int_attr.
2228 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
2229 into ...
2230 (loongarch_<crc>_w_<size>_w): ... here.
2232 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
2234 PR target/114130
2235 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
2236 extend the expected value if needed.
2238 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2240 * config.gcc (target_gtfiles): Change coreout to btfext-out.
2241 (extra_objs): Change coreout to btfext-out.
2242 * config/bpf/coreout.cc: Rename to btfext-out.cc.
2243 * config/bpf/btfext-out.cc: Add.
2244 * config/bpf/coreout.h: Rename to btfext-out.h.
2245 * config/bpf/btfext-out.h: Add.
2246 * config/bpf/core-builtins.cc: Change include.
2247 * config/bpf/core-builtins.h: Change include.
2248 * config/bpf/t-bpf: Accomodate renamed files.
2250 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2252 PR target/113453
2253 * config/bpf/bpf.cc (bpf_function_prologue): Define target
2254 hook.
2255 * config/bpf/coreout.cc (brf_ext_info_section)
2256 (btf_ext_info): Move from coreout.h
2257 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
2258 (bpf_core_reloc): Rename to btf_ext_core_reloc.
2259 (btf_ext): Add static variable.
2260 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
2261 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
2262 (btf_ext_add_string, btf_funcinfo_type_callback)
2263 (btf_add_func_info_for, btf_validate_funcinfo)
2264 (btf_ext_info_len, output_btfext_func_info): Add function.
2265 (output_btfext_header, bpf_core_reloc_add)
2266 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
2267 Change to support new structs.
2268 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
2269 Move and change in coreout.cc.
2270 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
2272 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2274 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
2275 enabled by default for BPF.
2276 (bpf_file_end): Call BTF deallocation.
2277 (bpf_asm_init_sections): Correct condition.
2278 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
2279 deallocation.
2280 (ctf_debuf_finish): Correct condition for calling
2281 ctf_debug_finalize.
2283 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2285 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
2286 (traverse_btf_func_types): Define function.
2287 * ctfc.h (funcs_traverse_callback): Typedef for function
2288 prototype.
2289 (traverse_btf_func_types): Add prototype.
2291 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2293 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
2295 2024-02-28 Richard Biener <rguenther@suse.de>
2297 PR tree-optimization/113831
2298 PR tree-optimization/108355
2299 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
2300 PR113831 fix.
2302 2024-02-28 Richard Biener <rguenther@suse.de>
2304 PR tree-optimization/114121
2305 * tree-ssa-sccvn.h (vn_reference_s::offset,
2306 vn_reference_s::max_size): New fields.
2307 (vn_reference_insert_pieces): Adjust prototype.
2308 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
2309 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
2310 size, allow using "don't know" state.
2311 (vn_walk_cb_data::finish): Pass along offset/max_size.
2312 (vn_reference_lookup_or_insert_for_pieces): Take offset and
2313 max_size as argument and use it.
2314 (vn_reference_lookup_3): Properly adjust offset and max_size
2315 according to the adjusted ao_ref.
2316 (vn_reference_lookup_pieces): Initialize offset and max_size.
2317 (vn_reference_lookup): Likewise.
2318 (vn_reference_lookup_call): Likewise.
2319 (vn_reference_insert): Likewise.
2320 (visit_reference_op_call): Likewise.
2321 (vn_reference_insert_pieces): Take offset and max_size
2322 as argument and use it.
2324 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
2326 PR tree-optimization/114075
2327 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
2328 point vectors
2330 2024-02-28 Jakub Jelinek <jakub@redhat.com>
2332 PR tree-optimization/114041
2333 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
2334 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
2336 2024-02-28 Jakub Jelinek <jakub@redhat.com>
2338 PR tree-optimization/113988
2339 * stor-layout.h (bitwise_mode_for_size): Declare.
2340 * stor-layout.cc (bitwise_mode_for_size): New function.
2341 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
2342 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
2343 Use BITS_PER_UNIT instead of 8.
2345 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
2347 PR target/113871
2348 * config/i386/mmx.md (V248FI): Add V2BF mode.
2349 (V24FI_32): Ditto.
2351 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
2353 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
2354 if either ref->offset is not byte aligned or ref->size is not known
2355 to be equal to ref->max_size.
2356 (maybe_trim_complex_store): Fix description.
2357 (maybe_trim_constructor_store): Likewise.
2358 (maybe_trim_partially_dead_store): Likewise.
2360 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
2362 * config/arm/mmintrin.h: Warn if this header is included without
2363 defining __ENABLE_DEPRECATED_IWMMXT.
2365 2024-02-27 Richard Biener <rguenther@suse.de>
2367 PR tree-optimization/114074
2368 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
2369 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
2370 Handle poly vs. non-poly multiplication correctly with respect
2371 to undefined behavior on overflow.
2373 2024-02-27 Jakub Jelinek <jakub@redhat.com>
2375 PR rtl-optimization/114044
2376 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
2377 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
2378 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
2379 expand_PARITY): Declare.
2380 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
2381 expand_CTZ, expand_FFS, expand_PARITY): New functions.
2382 (expand_POPCOUNT): Use expand_bitquery.
2384 2024-02-27 Richard Biener <rguenther@suse.de>
2386 PR tree-optimization/114081
2387 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2388 Perform manual dominator update for prologue peeling.
2389 (vect_do_peeling): Properly update dominators after adding the
2390 prologue-around guard.
2392 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
2394 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
2395 (mstrict-X): Tag as "Optimization".
2397 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
2399 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
2400 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
2402 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2403 H.J. Lu <hjl.tools@gmail.com>
2405 PR rtl-optimization/113617
2406 * varasm.cc (default_elf_select_rtx_section): For
2407 references to private symbols in comdat sections
2408 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
2409 or .rodata.<comdat> comdat sections.
2411 2024-02-26 Richard Biener <rguenther@suse.de>
2413 PR tree-optimization/114099
2414 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2415 Create and fill in a needed virtual LC PHI for the alternate
2416 exits. Remove code dealing with that missing.
2418 2024-02-26 Richard Biener <rguenther@suse.de>
2420 PR tree-optimization/114068
2421 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
2422 New function.
2423 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
2424 on the main exit if needed. Remove band-aid for the case
2425 it was missing.
2427 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
2429 PR target/114097
2430 * config/i386/i386-options.cc (ix86_set_func_type): Check
2431 interrupt instead of noreturn attribute.
2433 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2435 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
2436 !TARGET_64BIT.
2438 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2440 PR tree-optimization/114090
2441 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
2442 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
2443 types.
2444 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
2446 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2448 PR middle-end/114084
2449 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
2450 if all subtrees of var0 come from one of the op0 or op1 operands
2451 and all subtrees of con0 come from the other one. Don't clear
2452 variables which are never used afterwards.
2454 2024-02-26 Richard Biener <rguenther@suse.de>
2456 PR middle-end/114070
2457 * genmatch.cc (parser::parse_c_expr): Do not record operand
2458 lists but only mark operators used.
2459 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
2460 Properly guard the case of tcc_comparison changing the VEC_COND
2461 value operand type.
2463 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2465 PR target/114094
2466 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
2467 to printed instruction.
2469 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
2471 PR target/114098
2472 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
2473 __builtin_ia32_ldtilecfg.
2474 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
2475 * config/i386/i386-builtin.def (BDESC): Add
2476 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
2477 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
2478 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
2479 * config/i386/i386.md (ldtilecfg): New pattern.
2480 (sttilecfg): Likewise.
2482 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
2484 PR tree-optimization/113205
2485 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
2486 the proposed layout if it does not allow a source partition with
2487 layout 2 to keep that layout.
2489 2024-02-24 Jakub Jelinek <jakub@redhat.com>
2491 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
2492 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
2493 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
2494 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
2495 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
2496 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
2497 macros.
2498 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
2499 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
2500 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
2501 HOST_WIDE_INT_UC macros.
2502 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
2503 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
2504 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
2505 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
2506 macros.
2507 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
2508 * config/i386/constraints.md (define_constraint "L"): Use
2509 HOST_WIDE_INT_C macro.
2510 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
2511 macro.
2512 (movl + movb peephole2): Likewise.
2513 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
2514 (const_32bit_mask): Likewise.
2516 2024-02-24 Jakub Jelinek <jakub@redhat.com>
2518 PR middle-end/114073
2519 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
2520 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
2521 types like vector or complex types.
2522 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
2523 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
2524 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
2526 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
2528 PR target/114028
2529 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
2530 Return false if inner mode is already Pmode.
2531 (rvv_builder::is_all_same_sequence): New function.
2532 (expand_vec_init): Emit broadcast if sequence is all same.
2534 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2536 PR target/113613
2537 * config/aarch64/aarch64-early-ra.cc
2538 (early_ra::m_current_region): New member variable.
2539 (early_ra::m_fpr_recency): Likewise.
2540 (early_ra::start_new_region): Bump m_current_region.
2541 (early_ra::allocate_colors): Prefer less recently used registers
2542 in the event of a tie. Add a comment to explain why we prefer(ed)
2543 higher-numbered registers.
2544 (early_ra::find_oldest_color): Prefer less recently used registers
2545 here too.
2546 (early_ra::finalize_allocation): Update recency information for
2547 allocated registers.
2548 (early_ra::process_blocks): Initialize m_current_region and
2549 m_fpr_recency.
2551 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2553 PR target/113295
2554 * config/aarch64/aarch64-early-ra.cc
2555 (early_ra::test_strictness): New enum.
2556 (early_ra::is_chain_candidate): Add a strictness parameter to
2557 control whether only correctness matters, or whether both correctness
2558 and heuristics should be used. Handle multiple levels of equivalence.
2559 (early_ra::find_related_start): Update call accordingly.
2560 (early_ra::strided_polarity_pref): Likewise.
2561 (early_ra::form_chains): Likewise.
2562 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
2563 correctness mode rather than trying to inline the test.
2565 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2567 PR target/113295
2568 * config/aarch64/aarch64-early-ra.cc
2569 (early_ra::find_related_start): Account for definitions by shared
2570 registers when testing for a single register definition.
2571 (early_ra::accumulate_defs): New function.
2572 (early_ra::record_copy): If A shares B's register, fold A's
2573 definition information into B's. Fold A's use information into B's.
2575 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
2577 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
2578 if R_X86_64_CODE_6_GOTTPOFF is supported.
2579 * config.in: Regenerated.
2580 * configure: Likewise.
2581 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
2582 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
2584 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
2586 PR target/108120
2587 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
2588 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
2590 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2592 PR rtl-optimization/114054
2593 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
2594 temp variable instead of target parameter for result.
2596 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2598 PR tree-optimization/114040
2599 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
2600 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
2601 probability from likely to unlikely. When handling the true true
2602 store, first cast to limb_access_type and then to l's type.
2604 2024-02-23 Richard Biener <rguenther@suse.de>
2606 PR target/90785
2607 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
2609 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2611 PR other/109668
2612 * config/riscv/arch-canonicalize: Move to python3
2613 * config/riscv/multilib-generator: Likewise
2615 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2617 * doc/invoke.texi: Document -mcpu.
2619 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
2621 * configure: Regenerate.
2622 * configure.ac: Add parameter "--fatal-warnings" to assemble
2623 when checking whether the assemble support conditional branch
2624 relaxation.
2626 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2628 PR c/114007
2629 * doc/extend.texi: (__extension__): Remove comments about scope
2630 tokens vs. two colons.
2632 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
2634 PR tree-optimization/109804
2635 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
2636 DEMANGLE_COMPONENT_UNNAMED_TYPE.
2638 2024-02-22 Richard Biener <rguenther@suse.de>
2640 PR tree-optimization/114048
2641 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
2642 can also produce -1 off.
2644 2024-02-22 Richard Biener <rguenther@suse.de>
2646 PR tree-optimization/114027
2647 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
2648 condition reduction classification only for single-element
2649 chains.
2651 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2653 PR ipa/111960
2654 * profile-count.h (profile_count::dump): Remove overload with
2655 char * first argument.
2656 * profile-count.cc (profile_count::dump): Change overload with char *
2657 first argument which uses sprintf into the overfload with FILE *
2658 first argument and use fprintf instead. Remove overload which wrapped
2659 it.
2661 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2663 PR tree-optimization/113993
2664 * tree-call-cdce.cc (get_no_error_domain): Handle
2665 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
2666 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
2667 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2668 the as the F128 suffixed cases, otherwise as non-suffixed ones.
2669 Handle BUILT_IN_{EXP,POW}10L for
2670 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2671 as (-inf, 4932).
2673 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2675 PR tree-optimization/114038
2676 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
2677 loop exit condition if end is divisible by limb_prec.
2679 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
2681 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
2682 problem of mabi=, mno-flush-func, mexplicit-relocs;
2683 add missing leading - of mbranch-cost option.
2684 * config/mips/mips.opt.urls: Regenerate.
2686 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
2688 PR target/109987
2689 * config/rs6000/constraints.md (we): Update internal doc without
2690 referring to option -mpower9-vector.
2691 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
2692 special handlings.
2693 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
2694 OTHER_P8_VECTOR_MASKS): Merge to ...
2695 (OTHER_VSX_VECTOR_MASKS): ... here.
2696 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
2697 some error message handlings and explicit option mask adjustments on
2698 explicit option power{8,9}-vector conflicting with other options.
2699 (rs6000_print_isa_options): Update comments.
2700 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
2701 related array items and handlings.
2702 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
2703 special handlings.
2704 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
2705 WarnRemoved.
2706 * doc/extend.texi: Remove documentation referring to option
2707 -mpower8-vector.
2708 * doc/invoke.texi: Remove documentation for option
2709 -mpower{8,9}-vector and adjust some documentation referring to them.
2710 * doc/md.texi: Update documentation for constraint we.
2711 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
2713 2024-02-22 Pan Li <pan2.li@intel.com>
2715 PR target/114017
2716 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
2717 the version to 0.12.
2719 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2721 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
2723 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2724 Robin Dapp <rdapp.gcc@gmail.com>
2726 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2727 (generic_ooo_vec_load): Ditto
2728 (generic_ooo_vec_store): Ditto
2729 (generic_ooo_vec_loadstore_seg): Ditto
2730 (generic_ooo_vec_alu): Ditto
2731 (generic_ooo_vec_fcmp): Ditto
2732 (generic_ooo_vec_imul): Ditto
2733 (generic_ooo_vec_fadd): Ditto
2734 (generic_ooo_vec_fmul): Ditto
2735 (generic_ooo_crypto): Ditto
2736 (generic_ooo_perm): Ditto
2737 (generic_ooo_vec_reduction): Ditto
2738 (generic_ooo_vec_ordered_reduction): Ditto
2739 (generic_ooo_vec_idiv): Ditto
2740 (generic_ooo_vec_float_divsqrt): Ditto
2741 (generic_ooo_vec_mask): Ditto
2742 (generic_ooo_vec_vesetvl): Ditto
2743 (generic_ooo_vec_setrm): Ditto
2744 (generic_ooo_vec_readlen): Ditto
2745 * config/riscv/riscv.md: Include generic-vector-ooo
2746 * config/riscv/generic-vector-ooo.md: New file. To here
2748 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2750 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2751 (generic_ooo_branch): Ditto
2752 * config/riscv/generic.md (generic_sfb_alu): Ditto
2753 (generic_fmul_half): Ditto
2754 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2755 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
2756 (sifive_7_popcount): Ditto
2757 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
2758 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
2759 * config/riscv/vector.md: Change rdfrm to fmove
2760 * config/riscv/zc.md: Change pushpop to load/store
2762 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
2764 * doc/invoke.texi (Warning Options): Fix typos.
2766 2024-02-21 David Faust <david.faust@oracle.com>
2768 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
2769 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
2770 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
2772 2024-02-21 Martin Jambor <mjambor@suse.cz>
2774 PR ipa/113476
2775 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
2776 initializers in the contructor.
2777 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
2778 * ipa-cp.h: New file.
2779 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
2780 (ipcp_value_source): Move to ipa-cp.h.
2781 (ipcp_value_base): Likewise.
2782 (ipcp_value): Likewise.
2783 (ipcp_lattice): Likewise.
2784 (ipcp_agg_lattice): Likewise.
2785 (ipcp_bits_lattice): Likewise.
2786 (ipcp_vr_lattice): Likewise.
2787 (ipcp_param_lattices): Likewise.
2788 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
2789 (ipa_value_from_jfunc): Adjust a check for empty lattices.
2790 (ipa_context_from_jfunc): Likewise.
2791 (ipa_agg_value_from_jfunc): Likewise.
2792 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
2793 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
2794 just in contiguous memory.
2795 (ipcp_store_vr_results): Adjust a check for empty lattices.
2796 * auto-profile.cc: Include sreal.h and ipa-cp.h.
2797 * cgraph.cc: Likewise.
2798 * cgraphclones.cc: Likewise.
2799 * cgraphunit.cc: Likewise.
2800 * config/aarch64/aarch64.cc: Likewise.
2801 * config/i386/i386-builtins.cc: Likewise.
2802 * config/i386/i386-expand.cc: Likewise.
2803 * config/i386/i386-features.cc: Likewise.
2804 * config/i386/i386-options.cc: Likewise.
2805 * config/i386/i386.cc: Likewise.
2806 * config/rs6000/rs6000.cc: Likewise.
2807 * config/s390/s390.cc: Likewise.
2808 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
2809 files to be included in gtype-desc.cc.
2810 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
2811 * ipa-devirt.cc: Likewise.
2812 * ipa-fnsummary.cc: Likewise.
2813 * ipa-icf.cc: Likewise.
2814 * ipa-inline-analysis.cc: Likewise.
2815 * ipa-inline-transform.cc: Likewise.
2816 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
2817 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
2818 * ipa-param-manipulation.cc: Likewise.
2819 * ipa-predicate.cc: Likewise.
2820 * ipa-profile.cc: Likewise.
2821 * ipa-prop.cc: Likewise.
2822 (ipa_node_params_t::duplicate): Assert new lattices remain empty
2823 instead of setting them to NULL.
2824 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
2825 * ipa-split.cc: Likewise.
2826 * ipa-sra.cc: Likewise.
2827 * ipa-strub.cc: Likewise.
2828 * ipa-utils.cc: Likewise.
2829 * ipa.cc: Likewise.
2830 * toplev.cc: Likewise.
2831 * tree-ssa-ccp.cc: Likewise.
2832 * tree-ssa-sccvn.cc: Likewise.
2833 * tree-vrp.cc: Likewise.
2835 2024-02-21 Tamar Christina <tamar.christina@arm.com>
2837 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
2838 Armv8.7-a.
2840 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2842 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2843 Use aarch64_gen_compare_zero_and_branch rather than emitting
2844 a CBZ directly.
2846 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2848 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
2849 Remove duplicated call.
2851 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2853 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
2854 Check that each individual piece of state is shared in the same
2855 way, rather than using an aggregate check for PSTATE.ZA.
2857 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2859 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2860 In the code that commits a lazy save, only zero ZA if the function
2861 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
2863 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2865 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
2866 directly inserting the associated sequence
2867 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2868 ...here instead.
2870 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2872 PR target/113995
2873 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
2874 fold the SVE allocation into the initial allocation if the
2875 initial allocation includes a VG save.
2877 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2879 PR target/113220
2880 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
2881 contain jumps even if called after initial RTL expansion.
2882 * mode-switching.cc: Include cfgbuild.h.
2883 (optimize_mode_switching): Allow the sequence returned by the
2884 emit hook to contain internal jumps. Record which blocks
2885 contain such jumps and split the blocks at the end.
2886 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
2887 non-debug insns when scanning the sequence.
2889 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
2891 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
2892 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
2894 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2896 * doc/invoke.texi (-mmcu): Add information about MCU specs.
2898 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2900 * doc/invoke.texi (-minrt): Clarify that main
2901 must take no arguments.
2903 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2905 * config/avr/builtins.def: Use function prototypes of given size
2906 and signedness.
2907 * config/avr/avr.cc (avr_init_builtins): Adjust types required
2908 by builtins.def.
2909 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
2911 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2913 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
2914 instead of @table.
2916 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
2918 * config/bpf/bpf.opt: Add help information for -mcpu.
2920 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
2922 PR target/113805
2923 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
2924 New pass.
2925 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
2926 Declare.
2927 * config/aarch64/aarch64.md (is_call): New attribute.
2928 (*and<mode>3nr_compare0): Rename to...
2929 (@aarch64_and<mode>3nr_compare0): ...this.
2930 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
2931 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
2932 * config/aarch64/aarch64-speculation.cc: Update file comment to
2933 describe the new late pass.
2934 (aarch64_do_track_speculation): Handle is_call insns like other calls.
2935 (pass_track_speculation): Add an is_late member variable.
2936 (pass_track_speculation::gate): Run the late pass for streaming-
2937 compatible functions and the early pass for other functions.
2938 (make_pass_track_speculation): Update accordingly.
2939 (make_pass_late_track_speculation): New function.
2940 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
2941 function.
2942 (aarch64_guard_switch_pstate_sm): Use it.
2944 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
2946 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
2947 Register these builtins with a pointer to uint64_t rather than unsigned
2948 DI mode.
2950 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2952 PR target/113615
2953 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
2954 Conditionalize on '!TARGET_RDNA2_PLUS'.
2955 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
2956 (gcn_expand_reduc_scalar):
2957 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
2959 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2961 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
2962 '__gfx90a__' target CPU definition. Add some safeguards for the future.
2964 2024-02-19 Richard Biener <rguenther@suse.de>
2966 PR rtl-optimization/54052
2967 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
2968 local defs by LR_OUT.
2970 2024-02-19 Jakub Jelinek <jakub@redhat.com>
2972 PR tree-optimization/113967
2973 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
2974 in condition that @rpos is multiple of vector element size.
2976 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2978 PR target/113696
2979 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
2980 Suppress vsetvl fusion.
2982 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
2984 PR target/113912
2985 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
2986 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
2987 (ix86_emit_save_regs): Don't generate push2 if
2988 ix86_can_use_push2pop2 return false.
2989 (ix86_expand_epilogue): Don't generate pop2 if
2990 ix86_can_use_push2pop2 return false.
2992 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2994 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
2995 Note on complete device support.
2997 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2999 * doc/extend.texi (AVR Function Attributes): Fuse description
3000 of "signal" and "interrupt" attribute. Link pseudo instruction.
3002 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
3004 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
3005 symbol type conversions.
3006 (__cacop_d): Likewise.
3007 (__cpucfg): Likewise.
3008 (__asrtle_d): Likewise.
3009 (__asrtgt_d): Likewise.
3010 (__lddir_d): Likewise.
3011 (__ldpte_d): Likewise.
3012 (__crc_w_b_w): Likewise.
3013 (__crc_w_h_w): Likewise.
3014 (__crc_w_w_w): Likewise.
3015 (__crc_w_d_w): Likewise.
3016 (__crcc_w_b_w): Likewise.
3017 (__crcc_w_h_w): Likewise.
3018 (__crcc_w_w_w): Likewise.
3019 (__crcc_w_d_w): Likewise.
3020 (__csrrd_w): Likewise.
3021 (__csrwr_w): Likewise.
3022 (__csrxchg_w): Likewise.
3023 (__csrrd_d): Likewise.
3024 (__csrwr_d): Likewise.
3025 (__csrxchg_d): Likewise.
3026 (__iocsrrd_b): Likewise.
3027 (__iocsrrd_h): Likewise.
3028 (__iocsrrd_w): Likewise.
3029 (__iocsrrd_d): Likewise.
3030 (__iocsrwr_b): Likewise.
3031 (__iocsrwr_h): Likewise.
3032 (__iocsrwr_w): Likewise.
3033 (__iocsrwr_d): Likewise.
3034 (__frecipe_s): Likewise.
3035 (__frecipe_d): Likewise.
3036 (__frsqrte_s): Likewise.
3037 (__frsqrte_d): Likewise.
3039 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
3041 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
3042 function return value type to unsigned short.
3044 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
3046 * doc/sourcebuild.texi: add scan-assembler-bound
3048 2024-02-16 Jason Merrill <jason@redhat.com>
3050 * gdbhooks.py: Fix regex syntax.
3052 2024-02-16 Richard Biener <rguenther@suse.de>
3054 PR tree-optimization/113895
3055 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
3056 consistency checking when there are out-of-bound array
3057 accesses. Allow -1 off when from an array reference with
3058 constant index.
3060 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
3062 PR target/106543
3063 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
3064 pattern.
3066 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3068 * doc/sourcebuild.texi (Effective-Target Keywords, Other
3069 attribugs): Document linker_plugin.
3070 (Require Support): Document dg-require-linker-plugin.
3072 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
3074 PR target/109349
3075 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
3076 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
3077 (RISCV_MINOR_VERSION_BASE): Ditto.
3078 (RISCV_REVISION_VERSION_BASE): Ditto.
3079 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
3080 rather than magic number.
3081 * config/riscv/riscv.h (riscv_arch_help): New.
3082 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
3083 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
3084 --print-supported-extensions.
3085 * config/riscv/riscv.opt (march=help): New.
3086 (print-supported-extensions): New.
3087 (-print-supported-extensions): New.
3088 * doc/invoke.texi (RISC-V Options): Document -march=help.
3090 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
3092 PR target/113780
3093 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
3094 for indirect calls with 4 or more arguments in pac-enabled functions.
3096 2024-02-15 David Faust <david.faust@oracle.com>
3098 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
3099 use ldxb instead of ldxh.
3101 2024-02-15 Jakub Jelinek <jakub@redhat.com>
3103 PR middle-end/113921
3104 * cfgrtl.h (prepend_insn_to_edge): New declaration.
3105 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
3106 comment.
3107 (prepend_insn_to_edge): New function.
3108 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
3109 insert_insn_on_edge.
3111 2024-02-15 Richard Biener <rguenther@suse.de>
3113 PR tree-optimization/111156
3114 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
3115 at the pattern stmt if any.
3117 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
3119 PR target/113927
3120 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
3121 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
3122 * config/avr/avr.cc (avr_adiw_reg_p): New function.
3123 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
3124 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
3125 * config/avr/avr.md: Same.
3126 (attr "isa") <tiny, no_tiny>: Remove.
3127 <adiw, no_adiw>: Add.
3128 (define_insn, define_insn_and_split): When an alternative has
3129 constraint "w", then set attribute "isa" to "adiw".
3130 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
3131 Built-in define __AVR_HAVE_ADIW__.
3132 * doc/invoke.texi (AVR Options): Document it.
3134 2024-02-15 Andrew Stubbs <ams@baylibre.com>
3136 * config/gcn/gcn-valu.md
3137 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
3138 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
3139 details are supported on RDNA devices.
3141 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
3143 PR middle-end/113508
3144 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
3145 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
3146 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
3147 Add sentence about what the mode m is.
3149 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
3151 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
3152 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
3153 var.
3155 2024-02-15 Richard Biener <rguenther@suse.de>
3157 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
3158 stmts.
3160 2024-02-15 Jakub Jelinek <jakub@redhat.com>
3162 PR tree-optimization/113567
3163 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
3164 _BitInt multiplication, division or modulo with
3165 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
3166 force the affected inputs into a new SSA_NAME.
3168 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
3170 PR target/113871
3171 * config/i386/mmx.md (V248FI): New mode iterator.
3172 (V24FI_32): DItto.
3173 (vec_shl_<V248FI:mode>): New expander.
3174 (vec_shl_<V24FI_32:mode>): Ditto.
3175 (vec_shr_<V248FI:mode>): Ditto.
3176 (vec_shr_<V24FI_32:mode>): Ditto.
3177 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
3178 (vec_shr_<V248FI:mode>): Ditto.
3180 2024-02-14 Jan Hubicka <jh@suse.cz>
3182 PR tree-optimization/111054
3183 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
3185 2024-02-14 Tamar Christina <tamar.christina@arm.com>
3187 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
3189 2024-02-14 Richard Biener <rguenther@suse.de>
3191 PR tree-optimization/113910
3192 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
3193 the hashval_t hash.
3195 2024-02-14 Jakub Jelinek <jakub@redhat.com>
3197 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
3198 (pp_integer_with_precision): For unsigned ptrdiff_t printing
3199 with u, o or x print ptrdiff_t argument converted to
3200 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
3202 2024-02-14 Richard Biener <rguenther@suse.de>
3204 PR middle-end/113576
3205 * expr.cc (do_store_flag): For vector bool compares of vectors
3206 with padding zero that.
3207 * dojump.cc (do_compare_and_jump): Likewise.
3209 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
3211 * doc/install.texi (Prerequisites): Update gettext link.
3213 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
3215 PR target/113876
3216 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
3217 Return false if the incoming stack isn't 16-byte aligned.
3219 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
3221 PR middle-end/113904
3222 * omp-general.cc (struct omp_ts_info): Update for splitting of
3223 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
3224 * omp-selectors.h (enum omp_tp_type): Replace
3225 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
3227 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
3229 PR target/113742
3230 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
3231 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
3233 2024-02-13 Richard Biener <rguenther@suse.de>
3235 PR tree-optimization/113895
3236 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
3237 offset to discover constant array indices in bits, handle
3238 COMPONENT_REF to bitfields.
3240 2024-02-13 Richard Biener <rguenther@suse.de>
3242 PR tree-optimization/113831
3243 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
3244 typo in comment.
3246 2024-02-13 Richard Biener <rguenther@suse.de>
3248 PR tree-optimization/113902
3249 * tree-vect-loop.cc (move_early_exit_stmts): Track
3250 last_seen_vuse for VUSE updating.
3252 2024-02-13 Tamar Christina <tamar.christina@arm.com>
3254 PR tree-optimization/113734
3255 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
3256 an early break loop as partial.
3258 2024-02-13 Richard Biener <rguenther@suse.de>
3260 PR tree-optimization/113898
3261 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
3262 missing accumulated off adjustment.
3264 2024-02-13 Jakub Jelinek <jakub@redhat.com>
3266 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
3267 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
3268 it against UINT_MAX and ULONG_MAX.
3270 2024-02-13 David Malcolm <dmalcolm@redhat.com>
3272 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
3273 to...
3274 (emit_diagnostic_valist_meta): ...this.
3275 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
3276 (emit_diagnostic_valist_meta): ...this.
3278 2024-02-12 Jakub Jelinek <jakub@redhat.com>
3280 PR tree-optimization/113849
3281 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
3282 fast path for widening casts where !m_upwards_2limb and lhs_type
3283 has precision which is a multiple of limb_prec.
3285 2024-02-12 Jakub Jelinek <jakub@redhat.com>
3287 PR c++/113674
3288 * attribs.cc (extract_attribute_substring): Remove.
3289 (lookup_scoped_attribute_spec): Don't call it.
3291 2024-02-12 Jakub Jelinek <jakub@redhat.com>
3293 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
3294 and cast to fmt_size_t instead of %lu and cast to unsigned long.
3296 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
3298 * Makefile.in: Add no-info dependency.
3299 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
3300 available.
3301 * configure: Regenerate.
3303 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
3305 PR target/113855
3306 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
3307 available to all sub-targets.
3308 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
3309 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
3311 2024-02-12 Richard Biener <rguenther@suse.de>
3313 PR tree-optimization/113831
3314 PR tree-optimization/108355
3315 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
3316 we see variable array indices and get_ref_base_and_extent
3317 can resolve those to constants fix up the ops to constants
3318 as well.
3319 (ao_ref_init_from_vn_reference): Use 'off' member for
3320 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
3321 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
3323 2024-02-12 Pan Li <pan2.li@intel.com>
3325 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
3326 Replace args to arguments for misspelled term.
3328 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
3330 PR target/112944
3331 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
3332 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
3333 when not linked with -mrodata-in-ram.
3335 2024-02-12 Richard Biener <rguenther@suse.de>
3337 PR tree-optimization/113863
3338 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3339 Record crossed virtual PHIs.
3340 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
3341 virtual PHIs.
3343 2024-02-10 Marek Polacek <polacek@redhat.com>
3345 DR 2237
3346 PR c++/107126
3347 PR c++/97202
3348 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
3350 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3352 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
3353 computation of idx for i == 4 of bitint_prec_huge.
3355 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3357 PR middle-end/110754
3358 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
3359 decls create PARM_DECL with pointer to original type, set
3360 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
3361 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
3362 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
3363 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
3364 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
3365 of the var as argument.
3367 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3369 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
3370 size_t and precision 4 for ptrdiff_t. Formatting fix.
3371 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
3372 Formatting fixes.
3373 (test_pp_format): Test t and z modifiers.
3374 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
3376 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3378 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
3379 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
3380 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
3381 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
3382 and casts to fmt_size_t instead of "%ld" and casts to long.
3383 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
3384 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
3385 instead of "%lu" and casts to unsigned long.
3386 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
3387 unsigned long.
3388 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
3389 and casts to fmt_size_t instead of "%ld" and casts to long.
3390 * cfgexpand.cc (dump_stack_var_partition): Use
3391 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
3392 and casts to unsigned long.
3393 * gengtype.cc (adjust_field_rtx_def): Likewise.
3394 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
3395 and casts to fmt_size_t instead of "%ld" and casts to long.
3396 * postreload-gcse.cc (dump_hash_table): Likewise.
3397 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
3398 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
3399 (ggc_internal_alloc, ggc_free): Likewise.
3400 * genpreds.cc (write_lookup_constraint_1): Likewise.
3401 (write_insn_constraint_len): Likewise.
3402 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
3403 and casts to fmt_size_t instead of "%ld" and casts to long.
3404 * varasm.cc (output_constant_pool_contents): Use
3405 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
3406 * var-tracking.cc (dump_var): Likewise.
3408 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3410 PR tree-optimization/113783
3411 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
3412 through VIEW_CONVERT_EXPR for final cast checks. Handle
3413 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
3414 INTEGER_TYPEs.
3415 (gimple_lower_bitint): Don't merge mergeable operations or other
3416 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
3417 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
3418 mode is BLKmode.
3420 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3422 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
3423 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
3424 HOST_SIZE_T_PRINT_HEX_PURE): Define.
3425 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
3426 fixes.
3428 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3430 PR middle-end/113415
3431 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
3432 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
3433 of hand written loop with emit_insn of copy_insn and emit original
3434 after_rtl_seq on the last edge.
3436 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3438 PR tree-optimization/113818
3439 * gimple-lower-bitint.cc (add_eh_edge): New function.
3440 (bitint_large_huge::handle_load,
3441 bitint_large_huge::lower_mergeable_stmt,
3442 bitint_large_huge::lower_muldiv_stmt): Use it.
3444 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3446 PR tree-optimization/113774
3447 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
3448 emit any comparison if m_first and low + 1 is equal to
3449 m_upwards_2limb, simplify condition for that. If not
3450 single_comparison, not m_first and we can prove that the idx <= low
3451 comparison will be always true, emit instead of idx <= low
3452 comparison low <= low such that cfg cleanup will optimize it at
3453 the end of the pass.
3455 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
3457 PR tree-optimization/113735
3458 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
3459 limit_check().
3461 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3463 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
3464 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
3466 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
3468 PR target/113711
3469 PR target/113733
3470 * config/i386/constraints.md: List all constraints with j prefix.
3471 (j>): Change auto-dec to auto-inc in documentation.
3472 (je): Changed to a memory constraint with APX NDD TLS operand
3473 check.
3474 (jM): New memory constraint for APX NDD instructions.
3475 (jO): Likewise.
3476 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
3477 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
3478 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
3479 (*add<mode>_1[SWI48]): Use je and jM.
3480 (addsi_1_zext): Use jM.
3481 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
3482 (*sub<mode>_1[SWI]): Use jM.
3483 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
3484 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
3485 (*and<dwi>3_doubleword): Likewise.
3486 (*anddi_1): Use jM.
3487 (*andsi_1_zext): Likewise.
3488 (*and<mode>_1[SWI24]): Likewise.
3489 (*<code><dwi>3_doubleword[any_or]): Use rjO
3490 (*code<mode>_1[any_or SWI248]): Use jM.
3491 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
3492 * config/i386/predicates.md (apx_ndd_memory_operand): New.
3493 (apx_ndd_add_memory_operand): Likewise.
3495 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3497 PR target/113824
3498 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
3499 * doc/avr-mmcu.texi: Rebuild.
3501 2024-02-08 Tamar Christina <tamar.christina@arm.com>
3503 PR tree-optimization/113808
3504 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
3505 value cross iterations.
3507 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3509 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
3510 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
3512 2024-02-08 Richard Biener <rguenther@suse.de>
3514 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3515 Revert last change to dr_may_alias_p.
3517 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3519 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
3520 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
3521 Remove spec asm_misc.
3522 * config/avr/specs.h: Same.
3524 2024-02-08 Pan Li <pan2.li@intel.com>
3526 PR target/113766
3527 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
3528 sure the c.arg_num is >= 2 before checking.
3529 (struct build_frm_base): Ditto.
3530 (struct narrow_alu_def): Ditto.
3532 2024-02-07 Richard Biener <rguenther@suse.de>
3534 PR tree-optimization/113796
3535 * tree-if-conv.cc (combine_blocks): Wipe range-info before
3536 replacing PHIs and inserting predicates.
3538 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
3539 Uros Bizjak <ubizjak@gmail.com>
3541 PR target/113690
3542 * config/i386/i386-features.cc (timode_convert_cst): New helper
3543 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
3544 CONST_VECTOR.
3545 (timode_scalar_chain::convert_op): Use timode_convert_cst.
3546 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
3547 Use timode_convert_cst.
3549 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
3551 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
3552 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
3553 (AARCH64_FL_DEBUGv8p9): Likewise.
3554 (AARCH64_FL_FGT2): Likewise.Likewise.
3555 (AARCH64_FL_ITE): Likewise.
3556 (AARCH64_FL_PFAR): Likewise.
3557 (AARCH64_FL_PMUv3_ICNTR): Likewise.
3558 (AARCH64_FL_PMUv3_SS): Likewise.
3559 (AARCH64_FL_PMUv3p9): Likewise.
3560 (AARCH64_FL_RASv2): Likewise.
3561 (AARCH64_FL_S1PIE): Likewise.
3562 (AARCH64_FL_S1POE): Likewise.
3563 (AARCH64_FL_S2PIE): Likewise.
3564 (AARCH64_FL_S2POE): Likewise.
3565 (AARCH64_FL_SCTLR2): Likewise.
3566 (AARCH64_FL_SEBEP): Likewise.
3567 (AARCH64_FL_SPE_FDS): Likewise.
3568 (AARCH64_FL_TCR2): Likewise.
3570 2024-02-07 Richard Biener <rguenther@suse.de>
3572 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3573 Only check whether reads are in-bound in places that are not safe.
3574 Fix dependence check. Add missing newline. Clarify comments.
3576 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3578 PR tree-optimization/113750
3579 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
3580 for single predecessor when doing early break vect.
3581 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
3582 after labels.
3584 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3586 PR tree-optimization/113731
3587 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
3588 method.
3589 * gimple-iterator.h (gsi_move_before): Default new param to
3590 GSI_SAME_STMT.
3591 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
3592 GSI_NEW_STMT.
3594 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3596 PR tree-optimization/113756
3597 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
3598 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
3599 of lh_bits value and mask.
3601 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3603 PR tree-optimization/113753
3604 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
3605 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
3606 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
3607 so that they start with r[half_blocks_needed] lowest bit. Fix up
3608 computation of top mask for SIGNED.
3610 2024-02-07 Pan Li <pan2.li@intel.com>
3612 PR target/113766
3613 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
3614 the signature of func.
3615 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
3616 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
3617 overloaded func with empty args error.
3619 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
3621 PR target/113689
3622 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
3623 R10_REG after sorry.
3625 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
3627 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
3628 Move before new caller, and add ".default" suffix.
3629 (get_suffixed_assembler_name): New.
3630 (make_resolver_func): Use get_suffixed_assembler_name.
3631 (aarch64_generate_version_dispatcher_body): Redo name mangling.
3633 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3635 PR target/113763
3636 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
3637 element from std::pair<unsigned int, char> to an unnamed struct.
3638 Adjust uses of tile range variable.
3640 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3642 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
3643 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
3645 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3647 PR sanitizer/110676
3648 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
3649 reset maxlen to sizetype maximum.
3651 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3653 PR tree-optimization/113736
3654 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
3655 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
3657 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3659 PR tree-optimization/113759
3660 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
3661 or from_unsignedN differs from properties of typeN, update typeN
3662 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
3663 uselessly convertible to typeN, convert it using fold_convert or
3664 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
3665 (convert_plusminus_to_widen): Likewise.
3667 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
3669 PR target/112577
3670 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
3671 vector structure modes correctly.
3673 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
3675 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
3676 warning.
3678 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
3680 PR target/113689
3681 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
3682 (x86_function_profiler): Call x86_64_select_profile_regnum to
3683 get a scratch register for large model profiling.
3685 2024-02-05 Richard Ball <richard.ball@arm.com>
3687 * config/arm/arm.cc (arm_output_mi_thunk): Emit
3688 insn for bti_c when bti is enabled.
3690 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3692 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
3693 neg.
3695 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3697 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
3698 (neg<mode>2): Change the mode iterator from MSA to IMSA because
3699 in FP arithmetic we cannot use (0 - x) for -x.
3700 (neg<mode>2): New define_insn to implement FP vector negation,
3701 using a bnegi instruction to negate the sign bit.
3703 2024-02-05 Richard Biener <rguenther@suse.de>
3705 PR tree-optimization/113707
3706 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
3707 checking the avail set treat out-of-region defines as
3708 available.
3710 2024-02-05 Richard Biener <rguenther@suse.de>
3712 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
3713 the default mode when building a pointer.
3715 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3717 PR tree-optimization/113737
3718 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
3719 has just a single label, remove it and make single successor edge
3720 EDGE_FALLTHRU.
3722 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3724 PR target/113059
3725 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
3726 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
3727 df_analyze call.
3729 2024-02-05 Richard Biener <rguenther@suse.de>
3731 PR target/113255
3732 * config/i386/i386-expand.cc
3733 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
3734 Use a new pseudo for the skipped number of bytes.
3736 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3738 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
3739 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
3740 sifive-p670.
3742 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3744 * config/riscv/riscv.md: Include sifive-p400.md.
3745 * config/riscv/sifive-p400.md: New file.
3746 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3747 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3748 Add sifive_p400.
3749 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
3750 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3751 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
3753 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3755 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
3756 Add missing ":SI" to the match_operator.
3758 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3760 * config/xtensa/xtensa.md (SHI): New mode iterator.
3761 (2 split patterns related to constsynth):
3762 Change to also accept HImode operands.
3764 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
3766 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
3767 similarly.
3769 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3771 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
3772 incorrect expand.
3773 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
3774 (elmsgnbit): Likewise.
3775 (neg<mode:FVEC>2): New define_insn.
3776 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
3777 are now instantiated in simd.md.
3779 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3781 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
3782 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
3783 MAX_MACHINE_MODE.
3785 2024-02-04 Li Wei <liwei@loongson.cn>
3787 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
3788 (loongarch_expand_vselect_vconcat): Ditto.
3789 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
3790 all 128-bit constant permutation situations.
3791 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
3792 (loongarch_is_imm_set_shuffle): Renamed function name.
3793 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
3794 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
3795 extract-even and extract-odd permutations.
3796 (loongarch_is_odd_extraction): Delete.
3797 (loongarch_is_even_extraction): Ditto.
3798 (loongarch_expand_vec_perm_const): Adjust.
3800 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3802 PR middle-end/113722
3803 * wide-int.cc (wi::bswap_large): Rename third argument from
3804 len to xlen and adjust use in safe_uhwi. Add len variable, set
3805 it to BLOCKS_NEEDED (precision) and use it for clearing of val
3806 and as canonize argument. Clear val using memset instead of
3807 a loop.
3809 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3811 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
3812 mmi.preferred_base + mmi.size - sizeof (void *).
3814 2024-02-03 Xi Ruoyao <xry111@xry111.site>
3816 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
3817 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
3818 the ODR-violating locale declaration.
3820 2024-02-02 Tamar Christina <tamar.christina@arm.com>
3822 PR tree-optimization/113588
3823 PR tree-optimization/113467
3824 * tree-vect-data-refs.cc
3825 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
3826 (vect_analyze_early_break_dependences): Update comments.
3828 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
3830 PR target/59778
3831 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
3832 and PA_BUILTIN_SET_FPSR builtins.
3833 * (pa_builtins_icode): Declare.
3834 * (def_builtin, pa_fpu_init_builtins): New.
3835 * (pa_init_builtins): Initialize FPU builtins.
3836 * (pa_builtin_decl, pa_expand_builtin_1): New.
3837 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
3838 PA_BUILTIN_SET_FPSR builtins.
3839 * (pa_atomic_assign_expand_fenv): New.
3840 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
3841 UNSPECV constants.
3842 (get_fpsr, put_fpsr): New expanders.
3843 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
3844 insn patterns.
3846 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3848 PR target/113697
3849 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
3851 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
3853 * doc/extend.texi (Common Type Attributes): Fix typo in
3854 description of hardbool.
3856 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3858 PR tree-optimization/113692
3859 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
3860 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
3861 final_cast_p.
3863 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3865 PR middle-end/113699
3866 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
3867 uninitialized large/huge _BitInt SSA_NAME inputs.
3869 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3871 PR middle-end/113705
3872 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
3873 around wi::to_wide in order to compare value in prec precision.
3875 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
3877 Revert:
3878 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3880 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3882 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3884 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3886 2024-02-02 Pan Li <pan2.li@intel.com>
3888 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
3889 (riscv_pass_by_reference): Ditto.
3890 (riscv_fntype_abi): Ditto.
3892 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3894 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
3895 (pre_vsetvl::cleaup): Remove vsetvl_pre.
3896 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
3898 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
3900 * config/loongarch/larchintrin.h
3901 (__frecipe_s): Update function return type.
3902 (__frecipe_d): Ditto.
3903 (__frsqrte_s): Ditto.
3904 (__frsqrte_d): Ditto.
3906 2024-02-02 Li Wei <liwei@loongson.cn>
3908 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
3909 (loongarch_vector_costs::add_stmt_cost): Adjust.
3911 2024-02-02 Xi Ruoyao <xry111@xry111.site>
3913 * config/loongarch/loongarch.md (unspec): Add
3914 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
3915 (la_pcrel64_two_parts): New define_insn.
3916 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
3917 typo in the comment.
3918 (loongarch_call_tls_get_addr): If -mcmodel=extreme
3919 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
3920 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
3921 note to allow CSE addressing __tls_get_addr.
3922 (loongarch_legitimize_tls_address): If -mcmodel=extreme
3923 -mexplicit-relocs={always,auto}, address TLS IE symbols with
3924 la_pcrel64_two_parts.
3925 (loongarch_split_symbol): If -mcmodel=extreme
3926 -mexplicit-relocs={always,auto}, address symbols with
3927 la_pcrel64_two_parts.
3928 (loongarch_output_mi_thunk): Clean up unreachable code. If
3929 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
3930 thunks with la_pcrel64_two_parts.
3932 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3934 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
3935 Add support for call36.
3937 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3939 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3940 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
3941 the macro instruction loading symbol address is not applicable.
3942 (loongarch_call_tls_get_addr): Adjust code.
3943 (loongarch_legitimize_tls_address): Likewise.
3945 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3947 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
3948 Add function declaration.
3949 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3950 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
3951 is not allowed
3952 (loongarch_load_tls): Added macro support in extreme mode.
3953 (loongarch_call_tls_get_addr): Likewise.
3954 (loongarch_legitimize_tls_address): Likewise.
3955 (loongarch_force_address): Likewise.
3956 (loongarch_legitimize_move): Likewise.
3957 (loongarch_output_mi_thunk): Likewise.
3958 (loongarch_option_override_internal): Remove the code that detects
3959 explicit relocs status.
3960 (loongarch_handle_model_attribute): Likewise.
3961 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
3962 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
3963 (symbolic_off64_or_reg_operand): Likewise.
3965 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3967 * config/loongarch/loongarch.cc (loongarch_load_tls):
3968 Load all types of tls symbols through one function.
3969 (loongarch_got_load_tls_gd): Delete.
3970 (loongarch_got_load_tls_ld): Delete.
3971 (loongarch_got_load_tls_ie): Delete.
3972 (loongarch_got_load_tls_le): Delete.
3973 (loongarch_call_tls_get_addr): Modify the called function name.
3974 (loongarch_legitimize_tls_address): Likewise.
3975 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
3976 (@load_tls<mode>): New template.
3977 (@got_load_tls_ld<mode>): Delete.
3978 (@got_load_tls_le<mode>): Delete.
3979 (@got_load_tls_ie<mode>): Delete.
3981 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3983 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
3984 (loongarch_legitimize_address): Add logical transformation code.
3986 2024-02-01 Marek Polacek <polacek@redhat.com>
3988 * doc/invoke.texi: Update -Wdangling-reference documentation.
3990 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
3992 PR target/113701
3993 * config/i386/i386.md (*cmp<dwi>_doubleword):
3994 Do not force SUBREG pieces to pseudos.
3996 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
3998 * config/pa/pa.md (atomic_storedi_1): Fix bug in
3999 alternative 1.
4001 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
4003 * config/avr/avr.cc: Tabify.
4005 2024-02-01 Richard Ball <richard.ball@arm.com>
4007 PR tree-optimization/111268
4008 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
4009 Add variable-length check for vector input arguments
4010 to a function.
4012 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
4014 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
4015 hard-code number of SGPR/VGPR/AVGPR registers.
4016 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
4017 SGPR/VGPR/AVGPR registers.
4019 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
4021 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
4022 attribute, and include sifive-p600.md.
4023 * config/riscv/generic-ooo.md: Update type attribute.
4024 * config/riscv/generic.md: Update type attribute.
4025 * config/riscv/sifive-7.md: Update type attribute.
4026 * config/riscv/sifive-p600.md: New file.
4027 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
4028 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
4029 Add sifive_p600.
4030 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
4031 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
4032 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
4034 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
4036 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
4037 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
4038 * config/riscv/riscv.opt: New macro for 7 new unprivileged
4039 extensions.
4040 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
4041 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
4043 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
4045 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
4046 -static-libasan. Add missing whitespace.
4048 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
4050 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
4051 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
4052 Don't 'define_constants'.
4054 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
4056 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
4058 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
4060 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
4061 [TARGET_RDNA3]: Adjust.
4063 2024-02-01 Richard Biener <rguenther@suse.de>
4065 PR tree-optimization/113693
4066 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
4067 data when available.
4069 2024-02-01 Jakub Jelinek <jakub@redhat.com>
4070 Jason Merrill <jason@redhat.com>
4072 PR c++/113531
4073 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
4074 on variables which were promoted to TREE_STATIC.
4076 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
4077 Richard Biener <rguenther@suse.de>
4079 PR target/113560
4080 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
4081 information via tree_non_zero_bits to check if this operand
4082 is suitably extended for a widening (or highpart) multiplication.
4083 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
4084 isn't already of the claimed type.
4086 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4088 Revert:
4089 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4091 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
4092 (generic_ooo_branch): ditto
4093 * config/riscv/generic.md (generic_sfb_alu): ditto
4094 (generic_fmul_half): ditto
4095 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
4096 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
4097 (sifive_7_popcount): ditto
4098 * config/riscv/vector.md: change rdfrm to fmove
4099 * config/riscv/zc.md: change pushpop to load/store
4101 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4103 Revert:
4104 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4105 Robin Dapp <rdapp.gcc@gmail.com>
4107 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
4108 (generic_ooo_vec_load): ditto
4109 (generic_ooo_vec_store): ditto
4110 (generic_ooo_vec_loadstore_seg): ditto
4111 (generic_ooo_vec_alu): ditto
4112 (generic_ooo_vec_fcmp): ditto
4113 (generic_ooo_vec_imul): ditto
4114 (generic_ooo_vec_fadd): ditto
4115 (generic_ooo_vec_fmul): ditto
4116 (generic_ooo_crypto): ditto
4117 (generic_ooo_perm): ditto
4118 (generic_ooo_vec_reduction): ditto
4119 (generic_ooo_vec_ordered_reduction): ditto
4120 (generic_ooo_vec_idiv): ditto
4121 (generic_ooo_vec_float_divsqrt): ditto
4122 (generic_ooo_vec_mask): ditto
4123 (generic_ooo_vec_vesetvl): ditto
4124 (generic_ooo_vec_setrm): ditto
4125 (generic_ooo_vec_readlen): ditto
4126 * config/riscv/riscv.md: include generic-vector-ooo
4127 * config/riscv/generic-vector-ooo.md: New file. to here
4129 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4131 Revert:
4132 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4134 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
4136 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4138 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
4140 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4141 Robin Dapp <rdapp.gcc@gmail.com>
4143 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
4144 (generic_ooo_vec_load): ditto
4145 (generic_ooo_vec_store): ditto
4146 (generic_ooo_vec_loadstore_seg): ditto
4147 (generic_ooo_vec_alu): ditto
4148 (generic_ooo_vec_fcmp): ditto
4149 (generic_ooo_vec_imul): ditto
4150 (generic_ooo_vec_fadd): ditto
4151 (generic_ooo_vec_fmul): ditto
4152 (generic_ooo_crypto): ditto
4153 (generic_ooo_perm): ditto
4154 (generic_ooo_vec_reduction): ditto
4155 (generic_ooo_vec_ordered_reduction): ditto
4156 (generic_ooo_vec_idiv): ditto
4157 (generic_ooo_vec_float_divsqrt): ditto
4158 (generic_ooo_vec_mask): ditto
4159 (generic_ooo_vec_vesetvl): ditto
4160 (generic_ooo_vec_setrm): ditto
4161 (generic_ooo_vec_readlen): ditto
4162 * config/riscv/riscv.md: include generic-vector-ooo
4163 * config/riscv/generic-vector-ooo.md: New file. to here
4165 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
4167 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
4168 (generic_ooo_branch): ditto
4169 * config/riscv/generic.md (generic_sfb_alu): ditto
4170 (generic_fmul_half): ditto
4171 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
4172 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
4173 (sifive_7_popcount): ditto
4174 * config/riscv/vector.md: change rdfrm to fmove
4175 * config/riscv/zc.md: change pushpop to load/store
4177 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
4179 PR target/113657
4180 * config/aarch64/aarch64-simd.md (split for movv8di):
4181 For strict aligned mode, use DImode instead of TImode.
4183 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
4185 PR middle-end/113607
4186 * match.pd: Make sure else values match when folding a
4187 vec_cond into a conditional operation.
4189 2024-01-31 Marek Polacek <polacek@redhat.com>
4191 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
4193 2024-01-31 Tamar Christina <tamar.christina@arm.com>
4194 Matthew Malcomson <matthew.malcomson@arm.com>
4196 PR sanitizer/112644
4197 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
4198 memcmp.
4199 * builtins.cc (expand_builtin): Include HWASAN when checking for
4200 builtin inlining.
4202 2024-01-31 Richard Biener <rguenther@suse.de>
4204 PR middle-end/110176
4205 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
4206 to match INTEGER_CST only without outstanding conversion.
4208 2024-01-31 Alex Coplan <alex.coplan@arm.com>
4210 PR target/111677
4211 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
4212 V16QImode for the full 16-byte FPR saves in the vector PCS case.
4214 2024-01-31 Richard Biener <rguenther@suse.de>
4216 PR tree-optimization/111444
4217 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
4218 vn_reference_lookup_2 when optimistically skipping may-defs.
4220 2024-01-31 Richard Biener <rguenther@suse.de>
4222 PR tree-optimization/113630
4223 * tree-ssa-pre.cc (compute_avail): Avoid registering a
4224 reference with a representation with not matching base
4225 access size.
4227 2024-01-31 Jakub Jelinek <jakub@redhat.com>
4229 PR rtl-optimization/113656
4230 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
4231 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
4233 2024-01-31 Jakub Jelinek <jakub@redhat.com>
4235 PR debug/113637
4236 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
4237 with BLKmode are larger than DWARF2_ADDR_SIZE.
4239 2024-01-31 Jakub Jelinek <jakub@redhat.com>
4241 PR tree-optimization/113639
4242 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
4243 For VIEW_CONVERT_EXPR set rhs1 to its operand.
4245 2024-01-31 Richard Biener <rguenther@suse.de>
4247 PR tree-optimization/113670
4248 * tree-vect-data-refs.cc (vect_check_gather_scatter):
4249 Make sure we can take the address of the reference base.
4251 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
4253 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
4254 ATA5835, ATtiny64AUTO, ATA5700M322.
4255 * doc/avr-mmcu.texi: Rebuild.
4257 2024-01-31 Alexandre Oliva <oliva@adacore.com>
4259 PR debug/113394
4260 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
4261 caller.
4263 2024-01-31 Alexandre Oliva <oliva@adacore.com>
4265 PR middle-end/112917
4266 PR middle-end/113100
4267 * builtins.cc (expand_builtin_stack_address): Use
4268 STACK_ADDRESS_OFFSET.
4269 * doc/extend.texi (__builtin_stack_address): Adjust.
4270 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
4271 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
4272 * doc/tm.texi: Rebuilt.
4274 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4276 PR target/113495
4277 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
4278 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
4279 (pre_vsetvl::compute_transparent): New function.
4280 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
4282 2024-01-30 Fangrui Song <maskray@google.com>
4284 PR target/105576
4285 * config/i386/constraints.md: Define constraint "Ws".
4286 * doc/md.texi: Document it.
4288 2024-01-30 Marek Polacek <polacek@redhat.com>
4290 PR c++/110358
4291 PR c++/109640
4292 * doc/invoke.texi: Update -Wdangling-reference description.
4294 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
4296 * config/xtensa/constraints.md (R, T, U):
4297 Change define_constraint to define_memory_constraint.
4298 * config/xtensa/predicates.md (move_operand): Don't check that a
4299 constant pool operand size is a multiple of UNITS_PER_WORD.
4300 * config/xtensa/xtensa.cc
4301 (xtensa_lra_p, TARGET_LRA_P): Remove.
4302 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
4303 clause as it can no longer be true.
4304 (fixup_subreg_mem): Drop function.
4305 (xtensa_output_integer_literal_parts): Consider 16-bit wide
4306 constants.
4307 (xtensa_legitimate_constant_p): Add short-circuit path for
4308 integer load instructions. Don't check that mode size is
4309 at least UNITS_PER_WORD.
4310 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
4311 rather reload_in_progress and reload_completed.
4312 (doloop_end): Drop operand 2.
4313 (movhi_internal): Add alternative loading constant from a
4314 literal pool.
4315 (define_split for DI register_operand): Don't limit to
4316 !TARGET_AUTO_LITPOOLS.
4317 * config/xtensa/xtensa.opt (mlra): Change to no effect.
4319 2024-01-30 Pan Li <pan2.li@intel.com>
4321 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
4322 calculate the gpr count required by vls mode.
4323 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
4324 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
4325 for vls mode.
4326 (riscv_get_arg_info): Add vls mode handling.
4327 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
4329 2024-01-30 Richard Biener <rguenther@suse.de>
4331 PR tree-optimization/113659
4332 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4333 Handle main exit without virtual use.
4335 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
4337 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
4339 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
4341 PR libgcc/113403
4342 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
4343 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
4344 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
4345 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
4346 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
4347 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
4349 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
4351 PR target/113623
4352 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
4353 Mark all registers that occur in addresses as needing a GPR.
4355 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
4357 PR target/113636
4358 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
4359 the containing insn as an extra parameter. Reset debug instructions
4360 if they reference a register that is no longer used by real insns.
4361 (early_ra::apply_allocation): Update calls accordingly.
4363 2024-01-30 Jakub Jelinek <jakub@redhat.com>
4365 PR tree-optimization/113603
4366 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
4367 count_nonzero_bytes call refetch si using get_strinfo in case it
4368 has been unshared in the meantime.
4370 2024-01-30 Jakub Jelinek <jakub@redhat.com>
4372 PR middle-end/101195
4373 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
4374 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
4376 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
4378 * config/riscv/thead.cc (th_print_operand_address): Change %ld
4379 to %lld.
4381 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
4382 Manolis Tsamis <manolis.tsamis@vrull.eu>
4383 Philipp Tomsich <philipp.tomsich@vrull.eu>
4385 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
4386 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
4387 Likewise.
4388 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
4389 Call on framework moved later.
4391 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
4393 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
4394 instruction in naked function epilogues.
4396 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
4398 PR target/113655
4399 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
4400 gcc_cv_as_mips_explicit_relocs.
4401 * configure: Regnerated.
4403 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
4405 PR target/108933
4406 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
4407 Correct generated RTL.
4408 (arm_rev16si2_alt1): Correctly handle conditional execution.
4409 (arm_rev16si2_alt2): Likewise.
4411 2024-01-29 Richard Biener <rguenther@suse.de>
4413 PR middle-end/113622
4414 * expr.cc (expand_assignment): Spill hard registers if
4415 we index them with a variable offset.
4417 2024-01-29 Richard Biener <rguenther@suse.de>
4419 PR middle-end/113622
4420 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
4421 Also allow DECL_HARD_REGISTER variables.
4423 2024-01-29 Alex Coplan <alex.coplan@arm.com>
4425 PR target/113616
4426 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
4427 Use iterate_safely when iterating over debug uses.
4428 (fixup_debug_uses): Likewise.
4429 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
4430 over nondebug insns instead of manually maintaining the next insn.
4431 * iterator-utils.h (class safe_iterator): New.
4432 (iterate_safely): New.
4434 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
4436 PR target/38534
4437 * config/i386/i386-options.cc (ix86_set_func_type): Save
4438 callee-saved registers in noreturn functions for -O0/-Og.
4440 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4442 PR target/113615
4443 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
4444 define for !TARGET_RDNA2_PLUS.
4446 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
4448 PR target/113281
4449 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
4450 workaround for right shifts.
4451 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
4452 (vect_determine_precisions_from_range): Be more selective about
4453 which codes can be narrowed based on their input and output ranges.
4454 For shifts, require at least one more bit of precision than the
4455 maximum shift amount.
4457 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4459 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
4461 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4463 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
4464 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
4465 LLVM 13.0.1+.
4467 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4469 PR other/111966
4470 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
4471 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
4472 (SET_SRAM_ECC_UNSET): ... this.
4473 (copy_early_debug_info): Remove gfx900 special case, now handled as
4474 part of the generic handling.
4475 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
4477 2024-01-29 Jakub Jelinek <jakub@redhat.com>
4479 PR tree-optimization/110603
4480 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
4481 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
4482 overwritten anyway). Avoid creating invalid range with minlen
4483 larger than maxlen. Formatting fix.
4485 2024-01-29 Richard Biener <rguenther@suse.de>
4487 PR debug/103047
4488 * tree-inline.cc (initialize_inlined_parameters): Reverse
4489 the decl chain of inlined parameters.
4491 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
4493 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
4494 alignment of CFString constants by setting DECL_USER_ALIGN.
4496 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
4497 Jakub Jelinek <jakub@redhat.com>
4499 PR libgcc/113402
4500 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
4501 and BUILT_IN_GCC_NESTED_PTR_DELETED.
4502 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
4503 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
4504 rename the library fallbacks to __gcc_nested_func_ptr_created and
4505 __gcc_nested_func_ptr_deleted.
4506 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
4507 and __gcc_nested_func_ptr_deleted.
4508 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
4509 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
4510 * tree.cc (build_common_builtin_nodes): Build the
4511 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
4512 builtins only for non-explicit.
4514 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
4516 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
4518 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
4520 PR target/38534
4521 * config/i386/i386-options.cc (ix86_set_func_type): Don't
4522 save and restore callee saved registers for a noreturn function
4523 with nothrow or compiled with -fno-exceptions.
4525 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
4527 PR target/103503
4528 PR target/113312
4529 * config/i386/i386-expand.cc (ix86_expand_call): Replace
4530 no_caller_saved_registers check with call_saved_registers check.
4531 Clobber all registers that are not used by the callee with
4532 no_callee_saved_registers attribute.
4533 * config/i386/i386-options.cc (ix86_set_func_type): Set
4534 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
4535 noreturn function. Disallow no_callee_saved_registers with
4536 interrupt or no_caller_saved_registers attributes together.
4537 (ix86_set_current_function): Replace no_caller_saved_registers
4538 check with call_saved_registers check.
4539 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
4540 (ix86_handle_call_saved_registers_attribute): This.
4541 (ix86_gnu_attributes): Add
4542 ix86_handle_call_saved_registers_attribute.
4543 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
4544 no_caller_saved_registers check with call_saved_registers check.
4545 (ix86_function_ok_for_sibcall): Don't allow callee with
4546 no_callee_saved_registers attribute when the calling function
4547 has callee-saved registers.
4548 (ix86_comp_type_attributes): Also check
4549 no_callee_saved_registers.
4550 (ix86_epilogue_uses): Replace no_caller_saved_registers check
4551 with call_saved_registers check.
4552 (ix86_hard_regno_scratch_ok): Likewise.
4553 (ix86_save_reg): Replace no_caller_saved_registers check with
4554 call_saved_registers check. Don't save any registers for
4555 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
4556 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
4557 no_callee_saved_registers attribute is called.
4558 (find_drap_reg): Replace no_caller_saved_registers check with
4559 call_saved_registers check.
4560 * config/i386/i386.h (call_saved_registers_type): New enum.
4561 (machine_function): Replace no_caller_saved_registers with
4562 call_saved_registers.
4563 * doc/extend.texi: Document no_callee_saved_registers attribute.
4565 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4567 PR tree-optimization/113614
4568 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
4569 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
4570 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
4572 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4574 PR tree-optimization/113568
4575 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
4576 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
4577 in the widening extension checks.
4579 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4581 * gimple-lower-bitint.cc (gimple_lower_bitint): For
4582 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
4584 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
4586 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
4587 the warning for an attribute-always_inline without inline declaration.
4589 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
4591 PR other/113575
4592 * genopinit.cc (main): Split init_all_optabs into functions
4593 of 1000 patterns each.
4595 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4597 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
4598 TM_MULTILIB_CONFIG.
4599 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
4600 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
4601 -march/-mtune.
4603 2024-01-26 Andrew Stubbs <ams@baylibre.com>
4605 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
4606 * config/gcn/gcn-valu.md (all_convert): New iterator.
4607 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
4608 define_expand, and rename the old one to ...
4609 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
4610 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
4611 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
4612 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
4613 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
4614 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
4615 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
4616 (<u>mulqihi3_scalar): Likewise.
4618 2024-01-26 Richard Biener <rguenther@suse.de>
4620 PR tree-optimization/113602
4621 * tree-data-ref.cc (dr_analyze_innermost): Fail when
4622 the base object isn't addressable.
4624 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4626 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
4627 "--amdhsa-code-object-version=" argument.
4628 (ASM_SPEC): Use it; replace previous version of it.
4630 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4632 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
4633 (pre_vsetvl::emit_vsetvl): Ditto.
4635 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4637 * config/loongarch/lasx.md (vec_extract<mode>_0):
4638 New define_insn_and_split patten.
4640 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4642 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
4644 2024-01-26 Li Wei <liwei@loongson.cn>
4646 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
4648 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4650 PR target/113469
4651 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
4653 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
4655 PR target/100212
4656 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
4657 undefined shift after the call to exact_log2.
4659 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
4661 PR target/100204
4662 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
4663 before taking the negative of it.
4665 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
4667 PR target/113526
4668 * lra-constraints.cc (curr_insn_transform): Change class even for
4669 spilled pseudo successfully matched with with NO_REGS.
4671 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
4673 PR target/113601
4674 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
4676 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
4678 PR target/112987
4679 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
4680 (aarch64_expand_epilogue): Use the new function.
4681 (aarch64_split_compare_and_swap): Likewise.
4682 (aarch64_split_atomic_op): Likewise.
4684 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
4686 PR middle-end/112971
4687 * fold-const.cc (simplify_const_binop): New function for binop
4688 simplification of two constant vectors when element-wise
4689 handling is not necessary.
4690 (const_binop): Call new function.
4692 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
4694 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
4695 * config/riscv/constraints.md: Likewise.
4696 * config/riscv/corev.def: Likewise.
4697 * config/riscv/corev.md: Likewise.
4698 * config/riscv/predicates.md: Likewise.
4699 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
4700 * config/riscv/riscv-ftypes.def: Likewise.
4701 * config/riscv/riscv.opt: Likewise.
4702 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
4703 * doc/extend.texi: Add XCVbitmanip builtin documentation.
4704 * doc/sourcebuild.texi: Likewise.
4706 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
4708 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
4710 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
4712 PR target/113538
4713 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
4714 (riscv_fntype_abi): Ditto.
4715 * config/riscv/riscv.opt: Ditto.
4717 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4719 PR middle-end/113574
4720 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
4721 count against TYPE_PRECISION rather than TYPE_SIZE.
4723 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4725 PR target/113572
4726 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
4727 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
4729 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4731 PR target/113550
4732 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
4733 whether each split instruction is a load that clobbers the source
4734 address. Emit that instruction last if so.
4736 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4738 PR target/113485
4739 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
4740 pattern.
4741 (<optab><Vnarrowq><mode>2): Use it instead of generating a
4742 paradoxical subreg for the input.
4744 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4746 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
4747 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
4748 predecessors dump information.
4750 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4752 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
4753 redundant full available computation.
4754 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4756 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4758 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
4759 * doc/rtl.texi (CONST_VECTOR): Likewise.
4761 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4763 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
4764 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
4765 (pass_vsetvl::execute): Ditto.
4766 * config/riscv/riscv.opt: Ditto.
4768 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
4770 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
4771 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
4773 2024-01-25 Richard Biener <rguenther@suse.de>
4775 PR tree-optimization/113576
4776 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
4777 exits with may_be_zero niters when its the last one.
4779 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
4781 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
4782 For symbols of type tls, non-zero Offset is not generated.
4784 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
4786 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
4787 P9 with m32 and mpowerpc64.
4789 2024-01-25 liuhongt <hongtao.liu@intel.com>
4791 * config/i386/i386-options.cc (ix86_option_override_internal):
4792 Enable -mlam=u57 by default when compiled with
4793 -fsanitize=hwaddress.
4795 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
4797 * common/config/riscv/riscv-common.cc (riscv_implied_info):
4798 Remove {"ztso", "a"}.
4800 2024-01-24 Martin Jambor <mjambor@suse.cz>
4802 PR ipa/108007
4803 PR ipa/112616
4804 * cgraph.h (cgraph_edge): Add a parameter to
4805 redirect_call_stmt_to_callee.
4806 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
4807 parameter to modify_call.
4808 (ipa_release_ssas_in_hash): Declare.
4809 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
4810 parameter killed_ssas, pass it to padjs->modify_call.
4811 * ipa-param-manipulation.cc (purge_all_uses): New function.
4812 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
4813 Instead of substituting uses, invoke purge_all_uses. If
4814 hash of killed SSAs has not been provided, create a temporary one
4815 and release SSAs that have been added to it.
4816 (compare_ssa_versions): New function.
4817 (ipa_release_ssas_in_hash): Likewise.
4818 * tree-inline.cc (redirect_all_calls): Create
4819 id->killed_new_ssa_names earlier, pass it to edge redirection,
4820 adjust a comment.
4821 (copy_body): Release SSAs in id->killed_new_ssa_names.
4823 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
4825 PR target/113486
4826 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
4827 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
4829 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
4831 PR target/113095
4832 * config/riscv/sfb.md: New splitters to rewrite single bit
4833 sign extension as the condition to SFB instructions.
4835 2024-01-24 Jan Hubicka <jh@suse.cz>
4837 PR middle-end/88345
4838 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
4839 (fmin-function-alignment): New parameter.
4840 * doc/invoke.texi: (-fmin-function-alignment): Document.
4841 (-falign-functions,-falign-loops,-falign-labels): Mention that
4842 aglinments are ignored in cold code.
4843 * varasm.cc (assemble_start_function): Handle min-function-alignment.
4845 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4847 PR target/109636
4848 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
4849 mulv2di3): Remove.
4850 * config/aarch64/iterators.md (VQDIV): Remove.
4851 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
4852 SVE_I_SIMD_DI): New.
4853 (VPRED, sve_lane_con): Add V4SI and V2DI.
4854 * config/aarch64/aarch64-sve.md (<optab><mode>3,
4855 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
4856 (mul<mode>3): New, split from <optab><mode>3.
4857 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
4858 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
4859 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
4860 SVE_FULL_HSDI_SIMD_DI.
4862 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4864 PR tree-optimization/113552
4865 * config/aarch64/aarch64.cc
4866 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
4868 2024-01-24 Martin Jambor <mjambor@suse.cz>
4870 PR ipa/113490
4871 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
4872 count is equal or greater than the limit. Use the limit from the
4873 callee.
4875 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
4877 * configure.ac: Detect the explicit relocs support for
4878 mips, and define C macro MIPS_EXPLICIT_RELOCS.
4879 * config.in: Regenerated.
4880 * configure: Regenerated.
4881 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
4882 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
4883 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
4884 !TARGET_EXPLICIT_RELOCS instead of just set it.
4885 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
4886 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
4887 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
4888 and define -m(no-)explicit-relocs as aliases.
4890 2024-01-24 Alex Coplan <alex.coplan@arm.com>
4892 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
4893 to 1.
4894 (-mlate-ldp-fusion): Likewise.
4896 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4898 * tree-vect-loop.cc (vect_get_vect_def,
4899 vect_create_epilog_for_reduction): Rename main_exit_p to
4900 last_val_reduc_p.
4902 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4904 PR tree-optimization/113364
4905 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
4906 early exits then we must reduce from the first offset for all of them.
4908 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4910 PR target/113495
4911 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
4912 (get_regno): Ditto.
4913 (get_bb_index): Ditto.
4914 (pre_vsetvl::compute_avl_def_data): Ditto.
4915 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
4916 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4918 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
4919 Richard Sandiford <richard.sandiford@arm.com>
4921 PR target/100942
4922 * ccmp.cc (ccmp_candidate_p): Add outer argument.
4923 Allow if the outer is true and the lhs is used more
4924 than once.
4925 (expand_ccmp_expr): Update call to ccmp_candidate_p.
4926 * expr.h (expand_expr_real_gassign): Declare.
4927 * expr.cc (expand_expr_real_gassign): New function, split out from...
4928 (expand_expr_real_1): ...here.
4929 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
4931 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4933 PR target/113089
4934 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
4935 (fixup_debug_use): New.
4936 (fixup_debug_uses_trailing_add): New.
4937 (fixup_debug_uses): New. Use it ...
4938 (ldp_bb_info::fuse_pair): ... here.
4939 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
4940 fix up debug uses of the base register that are affected by
4941 folding in the trailing add insn.
4943 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4945 PR target/113089
4946 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
4947 Update trailing nondebug uses of the base register in the case
4948 of cancelling writeback.
4950 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4952 PR target/113089
4953 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
4954 (debug_insn_use_iterator): New.
4955 (set_info::first_debug_insn_use): New.
4956 (set_info::debug_insn_uses): New.
4957 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
4958 (set_info::first_debug_insn_use): New.
4959 (set_info::debug_insn_uses): New.
4961 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4963 PR target/113356
4964 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
4965 Don't record hazards against the opposite insn in the pair.
4967 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4969 PR target/113070
4970 * config/aarch64/aarch64-ldp-fusion.cc
4971 (struct stp_change_builder): New.
4972 (decide_stp_strategy): Reanme to ...
4973 (try_repurpose_store): ... this.
4974 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
4975 construct stp changes. Fix up uses when inserting new stp insns.
4977 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4979 PR target/113070
4980 * rtl-ssa.h: Include hash-set.h.
4981 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
4982 new_sets parameter and use it to keep track of new user-created sets.
4983 (function_info::apply_changes_to_insn): Also call add_def on new sets.
4984 (function_info::change_insns): Add hash_set to keep track of new
4985 user-created defs. Plumb it through.
4986 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
4987 apply_changes_to_insn.
4989 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4991 PR target/113070
4992 * rtl-ssa/accesses.cc (function_info::create_use): New.
4993 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
4994 Ensure new uses end up referring to permanent defs.
4995 * rtl-ssa/functions.h (function_info::create_use): Declare.
4997 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4999 PR target/113070
5000 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
5001 to finalize_new_accesses from the backwards placement loop, run it
5002 forwards in a separate loop.
5004 2024-01-23 Richard Biener <rguenther@suse.de>
5006 PR tree-optimization/113552
5007 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
5008 floor_log2 instead of exact_log2 on the number of calls.
5010 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
5011 Jakub Jelinek <jakub@redhat.com>
5013 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
5014 decl.
5016 2024-01-23 Richard Biener <rguenther@suse.de>
5018 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5019 Separate single and multi-exit case when creating PHIs between
5020 the main and epilogue.
5022 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
5024 PR target/112989
5025 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
5026 MODE_single variants of functions that don't take tuple arguments.
5028 2024-01-23 Alex Coplan <alex.coplan@arm.com>
5030 PR target/113114
5031 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
5032 Don't assert recog success, just punt if the writeback pair
5033 isn't recognized.
5035 2024-01-23 Jakub Jelinek <jakub@redhat.com>
5037 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
5038 ATTRIBUTE_UNUSED to decl.
5040 2024-01-23 Richard Biener <rguenther@suse.de>
5042 PR debug/107058
5043 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
5044 handle unexpected but bogus DIE contexts when not checking
5045 enabled.
5047 2024-01-23 Jakub Jelinek <jakub@redhat.com>
5049 PR tree-optimization/113462
5050 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
5051 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
5052 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
5053 sizes between 129 and 8192 bytes.
5055 2024-01-23 Xi Ruoyao <xry111@xry111.site>
5057 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
5058 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
5059 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
5060 (loongarch_call_tls_get_addr): Do not split symbols of
5061 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
5062 EXPLICIT_RELOCS_AUTO.
5064 2024-01-23 Richard Biener <rguenther@suse.de>
5066 * alias.cc (known_base_value_p): Remove.
5067 (find_base_value): Remove PLUS/MINUS handling
5068 when both operands are not CONST_INT_P.
5070 2024-01-23 Richard Biener <rguenther@suse.de>
5072 PR rtl-optimization/113255
5073 * alias.cc (find_base_term): Remove PLUS/MINUS handling
5074 when both operands are not CONST_INT_P.
5076 2024-01-23 Richard Biener <rguenther@suse.de>
5078 PR debug/112718
5079 * dwarf2out.cc (dwarf2out_finish): Reset all type units
5080 for the fat part of an LTO compile.
5082 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
5084 * doc/sourcebuild.texi: Add attributes for keywords.
5086 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
5088 PR c++/90463
5089 * doc/invoke.texi (Warning Options): Correct lists of options
5090 enabled by -Wall and -Wextra by checking against common.opt
5091 and c-family/c.opt.
5093 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
5095 PR target/113030
5096 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
5097 instead of cpu_optaliases.
5098 (check_arch): Use arch_opt_alias instead of arch_optaliases.
5100 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5102 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
5103 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
5104 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
5106 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5108 PR target/109092
5109 * config/riscv/riscv.md: Use reg instead of subreg.
5111 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
5113 PR other/111966
5114 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
5115 to match the compiler default.
5116 (simple_object_copy_lto_debug_sections): Never unlink the outfile
5117 on error as the caller does so.
5118 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
5119 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
5121 2024-01-22 Richard Biener <rguenther@suse.de>
5123 PR tree-optimization/113373
5124 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5125 Create LC PHIs in the exit blocks where necessary.
5126 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
5127 to handle missing LC PHIs.
5128 (find_connected_edge): Remove.
5129 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
5131 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5133 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
5135 2024-01-22 xuli <xuli1@eswincomputing.com>
5137 PR target/113420
5138 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
5139 (registered_function::overloaded_hash):refactor.
5140 (resolve_overloaded_builtin):avoid internal ICE.
5142 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
5144 PR target/82420
5145 PR target/111279
5146 * calls.cc (emit_library_call_value_1): Pass valid TYPE
5147 to emit_push_insn.
5148 * expr.cc (emit_push_insn): Likewise.
5150 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
5152 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
5153 correcction version of last change.
5155 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
5157 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
5158 fix bugs in signature.
5160 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
5161 Richard Biener <rguenther@suse.de>
5163 PR rtl-optimization/111267
5164 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
5165 profitable_p method to likely_profitable_p.
5166 (try_fwprop_subst_node): Update call to likely_profitable_p.
5167 Only bail-out early when !prop.likely_profitable_p for instructions
5168 that are not single sets. When comparing costs, bail-out if the
5169 cost is unchanged and !prop.likely_profitable_p.
5171 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
5173 PR c++/90464
5174 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
5175 isn't enabled by -Wunused unless -Wextra is provided, and that
5176 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
5177 -Wunused doesn't enable -Wunused-* options documented as behaving
5178 otherwise, and list them explicitly.
5180 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
5182 PR c/109708
5183 * doc/invoke.texi (Warning Options): Fix broken example and
5184 clean up/reorganize the others. Also describe what the short-form
5185 options mean.
5187 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
5189 PR c/102998
5190 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
5191 (Warning Options): Correct/edit discussion of -Warray-parameter
5192 to make the first example less confusing, and fill in missing info.
5194 2024-01-20 Jakub Jelinek <jakub@redhat.com>
5196 PR tree-optimization/113462
5197 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
5198 Handle rhs1 INTEGER_CST like SSA_NAME.
5200 2024-01-20 Jakub Jelinek <jakub@redhat.com>
5202 PR tree-optimization/113491
5203 * tree-switch-conversion.cc (switch_conversion::build_constructors):
5204 If elt.index has precision higher than sizetype, fold_convert it to
5205 sizetype.
5206 (switch_conversion::array_value_type): Return type if type is
5207 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
5208 (switch_conversion::build_arrays): Use unsigned_type_for rather than
5209 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
5210 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
5211 higher than sizetype, use sizetype as tidx type and fold_convert the
5212 subtraction to sizetype.
5214 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5216 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
5217 (riscv_vector_mode_supported_any_target_p): Ditto.
5219 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
5221 PR target/110934
5222 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
5223 (TARGET_ZERO_CALL_USED_REGS): Define.
5225 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
5227 PR target/108640
5228 * config/m68k/m68k.cc (output_andsi3): Use QImode for
5229 address adjusted for 1-byte RMW access.
5230 (output_iorsi3): Likewise.
5231 (output_xorsi3): Likewise.
5233 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5235 * doc/invoke.texi (RISC-V Options): Add list of supported
5236 extensions.
5238 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5240 PR target/113495
5241 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
5242 (RVV_VUNDEF): Ditto.
5243 * config/riscv/riscv-vsetvl.cc: Add timevar.
5245 2024-01-19 Richard Biener <rguenther@suse.de>
5247 PR debug/113488
5248 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
5249 an early DIE but there should be, do not pretend there is.
5251 2024-01-19 Richard Biener <rguenther@suse.de>
5253 PR tree-optimization/113494
5254 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5255 Handle endless loop on exit. Handle re-allocated PHI.
5257 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5259 PR tree-optimization/113464
5260 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
5261 optimize loads into GIMPLE_ASM stmts.
5263 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5265 PR tree-optimization/113463
5266 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
5267 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
5268 lhs.
5270 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5272 PR tree-optimization/113459
5273 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
5274 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
5275 of SCALAR_INT_TYPE_MODE if type has BLKmode.
5276 (vn_reference_lookup_3): Likewise. Formatting fix.
5278 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5279 Richard Biener <rguenther@suse.de>
5281 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
5282 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
5283 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
5284 but adjust_address also for BLKmode mode and MEM op0.
5286 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
5288 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
5289 extensions.
5291 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5293 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
5295 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5297 * common/config/riscv/riscv-common.cc
5298 (riscv_subset_list::parse_std_ext): Remove.
5299 (riscv_subset_list::parse_multiletter_ext): Remove.
5300 * config/riscv/riscv-subset.h
5301 (riscv_subset_list::parse_std_ext): Remove.
5302 (riscv_subset_list::parse_multiletter_ext): Remove.
5304 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5306 * common/config/riscv/riscv-common.cc
5307 (riscv_subset_list::parse_single_std_ext): New parameter.
5308 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
5309 (riscv_subset_list::parse_single_ext): Ditto.
5310 (riscv_subset_list::parse): Relax the order for the input of ISA
5311 string.
5312 * config/riscv/riscv-subset.h
5313 (riscv_subset_list::parse_single_std_ext): New parameter.
5314 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
5315 (riscv_subset_list::parse_single_ext): Ditto.
5317 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5319 * common/config/riscv/riscv-common.cc
5320 (riscv_subset_list::parse_base_ext): New.
5321 (riscv_subset_list::parse): Extract part of logic into
5322 riscv_subset_list::parse_base_ext.
5323 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
5324 New.
5326 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5328 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
5329 sorry message.
5331 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
5333 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
5334 UNSPEC_CLMUL_VC.
5336 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
5338 PR c/110029
5339 * doc/extend.texi (Common Variable Attributes): Explain what
5340 happens when multiple variables with cleanups are in the same scope.
5342 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5344 PR ipa/108470
5345 * doc/extend.texi (Common Function Attributes): Document that
5346 noinline also disables some interprocedural optimizations and
5347 improve flow to the part about using inline asm instead to
5348 disable calls from being optimized away completely. Remove the
5349 sentence that says noipa is mainly for internal compiler testing.
5351 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
5353 PR tree-optimization/69807
5354 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
5356 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
5358 PR target/108521
5359 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
5360 from x86 Windows Options.
5362 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5364 PR c/107942
5365 * doc/extend.texi (C Extensions): Add new section to menu.
5366 (Function Attributes): Move dangling index entries to....
5367 (Const and Volatile Functions): New section.
5369 2024-01-18 David Malcolm <dmalcolm@redhat.com>
5371 PR middle-end/112684
5372 * toplev.cc (toplev::main): Don't ICE in
5373 -fdiagnostics-generate-patch when exiting after options,
5374 since no edit context will have been created.
5376 2024-01-18 Richard Biener <rguenther@suse.de>
5378 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
5379 operands vector.
5381 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5383 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
5384 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
5386 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5387 Jin Ma <jinma@linux.alibaba.com>
5388 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5389 Christoph Müllner <christoph.muellner@vrull.eu>
5391 * config/riscv/thead.cc
5392 (th_asm_output_opcode): Rewrite some instructions.
5394 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5395 Jin Ma <jinma@linux.alibaba.com>
5396 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5397 Christoph Müllner <christoph.muellner@vrull.eu>
5399 * config/riscv/riscv.md (none,thv,rvv): New attribute.
5400 (no,yes): Add an attribute to disable alternative
5401 for xtheadvector or RVV1.0.
5402 * config/riscv/vector.md:
5403 Disable alternatives that destination register overlaps
5404 source register group for xtheadvector.
5406 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5407 Jin Ma <jinma@linux.alibaba.com>
5408 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5409 Christoph Müllner <christoph.muellner@vrull.eu>
5411 * config/riscv/riscv-vector-builtins-bases.cc
5412 (class th_loadstore_width): Define new builtin bases.
5413 (class th_extract): Define new builtin bases.
5414 (BASE): Define new builtin bases.
5415 * config/riscv/riscv-vector-builtins-bases.h:
5416 Define new builtin class.
5417 * config/riscv/riscv-vector-builtins-shapes.cc
5418 (struct th_loadstore_width_def): Define new builtin shapes.
5419 (struct th_indexed_loadstore_width_def):
5420 Define new builtin shapes.
5421 (struct th_extract_def): Define new builtin shapes.
5422 (SHAPE): Define new builtin shapes.
5423 * config/riscv/riscv-vector-builtins-shapes.h:
5424 Define new builtin shapes.
5425 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
5426 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
5427 * config/riscv/riscv-vector-builtins.h
5428 (enum required_ext): Add new XTheadVector member.
5429 (struct function_group_info): Likewise.
5430 * config/riscv/t-riscv:
5431 Add thead-vector-builtins-functions.def
5432 * config/riscv/thead-vector.md
5433 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
5434 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
5435 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
5436 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
5437 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
5438 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
5439 (@pred_th_extract<mode>): Likewise.
5440 (*pred_th_extract<mode>): Likewise.
5441 * config/riscv/thead-vector-builtins-functions.def: New file.
5443 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5444 Jin Ma <jinma@linux.alibaba.com>
5445 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5446 Christoph Müllner <christoph.muellner@vrull.eu>
5448 * config.gcc: Add files for XTheadVector intrinsics.
5449 * config/riscv/autovec.md: Guard XTheadVector.
5450 * config/riscv/predicates.md: Disable immediate vl
5451 for XTheadVector.
5452 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
5453 Add pragma for XTheadVector.
5454 * config/riscv/riscv-string.cc (riscv_expand_block_move):
5455 Guard XTheadVector.
5456 * config/riscv/riscv-v.cc (vls_mode_valid_p):
5457 Avoid autovec.
5458 * config/riscv/riscv-vector-builtins-bases.cc:
5459 Do not normalize vsetvl instructions for XTheadVector.
5460 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
5461 New check type function.
5462 (build_one): Adjust for XTheadVector.
5463 * config/riscv/riscv-vector-switch.def (ENTRY):
5464 Disable fractional mode for the XTheadVector extension.
5465 (TUPLE_ENTRY): Likewise.
5466 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
5467 Guard XTheadVector.
5468 (riscv_preferred_simd_mode): Likewsie.
5469 (riscv_autovectorize_vector_modes): Likewise.
5470 (riscv_vector_mode_supported_any_target_p): Likewise.
5471 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
5472 * config/riscv/thead.cc (th_asm_output_opcode):
5473 Rewrite vsetvl instructions.
5474 * config/riscv/vector.md:
5475 Include thead-vector.md and change fractional LMUL
5476 into 1 for vbool.
5477 * config/riscv/riscv_th_vector.h: New file.
5478 * config/riscv/thead-vector.md: New file.
5480 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5481 Jin Ma <jinma@linux.alibaba.com>
5482 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5483 Christoph Müllner <christoph.muellner@vrull.eu>
5485 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
5486 Add new function to add assembler insn code prefix/suffix.
5487 (th_asm_output_opcode):
5488 Add Thead function to add assembler insn code prefix/suffix.
5489 * config/riscv/riscv.cc (riscv_asm_output_opcode):
5490 Implement function to add assembler insn code prefix/suffix.
5491 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
5492 Add new function to add assembler insn code prefix/suffix.
5493 * config/riscv/thead.cc (th_asm_output_opcode):
5494 Implement Thead function to add assembler insn code
5495 prefix/suffix.
5497 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5498 Jin Ma <jinma@linux.alibaba.com>
5499 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5500 Christoph Müllner <christoph.muellner@vrull.eu>
5502 * common/config/riscv/riscv-common.cc
5503 (riscv_subset_list::parse): Add new vendor extension.
5504 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
5505 Add test marco.
5506 * config/riscv/riscv.opt: Add new mask.
5508 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5510 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
5511 to be conditional on macosx-version-min.
5513 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5515 * config/darwin.cc (darwin_objc1_section): Use the correct
5516 meta-data version for constant strings.
5517 (machopic_select_section): Assert if we fail to handle CFString
5518 sections as Obejctive-C meta-data or drectly.
5520 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5522 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
5523 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
5524 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
5525 versions when the object format is Mach-O.
5527 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5529 PR target/105522
5530 * config/darwin.cc (machopic_select_section): Handle C and C++
5531 CFStrings.
5532 (darwin_rename_builtins): Move this out of the CFString code.
5533 (darwin_libc_has_function): Likewise.
5534 (darwin_build_constant_cfstring): Create an anonymous var to
5535 hold each CFString.
5536 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
5537 CFstrings.
5539 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5541 PR bootstrap/113445
5542 * haifa-sched.cc (dep_list_size): Make global.
5543 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
5544 * sched-int.h (dep_list_size): Declare.
5546 2024-01-18 Martin Jambor <mjambor@suse.cz>
5548 PR tree-optimization/110422
5549 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
5550 gotos.
5552 2024-01-18 Richard Biener <rguenther@suse.de>
5554 PR tree-optimization/113475
5555 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
5556 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
5557 (phi_analyzer::~phi_analyzer): Deallocate and free collected
5558 phi_grous.
5559 (phi_analyzer::process_phi): Record allocated phi_groups.
5561 2024-01-18 Richard Biener <rguenther@suse.de>
5563 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
5564 storage for gvec_oprnds elements.
5566 2024-01-18 Richard Biener <rguenther@suse.de>
5568 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
5569 prefer all later exits we can handle.
5570 (vect_analyze_loop_form): Free the allocated loop body.
5571 Adjust comments.
5573 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5575 * config/avr/avr-log.cc: Tabify.
5577 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5579 * config/riscv/autovec.md: Support vi variant.
5581 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5583 * config/avr/avr-devices.cc: Tabify.
5585 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5587 * config/avr/avr-c.cc: Tabify.
5589 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5591 * config/avr/driver-avr.cc: Tabify.
5593 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5595 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
5597 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5599 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
5601 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5603 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
5604 minline-strcmp, minline-strncmp, minline-strlen,
5605 -param=riscv-vector-abi): Remove Bool keywords.
5607 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5609 PR target/113122
5610 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
5611 support. Add missing space after , in emitted assembly in some
5612 cases. Formatting fixes.
5614 2024-01-18 Xi Ruoyao <xry111@xry111.site>
5616 * config/loongarch/loongarch.md (movsi_internal): Remove
5617 constraint z.
5619 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5621 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
5622 in the diagnostic, and capitalize the device name.
5623 (print_mcu): Generate specs such that:
5624 <*check_rodata_in_ram>: New.
5625 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
5626 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
5627 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
5629 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5631 PR other/113399
5632 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
5633 Common and Optimization.
5635 2024-01-18 Richard Biener <rguenther@suse.de>
5637 PR tree-optimization/113431
5638 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
5639 When there is an invariant load we might not preserve
5640 scalar order.
5642 2024-01-18 Richard Biener <rguenther@suse.de>
5644 PR tree-optimization/113374
5645 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
5646 * tree-vect-loop.cc (move_early_exit_stmts): Update
5647 virtual LC PHIs.
5648 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5649 Refactor. Preserve virtual LC PHIs on all exits.
5651 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
5653 * config/loongarch/loongarch.cc (loongarch_split_symbol):
5654 Assign the '/u' attribute to the mem.
5656 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5658 PR middle-end/110847
5659 * doc/invoke.texi (Option Summary): Document negative forms of
5660 -Wtsan and -Wxor-used-as-pow.
5661 (Warning Options): Likewise.
5663 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5665 PR target/113429
5666 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
5668 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5670 * doc/extend.texi (Common Function Attributes): Re-alphabetize
5671 the table.
5672 (Common Variable Attributes): Likewise.
5673 (Common Type Attributes): Likewise.
5675 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5677 PR middle-end/111659
5678 * doc/extend.texi (Common Variable Attributes): Fix long lines
5679 in documentation of strict_flex_array + other minor copy-editing.
5680 Add a cross-reference to -Wstrict-flex-arrays.
5681 * doc/invoke.texi (Option Summary): Fix whitespace in tables
5682 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
5683 (C Dialect Options): Combine the docs for the two
5684 -fstrict-flex-arrays forms into a single entry. Note this option
5685 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
5686 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
5687 Minor copy-editing. Add cross references to the strict_flex_array
5688 attribute and -fstrict-flex-arrays option. Add note that this
5689 option depends on -ftree-vrp.
5691 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
5693 PR target/113221
5694 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
5695 only allow REG operands instead of allowing all.
5697 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5699 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
5700 Remove redundant checks in else condition for readablity.
5701 (earliest_fuse_vsetvl_info) Print iteration count in debug
5702 prints.
5703 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
5704 dump details in certain cases.
5706 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5708 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
5709 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
5710 * config/riscv/riscv-vsetvl.cc
5711 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
5712 (pass_vsetvl::execute): Use vsetvl_strategy.
5714 2024-01-17 Jan Hubicka <jh@suse.cz>
5716 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
5717 accidental hack reseting offset.
5719 2024-01-17 Jan Hubicka <jh@suse.cz>
5721 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
5722 handling of X86_TUNE_AVOID_512FMA_CHAINS.
5724 2024-01-17 Jan Hubicka <jh@suse.cz>
5725 Jakub Jelinek <jakub@redhat.com>
5727 PR tree-optimization/110852
5728 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
5729 binary operations
5730 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
5731 PRED_COMBINED_VALUE_PREDICTIONS_PHI
5732 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
5733 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
5735 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5737 PR tree-optimization/113421
5738 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
5739 comment.
5740 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
5741 formatting. Start at vop rather than cvop even if stmt is a store
5742 and needs_operand_addr.
5744 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5746 PR middle-end/113410
5747 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
5748 If access_nelts is integral with larger precision than sizetype,
5749 fold_convert it to sizetype.
5751 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5753 PR tree-optimization/113408
5754 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
5755 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
5756 to handle_cast.
5758 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5760 PR middle-end/113406
5761 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
5762 regardless of whether is_gimple_reg_type (restype) or not.
5764 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5766 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
5767 funcions -> functions, and use were instead of was.
5768 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
5769 and guaranteee -> guarantee.
5770 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
5772 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5774 PR middle-end/113409
5775 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
5776 INTEGER_TYPE.
5777 (omp_extract_for_data): Use build_bitint_type rather than
5778 build_nonstandard_integer_type if either iter_type or loop->v type
5779 is BITINT_TYPE.
5780 * omp-expand.cc (expand_omp_for_generic,
5781 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
5782 BITINT_TYPE like INTEGER_TYPE.
5784 2024-01-17 Richard Biener <rguenther@suse.de>
5786 PR tree-optimization/113371
5787 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
5788 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5789 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
5790 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5792 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5794 PR rtl-optimization/96388
5795 PR rtl-optimization/111554
5796 * sched-deps.cc (find_inc): Avoid exponential behavior.
5798 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5800 PR c/111693
5801 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
5802 from C++ Language Options to Warning Options. Add entry for
5803 -Wuse-after-free.
5804 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
5805 from here....
5806 (Warning Options): ...to here. Minor copy-editing to fix typo
5807 and grammar.
5809 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
5811 * config/mips/mips.cc (mips_compute_frame_info): If another
5812 register is used as global_pointer, mark $GP live false.
5814 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5816 PR target/112973
5817 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
5818 give the section a light copy-editing pass.
5820 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5822 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
5823 * config/aarch64/aarch64-tune.md: Regenerated.
5824 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
5826 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5828 PR target/112573
5829 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
5830 badly formed CONST expressions.
5832 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5834 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
5836 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5838 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
5839 * config/sparc/sync.md (membar_storeload): Turn into named insn
5840 and add GR712RC errata workaround.
5841 (membar_v8): Add GR712RC errata workaround.
5843 2024-01-16 Andreas Larsson <andreas@gaisler.com>
5845 * config/sparc/sync.md (*membar_storeload_leon3): Remove
5846 (*membar_storeload): Enable for LEON
5848 2024-01-16 Jakub Jelinek <jakub@redhat.com>
5850 PR tree-optimization/113372
5851 PR middle-end/90348
5852 PR middle-end/110115
5853 PR middle-end/111422
5854 * cfgexpand.cc (add_scope_conflicts_2): New function.
5855 (add_scope_conflicts_1): Use it.
5857 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
5859 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
5860 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
5861 * doc/avr-mmcu.texi: Regenerate.
5863 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
5865 PR tree-optimization/113091
5866 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
5867 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
5868 scalar use with new function.
5869 (vect_bb_slp_mark_live_stmts): New function as entry to existing
5870 overriden functions with same name.
5871 (vect_slp_analyze_operations): Call new entry function to mark
5872 live statements.
5874 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5876 PR target/113404
5877 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
5878 for RVV in big-endian mode.
5880 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
5882 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
5883 (riscv_pass_in_vector_p): Delete.
5884 (riscv_init_cumulative_args): Delete the checking.
5885 (riscv_get_arg_info): Delete the checking.
5886 (riscv_function_value): Delete the checking.
5887 * config/riscv/riscv.h: Delete the member for checking.
5889 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5891 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
5893 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5895 * config.gcc: Include riscv_bitmanip.h.
5896 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
5897 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
5898 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
5899 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
5900 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
5901 * config/riscv/riscv-ftypes.def (2): New ftypes.
5902 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
5903 (RISCV_BUILTIN_NO_PREFIX): Likewise.
5904 * config/riscv/riscv_bitmanip.h: New file.
5906 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5908 * config.gcc: Include riscv_crypto.h.
5909 * config/riscv/riscv_crypto.h: New file.
5911 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
5913 PR middle-end/113354
5914 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
5915 in the insn if the corresponding operand does not require hard
5916 register anymore.
5918 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5920 PR target/107201
5921 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
5922 * config/avr/driver-avr.cc (avr_no_devlib): New function.
5923 (avr_devicespecs_file): Use it to remove -nodevicelib from the
5924 options for cores only.
5925 * config/avr/avr-arch.h (avr_get_parch): New prototype.
5926 * config/avr/avr-devices.cc (avr_get_parch): New function.
5928 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5930 PR target/113247
5931 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
5932 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
5933 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
5935 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5937 PR target/113281
5938 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
5939 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
5940 * config/riscv/riscv-vector-costs.h: New function.
5942 2024-01-15 Richard Biener <rguenther@suse.de>
5944 PR tree-optimization/113385
5945 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5946 First redirect, then split the exit edge.
5948 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5950 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
5951 Remove m_num_vector_iterations.
5952 * config/riscv/riscv-vector-costs.h: Ditto.
5954 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
5956 PR target/113156
5957 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
5958 (-mbranch-cost): Set "Optimization" flag.
5960 2024-01-15 Jakub Jelinek <jakub@redhat.com>
5962 PR tree-optimization/113370
5963 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
5964 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
5965 set it to just prec % limb_prec.
5967 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5969 PR target/113393
5970 * config/riscv/vector.md: Fix ternary attributes.
5972 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
5974 PR target/112944
5975 * configure.ac [target=avr]: Check availability of emulations
5976 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
5977 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
5978 * configure: Regenerate.
5979 * config.in: Regenerate.
5980 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
5981 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
5982 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
5983 * config/avr/avr-arch.h (enum avr_device_specific_features):
5984 Add AVR_ISA_FLMAP.
5985 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
5986 AVR_ISA_FLMAP.
5987 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
5988 (avr_set_core_architecture): Set avr_arch_index.
5989 (have_avrxmega2_flmap, have_avrxmega4_flmap)
5990 (have_avrxmega3_rodata_in_flash): Set new static const bool according
5991 to configure results.
5992 (avr_rodata_in_flash_p): New function using them.
5993 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
5994 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
5995 (avr_asm_named_section): Track avr_has_rodata_p.
5996 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
5997 and not avr_rodata_in_flash_p ().
5998 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
5999 (LINK_SPEC): Add %(link_rodata_in_ram).
6000 (LINK_ARCH_SPEC): Remove.
6001 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
6002 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
6003 const bool according to configure results.
6004 (diagnose_mrodata_in_ram): New function.
6005 (print_mcu): Generate specs with the following changes:
6006 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
6007 need to extend avr/specs.h each time we add a new bell or whistle.
6008 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
6009 -m[no-]rodata-in-ram.
6010 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
6011 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
6012 <*cpp>: Add %(cpp_rodata_in_ram).
6013 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
6014 requested.
6015 <*self_spec>: Add -mflmap or %<mflmap as needed.
6017 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
6019 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
6020 not the GPR iterator. Adjust pattern name and mode attribute
6021 accordingly.
6023 2024-01-13 Jakub Jelinek <jakub@redhat.com>
6025 PR tree-optimization/113361
6026 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
6027 Fix up determination of the type for > limb_prec constants.
6029 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
6031 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
6032 Add web-link to the avr-gcc wiki.
6034 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
6036 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
6037 documentation for a version without argument, which is not supported.
6039 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6041 * config/arm/arm_neon.h
6042 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
6043 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
6044 (vld1_f16_x4, vld1_f32_x4): New.
6045 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
6046 (vld1_bf16_x4): New.
6047 (vld1q_types_x4): Updated to use vld1q_x4
6048 from arm_neon_builtins.def
6049 * config/arm/arm_neon_builtins.def
6050 (vld1_x4): Updated entries.
6051 (vld1q_x4): New entries, but comes from the old vld1_x4
6052 * config/arm/neon.md
6053 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
6055 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6057 * config/arm/arm_neon.h
6058 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
6059 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
6060 (vld1_f16_x3, vld1_f32_x3): New.
6061 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
6062 (vld1_bf16_x3): New.
6063 (vld1q_types_x3): Updated to use vld1q_x3 from
6064 arm_neon_builtins.def
6065 * config/arm/arm_neon_builtins.def
6066 (vld1_x3): Updated entries.
6067 (vld1q_x3): New entries, but comes from the old vld1_x2
6068 * config/arm/neon.md
6069 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
6071 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6073 * config/arm/arm_neon.h
6074 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
6075 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
6076 (vld1_f16_x2, vld1_f32_x2): New.
6077 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
6078 (vld1_bf16_x2): New.
6079 (vld1q_types_x2): Updated to use vld1q_x2 from
6080 arm_neon_builtins.def
6081 * config/arm/arm_neon_builtins.def
6082 (vld1_x2): Updated entries.
6083 (vld1q_x2): New entries, but comes from the old vld1_x2
6084 * config/arm/neon.md
6085 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
6086 neon_vld1_x2<mode>.
6088 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6090 * config/arm/arm_neon.h
6091 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
6092 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
6093 (vst1q_f16_x4, vst1q_f32_x4): New.
6094 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
6095 (vst1q_bf16_x4): New.
6096 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
6097 * config/arm/neon.md
6098 (neon_vst1q_x4<mode>): New.
6099 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
6100 * config/arm/unspecs.md
6101 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
6103 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6105 * config/arm/arm_neon.h
6106 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
6107 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
6108 (vst1q_f16_x3, vst1q_f32_x3): New.
6109 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
6110 (vst1q_bf16_x3): New.
6111 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
6112 * config/arm/neon.md
6113 (neon_vst1q_x3<mode>): New.
6114 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
6115 * config/arm/unspecs.md
6116 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
6118 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6120 * config/arm/arm_neon.h
6121 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
6122 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
6123 (vst1q_f16_x2, vst1q_f32_x2): New.
6124 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
6125 (vst1q_bf16_x2): New.
6126 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
6127 * config/arm/neon.md
6128 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
6129 neon_vst1_x2<mode>.
6130 * config/arm/iterators.md
6131 (VMEMX2): New mode iterator.
6132 (VMEMX2_q): New mode attribute.
6134 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6136 * config/arm/arm_neon.h
6137 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
6138 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
6139 (vst1_f16_x4, vst1_f32_x4): New.
6140 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
6141 (vst1_bf16_x4): New.
6142 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
6143 * config/arm/neon.md (vst1_x4<mode>): New.
6145 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6147 * config/arm/arm_neon.h
6148 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
6149 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
6150 (vst1_f16_x3, vst1_f32_x3): New.
6151 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
6152 (vst1_bf16_x3): New.
6153 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
6154 * config/arm/neon.md (vst1_x3<mode>): New.
6156 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6158 * config/arm/arm_neon.h
6159 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
6160 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
6161 (vst1_f16_x2, vst1_f32_x2): New.
6162 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
6163 (vst1_bf16_x2): New.
6164 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
6165 * config/arm/neon.md (vst1_x2<mode>): New.
6167 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6169 * config/arm/arm_neon.h
6170 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
6171 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
6172 (vld1q_f16_x4, vld1q_f32_x4): New.
6173 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
6174 (vld1q_bf16_x4): New.
6175 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
6176 * config/arm/neon.md
6177 (neon_vld1_x4<mode>): New.
6178 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
6179 * config/arm/unspecs.md
6180 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
6182 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6184 * config/arm/arm_neon.h
6185 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
6186 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
6187 (vld1q_f16_x3, vld1q_f32_x3): New.
6188 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
6189 (vld1q_bf16_x3): New.
6190 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
6191 * config/arm/neon.md
6192 (neon_vld1_x3<mode>): New.
6193 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
6194 * config/arm/unspecs.md
6195 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
6197 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
6199 * config/arm/arm_neon.h
6200 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
6201 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
6202 (vld1q_f16_x2, vld1q_f32_x2): New.
6203 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
6204 (vld1q_bf16_x2): New.
6205 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
6206 * config/arm/neon.md (vld1_x2<mode>): New.
6208 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6210 PR tree-optimization/113287
6211 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
6213 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6215 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
6216 * tree-vect-loop.cc (vect_transform_loop): Likewise.
6218 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6220 PR tree-optimization/113178
6221 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
6222 alternate exits.
6224 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6226 PR tree-optimization/113237
6227 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
6228 existing LCSSA variable for exit when all exits are early break.
6230 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6232 PR tree-optimization/113137
6233 PR tree-optimization/113136
6234 PR tree-optimization/113172
6235 PR tree-optimization/113178
6236 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6237 Maintain PHIs on inverted loops.
6238 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
6239 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
6240 latch.
6241 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
6243 2024-01-12 Tamar Christina <tamar.christina@arm.com>
6245 PR tree-optimization/113135
6246 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
6247 dependency analysis.
6249 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
6251 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
6252 diagnostics class member name for abort of error.
6254 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
6256 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
6257 format string to %s argument.
6259 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
6260 Jakub Jelinek <jakub@redhat.com>
6262 PR middle-end/113182
6263 * varasm.cc (process_pending_assemble_externals,
6264 assemble_external_libcall): Use targetm.strip_name_encoding
6265 before calling get_identifier.
6267 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6269 PR target/113196
6270 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
6271 New member variable.
6272 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
6273 Declare.
6274 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
6275 * config/aarch64/aarch64-simd.md
6276 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
6277 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
6278 zip2 for zero-extends to...
6279 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
6280 instruction. Fix big-endian handling.
6281 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
6282 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
6283 zip1 for zero-extends to...
6284 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
6285 Fix big-endian handling.
6286 (*aarch64_zip1_uxtl): New pattern.
6287 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
6288 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
6289 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
6290 (aarch64_gen_shareable_zero): Use it.
6291 (aarch64_split_simd_shift_p): New function.
6293 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6295 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
6296 (function_beg_insn): New macro.
6297 * function.cc (expand_function_start): Initialize function_beg_insn.
6299 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6301 PR target/112989
6302 * config/aarch64/aarch64-sve-builtins.h
6303 (function_builder::m_overload_names): Replace with...
6304 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
6305 new global.
6306 (add_overloaded_function): Update accordingly, using get_identifier
6307 to get a GGC-friendly record of the name.
6309 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6311 PR target/112989
6312 * config/aarch64/aarch64-sve-builtins.def: Don't include
6313 aarch64-sve-builtins-sme.def.
6314 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
6315 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
6316 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
6317 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
6318 requires AARCH64_FL_SME2.
6319 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
6320 AARCH64_FL_SME adjustment here.
6321 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
6322 include SME intrinsics.
6323 (sme_function_groups): New array.
6324 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
6325 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
6327 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6329 PR target/113281
6330 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
6331 (struct cpu_vector_cost): Add regmove struct.
6332 (get_vector_costs): Export as global.
6333 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
6334 (costs::add_stmt_cost): Ditto.
6335 * config/riscv/riscv.cc (get_common_costs): Export global function.
6337 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6339 PR tree-optimization/113334
6340 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
6341 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
6342 to determine if number should be extended by all ones rather than zero
6343 extended.
6345 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6347 PR tree-optimization/113330
6348 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
6349 too large size.
6351 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6353 PR tree-optimization/113323
6354 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
6355 check for lhs being large/huge _BitInt not in m_names.
6357 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6359 PR tree-optimization/113316
6360 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
6361 uninitialized large/huge _BitInt arguments to calls.
6363 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6365 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
6366 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
6367 CEIL (TYPE_PRECISION (t), limb_prec).
6368 (bitint_large_huge::handle_cast): Likewise.
6370 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
6372 PR sanitizer/113284
6373 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
6374 Use assemble_function_label_final () for Power ELF V1 ABI.
6375 * output.h (assemble_function_label_final): New function.
6376 * varasm.cc (assemble_function_label_raw): Use
6377 assemble_function_label_final ().
6378 (assemble_function_label_final): New function.
6380 2024-01-12 Richard Biener <rguenther@suse.de>
6382 PR middle-end/113344
6383 * match.pd ((double)float CMP (double)float -> float CMP float):
6384 Perform result type check only for vectors.
6385 * fold-const.cc (fold_binary_loc): Likewise.
6387 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
6389 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
6390 (usdot_prod<mode>): Ditto.
6391 (sdot_prod<mode>): Ditto.
6392 (udot_prod<mode>): Ditto.
6394 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
6396 PR target/113288
6397 * config/i386/i386-c.cc (ix86_target_macros_internal):
6398 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
6400 2024-01-12 Richard Biener <rguenther@suse.de>
6402 PR target/112280
6403 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
6404 Do not generate code when d.testing_p.
6406 2024-01-12 liuhongt <hongtao.liu@intel.com>
6408 PR target/113039
6409 * doc/invoke.texi (fcf-protection=): Update documents.
6411 2024-01-12 Pan Li <pan2.li@intel.com>
6413 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
6414 comments of predicate func riscv_v_ext_mode_p.
6416 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
6418 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
6419 Modify ABI-name length of vfloat16m8_t
6421 2024-01-12 Li Wei <liwei@loongson.cn>
6423 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
6424 Adjust.
6426 2024-01-12 Li Wei <liwei@loongson.cn>
6428 * config/loongarch/loongarch.md (add<mode>3): Removed.
6429 (*addsi3): New.
6430 (addsi3): Ditto.
6431 (adddi3): Ditto.
6432 (*addsi3_extended): Removed.
6433 (addsi3_extended): New.
6435 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
6437 * config/riscv/thead.md: Add limits for splits.
6439 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
6441 PR middle-end/113322
6442 * expr.cc (do_store_flag): Don't try single bit tests with
6443 comparison on vector types.
6445 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
6447 PR tree-optimization/113301
6448 * match.pd (`1/x`): Delay signed case until late.
6450 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
6452 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
6453 and -msp8 to...
6454 (AVR Internal Options): ...this new @subsubsection.
6456 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
6458 PR rtl-optimization/112918
6459 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
6460 (in_class_p): Restrict condition for narrowing class in case of
6461 allow_all_reload_class_changes_p.
6462 (process_alt_operands): Try to match operand without and with
6463 narrowing reg class. Discourage narrowing the class. Finish insn
6464 matching only if there is no class narrowing.
6465 (curr_insn_transform): Pass true to in_class_p for reg operand win.
6467 2024-01-11 Richard Biener <rguenther@suse.de>
6469 PR tree-optimization/112505
6470 * tree-vect-loop.cc (vectorizable_induction): Reject
6471 bit-precision induction.
6473 2024-01-11 Richard Biener <rguenther@suse.de>
6475 PR tree-optimization/113126
6476 * match.pd ((double)float CMP (double)float -> float CMP float):
6477 Make sure the boolean type is the same.
6478 * fold-const.cc (fold_binary_loc): Likewise.
6480 2024-01-11 Richard Biener <rguenther@suse.de>
6482 PR tree-optimization/112636
6483 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
6484 estimate_numbers_of_iterations before querying
6485 get_max_loop_iterations_int.
6486 (pass_ch::execute): Initialize SCEV and loops appropriately.
6488 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
6490 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
6491 Reduced Tiny.
6492 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
6493 * doc/extend.texi (AVR Variable Attributes): Improve documentation
6494 of io, io_low and address attributes.
6495 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
6496 * doc/avr-mmcu.texi: Rebuild.
6498 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
6500 PR target/113233
6501 * config/loongarch/genopts/loongarch.opt.in: Mark options with
6502 the "Save" property.
6503 * config/loongarch/loongarch.opt: Same.
6504 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
6505 according to la_target.
6506 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
6507 RESTORE} for the la_target structure; Rename option conditions
6508 to have the same "la_" prefix.
6509 * config/loongarch/loongarch.h: Same.
6511 2024-01-11 Pan Li <pan2.li@intel.com>
6513 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
6514 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
6516 2024-01-11 Alex Coplan <alex.coplan@arm.com>
6518 PR target/113077
6519 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
6520 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
6521 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
6522 synthesize these if needed. Update caller ...
6523 (ldp_bb_info::fuse_pair): ... here.
6524 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
6525 and either insn is frame-related.
6526 (find_trailing_add): Punt on frame-related insns.
6527 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
6528 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
6530 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
6532 * config/mips/mips.cc (mips_start_function_definition):
6533 Add ATTRIBUTE_UNUSED.
6535 2024-01-11 Richard Biener <rguenther@suse.de>
6537 PR middle-end/112740
6538 * expr.cc (store_constructor): Check the integer vector
6539 mask has a single bit per element before using sign-extension
6540 to expand an uniform vector.
6542 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6544 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
6545 preempt VLS on unknown NITERS loop.
6547 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
6549 * doc/invoke.texi: Add -mevex512.
6551 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
6553 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
6554 (*nor<mode>3): Likewise.
6555 (nor<mode>3): Likewise.
6556 (*negsi2_extended): New template.
6557 (*<optab>si3_internal): Likewise.
6558 (*one_cmplsi2_internal): Likewise.
6559 (*norsi3_internal): Likewise.
6560 (*<optab>nsi_internal): Likewise.
6561 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
6562 modified bit operation to make the optimization work.
6564 2024-01-11 liuhongt <hongtao.liu@intel.com>
6566 PR target/104401
6567 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
6569 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6571 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
6572 (get_vector_costs): Ditto.
6573 (riscv_builtin_vectorization_cost): Ditto.
6575 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6577 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
6579 2024-01-10 Antoni Boucher <bouanto@zoho.com>
6581 PR jit/111396
6582 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
6583 ipa_free_size_summary.
6584 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
6585 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
6586 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
6587 * ipa-prop.h (ipa_prop_cc_finalize): New function.
6588 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
6589 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
6590 ipa_sra_cc_finalize): New functions.
6591 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
6592 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
6593 ipa_sra_cc_finalize
6594 Include ipa-utils.h.
6596 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
6598 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
6599 (th_int_get_save_adjustment): Likewise.
6600 (th_int_adjust_cfi_prologue): Likewise.
6601 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
6602 (TH_INT_INTERRUPT): New macro.
6603 (riscv_expand_prologue): Add the processing of XTheadInt.
6604 (riscv_expand_epilogue): Likewise.
6605 * config/riscv/riscv.h (BITSET_P): Moved to here.
6606 * config/riscv/riscv.md: New unspec.
6607 * config/riscv/thead.cc (th_int_get_mask): New function.
6608 (th_int_get_save_adjustment): Likewise.
6609 (th_int_adjust_cfi_prologue): Likewise.
6610 * config/riscv/thead.md (th_int_push): New pattern.
6611 (th_int_pop): new pattern.
6613 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6615 PR tree-optimization/112468
6616 * doc/sourcebuild.texi: Document ifn_copysign.
6617 * match.pd: Only apply transformation if target supports the IFN.
6619 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
6621 PR tree-optimization/112581
6622 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
6623 mark_ssa_maybe_undefs.
6624 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
6625 variables can not be reassociated.
6626 (init_range_entry): Check for uninitialized variables too.
6627 (init_reassoc): Call mark_ssa_maybe_undefs.
6629 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
6631 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
6632 Also handle sign extension.
6634 2024-01-10 Alex Coplan <alex.coplan@arm.com>
6636 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
6637 to 0.
6638 (-mlate-ldp-fusion): Likewise.
6640 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6642 PR tree-optimization/113287
6643 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
6644 instead of using BRANCH_EDGE to determine true edge.
6646 2024-01-10 Richard Biener <rguenther@suse.de>
6648 PR tree-optimization/113078
6649 * tree-vect-loop.cc (check_reduction_path): Canonicalize
6650 .COND_SUB to .COND_ADD.
6652 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6654 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
6655 Handle prefix mappings before calling find_opt.
6656 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
6657 "-fno-"-prefixed command-line option.
6658 * opts-common.cc (get_option_prefix_remapping): New.
6659 * opts.h (get_option_prefix_remapping): New decl.
6661 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6663 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
6664 m_urlifier to pp_output_formatted_text.
6665 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
6666 (obstack_append_string): New overload, taking a length.
6667 (urlify_quoted_string): Pass in an obstack ptr, rather than using
6668 that of the pp's buffer. Generalize to handle trailing text in
6669 the buffer beyond the run of quoted text.
6670 (class quoting_info): New.
6671 (on_begin_quote): New.
6672 (on_end_quote): New.
6673 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
6674 it to calls to on_begin_quote and on_end_quote.
6675 (struct auto_obstack): New.
6676 (quoting_info::handle_phase_3): New.
6677 (pp_output_formatted_text): Add urlifier param. Use it if there
6678 is deferred urlification. Delete m_quotes.
6679 (selftest::pp_printf_with_urlifier): Pass urlifier to
6680 pp_output_formatted_text.
6681 (selftest::test_urlification): Update results for the existing
6682 case of quoted text stradding chunks; add more such test cases.
6683 * pretty-print.h (class quoting_info): New forward decl.
6684 (chunk_info::m_quotes): New field.
6685 (pp_output_formatted_text): Add optional urlifier param.
6687 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6689 * pretty-print.cc (selftest::test_pp_format): Add selftest
6690 coverage for numbered args.
6692 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6694 PR tree-optimization/113144
6695 PR tree-optimization/113145
6696 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6697 Update all BB that the original exits dominated.
6699 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
6701 * dwarf2out.cc (modified_type_die): Extend the support of reverse
6702 storage order to enumeration types if -gstrict-dwarf is not passed.
6703 (gen_enumeration_type_die): Add REVERSE parameter and generate the
6704 DIE immediately after the existing one if it is true.
6705 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
6706 call to gen_enumeration_type_die.
6707 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
6708 first recursive call as well as the call to gen_tagged_type_die.
6709 (gen_type_die): Add REVERSE parameter and pass it in the call to
6710 gen_type_die_with_usage.
6712 2024-01-10 Jakub Jelinek <jakub@redhat.com>
6714 PR tree-optimization/113120
6715 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
6716 with root->size TYPE_PRECISION don't build anything new.
6717 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
6718 rather than build_nonstandard_integer_type.
6720 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
6722 * config/i386/i386.opt: Adjust document.
6723 * doc/invoke.texi: Add description for
6724 -mapx-inline-asm-use-gpr32.
6726 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6728 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
6729 (avg<v_double_trunc>3_floor): New pattern.
6730 (<u>avg<v_double_trunc>3_ceil): Remove.
6731 (avg<v_double_trunc>3_ceil): New pattern.
6732 (uavg<mode>3_floor): Ditto.
6733 (uavg<mode>3_ceil): Ditto.
6734 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
6735 (enum insn_type): Ditto.
6736 * config/riscv/riscv-v.cc: Ditto.
6737 * config/riscv/vector-iterators.md (ashiftrt): Remove.
6738 (ASHIFTRT): Ditto.
6739 * config/riscv/vector.md: Add VLS modes.
6741 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6743 PR target/111480
6744 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
6745 (vczlsbb_char): New int attribute.
6746 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
6747 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
6748 (*vctzlsbb_zext_<mode>): Rename to ...
6749 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
6750 cover vclzlsbb.
6752 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6754 PR target/112606
6755 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
6756 of the last argument from altivec_register_operand to any_operand. If
6757 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
6758 otherwise if it doesn't satisfy altivec_register_operand, force it to
6759 REG using copy_to_mode_reg.
6761 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6763 PR middle-end/113100
6764 * builtins.cc (expand_builtin_stack_address): Guard stack point
6765 adjustment with SPARC_STACK_BOUNDARY_HACK.
6767 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6769 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
6770 argument string definitions.
6771 * config/loongarch/loongarch-str.h: Same.
6772 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
6773 as aliases to -mexplicit-relocs={always,none}
6774 * config/loongarch/loongarch.opt: Regenerate.
6775 * config/loongarch/loongarch.cc: Same.
6777 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6779 * config/loongarch/loongarch-def.h: Define constants with
6780 enums instead of Macros.
6782 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6784 * config/loongarch/genopts/loongarch-strings: Rename.
6785 * config/loongarch/genopts/loongarch.opt.in: Same.
6786 * config/loongarch/loongarch-cpu.cc: Same.
6787 * config/loongarch/loongarch-def.cc: Same.
6788 * config/loongarch/loongarch-def.h: Same.
6789 * config/loongarch/loongarch-opts.cc: Same.
6790 * config/loongarch/loongarch-opts.h: Same.
6791 * config/loongarch/loongarch-str.h: Same.
6792 * config/loongarch/loongarch.opt: Same.
6794 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6796 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
6797 variable with the common la_ prefix.
6798 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
6799 flags as saved using TargetVariable.
6800 * config/loongarch/loongarch.opt: Same.
6801 * config/loongarch/loongarch-def.h: Define evolution_set to
6802 mark changes to the -march default.
6803 * config/loongarch/loongarch-driver.cc: Same.
6804 * config/loongarch/loongarch-opts.cc: Same.
6805 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
6806 conditions around the la_target structure.
6807 * config/loongarch/loongarch.cc: Same.
6808 * config/loongarch/loongarch.md: Same.
6809 * config/loongarch/loongarch-builtins.cc: Same.
6810 * config/loongarch/loongarch-c.cc: Same.
6811 * config/loongarch/lasx.md: Same.
6812 * config/loongarch/lsx.md: Same.
6813 * config/loongarch/sync.md: Same.
6815 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
6817 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
6818 no less.
6820 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
6822 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
6824 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6826 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
6827 restart_loop.
6828 (vectorizable_live_operation): Likewise.
6830 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6832 PR tree-optimization/113199
6833 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
6834 BIT_FIELD_REF.
6836 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6838 PR target/113270
6839 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
6840 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
6841 GTY(()) declaration before the definition, drop GTY(()) drom the
6842 definition.
6844 2024-01-09 Richard Biener <rguenther@suse.de>
6846 PR tree-optimization/113026
6847 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
6848 redundant and wrong niter bound setting. Move niter
6849 bound adjustment down.
6851 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6853 PR middle-end/113163
6854 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
6855 Reject non-linear inductions that aren't supported.
6857 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6859 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
6860 left shift implementation strategies.
6861 (arc_shift_info): Type for each entry of the shift strategy table.
6862 (arc_shift_context_idx): Return a integer value for each code
6863 generation context, used as an index
6864 (arc_ashl_alg): Table indexed by context and shifted bit count.
6865 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
6866 left shift implementation.
6867 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
6868 provide accurate costs, when optimizing for speed or size.
6870 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6872 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
6874 2024-01-09 Julian Brown <julian@codesourcery.com>
6876 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
6877 processed out before gimplification.
6878 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
6879 * tree.def (OMP_ARRAY_SECTION): New tree code.
6881 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6883 PR tree-optimization/113210
6884 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
6885 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
6886 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
6887 minus 1.
6889 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
6891 PR rtl-optimization/113140
6892 * reorg.cc (fill_slots_from_thread): If we are to branch after the
6893 last instruction of the function, create an end label.
6895 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6896 Hongtao Liu <hongtao.liu@intel.com>
6898 PR target/112992
6899 * config/i386/i386-expand.cc
6900 (ix86_convert_const_wide_int_to_broadcast): Allow call to
6901 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
6902 (ix86_broadcast_from_constant): Revert recent change; Return a
6903 suitable MEMREF independently of mode/target combinations.
6904 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
6905 to decide whether expansion is possible/preferrable. Only try
6906 forcing DImode constants to memory (and trying again) if calling
6907 ix86_expand_vector_init_duplicate fails with an DImode immediate
6908 constant.
6909 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
6910 V4SImode for suitable immediate constants.
6911 <case E_V4DImode>: Try using V8SImode for suitable constants.
6912 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
6913 <case E_V2HImode>: Likewise.
6914 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
6915 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
6916 <label widen>: Handle CONT_INTs via simplify_binary_operation.
6917 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
6918 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
6919 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
6920 (ix86_expand_vector_init): Move try using a broadcast for all_same
6921 with ix86_expand_vector_init_duplicate before using constant pool.
6923 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6925 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
6927 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6929 * config/arm/arm-cpus.in (cortex-m52): New cpu.
6930 * config/arm/arm-tables.opt: Regenerate.
6931 * config/arm/arm-tune.md: Regenerate.
6933 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
6935 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
6936 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
6937 (@vec_concatz<mode>): New insn pattern.
6938 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
6939 Handle VALS containing two vectors.
6941 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6943 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
6944 (vundefined): Ditto.
6946 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
6948 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6949 Add new function_base for crypto vector.
6950 (class bitmanip): Ditto.
6951 (class b_reverse):Ditto.
6952 (class vwsll): Ditto.
6953 (class clmul): Ditto.
6954 (class vg_nhab): Ditto.
6955 (class crypto_vv):Ditto.
6956 (class crypto_vi):Ditto.
6957 (class vaeskf2_vsm3c):Ditto.
6958 (class vsm3me): Ditto.
6959 (BASE): Add BASE declaration for crypto vector.
6960 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6961 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6962 Add crypto vector intrinsic definition.
6963 (vbrev): Ditto.
6964 (vclz): Ditto.
6965 (vctz): Ditto.
6966 (vwsll): Ditto.
6967 (vandn): Ditto.
6968 (vbrev8): Ditto.
6969 (vrev8): Ditto.
6970 (vrol): Ditto.
6971 (vror): Ditto.
6972 (vclmul): Ditto.
6973 (vclmulh): Ditto.
6974 (vghsh): Ditto.
6975 (vgmul): Ditto.
6976 (vaesef): Ditto.
6977 (vaesem): Ditto.
6978 (vaesdf): Ditto.
6979 (vaesdm): Ditto.
6980 (vaesz): Ditto.
6981 (vaeskf1): Ditto.
6982 (vaeskf2): Ditto.
6983 (vsha2ms): Ditto.
6984 (vsha2ch): Ditto.
6985 (vsha2cl): Ditto.
6986 (vsm4k): Ditto.
6987 (vsm4r): Ditto.
6988 (vsm3me): Ditto.
6989 (vsm3c): Ditto.
6990 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6991 Add new function_shape for crypto vector.
6992 (struct crypto_vi_def): Ditto.
6993 (struct crypto_vv_no_op_type_def): Ditto.
6994 (SHAPE): Add SHAPE declaration of crypto vector.
6995 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6996 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6997 Add new data type for crypto vector.
6998 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6999 (vuint32mf2_t): Ditto.
7000 (vuint32m1_t): Ditto.
7001 (vuint32m2_t): Ditto.
7002 (vuint32m4_t): Ditto.
7003 (vuint32m8_t): Ditto.
7004 (vuint64m1_t): Ditto.
7005 (vuint64m2_t): Ditto.
7006 (vuint64m4_t): Ditto.
7007 (vuint64m8_t): Ditto.
7008 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7009 Add new data struct for crypto vector.
7010 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7011 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7012 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7014 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
7016 PR sanitizer/113251
7017 * varasm.cc (assemble_function_label_raw): Do not call
7018 asan_function_start () without the current function.
7020 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
7022 PR target/113225
7023 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
7024 extern and kernel_helper attributed function decls.
7026 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
7028 * btfout.cc (output_btf_strs): Changed.
7030 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
7032 * config/gcn/mkoffload.cc (main): Handle gfx1100
7033 when setting the default XNACK.
7035 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
7037 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
7038 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
7039 (ASM_SPEC): Handle gfx1100.
7040 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
7041 (enum gcn_isa): Add ISA_RDNA3.
7042 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
7043 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
7044 * config/gcn/gcn.cc (gcn_option_override,
7045 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
7046 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
7047 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
7048 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
7049 with gfx1100.
7050 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
7051 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
7052 __gfx1100__.
7053 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
7054 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
7055 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
7056 (isa_has_combined_avgprs, main): Handle gfx1100.
7057 * config/gcn/t-omp-device (isa): Add gfx1100.
7059 2024-01-08 Richard Biener <rguenther@suse.de>
7061 * doc/invoke.texi (-mmovbe): Clarify.
7063 2024-01-08 Richard Biener <rguenther@suse.de>
7065 PR tree-optimization/113026
7066 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
7067 Avoid an epilog in more cases.
7068 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
7069 epilogues niter upper bounds and estimates.
7071 2024-01-08 Jakub Jelinek <jakub@redhat.com>
7073 PR tree-optimization/113228
7074 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
7076 2024-01-08 Jakub Jelinek <jakub@redhat.com>
7078 PR tree-optimization/113120
7079 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
7080 large _BitInt zero INTEGER_CST PHI argument.
7082 2024-01-08 Jakub Jelinek <jakub@redhat.com>
7084 PR tree-optimization/113119
7085 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
7086 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
7087 is before REALPART_EXPR.
7089 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
7091 PR target/112952
7092 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
7093 range when diagnosing attribute "io" and "io_low" are out of range.
7094 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
7095 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
7096 in contexts other than static storage.
7097 (avr_asm_output_aligned_decl_common): Move output of decls with
7098 attribute "address", "io", and "io_low" to...
7099 (avr_output_addr_attrib): ...this new function.
7100 (avr_asm_asm_output_aligned_bss): Remove output for decls with
7101 attribute "address", "io", and "io_low".
7102 (avr_encode_section_info): Rectify handling of decls with attribute
7103 "address", "io", and "io_low".
7105 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
7107 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
7108 (elf_flags): Remove XNACK from the default value.
7109 (main): Set a default XNACK according to the arch.
7111 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
7113 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
7114 (process_asm): Don't count avgprs.
7116 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
7118 * config/i386/i386.opt: Add supported sub-features.
7119 * doc/extend.texi: Add description for target attribute.
7121 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
7123 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
7125 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
7126 Uros Bizjak <ubizjak@gmail.com>
7128 PR target/113231
7129 * config/i386/i386-features.cc (compute_convert_gain): Include
7130 the overhead of explicit load and store (movd) instructions when
7131 converting non-store scalar operations with memory destinations.
7132 Various indentation whitespace fixes.
7134 2024-01-07 Tamar Christina <tamar.christina@arm.com>
7136 * config/arm/neon.md (cbranch<mode>4): New.
7138 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7140 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
7142 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
7144 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
7146 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7148 PR target/113248
7149 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
7150 Update the MAX_SEW.
7152 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7154 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
7155 (variable_vectorized_p): Teach loop invariant.
7156 (has_unexpected_spills_p): Ditto.
7158 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7160 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
7161 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
7162 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
7164 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
7166 PR target/113104
7167 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
7168 (aarch64-vect-compare-costs): ...this.
7169 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
7170 Replace with...
7171 (-param=aarch64-vect-compare-costs=): ...this new param.
7172 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
7173 Don't disable it when vectorizing for Advanced SIMD only.
7174 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
7175 whenever aarch64_vect_compare_costs is true.
7177 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
7179 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
7180 Modify the method of determining the memory offset of [x]vld/[x]vst.
7181 (lasx_mxst_<lasxfmt_f>): Likewise.
7182 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
7183 (loongarch_address_insns): Likewise.
7184 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
7185 (lsx_st_<lsxfmt_f>): Likewise.
7186 * config/loongarch/predicates.md (aq10b_operand): Likewise.
7187 (aq10h_operand): Likewise.
7188 (aq10w_operand): Likewise.
7189 (aq10d_operand): Likewise.
7191 2024-01-05 Alex Coplan <alex.coplan@arm.com>
7193 PR target/113217
7194 * config/aarch64/aarch64-ldp-fusion.cc
7195 (ldp_bb_info::try_fuse_pair): If the second access can throw,
7196 narrow the move range to exactly that insn.
7198 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
7200 * asan.cc (asan_function_start): Drop switch_to_section ().
7201 (asan_emit_stack_protection): Set .LASANPC alignment.
7202 * config/i386/i386.cc: Use assemble_function_label_raw ()
7203 instead of ASM_OUTPUT_LABEL ().
7204 * config/s390/s390.cc (s390_asm_output_function_label):
7205 Likewise.
7206 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
7207 * final.cc (final_start_function_1): Drop
7208 asan_function_start ().
7209 * output.h (assemble_function_label_raw): New function.
7210 * varasm.cc (assemble_function_label_raw): Likewise.
7212 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
7214 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
7215 Use ASM_OUTPUT_FUNCTION_LABEL ().
7216 * config/alpha/alpha.cc (alpha_start_function): Likewise.
7217 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
7218 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
7219 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
7220 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
7221 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
7222 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
7223 * config/ia64/ia64.cc (ia64_start_function): Likewise.
7224 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
7225 Likewise.
7226 * config/microblaze/microblaze.cc (microblaze_function_prologue):
7227 Likewise.
7228 * config/mips/mips.cc (mips_start_unique_function): Return the
7229 tree.
7230 (mips_start_function_definition): Use
7231 ASM_OUTPUT_FUNCTION_LABEL ().
7232 (mips_finish_stub): Pass the tree to
7233 mips_start_function_definition ().
7234 (mips16_build_function_stub): Likewise.
7235 (mips16_build_call_stub): Likewise.
7236 (mips_output_function_prologue): Likewise.
7237 * config/pa/pa.cc (pa_output_function_label): Use
7238 ASM_OUTPUT_FUNCTION_LABEL ().
7239 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
7240 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
7241 Likewise.
7242 (rs6000_xcoff_declare_function_name): Likewise.
7244 2024-01-05 Jakub Jelinek <jakub@redhat.com>
7246 PR tree-optimization/113201
7247 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
7248 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
7250 2024-01-05 Jakub Jelinek <jakub@redhat.com>
7252 PR tree-optimization/90693
7253 * tree-ssa-math-opts.cc (match_single_bit_test): If
7254 tree_expr_nonzero_p (arg), remember it in the second argument to
7255 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
7256 arg ^ (arg - 1) > arg - 1.
7257 * internal-fn.cc (expand_POPCOUNT): If second argument to
7258 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
7259 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
7261 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
7263 * config/riscv/riscv-v.cc (expand_load_store):
7264 Remove `value`.
7265 (expand_cond_len_op): Ditto.
7266 (expand_gather_scatter): Ditto.
7267 (expand_lanes_load_store): Ditto.
7268 (expand_fold_extract_last): Ditto.
7270 2024-01-05 Pan Li <pan2.li@intel.com>
7272 Revert:
7273 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
7275 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
7276 Add new function_base for crypto vector.
7277 (class bitmanip): Ditto.
7278 (class b_reverse):Ditto.
7279 (class vwsll): Ditto.
7280 (class clmul): Ditto.
7281 (class vg_nhab): Ditto.
7282 (class crypto_vv):Ditto.
7283 (class crypto_vi):Ditto.
7284 (class vaeskf2_vsm3c):Ditto.
7285 (class vsm3me): Ditto.
7286 (BASE): Add BASE declaration for crypto vector.
7287 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
7288 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
7289 Add crypto vector intrinsic definition.
7290 (vbrev): Ditto.
7291 (vclz): Ditto.
7292 (vctz): Ditto.
7293 (vwsll): Ditto.
7294 (vandn): Ditto.
7295 (vbrev8): Ditto.
7296 (vrev8): Ditto.
7297 (vrol): Ditto.
7298 (vror): Ditto.
7299 (vclmul): Ditto.
7300 (vclmulh): Ditto.
7301 (vghsh): Ditto.
7302 (vgmul): Ditto.
7303 (vaesef): Ditto.
7304 (vaesem): Ditto.
7305 (vaesdf): Ditto.
7306 (vaesdm): Ditto.
7307 (vaesz): Ditto.
7308 (vaeskf1): Ditto.
7309 (vaeskf2): Ditto.
7310 (vsha2ms): Ditto.
7311 (vsha2ch): Ditto.
7312 (vsha2cl): Ditto.
7313 (vsm4k): Ditto.
7314 (vsm4r): Ditto.
7315 (vsm3me): Ditto.
7316 (vsm3c): Ditto.
7317 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
7318 Add new function_shape for crypto vector.
7319 (struct crypto_vi_def): Ditto.
7320 (struct crypto_vv_no_op_type_def): Ditto.
7321 (SHAPE): Add SHAPE declaration of crypto vector.
7322 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
7323 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
7324 Add new data type for crypto vector.
7325 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7326 (vuint32mf2_t): Ditto.
7327 (vuint32m1_t): Ditto.
7328 (vuint32m2_t): Ditto.
7329 (vuint32m4_t): Ditto.
7330 (vuint32m8_t): Ditto.
7331 (vuint64m1_t): Ditto.
7332 (vuint64m2_t): Ditto.
7333 (vuint64m4_t): Ditto.
7334 (vuint64m8_t): Ditto.
7335 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7336 Add new data struct for crypto vector.
7337 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7338 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7339 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7341 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
7343 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
7344 Add new function_base for crypto vector.
7345 (class bitmanip): Ditto.
7346 (class b_reverse):Ditto.
7347 (class vwsll): Ditto.
7348 (class clmul): Ditto.
7349 (class vg_nhab): Ditto.
7350 (class crypto_vv):Ditto.
7351 (class crypto_vi):Ditto.
7352 (class vaeskf2_vsm3c):Ditto.
7353 (class vsm3me): Ditto.
7354 (BASE): Add BASE declaration for crypto vector.
7355 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
7356 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
7357 Add crypto vector intrinsic definition.
7358 (vbrev): Ditto.
7359 (vclz): Ditto.
7360 (vctz): Ditto.
7361 (vwsll): Ditto.
7362 (vandn): Ditto.
7363 (vbrev8): Ditto.
7364 (vrev8): Ditto.
7365 (vrol): Ditto.
7366 (vror): Ditto.
7367 (vclmul): Ditto.
7368 (vclmulh): Ditto.
7369 (vghsh): Ditto.
7370 (vgmul): Ditto.
7371 (vaesef): Ditto.
7372 (vaesem): Ditto.
7373 (vaesdf): Ditto.
7374 (vaesdm): Ditto.
7375 (vaesz): Ditto.
7376 (vaeskf1): Ditto.
7377 (vaeskf2): Ditto.
7378 (vsha2ms): Ditto.
7379 (vsha2ch): Ditto.
7380 (vsha2cl): Ditto.
7381 (vsm4k): Ditto.
7382 (vsm4r): Ditto.
7383 (vsm3me): Ditto.
7384 (vsm3c): Ditto.
7385 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
7386 Add new function_shape for crypto vector.
7387 (struct crypto_vi_def): Ditto.
7388 (struct crypto_vv_no_op_type_def): Ditto.
7389 (SHAPE): Add SHAPE declaration of crypto vector.
7390 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
7391 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
7392 Add new data type for crypto vector.
7393 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7394 (vuint32mf2_t): Ditto.
7395 (vuint32m1_t): Ditto.
7396 (vuint32m2_t): Ditto.
7397 (vuint32m4_t): Ditto.
7398 (vuint32m8_t): Ditto.
7399 (vuint64m1_t): Ditto.
7400 (vuint64m2_t): Ditto.
7401 (vuint64m4_t): Ditto.
7402 (vuint64m8_t): Ditto.
7403 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7404 Add new data struct for crypto vector.
7405 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7406 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7407 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7409 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7411 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7413 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
7415 PR tree-optimization/113186
7416 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
7417 Match `^` with the `==` for 1bit integral types.
7418 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
7419 integral types.
7421 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7423 * toplev.cc (general_init): Pass lang_mask to urlifier.
7425 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7427 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
7428 param.
7429 (diagnostic_context::make_option_url): Update for lang_mask param.
7430 * gcc-urlifier.cc: Include "opts.h" and "options.h".
7431 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
7432 (gcc_urlifier::m_lang_mask): New field.
7433 (doc_urls): Make static.
7434 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
7435 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7436 Look for an option by name before trying a binary search in
7437 doc_urls.
7438 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7439 (gcc_urlifier::get_url_suffix_for_option): New.
7440 (make_gcc_urlifier): Add lang_mask param.
7441 (selftest::gcc_urlifier_cc_tests): Update for above changes.
7442 Verify that a URL is found for "-fpack-struct".
7443 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
7444 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
7445 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
7446 to make_gcc_urlifier.
7447 * opts-diagnostic.h (get_option_url): Add lang_mask param.
7448 * opts.cc (get_option_html_page): Remove special-casing for
7449 analyzer and LTO.
7450 (get_option_url_suffix): New.
7451 (get_option_url): Reimplement.
7452 (selftest::test_get_option_html_page): Rename to...
7453 (selftest::test_get_option_url_suffix): ...this and update for
7454 above changes.
7455 (selftest::opts_cc_tests): Update for renaming.
7456 * opts.h: Include "rich-location.h".
7457 (get_option_url_suffix): New decl.
7459 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7461 * Makefile.in (ALL_OPT_URL_FILES): New.
7462 (GCC_OBJS): Add options-urls.o.
7463 (OBJS): Likewise.
7464 (OBJS-libcommon): Likewise.
7465 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
7466 inputs to opt-gather.awk.
7467 (options-urls.cc): New Makefile target.
7468 * opt-functions.awk (url_suffix): New function.
7469 (lang_url_suffix): New function.
7470 * options-urls-cc-gen.awk: New file.
7471 * opts.h (get_opt_url_suffix): New decl.
7473 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7475 * params.opt.urls: New file, autogenerated by
7476 regenerate-opt-urls.py.
7478 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7480 * common.opt.urls: New file, autogenerated by
7481 regenerate-opt-urls.py.
7482 * config/aarch64/aarch64.opt.urls: Likewise.
7483 * config/alpha/alpha.opt.urls: Likewise.
7484 * config/alpha/elf.opt.urls: Likewise.
7485 * config/arc/arc-tables.opt.urls: Likewise.
7486 * config/arc/arc.opt.urls: Likewise.
7487 * config/arm/arm-tables.opt.urls: Likewise.
7488 * config/arm/arm.opt.urls: Likewise.
7489 * config/arm/vxworks.opt.urls: Likewise.
7490 * config/avr/avr.opt.urls: Likewise.
7491 * config/bpf/bpf.opt.urls: Likewise.
7492 * config/c6x/c6x-tables.opt.urls: Likewise.
7493 * config/c6x/c6x.opt.urls: Likewise.
7494 * config/cris/cris.opt.urls: Likewise.
7495 * config/cris/elf.opt.urls: Likewise.
7496 * config/csky/csky.opt.urls: Likewise.
7497 * config/csky/csky_tables.opt.urls: Likewise.
7498 * config/darwin.opt.urls: Likewise.
7499 * config/dragonfly.opt.urls: Likewise.
7500 * config/epiphany/epiphany.opt.urls: Likewise.
7501 * config/fr30/fr30.opt.urls: Likewise.
7502 * config/freebsd.opt.urls: Likewise.
7503 * config/frv/frv.opt.urls: Likewise.
7504 * config/ft32/ft32.opt.urls: Likewise.
7505 * config/fused-madd.opt.urls: Likewise.
7506 * config/g.opt.urls: Likewise.
7507 * config/gcn/gcn.opt.urls: Likewise.
7508 * config/gnu-user.opt.urls: Likewise.
7509 * config/h8300/h8300.opt.urls: Likewise.
7510 * config/hpux11.opt.urls: Likewise.
7511 * config/i386/cygming.opt.urls: Likewise.
7512 * config/i386/cygwin.opt.urls: Likewise.
7513 * config/i386/djgpp.opt.urls: Likewise.
7514 * config/i386/i386.opt.urls: Likewise.
7515 * config/i386/mingw-w64.opt.urls: Likewise.
7516 * config/i386/mingw.opt.urls: Likewise.
7517 * config/i386/nto.opt.urls: Likewise.
7518 * config/ia64/ia64.opt.urls: Likewise.
7519 * config/ia64/ilp32.opt.urls: Likewise.
7520 * config/ia64/vms.opt.urls: Likewise.
7521 * config/iq2000/iq2000.opt.urls: Likewise.
7522 * config/linux-android.opt.urls: Likewise.
7523 * config/linux.opt.urls: Likewise.
7524 * config/lm32/lm32.opt.urls: Likewise.
7525 * config/loongarch/loongarch.opt.urls: Likewise.
7526 * config/lynx.opt.urls: Likewise.
7527 * config/m32c/m32c.opt.urls: Likewise.
7528 * config/m32r/m32r.opt.urls: Likewise.
7529 * config/m68k/ieee.opt.urls: Likewise.
7530 * config/m68k/m68k-tables.opt.urls: Likewise.
7531 * config/m68k/m68k.opt.urls: Likewise.
7532 * config/m68k/uclinux.opt.urls: Likewise.
7533 * config/mcore/mcore.opt.urls: Likewise.
7534 * config/microblaze/microblaze.opt.urls: Likewise.
7535 * config/mips/mips-tables.opt.urls: Likewise.
7536 * config/mips/mips.opt.urls: Likewise.
7537 * config/mips/sde.opt.urls: Likewise.
7538 * config/mmix/mmix.opt.urls: Likewise.
7539 * config/mn10300/mn10300.opt.urls: Likewise.
7540 * config/moxie/moxie.opt.urls: Likewise.
7541 * config/msp430/msp430.opt.urls: Likewise.
7542 * config/nds32/nds32-elf.opt.urls: Likewise.
7543 * config/nds32/nds32-linux.opt.urls: Likewise.
7544 * config/nds32/nds32.opt.urls: Likewise.
7545 * config/netbsd-elf.opt.urls: Likewise.
7546 * config/netbsd.opt.urls: Likewise.
7547 * config/nios2/elf.opt.urls: Likewise.
7548 * config/nios2/nios2.opt.urls: Likewise.
7549 * config/nvptx/nvptx-gen.opt.urls: Likewise.
7550 * config/nvptx/nvptx.opt.urls: Likewise.
7551 * config/openbsd.opt.urls: Likewise.
7552 * config/or1k/elf.opt.urls: Likewise.
7553 * config/or1k/or1k.opt.urls: Likewise.
7554 * config/pa/pa-hpux.opt.urls: Likewise.
7555 * config/pa/pa-hpux1010.opt.urls: Likewise.
7556 * config/pa/pa-hpux1111.opt.urls: Likewise.
7557 * config/pa/pa-hpux1131.opt.urls: Likewise.
7558 * config/pa/pa.opt.urls: Likewise.
7559 * config/pa/pa64-hpux.opt.urls: Likewise.
7560 * config/pdp11/pdp11.opt.urls: Likewise.
7561 * config/pru/pru.opt.urls: Likewise.
7562 * config/riscv/riscv.opt.urls: Likewise.
7563 * config/rl78/rl78.opt.urls: Likewise.
7564 * config/rpath.opt.urls: Likewise.
7565 * config/rs6000/476.opt.urls: Likewise.
7566 * config/rs6000/aix64.opt.urls: Likewise.
7567 * config/rs6000/darwin.opt.urls: Likewise.
7568 * config/rs6000/linux64.opt.urls: Likewise.
7569 * config/rs6000/rs6000-tables.opt.urls: Likewise.
7570 * config/rs6000/rs6000.opt.urls: Likewise.
7571 * config/rs6000/sysv4.opt.urls: Likewise.
7572 * config/rtems.opt.urls: Likewise.
7573 * config/rx/elf.opt.urls: Likewise.
7574 * config/rx/rx.opt.urls: Likewise.
7575 * config/s390/s390.opt.urls: Likewise.
7576 * config/s390/tpf.opt.urls: Likewise.
7577 * config/sh/sh.opt.urls: Likewise.
7578 * config/sh/superh.opt.urls: Likewise.
7579 * config/sol2.opt.urls: Likewise.
7580 * config/sparc/long-double-switch.opt.urls: Likewise.
7581 * config/sparc/sparc.opt.urls: Likewise.
7582 * config/stormy16/stormy16.opt.urls: Likewise.
7583 * config/v850/v850.opt.urls: Likewise.
7584 * config/vax/elf.opt.urls: Likewise.
7585 * config/vax/vax.opt.urls: Likewise.
7586 * config/visium/visium.opt.urls: Likewise.
7587 * config/vms/vms.opt.urls: Likewise.
7588 * config/vxworks-smp.opt.urls: Likewise.
7589 * config/vxworks.opt.urls: Likewise.
7590 * config/xtensa/elf.opt.urls: Likewise.
7591 * config/xtensa/uclinux.opt.urls: Likewise.
7592 * config/xtensa/xtensa.opt.urls: Likewise.
7593 * config/bfin/bfin.opt.urls: New file.
7595 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7597 * Makefile.in (OPT_URLS_HTML_DEPS): New.
7598 (regenerate-opt-urls): New target.
7599 (regenerate-opt-urls-unit-test): New target.
7600 * doc/options.texi (Option properties): Add UrlSuffix and
7601 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
7602 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
7603 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
7604 and Makefile.in's OPT_URLS_HTML_DEPS.
7605 (Anatomy of a Target Back End): Add
7606 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
7607 * regenerate-opt-urls.py: New file.
7609 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7611 * diagnostic-format-sarif.cc
7612 (sarif_builder::make_logical_location_object): Convert to...
7613 (make_sarif_logical_location_object): ...this.
7614 (sarif_builder::set_any_logical_locs_arr): Update for above
7615 change.
7616 (sarif_builder::make_thread_flow_location_object): Call
7617 maybe_add_sarif_properties on each diagnostic_event.
7618 * diagnostic-format-sarif.h (class logical_location): New forward
7619 decl.
7620 (make_sarif_logical_location_object): New decl.
7621 * diagnostic-path.h (class sarif_object): New forward decl.
7622 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
7624 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
7625 Patrick Lin <patrick@andestech.com>
7626 Rufus Chen <rufus@andestech.com>
7627 Monk Chiang <monk.chiang@sifive.com>
7629 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
7630 with Nan-boxing value.
7631 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
7633 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
7634 Jeff Law <jlaw@ventanamicro.com>
7636 PR rtl-optimization/104914
7637 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
7638 a sign or zero extension is only required if the modified field
7639 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
7640 targets, don't refer to the temporarily incorrectly extended value
7641 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
7643 2024-01-04 Pan Li <pan2.li@intel.com>
7645 Revert:
7646 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7648 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7650 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7652 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7654 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
7656 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
7657 offset of fcsr.
7659 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7661 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
7662 (compute_nregs_for_mode): Refine LMUL.
7663 (max_number_of_live_regs): Ditto.
7664 (compute_estimated_lmul): Ditto.
7665 (has_unexpected_spills_p): Ditto.
7667 2024-01-04 Li Wei <liwei@loongson.cn>
7669 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
7670 Remove useless forward declaration.
7671 (loongarch_is_even_extraction): Remove useless forward declaration.
7672 (loongarch_try_expand_lsx_vshuf_const): Removed.
7673 (loongarch_expand_vec_perm_const_1): Merged.
7674 (loongarch_is_double_duplicate): Removed.
7675 (loongarch_is_center_extraction): Ditto.
7676 (loongarch_is_reversing_permutation): Ditto.
7677 (loongarch_is_di_misalign_extract): Ditto.
7678 (loongarch_is_si_misalign_extract): Ditto.
7679 (loongarch_is_lasx_lowpart_extract): Ditto.
7680 (loongarch_is_op_reverse_perm): Ditto.
7681 (loongarch_is_single_op_perm): Ditto.
7682 (loongarch_is_divisible_perm): Ditto.
7683 (loongarch_is_triple_stride_extract): Ditto.
7684 (loongarch_expand_vec_perm_const_2): Merged.
7685 (loongarch_expand_vec_perm_const): New.
7686 (loongarch_vectorize_vec_perm_const): Adjust.
7688 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
7690 * omp-general.cc: Fix comment typos and misplaced/confusing
7691 comments. Delete redundant include of omp-general.h.
7693 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7695 PR rtl-optimization/104914
7696 * config/mips/mips.md (insqisi_extended): New patterns.
7697 (inshisi_extended): Ditto.
7699 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7701 * config/mips/mips.cc (mips_insn_cost): New function.
7703 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7705 * config/mips/mips.md (perf_ratio): New attribute.
7707 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7709 PR target/113206
7710 PR target/113209
7711 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
7712 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
7713 blocks belong to infinite loop.
7714 (pre_vsetvl::emit_vsetvl): Remove fake edges.
7715 * config/riscv/t-riscv: Add a new include file.
7717 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7719 * config/riscv/vector.md: Fix indent.
7721 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7723 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
7724 OMP_CLAUSE__SIMDUID_.
7725 * tree.cc (omp_clause_num_ops): Update position of entry for
7726 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
7727 (omp_clause_code_name): Likewise.
7729 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7731 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
7732 printing of FUNC_MAP/IND_FUNC_MAP labels.
7734 2024-01-03 Jakub Jelinek <jakub@redhat.com>
7736 * gcc.cc (process_command): Update copyright notice dates.
7737 * gcov-dump.cc (print_version): Ditto.
7738 * gcov.cc (print_version): Ditto.
7739 * gcov-tool.cc (print_version): Ditto.
7740 * gengtype.cc (create_file): Ditto.
7741 * doc/cpp.texi: Bump @copying's copyright year.
7742 * doc/cppinternals.texi: Ditto.
7743 * doc/gcc.texi: Ditto.
7744 * doc/gccint.texi: Ditto.
7745 * doc/gcov.texi: Ditto.
7746 * doc/install.texi: Ditto.
7747 * doc/invoke.texi: Ditto.
7749 2024-01-03 Xi Ruoyao <xry111@xry111.site>
7751 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
7752 (fmin<mode>3): Likewise.
7753 (reduc_fmax_scal_<mode>3): New define_expand.
7754 (reduc_fmin_scal_<mode>3): Likewise.
7756 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7758 PR target/113112
7759 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
7760 (max_number_of_live_regs): Ditto.
7761 (has_unexpected_spills_p): Ditto.
7763 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
7764 Jin Ma <jinma@linux.alibaba.com>
7765 Xianmiao Qu <cooper.qu@linux.alibaba.com>
7766 Christoph Müllner <christoph.muellner@vrull.eu>
7768 * config/riscv/vector.md:
7769 Use vector_length_operand for vsetvl patterns.
7771 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7773 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
7774 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
7776 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
7778 * config/aarch64/aarch64-tuning-flags.def
7779 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
7780 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
7781 * config/aarch64/aarch64.cc
7782 (aarch64_override_options_internal): Set
7783 param_fully_pipelined_fma according to tuning option.
7784 * config/aarch64/tuning_models/ampere1.h: Add
7785 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
7786 * config/aarch64/tuning_models/ampere1a.h: Likewise.
7787 * config/aarch64/tuning_models/ampere1b.h: Likewise.
7789 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7791 * config/riscv/vector-crypto.md: Modify copyright year.
7793 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7795 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
7797 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
7799 * config.in: Regenerate.
7800 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
7801 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
7802 Added TLS Le Relax support.
7803 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
7804 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
7805 * configure: Regenerate.
7806 * configure.ac: Check if binutils supports TLS le relax.
7808 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7810 * config/riscv/iterators.md: Add rotate insn name.
7811 * config/riscv/riscv.md: Add new insns name for crypto vector.
7812 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
7813 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
7814 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
7816 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7818 PR target/113112
7819 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
7820 pointer type liveness count.
7821 \f
7822 Copyright (C) 2024 Free Software Foundation, Inc.
7824 Copying and distribution of this file, with or without modification,
7825 are permitted in any medium without royalty provided the copyright
7826 notice and this notice are preserved.