gcc/testsuite/gcc.target/aarch64/vneg_s.c

   1 /* Test vneg works correctly.  */
   2 /* { dg-do run } */
   3 /* { dg-options "-std=gnu99 -O3 -Wno-div-by-zero --save-temps" } */
   4
   5 #include <arm_neon.h>
   6 #include <limits.h>
   7
   8 /* Used to force a variable to a SIMD register.  Also acts as a stronger
   9    inhibitor of optimization than the below - necessary for int64x1_t
  10    because more of the implementation is in terms of gcc vector extensions
  11    (which support constant propagation) than for other types.  */
  12 #define force_simd(V1)   asm volatile ("mov %d0, %1.d[0]"       \
  13            : "=w"(V1)                                           \
  14            : "w"(V1)                                            \
  15            : /* No clobbers */);
  16 #define INHIB_OPTIMIZATION asm volatile ("" : : : "memory")
  17
  18 #define TEST0 0
  19 #define TEST1 1
  20 #define TEST2 -1
  21 #define TEST3 10
  22 #define TEST4 -10
  23 #define TEST5 0
  24
  25 #define ANSW0 0
  26 #define ANSW1 -1
  27 #define ANSW2 1
  28 #define ANSW3 -10
  29 #define ANSW4 10
  30 #define ANSW5 0
  31
  32 extern void abort (void);
  33
  34 #define CONCAT(a, b) a##b
  35 #define CONCAT1(a, b) CONCAT (a, b)
  36 #define REG_INFEX64 _
  37 #define REG_INFEX128 q_
  38 #define REG_INFEX(reg_len) REG_INFEX##reg_len
  39 #define POSTFIX(reg_len, data_len) \
  40   CONCAT1 (REG_INFEX (reg_len), s##data_len)
  41 #define DATA_TYPE_32 float
  42 #define DATA_TYPE_64 double
  43 #define DATA_TYPE(data_len) DATA_TYPE_##data_len
  44
  45 #define FORCE_SIMD_INST64_8(data)
  46 #define FORCE_SIMD_INST64_16(data)
  47 #define FORCE_SIMD_INST64_32(data)
  48 #define FORCE_SIMD_INST64_64(data) force_simd (data)
  49 #define FORCE_SIMD_INST128_8(data)
  50 #define FORCE_SIMD_INST128_16(data)
  51 #define FORCE_SIMD_INST128_32(data)
  52 #define FORCE_SIMD_INST128_64(data)
  53
  54 #define FORCE_SIMD_INST(reg_len, data_len, data) \
  55   CONCAT1 (FORCE_SIMD_INST, reg_len##_##data_len) (data)
  56 #define LOAD_INST(reg_len, data_len) \
  57   CONCAT1 (vld1, POSTFIX (reg_len, data_len))
  58 #define NEG_INST(reg_len, data_len) \
  59   CONCAT1 (vneg, POSTFIX (reg_len, data_len))
  60
  61 #define RUN_TEST(test_set, answ_set, reg_len, data_len, n, a, b)        \
  62   {                                                                     \
  63     int i;                                                              \
  64     INHIB_OPTIMIZATION;                                                 \
  65     (a) = LOAD_INST (reg_len, data_len) (test_set);                     \
  66     (b) = LOAD_INST (reg_len, data_len) (answ_set);                     \
  67     FORCE_SIMD_INST (reg_len, data_len, a)                              \
  68     a = NEG_INST (reg_len, data_len) (a);                               \
  69     FORCE_SIMD_INST (reg_len, data_len, a)                              \
  70     for (i = 0; i < n; i++)                                             \
  71       {                                                                 \
  72         INHIB_OPTIMIZATION;                                             \
  73         if (a[i] != b[i])                                               \
  74           return 1;                                                     \
  75       }                                                                 \
  76   }
  77
  78 int
  79 test_vneg_s8 ()
  80 {
  81   int8x8_t a;
  82   int8x8_t b;
  83
  84   int8_t test_set0[8] = {
  85     TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, SCHAR_MAX, SCHAR_MIN
  86   };
  87   int8_t answ_set0[8] = {
  88     ANSW0, ANSW1, ANSW2, ANSW3, ANSW4, ANSW5, SCHAR_MIN + 1, SCHAR_MIN
  89   };
  90
  91   RUN_TEST (test_set0, answ_set0, 64, 8, 8, a, b);
  92
  93   return 0;
  94 }
  95
  96 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */
  97
  98 int
  99 test_vneg_s16 ()
 100 {
 101   int16x4_t a;
 102   int16x4_t b;
 103
 104   int16_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
 105   int16_t test_set1[4] = { TEST4, TEST5, SHRT_MAX, SHRT_MIN };
 106
 107   int16_t answ_set0[4] = { ANSW0, ANSW1, ANSW2, ANSW3 };
 108   int16_t answ_set1[4] = { ANSW4, ANSW5, SHRT_MIN + 1, SHRT_MIN };
 109
 110   RUN_TEST (test_set0, answ_set0, 64, 16, 4, a, b);
 111   RUN_TEST (test_set1, answ_set1, 64, 16, 4, a, b);
 112
 113   return 0;
 114 }
 115
 116 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 2 } } */
 117
 118 int
 119 test_vneg_s32 ()
 120 {
 121   int32x2_t a;
 122   int32x2_t b;
 123
 124   int32_t test_set0[2] = { TEST0, TEST1 };
 125   int32_t test_set1[2] = { TEST2, TEST3 };
 126   int32_t test_set2[2] = { TEST4, TEST5 };
 127   int32_t test_set3[2] = { INT_MAX, INT_MIN };
 128
 129   int32_t answ_set0[2] = { ANSW0, ANSW1 };
 130   int32_t answ_set1[2] = { ANSW2, ANSW3 };
 131   int32_t answ_set2[2] = { ANSW4, ANSW5 };
 132   int32_t answ_set3[2] = { INT_MIN + 1, INT_MIN };
 133
 134   RUN_TEST (test_set0, answ_set0, 64, 32, 2, a, b);
 135   RUN_TEST (test_set1, answ_set1, 64, 32, 2, a, b);
 136   RUN_TEST (test_set2, answ_set2, 64, 32, 2, a, b);
 137   RUN_TEST (test_set3, answ_set3, 64, 32, 2, a, b);
 138
 139   return 0;
 140 }
 141
 142 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 4 } } */
 143
 144 int
 145 test_vneg_s64 ()
 146 {
 147   int64x1_t a;
 148   int64x1_t b;
 149
 150   int64_t test_set0[1] = { TEST0 };
 151   int64_t test_set1[1] = { TEST1 };
 152   int64_t test_set2[1] = { TEST2 };
 153   int64_t test_set3[1] = { TEST3 };
 154   int64_t test_set4[1] = { TEST4 };
 155   int64_t test_set5[1] = { TEST5 };
 156   int64_t test_set6[1] = { LLONG_MAX };
 157   int64_t test_set7[1] = { LLONG_MIN };
 158
 159   int64_t answ_set0[1] = { ANSW0 };
 160   int64_t answ_set1[1] = { ANSW1 };
 161   int64_t answ_set2[1] = { ANSW2 };
 162   int64_t answ_set3[1] = { ANSW3 };
 163   int64_t answ_set4[1] = { ANSW4 };
 164   int64_t answ_set5[1] = { ANSW5 };
 165   int64_t answ_set6[1] = { LLONG_MIN + 1 };
 166   int64_t answ_set7[1] = { LLONG_MIN };
 167
 168   RUN_TEST (test_set0, answ_set0, 64, 64, 1, a, b);
 169   RUN_TEST (test_set1, answ_set1, 64, 64, 1, a, b);
 170   RUN_TEST (test_set2, answ_set2, 64, 64, 1, a, b);
 171   RUN_TEST (test_set3, answ_set3, 64, 64, 1, a, b);
 172   RUN_TEST (test_set4, answ_set4, 64, 64, 1, a, b);
 173   RUN_TEST (test_set5, answ_set5, 64, 64, 1, a, b);
 174   RUN_TEST (test_set6, answ_set6, 64, 64, 1, a, b);
 175   RUN_TEST (test_set7, answ_set7, 64, 64, 1, a, b);
 176
 177   return 0;
 178 }
 179
 180 /* { dg-final { scan-assembler-times "neg\\td\[0-9\]+, d\[0-9\]+" 8 } } */
 181
 182 int
 183 test_vnegq_s8 ()
 184 {
 185   int8x16_t a;
 186   int8x16_t b;
 187
 188   int8_t test_set0[16] = {
 189     TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, SCHAR_MAX, SCHAR_MIN,
 190     4, 8, 15, 16, 23, 42, -1, -2
 191   };
 192
 193   int8_t answ_set0[16] = {
 194     ANSW0, ANSW1, ANSW2, ANSW3, ANSW4, ANSW5, SCHAR_MIN + 1, SCHAR_MIN,
 195     -4, -8, -15, -16, -23, -42, 1, 2
 196   };
 197
 198   RUN_TEST (test_set0, answ_set0, 128, 8, 8, a, b);
 199
 200   return 0;
 201 }
 202
 203 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
 204
 205 int
 206 test_vnegq_s16 ()
 207 {
 208   int16x8_t a;
 209   int16x8_t b;
 210
 211   int16_t test_set0[8] = {
 212     TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, SHRT_MAX, SHRT_MIN
 213   };
 214   int16_t answ_set0[8] = {
 215     ANSW0, ANSW1, ANSW2, ANSW3, ANSW4, ANSW5, SHRT_MIN + 1, SHRT_MIN
 216   };
 217
 218   RUN_TEST (test_set0, answ_set0, 128, 16, 8, a, b);
 219
 220   return 0;
 221 }
 222
 223 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
 224
 225 int
 226 test_vnegq_s32 ()
 227 {
 228   int32x4_t a;
 229   int32x4_t b;
 230
 231   int32_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
 232   int32_t test_set1[4] = { TEST4, TEST5, INT_MAX, INT_MIN };
 233
 234   int32_t answ_set0[4] = { ANSW0, ANSW1, ANSW2, ANSW3 };
 235   int32_t answ_set1[4] = { ANSW4, ANSW5, INT_MIN + 1, INT_MIN };
 236
 237   RUN_TEST (test_set0, answ_set0, 128, 32, 4, a, b);
 238   RUN_TEST (test_set1, answ_set1, 128, 32, 4, a, b);
 239
 240   return 0;
 241 }
 242
 243 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
 244
 245 int
 246 test_vnegq_s64 ()
 247 {
 248   int64x2_t a;
 249   int64x2_t b;
 250
 251   int64_t test_set0[2] = { TEST0, TEST1 };
 252   int64_t test_set1[2] = { TEST2, TEST3 };
 253   int64_t test_set2[2] = { TEST4, TEST5 };
 254   int64_t test_set3[2] = { LLONG_MAX, LLONG_MIN };
 255
 256   int64_t answ_set0[2] = { ANSW0, ANSW1 };
 257   int64_t answ_set1[2] = { ANSW2, ANSW3 };
 258   int64_t answ_set2[2] = { ANSW4, ANSW5 };
 259   int64_t answ_set3[2] = { LLONG_MIN + 1, LLONG_MIN };
 260
 261   RUN_TEST (test_set0, answ_set0, 128, 64, 2, a, b);
 262   RUN_TEST (test_set1, answ_set1, 128, 64, 2, a, b);
 263   RUN_TEST (test_set2, answ_set2, 128, 64, 2, a, b);
 264   RUN_TEST (test_set3, answ_set3, 128, 64, 2, a, b);
 265
 266   return 0;
 267 }
 268
 269 /* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 4 } } */
 270
 271 int
 272 main (int argc, char **argv)
 273 {
 274   if (test_vneg_s8 ())
 275     abort ();
 276
 277   if (test_vneg_s16 ())
 278     abort ();
 279
 280   if (test_vneg_s32 ())
 281     abort ();
 282
 283   if (test_vneg_s64 ())
 284     abort ();
 285
 286   if (test_vnegq_s8 ())
 287     abort ();
 288
 289   if (test_vnegq_s16 ())
 290     abort ();
 291
 292   if (test_vnegq_s32 ())
 293     abort ();
 294
 295   if (test_vnegq_s64 ())
 296     abort ();
 297
 298   return 0;
 299 }
 300
 301 /* { dg-final { cleanup-saved-temps } } */