1 /* Test the vqdmlsl_high_lane_s32 AArch64 SIMD intrinsic. */
3 /* { dg-do compile } */
4 /* { dg-options "-save-temps -O3 -fno-inline" } */
9 t_vqdmlsl_high_lane_s32 (int64x2_t a
, int32x4_t b
, int32x2_t c
)
11 return vqdmlsl_high_lane_s32 (a
, b
, c
, 0);
14 /* { dg-final { scan-assembler-times "sqdmlsl2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
15 /* { dg-final { cleanup-saved-temps } } */