1 /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
2 /* { dg-require-effective-target powerpc_vsx_ok } */
3 /* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */
7 static int vec_long_long_eq (vector
long long x
, vector
long long y
)
9 return (x
[0] == y
[0] && x
[1] == y
[1]);
12 static int vec_double_eq (vector
double x
, vector
double y
)
14 return (x
[0] == y
[0] && x
[1] == y
[1]);
20 vector
long long vla
= {-2,-1};
21 vector
long long vlb
= {0,1};
22 vector
double vda
= {-2.0,-1.0};
23 vector
double vdb
= {0.0,1.0};
24 vector
unsigned int vuia
= {0,1,2,3};
25 vector
unsigned int vuib
= {4,5,6,7};
26 vector
signed int vsia
= {-4,-3,-2,-1};
27 vector
signed int vsib
= {0,1,2,3};
28 vector
float vfa
= {-4.0,-3.0,-2.0,-1.0};
29 vector
float vfb
= {0.0,1.0,2.0,3.0};
32 vector
long long vlh
, vll
;
33 vector
double vdh
, vdl
;
34 vector
unsigned int vuih
, vuil
;
35 vector
signed int vsih
, vsil
;
36 vector
float vfh
, vfl
;
38 /* Expected result vectors. */
39 vector
long long vlrh
= {-2,0};
40 vector
long long vlrl
= {-1,1};
41 vector
double vdrh
= {-2.0,0.0};
42 vector
double vdrl
= {-1.0,1.0};
43 vector
unsigned int vuirh
= {0,4,1,5};
44 vector
unsigned int vuirl
= {2,6,3,7};
45 vector
signed int vsirh
= {-4,0,-3,1};
46 vector
signed int vsirl
= {-2,2,-1,3};
47 vector
float vfrh
= {-4.0,0.0,-3.0,1.0};
48 vector
float vfrl
= {-2.0,2.0,-1.0,3.0};
50 vlh
= vec_mergeh (vla
, vlb
);
51 vll
= vec_mergel (vla
, vlb
);
52 vdh
= vec_mergeh (vda
, vdb
);
53 vdl
= vec_mergel (vda
, vdb
);
54 vuih
= vec_mergeh (vuia
, vuib
);
55 vuil
= vec_mergel (vuia
, vuib
);
56 vsih
= vec_mergeh (vsia
, vsib
);
57 vsil
= vec_mergel (vsia
, vsib
);
58 vfh
= vec_mergeh (vfa
, vfb
);
59 vfl
= vec_mergel (vfa
, vfb
);
61 check (vec_long_long_eq (vlh
, vlrh
), "vlh");
62 check (vec_long_long_eq (vll
, vlrl
), "vll");
63 check (vec_double_eq (vdh
, vdrh
), "vdh" );
64 check (vec_double_eq (vdl
, vdrl
), "vdl" );
65 check (vec_all_eq (vuih
, vuirh
), "vuih");
66 check (vec_all_eq (vuil
, vuirl
), "vuil");
67 check (vec_all_eq (vsih
, vsirh
), "vsih");
68 check (vec_all_eq (vsil
, vsirl
), "vsil");
69 check (vec_all_eq (vfh
, vfrh
), "vfh");
70 check (vec_all_eq (vfl
, vfrl
), "vfl");