gcc/doc/arm-neon-intrinsics.texi

   1 @c Copyright (C) 2006-2014 Free Software Foundation, Inc.
   2 @c This is part of the GCC manual.
   3 @c For copying conditions, see the file gcc.texi.
   4
   5 @subsubsection Addition
   6
   7 @itemize @bullet
   8 @item uint32x2_t vadd_u32 (uint32x2_t, uint32x2_t)
   9 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
  10 @end itemize
  11
  12
  13 @itemize @bullet
  14 @item uint16x4_t vadd_u16 (uint16x4_t, uint16x4_t)
  15 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
  16 @end itemize
  17
  18
  19 @itemize @bullet
  20 @item uint8x8_t vadd_u8 (uint8x8_t, uint8x8_t)
  21 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
  22 @end itemize
  23
  24
  25 @itemize @bullet
  26 @item int32x2_t vadd_s32 (int32x2_t, int32x2_t)
  27 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
  28 @end itemize
  29
  30
  31 @itemize @bullet
  32 @item int16x4_t vadd_s16 (int16x4_t, int16x4_t)
  33 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
  34 @end itemize
  35
  36
  37 @itemize @bullet
  38 @item int8x8_t vadd_s8 (int8x8_t, int8x8_t)
  39 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
  40 @end itemize
  41
  42
  43 @itemize @bullet
  44 @item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
  45 @*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
  46 @end itemize
  47
  48
  49 @itemize @bullet
  50 @item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
  51 @end itemize
  52
  53
  54 @itemize @bullet
  55 @item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
  56 @end itemize
  57
  58
  59 @itemize @bullet
  60 @item uint32x4_t vaddq_u32 (uint32x4_t, uint32x4_t)
  61 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
  62 @end itemize
  63
  64
  65 @itemize @bullet
  66 @item uint16x8_t vaddq_u16 (uint16x8_t, uint16x8_t)
  67 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
  68 @end itemize
  69
  70
  71 @itemize @bullet
  72 @item uint8x16_t vaddq_u8 (uint8x16_t, uint8x16_t)
  73 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
  74 @end itemize
  75
  76
  77 @itemize @bullet
  78 @item int32x4_t vaddq_s32 (int32x4_t, int32x4_t)
  79 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
  80 @end itemize
  81
  82
  83 @itemize @bullet
  84 @item int16x8_t vaddq_s16 (int16x8_t, int16x8_t)
  85 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
  86 @end itemize
  87
  88
  89 @itemize @bullet
  90 @item int8x16_t vaddq_s8 (int8x16_t, int8x16_t)
  91 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
  92 @end itemize
  93
  94
  95 @itemize @bullet
  96 @item uint64x2_t vaddq_u64 (uint64x2_t, uint64x2_t)
  97 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
  98 @end itemize
  99
 100
 101 @itemize @bullet
 102 @item int64x2_t vaddq_s64 (int64x2_t, int64x2_t)
 103 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
 104 @end itemize
 105
 106
 107 @itemize @bullet
 108 @item float32x4_t vaddq_f32 (float32x4_t, float32x4_t)
 109 @*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{q0}, @var{q0}, @var{q0}}
 110 @end itemize
 111
 112
 113 @itemize @bullet
 114 @item uint64x2_t vaddl_u32 (uint32x2_t, uint32x2_t)
 115 @*@emph{Form of expected instruction(s):} @code{vaddl.u32 @var{q0}, @var{d0}, @var{d0}}
 116 @end itemize
 117
 118
 119 @itemize @bullet
 120 @item uint32x4_t vaddl_u16 (uint16x4_t, uint16x4_t)
 121 @*@emph{Form of expected instruction(s):} @code{vaddl.u16 @var{q0}, @var{d0}, @var{d0}}
 122 @end itemize
 123
 124
 125 @itemize @bullet
 126 @item uint16x8_t vaddl_u8 (uint8x8_t, uint8x8_t)
 127 @*@emph{Form of expected instruction(s):} @code{vaddl.u8 @var{q0}, @var{d0}, @var{d0}}
 128 @end itemize
 129
 130
 131 @itemize @bullet
 132 @item int64x2_t vaddl_s32 (int32x2_t, int32x2_t)
 133 @*@emph{Form of expected instruction(s):} @code{vaddl.s32 @var{q0}, @var{d0}, @var{d0}}
 134 @end itemize
 135
 136
 137 @itemize @bullet
 138 @item int32x4_t vaddl_s16 (int16x4_t, int16x4_t)
 139 @*@emph{Form of expected instruction(s):} @code{vaddl.s16 @var{q0}, @var{d0}, @var{d0}}
 140 @end itemize
 141
 142
 143 @itemize @bullet
 144 @item int16x8_t vaddl_s8 (int8x8_t, int8x8_t)
 145 @*@emph{Form of expected instruction(s):} @code{vaddl.s8 @var{q0}, @var{d0}, @var{d0}}
 146 @end itemize
 147
 148
 149 @itemize @bullet
 150 @item uint64x2_t vaddw_u32 (uint64x2_t, uint32x2_t)
 151 @*@emph{Form of expected instruction(s):} @code{vaddw.u32 @var{q0}, @var{q0}, @var{d0}}
 152 @end itemize
 153
 154
 155 @itemize @bullet
 156 @item uint32x4_t vaddw_u16 (uint32x4_t, uint16x4_t)
 157 @*@emph{Form of expected instruction(s):} @code{vaddw.u16 @var{q0}, @var{q0}, @var{d0}}
 158 @end itemize
 159
 160
 161 @itemize @bullet
 162 @item uint16x8_t vaddw_u8 (uint16x8_t, uint8x8_t)
 163 @*@emph{Form of expected instruction(s):} @code{vaddw.u8 @var{q0}, @var{q0}, @var{d0}}
 164 @end itemize
 165
 166
 167 @itemize @bullet
 168 @item int64x2_t vaddw_s32 (int64x2_t, int32x2_t)
 169 @*@emph{Form of expected instruction(s):} @code{vaddw.s32 @var{q0}, @var{q0}, @var{d0}}
 170 @end itemize
 171
 172
 173 @itemize @bullet
 174 @item int32x4_t vaddw_s16 (int32x4_t, int16x4_t)
 175 @*@emph{Form of expected instruction(s):} @code{vaddw.s16 @var{q0}, @var{q0}, @var{d0}}
 176 @end itemize
 177
 178
 179 @itemize @bullet
 180 @item int16x8_t vaddw_s8 (int16x8_t, int8x8_t)
 181 @*@emph{Form of expected instruction(s):} @code{vaddw.s8 @var{q0}, @var{q0}, @var{d0}}
 182 @end itemize
 183
 184
 185 @itemize @bullet
 186 @item uint32x2_t vhadd_u32 (uint32x2_t, uint32x2_t)
 187 @*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{d0}, @var{d0}, @var{d0}}
 188 @end itemize
 189
 190
 191 @itemize @bullet
 192 @item uint16x4_t vhadd_u16 (uint16x4_t, uint16x4_t)
 193 @*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{d0}, @var{d0}, @var{d0}}
 194 @end itemize
 195
 196
 197 @itemize @bullet
 198 @item uint8x8_t vhadd_u8 (uint8x8_t, uint8x8_t)
 199 @*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{d0}, @var{d0}, @var{d0}}
 200 @end itemize
 201
 202
 203 @itemize @bullet
 204 @item int32x2_t vhadd_s32 (int32x2_t, int32x2_t)
 205 @*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{d0}, @var{d0}, @var{d0}}
 206 @end itemize
 207
 208
 209 @itemize @bullet
 210 @item int16x4_t vhadd_s16 (int16x4_t, int16x4_t)
 211 @*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{d0}, @var{d0}, @var{d0}}
 212 @end itemize
 213
 214
 215 @itemize @bullet
 216 @item int8x8_t vhadd_s8 (int8x8_t, int8x8_t)
 217 @*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{d0}, @var{d0}, @var{d0}}
 218 @end itemize
 219
 220
 221 @itemize @bullet
 222 @item uint32x4_t vhaddq_u32 (uint32x4_t, uint32x4_t)
 223 @*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{q0}, @var{q0}, @var{q0}}
 224 @end itemize
 225
 226
 227 @itemize @bullet
 228 @item uint16x8_t vhaddq_u16 (uint16x8_t, uint16x8_t)
 229 @*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{q0}, @var{q0}, @var{q0}}
 230 @end itemize
 231
 232
 233 @itemize @bullet
 234 @item uint8x16_t vhaddq_u8 (uint8x16_t, uint8x16_t)
 235 @*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{q0}, @var{q0}, @var{q0}}
 236 @end itemize
 237
 238
 239 @itemize @bullet
 240 @item int32x4_t vhaddq_s32 (int32x4_t, int32x4_t)
 241 @*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{q0}, @var{q0}, @var{q0}}
 242 @end itemize
 243
 244
 245 @itemize @bullet
 246 @item int16x8_t vhaddq_s16 (int16x8_t, int16x8_t)
 247 @*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{q0}, @var{q0}, @var{q0}}
 248 @end itemize
 249
 250
 251 @itemize @bullet
 252 @item int8x16_t vhaddq_s8 (int8x16_t, int8x16_t)
 253 @*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{q0}, @var{q0}, @var{q0}}
 254 @end itemize
 255
 256
 257 @itemize @bullet
 258 @item uint32x2_t vrhadd_u32 (uint32x2_t, uint32x2_t)
 259 @*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{d0}, @var{d0}, @var{d0}}
 260 @end itemize
 261
 262
 263 @itemize @bullet
 264 @item uint16x4_t vrhadd_u16 (uint16x4_t, uint16x4_t)
 265 @*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{d0}, @var{d0}, @var{d0}}
 266 @end itemize
 267
 268
 269 @itemize @bullet
 270 @item uint8x8_t vrhadd_u8 (uint8x8_t, uint8x8_t)
 271 @*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{d0}, @var{d0}, @var{d0}}
 272 @end itemize
 273
 274
 275 @itemize @bullet
 276 @item int32x2_t vrhadd_s32 (int32x2_t, int32x2_t)
 277 @*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{d0}, @var{d0}, @var{d0}}
 278 @end itemize
 279
 280
 281 @itemize @bullet
 282 @item int16x4_t vrhadd_s16 (int16x4_t, int16x4_t)
 283 @*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{d0}, @var{d0}, @var{d0}}
 284 @end itemize
 285
 286
 287 @itemize @bullet
 288 @item int8x8_t vrhadd_s8 (int8x8_t, int8x8_t)
 289 @*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{d0}, @var{d0}, @var{d0}}
 290 @end itemize
 291
 292
 293 @itemize @bullet
 294 @item uint32x4_t vrhaddq_u32 (uint32x4_t, uint32x4_t)
 295 @*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{q0}, @var{q0}, @var{q0}}
 296 @end itemize
 297
 298
 299 @itemize @bullet
 300 @item uint16x8_t vrhaddq_u16 (uint16x8_t, uint16x8_t)
 301 @*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{q0}, @var{q0}, @var{q0}}
 302 @end itemize
 303
 304
 305 @itemize @bullet
 306 @item uint8x16_t vrhaddq_u8 (uint8x16_t, uint8x16_t)
 307 @*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{q0}, @var{q0}, @var{q0}}
 308 @end itemize
 309
 310
 311 @itemize @bullet
 312 @item int32x4_t vrhaddq_s32 (int32x4_t, int32x4_t)
 313 @*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{q0}, @var{q0}, @var{q0}}
 314 @end itemize
 315
 316
 317 @itemize @bullet
 318 @item int16x8_t vrhaddq_s16 (int16x8_t, int16x8_t)
 319 @*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{q0}, @var{q0}, @var{q0}}
 320 @end itemize
 321
 322
 323 @itemize @bullet
 324 @item int8x16_t vrhaddq_s8 (int8x16_t, int8x16_t)
 325 @*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{q0}, @var{q0}, @var{q0}}
 326 @end itemize
 327
 328
 329 @itemize @bullet
 330 @item uint32x2_t vqadd_u32 (uint32x2_t, uint32x2_t)
 331 @*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{d0}, @var{d0}, @var{d0}}
 332 @end itemize
 333
 334
 335 @itemize @bullet
 336 @item uint16x4_t vqadd_u16 (uint16x4_t, uint16x4_t)
 337 @*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{d0}, @var{d0}, @var{d0}}
 338 @end itemize
 339
 340
 341 @itemize @bullet
 342 @item uint8x8_t vqadd_u8 (uint8x8_t, uint8x8_t)
 343 @*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{d0}, @var{d0}, @var{d0}}
 344 @end itemize
 345
 346
 347 @itemize @bullet
 348 @item int32x2_t vqadd_s32 (int32x2_t, int32x2_t)
 349 @*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{d0}, @var{d0}, @var{d0}}
 350 @end itemize
 351
 352
 353 @itemize @bullet
 354 @item int16x4_t vqadd_s16 (int16x4_t, int16x4_t)
 355 @*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{d0}, @var{d0}, @var{d0}}
 356 @end itemize
 357
 358
 359 @itemize @bullet
 360 @item int8x8_t vqadd_s8 (int8x8_t, int8x8_t)
 361 @*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{d0}, @var{d0}, @var{d0}}
 362 @end itemize
 363
 364
 365 @itemize @bullet
 366 @item uint64x1_t vqadd_u64 (uint64x1_t, uint64x1_t)
 367 @*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{d0}, @var{d0}, @var{d0}}
 368 @end itemize
 369
 370
 371 @itemize @bullet
 372 @item int64x1_t vqadd_s64 (int64x1_t, int64x1_t)
 373 @*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{d0}, @var{d0}, @var{d0}}
 374 @end itemize
 375
 376
 377 @itemize @bullet
 378 @item uint32x4_t vqaddq_u32 (uint32x4_t, uint32x4_t)
 379 @*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{q0}, @var{q0}, @var{q0}}
 380 @end itemize
 381
 382
 383 @itemize @bullet
 384 @item uint16x8_t vqaddq_u16 (uint16x8_t, uint16x8_t)
 385 @*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{q0}, @var{q0}, @var{q0}}
 386 @end itemize
 387
 388
 389 @itemize @bullet
 390 @item uint8x16_t vqaddq_u8 (uint8x16_t, uint8x16_t)
 391 @*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{q0}, @var{q0}, @var{q0}}
 392 @end itemize
 393
 394
 395 @itemize @bullet
 396 @item int32x4_t vqaddq_s32 (int32x4_t, int32x4_t)
 397 @*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{q0}, @var{q0}, @var{q0}}
 398 @end itemize
 399
 400
 401 @itemize @bullet
 402 @item int16x8_t vqaddq_s16 (int16x8_t, int16x8_t)
 403 @*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{q0}, @var{q0}, @var{q0}}
 404 @end itemize
 405
 406
 407 @itemize @bullet
 408 @item int8x16_t vqaddq_s8 (int8x16_t, int8x16_t)
 409 @*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{q0}, @var{q0}, @var{q0}}
 410 @end itemize
 411
 412
 413 @itemize @bullet
 414 @item uint64x2_t vqaddq_u64 (uint64x2_t, uint64x2_t)
 415 @*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{q0}, @var{q0}, @var{q0}}
 416 @end itemize
 417
 418
 419 @itemize @bullet
 420 @item int64x2_t vqaddq_s64 (int64x2_t, int64x2_t)
 421 @*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{q0}, @var{q0}, @var{q0}}
 422 @end itemize
 423
 424
 425 @itemize @bullet
 426 @item uint32x2_t vaddhn_u64 (uint64x2_t, uint64x2_t)
 427 @*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 428 @end itemize
 429
 430
 431 @itemize @bullet
 432 @item uint16x4_t vaddhn_u32 (uint32x4_t, uint32x4_t)
 433 @*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 434 @end itemize
 435
 436
 437 @itemize @bullet
 438 @item uint8x8_t vaddhn_u16 (uint16x8_t, uint16x8_t)
 439 @*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 440 @end itemize
 441
 442
 443 @itemize @bullet
 444 @item int32x2_t vaddhn_s64 (int64x2_t, int64x2_t)
 445 @*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 446 @end itemize
 447
 448
 449 @itemize @bullet
 450 @item int16x4_t vaddhn_s32 (int32x4_t, int32x4_t)
 451 @*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 452 @end itemize
 453
 454
 455 @itemize @bullet
 456 @item int8x8_t vaddhn_s16 (int16x8_t, int16x8_t)
 457 @*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 458 @end itemize
 459
 460
 461 @itemize @bullet
 462 @item uint32x2_t vraddhn_u64 (uint64x2_t, uint64x2_t)
 463 @*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 464 @end itemize
 465
 466
 467 @itemize @bullet
 468 @item uint16x4_t vraddhn_u32 (uint32x4_t, uint32x4_t)
 469 @*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 470 @end itemize
 471
 472
 473 @itemize @bullet
 474 @item uint8x8_t vraddhn_u16 (uint16x8_t, uint16x8_t)
 475 @*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 476 @end itemize
 477
 478
 479 @itemize @bullet
 480 @item int32x2_t vraddhn_s64 (int64x2_t, int64x2_t)
 481 @*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 482 @end itemize
 483
 484
 485 @itemize @bullet
 486 @item int16x4_t vraddhn_s32 (int32x4_t, int32x4_t)
 487 @*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 488 @end itemize
 489
 490
 491 @itemize @bullet
 492 @item int8x8_t vraddhn_s16 (int16x8_t, int16x8_t)
 493 @*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 494 @end itemize
 495
 496
 497
 498
 499 @subsubsection Multiplication
 500
 501 @itemize @bullet
 502 @item uint32x2_t vmul_u32 (uint32x2_t, uint32x2_t)
 503 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
 504 @end itemize
 505
 506
 507 @itemize @bullet
 508 @item uint16x4_t vmul_u16 (uint16x4_t, uint16x4_t)
 509 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
 510 @end itemize
 511
 512
 513 @itemize @bullet
 514 @item uint8x8_t vmul_u8 (uint8x8_t, uint8x8_t)
 515 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
 516 @end itemize
 517
 518
 519 @itemize @bullet
 520 @item int32x2_t vmul_s32 (int32x2_t, int32x2_t)
 521 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
 522 @end itemize
 523
 524
 525 @itemize @bullet
 526 @item int16x4_t vmul_s16 (int16x4_t, int16x4_t)
 527 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
 528 @end itemize
 529
 530
 531 @itemize @bullet
 532 @item int8x8_t vmul_s8 (int8x8_t, int8x8_t)
 533 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
 534 @end itemize
 535
 536
 537 @itemize @bullet
 538 @item float32x2_t vmul_f32 (float32x2_t, float32x2_t)
 539 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}}
 540 @end itemize
 541
 542
 543 @itemize @bullet
 544 @item poly8x8_t vmul_p8 (poly8x8_t, poly8x8_t)
 545 @*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{d0}, @var{d0}, @var{d0}}
 546 @end itemize
 547
 548
 549 @itemize @bullet
 550 @item uint32x4_t vmulq_u32 (uint32x4_t, uint32x4_t)
 551 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
 552 @end itemize
 553
 554
 555 @itemize @bullet
 556 @item uint16x8_t vmulq_u16 (uint16x8_t, uint16x8_t)
 557 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
 558 @end itemize
 559
 560
 561 @itemize @bullet
 562 @item uint8x16_t vmulq_u8 (uint8x16_t, uint8x16_t)
 563 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
 564 @end itemize
 565
 566
 567 @itemize @bullet
 568 @item int32x4_t vmulq_s32 (int32x4_t, int32x4_t)
 569 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
 570 @end itemize
 571
 572
 573 @itemize @bullet
 574 @item int16x8_t vmulq_s16 (int16x8_t, int16x8_t)
 575 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
 576 @end itemize
 577
 578
 579 @itemize @bullet
 580 @item int8x16_t vmulq_s8 (int8x16_t, int8x16_t)
 581 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
 582 @end itemize
 583
 584
 585 @itemize @bullet
 586 @item float32x4_t vmulq_f32 (float32x4_t, float32x4_t)
 587 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{q0}}
 588 @end itemize
 589
 590
 591 @itemize @bullet
 592 @item poly8x16_t vmulq_p8 (poly8x16_t, poly8x16_t)
 593 @*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{q0}, @var{q0}, @var{q0}}
 594 @end itemize
 595
 596
 597 @itemize @bullet
 598 @item int32x2_t vqdmulh_s32 (int32x2_t, int32x2_t)
 599 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
 600 @end itemize
 601
 602
 603 @itemize @bullet
 604 @item int16x4_t vqdmulh_s16 (int16x4_t, int16x4_t)
 605 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
 606 @end itemize
 607
 608
 609 @itemize @bullet
 610 @item int32x4_t vqdmulhq_s32 (int32x4_t, int32x4_t)
 611 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
 612 @end itemize
 613
 614
 615 @itemize @bullet
 616 @item int16x8_t vqdmulhq_s16 (int16x8_t, int16x8_t)
 617 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
 618 @end itemize
 619
 620
 621 @itemize @bullet
 622 @item int32x2_t vqrdmulh_s32 (int32x2_t, int32x2_t)
 623 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
 624 @end itemize
 625
 626
 627 @itemize @bullet
 628 @item int16x4_t vqrdmulh_s16 (int16x4_t, int16x4_t)
 629 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
 630 @end itemize
 631
 632
 633 @itemize @bullet
 634 @item int32x4_t vqrdmulhq_s32 (int32x4_t, int32x4_t)
 635 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
 636 @end itemize
 637
 638
 639 @itemize @bullet
 640 @item int16x8_t vqrdmulhq_s16 (int16x8_t, int16x8_t)
 641 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
 642 @end itemize
 643
 644
 645 @itemize @bullet
 646 @item uint64x2_t vmull_u32 (uint32x2_t, uint32x2_t)
 647 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}}
 648 @end itemize
 649
 650
 651 @itemize @bullet
 652 @item uint32x4_t vmull_u16 (uint16x4_t, uint16x4_t)
 653 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}}
 654 @end itemize
 655
 656
 657 @itemize @bullet
 658 @item uint16x8_t vmull_u8 (uint8x8_t, uint8x8_t)
 659 @*@emph{Form of expected instruction(s):} @code{vmull.u8 @var{q0}, @var{d0}, @var{d0}}
 660 @end itemize
 661
 662
 663 @itemize @bullet
 664 @item int64x2_t vmull_s32 (int32x2_t, int32x2_t)
 665 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}}
 666 @end itemize
 667
 668
 669 @itemize @bullet
 670 @item int32x4_t vmull_s16 (int16x4_t, int16x4_t)
 671 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}}
 672 @end itemize
 673
 674
 675 @itemize @bullet
 676 @item int16x8_t vmull_s8 (int8x8_t, int8x8_t)
 677 @*@emph{Form of expected instruction(s):} @code{vmull.s8 @var{q0}, @var{d0}, @var{d0}}
 678 @end itemize
 679
 680
 681 @itemize @bullet
 682 @item poly16x8_t vmull_p8 (poly8x8_t, poly8x8_t)
 683 @*@emph{Form of expected instruction(s):} @code{vmull.p8 @var{q0}, @var{d0}, @var{d0}}
 684 @end itemize
 685
 686
 687 @itemize @bullet
 688 @item int64x2_t vqdmull_s32 (int32x2_t, int32x2_t)
 689 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}}
 690 @end itemize
 691
 692
 693 @itemize @bullet
 694 @item int32x4_t vqdmull_s16 (int16x4_t, int16x4_t)
 695 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}}
 696 @end itemize
 697
 698
 699
 700
 701 @subsubsection Multiply-accumulate
 702
 703 @itemize @bullet
 704 @item uint32x2_t vmla_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
 705 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
 706 @end itemize
 707
 708
 709 @itemize @bullet
 710 @item uint16x4_t vmla_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
 711 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
 712 @end itemize
 713
 714
 715 @itemize @bullet
 716 @item uint8x8_t vmla_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
 717 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
 718 @end itemize
 719
 720
 721 @itemize @bullet
 722 @item int32x2_t vmla_s32 (int32x2_t, int32x2_t, int32x2_t)
 723 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
 724 @end itemize
 725
 726
 727 @itemize @bullet
 728 @item int16x4_t vmla_s16 (int16x4_t, int16x4_t, int16x4_t)
 729 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
 730 @end itemize
 731
 732
 733 @itemize @bullet
 734 @item int8x8_t vmla_s8 (int8x8_t, int8x8_t, int8x8_t)
 735 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
 736 @end itemize
 737
 738
 739 @itemize @bullet
 740 @item float32x2_t vmla_f32 (float32x2_t, float32x2_t, float32x2_t)
 741 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}}
 742 @end itemize
 743
 744
 745 @itemize @bullet
 746 @item uint32x4_t vmlaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
 747 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
 748 @end itemize
 749
 750
 751 @itemize @bullet
 752 @item uint16x8_t vmlaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
 753 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
 754 @end itemize
 755
 756
 757 @itemize @bullet
 758 @item uint8x16_t vmlaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
 759 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
 760 @end itemize
 761
 762
 763 @itemize @bullet
 764 @item int32x4_t vmlaq_s32 (int32x4_t, int32x4_t, int32x4_t)
 765 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
 766 @end itemize
 767
 768
 769 @itemize @bullet
 770 @item int16x8_t vmlaq_s16 (int16x8_t, int16x8_t, int16x8_t)
 771 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
 772 @end itemize
 773
 774
 775 @itemize @bullet
 776 @item int8x16_t vmlaq_s8 (int8x16_t, int8x16_t, int8x16_t)
 777 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
 778 @end itemize
 779
 780
 781 @itemize @bullet
 782 @item float32x4_t vmlaq_f32 (float32x4_t, float32x4_t, float32x4_t)
 783 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{q0}}
 784 @end itemize
 785
 786
 787 @itemize @bullet
 788 @item uint64x2_t vmlal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
 789 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}}
 790 @end itemize
 791
 792
 793 @itemize @bullet
 794 @item uint32x4_t vmlal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
 795 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}}
 796 @end itemize
 797
 798
 799 @itemize @bullet
 800 @item uint16x8_t vmlal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
 801 @*@emph{Form of expected instruction(s):} @code{vmlal.u8 @var{q0}, @var{d0}, @var{d0}}
 802 @end itemize
 803
 804
 805 @itemize @bullet
 806 @item int64x2_t vmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
 807 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}}
 808 @end itemize
 809
 810
 811 @itemize @bullet
 812 @item int32x4_t vmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
 813 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}}
 814 @end itemize
 815
 816
 817 @itemize @bullet
 818 @item int16x8_t vmlal_s8 (int16x8_t, int8x8_t, int8x8_t)
 819 @*@emph{Form of expected instruction(s):} @code{vmlal.s8 @var{q0}, @var{d0}, @var{d0}}
 820 @end itemize
 821
 822
 823 @itemize @bullet
 824 @item int64x2_t vqdmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
 825 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}}
 826 @end itemize
 827
 828
 829 @itemize @bullet
 830 @item int32x4_t vqdmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
 831 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}}
 832 @end itemize
 833
 834
 835
 836
 837 @subsubsection Multiply-subtract
 838
 839 @itemize @bullet
 840 @item uint32x2_t vmls_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
 841 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
 842 @end itemize
 843
 844
 845 @itemize @bullet
 846 @item uint16x4_t vmls_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
 847 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
 848 @end itemize
 849
 850
 851 @itemize @bullet
 852 @item uint8x8_t vmls_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
 853 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
 854 @end itemize
 855
 856
 857 @itemize @bullet
 858 @item int32x2_t vmls_s32 (int32x2_t, int32x2_t, int32x2_t)
 859 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
 860 @end itemize
 861
 862
 863 @itemize @bullet
 864 @item int16x4_t vmls_s16 (int16x4_t, int16x4_t, int16x4_t)
 865 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
 866 @end itemize
 867
 868
 869 @itemize @bullet
 870 @item int8x8_t vmls_s8 (int8x8_t, int8x8_t, int8x8_t)
 871 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
 872 @end itemize
 873
 874
 875 @itemize @bullet
 876 @item float32x2_t vmls_f32 (float32x2_t, float32x2_t, float32x2_t)
 877 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}}
 878 @end itemize
 879
 880
 881 @itemize @bullet
 882 @item uint32x4_t vmlsq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
 883 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
 884 @end itemize
 885
 886
 887 @itemize @bullet
 888 @item uint16x8_t vmlsq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
 889 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
 890 @end itemize
 891
 892
 893 @itemize @bullet
 894 @item uint8x16_t vmlsq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
 895 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
 896 @end itemize
 897
 898
 899 @itemize @bullet
 900 @item int32x4_t vmlsq_s32 (int32x4_t, int32x4_t, int32x4_t)
 901 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
 902 @end itemize
 903
 904
 905 @itemize @bullet
 906 @item int16x8_t vmlsq_s16 (int16x8_t, int16x8_t, int16x8_t)
 907 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
 908 @end itemize
 909
 910
 911 @itemize @bullet
 912 @item int8x16_t vmlsq_s8 (int8x16_t, int8x16_t, int8x16_t)
 913 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
 914 @end itemize
 915
 916
 917 @itemize @bullet
 918 @item float32x4_t vmlsq_f32 (float32x4_t, float32x4_t, float32x4_t)
 919 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{q0}}
 920 @end itemize
 921
 922
 923 @itemize @bullet
 924 @item uint64x2_t vmlsl_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
 925 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}}
 926 @end itemize
 927
 928
 929 @itemize @bullet
 930 @item uint32x4_t vmlsl_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
 931 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}}
 932 @end itemize
 933
 934
 935 @itemize @bullet
 936 @item uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
 937 @*@emph{Form of expected instruction(s):} @code{vmlsl.u8 @var{q0}, @var{d0}, @var{d0}}
 938 @end itemize
 939
 940
 941 @itemize @bullet
 942 @item int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
 943 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
 944 @end itemize
 945
 946
 947 @itemize @bullet
 948 @item int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
 949 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
 950 @end itemize
 951
 952
 953 @itemize @bullet
 954 @item int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t)
 955 @*@emph{Form of expected instruction(s):} @code{vmlsl.s8 @var{q0}, @var{d0}, @var{d0}}
 956 @end itemize
 957
 958
 959 @itemize @bullet
 960 @item int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
 961 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
 962 @end itemize
 963
 964
 965 @itemize @bullet
 966 @item int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
 967 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
 968 @end itemize
 969
 970
 971
 972
 973 @subsubsection Fused-multiply-accumulate
 974
 975 @itemize @bullet
 976 @item float32x2_t vfma_f32 (float32x2_t, float32x2_t, float32x2_t)
 977 @*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{d0}, @var{d0}, @var{d0}}
 978 @end itemize
 979
 980
 981 @itemize @bullet
 982 @item float32x4_t vfmaq_f32 (float32x4_t, float32x4_t, float32x4_t)
 983 @*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{q0}, @var{q0}, @var{q0}}
 984 @end itemize
 985
 986
 987
 988
 989 @subsubsection Fused-multiply-subtract
 990
 991 @itemize @bullet
 992 @item float32x2_t vfms_f32 (float32x2_t, float32x2_t, float32x2_t)
 993 @*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{d0}, @var{d0}, @var{d0}}
 994 @end itemize
 995
 996
 997 @itemize @bullet
 998 @item float32x4_t vfmsq_f32 (float32x4_t, float32x4_t, float32x4_t)
 999 @*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{q0}, @var{q0}, @var{q0}}
1000 @end itemize
1001
1002
1003
1004
1005 @subsubsection Round to integral (to nearest, ties to even)
1006
1007 @itemize @bullet
1008 @item float32x2_t vrndn_f32 (float32x2_t)
1009 @*@emph{Form of expected instruction(s):} @code{vrintn.f32 @var{d0}, @var{d0}}
1010 @end itemize
1011
1012
1013 @itemize @bullet
1014 @item float32x4_t vrndqn_f32 (float32x4_t)
1015 @*@emph{Form of expected instruction(s):} @code{vrintn.f32 @var{q0}, @var{q0}}
1016 @end itemize
1017
1018
1019
1020
1021 @subsubsection Round to integral (to nearest, ties away from zero)
1022
1023 @itemize @bullet
1024 @item float32x2_t vrnda_f32 (float32x2_t)
1025 @*@emph{Form of expected instruction(s):} @code{vrinta.f32 @var{d0}, @var{d0}}
1026 @end itemize
1027
1028
1029 @itemize @bullet
1030 @item float32x4_t vrndqa_f32 (float32x4_t)
1031 @*@emph{Form of expected instruction(s):} @code{vrinta.f32 @var{q0}, @var{q0}}
1032 @end itemize
1033
1034
1035
1036
1037 @subsubsection Round to integral (towards +Inf)
1038
1039 @itemize @bullet
1040 @item float32x2_t vrndp_f32 (float32x2_t)
1041 @*@emph{Form of expected instruction(s):} @code{vrintp.f32 @var{d0}, @var{d0}}
1042 @end itemize
1043
1044
1045 @itemize @bullet
1046 @item float32x4_t vrndqp_f32 (float32x4_t)
1047 @*@emph{Form of expected instruction(s):} @code{vrintp.f32 @var{q0}, @var{q0}}
1048 @end itemize
1049
1050
1051
1052
1053 @subsubsection Round to integral (towards -Inf)
1054
1055 @itemize @bullet
1056 @item float32x2_t vrndm_f32 (float32x2_t)
1057 @*@emph{Form of expected instruction(s):} @code{vrintm.f32 @var{d0}, @var{d0}}
1058 @end itemize
1059
1060
1061 @itemize @bullet
1062 @item float32x4_t vrndqm_f32 (float32x4_t)
1063 @*@emph{Form of expected instruction(s):} @code{vrintm.f32 @var{q0}, @var{q0}}
1064 @end itemize
1065
1066
1067
1068
1069 @subsubsection Round to integral (towards 0)
1070
1071 @itemize @bullet
1072 @item float32x2_t vrnd_f32 (float32x2_t)
1073 @*@emph{Form of expected instruction(s):} @code{vrintz.f32 @var{d0}, @var{d0}}
1074 @end itemize
1075
1076
1077 @itemize @bullet
1078 @item float32x4_t vrndq_f32 (float32x4_t)
1079 @*@emph{Form of expected instruction(s):} @code{vrintz.f32 @var{q0}, @var{q0}}
1080 @end itemize
1081
1082
1083
1084
1085 @subsubsection Subtraction
1086
1087 @itemize @bullet
1088 @item uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t)
1089 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
1090 @end itemize
1091
1092
1093 @itemize @bullet
1094 @item uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t)
1095 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
1096 @end itemize
1097
1098
1099 @itemize @bullet
1100 @item uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t)
1101 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
1102 @end itemize
1103
1104
1105 @itemize @bullet
1106 @item int32x2_t vsub_s32 (int32x2_t, int32x2_t)
1107 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
1108 @end itemize
1109
1110
1111 @itemize @bullet
1112 @item int16x4_t vsub_s16 (int16x4_t, int16x4_t)
1113 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
1114 @end itemize
1115
1116
1117 @itemize @bullet
1118 @item int8x8_t vsub_s8 (int8x8_t, int8x8_t)
1119 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
1120 @end itemize
1121
1122
1123 @itemize @bullet
1124 @item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
1125 @*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
1126 @end itemize
1127
1128
1129 @itemize @bullet
1130 @item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
1131 @end itemize
1132
1133
1134 @itemize @bullet
1135 @item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
1136 @end itemize
1137
1138
1139 @itemize @bullet
1140 @item uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t)
1141 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1142 @end itemize
1143
1144
1145 @itemize @bullet
1146 @item uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t)
1147 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1148 @end itemize
1149
1150
1151 @itemize @bullet
1152 @item uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t)
1153 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1154 @end itemize
1155
1156
1157 @itemize @bullet
1158 @item int32x4_t vsubq_s32 (int32x4_t, int32x4_t)
1159 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1160 @end itemize
1161
1162
1163 @itemize @bullet
1164 @item int16x8_t vsubq_s16 (int16x8_t, int16x8_t)
1165 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1166 @end itemize
1167
1168
1169 @itemize @bullet
1170 @item int8x16_t vsubq_s8 (int8x16_t, int8x16_t)
1171 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1172 @end itemize
1173
1174
1175 @itemize @bullet
1176 @item uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t)
1177 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1178 @end itemize
1179
1180
1181 @itemize @bullet
1182 @item int64x2_t vsubq_s64 (int64x2_t, int64x2_t)
1183 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1184 @end itemize
1185
1186
1187 @itemize @bullet
1188 @item float32x4_t vsubq_f32 (float32x4_t, float32x4_t)
1189 @*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{q0}, @var{q0}, @var{q0}}
1190 @end itemize
1191
1192
1193 @itemize @bullet
1194 @item uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t)
1195 @*@emph{Form of expected instruction(s):} @code{vsubl.u32 @var{q0}, @var{d0}, @var{d0}}
1196 @end itemize
1197
1198
1199 @itemize @bullet
1200 @item uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t)
1201 @*@emph{Form of expected instruction(s):} @code{vsubl.u16 @var{q0}, @var{d0}, @var{d0}}
1202 @end itemize
1203
1204
1205 @itemize @bullet
1206 @item uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t)
1207 @*@emph{Form of expected instruction(s):} @code{vsubl.u8 @var{q0}, @var{d0}, @var{d0}}
1208 @end itemize
1209
1210
1211 @itemize @bullet
1212 @item int64x2_t vsubl_s32 (int32x2_t, int32x2_t)
1213 @*@emph{Form of expected instruction(s):} @code{vsubl.s32 @var{q0}, @var{d0}, @var{d0}}
1214 @end itemize
1215
1216
1217 @itemize @bullet
1218 @item int32x4_t vsubl_s16 (int16x4_t, int16x4_t)
1219 @*@emph{Form of expected instruction(s):} @code{vsubl.s16 @var{q0}, @var{d0}, @var{d0}}
1220 @end itemize
1221
1222
1223 @itemize @bullet
1224 @item int16x8_t vsubl_s8 (int8x8_t, int8x8_t)
1225 @*@emph{Form of expected instruction(s):} @code{vsubl.s8 @var{q0}, @var{d0}, @var{d0}}
1226 @end itemize
1227
1228
1229 @itemize @bullet
1230 @item uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t)
1231 @*@emph{Form of expected instruction(s):} @code{vsubw.u32 @var{q0}, @var{q0}, @var{d0}}
1232 @end itemize
1233
1234
1235 @itemize @bullet
1236 @item uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t)
1237 @*@emph{Form of expected instruction(s):} @code{vsubw.u16 @var{q0}, @var{q0}, @var{d0}}
1238 @end itemize
1239
1240
1241 @itemize @bullet
1242 @item uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t)
1243 @*@emph{Form of expected instruction(s):} @code{vsubw.u8 @var{q0}, @var{q0}, @var{d0}}
1244 @end itemize
1245
1246
1247 @itemize @bullet
1248 @item int64x2_t vsubw_s32 (int64x2_t, int32x2_t)
1249 @*@emph{Form of expected instruction(s):} @code{vsubw.s32 @var{q0}, @var{q0}, @var{d0}}
1250 @end itemize
1251
1252
1253 @itemize @bullet
1254 @item int32x4_t vsubw_s16 (int32x4_t, int16x4_t)
1255 @*@emph{Form of expected instruction(s):} @code{vsubw.s16 @var{q0}, @var{q0}, @var{d0}}
1256 @end itemize
1257
1258
1259 @itemize @bullet
1260 @item int16x8_t vsubw_s8 (int16x8_t, int8x8_t)
1261 @*@emph{Form of expected instruction(s):} @code{vsubw.s8 @var{q0}, @var{q0}, @var{d0}}
1262 @end itemize
1263
1264
1265 @itemize @bullet
1266 @item uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t)
1267 @*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{d0}, @var{d0}, @var{d0}}
1268 @end itemize
1269
1270
1271 @itemize @bullet
1272 @item uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t)
1273 @*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{d0}, @var{d0}, @var{d0}}
1274 @end itemize
1275
1276
1277 @itemize @bullet
1278 @item uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t)
1279 @*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{d0}, @var{d0}, @var{d0}}
1280 @end itemize
1281
1282
1283 @itemize @bullet
1284 @item int32x2_t vhsub_s32 (int32x2_t, int32x2_t)
1285 @*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{d0}, @var{d0}, @var{d0}}
1286 @end itemize
1287
1288
1289 @itemize @bullet
1290 @item int16x4_t vhsub_s16 (int16x4_t, int16x4_t)
1291 @*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{d0}, @var{d0}, @var{d0}}
1292 @end itemize
1293
1294
1295 @itemize @bullet
1296 @item int8x8_t vhsub_s8 (int8x8_t, int8x8_t)
1297 @*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{d0}, @var{d0}, @var{d0}}
1298 @end itemize
1299
1300
1301 @itemize @bullet
1302 @item uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t)
1303 @*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{q0}, @var{q0}, @var{q0}}
1304 @end itemize
1305
1306
1307 @itemize @bullet
1308 @item uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t)
1309 @*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{q0}, @var{q0}, @var{q0}}
1310 @end itemize
1311
1312
1313 @itemize @bullet
1314 @item uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t)
1315 @*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{q0}, @var{q0}, @var{q0}}
1316 @end itemize
1317
1318
1319 @itemize @bullet
1320 @item int32x4_t vhsubq_s32 (int32x4_t, int32x4_t)
1321 @*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{q0}, @var{q0}, @var{q0}}
1322 @end itemize
1323
1324
1325 @itemize @bullet
1326 @item int16x8_t vhsubq_s16 (int16x8_t, int16x8_t)
1327 @*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{q0}, @var{q0}, @var{q0}}
1328 @end itemize
1329
1330
1331 @itemize @bullet
1332 @item int8x16_t vhsubq_s8 (int8x16_t, int8x16_t)
1333 @*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{q0}, @var{q0}, @var{q0}}
1334 @end itemize
1335
1336
1337 @itemize @bullet
1338 @item uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t)
1339 @*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{d0}, @var{d0}, @var{d0}}
1340 @end itemize
1341
1342
1343 @itemize @bullet
1344 @item uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t)
1345 @*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{d0}, @var{d0}, @var{d0}}
1346 @end itemize
1347
1348
1349 @itemize @bullet
1350 @item uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t)
1351 @*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{d0}, @var{d0}, @var{d0}}
1352 @end itemize
1353
1354
1355 @itemize @bullet
1356 @item int32x2_t vqsub_s32 (int32x2_t, int32x2_t)
1357 @*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{d0}, @var{d0}, @var{d0}}
1358 @end itemize
1359
1360
1361 @itemize @bullet
1362 @item int16x4_t vqsub_s16 (int16x4_t, int16x4_t)
1363 @*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{d0}, @var{d0}, @var{d0}}
1364 @end itemize
1365
1366
1367 @itemize @bullet
1368 @item int8x8_t vqsub_s8 (int8x8_t, int8x8_t)
1369 @*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{d0}, @var{d0}, @var{d0}}
1370 @end itemize
1371
1372
1373 @itemize @bullet
1374 @item uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t)
1375 @*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{d0}, @var{d0}, @var{d0}}
1376 @end itemize
1377
1378
1379 @itemize @bullet
1380 @item int64x1_t vqsub_s64 (int64x1_t, int64x1_t)
1381 @*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{d0}, @var{d0}, @var{d0}}
1382 @end itemize
1383
1384
1385 @itemize @bullet
1386 @item uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t)
1387 @*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{q0}, @var{q0}, @var{q0}}
1388 @end itemize
1389
1390
1391 @itemize @bullet
1392 @item uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t)
1393 @*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{q0}, @var{q0}, @var{q0}}
1394 @end itemize
1395
1396
1397 @itemize @bullet
1398 @item uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t)
1399 @*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{q0}, @var{q0}, @var{q0}}
1400 @end itemize
1401
1402
1403 @itemize @bullet
1404 @item int32x4_t vqsubq_s32 (int32x4_t, int32x4_t)
1405 @*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{q0}, @var{q0}, @var{q0}}
1406 @end itemize
1407
1408
1409 @itemize @bullet
1410 @item int16x8_t vqsubq_s16 (int16x8_t, int16x8_t)
1411 @*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{q0}, @var{q0}, @var{q0}}
1412 @end itemize
1413
1414
1415 @itemize @bullet
1416 @item int8x16_t vqsubq_s8 (int8x16_t, int8x16_t)
1417 @*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{q0}, @var{q0}, @var{q0}}
1418 @end itemize
1419
1420
1421 @itemize @bullet
1422 @item uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t)
1423 @*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{q0}, @var{q0}, @var{q0}}
1424 @end itemize
1425
1426
1427 @itemize @bullet
1428 @item int64x2_t vqsubq_s64 (int64x2_t, int64x2_t)
1429 @*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{q0}, @var{q0}, @var{q0}}
1430 @end itemize
1431
1432
1433 @itemize @bullet
1434 @item uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t)
1435 @*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1436 @end itemize
1437
1438
1439 @itemize @bullet
1440 @item uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t)
1441 @*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1442 @end itemize
1443
1444
1445 @itemize @bullet
1446 @item uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t)
1447 @*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1448 @end itemize
1449
1450
1451 @itemize @bullet
1452 @item int32x2_t vsubhn_s64 (int64x2_t, int64x2_t)
1453 @*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1454 @end itemize
1455
1456
1457 @itemize @bullet
1458 @item int16x4_t vsubhn_s32 (int32x4_t, int32x4_t)
1459 @*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1460 @end itemize
1461
1462
1463 @itemize @bullet
1464 @item int8x8_t vsubhn_s16 (int16x8_t, int16x8_t)
1465 @*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1466 @end itemize
1467
1468
1469 @itemize @bullet
1470 @item uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t)
1471 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1472 @end itemize
1473
1474
1475 @itemize @bullet
1476 @item uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t)
1477 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1478 @end itemize
1479
1480
1481 @itemize @bullet
1482 @item uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t)
1483 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1484 @end itemize
1485
1486
1487 @itemize @bullet
1488 @item int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t)
1489 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1490 @end itemize
1491
1492
1493 @itemize @bullet
1494 @item int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t)
1495 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1496 @end itemize
1497
1498
1499 @itemize @bullet
1500 @item int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t)
1501 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1502 @end itemize
1503
1504
1505
1506
1507 @subsubsection Comparison (equal-to)
1508
1509 @itemize @bullet
1510 @item uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t)
1511 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1512 @end itemize
1513
1514
1515 @itemize @bullet
1516 @item uint16x4_t vceq_u16 (uint16x4_t, uint16x4_t)
1517 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1518 @end itemize
1519
1520
1521 @itemize @bullet
1522 @item uint8x8_t vceq_u8 (uint8x8_t, uint8x8_t)
1523 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1524 @end itemize
1525
1526
1527 @itemize @bullet
1528 @item uint32x2_t vceq_s32 (int32x2_t, int32x2_t)
1529 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1530 @end itemize
1531
1532
1533 @itemize @bullet
1534 @item uint16x4_t vceq_s16 (int16x4_t, int16x4_t)
1535 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1536 @end itemize
1537
1538
1539 @itemize @bullet
1540 @item uint8x8_t vceq_s8 (int8x8_t, int8x8_t)
1541 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1542 @end itemize
1543
1544
1545 @itemize @bullet
1546 @item uint32x2_t vceq_f32 (float32x2_t, float32x2_t)
1547 @*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{d0}, @var{d0}, @var{d0}}
1548 @end itemize
1549
1550
1551 @itemize @bullet
1552 @item uint8x8_t vceq_p8 (poly8x8_t, poly8x8_t)
1553 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1554 @end itemize
1555
1556
1557 @itemize @bullet
1558 @item uint32x4_t vceqq_u32 (uint32x4_t, uint32x4_t)
1559 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1560 @end itemize
1561
1562
1563 @itemize @bullet
1564 @item uint16x8_t vceqq_u16 (uint16x8_t, uint16x8_t)
1565 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1566 @end itemize
1567
1568
1569 @itemize @bullet
1570 @item uint8x16_t vceqq_u8 (uint8x16_t, uint8x16_t)
1571 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1572 @end itemize
1573
1574
1575 @itemize @bullet
1576 @item uint32x4_t vceqq_s32 (int32x4_t, int32x4_t)
1577 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1578 @end itemize
1579
1580
1581 @itemize @bullet
1582 @item uint16x8_t vceqq_s16 (int16x8_t, int16x8_t)
1583 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1584 @end itemize
1585
1586
1587 @itemize @bullet
1588 @item uint8x16_t vceqq_s8 (int8x16_t, int8x16_t)
1589 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1590 @end itemize
1591
1592
1593 @itemize @bullet
1594 @item uint32x4_t vceqq_f32 (float32x4_t, float32x4_t)
1595 @*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{q0}, @var{q0}, @var{q0}}
1596 @end itemize
1597
1598
1599 @itemize @bullet
1600 @item uint8x16_t vceqq_p8 (poly8x16_t, poly8x16_t)
1601 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1602 @end itemize
1603
1604
1605
1606
1607 @subsubsection Comparison (greater-than-or-equal-to)
1608
1609 @itemize @bullet
1610 @item uint32x2_t vcge_s32 (int32x2_t, int32x2_t)
1611 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1612 @end itemize
1613
1614
1615 @itemize @bullet
1616 @item uint16x4_t vcge_s16 (int16x4_t, int16x4_t)
1617 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1618 @end itemize
1619
1620
1621 @itemize @bullet
1622 @item uint8x8_t vcge_s8 (int8x8_t, int8x8_t)
1623 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1624 @end itemize
1625
1626
1627 @itemize @bullet
1628 @item uint32x2_t vcge_f32 (float32x2_t, float32x2_t)
1629 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1630 @end itemize
1631
1632
1633 @itemize @bullet
1634 @item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t)
1635 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1636 @end itemize
1637
1638
1639 @itemize @bullet
1640 @item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t)
1641 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1642 @end itemize
1643
1644
1645 @itemize @bullet
1646 @item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t)
1647 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1648 @end itemize
1649
1650
1651 @itemize @bullet
1652 @item uint32x4_t vcgeq_s32 (int32x4_t, int32x4_t)
1653 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1654 @end itemize
1655
1656
1657 @itemize @bullet
1658 @item uint16x8_t vcgeq_s16 (int16x8_t, int16x8_t)
1659 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1660 @end itemize
1661
1662
1663 @itemize @bullet
1664 @item uint8x16_t vcgeq_s8 (int8x16_t, int8x16_t)
1665 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1666 @end itemize
1667
1668
1669 @itemize @bullet
1670 @item uint32x4_t vcgeq_f32 (float32x4_t, float32x4_t)
1671 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1672 @end itemize
1673
1674
1675 @itemize @bullet
1676 @item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t)
1677 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1678 @end itemize
1679
1680
1681 @itemize @bullet
1682 @item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t)
1683 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1684 @end itemize
1685
1686
1687 @itemize @bullet
1688 @item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t)
1689 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1690 @end itemize
1691
1692
1693
1694
1695 @subsubsection Comparison (less-than-or-equal-to)
1696
1697 @itemize @bullet
1698 @item uint32x2_t vcle_s32 (int32x2_t, int32x2_t)
1699 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1700 @end itemize
1701
1702
1703 @itemize @bullet
1704 @item uint16x4_t vcle_s16 (int16x4_t, int16x4_t)
1705 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1706 @end itemize
1707
1708
1709 @itemize @bullet
1710 @item uint8x8_t vcle_s8 (int8x8_t, int8x8_t)
1711 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1712 @end itemize
1713
1714
1715 @itemize @bullet
1716 @item uint32x2_t vcle_f32 (float32x2_t, float32x2_t)
1717 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1718 @end itemize
1719
1720
1721 @itemize @bullet
1722 @item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t)
1723 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1724 @end itemize
1725
1726
1727 @itemize @bullet
1728 @item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t)
1729 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1730 @end itemize
1731
1732
1733 @itemize @bullet
1734 @item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t)
1735 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1736 @end itemize
1737
1738
1739 @itemize @bullet
1740 @item uint32x4_t vcleq_s32 (int32x4_t, int32x4_t)
1741 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1742 @end itemize
1743
1744
1745 @itemize @bullet
1746 @item uint16x8_t vcleq_s16 (int16x8_t, int16x8_t)
1747 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1748 @end itemize
1749
1750
1751 @itemize @bullet
1752 @item uint8x16_t vcleq_s8 (int8x16_t, int8x16_t)
1753 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1754 @end itemize
1755
1756
1757 @itemize @bullet
1758 @item uint32x4_t vcleq_f32 (float32x4_t, float32x4_t)
1759 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1760 @end itemize
1761
1762
1763 @itemize @bullet
1764 @item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t)
1765 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1766 @end itemize
1767
1768
1769 @itemize @bullet
1770 @item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t)
1771 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1772 @end itemize
1773
1774
1775 @itemize @bullet
1776 @item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t)
1777 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1778 @end itemize
1779
1780
1781
1782
1783 @subsubsection Comparison (greater-than)
1784
1785 @itemize @bullet
1786 @item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t)
1787 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1788 @end itemize
1789
1790
1791 @itemize @bullet
1792 @item uint16x4_t vcgt_s16 (int16x4_t, int16x4_t)
1793 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1794 @end itemize
1795
1796
1797 @itemize @bullet
1798 @item uint8x8_t vcgt_s8 (int8x8_t, int8x8_t)
1799 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1800 @end itemize
1801
1802
1803 @itemize @bullet
1804 @item uint32x2_t vcgt_f32 (float32x2_t, float32x2_t)
1805 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1806 @end itemize
1807
1808
1809 @itemize @bullet
1810 @item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t)
1811 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1812 @end itemize
1813
1814
1815 @itemize @bullet
1816 @item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t)
1817 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1818 @end itemize
1819
1820
1821 @itemize @bullet
1822 @item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t)
1823 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1824 @end itemize
1825
1826
1827 @itemize @bullet
1828 @item uint32x4_t vcgtq_s32 (int32x4_t, int32x4_t)
1829 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1830 @end itemize
1831
1832
1833 @itemize @bullet
1834 @item uint16x8_t vcgtq_s16 (int16x8_t, int16x8_t)
1835 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1836 @end itemize
1837
1838
1839 @itemize @bullet
1840 @item uint8x16_t vcgtq_s8 (int8x16_t, int8x16_t)
1841 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1842 @end itemize
1843
1844
1845 @itemize @bullet
1846 @item uint32x4_t vcgtq_f32 (float32x4_t, float32x4_t)
1847 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1848 @end itemize
1849
1850
1851 @itemize @bullet
1852 @item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t)
1853 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1854 @end itemize
1855
1856
1857 @itemize @bullet
1858 @item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t)
1859 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1860 @end itemize
1861
1862
1863 @itemize @bullet
1864 @item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t)
1865 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1866 @end itemize
1867
1868
1869
1870
1871 @subsubsection Comparison (less-than)
1872
1873 @itemize @bullet
1874 @item uint32x2_t vclt_s32 (int32x2_t, int32x2_t)
1875 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1876 @end itemize
1877
1878
1879 @itemize @bullet
1880 @item uint16x4_t vclt_s16 (int16x4_t, int16x4_t)
1881 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1882 @end itemize
1883
1884
1885 @itemize @bullet
1886 @item uint8x8_t vclt_s8 (int8x8_t, int8x8_t)
1887 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1888 @end itemize
1889
1890
1891 @itemize @bullet
1892 @item uint32x2_t vclt_f32 (float32x2_t, float32x2_t)
1893 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1894 @end itemize
1895
1896
1897 @itemize @bullet
1898 @item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t)
1899 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1900 @end itemize
1901
1902
1903 @itemize @bullet
1904 @item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t)
1905 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1906 @end itemize
1907
1908
1909 @itemize @bullet
1910 @item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t)
1911 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1912 @end itemize
1913
1914
1915 @itemize @bullet
1916 @item uint32x4_t vcltq_s32 (int32x4_t, int32x4_t)
1917 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1918 @end itemize
1919
1920
1921 @itemize @bullet
1922 @item uint16x8_t vcltq_s16 (int16x8_t, int16x8_t)
1923 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1924 @end itemize
1925
1926
1927 @itemize @bullet
1928 @item uint8x16_t vcltq_s8 (int8x16_t, int8x16_t)
1929 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1930 @end itemize
1931
1932
1933 @itemize @bullet
1934 @item uint32x4_t vcltq_f32 (float32x4_t, float32x4_t)
1935 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1936 @end itemize
1937
1938
1939 @itemize @bullet
1940 @item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t)
1941 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1942 @end itemize
1943
1944
1945 @itemize @bullet
1946 @item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t)
1947 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1948 @end itemize
1949
1950
1951 @itemize @bullet
1952 @item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t)
1953 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1954 @end itemize
1955
1956
1957
1958
1959 @subsubsection Comparison (absolute greater-than-or-equal-to)
1960
1961 @itemize @bullet
1962 @item uint32x2_t vcage_f32 (float32x2_t, float32x2_t)
1963 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1964 @end itemize
1965
1966
1967 @itemize @bullet
1968 @item uint32x4_t vcageq_f32 (float32x4_t, float32x4_t)
1969 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1970 @end itemize
1971
1972
1973
1974
1975 @subsubsection Comparison (absolute less-than-or-equal-to)
1976
1977 @itemize @bullet
1978 @item uint32x2_t vcale_f32 (float32x2_t, float32x2_t)
1979 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1980 @end itemize
1981
1982
1983 @itemize @bullet
1984 @item uint32x4_t vcaleq_f32 (float32x4_t, float32x4_t)
1985 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1986 @end itemize
1987
1988
1989
1990
1991 @subsubsection Comparison (absolute greater-than)
1992
1993 @itemize @bullet
1994 @item uint32x2_t vcagt_f32 (float32x2_t, float32x2_t)
1995 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
1996 @end itemize
1997
1998
1999 @itemize @bullet
2000 @item uint32x4_t vcagtq_f32 (float32x4_t, float32x4_t)
2001 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
2002 @end itemize
2003
2004
2005
2006
2007 @subsubsection Comparison (absolute less-than)
2008
2009 @itemize @bullet
2010 @item uint32x2_t vcalt_f32 (float32x2_t, float32x2_t)
2011 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
2012 @end itemize
2013
2014
2015 @itemize @bullet
2016 @item uint32x4_t vcaltq_f32 (float32x4_t, float32x4_t)
2017 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
2018 @end itemize
2019
2020
2021
2022
2023 @subsubsection Test bits
2024
2025 @itemize @bullet
2026 @item uint32x2_t vtst_u32 (uint32x2_t, uint32x2_t)
2027 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
2028 @end itemize
2029
2030
2031 @itemize @bullet
2032 @item uint16x4_t vtst_u16 (uint16x4_t, uint16x4_t)
2033 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
2034 @end itemize
2035
2036
2037 @itemize @bullet
2038 @item uint8x8_t vtst_u8 (uint8x8_t, uint8x8_t)
2039 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
2040 @end itemize
2041
2042
2043 @itemize @bullet
2044 @item uint32x2_t vtst_s32 (int32x2_t, int32x2_t)
2045 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
2046 @end itemize
2047
2048
2049 @itemize @bullet
2050 @item uint16x4_t vtst_s16 (int16x4_t, int16x4_t)
2051 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
2052 @end itemize
2053
2054
2055 @itemize @bullet
2056 @item uint8x8_t vtst_s8 (int8x8_t, int8x8_t)
2057 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
2058 @end itemize
2059
2060
2061 @itemize @bullet
2062 @item uint8x8_t vtst_p8 (poly8x8_t, poly8x8_t)
2063 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
2064 @end itemize
2065
2066
2067 @itemize @bullet
2068 @item uint32x4_t vtstq_u32 (uint32x4_t, uint32x4_t)
2069 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
2070 @end itemize
2071
2072
2073 @itemize @bullet
2074 @item uint16x8_t vtstq_u16 (uint16x8_t, uint16x8_t)
2075 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
2076 @end itemize
2077
2078
2079 @itemize @bullet
2080 @item uint8x16_t vtstq_u8 (uint8x16_t, uint8x16_t)
2081 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2082 @end itemize
2083
2084
2085 @itemize @bullet
2086 @item uint32x4_t vtstq_s32 (int32x4_t, int32x4_t)
2087 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
2088 @end itemize
2089
2090
2091 @itemize @bullet
2092 @item uint16x8_t vtstq_s16 (int16x8_t, int16x8_t)
2093 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
2094 @end itemize
2095
2096
2097 @itemize @bullet
2098 @item uint8x16_t vtstq_s8 (int8x16_t, int8x16_t)
2099 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2100 @end itemize
2101
2102
2103 @itemize @bullet
2104 @item uint8x16_t vtstq_p8 (poly8x16_t, poly8x16_t)
2105 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2106 @end itemize
2107
2108
2109
2110
2111 @subsubsection Absolute difference
2112
2113 @itemize @bullet
2114 @item uint32x2_t vabd_u32 (uint32x2_t, uint32x2_t)
2115 @*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{d0}, @var{d0}, @var{d0}}
2116 @end itemize
2117
2118
2119 @itemize @bullet
2120 @item uint16x4_t vabd_u16 (uint16x4_t, uint16x4_t)
2121 @*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{d0}, @var{d0}, @var{d0}}
2122 @end itemize
2123
2124
2125 @itemize @bullet
2126 @item uint8x8_t vabd_u8 (uint8x8_t, uint8x8_t)
2127 @*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{d0}, @var{d0}, @var{d0}}
2128 @end itemize
2129
2130
2131 @itemize @bullet
2132 @item int32x2_t vabd_s32 (int32x2_t, int32x2_t)
2133 @*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{d0}, @var{d0}, @var{d0}}
2134 @end itemize
2135
2136
2137 @itemize @bullet
2138 @item int16x4_t vabd_s16 (int16x4_t, int16x4_t)
2139 @*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{d0}, @var{d0}, @var{d0}}
2140 @end itemize
2141
2142
2143 @itemize @bullet
2144 @item int8x8_t vabd_s8 (int8x8_t, int8x8_t)
2145 @*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{d0}, @var{d0}, @var{d0}}
2146 @end itemize
2147
2148
2149 @itemize @bullet
2150 @item float32x2_t vabd_f32 (float32x2_t, float32x2_t)
2151 @*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{d0}, @var{d0}, @var{d0}}
2152 @end itemize
2153
2154
2155 @itemize @bullet
2156 @item uint32x4_t vabdq_u32 (uint32x4_t, uint32x4_t)
2157 @*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{q0}, @var{q0}, @var{q0}}
2158 @end itemize
2159
2160
2161 @itemize @bullet
2162 @item uint16x8_t vabdq_u16 (uint16x8_t, uint16x8_t)
2163 @*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{q0}, @var{q0}, @var{q0}}
2164 @end itemize
2165
2166
2167 @itemize @bullet
2168 @item uint8x16_t vabdq_u8 (uint8x16_t, uint8x16_t)
2169 @*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{q0}, @var{q0}, @var{q0}}
2170 @end itemize
2171
2172
2173 @itemize @bullet
2174 @item int32x4_t vabdq_s32 (int32x4_t, int32x4_t)
2175 @*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{q0}, @var{q0}, @var{q0}}
2176 @end itemize
2177
2178
2179 @itemize @bullet
2180 @item int16x8_t vabdq_s16 (int16x8_t, int16x8_t)
2181 @*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{q0}, @var{q0}, @var{q0}}
2182 @end itemize
2183
2184
2185 @itemize @bullet
2186 @item int8x16_t vabdq_s8 (int8x16_t, int8x16_t)
2187 @*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{q0}, @var{q0}, @var{q0}}
2188 @end itemize
2189
2190
2191 @itemize @bullet
2192 @item float32x4_t vabdq_f32 (float32x4_t, float32x4_t)
2193 @*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{q0}, @var{q0}, @var{q0}}
2194 @end itemize
2195
2196
2197 @itemize @bullet
2198 @item uint64x2_t vabdl_u32 (uint32x2_t, uint32x2_t)
2199 @*@emph{Form of expected instruction(s):} @code{vabdl.u32 @var{q0}, @var{d0}, @var{d0}}
2200 @end itemize
2201
2202
2203 @itemize @bullet
2204 @item uint32x4_t vabdl_u16 (uint16x4_t, uint16x4_t)
2205 @*@emph{Form of expected instruction(s):} @code{vabdl.u16 @var{q0}, @var{d0}, @var{d0}}
2206 @end itemize
2207
2208
2209 @itemize @bullet
2210 @item uint16x8_t vabdl_u8 (uint8x8_t, uint8x8_t)
2211 @*@emph{Form of expected instruction(s):} @code{vabdl.u8 @var{q0}, @var{d0}, @var{d0}}
2212 @end itemize
2213
2214
2215 @itemize @bullet
2216 @item int64x2_t vabdl_s32 (int32x2_t, int32x2_t)
2217 @*@emph{Form of expected instruction(s):} @code{vabdl.s32 @var{q0}, @var{d0}, @var{d0}}
2218 @end itemize
2219
2220
2221 @itemize @bullet
2222 @item int32x4_t vabdl_s16 (int16x4_t, int16x4_t)
2223 @*@emph{Form of expected instruction(s):} @code{vabdl.s16 @var{q0}, @var{d0}, @var{d0}}
2224 @end itemize
2225
2226
2227 @itemize @bullet
2228 @item int16x8_t vabdl_s8 (int8x8_t, int8x8_t)
2229 @*@emph{Form of expected instruction(s):} @code{vabdl.s8 @var{q0}, @var{d0}, @var{d0}}
2230 @end itemize
2231
2232
2233
2234
2235 @subsubsection Absolute difference and accumulate
2236
2237 @itemize @bullet
2238 @item uint32x2_t vaba_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
2239 @*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{d0}, @var{d0}, @var{d0}}
2240 @end itemize
2241
2242
2243 @itemize @bullet
2244 @item uint16x4_t vaba_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
2245 @*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{d0}, @var{d0}, @var{d0}}
2246 @end itemize
2247
2248
2249 @itemize @bullet
2250 @item uint8x8_t vaba_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
2251 @*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{d0}, @var{d0}, @var{d0}}
2252 @end itemize
2253
2254
2255 @itemize @bullet
2256 @item int32x2_t vaba_s32 (int32x2_t, int32x2_t, int32x2_t)
2257 @*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{d0}, @var{d0}, @var{d0}}
2258 @end itemize
2259
2260
2261 @itemize @bullet
2262 @item int16x4_t vaba_s16 (int16x4_t, int16x4_t, int16x4_t)
2263 @*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{d0}, @var{d0}, @var{d0}}
2264 @end itemize
2265
2266
2267 @itemize @bullet
2268 @item int8x8_t vaba_s8 (int8x8_t, int8x8_t, int8x8_t)
2269 @*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{d0}, @var{d0}, @var{d0}}
2270 @end itemize
2271
2272
2273 @itemize @bullet
2274 @item uint32x4_t vabaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
2275 @*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{q0}, @var{q0}, @var{q0}}
2276 @end itemize
2277
2278
2279 @itemize @bullet
2280 @item uint16x8_t vabaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
2281 @*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{q0}, @var{q0}, @var{q0}}
2282 @end itemize
2283
2284
2285 @itemize @bullet
2286 @item uint8x16_t vabaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
2287 @*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{q0}, @var{q0}, @var{q0}}
2288 @end itemize
2289
2290
2291 @itemize @bullet
2292 @item int32x4_t vabaq_s32 (int32x4_t, int32x4_t, int32x4_t)
2293 @*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{q0}, @var{q0}, @var{q0}}
2294 @end itemize
2295
2296
2297 @itemize @bullet
2298 @item int16x8_t vabaq_s16 (int16x8_t, int16x8_t, int16x8_t)
2299 @*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{q0}, @var{q0}, @var{q0}}
2300 @end itemize
2301
2302
2303 @itemize @bullet
2304 @item int8x16_t vabaq_s8 (int8x16_t, int8x16_t, int8x16_t)
2305 @*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{q0}, @var{q0}, @var{q0}}
2306 @end itemize
2307
2308
2309 @itemize @bullet
2310 @item uint64x2_t vabal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
2311 @*@emph{Form of expected instruction(s):} @code{vabal.u32 @var{q0}, @var{d0}, @var{d0}}
2312 @end itemize
2313
2314
2315 @itemize @bullet
2316 @item uint32x4_t vabal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
2317 @*@emph{Form of expected instruction(s):} @code{vabal.u16 @var{q0}, @var{d0}, @var{d0}}
2318 @end itemize
2319
2320
2321 @itemize @bullet
2322 @item uint16x8_t vabal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
2323 @*@emph{Form of expected instruction(s):} @code{vabal.u8 @var{q0}, @var{d0}, @var{d0}}
2324 @end itemize
2325
2326
2327 @itemize @bullet
2328 @item int64x2_t vabal_s32 (int64x2_t, int32x2_t, int32x2_t)
2329 @*@emph{Form of expected instruction(s):} @code{vabal.s32 @var{q0}, @var{d0}, @var{d0}}
2330 @end itemize
2331
2332
2333 @itemize @bullet
2334 @item int32x4_t vabal_s16 (int32x4_t, int16x4_t, int16x4_t)
2335 @*@emph{Form of expected instruction(s):} @code{vabal.s16 @var{q0}, @var{d0}, @var{d0}}
2336 @end itemize
2337
2338
2339 @itemize @bullet
2340 @item int16x8_t vabal_s8 (int16x8_t, int8x8_t, int8x8_t)
2341 @*@emph{Form of expected instruction(s):} @code{vabal.s8 @var{q0}, @var{d0}, @var{d0}}
2342 @end itemize
2343
2344
2345
2346
2347 @subsubsection Maximum
2348
2349 @itemize @bullet
2350 @item uint32x2_t vmax_u32 (uint32x2_t, uint32x2_t)
2351 @*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{d0}, @var{d0}, @var{d0}}
2352 @end itemize
2353
2354
2355 @itemize @bullet
2356 @item uint16x4_t vmax_u16 (uint16x4_t, uint16x4_t)
2357 @*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{d0}, @var{d0}, @var{d0}}
2358 @end itemize
2359
2360
2361 @itemize @bullet
2362 @item uint8x8_t vmax_u8 (uint8x8_t, uint8x8_t)
2363 @*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{d0}, @var{d0}, @var{d0}}
2364 @end itemize
2365
2366
2367 @itemize @bullet
2368 @item int32x2_t vmax_s32 (int32x2_t, int32x2_t)
2369 @*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{d0}, @var{d0}, @var{d0}}
2370 @end itemize
2371
2372
2373 @itemize @bullet
2374 @item int16x4_t vmax_s16 (int16x4_t, int16x4_t)
2375 @*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{d0}, @var{d0}, @var{d0}}
2376 @end itemize
2377
2378
2379 @itemize @bullet
2380 @item int8x8_t vmax_s8 (int8x8_t, int8x8_t)
2381 @*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{d0}, @var{d0}, @var{d0}}
2382 @end itemize
2383
2384
2385 @itemize @bullet
2386 @item float32x2_t vmax_f32 (float32x2_t, float32x2_t)
2387 @*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{d0}, @var{d0}, @var{d0}}
2388 @end itemize
2389
2390
2391 @itemize @bullet
2392 @item uint32x4_t vmaxq_u32 (uint32x4_t, uint32x4_t)
2393 @*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{q0}, @var{q0}, @var{q0}}
2394 @end itemize
2395
2396
2397 @itemize @bullet
2398 @item uint16x8_t vmaxq_u16 (uint16x8_t, uint16x8_t)
2399 @*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{q0}, @var{q0}, @var{q0}}
2400 @end itemize
2401
2402
2403 @itemize @bullet
2404 @item uint8x16_t vmaxq_u8 (uint8x16_t, uint8x16_t)
2405 @*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{q0}, @var{q0}, @var{q0}}
2406 @end itemize
2407
2408
2409 @itemize @bullet
2410 @item int32x4_t vmaxq_s32 (int32x4_t, int32x4_t)
2411 @*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{q0}, @var{q0}, @var{q0}}
2412 @end itemize
2413
2414
2415 @itemize @bullet
2416 @item int16x8_t vmaxq_s16 (int16x8_t, int16x8_t)
2417 @*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{q0}, @var{q0}, @var{q0}}
2418 @end itemize
2419
2420
2421 @itemize @bullet
2422 @item int8x16_t vmaxq_s8 (int8x16_t, int8x16_t)
2423 @*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{q0}, @var{q0}, @var{q0}}
2424 @end itemize
2425
2426
2427 @itemize @bullet
2428 @item float32x4_t vmaxq_f32 (float32x4_t, float32x4_t)
2429 @*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{q0}, @var{q0}, @var{q0}}
2430 @end itemize
2431
2432
2433
2434
2435 @subsubsection Minimum
2436
2437 @itemize @bullet
2438 @item uint32x2_t vmin_u32 (uint32x2_t, uint32x2_t)
2439 @*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{d0}, @var{d0}, @var{d0}}
2440 @end itemize
2441
2442
2443 @itemize @bullet
2444 @item uint16x4_t vmin_u16 (uint16x4_t, uint16x4_t)
2445 @*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{d0}, @var{d0}, @var{d0}}
2446 @end itemize
2447
2448
2449 @itemize @bullet
2450 @item uint8x8_t vmin_u8 (uint8x8_t, uint8x8_t)
2451 @*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{d0}, @var{d0}, @var{d0}}
2452 @end itemize
2453
2454
2455 @itemize @bullet
2456 @item int32x2_t vmin_s32 (int32x2_t, int32x2_t)
2457 @*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{d0}, @var{d0}, @var{d0}}
2458 @end itemize
2459
2460
2461 @itemize @bullet
2462 @item int16x4_t vmin_s16 (int16x4_t, int16x4_t)
2463 @*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{d0}, @var{d0}, @var{d0}}
2464 @end itemize
2465
2466
2467 @itemize @bullet
2468 @item int8x8_t vmin_s8 (int8x8_t, int8x8_t)
2469 @*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{d0}, @var{d0}, @var{d0}}
2470 @end itemize
2471
2472
2473 @itemize @bullet
2474 @item float32x2_t vmin_f32 (float32x2_t, float32x2_t)
2475 @*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{d0}, @var{d0}, @var{d0}}
2476 @end itemize
2477
2478
2479 @itemize @bullet
2480 @item uint32x4_t vminq_u32 (uint32x4_t, uint32x4_t)
2481 @*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{q0}, @var{q0}, @var{q0}}
2482 @end itemize
2483
2484
2485 @itemize @bullet
2486 @item uint16x8_t vminq_u16 (uint16x8_t, uint16x8_t)
2487 @*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{q0}, @var{q0}, @var{q0}}
2488 @end itemize
2489
2490
2491 @itemize @bullet
2492 @item uint8x16_t vminq_u8 (uint8x16_t, uint8x16_t)
2493 @*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{q0}, @var{q0}, @var{q0}}
2494 @end itemize
2495
2496
2497 @itemize @bullet
2498 @item int32x4_t vminq_s32 (int32x4_t, int32x4_t)
2499 @*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{q0}, @var{q0}, @var{q0}}
2500 @end itemize
2501
2502
2503 @itemize @bullet
2504 @item int16x8_t vminq_s16 (int16x8_t, int16x8_t)
2505 @*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{q0}, @var{q0}, @var{q0}}
2506 @end itemize
2507
2508
2509 @itemize @bullet
2510 @item int8x16_t vminq_s8 (int8x16_t, int8x16_t)
2511 @*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{q0}, @var{q0}, @var{q0}}
2512 @end itemize
2513
2514
2515 @itemize @bullet
2516 @item float32x4_t vminq_f32 (float32x4_t, float32x4_t)
2517 @*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{q0}, @var{q0}, @var{q0}}
2518 @end itemize
2519
2520
2521
2522
2523 @subsubsection Pairwise add
2524
2525 @itemize @bullet
2526 @item uint32x2_t vpadd_u32 (uint32x2_t, uint32x2_t)
2527 @*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2528 @end itemize
2529
2530
2531 @itemize @bullet
2532 @item uint16x4_t vpadd_u16 (uint16x4_t, uint16x4_t)
2533 @*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2534 @end itemize
2535
2536
2537 @itemize @bullet
2538 @item uint8x8_t vpadd_u8 (uint8x8_t, uint8x8_t)
2539 @*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2540 @end itemize
2541
2542
2543 @itemize @bullet
2544 @item int32x2_t vpadd_s32 (int32x2_t, int32x2_t)
2545 @*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2546 @end itemize
2547
2548
2549 @itemize @bullet
2550 @item int16x4_t vpadd_s16 (int16x4_t, int16x4_t)
2551 @*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2552 @end itemize
2553
2554
2555 @itemize @bullet
2556 @item int8x8_t vpadd_s8 (int8x8_t, int8x8_t)
2557 @*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2558 @end itemize
2559
2560
2561 @itemize @bullet
2562 @item float32x2_t vpadd_f32 (float32x2_t, float32x2_t)
2563 @*@emph{Form of expected instruction(s):} @code{vpadd.f32 @var{d0}, @var{d0}, @var{d0}}
2564 @end itemize
2565
2566
2567 @itemize @bullet
2568 @item uint64x1_t vpaddl_u32 (uint32x2_t)
2569 @*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{d0}, @var{d0}}
2570 @end itemize
2571
2572
2573 @itemize @bullet
2574 @item uint32x2_t vpaddl_u16 (uint16x4_t)
2575 @*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{d0}, @var{d0}}
2576 @end itemize
2577
2578
2579 @itemize @bullet
2580 @item uint16x4_t vpaddl_u8 (uint8x8_t)
2581 @*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{d0}, @var{d0}}
2582 @end itemize
2583
2584
2585 @itemize @bullet
2586 @item int64x1_t vpaddl_s32 (int32x2_t)
2587 @*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{d0}, @var{d0}}
2588 @end itemize
2589
2590
2591 @itemize @bullet
2592 @item int32x2_t vpaddl_s16 (int16x4_t)
2593 @*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{d0}, @var{d0}}
2594 @end itemize
2595
2596
2597 @itemize @bullet
2598 @item int16x4_t vpaddl_s8 (int8x8_t)
2599 @*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{d0}, @var{d0}}
2600 @end itemize
2601
2602
2603 @itemize @bullet
2604 @item uint64x2_t vpaddlq_u32 (uint32x4_t)
2605 @*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{q0}, @var{q0}}
2606 @end itemize
2607
2608
2609 @itemize @bullet
2610 @item uint32x4_t vpaddlq_u16 (uint16x8_t)
2611 @*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{q0}, @var{q0}}
2612 @end itemize
2613
2614
2615 @itemize @bullet
2616 @item uint16x8_t vpaddlq_u8 (uint8x16_t)
2617 @*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{q0}, @var{q0}}
2618 @end itemize
2619
2620
2621 @itemize @bullet
2622 @item int64x2_t vpaddlq_s32 (int32x4_t)
2623 @*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{q0}, @var{q0}}
2624 @end itemize
2625
2626
2627 @itemize @bullet
2628 @item int32x4_t vpaddlq_s16 (int16x8_t)
2629 @*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{q0}, @var{q0}}
2630 @end itemize
2631
2632
2633 @itemize @bullet
2634 @item int16x8_t vpaddlq_s8 (int8x16_t)
2635 @*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{q0}, @var{q0}}
2636 @end itemize
2637
2638
2639
2640
2641 @subsubsection Pairwise add, single_opcode widen and accumulate
2642
2643 @itemize @bullet
2644 @item uint64x1_t vpadal_u32 (uint64x1_t, uint32x2_t)
2645 @*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{d0}, @var{d0}}
2646 @end itemize
2647
2648
2649 @itemize @bullet
2650 @item uint32x2_t vpadal_u16 (uint32x2_t, uint16x4_t)
2651 @*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{d0}, @var{d0}}
2652 @end itemize
2653
2654
2655 @itemize @bullet
2656 @item uint16x4_t vpadal_u8 (uint16x4_t, uint8x8_t)
2657 @*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{d0}, @var{d0}}
2658 @end itemize
2659
2660
2661 @itemize @bullet
2662 @item int64x1_t vpadal_s32 (int64x1_t, int32x2_t)
2663 @*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{d0}, @var{d0}}
2664 @end itemize
2665
2666
2667 @itemize @bullet
2668 @item int32x2_t vpadal_s16 (int32x2_t, int16x4_t)
2669 @*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{d0}, @var{d0}}
2670 @end itemize
2671
2672
2673 @itemize @bullet
2674 @item int16x4_t vpadal_s8 (int16x4_t, int8x8_t)
2675 @*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{d0}, @var{d0}}
2676 @end itemize
2677
2678
2679 @itemize @bullet
2680 @item uint64x2_t vpadalq_u32 (uint64x2_t, uint32x4_t)
2681 @*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{q0}, @var{q0}}
2682 @end itemize
2683
2684
2685 @itemize @bullet
2686 @item uint32x4_t vpadalq_u16 (uint32x4_t, uint16x8_t)
2687 @*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{q0}, @var{q0}}
2688 @end itemize
2689
2690
2691 @itemize @bullet
2692 @item uint16x8_t vpadalq_u8 (uint16x8_t, uint8x16_t)
2693 @*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{q0}, @var{q0}}
2694 @end itemize
2695
2696
2697 @itemize @bullet
2698 @item int64x2_t vpadalq_s32 (int64x2_t, int32x4_t)
2699 @*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{q0}, @var{q0}}
2700 @end itemize
2701
2702
2703 @itemize @bullet
2704 @item int32x4_t vpadalq_s16 (int32x4_t, int16x8_t)
2705 @*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{q0}, @var{q0}}
2706 @end itemize
2707
2708
2709 @itemize @bullet
2710 @item int16x8_t vpadalq_s8 (int16x8_t, int8x16_t)
2711 @*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{q0}, @var{q0}}
2712 @end itemize
2713
2714
2715
2716
2717 @subsubsection Folding maximum
2718
2719 @itemize @bullet
2720 @item uint32x2_t vpmax_u32 (uint32x2_t, uint32x2_t)
2721 @*@emph{Form of expected instruction(s):} @code{vpmax.u32 @var{d0}, @var{d0}, @var{d0}}
2722 @end itemize
2723
2724
2725 @itemize @bullet
2726 @item uint16x4_t vpmax_u16 (uint16x4_t, uint16x4_t)
2727 @*@emph{Form of expected instruction(s):} @code{vpmax.u16 @var{d0}, @var{d0}, @var{d0}}
2728 @end itemize
2729
2730
2731 @itemize @bullet
2732 @item uint8x8_t vpmax_u8 (uint8x8_t, uint8x8_t)
2733 @*@emph{Form of expected instruction(s):} @code{vpmax.u8 @var{d0}, @var{d0}, @var{d0}}
2734 @end itemize
2735
2736
2737 @itemize @bullet
2738 @item int32x2_t vpmax_s32 (int32x2_t, int32x2_t)
2739 @*@emph{Form of expected instruction(s):} @code{vpmax.s32 @var{d0}, @var{d0}, @var{d0}}
2740 @end itemize
2741
2742
2743 @itemize @bullet
2744 @item int16x4_t vpmax_s16 (int16x4_t, int16x4_t)
2745 @*@emph{Form of expected instruction(s):} @code{vpmax.s16 @var{d0}, @var{d0}, @var{d0}}
2746 @end itemize
2747
2748
2749 @itemize @bullet
2750 @item int8x8_t vpmax_s8 (int8x8_t, int8x8_t)
2751 @*@emph{Form of expected instruction(s):} @code{vpmax.s8 @var{d0}, @var{d0}, @var{d0}}
2752 @end itemize
2753
2754
2755 @itemize @bullet
2756 @item float32x2_t vpmax_f32 (float32x2_t, float32x2_t)
2757 @*@emph{Form of expected instruction(s):} @code{vpmax.f32 @var{d0}, @var{d0}, @var{d0}}
2758 @end itemize
2759
2760
2761
2762
2763 @subsubsection Folding minimum
2764
2765 @itemize @bullet
2766 @item uint32x2_t vpmin_u32 (uint32x2_t, uint32x2_t)
2767 @*@emph{Form of expected instruction(s):} @code{vpmin.u32 @var{d0}, @var{d0}, @var{d0}}
2768 @end itemize
2769
2770
2771 @itemize @bullet
2772 @item uint16x4_t vpmin_u16 (uint16x4_t, uint16x4_t)
2773 @*@emph{Form of expected instruction(s):} @code{vpmin.u16 @var{d0}, @var{d0}, @var{d0}}
2774 @end itemize
2775
2776
2777 @itemize @bullet
2778 @item uint8x8_t vpmin_u8 (uint8x8_t, uint8x8_t)
2779 @*@emph{Form of expected instruction(s):} @code{vpmin.u8 @var{d0}, @var{d0}, @var{d0}}
2780 @end itemize
2781
2782
2783 @itemize @bullet
2784 @item int32x2_t vpmin_s32 (int32x2_t, int32x2_t)
2785 @*@emph{Form of expected instruction(s):} @code{vpmin.s32 @var{d0}, @var{d0}, @var{d0}}
2786 @end itemize
2787
2788
2789 @itemize @bullet
2790 @item int16x4_t vpmin_s16 (int16x4_t, int16x4_t)
2791 @*@emph{Form of expected instruction(s):} @code{vpmin.s16 @var{d0}, @var{d0}, @var{d0}}
2792 @end itemize
2793
2794
2795 @itemize @bullet
2796 @item int8x8_t vpmin_s8 (int8x8_t, int8x8_t)
2797 @*@emph{Form of expected instruction(s):} @code{vpmin.s8 @var{d0}, @var{d0}, @var{d0}}
2798 @end itemize
2799
2800
2801 @itemize @bullet
2802 @item float32x2_t vpmin_f32 (float32x2_t, float32x2_t)
2803 @*@emph{Form of expected instruction(s):} @code{vpmin.f32 @var{d0}, @var{d0}, @var{d0}}
2804 @end itemize
2805
2806
2807
2808
2809 @subsubsection Reciprocal step
2810
2811 @itemize @bullet
2812 @item float32x2_t vrecps_f32 (float32x2_t, float32x2_t)
2813 @*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{d0}, @var{d0}, @var{d0}}
2814 @end itemize
2815
2816
2817 @itemize @bullet
2818 @item float32x4_t vrecpsq_f32 (float32x4_t, float32x4_t)
2819 @*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{q0}, @var{q0}, @var{q0}}
2820 @end itemize
2821
2822
2823 @itemize @bullet
2824 @item float32x2_t vrsqrts_f32 (float32x2_t, float32x2_t)
2825 @*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{d0}, @var{d0}, @var{d0}}
2826 @end itemize
2827
2828
2829 @itemize @bullet
2830 @item float32x4_t vrsqrtsq_f32 (float32x4_t, float32x4_t)
2831 @*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{q0}, @var{q0}, @var{q0}}
2832 @end itemize
2833
2834
2835
2836
2837 @subsubsection Vector shift left
2838
2839 @itemize @bullet
2840 @item uint32x2_t vshl_u32 (uint32x2_t, int32x2_t)
2841 @*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{d0}, @var{d0}, @var{d0}}
2842 @end itemize
2843
2844
2845 @itemize @bullet
2846 @item uint16x4_t vshl_u16 (uint16x4_t, int16x4_t)
2847 @*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{d0}, @var{d0}, @var{d0}}
2848 @end itemize
2849
2850
2851 @itemize @bullet
2852 @item uint8x8_t vshl_u8 (uint8x8_t, int8x8_t)
2853 @*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{d0}, @var{d0}, @var{d0}}
2854 @end itemize
2855
2856
2857 @itemize @bullet
2858 @item int32x2_t vshl_s32 (int32x2_t, int32x2_t)
2859 @*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{d0}, @var{d0}, @var{d0}}
2860 @end itemize
2861
2862
2863 @itemize @bullet
2864 @item int16x4_t vshl_s16 (int16x4_t, int16x4_t)
2865 @*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{d0}, @var{d0}, @var{d0}}
2866 @end itemize
2867
2868
2869 @itemize @bullet
2870 @item int8x8_t vshl_s8 (int8x8_t, int8x8_t)
2871 @*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{d0}, @var{d0}, @var{d0}}
2872 @end itemize
2873
2874
2875 @itemize @bullet
2876 @item uint64x1_t vshl_u64 (uint64x1_t, int64x1_t)
2877 @*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{d0}, @var{d0}, @var{d0}}
2878 @end itemize
2879
2880
2881 @itemize @bullet
2882 @item int64x1_t vshl_s64 (int64x1_t, int64x1_t)
2883 @*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{d0}, @var{d0}, @var{d0}}
2884 @end itemize
2885
2886
2887 @itemize @bullet
2888 @item uint32x4_t vshlq_u32 (uint32x4_t, int32x4_t)
2889 @*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{q0}, @var{q0}, @var{q0}}
2890 @end itemize
2891
2892
2893 @itemize @bullet
2894 @item uint16x8_t vshlq_u16 (uint16x8_t, int16x8_t)
2895 @*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{q0}, @var{q0}, @var{q0}}
2896 @end itemize
2897
2898
2899 @itemize @bullet
2900 @item uint8x16_t vshlq_u8 (uint8x16_t, int8x16_t)
2901 @*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{q0}, @var{q0}, @var{q0}}
2902 @end itemize
2903
2904
2905 @itemize @bullet
2906 @item int32x4_t vshlq_s32 (int32x4_t, int32x4_t)
2907 @*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{q0}, @var{q0}, @var{q0}}
2908 @end itemize
2909
2910
2911 @itemize @bullet
2912 @item int16x8_t vshlq_s16 (int16x8_t, int16x8_t)
2913 @*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{q0}, @var{q0}, @var{q0}}
2914 @end itemize
2915
2916
2917 @itemize @bullet
2918 @item int8x16_t vshlq_s8 (int8x16_t, int8x16_t)
2919 @*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{q0}, @var{q0}, @var{q0}}
2920 @end itemize
2921
2922
2923 @itemize @bullet
2924 @item uint64x2_t vshlq_u64 (uint64x2_t, int64x2_t)
2925 @*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{q0}, @var{q0}, @var{q0}}
2926 @end itemize
2927
2928
2929 @itemize @bullet
2930 @item int64x2_t vshlq_s64 (int64x2_t, int64x2_t)
2931 @*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{q0}, @var{q0}, @var{q0}}
2932 @end itemize
2933
2934
2935 @itemize @bullet
2936 @item uint32x2_t vrshl_u32 (uint32x2_t, int32x2_t)
2937 @*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{d0}, @var{d0}, @var{d0}}
2938 @end itemize
2939
2940
2941 @itemize @bullet
2942 @item uint16x4_t vrshl_u16 (uint16x4_t, int16x4_t)
2943 @*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{d0}, @var{d0}, @var{d0}}
2944 @end itemize
2945
2946
2947 @itemize @bullet
2948 @item uint8x8_t vrshl_u8 (uint8x8_t, int8x8_t)
2949 @*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{d0}, @var{d0}, @var{d0}}
2950 @end itemize
2951
2952
2953 @itemize @bullet
2954 @item int32x2_t vrshl_s32 (int32x2_t, int32x2_t)
2955 @*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{d0}, @var{d0}, @var{d0}}
2956 @end itemize
2957
2958
2959 @itemize @bullet
2960 @item int16x4_t vrshl_s16 (int16x4_t, int16x4_t)
2961 @*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{d0}, @var{d0}, @var{d0}}
2962 @end itemize
2963
2964
2965 @itemize @bullet
2966 @item int8x8_t vrshl_s8 (int8x8_t, int8x8_t)
2967 @*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{d0}, @var{d0}, @var{d0}}
2968 @end itemize
2969
2970
2971 @itemize @bullet
2972 @item uint64x1_t vrshl_u64 (uint64x1_t, int64x1_t)
2973 @*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{d0}, @var{d0}, @var{d0}}
2974 @end itemize
2975
2976
2977 @itemize @bullet
2978 @item int64x1_t vrshl_s64 (int64x1_t, int64x1_t)
2979 @*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{d0}, @var{d0}, @var{d0}}
2980 @end itemize
2981
2982
2983 @itemize @bullet
2984 @item uint32x4_t vrshlq_u32 (uint32x4_t, int32x4_t)
2985 @*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{q0}, @var{q0}, @var{q0}}
2986 @end itemize
2987
2988
2989 @itemize @bullet
2990 @item uint16x8_t vrshlq_u16 (uint16x8_t, int16x8_t)
2991 @*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{q0}, @var{q0}, @var{q0}}
2992 @end itemize
2993
2994
2995 @itemize @bullet
2996 @item uint8x16_t vrshlq_u8 (uint8x16_t, int8x16_t)
2997 @*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{q0}, @var{q0}, @var{q0}}
2998 @end itemize
2999
3000
3001 @itemize @bullet
3002 @item int32x4_t vrshlq_s32 (int32x4_t, int32x4_t)
3003 @*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{q0}, @var{q0}, @var{q0}}
3004 @end itemize
3005
3006
3007 @itemize @bullet
3008 @item int16x8_t vrshlq_s16 (int16x8_t, int16x8_t)
3009 @*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{q0}, @var{q0}, @var{q0}}
3010 @end itemize
3011
3012
3013 @itemize @bullet
3014 @item int8x16_t vrshlq_s8 (int8x16_t, int8x16_t)
3015 @*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{q0}, @var{q0}, @var{q0}}
3016 @end itemize
3017
3018
3019 @itemize @bullet
3020 @item uint64x2_t vrshlq_u64 (uint64x2_t, int64x2_t)
3021 @*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{q0}, @var{q0}, @var{q0}}
3022 @end itemize
3023
3024
3025 @itemize @bullet
3026 @item int64x2_t vrshlq_s64 (int64x2_t, int64x2_t)
3027 @*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{q0}, @var{q0}, @var{q0}}
3028 @end itemize
3029
3030
3031 @itemize @bullet
3032 @item uint32x2_t vqshl_u32 (uint32x2_t, int32x2_t)
3033 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, @var{d0}}
3034 @end itemize
3035
3036
3037 @itemize @bullet
3038 @item uint16x4_t vqshl_u16 (uint16x4_t, int16x4_t)
3039 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, @var{d0}}
3040 @end itemize
3041
3042
3043 @itemize @bullet
3044 @item uint8x8_t vqshl_u8 (uint8x8_t, int8x8_t)
3045 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, @var{d0}}
3046 @end itemize
3047
3048
3049 @itemize @bullet
3050 @item int32x2_t vqshl_s32 (int32x2_t, int32x2_t)
3051 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, @var{d0}}
3052 @end itemize
3053
3054
3055 @itemize @bullet
3056 @item int16x4_t vqshl_s16 (int16x4_t, int16x4_t)
3057 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, @var{d0}}
3058 @end itemize
3059
3060
3061 @itemize @bullet
3062 @item int8x8_t vqshl_s8 (int8x8_t, int8x8_t)
3063 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, @var{d0}}
3064 @end itemize
3065
3066
3067 @itemize @bullet
3068 @item uint64x1_t vqshl_u64 (uint64x1_t, int64x1_t)
3069 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, @var{d0}}
3070 @end itemize
3071
3072
3073 @itemize @bullet
3074 @item int64x1_t vqshl_s64 (int64x1_t, int64x1_t)
3075 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, @var{d0}}
3076 @end itemize
3077
3078
3079 @itemize @bullet
3080 @item uint32x4_t vqshlq_u32 (uint32x4_t, int32x4_t)
3081 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, @var{q0}}
3082 @end itemize
3083
3084
3085 @itemize @bullet
3086 @item uint16x8_t vqshlq_u16 (uint16x8_t, int16x8_t)
3087 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, @var{q0}}
3088 @end itemize
3089
3090
3091 @itemize @bullet
3092 @item uint8x16_t vqshlq_u8 (uint8x16_t, int8x16_t)
3093 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, @var{q0}}
3094 @end itemize
3095
3096
3097 @itemize @bullet
3098 @item int32x4_t vqshlq_s32 (int32x4_t, int32x4_t)
3099 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, @var{q0}}
3100 @end itemize
3101
3102
3103 @itemize @bullet
3104 @item int16x8_t vqshlq_s16 (int16x8_t, int16x8_t)
3105 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, @var{q0}}
3106 @end itemize
3107
3108
3109 @itemize @bullet
3110 @item int8x16_t vqshlq_s8 (int8x16_t, int8x16_t)
3111 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, @var{q0}}
3112 @end itemize
3113
3114
3115 @itemize @bullet
3116 @item uint64x2_t vqshlq_u64 (uint64x2_t, int64x2_t)
3117 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, @var{q0}}
3118 @end itemize
3119
3120
3121 @itemize @bullet
3122 @item int64x2_t vqshlq_s64 (int64x2_t, int64x2_t)
3123 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, @var{q0}}
3124 @end itemize
3125
3126
3127 @itemize @bullet
3128 @item uint32x2_t vqrshl_u32 (uint32x2_t, int32x2_t)
3129 @*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{d0}, @var{d0}, @var{d0}}
3130 @end itemize
3131
3132
3133 @itemize @bullet
3134 @item uint16x4_t vqrshl_u16 (uint16x4_t, int16x4_t)
3135 @*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{d0}, @var{d0}, @var{d0}}
3136 @end itemize
3137
3138
3139 @itemize @bullet
3140 @item uint8x8_t vqrshl_u8 (uint8x8_t, int8x8_t)
3141 @*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{d0}, @var{d0}, @var{d0}}
3142 @end itemize
3143
3144
3145 @itemize @bullet
3146 @item int32x2_t vqrshl_s32 (int32x2_t, int32x2_t)
3147 @*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{d0}, @var{d0}, @var{d0}}
3148 @end itemize
3149
3150
3151 @itemize @bullet
3152 @item int16x4_t vqrshl_s16 (int16x4_t, int16x4_t)
3153 @*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{d0}, @var{d0}, @var{d0}}
3154 @end itemize
3155
3156
3157 @itemize @bullet
3158 @item int8x8_t vqrshl_s8 (int8x8_t, int8x8_t)
3159 @*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{d0}, @var{d0}, @var{d0}}
3160 @end itemize
3161
3162
3163 @itemize @bullet
3164 @item uint64x1_t vqrshl_u64 (uint64x1_t, int64x1_t)
3165 @*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{d0}, @var{d0}, @var{d0}}
3166 @end itemize
3167
3168
3169 @itemize @bullet
3170 @item int64x1_t vqrshl_s64 (int64x1_t, int64x1_t)
3171 @*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{d0}, @var{d0}, @var{d0}}
3172 @end itemize
3173
3174
3175 @itemize @bullet
3176 @item uint32x4_t vqrshlq_u32 (uint32x4_t, int32x4_t)
3177 @*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{q0}, @var{q0}, @var{q0}}
3178 @end itemize
3179
3180
3181 @itemize @bullet
3182 @item uint16x8_t vqrshlq_u16 (uint16x8_t, int16x8_t)
3183 @*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{q0}, @var{q0}, @var{q0}}
3184 @end itemize
3185
3186
3187 @itemize @bullet
3188 @item uint8x16_t vqrshlq_u8 (uint8x16_t, int8x16_t)
3189 @*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{q0}, @var{q0}, @var{q0}}
3190 @end itemize
3191
3192
3193 @itemize @bullet
3194 @item int32x4_t vqrshlq_s32 (int32x4_t, int32x4_t)
3195 @*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{q0}, @var{q0}, @var{q0}}
3196 @end itemize
3197
3198
3199 @itemize @bullet
3200 @item int16x8_t vqrshlq_s16 (int16x8_t, int16x8_t)
3201 @*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{q0}, @var{q0}, @var{q0}}
3202 @end itemize
3203
3204
3205 @itemize @bullet
3206 @item int8x16_t vqrshlq_s8 (int8x16_t, int8x16_t)
3207 @*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{q0}, @var{q0}, @var{q0}}
3208 @end itemize
3209
3210
3211 @itemize @bullet
3212 @item uint64x2_t vqrshlq_u64 (uint64x2_t, int64x2_t)
3213 @*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{q0}, @var{q0}, @var{q0}}
3214 @end itemize
3215
3216
3217 @itemize @bullet
3218 @item int64x2_t vqrshlq_s64 (int64x2_t, int64x2_t)
3219 @*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{q0}, @var{q0}, @var{q0}}
3220 @end itemize
3221
3222
3223
3224
3225 @subsubsection Vector shift left by constant
3226
3227 @itemize @bullet
3228 @item uint32x2_t vshl_n_u32 (uint32x2_t, const int)
3229 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3230 @end itemize
3231
3232
3233 @itemize @bullet
3234 @item uint16x4_t vshl_n_u16 (uint16x4_t, const int)
3235 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3236 @end itemize
3237
3238
3239 @itemize @bullet
3240 @item uint8x8_t vshl_n_u8 (uint8x8_t, const int)
3241 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3242 @end itemize
3243
3244
3245 @itemize @bullet
3246 @item int32x2_t vshl_n_s32 (int32x2_t, const int)
3247 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3248 @end itemize
3249
3250
3251 @itemize @bullet
3252 @item int16x4_t vshl_n_s16 (int16x4_t, const int)
3253 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3254 @end itemize
3255
3256
3257 @itemize @bullet
3258 @item int8x8_t vshl_n_s8 (int8x8_t, const int)
3259 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3260 @end itemize
3261
3262
3263 @itemize @bullet
3264 @item uint64x1_t vshl_n_u64 (uint64x1_t, const int)
3265 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3266 @end itemize
3267
3268
3269 @itemize @bullet
3270 @item int64x1_t vshl_n_s64 (int64x1_t, const int)
3271 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3272 @end itemize
3273
3274
3275 @itemize @bullet
3276 @item uint32x4_t vshlq_n_u32 (uint32x4_t, const int)
3277 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3278 @end itemize
3279
3280
3281 @itemize @bullet
3282 @item uint16x8_t vshlq_n_u16 (uint16x8_t, const int)
3283 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3284 @end itemize
3285
3286
3287 @itemize @bullet
3288 @item uint8x16_t vshlq_n_u8 (uint8x16_t, const int)
3289 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3290 @end itemize
3291
3292
3293 @itemize @bullet
3294 @item int32x4_t vshlq_n_s32 (int32x4_t, const int)
3295 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3296 @end itemize
3297
3298
3299 @itemize @bullet
3300 @item int16x8_t vshlq_n_s16 (int16x8_t, const int)
3301 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3302 @end itemize
3303
3304
3305 @itemize @bullet
3306 @item int8x16_t vshlq_n_s8 (int8x16_t, const int)
3307 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3308 @end itemize
3309
3310
3311 @itemize @bullet
3312 @item uint64x2_t vshlq_n_u64 (uint64x2_t, const int)
3313 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3314 @end itemize
3315
3316
3317 @itemize @bullet
3318 @item int64x2_t vshlq_n_s64 (int64x2_t, const int)
3319 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3320 @end itemize
3321
3322
3323 @itemize @bullet
3324 @item uint32x2_t vqshl_n_u32 (uint32x2_t, const int)
3325 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, #@var{0}}
3326 @end itemize
3327
3328
3329 @itemize @bullet
3330 @item uint16x4_t vqshl_n_u16 (uint16x4_t, const int)
3331 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, #@var{0}}
3332 @end itemize
3333
3334
3335 @itemize @bullet
3336 @item uint8x8_t vqshl_n_u8 (uint8x8_t, const int)
3337 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, #@var{0}}
3338 @end itemize
3339
3340
3341 @itemize @bullet
3342 @item int32x2_t vqshl_n_s32 (int32x2_t, const int)
3343 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, #@var{0}}
3344 @end itemize
3345
3346
3347 @itemize @bullet
3348 @item int16x4_t vqshl_n_s16 (int16x4_t, const int)
3349 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, #@var{0}}
3350 @end itemize
3351
3352
3353 @itemize @bullet
3354 @item int8x8_t vqshl_n_s8 (int8x8_t, const int)
3355 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, #@var{0}}
3356 @end itemize
3357
3358
3359 @itemize @bullet
3360 @item uint64x1_t vqshl_n_u64 (uint64x1_t, const int)
3361 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, #@var{0}}
3362 @end itemize
3363
3364
3365 @itemize @bullet
3366 @item int64x1_t vqshl_n_s64 (int64x1_t, const int)
3367 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, #@var{0}}
3368 @end itemize
3369
3370
3371 @itemize @bullet
3372 @item uint32x4_t vqshlq_n_u32 (uint32x4_t, const int)
3373 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, #@var{0}}
3374 @end itemize
3375
3376
3377 @itemize @bullet
3378 @item uint16x8_t vqshlq_n_u16 (uint16x8_t, const int)
3379 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, #@var{0}}
3380 @end itemize
3381
3382
3383 @itemize @bullet
3384 @item uint8x16_t vqshlq_n_u8 (uint8x16_t, const int)
3385 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, #@var{0}}
3386 @end itemize
3387
3388
3389 @itemize @bullet
3390 @item int32x4_t vqshlq_n_s32 (int32x4_t, const int)
3391 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, #@var{0}}
3392 @end itemize
3393
3394
3395 @itemize @bullet
3396 @item int16x8_t vqshlq_n_s16 (int16x8_t, const int)
3397 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, #@var{0}}
3398 @end itemize
3399
3400
3401 @itemize @bullet
3402 @item int8x16_t vqshlq_n_s8 (int8x16_t, const int)
3403 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, #@var{0}}
3404 @end itemize
3405
3406
3407 @itemize @bullet
3408 @item uint64x2_t vqshlq_n_u64 (uint64x2_t, const int)
3409 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, #@var{0}}
3410 @end itemize
3411
3412
3413 @itemize @bullet
3414 @item int64x2_t vqshlq_n_s64 (int64x2_t, const int)
3415 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, #@var{0}}
3416 @end itemize
3417
3418
3419 @itemize @bullet
3420 @item uint64x1_t vqshlu_n_s64 (int64x1_t, const int)
3421 @*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{d0}, @var{d0}, #@var{0}}
3422 @end itemize
3423
3424
3425 @itemize @bullet
3426 @item uint32x2_t vqshlu_n_s32 (int32x2_t, const int)
3427 @*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{d0}, @var{d0}, #@var{0}}
3428 @end itemize
3429
3430
3431 @itemize @bullet
3432 @item uint16x4_t vqshlu_n_s16 (int16x4_t, const int)
3433 @*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{d0}, @var{d0}, #@var{0}}
3434 @end itemize
3435
3436
3437 @itemize @bullet
3438 @item uint8x8_t vqshlu_n_s8 (int8x8_t, const int)
3439 @*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{d0}, @var{d0}, #@var{0}}
3440 @end itemize
3441
3442
3443 @itemize @bullet
3444 @item uint64x2_t vqshluq_n_s64 (int64x2_t, const int)
3445 @*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{q0}, @var{q0}, #@var{0}}
3446 @end itemize
3447
3448
3449 @itemize @bullet
3450 @item uint32x4_t vqshluq_n_s32 (int32x4_t, const int)
3451 @*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{q0}, @var{q0}, #@var{0}}
3452 @end itemize
3453
3454
3455 @itemize @bullet
3456 @item uint16x8_t vqshluq_n_s16 (int16x8_t, const int)
3457 @*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{q0}, @var{q0}, #@var{0}}
3458 @end itemize
3459
3460
3461 @itemize @bullet
3462 @item uint8x16_t vqshluq_n_s8 (int8x16_t, const int)
3463 @*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{q0}, @var{q0}, #@var{0}}
3464 @end itemize
3465
3466
3467 @itemize @bullet
3468 @item uint64x2_t vshll_n_u32 (uint32x2_t, const int)
3469 @*@emph{Form of expected instruction(s):} @code{vshll.u32 @var{q0}, @var{d0}, #@var{0}}
3470 @end itemize
3471
3472
3473 @itemize @bullet
3474 @item uint32x4_t vshll_n_u16 (uint16x4_t, const int)
3475 @*@emph{Form of expected instruction(s):} @code{vshll.u16 @var{q0}, @var{d0}, #@var{0}}
3476 @end itemize
3477
3478
3479 @itemize @bullet
3480 @item uint16x8_t vshll_n_u8 (uint8x8_t, const int)
3481 @*@emph{Form of expected instruction(s):} @code{vshll.u8 @var{q0}, @var{d0}, #@var{0}}
3482 @end itemize
3483
3484
3485 @itemize @bullet
3486 @item int64x2_t vshll_n_s32 (int32x2_t, const int)
3487 @*@emph{Form of expected instruction(s):} @code{vshll.s32 @var{q0}, @var{d0}, #@var{0}}
3488 @end itemize
3489
3490
3491 @itemize @bullet
3492 @item int32x4_t vshll_n_s16 (int16x4_t, const int)
3493 @*@emph{Form of expected instruction(s):} @code{vshll.s16 @var{q0}, @var{d0}, #@var{0}}
3494 @end itemize
3495
3496
3497 @itemize @bullet
3498 @item int16x8_t vshll_n_s8 (int8x8_t, const int)
3499 @*@emph{Form of expected instruction(s):} @code{vshll.s8 @var{q0}, @var{d0}, #@var{0}}
3500 @end itemize
3501
3502
3503
3504
3505 @subsubsection Vector shift right by constant
3506
3507 @itemize @bullet
3508 @item uint32x2_t vshr_n_u32 (uint32x2_t, const int)
3509 @*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{d0}, @var{d0}, #@var{0}}
3510 @end itemize
3511
3512
3513 @itemize @bullet
3514 @item uint16x4_t vshr_n_u16 (uint16x4_t, const int)
3515 @*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{d0}, @var{d0}, #@var{0}}
3516 @end itemize
3517
3518
3519 @itemize @bullet
3520 @item uint8x8_t vshr_n_u8 (uint8x8_t, const int)
3521 @*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{d0}, @var{d0}, #@var{0}}
3522 @end itemize
3523
3524
3525 @itemize @bullet
3526 @item int32x2_t vshr_n_s32 (int32x2_t, const int)
3527 @*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{d0}, @var{d0}, #@var{0}}
3528 @end itemize
3529
3530
3531 @itemize @bullet
3532 @item int16x4_t vshr_n_s16 (int16x4_t, const int)
3533 @*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{d0}, @var{d0}, #@var{0}}
3534 @end itemize
3535
3536
3537 @itemize @bullet
3538 @item int8x8_t vshr_n_s8 (int8x8_t, const int)
3539 @*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{d0}, @var{d0}, #@var{0}}
3540 @end itemize
3541
3542
3543 @itemize @bullet
3544 @item uint64x1_t vshr_n_u64 (uint64x1_t, const int)
3545 @*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{d0}, @var{d0}, #@var{0}}
3546 @end itemize
3547
3548
3549 @itemize @bullet
3550 @item int64x1_t vshr_n_s64 (int64x1_t, const int)
3551 @*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{d0}, @var{d0}, #@var{0}}
3552 @end itemize
3553
3554
3555 @itemize @bullet
3556 @item uint32x4_t vshrq_n_u32 (uint32x4_t, const int)
3557 @*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{q0}, @var{q0}, #@var{0}}
3558 @end itemize
3559
3560
3561 @itemize @bullet
3562 @item uint16x8_t vshrq_n_u16 (uint16x8_t, const int)
3563 @*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{q0}, @var{q0}, #@var{0}}
3564 @end itemize
3565
3566
3567 @itemize @bullet
3568 @item uint8x16_t vshrq_n_u8 (uint8x16_t, const int)
3569 @*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{q0}, @var{q0}, #@var{0}}
3570 @end itemize
3571
3572
3573 @itemize @bullet
3574 @item int32x4_t vshrq_n_s32 (int32x4_t, const int)
3575 @*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{q0}, @var{q0}, #@var{0}}
3576 @end itemize
3577
3578
3579 @itemize @bullet
3580 @item int16x8_t vshrq_n_s16 (int16x8_t, const int)
3581 @*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{q0}, @var{q0}, #@var{0}}
3582 @end itemize
3583
3584
3585 @itemize @bullet
3586 @item int8x16_t vshrq_n_s8 (int8x16_t, const int)
3587 @*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{q0}, @var{q0}, #@var{0}}
3588 @end itemize
3589
3590
3591 @itemize @bullet
3592 @item uint64x2_t vshrq_n_u64 (uint64x2_t, const int)
3593 @*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{q0}, @var{q0}, #@var{0}}
3594 @end itemize
3595
3596
3597 @itemize @bullet
3598 @item int64x2_t vshrq_n_s64 (int64x2_t, const int)
3599 @*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{q0}, @var{q0}, #@var{0}}
3600 @end itemize
3601
3602
3603 @itemize @bullet
3604 @item uint32x2_t vrshr_n_u32 (uint32x2_t, const int)
3605 @*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{d0}, @var{d0}, #@var{0}}
3606 @end itemize
3607
3608
3609 @itemize @bullet
3610 @item uint16x4_t vrshr_n_u16 (uint16x4_t, const int)
3611 @*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{d0}, @var{d0}, #@var{0}}
3612 @end itemize
3613
3614
3615 @itemize @bullet
3616 @item uint8x8_t vrshr_n_u8 (uint8x8_t, const int)
3617 @*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{d0}, @var{d0}, #@var{0}}
3618 @end itemize
3619
3620
3621 @itemize @bullet
3622 @item int32x2_t vrshr_n_s32 (int32x2_t, const int)
3623 @*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{d0}, @var{d0}, #@var{0}}
3624 @end itemize
3625
3626
3627 @itemize @bullet
3628 @item int16x4_t vrshr_n_s16 (int16x4_t, const int)
3629 @*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{d0}, @var{d0}, #@var{0}}
3630 @end itemize
3631
3632
3633 @itemize @bullet
3634 @item int8x8_t vrshr_n_s8 (int8x8_t, const int)
3635 @*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{d0}, @var{d0}, #@var{0}}
3636 @end itemize
3637
3638
3639 @itemize @bullet
3640 @item uint64x1_t vrshr_n_u64 (uint64x1_t, const int)
3641 @*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{d0}, @var{d0}, #@var{0}}
3642 @end itemize
3643
3644
3645 @itemize @bullet
3646 @item int64x1_t vrshr_n_s64 (int64x1_t, const int)
3647 @*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{d0}, @var{d0}, #@var{0}}
3648 @end itemize
3649
3650
3651 @itemize @bullet
3652 @item uint32x4_t vrshrq_n_u32 (uint32x4_t, const int)
3653 @*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{q0}, @var{q0}, #@var{0}}
3654 @end itemize
3655
3656
3657 @itemize @bullet
3658 @item uint16x8_t vrshrq_n_u16 (uint16x8_t, const int)
3659 @*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{q0}, @var{q0}, #@var{0}}
3660 @end itemize
3661
3662
3663 @itemize @bullet
3664 @item uint8x16_t vrshrq_n_u8 (uint8x16_t, const int)
3665 @*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{q0}, @var{q0}, #@var{0}}
3666 @end itemize
3667
3668
3669 @itemize @bullet
3670 @item int32x4_t vrshrq_n_s32 (int32x4_t, const int)
3671 @*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{q0}, @var{q0}, #@var{0}}
3672 @end itemize
3673
3674
3675 @itemize @bullet
3676 @item int16x8_t vrshrq_n_s16 (int16x8_t, const int)
3677 @*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{q0}, @var{q0}, #@var{0}}
3678 @end itemize
3679
3680
3681 @itemize @bullet
3682 @item int8x16_t vrshrq_n_s8 (int8x16_t, const int)
3683 @*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{q0}, @var{q0}, #@var{0}}
3684 @end itemize
3685
3686
3687 @itemize @bullet
3688 @item uint64x2_t vrshrq_n_u64 (uint64x2_t, const int)
3689 @*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{q0}, @var{q0}, #@var{0}}
3690 @end itemize
3691
3692
3693 @itemize @bullet
3694 @item int64x2_t vrshrq_n_s64 (int64x2_t, const int)
3695 @*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{q0}, @var{q0}, #@var{0}}
3696 @end itemize
3697
3698
3699 @itemize @bullet
3700 @item uint32x2_t vshrn_n_u64 (uint64x2_t, const int)
3701 @*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3702 @end itemize
3703
3704
3705 @itemize @bullet
3706 @item uint16x4_t vshrn_n_u32 (uint32x4_t, const int)
3707 @*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3708 @end itemize
3709
3710
3711 @itemize @bullet
3712 @item uint8x8_t vshrn_n_u16 (uint16x8_t, const int)
3713 @*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3714 @end itemize
3715
3716
3717 @itemize @bullet
3718 @item int32x2_t vshrn_n_s64 (int64x2_t, const int)
3719 @*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3720 @end itemize
3721
3722
3723 @itemize @bullet
3724 @item int16x4_t vshrn_n_s32 (int32x4_t, const int)
3725 @*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3726 @end itemize
3727
3728
3729 @itemize @bullet
3730 @item int8x8_t vshrn_n_s16 (int16x8_t, const int)
3731 @*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3732 @end itemize
3733
3734
3735 @itemize @bullet
3736 @item uint32x2_t vrshrn_n_u64 (uint64x2_t, const int)
3737 @*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3738 @end itemize
3739
3740
3741 @itemize @bullet
3742 @item uint16x4_t vrshrn_n_u32 (uint32x4_t, const int)
3743 @*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3744 @end itemize
3745
3746
3747 @itemize @bullet
3748 @item uint8x8_t vrshrn_n_u16 (uint16x8_t, const int)
3749 @*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3750 @end itemize
3751
3752
3753 @itemize @bullet
3754 @item int32x2_t vrshrn_n_s64 (int64x2_t, const int)
3755 @*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3756 @end itemize
3757
3758
3759 @itemize @bullet
3760 @item int16x4_t vrshrn_n_s32 (int32x4_t, const int)
3761 @*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3762 @end itemize
3763
3764
3765 @itemize @bullet
3766 @item int8x8_t vrshrn_n_s16 (int16x8_t, const int)
3767 @*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3768 @end itemize
3769
3770
3771 @itemize @bullet
3772 @item uint32x2_t vqshrn_n_u64 (uint64x2_t, const int)
3773 @*@emph{Form of expected instruction(s):} @code{vqshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3774 @end itemize
3775
3776
3777 @itemize @bullet
3778 @item uint16x4_t vqshrn_n_u32 (uint32x4_t, const int)
3779 @*@emph{Form of expected instruction(s):} @code{vqshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3780 @end itemize
3781
3782
3783 @itemize @bullet
3784 @item uint8x8_t vqshrn_n_u16 (uint16x8_t, const int)
3785 @*@emph{Form of expected instruction(s):} @code{vqshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3786 @end itemize
3787
3788
3789 @itemize @bullet
3790 @item int32x2_t vqshrn_n_s64 (int64x2_t, const int)
3791 @*@emph{Form of expected instruction(s):} @code{vqshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3792 @end itemize
3793
3794
3795 @itemize @bullet
3796 @item int16x4_t vqshrn_n_s32 (int32x4_t, const int)
3797 @*@emph{Form of expected instruction(s):} @code{vqshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3798 @end itemize
3799
3800
3801 @itemize @bullet
3802 @item int8x8_t vqshrn_n_s16 (int16x8_t, const int)
3803 @*@emph{Form of expected instruction(s):} @code{vqshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3804 @end itemize
3805
3806
3807 @itemize @bullet
3808 @item uint32x2_t vqrshrn_n_u64 (uint64x2_t, const int)
3809 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3810 @end itemize
3811
3812
3813 @itemize @bullet
3814 @item uint16x4_t vqrshrn_n_u32 (uint32x4_t, const int)
3815 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3816 @end itemize
3817
3818
3819 @itemize @bullet
3820 @item uint8x8_t vqrshrn_n_u16 (uint16x8_t, const int)
3821 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3822 @end itemize
3823
3824
3825 @itemize @bullet
3826 @item int32x2_t vqrshrn_n_s64 (int64x2_t, const int)
3827 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3828 @end itemize
3829
3830
3831 @itemize @bullet
3832 @item int16x4_t vqrshrn_n_s32 (int32x4_t, const int)
3833 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3834 @end itemize
3835
3836
3837 @itemize @bullet
3838 @item int8x8_t vqrshrn_n_s16 (int16x8_t, const int)
3839 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3840 @end itemize
3841
3842
3843 @itemize @bullet
3844 @item uint32x2_t vqshrun_n_s64 (int64x2_t, const int)
3845 @*@emph{Form of expected instruction(s):} @code{vqshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3846 @end itemize
3847
3848
3849 @itemize @bullet
3850 @item uint16x4_t vqshrun_n_s32 (int32x4_t, const int)
3851 @*@emph{Form of expected instruction(s):} @code{vqshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3852 @end itemize
3853
3854
3855 @itemize @bullet
3856 @item uint8x8_t vqshrun_n_s16 (int16x8_t, const int)
3857 @*@emph{Form of expected instruction(s):} @code{vqshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3858 @end itemize
3859
3860
3861 @itemize @bullet
3862 @item uint32x2_t vqrshrun_n_s64 (int64x2_t, const int)
3863 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3864 @end itemize
3865
3866
3867 @itemize @bullet
3868 @item uint16x4_t vqrshrun_n_s32 (int32x4_t, const int)
3869 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3870 @end itemize
3871
3872
3873 @itemize @bullet
3874 @item uint8x8_t vqrshrun_n_s16 (int16x8_t, const int)
3875 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3876 @end itemize
3877
3878
3879
3880
3881 @subsubsection Vector shift right by constant and accumulate
3882
3883 @itemize @bullet
3884 @item uint32x2_t vsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3885 @*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{d0}, @var{d0}, #@var{0}}
3886 @end itemize
3887
3888
3889 @itemize @bullet
3890 @item uint16x4_t vsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3891 @*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{d0}, @var{d0}, #@var{0}}
3892 @end itemize
3893
3894
3895 @itemize @bullet
3896 @item uint8x8_t vsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3897 @*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{d0}, @var{d0}, #@var{0}}
3898 @end itemize
3899
3900
3901 @itemize @bullet
3902 @item int32x2_t vsra_n_s32 (int32x2_t, int32x2_t, const int)
3903 @*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{d0}, @var{d0}, #@var{0}}
3904 @end itemize
3905
3906
3907 @itemize @bullet
3908 @item int16x4_t vsra_n_s16 (int16x4_t, int16x4_t, const int)
3909 @*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{d0}, @var{d0}, #@var{0}}
3910 @end itemize
3911
3912
3913 @itemize @bullet
3914 @item int8x8_t vsra_n_s8 (int8x8_t, int8x8_t, const int)
3915 @*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{d0}, @var{d0}, #@var{0}}
3916 @end itemize
3917
3918
3919 @itemize @bullet
3920 @item uint64x1_t vsra_n_u64 (uint64x1_t, uint64x1_t, const int)
3921 @*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{d0}, @var{d0}, #@var{0}}
3922 @end itemize
3923
3924
3925 @itemize @bullet
3926 @item int64x1_t vsra_n_s64 (int64x1_t, int64x1_t, const int)
3927 @*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{d0}, @var{d0}, #@var{0}}
3928 @end itemize
3929
3930
3931 @itemize @bullet
3932 @item uint32x4_t vsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
3933 @*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{q0}, @var{q0}, #@var{0}}
3934 @end itemize
3935
3936
3937 @itemize @bullet
3938 @item uint16x8_t vsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
3939 @*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{q0}, @var{q0}, #@var{0}}
3940 @end itemize
3941
3942
3943 @itemize @bullet
3944 @item uint8x16_t vsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
3945 @*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{q0}, @var{q0}, #@var{0}}
3946 @end itemize
3947
3948
3949 @itemize @bullet
3950 @item int32x4_t vsraq_n_s32 (int32x4_t, int32x4_t, const int)
3951 @*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{q0}, @var{q0}, #@var{0}}
3952 @end itemize
3953
3954
3955 @itemize @bullet
3956 @item int16x8_t vsraq_n_s16 (int16x8_t, int16x8_t, const int)
3957 @*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{q0}, @var{q0}, #@var{0}}
3958 @end itemize
3959
3960
3961 @itemize @bullet
3962 @item int8x16_t vsraq_n_s8 (int8x16_t, int8x16_t, const int)
3963 @*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{q0}, @var{q0}, #@var{0}}
3964 @end itemize
3965
3966
3967 @itemize @bullet
3968 @item uint64x2_t vsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
3969 @*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{q0}, @var{q0}, #@var{0}}
3970 @end itemize
3971
3972
3973 @itemize @bullet
3974 @item int64x2_t vsraq_n_s64 (int64x2_t, int64x2_t, const int)
3975 @*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{q0}, @var{q0}, #@var{0}}
3976 @end itemize
3977
3978
3979 @itemize @bullet
3980 @item uint32x2_t vrsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3981 @*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{d0}, @var{d0}, #@var{0}}
3982 @end itemize
3983
3984
3985 @itemize @bullet
3986 @item uint16x4_t vrsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3987 @*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{d0}, @var{d0}, #@var{0}}
3988 @end itemize
3989
3990
3991 @itemize @bullet
3992 @item uint8x8_t vrsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3993 @*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{d0}, @var{d0}, #@var{0}}
3994 @end itemize
3995
3996
3997 @itemize @bullet
3998 @item int32x2_t vrsra_n_s32 (int32x2_t, int32x2_t, const int)
3999 @*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{d0}, @var{d0}, #@var{0}}
4000 @end itemize
4001
4002
4003 @itemize @bullet
4004 @item int16x4_t vrsra_n_s16 (int16x4_t, int16x4_t, const int)
4005 @*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{d0}, @var{d0}, #@var{0}}
4006 @end itemize
4007
4008
4009 @itemize @bullet
4010 @item int8x8_t vrsra_n_s8 (int8x8_t, int8x8_t, const int)
4011 @*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{d0}, @var{d0}, #@var{0}}
4012 @end itemize
4013
4014
4015 @itemize @bullet
4016 @item uint64x1_t vrsra_n_u64 (uint64x1_t, uint64x1_t, const int)
4017 @*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{d0}, @var{d0}, #@var{0}}
4018 @end itemize
4019
4020
4021 @itemize @bullet
4022 @item int64x1_t vrsra_n_s64 (int64x1_t, int64x1_t, const int)
4023 @*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{d0}, @var{d0}, #@var{0}}
4024 @end itemize
4025
4026
4027 @itemize @bullet
4028 @item uint32x4_t vrsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
4029 @*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{q0}, @var{q0}, #@var{0}}
4030 @end itemize
4031
4032
4033 @itemize @bullet
4034 @item uint16x8_t vrsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
4035 @*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{q0}, @var{q0}, #@var{0}}
4036 @end itemize
4037
4038
4039 @itemize @bullet
4040 @item uint8x16_t vrsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
4041 @*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{q0}, @var{q0}, #@var{0}}
4042 @end itemize
4043
4044
4045 @itemize @bullet
4046 @item int32x4_t vrsraq_n_s32 (int32x4_t, int32x4_t, const int)
4047 @*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{q0}, @var{q0}, #@var{0}}
4048 @end itemize
4049
4050
4051 @itemize @bullet
4052 @item int16x8_t vrsraq_n_s16 (int16x8_t, int16x8_t, const int)
4053 @*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{q0}, @var{q0}, #@var{0}}
4054 @end itemize
4055
4056
4057 @itemize @bullet
4058 @item int8x16_t vrsraq_n_s8 (int8x16_t, int8x16_t, const int)
4059 @*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{q0}, @var{q0}, #@var{0}}
4060 @end itemize
4061
4062
4063 @itemize @bullet
4064 @item uint64x2_t vrsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
4065 @*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{q0}, @var{q0}, #@var{0}}
4066 @end itemize
4067
4068
4069 @itemize @bullet
4070 @item int64x2_t vrsraq_n_s64 (int64x2_t, int64x2_t, const int)
4071 @*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{q0}, @var{q0}, #@var{0}}
4072 @end itemize
4073
4074
4075
4076
4077 @subsubsection Vector shift right and insert
4078
4079 @itemize @bullet
4080 @item poly64x1_t vsri_n_p64 (poly64x1_t, poly64x1_t, const int)
4081 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4082 @end itemize
4083
4084
4085 @itemize @bullet
4086 @item uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int)
4087 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
4088 @end itemize
4089
4090
4091 @itemize @bullet
4092 @item uint16x4_t vsri_n_u16 (uint16x4_t, uint16x4_t, const int)
4093 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4094 @end itemize
4095
4096
4097 @itemize @bullet
4098 @item uint8x8_t vsri_n_u8 (uint8x8_t, uint8x8_t, const int)
4099 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4100 @end itemize
4101
4102
4103 @itemize @bullet
4104 @item int32x2_t vsri_n_s32 (int32x2_t, int32x2_t, const int)
4105 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
4106 @end itemize
4107
4108
4109 @itemize @bullet
4110 @item int16x4_t vsri_n_s16 (int16x4_t, int16x4_t, const int)
4111 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4112 @end itemize
4113
4114
4115 @itemize @bullet
4116 @item int8x8_t vsri_n_s8 (int8x8_t, int8x8_t, const int)
4117 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4118 @end itemize
4119
4120
4121 @itemize @bullet
4122 @item uint64x1_t vsri_n_u64 (uint64x1_t, uint64x1_t, const int)
4123 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4124 @end itemize
4125
4126
4127 @itemize @bullet
4128 @item int64x1_t vsri_n_s64 (int64x1_t, int64x1_t, const int)
4129 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4130 @end itemize
4131
4132
4133 @itemize @bullet
4134 @item poly16x4_t vsri_n_p16 (poly16x4_t, poly16x4_t, const int)
4135 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4136 @end itemize
4137
4138
4139 @itemize @bullet
4140 @item poly8x8_t vsri_n_p8 (poly8x8_t, poly8x8_t, const int)
4141 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4142 @end itemize
4143
4144
4145 @itemize @bullet
4146 @item poly64x2_t vsriq_n_p64 (poly64x2_t, poly64x2_t, const int)
4147 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4148 @end itemize
4149
4150
4151 @itemize @bullet
4152 @item uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int)
4153 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4154 @end itemize
4155
4156
4157 @itemize @bullet
4158 @item uint16x8_t vsriq_n_u16 (uint16x8_t, uint16x8_t, const int)
4159 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4160 @end itemize
4161
4162
4163 @itemize @bullet
4164 @item uint8x16_t vsriq_n_u8 (uint8x16_t, uint8x16_t, const int)
4165 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4166 @end itemize
4167
4168
4169 @itemize @bullet
4170 @item int32x4_t vsriq_n_s32 (int32x4_t, int32x4_t, const int)
4171 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4172 @end itemize
4173
4174
4175 @itemize @bullet
4176 @item int16x8_t vsriq_n_s16 (int16x8_t, int16x8_t, const int)
4177 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4178 @end itemize
4179
4180
4181 @itemize @bullet
4182 @item int8x16_t vsriq_n_s8 (int8x16_t, int8x16_t, const int)
4183 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4184 @end itemize
4185
4186
4187 @itemize @bullet
4188 @item uint64x2_t vsriq_n_u64 (uint64x2_t, uint64x2_t, const int)
4189 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4190 @end itemize
4191
4192
4193 @itemize @bullet
4194 @item int64x2_t vsriq_n_s64 (int64x2_t, int64x2_t, const int)
4195 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4196 @end itemize
4197
4198
4199 @itemize @bullet
4200 @item poly16x8_t vsriq_n_p16 (poly16x8_t, poly16x8_t, const int)
4201 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4202 @end itemize
4203
4204
4205 @itemize @bullet
4206 @item poly8x16_t vsriq_n_p8 (poly8x16_t, poly8x16_t, const int)
4207 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4208 @end itemize
4209
4210
4211
4212
4213 @subsubsection Vector shift left and insert
4214
4215 @itemize @bullet
4216 @item poly64x1_t vsli_n_p64 (poly64x1_t, poly64x1_t, const int)
4217 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4218 @end itemize
4219
4220
4221 @itemize @bullet
4222 @item uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int)
4223 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4224 @end itemize
4225
4226
4227 @itemize @bullet
4228 @item uint16x4_t vsli_n_u16 (uint16x4_t, uint16x4_t, const int)
4229 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4230 @end itemize
4231
4232
4233 @itemize @bullet
4234 @item uint8x8_t vsli_n_u8 (uint8x8_t, uint8x8_t, const int)
4235 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4236 @end itemize
4237
4238
4239 @itemize @bullet
4240 @item int32x2_t vsli_n_s32 (int32x2_t, int32x2_t, const int)
4241 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4242 @end itemize
4243
4244
4245 @itemize @bullet
4246 @item int16x4_t vsli_n_s16 (int16x4_t, int16x4_t, const int)
4247 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4248 @end itemize
4249
4250
4251 @itemize @bullet
4252 @item int8x8_t vsli_n_s8 (int8x8_t, int8x8_t, const int)
4253 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4254 @end itemize
4255
4256
4257 @itemize @bullet
4258 @item uint64x1_t vsli_n_u64 (uint64x1_t, uint64x1_t, const int)
4259 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4260 @end itemize
4261
4262
4263 @itemize @bullet
4264 @item int64x1_t vsli_n_s64 (int64x1_t, int64x1_t, const int)
4265 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4266 @end itemize
4267
4268
4269 @itemize @bullet
4270 @item poly16x4_t vsli_n_p16 (poly16x4_t, poly16x4_t, const int)
4271 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4272 @end itemize
4273
4274
4275 @itemize @bullet
4276 @item poly8x8_t vsli_n_p8 (poly8x8_t, poly8x8_t, const int)
4277 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4278 @end itemize
4279
4280
4281 @itemize @bullet
4282 @item poly64x2_t vsliq_n_p64 (poly64x2_t, poly64x2_t, const int)
4283 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4284 @end itemize
4285
4286
4287 @itemize @bullet
4288 @item uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int)
4289 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4290 @end itemize
4291
4292
4293 @itemize @bullet
4294 @item uint16x8_t vsliq_n_u16 (uint16x8_t, uint16x8_t, const int)
4295 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4296 @end itemize
4297
4298
4299 @itemize @bullet
4300 @item uint8x16_t vsliq_n_u8 (uint8x16_t, uint8x16_t, const int)
4301 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4302 @end itemize
4303
4304
4305 @itemize @bullet
4306 @item int32x4_t vsliq_n_s32 (int32x4_t, int32x4_t, const int)
4307 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4308 @end itemize
4309
4310
4311 @itemize @bullet
4312 @item int16x8_t vsliq_n_s16 (int16x8_t, int16x8_t, const int)
4313 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4314 @end itemize
4315
4316
4317 @itemize @bullet
4318 @item int8x16_t vsliq_n_s8 (int8x16_t, int8x16_t, const int)
4319 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4320 @end itemize
4321
4322
4323 @itemize @bullet
4324 @item uint64x2_t vsliq_n_u64 (uint64x2_t, uint64x2_t, const int)
4325 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4326 @end itemize
4327
4328
4329 @itemize @bullet
4330 @item int64x2_t vsliq_n_s64 (int64x2_t, int64x2_t, const int)
4331 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4332 @end itemize
4333
4334
4335 @itemize @bullet
4336 @item poly16x8_t vsliq_n_p16 (poly16x8_t, poly16x8_t, const int)
4337 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4338 @end itemize
4339
4340
4341 @itemize @bullet
4342 @item poly8x16_t vsliq_n_p8 (poly8x16_t, poly8x16_t, const int)
4343 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4344 @end itemize
4345
4346
4347
4348
4349 @subsubsection Absolute value
4350
4351 @itemize @bullet
4352 @item float32x2_t vabs_f32 (float32x2_t)
4353 @*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{d0}, @var{d0}}
4354 @end itemize
4355
4356
4357 @itemize @bullet
4358 @item int32x2_t vabs_s32 (int32x2_t)
4359 @*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{d0}, @var{d0}}
4360 @end itemize
4361
4362
4363 @itemize @bullet
4364 @item int16x4_t vabs_s16 (int16x4_t)
4365 @*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{d0}, @var{d0}}
4366 @end itemize
4367
4368
4369 @itemize @bullet
4370 @item int8x8_t vabs_s8 (int8x8_t)
4371 @*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{d0}, @var{d0}}
4372 @end itemize
4373
4374
4375 @itemize @bullet
4376 @item float32x4_t vabsq_f32 (float32x4_t)
4377 @*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{q0}, @var{q0}}
4378 @end itemize
4379
4380
4381 @itemize @bullet
4382 @item int32x4_t vabsq_s32 (int32x4_t)
4383 @*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{q0}, @var{q0}}
4384 @end itemize
4385
4386
4387 @itemize @bullet
4388 @item int16x8_t vabsq_s16 (int16x8_t)
4389 @*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{q0}, @var{q0}}
4390 @end itemize
4391
4392
4393 @itemize @bullet
4394 @item int8x16_t vabsq_s8 (int8x16_t)
4395 @*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{q0}, @var{q0}}
4396 @end itemize
4397
4398
4399 @itemize @bullet
4400 @item int32x2_t vqabs_s32 (int32x2_t)
4401 @*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{d0}, @var{d0}}
4402 @end itemize
4403
4404
4405 @itemize @bullet
4406 @item int16x4_t vqabs_s16 (int16x4_t)
4407 @*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{d0}, @var{d0}}
4408 @end itemize
4409
4410
4411 @itemize @bullet
4412 @item int8x8_t vqabs_s8 (int8x8_t)
4413 @*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{d0}, @var{d0}}
4414 @end itemize
4415
4416
4417 @itemize @bullet
4418 @item int32x4_t vqabsq_s32 (int32x4_t)
4419 @*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{q0}, @var{q0}}
4420 @end itemize
4421
4422
4423 @itemize @bullet
4424 @item int16x8_t vqabsq_s16 (int16x8_t)
4425 @*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{q0}, @var{q0}}
4426 @end itemize
4427
4428
4429 @itemize @bullet
4430 @item int8x16_t vqabsq_s8 (int8x16_t)
4431 @*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{q0}, @var{q0}}
4432 @end itemize
4433
4434
4435
4436
4437 @subsubsection Negation
4438
4439 @itemize @bullet
4440 @item float32x2_t vneg_f32 (float32x2_t)
4441 @*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{d0}, @var{d0}}
4442 @end itemize
4443
4444
4445 @itemize @bullet
4446 @item int32x2_t vneg_s32 (int32x2_t)
4447 @*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{d0}, @var{d0}}
4448 @end itemize
4449
4450
4451 @itemize @bullet
4452 @item int16x4_t vneg_s16 (int16x4_t)
4453 @*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{d0}, @var{d0}}
4454 @end itemize
4455
4456
4457 @itemize @bullet
4458 @item int8x8_t vneg_s8 (int8x8_t)
4459 @*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{d0}, @var{d0}}
4460 @end itemize
4461
4462
4463 @itemize @bullet
4464 @item float32x4_t vnegq_f32 (float32x4_t)
4465 @*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{q0}, @var{q0}}
4466 @end itemize
4467
4468
4469 @itemize @bullet
4470 @item int32x4_t vnegq_s32 (int32x4_t)
4471 @*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{q0}, @var{q0}}
4472 @end itemize
4473
4474
4475 @itemize @bullet
4476 @item int16x8_t vnegq_s16 (int16x8_t)
4477 @*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{q0}, @var{q0}}
4478 @end itemize
4479
4480
4481 @itemize @bullet
4482 @item int8x16_t vnegq_s8 (int8x16_t)
4483 @*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{q0}, @var{q0}}
4484 @end itemize
4485
4486
4487 @itemize @bullet
4488 @item int32x2_t vqneg_s32 (int32x2_t)
4489 @*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{d0}, @var{d0}}
4490 @end itemize
4491
4492
4493 @itemize @bullet
4494 @item int16x4_t vqneg_s16 (int16x4_t)
4495 @*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{d0}, @var{d0}}
4496 @end itemize
4497
4498
4499 @itemize @bullet
4500 @item int8x8_t vqneg_s8 (int8x8_t)
4501 @*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{d0}, @var{d0}}
4502 @end itemize
4503
4504
4505 @itemize @bullet
4506 @item int32x4_t vqnegq_s32 (int32x4_t)
4507 @*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{q0}, @var{q0}}
4508 @end itemize
4509
4510
4511 @itemize @bullet
4512 @item int16x8_t vqnegq_s16 (int16x8_t)
4513 @*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{q0}, @var{q0}}
4514 @end itemize
4515
4516
4517 @itemize @bullet
4518 @item int8x16_t vqnegq_s8 (int8x16_t)
4519 @*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{q0}, @var{q0}}
4520 @end itemize
4521
4522
4523
4524
4525 @subsubsection Bitwise not
4526
4527 @itemize @bullet
4528 @item uint32x2_t vmvn_u32 (uint32x2_t)
4529 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4530 @end itemize
4531
4532
4533 @itemize @bullet
4534 @item uint16x4_t vmvn_u16 (uint16x4_t)
4535 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4536 @end itemize
4537
4538
4539 @itemize @bullet
4540 @item uint8x8_t vmvn_u8 (uint8x8_t)
4541 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4542 @end itemize
4543
4544
4545 @itemize @bullet
4546 @item int32x2_t vmvn_s32 (int32x2_t)
4547 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4548 @end itemize
4549
4550
4551 @itemize @bullet
4552 @item int16x4_t vmvn_s16 (int16x4_t)
4553 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4554 @end itemize
4555
4556
4557 @itemize @bullet
4558 @item int8x8_t vmvn_s8 (int8x8_t)
4559 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4560 @end itemize
4561
4562
4563 @itemize @bullet
4564 @item poly8x8_t vmvn_p8 (poly8x8_t)
4565 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4566 @end itemize
4567
4568
4569 @itemize @bullet
4570 @item uint32x4_t vmvnq_u32 (uint32x4_t)
4571 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4572 @end itemize
4573
4574
4575 @itemize @bullet
4576 @item uint16x8_t vmvnq_u16 (uint16x8_t)
4577 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4578 @end itemize
4579
4580
4581 @itemize @bullet
4582 @item uint8x16_t vmvnq_u8 (uint8x16_t)
4583 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4584 @end itemize
4585
4586
4587 @itemize @bullet
4588 @item int32x4_t vmvnq_s32 (int32x4_t)
4589 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4590 @end itemize
4591
4592
4593 @itemize @bullet
4594 @item int16x8_t vmvnq_s16 (int16x8_t)
4595 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4596 @end itemize
4597
4598
4599 @itemize @bullet
4600 @item int8x16_t vmvnq_s8 (int8x16_t)
4601 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4602 @end itemize
4603
4604
4605 @itemize @bullet
4606 @item poly8x16_t vmvnq_p8 (poly8x16_t)
4607 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4608 @end itemize
4609
4610
4611
4612
4613 @subsubsection Count leading sign bits
4614
4615 @itemize @bullet
4616 @item int32x2_t vcls_s32 (int32x2_t)
4617 @*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{d0}, @var{d0}}
4618 @end itemize
4619
4620
4621 @itemize @bullet
4622 @item int16x4_t vcls_s16 (int16x4_t)
4623 @*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{d0}, @var{d0}}
4624 @end itemize
4625
4626
4627 @itemize @bullet
4628 @item int8x8_t vcls_s8 (int8x8_t)
4629 @*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{d0}, @var{d0}}
4630 @end itemize
4631
4632
4633 @itemize @bullet
4634 @item int32x4_t vclsq_s32 (int32x4_t)
4635 @*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{q0}, @var{q0}}
4636 @end itemize
4637
4638
4639 @itemize @bullet
4640 @item int16x8_t vclsq_s16 (int16x8_t)
4641 @*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{q0}, @var{q0}}
4642 @end itemize
4643
4644
4645 @itemize @bullet
4646 @item int8x16_t vclsq_s8 (int8x16_t)
4647 @*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{q0}, @var{q0}}
4648 @end itemize
4649
4650
4651
4652
4653 @subsubsection Count leading zeros
4654
4655 @itemize @bullet
4656 @item uint32x2_t vclz_u32 (uint32x2_t)
4657 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4658 @end itemize
4659
4660
4661 @itemize @bullet
4662 @item uint16x4_t vclz_u16 (uint16x4_t)
4663 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4664 @end itemize
4665
4666
4667 @itemize @bullet
4668 @item uint8x8_t vclz_u8 (uint8x8_t)
4669 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4670 @end itemize
4671
4672
4673 @itemize @bullet
4674 @item int32x2_t vclz_s32 (int32x2_t)
4675 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4676 @end itemize
4677
4678
4679 @itemize @bullet
4680 @item int16x4_t vclz_s16 (int16x4_t)
4681 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4682 @end itemize
4683
4684
4685 @itemize @bullet
4686 @item int8x8_t vclz_s8 (int8x8_t)
4687 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4688 @end itemize
4689
4690
4691 @itemize @bullet
4692 @item uint32x4_t vclzq_u32 (uint32x4_t)
4693 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4694 @end itemize
4695
4696
4697 @itemize @bullet
4698 @item uint16x8_t vclzq_u16 (uint16x8_t)
4699 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4700 @end itemize
4701
4702
4703 @itemize @bullet
4704 @item uint8x16_t vclzq_u8 (uint8x16_t)
4705 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4706 @end itemize
4707
4708
4709 @itemize @bullet
4710 @item int32x4_t vclzq_s32 (int32x4_t)
4711 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4712 @end itemize
4713
4714
4715 @itemize @bullet
4716 @item int16x8_t vclzq_s16 (int16x8_t)
4717 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4718 @end itemize
4719
4720
4721 @itemize @bullet
4722 @item int8x16_t vclzq_s8 (int8x16_t)
4723 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4724 @end itemize
4725
4726
4727
4728
4729 @subsubsection Count number of set bits
4730
4731 @itemize @bullet
4732 @item uint8x8_t vcnt_u8 (uint8x8_t)
4733 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4734 @end itemize
4735
4736
4737 @itemize @bullet
4738 @item int8x8_t vcnt_s8 (int8x8_t)
4739 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4740 @end itemize
4741
4742
4743 @itemize @bullet
4744 @item poly8x8_t vcnt_p8 (poly8x8_t)
4745 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4746 @end itemize
4747
4748
4749 @itemize @bullet
4750 @item uint8x16_t vcntq_u8 (uint8x16_t)
4751 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4752 @end itemize
4753
4754
4755 @itemize @bullet
4756 @item int8x16_t vcntq_s8 (int8x16_t)
4757 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4758 @end itemize
4759
4760
4761 @itemize @bullet
4762 @item poly8x16_t vcntq_p8 (poly8x16_t)
4763 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4764 @end itemize
4765
4766
4767
4768
4769 @subsubsection Reciprocal estimate
4770
4771 @itemize @bullet
4772 @item float32x2_t vrecpe_f32 (float32x2_t)
4773 @*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{d0}, @var{d0}}
4774 @end itemize
4775
4776
4777 @itemize @bullet
4778 @item uint32x2_t vrecpe_u32 (uint32x2_t)
4779 @*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{d0}, @var{d0}}
4780 @end itemize
4781
4782
4783 @itemize @bullet
4784 @item float32x4_t vrecpeq_f32 (float32x4_t)
4785 @*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{q0}, @var{q0}}
4786 @end itemize
4787
4788
4789 @itemize @bullet
4790 @item uint32x4_t vrecpeq_u32 (uint32x4_t)
4791 @*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{q0}, @var{q0}}
4792 @end itemize
4793
4794
4795
4796
4797 @subsubsection Reciprocal square-root estimate
4798
4799 @itemize @bullet
4800 @item float32x2_t vrsqrte_f32 (float32x2_t)
4801 @*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{d0}, @var{d0}}
4802 @end itemize
4803
4804
4805 @itemize @bullet
4806 @item uint32x2_t vrsqrte_u32 (uint32x2_t)
4807 @*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{d0}, @var{d0}}
4808 @end itemize
4809
4810
4811 @itemize @bullet
4812 @item float32x4_t vrsqrteq_f32 (float32x4_t)
4813 @*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{q0}, @var{q0}}
4814 @end itemize
4815
4816
4817 @itemize @bullet
4818 @item uint32x4_t vrsqrteq_u32 (uint32x4_t)
4819 @*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{q0}, @var{q0}}
4820 @end itemize
4821
4822
4823
4824
4825 @subsubsection Get lanes from a vector
4826
4827 @itemize @bullet
4828 @item uint32_t vget_lane_u32 (uint32x2_t, const int)
4829 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4830 @end itemize
4831
4832
4833 @itemize @bullet
4834 @item uint16_t vget_lane_u16 (uint16x4_t, const int)
4835 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4836 @end itemize
4837
4838
4839 @itemize @bullet
4840 @item uint8_t vget_lane_u8 (uint8x8_t, const int)
4841 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4842 @end itemize
4843
4844
4845 @itemize @bullet
4846 @item int32_t vget_lane_s32 (int32x2_t, const int)
4847 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4848 @end itemize
4849
4850
4851 @itemize @bullet
4852 @item int16_t vget_lane_s16 (int16x4_t, const int)
4853 @*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4854 @end itemize
4855
4856
4857 @itemize @bullet
4858 @item int8_t vget_lane_s8 (int8x8_t, const int)
4859 @*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4860 @end itemize
4861
4862
4863 @itemize @bullet
4864 @item float32_t vget_lane_f32 (float32x2_t, const int)
4865 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4866 @end itemize
4867
4868
4869 @itemize @bullet
4870 @item poly16_t vget_lane_p16 (poly16x4_t, const int)
4871 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4872 @end itemize
4873
4874
4875 @itemize @bullet
4876 @item poly8_t vget_lane_p8 (poly8x8_t, const int)
4877 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4878 @end itemize
4879
4880
4881 @itemize @bullet
4882 @item uint64_t vget_lane_u64 (uint64x1_t, const int)
4883 @end itemize
4884
4885
4886 @itemize @bullet
4887 @item int64_t vget_lane_s64 (int64x1_t, const int)
4888 @end itemize
4889
4890
4891 @itemize @bullet
4892 @item uint32_t vgetq_lane_u32 (uint32x4_t, const int)
4893 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4894 @end itemize
4895
4896
4897 @itemize @bullet
4898 @item uint16_t vgetq_lane_u16 (uint16x8_t, const int)
4899 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4900 @end itemize
4901
4902
4903 @itemize @bullet
4904 @item uint8_t vgetq_lane_u8 (uint8x16_t, const int)
4905 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4906 @end itemize
4907
4908
4909 @itemize @bullet
4910 @item int32_t vgetq_lane_s32 (int32x4_t, const int)
4911 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4912 @end itemize
4913
4914
4915 @itemize @bullet
4916 @item int16_t vgetq_lane_s16 (int16x8_t, const int)
4917 @*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4918 @end itemize
4919
4920
4921 @itemize @bullet
4922 @item int8_t vgetq_lane_s8 (int8x16_t, const int)
4923 @*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4924 @end itemize
4925
4926
4927 @itemize @bullet
4928 @item float32_t vgetq_lane_f32 (float32x4_t, const int)
4929 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4930 @end itemize
4931
4932
4933 @itemize @bullet
4934 @item poly16_t vgetq_lane_p16 (poly16x8_t, const int)
4935 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4936 @end itemize
4937
4938
4939 @itemize @bullet
4940 @item poly8_t vgetq_lane_p8 (poly8x16_t, const int)
4941 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4942 @end itemize
4943
4944
4945 @itemize @bullet
4946 @item uint64_t vgetq_lane_u64 (uint64x2_t, const int)
4947 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}}
4948 @end itemize
4949
4950
4951 @itemize @bullet
4952 @item int64_t vgetq_lane_s64 (int64x2_t, const int)
4953 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}}
4954 @end itemize
4955
4956
4957
4958
4959 @subsubsection Set lanes in a vector
4960
4961 @itemize @bullet
4962 @item uint32x2_t vset_lane_u32 (uint32_t, uint32x2_t, const int)
4963 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4964 @end itemize
4965
4966
4967 @itemize @bullet
4968 @item uint16x4_t vset_lane_u16 (uint16_t, uint16x4_t, const int)
4969 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4970 @end itemize
4971
4972
4973 @itemize @bullet
4974 @item uint8x8_t vset_lane_u8 (uint8_t, uint8x8_t, const int)
4975 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4976 @end itemize
4977
4978
4979 @itemize @bullet
4980 @item int32x2_t vset_lane_s32 (int32_t, int32x2_t, const int)
4981 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4982 @end itemize
4983
4984
4985 @itemize @bullet
4986 @item int16x4_t vset_lane_s16 (int16_t, int16x4_t, const int)
4987 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4988 @end itemize
4989
4990
4991 @itemize @bullet
4992 @item int8x8_t vset_lane_s8 (int8_t, int8x8_t, const int)
4993 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4994 @end itemize
4995
4996
4997 @itemize @bullet
4998 @item float32x2_t vset_lane_f32 (float32_t, float32x2_t, const int)
4999 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
5000 @end itemize
5001
5002
5003 @itemize @bullet
5004 @item poly16x4_t vset_lane_p16 (poly16_t, poly16x4_t, const int)
5005 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
5006 @end itemize
5007
5008
5009 @itemize @bullet
5010 @item poly8x8_t vset_lane_p8 (poly8_t, poly8x8_t, const int)
5011 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
5012 @end itemize
5013
5014
5015 @itemize @bullet
5016 @item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
5017 @end itemize
5018
5019
5020 @itemize @bullet
5021 @item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
5022 @end itemize
5023
5024
5025 @itemize @bullet
5026 @item uint32x4_t vsetq_lane_u32 (uint32_t, uint32x4_t, const int)
5027 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
5028 @end itemize
5029
5030
5031 @itemize @bullet
5032 @item uint16x8_t vsetq_lane_u16 (uint16_t, uint16x8_t, const int)
5033 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
5034 @end itemize
5035
5036
5037 @itemize @bullet
5038 @item uint8x16_t vsetq_lane_u8 (uint8_t, uint8x16_t, const int)
5039 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
5040 @end itemize
5041
5042
5043 @itemize @bullet
5044 @item int32x4_t vsetq_lane_s32 (int32_t, int32x4_t, const int)
5045 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
5046 @end itemize
5047
5048
5049 @itemize @bullet
5050 @item int16x8_t vsetq_lane_s16 (int16_t, int16x8_t, const int)
5051 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
5052 @end itemize
5053
5054
5055 @itemize @bullet
5056 @item int8x16_t vsetq_lane_s8 (int8_t, int8x16_t, const int)
5057 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
5058 @end itemize
5059
5060
5061 @itemize @bullet
5062 @item float32x4_t vsetq_lane_f32 (float32_t, float32x4_t, const int)
5063 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
5064 @end itemize
5065
5066
5067 @itemize @bullet
5068 @item poly16x8_t vsetq_lane_p16 (poly16_t, poly16x8_t, const int)
5069 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
5070 @end itemize
5071
5072
5073 @itemize @bullet
5074 @item poly8x16_t vsetq_lane_p8 (poly8_t, poly8x16_t, const int)
5075 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
5076 @end itemize
5077
5078
5079 @itemize @bullet
5080 @item uint64x2_t vsetq_lane_u64 (uint64_t, uint64x2_t, const int)
5081 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5082 @end itemize
5083
5084
5085 @itemize @bullet
5086 @item int64x2_t vsetq_lane_s64 (int64_t, int64x2_t, const int)
5087 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5088 @end itemize
5089
5090
5091
5092
5093 @subsubsection Create vector from literal bit pattern
5094
5095 @itemize @bullet
5096 @item poly64x1_t vcreate_p64 (uint64_t)
5097 @end itemize
5098
5099
5100 @itemize @bullet
5101 @item uint32x2_t vcreate_u32 (uint64_t)
5102 @end itemize
5103
5104
5105 @itemize @bullet
5106 @item uint16x4_t vcreate_u16 (uint64_t)
5107 @end itemize
5108
5109
5110 @itemize @bullet
5111 @item uint8x8_t vcreate_u8 (uint64_t)
5112 @end itemize
5113
5114
5115 @itemize @bullet
5116 @item int32x2_t vcreate_s32 (uint64_t)
5117 @end itemize
5118
5119
5120 @itemize @bullet
5121 @item int16x4_t vcreate_s16 (uint64_t)
5122 @end itemize
5123
5124
5125 @itemize @bullet
5126 @item int8x8_t vcreate_s8 (uint64_t)
5127 @end itemize
5128
5129
5130 @itemize @bullet
5131 @item uint64x1_t vcreate_u64 (uint64_t)
5132 @end itemize
5133
5134
5135 @itemize @bullet
5136 @item int64x1_t vcreate_s64 (uint64_t)
5137 @end itemize
5138
5139
5140 @itemize @bullet
5141 @item float32x2_t vcreate_f32 (uint64_t)
5142 @end itemize
5143
5144
5145 @itemize @bullet
5146 @item poly16x4_t vcreate_p16 (uint64_t)
5147 @end itemize
5148
5149
5150 @itemize @bullet
5151 @item poly8x8_t vcreate_p8 (uint64_t)
5152 @end itemize
5153
5154
5155
5156
5157 @subsubsection Set all lanes to the same value
5158
5159 @itemize @bullet
5160 @item uint32x2_t vdup_n_u32 (uint32_t)
5161 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5162 @end itemize
5163
5164
5165 @itemize @bullet
5166 @item uint16x4_t vdup_n_u16 (uint16_t)
5167 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5168 @end itemize
5169
5170
5171 @itemize @bullet
5172 @item uint8x8_t vdup_n_u8 (uint8_t)
5173 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5174 @end itemize
5175
5176
5177 @itemize @bullet
5178 @item int32x2_t vdup_n_s32 (int32_t)
5179 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5180 @end itemize
5181
5182
5183 @itemize @bullet
5184 @item int16x4_t vdup_n_s16 (int16_t)
5185 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5186 @end itemize
5187
5188
5189 @itemize @bullet
5190 @item int8x8_t vdup_n_s8 (int8_t)
5191 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5192 @end itemize
5193
5194
5195 @itemize @bullet
5196 @item float32x2_t vdup_n_f32 (float32_t)
5197 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5198 @end itemize
5199
5200
5201 @itemize @bullet
5202 @item poly16x4_t vdup_n_p16 (poly16_t)
5203 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5204 @end itemize
5205
5206
5207 @itemize @bullet
5208 @item poly8x8_t vdup_n_p8 (poly8_t)
5209 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5210 @end itemize
5211
5212
5213 @itemize @bullet
5214 @item poly64x1_t vdup_n_p64 (poly64_t)
5215 @end itemize
5216
5217
5218 @itemize @bullet
5219 @item uint64x1_t vdup_n_u64 (uint64_t)
5220 @end itemize
5221
5222
5223 @itemize @bullet
5224 @item int64x1_t vdup_n_s64 (int64_t)
5225 @end itemize
5226
5227
5228 @itemize @bullet
5229 @item poly64x2_t vdupq_n_p64 (poly64_t)
5230 @end itemize
5231
5232
5233 @itemize @bullet
5234 @item uint32x4_t vdupq_n_u32 (uint32_t)
5235 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5236 @end itemize
5237
5238
5239 @itemize @bullet
5240 @item uint16x8_t vdupq_n_u16 (uint16_t)
5241 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5242 @end itemize
5243
5244
5245 @itemize @bullet
5246 @item uint8x16_t vdupq_n_u8 (uint8_t)
5247 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5248 @end itemize
5249
5250
5251 @itemize @bullet
5252 @item int32x4_t vdupq_n_s32 (int32_t)
5253 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5254 @end itemize
5255
5256
5257 @itemize @bullet
5258 @item int16x8_t vdupq_n_s16 (int16_t)
5259 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5260 @end itemize
5261
5262
5263 @itemize @bullet
5264 @item int8x16_t vdupq_n_s8 (int8_t)
5265 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5266 @end itemize
5267
5268
5269 @itemize @bullet
5270 @item float32x4_t vdupq_n_f32 (float32_t)
5271 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5272 @end itemize
5273
5274
5275 @itemize @bullet
5276 @item poly16x8_t vdupq_n_p16 (poly16_t)
5277 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5278 @end itemize
5279
5280
5281 @itemize @bullet
5282 @item poly8x16_t vdupq_n_p8 (poly8_t)
5283 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5284 @end itemize
5285
5286
5287 @itemize @bullet
5288 @item uint64x2_t vdupq_n_u64 (uint64_t)
5289 @end itemize
5290
5291
5292 @itemize @bullet
5293 @item int64x2_t vdupq_n_s64 (int64_t)
5294 @end itemize
5295
5296
5297 @itemize @bullet
5298 @item uint32x2_t vmov_n_u32 (uint32_t)
5299 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5300 @end itemize
5301
5302
5303 @itemize @bullet
5304 @item uint16x4_t vmov_n_u16 (uint16_t)
5305 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5306 @end itemize
5307
5308
5309 @itemize @bullet
5310 @item uint8x8_t vmov_n_u8 (uint8_t)
5311 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5312 @end itemize
5313
5314
5315 @itemize @bullet
5316 @item int32x2_t vmov_n_s32 (int32_t)
5317 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5318 @end itemize
5319
5320
5321 @itemize @bullet
5322 @item int16x4_t vmov_n_s16 (int16_t)
5323 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5324 @end itemize
5325
5326
5327 @itemize @bullet
5328 @item int8x8_t vmov_n_s8 (int8_t)
5329 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5330 @end itemize
5331
5332
5333 @itemize @bullet
5334 @item float32x2_t vmov_n_f32 (float32_t)
5335 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5336 @end itemize
5337
5338
5339 @itemize @bullet
5340 @item poly16x4_t vmov_n_p16 (poly16_t)
5341 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5342 @end itemize
5343
5344
5345 @itemize @bullet
5346 @item poly8x8_t vmov_n_p8 (poly8_t)
5347 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5348 @end itemize
5349
5350
5351 @itemize @bullet
5352 @item uint64x1_t vmov_n_u64 (uint64_t)
5353 @end itemize
5354
5355
5356 @itemize @bullet
5357 @item int64x1_t vmov_n_s64 (int64_t)
5358 @end itemize
5359
5360
5361 @itemize @bullet
5362 @item uint32x4_t vmovq_n_u32 (uint32_t)
5363 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5364 @end itemize
5365
5366
5367 @itemize @bullet
5368 @item uint16x8_t vmovq_n_u16 (uint16_t)
5369 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5370 @end itemize
5371
5372
5373 @itemize @bullet
5374 @item uint8x16_t vmovq_n_u8 (uint8_t)
5375 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5376 @end itemize
5377
5378
5379 @itemize @bullet
5380 @item int32x4_t vmovq_n_s32 (int32_t)
5381 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5382 @end itemize
5383
5384
5385 @itemize @bullet
5386 @item int16x8_t vmovq_n_s16 (int16_t)
5387 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5388 @end itemize
5389
5390
5391 @itemize @bullet
5392 @item int8x16_t vmovq_n_s8 (int8_t)
5393 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5394 @end itemize
5395
5396
5397 @itemize @bullet
5398 @item float32x4_t vmovq_n_f32 (float32_t)
5399 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5400 @end itemize
5401
5402
5403 @itemize @bullet
5404 @item poly16x8_t vmovq_n_p16 (poly16_t)
5405 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5406 @end itemize
5407
5408
5409 @itemize @bullet
5410 @item poly8x16_t vmovq_n_p8 (poly8_t)
5411 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5412 @end itemize
5413
5414
5415 @itemize @bullet
5416 @item uint64x2_t vmovq_n_u64 (uint64_t)
5417 @end itemize
5418
5419
5420 @itemize @bullet
5421 @item int64x2_t vmovq_n_s64 (int64_t)
5422 @end itemize
5423
5424
5425 @itemize @bullet
5426 @item uint32x2_t vdup_lane_u32 (uint32x2_t, const int)
5427 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5428 @end itemize
5429
5430
5431 @itemize @bullet
5432 @item uint16x4_t vdup_lane_u16 (uint16x4_t, const int)
5433 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5434 @end itemize
5435
5436
5437 @itemize @bullet
5438 @item uint8x8_t vdup_lane_u8 (uint8x8_t, const int)
5439 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5440 @end itemize
5441
5442
5443 @itemize @bullet
5444 @item int32x2_t vdup_lane_s32 (int32x2_t, const int)
5445 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5446 @end itemize
5447
5448
5449 @itemize @bullet
5450 @item int16x4_t vdup_lane_s16 (int16x4_t, const int)
5451 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5452 @end itemize
5453
5454
5455 @itemize @bullet
5456 @item int8x8_t vdup_lane_s8 (int8x8_t, const int)
5457 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5458 @end itemize
5459
5460
5461 @itemize @bullet
5462 @item float32x2_t vdup_lane_f32 (float32x2_t, const int)
5463 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5464 @end itemize
5465
5466
5467 @itemize @bullet
5468 @item poly16x4_t vdup_lane_p16 (poly16x4_t, const int)
5469 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5470 @end itemize
5471
5472
5473 @itemize @bullet
5474 @item poly8x8_t vdup_lane_p8 (poly8x8_t, const int)
5475 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5476 @end itemize
5477
5478
5479 @itemize @bullet
5480 @item poly64x1_t vdup_lane_p64 (poly64x1_t, const int)
5481 @end itemize
5482
5483
5484 @itemize @bullet
5485 @item uint64x1_t vdup_lane_u64 (uint64x1_t, const int)
5486 @end itemize
5487
5488
5489 @itemize @bullet
5490 @item int64x1_t vdup_lane_s64 (int64x1_t, const int)
5491 @end itemize
5492
5493
5494 @itemize @bullet
5495 @item uint32x4_t vdupq_lane_u32 (uint32x2_t, const int)
5496 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5497 @end itemize
5498
5499
5500 @itemize @bullet
5501 @item uint16x8_t vdupq_lane_u16 (uint16x4_t, const int)
5502 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5503 @end itemize
5504
5505
5506 @itemize @bullet
5507 @item uint8x16_t vdupq_lane_u8 (uint8x8_t, const int)
5508 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5509 @end itemize
5510
5511
5512 @itemize @bullet
5513 @item int32x4_t vdupq_lane_s32 (int32x2_t, const int)
5514 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5515 @end itemize
5516
5517
5518 @itemize @bullet
5519 @item int16x8_t vdupq_lane_s16 (int16x4_t, const int)
5520 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5521 @end itemize
5522
5523
5524 @itemize @bullet
5525 @item int8x16_t vdupq_lane_s8 (int8x8_t, const int)
5526 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5527 @end itemize
5528
5529
5530 @itemize @bullet
5531 @item float32x4_t vdupq_lane_f32 (float32x2_t, const int)
5532 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5533 @end itemize
5534
5535
5536 @itemize @bullet
5537 @item poly16x8_t vdupq_lane_p16 (poly16x4_t, const int)
5538 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5539 @end itemize
5540
5541
5542 @itemize @bullet
5543 @item poly8x16_t vdupq_lane_p8 (poly8x8_t, const int)
5544 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5545 @end itemize
5546
5547
5548 @itemize @bullet
5549 @item poly64x2_t vdupq_lane_p64 (poly64x1_t, const int)
5550 @end itemize
5551
5552
5553 @itemize @bullet
5554 @item uint64x2_t vdupq_lane_u64 (uint64x1_t, const int)
5555 @end itemize
5556
5557
5558 @itemize @bullet
5559 @item int64x2_t vdupq_lane_s64 (int64x1_t, const int)
5560 @end itemize
5561
5562
5563
5564
5565 @subsubsection Combining vectors
5566
5567 @itemize @bullet
5568 @item poly64x2_t vcombine_p64 (poly64x1_t, poly64x1_t)
5569 @end itemize
5570
5571
5572 @itemize @bullet
5573 @item uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t)
5574 @end itemize
5575
5576
5577 @itemize @bullet
5578 @item uint16x8_t vcombine_u16 (uint16x4_t, uint16x4_t)
5579 @end itemize
5580
5581
5582 @itemize @bullet
5583 @item uint8x16_t vcombine_u8 (uint8x8_t, uint8x8_t)
5584 @end itemize
5585
5586
5587 @itemize @bullet
5588 @item int32x4_t vcombine_s32 (int32x2_t, int32x2_t)
5589 @end itemize
5590
5591
5592 @itemize @bullet
5593 @item int16x8_t vcombine_s16 (int16x4_t, int16x4_t)
5594 @end itemize
5595
5596
5597 @itemize @bullet
5598 @item int8x16_t vcombine_s8 (int8x8_t, int8x8_t)
5599 @end itemize
5600
5601
5602 @itemize @bullet
5603 @item uint64x2_t vcombine_u64 (uint64x1_t, uint64x1_t)
5604 @end itemize
5605
5606
5607 @itemize @bullet
5608 @item int64x2_t vcombine_s64 (int64x1_t, int64x1_t)
5609 @end itemize
5610
5611
5612 @itemize @bullet
5613 @item float32x4_t vcombine_f32 (float32x2_t, float32x2_t)
5614 @end itemize
5615
5616
5617 @itemize @bullet
5618 @item poly16x8_t vcombine_p16 (poly16x4_t, poly16x4_t)
5619 @end itemize
5620
5621
5622 @itemize @bullet
5623 @item poly8x16_t vcombine_p8 (poly8x8_t, poly8x8_t)
5624 @end itemize
5625
5626
5627
5628
5629 @subsubsection Splitting vectors
5630
5631 @itemize @bullet
5632 @item poly64x1_t vget_high_p64 (poly64x2_t)
5633 @end itemize
5634
5635
5636 @itemize @bullet
5637 @item uint32x2_t vget_high_u32 (uint32x4_t)
5638 @end itemize
5639
5640
5641 @itemize @bullet
5642 @item uint16x4_t vget_high_u16 (uint16x8_t)
5643 @end itemize
5644
5645
5646 @itemize @bullet
5647 @item uint8x8_t vget_high_u8 (uint8x16_t)
5648 @end itemize
5649
5650
5651 @itemize @bullet
5652 @item int32x2_t vget_high_s32 (int32x4_t)
5653 @end itemize
5654
5655
5656 @itemize @bullet
5657 @item int16x4_t vget_high_s16 (int16x8_t)
5658 @end itemize
5659
5660
5661 @itemize @bullet
5662 @item int8x8_t vget_high_s8 (int8x16_t)
5663 @end itemize
5664
5665
5666 @itemize @bullet
5667 @item uint64x1_t vget_high_u64 (uint64x2_t)
5668 @end itemize
5669
5670
5671 @itemize @bullet
5672 @item int64x1_t vget_high_s64 (int64x2_t)
5673 @end itemize
5674
5675
5676 @itemize @bullet
5677 @item float32x2_t vget_high_f32 (float32x4_t)
5678 @end itemize
5679
5680
5681 @itemize @bullet
5682 @item poly16x4_t vget_high_p16 (poly16x8_t)
5683 @end itemize
5684
5685
5686 @itemize @bullet
5687 @item poly8x8_t vget_high_p8 (poly8x16_t)
5688 @end itemize
5689
5690
5691 @itemize @bullet
5692 @item uint32x2_t vget_low_u32 (uint32x4_t)
5693 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5694 @end itemize
5695
5696
5697 @itemize @bullet
5698 @item uint16x4_t vget_low_u16 (uint16x8_t)
5699 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5700 @end itemize
5701
5702
5703 @itemize @bullet
5704 @item uint8x8_t vget_low_u8 (uint8x16_t)
5705 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5706 @end itemize
5707
5708
5709 @itemize @bullet
5710 @item int32x2_t vget_low_s32 (int32x4_t)
5711 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5712 @end itemize
5713
5714
5715 @itemize @bullet
5716 @item int16x4_t vget_low_s16 (int16x8_t)
5717 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5718 @end itemize
5719
5720
5721 @itemize @bullet
5722 @item int8x8_t vget_low_s8 (int8x16_t)
5723 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5724 @end itemize
5725
5726
5727 @itemize @bullet
5728 @item float32x2_t vget_low_f32 (float32x4_t)
5729 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5730 @end itemize
5731
5732
5733 @itemize @bullet
5734 @item poly16x4_t vget_low_p16 (poly16x8_t)
5735 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5736 @end itemize
5737
5738
5739 @itemize @bullet
5740 @item poly8x8_t vget_low_p8 (poly8x16_t)
5741 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5742 @end itemize
5743
5744
5745 @itemize @bullet
5746 @item poly64x1_t vget_low_p64 (poly64x2_t)
5747 @end itemize
5748
5749
5750 @itemize @bullet
5751 @item uint64x1_t vget_low_u64 (uint64x2_t)
5752 @end itemize
5753
5754
5755 @itemize @bullet
5756 @item int64x1_t vget_low_s64 (int64x2_t)
5757 @end itemize
5758
5759
5760
5761
5762 @subsubsection Conversions
5763
5764 @itemize @bullet
5765 @item float32x2_t vcvt_f32_u32 (uint32x2_t)
5766 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}}
5767 @end itemize
5768
5769
5770 @itemize @bullet
5771 @item float32x2_t vcvt_f32_s32 (int32x2_t)
5772 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}}
5773 @end itemize
5774
5775
5776 @itemize @bullet
5777 @item uint32x2_t vcvt_u32_f32 (float32x2_t)
5778 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}}
5779 @end itemize
5780
5781
5782 @itemize @bullet
5783 @item int32x2_t vcvt_s32_f32 (float32x2_t)
5784 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}}
5785 @end itemize
5786
5787
5788 @itemize @bullet
5789 @item float32x4_t vcvtq_f32_u32 (uint32x4_t)
5790 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}}
5791 @end itemize
5792
5793
5794 @itemize @bullet
5795 @item float32x4_t vcvtq_f32_s32 (int32x4_t)
5796 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}}
5797 @end itemize
5798
5799
5800 @itemize @bullet
5801 @item uint32x4_t vcvtq_u32_f32 (float32x4_t)
5802 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}}
5803 @end itemize
5804
5805
5806 @itemize @bullet
5807 @item int32x4_t vcvtq_s32_f32 (float32x4_t)
5808 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}}
5809 @end itemize
5810
5811
5812 @itemize @bullet
5813 @item float16x4_t vcvt_f16_f32 (float32x4_t)
5814 @*@emph{Form of expected instruction(s):} @code{vcvt.f16.f32 @var{d0}, @var{q0}}
5815 @end itemize
5816
5817
5818 @itemize @bullet
5819 @item float32x4_t vcvt_f32_f16 (float16x4_t)
5820 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.f16 @var{q0}, @var{d0}}
5821 @end itemize
5822
5823
5824 @itemize @bullet
5825 @item float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int)
5826 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}, #@var{0}}
5827 @end itemize
5828
5829
5830 @itemize @bullet
5831 @item float32x2_t vcvt_n_f32_s32 (int32x2_t, const int)
5832 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}, #@var{0}}
5833 @end itemize
5834
5835
5836 @itemize @bullet
5837 @item uint32x2_t vcvt_n_u32_f32 (float32x2_t, const int)
5838 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}, #@var{0}}
5839 @end itemize
5840
5841
5842 @itemize @bullet
5843 @item int32x2_t vcvt_n_s32_f32 (float32x2_t, const int)
5844 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}, #@var{0}}
5845 @end itemize
5846
5847
5848 @itemize @bullet
5849 @item float32x4_t vcvtq_n_f32_u32 (uint32x4_t, const int)
5850 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}, #@var{0}}
5851 @end itemize
5852
5853
5854 @itemize @bullet
5855 @item float32x4_t vcvtq_n_f32_s32 (int32x4_t, const int)
5856 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}, #@var{0}}
5857 @end itemize
5858
5859
5860 @itemize @bullet
5861 @item uint32x4_t vcvtq_n_u32_f32 (float32x4_t, const int)
5862 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}, #@var{0}}
5863 @end itemize
5864
5865
5866 @itemize @bullet
5867 @item int32x4_t vcvtq_n_s32_f32 (float32x4_t, const int)
5868 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}, #@var{0}}
5869 @end itemize
5870
5871
5872
5873
5874 @subsubsection Move, single_opcode narrowing
5875
5876 @itemize @bullet
5877 @item uint32x2_t vmovn_u64 (uint64x2_t)
5878 @*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5879 @end itemize
5880
5881
5882 @itemize @bullet
5883 @item uint16x4_t vmovn_u32 (uint32x4_t)
5884 @*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5885 @end itemize
5886
5887
5888 @itemize @bullet
5889 @item uint8x8_t vmovn_u16 (uint16x8_t)
5890 @*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5891 @end itemize
5892
5893
5894 @itemize @bullet
5895 @item int32x2_t vmovn_s64 (int64x2_t)
5896 @*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5897 @end itemize
5898
5899
5900 @itemize @bullet
5901 @item int16x4_t vmovn_s32 (int32x4_t)
5902 @*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5903 @end itemize
5904
5905
5906 @itemize @bullet
5907 @item int8x8_t vmovn_s16 (int16x8_t)
5908 @*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5909 @end itemize
5910
5911
5912 @itemize @bullet
5913 @item uint32x2_t vqmovn_u64 (uint64x2_t)
5914 @*@emph{Form of expected instruction(s):} @code{vqmovn.u64 @var{d0}, @var{q0}}
5915 @end itemize
5916
5917
5918 @itemize @bullet
5919 @item uint16x4_t vqmovn_u32 (uint32x4_t)
5920 @*@emph{Form of expected instruction(s):} @code{vqmovn.u32 @var{d0}, @var{q0}}
5921 @end itemize
5922
5923
5924 @itemize @bullet
5925 @item uint8x8_t vqmovn_u16 (uint16x8_t)
5926 @*@emph{Form of expected instruction(s):} @code{vqmovn.u16 @var{d0}, @var{q0}}
5927 @end itemize
5928
5929
5930 @itemize @bullet
5931 @item int32x2_t vqmovn_s64 (int64x2_t)
5932 @*@emph{Form of expected instruction(s):} @code{vqmovn.s64 @var{d0}, @var{q0}}
5933 @end itemize
5934
5935
5936 @itemize @bullet
5937 @item int16x4_t vqmovn_s32 (int32x4_t)
5938 @*@emph{Form of expected instruction(s):} @code{vqmovn.s32 @var{d0}, @var{q0}}
5939 @end itemize
5940
5941
5942 @itemize @bullet
5943 @item int8x8_t vqmovn_s16 (int16x8_t)
5944 @*@emph{Form of expected instruction(s):} @code{vqmovn.s16 @var{d0}, @var{q0}}
5945 @end itemize
5946
5947
5948 @itemize @bullet
5949 @item uint32x2_t vqmovun_s64 (int64x2_t)
5950 @*@emph{Form of expected instruction(s):} @code{vqmovun.s64 @var{d0}, @var{q0}}
5951 @end itemize
5952
5953
5954 @itemize @bullet
5955 @item uint16x4_t vqmovun_s32 (int32x4_t)
5956 @*@emph{Form of expected instruction(s):} @code{vqmovun.s32 @var{d0}, @var{q0}}
5957 @end itemize
5958
5959
5960 @itemize @bullet
5961 @item uint8x8_t vqmovun_s16 (int16x8_t)
5962 @*@emph{Form of expected instruction(s):} @code{vqmovun.s16 @var{d0}, @var{q0}}
5963 @end itemize
5964
5965
5966
5967
5968 @subsubsection Move, single_opcode long
5969
5970 @itemize @bullet
5971 @item uint64x2_t vmovl_u32 (uint32x2_t)
5972 @*@emph{Form of expected instruction(s):} @code{vmovl.u32 @var{q0}, @var{d0}}
5973 @end itemize
5974
5975
5976 @itemize @bullet
5977 @item uint32x4_t vmovl_u16 (uint16x4_t)
5978 @*@emph{Form of expected instruction(s):} @code{vmovl.u16 @var{q0}, @var{d0}}
5979 @end itemize
5980
5981
5982 @itemize @bullet
5983 @item uint16x8_t vmovl_u8 (uint8x8_t)
5984 @*@emph{Form of expected instruction(s):} @code{vmovl.u8 @var{q0}, @var{d0}}
5985 @end itemize
5986
5987
5988 @itemize @bullet
5989 @item int64x2_t vmovl_s32 (int32x2_t)
5990 @*@emph{Form of expected instruction(s):} @code{vmovl.s32 @var{q0}, @var{d0}}
5991 @end itemize
5992
5993
5994 @itemize @bullet
5995 @item int32x4_t vmovl_s16 (int16x4_t)
5996 @*@emph{Form of expected instruction(s):} @code{vmovl.s16 @var{q0}, @var{d0}}
5997 @end itemize
5998
5999
6000 @itemize @bullet
6001 @item int16x8_t vmovl_s8 (int8x8_t)
6002 @*@emph{Form of expected instruction(s):} @code{vmovl.s8 @var{q0}, @var{d0}}
6003 @end itemize
6004
6005
6006
6007
6008 @subsubsection Table lookup
6009
6010 @itemize @bullet
6011 @item poly8x8_t vtbl1_p8 (poly8x8_t, uint8x8_t)
6012 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6013 @end itemize
6014
6015
6016 @itemize @bullet
6017 @item int8x8_t vtbl1_s8 (int8x8_t, int8x8_t)
6018 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6019 @end itemize
6020
6021
6022 @itemize @bullet
6023 @item uint8x8_t vtbl1_u8 (uint8x8_t, uint8x8_t)
6024 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6025 @end itemize
6026
6027
6028 @itemize @bullet
6029 @item poly8x8_t vtbl2_p8 (poly8x8x2_t, uint8x8_t)
6030 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6031 @end itemize
6032
6033
6034 @itemize @bullet
6035 @item int8x8_t vtbl2_s8 (int8x8x2_t, int8x8_t)
6036 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6037 @end itemize
6038
6039
6040 @itemize @bullet
6041 @item uint8x8_t vtbl2_u8 (uint8x8x2_t, uint8x8_t)
6042 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6043 @end itemize
6044
6045
6046 @itemize @bullet
6047 @item poly8x8_t vtbl3_p8 (poly8x8x3_t, uint8x8_t)
6048 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6049 @end itemize
6050
6051
6052 @itemize @bullet
6053 @item int8x8_t vtbl3_s8 (int8x8x3_t, int8x8_t)
6054 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6055 @end itemize
6056
6057
6058 @itemize @bullet
6059 @item uint8x8_t vtbl3_u8 (uint8x8x3_t, uint8x8_t)
6060 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6061 @end itemize
6062
6063
6064 @itemize @bullet
6065 @item poly8x8_t vtbl4_p8 (poly8x8x4_t, uint8x8_t)
6066 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6067 @end itemize
6068
6069
6070 @itemize @bullet
6071 @item int8x8_t vtbl4_s8 (int8x8x4_t, int8x8_t)
6072 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6073 @end itemize
6074
6075
6076 @itemize @bullet
6077 @item uint8x8_t vtbl4_u8 (uint8x8x4_t, uint8x8_t)
6078 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6079 @end itemize
6080
6081
6082
6083
6084 @subsubsection Extended table lookup
6085
6086 @itemize @bullet
6087 @item poly8x8_t vtbx1_p8 (poly8x8_t, poly8x8_t, uint8x8_t)
6088 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6089 @end itemize
6090
6091
6092 @itemize @bullet
6093 @item int8x8_t vtbx1_s8 (int8x8_t, int8x8_t, int8x8_t)
6094 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6095 @end itemize
6096
6097
6098 @itemize @bullet
6099 @item uint8x8_t vtbx1_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
6100 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6101 @end itemize
6102
6103
6104 @itemize @bullet
6105 @item poly8x8_t vtbx2_p8 (poly8x8_t, poly8x8x2_t, uint8x8_t)
6106 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6107 @end itemize
6108
6109
6110 @itemize @bullet
6111 @item int8x8_t vtbx2_s8 (int8x8_t, int8x8x2_t, int8x8_t)
6112 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6113 @end itemize
6114
6115
6116 @itemize @bullet
6117 @item uint8x8_t vtbx2_u8 (uint8x8_t, uint8x8x2_t, uint8x8_t)
6118 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6119 @end itemize
6120
6121
6122 @itemize @bullet
6123 @item poly8x8_t vtbx3_p8 (poly8x8_t, poly8x8x3_t, uint8x8_t)
6124 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6125 @end itemize
6126
6127
6128 @itemize @bullet
6129 @item int8x8_t vtbx3_s8 (int8x8_t, int8x8x3_t, int8x8_t)
6130 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6131 @end itemize
6132
6133
6134 @itemize @bullet
6135 @item uint8x8_t vtbx3_u8 (uint8x8_t, uint8x8x3_t, uint8x8_t)
6136 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6137 @end itemize
6138
6139
6140 @itemize @bullet
6141 @item poly8x8_t vtbx4_p8 (poly8x8_t, poly8x8x4_t, uint8x8_t)
6142 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6143 @end itemize
6144
6145
6146 @itemize @bullet
6147 @item int8x8_t vtbx4_s8 (int8x8_t, int8x8x4_t, int8x8_t)
6148 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6149 @end itemize
6150
6151
6152 @itemize @bullet
6153 @item uint8x8_t vtbx4_u8 (uint8x8_t, uint8x8x4_t, uint8x8_t)
6154 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6155 @end itemize
6156
6157
6158
6159
6160 @subsubsection Multiply, lane
6161
6162 @itemize @bullet
6163 @item float32x2_t vmul_lane_f32 (float32x2_t, float32x2_t, const int)
6164 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6165 @end itemize
6166
6167
6168 @itemize @bullet
6169 @item uint32x2_t vmul_lane_u32 (uint32x2_t, uint32x2_t, const int)
6170 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6171 @end itemize
6172
6173
6174 @itemize @bullet
6175 @item uint16x4_t vmul_lane_u16 (uint16x4_t, uint16x4_t, const int)
6176 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6177 @end itemize
6178
6179
6180 @itemize @bullet
6181 @item int32x2_t vmul_lane_s32 (int32x2_t, int32x2_t, const int)
6182 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6183 @end itemize
6184
6185
6186 @itemize @bullet
6187 @item int16x4_t vmul_lane_s16 (int16x4_t, int16x4_t, const int)
6188 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6189 @end itemize
6190
6191
6192 @itemize @bullet
6193 @item float32x4_t vmulq_lane_f32 (float32x4_t, float32x2_t, const int)
6194 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6195 @end itemize
6196
6197
6198 @itemize @bullet
6199 @item uint32x4_t vmulq_lane_u32 (uint32x4_t, uint32x2_t, const int)
6200 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6201 @end itemize
6202
6203
6204 @itemize @bullet
6205 @item uint16x8_t vmulq_lane_u16 (uint16x8_t, uint16x4_t, const int)
6206 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6207 @end itemize
6208
6209
6210 @itemize @bullet
6211 @item int32x4_t vmulq_lane_s32 (int32x4_t, int32x2_t, const int)
6212 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6213 @end itemize
6214
6215
6216 @itemize @bullet
6217 @item int16x8_t vmulq_lane_s16 (int16x8_t, int16x4_t, const int)
6218 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6219 @end itemize
6220
6221
6222
6223
6224 @subsubsection Long multiply, lane
6225
6226 @itemize @bullet
6227 @item uint64x2_t vmull_lane_u32 (uint32x2_t, uint32x2_t, const int)
6228 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6229 @end itemize
6230
6231
6232 @itemize @bullet
6233 @item uint32x4_t vmull_lane_u16 (uint16x4_t, uint16x4_t, const int)
6234 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6235 @end itemize
6236
6237
6238 @itemize @bullet
6239 @item int64x2_t vmull_lane_s32 (int32x2_t, int32x2_t, const int)
6240 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6241 @end itemize
6242
6243
6244 @itemize @bullet
6245 @item int32x4_t vmull_lane_s16 (int16x4_t, int16x4_t, const int)
6246 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6247 @end itemize
6248
6249
6250
6251
6252 @subsubsection Saturating doubling long multiply, lane
6253
6254 @itemize @bullet
6255 @item int64x2_t vqdmull_lane_s32 (int32x2_t, int32x2_t, const int)
6256 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6257 @end itemize
6258
6259
6260 @itemize @bullet
6261 @item int32x4_t vqdmull_lane_s16 (int16x4_t, int16x4_t, const int)
6262 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6263 @end itemize
6264
6265
6266
6267
6268 @subsubsection Saturating doubling multiply high, lane
6269
6270 @itemize @bullet
6271 @item int32x4_t vqdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6272 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6273 @end itemize
6274
6275
6276 @itemize @bullet
6277 @item int16x8_t vqdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6278 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6279 @end itemize
6280
6281
6282 @itemize @bullet
6283 @item int32x2_t vqdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6284 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6285 @end itemize
6286
6287
6288 @itemize @bullet
6289 @item int16x4_t vqdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6290 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6291 @end itemize
6292
6293
6294 @itemize @bullet
6295 @item int32x4_t vqrdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6296 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6297 @end itemize
6298
6299
6300 @itemize @bullet
6301 @item int16x8_t vqrdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6302 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6303 @end itemize
6304
6305
6306 @itemize @bullet
6307 @item int32x2_t vqrdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6308 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6309 @end itemize
6310
6311
6312 @itemize @bullet
6313 @item int16x4_t vqrdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6314 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6315 @end itemize
6316
6317
6318
6319
6320 @subsubsection Multiply-accumulate, lane
6321
6322 @itemize @bullet
6323 @item float32x2_t vmla_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6324 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6325 @end itemize
6326
6327
6328 @itemize @bullet
6329 @item uint32x2_t vmla_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6330 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6331 @end itemize
6332
6333
6334 @itemize @bullet
6335 @item uint16x4_t vmla_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6336 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6337 @end itemize
6338
6339
6340 @itemize @bullet
6341 @item int32x2_t vmla_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6342 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6343 @end itemize
6344
6345
6346 @itemize @bullet
6347 @item int16x4_t vmla_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6348 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6349 @end itemize
6350
6351
6352 @itemize @bullet
6353 @item float32x4_t vmlaq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6354 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6355 @end itemize
6356
6357
6358 @itemize @bullet
6359 @item uint32x4_t vmlaq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6360 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6361 @end itemize
6362
6363
6364 @itemize @bullet
6365 @item uint16x8_t vmlaq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6366 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6367 @end itemize
6368
6369
6370 @itemize @bullet
6371 @item int32x4_t vmlaq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6372 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6373 @end itemize
6374
6375
6376 @itemize @bullet
6377 @item int16x8_t vmlaq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6378 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6379 @end itemize
6380
6381
6382 @itemize @bullet
6383 @item uint64x2_t vmlal_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6384 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6385 @end itemize
6386
6387
6388 @itemize @bullet
6389 @item uint32x4_t vmlal_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6390 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6391 @end itemize
6392
6393
6394 @itemize @bullet
6395 @item int64x2_t vmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6396 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6397 @end itemize
6398
6399
6400 @itemize @bullet
6401 @item int32x4_t vmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6402 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6403 @end itemize
6404
6405
6406 @itemize @bullet
6407 @item int64x2_t vqdmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6408 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6409 @end itemize
6410
6411
6412 @itemize @bullet
6413 @item int32x4_t vqdmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6414 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6415 @end itemize
6416
6417
6418
6419
6420 @subsubsection Multiply-subtract, lane
6421
6422 @itemize @bullet
6423 @item float32x2_t vmls_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6424 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6425 @end itemize
6426
6427
6428 @itemize @bullet
6429 @item uint32x2_t vmls_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6430 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6431 @end itemize
6432
6433
6434 @itemize @bullet
6435 @item uint16x4_t vmls_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6436 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6437 @end itemize
6438
6439
6440 @itemize @bullet
6441 @item int32x2_t vmls_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6442 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6443 @end itemize
6444
6445
6446 @itemize @bullet
6447 @item int16x4_t vmls_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6448 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6449 @end itemize
6450
6451
6452 @itemize @bullet
6453 @item float32x4_t vmlsq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6454 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6455 @end itemize
6456
6457
6458 @itemize @bullet
6459 @item uint32x4_t vmlsq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6460 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6461 @end itemize
6462
6463
6464 @itemize @bullet
6465 @item uint16x8_t vmlsq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6466 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6467 @end itemize
6468
6469
6470 @itemize @bullet
6471 @item int32x4_t vmlsq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6472 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6473 @end itemize
6474
6475
6476 @itemize @bullet
6477 @item int16x8_t vmlsq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6478 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6479 @end itemize
6480
6481
6482 @itemize @bullet
6483 @item uint64x2_t vmlsl_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6484 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6485 @end itemize
6486
6487
6488 @itemize @bullet
6489 @item uint32x4_t vmlsl_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6490 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6491 @end itemize
6492
6493
6494 @itemize @bullet
6495 @item int64x2_t vmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6496 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6497 @end itemize
6498
6499
6500 @itemize @bullet
6501 @item int32x4_t vmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6502 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6503 @end itemize
6504
6505
6506 @itemize @bullet
6507 @item int64x2_t vqdmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6508 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6509 @end itemize
6510
6511
6512 @itemize @bullet
6513 @item int32x4_t vqdmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6514 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6515 @end itemize
6516
6517
6518
6519
6520 @subsubsection Vector multiply by scalar
6521
6522 @itemize @bullet
6523 @item float32x2_t vmul_n_f32 (float32x2_t, float32_t)
6524 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6525 @end itemize
6526
6527
6528 @itemize @bullet
6529 @item uint32x2_t vmul_n_u32 (uint32x2_t, uint32_t)
6530 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6531 @end itemize
6532
6533
6534 @itemize @bullet
6535 @item uint16x4_t vmul_n_u16 (uint16x4_t, uint16_t)
6536 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6537 @end itemize
6538
6539
6540 @itemize @bullet
6541 @item int32x2_t vmul_n_s32 (int32x2_t, int32_t)
6542 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6543 @end itemize
6544
6545
6546 @itemize @bullet
6547 @item int16x4_t vmul_n_s16 (int16x4_t, int16_t)
6548 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6549 @end itemize
6550
6551
6552 @itemize @bullet
6553 @item float32x4_t vmulq_n_f32 (float32x4_t, float32_t)
6554 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6555 @end itemize
6556
6557
6558 @itemize @bullet
6559 @item uint32x4_t vmulq_n_u32 (uint32x4_t, uint32_t)
6560 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6561 @end itemize
6562
6563
6564 @itemize @bullet
6565 @item uint16x8_t vmulq_n_u16 (uint16x8_t, uint16_t)
6566 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6567 @end itemize
6568
6569
6570 @itemize @bullet
6571 @item int32x4_t vmulq_n_s32 (int32x4_t, int32_t)
6572 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6573 @end itemize
6574
6575
6576 @itemize @bullet
6577 @item int16x8_t vmulq_n_s16 (int16x8_t, int16_t)
6578 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6579 @end itemize
6580
6581
6582
6583
6584 @subsubsection Vector long multiply by scalar
6585
6586 @itemize @bullet
6587 @item uint64x2_t vmull_n_u32 (uint32x2_t, uint32_t)
6588 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6589 @end itemize
6590
6591
6592 @itemize @bullet
6593 @item uint32x4_t vmull_n_u16 (uint16x4_t, uint16_t)
6594 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6595 @end itemize
6596
6597
6598 @itemize @bullet
6599 @item int64x2_t vmull_n_s32 (int32x2_t, int32_t)
6600 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6601 @end itemize
6602
6603
6604 @itemize @bullet
6605 @item int32x4_t vmull_n_s16 (int16x4_t, int16_t)
6606 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6607 @end itemize
6608
6609
6610
6611
6612 @subsubsection Vector saturating doubling long multiply by scalar
6613
6614 @itemize @bullet
6615 @item int64x2_t vqdmull_n_s32 (int32x2_t, int32_t)
6616 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6617 @end itemize
6618
6619
6620 @itemize @bullet
6621 @item int32x4_t vqdmull_n_s16 (int16x4_t, int16_t)
6622 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6623 @end itemize
6624
6625
6626
6627
6628 @subsubsection Vector saturating doubling multiply high by scalar
6629
6630 @itemize @bullet
6631 @item int32x4_t vqdmulhq_n_s32 (int32x4_t, int32_t)
6632 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6633 @end itemize
6634
6635
6636 @itemize @bullet
6637 @item int16x8_t vqdmulhq_n_s16 (int16x8_t, int16_t)
6638 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6639 @end itemize
6640
6641
6642 @itemize @bullet
6643 @item int32x2_t vqdmulh_n_s32 (int32x2_t, int32_t)
6644 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6645 @end itemize
6646
6647
6648 @itemize @bullet
6649 @item int16x4_t vqdmulh_n_s16 (int16x4_t, int16_t)
6650 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6651 @end itemize
6652
6653
6654 @itemize @bullet
6655 @item int32x4_t vqrdmulhq_n_s32 (int32x4_t, int32_t)
6656 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6657 @end itemize
6658
6659
6660 @itemize @bullet
6661 @item int16x8_t vqrdmulhq_n_s16 (int16x8_t, int16_t)
6662 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6663 @end itemize
6664
6665
6666 @itemize @bullet
6667 @item int32x2_t vqrdmulh_n_s32 (int32x2_t, int32_t)
6668 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6669 @end itemize
6670
6671
6672 @itemize @bullet
6673 @item int16x4_t vqrdmulh_n_s16 (int16x4_t, int16_t)
6674 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6675 @end itemize
6676
6677
6678
6679
6680 @subsubsection Vector multiply-accumulate by scalar
6681
6682 @itemize @bullet
6683 @item float32x2_t vmla_n_f32 (float32x2_t, float32x2_t, float32_t)
6684 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6685 @end itemize
6686
6687
6688 @itemize @bullet
6689 @item uint32x2_t vmla_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6690 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6691 @end itemize
6692
6693
6694 @itemize @bullet
6695 @item uint16x4_t vmla_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6696 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6697 @end itemize
6698
6699
6700 @itemize @bullet
6701 @item int32x2_t vmla_n_s32 (int32x2_t, int32x2_t, int32_t)
6702 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6703 @end itemize
6704
6705
6706 @itemize @bullet
6707 @item int16x4_t vmla_n_s16 (int16x4_t, int16x4_t, int16_t)
6708 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6709 @end itemize
6710
6711
6712 @itemize @bullet
6713 @item float32x4_t vmlaq_n_f32 (float32x4_t, float32x4_t, float32_t)
6714 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6715 @end itemize
6716
6717
6718 @itemize @bullet
6719 @item uint32x4_t vmlaq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6720 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6721 @end itemize
6722
6723
6724 @itemize @bullet
6725 @item uint16x8_t vmlaq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6726 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6727 @end itemize
6728
6729
6730 @itemize @bullet
6731 @item int32x4_t vmlaq_n_s32 (int32x4_t, int32x4_t, int32_t)
6732 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6733 @end itemize
6734
6735
6736 @itemize @bullet
6737 @item int16x8_t vmlaq_n_s16 (int16x8_t, int16x8_t, int16_t)
6738 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6739 @end itemize
6740
6741
6742 @itemize @bullet
6743 @item uint64x2_t vmlal_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6744 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6745 @end itemize
6746
6747
6748 @itemize @bullet
6749 @item uint32x4_t vmlal_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6750 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6751 @end itemize
6752
6753
6754 @itemize @bullet
6755 @item int64x2_t vmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6756 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6757 @end itemize
6758
6759
6760 @itemize @bullet
6761 @item int32x4_t vmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6762 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6763 @end itemize
6764
6765
6766 @itemize @bullet
6767 @item int64x2_t vqdmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6768 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6769 @end itemize
6770
6771
6772 @itemize @bullet
6773 @item int32x4_t vqdmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6774 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6775 @end itemize
6776
6777
6778
6779
6780 @subsubsection Vector multiply-subtract by scalar
6781
6782 @itemize @bullet
6783 @item float32x2_t vmls_n_f32 (float32x2_t, float32x2_t, float32_t)
6784 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6785 @end itemize
6786
6787
6788 @itemize @bullet
6789 @item uint32x2_t vmls_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6790 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6791 @end itemize
6792
6793
6794 @itemize @bullet
6795 @item uint16x4_t vmls_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6796 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6797 @end itemize
6798
6799
6800 @itemize @bullet
6801 @item int32x2_t vmls_n_s32 (int32x2_t, int32x2_t, int32_t)
6802 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6803 @end itemize
6804
6805
6806 @itemize @bullet
6807 @item int16x4_t vmls_n_s16 (int16x4_t, int16x4_t, int16_t)
6808 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6809 @end itemize
6810
6811
6812 @itemize @bullet
6813 @item float32x4_t vmlsq_n_f32 (float32x4_t, float32x4_t, float32_t)
6814 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6815 @end itemize
6816
6817
6818 @itemize @bullet
6819 @item uint32x4_t vmlsq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6820 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6821 @end itemize
6822
6823
6824 @itemize @bullet
6825 @item uint16x8_t vmlsq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6826 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6827 @end itemize
6828
6829
6830 @itemize @bullet
6831 @item int32x4_t vmlsq_n_s32 (int32x4_t, int32x4_t, int32_t)
6832 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6833 @end itemize
6834
6835
6836 @itemize @bullet
6837 @item int16x8_t vmlsq_n_s16 (int16x8_t, int16x8_t, int16_t)
6838 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6839 @end itemize
6840
6841
6842 @itemize @bullet
6843 @item uint64x2_t vmlsl_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6844 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6845 @end itemize
6846
6847
6848 @itemize @bullet
6849 @item uint32x4_t vmlsl_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6850 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6851 @end itemize
6852
6853
6854 @itemize @bullet
6855 @item int64x2_t vmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6856 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6857 @end itemize
6858
6859
6860 @itemize @bullet
6861 @item int32x4_t vmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6862 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6863 @end itemize
6864
6865
6866 @itemize @bullet
6867 @item int64x2_t vqdmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6868 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6869 @end itemize
6870
6871
6872 @itemize @bullet
6873 @item int32x4_t vqdmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6874 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6875 @end itemize
6876
6877
6878
6879
6880 @subsubsection Vector extract
6881
6882 @itemize @bullet
6883 @item poly64x1_t vext_p64 (poly64x1_t, poly64x1_t, const int)
6884 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6885 @end itemize
6886
6887
6888 @itemize @bullet
6889 @item uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int)
6890 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6891 @end itemize
6892
6893
6894 @itemize @bullet
6895 @item uint16x4_t vext_u16 (uint16x4_t, uint16x4_t, const int)
6896 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6897 @end itemize
6898
6899
6900 @itemize @bullet
6901 @item uint8x8_t vext_u8 (uint8x8_t, uint8x8_t, const int)
6902 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6903 @end itemize
6904
6905
6906 @itemize @bullet
6907 @item int32x2_t vext_s32 (int32x2_t, int32x2_t, const int)
6908 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6909 @end itemize
6910
6911
6912 @itemize @bullet
6913 @item int16x4_t vext_s16 (int16x4_t, int16x4_t, const int)
6914 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6915 @end itemize
6916
6917
6918 @itemize @bullet
6919 @item int8x8_t vext_s8 (int8x8_t, int8x8_t, const int)
6920 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6921 @end itemize
6922
6923
6924 @itemize @bullet
6925 @item uint64x1_t vext_u64 (uint64x1_t, uint64x1_t, const int)
6926 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6927 @end itemize
6928
6929
6930 @itemize @bullet
6931 @item int64x1_t vext_s64 (int64x1_t, int64x1_t, const int)
6932 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6933 @end itemize
6934
6935
6936 @itemize @bullet
6937 @item float32x2_t vext_f32 (float32x2_t, float32x2_t, const int)
6938 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6939 @end itemize
6940
6941
6942 @itemize @bullet
6943 @item poly16x4_t vext_p16 (poly16x4_t, poly16x4_t, const int)
6944 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6945 @end itemize
6946
6947
6948 @itemize @bullet
6949 @item poly8x8_t vext_p8 (poly8x8_t, poly8x8_t, const int)
6950 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6951 @end itemize
6952
6953
6954 @itemize @bullet
6955 @item poly64x2_t vextq_p64 (poly64x2_t, poly64x2_t, const int)
6956 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6957 @end itemize
6958
6959
6960 @itemize @bullet
6961 @item uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int)
6962 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6963 @end itemize
6964
6965
6966 @itemize @bullet
6967 @item uint16x8_t vextq_u16 (uint16x8_t, uint16x8_t, const int)
6968 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6969 @end itemize
6970
6971
6972 @itemize @bullet
6973 @item uint8x16_t vextq_u8 (uint8x16_t, uint8x16_t, const int)
6974 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6975 @end itemize
6976
6977
6978 @itemize @bullet
6979 @item int32x4_t vextq_s32 (int32x4_t, int32x4_t, const int)
6980 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6981 @end itemize
6982
6983
6984 @itemize @bullet
6985 @item int16x8_t vextq_s16 (int16x8_t, int16x8_t, const int)
6986 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6987 @end itemize
6988
6989
6990 @itemize @bullet
6991 @item int8x16_t vextq_s8 (int8x16_t, int8x16_t, const int)
6992 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6993 @end itemize
6994
6995
6996 @itemize @bullet
6997 @item uint64x2_t vextq_u64 (uint64x2_t, uint64x2_t, const int)
6998 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6999 @end itemize
7000
7001
7002 @itemize @bullet
7003 @item int64x2_t vextq_s64 (int64x2_t, int64x2_t, const int)
7004 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
7005 @end itemize
7006
7007
7008 @itemize @bullet
7009 @item float32x4_t vextq_f32 (float32x4_t, float32x4_t, const int)
7010 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
7011 @end itemize
7012
7013
7014 @itemize @bullet
7015 @item poly16x8_t vextq_p16 (poly16x8_t, poly16x8_t, const int)
7016 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
7017 @end itemize
7018
7019
7020 @itemize @bullet
7021 @item poly8x16_t vextq_p8 (poly8x16_t, poly8x16_t, const int)
7022 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
7023 @end itemize
7024
7025
7026
7027
7028 @subsubsection Reverse elements
7029
7030 @itemize @bullet
7031 @item uint32x2_t vrev64_u32 (uint32x2_t)
7032 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
7033 @end itemize
7034
7035
7036 @itemize @bullet
7037 @item uint16x4_t vrev64_u16 (uint16x4_t)
7038 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
7039 @end itemize
7040
7041
7042 @itemize @bullet
7043 @item uint8x8_t vrev64_u8 (uint8x8_t)
7044 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
7045 @end itemize
7046
7047
7048 @itemize @bullet
7049 @item int32x2_t vrev64_s32 (int32x2_t)
7050 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
7051 @end itemize
7052
7053
7054 @itemize @bullet
7055 @item int16x4_t vrev64_s16 (int16x4_t)
7056 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
7057 @end itemize
7058
7059
7060 @itemize @bullet
7061 @item int8x8_t vrev64_s8 (int8x8_t)
7062 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
7063 @end itemize
7064
7065
7066 @itemize @bullet
7067 @item float32x2_t vrev64_f32 (float32x2_t)
7068 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
7069 @end itemize
7070
7071
7072 @itemize @bullet
7073 @item poly16x4_t vrev64_p16 (poly16x4_t)
7074 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
7075 @end itemize
7076
7077
7078 @itemize @bullet
7079 @item poly8x8_t vrev64_p8 (poly8x8_t)
7080 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
7081 @end itemize
7082
7083
7084 @itemize @bullet
7085 @item uint32x4_t vrev64q_u32 (uint32x4_t)
7086 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
7087 @end itemize
7088
7089
7090 @itemize @bullet
7091 @item uint16x8_t vrev64q_u16 (uint16x8_t)
7092 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
7093 @end itemize
7094
7095
7096 @itemize @bullet
7097 @item uint8x16_t vrev64q_u8 (uint8x16_t)
7098 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
7099 @end itemize
7100
7101
7102 @itemize @bullet
7103 @item int32x4_t vrev64q_s32 (int32x4_t)
7104 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
7105 @end itemize
7106
7107
7108 @itemize @bullet
7109 @item int16x8_t vrev64q_s16 (int16x8_t)
7110 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
7111 @end itemize
7112
7113
7114 @itemize @bullet
7115 @item int8x16_t vrev64q_s8 (int8x16_t)
7116 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
7117 @end itemize
7118
7119
7120 @itemize @bullet
7121 @item float32x4_t vrev64q_f32 (float32x4_t)
7122 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
7123 @end itemize
7124
7125
7126 @itemize @bullet
7127 @item poly16x8_t vrev64q_p16 (poly16x8_t)
7128 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
7129 @end itemize
7130
7131
7132 @itemize @bullet
7133 @item poly8x16_t vrev64q_p8 (poly8x16_t)
7134 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
7135 @end itemize
7136
7137
7138 @itemize @bullet
7139 @item uint16x4_t vrev32_u16 (uint16x4_t)
7140 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
7141 @end itemize
7142
7143
7144 @itemize @bullet
7145 @item int16x4_t vrev32_s16 (int16x4_t)
7146 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
7147 @end itemize
7148
7149
7150 @itemize @bullet
7151 @item uint8x8_t vrev32_u8 (uint8x8_t)
7152 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
7153 @end itemize
7154
7155
7156 @itemize @bullet
7157 @item int8x8_t vrev32_s8 (int8x8_t)
7158 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
7159 @end itemize
7160
7161
7162 @itemize @bullet
7163 @item poly16x4_t vrev32_p16 (poly16x4_t)
7164 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
7165 @end itemize
7166
7167
7168 @itemize @bullet
7169 @item poly8x8_t vrev32_p8 (poly8x8_t)
7170 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
7171 @end itemize
7172
7173
7174 @itemize @bullet
7175 @item uint16x8_t vrev32q_u16 (uint16x8_t)
7176 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7177 @end itemize
7178
7179
7180 @itemize @bullet
7181 @item int16x8_t vrev32q_s16 (int16x8_t)
7182 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7183 @end itemize
7184
7185
7186 @itemize @bullet
7187 @item uint8x16_t vrev32q_u8 (uint8x16_t)
7188 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7189 @end itemize
7190
7191
7192 @itemize @bullet
7193 @item int8x16_t vrev32q_s8 (int8x16_t)
7194 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7195 @end itemize
7196
7197
7198 @itemize @bullet
7199 @item poly16x8_t vrev32q_p16 (poly16x8_t)
7200 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7201 @end itemize
7202
7203
7204 @itemize @bullet
7205 @item poly8x16_t vrev32q_p8 (poly8x16_t)
7206 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7207 @end itemize
7208
7209
7210 @itemize @bullet
7211 @item uint8x8_t vrev16_u8 (uint8x8_t)
7212 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7213 @end itemize
7214
7215
7216 @itemize @bullet
7217 @item int8x8_t vrev16_s8 (int8x8_t)
7218 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7219 @end itemize
7220
7221
7222 @itemize @bullet
7223 @item poly8x8_t vrev16_p8 (poly8x8_t)
7224 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7225 @end itemize
7226
7227
7228 @itemize @bullet
7229 @item uint8x16_t vrev16q_u8 (uint8x16_t)
7230 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7231 @end itemize
7232
7233
7234 @itemize @bullet
7235 @item int8x16_t vrev16q_s8 (int8x16_t)
7236 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7237 @end itemize
7238
7239
7240 @itemize @bullet
7241 @item poly8x16_t vrev16q_p8 (poly8x16_t)
7242 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7243 @end itemize
7244
7245
7246
7247
7248 @subsubsection Bit selection
7249
7250 @itemize @bullet
7251 @item poly64x1_t vbsl_p64 (uint64x1_t, poly64x1_t, poly64x1_t)
7252 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7253 @end itemize
7254
7255
7256 @itemize @bullet
7257 @item uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
7258 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7259 @end itemize
7260
7261
7262 @itemize @bullet
7263 @item uint16x4_t vbsl_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
7264 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7265 @end itemize
7266
7267
7268 @itemize @bullet
7269 @item uint8x8_t vbsl_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
7270 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7271 @end itemize
7272
7273
7274 @itemize @bullet
7275 @item int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t)
7276 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7277 @end itemize
7278
7279
7280 @itemize @bullet
7281 @item int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t)
7282 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7283 @end itemize
7284
7285
7286 @itemize @bullet
7287 @item int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t)
7288 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7289 @end itemize
7290
7291
7292 @itemize @bullet
7293 @item uint64x1_t vbsl_u64 (uint64x1_t, uint64x1_t, uint64x1_t)
7294 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7295 @end itemize
7296
7297
7298 @itemize @bullet
7299 @item int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t)
7300 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7301 @end itemize
7302
7303
7304 @itemize @bullet
7305 @item float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t)
7306 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7307 @end itemize
7308
7309
7310 @itemize @bullet
7311 @item poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t)
7312 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7313 @end itemize
7314
7315
7316 @itemize @bullet
7317 @item poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t)
7318 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7319 @end itemize
7320
7321
7322 @itemize @bullet
7323 @item poly64x2_t vbslq_p64 (uint64x2_t, poly64x2_t, poly64x2_t)
7324 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7325 @end itemize
7326
7327
7328 @itemize @bullet
7329 @item uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
7330 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7331 @end itemize
7332
7333
7334 @itemize @bullet
7335 @item uint16x8_t vbslq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
7336 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7337 @end itemize
7338
7339
7340 @itemize @bullet
7341 @item uint8x16_t vbslq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
7342 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7343 @end itemize
7344
7345
7346 @itemize @bullet
7347 @item int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t)
7348 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7349 @end itemize
7350
7351
7352 @itemize @bullet
7353 @item int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t)
7354 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7355 @end itemize
7356
7357
7358 @itemize @bullet
7359 @item int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t)
7360 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7361 @end itemize
7362
7363
7364 @itemize @bullet
7365 @item uint64x2_t vbslq_u64 (uint64x2_t, uint64x2_t, uint64x2_t)
7366 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7367 @end itemize
7368
7369
7370 @itemize @bullet
7371 @item int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t)
7372 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7373 @end itemize
7374
7375
7376 @itemize @bullet
7377 @item float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t)
7378 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7379 @end itemize
7380
7381
7382 @itemize @bullet
7383 @item poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t)
7384 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7385 @end itemize
7386
7387
7388 @itemize @bullet
7389 @item poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t)
7390 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7391 @end itemize
7392
7393
7394
7395
7396 @subsubsection Transpose elements
7397
7398 @itemize @bullet
7399 @item uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t)
7400 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7401 @end itemize
7402
7403
7404 @itemize @bullet
7405 @item uint8x8x2_t vtrn_u8 (uint8x8_t, uint8x8_t)
7406 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7407 @end itemize
7408
7409
7410 @itemize @bullet
7411 @item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
7412 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7413 @end itemize
7414
7415
7416 @itemize @bullet
7417 @item int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t)
7418 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7419 @end itemize
7420
7421
7422 @itemize @bullet
7423 @item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
7424 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7425 @end itemize
7426
7427
7428 @itemize @bullet
7429 @item poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t)
7430 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7431 @end itemize
7432
7433
7434 @itemize @bullet
7435 @item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
7436 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7437 @end itemize
7438
7439
7440 @itemize @bullet
7441 @item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
7442 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7443 @end itemize
7444
7445
7446 @itemize @bullet
7447 @item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
7448 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7449 @end itemize
7450
7451
7452 @itemize @bullet
7453 @item uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t)
7454 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7455 @end itemize
7456
7457
7458 @itemize @bullet
7459 @item uint16x8x2_t vtrnq_u16 (uint16x8_t, uint16x8_t)
7460 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7461 @end itemize
7462
7463
7464 @itemize @bullet
7465 @item uint8x16x2_t vtrnq_u8 (uint8x16_t, uint8x16_t)
7466 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7467 @end itemize
7468
7469
7470 @itemize @bullet
7471 @item int32x4x2_t vtrnq_s32 (int32x4_t, int32x4_t)
7472 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7473 @end itemize
7474
7475
7476 @itemize @bullet
7477 @item int16x8x2_t vtrnq_s16 (int16x8_t, int16x8_t)
7478 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7479 @end itemize
7480
7481
7482 @itemize @bullet
7483 @item int8x16x2_t vtrnq_s8 (int8x16_t, int8x16_t)
7484 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7485 @end itemize
7486
7487
7488 @itemize @bullet
7489 @item float32x4x2_t vtrnq_f32 (float32x4_t, float32x4_t)
7490 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7491 @end itemize
7492
7493
7494 @itemize @bullet
7495 @item poly16x8x2_t vtrnq_p16 (poly16x8_t, poly16x8_t)
7496 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7497 @end itemize
7498
7499
7500 @itemize @bullet
7501 @item poly8x16x2_t vtrnq_p8 (poly8x16_t, poly8x16_t)
7502 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7503 @end itemize
7504
7505
7506
7507
7508 @subsubsection Zip elements
7509
7510 @itemize @bullet
7511 @item uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t)
7512 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7513 @end itemize
7514
7515
7516 @itemize @bullet
7517 @item uint8x8x2_t vzip_u8 (uint8x8_t, uint8x8_t)
7518 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7519 @end itemize
7520
7521
7522 @itemize @bullet
7523 @item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
7524 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7525 @end itemize
7526
7527
7528 @itemize @bullet
7529 @item int8x8x2_t vzip_s8 (int8x8_t, int8x8_t)
7530 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7531 @end itemize
7532
7533
7534 @itemize @bullet
7535 @item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
7536 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7537 @end itemize
7538
7539
7540 @itemize @bullet
7541 @item poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t)
7542 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7543 @end itemize
7544
7545
7546 @itemize @bullet
7547 @item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
7548 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7549 @end itemize
7550
7551
7552 @itemize @bullet
7553 @item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
7554 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7555 @end itemize
7556
7557
7558 @itemize @bullet
7559 @item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
7560 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7561 @end itemize
7562
7563
7564 @itemize @bullet
7565 @item uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t)
7566 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7567 @end itemize
7568
7569
7570 @itemize @bullet
7571 @item uint16x8x2_t vzipq_u16 (uint16x8_t, uint16x8_t)
7572 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7573 @end itemize
7574
7575
7576 @itemize @bullet
7577 @item uint8x16x2_t vzipq_u8 (uint8x16_t, uint8x16_t)
7578 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7579 @end itemize
7580
7581
7582 @itemize @bullet
7583 @item int32x4x2_t vzipq_s32 (int32x4_t, int32x4_t)
7584 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7585 @end itemize
7586
7587
7588 @itemize @bullet
7589 @item int16x8x2_t vzipq_s16 (int16x8_t, int16x8_t)
7590 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7591 @end itemize
7592
7593
7594 @itemize @bullet
7595 @item int8x16x2_t vzipq_s8 (int8x16_t, int8x16_t)
7596 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7597 @end itemize
7598
7599
7600 @itemize @bullet
7601 @item float32x4x2_t vzipq_f32 (float32x4_t, float32x4_t)
7602 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7603 @end itemize
7604
7605
7606 @itemize @bullet
7607 @item poly16x8x2_t vzipq_p16 (poly16x8_t, poly16x8_t)
7608 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7609 @end itemize
7610
7611
7612 @itemize @bullet
7613 @item poly8x16x2_t vzipq_p8 (poly8x16_t, poly8x16_t)
7614 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7615 @end itemize
7616
7617
7618
7619
7620 @subsubsection Unzip elements
7621
7622 @itemize @bullet
7623 @item uint32x2x2_t vuzp_u32 (uint32x2_t, uint32x2_t)
7624 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7625 @end itemize
7626
7627
7628 @itemize @bullet
7629 @item uint16x4x2_t vuzp_u16 (uint16x4_t, uint16x4_t)
7630 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7631 @end itemize
7632
7633
7634 @itemize @bullet
7635 @item uint8x8x2_t vuzp_u8 (uint8x8_t, uint8x8_t)
7636 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7637 @end itemize
7638
7639
7640 @itemize @bullet
7641 @item int32x2x2_t vuzp_s32 (int32x2_t, int32x2_t)
7642 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7643 @end itemize
7644
7645
7646 @itemize @bullet
7647 @item int16x4x2_t vuzp_s16 (int16x4_t, int16x4_t)
7648 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7649 @end itemize
7650
7651
7652 @itemize @bullet
7653 @item int8x8x2_t vuzp_s8 (int8x8_t, int8x8_t)
7654 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7655 @end itemize
7656
7657
7658 @itemize @bullet
7659 @item float32x2x2_t vuzp_f32 (float32x2_t, float32x2_t)
7660 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7661 @end itemize
7662
7663
7664 @itemize @bullet
7665 @item poly16x4x2_t vuzp_p16 (poly16x4_t, poly16x4_t)
7666 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7667 @end itemize
7668
7669
7670 @itemize @bullet
7671 @item poly8x8x2_t vuzp_p8 (poly8x8_t, poly8x8_t)
7672 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7673 @end itemize
7674
7675
7676 @itemize @bullet
7677 @item uint32x4x2_t vuzpq_u32 (uint32x4_t, uint32x4_t)
7678 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7679 @end itemize
7680
7681
7682 @itemize @bullet
7683 @item uint16x8x2_t vuzpq_u16 (uint16x8_t, uint16x8_t)
7684 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7685 @end itemize
7686
7687
7688 @itemize @bullet
7689 @item uint8x16x2_t vuzpq_u8 (uint8x16_t, uint8x16_t)
7690 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7691 @end itemize
7692
7693
7694 @itemize @bullet
7695 @item int32x4x2_t vuzpq_s32 (int32x4_t, int32x4_t)
7696 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7697 @end itemize
7698
7699
7700 @itemize @bullet
7701 @item int16x8x2_t vuzpq_s16 (int16x8_t, int16x8_t)
7702 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7703 @end itemize
7704
7705
7706 @itemize @bullet
7707 @item int8x16x2_t vuzpq_s8 (int8x16_t, int8x16_t)
7708 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7709 @end itemize
7710
7711
7712 @itemize @bullet
7713 @item float32x4x2_t vuzpq_f32 (float32x4_t, float32x4_t)
7714 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7715 @end itemize
7716
7717
7718 @itemize @bullet
7719 @item poly16x8x2_t vuzpq_p16 (poly16x8_t, poly16x8_t)
7720 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7721 @end itemize
7722
7723
7724 @itemize @bullet
7725 @item poly8x16x2_t vuzpq_p8 (poly8x16_t, poly8x16_t)
7726 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7727 @end itemize
7728
7729
7730
7731
7732 @subsubsection Element/structure loads, VLD1 variants
7733
7734 @itemize @bullet
7735 @item poly64x1_t vld1_p64 (const poly64_t *)
7736 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7737 @end itemize
7738
7739
7740 @itemize @bullet
7741 @item uint32x2_t vld1_u32 (const uint32_t *)
7742 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7743 @end itemize
7744
7745
7746 @itemize @bullet
7747 @item uint16x4_t vld1_u16 (const uint16_t *)
7748 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7749 @end itemize
7750
7751
7752 @itemize @bullet
7753 @item uint8x8_t vld1_u8 (const uint8_t *)
7754 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7755 @end itemize
7756
7757
7758 @itemize @bullet
7759 @item int32x2_t vld1_s32 (const int32_t *)
7760 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7761 @end itemize
7762
7763
7764 @itemize @bullet
7765 @item int16x4_t vld1_s16 (const int16_t *)
7766 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7767 @end itemize
7768
7769
7770 @itemize @bullet
7771 @item int8x8_t vld1_s8 (const int8_t *)
7772 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7773 @end itemize
7774
7775
7776 @itemize @bullet
7777 @item uint64x1_t vld1_u64 (const uint64_t *)
7778 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7779 @end itemize
7780
7781
7782 @itemize @bullet
7783 @item int64x1_t vld1_s64 (const int64_t *)
7784 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7785 @end itemize
7786
7787
7788 @itemize @bullet
7789 @item float32x2_t vld1_f32 (const float32_t *)
7790 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7791 @end itemize
7792
7793
7794 @itemize @bullet
7795 @item poly16x4_t vld1_p16 (const poly16_t *)
7796 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7797 @end itemize
7798
7799
7800 @itemize @bullet
7801 @item poly8x8_t vld1_p8 (const poly8_t *)
7802 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7803 @end itemize
7804
7805
7806 @itemize @bullet
7807 @item poly64x2_t vld1q_p64 (const poly64_t *)
7808 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7809 @end itemize
7810
7811
7812 @itemize @bullet
7813 @item uint32x4_t vld1q_u32 (const uint32_t *)
7814 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7815 @end itemize
7816
7817
7818 @itemize @bullet
7819 @item uint16x8_t vld1q_u16 (const uint16_t *)
7820 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7821 @end itemize
7822
7823
7824 @itemize @bullet
7825 @item uint8x16_t vld1q_u8 (const uint8_t *)
7826 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7827 @end itemize
7828
7829
7830 @itemize @bullet
7831 @item int32x4_t vld1q_s32 (const int32_t *)
7832 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7833 @end itemize
7834
7835
7836 @itemize @bullet
7837 @item int16x8_t vld1q_s16 (const int16_t *)
7838 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7839 @end itemize
7840
7841
7842 @itemize @bullet
7843 @item int8x16_t vld1q_s8 (const int8_t *)
7844 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7845 @end itemize
7846
7847
7848 @itemize @bullet
7849 @item uint64x2_t vld1q_u64 (const uint64_t *)
7850 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7851 @end itemize
7852
7853
7854 @itemize @bullet
7855 @item int64x2_t vld1q_s64 (const int64_t *)
7856 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7857 @end itemize
7858
7859
7860 @itemize @bullet
7861 @item float32x4_t vld1q_f32 (const float32_t *)
7862 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7863 @end itemize
7864
7865
7866 @itemize @bullet
7867 @item poly16x8_t vld1q_p16 (const poly16_t *)
7868 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7869 @end itemize
7870
7871
7872 @itemize @bullet
7873 @item poly8x16_t vld1q_p8 (const poly8_t *)
7874 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7875 @end itemize
7876
7877
7878 @itemize @bullet
7879 @item uint32x2_t vld1_lane_u32 (const uint32_t *, uint32x2_t, const int)
7880 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7881 @end itemize
7882
7883
7884 @itemize @bullet
7885 @item uint16x4_t vld1_lane_u16 (const uint16_t *, uint16x4_t, const int)
7886 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7887 @end itemize
7888
7889
7890 @itemize @bullet
7891 @item uint8x8_t vld1_lane_u8 (const uint8_t *, uint8x8_t, const int)
7892 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7893 @end itemize
7894
7895
7896 @itemize @bullet
7897 @item int32x2_t vld1_lane_s32 (const int32_t *, int32x2_t, const int)
7898 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7899 @end itemize
7900
7901
7902 @itemize @bullet
7903 @item int16x4_t vld1_lane_s16 (const int16_t *, int16x4_t, const int)
7904 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7905 @end itemize
7906
7907
7908 @itemize @bullet
7909 @item int8x8_t vld1_lane_s8 (const int8_t *, int8x8_t, const int)
7910 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7911 @end itemize
7912
7913
7914 @itemize @bullet
7915 @item float32x2_t vld1_lane_f32 (const float32_t *, float32x2_t, const int)
7916 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7917 @end itemize
7918
7919
7920 @itemize @bullet
7921 @item poly16x4_t vld1_lane_p16 (const poly16_t *, poly16x4_t, const int)
7922 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7923 @end itemize
7924
7925
7926 @itemize @bullet
7927 @item poly8x8_t vld1_lane_p8 (const poly8_t *, poly8x8_t, const int)
7928 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7929 @end itemize
7930
7931
7932 @itemize @bullet
7933 @item poly64x1_t vld1_lane_p64 (const poly64_t *, poly64x1_t, const int)
7934 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7935 @end itemize
7936
7937
7938 @itemize @bullet
7939 @item uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int)
7940 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7941 @end itemize
7942
7943
7944 @itemize @bullet
7945 @item int64x1_t vld1_lane_s64 (const int64_t *, int64x1_t, const int)
7946 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7947 @end itemize
7948
7949
7950 @itemize @bullet
7951 @item uint32x4_t vld1q_lane_u32 (const uint32_t *, uint32x4_t, const int)
7952 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7953 @end itemize
7954
7955
7956 @itemize @bullet
7957 @item uint16x8_t vld1q_lane_u16 (const uint16_t *, uint16x8_t, const int)
7958 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7959 @end itemize
7960
7961
7962 @itemize @bullet
7963 @item uint8x16_t vld1q_lane_u8 (const uint8_t *, uint8x16_t, const int)
7964 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7965 @end itemize
7966
7967
7968 @itemize @bullet
7969 @item int32x4_t vld1q_lane_s32 (const int32_t *, int32x4_t, const int)
7970 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7971 @end itemize
7972
7973
7974 @itemize @bullet
7975 @item int16x8_t vld1q_lane_s16 (const int16_t *, int16x8_t, const int)
7976 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7977 @end itemize
7978
7979
7980 @itemize @bullet
7981 @item int8x16_t vld1q_lane_s8 (const int8_t *, int8x16_t, const int)
7982 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7983 @end itemize
7984
7985
7986 @itemize @bullet
7987 @item float32x4_t vld1q_lane_f32 (const float32_t *, float32x4_t, const int)
7988 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7989 @end itemize
7990
7991
7992 @itemize @bullet
7993 @item poly16x8_t vld1q_lane_p16 (const poly16_t *, poly16x8_t, const int)
7994 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7995 @end itemize
7996
7997
7998 @itemize @bullet
7999 @item poly8x16_t vld1q_lane_p8 (const poly8_t *, poly8x16_t, const int)
8000 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8001 @end itemize
8002
8003
8004 @itemize @bullet
8005 @item poly64x2_t vld1q_lane_p64 (const poly64_t *, poly64x2_t, const int)
8006 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8007 @end itemize
8008
8009
8010 @itemize @bullet
8011 @item uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int)
8012 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8013 @end itemize
8014
8015
8016 @itemize @bullet
8017 @item int64x2_t vld1q_lane_s64 (const int64_t *, int64x2_t, const int)
8018 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8019 @end itemize
8020
8021
8022 @itemize @bullet
8023 @item uint32x2_t vld1_dup_u32 (const uint32_t *)
8024 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
8025 @end itemize
8026
8027
8028 @itemize @bullet
8029 @item uint16x4_t vld1_dup_u16 (const uint16_t *)
8030 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
8031 @end itemize
8032
8033
8034 @itemize @bullet
8035 @item uint8x8_t vld1_dup_u8 (const uint8_t *)
8036 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
8037 @end itemize
8038
8039
8040 @itemize @bullet
8041 @item int32x2_t vld1_dup_s32 (const int32_t *)
8042 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
8043 @end itemize
8044
8045
8046 @itemize @bullet
8047 @item int16x4_t vld1_dup_s16 (const int16_t *)
8048 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
8049 @end itemize
8050
8051
8052 @itemize @bullet
8053 @item int8x8_t vld1_dup_s8 (const int8_t *)
8054 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
8055 @end itemize
8056
8057
8058 @itemize @bullet
8059 @item float32x2_t vld1_dup_f32 (const float32_t *)
8060 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
8061 @end itemize
8062
8063
8064 @itemize @bullet
8065 @item poly16x4_t vld1_dup_p16 (const poly16_t *)
8066 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
8067 @end itemize
8068
8069
8070 @itemize @bullet
8071 @item poly8x8_t vld1_dup_p8 (const poly8_t *)
8072 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
8073 @end itemize
8074
8075
8076 @itemize @bullet
8077 @item poly64x1_t vld1_dup_p64 (const poly64_t *)
8078 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8079 @end itemize
8080
8081
8082 @itemize @bullet
8083 @item uint64x1_t vld1_dup_u64 (const uint64_t *)
8084 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8085 @end itemize
8086
8087
8088 @itemize @bullet
8089 @item int64x1_t vld1_dup_s64 (const int64_t *)
8090 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8091 @end itemize
8092
8093
8094 @itemize @bullet
8095 @item uint32x4_t vld1q_dup_u32 (const uint32_t *)
8096 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8097 @end itemize
8098
8099
8100 @itemize @bullet
8101 @item uint16x8_t vld1q_dup_u16 (const uint16_t *)
8102 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8103 @end itemize
8104
8105
8106 @itemize @bullet
8107 @item uint8x16_t vld1q_dup_u8 (const uint8_t *)
8108 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8109 @end itemize
8110
8111
8112 @itemize @bullet
8113 @item int32x4_t vld1q_dup_s32 (const int32_t *)
8114 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8115 @end itemize
8116
8117
8118 @itemize @bullet
8119 @item int16x8_t vld1q_dup_s16 (const int16_t *)
8120 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8121 @end itemize
8122
8123
8124 @itemize @bullet
8125 @item int8x16_t vld1q_dup_s8 (const int8_t *)
8126 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8127 @end itemize
8128
8129
8130 @itemize @bullet
8131 @item float32x4_t vld1q_dup_f32 (const float32_t *)
8132 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8133 @end itemize
8134
8135
8136 @itemize @bullet
8137 @item poly16x8_t vld1q_dup_p16 (const poly16_t *)
8138 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8139 @end itemize
8140
8141
8142 @itemize @bullet
8143 @item poly8x16_t vld1q_dup_p8 (const poly8_t *)
8144 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8145 @end itemize
8146
8147
8148 @itemize @bullet
8149 @item poly64x2_t vld1q_dup_p64 (const poly64_t *)
8150 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8151 @end itemize
8152
8153
8154 @itemize @bullet
8155 @item uint64x2_t vld1q_dup_u64 (const uint64_t *)
8156 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8157 @end itemize
8158
8159
8160 @itemize @bullet
8161 @item int64x2_t vld1q_dup_s64 (const int64_t *)
8162 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8163 @end itemize
8164
8165
8166
8167
8168 @subsubsection Element/structure stores, VST1 variants
8169
8170 @itemize @bullet
8171 @item void vst1_p64 (poly64_t *, poly64x1_t)
8172 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8173 @end itemize
8174
8175
8176 @itemize @bullet
8177 @item void vst1_u32 (uint32_t *, uint32x2_t)
8178 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
8179 @end itemize
8180
8181
8182 @itemize @bullet
8183 @item void vst1_u16 (uint16_t *, uint16x4_t)
8184 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
8185 @end itemize
8186
8187
8188 @itemize @bullet
8189 @item void vst1_u8 (uint8_t *, uint8x8_t)
8190 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
8191 @end itemize
8192
8193
8194 @itemize @bullet
8195 @item void vst1_s32 (int32_t *, int32x2_t)
8196 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
8197 @end itemize
8198
8199
8200 @itemize @bullet
8201 @item void vst1_s16 (int16_t *, int16x4_t)
8202 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
8203 @end itemize
8204
8205
8206 @itemize @bullet
8207 @item void vst1_s8 (int8_t *, int8x8_t)
8208 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
8209 @end itemize
8210
8211
8212 @itemize @bullet
8213 @item void vst1_u64 (uint64_t *, uint64x1_t)
8214 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8215 @end itemize
8216
8217
8218 @itemize @bullet
8219 @item void vst1_s64 (int64_t *, int64x1_t)
8220 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8221 @end itemize
8222
8223
8224 @itemize @bullet
8225 @item void vst1_f32 (float32_t *, float32x2_t)
8226 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
8227 @end itemize
8228
8229
8230 @itemize @bullet
8231 @item void vst1_p16 (poly16_t *, poly16x4_t)
8232 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
8233 @end itemize
8234
8235
8236 @itemize @bullet
8237 @item void vst1_p8 (poly8_t *, poly8x8_t)
8238 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
8239 @end itemize
8240
8241
8242 @itemize @bullet
8243 @item void vst1q_p64 (poly64_t *, poly64x2_t)
8244 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8245 @end itemize
8246
8247
8248 @itemize @bullet
8249 @item void vst1q_u32 (uint32_t *, uint32x4_t)
8250 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8251 @end itemize
8252
8253
8254 @itemize @bullet
8255 @item void vst1q_u16 (uint16_t *, uint16x8_t)
8256 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8257 @end itemize
8258
8259
8260 @itemize @bullet
8261 @item void vst1q_u8 (uint8_t *, uint8x16_t)
8262 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8263 @end itemize
8264
8265
8266 @itemize @bullet
8267 @item void vst1q_s32 (int32_t *, int32x4_t)
8268 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8269 @end itemize
8270
8271
8272 @itemize @bullet
8273 @item void vst1q_s16 (int16_t *, int16x8_t)
8274 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8275 @end itemize
8276
8277
8278 @itemize @bullet
8279 @item void vst1q_s8 (int8_t *, int8x16_t)
8280 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8281 @end itemize
8282
8283
8284 @itemize @bullet
8285 @item void vst1q_u64 (uint64_t *, uint64x2_t)
8286 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8287 @end itemize
8288
8289
8290 @itemize @bullet
8291 @item void vst1q_s64 (int64_t *, int64x2_t)
8292 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8293 @end itemize
8294
8295
8296 @itemize @bullet
8297 @item void vst1q_f32 (float32_t *, float32x4_t)
8298 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8299 @end itemize
8300
8301
8302 @itemize @bullet
8303 @item void vst1q_p16 (poly16_t *, poly16x8_t)
8304 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8305 @end itemize
8306
8307
8308 @itemize @bullet
8309 @item void vst1q_p8 (poly8_t *, poly8x16_t)
8310 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8311 @end itemize
8312
8313
8314 @itemize @bullet
8315 @item void vst1_lane_u32 (uint32_t *, uint32x2_t, const int)
8316 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8317 @end itemize
8318
8319
8320 @itemize @bullet
8321 @item void vst1_lane_u16 (uint16_t *, uint16x4_t, const int)
8322 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8323 @end itemize
8324
8325
8326 @itemize @bullet
8327 @item void vst1_lane_u8 (uint8_t *, uint8x8_t, const int)
8328 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8329 @end itemize
8330
8331
8332 @itemize @bullet
8333 @item void vst1_lane_s32 (int32_t *, int32x2_t, const int)
8334 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8335 @end itemize
8336
8337
8338 @itemize @bullet
8339 @item void vst1_lane_s16 (int16_t *, int16x4_t, const int)
8340 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8341 @end itemize
8342
8343
8344 @itemize @bullet
8345 @item void vst1_lane_s8 (int8_t *, int8x8_t, const int)
8346 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8347 @end itemize
8348
8349
8350 @itemize @bullet
8351 @item void vst1_lane_f32 (float32_t *, float32x2_t, const int)
8352 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8353 @end itemize
8354
8355
8356 @itemize @bullet
8357 @item void vst1_lane_p16 (poly16_t *, poly16x4_t, const int)
8358 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8359 @end itemize
8360
8361
8362 @itemize @bullet
8363 @item void vst1_lane_p8 (poly8_t *, poly8x8_t, const int)
8364 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8365 @end itemize
8366
8367
8368 @itemize @bullet
8369 @item void vst1_lane_p64 (poly64_t *, poly64x1_t, const int)
8370 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8371 @end itemize
8372
8373
8374 @itemize @bullet
8375 @item void vst1_lane_s64 (int64_t *, int64x1_t, const int)
8376 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8377 @end itemize
8378
8379
8380 @itemize @bullet
8381 @item void vst1_lane_u64 (uint64_t *, uint64x1_t, const int)
8382 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8383 @end itemize
8384
8385
8386 @itemize @bullet
8387 @item void vst1q_lane_u32 (uint32_t *, uint32x4_t, const int)
8388 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8389 @end itemize
8390
8391
8392 @itemize @bullet
8393 @item void vst1q_lane_u16 (uint16_t *, uint16x8_t, const int)
8394 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8395 @end itemize
8396
8397
8398 @itemize @bullet
8399 @item void vst1q_lane_u8 (uint8_t *, uint8x16_t, const int)
8400 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8401 @end itemize
8402
8403
8404 @itemize @bullet
8405 @item void vst1q_lane_s32 (int32_t *, int32x4_t, const int)
8406 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8407 @end itemize
8408
8409
8410 @itemize @bullet
8411 @item void vst1q_lane_s16 (int16_t *, int16x8_t, const int)
8412 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8413 @end itemize
8414
8415
8416 @itemize @bullet
8417 @item void vst1q_lane_s8 (int8_t *, int8x16_t, const int)
8418 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8419 @end itemize
8420
8421
8422 @itemize @bullet
8423 @item void vst1q_lane_f32 (float32_t *, float32x4_t, const int)
8424 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8425 @end itemize
8426
8427
8428 @itemize @bullet
8429 @item void vst1q_lane_p16 (poly16_t *, poly16x8_t, const int)
8430 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8431 @end itemize
8432
8433
8434 @itemize @bullet
8435 @item void vst1q_lane_p8 (poly8_t *, poly8x16_t, const int)
8436 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8437 @end itemize
8438
8439
8440 @itemize @bullet
8441 @item void vst1q_lane_p64 (poly64_t *, poly64x2_t, const int)
8442 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8443 @end itemize
8444
8445
8446 @itemize @bullet
8447 @item void vst1q_lane_s64 (int64_t *, int64x2_t, const int)
8448 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8449 @end itemize
8450
8451
8452 @itemize @bullet
8453 @item void vst1q_lane_u64 (uint64_t *, uint64x2_t, const int)
8454 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8455 @end itemize
8456
8457
8458
8459
8460 @subsubsection Element/structure loads, VLD2 variants
8461
8462 @itemize @bullet
8463 @item uint32x2x2_t vld2_u32 (const uint32_t *)
8464 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8465 @end itemize
8466
8467
8468 @itemize @bullet
8469 @item uint16x4x2_t vld2_u16 (const uint16_t *)
8470 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8471 @end itemize
8472
8473
8474 @itemize @bullet
8475 @item uint8x8x2_t vld2_u8 (const uint8_t *)
8476 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8477 @end itemize
8478
8479
8480 @itemize @bullet
8481 @item int32x2x2_t vld2_s32 (const int32_t *)
8482 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8483 @end itemize
8484
8485
8486 @itemize @bullet
8487 @item int16x4x2_t vld2_s16 (const int16_t *)
8488 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8489 @end itemize
8490
8491
8492 @itemize @bullet
8493 @item int8x8x2_t vld2_s8 (const int8_t *)
8494 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8495 @end itemize
8496
8497
8498 @itemize @bullet
8499 @item float32x2x2_t vld2_f32 (const float32_t *)
8500 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8501 @end itemize
8502
8503
8504 @itemize @bullet
8505 @item poly16x4x2_t vld2_p16 (const poly16_t *)
8506 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8507 @end itemize
8508
8509
8510 @itemize @bullet
8511 @item poly8x8x2_t vld2_p8 (const poly8_t *)
8512 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8513 @end itemize
8514
8515
8516 @itemize @bullet
8517 @item poly64x1x2_t vld2_p64 (const poly64_t *)
8518 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8519 @end itemize
8520
8521
8522 @itemize @bullet
8523 @item uint64x1x2_t vld2_u64 (const uint64_t *)
8524 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8525 @end itemize
8526
8527
8528 @itemize @bullet
8529 @item int64x1x2_t vld2_s64 (const int64_t *)
8530 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8531 @end itemize
8532
8533
8534 @itemize @bullet
8535 @item uint32x4x2_t vld2q_u32 (const uint32_t *)
8536 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8537 @end itemize
8538
8539
8540 @itemize @bullet
8541 @item uint16x8x2_t vld2q_u16 (const uint16_t *)
8542 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8543 @end itemize
8544
8545
8546 @itemize @bullet
8547 @item uint8x16x2_t vld2q_u8 (const uint8_t *)
8548 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8549 @end itemize
8550
8551
8552 @itemize @bullet
8553 @item int32x4x2_t vld2q_s32 (const int32_t *)
8554 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8555 @end itemize
8556
8557
8558 @itemize @bullet
8559 @item int16x8x2_t vld2q_s16 (const int16_t *)
8560 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8561 @end itemize
8562
8563
8564 @itemize @bullet
8565 @item int8x16x2_t vld2q_s8 (const int8_t *)
8566 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8567 @end itemize
8568
8569
8570 @itemize @bullet
8571 @item float32x4x2_t vld2q_f32 (const float32_t *)
8572 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8573 @end itemize
8574
8575
8576 @itemize @bullet
8577 @item poly16x8x2_t vld2q_p16 (const poly16_t *)
8578 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8579 @end itemize
8580
8581
8582 @itemize @bullet
8583 @item poly8x16x2_t vld2q_p8 (const poly8_t *)
8584 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8585 @end itemize
8586
8587
8588 @itemize @bullet
8589 @item uint32x2x2_t vld2_lane_u32 (const uint32_t *, uint32x2x2_t, const int)
8590 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8591 @end itemize
8592
8593
8594 @itemize @bullet
8595 @item uint16x4x2_t vld2_lane_u16 (const uint16_t *, uint16x4x2_t, const int)
8596 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8597 @end itemize
8598
8599
8600 @itemize @bullet
8601 @item uint8x8x2_t vld2_lane_u8 (const uint8_t *, uint8x8x2_t, const int)
8602 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8603 @end itemize
8604
8605
8606 @itemize @bullet
8607 @item int32x2x2_t vld2_lane_s32 (const int32_t *, int32x2x2_t, const int)
8608 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8609 @end itemize
8610
8611
8612 @itemize @bullet
8613 @item int16x4x2_t vld2_lane_s16 (const int16_t *, int16x4x2_t, const int)
8614 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8615 @end itemize
8616
8617
8618 @itemize @bullet
8619 @item int8x8x2_t vld2_lane_s8 (const int8_t *, int8x8x2_t, const int)
8620 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8621 @end itemize
8622
8623
8624 @itemize @bullet
8625 @item float32x2x2_t vld2_lane_f32 (const float32_t *, float32x2x2_t, const int)
8626 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8627 @end itemize
8628
8629
8630 @itemize @bullet
8631 @item poly16x4x2_t vld2_lane_p16 (const poly16_t *, poly16x4x2_t, const int)
8632 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8633 @end itemize
8634
8635
8636 @itemize @bullet
8637 @item poly8x8x2_t vld2_lane_p8 (const poly8_t *, poly8x8x2_t, const int)
8638 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8639 @end itemize
8640
8641
8642 @itemize @bullet
8643 @item int32x4x2_t vld2q_lane_s32 (const int32_t *, int32x4x2_t, const int)
8644 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8645 @end itemize
8646
8647
8648 @itemize @bullet
8649 @item int16x8x2_t vld2q_lane_s16 (const int16_t *, int16x8x2_t, const int)
8650 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8651 @end itemize
8652
8653
8654 @itemize @bullet
8655 @item uint32x4x2_t vld2q_lane_u32 (const uint32_t *, uint32x4x2_t, const int)
8656 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8657 @end itemize
8658
8659
8660 @itemize @bullet
8661 @item uint16x8x2_t vld2q_lane_u16 (const uint16_t *, uint16x8x2_t, const int)
8662 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8663 @end itemize
8664
8665
8666 @itemize @bullet
8667 @item float32x4x2_t vld2q_lane_f32 (const float32_t *, float32x4x2_t, const int)
8668 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8669 @end itemize
8670
8671
8672 @itemize @bullet
8673 @item poly16x8x2_t vld2q_lane_p16 (const poly16_t *, poly16x8x2_t, const int)
8674 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8675 @end itemize
8676
8677
8678 @itemize @bullet
8679 @item uint32x2x2_t vld2_dup_u32 (const uint32_t *)
8680 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8681 @end itemize
8682
8683
8684 @itemize @bullet
8685 @item uint16x4x2_t vld2_dup_u16 (const uint16_t *)
8686 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8687 @end itemize
8688
8689
8690 @itemize @bullet
8691 @item uint8x8x2_t vld2_dup_u8 (const uint8_t *)
8692 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8693 @end itemize
8694
8695
8696 @itemize @bullet
8697 @item int32x2x2_t vld2_dup_s32 (const int32_t *)
8698 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8699 @end itemize
8700
8701
8702 @itemize @bullet
8703 @item int16x4x2_t vld2_dup_s16 (const int16_t *)
8704 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8705 @end itemize
8706
8707
8708 @itemize @bullet
8709 @item int8x8x2_t vld2_dup_s8 (const int8_t *)
8710 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8711 @end itemize
8712
8713
8714 @itemize @bullet
8715 @item float32x2x2_t vld2_dup_f32 (const float32_t *)
8716 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8717 @end itemize
8718
8719
8720 @itemize @bullet
8721 @item poly16x4x2_t vld2_dup_p16 (const poly16_t *)
8722 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8723 @end itemize
8724
8725
8726 @itemize @bullet
8727 @item poly8x8x2_t vld2_dup_p8 (const poly8_t *)
8728 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8729 @end itemize
8730
8731
8732 @itemize @bullet
8733 @item poly64x1x2_t vld2_dup_p64 (const poly64_t *)
8734 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8735 @end itemize
8736
8737
8738 @itemize @bullet
8739 @item uint64x1x2_t vld2_dup_u64 (const uint64_t *)
8740 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8741 @end itemize
8742
8743
8744 @itemize @bullet
8745 @item int64x1x2_t vld2_dup_s64 (const int64_t *)
8746 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8747 @end itemize
8748
8749
8750
8751
8752 @subsubsection Element/structure stores, VST2 variants
8753
8754 @itemize @bullet
8755 @item void vst2_u32 (uint32_t *, uint32x2x2_t)
8756 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8757 @end itemize
8758
8759
8760 @itemize @bullet
8761 @item void vst2_u16 (uint16_t *, uint16x4x2_t)
8762 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8763 @end itemize
8764
8765
8766 @itemize @bullet
8767 @item void vst2_u8 (uint8_t *, uint8x8x2_t)
8768 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8769 @end itemize
8770
8771
8772 @itemize @bullet
8773 @item void vst2_s32 (int32_t *, int32x2x2_t)
8774 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8775 @end itemize
8776
8777
8778 @itemize @bullet
8779 @item void vst2_s16 (int16_t *, int16x4x2_t)
8780 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8781 @end itemize
8782
8783
8784 @itemize @bullet
8785 @item void vst2_s8 (int8_t *, int8x8x2_t)
8786 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8787 @end itemize
8788
8789
8790 @itemize @bullet
8791 @item void vst2_f32 (float32_t *, float32x2x2_t)
8792 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8793 @end itemize
8794
8795
8796 @itemize @bullet
8797 @item void vst2_p16 (poly16_t *, poly16x4x2_t)
8798 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8799 @end itemize
8800
8801
8802 @itemize @bullet
8803 @item void vst2_p8 (poly8_t *, poly8x8x2_t)
8804 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8805 @end itemize
8806
8807
8808 @itemize @bullet
8809 @item void vst2_p64 (poly64_t *, poly64x1x2_t)
8810 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8811 @end itemize
8812
8813
8814 @itemize @bullet
8815 @item void vst2_u64 (uint64_t *, uint64x1x2_t)
8816 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8817 @end itemize
8818
8819
8820 @itemize @bullet
8821 @item void vst2_s64 (int64_t *, int64x1x2_t)
8822 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8823 @end itemize
8824
8825
8826 @itemize @bullet
8827 @item void vst2q_u32 (uint32_t *, uint32x4x2_t)
8828 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8829 @end itemize
8830
8831
8832 @itemize @bullet
8833 @item void vst2q_u16 (uint16_t *, uint16x8x2_t)
8834 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8835 @end itemize
8836
8837
8838 @itemize @bullet
8839 @item void vst2q_u8 (uint8_t *, uint8x16x2_t)
8840 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8841 @end itemize
8842
8843
8844 @itemize @bullet
8845 @item void vst2q_s32 (int32_t *, int32x4x2_t)
8846 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8847 @end itemize
8848
8849
8850 @itemize @bullet
8851 @item void vst2q_s16 (int16_t *, int16x8x2_t)
8852 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8853 @end itemize
8854
8855
8856 @itemize @bullet
8857 @item void vst2q_s8 (int8_t *, int8x16x2_t)
8858 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8859 @end itemize
8860
8861
8862 @itemize @bullet
8863 @item void vst2q_f32 (float32_t *, float32x4x2_t)
8864 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8865 @end itemize
8866
8867
8868 @itemize @bullet
8869 @item void vst2q_p16 (poly16_t *, poly16x8x2_t)
8870 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8871 @end itemize
8872
8873
8874 @itemize @bullet
8875 @item void vst2q_p8 (poly8_t *, poly8x16x2_t)
8876 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8877 @end itemize
8878
8879
8880 @itemize @bullet
8881 @item void vst2_lane_u32 (uint32_t *, uint32x2x2_t, const int)
8882 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8883 @end itemize
8884
8885
8886 @itemize @bullet
8887 @item void vst2_lane_u16 (uint16_t *, uint16x4x2_t, const int)
8888 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8889 @end itemize
8890
8891
8892 @itemize @bullet
8893 @item void vst2_lane_u8 (uint8_t *, uint8x8x2_t, const int)
8894 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8895 @end itemize
8896
8897
8898 @itemize @bullet
8899 @item void vst2_lane_s32 (int32_t *, int32x2x2_t, const int)
8900 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8901 @end itemize
8902
8903
8904 @itemize @bullet
8905 @item void vst2_lane_s16 (int16_t *, int16x4x2_t, const int)
8906 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8907 @end itemize
8908
8909
8910 @itemize @bullet
8911 @item void vst2_lane_s8 (int8_t *, int8x8x2_t, const int)
8912 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8913 @end itemize
8914
8915
8916 @itemize @bullet
8917 @item void vst2_lane_f32 (float32_t *, float32x2x2_t, const int)
8918 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8919 @end itemize
8920
8921
8922 @itemize @bullet
8923 @item void vst2_lane_p16 (poly16_t *, poly16x4x2_t, const int)
8924 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8925 @end itemize
8926
8927
8928 @itemize @bullet
8929 @item void vst2_lane_p8 (poly8_t *, poly8x8x2_t, const int)
8930 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8931 @end itemize
8932
8933
8934 @itemize @bullet
8935 @item void vst2q_lane_s32 (int32_t *, int32x4x2_t, const int)
8936 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8937 @end itemize
8938
8939
8940 @itemize @bullet
8941 @item void vst2q_lane_s16 (int16_t *, int16x8x2_t, const int)
8942 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8943 @end itemize
8944
8945
8946 @itemize @bullet
8947 @item void vst2q_lane_u32 (uint32_t *, uint32x4x2_t, const int)
8948 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8949 @end itemize
8950
8951
8952 @itemize @bullet
8953 @item void vst2q_lane_u16 (uint16_t *, uint16x8x2_t, const int)
8954 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8955 @end itemize
8956
8957
8958 @itemize @bullet
8959 @item void vst2q_lane_f32 (float32_t *, float32x4x2_t, const int)
8960 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8961 @end itemize
8962
8963
8964 @itemize @bullet
8965 @item void vst2q_lane_p16 (poly16_t *, poly16x8x2_t, const int)
8966 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8967 @end itemize
8968
8969
8970
8971
8972 @subsubsection Element/structure loads, VLD3 variants
8973
8974 @itemize @bullet
8975 @item uint32x2x3_t vld3_u32 (const uint32_t *)
8976 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8977 @end itemize
8978
8979
8980 @itemize @bullet
8981 @item uint16x4x3_t vld3_u16 (const uint16_t *)
8982 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8983 @end itemize
8984
8985
8986 @itemize @bullet
8987 @item uint8x8x3_t vld3_u8 (const uint8_t *)
8988 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8989 @end itemize
8990
8991
8992 @itemize @bullet
8993 @item int32x2x3_t vld3_s32 (const int32_t *)
8994 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8995 @end itemize
8996
8997
8998 @itemize @bullet
8999 @item int16x4x3_t vld3_s16 (const int16_t *)
9000 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9001 @end itemize
9002
9003
9004 @itemize @bullet
9005 @item int8x8x3_t vld3_s8 (const int8_t *)
9006 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9007 @end itemize
9008
9009
9010 @itemize @bullet
9011 @item float32x2x3_t vld3_f32 (const float32_t *)
9012 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9013 @end itemize
9014
9015
9016 @itemize @bullet
9017 @item poly16x4x3_t vld3_p16 (const poly16_t *)
9018 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9019 @end itemize
9020
9021
9022 @itemize @bullet
9023 @item poly8x8x3_t vld3_p8 (const poly8_t *)
9024 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9025 @end itemize
9026
9027
9028 @itemize @bullet
9029 @item poly64x1x3_t vld3_p64 (const poly64_t *)
9030 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9031 @end itemize
9032
9033
9034 @itemize @bullet
9035 @item uint64x1x3_t vld3_u64 (const uint64_t *)
9036 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9037 @end itemize
9038
9039
9040 @itemize @bullet
9041 @item int64x1x3_t vld3_s64 (const int64_t *)
9042 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9043 @end itemize
9044
9045
9046 @itemize @bullet
9047 @item uint32x4x3_t vld3q_u32 (const uint32_t *)
9048 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9049 @end itemize
9050
9051
9052 @itemize @bullet
9053 @item uint16x8x3_t vld3q_u16 (const uint16_t *)
9054 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9055 @end itemize
9056
9057
9058 @itemize @bullet
9059 @item uint8x16x3_t vld3q_u8 (const uint8_t *)
9060 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9061 @end itemize
9062
9063
9064 @itemize @bullet
9065 @item int32x4x3_t vld3q_s32 (const int32_t *)
9066 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9067 @end itemize
9068
9069
9070 @itemize @bullet
9071 @item int16x8x3_t vld3q_s16 (const int16_t *)
9072 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9073 @end itemize
9074
9075
9076 @itemize @bullet
9077 @item int8x16x3_t vld3q_s8 (const int8_t *)
9078 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9079 @end itemize
9080
9081
9082 @itemize @bullet
9083 @item float32x4x3_t vld3q_f32 (const float32_t *)
9084 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9085 @end itemize
9086
9087
9088 @itemize @bullet
9089 @item poly16x8x3_t vld3q_p16 (const poly16_t *)
9090 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9091 @end itemize
9092
9093
9094 @itemize @bullet
9095 @item poly8x16x3_t vld3q_p8 (const poly8_t *)
9096 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9097 @end itemize
9098
9099
9100 @itemize @bullet
9101 @item uint32x2x3_t vld3_lane_u32 (const uint32_t *, uint32x2x3_t, const int)
9102 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9103 @end itemize
9104
9105
9106 @itemize @bullet
9107 @item uint16x4x3_t vld3_lane_u16 (const uint16_t *, uint16x4x3_t, const int)
9108 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9109 @end itemize
9110
9111
9112 @itemize @bullet
9113 @item uint8x8x3_t vld3_lane_u8 (const uint8_t *, uint8x8x3_t, const int)
9114 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9115 @end itemize
9116
9117
9118 @itemize @bullet
9119 @item int32x2x3_t vld3_lane_s32 (const int32_t *, int32x2x3_t, const int)
9120 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9121 @end itemize
9122
9123
9124 @itemize @bullet
9125 @item int16x4x3_t vld3_lane_s16 (const int16_t *, int16x4x3_t, const int)
9126 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9127 @end itemize
9128
9129
9130 @itemize @bullet
9131 @item int8x8x3_t vld3_lane_s8 (const int8_t *, int8x8x3_t, const int)
9132 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9133 @end itemize
9134
9135
9136 @itemize @bullet
9137 @item float32x2x3_t vld3_lane_f32 (const float32_t *, float32x2x3_t, const int)
9138 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9139 @end itemize
9140
9141
9142 @itemize @bullet
9143 @item poly16x4x3_t vld3_lane_p16 (const poly16_t *, poly16x4x3_t, const int)
9144 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9145 @end itemize
9146
9147
9148 @itemize @bullet
9149 @item poly8x8x3_t vld3_lane_p8 (const poly8_t *, poly8x8x3_t, const int)
9150 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9151 @end itemize
9152
9153
9154 @itemize @bullet
9155 @item int32x4x3_t vld3q_lane_s32 (const int32_t *, int32x4x3_t, const int)
9156 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9157 @end itemize
9158
9159
9160 @itemize @bullet
9161 @item int16x8x3_t vld3q_lane_s16 (const int16_t *, int16x8x3_t, const int)
9162 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9163 @end itemize
9164
9165
9166 @itemize @bullet
9167 @item uint32x4x3_t vld3q_lane_u32 (const uint32_t *, uint32x4x3_t, const int)
9168 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9169 @end itemize
9170
9171
9172 @itemize @bullet
9173 @item uint16x8x3_t vld3q_lane_u16 (const uint16_t *, uint16x8x3_t, const int)
9174 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9175 @end itemize
9176
9177
9178 @itemize @bullet
9179 @item float32x4x3_t vld3q_lane_f32 (const float32_t *, float32x4x3_t, const int)
9180 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9181 @end itemize
9182
9183
9184 @itemize @bullet
9185 @item poly16x8x3_t vld3q_lane_p16 (const poly16_t *, poly16x8x3_t, const int)
9186 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9187 @end itemize
9188
9189
9190 @itemize @bullet
9191 @item uint32x2x3_t vld3_dup_u32 (const uint32_t *)
9192 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9193 @end itemize
9194
9195
9196 @itemize @bullet
9197 @item uint16x4x3_t vld3_dup_u16 (const uint16_t *)
9198 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9199 @end itemize
9200
9201
9202 @itemize @bullet
9203 @item uint8x8x3_t vld3_dup_u8 (const uint8_t *)
9204 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9205 @end itemize
9206
9207
9208 @itemize @bullet
9209 @item int32x2x3_t vld3_dup_s32 (const int32_t *)
9210 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9211 @end itemize
9212
9213
9214 @itemize @bullet
9215 @item int16x4x3_t vld3_dup_s16 (const int16_t *)
9216 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9217 @end itemize
9218
9219
9220 @itemize @bullet
9221 @item int8x8x3_t vld3_dup_s8 (const int8_t *)
9222 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9223 @end itemize
9224
9225
9226 @itemize @bullet
9227 @item float32x2x3_t vld3_dup_f32 (const float32_t *)
9228 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9229 @end itemize
9230
9231
9232 @itemize @bullet
9233 @item poly16x4x3_t vld3_dup_p16 (const poly16_t *)
9234 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9235 @end itemize
9236
9237
9238 @itemize @bullet
9239 @item poly8x8x3_t vld3_dup_p8 (const poly8_t *)
9240 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9241 @end itemize
9242
9243
9244 @itemize @bullet
9245 @item poly64x1x3_t vld3_dup_p64 (const poly64_t *)
9246 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9247 @end itemize
9248
9249
9250 @itemize @bullet
9251 @item uint64x1x3_t vld3_dup_u64 (const uint64_t *)
9252 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9253 @end itemize
9254
9255
9256 @itemize @bullet
9257 @item int64x1x3_t vld3_dup_s64 (const int64_t *)
9258 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9259 @end itemize
9260
9261
9262
9263
9264 @subsubsection Element/structure stores, VST3 variants
9265
9266 @itemize @bullet
9267 @item void vst3_u32 (uint32_t *, uint32x2x3_t)
9268 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9269 @end itemize
9270
9271
9272 @itemize @bullet
9273 @item void vst3_u16 (uint16_t *, uint16x4x3_t)
9274 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9275 @end itemize
9276
9277
9278 @itemize @bullet
9279 @item void vst3_u8 (uint8_t *, uint8x8x3_t)
9280 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9281 @end itemize
9282
9283
9284 @itemize @bullet
9285 @item void vst3_s32 (int32_t *, int32x2x3_t)
9286 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9287 @end itemize
9288
9289
9290 @itemize @bullet
9291 @item void vst3_s16 (int16_t *, int16x4x3_t)
9292 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9293 @end itemize
9294
9295
9296 @itemize @bullet
9297 @item void vst3_s8 (int8_t *, int8x8x3_t)
9298 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9299 @end itemize
9300
9301
9302 @itemize @bullet
9303 @item void vst3_f32 (float32_t *, float32x2x3_t)
9304 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9305 @end itemize
9306
9307
9308 @itemize @bullet
9309 @item void vst3_p16 (poly16_t *, poly16x4x3_t)
9310 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9311 @end itemize
9312
9313
9314 @itemize @bullet
9315 @item void vst3_p8 (poly8_t *, poly8x8x3_t)
9316 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9317 @end itemize
9318
9319
9320 @itemize @bullet
9321 @item void vst3_p64 (poly64_t *, poly64x1x3_t)
9322 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9323 @end itemize
9324
9325
9326 @itemize @bullet
9327 @item void vst3_u64 (uint64_t *, uint64x1x3_t)
9328 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9329 @end itemize
9330
9331
9332 @itemize @bullet
9333 @item void vst3_s64 (int64_t *, int64x1x3_t)
9334 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9335 @end itemize
9336
9337
9338 @itemize @bullet
9339 @item void vst3q_u32 (uint32_t *, uint32x4x3_t)
9340 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9341 @end itemize
9342
9343
9344 @itemize @bullet
9345 @item void vst3q_u16 (uint16_t *, uint16x8x3_t)
9346 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9347 @end itemize
9348
9349
9350 @itemize @bullet
9351 @item void vst3q_u8 (uint8_t *, uint8x16x3_t)
9352 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9353 @end itemize
9354
9355
9356 @itemize @bullet
9357 @item void vst3q_s32 (int32_t *, int32x4x3_t)
9358 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9359 @end itemize
9360
9361
9362 @itemize @bullet
9363 @item void vst3q_s16 (int16_t *, int16x8x3_t)
9364 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9365 @end itemize
9366
9367
9368 @itemize @bullet
9369 @item void vst3q_s8 (int8_t *, int8x16x3_t)
9370 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9371 @end itemize
9372
9373
9374 @itemize @bullet
9375 @item void vst3q_f32 (float32_t *, float32x4x3_t)
9376 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9377 @end itemize
9378
9379
9380 @itemize @bullet
9381 @item void vst3q_p16 (poly16_t *, poly16x8x3_t)
9382 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9383 @end itemize
9384
9385
9386 @itemize @bullet
9387 @item void vst3q_p8 (poly8_t *, poly8x16x3_t)
9388 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9389 @end itemize
9390
9391
9392 @itemize @bullet
9393 @item void vst3_lane_u32 (uint32_t *, uint32x2x3_t, const int)
9394 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9395 @end itemize
9396
9397
9398 @itemize @bullet
9399 @item void vst3_lane_u16 (uint16_t *, uint16x4x3_t, const int)
9400 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9401 @end itemize
9402
9403
9404 @itemize @bullet
9405 @item void vst3_lane_u8 (uint8_t *, uint8x8x3_t, const int)
9406 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9407 @end itemize
9408
9409
9410 @itemize @bullet
9411 @item void vst3_lane_s32 (int32_t *, int32x2x3_t, const int)
9412 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9413 @end itemize
9414
9415
9416 @itemize @bullet
9417 @item void vst3_lane_s16 (int16_t *, int16x4x3_t, const int)
9418 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9419 @end itemize
9420
9421
9422 @itemize @bullet
9423 @item void vst3_lane_s8 (int8_t *, int8x8x3_t, const int)
9424 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9425 @end itemize
9426
9427
9428 @itemize @bullet
9429 @item void vst3_lane_f32 (float32_t *, float32x2x3_t, const int)
9430 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9431 @end itemize
9432
9433
9434 @itemize @bullet
9435 @item void vst3_lane_p16 (poly16_t *, poly16x4x3_t, const int)
9436 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9437 @end itemize
9438
9439
9440 @itemize @bullet
9441 @item void vst3_lane_p8 (poly8_t *, poly8x8x3_t, const int)
9442 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9443 @end itemize
9444
9445
9446 @itemize @bullet
9447 @item void vst3q_lane_s32 (int32_t *, int32x4x3_t, const int)
9448 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9449 @end itemize
9450
9451
9452 @itemize @bullet
9453 @item void vst3q_lane_s16 (int16_t *, int16x8x3_t, const int)
9454 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9455 @end itemize
9456
9457
9458 @itemize @bullet
9459 @item void vst3q_lane_u32 (uint32_t *, uint32x4x3_t, const int)
9460 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9461 @end itemize
9462
9463
9464 @itemize @bullet
9465 @item void vst3q_lane_u16 (uint16_t *, uint16x8x3_t, const int)
9466 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9467 @end itemize
9468
9469
9470 @itemize @bullet
9471 @item void vst3q_lane_f32 (float32_t *, float32x4x3_t, const int)
9472 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9473 @end itemize
9474
9475
9476 @itemize @bullet
9477 @item void vst3q_lane_p16 (poly16_t *, poly16x8x3_t, const int)
9478 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9479 @end itemize
9480
9481
9482
9483
9484 @subsubsection Element/structure loads, VLD4 variants
9485
9486 @itemize @bullet
9487 @item uint32x2x4_t vld4_u32 (const uint32_t *)
9488 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9489 @end itemize
9490
9491
9492 @itemize @bullet
9493 @item uint16x4x4_t vld4_u16 (const uint16_t *)
9494 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9495 @end itemize
9496
9497
9498 @itemize @bullet
9499 @item uint8x8x4_t vld4_u8 (const uint8_t *)
9500 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9501 @end itemize
9502
9503
9504 @itemize @bullet
9505 @item int32x2x4_t vld4_s32 (const int32_t *)
9506 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9507 @end itemize
9508
9509
9510 @itemize @bullet
9511 @item int16x4x4_t vld4_s16 (const int16_t *)
9512 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9513 @end itemize
9514
9515
9516 @itemize @bullet
9517 @item int8x8x4_t vld4_s8 (const int8_t *)
9518 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9519 @end itemize
9520
9521
9522 @itemize @bullet
9523 @item float32x2x4_t vld4_f32 (const float32_t *)
9524 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9525 @end itemize
9526
9527
9528 @itemize @bullet
9529 @item poly16x4x4_t vld4_p16 (const poly16_t *)
9530 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9531 @end itemize
9532
9533
9534 @itemize @bullet
9535 @item poly8x8x4_t vld4_p8 (const poly8_t *)
9536 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9537 @end itemize
9538
9539
9540 @itemize @bullet
9541 @item poly64x1x4_t vld4_p64 (const poly64_t *)
9542 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9543 @end itemize
9544
9545
9546 @itemize @bullet
9547 @item uint64x1x4_t vld4_u64 (const uint64_t *)
9548 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9549 @end itemize
9550
9551
9552 @itemize @bullet
9553 @item int64x1x4_t vld4_s64 (const int64_t *)
9554 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9555 @end itemize
9556
9557
9558 @itemize @bullet
9559 @item uint32x4x4_t vld4q_u32 (const uint32_t *)
9560 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9561 @end itemize
9562
9563
9564 @itemize @bullet
9565 @item uint16x8x4_t vld4q_u16 (const uint16_t *)
9566 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9567 @end itemize
9568
9569
9570 @itemize @bullet
9571 @item uint8x16x4_t vld4q_u8 (const uint8_t *)
9572 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9573 @end itemize
9574
9575
9576 @itemize @bullet
9577 @item int32x4x4_t vld4q_s32 (const int32_t *)
9578 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9579 @end itemize
9580
9581
9582 @itemize @bullet
9583 @item int16x8x4_t vld4q_s16 (const int16_t *)
9584 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9585 @end itemize
9586
9587
9588 @itemize @bullet
9589 @item int8x16x4_t vld4q_s8 (const int8_t *)
9590 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9591 @end itemize
9592
9593
9594 @itemize @bullet
9595 @item float32x4x4_t vld4q_f32 (const float32_t *)
9596 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9597 @end itemize
9598
9599
9600 @itemize @bullet
9601 @item poly16x8x4_t vld4q_p16 (const poly16_t *)
9602 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9603 @end itemize
9604
9605
9606 @itemize @bullet
9607 @item poly8x16x4_t vld4q_p8 (const poly8_t *)
9608 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9609 @end itemize
9610
9611
9612 @itemize @bullet
9613 @item uint32x2x4_t vld4_lane_u32 (const uint32_t *, uint32x2x4_t, const int)
9614 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9615 @end itemize
9616
9617
9618 @itemize @bullet
9619 @item uint16x4x4_t vld4_lane_u16 (const uint16_t *, uint16x4x4_t, const int)
9620 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9621 @end itemize
9622
9623
9624 @itemize @bullet
9625 @item uint8x8x4_t vld4_lane_u8 (const uint8_t *, uint8x8x4_t, const int)
9626 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9627 @end itemize
9628
9629
9630 @itemize @bullet
9631 @item int32x2x4_t vld4_lane_s32 (const int32_t *, int32x2x4_t, const int)
9632 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9633 @end itemize
9634
9635
9636 @itemize @bullet
9637 @item int16x4x4_t vld4_lane_s16 (const int16_t *, int16x4x4_t, const int)
9638 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9639 @end itemize
9640
9641
9642 @itemize @bullet
9643 @item int8x8x4_t vld4_lane_s8 (const int8_t *, int8x8x4_t, const int)
9644 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9645 @end itemize
9646
9647
9648 @itemize @bullet
9649 @item float32x2x4_t vld4_lane_f32 (const float32_t *, float32x2x4_t, const int)
9650 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9651 @end itemize
9652
9653
9654 @itemize @bullet
9655 @item poly16x4x4_t vld4_lane_p16 (const poly16_t *, poly16x4x4_t, const int)
9656 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9657 @end itemize
9658
9659
9660 @itemize @bullet
9661 @item poly8x8x4_t vld4_lane_p8 (const poly8_t *, poly8x8x4_t, const int)
9662 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9663 @end itemize
9664
9665
9666 @itemize @bullet
9667 @item int32x4x4_t vld4q_lane_s32 (const int32_t *, int32x4x4_t, const int)
9668 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9669 @end itemize
9670
9671
9672 @itemize @bullet
9673 @item int16x8x4_t vld4q_lane_s16 (const int16_t *, int16x8x4_t, const int)
9674 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9675 @end itemize
9676
9677
9678 @itemize @bullet
9679 @item uint32x4x4_t vld4q_lane_u32 (const uint32_t *, uint32x4x4_t, const int)
9680 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9681 @end itemize
9682
9683
9684 @itemize @bullet
9685 @item uint16x8x4_t vld4q_lane_u16 (const uint16_t *, uint16x8x4_t, const int)
9686 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9687 @end itemize
9688
9689
9690 @itemize @bullet
9691 @item float32x4x4_t vld4q_lane_f32 (const float32_t *, float32x4x4_t, const int)
9692 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9693 @end itemize
9694
9695
9696 @itemize @bullet
9697 @item poly16x8x4_t vld4q_lane_p16 (const poly16_t *, poly16x8x4_t, const int)
9698 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9699 @end itemize
9700
9701
9702 @itemize @bullet
9703 @item uint32x2x4_t vld4_dup_u32 (const uint32_t *)
9704 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9705 @end itemize
9706
9707
9708 @itemize @bullet
9709 @item uint16x4x4_t vld4_dup_u16 (const uint16_t *)
9710 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9711 @end itemize
9712
9713
9714 @itemize @bullet
9715 @item uint8x8x4_t vld4_dup_u8 (const uint8_t *)
9716 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9717 @end itemize
9718
9719
9720 @itemize @bullet
9721 @item int32x2x4_t vld4_dup_s32 (const int32_t *)
9722 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9723 @end itemize
9724
9725
9726 @itemize @bullet
9727 @item int16x4x4_t vld4_dup_s16 (const int16_t *)
9728 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9729 @end itemize
9730
9731
9732 @itemize @bullet
9733 @item int8x8x4_t vld4_dup_s8 (const int8_t *)
9734 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9735 @end itemize
9736
9737
9738 @itemize @bullet
9739 @item float32x2x4_t vld4_dup_f32 (const float32_t *)
9740 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9741 @end itemize
9742
9743
9744 @itemize @bullet
9745 @item poly16x4x4_t vld4_dup_p16 (const poly16_t *)
9746 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9747 @end itemize
9748
9749
9750 @itemize @bullet
9751 @item poly8x8x4_t vld4_dup_p8 (const poly8_t *)
9752 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9753 @end itemize
9754
9755
9756 @itemize @bullet
9757 @item poly64x1x4_t vld4_dup_p64 (const poly64_t *)
9758 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9759 @end itemize
9760
9761
9762 @itemize @bullet
9763 @item uint64x1x4_t vld4_dup_u64 (const uint64_t *)
9764 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9765 @end itemize
9766
9767
9768 @itemize @bullet
9769 @item int64x1x4_t vld4_dup_s64 (const int64_t *)
9770 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9771 @end itemize
9772
9773
9774
9775
9776 @subsubsection Element/structure stores, VST4 variants
9777
9778 @itemize @bullet
9779 @item void vst4_u32 (uint32_t *, uint32x2x4_t)
9780 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9781 @end itemize
9782
9783
9784 @itemize @bullet
9785 @item void vst4_u16 (uint16_t *, uint16x4x4_t)
9786 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9787 @end itemize
9788
9789
9790 @itemize @bullet
9791 @item void vst4_u8 (uint8_t *, uint8x8x4_t)
9792 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9793 @end itemize
9794
9795
9796 @itemize @bullet
9797 @item void vst4_s32 (int32_t *, int32x2x4_t)
9798 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9799 @end itemize
9800
9801
9802 @itemize @bullet
9803 @item void vst4_s16 (int16_t *, int16x4x4_t)
9804 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9805 @end itemize
9806
9807
9808 @itemize @bullet
9809 @item void vst4_s8 (int8_t *, int8x8x4_t)
9810 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9811 @end itemize
9812
9813
9814 @itemize @bullet
9815 @item void vst4_f32 (float32_t *, float32x2x4_t)
9816 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9817 @end itemize
9818
9819
9820 @itemize @bullet
9821 @item void vst4_p16 (poly16_t *, poly16x4x4_t)
9822 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9823 @end itemize
9824
9825
9826 @itemize @bullet
9827 @item void vst4_p8 (poly8_t *, poly8x8x4_t)
9828 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9829 @end itemize
9830
9831
9832 @itemize @bullet
9833 @item void vst4_p64 (poly64_t *, poly64x1x4_t)
9834 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9835 @end itemize
9836
9837
9838 @itemize @bullet
9839 @item void vst4_u64 (uint64_t *, uint64x1x4_t)
9840 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9841 @end itemize
9842
9843
9844 @itemize @bullet
9845 @item void vst4_s64 (int64_t *, int64x1x4_t)
9846 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9847 @end itemize
9848
9849
9850 @itemize @bullet
9851 @item void vst4q_u32 (uint32_t *, uint32x4x4_t)
9852 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9853 @end itemize
9854
9855
9856 @itemize @bullet
9857 @item void vst4q_u16 (uint16_t *, uint16x8x4_t)
9858 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9859 @end itemize
9860
9861
9862 @itemize @bullet
9863 @item void vst4q_u8 (uint8_t *, uint8x16x4_t)
9864 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9865 @end itemize
9866
9867
9868 @itemize @bullet
9869 @item void vst4q_s32 (int32_t *, int32x4x4_t)
9870 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9871 @end itemize
9872
9873
9874 @itemize @bullet
9875 @item void vst4q_s16 (int16_t *, int16x8x4_t)
9876 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9877 @end itemize
9878
9879
9880 @itemize @bullet
9881 @item void vst4q_s8 (int8_t *, int8x16x4_t)
9882 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9883 @end itemize
9884
9885
9886 @itemize @bullet
9887 @item void vst4q_f32 (float32_t *, float32x4x4_t)
9888 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9889 @end itemize
9890
9891
9892 @itemize @bullet
9893 @item void vst4q_p16 (poly16_t *, poly16x8x4_t)
9894 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9895 @end itemize
9896
9897
9898 @itemize @bullet
9899 @item void vst4q_p8 (poly8_t *, poly8x16x4_t)
9900 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9901 @end itemize
9902
9903
9904 @itemize @bullet
9905 @item void vst4_lane_u32 (uint32_t *, uint32x2x4_t, const int)
9906 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9907 @end itemize
9908
9909
9910 @itemize @bullet
9911 @item void vst4_lane_u16 (uint16_t *, uint16x4x4_t, const int)
9912 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9913 @end itemize
9914
9915
9916 @itemize @bullet
9917 @item void vst4_lane_u8 (uint8_t *, uint8x8x4_t, const int)
9918 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9919 @end itemize
9920
9921
9922 @itemize @bullet
9923 @item void vst4_lane_s32 (int32_t *, int32x2x4_t, const int)
9924 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9925 @end itemize
9926
9927
9928 @itemize @bullet
9929 @item void vst4_lane_s16 (int16_t *, int16x4x4_t, const int)
9930 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9931 @end itemize
9932
9933
9934 @itemize @bullet
9935 @item void vst4_lane_s8 (int8_t *, int8x8x4_t, const int)
9936 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9937 @end itemize
9938
9939
9940 @itemize @bullet
9941 @item void vst4_lane_f32 (float32_t *, float32x2x4_t, const int)
9942 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9943 @end itemize
9944
9945
9946 @itemize @bullet
9947 @item void vst4_lane_p16 (poly16_t *, poly16x4x4_t, const int)
9948 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9949 @end itemize
9950
9951
9952 @itemize @bullet
9953 @item void vst4_lane_p8 (poly8_t *, poly8x8x4_t, const int)
9954 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9955 @end itemize
9956
9957
9958 @itemize @bullet
9959 @item void vst4q_lane_s32 (int32_t *, int32x4x4_t, const int)
9960 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9961 @end itemize
9962
9963
9964 @itemize @bullet
9965 @item void vst4q_lane_s16 (int16_t *, int16x8x4_t, const int)
9966 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9967 @end itemize
9968
9969
9970 @itemize @bullet
9971 @item void vst4q_lane_u32 (uint32_t *, uint32x4x4_t, const int)
9972 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9973 @end itemize
9974
9975
9976 @itemize @bullet
9977 @item void vst4q_lane_u16 (uint16_t *, uint16x8x4_t, const int)
9978 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9979 @end itemize
9980
9981
9982 @itemize @bullet
9983 @item void vst4q_lane_f32 (float32_t *, float32x4x4_t, const int)
9984 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9985 @end itemize
9986
9987
9988 @itemize @bullet
9989 @item void vst4q_lane_p16 (poly16_t *, poly16x8x4_t, const int)
9990 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9991 @end itemize
9992
9993
9994
9995
9996 @subsubsection Logical operations (AND)
9997
9998 @itemize @bullet
9999 @item uint32x2_t vand_u32 (uint32x2_t, uint32x2_t)
10000 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10001 @end itemize
10002
10003
10004 @itemize @bullet
10005 @item uint16x4_t vand_u16 (uint16x4_t, uint16x4_t)
10006 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10007 @end itemize
10008
10009
10010 @itemize @bullet
10011 @item uint8x8_t vand_u8 (uint8x8_t, uint8x8_t)
10012 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10013 @end itemize
10014
10015
10016 @itemize @bullet
10017 @item int32x2_t vand_s32 (int32x2_t, int32x2_t)
10018 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10019 @end itemize
10020
10021
10022 @itemize @bullet
10023 @item int16x4_t vand_s16 (int16x4_t, int16x4_t)
10024 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10025 @end itemize
10026
10027
10028 @itemize @bullet
10029 @item int8x8_t vand_s8 (int8x8_t, int8x8_t)
10030 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10031 @end itemize
10032
10033
10034 @itemize @bullet
10035 @item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t)
10036 @end itemize
10037
10038
10039 @itemize @bullet
10040 @item int64x1_t vand_s64 (int64x1_t, int64x1_t)
10041 @end itemize
10042
10043
10044 @itemize @bullet
10045 @item uint32x4_t vandq_u32 (uint32x4_t, uint32x4_t)
10046 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10047 @end itemize
10048
10049
10050 @itemize @bullet
10051 @item uint16x8_t vandq_u16 (uint16x8_t, uint16x8_t)
10052 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10053 @end itemize
10054
10055
10056 @itemize @bullet
10057 @item uint8x16_t vandq_u8 (uint8x16_t, uint8x16_t)
10058 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10059 @end itemize
10060
10061
10062 @itemize @bullet
10063 @item int32x4_t vandq_s32 (int32x4_t, int32x4_t)
10064 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10065 @end itemize
10066
10067
10068 @itemize @bullet
10069 @item int16x8_t vandq_s16 (int16x8_t, int16x8_t)
10070 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10071 @end itemize
10072
10073
10074 @itemize @bullet
10075 @item int8x16_t vandq_s8 (int8x16_t, int8x16_t)
10076 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10077 @end itemize
10078
10079
10080 @itemize @bullet
10081 @item uint64x2_t vandq_u64 (uint64x2_t, uint64x2_t)
10082 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10083 @end itemize
10084
10085
10086 @itemize @bullet
10087 @item int64x2_t vandq_s64 (int64x2_t, int64x2_t)
10088 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10089 @end itemize
10090
10091
10092
10093
10094 @subsubsection Logical operations (OR)
10095
10096 @itemize @bullet
10097 @item uint32x2_t vorr_u32 (uint32x2_t, uint32x2_t)
10098 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10099 @end itemize
10100
10101
10102 @itemize @bullet
10103 @item uint16x4_t vorr_u16 (uint16x4_t, uint16x4_t)
10104 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10105 @end itemize
10106
10107
10108 @itemize @bullet
10109 @item uint8x8_t vorr_u8 (uint8x8_t, uint8x8_t)
10110 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10111 @end itemize
10112
10113
10114 @itemize @bullet
10115 @item int32x2_t vorr_s32 (int32x2_t, int32x2_t)
10116 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10117 @end itemize
10118
10119
10120 @itemize @bullet
10121 @item int16x4_t vorr_s16 (int16x4_t, int16x4_t)
10122 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10123 @end itemize
10124
10125
10126 @itemize @bullet
10127 @item int8x8_t vorr_s8 (int8x8_t, int8x8_t)
10128 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10129 @end itemize
10130
10131
10132 @itemize @bullet
10133 @item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t)
10134 @end itemize
10135
10136
10137 @itemize @bullet
10138 @item int64x1_t vorr_s64 (int64x1_t, int64x1_t)
10139 @end itemize
10140
10141
10142 @itemize @bullet
10143 @item uint32x4_t vorrq_u32 (uint32x4_t, uint32x4_t)
10144 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10145 @end itemize
10146
10147
10148 @itemize @bullet
10149 @item uint16x8_t vorrq_u16 (uint16x8_t, uint16x8_t)
10150 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10151 @end itemize
10152
10153
10154 @itemize @bullet
10155 @item uint8x16_t vorrq_u8 (uint8x16_t, uint8x16_t)
10156 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10157 @end itemize
10158
10159
10160 @itemize @bullet
10161 @item int32x4_t vorrq_s32 (int32x4_t, int32x4_t)
10162 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10163 @end itemize
10164
10165
10166 @itemize @bullet
10167 @item int16x8_t vorrq_s16 (int16x8_t, int16x8_t)
10168 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10169 @end itemize
10170
10171
10172 @itemize @bullet
10173 @item int8x16_t vorrq_s8 (int8x16_t, int8x16_t)
10174 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10175 @end itemize
10176
10177
10178 @itemize @bullet
10179 @item uint64x2_t vorrq_u64 (uint64x2_t, uint64x2_t)
10180 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10181 @end itemize
10182
10183
10184 @itemize @bullet
10185 @item int64x2_t vorrq_s64 (int64x2_t, int64x2_t)
10186 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10187 @end itemize
10188
10189
10190
10191
10192 @subsubsection Logical operations (exclusive OR)
10193
10194 @itemize @bullet
10195 @item uint32x2_t veor_u32 (uint32x2_t, uint32x2_t)
10196 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10197 @end itemize
10198
10199
10200 @itemize @bullet
10201 @item uint16x4_t veor_u16 (uint16x4_t, uint16x4_t)
10202 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10203 @end itemize
10204
10205
10206 @itemize @bullet
10207 @item uint8x8_t veor_u8 (uint8x8_t, uint8x8_t)
10208 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10209 @end itemize
10210
10211
10212 @itemize @bullet
10213 @item int32x2_t veor_s32 (int32x2_t, int32x2_t)
10214 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10215 @end itemize
10216
10217
10218 @itemize @bullet
10219 @item int16x4_t veor_s16 (int16x4_t, int16x4_t)
10220 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10221 @end itemize
10222
10223
10224 @itemize @bullet
10225 @item int8x8_t veor_s8 (int8x8_t, int8x8_t)
10226 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10227 @end itemize
10228
10229
10230 @itemize @bullet
10231 @item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t)
10232 @end itemize
10233
10234
10235 @itemize @bullet
10236 @item int64x1_t veor_s64 (int64x1_t, int64x1_t)
10237 @end itemize
10238
10239
10240 @itemize @bullet
10241 @item uint32x4_t veorq_u32 (uint32x4_t, uint32x4_t)
10242 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10243 @end itemize
10244
10245
10246 @itemize @bullet
10247 @item uint16x8_t veorq_u16 (uint16x8_t, uint16x8_t)
10248 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10249 @end itemize
10250
10251
10252 @itemize @bullet
10253 @item uint8x16_t veorq_u8 (uint8x16_t, uint8x16_t)
10254 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10255 @end itemize
10256
10257
10258 @itemize @bullet
10259 @item int32x4_t veorq_s32 (int32x4_t, int32x4_t)
10260 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10261 @end itemize
10262
10263
10264 @itemize @bullet
10265 @item int16x8_t veorq_s16 (int16x8_t, int16x8_t)
10266 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10267 @end itemize
10268
10269
10270 @itemize @bullet
10271 @item int8x16_t veorq_s8 (int8x16_t, int8x16_t)
10272 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10273 @end itemize
10274
10275
10276 @itemize @bullet
10277 @item uint64x2_t veorq_u64 (uint64x2_t, uint64x2_t)
10278 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10279 @end itemize
10280
10281
10282 @itemize @bullet
10283 @item int64x2_t veorq_s64 (int64x2_t, int64x2_t)
10284 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10285 @end itemize
10286
10287
10288
10289
10290 @subsubsection Logical operations (AND-NOT)
10291
10292 @itemize @bullet
10293 @item uint32x2_t vbic_u32 (uint32x2_t, uint32x2_t)
10294 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10295 @end itemize
10296
10297
10298 @itemize @bullet
10299 @item uint16x4_t vbic_u16 (uint16x4_t, uint16x4_t)
10300 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10301 @end itemize
10302
10303
10304 @itemize @bullet
10305 @item uint8x8_t vbic_u8 (uint8x8_t, uint8x8_t)
10306 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10307 @end itemize
10308
10309
10310 @itemize @bullet
10311 @item int32x2_t vbic_s32 (int32x2_t, int32x2_t)
10312 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10313 @end itemize
10314
10315
10316 @itemize @bullet
10317 @item int16x4_t vbic_s16 (int16x4_t, int16x4_t)
10318 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10319 @end itemize
10320
10321
10322 @itemize @bullet
10323 @item int8x8_t vbic_s8 (int8x8_t, int8x8_t)
10324 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10325 @end itemize
10326
10327
10328 @itemize @bullet
10329 @item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t)
10330 @end itemize
10331
10332
10333 @itemize @bullet
10334 @item int64x1_t vbic_s64 (int64x1_t, int64x1_t)
10335 @end itemize
10336
10337
10338 @itemize @bullet
10339 @item uint32x4_t vbicq_u32 (uint32x4_t, uint32x4_t)
10340 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10341 @end itemize
10342
10343
10344 @itemize @bullet
10345 @item uint16x8_t vbicq_u16 (uint16x8_t, uint16x8_t)
10346 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10347 @end itemize
10348
10349
10350 @itemize @bullet
10351 @item uint8x16_t vbicq_u8 (uint8x16_t, uint8x16_t)
10352 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10353 @end itemize
10354
10355
10356 @itemize @bullet
10357 @item int32x4_t vbicq_s32 (int32x4_t, int32x4_t)
10358 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10359 @end itemize
10360
10361
10362 @itemize @bullet
10363 @item int16x8_t vbicq_s16 (int16x8_t, int16x8_t)
10364 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10365 @end itemize
10366
10367
10368 @itemize @bullet
10369 @item int8x16_t vbicq_s8 (int8x16_t, int8x16_t)
10370 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10371 @end itemize
10372
10373
10374 @itemize @bullet
10375 @item uint64x2_t vbicq_u64 (uint64x2_t, uint64x2_t)
10376 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10377 @end itemize
10378
10379
10380 @itemize @bullet
10381 @item int64x2_t vbicq_s64 (int64x2_t, int64x2_t)
10382 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10383 @end itemize
10384
10385
10386
10387
10388 @subsubsection Logical operations (OR-NOT)
10389
10390 @itemize @bullet
10391 @item uint32x2_t vorn_u32 (uint32x2_t, uint32x2_t)
10392 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10393 @end itemize
10394
10395
10396 @itemize @bullet
10397 @item uint16x4_t vorn_u16 (uint16x4_t, uint16x4_t)
10398 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10399 @end itemize
10400
10401
10402 @itemize @bullet
10403 @item uint8x8_t vorn_u8 (uint8x8_t, uint8x8_t)
10404 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10405 @end itemize
10406
10407
10408 @itemize @bullet
10409 @item int32x2_t vorn_s32 (int32x2_t, int32x2_t)
10410 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10411 @end itemize
10412
10413
10414 @itemize @bullet
10415 @item int16x4_t vorn_s16 (int16x4_t, int16x4_t)
10416 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10417 @end itemize
10418
10419
10420 @itemize @bullet
10421 @item int8x8_t vorn_s8 (int8x8_t, int8x8_t)
10422 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10423 @end itemize
10424
10425
10426 @itemize @bullet
10427 @item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t)
10428 @end itemize
10429
10430
10431 @itemize @bullet
10432 @item int64x1_t vorn_s64 (int64x1_t, int64x1_t)
10433 @end itemize
10434
10435
10436 @itemize @bullet
10437 @item uint32x4_t vornq_u32 (uint32x4_t, uint32x4_t)
10438 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10439 @end itemize
10440
10441
10442 @itemize @bullet
10443 @item uint16x8_t vornq_u16 (uint16x8_t, uint16x8_t)
10444 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10445 @end itemize
10446
10447
10448 @itemize @bullet
10449 @item uint8x16_t vornq_u8 (uint8x16_t, uint8x16_t)
10450 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10451 @end itemize
10452
10453
10454 @itemize @bullet
10455 @item int32x4_t vornq_s32 (int32x4_t, int32x4_t)
10456 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10457 @end itemize
10458
10459
10460 @itemize @bullet
10461 @item int16x8_t vornq_s16 (int16x8_t, int16x8_t)
10462 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10463 @end itemize
10464
10465
10466 @itemize @bullet
10467 @item int8x16_t vornq_s8 (int8x16_t, int8x16_t)
10468 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10469 @end itemize
10470
10471
10472 @itemize @bullet
10473 @item uint64x2_t vornq_u64 (uint64x2_t, uint64x2_t)
10474 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10475 @end itemize
10476
10477
10478 @itemize @bullet
10479 @item int64x2_t vornq_s64 (int64x2_t, int64x2_t)
10480 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10481 @end itemize
10482
10483
10484
10485
10486 @subsubsection Reinterpret casts
10487
10488 @itemize @bullet
10489 @item poly8x8_t vreinterpret_p8_p16 (poly16x4_t)
10490 @end itemize
10491
10492
10493 @itemize @bullet
10494 @item poly8x8_t vreinterpret_p8_f32 (float32x2_t)
10495 @end itemize
10496
10497
10498 @itemize @bullet
10499 @item poly8x8_t vreinterpret_p8_p64 (poly64x1_t)
10500 @end itemize
10501
10502
10503 @itemize @bullet
10504 @item poly8x8_t vreinterpret_p8_s64 (int64x1_t)
10505 @end itemize
10506
10507
10508 @itemize @bullet
10509 @item poly8x8_t vreinterpret_p8_u64 (uint64x1_t)
10510 @end itemize
10511
10512
10513 @itemize @bullet
10514 @item poly8x8_t vreinterpret_p8_s8 (int8x8_t)
10515 @end itemize
10516
10517
10518 @itemize @bullet
10519 @item poly8x8_t vreinterpret_p8_s16 (int16x4_t)
10520 @end itemize
10521
10522
10523 @itemize @bullet
10524 @item poly8x8_t vreinterpret_p8_s32 (int32x2_t)
10525 @end itemize
10526
10527
10528 @itemize @bullet
10529 @item poly8x8_t vreinterpret_p8_u8 (uint8x8_t)
10530 @end itemize
10531
10532
10533 @itemize @bullet
10534 @item poly8x8_t vreinterpret_p8_u16 (uint16x4_t)
10535 @end itemize
10536
10537
10538 @itemize @bullet
10539 @item poly8x8_t vreinterpret_p8_u32 (uint32x2_t)
10540 @end itemize
10541
10542
10543 @itemize @bullet
10544 @item poly16x4_t vreinterpret_p16_p8 (poly8x8_t)
10545 @end itemize
10546
10547
10548 @itemize @bullet
10549 @item poly16x4_t vreinterpret_p16_f32 (float32x2_t)
10550 @end itemize
10551
10552
10553 @itemize @bullet
10554 @item poly16x4_t vreinterpret_p16_p64 (poly64x1_t)
10555 @end itemize
10556
10557
10558 @itemize @bullet
10559 @item poly16x4_t vreinterpret_p16_s64 (int64x1_t)
10560 @end itemize
10561
10562
10563 @itemize @bullet
10564 @item poly16x4_t vreinterpret_p16_u64 (uint64x1_t)
10565 @end itemize
10566
10567
10568 @itemize @bullet
10569 @item poly16x4_t vreinterpret_p16_s8 (int8x8_t)
10570 @end itemize
10571
10572
10573 @itemize @bullet
10574 @item poly16x4_t vreinterpret_p16_s16 (int16x4_t)
10575 @end itemize
10576
10577
10578 @itemize @bullet
10579 @item poly16x4_t vreinterpret_p16_s32 (int32x2_t)
10580 @end itemize
10581
10582
10583 @itemize @bullet
10584 @item poly16x4_t vreinterpret_p16_u8 (uint8x8_t)
10585 @end itemize
10586
10587
10588 @itemize @bullet
10589 @item poly16x4_t vreinterpret_p16_u16 (uint16x4_t)
10590 @end itemize
10591
10592
10593 @itemize @bullet
10594 @item poly16x4_t vreinterpret_p16_u32 (uint32x2_t)
10595 @end itemize
10596
10597
10598 @itemize @bullet
10599 @item float32x2_t vreinterpret_f32_p8 (poly8x8_t)
10600 @end itemize
10601
10602
10603 @itemize @bullet
10604 @item float32x2_t vreinterpret_f32_p16 (poly16x4_t)
10605 @end itemize
10606
10607
10608 @itemize @bullet
10609 @item float32x2_t vreinterpret_f32_p64 (poly64x1_t)
10610 @end itemize
10611
10612
10613 @itemize @bullet
10614 @item float32x2_t vreinterpret_f32_s64 (int64x1_t)
10615 @end itemize
10616
10617
10618 @itemize @bullet
10619 @item float32x2_t vreinterpret_f32_u64 (uint64x1_t)
10620 @end itemize
10621
10622
10623 @itemize @bullet
10624 @item float32x2_t vreinterpret_f32_s8 (int8x8_t)
10625 @end itemize
10626
10627
10628 @itemize @bullet
10629 @item float32x2_t vreinterpret_f32_s16 (int16x4_t)
10630 @end itemize
10631
10632
10633 @itemize @bullet
10634 @item float32x2_t vreinterpret_f32_s32 (int32x2_t)
10635 @end itemize
10636
10637
10638 @itemize @bullet
10639 @item float32x2_t vreinterpret_f32_u8 (uint8x8_t)
10640 @end itemize
10641
10642
10643 @itemize @bullet
10644 @item float32x2_t vreinterpret_f32_u16 (uint16x4_t)
10645 @end itemize
10646
10647
10648 @itemize @bullet
10649 @item float32x2_t vreinterpret_f32_u32 (uint32x2_t)
10650 @end itemize
10651
10652
10653 @itemize @bullet
10654 @item poly64x1_t vreinterpret_p64_p8 (poly8x8_t)
10655 @end itemize
10656
10657
10658 @itemize @bullet
10659 @item poly64x1_t vreinterpret_p64_p16 (poly16x4_t)
10660 @end itemize
10661
10662
10663 @itemize @bullet
10664 @item poly64x1_t vreinterpret_p64_f32 (float32x2_t)
10665 @end itemize
10666
10667
10668 @itemize @bullet
10669 @item poly64x1_t vreinterpret_p64_s64 (int64x1_t)
10670 @end itemize
10671
10672
10673 @itemize @bullet
10674 @item poly64x1_t vreinterpret_p64_u64 (uint64x1_t)
10675 @end itemize
10676
10677
10678 @itemize @bullet
10679 @item poly64x1_t vreinterpret_p64_s8 (int8x8_t)
10680 @end itemize
10681
10682
10683 @itemize @bullet
10684 @item poly64x1_t vreinterpret_p64_s16 (int16x4_t)
10685 @end itemize
10686
10687
10688 @itemize @bullet
10689 @item poly64x1_t vreinterpret_p64_s32 (int32x2_t)
10690 @end itemize
10691
10692
10693 @itemize @bullet
10694 @item poly64x1_t vreinterpret_p64_u8 (uint8x8_t)
10695 @end itemize
10696
10697
10698 @itemize @bullet
10699 @item poly64x1_t vreinterpret_p64_u16 (uint16x4_t)
10700 @end itemize
10701
10702
10703 @itemize @bullet
10704 @item poly64x1_t vreinterpret_p64_u32 (uint32x2_t)
10705 @end itemize
10706
10707
10708 @itemize @bullet
10709 @item int64x1_t vreinterpret_s64_p8 (poly8x8_t)
10710 @end itemize
10711
10712
10713 @itemize @bullet
10714 @item int64x1_t vreinterpret_s64_p16 (poly16x4_t)
10715 @end itemize
10716
10717
10718 @itemize @bullet
10719 @item int64x1_t vreinterpret_s64_f32 (float32x2_t)
10720 @end itemize
10721
10722
10723 @itemize @bullet
10724 @item int64x1_t vreinterpret_s64_p64 (poly64x1_t)
10725 @end itemize
10726
10727
10728 @itemize @bullet
10729 @item int64x1_t vreinterpret_s64_u64 (uint64x1_t)
10730 @end itemize
10731
10732
10733 @itemize @bullet
10734 @item int64x1_t vreinterpret_s64_s8 (int8x8_t)
10735 @end itemize
10736
10737
10738 @itemize @bullet
10739 @item int64x1_t vreinterpret_s64_s16 (int16x4_t)
10740 @end itemize
10741
10742
10743 @itemize @bullet
10744 @item int64x1_t vreinterpret_s64_s32 (int32x2_t)
10745 @end itemize
10746
10747
10748 @itemize @bullet
10749 @item int64x1_t vreinterpret_s64_u8 (uint8x8_t)
10750 @end itemize
10751
10752
10753 @itemize @bullet
10754 @item int64x1_t vreinterpret_s64_u16 (uint16x4_t)
10755 @end itemize
10756
10757
10758 @itemize @bullet
10759 @item int64x1_t vreinterpret_s64_u32 (uint32x2_t)
10760 @end itemize
10761
10762
10763 @itemize @bullet
10764 @item uint64x1_t vreinterpret_u64_p8 (poly8x8_t)
10765 @end itemize
10766
10767
10768 @itemize @bullet
10769 @item uint64x1_t vreinterpret_u64_p16 (poly16x4_t)
10770 @end itemize
10771
10772
10773 @itemize @bullet
10774 @item uint64x1_t vreinterpret_u64_f32 (float32x2_t)
10775 @end itemize
10776
10777
10778 @itemize @bullet
10779 @item uint64x1_t vreinterpret_u64_p64 (poly64x1_t)
10780 @end itemize
10781
10782
10783 @itemize @bullet
10784 @item uint64x1_t vreinterpret_u64_s64 (int64x1_t)
10785 @end itemize
10786
10787
10788 @itemize @bullet
10789 @item uint64x1_t vreinterpret_u64_s8 (int8x8_t)
10790 @end itemize
10791
10792
10793 @itemize @bullet
10794 @item uint64x1_t vreinterpret_u64_s16 (int16x4_t)
10795 @end itemize
10796
10797
10798 @itemize @bullet
10799 @item uint64x1_t vreinterpret_u64_s32 (int32x2_t)
10800 @end itemize
10801
10802
10803 @itemize @bullet
10804 @item uint64x1_t vreinterpret_u64_u8 (uint8x8_t)
10805 @end itemize
10806
10807
10808 @itemize @bullet
10809 @item uint64x1_t vreinterpret_u64_u16 (uint16x4_t)
10810 @end itemize
10811
10812
10813 @itemize @bullet
10814 @item uint64x1_t vreinterpret_u64_u32 (uint32x2_t)
10815 @end itemize
10816
10817
10818 @itemize @bullet
10819 @item int8x8_t vreinterpret_s8_p8 (poly8x8_t)
10820 @end itemize
10821
10822
10823 @itemize @bullet
10824 @item int8x8_t vreinterpret_s8_p16 (poly16x4_t)
10825 @end itemize
10826
10827
10828 @itemize @bullet
10829 @item int8x8_t vreinterpret_s8_f32 (float32x2_t)
10830 @end itemize
10831
10832
10833 @itemize @bullet
10834 @item int8x8_t vreinterpret_s8_p64 (poly64x1_t)
10835 @end itemize
10836
10837
10838 @itemize @bullet
10839 @item int8x8_t vreinterpret_s8_s64 (int64x1_t)
10840 @end itemize
10841
10842
10843 @itemize @bullet
10844 @item int8x8_t vreinterpret_s8_u64 (uint64x1_t)
10845 @end itemize
10846
10847
10848 @itemize @bullet
10849 @item int8x8_t vreinterpret_s8_s16 (int16x4_t)
10850 @end itemize
10851
10852
10853 @itemize @bullet
10854 @item int8x8_t vreinterpret_s8_s32 (int32x2_t)
10855 @end itemize
10856
10857
10858 @itemize @bullet
10859 @item int8x8_t vreinterpret_s8_u8 (uint8x8_t)
10860 @end itemize
10861
10862
10863 @itemize @bullet
10864 @item int8x8_t vreinterpret_s8_u16 (uint16x4_t)
10865 @end itemize
10866
10867
10868 @itemize @bullet
10869 @item int8x8_t vreinterpret_s8_u32 (uint32x2_t)
10870 @end itemize
10871
10872
10873 @itemize @bullet
10874 @item int16x4_t vreinterpret_s16_p8 (poly8x8_t)
10875 @end itemize
10876
10877
10878 @itemize @bullet
10879 @item int16x4_t vreinterpret_s16_p16 (poly16x4_t)
10880 @end itemize
10881
10882
10883 @itemize @bullet
10884 @item int16x4_t vreinterpret_s16_f32 (float32x2_t)
10885 @end itemize
10886
10887
10888 @itemize @bullet
10889 @item int16x4_t vreinterpret_s16_p64 (poly64x1_t)
10890 @end itemize
10891
10892
10893 @itemize @bullet
10894 @item int16x4_t vreinterpret_s16_s64 (int64x1_t)
10895 @end itemize
10896
10897
10898 @itemize @bullet
10899 @item int16x4_t vreinterpret_s16_u64 (uint64x1_t)
10900 @end itemize
10901
10902
10903 @itemize @bullet
10904 @item int16x4_t vreinterpret_s16_s8 (int8x8_t)
10905 @end itemize
10906
10907
10908 @itemize @bullet
10909 @item int16x4_t vreinterpret_s16_s32 (int32x2_t)
10910 @end itemize
10911
10912
10913 @itemize @bullet
10914 @item int16x4_t vreinterpret_s16_u8 (uint8x8_t)
10915 @end itemize
10916
10917
10918 @itemize @bullet
10919 @item int16x4_t vreinterpret_s16_u16 (uint16x4_t)
10920 @end itemize
10921
10922
10923 @itemize @bullet
10924 @item int16x4_t vreinterpret_s16_u32 (uint32x2_t)
10925 @end itemize
10926
10927
10928 @itemize @bullet
10929 @item int32x2_t vreinterpret_s32_p8 (poly8x8_t)
10930 @end itemize
10931
10932
10933 @itemize @bullet
10934 @item int32x2_t vreinterpret_s32_p16 (poly16x4_t)
10935 @end itemize
10936
10937
10938 @itemize @bullet
10939 @item int32x2_t vreinterpret_s32_f32 (float32x2_t)
10940 @end itemize
10941
10942
10943 @itemize @bullet
10944 @item int32x2_t vreinterpret_s32_p64 (poly64x1_t)
10945 @end itemize
10946
10947
10948 @itemize @bullet
10949 @item int32x2_t vreinterpret_s32_s64 (int64x1_t)
10950 @end itemize
10951
10952
10953 @itemize @bullet
10954 @item int32x2_t vreinterpret_s32_u64 (uint64x1_t)
10955 @end itemize
10956
10957
10958 @itemize @bullet
10959 @item int32x2_t vreinterpret_s32_s8 (int8x8_t)
10960 @end itemize
10961
10962
10963 @itemize @bullet
10964 @item int32x2_t vreinterpret_s32_s16 (int16x4_t)
10965 @end itemize
10966
10967
10968 @itemize @bullet
10969 @item int32x2_t vreinterpret_s32_u8 (uint8x8_t)
10970 @end itemize
10971
10972
10973 @itemize @bullet
10974 @item int32x2_t vreinterpret_s32_u16 (uint16x4_t)
10975 @end itemize
10976
10977
10978 @itemize @bullet
10979 @item int32x2_t vreinterpret_s32_u32 (uint32x2_t)
10980 @end itemize
10981
10982
10983 @itemize @bullet
10984 @item uint8x8_t vreinterpret_u8_p8 (poly8x8_t)
10985 @end itemize
10986
10987
10988 @itemize @bullet
10989 @item uint8x8_t vreinterpret_u8_p16 (poly16x4_t)
10990 @end itemize
10991
10992
10993 @itemize @bullet
10994 @item uint8x8_t vreinterpret_u8_f32 (float32x2_t)
10995 @end itemize
10996
10997
10998 @itemize @bullet
10999 @item uint8x8_t vreinterpret_u8_p64 (poly64x1_t)
11000 @end itemize
11001
11002
11003 @itemize @bullet
11004 @item uint8x8_t vreinterpret_u8_s64 (int64x1_t)
11005 @end itemize
11006
11007
11008 @itemize @bullet
11009 @item uint8x8_t vreinterpret_u8_u64 (uint64x1_t)
11010 @end itemize
11011
11012
11013 @itemize @bullet
11014 @item uint8x8_t vreinterpret_u8_s8 (int8x8_t)
11015 @end itemize
11016
11017
11018 @itemize @bullet
11019 @item uint8x8_t vreinterpret_u8_s16 (int16x4_t)
11020 @end itemize
11021
11022
11023 @itemize @bullet
11024 @item uint8x8_t vreinterpret_u8_s32 (int32x2_t)
11025 @end itemize
11026
11027
11028 @itemize @bullet
11029 @item uint8x8_t vreinterpret_u8_u16 (uint16x4_t)
11030 @end itemize
11031
11032
11033 @itemize @bullet
11034 @item uint8x8_t vreinterpret_u8_u32 (uint32x2_t)
11035 @end itemize
11036
11037
11038 @itemize @bullet
11039 @item uint16x4_t vreinterpret_u16_p8 (poly8x8_t)
11040 @end itemize
11041
11042
11043 @itemize @bullet
11044 @item uint16x4_t vreinterpret_u16_p16 (poly16x4_t)
11045 @end itemize
11046
11047
11048 @itemize @bullet
11049 @item uint16x4_t vreinterpret_u16_f32 (float32x2_t)
11050 @end itemize
11051
11052
11053 @itemize @bullet
11054 @item uint16x4_t vreinterpret_u16_p64 (poly64x1_t)
11055 @end itemize
11056
11057
11058 @itemize @bullet
11059 @item uint16x4_t vreinterpret_u16_s64 (int64x1_t)
11060 @end itemize
11061
11062
11063 @itemize @bullet
11064 @item uint16x4_t vreinterpret_u16_u64 (uint64x1_t)
11065 @end itemize
11066
11067
11068 @itemize @bullet
11069 @item uint16x4_t vreinterpret_u16_s8 (int8x8_t)
11070 @end itemize
11071
11072
11073 @itemize @bullet
11074 @item uint16x4_t vreinterpret_u16_s16 (int16x4_t)
11075 @end itemize
11076
11077
11078 @itemize @bullet
11079 @item uint16x4_t vreinterpret_u16_s32 (int32x2_t)
11080 @end itemize
11081
11082
11083 @itemize @bullet
11084 @item uint16x4_t vreinterpret_u16_u8 (uint8x8_t)
11085 @end itemize
11086
11087
11088 @itemize @bullet
11089 @item uint16x4_t vreinterpret_u16_u32 (uint32x2_t)
11090 @end itemize
11091
11092
11093 @itemize @bullet
11094 @item uint32x2_t vreinterpret_u32_p8 (poly8x8_t)
11095 @end itemize
11096
11097
11098 @itemize @bullet
11099 @item uint32x2_t vreinterpret_u32_p16 (poly16x4_t)
11100 @end itemize
11101
11102
11103 @itemize @bullet
11104 @item uint32x2_t vreinterpret_u32_f32 (float32x2_t)
11105 @end itemize
11106
11107
11108 @itemize @bullet
11109 @item uint32x2_t vreinterpret_u32_p64 (poly64x1_t)
11110 @end itemize
11111
11112
11113 @itemize @bullet
11114 @item uint32x2_t vreinterpret_u32_s64 (int64x1_t)
11115 @end itemize
11116
11117
11118 @itemize @bullet
11119 @item uint32x2_t vreinterpret_u32_u64 (uint64x1_t)
11120 @end itemize
11121
11122
11123 @itemize @bullet
11124 @item uint32x2_t vreinterpret_u32_s8 (int8x8_t)
11125 @end itemize
11126
11127
11128 @itemize @bullet
11129 @item uint32x2_t vreinterpret_u32_s16 (int16x4_t)
11130 @end itemize
11131
11132
11133 @itemize @bullet
11134 @item uint32x2_t vreinterpret_u32_s32 (int32x2_t)
11135 @end itemize
11136
11137
11138 @itemize @bullet
11139 @item uint32x2_t vreinterpret_u32_u8 (uint8x8_t)
11140 @end itemize
11141
11142
11143 @itemize @bullet
11144 @item uint32x2_t vreinterpret_u32_u16 (uint16x4_t)
11145 @end itemize
11146
11147
11148 @itemize @bullet
11149 @item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t)
11150 @end itemize
11151
11152
11153 @itemize @bullet
11154 @item poly8x16_t vreinterpretq_p8_f32 (float32x4_t)
11155 @end itemize
11156
11157
11158 @itemize @bullet
11159 @item poly8x16_t vreinterpretq_p8_p64 (poly64x2_t)
11160 @end itemize
11161
11162
11163 @itemize @bullet
11164 @item poly8x16_t vreinterpretq_p8_p128 (poly128_t)
11165 @end itemize
11166
11167
11168 @itemize @bullet
11169 @item poly8x16_t vreinterpretq_p8_s64 (int64x2_t)
11170 @end itemize
11171
11172
11173 @itemize @bullet
11174 @item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t)
11175 @end itemize
11176
11177
11178 @itemize @bullet
11179 @item poly8x16_t vreinterpretq_p8_s8 (int8x16_t)
11180 @end itemize
11181
11182
11183 @itemize @bullet
11184 @item poly8x16_t vreinterpretq_p8_s16 (int16x8_t)
11185 @end itemize
11186
11187
11188 @itemize @bullet
11189 @item poly8x16_t vreinterpretq_p8_s32 (int32x4_t)
11190 @end itemize
11191
11192
11193 @itemize @bullet
11194 @item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t)
11195 @end itemize
11196
11197
11198 @itemize @bullet
11199 @item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t)
11200 @end itemize
11201
11202
11203 @itemize @bullet
11204 @item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t)
11205 @end itemize
11206
11207
11208 @itemize @bullet
11209 @item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t)
11210 @end itemize
11211
11212
11213 @itemize @bullet
11214 @item poly16x8_t vreinterpretq_p16_f32 (float32x4_t)
11215 @end itemize
11216
11217
11218 @itemize @bullet
11219 @item poly16x8_t vreinterpretq_p16_p64 (poly64x2_t)
11220 @end itemize
11221
11222
11223 @itemize @bullet
11224 @item poly16x8_t vreinterpretq_p16_p128 (poly128_t)
11225 @end itemize
11226
11227
11228 @itemize @bullet
11229 @item poly16x8_t vreinterpretq_p16_s64 (int64x2_t)
11230 @end itemize
11231
11232
11233 @itemize @bullet
11234 @item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t)
11235 @end itemize
11236
11237
11238 @itemize @bullet
11239 @item poly16x8_t vreinterpretq_p16_s8 (int8x16_t)
11240 @end itemize
11241
11242
11243 @itemize @bullet
11244 @item poly16x8_t vreinterpretq_p16_s16 (int16x8_t)
11245 @end itemize
11246
11247
11248 @itemize @bullet
11249 @item poly16x8_t vreinterpretq_p16_s32 (int32x4_t)
11250 @end itemize
11251
11252
11253 @itemize @bullet
11254 @item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t)
11255 @end itemize
11256
11257
11258 @itemize @bullet
11259 @item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t)
11260 @end itemize
11261
11262
11263 @itemize @bullet
11264 @item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t)
11265 @end itemize
11266
11267
11268 @itemize @bullet
11269 @item float32x4_t vreinterpretq_f32_p8 (poly8x16_t)
11270 @end itemize
11271
11272
11273 @itemize @bullet
11274 @item float32x4_t vreinterpretq_f32_p16 (poly16x8_t)
11275 @end itemize
11276
11277
11278 @itemize @bullet
11279 @item float32x4_t vreinterpretq_f32_p64 (poly64x2_t)
11280 @end itemize
11281
11282
11283 @itemize @bullet
11284 @item float32x4_t vreinterpretq_f32_p128 (poly128_t)
11285 @end itemize
11286
11287
11288 @itemize @bullet
11289 @item float32x4_t vreinterpretq_f32_s64 (int64x2_t)
11290 @end itemize
11291
11292
11293 @itemize @bullet
11294 @item float32x4_t vreinterpretq_f32_u64 (uint64x2_t)
11295 @end itemize
11296
11297
11298 @itemize @bullet
11299 @item float32x4_t vreinterpretq_f32_s8 (int8x16_t)
11300 @end itemize
11301
11302
11303 @itemize @bullet
11304 @item float32x4_t vreinterpretq_f32_s16 (int16x8_t)
11305 @end itemize
11306
11307
11308 @itemize @bullet
11309 @item float32x4_t vreinterpretq_f32_s32 (int32x4_t)
11310 @end itemize
11311
11312
11313 @itemize @bullet
11314 @item float32x4_t vreinterpretq_f32_u8 (uint8x16_t)
11315 @end itemize
11316
11317
11318 @itemize @bullet
11319 @item float32x4_t vreinterpretq_f32_u16 (uint16x8_t)
11320 @end itemize
11321
11322
11323 @itemize @bullet
11324 @item float32x4_t vreinterpretq_f32_u32 (uint32x4_t)
11325 @end itemize
11326
11327
11328 @itemize @bullet
11329 @item poly64x2_t vreinterpretq_p64_p8 (poly8x16_t)
11330 @end itemize
11331
11332
11333 @itemize @bullet
11334 @item poly64x2_t vreinterpretq_p64_p16 (poly16x8_t)
11335 @end itemize
11336
11337
11338 @itemize @bullet
11339 @item poly64x2_t vreinterpretq_p64_f32 (float32x4_t)
11340 @end itemize
11341
11342
11343 @itemize @bullet
11344 @item poly64x2_t vreinterpretq_p64_p128 (poly128_t)
11345 @end itemize
11346
11347
11348 @itemize @bullet
11349 @item poly64x2_t vreinterpretq_p64_s64 (int64x2_t)
11350 @end itemize
11351
11352
11353 @itemize @bullet
11354 @item poly64x2_t vreinterpretq_p64_u64 (uint64x2_t)
11355 @end itemize
11356
11357
11358 @itemize @bullet
11359 @item poly64x2_t vreinterpretq_p64_s8 (int8x16_t)
11360 @end itemize
11361
11362
11363 @itemize @bullet
11364 @item poly64x2_t vreinterpretq_p64_s16 (int16x8_t)
11365 @end itemize
11366
11367
11368 @itemize @bullet
11369 @item poly64x2_t vreinterpretq_p64_s32 (int32x4_t)
11370 @end itemize
11371
11372
11373 @itemize @bullet
11374 @item poly64x2_t vreinterpretq_p64_u8 (uint8x16_t)
11375 @end itemize
11376
11377
11378 @itemize @bullet
11379 @item poly64x2_t vreinterpretq_p64_u16 (uint16x8_t)
11380 @end itemize
11381
11382
11383 @itemize @bullet
11384 @item poly64x2_t vreinterpretq_p64_u32 (uint32x4_t)
11385 @end itemize
11386
11387
11388 @itemize @bullet
11389 @item poly128_t vreinterpretq_p128_p8 (poly8x16_t)
11390 @end itemize
11391
11392
11393 @itemize @bullet
11394 @item poly128_t vreinterpretq_p128_p16 (poly16x8_t)
11395 @end itemize
11396
11397
11398 @itemize @bullet
11399 @item poly128_t vreinterpretq_p128_f32 (float32x4_t)
11400 @end itemize
11401
11402
11403 @itemize @bullet
11404 @item poly128_t vreinterpretq_p128_p64 (poly64x2_t)
11405 @end itemize
11406
11407
11408 @itemize @bullet
11409 @item poly128_t vreinterpretq_p128_s64 (int64x2_t)
11410 @end itemize
11411
11412
11413 @itemize @bullet
11414 @item poly128_t vreinterpretq_p128_u64 (uint64x2_t)
11415 @end itemize
11416
11417
11418 @itemize @bullet
11419 @item poly128_t vreinterpretq_p128_s8 (int8x16_t)
11420 @end itemize
11421
11422
11423 @itemize @bullet
11424 @item poly128_t vreinterpretq_p128_s16 (int16x8_t)
11425 @end itemize
11426
11427
11428 @itemize @bullet
11429 @item poly128_t vreinterpretq_p128_s32 (int32x4_t)
11430 @end itemize
11431
11432
11433 @itemize @bullet
11434 @item poly128_t vreinterpretq_p128_u8 (uint8x16_t)
11435 @end itemize
11436
11437
11438 @itemize @bullet
11439 @item poly128_t vreinterpretq_p128_u16 (uint16x8_t)
11440 @end itemize
11441
11442
11443 @itemize @bullet
11444 @item poly128_t vreinterpretq_p128_u32 (uint32x4_t)
11445 @end itemize
11446
11447
11448 @itemize @bullet
11449 @item int64x2_t vreinterpretq_s64_p8 (poly8x16_t)
11450 @end itemize
11451
11452
11453 @itemize @bullet
11454 @item int64x2_t vreinterpretq_s64_p16 (poly16x8_t)
11455 @end itemize
11456
11457
11458 @itemize @bullet
11459 @item int64x2_t vreinterpretq_s64_f32 (float32x4_t)
11460 @end itemize
11461
11462
11463 @itemize @bullet
11464 @item int64x2_t vreinterpretq_s64_p64 (poly64x2_t)
11465 @end itemize
11466
11467
11468 @itemize @bullet
11469 @item int64x2_t vreinterpretq_s64_p128 (poly128_t)
11470 @end itemize
11471
11472
11473 @itemize @bullet
11474 @item int64x2_t vreinterpretq_s64_u64 (uint64x2_t)
11475 @end itemize
11476
11477
11478 @itemize @bullet
11479 @item int64x2_t vreinterpretq_s64_s8 (int8x16_t)
11480 @end itemize
11481
11482
11483 @itemize @bullet
11484 @item int64x2_t vreinterpretq_s64_s16 (int16x8_t)
11485 @end itemize
11486
11487
11488 @itemize @bullet
11489 @item int64x2_t vreinterpretq_s64_s32 (int32x4_t)
11490 @end itemize
11491
11492
11493 @itemize @bullet
11494 @item int64x2_t vreinterpretq_s64_u8 (uint8x16_t)
11495 @end itemize
11496
11497
11498 @itemize @bullet
11499 @item int64x2_t vreinterpretq_s64_u16 (uint16x8_t)
11500 @end itemize
11501
11502
11503 @itemize @bullet
11504 @item int64x2_t vreinterpretq_s64_u32 (uint32x4_t)
11505 @end itemize
11506
11507
11508 @itemize @bullet
11509 @item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t)
11510 @end itemize
11511
11512
11513 @itemize @bullet
11514 @item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t)
11515 @end itemize
11516
11517
11518 @itemize @bullet
11519 @item uint64x2_t vreinterpretq_u64_f32 (float32x4_t)
11520 @end itemize
11521
11522
11523 @itemize @bullet
11524 @item uint64x2_t vreinterpretq_u64_p64 (poly64x2_t)
11525 @end itemize
11526
11527
11528 @itemize @bullet
11529 @item uint64x2_t vreinterpretq_u64_p128 (poly128_t)
11530 @end itemize
11531
11532
11533 @itemize @bullet
11534 @item uint64x2_t vreinterpretq_u64_s64 (int64x2_t)
11535 @end itemize
11536
11537
11538 @itemize @bullet
11539 @item uint64x2_t vreinterpretq_u64_s8 (int8x16_t)
11540 @end itemize
11541
11542
11543 @itemize @bullet
11544 @item uint64x2_t vreinterpretq_u64_s16 (int16x8_t)
11545 @end itemize
11546
11547
11548 @itemize @bullet
11549 @item uint64x2_t vreinterpretq_u64_s32 (int32x4_t)
11550 @end itemize
11551
11552
11553 @itemize @bullet
11554 @item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t)
11555 @end itemize
11556
11557
11558 @itemize @bullet
11559 @item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t)
11560 @end itemize
11561
11562
11563 @itemize @bullet
11564 @item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t)
11565 @end itemize
11566
11567
11568 @itemize @bullet
11569 @item int8x16_t vreinterpretq_s8_p8 (poly8x16_t)
11570 @end itemize
11571
11572
11573 @itemize @bullet
11574 @item int8x16_t vreinterpretq_s8_p16 (poly16x8_t)
11575 @end itemize
11576
11577
11578 @itemize @bullet
11579 @item int8x16_t vreinterpretq_s8_f32 (float32x4_t)
11580 @end itemize
11581
11582
11583 @itemize @bullet
11584 @item int8x16_t vreinterpretq_s8_p64 (poly64x2_t)
11585 @end itemize
11586
11587
11588 @itemize @bullet
11589 @item int8x16_t vreinterpretq_s8_p128 (poly128_t)
11590 @end itemize
11591
11592
11593 @itemize @bullet
11594 @item int8x16_t vreinterpretq_s8_s64 (int64x2_t)
11595 @end itemize
11596
11597
11598 @itemize @bullet
11599 @item int8x16_t vreinterpretq_s8_u64 (uint64x2_t)
11600 @end itemize
11601
11602
11603 @itemize @bullet
11604 @item int8x16_t vreinterpretq_s8_s16 (int16x8_t)
11605 @end itemize
11606
11607
11608 @itemize @bullet
11609 @item int8x16_t vreinterpretq_s8_s32 (int32x4_t)
11610 @end itemize
11611
11612
11613 @itemize @bullet
11614 @item int8x16_t vreinterpretq_s8_u8 (uint8x16_t)
11615 @end itemize
11616
11617
11618 @itemize @bullet
11619 @item int8x16_t vreinterpretq_s8_u16 (uint16x8_t)
11620 @end itemize
11621
11622
11623 @itemize @bullet
11624 @item int8x16_t vreinterpretq_s8_u32 (uint32x4_t)
11625 @end itemize
11626
11627
11628 @itemize @bullet
11629 @item int16x8_t vreinterpretq_s16_p8 (poly8x16_t)
11630 @end itemize
11631
11632
11633 @itemize @bullet
11634 @item int16x8_t vreinterpretq_s16_p16 (poly16x8_t)
11635 @end itemize
11636
11637
11638 @itemize @bullet
11639 @item int16x8_t vreinterpretq_s16_f32 (float32x4_t)
11640 @end itemize
11641
11642
11643 @itemize @bullet
11644 @item int16x8_t vreinterpretq_s16_p64 (poly64x2_t)
11645 @end itemize
11646
11647
11648 @itemize @bullet
11649 @item int16x8_t vreinterpretq_s16_p128 (poly128_t)
11650 @end itemize
11651
11652
11653 @itemize @bullet
11654 @item int16x8_t vreinterpretq_s16_s64 (int64x2_t)
11655 @end itemize
11656
11657
11658 @itemize @bullet
11659 @item int16x8_t vreinterpretq_s16_u64 (uint64x2_t)
11660 @end itemize
11661
11662
11663 @itemize @bullet
11664 @item int16x8_t vreinterpretq_s16_s8 (int8x16_t)
11665 @end itemize
11666
11667
11668 @itemize @bullet
11669 @item int16x8_t vreinterpretq_s16_s32 (int32x4_t)
11670 @end itemize
11671
11672
11673 @itemize @bullet
11674 @item int16x8_t vreinterpretq_s16_u8 (uint8x16_t)
11675 @end itemize
11676
11677
11678 @itemize @bullet
11679 @item int16x8_t vreinterpretq_s16_u16 (uint16x8_t)
11680 @end itemize
11681
11682
11683 @itemize @bullet
11684 @item int16x8_t vreinterpretq_s16_u32 (uint32x4_t)
11685 @end itemize
11686
11687
11688 @itemize @bullet
11689 @item int32x4_t vreinterpretq_s32_p8 (poly8x16_t)
11690 @end itemize
11691
11692
11693 @itemize @bullet
11694 @item int32x4_t vreinterpretq_s32_p16 (poly16x8_t)
11695 @end itemize
11696
11697
11698 @itemize @bullet
11699 @item int32x4_t vreinterpretq_s32_f32 (float32x4_t)
11700 @end itemize
11701
11702
11703 @itemize @bullet
11704 @item int32x4_t vreinterpretq_s32_p64 (poly64x2_t)
11705 @end itemize
11706
11707
11708 @itemize @bullet
11709 @item int32x4_t vreinterpretq_s32_p128 (poly128_t)
11710 @end itemize
11711
11712
11713 @itemize @bullet
11714 @item int32x4_t vreinterpretq_s32_s64 (int64x2_t)
11715 @end itemize
11716
11717
11718 @itemize @bullet
11719 @item int32x4_t vreinterpretq_s32_u64 (uint64x2_t)
11720 @end itemize
11721
11722
11723 @itemize @bullet
11724 @item int32x4_t vreinterpretq_s32_s8 (int8x16_t)
11725 @end itemize
11726
11727
11728 @itemize @bullet
11729 @item int32x4_t vreinterpretq_s32_s16 (int16x8_t)
11730 @end itemize
11731
11732
11733 @itemize @bullet
11734 @item int32x4_t vreinterpretq_s32_u8 (uint8x16_t)
11735 @end itemize
11736
11737
11738 @itemize @bullet
11739 @item int32x4_t vreinterpretq_s32_u16 (uint16x8_t)
11740 @end itemize
11741
11742
11743 @itemize @bullet
11744 @item int32x4_t vreinterpretq_s32_u32 (uint32x4_t)
11745 @end itemize
11746
11747
11748 @itemize @bullet
11749 @item uint8x16_t vreinterpretq_u8_p8 (poly8x16_t)
11750 @end itemize
11751
11752
11753 @itemize @bullet
11754 @item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t)
11755 @end itemize
11756
11757
11758 @itemize @bullet
11759 @item uint8x16_t vreinterpretq_u8_f32 (float32x4_t)
11760 @end itemize
11761
11762
11763 @itemize @bullet
11764 @item uint8x16_t vreinterpretq_u8_p64 (poly64x2_t)
11765 @end itemize
11766
11767
11768 @itemize @bullet
11769 @item uint8x16_t vreinterpretq_u8_p128 (poly128_t)
11770 @end itemize
11771
11772
11773 @itemize @bullet
11774 @item uint8x16_t vreinterpretq_u8_s64 (int64x2_t)
11775 @end itemize
11776
11777
11778 @itemize @bullet
11779 @item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t)
11780 @end itemize
11781
11782
11783 @itemize @bullet
11784 @item uint8x16_t vreinterpretq_u8_s8 (int8x16_t)
11785 @end itemize
11786
11787
11788 @itemize @bullet
11789 @item uint8x16_t vreinterpretq_u8_s16 (int16x8_t)
11790 @end itemize
11791
11792
11793 @itemize @bullet
11794 @item uint8x16_t vreinterpretq_u8_s32 (int32x4_t)
11795 @end itemize
11796
11797
11798 @itemize @bullet
11799 @item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t)
11800 @end itemize
11801
11802
11803 @itemize @bullet
11804 @item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t)
11805 @end itemize
11806
11807
11808 @itemize @bullet
11809 @item uint16x8_t vreinterpretq_u16_p8 (poly8x16_t)
11810 @end itemize
11811
11812
11813 @itemize @bullet
11814 @item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t)
11815 @end itemize
11816
11817
11818 @itemize @bullet
11819 @item uint16x8_t vreinterpretq_u16_f32 (float32x4_t)
11820 @end itemize
11821
11822
11823 @itemize @bullet
11824 @item uint16x8_t vreinterpretq_u16_p64 (poly64x2_t)
11825 @end itemize
11826
11827
11828 @itemize @bullet
11829 @item uint16x8_t vreinterpretq_u16_p128 (poly128_t)
11830 @end itemize
11831
11832
11833 @itemize @bullet
11834 @item uint16x8_t vreinterpretq_u16_s64 (int64x2_t)
11835 @end itemize
11836
11837
11838 @itemize @bullet
11839 @item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t)
11840 @end itemize
11841
11842
11843 @itemize @bullet
11844 @item uint16x8_t vreinterpretq_u16_s8 (int8x16_t)
11845 @end itemize
11846
11847
11848 @itemize @bullet
11849 @item uint16x8_t vreinterpretq_u16_s16 (int16x8_t)
11850 @end itemize
11851
11852
11853 @itemize @bullet
11854 @item uint16x8_t vreinterpretq_u16_s32 (int32x4_t)
11855 @end itemize
11856
11857
11858 @itemize @bullet
11859 @item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t)
11860 @end itemize
11861
11862
11863 @itemize @bullet
11864 @item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t)
11865 @end itemize
11866
11867
11868 @itemize @bullet
11869 @item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t)
11870 @end itemize
11871
11872
11873 @itemize @bullet
11874 @item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t)
11875 @end itemize
11876
11877
11878 @itemize @bullet
11879 @item uint32x4_t vreinterpretq_u32_f32 (float32x4_t)
11880 @end itemize
11881
11882
11883 @itemize @bullet
11884 @item uint32x4_t vreinterpretq_u32_p64 (poly64x2_t)
11885 @end itemize
11886
11887
11888 @itemize @bullet
11889 @item uint32x4_t vreinterpretq_u32_p128 (poly128_t)
11890 @end itemize
11891
11892
11893 @itemize @bullet
11894 @item uint32x4_t vreinterpretq_u32_s64 (int64x2_t)
11895 @end itemize
11896
11897
11898 @itemize @bullet
11899 @item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t)
11900 @end itemize
11901
11902
11903 @itemize @bullet
11904 @item uint32x4_t vreinterpretq_u32_s8 (int8x16_t)
11905 @end itemize
11906
11907
11908 @itemize @bullet
11909 @item uint32x4_t vreinterpretq_u32_s16 (int16x8_t)
11910 @end itemize
11911
11912
11913 @itemize @bullet
11914 @item uint32x4_t vreinterpretq_u32_s32 (int32x4_t)
11915 @end itemize
11916
11917
11918 @itemize @bullet
11919 @item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t)
11920 @end itemize
11921
11922
11923 @itemize @bullet
11924 @item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t)
11925 @end itemize
11926
11927
11928
11929
11930
11931 @itemize @bullet
11932 @item poly128_t vldrq_p128(poly128_t const *)
11933 @end itemize
11934
11935 @itemize @bullet
11936 @item void vstrq_p128(poly128_t *, poly128_t)
11937 @end itemize
11938
11939 @itemize @bullet
11940 @item uint64x1_t vceq_p64 (poly64x1_t, poly64x1_t)
11941 @end itemize
11942
11943 @itemize @bullet
11944 @item uint64x1_t vtst_p64 (poly64x1_t, poly64x1_t)
11945 @end itemize
11946
11947 @itemize @bullet
11948 @item uint32_t vsha1h_u32 (uint32_t)
11949 @*@emph{Form of expected instruction(s):} @code{sha1h.32 @var{q0}, @var{q1}}
11950 @end itemize
11951
11952 @itemize @bullet
11953 @item uint32x4_t vsha1cq_u32 (uint32x4_t, uint32_t, uint32x4_t)
11954 @*@emph{Form of expected instruction(s):} @code{sha1c.32 @var{q0}, @var{q1}, @var{q2}}
11955 @end itemize
11956
11957 @itemize @bullet
11958 @item uint32x4_t vsha1pq_u32 (uint32x4_t, uint32_t, uint32x4_t)
11959 @*@emph{Form of expected instruction(s):} @code{sha1p.32 @var{q0}, @var{q1}, @var{q2}}
11960 @end itemize
11961
11962 @itemize @bullet
11963 @item uint32x4_t vsha1mq_u32 (uint32x4_t, uint32_t, uint32x4_t)
11964 @*@emph{Form of expected instruction(s):} @code{sha1m.32 @var{q0}, @var{q1}, @var{q2}}
11965 @end itemize
11966
11967 @itemize @bullet
11968 @item uint32x4_t vsha1su0q_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
11969 @*@emph{Form of expected instruction(s):} @code{sha1su0.32 @var{q0}, @var{q1}, @var{q2}}
11970 @end itemize
11971
11972 @itemize @bullet
11973 @item uint32x4_t vsha1su1q_u32 (uint32x4_t, uint32x4_t)
11974 @*@emph{Form of expected instruction(s):} @code{sha1su1.32 @var{q0}, @var{q1}, @var{q2}}
11975 @end itemize
11976
11977 @itemize @bullet
11978 @item uint32x4_t vsha256hq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
11979 @*@emph{Form of expected instruction(s):} @code{sha256h.32 @var{q0}, @var{q1}, @var{q2}}
11980 @end itemize
11981
11982 @itemize @bullet
11983 @item uint32x4_t vsha256h2q_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
11984 @*@emph{Form of expected instruction(s):} @code{sha256h2.32 @var{q0}, @var{q1}, @var{q2}}
11985 @end itemize
11986
11987 @itemize @bullet
11988 @item uint32x4_t vsha256su0q_u32 (uint32x4_t, uint32x4_t)
11989 @*@emph{Form of expected instruction(s):} @code{sha256su0.32 @var{q0}, @var{q1}}
11990 @end itemize
11991
11992 @itemize @bullet
11993 @item uint32x4_t vsha256su1q_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
11994 @*@emph{Form of expected instruction(s):} @code{sha256su1.32 @var{q0}, @var{q1}, @var{q2}}
11995 @end itemize
11996
11997 @itemize @bullet
11998 @item poly128_t vmull_p64 (poly64_t a, poly64_t b)
11999 @*@emph{Form of expected instruction(s):} @code{vmull.p64 @var{q0}, @var{d1}, @var{d2}}
12000 @end itemize
12001
12002 @itemize @bullet
12003 @item poly128_t vmull_high_p64 (poly64x2_t a, poly64x2_t b)
12004 @*@emph{Form of expected instruction(s):} @code{vmull.p64 @var{q0}, @var{d1}, @var{d2}}
12005 @end itemize
12006