gcc/config/stormy16/stormy16.c

   1 /* Xstormy16 target functions.
   2    Copyright (C) 1997-2014 Free Software Foundation, Inc.
   3    Contributed by Red Hat, Inc.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 #include "config.h"
  22 #include "system.h"
  23 #include "coretypes.h"
  24 #include "tm.h"
  25 #include "rtl.h"
  26 #include "regs.h"
  27 #include "hard-reg-set.h"
  28 #include "insn-config.h"
  29 #include "conditions.h"
  30 #include "insn-flags.h"
  31 #include "output.h"
  32 #include "insn-attr.h"
  33 #include "flags.h"
  34 #include "recog.h"
  35 #include "diagnostic-core.h"
  36 #include "obstack.h"
  37 #include "tree.h"
  38 #include "stringpool.h"
  39 #include "stor-layout.h"
  40 #include "varasm.h"
  41 #include "calls.h"
  42 #include "expr.h"
  43 #include "optabs.h"
  44 #include "except.h"
  45 #include "function.h"
  46 #include "target.h"
  47 #include "target-def.h"
  48 #include "tm_p.h"
  49 #include "langhooks.h"
  50 #include "pointer-set.h"
  51 #include "hash-table.h"
  52 #include "vec.h"
  53 #include "ggc.h"
  54 #include "basic-block.h"
  55 #include "tree-ssa-alias.h"
  56 #include "internal-fn.h"
  57 #include "gimple-fold.h"
  58 #include "tree-eh.h"
  59 #include "gimple-expr.h"
  60 #include "is-a.h"
  61 #include "gimple.h"
  62 #include "gimplify.h"
  63 #include "df.h"
  64 #include "reload.h"
  65 #include "builtins.h"
  66
  67 static rtx emit_addhi3_postreload (rtx, rtx, rtx);
  68 static void xstormy16_asm_out_constructor (rtx, int);
  69 static void xstormy16_asm_out_destructor (rtx, int);
  70 static void xstormy16_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
  71                                            HOST_WIDE_INT, tree);
  72
  73 static void xstormy16_init_builtins (void);
  74 static rtx xstormy16_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
  75 static bool xstormy16_rtx_costs (rtx, int, int, int, int *, bool);
  76 static int xstormy16_address_cost (rtx, enum machine_mode, addr_space_t, bool);
  77 static bool xstormy16_return_in_memory (const_tree, const_tree);
  78
  79 static GTY(()) section *bss100_section;
  80
  81 /* Compute a (partial) cost for rtx X.  Return true if the complete
  82    cost has been computed, and false if subexpressions should be
  83    scanned.  In either case, *TOTAL contains the cost result.  */
  84
  85 static bool
  86 xstormy16_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
  87                      int opno ATTRIBUTE_UNUSED, int *total,
  88                      bool speed ATTRIBUTE_UNUSED)
  89 {
  90   switch (code)
  91     {
  92     case CONST_INT:
  93       if (INTVAL (x) < 16 && INTVAL (x) >= 0)
  94         *total = COSTS_N_INSNS (1) / 2;
  95       else if (INTVAL (x) < 256 && INTVAL (x) >= 0)
  96         *total = COSTS_N_INSNS (1);
  97       else
  98         *total = COSTS_N_INSNS (2);
  99       return true;
 100
 101     case CONST_DOUBLE:
 102     case CONST:
 103     case SYMBOL_REF:
 104     case LABEL_REF:
 105       *total = COSTS_N_INSNS (2);
 106       return true;
 107
 108     case MULT:
 109       *total = COSTS_N_INSNS (35 + 6);
 110       return true;
 111     case DIV:
 112       *total = COSTS_N_INSNS (51 - 6);
 113       return true;
 114
 115     default:
 116       return false;
 117     }
 118 }
 119
 120 static int
 121 xstormy16_address_cost (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED,
 122                         addr_space_t as ATTRIBUTE_UNUSED,
 123                         bool speed ATTRIBUTE_UNUSED)
 124 {
 125   return (CONST_INT_P (x) ? 2
 126           : GET_CODE (x) == PLUS ? 7
 127           : 5);
 128 }
 129
 130 /* Worker function for TARGET_MEMORY_MOVE_COST.  */
 131
 132 static int
 133 xstormy16_memory_move_cost (enum machine_mode mode, reg_class_t rclass,
 134                             bool in)
 135 {
 136   return (5 + memory_move_secondary_cost (mode, rclass, in));
 137 }
 138
 139 /* Branches are handled as follows:
 140
 141    1. HImode compare-and-branches.  The machine supports these
 142       natively, so the appropriate pattern is emitted directly.
 143
 144    2. SImode EQ and NE.  These are emitted as pairs of HImode
 145       compare-and-branches.
 146
 147    3. SImode LT, GE, LTU and GEU.  These are emitted as a sequence
 148       of a SImode subtract followed by a branch (not a compare-and-branch),
 149       like this:
 150       sub
 151       sbc
 152       blt
 153
 154    4. SImode GT, LE, GTU, LEU.  These are emitted as a sequence like:
 155       sub
 156       sbc
 157       blt
 158       or
 159       bne.  */
 160
 161 /* Emit a branch of kind CODE to location LOC.  */
 162
 163 void
 164 xstormy16_emit_cbranch (enum rtx_code code, rtx op0, rtx op1, rtx loc)
 165 {
 166   rtx condition_rtx, loc_ref, branch, cy_clobber;
 167   rtvec vec;
 168   enum machine_mode mode;
 169
 170   mode = GET_MODE (op0);
 171   gcc_assert (mode == HImode || mode == SImode);
 172
 173   if (mode == SImode
 174       && (code == GT || code == LE || code == GTU || code == LEU))
 175     {
 176       int unsigned_p = (code == GTU || code == LEU);
 177       int gt_p = (code == GT || code == GTU);
 178       rtx lab = NULL_RTX;
 179
 180       if (gt_p)
 181         lab = gen_label_rtx ();
 182       xstormy16_emit_cbranch (unsigned_p ? LTU : LT, op0, op1, gt_p ? lab : loc);
 183       /* This should be generated as a comparison against the temporary
 184          created by the previous insn, but reload can't handle that.  */
 185       xstormy16_emit_cbranch (gt_p ? NE : EQ, op0, op1, loc);
 186       if (gt_p)
 187         emit_label (lab);
 188       return;
 189     }
 190   else if (mode == SImode
 191            && (code == NE || code == EQ)
 192            && op1 != const0_rtx)
 193     {
 194       rtx op0_word, op1_word;
 195       rtx lab = NULL_RTX;
 196       int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD;
 197       int i;
 198
 199       if (code == EQ)
 200         lab = gen_label_rtx ();
 201
 202       for (i = 0; i < num_words - 1; i++)
 203         {
 204           op0_word = simplify_gen_subreg (word_mode, op0, mode,
 205                                           i * UNITS_PER_WORD);
 206           op1_word = simplify_gen_subreg (word_mode, op1, mode,
 207                                           i * UNITS_PER_WORD);
 208           xstormy16_emit_cbranch (NE, op0_word, op1_word, code == EQ ? lab : loc);
 209         }
 210       op0_word = simplify_gen_subreg (word_mode, op0, mode,
 211                                       i * UNITS_PER_WORD);
 212       op1_word = simplify_gen_subreg (word_mode, op1, mode,
 213                                       i * UNITS_PER_WORD);
 214       xstormy16_emit_cbranch (code, op0_word, op1_word, loc);
 215
 216       if (code == EQ)
 217         emit_label (lab);
 218       return;
 219     }
 220
 221   /* We can't allow reload to try to generate any reload after a branch,
 222      so when some register must match we must make the temporary ourselves.  */
 223   if (mode != HImode)
 224     {
 225       rtx tmp;
 226       tmp = gen_reg_rtx (mode);
 227       emit_move_insn (tmp, op0);
 228       op0 = tmp;
 229     }
 230
 231   condition_rtx = gen_rtx_fmt_ee (code, mode, op0, op1);
 232   loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
 233   branch = gen_rtx_SET (VOIDmode, pc_rtx,
 234                         gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
 235                                               loc_ref, pc_rtx));
 236
 237   cy_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM));
 238
 239   if (mode == HImode)
 240     vec = gen_rtvec (2, branch, cy_clobber);
 241   else if (code == NE || code == EQ)
 242     vec = gen_rtvec (2, branch, gen_rtx_CLOBBER (VOIDmode, op0));
 243   else
 244     {
 245       rtx sub;
 246 #if 0
 247       sub = gen_rtx_SET (VOIDmode, op0, gen_rtx_MINUS (SImode, op0, op1));
 248 #else
 249       sub = gen_rtx_CLOBBER (SImode, op0);
 250 #endif
 251       vec = gen_rtvec (3, branch, sub, cy_clobber);
 252     }
 253
 254   emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
 255 }
 256
 257 /* Take a SImode conditional branch, one of GT/LE/GTU/LEU, and split
 258    the arithmetic operation.  Most of the work is done by
 259    xstormy16_expand_arith.  */
 260
 261 void
 262 xstormy16_split_cbranch (enum machine_mode mode, rtx label, rtx comparison,
 263                          rtx dest)
 264 {
 265   rtx op0 = XEXP (comparison, 0);
 266   rtx op1 = XEXP (comparison, 1);
 267   rtx seq, last_insn;
 268   rtx compare;
 269
 270   start_sequence ();
 271   xstormy16_expand_arith (mode, COMPARE, dest, op0, op1);
 272   seq = get_insns ();
 273   end_sequence ();
 274
 275   gcc_assert (INSN_P (seq));
 276
 277   last_insn = seq;
 278   while (NEXT_INSN (last_insn) != NULL_RTX)
 279     last_insn = NEXT_INSN (last_insn);
 280
 281   compare = SET_SRC (XVECEXP (PATTERN (last_insn), 0, 0));
 282   PUT_CODE (XEXP (compare, 0), GET_CODE (comparison));
 283   XEXP (compare, 1) = gen_rtx_LABEL_REF (VOIDmode, label);
 284   emit_insn (seq);
 285 }
 286
 287
 288 /* Return the string to output a conditional branch to LABEL, which is
 289    the operand number of the label.
 290
 291    OP is the conditional expression, or NULL for branch-always.
 292
 293    REVERSED is nonzero if we should reverse the sense of the comparison.
 294
 295    INSN is the insn.  */
 296
 297 char *
 298 xstormy16_output_cbranch_hi (rtx op, const char *label, int reversed, rtx insn)
 299 {
 300   static char string[64];
 301   int need_longbranch = (op != NULL_RTX
 302                          ? get_attr_length (insn) == 8
 303                          : get_attr_length (insn) == 4);
 304   int really_reversed = reversed ^ need_longbranch;
 305   const char *ccode;
 306   const char *templ;
 307   const char *operands;
 308   enum rtx_code code;
 309
 310   if (! op)
 311     {
 312       if (need_longbranch)
 313         ccode = "jmpf";
 314       else
 315         ccode = "br";
 316       sprintf (string, "%s %s", ccode, label);
 317       return string;
 318     }
 319
 320   code = GET_CODE (op);
 321
 322   if (! REG_P (XEXP (op, 0)))
 323     {
 324       code = swap_condition (code);
 325       operands = "%3,%2";
 326     }
 327   else
 328       operands = "%2,%3";
 329
 330   /* Work out which way this really branches.  */
 331   if (really_reversed)
 332     code = reverse_condition (code);
 333
 334   switch (code)
 335     {
 336     case EQ:   ccode = "z";   break;
 337     case NE:   ccode = "nz";  break;
 338     case GE:   ccode = "ge";  break;
 339     case LT:   ccode = "lt";  break;
 340     case GT:   ccode = "gt";  break;
 341     case LE:   ccode = "le";  break;
 342     case GEU:  ccode = "nc";  break;
 343     case LTU:  ccode = "c";   break;
 344     case GTU:  ccode = "hi";  break;
 345     case LEU:  ccode = "ls";  break;
 346
 347     default:
 348       gcc_unreachable ();
 349     }
 350
 351   if (need_longbranch)
 352     templ = "b%s %s,.+8 | jmpf %s";
 353   else
 354     templ = "b%s %s,%s";
 355   sprintf (string, templ, ccode, operands, label);
 356
 357   return string;
 358 }
 359
 360 /* Return the string to output a conditional branch to LABEL, which is
 361    the operand number of the label, but suitable for the tail of a
 362    SImode branch.
 363
 364    OP is the conditional expression (OP is never NULL_RTX).
 365
 366    REVERSED is nonzero if we should reverse the sense of the comparison.
 367
 368    INSN is the insn.  */
 369
 370 char *
 371 xstormy16_output_cbranch_si (rtx op, const char *label, int reversed, rtx insn)
 372 {
 373   static char string[64];
 374   int need_longbranch = get_attr_length (insn) >= 8;
 375   int really_reversed = reversed ^ need_longbranch;
 376   const char *ccode;
 377   const char *templ;
 378   char prevop[16];
 379   enum rtx_code code;
 380
 381   code = GET_CODE (op);
 382
 383   /* Work out which way this really branches.  */
 384   if (really_reversed)
 385     code = reverse_condition (code);
 386
 387   switch (code)
 388     {
 389     case EQ:   ccode = "z";   break;
 390     case NE:   ccode = "nz";  break;
 391     case GE:   ccode = "ge";  break;
 392     case LT:   ccode = "lt";  break;
 393     case GEU:  ccode = "nc";  break;
 394     case LTU:  ccode = "c";   break;
 395
 396       /* The missing codes above should never be generated.  */
 397     default:
 398       gcc_unreachable ();
 399     }
 400
 401   switch (code)
 402     {
 403     case EQ: case NE:
 404       {
 405         int regnum;
 406
 407         gcc_assert (REG_P (XEXP (op, 0)));
 408
 409         regnum = REGNO (XEXP (op, 0));
 410         sprintf (prevop, "or %s,%s", reg_names[regnum], reg_names[regnum+1]);
 411       }
 412       break;
 413
 414     case GE: case LT: case GEU: case LTU:
 415       strcpy (prevop, "sbc %2,%3");
 416       break;
 417
 418     default:
 419       gcc_unreachable ();
 420     }
 421
 422   if (need_longbranch)
 423     templ = "%s | b%s .+6 | jmpf %s";
 424   else
 425     templ = "%s | b%s %s";
 426   sprintf (string, templ, prevop, ccode, label);
 427
 428   return string;
 429 }
 430 \f
 431 /* Many machines have some registers that cannot be copied directly to or from
 432    memory or even from other types of registers.  An example is the `MQ'
 433    register, which on most machines, can only be copied to or from general
 434    registers, but not memory.  Some machines allow copying all registers to and
 435    from memory, but require a scratch register for stores to some memory
 436    locations (e.g., those with symbolic address on the RT, and those with
 437    certain symbolic address on the SPARC when compiling PIC).  In some cases,
 438    both an intermediate and a scratch register are required.
 439
 440    You should define these macros to indicate to the reload phase that it may
 441    need to allocate at least one register for a reload in addition to the
 442    register to contain the data.  Specifically, if copying X to a register
 443    RCLASS in MODE requires an intermediate register, you should define
 444    `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
 445    whose registers can be used as intermediate registers or scratch registers.
 446
 447    If copying a register RCLASS in MODE to X requires an intermediate or scratch
 448    register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
 449    largest register class required.  If the requirements for input and output
 450    reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
 451    instead of defining both macros identically.
 452
 453    The values returned by these macros are often `GENERAL_REGS'.  Return
 454    `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
 455    to or from a register of RCLASS in MODE without requiring a scratch register.
 456    Do not define this macro if it would always return `NO_REGS'.
 457
 458    If a scratch register is required (either with or without an intermediate
 459    register), you should define patterns for `reload_inM' or `reload_outM', as
 460    required..  These patterns, which will normally be implemented with a
 461    `define_expand', should be similar to the `movM' patterns, except that
 462    operand 2 is the scratch register.
 463
 464    Define constraints for the reload register and scratch register that contain
 465    a single register class.  If the original reload register (whose class is
 466    RCLASS) can meet the constraint given in the pattern, the value returned by
 467    these macros is used for the class of the scratch register.  Otherwise, two
 468    additional reload registers are required.  Their classes are obtained from
 469    the constraints in the insn pattern.
 470
 471    X might be a pseudo-register or a `subreg' of a pseudo-register, which could
 472    either be in a hard register or in memory.  Use `true_regnum' to find out;
 473    it will return -1 if the pseudo is in memory and the hard register number if
 474    it is in a register.
 475
 476    These macros should not be used in the case where a particular class of
 477    registers can only be copied to memory and not to another class of
 478    registers.  In that case, secondary reload registers are not needed and
 479    would not be helpful.  Instead, a stack location must be used to perform the
 480    copy and the `movM' pattern should use memory as an intermediate storage.
 481    This case often occurs between floating-point and general registers.  */
 482
 483 enum reg_class
 484 xstormy16_secondary_reload_class (enum reg_class rclass,
 485                                   enum machine_mode mode ATTRIBUTE_UNUSED,
 486                                   rtx x)
 487 {
 488   /* This chip has the interesting property that only the first eight
 489      registers can be moved to/from memory.  */
 490   if ((MEM_P (x)
 491        || ((GET_CODE (x) == SUBREG || REG_P (x))
 492            && (true_regnum (x) == -1
 493                || true_regnum (x) >= FIRST_PSEUDO_REGISTER)))
 494       && ! reg_class_subset_p (rclass, EIGHT_REGS))
 495     return EIGHT_REGS;
 496
 497   return NO_REGS;
 498 }
 499
 500 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS
 501    and TARGET_PREFERRED_OUTPUT_RELOAD_CLASS.  */
 502
 503 static reg_class_t
 504 xstormy16_preferred_reload_class (rtx x, reg_class_t rclass)
 505 {
 506   if (rclass == GENERAL_REGS && MEM_P (x))
 507     return EIGHT_REGS;
 508
 509   return rclass;
 510 }
 511
 512 /* Predicate for symbols and addresses that reflect special 8-bit
 513    addressing.  */
 514
 515 int
 516 xstormy16_below100_symbol (rtx x,
 517                            enum machine_mode mode ATTRIBUTE_UNUSED)
 518 {
 519   if (GET_CODE (x) == CONST)
 520     x = XEXP (x, 0);
 521   if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
 522     x = XEXP (x, 0);
 523
 524   if (GET_CODE (x) == SYMBOL_REF)
 525     return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_XSTORMY16_BELOW100) != 0;
 526
 527   if (CONST_INT_P (x))
 528     {
 529       HOST_WIDE_INT i = INTVAL (x);
 530
 531       if ((i >= 0x0000 && i <= 0x00ff)
 532           || (i >= 0x7f00 && i <= 0x7fff))
 533         return 1;
 534     }
 535   return 0;
 536 }
 537
 538 /* Likewise, but only for non-volatile MEMs, for patterns where the
 539    MEM will get split into smaller sized accesses.  */
 540
 541 int
 542 xstormy16_splittable_below100_operand (rtx x, enum machine_mode mode)
 543 {
 544   if (MEM_P (x) && MEM_VOLATILE_P (x))
 545     return 0;
 546   return xstormy16_below100_operand (x, mode);
 547 }
 548
 549 /* Expand an 8-bit IOR.  This either detects the one case we can
 550    actually do, or uses a 16-bit IOR.  */
 551
 552 void
 553 xstormy16_expand_iorqi3 (rtx *operands)
 554 {
 555   rtx in, out, outsub, val;
 556
 557   out = operands[0];
 558   in = operands[1];
 559   val = operands[2];
 560
 561   if (xstormy16_onebit_set_operand (val, QImode))
 562     {
 563       if (!xstormy16_below100_or_register (in, QImode))
 564         in = copy_to_mode_reg (QImode, in);
 565       if (!xstormy16_below100_or_register (out, QImode))
 566         out = gen_reg_rtx (QImode);
 567       emit_insn (gen_iorqi3_internal (out, in, val));
 568       if (out != operands[0])
 569         emit_move_insn (operands[0], out);
 570       return;
 571     }
 572
 573   if (! REG_P (in))
 574     in = copy_to_mode_reg (QImode, in);
 575
 576   if (! REG_P (val) && ! CONST_INT_P (val))
 577     val = copy_to_mode_reg (QImode, val);
 578
 579   if (! REG_P (out))
 580     out = gen_reg_rtx (QImode);
 581
 582   in = simplify_gen_subreg (HImode, in, QImode, 0);
 583   outsub = simplify_gen_subreg (HImode, out, QImode, 0);
 584
 585   if (! CONST_INT_P (val))
 586     val = simplify_gen_subreg (HImode, val, QImode, 0);
 587
 588   emit_insn (gen_iorhi3 (outsub, in, val));
 589
 590   if (out != operands[0])
 591     emit_move_insn (operands[0], out);
 592 }
 593
 594 /* Expand an 8-bit AND.  This either detects the one case we can
 595    actually do, or uses a 16-bit AND.  */
 596
 597 void
 598 xstormy16_expand_andqi3 (rtx *operands)
 599 {
 600   rtx in, out, outsub, val;
 601
 602   out = operands[0];
 603   in = operands[1];
 604   val = operands[2];
 605
 606   if (xstormy16_onebit_clr_operand (val, QImode))
 607     {
 608       if (!xstormy16_below100_or_register (in, QImode))
 609         in = copy_to_mode_reg (QImode, in);
 610       if (!xstormy16_below100_or_register (out, QImode))
 611         out = gen_reg_rtx (QImode);
 612       emit_insn (gen_andqi3_internal (out, in, val));
 613       if (out != operands[0])
 614         emit_move_insn (operands[0], out);
 615       return;
 616     }
 617
 618   if (! REG_P (in))
 619     in = copy_to_mode_reg (QImode, in);
 620
 621   if (! REG_P (val) && ! CONST_INT_P (val))
 622     val = copy_to_mode_reg (QImode, val);
 623
 624   if (! REG_P (out))
 625     out = gen_reg_rtx (QImode);
 626
 627   in = simplify_gen_subreg (HImode, in, QImode, 0);
 628   outsub = simplify_gen_subreg (HImode, out, QImode, 0);
 629
 630   if (! CONST_INT_P (val))
 631     val = simplify_gen_subreg (HImode, val, QImode, 0);
 632
 633   emit_insn (gen_andhi3 (outsub, in, val));
 634
 635   if (out != operands[0])
 636     emit_move_insn (operands[0], out);
 637 }
 638
 639 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET)                         \
 640   (CONST_INT_P (X)                                                      \
 641   && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 2048) < 4096)
 642
 643 #define LEGITIMATE_ADDRESS_CONST_INT_P(X, OFFSET)                        \
 644  (CONST_INT_P (X)                                                        \
 645   && INTVAL (X) + (OFFSET) >= 0                                          \
 646   && INTVAL (X) + (OFFSET) < 0x8000                                      \
 647   && (INTVAL (X) + (OFFSET) < 0x100 || INTVAL (X) + (OFFSET) >= 0x7F00))
 648
 649 bool
 650 xstormy16_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
 651                                 rtx x, bool strict)
 652 {
 653   if (LEGITIMATE_ADDRESS_CONST_INT_P (x, 0))
 654     return true;
 655
 656   if (GET_CODE (x) == PLUS
 657       && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 0))
 658     {
 659       x = XEXP (x, 0);
 660       /* PR 31232: Do not allow INT+INT as an address.  */
 661       if (CONST_INT_P (x))
 662         return false;
 663     }
 664
 665   if ((GET_CODE (x) == PRE_MODIFY && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
 666       || GET_CODE (x) == POST_INC
 667       || GET_CODE (x) == PRE_DEC)
 668     x = XEXP (x, 0);
 669
 670   if (REG_P (x)
 671       && REGNO_OK_FOR_BASE_P (REGNO (x))
 672       && (! strict || REGNO (x) < FIRST_PSEUDO_REGISTER))
 673     return true;
 674
 675   if (xstormy16_below100_symbol (x, mode))
 676     return true;
 677
 678   return false;
 679 }
 680
 681 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
 682
 683    On this chip, this is true if the address is valid with an offset
 684    of 0 but not of 6, because in that case it cannot be used as an
 685    address for DImode or DFmode, or if the address is a post-increment
 686    or pre-decrement address.  */
 687
 688 static bool
 689 xstormy16_mode_dependent_address_p (const_rtx x,
 690                                     addr_space_t as ATTRIBUTE_UNUSED)
 691 {
 692   if (LEGITIMATE_ADDRESS_CONST_INT_P (x, 0)
 693       && ! LEGITIMATE_ADDRESS_CONST_INT_P (x, 6))
 694     return true;
 695
 696   if (GET_CODE (x) == PLUS
 697       && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 0)
 698       && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 6))
 699     return true;
 700
 701   /* Auto-increment addresses are now treated generically in recog.c.  */
 702   return false;
 703 }
 704
 705 int
 706 short_memory_operand (rtx x, enum machine_mode mode)
 707 {
 708   if (! memory_operand (x, mode))
 709     return 0;
 710   return (GET_CODE (XEXP (x, 0)) != PLUS);
 711 }
 712
 713 /* Splitter for the 'move' patterns, for modes not directly implemented
 714    by hardware.  Emit insns to copy a value of mode MODE from SRC to
 715    DEST.
 716
 717    This function is only called when reload_completed.  */
 718
 719 void
 720 xstormy16_split_move (enum machine_mode mode, rtx dest, rtx src)
 721 {
 722   int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD;
 723   int direction, end, i;
 724   int src_modifies = 0;
 725   int dest_modifies = 0;
 726   int src_volatile = 0;
 727   int dest_volatile = 0;
 728   rtx mem_operand;
 729   rtx auto_inc_reg_rtx = NULL_RTX;
 730
 731   /* Check initial conditions.  */
 732   gcc_assert (reload_completed
 733               && mode != QImode && mode != HImode
 734               && nonimmediate_operand (dest, mode)
 735               && general_operand (src, mode));
 736
 737   /* This case is not supported below, and shouldn't be generated.  */
 738   gcc_assert (! MEM_P (dest) || ! MEM_P (src));
 739
 740   /* This case is very very bad after reload, so trap it now.  */
 741   gcc_assert (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
 742
 743   /* The general idea is to copy by words, offsetting the source and
 744      destination.  Normally the least-significant word will be copied
 745      first, but for pre-dec operations it's better to copy the
 746      most-significant word first.  Only one operand can be a pre-dec
 747      or post-inc operand.
 748
 749      It's also possible that the copy overlaps so that the direction
 750      must be reversed.  */
 751   direction = 1;
 752
 753   if (MEM_P (dest))
 754     {
 755       mem_operand = XEXP (dest, 0);
 756       dest_modifies = side_effects_p (mem_operand);
 757       if (auto_inc_p (mem_operand))
 758         auto_inc_reg_rtx = XEXP (mem_operand, 0);
 759       dest_volatile = MEM_VOLATILE_P (dest);
 760       if (dest_volatile)
 761         {
 762           dest = copy_rtx (dest);
 763           MEM_VOLATILE_P (dest) = 0;
 764         }
 765     }
 766   else if (MEM_P (src))
 767     {
 768       mem_operand = XEXP (src, 0);
 769       src_modifies = side_effects_p (mem_operand);
 770       if (auto_inc_p (mem_operand))
 771         auto_inc_reg_rtx = XEXP (mem_operand, 0);
 772       src_volatile = MEM_VOLATILE_P (src);
 773       if (src_volatile)
 774         {
 775           src = copy_rtx (src);
 776           MEM_VOLATILE_P (src) = 0;
 777         }
 778     }
 779   else
 780     mem_operand = NULL_RTX;
 781
 782   if (mem_operand == NULL_RTX)
 783     {
 784       if (REG_P (src)
 785           && REG_P (dest)
 786           && reg_overlap_mentioned_p (dest, src)
 787           && REGNO (dest) > REGNO (src))
 788         direction = -1;
 789     }
 790   else if (GET_CODE (mem_operand) == PRE_DEC
 791       || (GET_CODE (mem_operand) == PLUS
 792           && GET_CODE (XEXP (mem_operand, 0)) == PRE_DEC))
 793     direction = -1;
 794   else if (MEM_P (src) && reg_overlap_mentioned_p (dest, src))
 795     {
 796       int regno;
 797
 798       gcc_assert (REG_P (dest));
 799       regno = REGNO (dest);
 800
 801       gcc_assert (refers_to_regno_p (regno, regno + num_words,
 802                                      mem_operand, 0));
 803
 804       if (refers_to_regno_p (regno, regno + 1, mem_operand, 0))
 805         direction = -1;
 806       else if (refers_to_regno_p (regno + num_words - 1, regno + num_words,
 807                                   mem_operand, 0))
 808         direction = 1;
 809       else
 810         /* This means something like
 811            (set (reg:DI r0) (mem:DI (reg:HI r1)))
 812            which we'd need to support by doing the set of the second word
 813            last.  */
 814         gcc_unreachable ();
 815     }
 816
 817   end = direction < 0 ? -1 : num_words;
 818   for (i = direction < 0 ? num_words - 1 : 0; i != end; i += direction)
 819     {
 820       rtx w_src, w_dest, insn;
 821
 822       if (src_modifies)
 823         w_src = gen_rtx_MEM (word_mode, mem_operand);
 824       else
 825         w_src = simplify_gen_subreg (word_mode, src, mode, i * UNITS_PER_WORD);
 826       if (src_volatile)
 827         MEM_VOLATILE_P (w_src) = 1;
 828       if (dest_modifies)
 829         w_dest = gen_rtx_MEM (word_mode, mem_operand);
 830       else
 831         w_dest = simplify_gen_subreg (word_mode, dest, mode,
 832                                       i * UNITS_PER_WORD);
 833       if (dest_volatile)
 834         MEM_VOLATILE_P (w_dest) = 1;
 835
 836       /* The simplify_subreg calls must always be able to simplify.  */
 837       gcc_assert (GET_CODE (w_src) != SUBREG
 838                   && GET_CODE (w_dest) != SUBREG);
 839
 840       insn = emit_insn (gen_rtx_SET (VOIDmode, w_dest, w_src));
 841       if (auto_inc_reg_rtx)
 842         REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC,
 843                                             auto_inc_reg_rtx,
 844                                             REG_NOTES (insn));
 845     }
 846 }
 847
 848 /* Expander for the 'move' patterns.  Emit insns to copy a value of
 849    mode MODE from SRC to DEST.  */
 850
 851 void
 852 xstormy16_expand_move (enum machine_mode mode, rtx dest, rtx src)
 853 {
 854   if (MEM_P (dest) && (GET_CODE (XEXP (dest, 0)) == PRE_MODIFY))
 855     {
 856       rtx pmv      = XEXP (dest, 0);
 857       rtx dest_reg = XEXP (pmv, 0);
 858       rtx dest_mod = XEXP (pmv, 1);
 859       rtx set      = gen_rtx_SET (Pmode, dest_reg, dest_mod);
 860       rtx clobber  = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM));
 861
 862       dest = gen_rtx_MEM (mode, dest_reg);
 863       emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
 864     }
 865   else if (MEM_P (src) && (GET_CODE (XEXP (src, 0)) == PRE_MODIFY))
 866     {
 867       rtx pmv     = XEXP (src, 0);
 868       rtx src_reg = XEXP (pmv, 0);
 869       rtx src_mod = XEXP (pmv, 1);
 870       rtx set     = gen_rtx_SET (Pmode, src_reg, src_mod);
 871       rtx clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM));
 872
 873       src = gen_rtx_MEM (mode, src_reg);
 874       emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
 875     }
 876
 877   /* There are only limited immediate-to-memory move instructions.  */
 878   if (! reload_in_progress
 879       && ! reload_completed
 880       && MEM_P (dest)
 881       && (! CONST_INT_P (XEXP (dest, 0))
 882           || ! xstormy16_legitimate_address_p (mode, XEXP (dest, 0), 0))
 883       && ! xstormy16_below100_operand (dest, mode)
 884       && ! REG_P (src)
 885       && GET_CODE (src) != SUBREG)
 886     src = copy_to_mode_reg (mode, src);
 887
 888   /* Don't emit something we would immediately split.  */
 889   if (reload_completed
 890       && mode != HImode && mode != QImode)
 891     {
 892       xstormy16_split_move (mode, dest, src);
 893       return;
 894     }
 895
 896   emit_insn (gen_rtx_SET (VOIDmode, dest, src));
 897 }
 898 \f
 899 /* Stack Layout:
 900
 901    The stack is laid out as follows:
 902
 903 SP->
 904 FP->    Local variables
 905         Register save area (up to 4 words)
 906         Argument register save area for stdarg (NUM_ARGUMENT_REGISTERS words)
 907
 908 AP->    Return address (two words)
 909         9th procedure parameter word
 910         10th procedure parameter word
 911         ...
 912         last procedure parameter word
 913
 914   The frame pointer location is tuned to make it most likely that all
 915   parameters and local variables can be accessed using a load-indexed
 916   instruction.  */
 917
 918 /* A structure to describe the layout.  */
 919 struct xstormy16_stack_layout
 920 {
 921   /* Size of the topmost three items on the stack.  */
 922   int locals_size;
 923   int register_save_size;
 924   int stdarg_save_size;
 925   /* Sum of the above items.  */
 926   int frame_size;
 927   /* Various offsets.  */
 928   int first_local_minus_ap;
 929   int sp_minus_fp;
 930   int fp_minus_ap;
 931 };
 932
 933 /* Does REGNO need to be saved?  */
 934 #define REG_NEEDS_SAVE(REGNUM, IFUN)                                    \
 935   ((df_regs_ever_live_p (REGNUM) && ! call_used_regs[REGNUM])           \
 936    || (IFUN && ! fixed_regs[REGNUM] && call_used_regs[REGNUM]           \
 937        && (REGNUM != CARRY_REGNUM)                                      \
 938        && (df_regs_ever_live_p (REGNUM) || ! crtl->is_leaf)))
 939
 940 /* Compute the stack layout.  */
 941
 942 struct xstormy16_stack_layout
 943 xstormy16_compute_stack_layout (void)
 944 {
 945   struct xstormy16_stack_layout layout;
 946   int regno;
 947   const int ifun = xstormy16_interrupt_function_p ();
 948
 949   layout.locals_size = get_frame_size ();
 950
 951   layout.register_save_size = 0;
 952   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 953     if (REG_NEEDS_SAVE (regno, ifun))
 954       layout.register_save_size += UNITS_PER_WORD;
 955
 956   if (cfun->stdarg)
 957     layout.stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD;
 958   else
 959     layout.stdarg_save_size = 0;
 960
 961   layout.frame_size = (layout.locals_size
 962                        + layout.register_save_size
 963                        + layout.stdarg_save_size);
 964
 965   if (crtl->args.size <= 2048 && crtl->args.size != -1)
 966     {
 967       if (layout.frame_size - INCOMING_FRAME_SP_OFFSET
 968           + crtl->args.size <= 2048)
 969         layout.fp_minus_ap = layout.frame_size - INCOMING_FRAME_SP_OFFSET;
 970       else
 971         layout.fp_minus_ap = 2048 - crtl->args.size;
 972     }
 973   else
 974     layout.fp_minus_ap = (layout.stdarg_save_size
 975                           + layout.register_save_size
 976                           - INCOMING_FRAME_SP_OFFSET);
 977   layout.sp_minus_fp = (layout.frame_size - INCOMING_FRAME_SP_OFFSET
 978                         - layout.fp_minus_ap);
 979   layout.first_local_minus_ap = layout.sp_minus_fp - layout.locals_size;
 980   return layout;
 981 }
 982
 983 /* Worker function for TARGET_CAN_ELIMINATE.  */
 984
 985 static bool
 986 xstormy16_can_eliminate (const int from, const int to)
 987 {
 988   return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
 989           ? ! frame_pointer_needed
 990           : true);
 991 }
 992
 993 /* Determine how all the special registers get eliminated.  */
 994
 995 int
 996 xstormy16_initial_elimination_offset (int from, int to)
 997 {
 998   struct xstormy16_stack_layout layout;
 999   int result;
1000
1001   layout = xstormy16_compute_stack_layout ();
1002
1003   if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
1004     result = layout.sp_minus_fp - layout.locals_size;
1005   else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1006     result = - layout.locals_size;
1007   else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
1008     result = - layout.fp_minus_ap;
1009   else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1010     result = - (layout.sp_minus_fp + layout.fp_minus_ap);
1011   else
1012     gcc_unreachable ();
1013
1014   return result;
1015 }
1016
1017 static rtx
1018 emit_addhi3_postreload (rtx dest, rtx src0, rtx src1)
1019 {
1020   rtx set, clobber, insn;
1021
1022   set = gen_rtx_SET (VOIDmode, dest, gen_rtx_PLUS (HImode, src0, src1));
1023   clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM));
1024   insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
1025   return insn;
1026 }
1027
1028 /* Called after register allocation to add any instructions needed for
1029    the prologue.  Using a prologue insn is favored compared to putting
1030    all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro,
1031    since it allows the scheduler to intermix instructions with the
1032    saves of the caller saved registers.  In some cases, it might be
1033    necessary to emit a barrier instruction as the last insn to prevent
1034    such scheduling.
1035
1036    Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1037    so that the debug info generation code can handle them properly.  */
1038
1039 void
1040 xstormy16_expand_prologue (void)
1041 {
1042   struct xstormy16_stack_layout layout;
1043   int regno;
1044   rtx insn;
1045   rtx mem_push_rtx;
1046   const int ifun = xstormy16_interrupt_function_p ();
1047
1048   mem_push_rtx = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
1049   mem_push_rtx = gen_rtx_MEM (HImode, mem_push_rtx);
1050
1051   layout = xstormy16_compute_stack_layout ();
1052
1053   if (layout.locals_size >= 32768)
1054     error ("local variable memory requirements exceed capacity");
1055
1056   if (flag_stack_usage_info)
1057     current_function_static_stack_size = layout.frame_size;
1058
1059   /* Save the argument registers if necessary.  */
1060   if (layout.stdarg_save_size)
1061     for (regno = FIRST_ARGUMENT_REGISTER;
1062          regno < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS;
1063          regno++)
1064       {
1065         rtx dwarf;
1066         rtx reg = gen_rtx_REG (HImode, regno);
1067
1068         insn = emit_move_insn (mem_push_rtx, reg);
1069         RTX_FRAME_RELATED_P (insn) = 1;
1070
1071         dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2));
1072
1073         XVECEXP (dwarf, 0, 0) = gen_rtx_SET (VOIDmode,
1074                                              gen_rtx_MEM (Pmode, stack_pointer_rtx),
1075                                              reg);
1076         XVECEXP (dwarf, 0, 1) = gen_rtx_SET (Pmode, stack_pointer_rtx,
1077                                              plus_constant (Pmode,
1078                                                             stack_pointer_rtx,
1079                                                             GET_MODE_SIZE (Pmode)));
1080         add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
1081         RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 0)) = 1;
1082         RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 1)) = 1;
1083       }
1084
1085   /* Push each of the registers to save.  */
1086   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1087     if (REG_NEEDS_SAVE (regno, ifun))
1088       {
1089         rtx dwarf;
1090         rtx reg = gen_rtx_REG (HImode, regno);
1091
1092         insn = emit_move_insn (mem_push_rtx, reg);
1093         RTX_FRAME_RELATED_P (insn) = 1;
1094
1095         dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2));
1096
1097         XVECEXP (dwarf, 0, 0) = gen_rtx_SET (VOIDmode,
1098                                              gen_rtx_MEM (Pmode, stack_pointer_rtx),
1099                                              reg);
1100         XVECEXP (dwarf, 0, 1) = gen_rtx_SET (Pmode, stack_pointer_rtx,
1101                                              plus_constant (Pmode,
1102                                                             stack_pointer_rtx,
1103                                                             GET_MODE_SIZE (Pmode)));
1104         add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
1105         RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 0)) = 1;
1106         RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 1)) = 1;
1107       }
1108
1109   /* It's just possible that the SP here might be what we need for
1110      the new FP...  */
1111   if (frame_pointer_needed && layout.sp_minus_fp == layout.locals_size)
1112     {
1113       insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
1114       RTX_FRAME_RELATED_P (insn) = 1;
1115     }
1116
1117   /* Allocate space for local variables.  */
1118   if (layout.locals_size)
1119     {
1120       insn = emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx,
1121                                      GEN_INT (layout.locals_size));
1122       RTX_FRAME_RELATED_P (insn) = 1;
1123     }
1124
1125   /* Set up the frame pointer, if required.  */
1126   if (frame_pointer_needed && layout.sp_minus_fp != layout.locals_size)
1127     {
1128       insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
1129       RTX_FRAME_RELATED_P (insn) = 1;
1130
1131       if (layout.sp_minus_fp)
1132         {
1133           insn = emit_addhi3_postreload (hard_frame_pointer_rtx,
1134                                          hard_frame_pointer_rtx,
1135                                          GEN_INT (- layout.sp_minus_fp));
1136           RTX_FRAME_RELATED_P (insn) = 1;
1137         }
1138     }
1139 }
1140
1141 /* Do we need an epilogue at all?  */
1142
1143 int
1144 direct_return (void)
1145 {
1146   return (reload_completed
1147           && xstormy16_compute_stack_layout ().frame_size == 0
1148           && ! xstormy16_interrupt_function_p ());
1149 }
1150
1151 /* Called after register allocation to add any instructions needed for
1152    the epilogue.  Using an epilogue insn is favored compared to putting
1153    all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro,
1154    since it allows the scheduler to intermix instructions with the
1155    saves of the caller saved registers.  In some cases, it might be
1156    necessary to emit a barrier instruction as the last insn to prevent
1157    such scheduling.  */
1158
1159 void
1160 xstormy16_expand_epilogue (void)
1161 {
1162   struct xstormy16_stack_layout layout;
1163   rtx mem_pop_rtx;
1164   int regno;
1165   const int ifun = xstormy16_interrupt_function_p ();
1166
1167   mem_pop_rtx = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
1168   mem_pop_rtx = gen_rtx_MEM (HImode, mem_pop_rtx);
1169
1170   layout = xstormy16_compute_stack_layout ();
1171
1172   /* Pop the stack for the locals.  */
1173   if (layout.locals_size)
1174     {
1175       if (frame_pointer_needed && layout.sp_minus_fp == layout.locals_size)
1176         emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
1177       else
1178         emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx,
1179                                 GEN_INT (- layout.locals_size));
1180     }
1181
1182   /* Restore any call-saved registers.  */
1183   for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
1184     if (REG_NEEDS_SAVE (regno, ifun))
1185       emit_move_insn (gen_rtx_REG (HImode, regno), mem_pop_rtx);
1186
1187   /* Pop the stack for the stdarg save area.  */
1188   if (layout.stdarg_save_size)
1189     emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx,
1190                             GEN_INT (- layout.stdarg_save_size));
1191
1192   /* Return.  */
1193   if (ifun)
1194     emit_jump_insn (gen_return_internal_interrupt ());
1195   else
1196     emit_jump_insn (gen_return_internal ());
1197 }
1198
1199 int
1200 xstormy16_epilogue_uses (int regno)
1201 {
1202   if (reload_completed && call_used_regs[regno])
1203     {
1204       const int ifun = xstormy16_interrupt_function_p ();
1205       return REG_NEEDS_SAVE (regno, ifun);
1206     }
1207   return 0;
1208 }
1209
1210 void
1211 xstormy16_function_profiler (void)
1212 {
1213   sorry ("function_profiler support");
1214 }
1215 \f
1216 /* Update CUM to advance past an argument in the argument list.  The
1217    values MODE, TYPE and NAMED describe that argument.  Once this is
1218    done, the variable CUM is suitable for analyzing the *following*
1219    argument with `TARGET_FUNCTION_ARG', etc.
1220
1221    This function need not do anything if the argument in question was
1222    passed on the stack.  The compiler knows how to track the amount of
1223    stack space used for arguments without any special help.  However,
1224    it makes life easier for xstormy16_build_va_list if it does update
1225    the word count.  */
1226
1227 static void
1228 xstormy16_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
1229                                 const_tree type, bool named ATTRIBUTE_UNUSED)
1230 {
1231   CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1232
1233   /* If an argument would otherwise be passed partially in registers,
1234      and partially on the stack, the whole of it is passed on the
1235      stack.  */
1236   if (*cum < NUM_ARGUMENT_REGISTERS
1237       && *cum + XSTORMY16_WORD_SIZE (type, mode) > NUM_ARGUMENT_REGISTERS)
1238     *cum = NUM_ARGUMENT_REGISTERS;
1239
1240   *cum += XSTORMY16_WORD_SIZE (type, mode);
1241 }
1242
1243 static rtx
1244 xstormy16_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
1245                         const_tree type, bool named ATTRIBUTE_UNUSED)
1246 {
1247   CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1248
1249   if (mode == VOIDmode)
1250     return const0_rtx;
1251   if (targetm.calls.must_pass_in_stack (mode, type)
1252       || *cum + XSTORMY16_WORD_SIZE (type, mode) > NUM_ARGUMENT_REGISTERS)
1253     return NULL_RTX;
1254   return gen_rtx_REG (mode, *cum + FIRST_ARGUMENT_REGISTER);
1255 }
1256
1257 /* Build the va_list type.
1258
1259    For this chip, va_list is a record containing a counter and a pointer.
1260    The counter is of type 'int' and indicates how many bytes
1261    have been used to date.  The pointer indicates the stack position
1262    for arguments that have not been passed in registers.
1263    To keep the layout nice, the pointer is first in the structure.  */
1264
1265 static tree
1266 xstormy16_build_builtin_va_list (void)
1267 {
1268   tree f_1, f_2, record, type_decl;
1269
1270   record = (*lang_hooks.types.make_type) (RECORD_TYPE);
1271   type_decl = build_decl (BUILTINS_LOCATION,
1272                           TYPE_DECL, get_identifier ("__va_list_tag"), record);
1273
1274   f_1 = build_decl (BUILTINS_LOCATION,
1275                     FIELD_DECL, get_identifier ("base"),
1276                       ptr_type_node);
1277   f_2 = build_decl (BUILTINS_LOCATION,
1278                     FIELD_DECL, get_identifier ("count"),
1279                       unsigned_type_node);
1280
1281   DECL_FIELD_CONTEXT (f_1) = record;
1282   DECL_FIELD_CONTEXT (f_2) = record;
1283
1284   TYPE_STUB_DECL (record) = type_decl;
1285   TYPE_NAME (record) = type_decl;
1286   TYPE_FIELDS (record) = f_1;
1287   DECL_CHAIN (f_1) = f_2;
1288
1289   layout_type (record);
1290
1291   return record;
1292 }
1293
1294 /* Implement the stdarg/varargs va_start macro.  STDARG_P is nonzero if this
1295    is stdarg.h instead of varargs.h.  VALIST is the tree of the va_list
1296    variable to initialize.  NEXTARG is the machine independent notion of the
1297    'next' argument after the variable arguments.  */
1298
1299 static void
1300 xstormy16_expand_builtin_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
1301 {
1302   tree f_base, f_count;
1303   tree base, count;
1304   tree t,u;
1305
1306   if (xstormy16_interrupt_function_p ())
1307     error ("cannot use va_start in interrupt function");
1308
1309   f_base = TYPE_FIELDS (va_list_type_node);
1310   f_count = DECL_CHAIN (f_base);
1311
1312   base = build3 (COMPONENT_REF, TREE_TYPE (f_base), valist, f_base, NULL_TREE);
1313   count = build3 (COMPONENT_REF, TREE_TYPE (f_count), valist, f_count,
1314                   NULL_TREE);
1315
1316   t = make_tree (TREE_TYPE (base), virtual_incoming_args_rtx);
1317   u = build_int_cst (NULL_TREE, - INCOMING_FRAME_SP_OFFSET);
1318   u = fold_convert (TREE_TYPE (count), u);
1319   t = fold_build_pointer_plus (t, u);
1320   t = build2 (MODIFY_EXPR, TREE_TYPE (base), base, t);
1321   TREE_SIDE_EFFECTS (t) = 1;
1322   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1323
1324   t = build2 (MODIFY_EXPR, TREE_TYPE (count), count,
1325               build_int_cst (NULL_TREE,
1326                              crtl->args.info * UNITS_PER_WORD));
1327   TREE_SIDE_EFFECTS (t) = 1;
1328   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1329 }
1330
1331 /* Implement the stdarg/varargs va_arg macro.  VALIST is the variable
1332    of type va_list as a tree, TYPE is the type passed to va_arg.
1333    Note:  This algorithm is documented in stormy-abi.  */
1334
1335 static tree
1336 xstormy16_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
1337                                 gimple_seq *post_p ATTRIBUTE_UNUSED)
1338 {
1339   tree f_base, f_count;
1340   tree base, count;
1341   tree count_tmp, addr, t;
1342   tree lab_gotaddr, lab_fromstack;
1343   int size, size_of_reg_args, must_stack;
1344   tree size_tree;
1345
1346   f_base = TYPE_FIELDS (va_list_type_node);
1347   f_count = DECL_CHAIN (f_base);
1348
1349   base = build3 (COMPONENT_REF, TREE_TYPE (f_base), valist, f_base, NULL_TREE);
1350   count = build3 (COMPONENT_REF, TREE_TYPE (f_count), valist, f_count,
1351                   NULL_TREE);
1352
1353   must_stack = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
1354   size_tree = round_up (size_in_bytes (type), UNITS_PER_WORD);
1355   gimplify_expr (&size_tree, pre_p, NULL, is_gimple_val, fb_rvalue);
1356
1357   size_of_reg_args = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD;
1358
1359   count_tmp = get_initialized_tmp_var (count, pre_p, NULL);
1360   lab_gotaddr = create_artificial_label (UNKNOWN_LOCATION);
1361   lab_fromstack = create_artificial_label (UNKNOWN_LOCATION);
1362   addr = create_tmp_var (ptr_type_node, NULL);
1363
1364   if (!must_stack)
1365     {
1366       tree r;
1367
1368       t = fold_convert (TREE_TYPE (count), size_tree);
1369       t = build2 (PLUS_EXPR, TREE_TYPE (count), count_tmp, t);
1370       r = fold_convert (TREE_TYPE (count), size_int (size_of_reg_args));
1371       t = build2 (GT_EXPR, boolean_type_node, t, r);
1372       t = build3 (COND_EXPR, void_type_node, t,
1373                   build1 (GOTO_EXPR, void_type_node, lab_fromstack),
1374                   NULL_TREE);
1375       gimplify_and_add (t, pre_p);
1376
1377       t = fold_build_pointer_plus (base, count_tmp);
1378       gimplify_assign (addr, t, pre_p);
1379
1380       t = build1 (GOTO_EXPR, void_type_node, lab_gotaddr);
1381       gimplify_and_add (t, pre_p);
1382
1383       t = build1 (LABEL_EXPR, void_type_node, lab_fromstack);
1384       gimplify_and_add (t, pre_p);
1385     }
1386
1387   /* Arguments larger than a word might need to skip over some
1388      registers, since arguments are either passed entirely in
1389      registers or entirely on the stack.  */
1390   size = PUSH_ROUNDING (int_size_in_bytes (type));
1391   if (size > 2 || size < 0 || must_stack)
1392     {
1393       tree r, u;
1394
1395       r = size_int (NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD);
1396       u = build2 (MODIFY_EXPR, TREE_TYPE (count_tmp), count_tmp, r);
1397
1398       t = fold_convert (TREE_TYPE (count), r);
1399       t = build2 (GE_EXPR, boolean_type_node, count_tmp, t);
1400       t = build3 (COND_EXPR, void_type_node, t, NULL_TREE, u);
1401       gimplify_and_add (t, pre_p);
1402     }
1403
1404   t = size_int (NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD
1405                 + INCOMING_FRAME_SP_OFFSET);
1406   t = fold_convert (TREE_TYPE (count), t);
1407   t = build2 (MINUS_EXPR, TREE_TYPE (count), count_tmp, t);
1408   t = build2 (PLUS_EXPR, TREE_TYPE (count), t,
1409               fold_convert (TREE_TYPE (count), size_tree));
1410   t = fold_convert (TREE_TYPE (t), fold (t));
1411   t = fold_build1 (NEGATE_EXPR, TREE_TYPE (t), t);
1412   t = fold_build_pointer_plus (base, t);
1413   gimplify_assign (addr, t, pre_p);
1414
1415   t = build1 (LABEL_EXPR, void_type_node, lab_gotaddr);
1416   gimplify_and_add (t, pre_p);
1417
1418   t = fold_convert (TREE_TYPE (count), size_tree);
1419   t = build2 (PLUS_EXPR, TREE_TYPE (count), count_tmp, t);
1420   gimplify_assign (count, t, pre_p);
1421
1422   addr = fold_convert (build_pointer_type (type), addr);
1423   return build_va_arg_indirect_ref (addr);
1424 }
1425
1426 /* Worker function for TARGET_TRAMPOLINE_INIT.  */
1427
1428 static void
1429 xstormy16_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
1430 {
1431   rtx temp = gen_reg_rtx (HImode);
1432   rtx reg_fnaddr = gen_reg_rtx (HImode);
1433   rtx reg_addr, reg_addr_mem;
1434
1435   reg_addr = copy_to_reg (XEXP (m_tramp, 0));
1436   reg_addr_mem = adjust_automodify_address (m_tramp, HImode, reg_addr, 0);
1437
1438   emit_move_insn (temp, GEN_INT (0x3130 | STATIC_CHAIN_REGNUM));
1439   emit_move_insn (reg_addr_mem, temp);
1440   emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx));
1441   reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2);
1442
1443   emit_move_insn (temp, static_chain);
1444   emit_move_insn (reg_addr_mem, temp);
1445   emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx));
1446   reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2);
1447
1448   emit_move_insn (reg_fnaddr, XEXP (DECL_RTL (fndecl), 0));
1449   emit_move_insn (temp, reg_fnaddr);
1450   emit_insn (gen_andhi3 (temp, temp, GEN_INT (0xFF)));
1451   emit_insn (gen_iorhi3 (temp, temp, GEN_INT (0x0200)));
1452   emit_move_insn (reg_addr_mem, temp);
1453   emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx));
1454   reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2);
1455
1456   emit_insn (gen_lshrhi3 (reg_fnaddr, reg_fnaddr, GEN_INT (8)));
1457   emit_move_insn (reg_addr_mem, reg_fnaddr);
1458 }
1459
1460 /* Worker function for TARGET_FUNCTION_VALUE.  */
1461
1462 static rtx
1463 xstormy16_function_value (const_tree valtype,
1464                           const_tree func ATTRIBUTE_UNUSED,
1465                           bool outgoing ATTRIBUTE_UNUSED)
1466 {
1467   enum machine_mode mode;
1468   mode = TYPE_MODE (valtype);
1469   PROMOTE_MODE (mode, 0, valtype);
1470   return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
1471 }
1472
1473 /* Worker function for TARGET_LIBCALL_VALUE.  */
1474
1475 static rtx
1476 xstormy16_libcall_value (enum machine_mode mode,
1477                          const_rtx fun ATTRIBUTE_UNUSED)
1478 {
1479   return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
1480 }
1481
1482 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.  */
1483
1484 static bool
1485 xstormy16_function_value_regno_p (const unsigned int regno)
1486 {
1487   return (regno == RETURN_VALUE_REGNUM);
1488 }
1489
1490 /* A C compound statement that outputs the assembler code for a thunk function,
1491    used to implement C++ virtual function calls with multiple inheritance.  The
1492    thunk acts as a wrapper around a virtual function, adjusting the implicit
1493    object parameter before handing control off to the real function.
1494
1495    First, emit code to add the integer DELTA to the location that contains the
1496    incoming first argument.  Assume that this argument contains a pointer, and
1497    is the one used to pass the `this' pointer in C++.  This is the incoming
1498    argument *before* the function prologue, e.g. `%o0' on a sparc.  The
1499    addition must preserve the values of all other incoming arguments.
1500
1501    After the addition, emit code to jump to FUNCTION, which is a
1502    `FUNCTION_DECL'.  This is a direct pure jump, not a call, and does not touch
1503    the return address.  Hence returning from FUNCTION will return to whoever
1504    called the current `thunk'.
1505
1506    The effect must be as if @var{function} had been called directly
1507    with the adjusted first argument.  This macro is responsible for
1508    emitting all of the code for a thunk function;
1509    TARGET_ASM_FUNCTION_PROLOGUE and TARGET_ASM_FUNCTION_EPILOGUE are
1510    not invoked.
1511
1512    The THUNK_FNDECL is redundant.  (DELTA and FUNCTION have already been
1513    extracted from it.)  It might possibly be useful on some targets, but
1514    probably not.  */
1515
1516 static void
1517 xstormy16_asm_output_mi_thunk (FILE *file,
1518                                tree thunk_fndecl ATTRIBUTE_UNUSED,
1519                                HOST_WIDE_INT delta,
1520                                HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1521                                tree function)
1522 {
1523   int regnum = FIRST_ARGUMENT_REGISTER;
1524
1525   /* There might be a hidden first argument for a returned structure.  */
1526   if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
1527     regnum += 1;
1528
1529   fprintf (file, "\tadd %s,#0x%x\n", reg_names[regnum], (int) delta & 0xFFFF);
1530   fputs ("\tjmpf ", file);
1531   assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
1532   putc ('\n', file);
1533 }
1534
1535 /* The purpose of this function is to override the default behavior of
1536    BSS objects.  Normally, they go into .bss or .sbss via ".common"
1537    directives, but we need to override that and put them in
1538    .bss_below100.  We can't just use a section override (like we do
1539    for .data_below100), because that makes them initialized rather
1540    than uninitialized.  */
1541
1542 void
1543 xstormy16_asm_output_aligned_common (FILE *stream,
1544                                      tree decl,
1545                                      const char *name,
1546                                      int size,
1547                                      int align,
1548                                      int global)
1549 {
1550   rtx mem = decl == NULL_TREE ? NULL_RTX : DECL_RTL (decl);
1551   rtx symbol;
1552
1553   if (mem != NULL_RTX
1554       && MEM_P (mem)
1555       && GET_CODE (symbol = XEXP (mem, 0)) == SYMBOL_REF
1556       && SYMBOL_REF_FLAGS (symbol) & SYMBOL_FLAG_XSTORMY16_BELOW100)
1557     {
1558       const char *name2;
1559       int p2align = 0;
1560
1561       switch_to_section (bss100_section);
1562
1563       while (align > 8)
1564         {
1565           align /= 2;
1566           p2align ++;
1567         }
1568
1569       name2 = default_strip_name_encoding (name);
1570       if (global)
1571         fprintf (stream, "\t.globl\t%s\n", name2);
1572       if (p2align)
1573         fprintf (stream, "\t.p2align %d\n", p2align);
1574       fprintf (stream, "\t.type\t%s, @object\n", name2);
1575       fprintf (stream, "\t.size\t%s, %d\n", name2, size);
1576       fprintf (stream, "%s:\n\t.space\t%d\n", name2, size);
1577       return;
1578     }
1579
1580   if (!global)
1581     {
1582       fprintf (stream, "\t.local\t");
1583       assemble_name (stream, name);
1584       fprintf (stream, "\n");
1585     }
1586   fprintf (stream, "\t.comm\t");
1587   assemble_name (stream, name);
1588   fprintf (stream, ",%u,%u\n", size, align / BITS_PER_UNIT);
1589 }
1590
1591 /* Implement TARGET_ASM_INIT_SECTIONS.  */
1592
1593 static void
1594 xstormy16_asm_init_sections (void)
1595 {
1596   bss100_section
1597     = get_unnamed_section (SECTION_WRITE | SECTION_BSS,
1598                            output_section_asm_op,
1599                            "\t.section \".bss_below100\",\"aw\",@nobits");
1600 }
1601
1602 /* Mark symbols with the "below100" attribute so that we can use the
1603    special addressing modes for them.  */
1604
1605 static void
1606 xstormy16_encode_section_info (tree decl, rtx r, int first)
1607 {
1608   default_encode_section_info (decl, r, first);
1609
1610    if (TREE_CODE (decl) == VAR_DECL
1611       && (lookup_attribute ("below100", DECL_ATTRIBUTES (decl))
1612           || lookup_attribute ("BELOW100", DECL_ATTRIBUTES (decl))))
1613     {
1614       rtx symbol = XEXP (r, 0);
1615
1616       gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
1617       SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_XSTORMY16_BELOW100;
1618     }
1619 }
1620
1621 #undef  TARGET_ASM_CONSTRUCTOR
1622 #define TARGET_ASM_CONSTRUCTOR  xstormy16_asm_out_constructor
1623 #undef  TARGET_ASM_DESTRUCTOR
1624 #define TARGET_ASM_DESTRUCTOR   xstormy16_asm_out_destructor
1625
1626 /* Output constructors and destructors.  Just like
1627    default_named_section_asm_out_* but don't set the sections writable.  */
1628
1629 static void
1630 xstormy16_asm_out_destructor (rtx symbol, int priority)
1631 {
1632   const char *section = ".dtors";
1633   char buf[16];
1634
1635   /* ??? This only works reliably with the GNU linker.  */
1636   if (priority != DEFAULT_INIT_PRIORITY)
1637     {
1638       sprintf (buf, ".dtors.%.5u",
1639                /* Invert the numbering so the linker puts us in the proper
1640                   order; constructors are run from right to left, and the
1641                   linker sorts in increasing order.  */
1642                MAX_INIT_PRIORITY - priority);
1643       section = buf;
1644     }
1645
1646   switch_to_section (get_section (section, 0, NULL));
1647   assemble_align (POINTER_SIZE);
1648   assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
1649 }
1650
1651 static void
1652 xstormy16_asm_out_constructor (rtx symbol, int priority)
1653 {
1654   const char *section = ".ctors";
1655   char buf[16];
1656
1657   /* ??? This only works reliably with the GNU linker.  */
1658   if (priority != DEFAULT_INIT_PRIORITY)
1659     {
1660       sprintf (buf, ".ctors.%.5u",
1661                /* Invert the numbering so the linker puts us in the proper
1662                   order; constructors are run from right to left, and the
1663                   linker sorts in increasing order.  */
1664                MAX_INIT_PRIORITY - priority);
1665       section = buf;
1666     }
1667
1668   switch_to_section (get_section (section, 0, NULL));
1669   assemble_align (POINTER_SIZE);
1670   assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
1671 }
1672 \f
1673 /* Worker function for TARGET_PRINT_OPERAND_ADDRESS.
1674
1675    Print a memory address as an operand to reference that memory location.  */
1676
1677 static void
1678 xstormy16_print_operand_address (FILE *file, rtx address)
1679 {
1680   HOST_WIDE_INT offset;
1681   int pre_dec, post_inc;
1682
1683   /* There are a few easy cases.  */
1684   if (CONST_INT_P (address))
1685     {
1686       fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (address) & 0xFFFF);
1687       return;
1688     }
1689
1690   if (CONSTANT_P (address) || LABEL_P (address))
1691     {
1692       output_addr_const (file, address);
1693       return;
1694     }
1695
1696   /* Otherwise, it's hopefully something of the form
1697      (plus:HI (pre_dec:HI (reg:HI ...)) (const_int ...)).  */
1698   if (GET_CODE (address) == PLUS)
1699     {
1700       gcc_assert (CONST_INT_P (XEXP (address, 1)));
1701       offset = INTVAL (XEXP (address, 1));
1702       address = XEXP (address, 0);
1703     }
1704   else
1705     offset = 0;
1706
1707   pre_dec = (GET_CODE (address) == PRE_DEC);
1708   post_inc = (GET_CODE (address) == POST_INC);
1709   if (pre_dec || post_inc)
1710     address = XEXP (address, 0);
1711
1712   gcc_assert (REG_P (address));
1713
1714   fputc ('(', file);
1715   if (pre_dec)
1716     fputs ("--", file);
1717   fputs (reg_names [REGNO (address)], file);
1718   if (post_inc)
1719     fputs ("++", file);
1720   if (offset != 0)
1721     fprintf (file, "," HOST_WIDE_INT_PRINT_DEC, offset);
1722   fputc (')', file);
1723 }
1724
1725 /* Worker function for TARGET_PRINT_OPERAND.
1726
1727    Print an operand to an assembler instruction.  */
1728
1729 static void
1730 xstormy16_print_operand (FILE *file, rtx x, int code)
1731 {
1732   switch (code)
1733     {
1734     case 'B':
1735         /* There is either one bit set, or one bit clear, in X.
1736            Print it preceded by '#'.  */
1737       {
1738         static int bits_set[8] = { 0, 1, 1, 2, 1, 2, 2, 3 };
1739         HOST_WIDE_INT xx = 1;
1740         HOST_WIDE_INT l;
1741
1742         if (CONST_INT_P (x))
1743           xx = INTVAL (x);
1744         else
1745           output_operand_lossage ("'B' operand is not constant");
1746
1747         /* GCC sign-extends masks with the MSB set, so we have to
1748            detect all the cases that differ only in sign extension
1749            beyond the bits we care about.  Normally, the predicates
1750            and constraints ensure that we have the right values.  This
1751            works correctly for valid masks.  */
1752         if (bits_set[xx & 7] <= 1)
1753           {
1754             /* Remove sign extension bits.  */
1755             if ((~xx & ~(HOST_WIDE_INT)0xff) == 0)
1756               xx &= 0xff;
1757             else if ((~xx & ~(HOST_WIDE_INT)0xffff) == 0)
1758               xx &= 0xffff;
1759             l = exact_log2 (xx);
1760           }
1761         else
1762           {
1763             /* Add sign extension bits.  */
1764             if ((xx & ~(HOST_WIDE_INT)0xff) == 0)
1765               xx |= ~(HOST_WIDE_INT)0xff;
1766             else if ((xx & ~(HOST_WIDE_INT)0xffff) == 0)
1767               xx |= ~(HOST_WIDE_INT)0xffff;
1768             l = exact_log2 (~xx);
1769           }
1770
1771         if (l == -1)
1772           output_operand_lossage ("'B' operand has multiple bits set");
1773
1774         fprintf (file, IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC, l);
1775         return;
1776       }
1777
1778     case 'C':
1779       /* Print the symbol without a surrounding @fptr().  */
1780       if (GET_CODE (x) == SYMBOL_REF)
1781         assemble_name (file, XSTR (x, 0));
1782       else if (LABEL_P (x))
1783         output_asm_label (x);
1784       else
1785         xstormy16_print_operand_address (file, x);
1786       return;
1787
1788     case 'o':
1789     case 'O':
1790       /* Print the immediate operand less one, preceded by '#'.
1791          For 'O', negate it first.  */
1792       {
1793         HOST_WIDE_INT xx = 0;
1794
1795         if (CONST_INT_P (x))
1796           xx = INTVAL (x);
1797         else
1798           output_operand_lossage ("'o' operand is not constant");
1799
1800         if (code == 'O')
1801           xx = -xx;
1802
1803         fprintf (file, IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC, xx - 1);
1804         return;
1805       }
1806
1807     case 'b':
1808       /* Print the shift mask for bp/bn.  */
1809       {
1810         HOST_WIDE_INT xx = 1;
1811         HOST_WIDE_INT l;
1812
1813         if (CONST_INT_P (x))
1814           xx = INTVAL (x);
1815         else
1816           output_operand_lossage ("'B' operand is not constant");
1817
1818         l = 7 - xx;
1819
1820         fputs (IMMEDIATE_PREFIX, file);
1821         fprintf (file, HOST_WIDE_INT_PRINT_DEC, l);
1822         return;
1823       }
1824
1825     case 0:
1826       /* Handled below.  */
1827       break;
1828
1829     default:
1830       output_operand_lossage ("xstormy16_print_operand: unknown code");
1831       return;
1832     }
1833
1834   switch (GET_CODE (x))
1835     {
1836     case REG:
1837       fputs (reg_names [REGNO (x)], file);
1838       break;
1839
1840     case MEM:
1841       xstormy16_print_operand_address (file, XEXP (x, 0));
1842       break;
1843
1844     default:
1845       /* Some kind of constant or label; an immediate operand,
1846          so prefix it with '#' for the assembler.  */
1847       fputs (IMMEDIATE_PREFIX, file);
1848       output_addr_const (file, x);
1849       break;
1850     }
1851
1852   return;
1853 }
1854 \f
1855 /* Expander for the `casesi' pattern.
1856    INDEX is the index of the switch statement.
1857    LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding
1858      to the first table entry.
1859    RANGE is the number of table entries.
1860    TABLE is an ADDR_VEC that is the jump table.
1861    DEFAULT_LABEL is the address to branch to if INDEX is outside the
1862      range LOWER_BOUND to LOWER_BOUND + RANGE - 1.  */
1863
1864 void
1865 xstormy16_expand_casesi (rtx index, rtx lower_bound, rtx range,
1866                          rtx table, rtx default_label)
1867 {
1868   HOST_WIDE_INT range_i = INTVAL (range);
1869   rtx int_index;
1870
1871   /* This code uses 'br', so it can deal only with tables of size up to
1872      8192 entries.  */
1873   if (range_i >= 8192)
1874     sorry ("switch statement of size %lu entries too large",
1875            (unsigned long) range_i);
1876
1877   index = expand_binop (SImode, sub_optab, index, lower_bound, NULL_RTX, 0,
1878                         OPTAB_LIB_WIDEN);
1879   emit_cmp_and_jump_insns (index, range, GTU, NULL_RTX, SImode, 1,
1880                            default_label);
1881   int_index = gen_lowpart_common (HImode, index);
1882   emit_insn (gen_ashlhi3 (int_index, int_index, const2_rtx));
1883   emit_jump_insn (gen_tablejump_pcrel (int_index, table));
1884 }
1885
1886 /* Output an ADDR_VEC.  It is output as a sequence of 'jmpf'
1887    instructions, without label or alignment or any other special
1888    constructs.  We know that the previous instruction will be the
1889    `tablejump_pcrel' output above.
1890
1891    TODO: it might be nice to output 'br' instructions if they could
1892    all reach.  */
1893
1894 void
1895 xstormy16_output_addr_vec (FILE *file, rtx label ATTRIBUTE_UNUSED, rtx table)
1896 {
1897   int vlen, idx;
1898
1899   switch_to_section (current_function_section ());
1900
1901   vlen = XVECLEN (table, 0);
1902   for (idx = 0; idx < vlen; idx++)
1903     {
1904       fputs ("\tjmpf ", file);
1905       output_asm_label (XEXP (XVECEXP (table, 0, idx), 0));
1906       fputc ('\n', file);
1907     }
1908 }
1909 \f
1910 /* Expander for the `call' patterns.
1911    RETVAL is the RTL for the return register or NULL for void functions.
1912    DEST is the function to call, expressed as a MEM.
1913    COUNTER is ignored.  */
1914
1915 void
1916 xstormy16_expand_call (rtx retval, rtx dest, rtx counter)
1917 {
1918   rtx call, temp;
1919   enum machine_mode mode;
1920
1921   gcc_assert (MEM_P (dest));
1922   dest = XEXP (dest, 0);
1923
1924   if (! CONSTANT_P (dest) && ! REG_P (dest))
1925     dest = force_reg (Pmode, dest);
1926
1927   if (retval == NULL)
1928     mode = VOIDmode;
1929   else
1930     mode = GET_MODE (retval);
1931
1932   call = gen_rtx_CALL (mode, gen_rtx_MEM (FUNCTION_MODE, dest),
1933                        counter);
1934   if (retval)
1935     call = gen_rtx_SET (VOIDmode, retval, call);
1936
1937   if (! CONSTANT_P (dest))
1938     {
1939       temp = gen_reg_rtx (HImode);
1940       emit_move_insn (temp, const0_rtx);
1941     }
1942   else
1943     temp = const0_rtx;
1944
1945   call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call,
1946                                                 gen_rtx_USE (VOIDmode, temp)));
1947   emit_call_insn (call);
1948 }
1949 \f
1950 /* Expanders for multiword computational operations.  */
1951
1952 /* Expander for arithmetic operations; emit insns to compute
1953
1954    (set DEST (CODE:MODE SRC0 SRC1))
1955
1956    When CODE is COMPARE, a branch template is generated
1957    (this saves duplicating code in xstormy16_split_cbranch).  */
1958
1959 void
1960 xstormy16_expand_arith (enum machine_mode mode, enum rtx_code code,
1961                         rtx dest, rtx src0, rtx src1)
1962 {
1963   int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD;
1964   int i;
1965   int firstloop = 1;
1966
1967   if (code == NEG)
1968     emit_move_insn (src0, const0_rtx);
1969
1970   for (i = 0; i < num_words; i++)
1971     {
1972       rtx w_src0, w_src1, w_dest;
1973       rtx insn;
1974
1975       w_src0 = simplify_gen_subreg (word_mode, src0, mode,
1976                                     i * UNITS_PER_WORD);
1977       w_src1 = simplify_gen_subreg (word_mode, src1, mode, i * UNITS_PER_WORD);
1978       w_dest = simplify_gen_subreg (word_mode, dest, mode, i * UNITS_PER_WORD);
1979
1980       switch (code)
1981         {
1982         case PLUS:
1983           if (firstloop
1984               && CONST_INT_P (w_src1)
1985               && INTVAL (w_src1) == 0)
1986             continue;
1987
1988           if (firstloop)
1989             insn = gen_addchi4 (w_dest, w_src0, w_src1);
1990           else
1991             insn = gen_addchi5 (w_dest, w_src0, w_src1);
1992           break;
1993
1994         case NEG:
1995         case MINUS:
1996         case COMPARE:
1997           if (code == COMPARE && i == num_words - 1)
1998             {
1999               rtx branch, sub, clobber, sub_1;
2000
2001               sub_1 = gen_rtx_MINUS (HImode, w_src0,
2002                                      gen_rtx_ZERO_EXTEND (HImode, gen_rtx_REG (BImode, CARRY_REGNUM)));
2003               sub = gen_rtx_SET (VOIDmode, w_dest,
2004                                  gen_rtx_MINUS (HImode, sub_1, w_src1));
2005               clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM));
2006               branch = gen_rtx_SET (VOIDmode, pc_rtx,
2007                                     gen_rtx_IF_THEN_ELSE (VOIDmode,
2008                                                           gen_rtx_EQ (HImode,
2009                                                                       sub_1,
2010                                                                       w_src1),
2011                                                           pc_rtx,
2012                                                           pc_rtx));
2013               insn = gen_rtx_PARALLEL (VOIDmode,
2014                                        gen_rtvec (3, branch, sub, clobber));
2015             }
2016           else if (firstloop
2017                    && code != COMPARE
2018                    && CONST_INT_P (w_src1)
2019                    && INTVAL (w_src1) == 0)
2020             continue;
2021           else if (firstloop)
2022             insn = gen_subchi4 (w_dest, w_src0, w_src1);
2023           else
2024             insn = gen_subchi5 (w_dest, w_src0, w_src1);
2025           break;
2026
2027         case IOR:
2028         case XOR:
2029         case AND:
2030           if (CONST_INT_P (w_src1)
2031               && INTVAL (w_src1) == -(code == AND))
2032             continue;
2033
2034           insn = gen_rtx_SET (VOIDmode, w_dest, gen_rtx_fmt_ee (code, mode,
2035                                                                 w_src0, w_src1));
2036           break;
2037
2038         case NOT:
2039           insn = gen_rtx_SET (VOIDmode, w_dest, gen_rtx_NOT (mode, w_src0));
2040           break;
2041
2042         default:
2043           gcc_unreachable ();
2044         }
2045
2046       firstloop = 0;
2047       emit (insn);
2048     }
2049
2050   /* If we emit nothing, try_split() will think we failed.  So emit
2051      something that does nothing and can be optimized away.  */
2052   if (firstloop)
2053     emit (gen_nop ());
2054 }
2055
2056 /* The shift operations are split at output time for constant values;
2057    variable-width shifts get handed off to a library routine.
2058
2059    Generate an output string to do (set X (CODE:MODE X SIZE_R))
2060    SIZE_R will be a CONST_INT, X will be a hard register.  */
2061
2062 const char *
2063 xstormy16_output_shift (enum machine_mode mode, enum rtx_code code,
2064                         rtx x, rtx size_r, rtx temp)
2065 {
2066   HOST_WIDE_INT size;
2067   const char *r0, *r1, *rt;
2068   static char r[64];
2069
2070   gcc_assert (CONST_INT_P (size_r)
2071               && REG_P (x)
2072               && mode == SImode);
2073
2074   size = INTVAL (size_r) & (GET_MODE_BITSIZE (mode) - 1);
2075
2076   if (size == 0)
2077     return "";
2078
2079   r0 = reg_names [REGNO (x)];
2080   r1 = reg_names [REGNO (x) + 1];
2081
2082   /* For shifts of size 1, we can use the rotate instructions.  */
2083   if (size == 1)
2084     {
2085       switch (code)
2086         {
2087         case ASHIFT:
2088           sprintf (r, "shl %s,#1 | rlc %s,#1", r0, r1);
2089           break;
2090         case ASHIFTRT:
2091           sprintf (r, "asr %s,#1 | rrc %s,#1", r1, r0);
2092           break;
2093         case LSHIFTRT:
2094           sprintf (r, "shr %s,#1 | rrc %s,#1", r1, r0);
2095           break;
2096         default:
2097           gcc_unreachable ();
2098         }
2099       return r;
2100     }
2101
2102   /* For large shifts, there are easy special cases.  */
2103   if (size == 16)
2104     {
2105       switch (code)
2106         {
2107         case ASHIFT:
2108           sprintf (r, "mov %s,%s | mov %s,#0", r1, r0, r0);
2109           break;
2110         case ASHIFTRT:
2111           sprintf (r, "mov %s,%s | asr %s,#15", r0, r1, r1);
2112           break;
2113         case LSHIFTRT:
2114           sprintf (r, "mov %s,%s | mov %s,#0", r0, r1, r1);
2115           break;
2116         default:
2117           gcc_unreachable ();
2118         }
2119       return r;
2120     }
2121   if (size > 16)
2122     {
2123       switch (code)
2124         {
2125         case ASHIFT:
2126           sprintf (r, "mov %s,%s | mov %s,#0 | shl %s,#%d",
2127                    r1, r0, r0, r1, (int) size - 16);
2128           break;
2129         case ASHIFTRT:
2130           sprintf (r, "mov %s,%s | asr %s,#15 | asr %s,#%d",
2131                    r0, r1, r1, r0, (int) size - 16);
2132           break;
2133         case LSHIFTRT:
2134           sprintf (r, "mov %s,%s | mov %s,#0 | shr %s,#%d",
2135                    r0, r1, r1, r0, (int) size - 16);
2136           break;
2137         default:
2138           gcc_unreachable ();
2139         }
2140       return r;
2141     }
2142
2143   /* For the rest, we have to do more work.  In particular, we
2144      need a temporary.  */
2145   rt = reg_names [REGNO (temp)];
2146   switch (code)
2147     {
2148     case ASHIFT:
2149       sprintf (r,
2150                "mov %s,%s | shl %s,#%d | shl %s,#%d | shr %s,#%d | or %s,%s",
2151                rt, r0, r0, (int) size, r1, (int) size, rt, (int) (16 - size),
2152                r1, rt);
2153       break;
2154     case ASHIFTRT:
2155       sprintf (r,
2156                "mov %s,%s | asr %s,#%d | shr %s,#%d | shl %s,#%d | or %s,%s",
2157                rt, r1, r1, (int) size, r0, (int) size, rt, (int) (16 - size),
2158                r0, rt);
2159       break;
2160     case LSHIFTRT:
2161       sprintf (r,
2162                "mov %s,%s | shr %s,#%d | shr %s,#%d | shl %s,#%d | or %s,%s",
2163                rt, r1, r1, (int) size, r0, (int) size, rt, (int) (16 - size),
2164                r0, rt);
2165       break;
2166     default:
2167       gcc_unreachable ();
2168     }
2169   return r;
2170 }
2171 \f
2172 /* Attribute handling.  */
2173
2174 /* Return nonzero if the function is an interrupt function.  */
2175
2176 int
2177 xstormy16_interrupt_function_p (void)
2178 {
2179   tree attributes;
2180
2181   /* The dwarf2 mechanism asks for INCOMING_FRAME_SP_OFFSET before
2182      any functions are declared, which is demonstrably wrong, but
2183      it is worked around here.  FIXME.  */
2184   if (!cfun)
2185     return 0;
2186
2187   attributes = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl));
2188   return lookup_attribute ("interrupt", attributes) != NULL_TREE;
2189 }
2190
2191 #undef  TARGET_ATTRIBUTE_TABLE
2192 #define TARGET_ATTRIBUTE_TABLE  xstormy16_attribute_table
2193
2194 static tree xstormy16_handle_interrupt_attribute
2195   (tree *, tree, tree, int, bool *);
2196 static tree xstormy16_handle_below100_attribute
2197   (tree *, tree, tree, int, bool *);
2198
2199 static const struct attribute_spec xstormy16_attribute_table[] =
2200 {
2201   /* name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
2202      affects_type_identity.  */
2203   { "interrupt", 0, 0, false, true,  true,
2204     xstormy16_handle_interrupt_attribute , false },
2205   { "BELOW100",  0, 0, false, false, false,
2206     xstormy16_handle_below100_attribute, false },
2207   { "below100",  0, 0, false, false, false,
2208     xstormy16_handle_below100_attribute, false },
2209   { NULL,        0, 0, false, false, false, NULL, false }
2210 };
2211
2212 /* Handle an "interrupt" attribute;
2213    arguments as in struct attribute_spec.handler.  */
2214
2215 static tree
2216 xstormy16_handle_interrupt_attribute (tree *node, tree name,
2217                                       tree args ATTRIBUTE_UNUSED,
2218                                       int flags ATTRIBUTE_UNUSED,
2219                                       bool *no_add_attrs)
2220 {
2221   if (TREE_CODE (*node) != FUNCTION_TYPE)
2222     {
2223       warning (OPT_Wattributes, "%qE attribute only applies to functions",
2224                name);
2225       *no_add_attrs = true;
2226     }
2227
2228   return NULL_TREE;
2229 }
2230
2231 /* Handle an "below" attribute;
2232    arguments as in struct attribute_spec.handler.  */
2233
2234 static tree
2235 xstormy16_handle_below100_attribute (tree *node,
2236                                      tree name ATTRIBUTE_UNUSED,
2237                                      tree args ATTRIBUTE_UNUSED,
2238                                      int flags ATTRIBUTE_UNUSED,
2239                                      bool *no_add_attrs)
2240 {
2241   if (TREE_CODE (*node) != VAR_DECL
2242       && TREE_CODE (*node) != POINTER_TYPE
2243       && TREE_CODE (*node) != TYPE_DECL)
2244     {
2245       warning (OPT_Wattributes,
2246                "%<__BELOW100__%> attribute only applies to variables");
2247       *no_add_attrs = true;
2248     }
2249   else if (args == NULL_TREE && TREE_CODE (*node) == VAR_DECL)
2250     {
2251       if (! (TREE_PUBLIC (*node) || TREE_STATIC (*node)))
2252         {
2253           warning (OPT_Wattributes, "__BELOW100__ attribute not allowed "
2254                    "with auto storage class");
2255           *no_add_attrs = true;
2256         }
2257     }
2258
2259   return NULL_TREE;
2260 }
2261 \f
2262 #undef  TARGET_INIT_BUILTINS
2263 #define TARGET_INIT_BUILTINS   xstormy16_init_builtins
2264 #undef  TARGET_EXPAND_BUILTIN
2265 #define TARGET_EXPAND_BUILTIN  xstormy16_expand_builtin
2266
2267 static struct
2268 {
2269   const char * name;
2270   int          md_code;
2271   const char * arg_ops;   /* 0..9, t for temp register, r for return value.  */
2272   const char * arg_types; /* s=short,l=long, upper case for unsigned.  */
2273 }
2274   s16builtins[] =
2275 {
2276   { "__sdivlh", CODE_FOR_sdivlh, "rt01", "sls" },
2277   { "__smodlh", CODE_FOR_sdivlh, "tr01", "sls" },
2278   { "__udivlh", CODE_FOR_udivlh, "rt01", "SLS" },
2279   { "__umodlh", CODE_FOR_udivlh, "tr01", "SLS" },
2280   { NULL, 0, NULL, NULL }
2281 };
2282
2283 static void
2284 xstormy16_init_builtins (void)
2285 {
2286   tree args[2], ret_type, arg = NULL_TREE, ftype;
2287   int i, a, n_args;
2288
2289   ret_type = void_type_node;
2290
2291   for (i = 0; s16builtins[i].name; i++)
2292     {
2293       n_args = strlen (s16builtins[i].arg_types) - 1;
2294
2295       gcc_assert (n_args <= (int) ARRAY_SIZE (args));
2296
2297       for (a = n_args - 1; a >= 0; a--)
2298         args[a] = NULL_TREE;
2299
2300       for (a = n_args; a >= 0; a--)
2301         {
2302           switch (s16builtins[i].arg_types[a])
2303             {
2304             case 's': arg = short_integer_type_node; break;
2305             case 'S': arg = short_unsigned_type_node; break;
2306             case 'l': arg = long_integer_type_node; break;
2307             case 'L': arg = long_unsigned_type_node; break;
2308             default: gcc_unreachable ();
2309             }
2310           if (a == 0)
2311             ret_type = arg;
2312           else
2313             args[a-1] = arg;
2314         }
2315       ftype = build_function_type_list (ret_type, args[0], args[1], NULL_TREE);
2316       add_builtin_function (s16builtins[i].name, ftype,
2317                             i, BUILT_IN_MD, NULL, NULL_TREE);
2318     }
2319 }
2320
2321 static rtx
2322 xstormy16_expand_builtin (tree exp, rtx target,
2323                           rtx subtarget ATTRIBUTE_UNUSED,
2324                           enum machine_mode mode ATTRIBUTE_UNUSED,
2325                           int ignore ATTRIBUTE_UNUSED)
2326 {
2327   rtx op[10], args[10], pat, copyto[10], retval = 0;
2328   tree fndecl, argtree;
2329   int i, a, o, code;
2330
2331   fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
2332   argtree = TREE_OPERAND (exp, 1);
2333   i = DECL_FUNCTION_CODE (fndecl);
2334   code = s16builtins[i].md_code;
2335
2336   for (a = 0; a < 10 && argtree; a++)
2337     {
2338       args[a] = expand_normal (TREE_VALUE (argtree));
2339       argtree = TREE_CHAIN (argtree);
2340     }
2341
2342   for (o = 0; s16builtins[i].arg_ops[o]; o++)
2343     {
2344       char ao = s16builtins[i].arg_ops[o];
2345       char c = insn_data[code].operand[o].constraint[0];
2346       enum machine_mode omode;
2347
2348       copyto[o] = 0;
2349
2350       omode = (enum machine_mode) insn_data[code].operand[o].mode;
2351       if (ao == 'r')
2352         op[o] = target ? target : gen_reg_rtx (omode);
2353       else if (ao == 't')
2354         op[o] = gen_reg_rtx (omode);
2355       else
2356         op[o] = args[(int) hex_value (ao)];
2357
2358       if (! (*insn_data[code].operand[o].predicate) (op[o], GET_MODE (op[o])))
2359         {
2360           if (c == '+' || c == '=')
2361             {
2362               copyto[o] = op[o];
2363               op[o] = gen_reg_rtx (omode);
2364             }
2365           else
2366             op[o] = copy_to_mode_reg (omode, op[o]);
2367         }
2368
2369       if (ao == 'r')
2370         retval = op[o];
2371     }
2372
2373   pat = GEN_FCN (code) (op[0], op[1], op[2], op[3], op[4],
2374                         op[5], op[6], op[7], op[8], op[9]);
2375   emit_insn (pat);
2376
2377   for (o = 0; s16builtins[i].arg_ops[o]; o++)
2378     if (copyto[o])
2379       {
2380         emit_move_insn (copyto[o], op[o]);
2381         if (op[o] == retval)
2382           retval = copyto[o];
2383       }
2384
2385   return retval;
2386 }
2387 \f
2388 /* Look for combinations of insns that can be converted to BN or BP
2389    opcodes.  This is, unfortunately, too complex to do with MD
2390    patterns.  */
2391
2392 static void
2393 combine_bnp (rtx insn)
2394 {
2395   int insn_code, regno, need_extend;
2396   unsigned int mask;
2397   rtx cond, reg, and_insn, load, qireg, mem;
2398   enum machine_mode load_mode = QImode;
2399   enum machine_mode and_mode = QImode;
2400   rtx shift = NULL_RTX;
2401
2402   insn_code = recog_memoized (insn);
2403   if (insn_code != CODE_FOR_cbranchhi
2404       && insn_code != CODE_FOR_cbranchhi_neg)
2405     return;
2406
2407   cond = XVECEXP (PATTERN (insn), 0, 0); /* set */
2408   cond = XEXP (cond, 1); /* if */
2409   cond = XEXP (cond, 0); /* cond */
2410   switch (GET_CODE (cond))
2411     {
2412     case NE:
2413     case EQ:
2414       need_extend = 0;
2415       break;
2416     case LT:
2417     case GE:
2418       need_extend = 1;
2419       break;
2420     default:
2421       return;
2422     }
2423
2424   reg = XEXP (cond, 0);
2425   if (! REG_P (reg))
2426     return;
2427   regno = REGNO (reg);
2428   if (XEXP (cond, 1) != const0_rtx)
2429     return;
2430   if (! find_regno_note (insn, REG_DEAD, regno))
2431     return;
2432   qireg = gen_rtx_REG (QImode, regno);
2433
2434   if (need_extend)
2435     {
2436       /* LT and GE conditionals should have a sign extend before
2437          them.  */
2438       for (and_insn = prev_real_insn (insn);
2439            and_insn != NULL_RTX;
2440            and_insn = prev_real_insn (and_insn))
2441         {
2442           int and_code = recog_memoized (and_insn);
2443
2444           if (and_code == CODE_FOR_extendqihi2
2445               && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg)
2446               && rtx_equal_p (XEXP (SET_SRC (PATTERN (and_insn)), 0), qireg))
2447             break;
2448
2449           if (and_code == CODE_FOR_movhi_internal
2450               && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg))
2451             {
2452               /* This is for testing bit 15.  */
2453               and_insn = insn;
2454               break;
2455             }
2456
2457           if (reg_mentioned_p (reg, and_insn))
2458             return;
2459
2460           if (! NOTE_P (and_insn) && ! NONJUMP_INSN_P (and_insn))
2461             return;
2462         }
2463     }
2464   else
2465     {
2466       /* EQ and NE conditionals have an AND before them.  */
2467       for (and_insn = prev_real_insn (insn);
2468            and_insn != NULL_RTX;
2469            and_insn = prev_real_insn (and_insn))
2470         {
2471           if (recog_memoized (and_insn) == CODE_FOR_andhi3
2472               && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg)
2473               && rtx_equal_p (XEXP (SET_SRC (PATTERN (and_insn)), 0), reg))
2474             break;
2475
2476           if (reg_mentioned_p (reg, and_insn))
2477             return;
2478
2479           if (! NOTE_P (and_insn) && ! NONJUMP_INSN_P (and_insn))
2480             return;
2481         }
2482
2483       if (and_insn)
2484         {
2485           /* Some mis-optimizations by GCC can generate a RIGHT-SHIFT
2486              followed by an AND like this:
2487
2488                (parallel [(set (reg:HI r7) (lshiftrt:HI (reg:HI r7) (const_int 3)))
2489                           (clobber (reg:BI carry))]
2490
2491                (set (reg:HI r7) (and:HI (reg:HI r7) (const_int 1)))
2492
2493              Attempt to detect this here.  */
2494           for (shift = prev_real_insn (and_insn); shift;
2495                shift = prev_real_insn (shift))
2496             {
2497               if (recog_memoized (shift) == CODE_FOR_lshrhi3
2498                   && rtx_equal_p (SET_DEST (XVECEXP (PATTERN (shift), 0, 0)), reg)
2499                   && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (shift), 0, 0)), 0), reg))
2500                 break;
2501
2502               if (reg_mentioned_p (reg, shift)
2503                   || (! NOTE_P (shift) && ! NONJUMP_INSN_P (shift)))
2504                 {
2505                   shift = NULL_RTX;
2506                   break;
2507                 }
2508             }
2509         }
2510     }
2511
2512   if (and_insn == NULL_RTX)
2513     return;
2514
2515   for (load = shift ? prev_real_insn (shift) : prev_real_insn (and_insn);
2516        load;
2517        load = prev_real_insn (load))
2518     {
2519       int load_code = recog_memoized (load);
2520
2521       if (load_code == CODE_FOR_movhi_internal
2522           && rtx_equal_p (SET_DEST (PATTERN (load)), reg)
2523           && xstormy16_below100_operand (SET_SRC (PATTERN (load)), HImode)
2524           && ! MEM_VOLATILE_P (SET_SRC (PATTERN (load))))
2525         {
2526           load_mode = HImode;
2527           break;
2528         }
2529
2530       if (load_code == CODE_FOR_movqi_internal
2531           && rtx_equal_p (SET_DEST (PATTERN (load)), qireg)
2532           && xstormy16_below100_operand (SET_SRC (PATTERN (load)), QImode))
2533         {
2534           load_mode = QImode;
2535           break;
2536         }
2537
2538       if (load_code == CODE_FOR_zero_extendqihi2
2539           && rtx_equal_p (SET_DEST (PATTERN (load)), reg)
2540           && xstormy16_below100_operand (XEXP (SET_SRC (PATTERN (load)), 0), QImode))
2541         {
2542           load_mode = QImode;
2543           and_mode = HImode;
2544           break;
2545         }
2546
2547       if (reg_mentioned_p (reg, load))
2548         return;
2549
2550       if (! NOTE_P (load) && ! NONJUMP_INSN_P (load))
2551         return;
2552     }
2553   if (!load)
2554     return;
2555
2556   mem = SET_SRC (PATTERN (load));
2557
2558   if (need_extend)
2559     {
2560       mask = (load_mode == HImode) ? 0x8000 : 0x80;
2561
2562       /* If the mem includes a zero-extend operation and we are
2563          going to generate a sign-extend operation then move the
2564          mem inside the zero-extend.  */
2565       if (GET_CODE (mem) == ZERO_EXTEND)
2566         mem = XEXP (mem, 0);
2567     }
2568   else
2569     {
2570       if (!xstormy16_onebit_set_operand (XEXP (SET_SRC (PATTERN (and_insn)), 1),
2571                                          load_mode))
2572         return;
2573
2574       mask = (int) INTVAL (XEXP (SET_SRC (PATTERN (and_insn)), 1));
2575
2576       if (shift)
2577         mask <<= INTVAL (XEXP (SET_SRC (XVECEXP (PATTERN (shift), 0, 0)), 1));
2578     }
2579
2580   if (load_mode == HImode)
2581     {
2582       rtx addr = XEXP (mem, 0);
2583
2584       if (! (mask & 0xff))
2585         {
2586           addr = plus_constant (Pmode, addr, 1);
2587           mask >>= 8;
2588         }
2589       mem = gen_rtx_MEM (QImode, addr);
2590     }
2591
2592   if (need_extend)
2593     XEXP (cond, 0) = gen_rtx_SIGN_EXTEND (HImode, mem);
2594   else
2595     XEXP (cond, 0) = gen_rtx_AND (and_mode, mem, GEN_INT (mask));
2596
2597   INSN_CODE (insn) = -1;
2598   delete_insn (load);
2599
2600   if (and_insn != insn)
2601     delete_insn (and_insn);
2602
2603   if (shift != NULL_RTX)
2604     delete_insn (shift);
2605 }
2606
2607 static void
2608 xstormy16_reorg (void)
2609 {
2610   rtx insn;
2611
2612   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2613     {
2614       if (! JUMP_P (insn))
2615         continue;
2616       combine_bnp (insn);
2617     }
2618 }
2619 \f
2620 /* Worker function for TARGET_RETURN_IN_MEMORY.  */
2621
2622 static bool
2623 xstormy16_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
2624 {
2625   const HOST_WIDE_INT size = int_size_in_bytes (type);
2626   return (size == -1 || size > UNITS_PER_WORD * NUM_ARGUMENT_REGISTERS);
2627 }
2628 \f
2629 #undef  TARGET_ASM_ALIGNED_HI_OP
2630 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
2631 #undef  TARGET_ASM_ALIGNED_SI_OP
2632 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
2633 #undef  TARGET_ENCODE_SECTION_INFO
2634 #define TARGET_ENCODE_SECTION_INFO xstormy16_encode_section_info
2635
2636 /* Select_section doesn't handle .bss_below100.  */
2637 #undef  TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
2638 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS false
2639
2640 #undef  TARGET_ASM_OUTPUT_MI_THUNK
2641 #define TARGET_ASM_OUTPUT_MI_THUNK xstormy16_asm_output_mi_thunk
2642 #undef  TARGET_ASM_CAN_OUTPUT_MI_THUNK
2643 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
2644
2645 #undef  TARGET_PRINT_OPERAND
2646 #define TARGET_PRINT_OPERAND xstormy16_print_operand
2647 #undef  TARGET_PRINT_OPERAND_ADDRESS
2648 #define TARGET_PRINT_OPERAND_ADDRESS xstormy16_print_operand_address
2649
2650 #undef  TARGET_MEMORY_MOVE_COST
2651 #define TARGET_MEMORY_MOVE_COST xstormy16_memory_move_cost
2652 #undef  TARGET_RTX_COSTS
2653 #define TARGET_RTX_COSTS xstormy16_rtx_costs
2654 #undef  TARGET_ADDRESS_COST
2655 #define TARGET_ADDRESS_COST xstormy16_address_cost
2656
2657 #undef  TARGET_BUILD_BUILTIN_VA_LIST
2658 #define TARGET_BUILD_BUILTIN_VA_LIST xstormy16_build_builtin_va_list
2659 #undef  TARGET_EXPAND_BUILTIN_VA_START
2660 #define TARGET_EXPAND_BUILTIN_VA_START xstormy16_expand_builtin_va_start
2661 #undef  TARGET_GIMPLIFY_VA_ARG_EXPR
2662 #define TARGET_GIMPLIFY_VA_ARG_EXPR xstormy16_gimplify_va_arg_expr
2663
2664 #undef  TARGET_PROMOTE_FUNCTION_MODE
2665 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
2666 #undef  TARGET_PROMOTE_PROTOTYPES
2667 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
2668
2669 #undef  TARGET_FUNCTION_ARG
2670 #define TARGET_FUNCTION_ARG xstormy16_function_arg
2671 #undef  TARGET_FUNCTION_ARG_ADVANCE
2672 #define TARGET_FUNCTION_ARG_ADVANCE xstormy16_function_arg_advance
2673
2674 #undef  TARGET_RETURN_IN_MEMORY
2675 #define TARGET_RETURN_IN_MEMORY xstormy16_return_in_memory
2676 #undef TARGET_FUNCTION_VALUE
2677 #define TARGET_FUNCTION_VALUE xstormy16_function_value
2678 #undef TARGET_LIBCALL_VALUE
2679 #define TARGET_LIBCALL_VALUE xstormy16_libcall_value
2680 #undef TARGET_FUNCTION_VALUE_REGNO_P
2681 #define TARGET_FUNCTION_VALUE_REGNO_P xstormy16_function_value_regno_p
2682
2683 #undef  TARGET_MACHINE_DEPENDENT_REORG
2684 #define TARGET_MACHINE_DEPENDENT_REORG xstormy16_reorg
2685
2686 #undef  TARGET_PREFERRED_RELOAD_CLASS
2687 #define TARGET_PREFERRED_RELOAD_CLASS xstormy16_preferred_reload_class
2688 #undef  TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
2689 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xstormy16_preferred_reload_class
2690
2691 #undef TARGET_LEGITIMATE_ADDRESS_P
2692 #define TARGET_LEGITIMATE_ADDRESS_P     xstormy16_legitimate_address_p
2693 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
2694 #define TARGET_MODE_DEPENDENT_ADDRESS_P xstormy16_mode_dependent_address_p
2695
2696 #undef TARGET_CAN_ELIMINATE
2697 #define TARGET_CAN_ELIMINATE xstormy16_can_eliminate
2698
2699 #undef TARGET_TRAMPOLINE_INIT
2700 #define TARGET_TRAMPOLINE_INIT xstormy16_trampoline_init
2701
2702 struct gcc_target targetm = TARGET_INITIALIZER;
2703
2704 #include "gt-stormy16.h"