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PR target/16201
[official-gcc.git] / gcc / config / sh / sh.h
blobedeb135714b57085f3ab510794cdd3a7e1ba3ee4
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
29
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
34
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
43 builtin_define ("__sh1__"); \
44 break; \
45 case PROCESSOR_SH2: \
46 builtin_define ("__sh2__"); \
47 break; \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
50 break; \
51 case PROCESSOR_SH2A: \
52 builtin_define ("__SH2A__"); \
53 builtin_define (TARGET_SH2A_DOUBLE \
54 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
55 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
56 : "__SH2A_NOFPU__"); \
57 break; \
58 case PROCESSOR_SH3: \
59 builtin_define ("__sh3__"); \
60 builtin_define ("__SH3__"); \
61 if (TARGET_HARD_SH4) \
62 builtin_define ("__SH4_NOFPU__"); \
63 break; \
64 case PROCESSOR_SH3E: \
65 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
66 break; \
67 case PROCESSOR_SH4: \
68 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
69 break; \
70 case PROCESSOR_SH4A: \
71 builtin_define ("__SH4A__"); \
72 builtin_define (TARGET_SH4 \
73 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
74 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
75 : "__SH4_NOFPU__"); \
76 break; \
77 case PROCESSOR_SH5: \
78 { \
79 builtin_define_with_value ("__SH5__", \
80 TARGET_SHMEDIA64 ? "64" : "32", 0); \
81 builtin_define_with_value ("__SHMEDIA__", \
82 TARGET_SHMEDIA ? "1" : "0", 0); \
83 if (! TARGET_FPU_DOUBLE) \
84 builtin_define ("__SH4_NOFPU__"); \
85 } \
86 } \
87 if (TARGET_HITACHI) \
88 builtin_define ("__HITACHI__"); \
89 builtin_define (TARGET_LITTLE_ENDIAN \
90 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
91 if (flag_pic) \
92 { \
93 builtin_define ("__pic__"); \
94 builtin_define ("__PIC__"); \
95 } \
96 } while (0)
97
98 /* We can not debug without a frame pointer. */
99 /* #define CAN_DEBUG_WITHOUT_FP */
100
101 #define CONDITIONAL_REGISTER_USAGE do \
102 { \
103 int regno; \
104 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
105 if (! VALID_REGISTER_P (regno)) \
106 fixed_regs[regno] = call_used_regs[regno] = 1; \
107 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
108 if (TARGET_SH5) \
109 { \
110 call_used_regs[FIRST_GENERAL_REG + 8] \
111 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
112 call_really_used_regs[FIRST_GENERAL_REG + 8] \
113 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
114 } \
115 if (TARGET_SHMEDIA) \
116 { \
117 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
118 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
119 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
120 } \
121 if (flag_pic) \
122 { \
123 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
125 } \
126 /* Renesas saves and restores mac registers on call. */ \
127 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
128 { \
129 call_really_used_regs[MACH_REG] = 0; \
130 call_really_used_regs[MACL_REG] = 0; \
131 } \
132 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
133 regno <= LAST_FP_REG; regno += 2) \
134 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
135 if (TARGET_SHMEDIA) \
136 { \
137 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
138 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
139 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
140 } \
141 else \
142 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
143 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
144 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
145 } while (0)
146 \f
147 /* ??? Need to write documentation for all SH options and add it to the
148 invoke.texi file. */
149
150 /* Run-time compilation parameters selecting different hardware subsets. */
151
152 extern int target_flags;
153 #define ISIZE_BIT (1<<1)
154 #define DALIGN_BIT (1<<6)
155 #define SH1_BIT (1<<8)
156 #define SH2_BIT (1<<9)
157 #define SH3_BIT (1<<10)
158 #define SH_E_BIT (1<<11)
159 #define HARD_SH4_BIT (1<<5)
160 #define FPU_SINGLE_BIT (1<<7)
161 #define SH4_BIT (1<<12)
162 #define SH4A_BIT (1<<3)
163 #define FMOVD_BIT (1<<4)
164 #define SH5_BIT (1<<0)
165 #define SPACE_BIT (1<<13)
166 #define BIGTABLE_BIT (1<<14)
167 #define RELAX_BIT (1<<15)
168 #define USERMODE_BIT (1<<16)
169 #define HITACHI_BIT (1<<22)
170 #define NOMACSAVE_BIT (1<<23)
171 #define PREFERGOT_BIT (1<<24)
172 #define PADSTRUCT_BIT (1<<28)
173 #define LITTLE_ENDIAN_BIT (1<<29)
174 #define IEEE_BIT (1<<30)
175 #define SAVE_ALL_TR_BIT (1<<2)
176 #define HARD_SH2A_BIT (1<<17)
177 #define HARD_SH2A_DOUBLE_BIT (1<<18)
178
179 /* Nonzero if this is an ELF target - compile time only */
180 #define TARGET_ELF 0
181
182 /* Nonzero if we should dump out instruction size info. */
183 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
184
185 /* Nonzero to align doubles on 64 bit boundaries. */
186 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
187
188 /* Nonzero if we should generate code using type 1 insns. */
189 #define TARGET_SH1 (target_flags & SH1_BIT)
190
191 /* Nonzero if we should generate code using type 2 insns. */
192 #define TARGET_SH2 (target_flags & SH2_BIT)
193
194 /* Nonzero if we should generate code using type 2E insns. */
195 #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
196
197 /* Nonzero if we should generate code using type 2A insns. */
198 #define TARGET_SH2A (target_flags & HARD_SH2A_BIT)
199 /* Nonzero if we should generate code using type 2A SF insns. */
200 #define TARGET_SH2A_SINGLE ((target_flags & HARD_SH2A_BIT) && TARGET_SH2E)
201 /* Nonzero if we should generate code using type 2A DF insns. */
202 #define TARGET_SH2A_DOUBLE ((target_flags & HARD_SH2A_DOUBLE_BIT) && TARGET_SH2A)
203
204 /* Nonzero if we should generate code using type 3 insns. */
205 #define TARGET_SH3 (target_flags & SH3_BIT)
206
207 /* Nonzero if we should generate code using type 3E insns. */
208 #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
209
210 /* Nonzero if the cache line size is 32. */
211 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
212
213 /* Nonzero if we schedule for a superscalar implementation. */
214 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
215
216 /* Nonzero if the target has separate instruction and data caches. */
217 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
218
219 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
220 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
221
222 /* Nonzero if the default precision of th FPU is single */
223 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
224
225 /* Nonzero if a double-precision FPU is available. */
226 #define TARGET_FPU_DOUBLE ((target_flags & SH4_BIT) || TARGET_SH2A_DOUBLE)
227
228 /* Nonzero if an FPU is available. */
229 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
230
231 /* Nonzero if we should generate code using type 4 insns. */
232 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
233
234 /* Nonzero if we're generating code for the common subset of
235 instructions present on both SH4a and SH4al-dsp. */
236 #define TARGET_SH4A_ARCH (target_flags & SH4A_BIT)
237
238 /* Nonzero if we're generating code for SH4a, unless the use of the
239 FPU is disabled (which makes it compatible with SH4al-dsp). */
240 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
241
242 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
243 #define TARGET_SH5 (target_flags & SH5_BIT)
244
245 /* Nonzero if we should generate code using the SHcompact instruction
246 set and 32-bit ABI. */
247 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
248
249 /* Nonzero if we should generate code using the SHmedia instruction
250 set and ABI. */
251 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
252
253 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
254 ABI. */
255 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
256 && (target_flags & SH_E_BIT))
257
258 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
259 ABI. */
260 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
261 && ! (target_flags & SH_E_BIT))
262
263 /* Nonzero if we should generate code using SHmedia FPU instructions. */
264 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
265 /* Nonzero if we should generate fmovd. */
266 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
267
268 /* Nonzero if we respect NANs. */
269 #define TARGET_IEEE (target_flags & IEEE_BIT)
270
271 /* Nonzero if we should generate smaller code rather than faster code. */
272 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
273
274 /* Nonzero to use long jump tables. */
275 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
276
277 /* Nonzero to generate pseudo-ops needed by the assembler and linker
278 to do function call relaxing. */
279 #define TARGET_RELAX (target_flags & RELAX_BIT)
280
281 /* Nonzero if using Renesas's calling convention. */
282 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
283
284 /* Nonzero if not saving macl/mach when using -mhitachi */
285 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
286
287 /* Nonzero if padding structures to a multiple of 4 bytes. This is
288 incompatible with Renesas's compiler, and gives unusual structure layouts
289 which confuse programmers.
290 ??? This option is not useful, but is retained in case there are people
291 who are still relying on it. It may be deleted in the future. */
292 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
293
294 /* Nonzero if generating code for a little endian SH. */
295 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
296
297 /* Nonzero if we should do everything in userland. */
298 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
299
300 /* Nonzero if we should prefer @GOT calls when generating PIC. */
301 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
302
303 #define TARGET_SAVE_ALL_TARGET_REGS (target_flags & SAVE_ALL_TR_BIT)
304
305 /* This is not used by the SH2E calling convention */
306 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
307 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
308 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
309
310 #ifndef TARGET_CPU_DEFAULT
311 #define TARGET_CPU_DEFAULT SELECT_SH1
312 #define SUPPORT_SH1
313 #define SUPPORT_SH2E
314 #define SUPPORT_SH4
315 #define SUPPORT_SH4_SINGLE
316 #define SUPPORT_SH2A
317 #define SUPPORT_SH2A_SINGLE
318 #endif
319
320 #define SELECT_SH1 (SH1_BIT)
321 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
322 #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
323 #define SELECT_SH2A (SH_E_BIT | HARD_SH2A_BIT | HARD_SH2A_DOUBLE_BIT | SH2_BIT | SH1_BIT)
324 #define SELECT_SH2A_NOFPU (HARD_SH2A_BIT | SH2_BIT | SH1_BIT)
325 #define SELECT_SH2A_SINGLE_ONLY (SH_E_BIT | HARD_SH2A_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
326 #define SELECT_SH2A_SINGLE (SH_E_BIT | HARD_SH2A_BIT | FPU_SINGLE_BIT \
327 | HARD_SH2A_DOUBLE_BIT | SH2_BIT | SH1_BIT)
328 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
329 #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
330 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
331 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
332 #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
333 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
334 #define SELECT_SH4A_NOFPU (SH4A_BIT | SELECT_SH4_NOFPU)
335 #define SELECT_SH4A_SINGLE_ONLY (SH4A_BIT | SELECT_SH4_SINGLE_ONLY)
336 #define SELECT_SH4A (SH4A_BIT | SELECT_SH4)
337 #define SELECT_SH4A_SINGLE (SH4A_BIT | SELECT_SH4_SINGLE)
338 #define SELECT_SH5_64MEDIA (SH5_BIT | SH4_BIT)
339 #define SELECT_SH5_64MEDIA_NOFPU (SH5_BIT)
340 #define SELECT_SH5_32MEDIA (SH5_BIT | SH4_BIT | SH_E_BIT)
341 #define SELECT_SH5_32MEDIA_NOFPU (SH5_BIT | SH_E_BIT)
342 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
343 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
344
345 /* Disable processor switches for which we have no suitable multilibs. */
346 #ifndef SUPPORT_SH1
347 #define TARGET_SWITCH_SH1
348 #ifndef SUPPORT_SH2
349 #define TARGET_SWITCH_SH2
350 #ifndef SUPPORT_SH3
351 #define TARGET_SWITCH_SH3
352 #ifndef SUPPORT_SH4_NOFPU
353 #define TARGET_SWITCH_SH4_NOFPU
354 #endif
355 #ifndef SUPPORT_SH4A_NOFPU
356 #define TARGET_SWITCH_SH4A_NOFPU
357 #endif
358 #ifndef SUPPORT_SH4AL
359 #define TARGET_SWITCH_SH4AL
360 #endif
361 #ifndef SUPPORT_SH2A_NOFPU
362 #define TARGET_SWITCH_SH2A_NOFPU
363 #endif
364 #endif
365 #endif
366 #endif
367
368 #ifndef SUPPORT_SH2E
369 #define TARGET_SWITCH_SH2E
370 #ifndef SUPPORT_SH3E
371 #define TARGET_SWITCH_SH3E
372 #ifndef SUPPORT_SH4_SINGLE_ONLY
373 #define TARGET_SWITCH_SH4_SINGLE_ONLY
374 #endif
375 #ifndef SUPPORT_SH4A_SINGLE_ONLY
376 #define TARGET_SWITCH_SH4A_SINGLE_ONLY
377 #endif
378 #ifndef SUPPORT_SH2A_SINGLE_ONLY
379 #define TARGET_SWITCH_SH2A_SINGLE_ONLY
380 #endif
381 #endif
382 #endif
383
384 #ifndef SUPPORT_SH4
385 #define TARGET_SWITCH_SH4
386 #ifndef SUPPORT_SH4A
387 #define TARGET_SWITCH_SH4A
388 #endif
389 #endif
390
391 #ifndef SUPPORT_SH4_SINGLE
392 #define TARGET_SWITCH_SH4_SINGLE
393 #ifndef SUPPORT_SH4A_SINGLE
394 #define TARGET_SWITCH_SH4A_SINGLE
395 #endif
396 #endif
397
398 #ifndef SUPPORT_SH2A
399 #define TARGET_SWITCH_SH2A
400 #endif
401
402 #ifndef SUPPORT_SH2A_SINGLE
403 #define TARGET_SWITCH_SH2A_SINGLE
404 #endif
405
406 #ifndef SUPPORT_SH5_64MEDIA
407 #define TARGET_SWITCH_SH5_64MEDIA
408 #endif
409
410 #ifndef SUPPORT_SH5_64MEDIA_NOFPU
411 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU
412 #endif
413
414 #if !defined(SUPPORT_SH5_32MEDIA) && !defined (SUPPORT_SH5_COMPACT)
415 #define TARGET_SWITCHES_SH5_32MEDIA
416 #endif
417
418 #if !defined(SUPPORT_SH5_32MEDIA_NOFPU) && !defined (SUPPORT_SH5_COMPACT_NOFPU)
419 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU
420 #endif
421
422 /* Reset all target-selection flags. */
423 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
424 | HARD_SH2A_BIT | HARD_SH2A_DOUBLE_BIT \
425 | SH4A_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
426
427 #ifndef TARGET_SWITCH_SH1
428 #define TARGET_SWITCH_SH1 \
429 {"1", TARGET_NONE, "" }, \
430 {"1", SELECT_SH1, "Generate SH1 code" },
431 #endif
432 #ifndef TARGET_SWITCH_SH2
433 #define TARGET_SWITCH_SH2 \
434 {"2", TARGET_NONE, "" }, \
435 {"2", SELECT_SH2, "Generate SH2 code" },
436 #endif
437 #ifndef TARGET_SWITCH_SH2E
438 #define TARGET_SWITCH_SH2E \
439 {"2e", TARGET_NONE, "" }, \
440 {"2e", SELECT_SH2E, "Generate SH2e code" },
441 #endif
442 #ifndef TARGET_SWITCH_SH2A
443 #define TARGET_SWITCH_SH2A \
444 {"2a", TARGET_NONE, "" }, \
445 {"2a", SELECT_SH2A, "Generate SH2a code" },
446 #endif
447 #ifndef TARGET_SWITCH_SH2A_SINGLE_ONLY
448 #define TARGET_SWITCH_SH2A_SINGLE_ONLY \
449 {"2a-single-only", TARGET_NONE, "" }, \
450 {"2a-single-only", SELECT_SH2A_SINGLE_ONLY, "Generate only single-precision SH2a code" },
451 #endif
452 #ifndef TARGET_SWITCH_SH2A_SINGLE
453 #define TARGET_SWITCH_SH2A_SINGLE \
454 {"2a-single", TARGET_NONE, "" }, \
455 {"2a-single", SELECT_SH2A_SINGLE, "Generate default single-precision SH2a code" },
456 #endif
457 #ifndef TARGET_SWITCH_SH2A_NOFPU
458 #define TARGET_SWITCH_SH2A_NOFPU \
459 {"2a-nofpu", TARGET_NONE, "" }, \
460 {"2a-nofpu", SELECT_SH2A_NOFPU, "Generate SH2a FPU-less code" },
461 #endif
462 #ifndef TARGET_SWITCH_SH3
463 #define TARGET_SWITCH_SH3 \
464 {"3", TARGET_NONE, "" }, \
465 {"3", SELECT_SH3, "Generate SH3 code" },
466 #endif
467 #ifndef TARGET_SWITCH_SH3E
468 #define TARGET_SWITCH_SH3E \
469 {"3e", TARGET_NONE, "" }, \
470 {"3e", SELECT_SH3E, "Generate SH3e code" },
471 #endif
472 #ifndef TARGET_SWITCH_SH4_SINGLE_ONLY
473 #define TARGET_SWITCH_SH4_SINGLE_ONLY \
474 {"4-single-only", TARGET_NONE, "" }, \
475 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" },
476 #endif
477 #ifndef TARGET_SWITCH_SH4_SINGLE
478 #define TARGET_SWITCH_SH4_SINGLE \
479 {"4-single", TARGET_NONE, "" }, \
480 {"4-single", SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" },
481 #endif
482 #ifndef TARGET_SWITCH_SH4_NOFPU
483 #define TARGET_SWITCH_SH4_NOFPU \
484 {"4-nofpu", TARGET_NONE, "" }, \
485 {"4-nofpu", SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" },
486 #endif
487 #ifndef TARGET_SWITCH_SH4
488 #define TARGET_SWITCH_SH4 \
489 {"4", TARGET_NONE, "" }, \
490 {"4", SELECT_SH4, "Generate SH4 code" },
491 #endif
492 #ifndef TARGET_SWITCH_SH4A
493 #define TARGET_SWITCH_SH4A \
494 {"4a", TARGET_NONE, "" }, \
495 {"4a", SELECT_SH4A, "Generate SH4a code" },
496 #endif
497 #ifndef TARGET_SWITCH_SH4A_SINGLE_ONLY
498 #define TARGET_SWITCH_SH4A_SINGLE_ONLY \
499 {"4a-single-only", TARGET_NONE, "" }, \
500 {"4a-single-only", SELECT_SH4A_SINGLE_ONLY, "Generate only single-precision SH4a code" },
501 #endif
502 #ifndef TARGET_SWITCH_SH4A_SINGLE
503 #define TARGET_SWITCH_SH4A_SINGLE \
504 {"4a-single", TARGET_NONE, "" },\
505 {"4a-single", SELECT_SH4A_SINGLE, "Generate default single-precision SH4a code" },
506 #endif
507 #ifndef TARGET_SWITCH_SH4A_NOFPU
508 #define TARGET_SWITCH_SH4A_NOFPU \
509 {"4a-nofpu", TARGET_NONE, "" },\
510 {"4a-nofpu", SELECT_SH4A_NOFPU, "Generate SH4a FPU-less code" },
511 #endif
512 #ifndef TARGET_SWITCH_SH4AL
513 #define TARGET_SWITCH_SH4AL \
514 {"4al", TARGET_NONE, "" },\
515 {"4al", SELECT_SH4A_NOFPU, "Generate SH4al-dsp code" },
516 #endif
517 #ifndef TARGET_SWITCH_SH5_64MEDIA
518 #define TARGET_SWITCH_SH5_64MEDIA \
519 {"5-64media", TARGET_NONE, "" }, \
520 {"5-64media", SELECT_SH5_64MEDIA, "Generate 64-bit SHmedia code" },
521 #endif
522 #ifndef TARGET_SWITCH_SH5_64MEDIA_NOFPU
523 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU \
524 {"5-64media-nofpu", TARGET_NONE, "" }, \
525 {"5-64media-nofpu", SELECT_SH5_64MEDIA_NOFPU, "Generate 64-bit FPU-less SHmedia code" },
526 #endif
527 #ifndef TARGET_SWITCHES_SH5_32MEDIA
528 #define TARGET_SWITCHES_SH5_32MEDIA \
529 {"5-32media", TARGET_NONE, "" }, \
530 {"5-32media", SELECT_SH5_32MEDIA, "Generate 32-bit SHmedia code" }, \
531 {"5-compact", TARGET_NONE, "" }, \
532 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" },
533 #endif
534 #ifndef TARGET_SWITCHES_SH5_32MEDIA_NOFPU
535 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
536 {"5-32media-nofpu", TARGET_NONE, "" }, \
537 {"5-32media-nofpu", SELECT_SH5_32MEDIA_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
538 {"5-compact-nofpu", TARGET_NONE, "" }, \
539 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" },
540 #endif
541
542 #define TARGET_SWITCHES \
543 { TARGET_SWITCH_SH1 \
544 TARGET_SWITCH_SH2 \
545 TARGET_SWITCH_SH2A_SINGLE_ONLY \
546 TARGET_SWITCH_SH2A_SINGLE \
547 TARGET_SWITCH_SH2A_NOFPU \
548 TARGET_SWITCH_SH2A \
549 TARGET_SWITCH_SH2E \
550 TARGET_SWITCH_SH3 \
551 TARGET_SWITCH_SH3E \
552 TARGET_SWITCH_SH4_SINGLE_ONLY \
553 TARGET_SWITCH_SH4_SINGLE \
554 TARGET_SWITCH_SH4_NOFPU \
555 TARGET_SWITCH_SH4 \
556 TARGET_SWITCH_SH4A_SINGLE_ONLY \
557 TARGET_SWITCH_SH4A_SINGLE \
558 TARGET_SWITCH_SH4A_NOFPU \
559 TARGET_SWITCH_SH4A \
560 TARGET_SWITCH_SH4AL \
561 TARGET_SWITCH_SH5_64MEDIA \
562 TARGET_SWITCH_SH5_64MEDIA_NOFPU \
563 TARGET_SWITCHES_SH5_32MEDIA \
564 TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
565 {"b", -LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
566 {"bigtable", BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
567 {"dalign", DALIGN_BIT, "Aligns doubles at 64-bit boundaries" }, \
568 {"fmovd", FMOVD_BIT, "" }, \
569 {"hitachi", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
570 {"renesas", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
571 {"no-renesas",-HITACHI_BIT,"Follow the GCC calling conventions" }, \
572 {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" }, \
573 {"ieee", IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
574 {"isize", ISIZE_BIT, "" }, \
575 {"l", LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
576 {"no-ieee", -IEEE_BIT, "" }, \
577 {"padstruct", PADSTRUCT_BIT, "" }, \
578 {"prefergot", PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
579 {"relax", RELAX_BIT, "Shorten address references during linking" }, \
580 {"space", SPACE_BIT, "Deprecated. Use -Os instead" }, \
581 {"usermode", USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
582 SUBTARGET_SWITCHES \
583 {"", TARGET_DEFAULT, "" } \
584 }
585
586 /* This are meant to be redefined in the host dependent files */
587 #define SUBTARGET_SWITCHES
588
589 /* This defaults us to big-endian. */
590 #ifndef TARGET_ENDIAN_DEFAULT
591 #define TARGET_ENDIAN_DEFAULT 0
592 #endif
593
594 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
595
596 #ifndef SH_MULTILIB_CPU_DEFAULT
597 #define SH_MULTILIB_CPU_DEFAULT "m1"
598 #endif
599
600 #if TARGET_ENDIAN_DEFAULT
601 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
602 #else
603 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
604 #endif
605
606 #define CPP_SPEC " %(subtarget_cpp_spec) "
607
608 #ifndef SUBTARGET_CPP_SPEC
609 #define SUBTARGET_CPP_SPEC ""
610 #endif
611
612 #ifndef SUBTARGET_EXTRA_SPECS
613 #define SUBTARGET_EXTRA_SPECS
614 #endif
615
616 #define EXTRA_SPECS \
617 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
618 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
619 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
620 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
621 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
622 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
623 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
624 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
625 SUBTARGET_EXTRA_SPECS
626
627 #if TARGET_CPU_DEFAULT & HARD_SH4_BIT
628 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
629 #else
630 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
631 #endif
632
633 #define SH_ASM_SPEC \
634 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
635 %(subtarget_asm_isa_spec) %{m4al:-dsp}"
636
637 #define ASM_SPEC SH_ASM_SPEC
638
639 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
640 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
641 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
642 #else
643 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
644 #endif
645 #endif
646
647 #define SUBTARGET_ASM_ISA_SPEC ""
648
649 #define LINK_EMUL_PREFIX "sh%{ml:l}"
650
651 #if TARGET_CPU_DEFAULT & SH5_BIT
652 #if TARGET_CPU_DEFAULT & SH_E_BIT
653 #define LINK_DEFAULT_CPU_EMUL "32"
654 #if TARGET_CPU_DEFAULT & SH1_BIT
655 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
656 #else
657 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
658 #endif /* SH1_BIT */
659 #else /* !SH_E_BIT */
660 #define LINK_DEFAULT_CPU_EMUL "64"
661 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
662 #endif /* SH_E_BIT */
663 #define ASM_ISA_DEFAULT_SPEC \
664 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
665 #else /* !SH5_BIT */
666 #define LINK_DEFAULT_CPU_EMUL ""
667 #define ASM_ISA_DEFAULT_SPEC ""
668 #endif /* SH5_BIT */
669
670 #define SUBTARGET_LINK_EMUL_SUFFIX ""
671 #define SUBTARGET_LINK_SPEC ""
672
673 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
674 so that we can undo the damage without code replication. */
675 #define LINK_SPEC SH_LINK_SPEC
676
677 #define SH_LINK_SPEC "\
678 -m %(link_emul_prefix)\
679 %{m5-compact*|m5-32media*:32}\
680 %{m5-64media*:64}\
681 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
682 %(subtarget_link_emul_suffix) \
683 %{mrelax:-relax} %(subtarget_link_spec)"
684
685 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
686 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
687 do { \
688 if (LEVEL) \
689 flag_omit_frame_pointer = -1; \
690 if (SIZE) \
691 target_flags |= SPACE_BIT; \
692 if (TARGET_SHMEDIA && LEVEL > 1) \
693 { \
694 flag_branch_target_load_optimize = 1; \
695 if (! (SIZE)) \
696 target_flags |= SAVE_ALL_TR_BIT; \
697 } \
698 } while (0)
699
700 #define ASSEMBLER_DIALECT assembler_dialect
701
702 extern int assembler_dialect;
703
704 #define OVERRIDE_OPTIONS \
705 do { \
706 int regno; \
707 \
708 sh_cpu = CPU_SH1; \
709 assembler_dialect = 0; \
710 if (TARGET_SH2) \
711 sh_cpu = CPU_SH2; \
712 if (TARGET_SH2E) \
713 sh_cpu = CPU_SH2E; \
714 if (TARGET_SH2A) \
715 { \
716 sh_cpu = CPU_SH2A; \
717 if (TARGET_SH2A_DOUBLE) \
718 target_flags |= FMOVD_BIT; \
719 } \
720 if (TARGET_SH3) \
721 sh_cpu = CPU_SH3; \
722 if (TARGET_SH3E) \
723 sh_cpu = CPU_SH3E; \
724 if (TARGET_SH4) \
725 { \
726 assembler_dialect = 1; \
727 sh_cpu = CPU_SH4; \
728 } \
729 if (TARGET_SH4A_ARCH) \
730 { \
731 assembler_dialect = 1; \
732 sh_cpu = CPU_SH4A; \
733 } \
734 if (TARGET_SH5) \
735 { \
736 sh_cpu = CPU_SH5; \
737 target_flags |= DALIGN_BIT; \
738 if (TARGET_FPU_ANY \
739 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
740 target_flags |= FMOVD_BIT; \
741 if (TARGET_SHMEDIA) \
742 { \
743 /* There are no delay slots on SHmedia. */ \
744 flag_delayed_branch = 0; \
745 /* Relaxation isn't yet supported for SHmedia */ \
746 target_flags &= ~RELAX_BIT; \
747 } \
748 /* -fprofile-arcs needs a working libgcov . In unified tree \
749 configurations with newlib, this requires to configure with \
750 --with-newlib --with-headers. But there is no way to check \
751 here we have a working libgcov, so just assume that we have. */\
752 if (profile_flag) \
753 { \
754 warning ("Profiling is not supported on this target."); \
755 profile_flag = profile_arc_flag = 0; \
756 } \
757 } \
758 else \
759 { \
760 /* Only the sh64-elf assembler fully supports .quad properly. */\
761 targetm.asm_out.aligned_op.di = NULL; \
762 targetm.asm_out.unaligned_op.di = NULL; \
763 } \
764 if (TARGET_FMOVD) \
765 reg_class_from_letter['e' - 'a'] = NO_REGS; \
766 \
767 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
768 if (! VALID_REGISTER_P (regno)) \
769 sh_register_names[regno][0] = '\0'; \
770 \
771 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
772 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
773 sh_additional_register_names[regno][0] = '\0'; \
774 \
775 if (flag_omit_frame_pointer < 0) \
776 { \
777 /* The debugging information is sufficient, \
778 but gdb doesn't implement this yet */ \
779 if (0) \
780 flag_omit_frame_pointer \
781 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
782 else \
783 flag_omit_frame_pointer = 0; \
784 } \
785 \
786 if (flag_pic && ! TARGET_PREFERGOT) \
787 flag_no_function_cse = 1; \
788 \
789 if (SMALL_REGISTER_CLASSES) \
790 { \
791 /* Never run scheduling before reload, since that can \
792 break global alloc, and generates slower code anyway due \
793 to the pressure on R0. */ \
794 /* Enable sched1 for SH4; ready queue will be reordered by \
795 the target hooks when pressure is high. We can not do this for \
796 SH3 and lower as they give spill failures for R0. */ \
797 if (!TARGET_HARD_SH4) \
798 flag_schedule_insns = 0; \
799 } \
800 \
801 if (align_loops == 0) \
802 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
803 if (align_jumps == 0) \
804 align_jumps = 1 << CACHE_LOG; \
805 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
806 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
807 \
808 /* Allocation boundary (in *bytes*) for the code of a function. \
809 SH1: 32 bit alignment is faster, because instructions are always \
810 fetched as a pair from a longword boundary. \
811 SH2 .. SH5 : align to cache line start. */ \
812 if (align_functions == 0) \
813 align_functions \
814 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
815 /* The linker relaxation code breaks when a function contains \
816 alignments that are larger than that at the start of a \
817 compilation unit. */ \
818 if (TARGET_RELAX) \
819 { \
820 int min_align \
821 = align_loops > align_jumps ? align_loops : align_jumps; \
822 \
823 /* Also take possible .long constants / mova tables int account. */\
824 if (min_align < 4) \
825 min_align = 4; \
826 if (align_functions < min_align) \
827 align_functions = min_align; \
828 } \
829 } while (0)
830 \f
831 /* Target machine storage layout. */
832
833 /* Define this if most significant bit is lowest numbered
834 in instructions that operate on numbered bit-fields. */
835
836 #define BITS_BIG_ENDIAN 0
837
838 /* Define this if most significant byte of a word is the lowest numbered. */
839 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
840
841 /* Define this if most significant word of a multiword number is the lowest
842 numbered. */
843 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
844
845 /* Define this to set the endianness to use in libgcc2.c, which can
846 not depend on target_flags. */
847 #if defined(__LITTLE_ENDIAN__)
848 #define LIBGCC2_WORDS_BIG_ENDIAN 0
849 #else
850 #define LIBGCC2_WORDS_BIG_ENDIAN 1
851 #endif
852
853 #define MAX_BITS_PER_WORD 64
854
855 /* Width in bits of an `int'. We want just 32-bits, even if words are
856 longer. */
857 #define INT_TYPE_SIZE 32
858
859 /* Width in bits of a `long'. */
860 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
861
862 /* Width in bits of a `long long'. */
863 #define LONG_LONG_TYPE_SIZE 64
864
865 /* Width in bits of a `long double'. */
866 #define LONG_DOUBLE_TYPE_SIZE 64
867
868 /* Width of a word, in units (bytes). */
869 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
870 #define MIN_UNITS_PER_WORD 4
871
872 /* Scaling factor for Dwarf data offsets for CFI information.
873 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
874 SHmedia; however, since we do partial register saves for the registers
875 visible to SHcompact, and for target registers for SHMEDIA32, we have
876 to allow saves that are only 4-byte aligned. */
877 #define DWARF_CIE_DATA_ALIGNMENT -4
878
879 /* Width in bits of a pointer.
880 See also the macro `Pmode' defined below. */
881 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
882
883 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
884 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
885
886 /* Boundary (in *bits*) on which stack pointer should be aligned. */
887 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
888
889 /* The log (base 2) of the cache line size, in bytes. Processors prior to
890 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
891 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
892 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
893
894 /* ABI given & required minimum allocation boundary (in *bits*) for the
895 code of a function. */
896 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
897
898 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
899 the vbit must go into the delta field of
900 pointers-to-member-functions. */
901 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
902 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
903
904 /* Alignment of field after `int : 0' in a structure. */
905 #define EMPTY_FIELD_BOUNDARY 32
906
907 /* No data type wants to be aligned rounder than this. */
908 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
909
910 /* The best alignment to use in cases where we have a choice. */
911 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
912
913 /* Make strings word-aligned so strcpy from constants will be faster. */
914 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
915 ((TREE_CODE (EXP) == STRING_CST \
916 && (ALIGN) < FASTEST_ALIGNMENT) \
917 ? FASTEST_ALIGNMENT : (ALIGN))
918
919 /* get_mode_alignment assumes complex values are always held in multiple
920 registers, but that is not the case on the SH; CQImode and CHImode are
921 held in a single integer register. SH5 also holds CSImode and SCmode
922 values in integer registers. This is relevant for argument passing on
923 SHcompact as we use a stack temp in order to pass CSImode by reference. */
924 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
925 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
926 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
927 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
928 : (unsigned) ALIGN)
929
930 /* Make arrays of chars word-aligned for the same reasons. */
931 #define DATA_ALIGNMENT(TYPE, ALIGN) \
932 (TREE_CODE (TYPE) == ARRAY_TYPE \
933 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
934 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
935
936 /* Number of bits which any structure or union's size must be a
937 multiple of. Each structure or union's size is rounded up to a
938 multiple of this. */
939 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
940
941 /* Set this nonzero if move instructions will actually fail to work
942 when given unaligned data. */
943 #define STRICT_ALIGNMENT 1
944
945 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
946 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
947 barrier_align (LABEL_AFTER_BARRIER)
948
949 #define LOOP_ALIGN(A_LABEL) \
950 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
951 ? 0 : sh_loop_align (A_LABEL))
952
953 #define LABEL_ALIGN(A_LABEL) \
954 ( \
955 (PREV_INSN (A_LABEL) \
956 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
957 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
958 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
959 /* explicit alignment insn in constant tables. */ \
960 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
961 : 0)
962
963 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
964 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
965
966 /* The base two logarithm of the known minimum alignment of an insn length. */
967 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
968 (GET_CODE (A_INSN) == INSN \
969 ? 1 << TARGET_SHMEDIA \
970 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
971 ? 1 << TARGET_SHMEDIA \
972 : CACHE_LOG)
973 \f
974 /* Standard register usage. */
975
976 /* Register allocation for the Renesas calling convention:
977
978 r0 arg return
979 r1..r3 scratch
980 r4..r7 args in
981 r8..r13 call saved
982 r14 frame pointer/call saved
983 r15 stack pointer
984 ap arg pointer (doesn't really exist, always eliminated)
985 pr subroutine return address
986 t t bit
987 mach multiply/accumulate result, high part
988 macl multiply/accumulate result, low part.
989 fpul fp/int communication register
990 rap return address pointer register
991 fr0 fp arg return
992 fr1..fr3 scratch floating point registers
993 fr4..fr11 fp args in
994 fr12..fr15 call saved floating point registers */
995
996 #define MAX_REGISTER_NAME_LENGTH 5
997 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
998
999 #define SH_REGISTER_NAMES_INITIALIZER \
1000 { \
1001 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1002 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1003 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
1004 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
1005 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
1006 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
1007 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
1008 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
1009 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1010 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
1011 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
1012 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
1013 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
1014 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
1015 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
1016 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
1017 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
1018 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
1019 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
1020 "rap" \
1021 }
1022
1023 #define REGNAMES_ARR_INDEX_1(index) \
1024 (sh_register_names[index])
1025 #define REGNAMES_ARR_INDEX_2(index) \
1026 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
1027 #define REGNAMES_ARR_INDEX_4(index) \
1028 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
1029 #define REGNAMES_ARR_INDEX_8(index) \
1030 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
1031 #define REGNAMES_ARR_INDEX_16(index) \
1032 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
1033 #define REGNAMES_ARR_INDEX_32(index) \
1034 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
1035 #define REGNAMES_ARR_INDEX_64(index) \
1036 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
1037
1038 #define REGISTER_NAMES \
1039 { \
1040 REGNAMES_ARR_INDEX_64 (0), \
1041 REGNAMES_ARR_INDEX_64 (64), \
1042 REGNAMES_ARR_INDEX_8 (128), \
1043 REGNAMES_ARR_INDEX_8 (136), \
1044 REGNAMES_ARR_INDEX_8 (144), \
1045 REGNAMES_ARR_INDEX_1 (152) \
1046 }
1047
1048 #define ADDREGNAMES_SIZE 32
1049 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
1050 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
1051 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
1052
1053 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
1054 { \
1055 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
1056 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
1057 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
1058 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
1059 }
1060
1061 #define ADDREGNAMES_REGNO(index) \
1062 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
1063 : (-1))
1064
1065 #define ADDREGNAMES_ARR_INDEX_1(index) \
1066 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
1067 #define ADDREGNAMES_ARR_INDEX_2(index) \
1068 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
1069 #define ADDREGNAMES_ARR_INDEX_4(index) \
1070 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
1071 #define ADDREGNAMES_ARR_INDEX_8(index) \
1072 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1073 #define ADDREGNAMES_ARR_INDEX_16(index) \
1074 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1075 #define ADDREGNAMES_ARR_INDEX_32(index) \
1076 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1077
1078 #define ADDITIONAL_REGISTER_NAMES \
1079 { \
1080 ADDREGNAMES_ARR_INDEX_32 (0) \
1081 }
1082
1083 /* Number of actual hardware registers.
1084 The hardware registers are assigned numbers for the compiler
1085 from 0 to just below FIRST_PSEUDO_REGISTER.
1086 All registers that the compiler knows about must be given numbers,
1087 even those that are not normally considered general registers. */
1088
1089 /* There are many other relevant definitions in sh.md's md_constants. */
1090
1091 #define FIRST_GENERAL_REG R0_REG
1092 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1093 #define FIRST_FP_REG DR0_REG
1094 #define LAST_FP_REG (FIRST_FP_REG + \
1095 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1096 #define FIRST_XD_REG XD0_REG
1097 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1098 #define FIRST_TARGET_REG TR0_REG
1099 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1100
1101 #define GENERAL_REGISTER_P(REGNO) \
1102 IN_RANGE ((REGNO), \
1103 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1104 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1105
1106 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1107 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
1108
1109 #define FP_REGISTER_P(REGNO) \
1110 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1111
1112 #define XD_REGISTER_P(REGNO) \
1113 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1114
1115 #define FP_OR_XD_REGISTER_P(REGNO) \
1116 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1117
1118 #define FP_ANY_REGISTER_P(REGNO) \
1119 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1120
1121 #define SPECIAL_REGISTER_P(REGNO) \
1122 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1123 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1124
1125 #define TARGET_REGISTER_P(REGNO) \
1126 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1127
1128 #define SHMEDIA_REGISTER_P(REGNO) \
1129 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1130 || TARGET_REGISTER_P (REGNO))
1131
1132 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1133 that should be fixed. */
1134 #define VALID_REGISTER_P(REGNO) \
1135 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1136 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1137 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1138 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1139
1140 /* The mode that should be generally used to store a register by
1141 itself in the stack, or to load it back. */
1142 #define REGISTER_NATURAL_MODE(REGNO) \
1143 (FP_REGISTER_P (REGNO) ? SFmode \
1144 : XD_REGISTER_P (REGNO) ? DFmode \
1145 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1146 ? DImode \
1147 : SImode)
1148
1149 #define FIRST_PSEUDO_REGISTER 153
1150
1151 /* 1 for registers that have pervasive standard uses
1152 and are not available for the register allocator.
1153
1154 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1155 It is 32 bits wide for SH2. */
1156
1157 #define FIXED_REGISTERS \
1158 { \
1159 /* Regular registers. */ \
1160 0, 0, 0, 0, 0, 0, 0, 0, \
1161 0, 0, 0, 0, 0, 0, 0, 1, \
1162 /* r16 is reserved, r18 is the former pr. */ \
1163 1, 0, 0, 0, 0, 0, 0, 0, \
1164 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1165 /* r26 is a global variable data pointer; r27 is for constants. */ \
1166 1, 1, 1, 1, 0, 0, 0, 0, \
1167 0, 0, 0, 0, 0, 0, 0, 0, \
1168 0, 0, 0, 0, 0, 0, 0, 0, \
1169 0, 0, 0, 0, 0, 0, 0, 0, \
1170 0, 0, 0, 0, 0, 0, 0, 1, \
1171 /* FP registers. */ \
1172 0, 0, 0, 0, 0, 0, 0, 0, \
1173 0, 0, 0, 0, 0, 0, 0, 0, \
1174 0, 0, 0, 0, 0, 0, 0, 0, \
1175 0, 0, 0, 0, 0, 0, 0, 0, \
1176 0, 0, 0, 0, 0, 0, 0, 0, \
1177 0, 0, 0, 0, 0, 0, 0, 0, \
1178 0, 0, 0, 0, 0, 0, 0, 0, \
1179 0, 0, 0, 0, 0, 0, 0, 0, \
1180 /* Branch target registers. */ \
1181 0, 0, 0, 0, 0, 0, 0, 0, \
1182 /* XD registers. */ \
1183 0, 0, 0, 0, 0, 0, 0, 0, \
1184 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1185 1, 1, 1, 1, 1, 1, 0, 1, \
1186 /*"rap" */ \
1187 1, \
1188 }
1189
1190 /* 1 for registers not available across function calls.
1191 These must include the FIXED_REGISTERS and also any
1192 registers that can be used without being saved.
1193 The latter must include the registers where values are returned
1194 and the register where structure-value addresses are passed.
1195 Aside from that, you can include as many other registers as you like. */
1196
1197 #define CALL_USED_REGISTERS \
1198 { \
1199 /* Regular registers. */ \
1200 1, 1, 1, 1, 1, 1, 1, 1, \
1201 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1202 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1203 across SH5 function calls. */ \
1204 0, 0, 0, 0, 0, 0, 0, 1, \
1205 1, 1, 1, 1, 1, 1, 1, 1, \
1206 1, 1, 1, 1, 0, 0, 0, 0, \
1207 0, 0, 0, 0, 1, 1, 1, 1, \
1208 1, 1, 1, 1, 0, 0, 0, 0, \
1209 0, 0, 0, 0, 0, 0, 0, 0, \
1210 0, 0, 0, 0, 1, 1, 1, 1, \
1211 /* FP registers. */ \
1212 1, 1, 1, 1, 1, 1, 1, 1, \
1213 1, 1, 1, 1, 0, 0, 0, 0, \
1214 1, 1, 1, 1, 1, 1, 1, 1, \
1215 1, 1, 1, 1, 1, 1, 1, 1, \
1216 1, 1, 1, 1, 0, 0, 0, 0, \
1217 0, 0, 0, 0, 0, 0, 0, 0, \
1218 0, 0, 0, 0, 0, 0, 0, 0, \
1219 0, 0, 0, 0, 0, 0, 0, 0, \
1220 /* Branch target registers. */ \
1221 1, 1, 1, 1, 1, 0, 0, 0, \
1222 /* XD registers. */ \
1223 1, 1, 1, 1, 1, 1, 0, 0, \
1224 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1225 1, 1, 1, 1, 1, 1, 1, 1, \
1226 /*"rap" */ \
1227 1, \
1228 }
1229
1230 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1231 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1232 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1233
1234 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1235 across SHcompact function calls. We can't tell whether a called
1236 function is SHmedia or SHcompact, so we assume it may be when
1237 compiling SHmedia code with the 32-bit ABI, since that's the only
1238 ABI that can be linked with SHcompact code. */
1239 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1240 (TARGET_SHMEDIA32 \
1241 && GET_MODE_SIZE (MODE) > 4 \
1242 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1243 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1244 || TARGET_REGISTER_P (REGNO) \
1245 || (REGNO) == PR_MEDIA_REG))
1246
1247 /* Return number of consecutive hard regs needed starting at reg REGNO
1248 to hold something of mode MODE.
1249 This is ordinarily the length in words of a value of mode MODE
1250 but can be less for certain modes in special long registers.
1251
1252 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1253
1254 #define HARD_REGNO_NREGS(REGNO, MODE) \
1255 (XD_REGISTER_P (REGNO) \
1256 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1257 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1258 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1259 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1260
1261 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1262 We can allow any mode in any general register. The special registers
1263 only allow SImode. Don't allow any mode in the PR. */
1264
1265 /* We cannot hold DCmode values in the XD registers because alter_reg
1266 handles subregs of them incorrectly. We could work around this by
1267 spacing the XD registers like the DR registers, but this would require
1268 additional memory in every compilation to hold larger register vectors.
1269 We could hold SFmode / SCmode values in XD registers, but that
1270 would require a tertiary reload when reloading from / to memory,
1271 and a secondary reload to reload from / to general regs; that
1272 seems to be a loosing proposition. */
1273 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1274 it won't be ferried through GP registers first. */
1275 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1276 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1277 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1278 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1279 ? 1 \
1280 : (MODE) == V2SFmode \
1281 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1282 || GENERAL_REGISTER_P (REGNO)) \
1283 : (MODE) == V4SFmode \
1284 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1285 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
1286 : (MODE) == V16SFmode \
1287 ? (TARGET_SHMEDIA \
1288 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1289 : (REGNO) == FIRST_XD_REG) \
1290 : FP_REGISTER_P (REGNO) \
1291 ? ((MODE) == SFmode || (MODE) == SImode \
1292 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1293 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1294 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1295 || (MODE) == V2SFmode || (MODE) == TImode))) \
1296 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
1297 : XD_REGISTER_P (REGNO) \
1298 ? (MODE) == DFmode \
1299 : TARGET_REGISTER_P (REGNO) \
1300 ? ((MODE) == DImode || (MODE) == SImode) \
1301 : (REGNO) == PR_REG ? (MODE) == SImode \
1302 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1303 : 1)
1304
1305 /* Value is 1 if it is a good idea to tie two pseudo registers
1306 when one has mode MODE1 and one has mode MODE2.
1307 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1308 for any hard reg, then this must be 0 for correct output.
1309 That's the case for xd registers: we don't hold SFmode values in
1310 them, so we can't tie an SFmode pseudos with one in another
1311 floating-point mode. */
1312
1313 #define MODES_TIEABLE_P(MODE1, MODE2) \
1314 ((MODE1) == (MODE2) \
1315 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1316 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1317 && (GET_MODE_SIZE (MODE2) <= 4)) \
1318 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1319
1320 /* A C expression that is nonzero if hard register NEW_REG can be
1321 considered for use as a rename register for OLD_REG register */
1322
1323 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1324 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1325
1326 /* Specify the registers used for certain standard purposes.
1327 The values of these macros are register numbers. */
1328
1329 /* Define this if the program counter is overloaded on a register. */
1330 /* #define PC_REGNUM 15*/
1331
1332 /* Register to use for pushing function arguments. */
1333 #define STACK_POINTER_REGNUM SP_REG
1334
1335 /* Base register for access to local variables of the function. */
1336 #define FRAME_POINTER_REGNUM FP_REG
1337
1338 /* Fake register that holds the address on the stack of the
1339 current function's return address. */
1340 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1341
1342 /* Register to hold the addressing base for position independent
1343 code access to data items. */
1344 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1345
1346 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1347
1348 /* Value should be nonzero if functions must have frame pointers.
1349 Zero means the frame pointer need not be set up (and parms may be accessed
1350 via the stack pointer) in functions that seem suitable. */
1351
1352 #define FRAME_POINTER_REQUIRED 0
1353
1354 /* Definitions for register eliminations.
1355
1356 We have three registers that can be eliminated on the SH. First, the
1357 frame pointer register can often be eliminated in favor of the stack
1358 pointer register. Secondly, the argument pointer register can always be
1359 eliminated; it is replaced with either the stack or frame pointer.
1360 Third, there is the return address pointer, which can also be replaced
1361 with either the stack or the frame pointer. */
1362
1363 /* This is an array of structures. Each structure initializes one pair
1364 of eliminable registers. The "from" register number is given first,
1365 followed by "to". Eliminations of the same "from" register are listed
1366 in order of preference. */
1367
1368 /* If you add any registers here that are not actually hard registers,
1369 and that have any alternative of elimination that doesn't always
1370 apply, you need to amend calc_live_regs to exclude it, because
1371 reload spills all eliminable registers where it sees an
1372 can_eliminate == 0 entry, thus making them 'live' .
1373 If you add any hard registers that can be eliminated in different
1374 ways, you have to patch reload to spill them only when all alternatives
1375 of elimination fail. */
1376
1377 #define ELIMINABLE_REGS \
1378 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1379 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1380 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1381 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1382 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1383
1384 /* Given FROM and TO register numbers, say whether this elimination
1385 is allowed. */
1386 #define CAN_ELIMINATE(FROM, TO) \
1387 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1388
1389 /* Define the offset between two registers, one to be eliminated, and the other
1390 its replacement, at the start of a routine. */
1391
1392 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1393 OFFSET = initial_elimination_offset ((FROM), (TO))
1394
1395 /* Base register for access to arguments of the function. */
1396 #define ARG_POINTER_REGNUM AP_REG
1397
1398 /* Register in which the static-chain is passed to a function. */
1399 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1400
1401 /* Don't default to pcc-struct-return, because we have already specified
1402 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1403 target hook. */
1404
1405 #define DEFAULT_PCC_STRUCT_RETURN 0
1406
1407 #define SHMEDIA_REGS_STACK_ADJUST() \
1408 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1409 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1410 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1411 : 0)
1412
1413 \f
1414 /* Define the classes of registers for register constraints in the
1415 machine description. Also define ranges of constants.
1416
1417 One of the classes must always be named ALL_REGS and include all hard regs.
1418 If there is more than one class, another class must be named NO_REGS
1419 and contain no registers.
1420
1421 The name GENERAL_REGS must be the name of a class (or an alias for
1422 another name such as ALL_REGS). This is the class of registers
1423 that is allowed by "g" or "r" in a register constraint.
1424 Also, registers outside this class are allocated only when
1425 instructions express preferences for them.
1426
1427 The classes must be numbered in nondecreasing order; that is,
1428 a larger-numbered class must never be contained completely
1429 in a smaller-numbered class.
1430
1431 For any two classes, it is very desirable that there be another
1432 class that represents their union. */
1433
1434 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1435 be used as the destination of some of the arithmetic ops. There are
1436 also some special purpose registers; the T bit register, the
1437 Procedure Return Register and the Multiply Accumulate Registers. */
1438 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1439 reg_class_subunion. We don't want to have an actual union class
1440 of these, because it would only be used when both classes are calculated
1441 to give the same cost, but there is only one FPUL register.
1442 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1443 applying to the actual instruction alternative considered. E.g., the
1444 y/r alternative of movsi_ie is considered to have no more cost that
1445 the r/r alternative, which is patently untrue. */
1446
1447 enum reg_class
1448 {
1449 NO_REGS,
1450 R0_REGS,
1451 PR_REGS,
1452 T_REGS,
1453 MAC_REGS,
1454 FPUL_REGS,
1455 SIBCALL_REGS,
1456 GENERAL_REGS,
1457 FP0_REGS,
1458 FP_REGS,
1459 DF_HI_REGS,
1460 DF_REGS,
1461 FPSCR_REGS,
1462 GENERAL_FP_REGS,
1463 TARGET_REGS,
1464 ALL_REGS,
1465 LIM_REG_CLASSES
1466 };
1467
1468 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1469
1470 /* Give names of register classes as strings for dump file. */
1471 #define REG_CLASS_NAMES \
1472 { \
1473 "NO_REGS", \
1474 "R0_REGS", \
1475 "PR_REGS", \
1476 "T_REGS", \
1477 "MAC_REGS", \
1478 "FPUL_REGS", \
1479 "SIBCALL_REGS", \
1480 "GENERAL_REGS", \
1481 "FP0_REGS", \
1482 "FP_REGS", \
1483 "DF_HI_REGS", \
1484 "DF_REGS", \
1485 "FPSCR_REGS", \
1486 "GENERAL_FP_REGS", \
1487 "TARGET_REGS", \
1488 "ALL_REGS", \
1489 }
1490
1491 /* Define which registers fit in which classes.
1492 This is an initializer for a vector of HARD_REG_SET
1493 of length N_REG_CLASSES. */
1494
1495 #define REG_CLASS_CONTENTS \
1496 { \
1497 /* NO_REGS: */ \
1498 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1499 /* R0_REGS: */ \
1500 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1501 /* PR_REGS: */ \
1502 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1503 /* T_REGS: */ \
1504 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1505 /* MAC_REGS: */ \
1506 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1507 /* FPUL_REGS: */ \
1508 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1509 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1510 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1511 /* GENERAL_REGS: */ \
1512 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1513 /* FP0_REGS: */ \
1514 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1515 /* FP_REGS: */ \
1516 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1517 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1518 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1519 /* DF_REGS: */ \
1520 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1521 /* FPSCR_REGS: */ \
1522 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1523 /* GENERAL_FP_REGS: */ \
1524 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1525 /* TARGET_REGS: */ \
1526 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1527 /* ALL_REGS: */ \
1528 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1529 }
1530
1531 /* The same information, inverted:
1532 Return the class number of the smallest class containing
1533 reg number REGNO. This could be a conditional expression
1534 or could index an array. */
1535
1536 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1537 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1538
1539 /* When defined, the compiler allows registers explicitly used in the
1540 rtl to be used as spill registers but prevents the compiler from
1541 extending the lifetime of these registers. */
1542
1543 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1544
1545 /* The order in which register should be allocated. */
1546 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1547 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1548 spilled or used otherwise, we better have the FP_REGS allocated first. */
1549 #define REG_ALLOC_ORDER \
1550 {/* Caller-saved FPRs */ \
1551 65, 66, 67, 68, 69, 70, 71, 64, \
1552 72, 73, 74, 75, 80, 81, 82, 83, \
1553 84, 85, 86, 87, 88, 89, 90, 91, \
1554 92, 93, 94, 95, 96, 97, 98, 99, \
1555 /* Callee-saved FPRs */ \
1556 76, 77, 78, 79,100,101,102,103, \
1557 104,105,106,107,108,109,110,111, \
1558 112,113,114,115,116,117,118,119, \
1559 120,121,122,123,124,125,126,127, \
1560 136,137,138,139,140,141,142,143, \
1561 /* FPSCR */ 151, \
1562 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1563 1, 2, 3, 7, 6, 5, 4, 0, \
1564 8, 9, 17, 19, 20, 21, 22, 23, \
1565 36, 37, 38, 39, 40, 41, 42, 43, \
1566 60, 61, 62, \
1567 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1568 10, 11, 12, 13, 14, 18, \
1569 /* SH5 callee-saved GPRs */ \
1570 28, 29, 30, 31, 32, 33, 34, 35, \
1571 44, 45, 46, 47, 48, 49, 50, 51, \
1572 52, 53, 54, 55, 56, 57, 58, 59, \
1573 /* FPUL */ 150, \
1574 /* SH5 branch target registers */ \
1575 128,129,130,131,132,133,134,135, \
1576 /* Fixed registers */ \
1577 15, 16, 24, 25, 26, 27, 63,144, \
1578 145,146,147,148,149,152 }
1579
1580 /* The class value for index registers, and the one for base regs. */
1581 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1582 #define BASE_REG_CLASS GENERAL_REGS
1583
1584 /* Get reg_class from a letter such as appears in the machine
1585 description. */
1586 extern enum reg_class reg_class_from_letter[];
1587
1588 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1589 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1590 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1591 \f
1592 /* Overview of uppercase letter constraints:
1593 A: Addresses (constraint len == 3)
1594 Ac4: sh4 cache operations
1595 Ac5: sh5 cache operations
1596 Bxx: miscellaneous constraints
1597 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1598 fldi0 / fldi0 cases
1599 C: Constants other than only CONST_INT (constraint len == 3)
1600 C16: 16 bit constant, literal or symbolic
1601 Csy: label or symbol
1602 Cpg: non-explicit constants that can be directly loaded into a general
1603 purpose register in PIC code. like 's' except we don't allow
1604 PIC_DIRECT_ADDR_P
1605 IJKLMNOP: CONT_INT constants
1606 Ixx: signed xx bit
1607 J16: 0xffffffff00000000 | 0x00000000ffffffff
1608 Kxx: unsigned xx bit
1609 M: 1
1610 N: 0
1611 P27: 1 | 2 | 8 | 16
1612 Q: pc relative load operand
1613 Rxx: reserved for exotic register classes.
1614 S: extra memory (storage) constraints (constraint len == 3)
1615 Sua: unaligned memory operations
1616 W: vector
1617 Z: zero in any mode
1618
1619 unused CONST_INT constraint letters: LO
1620 unused EXTRA_CONSTRAINT letters: D T U Y */
1621
1622 #if 1 /* check that the transition went well. */
1623 #define CONSTRAINT_LEN(C,STR) \
1624 (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
1625 || (C) == 'Y' \
1626 || ((C) == 'I' \
1627 && (((STR)[1] != '0' && (STR)[1] != '1' && (STR)[1] != '2') \
1628 || (STR)[2] < '0' || (STR)[2] > '9')) \
1629 || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
1630 || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
1631 || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
1632 || ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
1633 ? -1 \
1634 : ((C) == 'A' || (C) == 'B' || (C) == 'C' \
1635 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1636 || (C) == 'R' || (C) == 'S') \
1637 ? 3 \
1638 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1639 #else
1640 #define CONSTRAINT_LEN(C,STR) \
1641 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1642 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1643 || (C) == 'R' || (C) == 'S') \
1644 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1645 #endif
1646
1647 /* The letters I, J, K, L and M in a register constraint string
1648 can be used to stand for particular ranges of immediate operands.
1649 This macro defines what the ranges are.
1650 C is the letter, and VALUE is a constant value.
1651 Return 1 if VALUE is in the range specified by C.
1652 I08: arithmetic operand -127..128, as used in add, sub, etc
1653 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1654 P27: shift operand 1,2,8 or 16
1655 K08: logical operand 0..255, as used in and, or, etc.
1656 M: constant 1
1657 N: constant 0
1658 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1659 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1660 */
1661
1662 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1663 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1664 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1665 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1666 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1667 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1668 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1669 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1670 #define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
1671 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \
1672 && TARGET_SH2A)
1673 #define CONST_OK_FOR_I(VALUE, STR) \
1674 ((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
1675 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1676 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1677 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1678 : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
1679 : 0)
1680
1681 #define CONST_OK_FOR_J16(VALUE) \
1682 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1683 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1684 #define CONST_OK_FOR_J(VALUE, STR) \
1685 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1686 : 0)
1687
1688 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1689 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1690 #define CONST_OK_FOR_K(VALUE, STR) \
1691 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1692 : 0)
1693 #define CONST_OK_FOR_P27(VALUE) \
1694 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1695 #define CONST_OK_FOR_P(VALUE, STR) \
1696 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1697 : 0)
1698 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1699 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1700 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1701 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1702 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1703 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1704 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1705 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1706 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1707 : 0)
1708
1709 /* Similar, but for floating constants, and defining letters G and H.
1710 Here VALUE is the CONST_DOUBLE rtx itself. */
1711
1712 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1713 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1714 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1715 : (C) == 'F')
1716
1717 /* Given an rtx X being reloaded into a reg required to be
1718 in class CLASS, return the class of reg to actually use.
1719 In general this is just CLASS; but on some machines
1720 in some cases it is preferable to use a more restrictive class. */
1721
1722 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1723 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1724 && (GET_CODE (X) == CONST_DOUBLE \
1725 || GET_CODE (X) == SYMBOL_REF) \
1726 ? GENERAL_REGS \
1727 : (CLASS)) \
1728
1729 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1730 ((((REGCLASS_HAS_FP_REG (CLASS) \
1731 && (GET_CODE (X) == REG \
1732 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1733 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1734 && TARGET_FMOVD)))) \
1735 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1736 && GET_CODE (X) == REG \
1737 && FP_REGISTER_P (REGNO (X)))) \
1738 && ! TARGET_SHMEDIA \
1739 && ((MODE) == SFmode || (MODE) == SImode)) \
1740 ? FPUL_REGS \
1741 : (((CLASS) == FPUL_REGS \
1742 || (REGCLASS_HAS_FP_REG (CLASS) \
1743 && ! TARGET_SHMEDIA && MODE == SImode)) \
1744 && (GET_CODE (X) == MEM \
1745 || (GET_CODE (X) == REG \
1746 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1747 || REGNO (X) == T_REG \
1748 || system_reg_operand (X, VOIDmode))))) \
1749 ? GENERAL_REGS \
1750 : ((CLASS) == TARGET_REGS \
1751 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1752 ? ((target_operand ((X), (MODE)) \
1753 && ! target_reg_operand ((X), (MODE))) \
1754 ? NO_REGS : GENERAL_REGS) \
1755 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1756 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1757 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1758 ? GENERAL_REGS \
1759 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1760 && TARGET_REGISTER_P (REGNO (X))) \
1761 ? GENERAL_REGS : NO_REGS)
1762
1763 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1764 ((REGCLASS_HAS_FP_REG (CLASS) \
1765 && ! TARGET_SHMEDIA \
1766 && immediate_operand ((X), (MODE)) \
1767 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1768 && (MODE) == SFmode && fldi_ok ())) \
1769 ? R0_REGS \
1770 : (CLASS == FPUL_REGS \
1771 && ((GET_CODE (X) == REG \
1772 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1773 || REGNO (X) == T_REG)) \
1774 || GET_CODE (X) == PLUS)) \
1775 ? GENERAL_REGS \
1776 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1777 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1778 ? GENERAL_REGS \
1779 : R0_REGS) \
1780 : (CLASS == FPSCR_REGS \
1781 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1782 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1783 ? GENERAL_REGS \
1784 : (REGCLASS_HAS_FP_REG (CLASS) \
1785 && TARGET_SHMEDIA \
1786 && immediate_operand ((X), (MODE)) \
1787 && (X) != CONST0_RTX (GET_MODE (X)) \
1788 && GET_MODE (X) != V4SFmode) \
1789 ? GENERAL_REGS \
1790 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1791
1792 /* Return the maximum number of consecutive registers
1793 needed to represent mode MODE in a register of class CLASS.
1794
1795 If TARGET_SHMEDIA, we need two FP registers per word.
1796 Otherwise we will need at most one register per word. */
1797 #define CLASS_MAX_NREGS(CLASS, MODE) \
1798 (TARGET_SHMEDIA \
1799 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1800 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1801 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1802
1803 /* If defined, gives a class of registers that cannot be used as the
1804 operand of a SUBREG that changes the mode of the object illegally. */
1805 /* ??? We need to renumber the internal numbers for the frnn registers
1806 when in little endian in order to allow mode size changes. */
1807
1808 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1809 sh_cannot_change_mode_class (FROM, TO, CLASS)
1810 \f
1811 /* Stack layout; function entry, exit and calling. */
1812
1813 /* Define the number of registers that can hold parameters.
1814 These macros are used only in other macro definitions below. */
1815
1816 #define NPARM_REGS(MODE) \
1817 (TARGET_FPU_ANY && (MODE) == SFmode \
1818 ? (TARGET_SH5 ? 12 : 8) \
1819 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1820 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1821 ? (TARGET_SH5 ? 12 : 8) \
1822 : (TARGET_SH5 ? 8 : 4))
1823
1824 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1825 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1826
1827 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1828 #define FIRST_FP_RET_REG FIRST_FP_REG
1829
1830 /* Define this if pushing a word on the stack
1831 makes the stack pointer a smaller address. */
1832 #define STACK_GROWS_DOWNWARD
1833
1834 /* Define this macro if the addresses of local variable slots are at
1835 negative offsets from the frame pointer.
1836
1837 The SH only has positive indexes, so grow the frame up. */
1838 /* #define FRAME_GROWS_DOWNWARD */
1839
1840 /* Offset from the frame pointer to the first local variable slot to
1841 be allocated. */
1842 #define STARTING_FRAME_OFFSET 0
1843
1844 /* If we generate an insn to push BYTES bytes,
1845 this says how many the stack pointer really advances by. */
1846 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1847 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1848 do correct alignment. */
1849 #if 0
1850 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1851 #endif
1852
1853 /* Offset of first parameter from the argument pointer register value. */
1854 #define FIRST_PARM_OFFSET(FNDECL) 0
1855
1856 /* Value is the number of byte of arguments automatically
1857 popped when returning from a subroutine call.
1858 FUNDECL is the declaration node of the function (as a tree),
1859 FUNTYPE is the data type of the function (as a tree),
1860 or for a library call it is an identifier node for the subroutine name.
1861 SIZE is the number of bytes of arguments passed on the stack.
1862
1863 On the SH, the caller does not pop any of its arguments that were passed
1864 on the stack. */
1865 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1866
1867 /* Value is the number of bytes of arguments automatically popped when
1868 calling a subroutine.
1869 CUM is the accumulated argument list.
1870
1871 On SHcompact, the call trampoline pops arguments off the stack. */
1872 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1873
1874 /* Some subroutine macros specific to this machine. */
1875
1876 #define BASE_RETURN_VALUE_REG(MODE) \
1877 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1878 ? FIRST_FP_RET_REG \
1879 : TARGET_FPU_ANY && (MODE) == SCmode \
1880 ? FIRST_FP_RET_REG \
1881 : (TARGET_FPU_DOUBLE \
1882 && ((MODE) == DFmode || (MODE) == SFmode \
1883 || (MODE) == DCmode || (MODE) == SCmode )) \
1884 ? FIRST_FP_RET_REG \
1885 : FIRST_RET_REG)
1886
1887 #define BASE_ARG_REG(MODE) \
1888 ((TARGET_SH2E && ((MODE) == SFmode)) \
1889 ? FIRST_FP_PARM_REG \
1890 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1891 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1892 ? FIRST_FP_PARM_REG \
1893 : FIRST_PARM_REG)
1894
1895 /* Define how to find the value returned by a function.
1896 VALTYPE is the data type of the value (as a tree).
1897 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1898 otherwise, FUNC is 0.
1899 For the SH, this is like LIBCALL_VALUE, except that we must change the
1900 mode like PROMOTE_MODE does.
1901 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1902 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1903
1904 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1905 gen_rtx_REG ( \
1906 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1907 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1908 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1909 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1910 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1911 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1912 || TREE_CODE (VALTYPE) == REAL_TYPE \
1913 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1914 && sh_promote_prototypes (VALTYPE) \
1915 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1916 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1917
1918 /* Define how to find the value returned by a library function
1919 assuming the value has mode MODE. */
1920 #define LIBCALL_VALUE(MODE) \
1921 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1922
1923 /* 1 if N is a possible register number for a function value. */
1924 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1925 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1926 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1927
1928 /* 1 if N is a possible register number for function argument passing. */
1929 /* ??? There are some callers that pass REGNO as int, and others that pass
1930 it as unsigned. We get warnings unless we do casts everywhere. */
1931 #define FUNCTION_ARG_REGNO_P(REGNO) \
1932 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1933 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1934 || (TARGET_FPU_ANY \
1935 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1936 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1937 + NPARM_REGS (SFmode))))
1938 \f
1939 /* Define a data type for recording info about an argument list
1940 during the scan of that argument list. This data type should
1941 hold all necessary information about the function itself
1942 and about the args processed so far, enough to enable macros
1943 such as FUNCTION_ARG to determine where the next arg should go.
1944
1945 On SH, this is a single integer, which is a number of words
1946 of arguments scanned so far (including the invisible argument,
1947 if any, which holds the structure-value-address).
1948 Thus NARGREGS or more means all following args should go on the stack. */
1949
1950 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1951 struct sh_args {
1952 int arg_count[2];
1953 int force_mem;
1954 /* Nonzero if a prototype is available for the function. */
1955 int prototype_p;
1956 /* The number of an odd floating-point register, that should be used
1957 for the next argument of type float. */
1958 int free_single_fp_reg;
1959 /* Whether we're processing an outgoing function call. */
1960 int outgoing;
1961 /* The number of general-purpose registers that should have been
1962 used to pass partial arguments, that are passed totally on the
1963 stack. On SHcompact, a call trampoline will pop them off the
1964 stack before calling the actual function, and, if the called
1965 function is implemented in SHcompact mode, the incoming arguments
1966 decoder will push such arguments back onto the stack. For
1967 incoming arguments, STACK_REGS also takes into account other
1968 arguments passed by reference, that the decoder will also push
1969 onto the stack. */
1970 int stack_regs;
1971 /* The number of general-purpose registers that should have been
1972 used to pass arguments, if the arguments didn't have to be passed
1973 by reference. */
1974 int byref_regs;
1975 /* Set as by shcompact_byref if the current argument is to be passed
1976 by reference. */
1977 int byref;
1978
1979 /* call_cookie is a bitmask used by call expanders, as well as
1980 function prologue and epilogues, to allow SHcompact to comply
1981 with the SH5 32-bit ABI, that requires 64-bit registers to be
1982 used even though only the lower 32-bit half is visible in
1983 SHcompact mode. The strategy is to call SHmedia trampolines.
1984
1985 The alternatives for each of the argument-passing registers are
1986 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1987 contents from the address in it; (d) add 8 to it, storing the
1988 result in the next register, then (c); (e) copy it from some
1989 floating-point register,
1990
1991 Regarding copies from floating-point registers, r2 may only be
1992 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1993 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1994 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1995 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1996 dr10.
1997
1998 The bit mask is structured as follows:
1999
2000 - 1 bit to tell whether to set up a return trampoline.
2001
2002 - 3 bits to count the number consecutive registers to pop off the
2003 stack.
2004
2005 - 4 bits for each of r9, r8, r7 and r6.
2006
2007 - 3 bits for each of r5, r4, r3 and r2.
2008
2009 - 3 bits set to 0 (the most significant ones)
2010
2011 3 2 1 0
2012 1098 7654 3210 9876 5432 1098 7654 3210
2013 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
2014 2223 3344 4555 6666 7777 8888 9999 SSS-
2015
2016 - If F is set, the register must be copied from an FP register,
2017 whose number is encoded in the remaining bits.
2018
2019 - Else, if L is set, the register must be loaded from the address
2020 contained in it. If the P bit is *not* set, the address of the
2021 following dword should be computed first, and stored in the
2022 following register.
2023
2024 - Else, if P is set, the register alone should be popped off the
2025 stack.
2026
2027 - After all this processing, the number of registers represented
2028 in SSS will be popped off the stack. This is an optimization
2029 for pushing/popping consecutive registers, typically used for
2030 varargs and large arguments partially passed in registers.
2031
2032 - If T is set, a return trampoline will be set up for 64-bit
2033 return values to be split into 2 32-bit registers. */
2034 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
2035 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
2036 #define CALL_COOKIE_STACKSEQ_SHIFT 1
2037 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
2038 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
2039 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
2040 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
2041 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
2042 #define CALL_COOKIE_INT_REG(REG, VAL) \
2043 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
2044 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
2045 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
2046 long call_cookie;
2047
2048 /* This is set to nonzero when the call in question must use the Renesas ABI,
2049 even without the -mrenesas option. */
2050 int renesas_abi;
2051 };
2052
2053 #define CUMULATIVE_ARGS struct sh_args
2054
2055 #define GET_SH_ARG_CLASS(MODE) \
2056 ((TARGET_FPU_ANY && (MODE) == SFmode) \
2057 ? SH_ARG_FLOAT \
2058 /* There's no mention of complex float types in the SH5 ABI, so we
2059 should presumably handle them as aggregate types. */ \
2060 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
2061 ? SH_ARG_INT \
2062 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2063 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
2064 ? SH_ARG_FLOAT : SH_ARG_INT)
2065
2066 #define ROUND_ADVANCE(SIZE) \
2067 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2068
2069 /* Round a register number up to a proper boundary for an arg of mode
2070 MODE.
2071
2072 The SH doesn't care about double alignment, so we only
2073 round doubles to even regs when asked to explicitly. */
2074
2075 #define ROUND_REG(CUM, MODE) \
2076 (((TARGET_ALIGN_DOUBLE \
2077 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
2078 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
2079 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
2080 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
2081 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
2082 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
2083
2084 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2085 for a call to a function whose data type is FNTYPE.
2086 For a library call, FNTYPE is 0.
2087
2088 On SH, the offset always starts at 0: the first parm reg is always
2089 the same reg for a given argument class.
2090
2091 For TARGET_HITACHI, the structure value pointer is passed in memory. */
2092
2093 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
2094 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
2095
2096 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
2097 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
2098
2099 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2100 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
2101 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2102 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
2103
2104 /* Return boolean indicating arg of mode MODE will be passed in a reg.
2105 This macro is only used in this file. */
2106
2107 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2108 (((TYPE) == 0 \
2109 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2110 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2111 || ! (AGGREGATE_TYPE_P (TYPE) \
2112 || (!TARGET_FPU_ANY \
2113 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2114 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2115 && ! (CUM).force_mem \
2116 && (TARGET_SH2E \
2117 ? ((MODE) == BLKmode \
2118 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2119 + int_size_in_bytes (TYPE)) \
2120 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2121 : ((ROUND_REG((CUM), (MODE)) \
2122 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2123 <= NPARM_REGS (MODE))) \
2124 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2125
2126 /* By accident we got stuck with passing SCmode on SH4 little endian
2127 in two registers that are nominally successive - which is different from
2128 two single SFmode values, where we take endianness translation into
2129 account. That does not work at all if an odd number of registers is
2130 already in use, so that got fixed, but library functions are still more
2131 likely to use complex numbers without mixing them with SFmode arguments
2132 (which in C would have to be structures), so for the sake of ABI
2133 compatibility the way SCmode values are passed when an even number of
2134 FP registers is in use remains different from a pair of SFmode values for
2135 now.
2136 I.e.:
2137 foo (double); a: fr5,fr4
2138 foo (float a, float b); a: fr5 b: fr4
2139 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2140 this should be the other way round...
2141 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2142 #define FUNCTION_ARG_SCmode_WART 1
2143
2144 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2145 register in SHcompact mode, it must be padded in the most
2146 significant end. This means that passing it by reference wouldn't
2147 pad properly on a big-endian machine. In this particular case, we
2148 pass this argument on the stack, in a way that the call trampoline
2149 will load its value into the appropriate register. */
2150 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2151 ((MODE) == BLKmode \
2152 && TARGET_SHCOMPACT \
2153 && ! TARGET_LITTLE_ENDIAN \
2154 && int_size_in_bytes (TYPE) > 4 \
2155 && int_size_in_bytes (TYPE) < 8)
2156
2157 /* Minimum alignment for an argument to be passed by callee-copy
2158 reference. We need such arguments to be aligned to 8 byte
2159 boundaries, because they'll be loaded using quad loads. */
2160 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2161
2162 /* The SH5 ABI requires floating-point arguments to be passed to
2163 functions without a prototype in both an FP register and a regular
2164 register or the stack. When passing the argument in both FP and
2165 general-purpose registers, list the FP register first. */
2166 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2167 (gen_rtx_PARALLEL \
2168 ((MODE), \
2169 gen_rtvec (2, \
2170 gen_rtx_EXPR_LIST \
2171 (VOIDmode, \
2172 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2173 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2174 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2175 : NULL_RTX), \
2176 const0_rtx), \
2177 gen_rtx_EXPR_LIST \
2178 (VOIDmode, \
2179 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2180 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2181 + (CUM).arg_count[(int) SH_ARG_INT]) \
2182 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2183 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2184 const0_rtx))))
2185
2186 /* The SH5 ABI requires regular registers or stack slots to be
2187 reserved for floating-point arguments. Registers are taken care of
2188 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2189 Unfortunately, there's no way to just reserve a stack slot, so
2190 we'll end up needlessly storing a copy of the argument in the
2191 stack. For incoming arguments, however, the PARALLEL will be
2192 optimized to the register-only form, and the value in the stack
2193 slot won't be used at all. */
2194 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2195 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2196 ? gen_rtx_REG ((MODE), (REG)) \
2197 : gen_rtx_PARALLEL ((MODE), \
2198 gen_rtvec (2, \
2199 gen_rtx_EXPR_LIST \
2200 (VOIDmode, NULL_RTX, \
2201 const0_rtx), \
2202 gen_rtx_EXPR_LIST \
2203 (VOIDmode, gen_rtx_REG ((MODE), \
2204 (REG)), \
2205 const0_rtx))))
2206
2207 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2208 (TARGET_SH5 \
2209 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2210 || (MODE) == DCmode) \
2211 && ((CUM).arg_count[(int) SH_ARG_INT] \
2212 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2213
2214 /* Perform any needed actions needed for a function that is receiving a
2215 variable number of arguments. */
2216
2217 /* Implement `va_start' for varargs and stdarg. */
2218 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2219 sh_va_start (valist, nextarg)
2220
2221 /* Call the function profiler with a given profile label.
2222 We use two .aligns, so as to make sure that both the .long is aligned
2223 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2224 from the trapa instruction. */
2225
2226 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2227 { \
2228 fprintf((STREAM), "\t.align\t2\n"); \
2229 fprintf((STREAM), "\ttrapa\t#33\n"); \
2230 fprintf((STREAM), "\t.align\t2\n"); \
2231 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2232 }
2233
2234 /* Define this macro if the code for function profiling should come
2235 before the function prologue. Normally, the profiling code comes
2236 after. */
2237
2238 #define PROFILE_BEFORE_PROLOGUE
2239
2240 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2241 the stack pointer does not matter. The value is tested only in
2242 functions that have frame pointers.
2243 No definition is equivalent to always zero. */
2244
2245 #define EXIT_IGNORE_STACK 1
2246
2247 /*
2248 On the SH, the trampoline looks like
2249 2 0002 D202 mov.l l2,r2
2250 1 0000 D301 mov.l l1,r3
2251 3 0004 422B jmp @r2
2252 4 0006 0009 nop
2253 5 0008 00000000 l1: .long area
2254 6 000c 00000000 l2: .long function */
2255
2256 /* Length in units of the trampoline for entering a nested function. */
2257 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2258
2259 /* Alignment required for a trampoline in bits . */
2260 #define TRAMPOLINE_ALIGNMENT \
2261 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2262 : TARGET_SHMEDIA ? 256 : 64)
2263
2264 /* Emit RTL insns to initialize the variable parts of a trampoline.
2265 FNADDR is an RTX for the address of the function's pure code.
2266 CXT is an RTX for the static chain value for the function. */
2267
2268 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2269 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2270
2271 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2272
2273 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2274 { \
2275 if (TARGET_SHMEDIA) \
2276 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2277 gen_reg_rtx (Pmode), 0, \
2278 OPTAB_LIB_WIDEN); \
2279 } while (0)
2280
2281 /* A C expression whose value is RTL representing the value of the return
2282 address for the frame COUNT steps up from the current frame.
2283 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2284 can ignore COUNT. */
2285
2286 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2287 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2288
2289 /* A C expression whose value is RTL representing the location of the
2290 incoming return address at the beginning of any function, before the
2291 prologue. This RTL is either a REG, indicating that the return
2292 value is saved in REG, or a MEM representing a location in
2293 the stack. */
2294 #define INCOMING_RETURN_ADDR_RTX \
2295 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2296 \f
2297 /* Addressing modes, and classification of registers for them. */
2298 #define HAVE_POST_INCREMENT TARGET_SH1
2299 #define HAVE_PRE_DECREMENT TARGET_SH1
2300
2301 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2302 ? 0 : TARGET_SH1)
2303 #define USE_LOAD_PRE_DECREMENT(mode) 0
2304 #define USE_STORE_POST_INCREMENT(mode) 0
2305 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2306 ? 0 : TARGET_SH1)
2307
2308 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2309 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2310 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2311
2312 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2313 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2314 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2315
2316 /* Macros to check register numbers against specific register classes. */
2317
2318 /* These assume that REGNO is a hard or pseudo reg number.
2319 They give nonzero only if REGNO is a hard reg of the suitable class
2320 or a pseudo reg currently allocated to a suitable hard reg.
2321 Since they use reg_renumber, they are safe only once reg_renumber
2322 has been allocated, which happens in local-alloc.c. */
2323
2324 #define REGNO_OK_FOR_BASE_P(REGNO) \
2325 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2326 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2327 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2328 (TARGET_SHMEDIA \
2329 ? (GENERAL_REGISTER_P (REGNO) \
2330 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2331 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2332
2333 /* Maximum number of registers that can appear in a valid memory
2334 address. */
2335
2336 #define MAX_REGS_PER_ADDRESS 2
2337
2338 /* Recognize any constant value that is a valid address. */
2339
2340 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2341
2342 /* Nonzero if the constant value X is a legitimate general operand. */
2343
2344 #define LEGITIMATE_CONSTANT_P(X) \
2345 (TARGET_SHMEDIA \
2346 ? ((GET_MODE (X) != DFmode \
2347 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2348 || (X) == CONST0_RTX (GET_MODE (X)) \
2349 || ! TARGET_SHMEDIA_FPU \
2350 || TARGET_SHMEDIA64) \
2351 : (GET_CODE (X) != CONST_DOUBLE \
2352 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2353 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2354
2355 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2356 and check its validity for a certain class.
2357 We have two alternate definitions for each of them.
2358 The usual definition accepts all pseudo regs; the other rejects
2359 them unless they have been allocated suitable hard regs.
2360 The symbol REG_OK_STRICT causes the latter definition to be used. */
2361
2362 #ifndef REG_OK_STRICT
2363
2364 /* Nonzero if X is a hard reg that can be used as a base reg
2365 or if it is a pseudo reg. */
2366 #define REG_OK_FOR_BASE_P(X) \
2367 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2368
2369 /* Nonzero if X is a hard reg that can be used as an index
2370 or if it is a pseudo reg. */
2371 #define REG_OK_FOR_INDEX_P(X) \
2372 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2373 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2374
2375 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2376 or if X is a pseudo reg. */
2377 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2378 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2379 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2380
2381 #else
2382
2383 /* Nonzero if X is a hard reg that can be used as a base reg. */
2384 #define REG_OK_FOR_BASE_P(X) \
2385 REGNO_OK_FOR_BASE_P (REGNO (X))
2386
2387 /* Nonzero if X is a hard reg that can be used as an index. */
2388 #define REG_OK_FOR_INDEX_P(X) \
2389 REGNO_OK_FOR_INDEX_P (REGNO (X))
2390
2391 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2392 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2393 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2394
2395 #endif
2396
2397 /* The 'Q' constraint is a pc relative load operand. */
2398 #define EXTRA_CONSTRAINT_Q(OP) \
2399 (GET_CODE (OP) == MEM \
2400 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2401 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2402 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2403 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2404 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2405
2406 /* Extra address constraints. */
2407 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2408
2409 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2410 operand is not SCRATCH (i.e. REG) then R0 is probably being
2411 used, hence mova is being used, hence do not select this pattern */
2412 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2413 #define EXTRA_CONSTRAINT_B(OP, STR) \
2414 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2415 : 0)
2416
2417 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2418 #define EXTRA_CONSTRAINT_C16(OP) \
2419 (GET_CODE (OP) == CONST \
2420 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2421 && GET_MODE (XEXP ((OP), 0)) == DImode \
2422 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2423 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2424 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2425 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2426 && (MOVI_SHORI_BASE_OPERAND_P \
2427 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2428 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2429 1)) == CONST_INT)))
2430
2431 /* Check whether OP is a datalabel unspec. */
2432 #define DATALABEL_REF_NO_CONST_P(OP) \
2433 (GET_CODE (OP) == UNSPEC \
2434 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2435 && XVECLEN ((OP), 0) == 1 \
2436 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2437 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2438
2439 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2440 CONST. */
2441 #define DATALABEL_REF_P(OP) \
2442 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2443 || DATALABEL_REF_NO_CONST_P (OP))
2444
2445 #define GOT_ENTRY_P(OP) \
2446 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2447 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2448
2449 #define GOTPLT_ENTRY_P(OP) \
2450 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2451 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2452
2453 #define UNSPEC_GOTOFF_P(OP) \
2454 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2455
2456 #define GOTOFF_P(OP) \
2457 (GET_CODE (OP) == CONST \
2458 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2459 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2460 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2461 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2462
2463 #define PIC_ADDR_P(OP) \
2464 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2465 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2466
2467 #define PIC_OFFSET_P(OP) \
2468 (PIC_ADDR_P (OP) \
2469 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2470 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2471
2472 #define PIC_DIRECT_ADDR_P(OP) \
2473 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2474
2475 #define NON_PIC_REFERENCE_P(OP) \
2476 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2477 || DATALABEL_REF_P (OP) \
2478 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2479 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2480 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2481 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2482
2483 #define PIC_REFERENCE_P(OP) \
2484 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2485 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2486
2487 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2488 (flag_pic \
2489 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2490 || PIC_OFFSET_P (OP)) \
2491 : NON_PIC_REFERENCE_P (OP))
2492
2493 /* The `Csy' constraint is a label or a symbol. */
2494 #define EXTRA_CONSTRAINT_Csy(OP) \
2495 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2496
2497 /* A zero in any shape or form. */
2498 #define EXTRA_CONSTRAINT_Z(OP) \
2499 ((OP) == CONST0_RTX (GET_MODE (OP)))
2500
2501 /* Any vector constant we can handle. */
2502 #define EXTRA_CONSTRAINT_W(OP) \
2503 (GET_CODE (OP) == CONST_VECTOR \
2504 && (sh_rep_vec ((OP), VOIDmode) \
2505 || (HOST_BITS_PER_WIDE_INT >= 64 \
2506 ? sh_const_vec ((OP), VOIDmode) \
2507 : sh_1el_vec ((OP), VOIDmode))))
2508
2509 /* A non-explicit constant that can be loaded directly into a general purpose
2510 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2511 #define EXTRA_CONSTRAINT_Cpg(OP) \
2512 (CONSTANT_P (OP) \
2513 && GET_CODE (OP) != CONST_INT \
2514 && GET_CODE (OP) != CONST_DOUBLE \
2515 && (!flag_pic \
2516 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2517 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2518 && GET_CODE (OP) != LABEL_REF)))
2519 #define EXTRA_CONSTRAINT_C(OP, STR) \
2520 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2521 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2522 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2523 : 0)
2524
2525 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2526 #define EXTRA_CONSTRAINT_Sr0(OP) \
2527 (memory_operand((OP), GET_MODE (OP)) \
2528 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2529 #define EXTRA_CONSTRAINT_Sua(OP) \
2530 (memory_operand((OP), GET_MODE (OP)) \
2531 && GET_CODE (XEXP (OP, 0)) != PLUS)
2532 #define EXTRA_CONSTRAINT_S(OP, STR) \
2533 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2534 : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
2535 : 0)
2536
2537 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2538 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2539 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2540 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2541 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2542 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2543 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2544 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2545 : 0)
2546 \f
2547 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2548 that is a valid memory address for an instruction.
2549 The MODE argument is the machine mode for the MEM expression
2550 that wants to use this address. */
2551
2552 #define MODE_DISP_OK_4(X,MODE) \
2553 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2554 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2555
2556 #define MODE_DISP_OK_8(X,MODE) \
2557 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2558 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2559
2560 #undef MODE_DISP_OK_4
2561 #define MODE_DISP_OK_4(X,MODE) \
2562 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2563 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2564 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2565 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2566
2567 #undef MODE_DISP_OK_8
2568 #define MODE_DISP_OK_8(X,MODE) \
2569 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2570 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2571 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2572 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2573
2574 #define BASE_REGISTER_RTX_P(X) \
2575 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2576 || (GET_CODE (X) == SUBREG \
2577 && GET_CODE (SUBREG_REG (X)) == REG \
2578 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2579
2580 /* Since this must be r0, which is a single register class, we must check
2581 SUBREGs more carefully, to be sure that we don't accept one that extends
2582 outside the class. */
2583 #define INDEX_REGISTER_RTX_P(X) \
2584 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2585 || (GET_CODE (X) == SUBREG \
2586 && GET_CODE (SUBREG_REG (X)) == REG \
2587 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2588
2589 /* Jump to LABEL if X is a valid address RTX. This must also take
2590 REG_OK_STRICT into account when deciding about valid registers, but it uses
2591 the above macros so we are in luck.
2592
2593 Allow REG
2594 REG+disp
2595 REG+r0
2596 REG++
2597 --REG */
2598
2599 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2600 into the FRx registers. We implement this by setting the maximum offset
2601 to zero when the value is SFmode. This also restricts loading of SFmode
2602 values into the integer registers, but that can't be helped. */
2603
2604 /* The SH allows a displacement in a QI or HI amode, but only when the
2605 other operand is R0. GCC doesn't handle this very well, so we forgo
2606 all of that.
2607
2608 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2609 DI can be any number 0..60. */
2610
2611 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2612 do { \
2613 if (GET_CODE (OP) == CONST_INT) \
2614 { \
2615 if (TARGET_SHMEDIA) \
2616 { \
2617 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2618 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2619 && INTVAL (OP) >= -512 * MODE_SIZE \
2620 && INTVAL (OP) < 512 * MODE_SIZE) \
2621 goto LABEL; \
2622 else \
2623 break; \
2624 } \
2625 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2626 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2627 } \
2628 } while(0)
2629
2630 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2631 { \
2632 if (BASE_REGISTER_RTX_P (X)) \
2633 goto LABEL; \
2634 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2635 && ! TARGET_SHMEDIA \
2636 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2637 goto LABEL; \
2638 else if (GET_CODE (X) == PLUS \
2639 && ((MODE) != PSImode || reload_completed)) \
2640 { \
2641 rtx xop0 = XEXP ((X), 0); \
2642 rtx xop1 = XEXP ((X), 1); \
2643 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2644 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2645 if (GET_MODE_SIZE (MODE) <= 4 \
2646 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2647 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && MODE == DFmode)) \
2648 { \
2649 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2650 goto LABEL; \
2651 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2652 goto LABEL; \
2653 } \
2654 } \
2655 }
2656 \f
2657 /* Try machine-dependent ways of modifying an illegitimate address
2658 to be legitimate. If we find one, return the new, valid address.
2659 This macro is used in only one place: `memory_address' in explow.c.
2660
2661 OLDX is the address as it was before break_out_memory_refs was called.
2662 In some cases it is useful to look at this to decide what needs to be done.
2663
2664 MODE and WIN are passed so that this macro can use
2665 GO_IF_LEGITIMATE_ADDRESS.
2666
2667 It is always safe for this macro to do nothing. It exists to recognize
2668 opportunities to optimize the output.
2669
2670 For the SH, if X is almost suitable for indexing, but the offset is
2671 out of range, convert it into a normal form so that cse has a chance
2672 of reducing the number of address registers used. */
2673
2674 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2675 { \
2676 if (flag_pic) \
2677 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2678 if (GET_CODE (X) == PLUS \
2679 && (GET_MODE_SIZE (MODE) == 4 \
2680 || GET_MODE_SIZE (MODE) == 8) \
2681 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2682 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2683 && ! TARGET_SHMEDIA \
2684 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2685 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2686 { \
2687 rtx index_rtx = XEXP ((X), 1); \
2688 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2689 rtx sum; \
2690 \
2691 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2692 /* On rare occasions, we might get an unaligned pointer \
2693 that is indexed in a way to give an aligned address. \
2694 Therefore, keep the lower two bits in offset_base. */ \
2695 /* Instead of offset_base 128..131 use 124..127, so that \
2696 simple add suffices. */ \
2697 if (offset > 127) \
2698 { \
2699 offset_base = ((offset + 4) & ~60) - 4; \
2700 } \
2701 else \
2702 offset_base = offset & ~60; \
2703 /* Sometimes the normal form does not suit DImode. We \
2704 could avoid that by using smaller ranges, but that \
2705 would give less optimized code when SImode is \
2706 prevalent. */ \
2707 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2708 { \
2709 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2710 GEN_INT (offset_base), NULL_RTX, 0, \
2711 OPTAB_LIB_WIDEN); \
2712 \
2713 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2714 goto WIN; \
2715 } \
2716 } \
2717 }
2718
2719 /* A C compound statement that attempts to replace X, which is an address
2720 that needs reloading, with a valid memory address for an operand of
2721 mode MODE. WIN is a C statement label elsewhere in the code.
2722
2723 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2724 of the address. That will allow inheritance of the address reloads. */
2725
2726 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2727 { \
2728 if (GET_CODE (X) == PLUS \
2729 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2730 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2731 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2732 && ! TARGET_SHMEDIA \
2733 && ! (TARGET_SH4 && (MODE) == DFmode) \
2734 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2735 { \
2736 rtx index_rtx = XEXP (X, 1); \
2737 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2738 rtx sum; \
2739 \
2740 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2741 { \
2742 push_reload (X, NULL_RTX, &X, NULL, \
2743 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2744 (TYPE)); \
2745 goto WIN; \
2746 } \
2747 if (TARGET_SH2E && MODE == SFmode) \
2748 { \
2749 X = copy_rtx (X); \
2750 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2751 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2752 (TYPE)); \
2753 goto WIN; \
2754 } \
2755 /* Instead of offset_base 128..131 use 124..127, so that \
2756 simple add suffices. */ \
2757 if (offset > 127) \
2758 { \
2759 offset_base = ((offset + 4) & ~60) - 4; \
2760 } \
2761 else \
2762 offset_base = offset & ~60; \
2763 /* Sometimes the normal form does not suit DImode. We \
2764 could avoid that by using smaller ranges, but that \
2765 would give less optimized code when SImode is \
2766 prevalent. */ \
2767 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2768 { \
2769 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2770 GEN_INT (offset_base)); \
2771 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2772 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2773 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2774 (TYPE)); \
2775 goto WIN; \
2776 } \
2777 } \
2778 /* We must re-recognize what we created before. */ \
2779 else if (GET_CODE (X) == PLUS \
2780 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2781 && GET_CODE (XEXP (X, 0)) == PLUS \
2782 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2783 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2784 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2785 && ! TARGET_SHMEDIA \
2786 && ! (TARGET_SH2E && MODE == SFmode)) \
2787 { \
2788 /* Because this address is so complex, we know it must have \
2789 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2790 it is already unshared, and needs no further unsharing. */ \
2791 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2792 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2793 goto WIN; \
2794 } \
2795 }
2796
2797 /* Go to LABEL if ADDR (a legitimate address expression)
2798 has an effect that depends on the machine mode it is used for.
2799
2800 ??? Strictly speaking, we should also include all indexed addressing,
2801 because the index scale factor is the length of the operand.
2802 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2803 high if we did that. So we rely on reload to fix things up. */
2804
2805 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2806 { \
2807 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2808 goto LABEL; \
2809 }
2810 \f
2811 /* Specify the machine mode that this machine uses
2812 for the index in the tablejump instruction. */
2813 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2814
2815 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2816 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2817 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2818 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2819 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2820 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2821 : SImode)
2822
2823 /* Define as C expression which evaluates to nonzero if the tablejump
2824 instruction expects the table to contain offsets from the address of the
2825 table.
2826 Do not define this if the table should contain absolute addresses. */
2827 #define CASE_VECTOR_PC_RELATIVE 1
2828
2829 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2830 #define FLOAT_TYPE_SIZE 32
2831
2832 /* Since the SH2e has only `float' support, it is desirable to make all
2833 floating point types equivalent to `float'. */
2834 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2835
2836 /* 'char' is signed by default. */
2837 #define DEFAULT_SIGNED_CHAR 1
2838
2839 /* The type of size_t unsigned int. */
2840 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2841
2842 #undef PTRDIFF_TYPE
2843 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2844
2845 #define WCHAR_TYPE "short unsigned int"
2846 #define WCHAR_TYPE_SIZE 16
2847
2848 #define SH_ELF_WCHAR_TYPE "long int"
2849
2850 /* Max number of bytes we can move from memory to memory
2851 in one reasonably fast instruction. */
2852 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2853
2854 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2855 MOVE_MAX is not a compile-time constant. */
2856 #define MAX_MOVE_MAX 8
2857
2858 /* Max number of bytes we want move_by_pieces to be able to copy
2859 efficiently. */
2860 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2861
2862 /* Define if operations between registers always perform the operation
2863 on the full register even if a narrower mode is specified. */
2864 #define WORD_REGISTER_OPERATIONS
2865
2866 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2867 will either zero-extend or sign-extend. The value of this macro should
2868 be the code that says which one of the two operations is implicitly
2869 done, UNKNOWN if none. */
2870 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2871 /* FP registers can load SImode values, but don't implicitly sign-extend
2872 them to DImode. */
2873 #define LOAD_EXTEND_OP(MODE) \
2874 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2875 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2876
2877 /* Define if loading short immediate values into registers sign extends. */
2878 #define SHORT_IMMEDIATES_SIGN_EXTEND
2879
2880 /* Nonzero if access to memory by bytes is no faster than for words. */
2881 #define SLOW_BYTE_ACCESS 1
2882
2883 /* Immediate shift counts are truncated by the output routines (or was it
2884 the assembler?). Shift counts in a register are truncated by SH. Note
2885 that the native compiler puts too large (> 32) immediate shift counts
2886 into a register and shifts by the register, letting the SH decide what
2887 to do instead of doing that itself. */
2888 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2889 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2890 expects - the sign bit is significant - so it appears that we need to
2891 leave this zero for correct SH3 code. */
2892 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2893
2894 /* All integers have the same format so truncation is easy. */
2895 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2896
2897 /* Define this if addresses of constant functions
2898 shouldn't be put through pseudo regs where they can be cse'd.
2899 Desirable on machines where ordinary constants are expensive
2900 but a CALL with constant address is cheap. */
2901 /*#define NO_FUNCTION_CSE 1*/
2902
2903 /* The machine modes of pointers and functions. */
2904 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2905 #define FUNCTION_MODE Pmode
2906
2907 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2908 are actually function calls with some special constraints on arguments
2909 and register usage.
2910
2911 These macros tell reorg that the references to arguments and
2912 register clobbers for insns of type sfunc do not appear to happen
2913 until after the millicode call. This allows reorg to put insns
2914 which set the argument registers into the delay slot of the millicode
2915 call -- thus they act more like traditional CALL_INSNs.
2916
2917 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2918 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2919 in particular. */
2920
2921 #define INSN_SETS_ARE_DELAYED(X) \
2922 ((GET_CODE (X) == INSN \
2923 && GET_CODE (PATTERN (X)) != SEQUENCE \
2924 && GET_CODE (PATTERN (X)) != USE \
2925 && GET_CODE (PATTERN (X)) != CLOBBER \
2926 && get_attr_is_sfunc (X)))
2927
2928 #define INSN_REFERENCES_ARE_DELAYED(X) \
2929 ((GET_CODE (X) == INSN \
2930 && GET_CODE (PATTERN (X)) != SEQUENCE \
2931 && GET_CODE (PATTERN (X)) != USE \
2932 && GET_CODE (PATTERN (X)) != CLOBBER \
2933 && get_attr_is_sfunc (X)))
2934
2935 \f
2936 /* Position Independent Code. */
2937
2938 /* We can't directly access anything that contains a symbol,
2939 nor can we indirect via the constant pool. */
2940 #define LEGITIMATE_PIC_OPERAND_P(X) \
2941 ((! nonpic_symbol_mentioned_p (X) \
2942 && (GET_CODE (X) != SYMBOL_REF \
2943 || ! CONSTANT_POOL_ADDRESS_P (X) \
2944 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2945 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2946
2947 #define SYMBOLIC_CONST_P(X) \
2948 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2949 && nonpic_symbol_mentioned_p (X))
2950 \f
2951 /* Compute extra cost of moving data between one register class
2952 and another. */
2953
2954 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2955 uses this information. Hence, the general register <-> floating point
2956 register information here is not used for SFmode. */
2957
2958 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2959 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2960 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2961
2962 #define REGCLASS_HAS_FP_REG(CLASS) \
2963 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2964 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2965
2966 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2967 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2968
2969 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2970 would be so that people with slow memory systems could generate
2971 different code that does fewer memory accesses. */
2972
2973 /* A C expression for the cost of a branch instruction. A value of 1
2974 is the default; other values are interpreted relative to that.
2975 The SH1 does not have delay slots, hence we get a pipeline stall
2976 at every branch. The SH4 is superscalar, so the single delay slot
2977 is not sufficient to keep both pipelines filled. */
2978 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2979 \f
2980 /* Assembler output control. */
2981
2982 /* A C string constant describing how to begin a comment in the target
2983 assembler language. The compiler assumes that the comment will end at
2984 the end of the line. */
2985 #define ASM_COMMENT_START "!"
2986
2987 #define ASM_APP_ON ""
2988 #define ASM_APP_OFF ""
2989 #define FILE_ASM_OP "\t.file\n"
2990 #define SET_ASM_OP "\t.set\t"
2991
2992 /* How to change between sections. */
2993
2994 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2995 #define DATA_SECTION_ASM_OP "\t.data"
2996
2997 #if defined CRT_BEGIN || defined CRT_END
2998 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2999 # undef TEXT_SECTION_ASM_OP
3000 # if __SHMEDIA__ == 1 && __SH5__ == 32
3001 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
3002 # else
3003 # define TEXT_SECTION_ASM_OP "\t.text"
3004 # endif
3005 #endif
3006
3007
3008 /* If defined, a C expression whose value is a string containing the
3009 assembler operation to identify the following data as
3010 uninitialized global data. If not defined, and neither
3011 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
3012 uninitialized global data will be output in the data section if
3013 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
3014 used. */
3015 #ifndef BSS_SECTION_ASM_OP
3016 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
3017 #endif
3018
3019 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
3020 separate, explicit argument. If you define this macro, it is used
3021 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
3022 handling the required alignment of the variable. The alignment is
3023 specified as the number of bits.
3024
3025 Try to use function `asm_output_aligned_bss' defined in file
3026 `varasm.c' when defining this macro. */
3027 #ifndef ASM_OUTPUT_ALIGNED_BSS
3028 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3029 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
3030 #endif
3031
3032 /* Define this so that jump tables go in same section as the current function,
3033 which could be text or it could be a user defined section. */
3034 #define JUMP_TABLES_IN_TEXT_SECTION 1
3035
3036 #undef DO_GLOBAL_CTORS_BODY
3037 #define DO_GLOBAL_CTORS_BODY \
3038 { \
3039 typedef (*pfunc)(); \
3040 extern pfunc __ctors[]; \
3041 extern pfunc __ctors_end[]; \
3042 pfunc *p; \
3043 for (p = __ctors_end; p > __ctors; ) \
3044 { \
3045 (*--p)(); \
3046 } \
3047 }
3048
3049 #undef DO_GLOBAL_DTORS_BODY
3050 #define DO_GLOBAL_DTORS_BODY \
3051 { \
3052 typedef (*pfunc)(); \
3053 extern pfunc __dtors[]; \
3054 extern pfunc __dtors_end[]; \
3055 pfunc *p; \
3056 for (p = __dtors; p < __dtors_end; p++) \
3057 { \
3058 (*p)(); \
3059 } \
3060 }
3061
3062 #define ASM_OUTPUT_REG_PUSH(file, v) \
3063 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
3064
3065 #define ASM_OUTPUT_REG_POP(file, v) \
3066 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
3067
3068 /* DBX register number for a given compiler register number. */
3069 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3070 to match gdb. */
3071 /* svr4.h undefines this macro, yet we really want to use the same numbers
3072 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
3073 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3074 register exists, so we should return -1 for invalid register numbers. */
3075 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3076
3077 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3078 used to use the encodings 245..260, but that doesn't make sense:
3079 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3080 the FP registers stay the same when switching between compact and media
3081 mode. Hence, we also need to use the same dwarf frame columns.
3082 Likewise, we need to support unwind information for SHmedia registers
3083 even in compact code. */
3084 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3085 (IN_RANGE ((REGNO), \
3086 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3087 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3088 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3089 : ((int) (REGNO) >= FIRST_FP_REG \
3090 && ((int) (REGNO) \
3091 <= (FIRST_FP_REG + \
3092 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3093 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3094 + (TARGET_SH5 ? 77 : 25)) \
3095 : XD_REGISTER_P (REGNO) \
3096 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3097 : TARGET_REGISTER_P (REGNO) \
3098 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3099 : (REGNO) == PR_REG \
3100 ? (TARGET_SH5 ? 18 : 17) \
3101 : (REGNO) == PR_MEDIA_REG \
3102 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3103 : (REGNO) == T_REG \
3104 ? (TARGET_SH5 ? 242 : 18) \
3105 : (REGNO) == GBR_REG \
3106 ? (TARGET_SH5 ? 238 : 19) \
3107 : (REGNO) == MACH_REG \
3108 ? (TARGET_SH5 ? 239 : 20) \
3109 : (REGNO) == MACL_REG \
3110 ? (TARGET_SH5 ? 240 : 21) \
3111 : (REGNO) == FPUL_REG \
3112 ? (TARGET_SH5 ? 244 : 23) \
3113 : (unsigned) -1)
3114
3115 /* This is how to output a reference to a symbol_ref. On SH5,
3116 references to non-code symbols must be preceded by `datalabel'. */
3117 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3118 do \
3119 { \
3120 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3121 fputs ("datalabel ", (FILE)); \
3122 assemble_name ((FILE), XSTR ((SYM), 0)); \
3123 } \
3124 while (0)
3125
3126 /* This is how to output an assembler line
3127 that says to advance the location counter
3128 to a multiple of 2**LOG bytes. */
3129
3130 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3131 if ((LOG) != 0) \
3132 fprintf ((FILE), "\t.align %d\n", (LOG))
3133
3134 /* Globalizing directive for a label. */
3135 #define GLOBAL_ASM_OP "\t.global\t"
3136
3137 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3138
3139 /* Output a relative address table. */
3140
3141 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3142 switch (GET_MODE (BODY)) \
3143 { \
3144 case SImode: \
3145 if (TARGET_SH5) \
3146 { \
3147 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3148 (VALUE), (REL)); \
3149 break; \
3150 } \
3151 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3152 break; \
3153 case HImode: \
3154 if (TARGET_SH5) \
3155 { \
3156 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3157 (VALUE), (REL)); \
3158 break; \
3159 } \
3160 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3161 break; \
3162 case QImode: \
3163 if (TARGET_SH5) \
3164 { \
3165 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3166 (VALUE), (REL)); \
3167 break; \
3168 } \
3169 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3170 break; \
3171 default: \
3172 break; \
3173 }
3174
3175 /* Output an absolute table element. */
3176
3177 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3178 if (! optimize || TARGET_BIGTABLE) \
3179 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3180 else \
3181 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3182
3183 \f
3184 /* A C statement to be executed just prior to the output of
3185 assembler code for INSN, to modify the extracted operands so
3186 they will be output differently.
3187
3188 Here the argument OPVEC is the vector containing the operands
3189 extracted from INSN, and NOPERANDS is the number of elements of
3190 the vector which contain meaningful data for this insn.
3191 The contents of this vector are what will be used to convert the insn
3192 template into assembler code, so you can change the assembler output
3193 by changing the contents of the vector. */
3194
3195 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3196 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3197
3198 /* Print operand X (an rtx) in assembler syntax to file FILE.
3199 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3200 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3201
3202 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3203
3204 /* Print a memory address as an operand to reference that memory location. */
3205
3206 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3207
3208 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3209 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3210 || (CHAR) == '$'|| (CHAR) == '\'')
3211
3212 /* Recognize machine-specific patterns that may appear within
3213 constants. Used for PIC-specific UNSPECs. */
3214 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3215 do \
3216 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3217 { \
3218 switch (XINT ((X), 1)) \
3219 { \
3220 case UNSPEC_DATALABEL: \
3221 fputs ("datalabel ", (STREAM)); \
3222 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3223 break; \
3224 case UNSPEC_PIC: \
3225 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3226 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3227 break; \
3228 case UNSPEC_GOT: \
3229 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3230 fputs ("@GOT", (STREAM)); \
3231 break; \
3232 case UNSPEC_GOTOFF: \
3233 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3234 fputs ("@GOTOFF", (STREAM)); \
3235 break; \
3236 case UNSPEC_PLT: \
3237 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3238 fputs ("@PLT", (STREAM)); \
3239 break; \
3240 case UNSPEC_GOTPLT: \
3241 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3242 fputs ("@GOTPLT", (STREAM)); \
3243 break; \
3244 case UNSPEC_DTPOFF: \
3245 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3246 fputs ("@DTPOFF", (STREAM)); \
3247 break; \
3248 case UNSPEC_GOTTPOFF: \
3249 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3250 fputs ("@GOTTPOFF", (STREAM)); \
3251 break; \
3252 case UNSPEC_TPOFF: \
3253 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3254 fputs ("@TPOFF", (STREAM)); \
3255 break; \
3256 case UNSPEC_CALLER: \
3257 { \
3258 char name[32]; \
3259 /* LPCS stands for Label for PIC Call Site. */ \
3260 ASM_GENERATE_INTERNAL_LABEL \
3261 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3262 assemble_name ((STREAM), name); \
3263 } \
3264 break; \
3265 default: \
3266 goto FAIL; \
3267 } \
3268 break; \
3269 } \
3270 else \
3271 goto FAIL; \
3272 while (0)
3273
3274 \f
3275 extern struct rtx_def *sh_compare_op0;
3276 extern struct rtx_def *sh_compare_op1;
3277
3278 /* Which processor to schedule for. The elements of the enumeration must
3279 match exactly the cpu attribute in the sh.md file. */
3280
3281 enum processor_type {
3282 PROCESSOR_SH1,
3283 PROCESSOR_SH2,
3284 PROCESSOR_SH2E,
3285 PROCESSOR_SH2A,
3286 PROCESSOR_SH3,
3287 PROCESSOR_SH3E,
3288 PROCESSOR_SH4,
3289 PROCESSOR_SH4A,
3290 PROCESSOR_SH5
3291 };
3292
3293 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3294 extern enum processor_type sh_cpu;
3295
3296 extern int optimize; /* needed for gen_casesi. */
3297
3298 enum mdep_reorg_phase_e
3299 {
3300 SH_BEFORE_MDEP_REORG,
3301 SH_INSERT_USES_LABELS,
3302 SH_SHORTEN_BRANCHES0,
3303 SH_FIXUP_PCLOAD,
3304 SH_SHORTEN_BRANCHES1,
3305 SH_AFTER_MDEP_REORG
3306 };
3307
3308 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3309
3310 /* Handle Renesas compiler's pragmas. */
3311 #define REGISTER_TARGET_PRAGMAS() do { \
3312 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3313 c_register_pragma (0, "trapa", sh_pr_trapa); \
3314 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3315 } while (0)
3316
3317 /* Set when processing a function with pragma interrupt turned on. */
3318
3319 extern int pragma_interrupt;
3320
3321 /* Set when processing a function with interrupt attribute. */
3322
3323 extern int current_function_interrupt;
3324
3325 /* Set to an RTX containing the address of the stack to switch to
3326 for interrupt functions. */
3327 extern struct rtx_def *sp_switch;
3328
3329 extern int rtx_equal_function_value_matters;
3330
3331 \f
3332 /* Instructions with unfilled delay slots take up an
3333 extra two bytes for the nop in the delay slot.
3334 sh-dsp parallel processing insns are four bytes long. */
3335
3336 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3337 (LENGTH) += sh_insn_length_adjustment (X);
3338 \f
3339 /* Define the codes that are matched by predicates in sh.c. */
3340 #define PREDICATE_CODES \
3341 {"and_operand", {SUBREG, REG, CONST_INT}}, \
3342 {"any_register_operand", {SUBREG, REG}}, \
3343 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3344 {"arith_reg_dest", {SUBREG, REG}}, \
3345 {"arith_reg_operand", {SUBREG, REG}}, \
3346 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
3347 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
3348 {"binary_logical_operator", {AND, IOR, XOR}}, \
3349 {"cmpsi_operand", {SUBREG, REG, CONST_INT}}, \
3350 {"commutative_float_operator", {PLUS, MULT}}, \
3351 {"equality_comparison_operator", {EQ,NE}}, \
3352 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3353 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
3354 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3355 {"fpscr_operand", {REG}}, \
3356 {"fpul_operand", {REG}}, \
3357 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
3358 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3359 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3360 {"unaligned_load_operand", {MEM}}, \
3361 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
3362 {"int_gpr_dest", {SUBREG, REG}}, \
3363 {"inqhi_operand", {TRUNCATE}}, \
3364 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
3365 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3366 {"mextr_bit_offset", {CONST_INT}}, \
3367 {"noncommutative_float_operator", {MINUS, DIV}}, \
3368 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3369 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \
3370 {"target_reg_operand", {SUBREG, REG}}, \
3371 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
3372 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
3373 {"sh_const_vec", {CONST_VECTOR}}, \
3374 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3375 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3376 {"symbol_ref_operand", {SYMBOL_REF}}, \
3377 {"unary_float_operator", {ABS, NEG, SQRT}}, \
3378
3379 #define SPECIAL_MODE_PREDICATES \
3380 "any_register_operand", \
3381 "int_gpr_dest", \
3382 "trunc_hi_operand", \
3383 /* This line intentionally left blank. */
3384
3385 #define any_register_operand register_operand
3386
3387 /* Define this macro if it is advisable to hold scalars in registers
3388 in a wider mode than that declared by the program. In such cases,
3389 the value is constrained to be within the bounds of the declared
3390 type, but kept valid in the wider mode. The signedness of the
3391 extension may differ from that of the type.
3392
3393 Leaving the unsignedp unchanged gives better code than always setting it
3394 to 0. This is despite the fact that we have only signed char and short
3395 load instructions. */
3396 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3397 if (GET_MODE_CLASS (MODE) == MODE_INT \
3398 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3399 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3400 (MODE) = (TARGET_SH1 ? SImode : DImode);
3401
3402 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3403
3404 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3405 and popping arguments. However, we do have push/pop instructions, and
3406 rather limited offsets (4 bits) in load/store instructions, so it isn't
3407 clear if this would give better code. If implemented, should check for
3408 compatibility problems. */
3409
3410 #define SH_DYNAMIC_SHIFT_COST \
3411 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3412
3413
3414 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3415
3416 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3417
3418 #define ACTUAL_NORMAL_MODE(ENTITY) \
3419 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3420
3421 #define NORMAL_MODE(ENTITY) \
3422 (sh_cfun_interrupt_handler_p () \
3423 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3424 : ACTUAL_NORMAL_MODE (ENTITY))
3425
3426 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3427
3428 #define MODE_EXIT(ENTITY) \
3429 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3430
3431 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3432 && (REGNO) == FPSCR_REG)
3433
3434 #define MODE_NEEDED(ENTITY, INSN) \
3435 (recog_memoized (INSN) >= 0 \
3436 ? get_attr_fp_mode (INSN) \
3437 : FP_MODE_NONE)
3438
3439 #define MODE_AFTER(MODE, INSN) \
3440 (TARGET_HITACHI \
3441 && recog_memoized (INSN) >= 0 \
3442 && get_attr_fp_set (INSN) != FP_SET_NONE \
3443 ? (int) get_attr_fp_set (INSN) \
3444 : (MODE))
3445
3446 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3447 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3448
3449 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3450 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3451
3452 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3453 sh_can_redirect_branch ((INSN), (SEQ))
3454
3455 #define DWARF_FRAME_RETURN_COLUMN \
3456 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3457
3458 #define EH_RETURN_DATA_REGNO(N) \
3459 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3460
3461 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3462 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3463
3464 /* We have to distinguish between code and data, so that we apply
3465 datalabel where and only where appropriate. Use sdataN for data. */
3466 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3467 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3468 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3469 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3470
3471 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3472 indirect are handled automatically. */
3473 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3474 do { \
3475 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3476 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3477 { \
3478 if (GET_CODE (ADDR) != SYMBOL_REF) \
3479 abort (); \
3480 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3481 if (0) goto DONE; \
3482 } \
3483 } while (0)
3484
3485 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3486 /* SH constant pool breaks the devices in crtstuff.c to control section
3487 in where code resides. We have to write it as asm code. */
3488 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3489 asm (SECTION_OP "\n\
3490 mov.l 1f,r1\n\
3491 mova 2f,r0\n\
3492 braf r1\n\
3493 lds r0,pr\n\
3494 0: .p2align 2\n\
3495 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3496 2:\n" TEXT_SECTION_ASM_OP);
3497 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3498
3499 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3500 (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
3501 ? (current_function_is_leaf \
3502 && ! sh_pr_n_sets () \
3503 && ! (TARGET_SHCOMPACT \
3504 && ((current_function_args_info.call_cookie \
3505 & ~ CALL_COOKIE_RET_TRAMP (1)) \
3506 || current_function_has_nonlocal_label)) \
3507 ? (hard_reg) \
3508 : gen_rtx_MEM (Pmode, return_address_pointer_rtx)) \
3509 : NULL_RTX)
3510
3511 #endif /* ! GCC_SH_H */
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