?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
PR target/16201
[official-gcc.git] / gcc / config / c4x / c4x.h
blob1112ab82736fd77a57fd0013e55271d3e3ee7d1c
1 /* Definitions of target machine for GNU compiler. TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4
5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 /* RUN-TIME TARGET SPECIFICATION. */
26
27 #define C4x 1
28
29 #define TARGET_CPU_CPP_BUILTINS() \
30 do \
31 { \
32 extern int flag_inline_trees; \
33 if (!TARGET_SMALL) \
34 builtin_define ("_BIGMODEL"); \
35 if (!TARGET_MEMPARM) \
36 builtin_define ("_REGPARM"); \
37 if (flag_inline_functions) \
38 builtin_define ("_INLINE"); \
39 if (TARGET_C3X) \
40 { \
41 builtin_define ("_TMS320C3x"); \
42 builtin_define ("_C3x"); \
43 if (TARGET_C30) \
44 { \
45 builtin_define ("_TMS320C30"); \
46 builtin_define ("_C30"); \
47 } \
48 else if (TARGET_C31) \
49 { \
50 builtin_define ("_TMS320C31"); \
51 builtin_define ("_C31"); \
52 } \
53 else if (TARGET_C32) \
54 { \
55 builtin_define ("_TMS320C32"); \
56 builtin_define ("_C32"); \
57 } \
58 else if (TARGET_C33) \
59 { \
60 builtin_define ("_TMS320C33"); \
61 builtin_define ("_C33"); \
62 } \
63 } \
64 else \
65 { \
66 builtin_define ("_TMS320C4x"); \
67 builtin_define ("_C4x"); \
68 if (TARGET_C40) \
69 { \
70 builtin_define ("_TMS320C40"); \
71 builtin_define ("_C40"); \
72 } \
73 else if (TARGET_C44) \
74 { \
75 builtin_define ("_TMS320C44"); \
76 builtin_define ("_C44"); \
77 } \
78 } \
79 } \
80 while (0)
81
82 /* Name of the c4x assembler. */
83
84 #define ASM_PROG "c4x-as"
85
86 /* Name of the c4x linker. */
87
88 #define LD_PROG "c4x-ld"
89
90 /* Define assembler options. */
91
92 #define ASM_SPEC "\
93 %{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
94 %{!m30:%{!m31:%{!m32:%{!m33:%{!m40:%{!m44:-m40}}}}}}}}}}}} \
95 %{mcpu=30} \
96 %{mcpu=31} \
97 %{mcpu=32} \
98 %{mcpu=33} \
99 %{mcpu=40} \
100 %{mcpu=44} \
101 %{m30} \
102 %{m31} \
103 %{m32} \
104 %{m33} \
105 %{m40} \
106 %{m44} \
107 %{mmemparm} %{mregparm} %{!mmemparm:%{!mregparm:-mregparm}} \
108 %{mbig} %{msmall} %{!msmall:%{!mbig:-mbig}}"
109
110 /* Define linker options. */
111
112 #define LINK_SPEC "\
113 %{m30:--architecture c3x} \
114 %{m31:--architecture c3x} \
115 %{m32:--architecture c3x} \
116 %{m33:--architecture c3x} \
117 %{mcpu=30:--architecture c3x} \
118 %{mcpu=31:--architecture c3x} \
119 %{mcpu=32:--architecture c3x} \
120 %{mcpu=33:--architecture c3x}"
121
122 /* Specify the end file to link with. */
123
124 #define ENDFILE_SPEC ""
125
126 /* Target compilation option flags. */
127
128 #define SMALL_MEMORY_FLAG 0x0000001 /* Small memory model. */
129 #define MPYI_FLAG 0x0000002 /* Use 24-bit MPYI for C3x. */
130 #define FAST_FIX_FLAG 0x0000004 /* Fast fixing of floats. */
131 #define RPTS_FLAG 0x0000008 /* Allow use of RPTS. */
132 #define C3X_FLAG 0x0000010 /* Emit C3x code. */
133 #define TI_FLAG 0x0000020 /* Be compatible with TI assembler. */
134 #define PARANOID_FLAG 0x0000040 /* Be paranoid about DP reg. in ISRs. */
135 #define MEMPARM_FLAG 0x0000080 /* Pass arguments on stack. */
136 #define DEVEL_FLAG 0x0000100 /* Enable features under development. */
137 #define RPTB_FLAG 0x0000200 /* Enable repeat block. */
138 #define BK_FLAG 0x0000400 /* Use BK as general register. */
139 #define DB_FLAG 0x0000800 /* Use decrement and branch for C3x. */
140 #define DEBUG_FLAG 0x0001000 /* Enable debugging of GCC. */
141 #define HOIST_FLAG 0x0002000 /* Force constants into registers. */
142 #define LOOP_UNSIGNED_FLAG 0x0004000 /* Allow unsigned loop counters. */
143 #define FORCE_FLAG 0x0008000 /* Force op0 and op1 to be same. */
144 #define PRESERVE_FLOAT_FLAG 0x0010000 /* Save all 40 bits for floats. */
145 #define PARALLEL_INSN_FLAG 0x0020000 /* Allow parallel insns. */
146 #define PARALLEL_MPY_FLAG 0x0040000 /* Allow MPY||ADD, MPY||SUB insns. */
147 #define ALIASES_FLAG 0x0080000 /* Assume mem refs possibly aliased. */
148
149 #define C30_FLAG 0x0100000 /* Emit C30 code. */
150 #define C31_FLAG 0x0200000 /* Emit C31 code. */
151 #define C32_FLAG 0x0400000 /* Emit C32 code. */
152 #define C33_FLAG 0x0800000 /* Emit C33 code. */
153 #define C40_FLAG 0x1000000 /* Emit C40 code. */
154 #define C44_FLAG 0x2000000 /* Emit C44 code. */
155
156 /* Run-time compilation parameters selecting different hardware subsets.
157
158 Macro to define tables used to set the flags.
159 This is a list in braces of triplets in braces,
160 each pair being { "NAME", VALUE, "DESCRIPTION" }
161 where VALUE is the bits to set or minus the bits to clear.
162 An empty string NAME is used to identify the default VALUE. */
163
164 #define TARGET_SWITCHES \
165 { { "small", SMALL_MEMORY_FLAG, \
166 N_("Small memory model") }, \
167 { "big", -SMALL_MEMORY_FLAG, \
168 N_("Big memory model") }, \
169 { "mpyi", MPYI_FLAG, \
170 N_("Use MPYI instruction for C3x") }, \
171 { "no-mpyi", -MPYI_FLAG, \
172 N_("Do not use MPYI instruction for C3x") }, \
173 { "fast-fix", FAST_FIX_FLAG, \
174 N_("Use fast but approximate float to integer conversion") }, \
175 { "no-fast-fix", -FAST_FIX_FLAG, \
176 N_("Use slow but accurate float to integer conversion") }, \
177 { "rpts", RPTS_FLAG, \
178 N_("Enable use of RTPS instruction") }, \
179 { "no-rpts", -RPTS_FLAG, \
180 N_("Disable use of RTPS instruction") }, \
181 { "rptb", RPTB_FLAG, \
182 N_("Enable use of RTPB instruction") }, \
183 { "no-rptb", -RPTB_FLAG, \
184 N_("Disable use of RTPB instruction") }, \
185 { "30", C30_FLAG, \
186 N_("Generate code for C30 CPU")}, \
187 { "31", C31_FLAG, \
188 N_("Generate code for C31 CPU")}, \
189 { "32", C32_FLAG, \
190 N_("Generate code for C32 CPU")}, \
191 { "33", C33_FLAG, \
192 N_("Generate code for C33 CPU")}, \
193 { "40", C40_FLAG, \
194 N_("Generate code for C40 CPU")}, \
195 { "44", C44_FLAG, \
196 N_("Generate code for C44 CPU")}, \
197 { "ti", TI_FLAG, \
198 N_("Emit code compatible with TI tools")}, \
199 { "no-ti", -TI_FLAG, \
200 N_("Emit code to use GAS extensions")}, \
201 { "paranoid", PARANOID_FLAG, \
202 N_("Save DP across ISR in small memory model") }, \
203 { "no-paranoid", -PARANOID_FLAG, \
204 N_("Don't save DP across ISR in small memory model") }, \
205 { "isr-dp-reload", PARANOID_FLAG, \
206 N_("Save DP across ISR in small memory model") }, \
207 { "no-isr-dp-reload", -PARANOID_FLAG, \
208 N_("Don't save DP across ISR in small memory model") }, \
209 { "memparm", MEMPARM_FLAG, \
210 N_("Pass arguments on the stack") }, \
211 { "regparm", -MEMPARM_FLAG, \
212 N_("Pass arguments in registers") }, \
213 { "devel", DEVEL_FLAG, \
214 N_("Enable new features under development") }, \
215 { "no-devel", -DEVEL_FLAG, \
216 N_("Disable new features under development") }, \
217 { "bk", BK_FLAG, \
218 N_("Use the BK register as a general purpose register") }, \
219 { "no-bk", -BK_FLAG, \
220 N_("Do not allocate BK register") }, \
221 { "db", DB_FLAG, \
222 N_("Enable use of DB instruction") }, \
223 { "no-db", -DB_FLAG, \
224 N_("Disable use of DB instruction") }, \
225 { "debug", DEBUG_FLAG, \
226 N_("Enable debugging") }, \
227 { "no-debug", -DEBUG_FLAG, \
228 N_("Disable debugging") }, \
229 { "hoist", HOIST_FLAG, \
230 N_("Force constants into registers to improve hoisting") }, \
231 { "no-hoist", -HOIST_FLAG, \
232 N_("Don't force constants into registers") }, \
233 { "force", FORCE_FLAG, \
234 N_("Force RTL generation to emit valid 3 operand insns") }, \
235 { "no-force", -FORCE_FLAG, \
236 N_("Allow RTL generation to emit invalid 3 operand insns") }, \
237 { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
238 N_("Allow unsigned iteration counts for RPTB/DB") }, \
239 { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
240 N_("Disallow unsigned iteration counts for RPTB/DB") }, \
241 { "preserve-float", PRESERVE_FLOAT_FLAG, \
242 N_("Preserve all 40 bits of FP reg across call") }, \
243 { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
244 N_("Only preserve 32 bits of FP reg across call") }, \
245 { "parallel-insns", PARALLEL_INSN_FLAG, \
246 N_("Enable parallel instructions") }, \
247 { "no-parallel-insns", -PARALLEL_INSN_FLAG, \
248 N_("Disable parallel instructions") }, \
249 { "parallel-mpy", PARALLEL_MPY_FLAG, \
250 N_("Enable MPY||ADD and MPY||SUB instructions") }, \
251 { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
252 N_("Disable MPY||ADD and MPY||SUB instructions") }, \
253 { "aliases", ALIASES_FLAG, \
254 N_("Assume that pointers may be aliased") }, \
255 { "no-aliases", -ALIASES_FLAG, \
256 N_("Assume that pointers not aliased") }, \
257 { "", TARGET_DEFAULT, ""} }
258
259 /* Default target switches. */
260
261 /* Play safe, not the fastest code. */
262 #define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_INSN_FLAG \
263 | PARALLEL_MPY_FLAG | RPTB_FLAG
264
265 /* Caveats:
266 Max iteration count for RPTB/RPTS is 2^31 + 1.
267 Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
268 RPTS blocks interrupts. */
269
270
271 extern int target_flags;
272
273 #define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
274 #define TARGET_SMALL_REG_CLASS 0
275
276 #define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
277 #define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
278 #define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
279 #define TARGET_RPTS (target_flags & RPTS_FLAG)
280 #define TARGET_TI (target_flags & TI_FLAG)
281 #define TARGET_PARANOID (target_flags & PARANOID_FLAG)
282 #define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
283 #define TARGET_DEVEL (target_flags & DEVEL_FLAG)
284 #define TARGET_RPTB (target_flags & RPTB_FLAG \
285 && optimize >= 2)
286 #define TARGET_BK (target_flags & BK_FLAG)
287 #define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
288 #define TARGET_DEBUG (target_flags & DEBUG_FLAG)
289 #define TARGET_HOIST (target_flags & HOIST_FLAG)
290 #define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
291 #define TARGET_FORCE (target_flags & FORCE_FLAG)
292 #define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
293 #define TARGET_PARALLEL ((target_flags & PARALLEL_INSN_FLAG) \
294 && optimize >= 2)
295 #define TARGET_PARALLEL_MPY (TARGET_PARALLEL \
296 && (target_flags & PARALLEL_MPY_FLAG))
297 #define TARGET_ALIASES (target_flags & ALIASES_FLAG)
298
299 #define TARGET_C3X (target_flags & C3X_FLAG)
300 #define TARGET_C30 (target_flags & C30_FLAG)
301 #define TARGET_C31 (target_flags & C31_FLAG)
302 #define TARGET_C32 (target_flags & C32_FLAG)
303 #define TARGET_C33 (target_flags & C33_FLAG)
304 #define TARGET_C40 (target_flags & C40_FLAG)
305 #define TARGET_C44 (target_flags & C44_FLAG)
306
307 /* Nonzero to use load_immed_addr pattern rather than forcing memory
308 addresses into memory. */
309 #define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
310
311 /* Nonzero to convert direct memory references into HIGH/LO_SUM pairs
312 during RTL generation. */
313 #define TARGET_EXPOSE_LDP 0
314
315 /* Nonzero to force loading of direct memory references into a register. */
316 #define TARGET_LOAD_DIRECT_MEMS 0
317
318 /* -mrpts allows the use of the RPTS instruction irregardless.
319 -mrpts=max-cycles will use RPTS if the number of cycles is constant
320 and less than max-cycles. */
321
322 #define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
323
324 /* -mcpu=XX with XX = target DSP version number. */
325
326 extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
327
328 #define TARGET_OPTIONS \
329 { {"rpts=", &c4x_rpts_cycles_string, \
330 N_("Specify maximum number of iterations for RPTS"), 0}, \
331 {"cpu=", &c4x_cpu_version_string, \
332 N_("Select CPU to generate code for"), 0} }
333
334 /* Sometimes certain combinations of command options do not make sense
335 on a particular target machine. You can define a macro
336 `OVERRIDE_OPTIONS' to take account of this. This macro, if
337 defined, is executed once just after all the command options have
338 been parsed. */
339
340 #define OVERRIDE_OPTIONS c4x_override_options ()
341
342 /* Define this to change the optimizations performed by default. */
343
344 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)
345
346 /* Run Time Target Specification. */
347
348 #define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");
349
350 /* Storage Layout. */
351
352 #define BITS_BIG_ENDIAN 0
353 #define BYTES_BIG_ENDIAN 0
354 #define WORDS_BIG_ENDIAN 0
355
356 /* Technically, we are little endian, but we put the floats out as
357 whole longs and this makes GCC put them out in the right order. */
358
359 #define FLOAT_WORDS_BIG_ENDIAN 1
360
361 /* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
362 all integral and floating point data types are stored in memory as
363 32-bits (floating point types can be stored as 40-bits in the
364 extended precision registers), so sizeof(char) = sizeof(short) =
365 sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
366
367 #define BITS_PER_UNIT 32
368 #define UNITS_PER_WORD 1
369 #define PARM_BOUNDARY 32
370 #define STACK_BOUNDARY 32
371 #define FUNCTION_BOUNDARY 32
372 #define BIGGEST_ALIGNMENT 32
373 #define EMPTY_FIELD_BOUNDARY 32
374 #define STRICT_ALIGNMENT 0
375 #define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
376 #define MAX_FIXED_MODE_SIZE 64 /* HImode. */
377
378 /* If a structure has a floating point field then force structure
379 to have BLKMODE, unless it is the only field. */
380 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
381 (TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE && (MODE) == VOIDmode)
382
383 /* Number of bits in the high and low parts of a two stage
384 load of an immediate constant. */
385 #define BITS_PER_HIGH 16
386 #define BITS_PER_LO_SUM 16
387
388 /* Define register numbers. */
389
390 /* Extended-precision registers. */
391
392 #define R0_REGNO 0
393 #define R1_REGNO 1
394 #define R2_REGNO 2
395 #define R3_REGNO 3
396 #define R4_REGNO 4
397 #define R5_REGNO 5
398 #define R6_REGNO 6
399 #define R7_REGNO 7
400
401 /* Auxiliary (address) registers. */
402
403 #define AR0_REGNO 8
404 #define AR1_REGNO 9
405 #define AR2_REGNO 10
406 #define AR3_REGNO 11
407 #define AR4_REGNO 12
408 #define AR5_REGNO 13
409 #define AR6_REGNO 14
410 #define AR7_REGNO 15
411
412 /* Data page register. */
413
414 #define DP_REGNO 16
415
416 /* Index registers. */
417
418 #define IR0_REGNO 17
419 #define IR1_REGNO 18
420
421 /* Block size register. */
422
423 #define BK_REGNO 19
424
425 /* Stack pointer. */
426
427 #define SP_REGNO 20
428
429 /* Status register. */
430
431 #define ST_REGNO 21
432
433 /* Misc. interrupt registers. */
434
435 #define DIE_REGNO 22 /* C4x only. */
436 #define IE_REGNO 22 /* C3x only. */
437 #define IIE_REGNO 23 /* C4x only. */
438 #define IF_REGNO 23 /* C3x only. */
439 #define IIF_REGNO 24 /* C4x only. */
440 #define IOF_REGNO 24 /* C3x only. */
441
442 /* Repeat block registers. */
443
444 #define RS_REGNO 25
445 #define RE_REGNO 26
446 #define RC_REGNO 27
447
448 /* Additional extended-precision registers. */
449
450 #define R8_REGNO 28 /* C4x only. */
451 #define R9_REGNO 29 /* C4x only. */
452 #define R10_REGNO 30 /* C4x only. */
453 #define R11_REGNO 31 /* C4x only. */
454
455 #define FIRST_PSEUDO_REGISTER 32
456
457 /* Extended precision registers (low set). */
458
459 #define IS_R0R1_REGNO(r) \
460 ((unsigned int)((r) - R0_REGNO) <= (R1_REGNO - R0_REGNO))
461 #define IS_R2R3_REGNO(r) \
462 ((unsigned int)((r) - R2_REGNO) <= (R3_REGNO - R2_REGNO))
463 #define IS_EXT_LOW_REGNO(r) \
464 ((unsigned int)((r) - R0_REGNO) <= (R7_REGNO - R0_REGNO))
465
466 /* Extended precision registers (high set). */
467
468 #define IS_EXT_HIGH_REGNO(r) \
469 (! TARGET_C3X \
470 && ((unsigned int) ((r) - R8_REGNO) <= (R11_REGNO - R8_REGNO)))
471
472 /* Address registers. */
473
474 #define IS_AUX_REGNO(r) \
475 ((unsigned int)((r) - AR0_REGNO) <= (AR7_REGNO - AR0_REGNO))
476 #define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
477 #define IS_DP_REGNO(r) ((r) == DP_REGNO)
478 #define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
479 #define IS_SP_REGNO(r) ((r) == SP_REGNO)
480 #define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
481
482 /* Misc registers. */
483
484 #define IS_ST_REGNO(r) ((r) == ST_REGNO)
485 #define IS_RC_REGNO(r) ((r) == RC_REGNO)
486 #define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
487
488 /* Composite register sets. */
489
490 #define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
491 #define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
492 #define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
493 || IS_REPEAT_REGNO(r) \
494 || IS_SP_REGNO(r) \
495 || IS_BK_REGNO(r))
496 #define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
497 #define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
498 #define IS_INT_CALL_SAVED_REGNO(r) (((r) == R4_REGNO) || ((r) == R5_REGNO) \
499 || ((r) == R8_REGNO))
500 #define IS_FLOAT_CALL_SAVED_REGNO(r) (((r) == R6_REGNO) || ((r) == R7_REGNO))
501
502 #define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
503 #define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
504 #define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
505 #define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
506 #define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
507 #define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
508 #define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
509 #define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
510 #define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
511 || IS_PSEUDO_REGNO(r))
512 #define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
513 #define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
514 #define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
515 #define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
516
517 #define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
518 #define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
519 #define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
520 #define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
521 #define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
522 #define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
523 #define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
524
525 #define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
526 #define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
527 #define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
528 #define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
529 #define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
530 #define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
531
532 #define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
533 #define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
534 #define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
535 #define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
536 #define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
537 #define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
538
539 /* 1 for registers that have pervasive standard uses
540 and are not available for the register allocator. */
541
542 #define FIXED_REGISTERS \
543 { \
544 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
545 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
546 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
547 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
548 }
549
550 /* 1 for registers not available across function calls.
551 These must include the FIXED_REGISTERS and also any
552 registers that can be used without being saved.
553 The latter must include the registers where values are returned
554 and the register where structure-value addresses are passed.
555 Aside from that, you can include as many other registers as you like.
556
557 Note that the extended precision registers are only saved in some
558 modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
559 get clobbered for a given regno. */
560
561 #define CALL_USED_REGISTERS \
562 { \
563 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
564 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
565 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
567 }
568
569 /* Macro to conditionally modify fixed_regs/call_used_regs. */
570
571 #define CONDITIONAL_REGISTER_USAGE \
572 { \
573 if (! TARGET_BK) \
574 { \
575 fixed_regs[BK_REGNO] = 1; \
576 call_used_regs[BK_REGNO] = 1; \
577 c4x_regclass_map[BK_REGNO] = NO_REGS; \
578 } \
579 if (TARGET_C3X) \
580 { \
581 int i; \
582 \
583 reg_names[DIE_REGNO] = "ie"; /* Clobber die. */ \
584 reg_names[IF_REGNO] = "if"; /* Clobber iie. */ \
585 reg_names[IOF_REGNO] = "iof"; /* Clobber iif. */ \
586 \
587 for (i = R8_REGNO; i <= R11_REGNO; i++) \
588 { \
589 fixed_regs[i] = call_used_regs[i] = 1; \
590 c4x_regclass_map[i] = NO_REGS; \
591 } \
592 } \
593 if (TARGET_PRESERVE_FLOAT) \
594 { \
595 c4x_caller_save_map[R6_REGNO] = HFmode; \
596 c4x_caller_save_map[R7_REGNO] = HFmode; \
597 } \
598 }
599
600 /* Order of Allocation of Registers. */
601
602 /* List the order in which to allocate registers. Each register must be
603 listed once, even those in FIXED_REGISTERS.
604
605 First allocate registers that don't need preservation across calls,
606 except index and address registers. Then allocate data registers
607 that require preservation across calls (even though this invokes an
608 extra overhead of having to save/restore these registers). Next
609 allocate the address and index registers, since using these
610 registers for arithmetic can cause pipeline stalls. Finally
611 allocated the fixed registers which won't be allocated anyhow. */
612
613 #define REG_ALLOC_ORDER \
614 {R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
615 R9_REGNO, R10_REGNO, R11_REGNO, \
616 RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
617 R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
618 AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
619 AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
620 IR0_REGNO, IR1_REGNO, \
621 SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
622
623 /* A C expression that is nonzero if hard register number REGNO2 can be
624 considered for use as a rename register for REGNO1 */
625
626 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
627 c4x_hard_regno_rename_ok((REGNO1), (REGNO2))
628
629 /* Determine which register classes are very likely used by spill registers.
630 local-alloc.c won't allocate pseudos that have these classes as their
631 preferred class unless they are "preferred or nothing". */
632
633 #define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS)
634
635 /* CCmode is wrongly defined in machmode.def. It should have a size
636 of UNITS_PER_WORD. HFmode is 40-bits and thus fits within a single
637 extended precision register. Similarly, HCmode fits within two
638 extended precision registers. */
639
640 #define HARD_REGNO_NREGS(REGNO, MODE) \
641 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : \
642 ((MODE) == HFmode) ? 1 : \
643 ((MODE) == HCmode) ? 2 : \
644 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
645
646
647 /* A C expression that is nonzero if the hard register REGNO is preserved
648 across a call in mode MODE. This does not have to include the call used
649 registers. */
650
651 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
652 ((IS_FLOAT_CALL_SAVED_REGNO (REGNO) && ! ((MODE) == QFmode)) \
653 || (IS_INT_CALL_SAVED_REGNO (REGNO) \
654 && ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
655
656 /* Specify the modes required to caller save a given hard regno. */
657
658 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) (c4x_caller_save_map[REGNO])
659
660 #define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
661
662 /* A C expression that is nonzero if it is desirable to choose
663 register allocation so as to avoid move instructions between a
664 value of mode MODE1 and a value of mode MODE2.
665
666 Value is 1 if it is a good idea to tie two pseudo registers
667 when one has mode MODE1 and one has mode MODE2.
668 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
669 for any hard reg, then this must be 0 for correct output. */
670
671 #define MODES_TIEABLE_P(MODE1, MODE2) 0
672
673
674 /* Define the classes of registers for register constraints in the
675 machine description. Also define ranges of constants.
676
677 One of the classes must always be named ALL_REGS and include all hard regs.
678 If there is more than one class, another class must be named NO_REGS
679 and contain no registers.
680
681 The name GENERAL_REGS must be the name of a class (or an alias for
682 another name such as ALL_REGS). This is the class of registers
683 that is allowed by "g" or "r" in a register constraint.
684 Also, registers outside this class are allocated only when
685 instructions express preferences for them.
686
687 The classes must be numbered in nondecreasing order; that is,
688 a larger-numbered class must never be contained completely
689 in a smaller-numbered class.
690
691 For any two classes, it is very desirable that there be another
692 class that represents their union. */
693
694 enum reg_class
695 {
696 NO_REGS,
697 R0R1_REGS, /* 't'. */
698 R2R3_REGS, /* 'u'. */
699 EXT_LOW_REGS, /* 'q'. */
700 EXT_REGS, /* 'f'. */
701 ADDR_REGS, /* 'a'. */
702 INDEX_REGS, /* 'x'. */
703 BK_REG, /* 'k'. */
704 SP_REG, /* 'b'. */
705 RC_REG, /* 'v'. */
706 COUNTER_REGS, /* */
707 INT_REGS, /* 'c'. */
708 GENERAL_REGS, /* 'r'. */
709 DP_REG, /* 'z'. */
710 ST_REG, /* 'y'. */
711 ALL_REGS,
712 LIM_REG_CLASSES
713 };
714
715 #define N_REG_CLASSES (int) LIM_REG_CLASSES
716
717 #define REG_CLASS_NAMES \
718 { \
719 "NO_REGS", \
720 "R0R1_REGS", \
721 "R2R3_REGS", \
722 "EXT_LOW_REGS", \
723 "EXT_REGS", \
724 "ADDR_REGS", \
725 "INDEX_REGS", \
726 "BK_REG", \
727 "SP_REG", \
728 "RC_REG", \
729 "COUNTER_REGS", \
730 "INT_REGS", \
731 "GENERAL_REGS", \
732 "DP_REG", \
733 "ST_REG", \
734 "ALL_REGS" \
735 }
736
737 /* Define which registers fit in which classes.
738 This is an initializer for a vector of HARD_REG_SET
739 of length N_REG_CLASSES. RC is not included in GENERAL_REGS
740 since the register allocator will often choose a general register
741 in preference to RC for the decrement_and_branch_on_count pattern. */
742
743 #define REG_CLASS_CONTENTS \
744 { \
745 {0x00000000}, /* No registers. */ \
746 {0x00000003}, /* 't' R0-R1 . */ \
747 {0x0000000c}, /* 'u' R2-R3 . */ \
748 {0x000000ff}, /* 'q' R0-R7 . */ \
749 {0xf00000ff}, /* 'f' R0-R11 */ \
750 {0x0000ff00}, /* 'a' AR0-AR7. */ \
751 {0x00060000}, /* 'x' IR0-IR1. */ \
752 {0x00080000}, /* 'k' BK. */ \
753 {0x00100000}, /* 'b' SP. */ \
754 {0x08000000}, /* 'v' RC. */ \
755 {0x0800ff00}, /* RC,AR0-AR7. */ \
756 {0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */ \
757 {0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */\
758 {0x00010000}, /* 'z' DP. */ \
759 {0x00200000}, /* 'y' ST. */ \
760 {0xffffffff}, /* All registers. */ \
761 }
762
763 /* The same information, inverted:
764 Return the class number of the smallest class containing
765 reg number REGNO. This could be a conditional expression
766 or could index an array. */
767
768 #define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
769
770 /* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
771 explicitly used in the rtl is kept as short as possible.
772
773 We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
774 is defined since the MPY|ADD insns require the classes R0R1_REGS and
775 R2R3_REGS which are used by the function return registers (R0,R1) and
776 the register arguments (R2,R3), respectively. I'm reluctant to define
777 this macro since it stomps on many potential optimizations. Ideally
778 it should have a register class argument so that not all the register
779 classes gets penalized for the sake of a naughty few... For long
780 double arithmetic we need two additional registers that we can use as
781 spill registers. */
782
783 #define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
784
785 #define BASE_REG_CLASS ADDR_REGS
786 #define INDEX_REG_CLASS INDEX_REGS
787
788 /*
789 Register constraints for the C4x
790
791 a - address reg (ar0-ar7)
792 b - stack reg (sp)
793 c - other gp int-only reg
794 d - data/int reg (equiv. to f)
795 f - data/float reg
796 h - data/long double reg (equiv. to f)
797 k - block count (bk)
798 q - r0-r7
799 t - r0-r1
800 u - r2-r3
801 v - repeat count (rc)
802 x - index register (ir0-ir1)
803 y - status register (st)
804 z - dp reg (dp)
805
806 Memory/constant constraints for the C4x
807
808 G - short float 16-bit
809 I - signed 16-bit constant (sign extended)
810 J - signed 8-bit constant (sign extended) (C4x only)
811 K - signed 5-bit constant (sign extended) (C4x only for stik)
812 L - unsigned 16-bit constant
813 M - unsigned 8-bit constant (C4x only)
814 N - ones complement of unsigned 16-bit constant
815 Q - indirect arx + 9-bit signed displacement
816 (a *-arx(n) or *+arx(n) is used to account for the sign bit)
817 R - indirect arx + 5-bit unsigned displacement (C4x only)
818 S - indirect arx + 0, 1, or irn displacement
819 T - direct symbol ref
820 > - indirect with autoincrement
821 < - indirect with autodecrement
822 } - indirect with post-modify
823 { - indirect with pre-modify
824 */
825
826 #define REG_CLASS_FROM_LETTER(CC) \
827 ( ((CC) == 'a') ? ADDR_REGS \
828 : ((CC) == 'b') ? SP_REG \
829 : ((CC) == 'c') ? INT_REGS \
830 : ((CC) == 'd') ? EXT_REGS \
831 : ((CC) == 'f') ? EXT_REGS \
832 : ((CC) == 'h') ? EXT_REGS \
833 : ((CC) == 'k') ? BK_REG \
834 : ((CC) == 'q') ? EXT_LOW_REGS \
835 : ((CC) == 't') ? R0R1_REGS \
836 : ((CC) == 'u') ? R2R3_REGS \
837 : ((CC) == 'v') ? RC_REG \
838 : ((CC) == 'x') ? INDEX_REGS \
839 : ((CC) == 'y') ? ST_REG \
840 : ((CC) == 'z') ? DP_REG \
841 : NO_REGS )
842
843 /* These assume that REGNO is a hard or pseudo reg number.
844 They give nonzero only if REGNO is a hard reg of the suitable class
845 or a pseudo reg currently allocated to a suitable hard reg.
846 Since they use reg_renumber, they are safe only once reg_renumber
847 has been allocated, which happens in local-alloc.c. */
848
849 #define REGNO_OK_FOR_BASE_P(REGNO) \
850 (IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
851
852 #define REGNO_OK_FOR_INDEX_P(REGNO) \
853 (IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
854
855 /* If we have to generate framepointer + constant prefer an ADDR_REGS
856 register. This avoids using EXT_REGS in addqi3_noclobber_reload. */
857
858 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
859 (GET_CODE (X) == PLUS \
860 && GET_MODE (X) == Pmode \
861 && GET_CODE (XEXP ((X), 0)) == REG \
862 && GET_MODE (XEXP ((X), 0)) == Pmode \
863 && REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM \
864 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
865 ? ADDR_REGS : (CLASS))
866
867 #define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
868
869 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0
870
871 #define CLASS_MAX_NREGS(CLASS, MODE) \
872 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
873 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
874
875 #define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K'. */
876
877 #define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R'. */
878
879 #define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J'. */
880
881 #define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M'. */
882
883 #define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I'. */
884
885 #define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L'. */
886
887 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N'. */
888
889 #define IS_HIGH_CONST(VAL) \
890 (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O'. */
891
892
893 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S'. */
894
895 #define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q'. */
896
897 #define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
898 && IS_DISP1_CONST (VAL + 1))
899
900 #define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
901 && IS_DISP8_CONST (VAL + 1))
902
903 #define CONST_OK_FOR_LETTER_P(VAL, C) \
904 ( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
905 : ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
906 : ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
907 : ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
908 : ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
909 : ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
910 : ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
911 : 0 )
912
913 #define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
914 ( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \
915 : ((C) == 'H') ? (c4x_H_constant (OP)) \
916 : 0 )
917
918 #define EXTRA_CONSTRAINT(OP, C) \
919 ( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
920 : ((C) == 'R') ? (c4x_R_constraint (OP)) \
921 : ((C) == 'S') ? (c4x_S_constraint (OP)) \
922 : ((C) == 'T') ? (c4x_T_constraint (OP)) \
923 : ((C) == 'U') ? (c4x_U_constraint (OP)) \
924 : 0 )
925
926 #define SMALL_CONST(VAL, insn) \
927 ( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
928 ? IS_INT16_CONST (VAL) \
929 : ( (get_attr_data (insn) == DATA_NOT_UINT16) \
930 ? IS_NOT_UINT16_CONST (VAL) \
931 : ( (get_attr_data (insn) == DATA_HIGH_16) \
932 ? IS_HIGH_CONST (VAL) \
933 : IS_UINT16_CONST (VAL) \
934 ) \
935 ) \
936 )
937
938 /*
939 I. Routine calling with arguments in registers
940 ----------------------------------------------
941
942 The TI C3x compiler has a rather unusual register passing algorithm.
943 Data is passed in the following registers (in order):
944
945 AR2, R2, R3, RC, RS, RE
946
947 However, the first and second floating point values are always in R2
948 and R3 (and all other floats are on the stack). Structs are always
949 passed on the stack. If the last argument is an ellipsis, the
950 previous argument is passed on the stack so that its address can be
951 taken for the stdargs macros.
952
953 Because of this, we have to pre-scan the list of arguments to figure
954 out what goes where in the list.
955
956 II. Routine calling with arguments on stack
957 -------------------------------------------
958
959 Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
960 variables loc0, loc1, and loc2. After the function prologue has
961 been executed, the stack frame will look like:
962
963 [stack grows towards increasing addresses]
964 I-------------I
965 5 I saved reg1 I <= SP points here
966 I-------------I
967 4 I saved reg0 I
968 I-------------I
969 3 I loc2 I
970 I-------------I
971 2 I loc1 I
972 I-------------I
973 1 I loc0 I
974 I-------------I
975 0 I old FP I <= FP (AR3) points here
976 I-------------I
977 -1 I return PC I
978 I-------------I
979 -2 I arg0 I
980 I-------------I
981 -3 I arg1 I
982 I-------------I
983 -4 I arg2 I
984 I-------------I
985
986 All local variables (locn) are accessible by means of +FP(n+1)
987 addressing, where n is the local variable number.
988
989 All stack arguments (argn) are accessible by means of -FP(n-2).
990
991 The stack pointer (SP) points to the last register saved in the
992 prologue (regn).
993
994 Note that a push instruction performs a preincrement of the stack
995 pointer. (STACK_PUSH_CODE == PRE_INC)
996
997 III. Registers used in function calling convention
998 --------------------------------------------------
999
1000 Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
1001 R6...R7 (only by PUSHF, i.e. upper 32 bits)
1002 AR3...AR7
1003
1004 (Because of this model, we only assign FP values in R6, R7 and
1005 only assign integer values in R4, R5.)
1006
1007 These registers are saved at each function entry and restored at
1008 the exit. Also it is expected any of these not affected by any
1009 call to user-defined (not service) functions.
1010
1011 Not preserved across calls: R0...R3
1012 R4...R5 (upper 8 bits)
1013 R6...R7 (lower 8 bits)
1014 AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
1015
1016 These registers are used arbitrary in a function without being preserved.
1017 It is also expected that any of these can be clobbered by any call.
1018
1019 Not used by GCC (except for in user "asm" statements):
1020 IE (DIE), IF (IIE), IOF (IIF)
1021
1022 These registers are never used by GCC for any data, but can be used
1023 with "asm" statements. */
1024
1025 #define C4X_ARG0 -2
1026 #define C4X_LOC0 1
1027
1028 /* Basic Stack Layout. */
1029
1030 /* The stack grows upward, stack frame grows upward, and args grow
1031 downward. */
1032
1033 #define STARTING_FRAME_OFFSET C4X_LOC0
1034 #define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
1035 #define ARGS_GROW_DOWNWARD
1036 #define STACK_POINTER_OFFSET 1
1037
1038 /* Define this if pushing a word on the stack
1039 makes the stack pointer a smaller address. */
1040
1041 /* #define STACK_GROWS_DOWNWARD. */
1042 /* Like the dsp16xx, i370, i960, and we32k ports. */
1043
1044 /* Define this if the nominal address of the stack frame
1045 is at the high-address end of the local variables;
1046 that is, each additional local variable allocated
1047 goes at a more negative offset in the frame. */
1048
1049 /* #define FRAME_GROWS_DOWNWARD. */
1050
1051
1052 /* Registers That Address the Stack Frame. */
1053
1054 #define STACK_POINTER_REGNUM SP_REGNO /* SP. */
1055 #define FRAME_POINTER_REGNUM AR3_REGNO /* AR3. */
1056 #define ARG_POINTER_REGNUM AR3_REGNO /* AR3. */
1057 #define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0. */
1058
1059 /* Eliminating Frame Pointer and Arg Pointer. */
1060
1061 #define FRAME_POINTER_REQUIRED 0
1062
1063 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1064 { \
1065 int regno; \
1066 int offset = 0; \
1067 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1068 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1069 offset += TARGET_PRESERVE_FLOAT \
1070 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1071 (DEPTH) = -(offset + get_frame_size ()); \
1072 }
1073
1074 /* This is a hack... We need to specify a register. */
1075 #define ELIMINABLE_REGS \
1076 {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
1077
1078 #define CAN_ELIMINATE(FROM, TO) \
1079 (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1080 || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
1081
1082 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1083 { \
1084 int regno; \
1085 int offset = 0; \
1086 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1087 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1088 offset += TARGET_PRESERVE_FLOAT \
1089 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1090 (OFFSET) = -(offset + get_frame_size ()); \
1091 }
1092
1093
1094 /* Passing Function Arguments on the Stack. */
1095
1096 #define PUSH_ARGS 1
1097 #define PUSH_ROUNDING(BYTES) (BYTES)
1098 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1099
1100 /* The following structure is used by calls.c, function.c, c4x.c. */
1101
1102 typedef struct c4x_args
1103 {
1104 int floats;
1105 int ints;
1106 int maxfloats;
1107 int maxints;
1108 int init;
1109 int var;
1110 int prototype;
1111 int args;
1112 }
1113 CUMULATIVE_ARGS;
1114
1115 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1116 (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1117
1118 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1119 (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1120
1121 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1122 (c4x_function_arg(&CUM, MODE, TYPE, NAMED))
1123
1124 /* Define the profitability of saving registers around calls.
1125 We disable caller save to avoid a bug in flow.c (this also affects
1126 other targets such as m68k). Since we must use stf/sti,
1127 the profitability is marginal anyway. */
1128
1129 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1130
1131 /* 1 if N is a possible register number for function argument passing. */
1132
1133 #define FUNCTION_ARG_REGNO_P(REGNO) \
1134 ( ( ((REGNO) == AR2_REGNO) /* AR2. */ \
1135 || ((REGNO) == R2_REGNO) /* R2. */ \
1136 || ((REGNO) == R3_REGNO) /* R3. */ \
1137 || ((REGNO) == RC_REGNO) /* RC. */ \
1138 || ((REGNO) == RS_REGNO) /* RS. */ \
1139 || ((REGNO) == RE_REGNO)) /* RE. */ \
1140 ? 1 \
1141 : 0)
1142
1143 /* How Scalar Function Values Are Returned. */
1144
1145 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1146 gen_rtx_REG (TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */
1147
1148 #define LIBCALL_VALUE(MODE) \
1149 gen_rtx_REG (MODE, R0_REGNO) /* Return in R0. */
1150
1151 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
1152
1153 /* How Large Values Are Returned. */
1154
1155 #define DEFAULT_PCC_STRUCT_RETURN 0
1156
1157 /* Generating Code for Profiling. */
1158
1159 /* Note that the generated assembly uses the ^ operator to load the 16
1160 MSBs of the address. This is not supported by the TI assembler.
1161 The FUNCTION profiler needs a function mcount which gets passed
1162 a pointer to the LABELNO. */
1163
1164 #define FUNCTION_PROFILER(FILE, LABELNO) \
1165 if (! TARGET_C3X) \
1166 { \
1167 fprintf (FILE, "\tpush\tar2\n"); \
1168 fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
1169 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1170 fprintf (FILE, "\tcall\tmcount\n"); \
1171 fprintf (FILE, "\tpop\tar2\n"); \
1172 } \
1173 else \
1174 { \
1175 fprintf (FILE, "\tpush\tar2\n"); \
1176 fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
1177 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1178 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1179 fprintf (FILE, "\tcall\tmcount\n"); \
1180 fprintf (FILE, "\tpop\tar2\n"); \
1181 }
1182
1183 /* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
1184 or MULT.
1185 CCmode should be used when no special processing is needed. */
1186 #define SELECT_CC_MODE(OP,X,Y) \
1187 ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1188 || GET_CODE (X) == NEG || GET_CODE (X) == MULT \
1189 || GET_MODE (X) == ABS \
1190 || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
1191 || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
1192 || GET_MODE (Y) == ABS) \
1193 ? CC_NOOVmode : CCmode)
1194
1195 /* Addressing Modes. */
1196
1197 #define HAVE_POST_INCREMENT 1
1198 #define HAVE_PRE_INCREMENT 1
1199 #define HAVE_POST_DECREMENT 1
1200 #define HAVE_PRE_DECREMENT 1
1201 #define HAVE_PRE_MODIFY_REG 1
1202 #define HAVE_POST_MODIFY_REG 1
1203 #define HAVE_PRE_MODIFY_DISP 1
1204 #define HAVE_POST_MODIFY_DISP 1
1205
1206 /* The number of insns that can be packed into a single opcode. */
1207 #define PACK_INSNS 2
1208
1209 /* Recognize any constant value that is a valid address.
1210 We could allow arbitrary constant addresses in the large memory
1211 model but for the small memory model we can only accept addresses
1212 within the data page. I suppose we could also allow
1213 CONST PLUS SYMBOL_REF. */
1214 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
1215
1216 /* Maximum number of registers that can appear in a valid memory
1217 address. */
1218 #define MAX_REGS_PER_ADDRESS 2
1219
1220 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1221 and check its validity for a certain class.
1222 We have two alternate definitions for each of them.
1223 The usual definition accepts all pseudo regs; the other rejects
1224 them unless they have been allocated suitable hard regs.
1225 The symbol REG_OK_STRICT causes the latter definition to be used.
1226
1227 Most source files want to accept pseudo regs in the hope that
1228 they will get allocated to the class that the insn wants them to be in.
1229 Source files for reload pass need to be strict.
1230 After reload, it makes no difference, since pseudo regs have
1231 been eliminated by then. */
1232
1233 #ifndef REG_OK_STRICT
1234
1235 /* Nonzero if X is a hard or pseudo reg that can be used as a base. */
1236
1237 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
1238
1239 /* Nonzero if X is a hard or pseudo reg that can be used as an index. */
1240
1241 #define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
1242
1243 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1244 { \
1245 if (c4x_legitimate_address_p (MODE, X, 0)) \
1246 goto ADDR; \
1247 }
1248
1249 #else
1250
1251 /* Nonzero if X is a hard reg that can be used as an index. */
1252
1253 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1254
1255 /* Nonzero if X is a hard reg that can be used as a base reg. */
1256
1257 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1258
1259 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1260 { \
1261 if (c4x_legitimate_address_p (MODE, X, 1)) \
1262 goto ADDR; \
1263 }
1264
1265 #endif
1266
1267 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1268 { \
1269 rtx new; \
1270 \
1271 new = c4x_legitimize_address (X, MODE); \
1272 if (new != NULL_RTX) \
1273 { \
1274 (X) = new; \
1275 goto WIN; \
1276 } \
1277 }
1278
1279 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1280 { \
1281 if (MODE != HImode \
1282 && MODE != HFmode \
1283 && GET_MODE (X) != HImode \
1284 && GET_MODE (X) != HFmode \
1285 && (GET_CODE (X) == CONST \
1286 || GET_CODE (X) == SYMBOL_REF \
1287 || GET_CODE (X) == LABEL_REF)) \
1288 { \
1289 if (! TARGET_SMALL) \
1290 { \
1291 int i; \
1292 (X) = gen_rtx_LO_SUM (GET_MODE (X), \
1293 gen_rtx_HIGH (GET_MODE (X), X), X); \
1294 i = push_reload (XEXP (X, 0), NULL_RTX, \
1295 &XEXP (X, 0), NULL, \
1296 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1297 OPNUM, TYPE); \
1298 /* The only valid reg is DP. This is a fixed reg and will \
1299 normally not be used so force it. */ \
1300 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1301 rld[i].nocombine = 1; \
1302 } \
1303 else \
1304 { \
1305 /* make_memloc in reload will substitute invalid memory \
1306 references. We need to fix them up. */ \
1307 (X) = gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, DP_REGNO), (X)); \
1308 } \
1309 goto WIN; \
1310 } \
1311 else if (MODE != HImode \
1312 && MODE != HFmode \
1313 && GET_MODE (X) != HImode \
1314 && GET_MODE (X) != HFmode \
1315 && GET_CODE (X) == LO_SUM \
1316 && GET_CODE (XEXP (X,0)) == HIGH \
1317 && (GET_CODE (XEXP (XEXP (X,0),0)) == CONST \
1318 || GET_CODE (XEXP (XEXP (X,0),0)) == SYMBOL_REF \
1319 || GET_CODE (XEXP (XEXP (X,0),0)) == LABEL_REF)) \
1320 { \
1321 if (! TARGET_SMALL) \
1322 { \
1323 int i = push_reload (XEXP (X, 0), NULL_RTX, \
1324 &XEXP (X, 0), NULL, \
1325 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1326 OPNUM, TYPE); \
1327 /* The only valid reg is DP. This is a fixed reg and will \
1328 normally not be used so force it. */ \
1329 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1330 rld[i].nocombine = 1; \
1331 } \
1332 goto WIN; \
1333 } \
1334 }
1335
1336 /* No mode-dependent addresses on the C4x are autoincrements. */
1337
1338 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1339 if (GET_CODE (ADDR) == PRE_DEC \
1340 || GET_CODE (ADDR) == POST_DEC \
1341 || GET_CODE (ADDR) == PRE_INC \
1342 || GET_CODE (ADDR) == POST_INC \
1343 || GET_CODE (ADDR) == POST_MODIFY \
1344 || GET_CODE (ADDR) == PRE_MODIFY) \
1345 goto LABEL
1346
1347
1348 /* Nonzero if the constant value X is a legitimate general operand.
1349 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1350
1351 The C4x can only load 16-bit immediate values, so we only allow a
1352 restricted subset of CONST_INT and CONST_DOUBLE. Disallow
1353 LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
1354 model) so that the symbols will be forced into the constant pool.
1355 On second thoughts, let's do this with the move expanders since
1356 the alias analysis has trouble if we force constant addresses
1357 into memory.
1358 */
1359
1360 #define LEGITIMATE_CONSTANT_P(X) \
1361 ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
1362 || (GET_CODE (X) == CONST_INT) \
1363 || (GET_CODE (X) == SYMBOL_REF) \
1364 || (GET_CODE (X) == LABEL_REF) \
1365 || (GET_CODE (X) == CONST) \
1366 || (GET_CODE (X) == HIGH && ! TARGET_C3X) \
1367 || (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
1368
1369 #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
1370
1371 /* Describing Relative Cost of Operations. */
1372
1373 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1374 if (REG_P (OP1) && ! REG_P (OP0)) \
1375 { \
1376 rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
1377 CODE = swap_condition (CODE); \
1378 }
1379
1380 #define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
1381 #define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
1382 #define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
1383 #define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
1384 || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
1385
1386 /* Compute extra cost of moving data between one register class
1387 and another. */
1388
1389 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
1390
1391 /* Memory move cost is same as fast register move. Maybe this should
1392 be bumped up?. */
1393
1394 #define MEMORY_MOVE_COST(M,C,I) 4
1395
1396 /* Branches are kind of expensive (even with delayed branching) so
1397 make their cost higher. */
1398
1399 #define BRANCH_COST 8
1400
1401 #define WORD_REGISTER_OPERATIONS
1402
1403 /* Dividing the Output into Sections. */
1404
1405 #define TEXT_SECTION_ASM_OP "\t.text"
1406
1407 #define DATA_SECTION_ASM_OP "\t.data"
1408
1409 #define READONLY_DATA_SECTION_ASM_OP "\t.sect\t\".const\""
1410
1411 /* Do not use .init section so __main will be called on startup. This will
1412 call __do_global_ctors and prepare for __do_global_dtors on exit. */
1413
1414 #if 0
1415 #define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
1416 #endif
1417
1418 #define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
1419
1420 #undef EXTRA_SECTIONS
1421 #define EXTRA_SECTIONS in_init, in_fini
1422
1423 #undef EXTRA_SECTION_FUNCTIONS
1424 #define EXTRA_SECTION_FUNCTIONS \
1425 INIT_SECTION_FUNCTION \
1426 FINI_SECTION_FUNCTION
1427
1428 #define INIT_SECTION_FUNCTION \
1429 extern void init_section (void); \
1430 void \
1431 init_section (void) \
1432 { \
1433 if (in_section != in_init) \
1434 { \
1435 fprintf (asm_out_file, ";\t.init\n"); \
1436 in_section = in_init; \
1437 } \
1438 }
1439
1440 #define FINI_SECTION_FUNCTION \
1441 void \
1442 fini_section () \
1443 { \
1444 if (in_section != in_fini) \
1445 { \
1446 fprintf (asm_out_file, "%s\n", FINI_SECTION_ASM_OP); \
1447 in_section = in_fini; \
1448 } \
1449 }
1450
1451 /* Switch into a generic section. */
1452 #define TARGET_ASM_NAMED_SECTION c4x_asm_named_section
1453
1454
1455 /* Overall Framework of an Assembler File. */
1456
1457 #define ASM_COMMENT_START ";"
1458
1459 #define ASM_APP_ON ""
1460 #define ASM_APP_OFF ""
1461
1462 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
1463
1464 /* Output and Generation of Labels. */
1465
1466 #define NO_DOT_IN_LABEL /* Only required for TI format. */
1467
1468 /* Globalizing directive for a label. */
1469 #define GLOBAL_ASM_OP "\t.global\t"
1470
1471 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1472 c4x_external_ref (NAME)
1473
1474 /* The prefix to add to user-visible assembler symbols. */
1475
1476 #define USER_LABEL_PREFIX "_"
1477
1478 /* This is how to store into the string LABEL
1479 the symbol_ref name of an internal numbered label where
1480 PREFIX is the class of label and NUM is the number within the class.
1481 This is suitable for output with `assemble_name'. */
1482
1483 #define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
1484 sprintf (BUFFER, "*%s%lu", PREFIX, (unsigned long)(NUM))
1485
1486 /* A C statement to output to the stdio stream STREAM assembler code which
1487 defines (equates) the symbol NAME to have the value VALUE. */
1488
1489 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1490 do { \
1491 assemble_name (STREAM, NAME); \
1492 fprintf (STREAM, "\t.set\t%s\n", VALUE); \
1493 } while (0)
1494
1495 /* Output of Dispatch Tables. */
1496
1497 /* This is how to output an element of a case-vector that is absolute. */
1498
1499 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1500 fprintf (FILE, "\t.long\tL%d\n", VALUE);
1501
1502 /* This is how to output an element of a case-vector that is relative. */
1503
1504 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1505 fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
1506
1507 #undef SIZE_TYPE
1508 #define SIZE_TYPE "unsigned int"
1509
1510 #undef PTRDIFF_TYPE
1511 #define PTRDIFF_TYPE "int"
1512
1513 #undef WCHAR_TYPE
1514 #define WCHAR_TYPE "long int"
1515
1516 #undef WCHAR_TYPE_SIZE
1517 #define WCHAR_TYPE_SIZE 32
1518
1519 #define INT_TYPE_SIZE 32
1520 #define LONG_LONG_TYPE_SIZE 64
1521 #define FLOAT_TYPE_SIZE 32
1522 #define DOUBLE_TYPE_SIZE 32
1523 #define LONG_DOUBLE_TYPE_SIZE 64 /* Actually only 40. */
1524
1525 /* Output #ident as a .ident. */
1526
1527 #define ASM_OUTPUT_IDENT(FILE, NAME) \
1528 fprintf (FILE, "\t.ident \"%s\"\n", NAME);
1529
1530 /* Output of Uninitialized Variables. */
1531
1532 /* This says how to output an assembler line to define a local
1533 uninitialized variable. */
1534
1535 #undef ASM_OUTPUT_LOCAL
1536 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1537 ( fputs ("\t.bss\t", FILE), \
1538 assemble_name (FILE, (NAME)), \
1539 fprintf (FILE, ",%u\n", (int)(ROUNDED)))
1540
1541 /* This says how to output an assembler line to define a global
1542 uninitialized variable. */
1543
1544 #undef ASM_OUTPUT_COMMON
1545 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1546 ( fputs ("\t.globl\t", FILE), \
1547 assemble_name (FILE, (NAME)), \
1548 fputs ("\n\t.bss\t", FILE), \
1549 assemble_name (FILE, (NAME)), \
1550 fprintf (FILE, ",%u\n", (int)(ROUNDED)))
1551
1552 #undef ASM_OUTPUT_BSS
1553 #define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1554 ( fputs ("\t.globl\t", FILE), \
1555 assemble_name (FILE, (NAME)), \
1556 fputs ("\n\t.bss\t", FILE), \
1557 assemble_name (FILE, (NAME)), \
1558 fprintf (FILE, ",%u\n", (int)(SIZE)))
1559
1560 /* Macros Controlling Initialization Routines. */
1561
1562 #define OBJECT_FORMAT_COFF
1563 #define REAL_NM_FILE_NAME "c4x-nm"
1564
1565 /* Output of Assembler Instructions. */
1566
1567 /* Register names when used for integer modes. */
1568
1569 #define REGISTER_NAMES \
1570 { \
1571 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1572 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
1573 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
1574 "iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
1575 }
1576
1577 /* Alternate register names when used for floating point modes. */
1578
1579 #define FLOAT_REGISTER_NAMES \
1580 { \
1581 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1582 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
1583 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
1584 "iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
1585 }
1586
1587 #define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
1588
1589 /* Determine which codes are valid without a following integer. These must
1590 not be alphabetic. */
1591
1592 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
1593
1594 #define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
1595
1596 /* C4x specific pragmas. */
1597 #define REGISTER_TARGET_PRAGMAS() do { \
1598 c_register_pragma (0, "CODE_SECTION", c4x_pr_CODE_SECTION); \
1599 c_register_pragma (0, "DATA_SECTION", c4x_pr_DATA_SECTION); \
1600 c_register_pragma (0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \
1601 c_register_pragma (0, "FUNC_EXT_CALLED", c4x_pr_ignored); \
1602 c_register_pragma (0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \
1603 c_register_pragma (0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \
1604 c_register_pragma (0, "FUNC_NEVER_RETURNS", c4x_pr_FUNC_NEVER_RETURNS); \
1605 c_register_pragma (0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \
1606 c_register_pragma (0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \
1607 c_register_pragma (0, "INTERRUPT", c4x_pr_INTERRUPT); \
1608 } while (0)
1609
1610 /* Assembler Commands for Alignment. */
1611
1612 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
1613 { int c = SIZE; \
1614 for (; c > 0; --c) \
1615 fprintf (FILE,"\t.word\t0\n"); \
1616 }
1617
1618 #define ASM_NO_SKIP_IN_TEXT 1
1619
1620 /* I'm not sure about this one. FIXME. */
1621
1622 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
1623 if ((LOG) != 0) \
1624 fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
1625
1626
1627 /* Macros for SDB and DWARF Output (use .sdef instead of .def
1628 to avoid conflict with TI's use of .def). */
1629
1630 #define SDB_DELIM "\n"
1631 #define SDB_DEBUGGING_INFO 1
1632
1633 /* Don't use octal since this can confuse gas for the c4x. */
1634 #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM)
1635
1636 #define PUT_SDB_DEF(A) \
1637 do { fprintf (asm_out_file, "\t.sdef\t"); \
1638 ASM_OUTPUT_LABELREF (asm_out_file, A); \
1639 fprintf (asm_out_file, SDB_DELIM); } while (0)
1640
1641 #define PUT_SDB_PLAIN_DEF(A) \
1642 fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
1643
1644 #define PUT_SDB_BLOCK_START(LINE) \
1645 fprintf (asm_out_file, \
1646 "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
1647 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1648
1649 #define PUT_SDB_BLOCK_END(LINE) \
1650 fprintf (asm_out_file, \
1651 "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
1652 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1653
1654 #define PUT_SDB_FUNCTION_START(LINE) \
1655 fprintf (asm_out_file, \
1656 "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
1657 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1658
1659 /* Note we output relative line numbers for .ef which gas converts
1660 to absolute line numbers. The TI compiler outputs absolute line numbers
1661 in the .sym directive which gas does not support. */
1662 #define PUT_SDB_FUNCTION_END(LINE) \
1663 fprintf (asm_out_file, \
1664 "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
1665 SDB_DELIM, SDB_DELIM, SDB_DELIM, \
1666 (LINE), SDB_DELIM)
1667
1668 #define PUT_SDB_EPILOGUE_END(NAME) \
1669 do { fprintf (asm_out_file, "\t.sdef\t"); \
1670 ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
1671 fprintf (asm_out_file, \
1672 "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
1673 SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
1674
1675 /* Define this as 1 if `char' should by default be signed; else as 0. */
1676
1677 #define DEFAULT_SIGNED_CHAR 1
1678
1679 /* A function address in a call instruction is a byte address (for
1680 indexing purposes) so give the MEM rtx a byte's mode. */
1681
1682 #define FUNCTION_MODE QImode
1683
1684 #define SLOW_BYTE_ACCESS 0
1685
1686 /* Specify the machine mode that pointers have. After generation of
1687 RTL, the compiler makes no further distinction between pointers and
1688 any other objects of this machine mode. */
1689
1690 #define Pmode QImode
1691
1692 /* On the C4x we can write the following code. We have to clear the cache
1693 every time we execute it because the data in the stack could change.
1694
1695 laj $+4
1696 addi3 4,r11,ar0
1697 lda *ar0,ar1
1698 lda *+ar0(1),ar0
1699 bud ar1
1700 nop
1701 nop
1702 or 1000h,st
1703 .word FNADDR
1704 .word CXT
1705
1706 On the c3x this is a bit more difficult. We have to write self
1707 modifying code here. So we have to clear the cache every time
1708 we execute it because the data in the stack could change.
1709
1710 ldiu TOP_OF_FUNCTION,ar1
1711 lsh 16,ar1
1712 or BOTTOM_OF_FUNCTION,ar1
1713 ldiu TOP_OF_STATIC,ar0
1714 bud ar1
1715 lsh 16,ar0
1716 or BOTTOM_OF_STATIC,ar0
1717 or 1000h,st
1718
1719 */
1720
1721 #define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
1722
1723 #define TRAMPOLINE_TEMPLATE(FILE) \
1724 { \
1725 if (TARGET_C3X) \
1726 { \
1727 fprintf (FILE, "\tldiu\t0,ar1\n"); \
1728 fprintf (FILE, "\tlsh\t16,ar1\n"); \
1729 fprintf (FILE, "\tor\t0,ar1\n"); \
1730 fprintf (FILE, "\tldiu\t0,ar0\n"); \
1731 fprintf (FILE, "\tbud\tar1\n"); \
1732 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1733 fprintf (FILE, "\tor\t0,ar0\n"); \
1734 fprintf (FILE, "\tor\t1000h,st\n"); \
1735 } \
1736 else \
1737 { \
1738 fprintf (FILE, "\tlaj\t$+4\n"); \
1739 fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
1740 fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
1741 fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
1742 fprintf (FILE, "\tbud\tar1\n"); \
1743 fprintf (FILE, "\tnop\n"); \
1744 fprintf (FILE, "\tnop\n"); \
1745 fprintf (FILE, "\tor\t1000h,st\n"); \
1746 fprintf (FILE, "\t.word\t0\n"); \
1747 fprintf (FILE, "\t.word\t0\n"); \
1748 } \
1749 }
1750
1751 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1752 { \
1753 if (TARGET_C3X) \
1754 { \
1755 rtx tmp1, tmp2; \
1756 tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
1757 size_int (16), 0, 1); \
1758 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1759 GEN_INT (0x5069), size_int (16), 0, 1); \
1760 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1761 emit_move_insn (gen_rtx_MEM (QImode, \
1762 plus_constant (TRAMP, 0)), tmp1); \
1763 tmp1 = expand_and (QImode, FNADDR, GEN_INT (0xffff), 0); \
1764 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1765 GEN_INT (0x1069), size_int (16), 0, 1); \
1766 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1767 emit_move_insn (gen_rtx_MEM (QImode, \
1768 plus_constant (TRAMP, 2)), tmp1); \
1769 tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
1770 size_int (16), 0, 1); \
1771 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1772 GEN_INT (0x5068), size_int (16), 0, 1); \
1773 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1774 emit_move_insn (gen_rtx_MEM (QImode, \
1775 plus_constant (TRAMP, 3)), tmp1); \
1776 tmp1 = expand_and (QImode, CXT, GEN_INT (0xffff), 0); \
1777 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1778 GEN_INT (0x1068), size_int (16), 0, 1); \
1779 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1780 emit_move_insn (gen_rtx_MEM (QImode, \
1781 plus_constant (TRAMP, 6)), tmp1); \
1782 } \
1783 else \
1784 { \
1785 emit_move_insn (gen_rtx_MEM (QImode, \
1786 plus_constant (TRAMP, 8)), FNADDR); \
1787 emit_move_insn (gen_rtx_MEM (QImode, \
1788 plus_constant (TRAMP, 9)), CXT); \
1789 } \
1790 }
1791
1792 /* Specify the machine mode that this machine uses for the index in
1793 the tablejump instruction. */
1794
1795 #define CASE_VECTOR_MODE Pmode
1796
1797 /* Max number of (32-bit) bytes we can move from memory to memory
1798 in one reasonably fast instruction. */
1799
1800 #define MOVE_MAX 1
1801
1802 /* MOVE_RATIO is the number of move instructions that is better than a
1803 block move. */
1804
1805 #define MOVE_RATIO 3
1806
1807 #define BSS_SECTION_ASM_OP "\t.bss"
1808
1809 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
1810 fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
1811
1812 /* This is how to output an insn to pop a register from the stack.
1813 It need not be very fast code. */
1814
1815 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
1816 fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
1817
1818 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1819 is done just by pretending it is already truncated. */
1820
1821 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1822
1823 #define DBR_OUTPUT_SEQEND(FILE) \
1824 if (final_sequence != NULL_RTX) \
1825 { \
1826 int count; \
1827 rtx insn = XVECEXP (final_sequence, 0, 0); \
1828 int laj = GET_CODE (insn) == CALL_INSN \
1829 || (GET_CODE (insn) == INSN \
1830 && GET_CODE (PATTERN (insn)) == TRAP_IF);\
1831 \
1832 count = dbr_sequence_length(); \
1833 while (count < (laj ? 2 : 3)) \
1834 { \
1835 fputs("\tnop\n", FILE); \
1836 count++; \
1837 } \
1838 if (laj) \
1839 fputs("\tpush\tr11\n", FILE); \
1840 }
1841
1842 #define NO_FUNCTION_CSE
1843
1844 /* We don't want a leading tab. */
1845
1846 #define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
1847
1848 /* Define the codes that are matched by predicates in c4x.c. */
1849
1850 #define PREDICATE_CODES \
1851 {"fp_zero_operand", {CONST_DOUBLE}}, \
1852 {"const_operand", {CONST_INT, CONST_DOUBLE}}, \
1853 {"stik_const_operand", {CONST_INT}}, \
1854 {"not_const_operand", {CONST_INT}}, \
1855 {"reg_operand", {REG, SUBREG}}, \
1856 {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
1857 {"r0r1_reg_operand", {REG, SUBREG}}, \
1858 {"r2r3_reg_operand", {REG, SUBREG}}, \
1859 {"ext_low_reg_operand", {REG, SUBREG}}, \
1860 {"ext_reg_operand", {REG, SUBREG}}, \
1861 {"std_reg_operand", {REG, SUBREG}}, \
1862 {"std_or_reg_operand", {REG, SUBREG}}, \
1863 {"addr_reg_operand", {REG, SUBREG}}, \
1864 {"index_reg_operand", {REG, SUBREG}}, \
1865 {"dp_reg_operand", {REG}}, \
1866 {"sp_reg_operand", {REG}}, \
1867 {"st_reg_operand", {REG}}, \
1868 {"rc_reg_operand", {REG}}, \
1869 {"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \
1870 {"dst_operand", {SUBREG, REG, MEM}}, \
1871 {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
1872 {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
1873 {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
1874 {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
1875 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
1876 {"nonimmediate_lsrc_operand", {SUBREG, REG, MEM}}, \
1877 {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
1878 {"par_ind_operand", {MEM}}, \
1879 {"parallel_operand", {SUBREG, REG, MEM}}, \
1880 {"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
1881 {"mem_operand", {MEM}},
1882
1883
1884 /* Define the intrinsic functions for the c3x/c4x. */
1885
1886 enum c4x_builtins
1887 {
1888 /* intrinsic name */
1889 C4X_BUILTIN_FIX, /* fast_ftoi */
1890 C4X_BUILTIN_FIX_ANSI, /* ansi_ftoi */
1891 C4X_BUILTIN_MPYI, /* fast_imult (only C3x) */
1892 C4X_BUILTIN_TOIEEE, /* toieee (only C4x) */
1893 C4X_BUILTIN_FRIEEE, /* frieee (only C4x) */
1894 C4X_BUILTIN_RCPF /* fast_invf (only C4x) */
1895 };
1896
1897
1898 /* Hack to overcome use of libgcc2.c using auto-host.h to determine
1899 HAVE_GAS_HIDDEN. */
1900 #undef HAVE_GAS_HIDDEN
Mirror of the offical gcc git repository hosted at gcc.gnu.org