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Convert STARTING_FRAME_OFFSET to a hook
[official-gcc.git] / gcc / config / sh / sh.h
blobf5d80da1451745e990461f5794c360878df62db2
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993-2017 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef GCC_SH_H
23 #define GCC_SH_H
24
25 #include "config/vxworks-dummy.h"
26
27 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
28 include it here, because bconfig.h is also included by gencodes.c . */
29 /* ??? No longer true. */
30 extern int code_for_indirect_jump_scratch;
31
32 #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile)
33
34 /* Value should be nonzero if functions must have frame pointers.
35 Zero means the frame pointer need not be set up (and parms may be accessed
36 via the stack pointer) in functions that seem suitable. */
37
38 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
39 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
40 #endif
41
42 \f
43 /* Nonzero if this is an ELF target - compile time only */
44 #define TARGET_ELF 0
45
46 /* Nonzero if we should generate code using type 2E insns. */
47 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
48
49 /* Nonzero if we should generate code using type 2A insns. */
50 #define TARGET_SH2A TARGET_HARD_SH2A
51 /* Nonzero if we should generate code using type 2A SF insns. */
52 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
53 /* Nonzero if we should generate code using type 2A DF insns. */
54 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
55
56 /* Nonzero if we should generate code using type 3E insns. */
57 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
58
59 /* Nonzero if we schedule for a superscalar implementation. */
60 #define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A)
61
62 /* Nonzero if a double-precision FPU is available. */
63 #define TARGET_FPU_DOUBLE (TARGET_SH4 || TARGET_SH2A_DOUBLE)
64
65 /* Nonzero if an FPU is available. */
66 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
67
68 /* Nonzero if we're generating code for SH4a, unless the use of the
69 FPU is disabled (which makes it compatible with SH4al-dsp). */
70 #define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY)
71
72
73 /* This is not used by the SH2E calling convention */
74 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
75 (! TARGET_SH2E \
76 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
77
78 #ifndef TARGET_CPU_DEFAULT
79 #define TARGET_CPU_DEFAULT SELECT_SH1
80 #define SUPPORT_SH1 1
81 #define SUPPORT_SH2E 1
82 #define SUPPORT_SH4 1
83 #define SUPPORT_SH4_SINGLE 1
84 #define SUPPORT_SH2A 1
85 #define SUPPORT_SH2A_SINGLE 1
86 #endif
87
88 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
89 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
90 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
91
92 #define SELECT_SH1 (MASK_SH1)
93 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
94 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
95 | MASK_FPU_SINGLE)
96 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
97 | MASK_HARD_SH2A_DOUBLE \
98 | MASK_SH2 | MASK_SH1)
99 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
100 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
101 | MASK_SH1 | MASK_FPU_SINGLE \
102 | MASK_FPU_SINGLE_ONLY)
103 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
104 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
105 | MASK_SH2 | MASK_SH1)
106 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
107 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
108 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
109 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E \
110 | MASK_FPU_SINGLE_ONLY)
111 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
112 | SELECT_SH3)
113 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
114 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
115 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
116 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
117 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
118
119 #if SUPPORT_SH1
120 #define SUPPORT_SH2 1
121 #endif
122 #if SUPPORT_SH2
123 #define SUPPORT_SH3 1
124 #define SUPPORT_SH2A_NOFPU 1
125 #endif
126 #if SUPPORT_SH3
127 #define SUPPORT_SH4_NOFPU 1
128 #endif
129 #if SUPPORT_SH4_NOFPU
130 #define SUPPORT_SH4A_NOFPU 1
131 #define SUPPORT_SH4AL 1
132 #endif
133
134 #if SUPPORT_SH2E
135 #define SUPPORT_SH3E 1
136 #define SUPPORT_SH2A_SINGLE_ONLY 1
137 #endif
138 #if SUPPORT_SH3E
139 #define SUPPORT_SH4_SINGLE_ONLY 1
140 #endif
141 #if SUPPORT_SH4_SINGLE_ONLY
142 #define SUPPORT_SH4A_SINGLE_ONLY 1
143 #endif
144
145 #if SUPPORT_SH4
146 #define SUPPORT_SH4A 1
147 #endif
148
149 #if SUPPORT_SH4_SINGLE
150 #define SUPPORT_SH4A_SINGLE 1
151 #endif
152
153 /* Reset all target-selection flags. */
154 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
155 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
156 | MASK_HARD_SH4 | MASK_FPU_SINGLE \
157 | MASK_FPU_SINGLE_ONLY)
158
159 /* This defaults us to big-endian. */
160 #ifndef TARGET_ENDIAN_DEFAULT
161 #define TARGET_ENDIAN_DEFAULT 0
162 #endif
163
164 #ifndef TARGET_OPT_DEFAULT
165 #define TARGET_OPT_DEFAULT 0
166 #endif
167
168 #define TARGET_DEFAULT \
169 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
170
171 #ifndef SH_MULTILIB_CPU_DEFAULT
172 #define SH_MULTILIB_CPU_DEFAULT "m1"
173 #endif
174
175 #if TARGET_ENDIAN_DEFAULT
176 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
177 #else
178 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
179 #endif
180
181 #define CPP_SPEC " %(subtarget_cpp_spec) "
182
183 #ifndef SUBTARGET_CPP_SPEC
184 #define SUBTARGET_CPP_SPEC ""
185 #endif
186
187 #ifndef SUBTARGET_EXTRA_SPECS
188 #define SUBTARGET_EXTRA_SPECS
189 #endif
190
191 #define EXTRA_SPECS \
192 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
193 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
194 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
195 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
196 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
197 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
198 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
199 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
200 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
201 SUBTARGET_EXTRA_SPECS
202
203 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
204 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:-isa=sh4-up}}}"
205 #else
206 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
207 #endif
208
209 /* Define which ISA type to pass to the assembler.
210 For SH4 we pass SH4A to allow using some instructions that are available
211 on some SH4 variants, but officially are part of the SH4A ISA. */
212 #define SH_ASM_SPEC \
213 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \
214 %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \
215 %{m1:--isa=sh} \
216 %{m2:--isa=sh2} \
217 %{m2e:--isa=sh2e} \
218 %{m3:--isa=sh3} \
219 %{m3e:--isa=sh3e} \
220 %{m4:--isa=sh4a} \
221 %{m4-single:--isa=sh4a} \
222 %{m4-single-only:--isa=sh4a} \
223 %{m4-nofpu:--isa=sh4a-nofpu} \
224 %{m4a:--isa=sh4a} \
225 %{m4a-single:--isa=sh4a} \
226 %{m4a-single-only:--isa=sh4a} \
227 %{m4a-nofpu:--isa=sh4a-nofpu} \
228 %{m2a:--isa=sh2a} \
229 %{m2a-single:--isa=sh2a} \
230 %{m2a-single-only:--isa=sh2a} \
231 %{m2a-nofpu:--isa=sh2a-nofpu} \
232 %{m4al:-dsp}"
233
234 #define ASM_SPEC SH_ASM_SPEC
235
236 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
237 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
238 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
239 #else
240 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
241 #endif
242 #endif
243
244 #if STRICT_NOFPU == 1
245 /* Strict nofpu means that the compiler should tell the assembler
246 to reject FPU instructions. E.g. from ASM inserts. */
247 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
248 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}"
249 #else
250
251 #define SUBTARGET_ASM_ISA_SPEC \
252 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
253 #endif
254 #else /* ! STRICT_NOFPU */
255 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
256 #endif
257
258 #ifndef SUBTARGET_ASM_SPEC
259 #define SUBTARGET_ASM_SPEC "%{mfdpic:--fdpic}"
260 #endif
261
262 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
263 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
264 #else
265 #define LINK_EMUL_PREFIX "sh%{ml:l}"
266 #endif
267
268 #define LINK_DEFAULT_CPU_EMUL ""
269 #define ASM_ISA_DEFAULT_SPEC ""
270
271 #define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}"
272 #define SUBTARGET_LINK_SPEC ""
273
274 /* Go via SH_LINK_SPEC to avoid code replication. */
275 #define LINK_SPEC SH_LINK_SPEC
276
277 #define SH_LINK_SPEC "\
278 -m %(link_emul_prefix)\
279 %{!m1:%{!m2:%{!m3*:%{!m4*:%(link_default_cpu_emul)}}}}\
280 %(subtarget_link_emul_suffix) \
281 %{mrelax:-relax} %(subtarget_link_spec)"
282
283 #ifndef SH_DIV_STR_FOR_SIZE
284 #define SH_DIV_STR_FOR_SIZE "call"
285 #endif
286
287 /* SH2A does not support little-endian. Catch such combinations
288 taking into account the default configuration. */
289 #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN
290 #define IS_LITTLE_ENDIAN_OPTION "%{ml:"
291 #else
292 #define IS_LITTLE_ENDIAN_OPTION "%{!mb:"
293 #endif
294
295 #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A
296 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
297 "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:%eSH2a does not support little-endian}}}}}"
298 #else
299 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
300 "%{m2a*:%eSH2a does not support little-endian}}"
301 #endif
302
303 #ifdef FDPIC_DEFAULT
304 #define FDPIC_SELF_SPECS "%{!mno-fdpic:-mfdpic}"
305 #else
306 #define FDPIC_SELF_SPECS
307 #endif
308
309 #undef DRIVER_SELF_SPECS
310 #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A SUBTARGET_DRIVER_SELF_SPECS \
311 FDPIC_SELF_SPECS
312
313 #undef SUBTARGET_DRIVER_SELF_SPECS
314 #define SUBTARGET_DRIVER_SELF_SPECS
315
316 #define ASSEMBLER_DIALECT assembler_dialect
317
318 extern int assembler_dialect;
319
320 enum sh_divide_strategy_e {
321 /* SH1 .. SH4 strategies. Because of the small number of registers
322 available, the compiler uses knowledge of the actual set of registers
323 being clobbered by the different functions called. */
324 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
325 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
326 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
327 SH_DIV_INTRINSIC
328 };
329
330 extern enum sh_divide_strategy_e sh_div_strategy;
331
332 #ifndef SH_DIV_STRATEGY_DEFAULT
333 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL_DIV1
334 #endif
335
336 #ifdef __cplusplus
337
338 /* Atomic model. */
339 struct sh_atomic_model
340 {
341 enum enum_type
342 {
343 none = 0,
344 soft_gusa,
345 hard_llcs,
346 soft_tcb,
347 soft_imask,
348
349 num_models
350 };
351
352 /* If strict is set, disallow mixing of different models, as it would
353 happen on SH4A. */
354 bool strict;
355 enum_type type;
356
357 /* Name string as it was specified on the command line. */
358 const char* name;
359
360 /* Name string as it is used in C/C++ defines. */
361 const char* cdef_name;
362
363 /* GBR offset variable for TCB model. */
364 int tcb_gbr_offset;
365 };
366
367 extern const sh_atomic_model& selected_atomic_model (void);
368
369 /* Shortcuts to check the currently selected atomic model. */
370 #define TARGET_ATOMIC_ANY \
371 (selected_atomic_model ().type != sh_atomic_model::none)
372
373 #define TARGET_ATOMIC_STRICT \
374 (selected_atomic_model ().strict)
375
376 #define TARGET_ATOMIC_SOFT_GUSA \
377 (selected_atomic_model ().type == sh_atomic_model::soft_gusa)
378
379 #define TARGET_ATOMIC_HARD_LLCS \
380 (selected_atomic_model ().type == sh_atomic_model::hard_llcs)
381
382 #define TARGET_ATOMIC_SOFT_TCB \
383 (selected_atomic_model ().type == sh_atomic_model::soft_tcb)
384
385 #define TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX \
386 GEN_INT (selected_atomic_model ().tcb_gbr_offset)
387
388 #define TARGET_ATOMIC_SOFT_IMASK \
389 (selected_atomic_model ().type == sh_atomic_model::soft_imask)
390
391 #endif // __cplusplus
392
393 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
394
395 \f
396 /* Target machine storage layout. */
397
398 #define TARGET_BIG_ENDIAN (!TARGET_LITTLE_ENDIAN)
399
400 #define SH_REG_MSW_OFFSET (TARGET_LITTLE_ENDIAN ? 1 : 0)
401 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1)
402
403 /* Define this if most significant bit is lowest numbered
404 in instructions that operate on numbered bit-fields. */
405 #define BITS_BIG_ENDIAN 0
406
407 /* Define this if most significant byte of a word is the lowest numbered. */
408 #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN
409
410 /* Define this if most significant word of a multiword number is the lowest
411 numbered. */
412 #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN
413
414 #define MAX_BITS_PER_WORD 64
415
416 /* Width in bits of an `int'. We want just 32-bits, even if words are
417 longer. */
418 #define INT_TYPE_SIZE 32
419
420 /* Width in bits of a `long'. */
421 #define LONG_TYPE_SIZE (32)
422
423 /* Width in bits of a `long long'. */
424 #define LONG_LONG_TYPE_SIZE 64
425
426 /* Width in bits of a `long double'. */
427 #define LONG_DOUBLE_TYPE_SIZE 64
428
429 /* Width of a word, in units (bytes). */
430 #define UNITS_PER_WORD (4)
431 #define MIN_UNITS_PER_WORD 4
432
433 /* Scaling factor for Dwarf data offsets for CFI information.
434 The dwarf2out.c default would use -UNITS_PER_WORD. */
435 #define DWARF_CIE_DATA_ALIGNMENT -4
436
437 /* Width in bits of a pointer.
438 See also the macro `Pmode' defined below. */
439 #define POINTER_SIZE (32)
440
441 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
442 #define PARM_BOUNDARY (32)
443
444 /* Boundary (in *bits*) on which stack pointer should be aligned. */
445 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
446
447 /* The log (base 2) of the cache line size, in bytes. Processors prior to
448 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
449 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
450 #define CACHE_LOG (TARGET_HARD_SH4 ? 5 : TARGET_SH2 ? 4 : 2)
451
452 /* ABI given & required minimum allocation boundary (in *bits*) for the
453 code of a function. */
454 #define FUNCTION_BOUNDARY (16)
455
456 /* Alignment of field after `int : 0' in a structure. */
457 #define EMPTY_FIELD_BOUNDARY 32
458
459 /* No data type wants to be aligned rounder than this. */
460 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
461
462 /* The best alignment to use in cases where we have a choice. */
463 #define FASTEST_ALIGNMENT (32)
464
465 /* get_mode_alignment assumes complex values are always held in multiple
466 registers, but that is not the case on the SH; CQImode and CHImode are
467 held in a single integer register. */
468 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
469 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
470 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
471 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
472 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
473
474 /* Make arrays of chars word-aligned for the same reasons. */
475 #define DATA_ALIGNMENT(TYPE, ALIGN) \
476 (TREE_CODE (TYPE) == ARRAY_TYPE \
477 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
478 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
479
480 /* Number of bits which any structure or union's size must be a
481 multiple of. Each structure or union's size is rounded up to a
482 multiple of this. */
483 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
484
485 /* Set this nonzero if move instructions will actually fail to work
486 when given unaligned data. */
487 #define STRICT_ALIGNMENT 1
488
489 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
490 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
491 barrier_align (LABEL_AFTER_BARRIER)
492
493 #define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL)
494
495 #define LABEL_ALIGN(A_LABEL) \
496 ( \
497 (PREV_INSN (A_LABEL) \
498 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
499 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
500 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
501 /* explicit alignment insn in constant tables. */ \
502 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
503 : 0)
504
505 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
506 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
507
508 /* The base two logarithm of the known minimum alignment of an insn length. */
509 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
510 (NONJUMP_INSN_P (A_INSN) \
511 ? 1 \
512 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
513 ? 1 \
514 : CACHE_LOG)
515 \f
516 /* Standard register usage. */
517
518 /* Register allocation for the Renesas calling convention:
519
520 r0 arg return
521 r1..r3 scratch
522 r4..r7 args in
523 r8..r13 call saved
524 r14 frame pointer/call saved
525 r15 stack pointer
526 ap arg pointer (doesn't really exist, always eliminated)
527 pr subroutine return address
528 t t bit
529 mach multiply/accumulate result, high part
530 macl multiply/accumulate result, low part.
531 fpul fp/int communication register
532 rap return address pointer register
533 fr0 fp arg return
534 fr1..fr3 scratch floating point registers
535 fr4..fr11 fp args in
536 fr12..fr15 call saved floating point registers */
537
538 #define MAX_REGISTER_NAME_LENGTH 6
539 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
540
541 #define SH_REGISTER_NAMES_INITIALIZER \
542 { \
543 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
544 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
545 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
546 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
547 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
548 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
549 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
550 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
551 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
552 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
553 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
554 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
555 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
556 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
557 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
558 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
559 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
560 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
561 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
562 "rap", "sfp", "fpscr0", "fpscr1" \
563 }
564
565 #define REGNAMES_ARR_INDEX_1(index) \
566 (sh_register_names[index])
567 #define REGNAMES_ARR_INDEX_2(index) \
568 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
569 #define REGNAMES_ARR_INDEX_4(index) \
570 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
571 #define REGNAMES_ARR_INDEX_8(index) \
572 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
573 #define REGNAMES_ARR_INDEX_16(index) \
574 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
575 #define REGNAMES_ARR_INDEX_32(index) \
576 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
577 #define REGNAMES_ARR_INDEX_64(index) \
578 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
579
580 #define REGISTER_NAMES \
581 { \
582 REGNAMES_ARR_INDEX_64 (0), \
583 REGNAMES_ARR_INDEX_64 (64), \
584 REGNAMES_ARR_INDEX_8 (128), \
585 REGNAMES_ARR_INDEX_8 (136), \
586 REGNAMES_ARR_INDEX_8 (144), \
587 REGNAMES_ARR_INDEX_4 (152) \
588 }
589
590 #define ADDREGNAMES_SIZE 32
591 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
592 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
593 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
594
595 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
596 { \
597 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
598 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
599 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
600 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
601 }
602
603 #define ADDREGNAMES_REGNO(index) \
604 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
605 : (-1))
606
607 #define ADDREGNAMES_ARR_INDEX_1(index) \
608 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
609 #define ADDREGNAMES_ARR_INDEX_2(index) \
610 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
611 #define ADDREGNAMES_ARR_INDEX_4(index) \
612 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
613 #define ADDREGNAMES_ARR_INDEX_8(index) \
614 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
615 #define ADDREGNAMES_ARR_INDEX_16(index) \
616 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
617 #define ADDREGNAMES_ARR_INDEX_32(index) \
618 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
619
620 #define ADDITIONAL_REGISTER_NAMES \
621 { \
622 ADDREGNAMES_ARR_INDEX_32 (0) \
623 }
624
625 /* Number of actual hardware registers.
626 The hardware registers are assigned numbers for the compiler
627 from 0 to just below FIRST_PSEUDO_REGISTER.
628 All registers that the compiler knows about must be given numbers,
629 even those that are not normally considered general registers. */
630
631 /* There are many other relevant definitions in sh.md's md_constants. */
632
633 #define FIRST_GENERAL_REG R0_REG
634 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (15))
635 #define FIRST_FP_REG DR0_REG
636 #define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1))
637 #define FIRST_XD_REG XD0_REG
638 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
639
640 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
641 #define FIRST_BANKED_REG R0_REG
642 #define LAST_BANKED_REG R7_REG
643
644 #define BANKED_REGISTER_P(REGNO) \
645 IN_RANGE ((REGNO), \
646 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
647 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
648
649 #define GENERAL_REGISTER_P(REGNO) \
650 IN_RANGE ((REGNO), \
651 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
652 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
653
654 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
655 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
656 || ((REGNO) == FRAME_POINTER_REGNUM))
657
658 #define FP_REGISTER_P(REGNO) \
659 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
660
661 #define XD_REGISTER_P(REGNO) \
662 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
663
664 #define FP_OR_XD_REGISTER_P(REGNO) \
665 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
666
667 #define FP_ANY_REGISTER_P(REGNO) \
668 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
669
670 #define SPECIAL_REGISTER_P(REGNO) \
671 ((REGNO) == GBR_REG || (REGNO) == T_REG \
672 || (REGNO) == MACH_REG || (REGNO) == MACL_REG \
673 || (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG)
674
675 #define VALID_REGISTER_P(REGNO) \
676 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
677 || XD_REGISTER_P (REGNO) \
678 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
679 || (REGNO) == FRAME_POINTER_REGNUM \
680 || ((SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
681 || (TARGET_SH2E && (REGNO) == FPUL_REG))
682
683 /* The mode that should be generally used to store a register by
684 itself in the stack, or to load it back. */
685 #define REGISTER_NATURAL_MODE(REGNO) \
686 (FP_REGISTER_P (REGNO) ? E_SFmode \
687 : XD_REGISTER_P (REGNO) ? E_DFmode : E_SImode)
688
689
690 #define FIRST_PSEUDO_REGISTER 156
691
692 /* Don't count soft frame pointer. */
693 #define DWARF_FRAME_REGISTERS (153)
694
695 /* 1 for registers that have pervasive standard uses
696 and are not available for the register allocator.
697
698 Mach register is fixed 'cause it's only 10 bits wide for SH1.
699 It is 32 bits wide for SH2. */
700 #define FIXED_REGISTERS \
701 { \
702 /* Regular registers. */ \
703 0, 0, 0, 0, 0, 0, 0, 0, \
704 0, 0, 0, 0, 0, 0, 0, 1, \
705 /* r16 is reserved, r18 is the former pr. */ \
706 1, 0, 0, 0, 0, 0, 0, 0, \
707 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
708 /* r26 is a global variable data pointer; r27 is for constants. */ \
709 1, 1, 1, 1, 0, 0, 0, 0, \
710 0, 0, 0, 0, 0, 0, 0, 0, \
711 0, 0, 0, 0, 0, 0, 0, 0, \
712 0, 0, 0, 0, 0, 0, 0, 0, \
713 0, 0, 0, 0, 0, 0, 0, 1, \
714 /* FP registers. */ \
715 0, 0, 0, 0, 0, 0, 0, 0, \
716 0, 0, 0, 0, 0, 0, 0, 0, \
717 0, 0, 0, 0, 0, 0, 0, 0, \
718 0, 0, 0, 0, 0, 0, 0, 0, \
719 0, 0, 0, 0, 0, 0, 0, 0, \
720 0, 0, 0, 0, 0, 0, 0, 0, \
721 0, 0, 0, 0, 0, 0, 0, 0, \
722 0, 0, 0, 0, 0, 0, 0, 0, \
723 /* Branch target registers. */ \
724 0, 0, 0, 0, 0, 0, 0, 0, \
725 /* XD registers. */ \
726 0, 0, 0, 0, 0, 0, 0, 0, \
727 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
728 1, 1, 1, 1, 1, 1, 0, 1, \
729 /*"rap", "sfp","fpscr0","fpscr1" */ \
730 1, 1, 1, 1, \
731 }
732
733 /* 1 for registers not available across function calls.
734 These must include the FIXED_REGISTERS and also any
735 registers that can be used without being saved.
736 The latter must include the registers where values are returned
737 and the register where structure-value addresses are passed.
738 Aside from that, you can include as many other registers as you like. */
739 #define CALL_USED_REGISTERS \
740 { \
741 /* Regular registers. */ \
742 1, 1, 1, 1, 1, 1, 1, 1, \
743 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
744 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
745 across SH5 function calls. */ \
746 0, 0, 0, 0, 0, 0, 0, 1, \
747 1, 1, 1, 1, 1, 1, 1, 1, \
748 1, 1, 1, 1, 0, 0, 0, 0, \
749 0, 0, 0, 0, 1, 1, 1, 1, \
750 1, 1, 1, 1, 0, 0, 0, 0, \
751 0, 0, 0, 0, 0, 0, 0, 0, \
752 0, 0, 0, 0, 1, 1, 1, 1, \
753 /* FP registers. */ \
754 1, 1, 1, 1, 1, 1, 1, 1, \
755 1, 1, 1, 1, 0, 0, 0, 0, \
756 1, 1, 1, 1, 1, 1, 1, 1, \
757 1, 1, 1, 1, 1, 1, 1, 1, \
758 1, 1, 1, 1, 0, 0, 0, 0, \
759 0, 0, 0, 0, 0, 0, 0, 0, \
760 0, 0, 0, 0, 0, 0, 0, 0, \
761 0, 0, 0, 0, 0, 0, 0, 0, \
762 /* Branch target registers. */ \
763 1, 1, 1, 1, 1, 0, 0, 0, \
764 /* XD registers. */ \
765 1, 1, 1, 1, 1, 1, 0, 0, \
766 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
767 1, 1, 1, 1, 1, 1, 1, 1, \
768 /*"rap", "sfp","fpscr0","fpscr1" */ \
769 1, 1, 1, 1, \
770 }
771
772 /* CALL_REALLY_USED_REGISTERS is used as a default setting, which is then
773 overridden by -fcall-saved-* and -fcall-used-* options and then by
774 TARGET_CONDITIONAL_REGISTER_USAGE. There we might want to make a
775 register call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */
776 #define CALL_REALLY_USED_REGISTERS \
777 { \
778 /* Regular registers. */ \
779 1, 1, 1, 1, 1, 1, 1, 1, \
780 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
781 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
782 across SH5 function calls. */ \
783 0, 0, 0, 0, 0, 0, 0, 1, \
784 1, 1, 1, 1, 1, 1, 1, 1, \
785 1, 1, 1, 1, 0, 0, 0, 0, \
786 0, 0, 0, 0, 1, 1, 1, 1, \
787 1, 1, 1, 1, 0, 0, 0, 0, \
788 0, 0, 0, 0, 0, 0, 0, 0, \
789 0, 0, 0, 0, 1, 1, 1, 1, \
790 /* FP registers. */ \
791 1, 1, 1, 1, 1, 1, 1, 1, \
792 1, 1, 1, 1, 0, 0, 0, 0, \
793 1, 1, 1, 1, 1, 1, 1, 1, \
794 1, 1, 1, 1, 1, 1, 1, 1, \
795 1, 1, 1, 1, 0, 0, 0, 0, \
796 0, 0, 0, 0, 0, 0, 0, 0, \
797 0, 0, 0, 0, 0, 0, 0, 0, \
798 0, 0, 0, 0, 0, 0, 0, 0, \
799 /* Branch target registers. */ \
800 1, 1, 1, 1, 1, 0, 0, 0, \
801 /* XD registers. */ \
802 1, 1, 1, 1, 1, 1, 0, 0, \
803 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
804 0, 1, 1, 1, 1, 1, 1, 1, \
805 /*"rap", "sfp","fpscr0","fpscr1" */ \
806 1, 1, 0, 0, \
807 }
808
809 /* Specify the modes required to caller save a given hard regno. */
810 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
811 sh_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
812
813 /* A C expression that is nonzero if hard register NEW_REG can be
814 considered for use as a rename register for OLD_REG register */
815 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
816 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
817
818 /* Specify the registers used for certain standard purposes.
819 The values of these macros are register numbers. */
820
821 /* Define this if the program counter is overloaded on a register. */
822 /* #define PC_REGNUM 15*/
823
824 /* Register to use for pushing function arguments. */
825 #define STACK_POINTER_REGNUM SP_REG
826
827 /* Base register for access to local variables of the function. */
828 #define HARD_FRAME_POINTER_REGNUM FP_REG
829
830 /* Base register for access to local variables of the function. */
831 #define FRAME_POINTER_REGNUM 153
832
833 /* Fake register that holds the address on the stack of the
834 current function's return address. */
835 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
836
837 /* Register to hold the addressing base for position independent
838 code access to data items. */
839 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
840
841 /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT
842 entries would need to handle saving and restoring it). */
843 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC
844
845 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
846
847 /* Definitions for register eliminations.
848
849 We have three registers that can be eliminated on the SH. First, the
850 frame pointer register can often be eliminated in favor of the stack
851 pointer register. Secondly, the argument pointer register can always be
852 eliminated; it is replaced with either the stack or frame pointer.
853 Third, there is the return address pointer, which can also be replaced
854 with either the stack or the frame pointer.
855
856 This is an array of structures. Each structure initializes one pair
857 of eliminable registers. The "from" register number is given first,
858 followed by "to". Eliminations of the same "from" register are listed
859 in order of preference.
860
861 If you add any registers here that are not actually hard registers,
862 and that have any alternative of elimination that doesn't always
863 apply, you need to amend calc_live_regs to exclude it, because
864 reload spills all eliminable registers where it sees an
865 can_eliminate == 0 entry, thus making them 'live' .
866 If you add any hard registers that can be eliminated in different
867 ways, you have to patch reload to spill them only when all alternatives
868 of elimination fail. */
869 #define ELIMINABLE_REGS \
870 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
871 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
872 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
873 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
874 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
875 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
876 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
877
878 /* Define the offset between two registers, one to be eliminated, and the other
879 its replacement, at the start of a routine. */
880 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
881 OFFSET = initial_elimination_offset ((FROM), (TO))
882
883 /* Base register for access to arguments of the function. */
884 #define ARG_POINTER_REGNUM AP_REG
885
886 /* Register in which the static-chain is passed to a function. */
887 #define STATIC_CHAIN_REGNUM (3)
888
889 /* Don't default to pcc-struct-return, because we have already specified
890 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
891 target hook. */
892 #define DEFAULT_PCC_STRUCT_RETURN 0
893
894 \f
895 /* Define the classes of registers for register constraints in the
896 machine description. Also define ranges of constants.
897
898 One of the classes must always be named ALL_REGS and include all hard regs.
899 If there is more than one class, another class must be named NO_REGS
900 and contain no registers.
901
902 The name GENERAL_REGS must be the name of a class (or an alias for
903 another name such as ALL_REGS). This is the class of registers
904 that is allowed by "g" or "r" in a register constraint.
905 Also, registers outside this class are allocated only when
906 instructions express preferences for them.
907
908 The classes must be numbered in nondecreasing order; that is,
909 a larger-numbered class must never be contained completely
910 in a smaller-numbered class.
911
912 For any two classes, it is very desirable that there be another
913 class that represents their union.
914
915 The SH has two sorts of general registers, R0 and the rest. R0 can
916 be used as the destination of some of the arithmetic ops. There are
917 also some special purpose registers; the T bit register, the
918 Procedure Return Register and the Multiply Accumulate Registers.
919
920 Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
921 reg_class_subunion. We don't want to have an actual union class
922 of these, because it would only be used when both classes are calculated
923 to give the same cost, but there is only one FPUL register.
924 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
925 applying to the actual instruction alternative considered. E.g., the
926 y/r alternative of movsi_ie is considered to have no more cost that
927 the r/r alternative, which is patently untrue. */
928 enum reg_class
929 {
930 NO_REGS,
931 R0_REGS,
932 PR_REGS,
933 T_REGS,
934 MAC_REGS,
935 FPUL_REGS,
936 SIBCALL_REGS,
937 NON_SP_REGS,
938 GENERAL_REGS,
939 FP0_REGS,
940 FP_REGS,
941 DF_REGS,
942 FPSCR_REGS,
943 GENERAL_FP_REGS,
944 GENERAL_DF_REGS,
945 TARGET_REGS,
946 ALL_REGS,
947 LIM_REG_CLASSES
948 };
949
950 #define N_REG_CLASSES (int) LIM_REG_CLASSES
951
952 /* Give names of register classes as strings for dump file. */
953 #define REG_CLASS_NAMES \
954 { \
955 "NO_REGS", \
956 "R0_REGS", \
957 "PR_REGS", \
958 "T_REGS", \
959 "MAC_REGS", \
960 "FPUL_REGS", \
961 "SIBCALL_REGS", \
962 "NON_SP_REGS", \
963 "GENERAL_REGS", \
964 "FP0_REGS", \
965 "FP_REGS", \
966 "DF_REGS", \
967 "FPSCR_REGS", \
968 "GENERAL_FP_REGS", \
969 "GENERAL_DF_REGS", \
970 "TARGET_REGS", \
971 "ALL_REGS", \
972 }
973
974 /* Define which registers fit in which classes.
975 This is an initializer for a vector of HARD_REG_SET
976 of length N_REG_CLASSES. */
977 #define REG_CLASS_CONTENTS \
978 { \
979 /* NO_REGS: */ \
980 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
981 /* R0_REGS: */ \
982 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
983 /* PR_REGS: */ \
984 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
985 /* T_REGS: */ \
986 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
987 /* MAC_REGS: */ \
988 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
989 /* FPUL_REGS: */ \
990 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
991 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
992 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
993 /* NON_SP_REGS: */ \
994 { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
995 /* GENERAL_REGS: */ \
996 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
997 /* FP0_REGS: */ \
998 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
999 /* FP_REGS: */ \
1000 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1001 /* DF_REGS: */ \
1002 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1003 /* FPSCR_REGS: */ \
1004 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1005 /* GENERAL_FP_REGS: */ \
1006 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1007 /* GENERAL_DF_REGS: */ \
1008 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1009 /* TARGET_REGS: */ \
1010 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1011 /* ALL_REGS: */ \
1012 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0fffffff }, \
1013 }
1014
1015 /* The same information, inverted:
1016 Return the class number of the smallest class containing
1017 reg number REGNO. This could be a conditional expression
1018 or could index an array. */
1019 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1020 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1021
1022 /* When this hook returns true for MODE, the compiler allows
1023 registers explicitly used in the rtl to be used as spill registers
1024 but prevents the compiler from extending the lifetime of these
1025 registers. */
1026 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1027 sh_small_register_classes_for_mode_p
1028
1029 /* The order in which register should be allocated. */
1030 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1031 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1032 spilled or used otherwise, we better have the FP_REGS allocated first. */
1033 #define REG_ALLOC_ORDER \
1034 {/* Caller-saved FPRs */ \
1035 65, 66, 67, 68, 69, 70, 71, 64, \
1036 72, 73, 74, 75, 80, 81, 82, 83, \
1037 84, 85, 86, 87, 88, 89, 90, 91, \
1038 92, 93, 94, 95, 96, 97, 98, 99, \
1039 /* Callee-saved FPRs */ \
1040 76, 77, 78, 79,100,101,102,103, \
1041 104,105,106,107,108,109,110,111, \
1042 112,113,114,115,116,117,118,119, \
1043 120,121,122,123,124,125,126,127, \
1044 136,137,138,139,140,141,142,143, \
1045 /* FPSCR */ 151, \
1046 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1047 1, 2, 3, 7, 6, 5, 4, 0, \
1048 8, 9, 17, 19, 20, 21, 22, 23, \
1049 36, 37, 38, 39, 40, 41, 42, 43, \
1050 60, 61, 62, \
1051 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1052 10, 11, 12, 13, 14, 18, \
1053 /* SH5 callee-saved GPRs */ \
1054 28, 29, 30, 31, 32, 33, 34, 35, \
1055 44, 45, 46, 47, 48, 49, 50, 51, \
1056 52, 53, 54, 55, 56, 57, 58, 59, \
1057 /* FPUL */ 150, \
1058 /* Fixed registers */ \
1059 15, 16, 24, 25, 26, 27, 63,144, \
1060 145,146,147,148,149,152,153,154,155 }
1061
1062 /* The class value for index registers, and the one for base regs. */
1063 #define INDEX_REG_CLASS R0_REGS
1064 #define BASE_REG_CLASS GENERAL_REGS
1065 \f
1066 /* Defines for sh.md and constraints.md. */
1067
1068 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1069 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1070
1071 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1072 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1073
1074 #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\
1075 (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX))
1076
1077 /* Return the maximum number of consecutive registers
1078 needed to represent mode MODE in a register of class CLASS.
1079
1080 If TARGET_SHMEDIA, we need two FP registers per word.
1081 Otherwise we will need at most one register per word. */
1082 #define CLASS_MAX_NREGS(CLASS, MODE) \
1083 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1084 \f
1085 /* Stack layout; function entry, exit and calling. */
1086
1087 /* Define the number of registers that can hold parameters.
1088 These macros are used only in other macro definitions below. */
1089 #define NPARM_REGS(MODE) \
1090 (TARGET_FPU_ANY && (MODE) == SFmode \
1091 ? 8 \
1092 : TARGET_FPU_DOUBLE \
1093 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1094 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1095 ? 8 \
1096 : 4)
1097
1098 #define FIRST_PARM_REG (FIRST_GENERAL_REG + 4)
1099 #define FIRST_RET_REG (FIRST_GENERAL_REG + 0)
1100
1101 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
1102 #define FIRST_FP_RET_REG FIRST_FP_REG
1103
1104 /* Define this if pushing a word on the stack
1105 makes the stack pointer a smaller address. */
1106 #define STACK_GROWS_DOWNWARD 1
1107
1108 /* Define this macro to nonzero if the addresses of local variable slots
1109 are at negative offsets from the frame pointer. */
1110 #define FRAME_GROWS_DOWNWARD 1
1111
1112 /* If we generate an insn to push BYTES bytes,
1113 this says how many the stack pointer really advances by. */
1114 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1115 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1116 do correct alignment. */
1117 #if 0
1118 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1119 #endif
1120
1121 /* Offset of first parameter from the argument pointer register value. */
1122 #define FIRST_PARM_OFFSET(FNDECL) 0
1123
1124 /* Value is the number of bytes of arguments automatically popped when
1125 calling a subroutine.
1126 CUM is the accumulated argument list. */
1127 #define CALL_POPS_ARGS(CUM) (0)
1128
1129 /* Some subroutine macros specific to this machine. */
1130
1131 #define BASE_RETURN_VALUE_REG(MODE) \
1132 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1133 ? FIRST_FP_RET_REG \
1134 : TARGET_FPU_ANY && (MODE) == SCmode \
1135 ? FIRST_FP_RET_REG \
1136 : (TARGET_FPU_DOUBLE \
1137 && ((MODE) == DFmode || (MODE) == SFmode \
1138 || (MODE) == DCmode || (MODE) == SCmode )) \
1139 ? FIRST_FP_RET_REG \
1140 : FIRST_RET_REG)
1141
1142 #define BASE_ARG_REG(MODE) \
1143 ((TARGET_SH2E && ((MODE) == SFmode)) \
1144 ? FIRST_FP_PARM_REG \
1145 : TARGET_FPU_DOUBLE \
1146 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1147 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1148 ? FIRST_FP_PARM_REG \
1149 : FIRST_PARM_REG)
1150
1151 /* 1 if N is a possible register number for function argument passing. */
1152 /* ??? There are some callers that pass REGNO as int, and others that pass
1153 it as unsigned. We get warnings unless we do casts everywhere. */
1154 #define FUNCTION_ARG_REGNO_P(REGNO) \
1155 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1156 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1157 || (TARGET_FPU_ANY \
1158 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1159 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1160 + NPARM_REGS (SFmode))))
1161 \f
1162 #ifdef __cplusplus
1163
1164 /* Define a data type for recording info about an argument list
1165 during the scan of that argument list. This data type should
1166 hold all necessary information about the function itself
1167 and about the args processed so far, enough to enable macros
1168 such as FUNCTION_ARG to determine where the next arg should go.
1169
1170 On SH, this is a single integer, which is a number of words
1171 of arguments scanned so far (including the invisible argument,
1172 if any, which holds the structure-value-address).
1173 Thus NARGREGS or more means all following args should go on the stack. */
1174
1175 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1176
1177 struct sh_args
1178 {
1179 /* How many SH_ARG_INT and how many SH_ARG_FLOAT args there are. */
1180 int arg_count[2];
1181
1182 bool force_mem;
1183
1184 /* Nonzero if a prototype is available for the function. */
1185 bool prototype_p;
1186
1187 /* The number of an odd floating-point register, that should be used
1188 for the next argument of type float. */
1189 int free_single_fp_reg;
1190
1191 /* Whether we're processing an outgoing function call. */
1192 bool outgoing;
1193
1194 /* This is set to nonzero when the call in question must use the Renesas ABI,
1195 even without the -mrenesas option. */
1196 bool renesas_abi;
1197 };
1198
1199 typedef sh_args CUMULATIVE_ARGS;
1200
1201 /* Set when processing a function with interrupt attribute. */
1202 extern bool current_function_interrupt;
1203
1204 #endif // __cplusplus
1205
1206 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1207 for a call to a function whose data type is FNTYPE.
1208 For a library call, FNTYPE is 0.
1209
1210 On SH, the offset always starts at 0: the first parm reg is always
1211 the same reg for a given argument class.
1212
1213 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1214 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1215 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\
1216 (N_NAMED_ARGS), VOIDmode)
1217
1218 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1219 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1220
1221 /* By accident we got stuck with passing SCmode on SH4 little endian
1222 in two registers that are nominally successive - which is different from
1223 two single SFmode values, where we take endianness translation into
1224 account. That does not work at all if an odd number of registers is
1225 already in use, so that got fixed, but library functions are still more
1226 likely to use complex numbers without mixing them with SFmode arguments
1227 (which in C would have to be structures), so for the sake of ABI
1228 compatibility the way SCmode values are passed when an even number of
1229 FP registers is in use remains different from a pair of SFmode values for
1230 now.
1231 I.e.:
1232 foo (double); a: fr5,fr4
1233 foo (float a, float b); a: fr5 b: fr4
1234 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1235 this should be the other way round...
1236 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1237 #define FUNCTION_ARG_SCmode_WART 1
1238
1239 /* Minimum alignment for an argument to be passed by callee-copy
1240 reference. We need such arguments to be aligned to 8 byte
1241 boundaries, because they'll be loaded using quad loads. */
1242 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1243
1244 /* Perform any needed actions needed for a function that is receiving a
1245 variable number of arguments. */
1246
1247 /* Call the function profiler with a given profile label.
1248 We use two .aligns, so as to make sure that both the .long is aligned
1249 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1250 from the trapa instruction. */
1251 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1252 { \
1253 fprintf((STREAM), "\t.align\t2\n"); \
1254 fprintf((STREAM), "\ttrapa\t#33\n"); \
1255 fprintf((STREAM), "\t.align\t2\n"); \
1256 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1257 }
1258
1259 /* Define this macro if the code for function profiling should come
1260 before the function prologue. Normally, the profiling code comes
1261 after. */
1262 #define PROFILE_BEFORE_PROLOGUE
1263
1264 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1265 the stack pointer does not matter. The value is tested only in
1266 functions that have frame pointers.
1267 No definition is equivalent to always zero. */
1268 #define EXIT_IGNORE_STACK 1
1269
1270 /*
1271 On the SH, the trampoline looks like
1272 2 0002 D202 mov.l l2,r2
1273 1 0000 D301 mov.l l1,r3
1274 3 0004 422B jmp @r2
1275 4 0006 0009 nop
1276 5 0008 00000000 l1: .long area
1277 6 000c 00000000 l2: .long function */
1278
1279 /* Length in units of the trampoline for entering a nested function. */
1280 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : 16)
1281
1282 /* Alignment required for a trampoline in bits. */
1283 #define TRAMPOLINE_ALIGNMENT \
1284 ((CACHE_LOG < 3 \
1285 || (optimize_size && ! (TARGET_HARD_SH4))) ? 32 \
1286 : 64)
1287
1288 /* A C expression whose value is RTL representing the value of the return
1289 address for the frame COUNT steps up from the current frame.
1290 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1291 can ignore COUNT. */
1292 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1293 (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX)
1294
1295 /* A C expression whose value is RTL representing the location of the
1296 incoming return address at the beginning of any function, before the
1297 prologue. This RTL is either a REG, indicating that the return
1298 value is saved in REG, or a MEM representing a location in
1299 the stack. */
1300 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, PR_REG)
1301 \f
1302 /* Addressing modes, and classification of registers for them. */
1303 #define HAVE_POST_INCREMENT TARGET_SH1
1304 #define HAVE_PRE_DECREMENT TARGET_SH1
1305
1306 #define USE_LOAD_POST_INCREMENT(mode) TARGET_SH1
1307 #define USE_LOAD_PRE_DECREMENT(mode) TARGET_SH2A
1308 #define USE_STORE_POST_INCREMENT(mode) TARGET_SH2A
1309 #define USE_STORE_PRE_DECREMENT(mode) TARGET_SH1
1310
1311 /* If a memory clear move would take CLEAR_RATIO or more simple
1312 move-instruction pairs, we will do a setmem instead. */
1313
1314 #define CLEAR_RATIO(speed) ((speed) ? 15 : 3)
1315
1316 /* Macros to check register numbers against specific register classes. */
1317
1318 /* These assume that REGNO is a hard or pseudo reg number.
1319 They give nonzero only if REGNO is a hard reg of the suitable class
1320 or a pseudo reg currently allocated to a suitable hard reg.
1321 Since they use reg_renumber, they are safe only once reg_renumber
1322 has been allocated, which happens in reginfo.c during register
1323 allocation. */
1324 #define REGNO_OK_FOR_BASE_P(REGNO) \
1325 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1326 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1327 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1328 ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1329
1330 /* True if SYMBOL + OFFSET constants must refer to something within
1331 SYMBOL's section. */
1332 #define SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P TARGET_FDPIC
1333
1334 /* Maximum number of registers that can appear in a valid memory
1335 address. */
1336 #define MAX_REGS_PER_ADDRESS 2
1337
1338 /* Recognize any constant value that is a valid address. */
1339 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1340
1341 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1342 and check its validity for a certain class.
1343 The suitable hard regs are always accepted and all pseudo regs
1344 are also accepted if STRICT is not set. */
1345
1346 /* Nonzero if X is a reg that can be used as a base reg. */
1347 #define REG_OK_FOR_BASE_P(X, STRICT) \
1348 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1349 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1350
1351 /* Nonzero if X is a reg that can be used as an index. */
1352 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1353 ((REGNO (X) == R0_REG) \
1354 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1355
1356 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1357 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1358 ((REGNO (X) == R0_REG && OFFSET == 0) \
1359 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1360
1361 /* Macros for extra constraints. */
1362
1363 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1364 ((GET_CODE ((OP)) == LABEL_REF) \
1365 || (GET_CODE ((OP)) == CONST \
1366 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1367 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1368 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1369
1370 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1371 (CONSTANT_P (OP) \
1372 && !CONST_INT_P (OP) \
1373 && GET_CODE (OP) != CONST_DOUBLE \
1374 && (!flag_pic \
1375 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1376 && !PIC_ADDR_P (OP) \
1377 && GET_CODE (OP) != LABEL_REF)))
1378
1379 #define GOT_ENTRY_P(OP) \
1380 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1381 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1382
1383 #define GOTPLT_ENTRY_P(OP) \
1384 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1385 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1386
1387 #define UNSPEC_GOTOFF_P(OP) \
1388 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1389
1390 #define GOTOFF_P(OP) \
1391 (GET_CODE (OP) == CONST \
1392 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1393 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1394 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1395 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1396
1397 #define PIC_ADDR_P(OP) \
1398 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1399 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1400
1401 #define PCREL_SYMOFF_P(OP) \
1402 (GET_CODE (OP) == CONST \
1403 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1404 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1405
1406 #define NON_PIC_REFERENCE_P(OP) \
1407 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1408 || (GET_CODE (OP) == CONST \
1409 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1410 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF)) \
1411 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1412 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1413 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF) \
1414 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1415
1416 #define PIC_REFERENCE_P(OP) \
1417 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1418 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1419
1420 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1421 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1422 || (GET_CODE (X) == SUBREG \
1423 && REG_P (SUBREG_REG (X)) \
1424 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1425
1426 /* Since this must be r0, which is a single register class, we must check
1427 SUBREGs more carefully, to be sure that we don't accept one that extends
1428 outside the class. */
1429 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1430 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1431 || (GET_CODE (X) == SUBREG \
1432 && REG_P (SUBREG_REG (X)) \
1433 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1434
1435 #ifdef REG_OK_STRICT
1436 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1437 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1438 #else
1439 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1440 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1441 #endif
1442
1443 \f
1444 /* A C compound statement that attempts to replace X, which is an address
1445 that needs reloading, with a valid memory address for an operand of
1446 mode MODE. WIN is a C statement label elsewhere in the code. */
1447 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1448 do { \
1449 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1450 goto WIN; \
1451 } while (0)
1452 \f
1453 /* Specify the machine mode that this machine uses
1454 for the index in the tablejump instruction. */
1455 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
1456
1457 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1458 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1459 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1460 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1461 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1462 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1463 : SImode)
1464
1465 /* Define as C expression which evaluates to nonzero if the tablejump
1466 instruction expects the table to contain offsets from the address of the
1467 table.
1468 Do not define this if the table should contain absolute addresses. */
1469 #define CASE_VECTOR_PC_RELATIVE 1
1470
1471 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
1472 #define FLOAT_TYPE_SIZE 32
1473
1474 /* Since the SH2e has only `float' support, it is desirable to make all
1475 floating point types equivalent to `float'. */
1476 #define DOUBLE_TYPE_SIZE (TARGET_FPU_SINGLE_ONLY ? 32 : 64)
1477
1478 /* 'char' is signed by default. */
1479 #define DEFAULT_SIGNED_CHAR 1
1480
1481 /* The type of size_t unsigned int. */
1482 #define SIZE_TYPE ("unsigned int")
1483
1484 #undef PTRDIFF_TYPE
1485 #define PTRDIFF_TYPE ("int")
1486
1487 #define WCHAR_TYPE "short unsigned int"
1488 #define WCHAR_TYPE_SIZE 16
1489
1490 #define SH_ELF_WCHAR_TYPE "long int"
1491
1492 /* Max number of bytes we can move from memory to memory
1493 in one reasonably fast instruction. */
1494 #define MOVE_MAX (4)
1495
1496 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
1497 MOVE_MAX is not a compile-time constant. */
1498 #define MAX_MOVE_MAX 8
1499
1500 /* Max number of bytes we want move_by_pieces to be able to copy
1501 efficiently. */
1502 #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4)
1503
1504 /* Define if operations between registers always perform the operation
1505 on the full register even if a narrower mode is specified. */
1506 #define WORD_REGISTER_OPERATIONS 1
1507
1508 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1509 will either zero-extend or sign-extend. The value of this macro should
1510 be the code that says which one of the two operations is implicitly
1511 done, UNKNOWN if none. */
1512 #define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
1513
1514 /* Define if loading short immediate values into registers sign extends. */
1515 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1516
1517 /* Nonzero if access to memory by bytes is no faster than for words. */
1518 #define SLOW_BYTE_ACCESS 1
1519
1520 /* Nonzero if the target supports dynamic shift instructions
1521 like shad and shld. */
1522 #define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
1523
1524 /* The cost of using the dynamic shift insns (shad, shld) are the same
1525 if they are available. If they are not available a library function will
1526 be emitted instead, which is more expensive. */
1527 #define SH_DYNAMIC_SHIFT_COST (TARGET_DYNSHIFT ? 1 : 20)
1528
1529 /* Defining SHIFT_COUNT_TRUNCATED tells the combine pass that code like
1530 (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1531 This is not generally true when hardware dynamic shifts (shad, shld) are
1532 used, because they check the sign bit _before_ the modulo op. The sign
1533 bit determines whether it is a left shift or a right shift:
1534 if (Y < 0)
1535 return X << (Y & 31);
1536 else
1537 return X >> (-Y) & 31);
1538
1539 The dynamic shift library routines in lib1funcs.S do not use the sign bit
1540 like the hardware dynamic shifts and truncate the shift count to 31.
1541 We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count
1542 truncation in the library function call patterns, as this gives slightly
1543 more compact code. */
1544 #define SHIFT_COUNT_TRUNCATED (0)
1545
1546 /* Define this if addresses of constant functions
1547 shouldn't be put through pseudo regs where they can be cse'd.
1548 Desirable on machines where ordinary constants are expensive
1549 but a CALL with constant address is cheap. */
1550 /*#define NO_FUNCTION_CSE 1*/
1551
1552 /* The machine modes of pointers and functions. */
1553 #define Pmode (SImode)
1554 #define FUNCTION_MODE Pmode
1555
1556 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1557 are actually function calls with some special constraints on arguments
1558 and register usage.
1559
1560 These macros tell reorg that the references to arguments and
1561 register clobbers for insns of type sfunc do not appear to happen
1562 until after the millicode call. This allows reorg to put insns
1563 which set the argument registers into the delay slot of the millicode
1564 call -- thus they act more like traditional CALL_INSNs.
1565
1566 get_attr_is_sfunc will try to recognize the given insn, so make sure to
1567 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1568 in particular. */
1569
1570 #define INSN_SETS_ARE_DELAYED(X) \
1571 ((NONJUMP_INSN_P (X) \
1572 && GET_CODE (PATTERN (X)) != SEQUENCE \
1573 && GET_CODE (PATTERN (X)) != USE \
1574 && GET_CODE (PATTERN (X)) != CLOBBER \
1575 && get_attr_is_sfunc (X)))
1576
1577 #define INSN_REFERENCES_ARE_DELAYED(X) \
1578 ((NONJUMP_INSN_P (X) \
1579 && GET_CODE (PATTERN (X)) != SEQUENCE \
1580 && GET_CODE (PATTERN (X)) != USE \
1581 && GET_CODE (PATTERN (X)) != CLOBBER \
1582 && get_attr_is_sfunc (X)))
1583
1584 \f
1585 /* Position Independent Code. */
1586
1587 /* We can't directly access anything that contains a symbol,
1588 nor can we indirect via the constant pool. */
1589 #define LEGITIMATE_PIC_OPERAND_P(X) \
1590 ((! nonpic_symbol_mentioned_p (X) \
1591 && (GET_CODE (X) != SYMBOL_REF \
1592 || ! CONSTANT_POOL_ADDRESS_P (X) \
1593 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))))
1594
1595 #define SYMBOLIC_CONST_P(X) \
1596 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
1597 && nonpic_symbol_mentioned_p (X))
1598 \f
1599 /* Compute extra cost of moving data between one register class
1600 and another. */
1601
1602 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
1603 uses this information. Hence, the general register <-> floating point
1604 register information here is not used for SFmode. */
1605 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
1606 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \
1607 || ((CLASS) == SIBCALL_REGS))
1608
1609 #define REGCLASS_HAS_FP_REG(CLASS) \
1610 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
1611 || (CLASS) == DF_REGS)
1612
1613 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1614 would be so that people with slow memory systems could generate
1615 different code that does fewer memory accesses. */
1616
1617 /* A C expression for the cost of a branch instruction. A value of 1
1618 is the default; other values are interpreted relative to that. */
1619 #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost
1620 \f
1621 /* Assembler output control. */
1622
1623 /* A C string constant describing how to begin a comment in the target
1624 assembler language. The compiler assumes that the comment will end at
1625 the end of the line. */
1626 #define ASM_COMMENT_START "!"
1627
1628 #define ASM_APP_ON ""
1629 #define ASM_APP_OFF ""
1630 #define FILE_ASM_OP "\t.file\n"
1631 #define SET_ASM_OP "\t.set\t"
1632
1633 /* How to change between sections. */
1634 #define TEXT_SECTION_ASM_OP "\t.text"
1635 #define DATA_SECTION_ASM_OP "\t.data"
1636
1637 #if defined CRT_BEGIN || defined CRT_END
1638 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
1639 #undef TEXT_SECTION_ASM_OP
1640 #define TEXT_SECTION_ASM_OP "\t.text"
1641 #endif
1642
1643 #ifndef BSS_SECTION_ASM_OP
1644 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1645 #endif
1646
1647 #ifndef ASM_OUTPUT_ALIGNED_BSS
1648 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1649 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1650 #endif
1651
1652 /* Define this so that jump tables go in same section as the current function,
1653 which could be text or it could be a user defined section. */
1654 #define JUMP_TABLES_IN_TEXT_SECTION 1
1655
1656 #undef DO_GLOBAL_CTORS_BODY
1657 #define DO_GLOBAL_CTORS_BODY \
1658 { \
1659 typedef void (*pfunc) (void); \
1660 extern pfunc __ctors[]; \
1661 extern pfunc __ctors_end[]; \
1662 pfunc *p; \
1663 for (p = __ctors_end; p > __ctors; ) \
1664 { \
1665 (*--p)(); \
1666 } \
1667 }
1668
1669 #undef DO_GLOBAL_DTORS_BODY
1670 #define DO_GLOBAL_DTORS_BODY \
1671 { \
1672 typedef void (*pfunc) (void); \
1673 extern pfunc __dtors[]; \
1674 extern pfunc __dtors_end[]; \
1675 pfunc *p; \
1676 for (p = __dtors; p < __dtors_end; p++) \
1677 { \
1678 (*p)(); \
1679 } \
1680 }
1681
1682 #define ASM_OUTPUT_REG_PUSH(file, v) \
1683 { \
1684 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
1685 }
1686
1687 #define ASM_OUTPUT_REG_POP(file, v) \
1688 { \
1689 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
1690 }
1691
1692 /* DBX register number for a given compiler register number. */
1693 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
1694 to match gdb. */
1695 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
1696 register exists, so we should return -1 for invalid register numbers. */
1697 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
1698
1699 #define SH_DBX_REGISTER_NUMBER(REGNO) \
1700 (IN_RANGE ((REGNO), \
1701 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1702 FIRST_GENERAL_REG + 15U) \
1703 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
1704 : ((int) (REGNO) >= FIRST_FP_REG \
1705 && ((int) (REGNO) \
1706 <= (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)))) \
1707 ? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \
1708 : XD_REGISTER_P (REGNO) \
1709 ? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \
1710 : (REGNO) == PR_REG \
1711 ? (17) \
1712 : (REGNO) == GBR_REG \
1713 ? (18) \
1714 : (REGNO) == MACH_REG \
1715 ? (20) \
1716 : (REGNO) == MACL_REG \
1717 ? (21) \
1718 : (REGNO) == T_REG \
1719 ? (22) \
1720 : (REGNO) == FPUL_REG \
1721 ? (23) \
1722 : (REGNO) == FPSCR_REG \
1723 ? (24) \
1724 : (unsigned) -1)
1725
1726 /* This is how to output an assembler line
1727 that says to advance the location counter
1728 to a multiple of 2**LOG bytes. */
1729
1730 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1731 if ((LOG) != 0) \
1732 fprintf ((FILE), "\t.align %d\n", (LOG))
1733
1734 /* Globalizing directive for a label. */
1735 #define GLOBAL_ASM_OP "\t.global\t"
1736
1737 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1738
1739 /* Output a relative address table. */
1740 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1741 switch (GET_MODE (BODY)) \
1742 { \
1743 case E_SImode: \
1744 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1745 break; \
1746 case E_HImode: \
1747 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1748 break; \
1749 case E_QImode: \
1750 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
1751 break; \
1752 default: \
1753 break; \
1754 }
1755
1756 /* Output an absolute table element. */
1757 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1758 if (! optimize || TARGET_BIGTABLE) \
1759 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
1760 else \
1761 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
1762
1763 \f
1764 /* A C statement to be executed just prior to the output of
1765 assembler code for INSN, to modify the extracted operands so
1766 they will be output differently.
1767
1768 Here the argument OPVEC is the vector containing the operands
1769 extracted from INSN, and NOPERANDS is the number of elements of
1770 the vector which contain meaningful data for this insn.
1771 The contents of this vector are what will be used to convert the insn
1772 template into assembler code, so you can change the assembler output
1773 by changing the contents of the vector. */
1774 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1775 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
1776
1777 /* Which processor to schedule for. The elements of the enumeration must
1778 match exactly the cpu attribute in the sh.md file. */
1779 enum processor_type {
1780 PROCESSOR_SH1,
1781 PROCESSOR_SH2,
1782 PROCESSOR_SH2E,
1783 PROCESSOR_SH2A,
1784 PROCESSOR_SH3,
1785 PROCESSOR_SH3E,
1786 PROCESSOR_SH4,
1787 PROCESSOR_SH4A
1788 };
1789
1790 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
1791 extern enum processor_type sh_cpu;
1792
1793 enum mdep_reorg_phase_e
1794 {
1795 SH_BEFORE_MDEP_REORG,
1796 SH_INSERT_USES_LABELS,
1797 SH_SHORTEN_BRANCHES0,
1798 SH_FIXUP_PCLOAD,
1799 SH_SHORTEN_BRANCHES1,
1800 SH_AFTER_MDEP_REORG
1801 };
1802
1803 extern enum mdep_reorg_phase_e mdep_reorg_phase;
1804
1805 /* Handle Renesas compiler's pragmas. */
1806 #define REGISTER_TARGET_PRAGMAS() do { \
1807 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
1808 c_register_pragma (0, "trapa", sh_pr_trapa); \
1809 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
1810 } while (0)
1811
1812 extern tree sh_deferred_function_attributes;
1813 extern tree *sh_deferred_function_attributes_tail;
1814
1815
1816 \f
1817 /* Instructions with unfilled delay slots take up an
1818 extra two bytes for the nop in the delay slot.
1819 sh-dsp parallel processing insns are four bytes long. */
1820 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1821 (LENGTH) += sh_insn_length_adjustment (X);
1822 \f
1823 /* Define this macro if it is advisable to hold scalars in registers
1824 in a wider mode than that declared by the program. In such cases,
1825 the value is constrained to be within the bounds of the declared
1826 type, but kept valid in the wider mode. The signedness of the
1827 extension may differ from that of the type.
1828
1829 Leaving the unsignedp unchanged gives better code than always setting it
1830 to 0. This is despite the fact that we have only signed char and short
1831 load instructions. */
1832 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1833 if (GET_MODE_CLASS (MODE) == MODE_INT \
1834 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
1835 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), (MODE) = SImode;
1836
1837 #define MAX_FIXED_MODE_SIZE (64)
1838
1839 /* Better to allocate once the maximum space for outgoing args in the
1840 prologue rather than duplicate around each call. */
1841 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1842
1843 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
1844
1845 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_FPU_DOUBLE)
1846
1847 #define ACTUAL_NORMAL_MODE(ENTITY) \
1848 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
1849
1850 #define NORMAL_MODE(ENTITY) \
1851 (sh_cfun_interrupt_handler_p () \
1852 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
1853 : ACTUAL_NORMAL_MODE (ENTITY))
1854
1855 #define EPILOGUE_USES(REGNO) (TARGET_FPU_ANY && REGNO == FPSCR_REG)
1856
1857 #define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (PR_REG))
1858
1859 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 4U : INVALID_REGNUM)
1860
1861 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
1862 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
1863
1864 /* We have to distinguish between code and data, so that we apply
1865 datalabel where and only where appropriate. Use sdataN for data. */
1866 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1867 ((TARGET_FDPIC \
1868 ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \
1869 : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
1870 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \
1871 | ((CODE) ? 0 : DW_EH_PE_sdata4))
1872
1873 /* Handle special EH pointer encodings. Absolute, pc-relative, and
1874 indirect are handled automatically. */
1875 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
1876 do { \
1877 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
1878 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
1879 { \
1880 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
1881 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
1882 if (0) goto DONE; \
1883 } \
1884 if (TARGET_FDPIC \
1885 && ((ENCODING) & 0xf0) == (DW_EH_PE_indirect | DW_EH_PE_datarel)) \
1886 { \
1887 fputs ("\t.ualong ", FILE); \
1888 output_addr_const (FILE, ADDR); \
1889 if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \
1890 fputs ("@GOTFUNCDESC", FILE); \
1891 else \
1892 fputs ("@GOT", FILE); \
1893 goto DONE; \
1894 } \
1895 } while (0)
1896
1897 #if (defined CRT_BEGIN || defined CRT_END)
1898 /* SH constant pool breaks the devices in crtstuff.c to control section
1899 in where code resides. We have to write it as asm code. */
1900 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1901 asm (SECTION_OP "\n\
1902 mov.l 1f,r1\n\
1903 mova 2f,r0\n\
1904 braf r1\n\
1905 lds r0,pr\n\
1906 0: .p2align 2\n\
1907 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
1908 2:\n" TEXT_SECTION_ASM_OP);
1909 #endif /* (defined CRT_BEGIN || defined CRT_END) */
1910
1911 #endif /* ! GCC_SH_H */
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