gcc/config/cr16/cr16.h

   1 /* Definitions of target machine for GNU compiler, for CR16.
   2    Copyright (C) 2012-2017 Free Software Foundation, Inc.
   3    Contributed by KPIT Cummins Infosystems Limited.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef GCC_CR16_H
  22 #define GCC_CR16_H
  23
  24 #define OBJECT_FORMAT_ELF
  25
  26 /* Controlling the driver.  */
  27
  28 /* The GNU C++ standard library requires that these macros be defined.  */
  29 #undef CPLUSPLUS_CPP_SPEC
  30 #define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
  31
  32 #undef  STARTFILE_SPEC
  33 #define STARTFILE_SPEC "crt1.o%s crti.o%s crtbegin.o%s crtlibid.o%s"
  34
  35 #undef  ENDFILE_SPEC
  36 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
  37
  38 #undef  MATH_LIBRARY
  39 #define MATH_LIBRARY ""
  40
  41 #undef  LIB_SPEC
  42 #define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
  43 %{msim*:%{!T*:-Tsim.ld}} \
  44 %{!T*:%{!msim*: %{-Telf32cr16.x}}}"
  45
  46 /* Run-time target specification.  */
  47 #ifndef TARGET_CPU_CPP_BUILTINS
  48 #define TARGET_CPU_CPP_BUILTINS()          \
  49 do                                         \
  50   {                                        \
  51     builtin_define ("__CR__");             \
  52     builtin_define ("__CR16__");           \
  53     builtin_define ("__CR16C__");          \
  54     if (TARGET_CR16CP)                     \
  55       builtin_define ("__CR16CP__");       \
  56     else                                   \
  57       builtin_define ("__CR16CSTD__");     \
  58     if (CR16_TARGET_DATA_NEAR)             \
  59       builtin_define ("__DATA_NEAR__");    \
  60     if (CR16_TARGET_DATA_MEDIUM)           \
  61       builtin_define ("__DATA_MEDIUM__");  \
  62     if (CR16_TARGET_DATA_FAR)              \
  63       builtin_define ("__DATA_FAR__");     \
  64     if (TARGET_INT32)                      \
  65       builtin_define ("__INT32__");        \
  66   }                                        \
  67 while (0)
  68 #endif
  69
  70 /* Force the generation of dwarf .debug_frame sections even if not
  71    compiling -g.  This guarantees that we can unwind the stack.  */
  72 #define DWARF2_FRAME_INFO 1
  73
  74 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
  75
  76 /* Generate .file/.loc directives, so that the assembler generates the
  77    line table.  */
  78 #define DWARF2_ASM_LINE_DEBUG_INFO 1
  79
  80 #define CR16_TARGET_DATA_NEAR   cr16_is_data_model (DM_NEAR)
  81 #define CR16_TARGET_DATA_MEDIUM cr16_is_data_model (DM_DEFAULT)
  82 #define CR16_TARGET_DATA_FAR    cr16_is_data_model (DM_FAR)
  83
  84 /* Storage layout.  */
  85 #define BITS_BIG_ENDIAN     0
  86
  87 #define BYTES_BIG_ENDIAN    0
  88
  89 #define WORDS_BIG_ENDIAN    0
  90
  91 #define UNITS_PER_WORD      2
  92
  93 /* Units per 32-bit (DWORD).  */
  94 #define CR16_UNITS_PER_DWORD 4
  95
  96 #define POINTER_SIZE        32
  97
  98 #define PARM_BOUNDARY       16
  99
 100 #define STACK_BOUNDARY      (MAX (BIGGEST_ALIGNMENT, PARM_BOUNDARY))
 101
 102 #define FUNCTION_BOUNDARY   BIGGEST_ALIGNMENT
 103
 104 /* Biggest alignment on CR16C+ is 32-bit as internal bus is AMBA based
 105    where as CR16C is proprietary internal bus architecture.  */
 106 #define BIGGEST_ALIGNMENT   ((TARGET_CR16CP) ? 32 : 16)
 107
 108 #define MAX_FIXED_MODE_SIZE 64
 109
 110 /* In CR16 arrays of chars are word-aligned, so strcpy () will be faster.  */
 111 #define DATA_ALIGNMENT(TYPE, ALIGN)              \
 112   (((TREE_CODE (TYPE) == ARRAY_TYPE)             \
 113      && (TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
 114      && ((ALIGN) < BITS_PER_WORD))               \
 115      ? (BITS_PER_WORD) : (ALIGN))
 116
 117 #define STRICT_ALIGNMENT 0
 118
 119 #define PCC_BITFIELD_TYPE_MATTERS 1
 120
 121 /* Layout of source language data types.  */
 122 #define INT_TYPE_SIZE       (TARGET_INT32 ? 32 : 16)
 123
 124 #define SHORT_TYPE_SIZE     16
 125
 126 #define LONG_TYPE_SIZE      32
 127
 128 #define LONG_LONG_TYPE_SIZE 64
 129
 130 #define FLOAT_TYPE_SIZE     32
 131
 132 #define DOUBLE_TYPE_SIZE    64
 133
 134 #define LONG_DOUBLE_TYPE_SIZE 64
 135
 136 #define DEFAULT_SIGNED_CHAR 1
 137
 138 #define SIZE_TYPE           "long unsigned int"
 139
 140 #define PTRDIFF_TYPE        "long int"
 141
 142 #define WCHAR_TYPE          "short unsigned int"
 143
 144 #define WCHAR_TYPE_SIZE     16
 145
 146 /* By default, the C++ compiler will use the lowest bit of the pointer
 147    to function to indicate a pointer-to-member-function points to a
 148    virtual member function.  However, in CR architecture FUNCTION_BOUNDARY
 149    indicates function addresses are always even, but function pointers can be
 150    odd (after right-shifting them when loading them into a register), and the
 151    default doesn't work.  In that case, the lowest bit of the delta
 152    field will be used (the remainder of the field is shifted to the left).  */
 153 #define TARGET_PTRMEMFUNC_VBIT_LOCATION     ptrmemfunc_vbit_in_delta
 154
 155 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
 156    values must be in memory.  */
 157 #define DEFAULT_PCC_STRUCT_RETURN 0
 158
 159 /* Register usage.  */
 160
 161 /* First 32-bit register is R12.  */
 162 #define CR16_FIRST_DWORD_REGISTER   12
 163
 164 #define FIRST_PSEUDO_REGISTER       16
 165
 166 /* 1 for registers that have pervasive standard uses
 167    and are not available for the register allocator.
 168    On the CR16, only the stack pointer (r15) is such.  */
 169 #define FIXED_REGISTERS                               \
 170   {                                                   \
 171   /* r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10.  */ \
 172     0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,        \
 173   /* r11 r12 r13 ra  sp.  */                          \
 174     0,  0,  0,  0,  1                                 \
 175   }
 176
 177 /* 1 for registers not available across function calls.
 178    These must include the FIXED_REGISTERS and also any
 179    registers that can be used without being saved.
 180    The latter must include the registers where values are returned
 181    and the register where structure-value addresses are passed.
 182
 183    On the CR16, calls clobbers r0-r6 (scratch registers),
 184    ra (the return address) and sp (the stack pointer).  */
 185 #define CALL_USED_REGISTERS                           \
 186   {                                                   \
 187   /* r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10.  */ \
 188     1,  1,  1,  1,  1,  1,  1,  0,  0,  0,  0,        \
 189   /* r11 r12 r13 ra  sp.  */                          \
 190     0,  0,  0,  1,  1                                 \
 191   }
 192
 193 /* Returns 1 if the register is longer than word size, 0 otherwise.  */
 194 #define LONG_REG_P(REGNO)                                                    \
 195   (targetm.hard_regno_nregs (REGNO,                                          \
 196                              GET_MODE_WIDER_MODE (word_mode).require ()) == 1)
 197
 198 #define NOTICE_UPDATE_CC(EXP, INSN) \
 199    notice_update_cc ((EXP))
 200
 201 /* Interrupt functions can only use registers that have already been
 202    saved by the prologue, even if they would normally be call-clobbered
 203    Check if sizes are same and then check if it is possible to rename.  */
 204 #define HARD_REGNO_RENAME_OK(SRC, DEST)                 \
 205   (!cr16_interrupt_function_p () || (df_regs_ever_live_p (DEST)))
 206
 207 /* Exception handling stuff.  */
 208
 209 /*To ensure correct dwarf unwinding.  */
 210 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((optimize ("no-gcse","no-dse")))
 211
 212 #define gen_rtx_RA      gen_rtx_REG (Pmode, RETURN_ADDRESS_REGNUM)
 213
 214 /* Use (r8,r7) and (r10,r9) to pass exception handling information.  */
 215 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N*2 + 7) : INVALID_REGNUM)
 216
 217 #define DWARF2_UNWIND_INFO 1
 218
 219 /* (r5,r4) holds a stack adjustment for returning to a handler.  */
 220 #define EH_RETURN_STACKADJ_RTX          gen_rtx_REG (Pmode, 4)
 221
 222 #define EH_RETURN_HANDLER_RTX \
 223   gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, -4))
 224
 225 #define INCOMING_RETURN_ADDR_RTX        gen_rtx_RA
 226
 227 #define DWARF_FRAME_RETURN_COLUMN       \
 228   DWARF_FRAME_REGNUM (RETURN_ADDRESS_REGNUM)
 229
 230 #define INCOMING_FRAME_SP_OFFSET                0
 231 #define FRAME_POINTER_CFA_OFFSET(FNDECL)        0
 232
 233 /* A C expression whose value is RTL representing the value of the return
 234    address for the frame COUNT steps up from the current frame.  */
 235 #define RETURN_ADDR_RTX(COUNT, FRAME)                                   \
 236   (0 == COUNT)  ?  gen_rtx_PLUS (Pmode, gen_rtx_RA, gen_rtx_RA)         \
 237                 :  const0_rtx
 238
 239 enum reg_class
 240 {
 241   NO_REGS,
 242   SHORT_REGS,
 243   LONG_REGS,
 244   NOSP_REGS,
 245   DOUBLE_BASE_REGS,
 246   GENERAL_REGS,
 247   ALL_REGS,
 248   LIM_REG_CLASSES
 249 };
 250
 251 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 252
 253 #define REG_CLASS_NAMES \
 254   {                     \
 255     "NO_REGS",          \
 256     "SHORT_REGS",       \
 257     "LONG_REGS",        \
 258     "NOSP_REGS",        \
 259     "DOUBLE_BASE_REGS", \
 260     "GENERAL_REGS",     \
 261     "ALL_REGS"          \
 262   }
 263
 264 #define REG_CLASS_CONTENTS                                      \
 265   {                                                             \
 266     {0x00000000}, /* NO_REGS                         */         \
 267     {0x00000FFF}, /* SHORT_REGS         : 0 - 11     */         \
 268     {0x0000F000}, /* LONG_REGS          : 12 - 15    */         \
 269     {0x00007FFF}, /* NOSP_REGS          : 0 - 14     */         \
 270     {0x0000F555}, /* DOUBLE_BASE_REGS   : 2,4,6,8,10 */         \
 271     {0x0000FFFF}, /* GENERAL_REGS       : 0 - 15     */         \
 272     {0x0000FFFF}  /* ALL_REGS           : 0 - 15     */         \
 273   }
 274
 275 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P  hook_bool_mode_true
 276
 277 #define REGNO_REG_CLASS(REGNO)  cr16_regno_reg_class (REGNO)
 278
 279 #define BASE_REG_CLASS      GENERAL_REGS
 280
 281 #define MODE_BASE_REG_CLASS(MODE) \
 282   (GET_MODE_SIZE (MODE) <= 4 ?  (BASE_REG_CLASS) :  (DOUBLE_BASE_REGS))
 283
 284 #define INDEX_REG_CLASS      LONG_REGS
 285
 286 #define CR16_REGNO_OK_FOR_BASE_P(REGNO)                  \
 287   (((REGNO) < FIRST_PSEUDO_REGISTER)                     \
 288      || (reg_renumber && ((unsigned) reg_renumber[REGNO] \
 289                         < FIRST_PSEUDO_REGISTER)))
 290
 291 /* Use even-numbered reg for 64-bit accesses.  */
 292 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE)     \
 293         (CR16_REGNO_OK_FOR_BASE_P(REGNO)  &&      \
 294           ((GET_MODE_SIZE (MODE) > 4  &&          \
 295              (REGNO) < CR16_FIRST_DWORD_REGISTER) \
 296              ? (0 == ((REGNO) & 1))               \
 297              : 1))
 298
 299 /* TODO: For now lets not support index addressing mode.  */
 300 #define REGNO_OK_FOR_INDEX_P(REGNO)        \
 301   (((REGNO >= CR16_FIRST_DWORD_REGISTER)   \
 302      && ((REGNO) < FIRST_PSEUDO_REGISTER)) \
 303    || (reg_renumber                        \
 304        && (((unsigned) reg_renumber[REGNO] >= CR16_FIRST_DWORD_REGISTER)  \
 305             && ((unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER))) \
 306   )
 307
 308 #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
 309
 310 /* The maximum number of consecutive registers of class CLASS needed to
 311    hold a value of mode MODE.
 312    On the CompactRISC architecture, the size of MODE in words.
 313    The size of MODE in double words for the class LONG_REGS.
 314
 315    The following check assumes if the class is not LONG_REGS, then
 316    all (NO_REGS, SHORT_REGS, NOSP_REGS and GENERAL_REGS) other classes are
 317    short.  We may have to check if this can cause any degradation in
 318    performance.  */
 319 #define CLASS_MAX_NREGS(CLASS, MODE) \
 320   (CLASS == LONG_REGS \
 321    ? (GET_MODE_SIZE (MODE) + CR16_UNITS_PER_DWORD - 1) / CR16_UNITS_PER_DWORD\
 322    : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 323
 324 /* Macros to check the range of integers . These macros were used across
 325    the port, majorly in constraints.md, predicates.md files. */
 326 #define SIGNED_INT_FITS_N_BITS(imm, N)           \
 327   ((((imm) < ((HOST_WIDE_INT) 1 << ((N) - 1)))       \
 328       && ((imm) >= -((HOST_WIDE_INT) 1 << ((N) - 1)))) ? 1 : 0)
 329
 330 #define UNSIGNED_INT_FITS_N_BITS(imm, N) \
 331   (((imm) < ((HOST_WIDE_INT) 1 << (N)) && (imm) >= (HOST_WIDE_INT) 0) ? 1 : 0)
 332
 333 #define IN_RANGE_P(VALUE, LOW, HIGH)                            \
 334   ((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW))           \
 335    && (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH))))
 336
 337 #define IN_RAN(VALUE, LOW, HIGH)                             \
 338   (((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW))       \
 339    && (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH)))) ? 1 : 0)
 340
 341 /* This check is for sbit/cbit instruction.  */
 342 #define OK_FOR_Z(OP) \
 343   ((GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST_INT) \
 344    || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) \
 345    || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \
 346        && GET_CODE (XEXP ((XEXP (OP, 0)), 0)) == REG \
 347        && GET_CODE (XEXP ((XEXP (OP, 0)), 1)) == CONST_INT))
 348
 349 /* Stack layout and calling conventions.  */
 350 #define STACK_GROWS_DOWNWARD 1
 351
 352 #define STACK_POINTER_REGNUM    15
 353
 354 #define FRAME_POINTER_REGNUM    13
 355
 356 #define ARG_POINTER_REGNUM      12
 357
 358 #define STATIC_CHAIN_REGNUM     1
 359
 360 #define RETURN_ADDRESS_REGNUM   14
 361
 362 #define FIRST_PARM_OFFSET(FNDECL) 0
 363
 364 #define ELIMINABLE_REGS                            \
 365   {                                                \
 366     { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM}, \
 367     { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM}, \
 368     { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}  \
 369   }
 370
 371 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)              \
 372   do                                                              \
 373     {                                                             \
 374       (OFFSET) = cr16_initial_elimination_offset ((FROM), (TO));  \
 375     }                                                             \
 376   while (0)
 377
 378 /* Passing function arguments.  */
 379
 380 #define ACCUMULATE_OUTGOING_ARGS 0
 381
 382 #define PUSH_ARGS 1
 383
 384 #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
 385
 386 #ifndef CUMULATIVE_ARGS
 387 struct cumulative_args
 388 {
 389   int ints;
 390   int last_parm_in_reg;
 391 };
 392
 393 #define CUMULATIVE_ARGS struct cumulative_args
 394 #endif
 395
 396 /* On the CR16 architecture, Varargs routines should receive their parameters
 397    on the stack.  */
 398
 399 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
 400   cr16_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
 401
 402 #define FUNCTION_ARG_REGNO_P(REGNO)  cr16_function_arg_regno_p (REGNO)
 403
 404 /* Generating code for profiling - NOT IMPLEMENTED.  */
 405 #undef  FUNCTION_PROFILER
 406 #define FUNCTION_PROFILER(STREAM, LABELNO)      \
 407 {                                               \
 408   sorry ("profiler support for CR16");          \
 409 }
 410
 411 /* Trampolines for nested functions - NOT SUPPORTED.  */
 412 #define TRAMPOLINE_SIZE    16
 413
 414 /* ADDRESSING MODES.  */
 415
 416 #define CONSTANT_ADDRESS_P(X)       \
 417   (GET_CODE (X) == LABEL_REF        \
 418    || GET_CODE (X) == SYMBOL_REF    \
 419    || GET_CODE (X) == CONST         \
 420    || GET_CODE (X) == CONST_INT)
 421
 422 #define MAX_REGS_PER_ADDRESS    2
 423
 424 #define HAVE_POST_INCREMENT     0
 425 #define HAVE_POST_DECREMENT     0
 426 #define HAVE_POST_MODIFY_DISP   0
 427 #define HAVE_POST_MODIFY_REG    0
 428
 429 #ifdef REG_OK_STRICT
 430 #define CR16_REG_OK_FOR_BASE_P(X)       CR16_REGNO_OK_FOR_BASE_P (REGNO (X))
 431 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 432   REGNO_MODE_OK_FOR_BASE_P (REGNO(X), MODE)
 433 #define REG_OK_FOR_INDEX_P(X)   REGNO_OK_FOR_INDEX_P (REGNO (X))
 434 #else /* not REG_OK_STRICT.  */
 435 #define CR16_REG_OK_FOR_BASE_P(X)       1
 436 #define REG_MODE_OK_FOR_BASE_P(X, MODE) 1
 437 #define REG_OK_FOR_INDEX_P(X)   1
 438 #endif /* not REG_OK_STRICT.  */
 439
 440 /* Assume best case (branch predicted).  */
 441 #define BRANCH_COST(speed_p, predictable_p)       2
 442
 443 #define SLOW_BYTE_ACCESS  1
 444
 445 /* It is as good or better to call a constant function address than to
 446    call an address kept in a register.  */
 447 #define NO_FUNCTION_CSE 1
 448
 449 /* Dividing the output into sections.  */
 450
 451 #define TEXT_SECTION_ASM_OP "\t.section\t.text"
 452
 453 #define DATA_SECTION_ASM_OP "\t.section\t.data"
 454
 455 #define BSS_SECTION_ASM_OP  "\t.section\t.bss"
 456
 457 /* Position independent code (PIC).  */
 458 /* NEAR_PIC for -fpic option.  */
 459
 460 #define NEAR_PIC 1
 461
 462 /* FAR_PIC for -fPIC option.  */
 463
 464 #define FAR_PIC  2
 465
 466 #define PIC_OFFSET_TABLE_REGNUM  12
 467
 468 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
 469
 470 /* Assembler format.  */
 471
 472 /* Character to start a comment.  */
 473 #define ASM_COMMENT_START "#"
 474
 475 #define GLOBAL_ASM_OP "\t.globl\t"
 476
 477 #undef USER_LABEL_PREFIX
 478 #define USER_LABEL_PREFIX "_"
 479
 480 #undef ASM_OUTPUT_LABELREF
 481 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
 482   asm_fprintf (STREAM, "%U%s", (*targetm.strip_name_encoding) (NAME));
 483
 484 #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL)   \
 485   do                                            \
 486     {                                           \
 487       const char *rn = XSTR (SYMBOL, 0);        \
 488       assemble_name (STREAM, rn);               \
 489       if (SYMBOL_REF_FUNCTION_P (SYMBOL))       \
 490       {                                         \
 491         fprintf ((STREAM), "@c");               \
 492       }                                         \
 493     }                                           \
 494   while (0)
 495
 496 #undef ASM_APP_ON
 497 #define ASM_APP_ON   "#APP\n"
 498
 499 #undef ASM_APP_OFF
 500 #define ASM_APP_OFF  "#NO_APP\n"
 501
 502 /* Switch into a generic section.  */
 503 #define TARGET_ASM_NAMED_SECTION        default_elf_asm_named_section
 504
 505 #undef INIT_SECTION_ASM_OP
 506 #define INIT_SECTION_ASM_OP             "\t.section\t.init"
 507
 508 #undef FINI_SECTION_ASM_OP
 509 #define FINI_SECTION_ASM_OP             "\t.section\t.fini"
 510
 511 /* Instruction output.  */
 512
 513 #define REGISTER_NAMES                                     \
 514   {                                                        \
 515     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7", \
 516     "r8",  "r9",  "r10", "r11", "r12", "r13", "ra",  "sp"  \
 517   }
 518
 519 /* Output of dispatch tables.  */
 520
 521 /* Revisit. No PC relative case as label expressions are not
 522    properly supported in binutils else we could have done this:
 523    #define CASE_VECTOR_PC_RELATIVE (optimize_size ? 1 : 0).  */
 524 #define CASE_VECTOR_PC_RELATIVE 0
 525
 526 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)    \
 527   ((GET_MODE (BODY) == QImode)                              \
 528    ? fprintf ((FILE), "\t.byte (.L%d-.L%d) >> 1\n",         \
 529               VALUE, REL)                                   \
 530    : fprintf ((FILE), "\t.word (.L%d-.L%d) >> 1\n",         \
 531               VALUE, REL))
 532
 533 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
 534   asm_fprintf ((STREAM), "\t.long\t.L%d@c\n", (VALUE))
 535
 536 /* Alignment in assembler file.  */
 537
 538 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
 539   asm_fprintf ((STREAM), "\t.align\t%d\n", 1 << (POWER))
 540
 541 /* Miscellaneous parameters.  */
 542
 543 #define CASE_VECTOR_MODE  Pmode
 544
 545 #define MOVE_MAX 4
 546
 547 #define STORE_FLAG_VALUE  1
 548
 549 #define Pmode SImode
 550
 551 #define FUNCTION_MODE QImode
 552
 553 /* Define this boolean macro(s) to indicate whether or not your architecture
 554    has (un)conditional branches that can span all of memory.  It is used in
 555    conjunction with an optimization that partitions hot and cold basic blocks
 556    into separate sections of the executable.
 557    CR16 contains branch instructions that span whole address space.  */
 558 #define HAS_LONG_COND_BRANCH    1
 559 #define HAS_LONG_UNCOND_BRANCH  1
 560
 561 #endif /* End of GCC_CR16_H.  */