1 ;; GCC machine description for CRX.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2007
4 ;; Free Software Foundation, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>. */
25 [(SP_REGNUM 15) ; Stack pointer
26 (RA_REGNUM 14) ; Return address
27 (LO_REGNUM 16) ; LO register
28 (HI_REGNUM 17) ; HI register
29 (CC_REGNUM 18) ; Condition code register
33 (define_attr "length" "" ( const_int 6 ))
35 (define_asm_attributes
36 [(set_attr "length" "6")]
41 (define_predicate "u4bits_operand"
42 (match_code "const_int,const_double")
44 if (GET_CODE (op) == CONST_DOUBLE)
45 return crx_const_double_ok (op);
46 return (UNSIGNED_INT_FITS_N_BITS(INTVAL(op), 4)) ? 1 : 0;
50 (define_predicate "cst4_operand"
51 (and (match_code "const_int")
52 (match_test "INT_CST4(INTVAL(op))")))
54 (define_predicate "reg_or_u4bits_operand"
55 (ior (match_operand 0 "u4bits_operand")
56 (match_operand 0 "register_operand")))
58 (define_predicate "reg_or_cst4_operand"
59 (ior (match_operand 0 "cst4_operand")
60 (match_operand 0 "register_operand")))
62 (define_predicate "reg_or_sym_operand"
63 (ior (match_code "symbol_ref")
64 (match_operand 0 "register_operand")))
66 (define_predicate "cc_reg_operand"
67 (and (match_code "reg")
68 (match_test "REGNO (op) == CC_REGNUM")))
70 (define_predicate "nosp_reg_operand"
71 (and (match_operand 0 "register_operand")
72 (match_test "REGNO (op) != SP_REGNUM")))
74 (define_predicate "store_operand"
75 (and (match_operand 0 "memory_operand")
76 (not (match_operand 0 "push_operand"))))
78 ;; Mode Macro Definitions
80 (define_mode_iterator ALLMT [QI HI SI SF DI DF])
81 (define_mode_iterator CRXMM [QI HI SI SF])
82 (define_mode_iterator CRXIM [QI HI SI])
83 (define_mode_iterator DIDFM [DI DF])
84 (define_mode_iterator SISFM [SI SF])
85 (define_mode_iterator SHORT [QI HI])
87 (define_mode_attr tIsa [(QI "b") (HI "w") (SI "d") (SF "d")])
88 (define_mode_attr lImmArith [(QI "4") (HI "4") (SI "6")])
89 (define_mode_attr lImmRotl [(QI "2") (HI "2") (SI "4")])
90 (define_mode_attr IJK [(QI "I") (HI "J") (SI "K")])
91 (define_mode_attr iF [(QI "i") (HI "i") (SI "i") (DI "i") (SF "F") (DF "F")])
92 (define_mode_attr JG [(QI "J") (HI "J") (SI "J") (DI "J") (SF "G") (DF "G")])
93 ; In HI or QI mode we push 4 bytes.
94 (define_mode_attr pushCnstr [(QI "X") (HI "X") (SI "<") (SF "<") (DI "<") (DF "<")])
95 (define_mode_attr tpush [(QI "") (HI "") (SI "") (SF "") (DI "sp, ") (DF "sp, ")])
96 (define_mode_attr lpush [(QI "2") (HI "2") (SI "2") (SF "2") (DI "4") (DF "4")])
99 ;; Code Macro Definitions
101 (define_code_iterator sz_xtnd [sign_extend zero_extend])
102 (define_code_attr sIsa [(sign_extend "") (zero_extend "u")])
103 (define_code_attr sPat [(sign_extend "s") (zero_extend "u")])
104 (define_code_attr szPat [(sign_extend "") (zero_extend "zero_")])
105 (define_code_attr szIsa [(sign_extend "s") (zero_extend "z")])
107 (define_code_iterator sh_oprnd [ashift ashiftrt lshiftrt])
108 (define_code_attr shIsa [(ashift "ll") (ashiftrt "ra") (lshiftrt "rl")])
109 (define_code_attr shPat [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr")])
111 (define_code_iterator mima_oprnd [smax umax smin umin])
112 (define_code_attr mimaIsa [(smax "maxs") (umax "maxu") (smin "mins") (umin "minu")])
114 ;; Addition Instructions
116 (define_insn "adddi3"
117 [(set (match_operand:DI 0 "register_operand" "=r,r")
118 (plus:DI (match_operand:DI 1 "register_operand" "%0,0")
119 (match_operand:DI 2 "nonmemory_operand" "r,i")))
120 (clobber (reg:CC CC_REGNUM))]
122 "addd\t%L2, %L1\;addcd\t%H2, %H1"
123 [(set_attr "length" "4,12")]
126 (define_insn "add<mode>3"
127 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
128 (plus:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
129 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
130 (clobber (reg:CC CC_REGNUM))]
133 [(set_attr "length" "2,<lImmArith>")]
136 ;; Subtract Instructions
138 (define_insn "subdi3"
139 [(set (match_operand:DI 0 "register_operand" "=r,r")
140 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
141 (match_operand:DI 2 "nonmemory_operand" "r,i")))
142 (clobber (reg:CC CC_REGNUM))]
144 "subd\t%L2, %L1\;subcd\t%H2, %H1"
145 [(set_attr "length" "4,12")]
148 (define_insn "sub<mode>3"
149 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
150 (minus:CRXIM (match_operand:CRXIM 1 "register_operand" "0,0")
151 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
152 (clobber (reg:CC CC_REGNUM))]
155 [(set_attr "length" "2,<lImmArith>")]
158 ;; Multiply Instructions
160 (define_insn "mul<mode>3"
161 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
162 (mult:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
163 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
164 (clobber (reg:CC CC_REGNUM))]
167 [(set_attr "length" "2,<lImmArith>")]
170 ;; Widening-multiplication Instructions
172 (define_insn "<sIsa>mulsidi3"
173 [(set (match_operand:DI 0 "register_operand" "=k")
174 (mult:DI (sz_xtnd:DI (match_operand:SI 1 "register_operand" "%r"))
175 (sz_xtnd:DI (match_operand:SI 2 "register_operand" "r"))))
176 (clobber (reg:CC CC_REGNUM))]
178 "mull<sPat>d\t%2, %1"
179 [(set_attr "length" "4")]
182 (define_insn "<sIsa>mulhisi3"
183 [(set (match_operand:SI 0 "register_operand" "=r")
184 (mult:SI (sz_xtnd:SI (match_operand:HI 1 "register_operand" "%0"))
185 (sz_xtnd:SI (match_operand:HI 2 "register_operand" "r"))))
186 (clobber (reg:CC CC_REGNUM))]
188 "mul<sPat>wd\t%2, %0"
189 [(set_attr "length" "4")]
192 (define_insn "<sIsa>mulqihi3"
193 [(set (match_operand:HI 0 "register_operand" "=r")
194 (mult:HI (sz_xtnd:HI (match_operand:QI 1 "register_operand" "%0"))
195 (sz_xtnd:HI (match_operand:QI 2 "register_operand" "r"))))
196 (clobber (reg:CC CC_REGNUM))]
198 "mul<sPat>bw\t%2, %0"
199 [(set_attr "length" "4")]
202 ;; Logical Instructions - and
204 (define_insn "and<mode>3"
205 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
206 (and:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
207 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
208 (clobber (reg:CC CC_REGNUM))]
211 [(set_attr "length" "2,<lImmArith>")]
214 ;; Logical Instructions - or
216 (define_insn "ior<mode>3"
217 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
218 (ior:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
219 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
220 (clobber (reg:CC CC_REGNUM))]
223 [(set_attr "length" "2,<lImmArith>")]
226 ;; Logical Instructions - xor
228 (define_insn "xor<mode>3"
229 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
230 (xor:CRXIM (match_operand:CRXIM 1 "register_operand" "%0,0")
231 (match_operand:CRXIM 2 "nonmemory_operand" "r,i")))
232 (clobber (reg:CC CC_REGNUM))]
235 [(set_attr "length" "2,<lImmArith>")]
238 ;; Sign and Zero Extend Instructions
240 (define_insn "<szPat>extendhisi2"
241 [(set (match_operand:SI 0 "register_operand" "=r")
242 (sz_xtnd:SI (match_operand:HI 1 "register_operand" "r")))
243 (clobber (reg:CC CC_REGNUM))]
245 "<szIsa>extwd\t%1, %0"
246 [(set_attr "length" "4")]
249 (define_insn "<szPat>extendqisi2"
250 [(set (match_operand:SI 0 "register_operand" "=r")
251 (sz_xtnd:SI (match_operand:QI 1 "register_operand" "r")))
252 (clobber (reg:CC CC_REGNUM))]
254 "<szIsa>extbd\t%1, %0"
255 [(set_attr "length" "4")]
258 (define_insn "<szPat>extendqihi2"
259 [(set (match_operand:HI 0 "register_operand" "=r")
260 (sz_xtnd:HI (match_operand:QI 1 "register_operand" "r")))
261 (clobber (reg:CC CC_REGNUM))]
263 "<szIsa>extbw\t%1, %0"
264 [(set_attr "length" "4")]
267 ;; Negation Instructions
269 (define_insn "neg<mode>2"
270 [(set (match_operand:CRXIM 0 "register_operand" "=r")
271 (neg:CRXIM (match_operand:CRXIM 1 "register_operand" "r")))
272 (clobber (reg:CC CC_REGNUM))]
275 [(set_attr "length" "4")]
278 ;; Absolute Instructions
280 (define_insn "abs<mode>2"
281 [(set (match_operand:CRXIM 0 "register_operand" "=r")
282 (abs:CRXIM (match_operand:CRXIM 1 "register_operand" "r")))
283 (clobber (reg:CC CC_REGNUM))]
286 [(set_attr "length" "4")]
289 ;; Max and Min Instructions
291 (define_insn "<code><mode>3"
292 [(set (match_operand:CRXIM 0 "register_operand" "=r")
293 (mima_oprnd:CRXIM (match_operand:CRXIM 1 "register_operand" "%0")
294 (match_operand:CRXIM 2 "register_operand" "r")))]
296 "<mimaIsa><tIsa>\t%2, %0"
297 [(set_attr "length" "4")]
302 (define_insn "one_cmpl<mode>2"
303 [(set (match_operand:CRXIM 0 "register_operand" "=r")
304 (not:CRXIM (match_operand:CRXIM 1 "register_operand" "0")))
305 (clobber (reg:CC CC_REGNUM))]
308 [(set_attr "length" "2")]
311 ;; Rotate Instructions
313 (define_insn "rotl<mode>3"
314 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
315 (rotate:CRXIM (match_operand:CRXIM 1 "register_operand" "0,0")
316 (match_operand:CRXIM 2 "nonmemory_operand" "r,<IJK>")))
317 (clobber (reg:CC CC_REGNUM))]
322 [(set_attr "length" "4,<lImmRotl>")]
325 (define_insn "rotr<mode>3"
326 [(set (match_operand:CRXIM 0 "register_operand" "=r")
327 (rotatert:CRXIM (match_operand:CRXIM 1 "register_operand" "0")
328 (match_operand:CRXIM 2 "register_operand" "r")))
329 (clobber (reg:CC CC_REGNUM))]
332 [(set_attr "length" "4")]
335 ;; Arithmetic Left and Right Shift Instructions
337 (define_insn "<shPat><mode>3"
338 [(set (match_operand:CRXIM 0 "register_operand" "=r,r")
339 (sh_oprnd:CRXIM (match_operand:CRXIM 1 "register_operand" "0,0")
340 (match_operand:QI 2 "nonmemory_operand" "r,<IJK>")))
341 (clobber (reg:CC CC_REGNUM))]
343 "s<shIsa><tIsa>\t%2, %0"
344 [(set_attr "length" "2,2")]
347 ;; Bit Set Instructions
350 [(set (match_operand:SI 0 "register_operand" "=r")
351 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
352 (match_operand:SI 2 "const_int_operand" "n")
353 (match_operand:SI 3 "const_int_operand" "n")))]
356 static char buf[100];
358 int size = INTVAL (operands[2]);
359 int pos = INTVAL (operands[3]);
360 strpntr = sprintf (buf, "ram\t$%d, $31, $%d, %%1, %%0\;",
361 BITS_PER_WORD - (size + pos), BITS_PER_WORD - size);
362 sprintf (buf + strpntr, "srad\t$%d, %%0", BITS_PER_WORD - size);
365 [(set_attr "length" "6")]
369 [(set (match_operand:SI 0 "register_operand" "=r")
370 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
371 (match_operand:SI 2 "const_int_operand" "n")
372 (match_operand:SI 3 "const_int_operand" "n")))]
376 int size = INTVAL (operands[2]);
377 int pos = INTVAL (operands[3]);
378 sprintf (buf, "ram\t$%d, $%d, $0, %%1, %%0",
379 (BITS_PER_WORD - pos) % BITS_PER_WORD, size - 1);
382 [(set_attr "length" "4")]
386 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
387 (match_operand:SI 1 "const_int_operand" "n")
388 (match_operand:SI 2 "const_int_operand" "n"))
389 (match_operand:SI 3 "register_operand" "r"))]
393 int size = INTVAL (operands[1]);
394 int pos = INTVAL (operands[2]);
395 sprintf (buf, "rim\t$%d, $%d, $%d, %%3, %%0",
396 pos, size + pos - 1, pos);
399 [(set_attr "length" "4")]
404 (define_expand "mov<mode>"
405 [(set (match_operand:ALLMT 0 "nonimmediate_operand" "")
406 (match_operand:ALLMT 1 "general_operand" ""))]
409 if (!(reload_in_progress || reload_completed))
411 if (!register_operand (operands[0], <MODE>mode))
413 if (push_operand (operands[0], <MODE>mode) ?
414 !nosp_reg_operand (operands[1], <MODE>mode) :
415 !reg_or_u4bits_operand (operands[1], <MODE>mode))
417 operands[1] = copy_to_mode_reg (<MODE>mode, operands[1]);
424 (define_insn "push<mode>_internal"
425 [(set (match_operand:ALLMT 0 "push_operand" "=<pushCnstr>")
426 (match_operand:ALLMT 1 "nosp_reg_operand" "b"))]
429 [(set_attr "length" "<lpush>")]
432 (define_insn "mov<mode>_regs"
433 [(set (match_operand:SISFM 0 "register_operand" "=r, r, r, k")
434 (match_operand:SISFM 1 "nonmemory_operand" "r, <iF>, k, r"))]
441 [(set_attr "length" "2,6,4,4")]
444 (define_insn "mov<mode>_regs"
445 [(set (match_operand:DIDFM 0 "register_operand" "=r, r, r, k")
446 (match_operand:DIDFM 1 "nonmemory_operand" "r, <iF>, k, r"))]
449 switch (which_alternative)
451 case 0: if (REGNO (operands[0]) > REGNO (operands[1]))
452 return "movd\t%H1, %H0\;movd\t%L1, %L0";
454 return "movd\t%L1, %L0\;movd\t%H1, %H0";
455 case 1: return "movd\t%H1, %H0\;movd\t%L1, %L0";
456 case 2: return "mfpr\t%H1, %H0\;mfpr\t%L1, %L0";
457 case 3: return "mtpr\t%H1, %H0\;mtpr\t%L1, %L0";
458 default: gcc_unreachable ();
461 [(set_attr "length" "4,12,8,8")]
464 (define_insn "mov<mode>_regs" ; no HI/QI mode in HILO regs
465 [(set (match_operand:SHORT 0 "register_operand" "=r, r")
466 (match_operand:SHORT 1 "nonmemory_operand" "r, i"))]
469 [(set_attr "length" "2,<lImmArith>")]
472 (define_insn "mov<mode>_load"
473 [(set (match_operand:CRXMM 0 "register_operand" "=r")
474 (match_operand:CRXMM 1 "memory_operand" "m"))]
477 [(set_attr "length" "6")]
480 (define_insn "mov<mode>_load"
481 [(set (match_operand:DIDFM 0 "register_operand" "=r")
482 (match_operand:DIDFM 1 "memory_operand" "m"))]
485 rtx first_dest_reg = gen_rtx_REG (SImode, REGNO (operands[0]));
486 if (reg_overlap_mentioned_p (first_dest_reg, operands[1]))
487 return "loadd\t%H1, %H0\;loadd\t%L1, %L0";
488 return "loadd\t%L1, %L0\;loadd\t%H1, %H0";
490 [(set_attr "length" "12")]
493 (define_insn "mov<mode>_store"
494 [(set (match_operand:CRXMM 0 "store_operand" "=m, m")
495 (match_operand:CRXMM 1 "reg_or_u4bits_operand" "r, <JG>"))]
498 [(set_attr "length" "6")]
501 (define_insn "mov<mode>_store"
502 [(set (match_operand:DIDFM 0 "store_operand" "=m, m")
503 (match_operand:DIDFM 1 "reg_or_u4bits_operand" "r, <JG>"))]
505 "stord\t%H1, %H0\;stord\t%L1, %L0"
506 [(set_attr "length" "12")]
509 ;; Movmem Instruction
511 (define_expand "movmemsi"
512 [(use (match_operand:BLK 0 "memory_operand" ""))
513 (use (match_operand:BLK 1 "memory_operand" ""))
514 (use (match_operand:SI 2 "nonmemory_operand" ""))
515 (use (match_operand:SI 3 "const_int_operand" ""))]
518 if (crx_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
525 ;; Compare and Branch Instructions
527 (define_insn "cbranchcc4"
529 (if_then_else (match_operator 0 "ordered_comparison_operator"
530 [(match_operand:CC 1 "cc_reg_operand" "r")
531 (match_operand 2 "cst4_operand" "L")])
532 (label_ref (match_operand 3 ""))
536 [(set_attr "length" "6")]
539 (define_insn "cbranch<mode>4"
541 (if_then_else (match_operator 0 "ordered_comparison_operator"
542 [(match_operand:CRXIM 1 "register_operand" "r")
543 (match_operand:CRXIM 2 "reg_or_cst4_operand" "rL")])
544 (label_ref (match_operand 3 "" ""))
546 (clobber (reg:CC CC_REGNUM))]
548 "cmpb%d0<tIsa>\t%2, %1, %l3"
549 [(set_attr "length" "6")]
553 ;; Scond Instructions
555 (define_expand "cstore<mode>4"
556 [(set (reg:CC CC_REGNUM)
557 (compare:CC (match_operand:CRXIM 2 "register_operand" "")
558 (match_operand:CRXIM 3 "nonmemory_operand" "")))
559 (set (match_operand:SI 0 "register_operand")
560 (match_operator:SI 1 "ordered_comparison_operator"
561 [(reg:CC CC_REGNUM) (const_int 0)]))]
566 (define_insn "cmp<mode>_internal"
567 [(set (reg:CC CC_REGNUM)
568 (compare:CC (match_operand:CRXIM 0 "register_operand" "r,r")
569 (match_operand:CRXIM 1 "nonmemory_operand" "r,i")))]
572 [(set_attr "length" "2,<lImmArith>")]
575 (define_insn "sCOND_internal"
576 [(set (match_operand:SI 0 "register_operand" "=r")
577 (match_operator:SI 1 "ordered_comparison_operator"
578 [(reg:CC CC_REGNUM) (const_int 0)]))]
581 [(set_attr "length" "2")]
584 ;; Jumps and Branches
586 (define_insn "indirect_jump_return"
594 [(set_attr "length" "2")]
597 (define_insn "indirect_jump"
599 (match_operand:SI 0 "reg_or_sym_operand" "r,i"))]
604 [(set_attr "length" "2,6")]
607 (define_insn "interrupt_return"
609 [(unspec_volatile [(const_int 0)] 0)
613 return crx_prepare_push_pop_string (1);
615 [(set_attr "length" "14")]
618 (define_insn "jump_to_imm"
620 (match_operand 0 "immediate_operand" "i"))]
623 [(set_attr "length" "6")]
628 (label_ref (match_operand 0 "" "")))]
631 [(set_attr "length" "6")]
634 ;; Function Prologue and Epilogue
636 (define_expand "prologue"
640 crx_expand_prologue ();
645 (define_insn "push_for_prologue"
647 [(set (reg:SI SP_REGNUM)
648 (minus:SI (reg:SI SP_REGNUM)
649 (match_operand:SI 0 "immediate_operand" "i")))])]
652 return crx_prepare_push_pop_string (0);
654 [(set_attr "length" "4")]
657 (define_expand "epilogue"
661 crx_expand_epilogue ();
666 (define_insn "pop_and_popret_return"
668 [(set (reg:SI SP_REGNUM)
669 (plus:SI (reg:SI SP_REGNUM)
670 (match_operand:SI 0 "immediate_operand" "i")))
671 (use (reg:SI RA_REGNUM))
676 return crx_prepare_push_pop_string (1);
678 [(set_attr "length" "4")]
681 (define_insn "popret_RA_return"
683 [(use (reg:SI RA_REGNUM))
688 [(set_attr "length" "2")]
693 (define_insn "tablejump"
695 (match_operand:SI 0 "register_operand" "r"))
696 (use (label_ref:SI (match_operand 1 "" "" )))]
699 [(set_attr "length" "2")]
704 (define_expand "call"
705 [(call (match_operand:QI 0 "memory_operand" "")
706 (match_operand 1 "" ""))]
709 emit_call_insn (gen_crx_call (operands[0], operands[1]));
714 (define_expand "crx_call"
716 [(call (match_operand:QI 0 "memory_operand" "")
717 (match_operand 1 "" ""))
718 (clobber (reg:SI RA_REGNUM))])]
723 (define_insn "crx_call_insn_branch"
724 [(call (mem:QI (match_operand:SI 0 "immediate_operand" "i"))
725 (match_operand 1 "" ""))
726 (clobber (match_operand:SI 2 "register_operand" "+r"))]
729 [(set_attr "length" "6")]
732 (define_insn "crx_call_insn_jump"
733 [(call (mem:QI (match_operand:SI 0 "register_operand" "r"))
734 (match_operand 1 "" ""))
735 (clobber (match_operand:SI 2 "register_operand" "+r"))]
738 [(set_attr "length" "2")]
741 (define_insn "crx_call_insn_jalid"
742 [(call (mem:QI (mem:SI (plus:SI
743 (match_operand:SI 0 "register_operand" "r")
744 (match_operand:SI 1 "register_operand" "r"))))
745 (match_operand 2 "" ""))
746 (clobber (match_operand:SI 3 "register_operand" "+r"))]
749 [(set_attr "length" "4")]
752 ;; Call Value Instructions
754 (define_expand "call_value"
755 [(set (match_operand 0 "general_operand" "")
756 (call (match_operand:QI 1 "memory_operand" "")
757 (match_operand 2 "" "")))]
760 emit_call_insn (gen_crx_call_value (operands[0], operands[1], operands[2]));
765 (define_expand "crx_call_value"
767 [(set (match_operand 0 "general_operand" "")
768 (call (match_operand 1 "memory_operand" "")
769 (match_operand 2 "" "")))
770 (clobber (reg:SI RA_REGNUM))])]
775 (define_insn "crx_call_value_insn_branch"
776 [(set (match_operand 0 "" "=g")
777 (call (mem:QI (match_operand:SI 1 "immediate_operand" "i"))
778 (match_operand 2 "" "")))
779 (clobber (match_operand:SI 3 "register_operand" "+r"))]
782 [(set_attr "length" "6")]
785 (define_insn "crx_call_value_insn_jump"
786 [(set (match_operand 0 "" "=g")
787 (call (mem:QI (match_operand:SI 1 "register_operand" "r"))
788 (match_operand 2 "" "")))
789 (clobber (match_operand:SI 3 "register_operand" "+r"))]
792 [(set_attr "length" "2")]
795 (define_insn "crx_call_value_insn_jalid"
796 [(set (match_operand 0 "" "=g")
797 (call (mem:QI (mem:SI (plus:SI
798 (match_operand:SI 1 "register_operand" "r")
799 (match_operand:SI 2 "register_operand" "r"))))
800 (match_operand 3 "" "")))
801 (clobber (match_operand:SI 4 "register_operand" "+r"))]
804 [(set_attr "length" "4")]
815 ;; Multiply and Accumulate Instructions
817 (define_insn "<sPat>madsidi3"
818 [(set (match_operand:DI 0 "register_operand" "+k")
820 (mult:DI (sz_xtnd:DI (match_operand:SI 1 "register_operand" "%r"))
821 (sz_xtnd:DI (match_operand:SI 2 "register_operand" "r")))
823 (clobber (reg:CC CC_REGNUM))]
826 [(set_attr "length" "4")]
829 (define_insn "<sPat>madhisi3"
830 [(set (match_operand:SI 0 "register_operand" "+l")
832 (mult:SI (sz_xtnd:SI (match_operand:HI 1 "register_operand" "%r"))
833 (sz_xtnd:SI (match_operand:HI 2 "register_operand" "r")))
835 (clobber (reg:CC CC_REGNUM))]
838 [(set_attr "length" "4")]
841 (define_insn "<sPat>madqihi3"
842 [(set (match_operand:HI 0 "register_operand" "+l")
844 (mult:HI (sz_xtnd:HI (match_operand:QI 1 "register_operand" "%r"))
845 (sz_xtnd:HI (match_operand:QI 2 "register_operand" "r")))
847 (clobber (reg:CC CC_REGNUM))]
850 [(set_attr "length" "4")]
855 (define_expand "doloop_end"
856 [(use (match_operand 0 "" "")) ; loop pseudo
857 (use (match_operand 1 "" "")) ; iterations; zero if unknown
858 (use (match_operand 2 "" "")) ; max iterations
859 (use (match_operand 3 "" "")) ; loop level
860 (use (match_operand 4 "" ""))] ; label
863 if (INTVAL (operands[3]) > crx_loop_nesting)
865 switch (GET_MODE (operands[0]))
868 emit_jump_insn (gen_doloop_end_si (operands[4], operands[0]));
871 emit_jump_insn (gen_doloop_end_hi (operands[4], operands[0]));
874 emit_jump_insn (gen_doloop_end_qi (operands[4], operands[0]));
883 ; CRX dbnz[bwd] used explicitly (see above) but also by the combiner.
885 (define_insn "doloop_end_<mode>"
887 (if_then_else (ne (match_operand:CRXIM 1 "register_operand" "+r,!m")
889 (label_ref (match_operand 0 "" ""))
891 (set (match_dup 1) (plus:CRXIM (match_dup 1) (const_int -1)))
892 (clobber (match_scratch:CRXIM 2 "=X,r"))
893 (clobber (reg:CC CC_REGNUM))]
897 load<tIsa>\t%1, %2\;add<tIsa>\t$-1, %2\;stor<tIsa>\t%2, %1\;bne\t%l0"
898 [(set_attr "length" "6, 12")]