| blob | cdcc3667f7478d3cc453c1b2ac6ea5a40a8e2eaa |
1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
48 /* Forward definitions of types. */
52 /* In order to improve the layout of the prototypes below
53 some short type abbreviations are defined here. */
54 #define Hint HOST_WIDE_INT
55 #define Mmode enum machine_mode
56 #define Ulong unsigned long
58 /* Forward function declarations. */
72 static const char * output_multi_immediate PARAMS ((rtx *, const char *, const char *, int, Hint));
98 \f
99 #undef Hint
100 #undef Mmode
101 #undef Ulong
103 /* Obstack for minipool constant handling. */
107 #define obstack_chunk_alloc xmalloc
108 #define obstack_chunk_free free
110 /* The maximum number of insns skipped which will be conditionalised if
111 possible. */
116 /* True if we are currently building a constant table. */
119 /* Define the information needed to generate branch insns. This is
120 stored from the compare operation. */
123 /* What type of floating point are we tuning for? */
126 /* What type of floating point instructions are available? */
129 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
132 /* Set by the -mfp=... option. */
135 /* Used to parse -mstructure_size_boundary command line option. */
139 /* Bit values used to identify processor capabilities. */
152 /* The bits in this mask specify which instructions we are
153 allowed to generate. */
156 /* The bits in this mask specify which instruction scheduling options should
157 be used. Note - there is an overlap with the FL_FAST_MULT. For some
158 hardware we want to be able to generate the multiply instructions, but to
159 tune as if they were not present in the architecture. */
162 /* The following are used in the arm.md file as equivalents to bits
163 in the above two flag variables. */
165 /* Nonzero if this is an "M" variant of the processor. */
168 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
171 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
174 /* Nonzero if this chip can benefit from load scheduling. */
177 /* Nonzero if this chip is a StrongARM. */
180 /* Nonzero if this chip is an XScale. */
183 /* Nonzero if this chip is a an ARM6 or an ARM7. */
186 /* Nonzero if generating Thumb instructions. */
189 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
190 must report the mode of the memory reference from PRINT_OPERAND to
191 PRINT_OPERAND_ADDRESS. */
194 /* Nonzero if the prologue must setup `fp'. */
197 /* The register number to be used for the PIC offset register. */
201 /* Set to 1 when a return insn is output, this means that the epilogue
202 is not needed. */
205 /* Set to 1 after arm_reorg has started. Reset to start at the start of
206 the next function. */
209 /* The maximum number of insns to be used when loading a constant. */
212 /* For an explanation of these variables, see final_prescan_insn below. */
215 rtx arm_target_insn;
218 /* The condition codes of the ARM, and the inverse function. */
220 {
223 };
225 #define streq(string1, string2) (strcmp (string1, string2) == 0)
226 \f
227 /* Initialization code. */
229 struct processors
230 {
233 };
235 /* Not all of these give usefully different compilation alternatives,
236 but there is no simple way of generalizing them. */
238 {
239 /* ARM Cores */
250 /* arm7m doesn't exist on its own, but only with D, (and I), but
251 those don't alter the code, so arm7m is sometimes used. */
265 /* Doesn't have an external co-proc, but does have embedded fpu. */
277 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_ARCH5 },
280 };
283 {
284 /* ARM Architectures */
291 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
292 implementations that support it, so we will leave it out for now. */
296 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
298 };
300 /* This is a magic stucture. The 'string' field is magically filled in
301 with a pointer to the value specified by the user on the command line
302 assuming that the user has specified such a value. */
305 {
306 /* string name processors */
310 };
312 /* Return the number of bits set in value' */
313 static unsigned long
316 {
320 {
323 }
326 }
328 /* Fix up any incompatible options that the user has specified.
329 This has now turned into a maze. */
330 void
332 {
335 /* Set up the flags based on the cpu/architecture selected by the user. */
337 {
341 {
346 {
349 else
350 {
351 /* If we have been given an architecture and a processor
352 make sure that they are compatible. We only generate
353 a warning though, and we prefer the CPU over the
354 architecture. */
360 }
363 }
367 }
368 }
370 /* If the user did not specify a processor, choose one for them. */
372 {
375 static struct cpu_default
376 {
379 }
380 cpu_defaults[] =
381 {
396 };
399 /* Find the default. */
404 /* Make sure we found the default CPU. */
408 /* Find the default CPU's flags. */
418 /* Now check to see if the user has specified some command line
419 switch that require certain abilities from the cpu. */
423 {
426 /* Force apcs-32 to be used for interworking. */
429 /* There are no ARM processors that support both APCS-26 and
430 interworking. Therefore we force FL_MODE26 to be removed
431 from insn_flags here (if it was set), so that the search
432 below will always be able to find a compatible processor. */
434 }
439 {
440 /* Try to locate a CPU type that supports all of the abilities
441 of the default CPU, plus the extra abilities requested by
442 the user. */
448 {
452 /* Ideally we would like to issue an error message here
453 saying that it was not possible to find a CPU compatible
454 with the default CPU, but which also supports the command
455 line options specified by the programmer, and so they
456 ought to use the -mcpu=<name> command line option to
457 override the default CPU type.
459 Unfortunately this does not work with multilibing. We
460 need to be able to support multilibs for -mapcs-26 and for
461 -mthumb-interwork and there is no CPU that can support both
462 options. Instead if we cannot find a cpu that has both the
463 characteristics of the default cpu and the given command line
464 options we scan the array again looking for a best match. */
467 {
473 {
476 }
477 }
481 else
483 }
486 }
487 }
489 /* If tuning has not been specified, tune for whichever processor or
490 architecture has been selected. */
494 /* Make sure that the processor choice does not conflict with any of the
495 other command line choices. */
497 {
498 /* If APCS-32 was not the default then it must have been set by the
499 user, so issue a warning message. If the user has specified
500 "-mapcs-32 -mcpu=arm2" then we loose here. */
504 }
506 {
509 }
512 {
515 }
518 {
521 }
524 {
525 /* warning ("ignoring -mapcs-frame because -mthumb was used."); */
527 }
529 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
530 from here where no function is being compiled currently. */
536 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb.");
539 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb.");
541 /* If interworking is enabled then APCS-32 must be selected as well. */
543 {
547 }
550 {
553 }
564 /* If this target is normally configured to use APCS frames, warn if they
565 are turned off and debugging is turned on. */
568 && !TARGET_APCS_FRAME
572 /* If stack checking is disabled, we can use r10 as the PIC register,
573 which keeps r9 available. */
580 /* Initialise boolean versions of the flags, for use in the arm.md file. */
592 /* Default value for floating point code... if no co-processor
593 bus, then schedule for emulated floating point. Otherwise,
594 assume the user has an FPA.
595 Note: this does not prevent use of floating point instructions,
596 -msoft-float does that. */
600 {
605 else
607 target_fp_name);
608 }
609 else
615 /* For arm2/3 there is no need to do any scheduling if there is only
616 a floating point emulator, or we are doing software floating-point. */
624 {
629 else
631 }
634 {
642 /* Prevent the user from choosing an obviously stupid PIC register. */
648 else
650 }
653 {
654 /* Don't warn since it's on by default in -O2. */
656 }
658 /* If optimizing for space, don't synthesize constants.
659 For processors with load scheduling, it never costs more than 2 cycles
660 to load a constant, and the load scheduler may well reduce that to 1. */
667 /* If optimizing for size, bump the number of instructions that we
668 are prepared to conditionally execute (even on a StrongARM).
669 Otherwise for the StrongARM, which has early execution of branches,
670 a sequence that is worth skipping is shorter. */
676 /* Register global variables with the garbage collector. */
678 }
680 static void
682 {
689 }
690 \f
691 /* Return 1 if it is possible to return using a single instruction. */
692 int
695 {
698 /* Never use a return instruction before reload has run. */
700 /* Or if the function is variadic. */
701 || current_function_pretend_args_size
702 || current_function_anonymous_args
703 /* Of if the function calls __builtin_eh_return () */
705 /* Or if there is no frame pointer and there is a stack adjustment. */
710 /* Can't be done if interworking with Thumb, and any registers have been
711 stacked. Similarly, on StrongARM, conditional returns are expensive
712 if they aren't taken and registers have been stacked. */
718 {
725 }
727 /* Can't be done if any of the FPU regs are pushed, since this also
728 requires an insn. */
734 /* If a function is naked, don't use the "return" insn. */
739 }
741 /* Return TRUE if int I is a valid immediate ARM constant. */
743 int
745 HOST_WIDE_INT i;
746 {
749 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
750 be all zero, or all one. */
757 /* Fast return for 0 and powers of 2 */
761 do
762 {
765 mask =
771 }
773 /* Return true if I is a valid constant for the operation CODE. */
774 static int
776 HOST_WIDE_INT i;
778 {
783 {
797 }
798 }
800 /* Emit a sequence of insns to handle a large constant.
801 CODE is the code of the operation required, it can be any of SET, PLUS,
802 IOR, AND, XOR, MINUS;
803 MODE is the mode in which the operation is being performed;
804 VAL is the integer to operate on;
805 SOURCE is the other operand (a register, or a null-pointer for SET);
806 SUBTARGETS means it is safe to create scratch registers if that will
807 either produce a simpler sequence, or we will want to cse the values.
808 Return value is the number of insns emitted. */
810 int
814 HOST_WIDE_INT val;
815 rtx target;
816 rtx source;
818 {
822 {
823 /* After arm_reorg has been called, we can't fix up expensive
824 constants by pushing them into memory so we must synthesise
825 them in-line, regardless of the cost. This is only likely to
826 be more costly on chips that have load delay slots and we are
827 compiling without running the scheduler (so no splitting
828 occurred before the final instruction emission).
830 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
831 */
835 {
837 {
838 /* Currently SET is the only monadic value for CODE, all
839 the rest are diadic. */
842 }
843 else
844 {
848 /* For MINUS, the value is subtracted from, since we never
849 have subtraction of a constant. */
853 else
857 }
858 }
859 }
862 }
864 /* As above, but extra parameter GENERATE which, if clear, suppresses
865 RTL generation. */
866 static int
870 HOST_WIDE_INT val;
871 rtx target;
872 rtx source;
875 {
890 /* Find out which operations are safe for a given CODE. Also do a quick
891 check for degenerate cases; these can occur when DImode operations
892 are split. */
894 {
908 {
913 }
915 {
921 }
926 {
930 }
932 {
938 }
944 {
950 }
952 {
957 }
959 /* We don't know how to handle this yet below. */
963 /* We treat MINUS as (val - source), since (source - val) is always
964 passed as (source + (-val)). */
966 {
971 }
973 {
977 source)));
979 }
986 }
988 /* If we can do it in one insn get out quickly. */
992 {
999 }
1001 /* Calculate a few attributes that may be useful for specific
1002 optimizations. */
1004 {
1006 clear_sign_bit_copies++;
1007 else
1009 }
1012 {
1014 set_sign_bit_copies++;
1015 else
1017 }
1020 {
1022 clear_zero_bit_copies++;
1023 else
1025 }
1028 {
1030 set_zero_bit_copies++;
1031 else
1033 }
1036 {
1038 /* See if we can do this by sign_extending a constant that is known
1039 to be negative. This is a good, way of doing it, since the shift
1040 may well merge into a subsequent insn. */
1042 {
1046 {
1048 {
1054 }
1056 }
1057 /* For an inverted constant, we will need to set the low bits,
1058 these will be shifted out of harm's way. */
1061 {
1063 {
1069 }
1071 }
1072 }
1074 /* See if we can generate this by setting the bottom (or the top)
1075 16 bits, and then shifting these into the other half of the
1076 word. We only look for the simplest cases, to do more would cost
1077 too much. Be careful, however, not to generate this when the
1078 alternative would take fewer insns. */
1080 {
1084 /* Overlaps outside this range are best done using other methods. */
1086 {
1090 {
1091 rtx new_src = (subtargets
1103 source)));
1105 }
1106 }
1108 /* Don't duplicate cases already considered. */
1110 {
1113 {
1114 rtx new_src = (subtargets
1121 emit_insn
1123 gen_rtx_IOR
1127 source)));
1129 }
1130 }
1131 }
1136 /* If we have IOR or XOR, and the constant can be loaded in a
1137 single instruction, and we can find a temporary to put it in,
1138 then this can be done in two instructions instead of 3-4. */
1140 /* TARGET can't be NULL if SUBTARGETS is 0 */
1142 {
1144 {
1146 {
1152 }
1154 }
1155 }
1162 {
1164 {
1171 source,
1172 shift))));
1176 shift))));
1177 }
1179 }
1183 {
1185 {
1192 source,
1193 shift))));
1197 shift))));
1198 }
1200 }
1203 {
1205 {
1217 }
1219 }
1223 /* See if two shifts will do 2 or more insn's worth of work. */
1225 {
1231 {
1233 {
1238 }
1239 else
1240 {
1244 }
1245 }
1248 {
1254 }
1257 }
1260 {
1264 {
1266 {
1272 }
1273 else
1274 {
1279 }
1280 }
1283 {
1289 }
1292 }
1298 }
1302 num_bits_set++;
1308 else
1309 {
1312 }
1314 /* Now try and find a way of doing the job in either two or three
1315 instructions.
1316 We start by looking for the largest block of zeros that are aligned on
1317 a 2-bit boundary, we then fill up the temps, wrapping around to the
1318 top of the word when we drop off the bottom.
1319 In the worst case this code should produce no more than four insns. */
1320 {
1325 {
1329 {
1331 {
1334 }
1336 {
1339 }
1341 }
1342 }
1344 /* Now start emitting the insns, starting with the one with the highest
1345 bit set: we do this so that the smallest number will be emitted last;
1346 this is more likely to be combinable with addressing insns. */
1348 do
1349 {
1355 {
1364 {
1365 rtx new_src;
1369 new_src = (subtargets
1376 new_src = (subtargets
1380 source)));
1381 else
1383 new_src = (remainder
1384 ? (subtargets
1390 : (can_negate
1391 ? -temp1
1394 }
1397 {
1400 }
1404 insns++;
1406 }
1409 }
1411 }
1413 /* Canonicalize a comparison so that we are more likely to recognize it.
1414 This can be done for a few constant compares, where we can make the
1415 immediate value easier to load. */
1416 enum rtx_code
1420 {
1424 {
1433 {
1436 }
1443 {
1446 }
1453 {
1456 }
1463 {
1466 }
1471 }
1474 }
1476 /* Decide whether a type should be returned in memory (true)
1477 or in a register (false). This is called by the macro
1478 RETURN_IN_MEMORY. */
1479 int
1481 tree type;
1482 {
1484 /* All simple types are returned in registers. */
1487 /* For the arm-wince targets we choose to be compitable with Microsoft's
1488 ARM and Thumb compilers, which always return aggregates in memory. */
1489 #ifndef ARM_WINCE
1492 /* All structures/unions bigger than one word are returned in memory. */
1496 {
1497 tree field;
1499 /* For a struct the APCS says that we only return in a register
1500 if the type is 'integer like' and every addressable element
1501 has an offset of zero. For practical purposes this means
1502 that the structure can have at most one non bit-field element
1503 and that this element must be the first one in the structure. */
1505 /* Find the first field, ignoring non FIELD_DECL things which will
1506 have been created by C++. */
1515 /* Check that the first field is valid for returning in a register. */
1517 /* ... Floats are not allowed */
1521 /* ... Aggregates that are not themselves valid for returning in
1522 a register are not allowed. */
1526 /* Now check the remaining fields, if any. Only bitfields are allowed,
1527 since they are not addressable. */
1529 field;
1531 {
1537 }
1540 }
1543 {
1544 tree field;
1546 /* Unions can be returned in registers if every element is
1547 integral, or can be returned in an integer register. */
1549 field;
1551 {
1560 }
1563 }
1566 /* Return all other types in memory. */
1568 }
1570 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1571 for a call to a function whose data type is FNTYPE.
1572 For a library call, FNTYPE is NULL. */
1573 void
1576 tree fntype;
1577 rtx libname ATTRIBUTE_UNUSED;
1579 {
1580 /* On the ARM, the offset starts at 0. */
1588 /* Check for long call/short call attributes. The attributes
1589 override any command line option. */
1591 {
1596 }
1597 }
1599 /* Determine where to put an argument to a function.
1600 Value is zero to push the argument on the stack,
1601 or a hard register in which to store the argument.
1603 MODE is the argument's machine mode.
1604 TYPE is the data type of the argument (as a tree).
1605 This is null for libcalls where that information may
1606 not be available.
1607 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1608 the preceding args and about the function being called.
1609 NAMED is nonzero if this argument is a named parameter
1610 (otherwise it is an extra parameter matching an ellipsis). */
1611 rtx
1615 tree type ATTRIBUTE_UNUSED;
1617 {
1619 /* Compute operand 2 of the call insn. */
1626 }
1627 \f
1628 /* Encode the current state of the #pragma [no_]long_calls. */
1630 {
1633 SHORT /* #pragma no_long_calls is in effect. */
1638 void
1641 {
1643 }
1645 void
1648 {
1650 }
1652 void
1655 {
1657 }
1659 \f
1660 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
1661 attribute for TYPE. The attributes in ATTRIBUTES have previously been
1662 assigned to TYPE. */
1663 int
1665 tree type;
1666 tree attributes ATTRIBUTE_UNUSED;
1667 tree identifier;
1668 tree args;
1669 {
1676 /* Function calls made to this symbol must be done indirectly, because
1677 it may lie outside of the 26 bit addressing range of a normal function
1678 call. */
1682 /* Whereas these functions are always known to reside within the 26 bit
1683 addressing range. */
1688 }
1690 /* Return 0 if the attributes for two types are incompatible, 1 if they
1691 are compatible, and 2 if they are nearly compatible (which causes a
1692 warning to be generated). */
1693 int
1695 tree type1;
1696 tree type2;
1697 {
1700 /* Check for mismatch of non-default calling convention. */
1704 /* Check for mismatched call attributes. */
1710 /* Only bother to check if an attribute is defined. */
1712 {
1713 /* If one type has an attribute, the other must have the same attribute. */
1717 /* Disallow mixed attributes. */
1720 }
1723 }
1725 /* Encode long_call or short_call attribute by prefixing
1726 symbol name in DECL with a special character FLAG. */
1727 void
1729 tree decl;
1731 {
1739 /* Do not allow weak functions to be treated as short call. */
1749 }
1751 /* Assigns default attributes to newly defined type. This is used to
1752 set short_call/long_call attributes for function types of
1753 functions defined inside corresponding #pragma scopes. */
1754 void
1756 tree type;
1757 {
1758 /* Add __attribute__ ((long_call)) to all functions, when
1759 inside #pragma long_calls or __attribute__ ((short_call)),
1760 when inside #pragma no_long_calls. */
1762 {
1770 else
1775 }
1776 }
1777 \f
1778 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
1779 defined within the current compilation unit. If this caanot be
1780 determined, then 0 is returned. */
1781 static int
1783 rtx sym_ref;
1784 {
1785 /* This is a bit of a fib. A function will have a short call flag
1786 applied to its name if it has the short call attribute, or it has
1787 already been defined within the current compilation unit. */
1791 /* The current function is always defined within the current compilation
1792 unit. if it s a weak defintion however, then this may not be the real
1793 defintion of the function, and so we have to say no. */
1798 /* We cannot make the determination - default to returning 0. */
1800 }
1802 /* Return non-zero if a 32 bit "long_call" should be generated for
1803 this call. We generate a long_call if the function:
1805 a. has an __attribute__((long call))
1806 or b. is within the scope of a #pragma long_calls
1807 or c. the -mlong-calls command line switch has been specified
1809 However we do not generate a long call if the function:
1811 d. has an __attribute__ ((short_call))
1812 or e. is inside the scope of a #pragma no_long_calls
1813 or f. has an __attribute__ ((section))
1814 or g. is defined within the current compilation unit.
1816 This function will be called by C fragments contained in the machine
1817 description file. CALL_REF and CALL_COOKIE correspond to the matched
1818 rtl operands. CALL_SYMBOL is used to distinguish between
1819 two different callers of the function. It is set to 1 in the
1820 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
1821 and "call_value" patterns. This is because of the difference in the
1822 SYM_REFs passed by these patterns. */
1823 int
1825 rtx sym_ref;
1828 {
1830 {
1835 }
1852 }
1854 /* Return non-zero if it is ok to make a tail-call to DECL. */
1855 int
1857 tree decl;
1858 {
1861 /* Never tailcall something for which we have no decl, or if we
1862 are in Thumb mode. */
1866 /* Get the calling method. */
1872 /* Cannot tail-call to long calls, since these are out of range of
1873 a branch instruction. However, if not compiling PIC, we know
1874 we can reach the symbol if it is in this compilation unit. */
1878 /* If we are interworking and the function is not declared static
1879 then we can't tail-call it unless we know that it exists in this
1880 compilation unit (since it might be a Thumb routine). */
1884 /* Everything else is ok. */
1886 }
1888 \f
1889 int
1891 rtx x;
1892 {
1894 && flag_pic
1902 }
1904 rtx
1906 rtx orig;
1908 rtx reg;
1909 {
1911 {
1913 rtx insn;
1917 {
1920 else
1924 }
1926 #ifdef AOF_ASSEMBLER
1927 /* The AOF assembler can generate relocations for these directly, and
1928 understands that the PIC register has to be added into the offset. */
1930 #else
1933 else
1938 else
1943 address));
1946 #endif
1948 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1949 by loop. */
1953 }
1955 {
1963 {
1966 else
1968 }
1971 {
1975 }
1976 else
1980 {
1981 /* The base register doesn't really matter, we only want to
1982 test the index for the appropriate mode. */
1987 else
1990 win:
1993 }
1998 {
2001 }
2004 }
2006 {
2010 {
2015 else
2022 }
2023 }
2026 }
2030 int
2032 rtx x;
2033 {
2037 }
2039 void
2041 {
2042 #ifndef AOF_ASSEMBLER
2044 rtx global_offset_table;
2056 /* On the ARM the PC register contains 'dot + 8' at the time of the
2057 addition, on the Thumb it is 'dot + 4'. */
2062 else
2068 {
2071 }
2072 else
2073 {
2076 }
2082 /* Need to emit this whether or not we obey regdecls,
2083 since setjmp/longjmp can cause life info to screw up. */
2086 }
2088 #define REG_OR_SUBREG_REG(X) \
2089 (GET_CODE (X) == REG \
2090 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2092 #define REG_OR_SUBREG_RTX(X) \
2093 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2095 #ifndef COSTS_N_INSNS
2096 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2097 #endif
2099 int
2101 rtx x;
2104 {
2110 {
2112 {
2126 {
2131 {
2133 cycles++;
2134 }
2136 }
2146 {
2152 }
2182 /* XXX guess. */
2187 /* XXX another guess. */
2188 /* Memory costs quite a lot for the first word, but subsequent words
2189 load at the equivalent of a single insn each. */
2194 /* XXX a guess. */
2200 /* XXX still guessing. */
2202 {
2216 }
2220 #if 0
2225 /* XXX guess */
2229 #endif
2230 }
2231 }
2234 {
2236 /* Memory costs quite a lot for the first word, but subsequent words
2237 load at the equivalent of a single insn each. */
2248 /* Fall through */
2252 /* Fall through */
2303 /* Fall through */
2313 /* Fall through */
2317 /* Normally the frame registers will be spilt into reg+const during
2318 reload, so it is a bad idea to combine them with other instructions,
2319 since then they might not be moved outside of loops. As a compromise
2320 we allow integration with ops that have a constant as their second
2321 operand. */
2360 /* There is no point basing this on the tuning, since it is always the
2361 fast variant if it exists at all. */
2373 {
2379 /* Tune as appropriate. */
2383 {
2386 }
2389 }
2409 /* Fall through */
2431 /* Fall through */
2434 {
2448 }
2461 else
2479 }
2480 }
2482 int
2484 rtx insn;
2485 rtx link;
2486 rtx dep;
2488 {
2491 /* Some true dependencies can have a higher cost depending
2492 on precisely how certain input operands are used. */
2497 {
2501 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
2502 operand for INSN. If we have a shifted input operand and the
2503 instruction we depend on is another ALU instruction, then we may
2504 have to account for an additional stall. */
2506 {
2507 rtx shifted_operand;
2510 /* Get the shifted operand. */
2514 /* Iterate over all the operands in DEP. If we write an operand
2515 that overlaps with SHIFTED_OPERAND, then we have increase the
2516 cost of this dependency. */
2520 {
2521 /* We can ignore strict inputs. */
2526 shifted_operand))
2528 }
2529 }
2530 }
2532 /* XXX This is not strictly true for the FPA. */
2537 /* Call insns don't incur a stall, even if they follow a load. */
2546 {
2547 /* This is a load after a store, there is no conflict if the load reads
2548 from a cached area. Assume that loads from the stack, and from the
2549 constant pool are cached, and that others will miss. This is a
2550 hack. */
2558 }
2561 }
2563 /* This code has been fixed for cross compilation. */
2568 {
2571 };
2575 static void
2577 {
2579 REAL_VALUE_TYPE r;
2582 {
2585 }
2588 }
2590 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2592 int
2594 rtx x;
2595 {
2596 REAL_VALUE_TYPE r;
2611 }
2613 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2615 int
2617 rtx x;
2618 {
2619 REAL_VALUE_TYPE r;
2635 }
2636 \f
2637 /* Predicates for `match_operand' and `match_operator'. */
2639 /* s_register_operand is the same as register_operand, but it doesn't accept
2640 (SUBREG (MEM)...).
2642 This function exists because at the time it was put in it led to better
2643 code. SUBREG(MEM) always needs a reload in the places where
2644 s_register_operand is used, and this seemed to lead to excessive
2645 reloading. */
2647 int
2651 {
2658 /* We don't consider registers whose class is NO_REGS
2659 to be a register operand. */
2660 /* XXX might have to check for lo regs only for thumb ??? */
2664 }
2666 /* Only accept reg, subreg(reg), const_int. */
2668 int
2672 {
2682 /* We don't consider registers whose class is NO_REGS
2683 to be a register operand. */
2687 }
2689 /* Return 1 if OP is an item in memory, given that we are in reload. */
2691 int
2693 rtx op;
2695 {
2702 }
2704 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2705 memory access (architecture V4).
2706 MODE is QImode if called when computing contraints, or VOIDmode when
2707 emitting patterns. In this latter case we cannot use memory_operand()
2708 because it will fail on badly formed MEMs, which is precisly what we are
2709 trying to catch. */
2710 int
2712 rtx op;
2714 {
2715 #if 0
2718 #endif
2724 /* A sum of anything more complex than reg + reg or reg + const is bad. */
2731 /* Big constants are also bad. */
2737 /* Everything else is good, or can will automatically be made so. */
2739 }
2741 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2743 int
2745 rtx op;
2747 {
2750 }
2752 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2753 */
2755 int
2757 rtx op;
2759 {
2763 }
2765 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2766 constant that is valid when negated. */
2768 int
2770 rtx op;
2772 {
2780 }
2782 int
2784 rtx op;
2786 {
2791 }
2793 /* Return TRUE if the operand is a memory reference which contains an
2794 offsettable address. */
2795 int
2799 {
2807 }
2809 /* Return TRUE if the operand is a memory reference which is, or can be
2810 made word aligned by adjusting the offset. */
2811 int
2815 {
2816 rtx reg;
2835 }
2837 /* Similar to s_register_operand, but does not allow hard integer
2838 registers. */
2839 int
2843 {
2850 /* We don't consider registers whose class is NO_REGS
2851 to be a register operand. */
2855 }
2857 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2859 int
2861 rtx op;
2863 {
2874 }
2876 int
2878 rtx op;
2880 {
2892 }
2894 /* Return nonzero if OP is a constant power of two. */
2896 int
2898 rtx op;
2900 {
2902 {
2905 }
2907 }
2909 /* Return TRUE for a valid operand of a DImode operation.
2910 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2911 Note that this disallows MEM(REG+REG), but allows
2912 MEM(PRE/POST_INC/DEC(REG)). */
2914 int
2916 rtx op;
2918 {
2929 {
2939 }
2940 }
2942 /* Like di_operand, but don't accept constants. */
2943 int
2945 rtx op;
2947 {
2961 }
2963 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2964 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2965 Note that this disallows MEM(REG+REG), but allows
2966 MEM(PRE/POST_INC/DEC(REG)). */
2968 int
2970 rtx op;
2972 {
2986 {
2995 }
2996 }
2998 /* Like soft_df_operand, but don't accept constants. */
2999 int
3001 rtx op;
3003 {
3016 }
3018 /* Return TRUE for valid index operands. */
3019 int
3021 rtx op;
3023 {
3028 }
3030 /* Return TRUE for valid shifts by a constant. This also accepts any
3031 power of two on the (somewhat overly relaxed) assumption that the
3032 shift operator in this case was a mult. */
3034 int
3036 rtx op;
3038 {
3043 }
3045 /* Return TRUE for arithmetic operators which can be combined with a multiply
3046 (shift). */
3048 int
3050 rtx x;
3052 {
3055 else
3056 {
3061 }
3062 }
3064 /* Return TRUE for binary logical operators. */
3066 int
3068 rtx x;
3070 {
3073 else
3074 {
3078 }
3079 }
3081 /* Return TRUE for shift operators. */
3083 int
3085 rtx x;
3087 {
3090 else
3091 {
3099 }
3100 }
3102 /* Return TRUE if x is EQ or NE. */
3103 int
3105 rtx x;
3107 {
3109 }
3111 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
3112 int
3114 rtx x;
3116 {
3120 }
3122 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3123 int
3125 rtx x;
3127 {
3134 }
3136 /* Return TRUE if this is the condition code register, if we aren't given
3137 a mode, accept any class CCmode register. */
3138 int
3140 rtx x;
3142 {
3144 {
3149 }
3157 }
3159 /* Return TRUE if this is the condition code register, if we aren't given
3160 a mode, accept any class CCmode register which indicates a dominance
3161 expression. */
3162 int
3164 rtx x;
3166 {
3168 {
3173 }
3183 }
3185 /* Return TRUE if X references a SYMBOL_REF. */
3186 int
3188 rtx x;
3189 {
3199 {
3201 {
3207 }
3210 }
3213 }
3215 /* Return TRUE if X references a LABEL_REF. */
3216 int
3218 rtx x;
3219 {
3228 {
3230 {
3236 }
3239 }
3242 }
3244 enum rtx_code
3246 rtx x;
3247 {
3260 }
3262 /* Return 1 if memory locations are adjacent. */
3263 int
3266 {
3276 {
3278 {
3281 }
3282 else
3285 {
3288 }
3289 else
3292 }
3294 }
3296 /* Return 1 if OP is a load multiple operation. It is known to be
3297 parallel and the first section will be tested. */
3298 int
3300 rtx op;
3302 {
3305 rtx src_addr;
3307 rtx elt;
3313 /* Check to see if this might be a write-back. */
3315 {
3316 i++;
3319 /* Now check it more carefully. */
3326 }
3328 /* Perform a quick check so we don't blow up below. */
3339 {
3353 }
3356 }
3358 /* Return 1 if OP is a store multiple operation. It is known to be
3359 parallel and the first section will be tested. */
3360 int
3362 rtx op;
3364 {
3367 rtx dest_addr;
3369 rtx elt;
3375 /* Check to see if this might be a write-back. */
3377 {
3378 i++;
3381 /* Now check it more carefully. */
3388 }
3390 /* Perform a quick check so we don't blow up below. */
3401 {
3415 }
3418 }
3420 int
3427 {
3434 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3435 extended if required. */
3439 /* Loop over the operands and check that the memory references are
3440 suitable (ie immediate offsets from the same base register). At
3441 the same time, extract the target register, and the memory
3442 offsets. */
3444 {
3445 rtx reg;
3446 rtx offset;
3448 /* Convert a subreg of a mem into the mem itself. */
3455 /* Don't reorder volatile memory references; it doesn't seem worth
3456 looking for the case where the order is ok anyway. */
3472 {
3474 {
3480 }
3481 else
3482 {
3484 /* Not addressed from the same base register. */
3492 }
3494 /* If it isn't an integer register, or if it overwrites the
3495 base register but isn't the last insn in the list, then
3496 we can't do this. */
3502 }
3503 else
3504 /* Not a suitable memory address. */
3506 }
3508 /* All the useful information has now been extracted from the
3509 operands into unsorted_regs and unsorted_offsets; additionally,
3510 order[0] has been set to the lowest numbered register in the
3511 list. Sort the registers into order, and check that the memory
3512 offsets are ascending and adjacent. */
3515 {
3525 /* Have we found a suitable register? if not, one must be used more
3526 than once. */
3530 /* Is the memory address adjacent and ascending? */
3533 }
3536 {
3543 }
3557 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3558 if the offset isn't small enough. The reason 2 ldrs are faster
3559 is because these ARMs are able to do more than one cache access
3560 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3561 whilst the ARM8 has a double bandwidth cache. This means that
3562 these cores can do both an instruction fetch and a data fetch in
3563 a single cycle, so the trick of calculating the address into a
3564 scratch register (one of the result regs) and then doing a load
3565 multiple actually becomes slower (and no smaller in code size).
3566 That is the transformation
3568 ldr rd1, [rbase + offset]
3569 ldr rd2, [rbase + offset + 4]
3571 to
3573 add rd1, rbase, offset
3574 ldmia rd1, {rd1, rd2}
3576 produces worse code -- '3 cycles + any stalls on rd2' instead of
3577 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3578 access per cycle, the first sequence could never complete in less
3579 than 6 cycles, whereas the ldm sequence would only take 5 and
3580 would make better use of sequential accesses if not hitting the
3581 cache.
3583 We cheat here and test 'arm_ld_sched' which we currently know to
3584 only be true for the ARM8, ARM9 and StrongARM. If this ever
3585 changes, then the test below needs to be reworked. */
3589 /* Can't do it without setting up the offset, only do this if it takes
3590 no more than one insn. */
3593 }
3599 {
3602 HOST_WIDE_INT offset;
3607 {
3629 else
3640 }
3653 }
3655 int
3662 {
3669 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3670 extended if required. */
3674 /* Loop over the operands and check that the memory references are
3675 suitable (ie immediate offsets from the same base register). At
3676 the same time, extract the target register, and the memory
3677 offsets. */
3679 {
3680 rtx reg;
3681 rtx offset;
3683 /* Convert a subreg of a mem into the mem itself. */
3690 /* Don't reorder volatile memory references; it doesn't seem worth
3691 looking for the case where the order is ok anyway. */
3707 {
3709 {
3715 }
3716 else
3717 {
3719 /* Not addressed from the same base register. */
3727 }
3729 /* If it isn't an integer register, then we can't do this. */
3734 }
3735 else
3736 /* Not a suitable memory address. */
3738 }
3740 /* All the useful information has now been extracted from the
3741 operands into unsorted_regs and unsorted_offsets; additionally,
3742 order[0] has been set to the lowest numbered register in the
3743 list. Sort the registers into order, and check that the memory
3744 offsets are ascending and adjacent. */
3747 {
3757 /* Have we found a suitable register? if not, one must be used more
3758 than once. */
3762 /* Is the memory address adjacent and ascending? */
3765 }
3768 {
3775 }
3790 }
3796 {
3799 HOST_WIDE_INT offset;
3804 {
3823 }
3836 }
3838 int
3840 rtx op;
3842 {
3850 }
3851 \f
3852 /* Routines for use with attributes. */
3854 /* Return nonzero if ATTR is a valid attribute for DECL.
3855 ATTRIBUTES are any existing attributes and ARGS are
3856 the arguments supplied with ATTR.
3858 Supported attributes:
3860 naked:
3861 don't output any prologue or epilogue code, the user is assumed
3862 to do the right thing.
3864 interfacearm:
3865 Always assume that this function will be entered in ARM mode,
3866 not Thumb mode, and that the caller wishes to be returned to in
3867 ARM mode. */
3868 int
3870 tree decl;
3871 tree attr;
3872 tree args;
3873 {
3880 #ifdef ARM_PE
3886 }
3888 /* Return non-zero if FUNC is a naked function. */
3889 static int
3891 tree func;
3892 {
3893 tree a;
3900 }
3901 \f
3902 /* Routines for use in generating RTL. */
3903 rtx
3908 rtx from;
3914 {
3916 rtx result;
3918 rtx mem;
3920 /* XScale has load-store double instructions, but they have stricter
3921 alignment requirements than load-store multiple, so we can not
3922 use them.
3924 For XScale ldm requires 2 + NREGS cycles to complete and blocks
3925 the pipeline until completion.
3927 NREGS CYCLES
3928 1 3
3929 2 4
3930 3 5
3931 4 6
3933 An ldr instruction takes 1-3 cycles, but does not block the
3934 pipeline.
3936 NREGS CYCLES
3937 1 1-3
3938 2 2-6
3939 3 3-9
3940 4 4-12
3942 Best case ldr will always win. However, the more ldr instructions
3943 we issue, the less likely we are to be able to schedule them well.
3944 Using ldr instructions also increases code size.
3946 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
3947 for counts of 3 or 4 regs. */
3949 {
3950 rtx seq;
3955 {
3961 }
3970 }
3975 {
3980 count++;
3981 }
3984 {
3991 }
3994 }
3996 rtx
4001 rtx to;
4007 {
4009 rtx result;
4011 rtx mem;
4013 /* See arm_gen_load_multiple for discussion of
4014 the pros/cons of ldm/stm usage for XScale. */
4016 {
4017 rtx seq;
4022 {
4028 }
4037 }
4042 {
4047 count++;
4048 }
4051 {
4059 }
4062 }
4064 int
4067 {
4073 rtx mem;
4104 {
4107 src_unchanging_p,
4108 src_in_struct_p,
4109 src_scalar_p));
4110 else
4116 {
4119 dst_unchanging_p,
4120 dst_in_struct_p,
4121 dst_scalar_p));
4127 dst_unchanging_p,
4128 dst_in_struct_p,
4129 dst_scalar_p));
4130 else
4131 {
4139 }
4140 }
4144 }
4146 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
4148 {
4149 rtx sreg;
4164 in_words_to_go--;
4168 }
4171 {
4180 }
4186 {
4189 /* The bytes we want are in the top end of the word. */
4195 {
4203 {
4207 }
4208 }
4210 }
4211 else
4212 {
4214 {
4222 {
4228 }
4229 }
4232 {
4238 }
4239 }
4242 }
4244 /* Generate a memory reference for a half word, such that it will be loaded
4245 into the top 16 bits of the word. We can assume that the address is
4246 known to be alignable and of the form reg, or plus (reg, const). */
4247 rtx
4249 rtx memref;
4250 {
4255 {
4258 }
4260 /* If we aren't allowed to generate unaligned addresses, then fail. */
4271 }
4273 /* Select a dominance comparison mode if possible. We support three forms.
4274 COND_OR == 0 => (X && Y)
4275 COND_OR == 1 => ((! X( || Y)
4276 COND_OR == 2 => (X || Y)
4277 If we are unable to support a dominance comparsison we return CC mode.
4278 This will then fail to match for the RTL expressions that generate this
4279 call. */
4281 static enum machine_mode
4283 rtx x;
4284 rtx y;
4285 HOST_WIDE_INT cond_or;
4286 {
4290 /* Currently we will probably get the wrong result if the individual
4291 comparisons are not simple. This also ensures that it is safe to
4292 reverse a comparison if necessary. */
4299 /* The if_then_else variant of this tests the second condition if the
4300 first passes, but is true if the first fails. Reverse the first
4301 condition to get a true "inclusive-or" expression. */
4305 /* If the comparisons are not equal, and one doesn't dominate the other,
4306 then we can't do this. */
4313 {
4317 }
4320 {
4326 {
4332 }
4372 /* The remaining cases only occur when both comparisons are the
4373 same. */
4391 }
4394 }
4396 enum machine_mode
4399 rtx x;
4400 rtx y;
4401 {
4402 /* All floating point compares return CCFP if it is an equality
4403 comparison, and CCFPE otherwise. */
4405 {
4407 {
4428 }
4429 }
4431 /* A compare with a shifted operand. Because of canonicalization, the
4432 comparison will have to be swapped when we emit the assembler. */
4439 /* This is a special case that is used by combine to allow a
4440 comparison of a shifted byte load to be split into a zero-extend
4441 followed by a comparison of the shifted integer (only valid for
4442 equalities and unsigned inequalities). */
4454 /* A construct for a conditional compare, if the false arm contains
4455 0, then both conditions must be true, otherwise either condition
4456 must be true. Not all conditions are possible, so CCmode is
4457 returned if it can't be done. */
4466 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
4477 /* An operation that sets the condition codes as a side-effect, the
4478 V flag is not set correctly, so we can only use comparisons where
4479 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4480 instead. */
4502 }
4504 /* X and Y are two things to compare using CODE. Emit the compare insn and
4505 return the rtx for register 0 in the proper mode. FP means this is a
4506 floating point compare: I don't think that it is needed on the arm. */
4508 rtx
4512 {
4520 }
4522 void
4525 {
4531 {
4538 }
4541 {
4542 /* We have a pseudo which has been spilt onto the stack; there
4543 are two cases here: the first where there is a simple
4544 stack-slot replacement and a second where the stack-slot is
4545 out of range, or is used as a subreg. */
4547 {
4550 }
4551 else
4552 /* The slot is out of range, or was dressed up in a SUBREG. */
4554 }
4555 else
4558 /* Handle the case where the address is too complex to be offset by 1. */
4561 {
4566 }
4568 {
4569 /* The addend must be CONST_INT, or we would have dealt with it above. */
4575 /* Rework the address into a legal sequence of insns. */
4576 /* Valid range for lo is -4095 -> 4095 */
4581 /* Corner case, if lo is the max offset then we would be out of range
4582 once we have added the additional 1 below, so bump the msb into the
4583 pre-loading insn(s). */
4595 {
4598 /* Get the base address; addsi3 knows how to handle constants
4599 that require more than one insn. */
4603 }
4604 }
4610 offset))));
4618 gen_rtx_ASHIFT
4622 scratch)));
4623 else
4630 }
4632 /* Handle storing a half-word to memory during reload by synthesising as two
4633 byte stores. Take care not to clobber the input values until after we
4634 have moved them somewhere safe. This code assumes that if the DImode
4635 scratch in operands[2] overlaps either the input value or output address
4636 in some way, then that value must die in this insn (we absolutely need
4637 two scratch registers for some corner cases). */
4638 void
4641 {
4648 {
4655 }
4659 {
4660 /* We have a pseudo which has been spilt onto the stack; there
4661 are two cases here: the first where there is a simple
4662 stack-slot replacement and a second where the stack-slot is
4663 out of range, or is used as a subreg. */
4665 {
4668 }
4669 else
4670 /* The slot is out of range, or was dressed up in a SUBREG. */
4672 }
4673 else
4678 /* Handle the case where the address is too complex to be offset by 1. */
4681 {
4684 /* Be careful not to destroy OUTVAL. */
4686 {
4687 /* Updating base_plus might destroy outval, see if we can
4688 swap the scratch and base_plus. */
4690 {
4694 }
4695 else
4696 {
4699 /* Be conservative and copy OUTVAL into the scratch now,
4700 this should only be necessary if outval is a subreg
4701 of something larger than a word. */
4702 /* XXX Might this clobber base? I can't see how it can,
4703 since scratch is known to overlap with OUTVAL, and
4704 must be wider than a word. */
4707 }
4708 }
4712 }
4714 {
4715 /* The addend must be CONST_INT, or we would have dealt with it above. */
4721 /* Rework the address into a legal sequence of insns. */
4722 /* Valid range for lo is -4095 -> 4095 */
4727 /* Corner case, if lo is the max offset then we would be out of range
4728 once we have added the additional 1 below, so bump the msb into the
4729 pre-loading insn(s). */
4741 {
4744 /* Be careful not to destroy OUTVAL. */
4746 {
4747 /* Updating base_plus might destroy outval, see if we
4748 can swap the scratch and base_plus. */
4750 {
4754 }
4755 else
4756 {
4759 /* Be conservative and copy outval into scratch now,
4760 this should only be necessary if outval is a
4761 subreg of something larger than a word. */
4762 /* XXX Might this clobber base? I can't see how it
4763 can, since scratch is known to overlap with
4764 outval. */
4767 }
4768 }
4770 /* Get the base address; addsi3 knows how to handle constants
4771 that require more than one insn. */
4775 }
4776 }
4779 {
4788 }
4789 else
4790 {
4799 }
4800 }
4801 \f
4802 /* Print a symbolic form of X to the debug file, F. */
4803 static void
4806 rtx x;
4807 {
4809 {
4847 }
4848 }
4849 \f
4850 /* Routines for manipulation of the constant pool. */
4852 /* Arm instructions cannot load a large constant directly into a
4853 register; they have to come from a pc relative load. The constant
4854 must therefore be placed in the addressable range of the pc
4855 relative load. Depending on the precise pc relative load
4856 instruction the range is somewhere between 256 bytes and 4k. This
4857 means that we often have to dump a constant inside a function, and
4858 generate code to branch around it.
4860 It is important to minimize this, since the branches will slow
4861 things down and make the code larger.
4863 Normally we can hide the table after an existing unconditional
4864 branch so that there is no interruption of the flow, but in the
4865 worst case the code looks like this:
4867 ldr rn, L1
4868 ...
4869 b L2
4870 align
4871 L1: .long value
4872 L2:
4873 ...
4875 ldr rn, L3
4876 ...
4877 b L4
4878 align
4879 L3: .long value
4880 L4:
4881 ...
4883 We fix this by performing a scan after scheduling, which notices
4884 which instructions need to have their operands fetched from the
4885 constant table and builds the table.
4887 The algorithm starts by building a table of all the constants that
4888 need fixing up and all the natural barriers in the function (places
4889 where a constant table can be dropped without breaking the flow).
4890 For each fixup we note how far the pc-relative replacement will be
4891 able to reach and the offset of the instruction into the function.
4893 Having built the table we then group the fixes together to form
4894 tables that are as large as possible (subject to addressing
4895 constraints) and emit each table of constants after the last
4896 barrier that is within range of all the instructions in the group.
4897 If a group does not contain a barrier, then we forcibly create one
4898 by inserting a jump instruction into the flow. Once the table has
4899 been inserted, the insns are then modified to reference the
4900 relevant entry in the pool.
4902 Possible enhancements to the algorithm (not implemented) are:
4904 1) For some processors and object formats, there may be benefit in
4905 aligning the pools to the start of cache lines; this alignment
4906 would need to be taken into account when calculating addressability
4907 of a pool. */
4909 /* These typedefs are located at the start of this file, so that
4910 they can be used in the prototypes there. This comment is to
4911 remind readers of that fact so that the following structures
4912 can be understood more easily.
4914 typedef struct minipool_node Mnode;
4915 typedef struct minipool_fixup Mfix; */
4917 struct minipool_node
4918 {
4919 /* Doubly linked chain of entries. */
4922 /* The maximum offset into the code that this entry can be placed. While
4923 pushing fixes for forward references, all entries are sorted in order
4924 of increasing max_address. */
4925 HOST_WIDE_INT max_address;
4926 /* Similarly for a entry inserted for a backwards ref. */
4927 HOST_WIDE_INT min_address;
4928 /* The number of fixes referencing this entry. This can become zero
4929 if we "unpush" an entry. In this case we ignore the entry when we
4930 come to emit the code. */
4932 /* The offset from the start of the minipool. */
4933 HOST_WIDE_INT offset;
4934 /* The value in table. */
4935 rtx value;
4936 /* The mode of value. */
4939 };
4941 struct minipool_fixup
4942 {
4944 rtx insn;
4945 HOST_WIDE_INT address;
4949 rtx value;
4951 HOST_WIDE_INT forwards;
4952 HOST_WIDE_INT backwards;
4953 };
4955 /* Fixes less than a word need padding out to a word boundary. */
4956 #define MINIPOOL_FIX_SIZE(mode) \
4957 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
4963 /* The linked list of all minipool fixes required for this function. */
4966 /* The fix entry for the current minipool, once it has been placed. */
4969 /* Determines if INSN is the start of a jump table. Returns the end
4970 of the TABLE or NULL_RTX. */
4971 static rtx
4973 rtx insn;
4974 {
4975 rtx table;
4988 }
4990 static HOST_WIDE_INT
4992 rtx insn;
4993 {
4998 }
5000 /* Move a minipool fix MP from its current location to before MAX_MP.
5001 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5002 contrains may need updating. */
5007 HOST_WIDE_INT max_address;
5008 {
5009 /* This should never be true and the code below assumes these are
5010 different. */
5015 {
5018 }
5019 else
5020 {
5023 else
5026 /* Unlink MP from its current position. Since max_mp is non-null,
5027 mp->prev must be non-null. */
5031 else
5034 /* Re-insert it before MAX_MP. */
5041 else
5043 }
5045 /* Save the new entry. */
5048 /* Scan over the preceeding entries and adjust their addresses as
5049 required. */
5052 {
5055 }
5058 }
5060 /* Add a constant to the minipool for a forward reference. Returns the
5061 node added or NULL if the constant will not fit in this pool. */
5065 {
5066 /* If set, max_mp is the first pool_entry that has a lower
5067 constraint than the one we are trying to add. */
5072 /* If this fix's address is greater than the address of the first
5073 entry, then we can't put the fix in this pool. We subtract the
5074 size of the current fix to ensure that if the table is fully
5075 packed we still have enough room to insert this value by suffling
5076 the other fixes forwards. */
5081 /* Scan the pool to see if a constant with the same value has
5082 already been added. While we are doing this, also note the
5083 location where we must insert the constant if it doesn't already
5084 exist. */
5086 {
5093 {
5094 /* More than one fix references this entry. */
5097 }
5099 /* Note the insertion point if necessary. */
5103 }
5105 /* The value is not currently in the minipool, so we need to create
5106 a new entry for it. If MAX_MP is NULL, the entry will be put on
5107 the end of the list since the placement is less constrained than
5108 any existing entry. Otherwise, we insert the new fix before
5109 MAX_MP and, if neceesary, adjust the constraints on the other
5110 entries. */
5116 /* Not yet required for a backwards ref. */
5120 {
5126 {
5129 }
5130 else
5134 }
5135 else
5136 {
5139 else
5147 else
5149 }
5151 /* Save the new entry. */
5154 /* Scan over the preceeding entries and adjust their addresses as
5155 required. */
5158 {
5161 }
5164 }
5170 HOST_WIDE_INT min_address;
5171 {
5172 HOST_WIDE_INT offset;
5174 /* This should never be true, and the code below assumes these are
5175 different. */
5180 {
5183 }
5184 else
5185 {
5186 /* We will adjust this below if it is too loose. */
5189 /* Unlink MP from its current position. Since min_mp is non-null,
5190 mp->next must be non-null. */
5194 else
5197 /* Reinsert it after MIN_MP. */
5203 else
5205 }
5211 {
5218 }
5221 }
5223 /* Add a constant to the minipool for a backward reference. Returns the
5224 node added or NULL if the constant will not fit in this pool.
5226 Note that the code for insertion for a backwards reference can be
5227 somewhat confusing because the calculated offsets for each fix do
5228 not take into account the size of the pool (which is still under
5229 construction. */
5233 {
5234 /* If set, min_mp is the last pool_entry that has a lower constraint
5235 than the one we are trying to add. */
5237 /* This can be negative, since it is only a constraint. */
5241 /* If we can't reach the current pool from this insn, or if we can't
5242 insert this entry at the end of the pool without pushing other
5243 fixes out of range, then we don't try. This ensures that we
5244 can't fail later on. */
5250 /* Scan the pool to see if a constant with the same value has
5251 already been added. While we are doing this, also note the
5252 location where we must insert the constant if it doesn't already
5253 exist. */
5255 {
5262 /* Check that there is enough slack to move this entry to the
5263 end of the table (this is conservative). */
5268 {
5271 }
5275 else
5276 {
5277 /* Note the insertion point if necessary. */
5282 {
5283 /* Inserting before this entry would push the fix beyond
5284 its maximum address (which can happen if we have
5285 re-located a forwards fix); force the new fix to come
5286 after it. */
5289 }
5290 }
5291 }
5293 /* We need to create a new entry. */
5304 {
5309 {
5312 }
5313 else
5317 }
5318 else
5319 {
5326 else
5328 }
5330 /* Save the new entry. */
5335 else
5338 /* Scan over the following entries and adjust their offsets. */
5340 {
5346 else
5350 }
5353 }
5355 static void
5358 {
5365 {
5370 }
5371 }
5373 /* Output the literal table */
5374 static void
5376 rtx scan;
5377 {
5391 {
5393 {
5395 {
5402 }
5405 {
5406 #ifdef HAVE_consttable_1
5411 #endif
5412 #ifdef HAVE_consttable_2
5417 #endif
5418 #ifdef HAVE_consttable_4
5423 #endif
5424 #ifdef HAVE_consttable_8
5429 #endif
5433 }
5434 }
5438 }
5443 }
5445 /* Return the cost of forcibly inserting a barrier after INSN. */
5446 static int
5448 rtx insn;
5449 {
5450 /* Basing the location of the pool on the loop depth is preferable,
5451 but at the moment, the basic block information seems to be
5452 corrupt by this stage of the compilation. */
5460 {
5462 /* It will always be better to place the table before the label, rather
5463 than after it. */
5475 }
5476 }
5478 /* Find the best place in the insn stream in the range
5479 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5480 Create the barrier by inserting a jump and add a new fix entry for
5481 it. */
5485 HOST_WIDE_INT max_address;
5486 {
5488 rtx barrier;
5492 HOST_WIDE_INT selected_address;
5501 {
5502 rtx tmp;
5505 /* This code shouldn't have been called if there was a natural barrier
5506 within range. */
5510 /* Count the length of this insn. */
5513 /* If there is a jump table, add its length. */
5516 {
5519 /* Jump tables aren't in a basic block, so base the cost on
5520 the dispatch insn. If we select this location, we will
5521 still put the pool after the table. */
5525 {
5529 }
5531 /* Continue after the dispatch table. */
5534 }
5539 {
5543 }
5546 }
5548 /* Create a new JUMP_INSN that branches around a barrier. */
5554 /* Create a minipool barrier entry for the new barrier. */
5562 }
5564 /* Record that there is a natural barrier in the insn stream at
5565 ADDRESS. */
5566 static void
5568 rtx insn;
5569 HOST_WIDE_INT address;
5570 {
5579 else
5583 }
5585 /* Record INSN, which will need fixing up to load a value from the
5586 minipool. ADDRESS is the offset of the insn since the start of the
5587 function; LOC is a pointer to the part of the insn which requires
5588 fixing; VALUE is the constant that must be loaded, which is of type
5589 MODE. */
5590 static void
5592 rtx insn;
5593 HOST_WIDE_INT address;
5596 rtx value;
5597 {
5600 #ifdef AOF_ASSEMBLER
5601 /* PIC symbol refereneces need to be converted into offsets into the
5602 based area. */
5603 /* XXX This shouldn't be done here. */
5618 /* If an insn doesn't have a range defined for it, then it isn't
5619 expecting to be reworked by this code. Better to abort now than
5620 to generate duff assembly code. */
5625 {
5633 }
5635 /* Add it to the chain of fixes. */
5640 else
5644 }
5646 /* Scan INSN and note any of its operands that need fixing. */
5647 static void
5649 rtx insn;
5650 HOST_WIDE_INT address;
5651 {
5659 /* Fill in recog_op_alt with information about the constraints of this
5660 insn. */
5664 {
5665 /* Things we need to fix can only occur in inputs. */
5669 /* If this alternative is a memory reference, then any mention
5670 of constants in this alternative is really to fool reload
5671 into allowing us to accept one there. We need to fix them up
5672 now so that we output the right code. */
5674 {
5680 #if 0
5681 /* RWE: Now we look correctly at the operands for the insn,
5682 this shouldn't be needed any more. */
5683 #ifndef AOF_ASSEMBLER
5684 /* XXX Is this still needed? */
5689 #endif
5690 #endif
5697 }
5698 }
5699 }
5701 void
5703 rtx first;
5704 {
5705 rtx insn;
5711 /* The first insn must always be a note, or the code below won't
5712 scan it properly. */
5716 /* Scan all the insns and record the operands that will need fixing. */
5718 {
5723 {
5724 rtx table;
5729 /* If the insn is a vector jump, add the size of the table
5730 and skip the table. */
5732 {
5735 }
5736 }
5737 }
5741 /* Now scan the fixups and perform the required changes. */
5743 {
5750 /* Skip any further barriers before the next fix. */
5754 /* No more fixes. */
5761 {
5763 {
5768 }
5773 }
5775 /* If we found a barrier, drop back to that; any fixes that we
5776 could have reached but come after the barrier will now go in
5777 the next mini-pool. */
5779 {
5780 /* Reduce the refcount for those fixes that won't go into this
5781 pool after all. */
5785 {
5788 }
5791 }
5792 else
5793 {
5794 /* ftmp is first fix that we can't fit into this pool and
5795 there no natural barriers that we could use. Insert a
5796 new barrier in the code somewhere between the previous
5797 fix and this one, and arrange to jump around it. */
5798 HOST_WIDE_INT max_address;
5800 /* The last item on the list of fixes must be a barrier, so
5801 we can never run off the end of the list of fixes without
5802 last_barrier being set. */
5807 /* Check that there isn't another fix that is in range that
5808 we couldn't fit into this pool because the pool was
5809 already too large: we need to put the pool before such an
5810 instruction. */
5815 }
5820 {
5827 }
5829 /* Scan over the fixes we have identified for this pool, fixing them
5830 up and adding the constants to the pool itself. */
5834 {
5835 rtx addr
5837 minipool_vector_label),
5840 }
5844 }
5846 /* From now on we must synthesize any constants that we can't handle
5847 directly. This can happen if the RTL gets split during final
5848 instruction generation. */
5851 /* Free the minipool memory. */
5853 }
5854 \f
5855 /* Routines to output assembly language. */
5857 /* If the rtx is the correct value then return the string of the number.
5858 In this way we can ensure that valid double constants are generated even
5859 when cross compiling. */
5862 rtx x;
5863 {
5864 REAL_VALUE_TYPE r;
5876 }
5878 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
5882 {
5893 }
5895 /* Output the operands of a LDM/STM instruction to STREAM.
5896 MASK is the ARM register set mask of which only bits 0-15 are important.
5897 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
5898 must follow the register list. */
5900 static void
5907 {
5917 {
5923 }
5926 }
5928 /* Output a 'call' insn. */
5933 {
5934 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
5937 {
5940 }
5946 else
5950 }
5952 static int
5955 {
5963 {
5966 {
5969 }
5972 /* Scan through the sub-elements and change any references there. */
5983 }
5984 }
5986 /* Output a 'call' insn that is a reference in memory. */
5991 {
5993 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
5998 {
6002 }
6003 else
6004 {
6007 }
6010 }
6013 /* Output a move from arm registers to an fpu registers.
6014 OPERANDS[0] is an fpu register.
6015 OPERANDS[1] is the first registers of an arm register pair. */
6020 {
6035 }
6037 /* Output a move from an fpu register to arm registers.
6038 OPERANDS[0] is the first registers of an arm register pair.
6039 OPERANDS[1] is an fpu register. */
6044 {
6058 }
6060 /* Output a move from arm registers to arm registers of a long double
6061 OPERANDS[0] is the destination.
6062 OPERANDS[1] is the source. */
6066 {
6067 /* We have to be careful here because the two might overlap. */
6074 {
6076 {
6080 }
6081 }
6082 else
6083 {
6085 {
6089 }
6090 }
6093 }
6096 /* Output a move from arm registers to an fpu registers.
6097 OPERANDS[0] is an fpu register.
6098 OPERANDS[1] is the first registers of an arm register pair. */
6103 {
6115 }
6117 /* Output a move from an fpu register to arm registers.
6118 OPERANDS[0] is the first registers of an arm register pair.
6119 OPERANDS[1] is an fpu register. */
6124 {
6136 }
6138 /* Output a move between double words.
6139 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
6140 or MEM<-REG and all MEMs must be offsettable addresses. */
6145 {
6151 {
6157 {
6162 /* Ensure the second source is not overwritten. */
6165 else
6167 }
6169 {
6171 {
6179 }
6183 {
6187 }
6188 else
6189 {
6193 }
6197 }
6199 {
6200 #if HOST_BITS_PER_WIDE_INT > 32
6201 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
6202 what the upper word is. */
6204 {
6207 }
6208 else
6209 {
6212 }
6213 #else
6214 /* Sign extend the intval into the high-order word. */
6216 {
6220 }
6221 else
6223 #endif
6226 }
6228 {
6230 {
6260 {
6265 {
6267 {
6269 {
6279 }
6282 else
6284 }
6285 else
6287 }
6288 else
6292 }
6293 else
6294 {
6296 /* Take care of overlapping base/data reg. */
6298 {
6301 }
6302 else
6303 {
6306 }
6307 }
6308 }
6309 }
6310 else
6312 }
6314 {
6319 {
6342 {
6344 {
6356 }
6357 }
6358 /* Fall through */
6365 }
6366 }
6367 else
6371 }
6374 /* Output an arbitrary MOV reg, #n.
6375 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6380 {
6385 /* Try to use one MOV */
6387 {
6390 }
6392 /* Try to use one MVN */
6394 {
6398 }
6400 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6404 n_ones++;
6408 else
6412 }
6415 /* Output an ADD r, s, #n where n may be too big for one instruction. If
6416 adding zero to one register, output nothing. */
6421 {
6425 {
6430 else
6433 n);
6434 }
6437 }
6439 /* Output a multiple immediate operation.
6440 OPERANDS is the vector of operands referred to in the output patterns.
6441 INSTR1 is the output pattern to use for the first constant.
6442 INSTR2 is the output pattern to use for subsequent constants.
6443 IMMED_OP is the index of the constant slot in OPERANDS.
6444 N is the constant value. */
6452 HOST_WIDE_INT n;
6453 {
6454 #if HOST_BITS_PER_WIDE_INT > 32
6456 #endif
6459 {
6462 }
6463 else
6464 {
6468 /* Note that n is never zero here (which would give no output). */
6470 {
6472 {
6477 }
6478 }
6479 }
6482 }
6485 /* Return the appropriate ARM instruction for the operation code.
6486 The returned result should not be overwritten. OP is the rtx of the
6487 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6488 was shifted. */
6492 rtx op;
6494 {
6496 {
6514 }
6515 }
6518 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6519 for the operation code. The returned result should not be overwritten.
6520 OP is the rtx code of the shift.
6521 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6522 shift. */
6526 rtx op;
6528 {
6536 else
6540 {
6558 /* We never have to worry about the amount being other than a
6559 power of 2, since this case can never be reloaded from a reg. */
6562 else
6568 }
6571 {
6572 /* This is not 100% correct, but follows from the desire to merge
6573 multiplication by a power of 2 with the recognizer for a
6574 shift. >=32 is not a valid shift for "asl", so we must try and
6575 output a shift that produces the correct arithmetical result.
6576 Using lsr #32 is identical except for the fact that the carry bit
6577 is not set correctly if we set the flags; but we never use the
6578 carry bit from such an operation, so we can ignore that. */
6582 {
6586 }
6588 /* Shifts of 0 are no-ops. */
6591 }
6594 }
6597 /* Obtain the shift from the POWER of two. */
6598 static HOST_WIDE_INT
6600 HOST_WIDE_INT power;
6601 {
6605 {
6608 shift++;
6609 }
6612 }
6614 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
6615 /bin/as is horribly restrictive. */
6616 #define MAX_ASCII_LEN 51
6618 void
6623 {
6630 {
6634 {
6637 }
6640 {
6666 /* This is a good place for a line break. */
6668 else
6675 len_so_far++;
6676 /* drop through. */
6680 {
6682 len_so_far++;
6683 }
6684 else
6685 {
6688 }
6690 }
6691 }
6694 }
6695 \f
6699 rtx operand;
6702 {
6707 /* If a function is naked, don't use the "return" insn. */
6714 {
6715 /* If this function was declared non-returning, and we have found a tail
6716 call, then we have to trust that the called function won't return. */
6718 {
6721 /* Otherwise, trap an attempted return by aborting. */
6727 }
6730 }
6737 live_regs++;
6740 && !frame_pointer_needed
6743 live_regs++;
6747 live_regs++;
6750 live_regs++;
6755 /* On some ARM architectures it is faster to use LDR rather than LDM to
6756 load a single register. On other architectures, the cost is the same. */
6768 {
6770 live_regs++;
6775 else
6784 {
6789 }
6792 {
6802 }
6803 else
6804 {
6808 {
6812 }
6818 else
6820 }
6826 {
6833 }
6834 }
6836 {
6839 else
6844 }
6847 }
6849 /* Return nonzero if optimizing and the current function is volatile.
6850 Such functions never return, and many memory cycles can be saved
6851 by not storing register values that will never be needed again.
6852 This optimization was added to speed up context switching in a
6853 kernel application. */
6854 int
6856 {
6858 && current_function_nothrow
6860 }
6862 /* Write the function name into the code section, directly preceding
6863 the function prologue.
6865 Code will be output similar to this:
6866 t0
6867 .ascii "arm_poke_function_name", 0
6868 .align
6869 t1
6870 .word 0xff000000 + (t1 - t0)
6871 arm_poke_function_name
6872 mov ip, sp
6873 stmfd sp!, {fp, ip, lr, pc}
6874 sub fp, ip, #4
6876 When performing a stack backtrace, code can inspect the value
6877 of 'pc' stored at 'fp' + 0. If the trace function then looks
6878 at location pc - 12 and the top 8 bits are set, then we know
6879 that there is a function name embedded immediately preceding this
6880 location and has length ((pc[-3]) & 0xff000000).
6882 We assume that pc is declared as a pointer to an unsigned long.
6884 It is of no benefit to output the function name if we are assembling
6885 a leaf function. These function types will not contain a stack
6886 backtrace structure, therefore it is not possible to determine the
6887 function name. */
6889 void
6893 {
6896 rtx x;
6905 }
6907 /* The amount of stack adjustment that happens here, in output_return and in
6908 output_epilogue must be exactly the same as was calculated during reload,
6909 or things will point to the wrong place. The only time we can safely
6910 ignore this constraint is when a function has no arguments on the stack,
6911 no stack frame requirement and no live registers execpt for `lr'. If we
6912 can guarantee that by making all function calls into tail calls and that
6913 lr is not clobbered in any other way, then there is no need to push lr
6914 onto the stack. */
6915 void
6919 {
6923 /* Nonzero if we must stuff some register arguments onto the stack as if
6924 they were passed there. */
6936 current_function_args_size,
6939 frame_pointer_needed,
6940 current_function_anonymous_args);
6956 && !frame_pointer_needed
6968 {
6970 }
6973 /* If a di mode load/store multiple is used, and the base register
6974 is r3, then r4 can become an ever live register without lr
6975 doing so, in this case we need to push lr as well, or we
6976 will fail to get a proper return. */
6979 #ifdef AOF_ASSEMBLER
6982 #endif
6983 }
6988 {
6991 /* If we need this, then it will always be at least this much. */
7003 /* Naked functions don't have epilogues. */
7007 /* If we are throwing an exception, the address we want to jump to is in
7008 R1; otherwise, it's in LR. */
7011 /* If we are throwing an exception, then we really must be doing a return,
7012 so we can't tail-call. */
7016 /* A volatile function should never return. Call abort. */
7018 {
7019 rtx op;
7024 }
7028 {
7031 }
7033 /* Handle the frame pointer as a special case. */
7035 && !frame_pointer_needed
7038 {
7041 }
7043 /* If we aren't loading the PIC register, don't stack it even though it may
7044 be live. */
7047 {
7050 }
7053 {
7055 {
7058 {
7062 }
7063 }
7064 else
7065 {
7069 {
7071 {
7074 /* We can't unstack more than four registers at once. */
7076 {
7080 }
7081 }
7082 else
7083 {
7089 }
7090 }
7092 /* Just in case the last register checked also needs unstacking. */
7097 }
7100 {
7108 }
7110 {
7114 {
7117 /* Even in 26-bit mode we do a mov (rather than a movs)
7118 because we don't have the PSR bits set in the
7119 address. */
7121 }
7122 }
7123 else
7124 {
7128 }
7129 }
7130 else
7131 {
7132 /* Restore stack pointer if necessary. */
7134 {
7139 }
7142 {
7147 }
7148 else
7149 {
7153 {
7155 {
7157 {
7161 }
7162 }
7163 else
7164 {
7168 SP_REGNUM);
7171 }
7172 }
7174 /* Just in case the last register checked also needs unstacking. */
7178 }
7181 {
7183 {
7186 /* Handle LR on its own. */
7188 {
7191 SP_REGNUM);
7192 else
7194 SP_REGNUM);
7195 }
7198 FALSE);
7206 }
7208 {
7211 else
7217 /* Jump to the target; even in 26-bit mode. */
7219 }
7227 else
7231 }
7232 else
7233 {
7235 {
7236 /* Restore the integer regs, and the return address into lr. */
7240 {
7243 SP_REGNUM);
7244 else
7246 SP_REGNUM);
7247 }
7250 FALSE);
7251 }
7254 {
7255 /* Unwind the pre-pushed regs. */
7259 }
7266 {
7267 /* And finally, go home. */
7272 else
7274 }
7275 }
7276 }
7279 }
7281 void
7284 {
7286 {
7287 /* ??? Probably not safe to set this here, since it assumes that a
7288 function will be emitted as assembly immediately after we generate
7289 RTL for it. This does not happen for inline functions. */
7291 }
7292 else
7293 {
7295 && return_used_this_function
7300 /* Reset the ARM-specific per-function variables. */
7303 }
7304 }
7306 /* Generate and emit an insn that we will recognize as a push_multi.
7307 Unfortunately, since this insn does not reflect very well the actual
7308 semantics of the operation, we need to annotate the insn for the benefit
7309 of DWARF2 frame unwind information. */
7310 static rtx
7313 {
7316 rtx par;
7317 rtx dwarf;
7323 num_regs++;
7328 /* For the body of the insn we are going to generate an UNSPEC in
7329 parallel with several USEs. This allows the insn to be recognised
7330 by the push_multi pattern in the arm.md file. The insn looks
7331 something like this:
7333 (parallel [
7334 (set (mem:BLK (pre_dec:BLK (reg:SI sp))) (unspec:BLK [(reg:SI r4)] 2))
7335 (use (reg:SI 11 fp))
7336 (use (reg:SI 12 ip))
7337 (use (reg:SI 14 lr))
7338 (use (reg:SI 15 pc))
7339 ])
7341 For the frame note however, we try to be more explicit and actually
7342 show each register being stored into the stack frame, plus a (single)
7343 decrement of the stack pointer. We do it this way in order to be
7344 friendly to the stack unwinding code, which only wants to see a single
7345 stack decrement per instruction. The RTL we generate for the note looks
7346 something like this:
7348 (sequence [
7349 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
7350 (set (mem:SI (reg:SI sp)) (reg:SI r4))
7351 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
7352 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
7353 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
7354 (set (mem:SI (plus:SI (reg:SI sp) (const_int 16))) (reg:SI pc))
7355 ])
7357 This sequence is used both by the code to support stack unwinding for
7358 exceptions handlers and the code to generate dwarf2 frame debugging. */
7366 {
7368 {
7375 stack_pointer_rtx)),
7382 reg);
7385 dwarf_par_index ++;
7388 }
7389 }
7392 {
7394 {
7402 stack_pointer_rtx,
7404 reg);
7408 j++;
7409 }
7410 }
7415 stack_pointer_rtx,
7417 stack_pointer_rtx,
7425 }
7427 static rtx
7431 {
7432 rtx par;
7433 rtx dwarf;
7450 tmp
7454 reg);
7459 {
7466 stack_pointer_rtx)),
7467 reg);
7470 }
7476 }
7478 void
7480 {
7486 /* If this function doesn't return, then there is no need to push
7487 the call-saved regs. */
7489 rtx insn;
7490 rtx ip_rtx;
7494 /* Naked functions don't have prologues. */
7502 {
7508 && !frame_pointer_needed
7518 }
7523 {
7525 {
7526 /* The Static chain register is the same as the IP register
7527 used as a scratch register during stack frame creation.
7528 To get around this need to find somewhere to store IP
7529 whilst the frame is being created. We try the following
7530 places in order:
7532 1. An unused argument register.
7533 2. A slot on the stack above the frame. (This only
7534 works if the function is not a varargs function).
7536 If neither of these places is available, we abort (for now). */
7538 {
7543 }
7545 {
7552 }
7553 else
7554 /* FIXME - the way to handle this situation is to allow
7555 the pretend args to be dumped onto the stack, then
7556 reuse r3 to save IP. This would involve moving the
7557 copying os SP into IP until after the pretend args
7558 have been dumped, but this is not too hard. */
7560 }
7565 {
7568 }
7569 else
7574 }
7577 {
7579 insn = emit_multi_reg_push
7581 else
7582 insn = emit_insn
7586 }
7589 {
7590 /* If we have to push any regs, then we must push lr as well, or
7591 we won't get a proper return. */
7595 }
7597 /* For now the integer regs are still pushed in output_arm_epilogue (). */
7600 {
7602 {
7605 {
7611 }
7612 }
7613 else
7614 {
7618 {
7620 {
7622 {
7626 }
7627 }
7628 else
7629 {
7631 {
7634 }
7636 }
7637 }
7640 {
7643 }
7644 }
7645 }
7648 {
7654 {
7655 /* Recover the static chain register. */
7657 {
7662 }
7664 {
7670 }
7671 }
7672 }
7675 {
7677 amount));
7680 /* If the frame pointer is needed, emit a special barrier that
7681 will prevent the scheduler from moving stores to the frame
7682 before the stack adjustment. */
7684 {
7691 }
7692 }
7694 /* If we are profiling, make sure no instructions are scheduled before
7695 the call to mcount. Similarly if the user has requested no
7696 scheduling in the prolog. */
7699 }
7700 \f
7701 /* If CODE is 'd', then the X is a condition operand and the instruction
7702 should only be executed if the condition is true.
7703 if CODE is 'D', then the X is a condition operand and the instruction
7704 should only be executed if the condition is false: however, if the mode
7705 of the comparison is CCFPEmode, then always execute the instruction -- we
7706 do this because in these circumstances !GE does not necessarily imply LT;
7707 in these cases the instruction pattern will take care to make sure that
7708 an instruction containing %d will follow, thereby undoing the effects of
7709 doing this instruction unconditionally.
7710 If CODE is 'N' then X is a floating point operand that must be negated
7711 before output.
7712 If CODE is 'B' then output a bitwise inverted value of X (a const int).
7713 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
7715 void
7718 rtx x;
7720 {
7722 {
7737 {
7742 }
7744 {
7752 }
7756 {
7757 REAL_VALUE_TYPE r;
7761 }
7766 {
7767 HOST_WIDE_INT val;
7770 }
7771 else
7772 {
7775 }
7787 {
7788 HOST_WIDE_INT val;
7792 {
7796 else
7797 {
7800 }
7801 }
7802 }
7805 /* An explanation of the 'Q', 'R' and 'H' register operands:
7807 In a pair of registers containing a DI or DF value the 'Q'
7808 operand returns the register number of the register containing
7809 the least signficant part of the value. The 'R' operand returns
7810 the register number of the register containing the most
7811 significant part of the value.
7813 The 'H' operand returns the higher of the two register numbers.
7814 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
7815 same as the 'Q' operand, since the most signficant part of the
7816 value is held in the lower number register. The reverse is true
7817 on systems where WORDS_BIG_ENDIAN is false.
7819 The purpose of these operands is to distinguish between cases
7820 where the endian-ness of the values is important (for example
7821 when they are added together), and cases where the endian-ness
7822 is irrelevant, but the order of register operations is important.
7823 For example when loading a value from memory into a register
7824 pair, the endian-ness does not matter. Provided that the value
7825 from the lower memory address is put into the lower numbered
7826 register, and the value from the higher address is put into the
7827 higher numbered register, the load will work regardless of whether
7828 the value being loaded is big-wordian or little-wordian. The
7829 order of the two register loads can matter however, if the address
7830 of the memory location is actually held in one of the registers
7831 being overwritten by the load. */
7868 stream);
7869 else
7880 stream);
7881 else
7892 {
7895 }
7900 else
7901 {
7904 }
7905 }
7906 }
7907 \f
7908 /* A finite state machine takes care of noticing whether or not instructions
7909 can be conditionally executed, and thus decrease execution time and code
7910 size by deleting branch instructions. The fsm is controlled by
7911 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
7913 /* The state of the fsm controlling condition codes are:
7914 0: normal, do nothing special
7915 1: make ASM_OUTPUT_OPCODE not output this instruction
7916 2: make ASM_OUTPUT_OPCODE not output this instruction
7917 3: make instructions conditional
7918 4: make instructions conditional
7920 State transitions (state->state by whom under condition):
7921 0 -> 1 final_prescan_insn if the `target' is a label
7922 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
7923 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
7924 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
7925 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
7926 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
7927 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
7928 (the target insn is arm_target_insn).
7930 If the jump clobbers the conditions then we use states 2 and 4.
7932 A similar thing can be done with conditional return insns.
7934 XXX In case the `target' is an unconditional branch, this conditionalising
7935 of the instructions always reduces code size, but not always execution
7936 time. But then, I want to reduce the code size to somewhere near what
7937 /bin/cc produces. */
7939 /* Returns the index of the ARM condition code string in
7940 `arm_condition_codes'. COMPARISON should be an rtx like
7941 `(eq (...) (...))'. */
7943 static enum arm_cond_code
7945 rtx comparison;
7946 {
7956 {
7968 dominance:
7978 {
7984 }
7988 {
7992 }
7996 /* These encodings assume that AC=1 in the FPA system control
7997 byte. This allows us to handle all cases except UNEQ and
7998 LTGT. */
8000 {
8013 /* UNEQ and LTGT do not have a representation. */
8017 }
8021 {
8033 }
8037 {
8041 }
8045 {
8057 }
8060 }
8063 }
8066 void
8068 rtx insn;
8069 {
8070 /* BODY will hold the body of INSN. */
8073 /* This will be 1 if trying to repeat the trick, and things need to be
8074 reversed if it appears to fail. */
8077 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
8078 taken are clobbered, even if the rtl suggests otherwise. It also
8079 means that we have to grub around within the jump expression to find
8080 out what the conditions are when the jump isn't taken. */
8083 /* If we start with a return insn, we only succeed if we find another one. */
8086 /* START_INSN will hold the insn from where we start looking. This is the
8087 first insn after the following code_label if REVERSE is true. */
8090 /* If in state 4, check if the target branch is reached, in order to
8091 change back to state 0. */
8093 {
8095 {
8098 }
8100 }
8102 /* If in state 3, it is possible to repeat the trick, if this insn is an
8103 unconditional branch to a label, and immediately following this branch
8104 is the previous target label which is only used once, and the label this
8105 branch jumps to is not too far off. */
8107 {
8109 {
8112 {
8113 /* XXX Isn't this always a barrier? */
8115 }
8120 else
8122 }
8124 {
8131 {
8134 }
8135 else
8137 }
8138 else
8140 }
8147 /* This jump might be paralleled with a clobber of the condition codes
8148 the jump should always come first */
8152 #if 0
8153 /* If this is a conditional return then we don't want to know */
8159 #endif
8164 {
8167 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
8171 /* If the jump cannot be done with one instruction, we cannot
8172 conditionally execute the instruction in the inverse case. */
8174 {
8177 }
8179 /* Register the insn jumped to. */
8181 {
8184 }
8188 {
8191 }
8195 {
8198 }
8199 else
8202 /* See how many insns this branch skips, and what kind of insns. If all
8203 insns are okay, and the label or unconditional branch to the same
8204 label is not too far away, succeed. */
8207 {
8208 rtx scanbody;
8215 {
8217 /* Succeed if it is the target label, otherwise fail since
8218 control falls in from somewhere else. */
8220 {
8222 {
8225 }
8226 else
8229 }
8230 else
8235 /* Succeed if the following insn is the target label.
8236 Otherwise fail.
8237 If return insns are used then the last insn in a function
8238 will be a barrier. */
8241 {
8243 {
8246 }
8247 else
8250 }
8251 else
8256 /* If using 32-bit addresses the cc is not preserved over
8257 calls. */
8259 {
8260 /* Succeed if the following insn is the target label,
8261 or if the following two insns are a barrier and
8262 the target label. */
8269 {
8271 {
8274 }
8275 else
8278 }
8279 else
8281 }
8285 /* If this is an unconditional branch to the same label, succeed.
8286 If it is to another label, do nothing. If it is conditional,
8287 fail. */
8288 /* XXX Probably, the tests for SET and the PC are unnecessary. */
8293 {
8296 {
8299 }
8302 }
8303 /* Fail if a conditional return is undesirable (eg on a
8304 StrongARM), but still allow this if optimizing for size. */
8311 {
8314 }
8316 {
8318 {
8324 }
8325 }
8326 else
8332 /* Instructions using or affecting the condition codes make it
8333 fail. */
8343 }
8344 }
8346 {
8350 {
8352 {
8357 }
8359 {
8360 /* Oh, dear! we ran off the end.. give up */
8365 }
8367 }
8368 else
8371 {
8374 arm_current_cc =
8381 }
8382 else
8383 {
8384 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
8385 what it was. */
8389 }
8393 }
8395 /* Restore recog_data (getting the attributes of other insns can
8396 destroy this array, but final.c assumes that it remains intact
8397 across this call; since the insn has been recognized already we
8398 call recog direct). */
8400 }
8401 }
8403 int
8406 {
8408 {
8416 }
8427 }
8429 /* Handle a special case when computing the offset
8430 of an argument from the frame pointer. */
8431 int
8434 rtx addr;
8435 {
8436 rtx insn;
8438 /* We are only interested if dbxout_parms() failed to compute the offset. */
8442 /* We can only cope with the case where the address is held in a register. */
8446 /* If we are using the frame pointer to point at the argument, then
8447 an offset of 0 is correct. */
8451 /* If we are using the stack pointer to point at the
8452 argument, then an offset of 0 is correct. */
8457 /* Oh dear. The argument is pointed to by a register rather
8458 than being held in a register, or being stored at a known
8459 offset from the frame pointer. Since GDB only understands
8460 those two kinds of argument we must translate the address
8461 held in the register into an offset from the frame pointer.
8462 We do this by searching through the insns for the function
8463 looking to see where this register gets its value. If the
8464 register is initialised from the frame pointer plus an offset
8465 then we are in luck and we can continue, otherwise we give up.
8467 This code is exercised by producing debugging information
8468 for a function with arguments like this:
8470 double func (double a, double b, int c, double d) {return d;}
8472 Without this code the stab for parameter 'd' will be set to
8473 an offset of 0 from the frame pointer, rather than 8. */
8475 /* The if() statement says:
8477 If the insn is a normal instruction
8478 and if the insn is setting the value in a register
8479 and if the register being set is the register holding the address of the argument
8480 and if the address is computing by an addition
8481 that involves adding to a register
8482 which is the frame pointer
8483 a constant integer
8485 then... */
8488 {
8496 )
8497 {
8501 }
8502 }
8505 {
8509 }
8512 }
8514 #define def_builtin(NAME, TYPE, CODE) \
8515 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL_PTR)
8517 void
8519 {
8526 /* void func (void *) */
8527 void_ftype_pchar
8531 /* int func (int) */
8532 int_ftype_int
8535 /* Initialize arm V5 builtins. */
8537 {
8540 ARM_BUILTIN_PREFETCH);
8541 }
8542 }
8544 /* Expand an expression EXP that calls a built-in function,
8545 with result going to TARGET if that's convenient
8546 (and in mode MODE if that's convenient).
8547 SUBTARGET may be used as the target for computing one of EXP's operands.
8548 IGNORE is nonzero if the value is to be ignored. */
8550 rtx
8552 tree exp;
8553 rtx target;
8554 rtx subtarget ATTRIBUTE_UNUSED;
8557 {
8561 tree arg0;
8567 {
8602 }
8604 /* @@@ Should really do something sensible here. */
8606 }
8607 \f
8608 /* Recursively search through all of the blocks in a function
8609 checking to see if any of the variables created in that
8610 function match the RTX called 'orig'. If they do then
8611 replace them with the RTX called 'new'. */
8613 static void
8615 tree block;
8616 rtx orig;
8618 {
8620 {
8621 tree sym;
8627 {
8633 )
8637 }
8640 }
8641 }
8643 /* Return the number (counting from 0) of the least significant set
8644 bit in MASK. */
8645 #ifdef __GNUC__
8646 inline
8647 #endif
8648 static int
8651 {
8660 }
8662 /* Generate code to return from a thumb function.
8663 If 'reg_containing_return_addr' is -1, then the return address is
8664 actually on the stack, at the stack pointer. */
8665 static void
8669 rtx eh_ofs;
8670 {
8680 /* Compute the registers we need to pop. */
8684 /* There is an assumption here, that if eh_ofs is not NULL, the
8685 normal return address will have been pushed. */
8687 {
8688 /* When we are generating a return for __builtin_eh_return,
8689 reg_containing_return_addr must specify the return regno. */
8695 }
8698 {
8699 /* Restore the (ARM) frame pointer and stack pointer. */
8702 }
8704 /* If there is nothing to pop then just emit the BX instruction and
8705 return. */
8707 {
8713 }
8714 /* Otherwise if we are not supporting interworking and we have not created
8715 a backtrace structure and the function was not entered in ARM mode then
8716 just pop the return address straight into the PC. */
8718 && !TARGET_BACKTRACE
8720 {
8722 {
8726 }
8727 else
8731 }
8733 /* Find out how many of the (return) argument registers we can corrupt. */
8736 /* If returning via __builtin_eh_return, the bottom three registers
8737 all contain information needed for the return. */
8740 else
8741 {
8742 #ifdef RTX_CODE
8743 /* If we can deduce the registers used from the function's
8744 return value. This is more reliable that examining
8745 regs_ever_live[] because that will be set if the register is
8746 ever used in the function, not just if the register is used
8747 to hold a return value. */
8751 else
8752 #endif
8758 {
8759 /* In a void function we can use any argument register.
8760 In a function that returns a structure on the stack
8761 we can use the second and third argument registers. */
8763 regs_available_for_popping =
8767 else
8768 regs_available_for_popping =
8771 }
8773 regs_available_for_popping =
8777 regs_available_for_popping =
8779 }
8781 /* Match registers to be popped with registers into which we pop them. */
8789 /* If we have any popping registers left over, remove them. */
8793 /* Otherwise if we need another popping register we can use
8794 the fourth argument register. */
8796 {
8797 /* If we have not found any free argument registers and
8798 reg a4 contains the return address, we must move it. */
8801 {
8804 }
8806 {
8807 /* Register a4 is being used to hold part of the return value,
8808 but we have dire need of a free, low register. */
8812 }
8815 {
8816 /* The fourth argument register is available. */
8820 }
8821 }
8823 /* Pop as many registers as we can. */
8826 /* Process the registers we popped. */
8828 {
8829 /* The return address was popped into the lowest numbered register. */
8832 reg_containing_return_addr =
8835 /* Remove this register for the mask of available registers, so that
8836 the return address will not be corrupted by futher pops. */
8838 }
8840 /* If we popped other registers then handle them here. */
8842 {
8845 /* Work out which register currently contains the frame pointer. */
8848 /* Move it into the correct place. */
8852 /* (Temporarily) remove it from the mask of popped registers. */
8857 {
8860 /* We popped the stack pointer as well,
8861 find the register that contains it. */
8864 /* Move it into the stack register. */
8867 /* At this point we have popped all necessary registers, so
8868 do not worry about restoring regs_available_for_popping
8869 to its correct value:
8871 assert (pops_needed == 0)
8872 assert (regs_available_for_popping == (1 << frame_pointer))
8873 assert (regs_to_pop == (1 << STACK_POINTER)) */
8874 }
8875 else
8876 {
8877 /* Since we have just move the popped value into the frame
8878 pointer, the popping register is available for reuse, and
8879 we know that we still have the stack pointer left to pop. */
8881 }
8882 }
8884 /* If we still have registers left on the stack, but we no longer have
8885 any registers into which we can pop them, then we must move the return
8886 address into the link register and make available the register that
8887 contained it. */
8889 {
8893 reg_containing_return_addr);
8896 }
8898 /* If we have registers left on the stack then pop some more.
8899 We know that at most we will want to pop FP and SP. */
8901 {
8907 /* We have popped either FP or SP.
8908 Move whichever one it is into the correct register. */
8917 }
8919 /* If we still have not popped everything then we must have only
8920 had one register available to us and we are now popping the SP. */
8922 {
8930 /*
8931 assert (regs_to_pop == (1 << STACK_POINTER))
8932 assert (pops_needed == 1)
8933 */
8934 }
8936 /* If necessary restore the a4 register. */
8938 {
8940 {
8943 }
8946 }
8951 /* Return to caller. */
8953 }
8955 /* Emit code to push or pop registers to or from the stack. */
8956 static void
8961 {
8966 {
8967 /* Special case. Do not generate a POP PC statement here, do it in
8968 thumb_exit() */
8971 }
8975 /* Look at the low registers first. */
8977 {
8979 {
8984 }
8985 }
8988 {
8989 /* Catch pushing the LR. */
8994 }
8996 {
8997 /* Catch popping the PC. */
8999 {
9000 /* The PC is never poped directly, instead
9001 it is popped into r3 and then BX is used. */
9007 }
9008 else
9009 {
9014 }
9015 }
9018 }
9019 \f
9020 void
9022 rtx insn;
9023 {
9027 }
9029 int
9032 {
9044 }
9046 /* Returns non-zero if the current function contains,
9047 or might contain a far jump. */
9048 int
9050 {
9051 rtx insn;
9053 /* This test is only important for leaf functions. */
9054 /* assert (!leaf_function_p ()); */
9056 /* If we have already decided that far jumps may be used,
9057 do not bother checking again, and always return true even if
9058 it turns out that they are not being used. Once we have made
9059 the decision that far jumps are present (and that hence the link
9060 register will be pushed onto the stack) we cannot go back on it. */
9064 /* If this function is not being called from the prologue/epilogue
9065 generation code then it must be being called from the
9066 INITIAL_ELIMINATION_OFFSET macro. */
9068 {
9069 /* In this case we know that we are being asked about the elimination
9070 of the arg pointer register. If that register is not being used,
9071 then there are no arguments on the stack, and we do not have to
9072 worry that a far jump might force the prologue to push the link
9073 register, changing the stack offsets. In this case we can just
9074 return false, since the presence of far jumps in the function will
9075 not affect stack offsets.
9077 If the arg pointer is live (or if it was live, but has now been
9078 eliminated and so set to dead) then we do have to test to see if
9079 the function might contain a far jump. This test can lead to some
9080 false negatives, since before reload is completed, then length of
9081 branch instructions is not known, so gcc defaults to returning their
9082 longest length, which in turn sets the far jump attribute to true.
9084 A false negative will not result in bad code being generated, but it
9085 will result in a needless push and pop of the link register. We
9086 hope that this does not occur too often. */
9091 }
9093 /* Check to see if the function contains a branch
9094 insn with the far jump attribute set. */
9096 {
9098 /* Ignore tablejump patterns. */
9102 )
9103 {
9104 /* Record the fact that we have decied that
9105 the function does use far jumps. */
9108 }
9109 }
9112 }
9114 /* Return non-zero if FUNC must be entered in ARM mode. */
9115 int
9117 tree func;
9118 {
9122 /* Ignore the problem about functions whoes address is taken. */
9126 #ifdef ARM_PE
9128 #else
9130 #endif
9131 }
9133 /* The bits which aren't usefully expanded as rtl. */
9136 {
9153 {
9156 high_regs_pushed++;
9157 }
9159 /* The prolog may have pushed some high registers to use as
9160 work registers. eg the testuite file:
9161 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
9162 compiles to produce:
9163 push {r4, r5, r6, r7, lr}
9164 mov r7, r9
9165 mov r6, r8
9166 push {r6, r7}
9167 as part of the prolog. We have to undo that pushing here. */
9170 {
9176 #ifdef RTX_CODE
9177 /* If we can deduce the registers used from the function's return value.
9178 This is more reliable that examining regs_ever_live[] because that
9179 will be set if the register is ever used in the function, not just if
9180 the register is used to hold a return value. */
9184 else
9185 #endif
9190 /* Unless we are returning a type of size > 12 register r3 is
9191 available. */
9196 /* Oh dear! We have no low registers into which we can pop
9197 high registers! */
9206 {
9207 /* Find lo register(s) into which the high register(s) can
9208 be popped. */
9210 {
9212 high_regs_pushed--;
9215 }
9219 /* Pop the values into the low register(s). */
9222 /* Move the value(s) into the high registers. */
9224 {
9226 {
9228 regno);
9233 && !(TARGET_SINGLE_PIC_BASE
9236 }
9237 }
9238 }
9239 }
9247 {
9248 /* The stack backtrace structure creation code had to
9249 push R7 in order to get a work register, so we pop
9250 it now. */
9252 }
9255 {
9261 /* Either no argument registers were pushed or a backtrace
9262 structure was created which includes an adjusted stack
9263 pointer, so just pop everything. */
9269 /* We have either just popped the return address into the
9270 PC or it is was kept in LR for the entire function or
9271 it is still on the stack because we do not want to
9272 return by doing a pop {pc}. */
9275 (had_to_push_lr
9278 }
9279 else
9280 {
9281 /* Pop everything but the return address. */
9288 /* Get the return address into a temporary register. */
9291 /* Remove the argument registers that were pushed onto the stack. */
9294 current_function_pretend_args_size);
9298 else
9301 }
9304 }
9306 /* Functions to save and restore machine-specific function data. */
9308 static void
9311 {
9316 }
9318 static void
9321 {
9324 }
9326 /* Return an RTX indicating where the return address to the
9327 calling function can be found. */
9328 rtx
9331 rtx frame ATTRIBUTE_UNUSED;
9332 {
9333 rtx reg;
9341 {
9342 rtx init;
9344 /* No rtx yet. Invent one, and initialize it for r14 (lr) in
9345 the prologue. */
9352 else
9357 /* Emit the insn to the prologue with the other argument copies. */
9361 }
9364 }
9366 /* Do anything needed before RTL is emitted for each function. */
9367 void
9369 {
9370 /* Arrange to initialize and mark the machine per-function status. */
9373 }
9375 /* Generate the rest of a function's prologue. */
9376 void
9378 {
9382 /* Naked functions don't have prologues. */
9390 {
9396 else
9397 {
9399 rtx reg;
9401 /* The stack decrement is too big for an immediate value in a single
9402 insn. In theory we could issue multiple subtracts, but after
9403 three of them it becomes more space efficient to place the full
9404 value in the constant pool and load into a register. (Also the
9405 ARM debugger really likes to see only one stack decrement per
9406 function). So instead we look for a scratch register into which
9407 we can load the decrement, and then we subtract this from the
9408 stack pointer. Unfortunately on the thumb the only available
9409 scratch registers are the argument registers, and we cannot use
9410 these as they may hold arguments to the function. Instead we
9411 attempt to locate a call preserved register which is used by this
9412 function. If we can find one, then we know that it will have
9413 been pushed at the start of the prologue and so we can corrupt
9414 it now. */
9419 && !(frame_pointer_needed
9424 {
9427 /* Choose an arbitary, non-argument low register. */
9430 /* Save it by copying it into a high, scratch register. */
9433 /* Decrement the stack. */
9436 reg));
9438 /* Restore the low register's original value. */
9441 /* Emit a USE of the restored scratch register, so that flow
9442 analysis will not consider the restore redundant. The
9443 register won't be used again in this function and isn't
9444 restored by the epilogue. */
9446 }
9447 else
9448 {
9453 reg));
9454 }
9455 }
9456 }
9460 }
9462 void
9464 {
9468 /* Naked functions don't have epilogues. */
9475 {
9481 else
9482 {
9483 /* r3 is always free in the epilogue. */
9488 }
9489 }
9491 /* Emit a USE (stack_pointer_rtx), so that
9492 the stack adjustment will not be deleted. */
9497 }
9499 void
9502 {
9512 {
9521 /* Generate code sequence to switch us into Thumb mode. */
9522 /* The .code 32 directive has already been emitted by
9523 ASM_DECLARE_FUNCTION_NAME. */
9527 /* Generate a label, so that the debugger will notice the
9528 change in instruction sets. This label is also used by
9529 the assembler to bypass the ARM code when this function
9530 is called from a Thumb encoded function elsewhere in the
9531 same file. Hence the definition of STUB_NAME here must
9532 agree with the definition in gas/config/tc-arm.c */
9537 #ifdef ARM_PE
9540 #endif
9544 }
9550 {
9552 {
9561 regno++)
9566 }
9567 else
9570 current_function_pretend_args_size);
9571 }
9582 {
9587 /* We have been asked to create a stack backtrace structure.
9588 The code looks like this:
9590 0 .align 2
9591 0 func:
9592 0 sub SP, #16 Reserve space for 4 registers.
9593 2 push {R7} Get a work register.
9594 4 add R7, SP, #20 Get the stack pointer before the push.
9595 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
9596 8 mov R7, PC Get hold of the start of this code plus 12.
9597 10 str R7, [SP, #16] Store it.
9598 12 mov R7, FP Get hold of the current frame pointer.
9599 14 str R7, [SP, #4] Store it.
9600 16 mov R7, LR Get hold of the current return address.
9601 18 str R7, [SP, #12] Store it.
9602 20 add R7, SP, #16 Point at the start of the backtrace structure.
9603 22 mov FP, R7 Put this value into the frame pointer. */
9606 {
9607 /* See if the a4 register is free. */
9613 }
9616 {
9617 /* Select a register from the list that will be pushed to
9618 use as our work register. */
9622 }
9624 asm_fprintf
9641 /* Make sure that the instruction fetching the PC is in the right place
9642 to calculate "start of backtrace creation code + 12". */
9644 {
9649 ARM_HARD_FRAME_POINTER_REGNUM);
9651 offset);
9652 }
9653 else
9654 {
9656 ARM_HARD_FRAME_POINTER_REGNUM);
9658 offset);
9662 }
9671 }
9676 {
9679 high_regs_pushed++;
9680 }
9683 {
9689 {
9691 && !(TARGET_SINGLE_PIC_BASE
9694 }
9699 {
9700 /* Desperation time -- this probably will never happen. */
9705 }
9708 {
9710 {
9712 {
9715 high_regs_pushed--;
9719 next_hi_reg--)
9720 {
9723 && !(TARGET_SINGLE_PIC_BASE
9726 }
9727 else
9728 {
9731 }
9732 }
9733 }
9736 }
9742 }
9743 }
9745 /* Handle the case of a double word load into a low register from
9746 a computed memory address. The computed address may involve a
9747 register which is overwritten by the load. */
9752 {
9753 rtx addr;
9754 rtx base;
9755 rtx offset;
9756 rtx arg1;
9757 rtx arg2;
9763 {
9766 }
9768 /* Get the memory address. */
9771 /* Work out how the memory address is computed. */
9773 {
9779 {
9782 }
9783 else
9784 {
9787 }
9791 /* Compute <address> + 4 for the high order load. */
9805 else
9811 /* Catch the case of <address> = <reg> + <reg> */
9813 {
9818 /* Add the base and offset registers together into the
9819 higher destination register. */
9823 /* Load the lower destination register from the address in
9824 the higher destination register. */
9828 /* Load the higher destination register from its own address
9829 plus 4. */
9832 }
9833 else
9834 {
9835 /* Compute <address> + 4 for the high order load. */
9839 /* If the computed address is held in the low order register
9840 then load the high order register first, otherwise always
9841 load the low order register first. */
9843 {
9846 }
9847 else
9848 {
9851 }
9852 }
9856 /* With no registers to worry about we can just load the value
9857 directly. */
9869 }
9872 }
9879 {
9880 rtx tmp;
9883 {
9886 {
9890 }
9897 {
9901 }
9903 {
9907 }
9909 {
9913 }
9921 }
9924 }
9926 /* Routines for generating rtl */
9928 void
9931 {
9938 {
9941 }
9944 {
9947 }
9950 {
9956 }
9959 {
9964 reg));
9967 }
9970 {
9975 reg));
9976 }
9977 }
9979 int
9981 rtx op;
9983 {
9987 }
9991 rtx x;
9993 {
9995 {
9998 };
10002 {
10015 }
10018 }
10020 /* Handle storing a half-word to memory during reload. */
10021 void
10024 {
10026 }
10028 /* Handle storing a half-word to memory during reload. */
10029 void
10032 {
10034 }
10036 /* Return the length of a function name prefix
10037 that starts with the character 'c'. */
10038 static int
10040 {
10042 {
10043 ARM_NAME_ENCODING_LENGTHS
10045 }
10046 }
10048 /* Return a pointer to a function's name with any
10049 and all prefix encodings stripped from it. */
10052 {
10059 }
10061 #ifdef AOF_ASSEMBLER
10062 /* Special functions only needed when producing AOF syntax assembler. */
10065 struct pic_chain
10066 {
10069 };
10073 rtx
10075 rtx x;
10076 {
10081 {
10082 /* We mark this here and not in arm_add_gc_roots() to avoid
10083 polluting even more code with ifdefs, and because it never
10084 contains anything useful until we assign to it here. */
10087 }
10098 }
10100 void
10103 {
10110 PIC_OFFSET_TABLE_REGNUM,
10111 PIC_OFFSET_TABLE_REGNUM);
10115 {
10119 }
10120 }
10126 {
10129 arm_text_section_count++);
10133 }
10139 {
10143 }
10145 /* The AOF assembler is religiously strict about declarations of
10146 imported and exported symbols, so that it is impossible to declare
10147 a function as imported near the beginning of the file, and then to
10148 export it later on. It is, however, possible to delay the decision
10149 until all the functions in the file have been compiled. To get
10150 around this, we maintain a list of the imports and exports, and
10151 delete from it any that are subsequently defined. At the end of
10152 compilation we spit the remainder of the list out before the END
10153 directive. */
10155 struct import
10156 {
10159 };
10163 void
10166 {
10177 }
10179 void
10182 {
10186 {
10188 {
10191 }
10192 }
10193 }
10197 void
10200 {
10201 /* The AOF assembler needs this to cause the startup code to be extracted
10202 from the library. Brining in __main causes the whole thing to work
10203 automagically. */
10205 {
10209 }
10211 /* Now dump the remaining imports. */
10213 {
10218 }
10219 }