| blob | 802441a64f76882747924c465c8ae5120a77d7e6 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; UNSPEC usage
27 ;;
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 ])
55 ;;
56 ;; UNSPEC_VOLATILE usage
57 ;;
59 (define_constants
60 [(UNSPECV_BLOCK 0)
61 (UNSPECV_EH_RR 9) ; eh_reg_restore
62 ])
63 \f
64 ;; Define an insn type attribute. This is used in function unit delay
65 ;; computations.
66 (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
67 (const_string "integer"))
69 ;; Length (in bytes).
70 ; '(pc)' in the following doesn't include the instruction itself; it is
71 ; calculated as if the instruction had zero size.
72 (define_attr "length" ""
73 (if_then_else (eq_attr "type" "branch")
74 (if_then_else (and (ge (minus (match_dup 0) (pc))
75 (const_int -32768))
76 (lt (minus (match_dup 0) (pc))
77 (const_int 32764)))
78 (const_int 4)
79 (const_int 8))
80 (const_int 4)))
82 ;; Processor type -- this attribute must exactly match the processor_type
83 ;; enumeration in rs6000.h.
85 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4"
86 (const (symbol_ref "rs6000_cpu_attr")))
88 (automata_option "ndfa")
90 (include "rios1.md")
91 (include "rios2.md")
92 (include "rs64.md")
93 (include "mpc.md")
94 (include "40x.md")
95 (include "440.md")
96 (include "603.md")
97 (include "6xx.md")
98 (include "7xx.md")
99 (include "7450.md")
100 (include "8540.md")
101 (include "power4.md")
103 \f
104 ;; Start with fixed-point load and store insns. Here we put only the more
105 ;; complex forms. Basic data transfer is done later.
107 (define_expand "zero_extendqidi2"
108 [(set (match_operand:DI 0 "gpc_reg_operand" "")
109 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
110 "TARGET_POWERPC64"
111 "")
113 (define_insn ""
114 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
115 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
116 "TARGET_POWERPC64"
117 "@
118 lbz%U1%X1 %0,%1
119 rldicl %0,%1,0,56"
120 [(set_attr "type" "load,*")])
122 (define_insn ""
123 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
124 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
125 (const_int 0)))
126 (clobber (match_scratch:DI 2 "=r,r"))]
127 "TARGET_64BIT"
128 "@
129 rldicl. %2,%1,0,56
130 #"
131 [(set_attr "type" "compare")
132 (set_attr "length" "4,8")])
134 (define_split
135 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
136 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
137 (const_int 0)))
138 (clobber (match_scratch:DI 2 ""))]
139 "TARGET_POWERPC64 && reload_completed"
140 [(set (match_dup 2)
141 (zero_extend:DI (match_dup 1)))
142 (set (match_dup 0)
143 (compare:CC (match_dup 2)
144 (const_int 0)))]
145 "")
147 (define_insn ""
148 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
149 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
150 (const_int 0)))
151 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
152 (zero_extend:DI (match_dup 1)))]
153 "TARGET_64BIT"
154 "@
155 rldicl. %0,%1,0,56
156 #"
157 [(set_attr "type" "compare")
158 (set_attr "length" "4,8")])
160 (define_split
161 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
162 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
163 (const_int 0)))
164 (set (match_operand:DI 0 "gpc_reg_operand" "")
165 (zero_extend:DI (match_dup 1)))]
166 "TARGET_POWERPC64 && reload_completed"
167 [(set (match_dup 0)
168 (zero_extend:DI (match_dup 1)))
169 (set (match_dup 2)
170 (compare:CC (match_dup 0)
171 (const_int 0)))]
172 "")
174 (define_insn "extendqidi2"
175 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
176 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
177 "TARGET_POWERPC64"
178 "extsb %0,%1")
180 (define_insn ""
181 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
182 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
183 (const_int 0)))
184 (clobber (match_scratch:DI 2 "=r,r"))]
185 "TARGET_64BIT"
186 "@
187 extsb. %2,%1
188 #"
189 [(set_attr "type" "compare")
190 (set_attr "length" "4,8")])
192 (define_split
193 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
194 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
195 (const_int 0)))
196 (clobber (match_scratch:DI 2 ""))]
197 "TARGET_POWERPC64 && reload_completed"
198 [(set (match_dup 2)
199 (sign_extend:DI (match_dup 1)))
200 (set (match_dup 0)
201 (compare:CC (match_dup 2)
202 (const_int 0)))]
203 "")
205 (define_insn ""
206 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
207 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
208 (const_int 0)))
209 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
210 (sign_extend:DI (match_dup 1)))]
211 "TARGET_64BIT"
212 "@
213 extsb. %0,%1
214 #"
215 [(set_attr "type" "compare")
216 (set_attr "length" "4,8")])
218 (define_split
219 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
220 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
221 (const_int 0)))
222 (set (match_operand:DI 0 "gpc_reg_operand" "")
223 (sign_extend:DI (match_dup 1)))]
224 "TARGET_POWERPC64 && reload_completed"
225 [(set (match_dup 0)
226 (sign_extend:DI (match_dup 1)))
227 (set (match_dup 2)
228 (compare:CC (match_dup 0)
229 (const_int 0)))]
230 "")
232 (define_expand "zero_extendhidi2"
233 [(set (match_operand:DI 0 "gpc_reg_operand" "")
234 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
235 "TARGET_POWERPC64"
236 "")
238 (define_insn ""
239 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
240 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
241 "TARGET_POWERPC64"
242 "@
243 lhz%U1%X1 %0,%1
244 rldicl %0,%1,0,48"
245 [(set_attr "type" "load,*")])
247 (define_insn ""
248 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
249 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
250 (const_int 0)))
251 (clobber (match_scratch:DI 2 "=r,r"))]
252 "TARGET_64BIT"
253 "@
254 rldicl. %2,%1,0,48
255 #"
256 [(set_attr "type" "compare")
257 (set_attr "length" "4,8")])
259 (define_split
260 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
261 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
262 (const_int 0)))
263 (clobber (match_scratch:DI 2 ""))]
264 "TARGET_POWERPC64 && reload_completed"
265 [(set (match_dup 2)
266 (zero_extend:DI (match_dup 1)))
267 (set (match_dup 0)
268 (compare:CC (match_dup 2)
269 (const_int 0)))]
270 "")
272 (define_insn ""
273 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
274 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
275 (const_int 0)))
276 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
277 (zero_extend:DI (match_dup 1)))]
278 "TARGET_64BIT"
279 "@
280 rldicl. %0,%1,0,48
281 #"
282 [(set_attr "type" "compare")
283 (set_attr "length" "4,8")])
285 (define_split
286 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
287 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
288 (const_int 0)))
289 (set (match_operand:DI 0 "gpc_reg_operand" "")
290 (zero_extend:DI (match_dup 1)))]
291 "TARGET_POWERPC64 && reload_completed"
292 [(set (match_dup 0)
293 (zero_extend:DI (match_dup 1)))
294 (set (match_dup 2)
295 (compare:CC (match_dup 0)
296 (const_int 0)))]
297 "")
299 (define_expand "extendhidi2"
300 [(set (match_operand:DI 0 "gpc_reg_operand" "")
301 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
302 "TARGET_POWERPC64"
303 "")
305 (define_insn ""
306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
307 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
308 "TARGET_POWERPC64"
309 "@
310 lha%U1%X1 %0,%1
311 extsh %0,%1"
312 [(set_attr "type" "load_ext,*")])
314 (define_insn ""
315 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
316 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
317 (const_int 0)))
318 (clobber (match_scratch:DI 2 "=r,r"))]
319 "TARGET_64BIT"
320 "@
321 extsh. %2,%1
322 #"
323 [(set_attr "type" "compare")
324 (set_attr "length" "4,8")])
326 (define_split
327 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
328 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
329 (const_int 0)))
330 (clobber (match_scratch:DI 2 ""))]
331 "TARGET_POWERPC64 && reload_completed"
332 [(set (match_dup 2)
333 (sign_extend:DI (match_dup 1)))
334 (set (match_dup 0)
335 (compare:CC (match_dup 2)
336 (const_int 0)))]
337 "")
339 (define_insn ""
340 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
341 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
342 (const_int 0)))
343 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
344 (sign_extend:DI (match_dup 1)))]
345 "TARGET_64BIT"
346 "@
347 extsh. %0,%1
348 #"
349 [(set_attr "type" "compare")
350 (set_attr "length" "4,8")])
352 (define_split
353 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
354 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
355 (const_int 0)))
356 (set (match_operand:DI 0 "gpc_reg_operand" "")
357 (sign_extend:DI (match_dup 1)))]
358 "TARGET_POWERPC64 && reload_completed"
359 [(set (match_dup 0)
360 (sign_extend:DI (match_dup 1)))
361 (set (match_dup 2)
362 (compare:CC (match_dup 0)
363 (const_int 0)))]
364 "")
366 (define_expand "zero_extendsidi2"
367 [(set (match_operand:DI 0 "gpc_reg_operand" "")
368 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
369 "TARGET_POWERPC64"
370 "")
372 (define_insn ""
373 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
374 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
375 "TARGET_POWERPC64"
376 "@
377 lwz%U1%X1 %0,%1
378 rldicl %0,%1,0,32"
379 [(set_attr "type" "load,*")])
381 (define_insn ""
382 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
383 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
384 (const_int 0)))
385 (clobber (match_scratch:DI 2 "=r,r"))]
386 "TARGET_64BIT"
387 "@
388 rldicl. %2,%1,0,32
389 #"
390 [(set_attr "type" "compare")
391 (set_attr "length" "4,8")])
393 (define_split
394 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
395 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
396 (const_int 0)))
397 (clobber (match_scratch:DI 2 ""))]
398 "TARGET_POWERPC64 && reload_completed"
399 [(set (match_dup 2)
400 (zero_extend:DI (match_dup 1)))
401 (set (match_dup 0)
402 (compare:CC (match_dup 2)
403 (const_int 0)))]
404 "")
406 (define_insn ""
407 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
408 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
409 (const_int 0)))
410 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
411 (zero_extend:DI (match_dup 1)))]
412 "TARGET_64BIT"
413 "@
414 rldicl. %0,%1,0,32
415 #"
416 [(set_attr "type" "compare")
417 (set_attr "length" "4,8")])
419 (define_split
420 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
421 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
422 (const_int 0)))
423 (set (match_operand:DI 0 "gpc_reg_operand" "")
424 (zero_extend:DI (match_dup 1)))]
425 "TARGET_POWERPC64 && reload_completed"
426 [(set (match_dup 0)
427 (zero_extend:DI (match_dup 1)))
428 (set (match_dup 2)
429 (compare:CC (match_dup 0)
430 (const_int 0)))]
431 "")
433 (define_expand "extendsidi2"
434 [(set (match_operand:DI 0 "gpc_reg_operand" "")
435 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
436 "TARGET_POWERPC64"
437 "")
439 (define_insn ""
440 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
441 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
442 "TARGET_POWERPC64"
443 "@
444 lwa%U1%X1 %0,%1
445 extsw %0,%1"
446 [(set_attr "type" "load_ext,*")])
448 (define_insn ""
449 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
450 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
451 (const_int 0)))
452 (clobber (match_scratch:DI 2 "=r,r"))]
453 "TARGET_64BIT"
454 "@
455 extsw. %2,%1
456 #"
457 [(set_attr "type" "compare")
458 (set_attr "length" "4,8")])
460 (define_split
461 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
462 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
463 (const_int 0)))
464 (clobber (match_scratch:DI 2 ""))]
465 "TARGET_POWERPC64 && reload_completed"
466 [(set (match_dup 2)
467 (sign_extend:DI (match_dup 1)))
468 (set (match_dup 0)
469 (compare:CC (match_dup 2)
470 (const_int 0)))]
471 "")
473 (define_insn ""
474 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
475 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
476 (const_int 0)))
477 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
478 (sign_extend:DI (match_dup 1)))]
479 "TARGET_64BIT"
480 "@
481 extsw. %0,%1
482 #"
483 [(set_attr "type" "compare")
484 (set_attr "length" "4,8")])
486 (define_split
487 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
488 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
489 (const_int 0)))
490 (set (match_operand:DI 0 "gpc_reg_operand" "")
491 (sign_extend:DI (match_dup 1)))]
492 "TARGET_POWERPC64 && reload_completed"
493 [(set (match_dup 0)
494 (sign_extend:DI (match_dup 1)))
495 (set (match_dup 2)
496 (compare:CC (match_dup 0)
497 (const_int 0)))]
498 "")
500 (define_expand "zero_extendqisi2"
501 [(set (match_operand:SI 0 "gpc_reg_operand" "")
502 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
503 ""
504 "")
506 (define_insn ""
507 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
508 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
509 ""
510 "@
511 lbz%U1%X1 %0,%1
512 {rlinm|rlwinm} %0,%1,0,0xff"
513 [(set_attr "type" "load,*")])
515 (define_insn ""
516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
517 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
518 (const_int 0)))
519 (clobber (match_scratch:SI 2 "=r,r"))]
520 ""
521 "@
522 {andil.|andi.} %2,%1,0xff
523 #"
524 [(set_attr "type" "compare")
525 (set_attr "length" "4,8")])
527 (define_split
528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
529 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
530 (const_int 0)))
531 (clobber (match_scratch:SI 2 ""))]
532 "reload_completed"
533 [(set (match_dup 2)
534 (zero_extend:SI (match_dup 1)))
535 (set (match_dup 0)
536 (compare:CC (match_dup 2)
537 (const_int 0)))]
538 "")
540 (define_insn ""
541 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
542 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
543 (const_int 0)))
544 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
545 (zero_extend:SI (match_dup 1)))]
546 ""
547 "@
548 {andil.|andi.} %0,%1,0xff
549 #"
550 [(set_attr "type" "compare")
551 (set_attr "length" "4,8")])
553 (define_split
554 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
555 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
556 (const_int 0)))
557 (set (match_operand:SI 0 "gpc_reg_operand" "")
558 (zero_extend:SI (match_dup 1)))]
559 "reload_completed"
560 [(set (match_dup 0)
561 (zero_extend:SI (match_dup 1)))
562 (set (match_dup 2)
563 (compare:CC (match_dup 0)
564 (const_int 0)))]
565 "")
567 (define_expand "extendqisi2"
568 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
569 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
570 ""
571 "
572 {
573 if (TARGET_POWERPC)
574 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
575 else if (TARGET_POWER)
576 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
577 else
578 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
579 DONE;
580 }")
582 (define_insn "extendqisi2_ppc"
583 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
584 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
585 "TARGET_POWERPC"
586 "extsb %0,%1")
588 (define_insn ""
589 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
590 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
591 (const_int 0)))
592 (clobber (match_scratch:SI 2 "=r,r"))]
593 "TARGET_POWERPC"
594 "@
595 extsb. %2,%1
596 #"
597 [(set_attr "type" "compare")
598 (set_attr "length" "4,8")])
600 (define_split
601 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
602 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
603 (const_int 0)))
604 (clobber (match_scratch:SI 2 ""))]
605 "TARGET_POWERPC && reload_completed"
606 [(set (match_dup 2)
607 (sign_extend:SI (match_dup 1)))
608 (set (match_dup 0)
609 (compare:CC (match_dup 2)
610 (const_int 0)))]
611 "")
613 (define_insn ""
614 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
615 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
616 (const_int 0)))
617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
618 (sign_extend:SI (match_dup 1)))]
619 "TARGET_POWERPC"
620 "@
621 extsb. %0,%1
622 #"
623 [(set_attr "type" "compare")
624 (set_attr "length" "4,8")])
626 (define_split
627 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
628 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
629 (const_int 0)))
630 (set (match_operand:SI 0 "gpc_reg_operand" "")
631 (sign_extend:SI (match_dup 1)))]
632 "TARGET_POWERPC && reload_completed"
633 [(set (match_dup 0)
634 (sign_extend:SI (match_dup 1)))
635 (set (match_dup 2)
636 (compare:CC (match_dup 0)
637 (const_int 0)))]
638 "")
640 (define_expand "extendqisi2_power"
641 [(parallel [(set (match_dup 2)
642 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
643 (const_int 24)))
644 (clobber (scratch:SI))])
645 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
646 (ashiftrt:SI (match_dup 2)
647 (const_int 24)))
648 (clobber (scratch:SI))])]
649 "TARGET_POWER"
650 "
651 { operands[1] = gen_lowpart (SImode, operands[1]);
652 operands[2] = gen_reg_rtx (SImode); }")
654 (define_expand "extendqisi2_no_power"
655 [(set (match_dup 2)
656 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
657 (const_int 24)))
658 (set (match_operand:SI 0 "gpc_reg_operand" "")
659 (ashiftrt:SI (match_dup 2)
660 (const_int 24)))]
661 "! TARGET_POWER && ! TARGET_POWERPC"
662 "
663 { operands[1] = gen_lowpart (SImode, operands[1]);
664 operands[2] = gen_reg_rtx (SImode); }")
666 (define_expand "zero_extendqihi2"
667 [(set (match_operand:HI 0 "gpc_reg_operand" "")
668 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
669 ""
670 "")
672 (define_insn ""
673 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
674 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
675 ""
676 "@
677 lbz%U1%X1 %0,%1
678 {rlinm|rlwinm} %0,%1,0,0xff"
679 [(set_attr "type" "load,*")])
681 (define_insn ""
682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
683 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
684 (const_int 0)))
685 (clobber (match_scratch:HI 2 "=r,r"))]
686 ""
687 "@
688 {andil.|andi.} %2,%1,0xff
689 #"
690 [(set_attr "type" "compare")
691 (set_attr "length" "4,8")])
693 (define_split
694 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
695 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
696 (const_int 0)))
697 (clobber (match_scratch:HI 2 ""))]
698 "reload_completed"
699 [(set (match_dup 2)
700 (zero_extend:HI (match_dup 1)))
701 (set (match_dup 0)
702 (compare:CC (match_dup 2)
703 (const_int 0)))]
704 "")
706 (define_insn ""
707 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
708 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
709 (const_int 0)))
710 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
711 (zero_extend:HI (match_dup 1)))]
712 ""
713 "@
714 {andil.|andi.} %0,%1,0xff
715 #"
716 [(set_attr "type" "compare")
717 (set_attr "length" "4,8")])
719 (define_split
720 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
721 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
722 (const_int 0)))
723 (set (match_operand:HI 0 "gpc_reg_operand" "")
724 (zero_extend:HI (match_dup 1)))]
725 "reload_completed"
726 [(set (match_dup 0)
727 (zero_extend:HI (match_dup 1)))
728 (set (match_dup 2)
729 (compare:CC (match_dup 0)
730 (const_int 0)))]
731 "")
733 (define_expand "extendqihi2"
734 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
735 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
736 ""
737 "
738 {
739 if (TARGET_POWERPC)
740 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
741 else if (TARGET_POWER)
742 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
743 else
744 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
745 DONE;
746 }")
748 (define_insn "extendqihi2_ppc"
749 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
750 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
751 "TARGET_POWERPC"
752 "extsb %0,%1")
754 (define_insn ""
755 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
756 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
757 (const_int 0)))
758 (clobber (match_scratch:HI 2 "=r,r"))]
759 "TARGET_POWERPC"
760 "@
761 extsb. %2,%1
762 #"
763 [(set_attr "type" "compare")
764 (set_attr "length" "4,8")])
766 (define_split
767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
768 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
769 (const_int 0)))
770 (clobber (match_scratch:HI 2 ""))]
771 "TARGET_POWERPC && reload_completed"
772 [(set (match_dup 2)
773 (sign_extend:HI (match_dup 1)))
774 (set (match_dup 0)
775 (compare:CC (match_dup 2)
776 (const_int 0)))]
777 "")
779 (define_insn ""
780 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
781 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
782 (const_int 0)))
783 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
784 (sign_extend:HI (match_dup 1)))]
785 "TARGET_POWERPC"
786 "@
787 extsb. %0,%1
788 #"
789 [(set_attr "type" "compare")
790 (set_attr "length" "4,8")])
792 (define_split
793 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
794 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
795 (const_int 0)))
796 (set (match_operand:HI 0 "gpc_reg_operand" "")
797 (sign_extend:HI (match_dup 1)))]
798 "TARGET_POWERPC && reload_completed"
799 [(set (match_dup 0)
800 (sign_extend:HI (match_dup 1)))
801 (set (match_dup 2)
802 (compare:CC (match_dup 0)
803 (const_int 0)))]
804 "")
806 (define_expand "extendqihi2_power"
807 [(parallel [(set (match_dup 2)
808 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
809 (const_int 24)))
810 (clobber (scratch:SI))])
811 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
812 (ashiftrt:SI (match_dup 2)
813 (const_int 24)))
814 (clobber (scratch:SI))])]
815 "TARGET_POWER"
816 "
817 { operands[0] = gen_lowpart (SImode, operands[0]);
818 operands[1] = gen_lowpart (SImode, operands[1]);
819 operands[2] = gen_reg_rtx (SImode); }")
821 (define_expand "extendqihi2_no_power"
822 [(set (match_dup 2)
823 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
824 (const_int 24)))
825 (set (match_operand:HI 0 "gpc_reg_operand" "")
826 (ashiftrt:SI (match_dup 2)
827 (const_int 24)))]
828 "! TARGET_POWER && ! TARGET_POWERPC"
829 "
830 { operands[0] = gen_lowpart (SImode, operands[0]);
831 operands[1] = gen_lowpart (SImode, operands[1]);
832 operands[2] = gen_reg_rtx (SImode); }")
834 (define_expand "zero_extendhisi2"
835 [(set (match_operand:SI 0 "gpc_reg_operand" "")
836 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
837 ""
838 "")
840 (define_insn ""
841 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
842 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
843 ""
844 "@
845 lhz%U1%X1 %0,%1
846 {rlinm|rlwinm} %0,%1,0,0xffff"
847 [(set_attr "type" "load,*")])
849 (define_insn ""
850 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
851 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
852 (const_int 0)))
853 (clobber (match_scratch:SI 2 "=r,r"))]
854 ""
855 "@
856 {andil.|andi.} %2,%1,0xffff
857 #"
858 [(set_attr "type" "compare")
859 (set_attr "length" "4,8")])
861 (define_split
862 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
863 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
864 (const_int 0)))
865 (clobber (match_scratch:SI 2 ""))]
866 "reload_completed"
867 [(set (match_dup 2)
868 (zero_extend:SI (match_dup 1)))
869 (set (match_dup 0)
870 (compare:CC (match_dup 2)
871 (const_int 0)))]
872 "")
874 (define_insn ""
875 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
876 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
877 (const_int 0)))
878 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
879 (zero_extend:SI (match_dup 1)))]
880 ""
881 "@
882 {andil.|andi.} %0,%1,0xffff
883 #"
884 [(set_attr "type" "compare")
885 (set_attr "length" "4,8")])
887 (define_split
888 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
889 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
890 (const_int 0)))
891 (set (match_operand:SI 0 "gpc_reg_operand" "")
892 (zero_extend:SI (match_dup 1)))]
893 "reload_completed"
894 [(set (match_dup 0)
895 (zero_extend:SI (match_dup 1)))
896 (set (match_dup 2)
897 (compare:CC (match_dup 0)
898 (const_int 0)))]
899 "")
901 (define_expand "extendhisi2"
902 [(set (match_operand:SI 0 "gpc_reg_operand" "")
903 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
904 ""
905 "")
907 (define_insn ""
908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
909 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
910 ""
911 "@
912 lha%U1%X1 %0,%1
913 {exts|extsh} %0,%1"
914 [(set_attr "type" "load_ext,*")])
916 (define_insn ""
917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
918 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
919 (const_int 0)))
920 (clobber (match_scratch:SI 2 "=r,r"))]
921 ""
922 "@
923 {exts.|extsh.} %2,%1
924 #"
925 [(set_attr "type" "compare")
926 (set_attr "length" "4,8")])
928 (define_split
929 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
930 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
931 (const_int 0)))
932 (clobber (match_scratch:SI 2 ""))]
933 "reload_completed"
934 [(set (match_dup 2)
935 (sign_extend:SI (match_dup 1)))
936 (set (match_dup 0)
937 (compare:CC (match_dup 2)
938 (const_int 0)))]
939 "")
941 (define_insn ""
942 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
943 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
944 (const_int 0)))
945 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
946 (sign_extend:SI (match_dup 1)))]
947 ""
948 "@
949 {exts.|extsh.} %0,%1
950 #"
951 [(set_attr "type" "compare")
952 (set_attr "length" "4,8")])
953 \f
954 (define_split
955 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
956 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
957 (const_int 0)))
958 (set (match_operand:SI 0 "gpc_reg_operand" "")
959 (sign_extend:SI (match_dup 1)))]
960 "reload_completed"
961 [(set (match_dup 0)
962 (sign_extend:SI (match_dup 1)))
963 (set (match_dup 2)
964 (compare:CC (match_dup 0)
965 (const_int 0)))]
966 "")
968 ;; Fixed-point arithmetic insns.
970 ;; Discourage ai/addic because of carry but provide it in an alternative
971 ;; allowing register zero as source.
972 (define_expand "addsi3"
973 [(set (match_operand:SI 0 "gpc_reg_operand" "")
974 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
975 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
976 ""
977 "
978 {
979 if (GET_CODE (operands[2]) == CONST_INT
980 && ! add_operand (operands[2], SImode))
981 {
982 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
983 ? operands[0] : gen_reg_rtx (SImode));
985 HOST_WIDE_INT val = INTVAL (operands[2]);
986 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
987 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
989 /* The ordering here is important for the prolog expander.
990 When space is allocated from the stack, adding 'low' first may
991 produce a temporary deallocation (which would be bad). */
992 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
993 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
994 DONE;
995 }
996 }")
998 (define_insn "*addsi3_internal1"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1000 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1001 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1002 ""
1003 "@
1004 {cax|add} %0,%1,%2
1005 {cal %0,%2(%1)|addi %0,%1,%2}
1006 {ai|addic} %0,%1,%2
1007 {cau|addis} %0,%1,%v2"
1008 [(set_attr "length" "4,4,4,4")])
1010 (define_insn "addsi3_high"
1011 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1012 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1013 (high:SI (match_operand 2 "" ""))))]
1014 "TARGET_MACHO && !TARGET_64BIT"
1015 "{cau|addis} %0,%1,ha16(%2)"
1016 [(set_attr "length" "4")])
1018 (define_insn "*addsi3_internal2"
1019 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1020 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1021 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1022 (const_int 0)))
1023 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1024 "TARGET_32BIT"
1025 "@
1026 {cax.|add.} %3,%1,%2
1027 {ai.|addic.} %3,%1,%2
1028 #
1029 #"
1030 [(set_attr "type" "fast_compare,compare,compare,compare")
1031 (set_attr "length" "4,4,8,8")])
1033 (define_split
1034 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1035 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1036 (match_operand:SI 2 "reg_or_short_operand" ""))
1037 (const_int 0)))
1038 (clobber (match_scratch:SI 3 ""))]
1039 "TARGET_32BIT && reload_completed"
1040 [(set (match_dup 3)
1041 (plus:SI (match_dup 1)
1042 (match_dup 2)))
1043 (set (match_dup 0)
1044 (compare:CC (match_dup 3)
1045 (const_int 0)))]
1046 "")
1048 (define_insn "*addsi3_internal3"
1049 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1050 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1051 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1052 (const_int 0)))
1053 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1054 (plus:SI (match_dup 1)
1055 (match_dup 2)))]
1056 "TARGET_32BIT"
1057 "@
1058 {cax.|add.} %0,%1,%2
1059 {ai.|addic.} %0,%1,%2
1060 #
1061 #"
1062 [(set_attr "type" "fast_compare,compare,compare,compare")
1063 (set_attr "length" "4,4,8,8")])
1065 (define_split
1066 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1067 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1068 (match_operand:SI 2 "reg_or_short_operand" ""))
1069 (const_int 0)))
1070 (set (match_operand:SI 0 "gpc_reg_operand" "")
1071 (plus:SI (match_dup 1) (match_dup 2)))]
1072 "TARGET_32BIT && reload_completed"
1073 [(set (match_dup 0)
1074 (plus:SI (match_dup 1)
1075 (match_dup 2)))
1076 (set (match_dup 3)
1077 (compare:CC (match_dup 0)
1078 (const_int 0)))]
1079 "")
1081 ;; Split an add that we can't do in one insn into two insns, each of which
1082 ;; does one 16-bit part. This is used by combine. Note that the low-order
1083 ;; add should be last in case the result gets used in an address.
1085 (define_split
1086 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1087 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1088 (match_operand:SI 2 "non_add_cint_operand" "")))]
1089 ""
1090 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1091 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1092 "
1093 {
1094 HOST_WIDE_INT val = INTVAL (operands[2]);
1095 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1096 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1098 operands[3] = GEN_INT (rest);
1099 operands[4] = GEN_INT (low);
1100 }")
1102 (define_insn "one_cmplsi2"
1103 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1104 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1105 ""
1106 "nor %0,%1,%1")
1108 (define_insn ""
1109 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1110 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1111 (const_int 0)))
1112 (clobber (match_scratch:SI 2 "=r,r"))]
1113 "TARGET_32BIT"
1114 "@
1115 nor. %2,%1,%1
1116 #"
1117 [(set_attr "type" "compare")
1118 (set_attr "length" "4,8")])
1120 (define_split
1121 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1122 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1123 (const_int 0)))
1124 (clobber (match_scratch:SI 2 ""))]
1125 "TARGET_32BIT && reload_completed"
1126 [(set (match_dup 2)
1127 (not:SI (match_dup 1)))
1128 (set (match_dup 0)
1129 (compare:CC (match_dup 2)
1130 (const_int 0)))]
1131 "")
1133 (define_insn ""
1134 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1135 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1136 (const_int 0)))
1137 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1138 (not:SI (match_dup 1)))]
1139 "TARGET_32BIT"
1140 "@
1141 nor. %0,%1,%1
1142 #"
1143 [(set_attr "type" "compare")
1144 (set_attr "length" "4,8")])
1146 (define_split
1147 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1148 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1149 (const_int 0)))
1150 (set (match_operand:SI 0 "gpc_reg_operand" "")
1151 (not:SI (match_dup 1)))]
1152 "TARGET_32BIT && reload_completed"
1153 [(set (match_dup 0)
1154 (not:SI (match_dup 1)))
1155 (set (match_dup 2)
1156 (compare:CC (match_dup 0)
1157 (const_int 0)))]
1158 "")
1160 (define_insn ""
1161 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1162 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1163 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1164 "! TARGET_POWERPC"
1165 "{sf%I1|subf%I1c} %0,%2,%1")
1167 (define_insn ""
1168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1169 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1170 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1171 "TARGET_POWERPC"
1172 "@
1173 subf %0,%2,%1
1174 subfic %0,%2,%1")
1176 (define_insn ""
1177 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1178 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1179 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1180 (const_int 0)))
1181 (clobber (match_scratch:SI 3 "=r,r"))]
1182 "! TARGET_POWERPC"
1183 "@
1184 {sf.|subfc.} %3,%2,%1
1185 #"
1186 [(set_attr "type" "compare")
1187 (set_attr "length" "4,8")])
1189 (define_insn ""
1190 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1191 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1192 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1193 (const_int 0)))
1194 (clobber (match_scratch:SI 3 "=r,r"))]
1195 "TARGET_POWERPC && TARGET_32BIT"
1196 "@
1197 subf. %3,%2,%1
1198 #"
1199 [(set_attr "type" "fast_compare")
1200 (set_attr "length" "4,8")])
1202 (define_split
1203 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1204 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1205 (match_operand:SI 2 "gpc_reg_operand" ""))
1206 (const_int 0)))
1207 (clobber (match_scratch:SI 3 ""))]
1208 "TARGET_32BIT && reload_completed"
1209 [(set (match_dup 3)
1210 (minus:SI (match_dup 1)
1211 (match_dup 2)))
1212 (set (match_dup 0)
1213 (compare:CC (match_dup 3)
1214 (const_int 0)))]
1215 "")
1217 (define_insn ""
1218 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1219 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1220 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1221 (const_int 0)))
1222 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1223 (minus:SI (match_dup 1) (match_dup 2)))]
1224 "! TARGET_POWERPC"
1225 "@
1226 {sf.|subfc.} %0,%2,%1
1227 #"
1228 [(set_attr "type" "compare")
1229 (set_attr "length" "4,8")])
1231 (define_insn ""
1232 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1233 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1234 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1235 (const_int 0)))
1236 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1237 (minus:SI (match_dup 1)
1238 (match_dup 2)))]
1239 "TARGET_POWERPC && TARGET_32BIT"
1240 "@
1241 subf. %0,%2,%1
1242 #"
1243 [(set_attr "type" "fast_compare")
1244 (set_attr "length" "4,8")])
1246 (define_split
1247 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1248 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1249 (match_operand:SI 2 "gpc_reg_operand" ""))
1250 (const_int 0)))
1251 (set (match_operand:SI 0 "gpc_reg_operand" "")
1252 (minus:SI (match_dup 1)
1253 (match_dup 2)))]
1254 "TARGET_32BIT && reload_completed"
1255 [(set (match_dup 0)
1256 (minus:SI (match_dup 1)
1257 (match_dup 2)))
1258 (set (match_dup 3)
1259 (compare:CC (match_dup 0)
1260 (const_int 0)))]
1261 "")
1263 (define_expand "subsi3"
1264 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1265 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1266 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1267 ""
1268 "
1269 {
1270 if (GET_CODE (operands[2]) == CONST_INT)
1271 {
1272 emit_insn (gen_addsi3 (operands[0], operands[1],
1273 negate_rtx (SImode, operands[2])));
1274 DONE;
1275 }
1276 }")
1278 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1279 ;; instruction and some auxiliary computations. Then we just have a single
1280 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1281 ;; combine.
1283 (define_expand "sminsi3"
1284 [(set (match_dup 3)
1285 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1286 (match_operand:SI 2 "reg_or_short_operand" ""))
1287 (const_int 0)
1288 (minus:SI (match_dup 2) (match_dup 1))))
1289 (set (match_operand:SI 0 "gpc_reg_operand" "")
1290 (minus:SI (match_dup 2) (match_dup 3)))]
1291 "TARGET_POWER || TARGET_ISEL"
1292 "
1293 {
1294 if (TARGET_ISEL)
1295 {
1296 operands[2] = force_reg (SImode, operands[2]);
1297 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1298 DONE;
1299 }
1301 operands[3] = gen_reg_rtx (SImode);
1302 }")
1304 (define_split
1305 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1306 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1307 (match_operand:SI 2 "reg_or_short_operand" "")))
1308 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1309 "TARGET_POWER"
1310 [(set (match_dup 3)
1311 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1312 (const_int 0)
1313 (minus:SI (match_dup 2) (match_dup 1))))
1314 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1315 "")
1317 (define_expand "smaxsi3"
1318 [(set (match_dup 3)
1319 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1320 (match_operand:SI 2 "reg_or_short_operand" ""))
1321 (const_int 0)
1322 (minus:SI (match_dup 2) (match_dup 1))))
1323 (set (match_operand:SI 0 "gpc_reg_operand" "")
1324 (plus:SI (match_dup 3) (match_dup 1)))]
1325 "TARGET_POWER || TARGET_ISEL"
1326 "
1327 {
1328 if (TARGET_ISEL)
1329 {
1330 operands[2] = force_reg (SImode, operands[2]);
1331 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1332 DONE;
1333 }
1334 operands[3] = gen_reg_rtx (SImode);
1335 }")
1337 (define_split
1338 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1339 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1340 (match_operand:SI 2 "reg_or_short_operand" "")))
1341 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1342 "TARGET_POWER"
1343 [(set (match_dup 3)
1344 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1345 (const_int 0)
1346 (minus:SI (match_dup 2) (match_dup 1))))
1347 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1348 "")
1350 (define_expand "uminsi3"
1351 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1352 (match_dup 5)))
1353 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1354 (match_dup 5)))
1355 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1356 (const_int 0)
1357 (minus:SI (match_dup 4) (match_dup 3))))
1358 (set (match_operand:SI 0 "gpc_reg_operand" "")
1359 (minus:SI (match_dup 2) (match_dup 3)))]
1360 "TARGET_POWER || TARGET_ISEL"
1361 "
1362 {
1363 if (TARGET_ISEL)
1364 {
1365 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1366 DONE;
1367 }
1368 operands[3] = gen_reg_rtx (SImode);
1369 operands[4] = gen_reg_rtx (SImode);
1370 operands[5] = GEN_INT (-2147483647 - 1);
1371 }")
1373 (define_expand "umaxsi3"
1374 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1375 (match_dup 5)))
1376 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1377 (match_dup 5)))
1378 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1379 (const_int 0)
1380 (minus:SI (match_dup 4) (match_dup 3))))
1381 (set (match_operand:SI 0 "gpc_reg_operand" "")
1382 (plus:SI (match_dup 3) (match_dup 1)))]
1383 "TARGET_POWER || TARGET_ISEL"
1384 "
1385 {
1386 if (TARGET_ISEL)
1387 {
1388 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1389 DONE;
1390 }
1391 operands[3] = gen_reg_rtx (SImode);
1392 operands[4] = gen_reg_rtx (SImode);
1393 operands[5] = GEN_INT (-2147483647 - 1);
1394 }")
1396 (define_insn ""
1397 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1398 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1399 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1400 (const_int 0)
1401 (minus:SI (match_dup 2) (match_dup 1))))]
1402 "TARGET_POWER"
1403 "doz%I2 %0,%1,%2")
1405 (define_insn ""
1406 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1407 (compare:CC
1408 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1409 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1410 (const_int 0)
1411 (minus:SI (match_dup 2) (match_dup 1)))
1412 (const_int 0)))
1413 (clobber (match_scratch:SI 3 "=r,r"))]
1414 "TARGET_POWER"
1415 "@
1416 doz%I2. %3,%1,%2
1417 #"
1418 [(set_attr "type" "delayed_compare")
1419 (set_attr "length" "4,8")])
1421 (define_split
1422 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1423 (compare:CC
1424 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1425 (match_operand:SI 2 "reg_or_short_operand" ""))
1426 (const_int 0)
1427 (minus:SI (match_dup 2) (match_dup 1)))
1428 (const_int 0)))
1429 (clobber (match_scratch:SI 3 ""))]
1430 "TARGET_POWER && reload_completed"
1431 [(set (match_dup 3)
1432 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1433 (const_int 0)
1434 (minus:SI (match_dup 2) (match_dup 1))))
1435 (set (match_dup 0)
1436 (compare:CC (match_dup 3)
1437 (const_int 0)))]
1438 "")
1440 (define_insn ""
1441 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1442 (compare:CC
1443 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1444 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1445 (const_int 0)
1446 (minus:SI (match_dup 2) (match_dup 1)))
1447 (const_int 0)))
1448 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1449 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1450 (const_int 0)
1451 (minus:SI (match_dup 2) (match_dup 1))))]
1452 "TARGET_POWER"
1453 "@
1454 doz%I2. %0,%1,%2
1455 #"
1456 [(set_attr "type" "delayed_compare")
1457 (set_attr "length" "4,8")])
1459 (define_split
1460 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1461 (compare:CC
1462 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1463 (match_operand:SI 2 "reg_or_short_operand" ""))
1464 (const_int 0)
1465 (minus:SI (match_dup 2) (match_dup 1)))
1466 (const_int 0)))
1467 (set (match_operand:SI 0 "gpc_reg_operand" "")
1468 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1469 (const_int 0)
1470 (minus:SI (match_dup 2) (match_dup 1))))]
1471 "TARGET_POWER && reload_completed"
1472 [(set (match_dup 0)
1473 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1474 (const_int 0)
1475 (minus:SI (match_dup 2) (match_dup 1))))
1476 (set (match_dup 3)
1477 (compare:CC (match_dup 0)
1478 (const_int 0)))]
1479 "")
1481 ;; We don't need abs with condition code because such comparisons should
1482 ;; never be done.
1483 (define_expand "abssi2"
1484 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1485 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1486 ""
1487 "
1488 {
1489 if (TARGET_ISEL)
1490 {
1491 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1492 DONE;
1493 }
1494 else if (! TARGET_POWER)
1495 {
1496 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1497 DONE;
1498 }
1499 }")
1501 (define_insn "*abssi2_power"
1502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1503 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1504 "TARGET_POWER"
1505 "abs %0,%1")
1507 (define_insn_and_split "abssi2_isel"
1508 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1509 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1510 (clobber (match_scratch:SI 2 "=&b"))
1511 (clobber (match_scratch:CC 3 "=y"))]
1512 "TARGET_ISEL"
1513 "#"
1514 "&& reload_completed"
1515 [(set (match_dup 2) (neg:SI (match_dup 1)))
1516 (set (match_dup 3)
1517 (compare:CC (match_dup 1)
1518 (const_int 0)))
1519 (set (match_dup 0)
1520 (if_then_else:SI (ge (match_dup 3)
1521 (const_int 0))
1522 (match_dup 1)
1523 (match_dup 2)))]
1524 "")
1526 (define_insn_and_split "abssi2_nopower"
1527 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1528 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1529 (clobber (match_scratch:SI 2 "=&r,&r"))]
1530 "! TARGET_POWER && ! TARGET_ISEL"
1531 "#"
1532 "&& reload_completed"
1533 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1534 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1535 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1536 "")
1538 (define_insn "*nabs_power"
1539 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1540 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1541 "TARGET_POWER"
1542 "nabs %0,%1")
1544 (define_insn_and_split "*nabs_nopower"
1545 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1546 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1547 (clobber (match_scratch:SI 2 "=&r,&r"))]
1548 "! TARGET_POWER"
1549 "#"
1550 "&& reload_completed"
1551 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1552 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1553 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1554 "")
1556 (define_insn "negsi2"
1557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1558 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1559 ""
1560 "neg %0,%1")
1562 (define_insn ""
1563 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1564 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1565 (const_int 0)))
1566 (clobber (match_scratch:SI 2 "=r,r"))]
1567 "TARGET_32BIT"
1568 "@
1569 neg. %2,%1
1570 #"
1571 [(set_attr "type" "fast_compare")
1572 (set_attr "length" "4,8")])
1574 (define_split
1575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1576 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1577 (const_int 0)))
1578 (clobber (match_scratch:SI 2 ""))]
1579 "TARGET_32BIT && reload_completed"
1580 [(set (match_dup 2)
1581 (neg:SI (match_dup 1)))
1582 (set (match_dup 0)
1583 (compare:CC (match_dup 2)
1584 (const_int 0)))]
1585 "")
1587 (define_insn ""
1588 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1589 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1590 (const_int 0)))
1591 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1592 (neg:SI (match_dup 1)))]
1593 "TARGET_32BIT"
1594 "@
1595 neg. %0,%1
1596 #"
1597 [(set_attr "type" "fast_compare")
1598 (set_attr "length" "4,8")])
1600 (define_split
1601 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1602 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1603 (const_int 0)))
1604 (set (match_operand:SI 0 "gpc_reg_operand" "")
1605 (neg:SI (match_dup 1)))]
1606 "TARGET_32BIT && reload_completed"
1607 [(set (match_dup 0)
1608 (neg:SI (match_dup 1)))
1609 (set (match_dup 2)
1610 (compare:CC (match_dup 0)
1611 (const_int 0)))]
1612 "")
1614 (define_insn "clzsi2"
1615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1616 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1617 ""
1618 "{cntlz|cntlzw} %0,%1")
1620 (define_expand "ctzsi2"
1621 [(set (match_dup 2)
1622 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1623 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1624 (match_dup 2)))
1625 (clobber (scratch:CC))])
1626 (set (match_dup 4) (clz:SI (match_dup 3)))
1627 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1628 (minus:SI (const_int 31) (match_dup 4)))]
1629 ""
1630 {
1631 operands[2] = gen_reg_rtx (SImode);
1632 operands[3] = gen_reg_rtx (SImode);
1633 operands[4] = gen_reg_rtx (SImode);
1634 })
1636 (define_expand "ffssi2"
1637 [(set (match_dup 2)
1638 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1639 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1640 (match_dup 2)))
1641 (clobber (scratch:CC))])
1642 (set (match_dup 4) (clz:SI (match_dup 3)))
1643 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1644 (minus:SI (const_int 32) (match_dup 4)))]
1645 ""
1646 {
1647 operands[2] = gen_reg_rtx (SImode);
1648 operands[3] = gen_reg_rtx (SImode);
1649 operands[4] = gen_reg_rtx (SImode);
1650 })
1652 (define_expand "mulsi3"
1653 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1654 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1655 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1656 ""
1657 "
1658 {
1659 if (TARGET_POWER)
1660 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1661 else
1662 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1663 DONE;
1664 }")
1666 (define_insn "mulsi3_mq"
1667 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1668 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1669 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1670 (clobber (match_scratch:SI 3 "=q,q"))]
1671 "TARGET_POWER"
1672 "@
1673 {muls|mullw} %0,%1,%2
1674 {muli|mulli} %0,%1,%2"
1675 [(set (attr "type")
1676 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1677 (const_string "imul3")
1678 (match_operand:SI 2 "short_cint_operand" "")
1679 (const_string "imul2")]
1680 (const_string "imul")))])
1682 (define_insn "mulsi3_no_mq"
1683 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1684 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1685 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1686 "! TARGET_POWER"
1687 "@
1688 {muls|mullw} %0,%1,%2
1689 {muli|mulli} %0,%1,%2"
1690 [(set (attr "type")
1691 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1692 (const_string "imul3")
1693 (match_operand:SI 2 "short_cint_operand" "")
1694 (const_string "imul2")]
1695 (const_string "imul")))])
1697 (define_insn "*mulsi3_mq_internal1"
1698 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1699 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1700 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1701 (const_int 0)))
1702 (clobber (match_scratch:SI 3 "=r,r"))
1703 (clobber (match_scratch:SI 4 "=q,q"))]
1704 "TARGET_POWER"
1705 "@
1706 {muls.|mullw.} %3,%1,%2
1707 #"
1708 [(set_attr "type" "imul_compare")
1709 (set_attr "length" "4,8")])
1711 (define_split
1712 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1713 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1714 (match_operand:SI 2 "gpc_reg_operand" ""))
1715 (const_int 0)))
1716 (clobber (match_scratch:SI 3 ""))
1717 (clobber (match_scratch:SI 4 ""))]
1718 "TARGET_POWER && reload_completed"
1719 [(parallel [(set (match_dup 3)
1720 (mult:SI (match_dup 1) (match_dup 2)))
1721 (clobber (match_dup 4))])
1722 (set (match_dup 0)
1723 (compare:CC (match_dup 3)
1724 (const_int 0)))]
1725 "")
1727 (define_insn "*mulsi3_no_mq_internal1"
1728 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1729 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1730 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1731 (const_int 0)))
1732 (clobber (match_scratch:SI 3 "=r,r"))]
1733 "! TARGET_POWER"
1734 "@
1735 {muls.|mullw.} %3,%1,%2
1736 #"
1737 [(set_attr "type" "imul_compare")
1738 (set_attr "length" "4,8")])
1740 (define_split
1741 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1742 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1743 (match_operand:SI 2 "gpc_reg_operand" ""))
1744 (const_int 0)))
1745 (clobber (match_scratch:SI 3 ""))]
1746 "! TARGET_POWER && reload_completed"
1747 [(set (match_dup 3)
1748 (mult:SI (match_dup 1) (match_dup 2)))
1749 (set (match_dup 0)
1750 (compare:CC (match_dup 3)
1751 (const_int 0)))]
1752 "")
1754 (define_insn "*mulsi3_mq_internal2"
1755 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1756 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1757 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1758 (const_int 0)))
1759 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1760 (mult:SI (match_dup 1) (match_dup 2)))
1761 (clobber (match_scratch:SI 4 "=q,q"))]
1762 "TARGET_POWER"
1763 "@
1764 {muls.|mullw.} %0,%1,%2
1765 #"
1766 [(set_attr "type" "imul_compare")
1767 (set_attr "length" "4,8")])
1769 (define_split
1770 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1771 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1772 (match_operand:SI 2 "gpc_reg_operand" ""))
1773 (const_int 0)))
1774 (set (match_operand:SI 0 "gpc_reg_operand" "")
1775 (mult:SI (match_dup 1) (match_dup 2)))
1776 (clobber (match_scratch:SI 4 ""))]
1777 "TARGET_POWER && reload_completed"
1778 [(parallel [(set (match_dup 0)
1779 (mult:SI (match_dup 1) (match_dup 2)))
1780 (clobber (match_dup 4))])
1781 (set (match_dup 3)
1782 (compare:CC (match_dup 0)
1783 (const_int 0)))]
1784 "")
1786 (define_insn "*mulsi3_no_mq_internal2"
1787 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1788 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1789 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1790 (const_int 0)))
1791 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1792 (mult:SI (match_dup 1) (match_dup 2)))]
1793 "! TARGET_POWER"
1794 "@
1795 {muls.|mullw.} %0,%1,%2
1796 #"
1797 [(set_attr "type" "imul_compare")
1798 (set_attr "length" "4,8")])
1800 (define_split
1801 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1802 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1803 (match_operand:SI 2 "gpc_reg_operand" ""))
1804 (const_int 0)))
1805 (set (match_operand:SI 0 "gpc_reg_operand" "")
1806 (mult:SI (match_dup 1) (match_dup 2)))]
1807 "! TARGET_POWER && reload_completed"
1808 [(set (match_dup 0)
1809 (mult:SI (match_dup 1) (match_dup 2)))
1810 (set (match_dup 3)
1811 (compare:CC (match_dup 0)
1812 (const_int 0)))]
1813 "")
1815 ;; Operand 1 is divided by operand 2; quotient goes to operand
1816 ;; 0 and remainder to operand 3.
1817 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1819 (define_expand "divmodsi4"
1820 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1821 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1822 (match_operand:SI 2 "gpc_reg_operand" "")))
1823 (set (match_operand:SI 3 "register_operand" "")
1824 (mod:SI (match_dup 1) (match_dup 2)))])]
1825 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1826 "
1827 {
1828 if (! TARGET_POWER && ! TARGET_POWERPC)
1829 {
1830 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1831 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1832 emit_insn (gen_divss_call ());
1833 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1834 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1835 DONE;
1836 }
1837 }")
1839 (define_insn "*divmodsi4_internal"
1840 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1841 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1842 (match_operand:SI 2 "gpc_reg_operand" "r")))
1843 (set (match_operand:SI 3 "register_operand" "=q")
1844 (mod:SI (match_dup 1) (match_dup 2)))]
1845 "TARGET_POWER"
1846 "divs %0,%1,%2"
1847 [(set_attr "type" "idiv")])
1849 (define_expand "udivsi3"
1850 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1851 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1852 (match_operand:SI 2 "gpc_reg_operand" "")))]
1853 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1854 "
1855 {
1856 if (! TARGET_POWER && ! TARGET_POWERPC)
1857 {
1858 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1859 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1860 emit_insn (gen_quous_call ());
1861 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1862 DONE;
1863 }
1864 else if (TARGET_POWER)
1865 {
1866 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1867 DONE;
1868 }
1869 }")
1871 (define_insn "udivsi3_mq"
1872 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1873 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1874 (match_operand:SI 2 "gpc_reg_operand" "r")))
1875 (clobber (match_scratch:SI 3 "=q"))]
1876 "TARGET_POWERPC && TARGET_POWER"
1877 "divwu %0,%1,%2"
1878 [(set_attr "type" "idiv")])
1880 (define_insn "*udivsi3_no_mq"
1881 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1882 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1883 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1884 "TARGET_POWERPC && ! TARGET_POWER"
1885 "divwu %0,%1,%2"
1886 [(set_attr "type" "idiv")])
1888 ;; For powers of two we can do srai/aze for divide and then adjust for
1889 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1890 ;; used; for PowerPC, force operands into register and do a normal divide;
1891 ;; for AIX common-mode, use quoss call on register operands.
1892 (define_expand "divsi3"
1893 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1894 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1895 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1896 ""
1897 "
1898 {
1899 if (GET_CODE (operands[2]) == CONST_INT
1900 && INTVAL (operands[2]) > 0
1901 && exact_log2 (INTVAL (operands[2])) >= 0)
1902 ;
1903 else if (TARGET_POWERPC)
1904 {
1905 operands[2] = force_reg (SImode, operands[2]);
1906 if (TARGET_POWER)
1907 {
1908 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1909 DONE;
1910 }
1911 }
1912 else if (TARGET_POWER)
1913 FAIL;
1914 else
1915 {
1916 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1917 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1918 emit_insn (gen_quoss_call ());
1919 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1920 DONE;
1921 }
1922 }")
1924 (define_insn "divsi3_mq"
1925 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1926 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1927 (match_operand:SI 2 "gpc_reg_operand" "r")))
1928 (clobber (match_scratch:SI 3 "=q"))]
1929 "TARGET_POWERPC && TARGET_POWER"
1930 "divw %0,%1,%2"
1931 [(set_attr "type" "idiv")])
1933 (define_insn "*divsi3_no_mq"
1934 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1935 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1936 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1937 "TARGET_POWERPC && ! TARGET_POWER"
1938 "divw %0,%1,%2"
1939 [(set_attr "type" "idiv")])
1941 (define_expand "modsi3"
1942 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1943 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1944 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1945 ""
1946 "
1947 {
1948 int i;
1949 rtx temp1;
1950 rtx temp2;
1952 if (GET_CODE (operands[2]) != CONST_INT
1953 || INTVAL (operands[2]) <= 0
1954 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1955 FAIL;
1957 temp1 = gen_reg_rtx (SImode);
1958 temp2 = gen_reg_rtx (SImode);
1960 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1961 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1962 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1963 DONE;
1964 }")
1966 (define_insn ""
1967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1968 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1969 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1970 ""
1971 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1972 [(set_attr "length" "8")])
1974 (define_insn ""
1975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1976 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1977 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1978 (const_int 0)))
1979 (clobber (match_scratch:SI 3 "=r,r"))]
1980 ""
1981 "@
1982 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1983 #"
1984 [(set_attr "type" "compare")
1985 (set_attr "length" "8,12")])
1987 (define_split
1988 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1989 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1990 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1991 (const_int 0)))
1992 (clobber (match_scratch:SI 3 ""))]
1993 "reload_completed"
1994 [(set (match_dup 3)
1995 (div:SI (match_dup 1) (match_dup 2)))
1996 (set (match_dup 0)
1997 (compare:CC (match_dup 3)
1998 (const_int 0)))]
1999 "")
2001 (define_insn ""
2002 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2003 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2004 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2005 (const_int 0)))
2006 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2007 (div:SI (match_dup 1) (match_dup 2)))]
2008 ""
2009 "@
2010 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2011 #"
2012 [(set_attr "type" "compare")
2013 (set_attr "length" "8,12")])
2015 (define_split
2016 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2017 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2018 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2019 (const_int 0)))
2020 (set (match_operand:SI 0 "gpc_reg_operand" "")
2021 (div:SI (match_dup 1) (match_dup 2)))]
2022 "reload_completed"
2023 [(set (match_dup 0)
2024 (div:SI (match_dup 1) (match_dup 2)))
2025 (set (match_dup 3)
2026 (compare:CC (match_dup 0)
2027 (const_int 0)))]
2028 "")
2030 (define_insn ""
2031 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2032 (udiv:SI
2033 (plus:DI (ashift:DI
2034 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2035 (const_int 32))
2036 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2037 (match_operand:SI 3 "gpc_reg_operand" "r")))
2038 (set (match_operand:SI 2 "register_operand" "=*q")
2039 (umod:SI
2040 (plus:DI (ashift:DI
2041 (zero_extend:DI (match_dup 1)) (const_int 32))
2042 (zero_extend:DI (match_dup 4)))
2043 (match_dup 3)))]
2044 "TARGET_POWER"
2045 "div %0,%1,%3"
2046 [(set_attr "type" "idiv")])
2048 ;; To do unsigned divide we handle the cases of the divisor looking like a
2049 ;; negative number. If it is a constant that is less than 2**31, we don't
2050 ;; have to worry about the branches. So make a few subroutines here.
2051 ;;
2052 ;; First comes the normal case.
2053 (define_expand "udivmodsi4_normal"
2054 [(set (match_dup 4) (const_int 0))
2055 (parallel [(set (match_operand:SI 0 "" "")
2056 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2057 (const_int 32))
2058 (zero_extend:DI (match_operand:SI 1 "" "")))
2059 (match_operand:SI 2 "" "")))
2060 (set (match_operand:SI 3 "" "")
2061 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2062 (const_int 32))
2063 (zero_extend:DI (match_dup 1)))
2064 (match_dup 2)))])]
2065 "TARGET_POWER"
2066 "
2067 { operands[4] = gen_reg_rtx (SImode); }")
2069 ;; This handles the branches.
2070 (define_expand "udivmodsi4_tests"
2071 [(set (match_operand:SI 0 "" "") (const_int 0))
2072 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2073 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2074 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2075 (label_ref (match_operand:SI 4 "" "")) (pc)))
2076 (set (match_dup 0) (const_int 1))
2077 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2078 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2079 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2080 (label_ref (match_dup 4)) (pc)))]
2081 "TARGET_POWER"
2082 "
2083 { operands[5] = gen_reg_rtx (CCUNSmode);
2084 operands[6] = gen_reg_rtx (CCmode);
2085 }")
2087 (define_expand "udivmodsi4"
2088 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2089 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2090 (match_operand:SI 2 "reg_or_cint_operand" "")))
2091 (set (match_operand:SI 3 "gpc_reg_operand" "")
2092 (umod:SI (match_dup 1) (match_dup 2)))])]
2093 ""
2094 "
2095 {
2096 rtx label = 0;
2098 if (! TARGET_POWER)
2099 {
2100 if (! TARGET_POWERPC)
2101 {
2102 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2103 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2104 emit_insn (gen_divus_call ());
2105 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2106 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2107 DONE;
2108 }
2109 else
2110 FAIL;
2111 }
2113 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2114 {
2115 operands[2] = force_reg (SImode, operands[2]);
2116 label = gen_label_rtx ();
2117 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2118 operands[3], label));
2119 }
2120 else
2121 operands[2] = force_reg (SImode, operands[2]);
2123 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2124 operands[3]));
2125 if (label)
2126 emit_label (label);
2128 DONE;
2129 }")
2131 ;; AIX architecture-independent common-mode multiply (DImode),
2132 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2133 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2134 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2135 ;; assumed unused if generating common-mode, so ignore.
2136 (define_insn "mulh_call"
2137 [(set (reg:SI 3)
2138 (truncate:SI
2139 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2140 (sign_extend:DI (reg:SI 4)))
2141 (const_int 32))))
2142 (clobber (match_scratch:SI 0 "=l"))]
2143 "! TARGET_POWER && ! TARGET_POWERPC"
2144 "bla __mulh"
2145 [(set_attr "type" "imul")])
2147 (define_insn "mull_call"
2148 [(set (reg:DI 3)
2149 (mult:DI (sign_extend:DI (reg:SI 3))
2150 (sign_extend:DI (reg:SI 4))))
2151 (clobber (match_scratch:SI 0 "=l"))
2152 (clobber (reg:SI 0))]
2153 "! TARGET_POWER && ! TARGET_POWERPC"
2154 "bla __mull"
2155 [(set_attr "type" "imul")])
2157 (define_insn "divss_call"
2158 [(set (reg:SI 3)
2159 (div:SI (reg:SI 3) (reg:SI 4)))
2160 (set (reg:SI 4)
2161 (mod:SI (reg:SI 3) (reg:SI 4)))
2162 (clobber (match_scratch:SI 0 "=l"))
2163 (clobber (reg:SI 0))]
2164 "! TARGET_POWER && ! TARGET_POWERPC"
2165 "bla __divss"
2166 [(set_attr "type" "idiv")])
2168 (define_insn "divus_call"
2169 [(set (reg:SI 3)
2170 (udiv:SI (reg:SI 3) (reg:SI 4)))
2171 (set (reg:SI 4)
2172 (umod:SI (reg:SI 3) (reg:SI 4)))
2173 (clobber (match_scratch:SI 0 "=l"))
2174 (clobber (reg:SI 0))
2175 (clobber (match_scratch:CC 1 "=x"))
2176 (clobber (reg:CC 69))]
2177 "! TARGET_POWER && ! TARGET_POWERPC"
2178 "bla __divus"
2179 [(set_attr "type" "idiv")])
2181 (define_insn "quoss_call"
2182 [(set (reg:SI 3)
2183 (div:SI (reg:SI 3) (reg:SI 4)))
2184 (clobber (match_scratch:SI 0 "=l"))]
2185 "! TARGET_POWER && ! TARGET_POWERPC"
2186 "bla __quoss"
2187 [(set_attr "type" "idiv")])
2189 (define_insn "quous_call"
2190 [(set (reg:SI 3)
2191 (udiv:SI (reg:SI 3) (reg:SI 4)))
2192 (clobber (match_scratch:SI 0 "=l"))
2193 (clobber (reg:SI 0))
2194 (clobber (match_scratch:CC 1 "=x"))
2195 (clobber (reg:CC 69))]
2196 "! TARGET_POWER && ! TARGET_POWERPC"
2197 "bla __quous"
2198 [(set_attr "type" "idiv")])
2199 \f
2200 ;; Logical instructions
2201 ;; The logical instructions are mostly combined by using match_operator,
2202 ;; but the plain AND insns are somewhat different because there is no
2203 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2204 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2206 (define_insn "andsi3"
2207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2208 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2209 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2210 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2211 ""
2212 "@
2213 and %0,%1,%2
2214 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2215 {andil.|andi.} %0,%1,%b2
2216 {andiu.|andis.} %0,%1,%u2")
2218 ;; Note to set cr's other than cr0 we do the and immediate and then
2219 ;; the test again -- this avoids a mfcr which on the higher end
2220 ;; machines causes an execution serialization
2222 (define_insn "*andsi3_internal2"
2223 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2224 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2225 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2226 (const_int 0)))
2227 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2228 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2229 "TARGET_32BIT"
2230 "@
2231 and. %3,%1,%2
2232 {andil.|andi.} %3,%1,%b2
2233 {andiu.|andis.} %3,%1,%u2
2234 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2235 #
2236 #
2237 #
2238 #"
2239 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2240 (set_attr "length" "4,4,4,4,8,8,8,8")])
2242 (define_insn "*andsi3_internal3"
2243 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2244 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2245 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2246 (const_int 0)))
2247 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2248 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2249 "TARGET_64BIT"
2250 "@
2251 #
2252 {andil.|andi.} %3,%1,%b2
2253 {andiu.|andis.} %3,%1,%u2
2254 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2255 #
2256 #
2257 #
2258 #"
2259 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2260 (set_attr "length" "8,4,4,4,8,8,8,8")])
2262 (define_split
2263 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2264 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2265 (match_operand:SI 2 "and_operand" ""))
2266 (const_int 0)))
2267 (clobber (match_scratch:SI 3 ""))
2268 (clobber (match_scratch:CC 4 ""))]
2269 "reload_completed"
2270 [(parallel [(set (match_dup 3)
2271 (and:SI (match_dup 1)
2272 (match_dup 2)))
2273 (clobber (match_dup 4))])
2274 (set (match_dup 0)
2275 (compare:CC (match_dup 3)
2276 (const_int 0)))]
2277 "")
2279 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2280 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2282 (define_split
2283 [(set (match_operand:CC 0 "cc_reg_operand" "")
2284 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2285 (match_operand:SI 2 "gpc_reg_operand" ""))
2286 (const_int 0)))
2287 (clobber (match_scratch:SI 3 ""))
2288 (clobber (match_scratch:CC 4 ""))]
2289 "TARGET_POWERPC64 && reload_completed"
2290 [(parallel [(set (match_dup 3)
2291 (and:SI (match_dup 1)
2292 (match_dup 2)))
2293 (clobber (match_dup 4))])
2294 (set (match_dup 0)
2295 (compare:CC (match_dup 3)
2296 (const_int 0)))]
2297 "")
2299 (define_insn "*andsi3_internal4"
2300 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2301 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2302 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2303 (const_int 0)))
2304 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2305 (and:SI (match_dup 1)
2306 (match_dup 2)))
2307 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2308 "TARGET_32BIT"
2309 "@
2310 and. %0,%1,%2
2311 {andil.|andi.} %0,%1,%b2
2312 {andiu.|andis.} %0,%1,%u2
2313 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2314 #
2315 #
2316 #
2317 #"
2318 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2319 (set_attr "length" "4,4,4,4,8,8,8,8")])
2321 (define_insn "*andsi3_internal5"
2322 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2323 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2324 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2325 (const_int 0)))
2326 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2327 (and:SI (match_dup 1)
2328 (match_dup 2)))
2329 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2330 "TARGET_64BIT"
2331 "@
2332 #
2333 {andil.|andi.} %0,%1,%b2
2334 {andiu.|andis.} %0,%1,%u2
2335 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2336 #
2337 #
2338 #
2339 #"
2340 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2341 (set_attr "length" "8,4,4,4,8,8,8,8")])
2343 (define_split
2344 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2345 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2346 (match_operand:SI 2 "and_operand" ""))
2347 (const_int 0)))
2348 (set (match_operand:SI 0 "gpc_reg_operand" "")
2349 (and:SI (match_dup 1)
2350 (match_dup 2)))
2351 (clobber (match_scratch:CC 4 ""))]
2352 "reload_completed"
2353 [(parallel [(set (match_dup 0)
2354 (and:SI (match_dup 1)
2355 (match_dup 2)))
2356 (clobber (match_dup 4))])
2357 (set (match_dup 3)
2358 (compare:CC (match_dup 0)
2359 (const_int 0)))]
2360 "")
2362 (define_split
2363 [(set (match_operand:CC 3 "cc_reg_operand" "")
2364 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2365 (match_operand:SI 2 "gpc_reg_operand" ""))
2366 (const_int 0)))
2367 (set (match_operand:SI 0 "gpc_reg_operand" "")
2368 (and:SI (match_dup 1)
2369 (match_dup 2)))
2370 (clobber (match_scratch:CC 4 ""))]
2371 "TARGET_POWERPC64 && reload_completed"
2372 [(parallel [(set (match_dup 0)
2373 (and:SI (match_dup 1)
2374 (match_dup 2)))
2375 (clobber (match_dup 4))])
2376 (set (match_dup 3)
2377 (compare:CC (match_dup 0)
2378 (const_int 0)))]
2379 "")
2381 ;; Handle the PowerPC64 rlwinm corner case
2383 (define_insn_and_split "*andsi3_internal6"
2384 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2385 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2386 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2387 "TARGET_POWERPC64"
2388 "#"
2389 "TARGET_POWERPC64"
2390 [(set (match_dup 0)
2391 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2392 (match_dup 4)))
2393 (set (match_dup 0)
2394 (rotate:SI (match_dup 0) (match_dup 5)))]
2395 "
2396 {
2397 int mb = extract_MB (operands[2]);
2398 int me = extract_ME (operands[2]);
2399 operands[3] = GEN_INT (me + 1);
2400 operands[5] = GEN_INT (32 - (me + 1));
2401 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2402 }"
2403 [(set_attr "length" "8")])
2405 (define_insn_and_split "*andsi3_internal7"
2406 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2407 (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
2408 (match_operand:SI 1 "mask_operand_wrap" "i,i"))
2409 (const_int 0)))
2410 (clobber (match_scratch:SI 3 "=r,r"))]
2411 "TARGET_POWERPC64"
2412 "#"
2413 "TARGET_POWERPC64"
2414 [(parallel [(set (match_dup 2)
2415 (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
2416 (match_dup 5))
2417 (const_int 0)))
2418 (clobber (match_dup 3))])]
2419 "
2420 {
2421 int mb = extract_MB (operands[1]);
2422 int me = extract_ME (operands[1]);
2423 operands[4] = GEN_INT (me + 1);
2424 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2425 }"
2426 [(set_attr "type" "delayed_compare,compare")
2427 (set_attr "length" "4,8")])
2429 (define_insn_and_split "*andsi3_internal8"
2430 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2431 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2432 (match_operand:SI 2 "mask_operand_wrap" "i,i"))
2433 (const_int 0)))
2434 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2435 (and:SI (match_dup 1)
2436 (match_dup 2)))]
2437 "TARGET_POWERPC64"
2438 "#"
2439 "TARGET_POWERPC64"
2440 [(parallel [(set (match_dup 3)
2441 (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2442 (match_dup 5))
2443 (const_int 0)))
2444 (set (match_dup 0)
2445 (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2446 (match_dup 5)))])
2447 (set (match_dup 0)
2448 (rotate:SI (match_dup 0) (match_dup 6)))]
2449 "
2450 {
2451 int mb = extract_MB (operands[2]);
2452 int me = extract_ME (operands[2]);
2453 operands[4] = GEN_INT (me + 1);
2454 operands[6] = GEN_INT (32 - (me + 1));
2455 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2456 }"
2457 [(set_attr "type" "delayed_compare,compare")
2458 (set_attr "length" "8,12")])
2460 (define_expand "iorsi3"
2461 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2462 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2463 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2464 ""
2465 "
2466 {
2467 if (GET_CODE (operands[2]) == CONST_INT
2468 && ! logical_operand (operands[2], SImode))
2469 {
2470 HOST_WIDE_INT value = INTVAL (operands[2]);
2471 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2472 ? operands[0] : gen_reg_rtx (SImode));
2474 emit_insn (gen_iorsi3 (tmp, operands[1],
2475 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2476 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2477 DONE;
2478 }
2479 }")
2481 (define_expand "xorsi3"
2482 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2483 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2484 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2485 ""
2486 "
2487 {
2488 if (GET_CODE (operands[2]) == CONST_INT
2489 && ! logical_operand (operands[2], SImode))
2490 {
2491 HOST_WIDE_INT value = INTVAL (operands[2]);
2492 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2493 ? operands[0] : gen_reg_rtx (SImode));
2495 emit_insn (gen_xorsi3 (tmp, operands[1],
2496 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2497 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2498 DONE;
2499 }
2500 }")
2502 (define_insn "*boolsi3_internal1"
2503 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2504 (match_operator:SI 3 "boolean_or_operator"
2505 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2506 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2507 ""
2508 "@
2509 %q3 %0,%1,%2
2510 {%q3il|%q3i} %0,%1,%b2
2511 {%q3iu|%q3is} %0,%1,%u2")
2513 (define_insn "*boolsi3_internal2"
2514 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2515 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2516 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2517 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2518 (const_int 0)))
2519 (clobber (match_scratch:SI 3 "=r,r"))]
2520 "TARGET_32BIT"
2521 "@
2522 %q4. %3,%1,%2
2523 #"
2524 [(set_attr "type" "compare")
2525 (set_attr "length" "4,8")])
2527 (define_split
2528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2529 (compare:CC (match_operator:SI 4 "boolean_operator"
2530 [(match_operand:SI 1 "gpc_reg_operand" "")
2531 (match_operand:SI 2 "gpc_reg_operand" "")])
2532 (const_int 0)))
2533 (clobber (match_scratch:SI 3 ""))]
2534 "TARGET_32BIT && reload_completed"
2535 [(set (match_dup 3) (match_dup 4))
2536 (set (match_dup 0)
2537 (compare:CC (match_dup 3)
2538 (const_int 0)))]
2539 "")
2541 (define_insn "*boolsi3_internal3"
2542 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2543 (compare:CC (match_operator:SI 4 "boolean_operator"
2544 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2545 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2546 (const_int 0)))
2547 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2548 (match_dup 4))]
2549 "TARGET_32BIT"
2550 "@
2551 %q4. %0,%1,%2
2552 #"
2553 [(set_attr "type" "compare")
2554 (set_attr "length" "4,8")])
2556 (define_split
2557 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2558 (compare:CC (match_operator:SI 4 "boolean_operator"
2559 [(match_operand:SI 1 "gpc_reg_operand" "")
2560 (match_operand:SI 2 "gpc_reg_operand" "")])
2561 (const_int 0)))
2562 (set (match_operand:SI 0 "gpc_reg_operand" "")
2563 (match_dup 4))]
2564 "TARGET_32BIT && reload_completed"
2565 [(set (match_dup 0) (match_dup 4))
2566 (set (match_dup 3)
2567 (compare:CC (match_dup 0)
2568 (const_int 0)))]
2569 "")
2571 ;; Split a logical operation that we can't do in one insn into two insns,
2572 ;; each of which does one 16-bit part. This is used by combine.
2574 (define_split
2575 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2576 (match_operator:SI 3 "boolean_or_operator"
2577 [(match_operand:SI 1 "gpc_reg_operand" "")
2578 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2579 ""
2580 [(set (match_dup 0) (match_dup 4))
2581 (set (match_dup 0) (match_dup 5))]
2582 "
2583 {
2584 rtx i;
2585 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2586 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
2587 operands[1], i);
2588 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2589 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
2590 operands[0], i);
2591 }")
2593 (define_insn "*boolcsi3_internal1"
2594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2595 (match_operator:SI 3 "boolean_operator"
2596 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2597 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2598 ""
2599 "%q3 %0,%2,%1")
2601 (define_insn "*boolcsi3_internal2"
2602 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2603 (compare:CC (match_operator:SI 4 "boolean_operator"
2604 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2605 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2606 (const_int 0)))
2607 (clobber (match_scratch:SI 3 "=r,r"))]
2608 "TARGET_32BIT"
2609 "@
2610 %q4. %3,%2,%1
2611 #"
2612 [(set_attr "type" "compare")
2613 (set_attr "length" "4,8")])
2615 (define_split
2616 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2617 (compare:CC (match_operator:SI 4 "boolean_operator"
2618 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2619 (match_operand:SI 2 "gpc_reg_operand" "")])
2620 (const_int 0)))
2621 (clobber (match_scratch:SI 3 ""))]
2622 "TARGET_32BIT && reload_completed"
2623 [(set (match_dup 3) (match_dup 4))
2624 (set (match_dup 0)
2625 (compare:CC (match_dup 3)
2626 (const_int 0)))]
2627 "")
2629 (define_insn "*boolcsi3_internal3"
2630 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2631 (compare:CC (match_operator:SI 4 "boolean_operator"
2632 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2633 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2634 (const_int 0)))
2635 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2636 (match_dup 4))]
2637 "TARGET_32BIT"
2638 "@
2639 %q4. %0,%2,%1
2640 #"
2641 [(set_attr "type" "compare")
2642 (set_attr "length" "4,8")])
2644 (define_split
2645 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2646 (compare:CC (match_operator:SI 4 "boolean_operator"
2647 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2648 (match_operand:SI 2 "gpc_reg_operand" "")])
2649 (const_int 0)))
2650 (set (match_operand:SI 0 "gpc_reg_operand" "")
2651 (match_dup 4))]
2652 "TARGET_32BIT && reload_completed"
2653 [(set (match_dup 0) (match_dup 4))
2654 (set (match_dup 3)
2655 (compare:CC (match_dup 0)
2656 (const_int 0)))]
2657 "")
2659 (define_insn "*boolccsi3_internal1"
2660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2661 (match_operator:SI 3 "boolean_operator"
2662 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2663 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2664 ""
2665 "%q3 %0,%1,%2")
2667 (define_insn "*boolccsi3_internal2"
2668 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2669 (compare:CC (match_operator:SI 4 "boolean_operator"
2670 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2671 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2672 (const_int 0)))
2673 (clobber (match_scratch:SI 3 "=r,r"))]
2674 "TARGET_32BIT"
2675 "@
2676 %q4. %3,%1,%2
2677 #"
2678 [(set_attr "type" "compare")
2679 (set_attr "length" "4,8")])
2681 (define_split
2682 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2683 (compare:CC (match_operator:SI 4 "boolean_operator"
2684 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2685 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2686 (const_int 0)))
2687 (clobber (match_scratch:SI 3 ""))]
2688 "TARGET_32BIT && reload_completed"
2689 [(set (match_dup 3) (match_dup 4))
2690 (set (match_dup 0)
2691 (compare:CC (match_dup 3)
2692 (const_int 0)))]
2693 "")
2695 (define_insn "*boolccsi3_internal3"
2696 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2697 (compare:CC (match_operator:SI 4 "boolean_operator"
2698 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2699 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2700 (const_int 0)))
2701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2702 (match_dup 4))]
2703 "TARGET_32BIT"
2704 "@
2705 %q4. %0,%1,%2
2706 #"
2707 [(set_attr "type" "compare")
2708 (set_attr "length" "4,8")])
2710 (define_split
2711 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2712 (compare:CC (match_operator:SI 4 "boolean_operator"
2713 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2714 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2715 (const_int 0)))
2716 (set (match_operand:SI 0 "gpc_reg_operand" "")
2717 (match_dup 4))]
2718 "TARGET_32BIT && reload_completed"
2719 [(set (match_dup 0) (match_dup 4))
2720 (set (match_dup 3)
2721 (compare:CC (match_dup 0)
2722 (const_int 0)))]
2723 "")
2725 ;; maskir insn. We need four forms because things might be in arbitrary
2726 ;; orders. Don't define forms that only set CR fields because these
2727 ;; would modify an input register.
2729 (define_insn "*maskir_internal1"
2730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2731 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2732 (match_operand:SI 1 "gpc_reg_operand" "0"))
2733 (and:SI (match_dup 2)
2734 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2735 "TARGET_POWER"
2736 "maskir %0,%3,%2")
2738 (define_insn "*maskir_internal2"
2739 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2740 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2741 (match_operand:SI 1 "gpc_reg_operand" "0"))
2742 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2743 (match_dup 2))))]
2744 "TARGET_POWER"
2745 "maskir %0,%3,%2")
2747 (define_insn "*maskir_internal3"
2748 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2749 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2750 (match_operand:SI 3 "gpc_reg_operand" "r"))
2751 (and:SI (not:SI (match_dup 2))
2752 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2753 "TARGET_POWER"
2754 "maskir %0,%3,%2")
2756 (define_insn "*maskir_internal4"
2757 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2758 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2759 (match_operand:SI 2 "gpc_reg_operand" "r"))
2760 (and:SI (not:SI (match_dup 2))
2761 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2762 "TARGET_POWER"
2763 "maskir %0,%3,%2")
2765 (define_insn "*maskir_internal5"
2766 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2767 (compare:CC
2768 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2769 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2770 (and:SI (match_dup 2)
2771 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2772 (const_int 0)))
2773 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2774 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2775 (and:SI (match_dup 2) (match_dup 3))))]
2776 "TARGET_POWER"
2777 "@
2778 maskir. %0,%3,%2
2779 #"
2780 [(set_attr "type" "compare")
2781 (set_attr "length" "4,8")])
2783 (define_split
2784 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2785 (compare:CC
2786 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2787 (match_operand:SI 1 "gpc_reg_operand" ""))
2788 (and:SI (match_dup 2)
2789 (match_operand:SI 3 "gpc_reg_operand" "")))
2790 (const_int 0)))
2791 (set (match_operand:SI 0 "gpc_reg_operand" "")
2792 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2793 (and:SI (match_dup 2) (match_dup 3))))]
2794 "TARGET_POWER && reload_completed"
2795 [(set (match_dup 0)
2796 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2797 (and:SI (match_dup 2) (match_dup 3))))
2798 (set (match_dup 4)
2799 (compare:CC (match_dup 0)
2800 (const_int 0)))]
2801 "")
2803 (define_insn "*maskir_internal6"
2804 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2805 (compare:CC
2806 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2807 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2808 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2809 (match_dup 2)))
2810 (const_int 0)))
2811 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2812 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2813 (and:SI (match_dup 3) (match_dup 2))))]
2814 "TARGET_POWER"
2815 "@
2816 maskir. %0,%3,%2
2817 #"
2818 [(set_attr "type" "compare")
2819 (set_attr "length" "4,8")])
2821 (define_split
2822 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2823 (compare:CC
2824 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2825 (match_operand:SI 1 "gpc_reg_operand" ""))
2826 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2827 (match_dup 2)))
2828 (const_int 0)))
2829 (set (match_operand:SI 0 "gpc_reg_operand" "")
2830 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2831 (and:SI (match_dup 3) (match_dup 2))))]
2832 "TARGET_POWER && reload_completed"
2833 [(set (match_dup 0)
2834 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2835 (and:SI (match_dup 3) (match_dup 2))))
2836 (set (match_dup 4)
2837 (compare:CC (match_dup 0)
2838 (const_int 0)))]
2839 "")
2841 (define_insn "*maskir_internal7"
2842 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2843 (compare:CC
2844 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2845 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2846 (and:SI (not:SI (match_dup 2))
2847 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2848 (const_int 0)))
2849 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2850 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2851 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2852 "TARGET_POWER"
2853 "@
2854 maskir. %0,%3,%2
2855 #"
2856 [(set_attr "type" "compare")
2857 (set_attr "length" "4,8")])
2859 (define_split
2860 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2861 (compare:CC
2862 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2863 (match_operand:SI 3 "gpc_reg_operand" ""))
2864 (and:SI (not:SI (match_dup 2))
2865 (match_operand:SI 1 "gpc_reg_operand" "")))
2866 (const_int 0)))
2867 (set (match_operand:SI 0 "gpc_reg_operand" "")
2868 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2869 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2870 "TARGET_POWER && reload_completed"
2871 [(set (match_dup 0)
2872 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2873 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2874 (set (match_dup 4)
2875 (compare:CC (match_dup 0)
2876 (const_int 0)))]
2877 "")
2879 (define_insn "*maskir_internal8"
2880 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2881 (compare:CC
2882 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2883 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2884 (and:SI (not:SI (match_dup 2))
2885 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2886 (const_int 0)))
2887 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2888 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2889 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2890 "TARGET_POWER"
2891 "@
2892 maskir. %0,%3,%2
2893 #"
2894 [(set_attr "type" "compare")
2895 (set_attr "length" "4,8")])
2897 (define_split
2898 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2899 (compare:CC
2900 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2901 (match_operand:SI 2 "gpc_reg_operand" ""))
2902 (and:SI (not:SI (match_dup 2))
2903 (match_operand:SI 1 "gpc_reg_operand" "")))
2904 (const_int 0)))
2905 (set (match_operand:SI 0 "gpc_reg_operand" "")
2906 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2907 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2908 "TARGET_POWER && reload_completed"
2909 [(set (match_dup 0)
2910 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2911 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2912 (set (match_dup 4)
2913 (compare:CC (match_dup 0)
2914 (const_int 0)))]
2915 "")
2916 \f
2917 ;; Rotate and shift insns, in all their variants. These support shifts,
2918 ;; field inserts and extracts, and various combinations thereof.
2919 (define_expand "insv"
2920 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2921 (match_operand:SI 1 "const_int_operand" "")
2922 (match_operand:SI 2 "const_int_operand" ""))
2923 (match_operand 3 "gpc_reg_operand" ""))]
2924 ""
2925 "
2926 {
2927 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2928 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2929 compiler if the address of the structure is taken later. */
2930 if (GET_CODE (operands[0]) == SUBREG
2931 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2932 FAIL;
2934 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2935 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2936 else
2937 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2938 DONE;
2939 }")
2941 (define_insn "insvsi"
2942 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2943 (match_operand:SI 1 "const_int_operand" "i")
2944 (match_operand:SI 2 "const_int_operand" "i"))
2945 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2946 ""
2947 "*
2948 {
2949 int start = INTVAL (operands[2]) & 31;
2950 int size = INTVAL (operands[1]) & 31;
2952 operands[4] = GEN_INT (32 - start - size);
2953 operands[1] = GEN_INT (start + size - 1);
2954 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2955 }"
2956 [(set_attr "type" "insert_word")])
2958 (define_insn "*insvsi_internal1"
2959 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2960 (match_operand:SI 1 "const_int_operand" "i")
2961 (match_operand:SI 2 "const_int_operand" "i"))
2962 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2963 (match_operand:SI 4 "const_int_operand" "i")))]
2964 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2965 "*
2966 {
2967 int shift = INTVAL (operands[4]) & 31;
2968 int start = INTVAL (operands[2]) & 31;
2969 int size = INTVAL (operands[1]) & 31;
2971 operands[4] = GEN_INT (shift - start - size);
2972 operands[1] = GEN_INT (start + size - 1);
2973 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2974 }"
2975 [(set_attr "type" "insert_word")])
2977 (define_insn "*insvsi_internal2"
2978 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2979 (match_operand:SI 1 "const_int_operand" "i")
2980 (match_operand:SI 2 "const_int_operand" "i"))
2981 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2982 (match_operand:SI 4 "const_int_operand" "i")))]
2983 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2984 "*
2985 {
2986 int shift = INTVAL (operands[4]) & 31;
2987 int start = INTVAL (operands[2]) & 31;
2988 int size = INTVAL (operands[1]) & 31;
2990 operands[4] = GEN_INT (32 - shift - start - size);
2991 operands[1] = GEN_INT (start + size - 1);
2992 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2993 }"
2994 [(set_attr "type" "insert_word")])
2996 (define_insn "*insvsi_internal3"
2997 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2998 (match_operand:SI 1 "const_int_operand" "i")
2999 (match_operand:SI 2 "const_int_operand" "i"))
3000 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3001 (match_operand:SI 4 "const_int_operand" "i")))]
3002 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3003 "*
3004 {
3005 int shift = INTVAL (operands[4]) & 31;
3006 int start = INTVAL (operands[2]) & 31;
3007 int size = INTVAL (operands[1]) & 31;
3009 operands[4] = GEN_INT (32 - shift - start - size);
3010 operands[1] = GEN_INT (start + size - 1);
3011 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3012 }"
3013 [(set_attr "type" "insert_word")])
3015 (define_insn "*insvsi_internal4"
3016 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3017 (match_operand:SI 1 "const_int_operand" "i")
3018 (match_operand:SI 2 "const_int_operand" "i"))
3019 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3020 (match_operand:SI 4 "const_int_operand" "i")
3021 (match_operand:SI 5 "const_int_operand" "i")))]
3022 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3023 "*
3024 {
3025 int extract_start = INTVAL (operands[5]) & 31;
3026 int extract_size = INTVAL (operands[4]) & 31;
3027 int insert_start = INTVAL (operands[2]) & 31;
3028 int insert_size = INTVAL (operands[1]) & 31;
3030 /* Align extract field with insert field */
3031 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3032 operands[1] = GEN_INT (insert_start + insert_size - 1);
3033 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3034 }"
3035 [(set_attr "type" "insert_word")])
3037 (define_insn "insvdi"
3038 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3039 (match_operand:SI 1 "const_int_operand" "i")
3040 (match_operand:SI 2 "const_int_operand" "i"))
3041 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3042 "TARGET_POWERPC64"
3043 "*
3044 {
3045 int start = INTVAL (operands[2]) & 63;
3046 int size = INTVAL (operands[1]) & 63;
3048 operands[1] = GEN_INT (64 - start - size);
3049 return \"rldimi %0,%3,%H1,%H2\";
3050 }")
3052 (define_expand "extzv"
3053 [(set (match_operand 0 "gpc_reg_operand" "")
3054 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3055 (match_operand:SI 2 "const_int_operand" "")
3056 (match_operand:SI 3 "const_int_operand" "")))]
3057 ""
3058 "
3059 {
3060 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3061 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3062 compiler if the address of the structure is taken later. */
3063 if (GET_CODE (operands[0]) == SUBREG
3064 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3065 FAIL;
3067 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3068 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3069 else
3070 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3071 DONE;
3072 }")
3074 (define_insn "extzvsi"
3075 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3076 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3077 (match_operand:SI 2 "const_int_operand" "i")
3078 (match_operand:SI 3 "const_int_operand" "i")))]
3079 ""
3080 "*
3081 {
3082 int start = INTVAL (operands[3]) & 31;
3083 int size = INTVAL (operands[2]) & 31;
3085 if (start + size >= 32)
3086 operands[3] = const0_rtx;
3087 else
3088 operands[3] = GEN_INT (start + size);
3089 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3090 }")
3092 (define_insn "*extzvsi_internal1"
3093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3094 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3095 (match_operand:SI 2 "const_int_operand" "i,i")
3096 (match_operand:SI 3 "const_int_operand" "i,i"))
3097 (const_int 0)))
3098 (clobber (match_scratch:SI 4 "=r,r"))]
3099 ""
3100 "*
3101 {
3102 int start = INTVAL (operands[3]) & 31;
3103 int size = INTVAL (operands[2]) & 31;
3105 /* Force split for non-cc0 compare. */
3106 if (which_alternative == 1)
3107 return \"#\";
3109 /* If the bit-field being tested fits in the upper or lower half of a
3110 word, it is possible to use andiu. or andil. to test it. This is
3111 useful because the condition register set-use delay is smaller for
3112 andi[ul]. than for rlinm. This doesn't work when the starting bit
3113 position is 0 because the LT and GT bits may be set wrong. */
3115 if ((start > 0 && start + size <= 16) || start >= 16)
3116 {
3117 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3118 - (1 << (16 - (start & 15) - size))));
3119 if (start < 16)
3120 return \"{andiu.|andis.} %4,%1,%3\";
3121 else
3122 return \"{andil.|andi.} %4,%1,%3\";
3123 }
3125 if (start + size >= 32)
3126 operands[3] = const0_rtx;
3127 else
3128 operands[3] = GEN_INT (start + size);
3129 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3130 }"
3131 [(set_attr "type" "compare")
3132 (set_attr "length" "4,8")])
3134 (define_split
3135 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3136 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3137 (match_operand:SI 2 "const_int_operand" "")
3138 (match_operand:SI 3 "const_int_operand" ""))
3139 (const_int 0)))
3140 (clobber (match_scratch:SI 4 ""))]
3141 "reload_completed"
3142 [(set (match_dup 4)
3143 (zero_extract:SI (match_dup 1) (match_dup 2)
3144 (match_dup 3)))
3145 (set (match_dup 0)
3146 (compare:CC (match_dup 4)
3147 (const_int 0)))]
3148 "")
3150 (define_insn "*extzvsi_internal2"
3151 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3152 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3153 (match_operand:SI 2 "const_int_operand" "i,i")
3154 (match_operand:SI 3 "const_int_operand" "i,i"))
3155 (const_int 0)))
3156 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3157 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3158 ""
3159 "*
3160 {
3161 int start = INTVAL (operands[3]) & 31;
3162 int size = INTVAL (operands[2]) & 31;
3164 /* Force split for non-cc0 compare. */
3165 if (which_alternative == 1)
3166 return \"#\";
3168 /* Since we are using the output value, we can't ignore any need for
3169 a shift. The bit-field must end at the LSB. */
3170 if (start >= 16 && start + size == 32)
3171 {
3172 operands[3] = GEN_INT ((1 << size) - 1);
3173 return \"{andil.|andi.} %0,%1,%3\";
3174 }
3176 if (start + size >= 32)
3177 operands[3] = const0_rtx;
3178 else
3179 operands[3] = GEN_INT (start + size);
3180 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3181 }"
3182 [(set_attr "type" "compare")
3183 (set_attr "length" "4,8")])
3185 (define_split
3186 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3187 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3188 (match_operand:SI 2 "const_int_operand" "")
3189 (match_operand:SI 3 "const_int_operand" ""))
3190 (const_int 0)))
3191 (set (match_operand:SI 0 "gpc_reg_operand" "")
3192 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3193 "reload_completed"
3194 [(set (match_dup 0)
3195 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3196 (set (match_dup 4)
3197 (compare:CC (match_dup 0)
3198 (const_int 0)))]
3199 "")
3201 (define_insn "extzvdi"
3202 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3203 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3204 (match_operand:SI 2 "const_int_operand" "i")
3205 (match_operand:SI 3 "const_int_operand" "i")))]
3206 "TARGET_POWERPC64"
3207 "*
3208 {
3209 int start = INTVAL (operands[3]) & 63;
3210 int size = INTVAL (operands[2]) & 63;
3212 if (start + size >= 64)
3213 operands[3] = const0_rtx;
3214 else
3215 operands[3] = GEN_INT (start + size);
3216 operands[2] = GEN_INT (64 - size);
3217 return \"rldicl %0,%1,%3,%2\";
3218 }")
3220 (define_insn "*extzvdi_internal1"
3221 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3222 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3223 (match_operand:SI 2 "const_int_operand" "i")
3224 (match_operand:SI 3 "const_int_operand" "i"))
3225 (const_int 0)))
3226 (clobber (match_scratch:DI 4 "=r"))]
3227 "TARGET_64BIT"
3228 "*
3229 {
3230 int start = INTVAL (operands[3]) & 63;
3231 int size = INTVAL (operands[2]) & 63;
3233 if (start + size >= 64)
3234 operands[3] = const0_rtx;
3235 else
3236 operands[3] = GEN_INT (start + size);
3237 operands[2] = GEN_INT (64 - size);
3238 return \"rldicl. %4,%1,%3,%2\";
3239 }")
3241 (define_insn "*extzvdi_internal2"
3242 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3243 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3244 (match_operand:SI 2 "const_int_operand" "i")
3245 (match_operand:SI 3 "const_int_operand" "i"))
3246 (const_int 0)))
3247 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3248 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3249 "TARGET_64BIT"
3250 "*
3251 {
3252 int start = INTVAL (operands[3]) & 63;
3253 int size = INTVAL (operands[2]) & 63;
3255 if (start + size >= 64)
3256 operands[3] = const0_rtx;
3257 else
3258 operands[3] = GEN_INT (start + size);
3259 operands[2] = GEN_INT (64 - size);
3260 return \"rldicl. %0,%1,%3,%2\";
3261 }")
3263 (define_insn "rotlsi3"
3264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3265 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3266 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3267 ""
3268 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3270 (define_insn "*rotlsi3_internal2"
3271 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3272 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3273 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3274 (const_int 0)))
3275 (clobber (match_scratch:SI 3 "=r,r"))]
3276 ""
3277 "@
3278 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3279 #"
3280 [(set_attr "type" "delayed_compare")
3281 (set_attr "length" "4,8")])
3283 (define_split
3284 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3285 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3286 (match_operand:SI 2 "reg_or_cint_operand" ""))
3287 (const_int 0)))
3288 (clobber (match_scratch:SI 3 ""))]
3289 "reload_completed"
3290 [(set (match_dup 3)
3291 (rotate:SI (match_dup 1) (match_dup 2)))
3292 (set (match_dup 0)
3293 (compare:CC (match_dup 3)
3294 (const_int 0)))]
3295 "")
3297 (define_insn "*rotlsi3_internal3"
3298 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3299 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3300 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3301 (const_int 0)))
3302 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3303 (rotate:SI (match_dup 1) (match_dup 2)))]
3304 ""
3305 "@
3306 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3307 #"
3308 [(set_attr "type" "delayed_compare")
3309 (set_attr "length" "4,8")])
3311 (define_split
3312 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3313 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3314 (match_operand:SI 2 "reg_or_cint_operand" ""))
3315 (const_int 0)))
3316 (set (match_operand:SI 0 "gpc_reg_operand" "")
3317 (rotate:SI (match_dup 1) (match_dup 2)))]
3318 "reload_completed"
3319 [(set (match_dup 0)
3320 (rotate:SI (match_dup 1) (match_dup 2)))
3321 (set (match_dup 3)
3322 (compare:CC (match_dup 0)
3323 (const_int 0)))]
3324 "")
3326 (define_insn "*rotlsi3_internal4"
3327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3328 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3329 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3330 (match_operand:SI 3 "mask_operand" "n")))]
3331 ""
3332 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3334 (define_insn "*rotlsi3_internal5"
3335 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3336 (compare:CC (and:SI
3337 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3338 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3339 (match_operand:SI 3 "mask_operand" "n,n"))
3340 (const_int 0)))
3341 (clobber (match_scratch:SI 4 "=r,r"))]
3342 ""
3343 "@
3344 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3345 #"
3346 [(set_attr "type" "delayed_compare")
3347 (set_attr "length" "4,8")])
3349 (define_split
3350 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3351 (compare:CC (and:SI
3352 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3353 (match_operand:SI 2 "reg_or_cint_operand" ""))
3354 (match_operand:SI 3 "mask_operand" ""))
3355 (const_int 0)))
3356 (clobber (match_scratch:SI 4 ""))]
3357 "reload_completed"
3358 [(set (match_dup 4)
3359 (and:SI (rotate:SI (match_dup 1)
3360 (match_dup 2))
3361 (match_dup 3)))
3362 (set (match_dup 0)
3363 (compare:CC (match_dup 4)
3364 (const_int 0)))]
3365 "")
3367 (define_insn "*rotlsi3_internal6"
3368 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3369 (compare:CC (and:SI
3370 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3371 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3372 (match_operand:SI 3 "mask_operand" "n,n"))
3373 (const_int 0)))
3374 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3375 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3376 ""
3377 "@
3378 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3379 #"
3380 [(set_attr "type" "delayed_compare")
3381 (set_attr "length" "4,8")])
3383 (define_split
3384 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3385 (compare:CC (and:SI
3386 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3387 (match_operand:SI 2 "reg_or_cint_operand" ""))
3388 (match_operand:SI 3 "mask_operand" ""))
3389 (const_int 0)))
3390 (set (match_operand:SI 0 "gpc_reg_operand" "")
3391 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3392 "reload_completed"
3393 [(set (match_dup 0)
3394 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3395 (set (match_dup 4)
3396 (compare:CC (match_dup 0)
3397 (const_int 0)))]
3398 "")
3400 (define_insn "*rotlsi3_internal7"
3401 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3402 (zero_extend:SI
3403 (subreg:QI
3404 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3405 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3406 ""
3407 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3409 (define_insn "*rotlsi3_internal8"
3410 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3411 (compare:CC (zero_extend:SI
3412 (subreg:QI
3413 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3414 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3415 (const_int 0)))
3416 (clobber (match_scratch:SI 3 "=r,r"))]
3417 ""
3418 "@
3419 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3420 #"
3421 [(set_attr "type" "delayed_compare")
3422 (set_attr "length" "4,8")])
3424 (define_split
3425 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3426 (compare:CC (zero_extend:SI
3427 (subreg:QI
3428 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3429 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3430 (const_int 0)))
3431 (clobber (match_scratch:SI 3 ""))]
3432 "reload_completed"
3433 [(set (match_dup 3)
3434 (zero_extend:SI (subreg:QI
3435 (rotate:SI (match_dup 1)
3436 (match_dup 2)) 0)))
3437 (set (match_dup 0)
3438 (compare:CC (match_dup 3)
3439 (const_int 0)))]
3440 "")
3442 (define_insn "*rotlsi3_internal9"
3443 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3444 (compare:CC (zero_extend:SI
3445 (subreg:QI
3446 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3447 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3448 (const_int 0)))
3449 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3450 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3451 ""
3452 "@
3453 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3454 #"
3455 [(set_attr "type" "delayed_compare")
3456 (set_attr "length" "4,8")])
3458 (define_split
3459 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3460 (compare:CC (zero_extend:SI
3461 (subreg:QI
3462 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3463 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3464 (const_int 0)))
3465 (set (match_operand:SI 0 "gpc_reg_operand" "")
3466 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3467 "reload_completed"
3468 [(set (match_dup 0)
3469 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3470 (set (match_dup 3)
3471 (compare:CC (match_dup 0)
3472 (const_int 0)))]
3473 "")
3475 (define_insn "*rotlsi3_internal10"
3476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3477 (zero_extend:SI
3478 (subreg:HI
3479 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3480 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3481 ""
3482 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3484 (define_insn "*rotlsi3_internal11"
3485 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3486 (compare:CC (zero_extend:SI
3487 (subreg:HI
3488 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3489 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3490 (const_int 0)))
3491 (clobber (match_scratch:SI 3 "=r,r"))]
3492 ""
3493 "@
3494 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3495 #"
3496 [(set_attr "type" "delayed_compare")
3497 (set_attr "length" "4,8")])
3499 (define_split
3500 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3501 (compare:CC (zero_extend:SI
3502 (subreg:HI
3503 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3504 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3505 (const_int 0)))
3506 (clobber (match_scratch:SI 3 ""))]
3507 "reload_completed"
3508 [(set (match_dup 3)
3509 (zero_extend:SI (subreg:HI
3510 (rotate:SI (match_dup 1)
3511 (match_dup 2)) 0)))
3512 (set (match_dup 0)
3513 (compare:CC (match_dup 3)
3514 (const_int 0)))]
3515 "")
3517 (define_insn "*rotlsi3_internal12"
3518 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3519 (compare:CC (zero_extend:SI
3520 (subreg:HI
3521 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3522 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3523 (const_int 0)))
3524 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3525 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3526 ""
3527 "@
3528 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3529 #"
3530 [(set_attr "type" "delayed_compare")
3531 (set_attr "length" "4,8")])
3533 (define_split
3534 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3535 (compare:CC (zero_extend:SI
3536 (subreg:HI
3537 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3538 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3539 (const_int 0)))
3540 (set (match_operand:SI 0 "gpc_reg_operand" "")
3541 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3542 "reload_completed"
3543 [(set (match_dup 0)
3544 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3545 (set (match_dup 3)
3546 (compare:CC (match_dup 0)
3547 (const_int 0)))]
3548 "")
3550 ;; Note that we use "sle." instead of "sl." so that we can set
3551 ;; SHIFT_COUNT_TRUNCATED.
3553 (define_expand "ashlsi3"
3554 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3555 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3556 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3557 ""
3558 "
3559 {
3560 if (TARGET_POWER)
3561 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3562 else
3563 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3564 DONE;
3565 }")
3567 (define_insn "ashlsi3_power"
3568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3569 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3570 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3571 (clobber (match_scratch:SI 3 "=q,X"))]
3572 "TARGET_POWER"
3573 "@
3574 sle %0,%1,%2
3575 {sli|slwi} %0,%1,%h2")
3577 (define_insn "ashlsi3_no_power"
3578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3579 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3580 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3581 "! TARGET_POWER"
3582 "{sl|slw}%I2 %0,%1,%h2")
3584 (define_insn ""
3585 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3586 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3587 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3588 (const_int 0)))
3589 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3590 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3591 "TARGET_POWER"
3592 "@
3593 sle. %3,%1,%2
3594 {sli.|slwi.} %3,%1,%h2
3595 #
3596 #"
3597 [(set_attr "type" "delayed_compare")
3598 (set_attr "length" "4,4,8,8")])
3600 (define_split
3601 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3602 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3603 (match_operand:SI 2 "reg_or_cint_operand" ""))
3604 (const_int 0)))
3605 (clobber (match_scratch:SI 3 ""))
3606 (clobber (match_scratch:SI 4 ""))]
3607 "TARGET_POWER && reload_completed"
3608 [(parallel [(set (match_dup 3)
3609 (ashift:SI (match_dup 1) (match_dup 2)))
3610 (clobber (match_dup 4))])
3611 (set (match_dup 0)
3612 (compare:CC (match_dup 3)
3613 (const_int 0)))]
3614 "")
3616 (define_insn ""
3617 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3618 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3619 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3620 (const_int 0)))
3621 (clobber (match_scratch:SI 3 "=r,r"))]
3622 "! TARGET_POWER && TARGET_32BIT"
3623 "@
3624 {sl|slw}%I2. %3,%1,%h2
3625 #"
3626 [(set_attr "type" "delayed_compare")
3627 (set_attr "length" "4,8")])
3629 (define_split
3630 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3631 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3632 (match_operand:SI 2 "reg_or_cint_operand" ""))
3633 (const_int 0)))
3634 (clobber (match_scratch:SI 3 ""))]
3635 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3636 [(set (match_dup 3)
3637 (ashift:SI (match_dup 1) (match_dup 2)))
3638 (set (match_dup 0)
3639 (compare:CC (match_dup 3)
3640 (const_int 0)))]
3641 "")
3643 (define_insn ""
3644 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3645 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3646 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3647 (const_int 0)))
3648 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3649 (ashift:SI (match_dup 1) (match_dup 2)))
3650 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3651 "TARGET_POWER"
3652 "@
3653 sle. %0,%1,%2
3654 {sli.|slwi.} %0,%1,%h2
3655 #
3656 #"
3657 [(set_attr "type" "delayed_compare")
3658 (set_attr "length" "4,4,8,8")])
3660 (define_split
3661 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3662 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3663 (match_operand:SI 2 "reg_or_cint_operand" ""))
3664 (const_int 0)))
3665 (set (match_operand:SI 0 "gpc_reg_operand" "")
3666 (ashift:SI (match_dup 1) (match_dup 2)))
3667 (clobber (match_scratch:SI 4 ""))]
3668 "TARGET_POWER && reload_completed"
3669 [(parallel [(set (match_dup 0)
3670 (ashift:SI (match_dup 1) (match_dup 2)))
3671 (clobber (match_dup 4))])
3672 (set (match_dup 3)
3673 (compare:CC (match_dup 0)
3674 (const_int 0)))]
3675 "")
3677 (define_insn ""
3678 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3679 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3680 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3681 (const_int 0)))
3682 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3683 (ashift:SI (match_dup 1) (match_dup 2)))]
3684 "! TARGET_POWER && TARGET_32BIT"
3685 "@
3686 {sl|slw}%I2. %0,%1,%h2
3687 #"
3688 [(set_attr "type" "delayed_compare")
3689 (set_attr "length" "4,8")])
3691 (define_split
3692 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3693 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3694 (match_operand:SI 2 "reg_or_cint_operand" ""))
3695 (const_int 0)))
3696 (set (match_operand:SI 0 "gpc_reg_operand" "")
3697 (ashift:SI (match_dup 1) (match_dup 2)))]
3698 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3699 [(set (match_dup 0)
3700 (ashift:SI (match_dup 1) (match_dup 2)))
3701 (set (match_dup 3)
3702 (compare:CC (match_dup 0)
3703 (const_int 0)))]
3704 "")
3706 (define_insn ""
3707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3708 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3709 (match_operand:SI 2 "const_int_operand" "i"))
3710 (match_operand:SI 3 "mask_operand" "n")))]
3711 "includes_lshift_p (operands[2], operands[3])"
3712 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3714 (define_insn ""
3715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3716 (compare:CC
3717 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3718 (match_operand:SI 2 "const_int_operand" "i,i"))
3719 (match_operand:SI 3 "mask_operand" "n,n"))
3720 (const_int 0)))
3721 (clobber (match_scratch:SI 4 "=r,r"))]
3722 "includes_lshift_p (operands[2], operands[3])"
3723 "@
3724 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3725 #"
3726 [(set_attr "type" "delayed_compare")
3727 (set_attr "length" "4,8")])
3729 (define_split
3730 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3731 (compare:CC
3732 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3733 (match_operand:SI 2 "const_int_operand" ""))
3734 (match_operand:SI 3 "mask_operand" ""))
3735 (const_int 0)))
3736 (clobber (match_scratch:SI 4 ""))]
3737 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3738 [(set (match_dup 4)
3739 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3740 (match_dup 3)))
3741 (set (match_dup 0)
3742 (compare:CC (match_dup 4)
3743 (const_int 0)))]
3744 "")
3746 (define_insn ""
3747 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3748 (compare:CC
3749 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3750 (match_operand:SI 2 "const_int_operand" "i,i"))
3751 (match_operand:SI 3 "mask_operand" "n,n"))
3752 (const_int 0)))
3753 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3754 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3755 "includes_lshift_p (operands[2], operands[3])"
3756 "@
3757 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3758 #"
3759 [(set_attr "type" "delayed_compare")
3760 (set_attr "length" "4,8")])
3762 (define_split
3763 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3764 (compare:CC
3765 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3766 (match_operand:SI 2 "const_int_operand" ""))
3767 (match_operand:SI 3 "mask_operand" ""))
3768 (const_int 0)))
3769 (set (match_operand:SI 0 "gpc_reg_operand" "")
3770 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3771 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3772 [(set (match_dup 0)
3773 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3774 (set (match_dup 4)
3775 (compare:CC (match_dup 0)
3776 (const_int 0)))]
3777 "")
3779 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3780 ;; "sli x,x,0".
3781 (define_expand "lshrsi3"
3782 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3783 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3784 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3785 ""
3786 "
3787 {
3788 if (TARGET_POWER)
3789 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3790 else
3791 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3792 DONE;
3793 }")
3795 (define_insn "lshrsi3_power"
3796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3797 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3798 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3799 (clobber (match_scratch:SI 3 "=q,X,X"))]
3800 "TARGET_POWER"
3801 "@
3802 sre %0,%1,%2
3803 mr %0,%1
3804 {s%A2i|s%A2wi} %0,%1,%h2")
3806 (define_insn "lshrsi3_no_power"
3807 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3808 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3809 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3810 "! TARGET_POWER"
3811 "@
3812 mr %0,%1
3813 {sr|srw}%I2 %0,%1,%h2")
3815 (define_insn ""
3816 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3817 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3818 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3819 (const_int 0)))
3820 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3821 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3822 "TARGET_POWER"
3823 "@
3824 sre. %3,%1,%2
3825 mr. %1,%1
3826 {s%A2i.|s%A2wi.} %3,%1,%h2
3827 #
3828 #
3829 #"
3830 [(set_attr "type" "delayed_compare")
3831 (set_attr "length" "4,4,4,8,8,8")])
3833 (define_split
3834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3835 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3836 (match_operand:SI 2 "reg_or_cint_operand" ""))
3837 (const_int 0)))
3838 (clobber (match_scratch:SI 3 ""))
3839 (clobber (match_scratch:SI 4 ""))]
3840 "TARGET_POWER && reload_completed"
3841 [(parallel [(set (match_dup 3)
3842 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3843 (clobber (match_dup 4))])
3844 (set (match_dup 0)
3845 (compare:CC (match_dup 3)
3846 (const_int 0)))]
3847 "")
3849 (define_insn ""
3850 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3851 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3852 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3853 (const_int 0)))
3854 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3855 "! TARGET_POWER && TARGET_32BIT"
3856 "@
3857 mr. %1,%1
3858 {sr|srw}%I2. %3,%1,%h2
3859 #
3860 #"
3861 [(set_attr "type" "delayed_compare")
3862 (set_attr "length" "4,4,8,8")])
3864 (define_split
3865 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3866 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3867 (match_operand:SI 2 "reg_or_cint_operand" ""))
3868 (const_int 0)))
3869 (clobber (match_scratch:SI 3 ""))]
3870 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3871 [(set (match_dup 3)
3872 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3873 (set (match_dup 0)
3874 (compare:CC (match_dup 3)
3875 (const_int 0)))]
3876 "")
3878 (define_insn ""
3879 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3880 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3881 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3882 (const_int 0)))
3883 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3884 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3885 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3886 "TARGET_POWER"
3887 "@
3888 sre. %0,%1,%2
3889 mr. %0,%1
3890 {s%A2i.|s%A2wi.} %0,%1,%h2
3891 #
3892 #
3893 #"
3894 [(set_attr "type" "delayed_compare")
3895 (set_attr "length" "4,4,4,8,8,8")])
3897 (define_split
3898 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3899 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3900 (match_operand:SI 2 "reg_or_cint_operand" ""))
3901 (const_int 0)))
3902 (set (match_operand:SI 0 "gpc_reg_operand" "")
3903 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3904 (clobber (match_scratch:SI 4 ""))]
3905 "TARGET_POWER && reload_completed"
3906 [(parallel [(set (match_dup 0)
3907 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3908 (clobber (match_dup 4))])
3909 (set (match_dup 3)
3910 (compare:CC (match_dup 0)
3911 (const_int 0)))]
3912 "")
3914 (define_insn ""
3915 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3916 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3917 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3918 (const_int 0)))
3919 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3920 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3921 "! TARGET_POWER && TARGET_32BIT"
3922 "@
3923 mr. %0,%1
3924 {sr|srw}%I2. %0,%1,%h2
3925 #
3926 #"
3927 [(set_attr "type" "delayed_compare")
3928 (set_attr "length" "4,4,8,8")])
3930 (define_split
3931 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3932 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3933 (match_operand:SI 2 "reg_or_cint_operand" ""))
3934 (const_int 0)))
3935 (set (match_operand:SI 0 "gpc_reg_operand" "")
3936 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3937 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3938 [(set (match_dup 0)
3939 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3940 (set (match_dup 3)
3941 (compare:CC (match_dup 0)
3942 (const_int 0)))]
3943 "")
3945 (define_insn ""
3946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3947 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3948 (match_operand:SI 2 "const_int_operand" "i"))
3949 (match_operand:SI 3 "mask_operand" "n")))]
3950 "includes_rshift_p (operands[2], operands[3])"
3951 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3953 (define_insn ""
3954 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3955 (compare:CC
3956 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3957 (match_operand:SI 2 "const_int_operand" "i,i"))
3958 (match_operand:SI 3 "mask_operand" "n,n"))
3959 (const_int 0)))
3960 (clobber (match_scratch:SI 4 "=r,r"))]
3961 "includes_rshift_p (operands[2], operands[3])"
3962 "@
3963 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3964 #"
3965 [(set_attr "type" "delayed_compare")
3966 (set_attr "length" "4,8")])
3968 (define_split
3969 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3970 (compare:CC
3971 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3972 (match_operand:SI 2 "const_int_operand" ""))
3973 (match_operand:SI 3 "mask_operand" ""))
3974 (const_int 0)))
3975 (clobber (match_scratch:SI 4 ""))]
3976 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3977 [(set (match_dup 4)
3978 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3979 (match_dup 3)))
3980 (set (match_dup 0)
3981 (compare:CC (match_dup 4)
3982 (const_int 0)))]
3983 "")
3985 (define_insn ""
3986 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3987 (compare:CC
3988 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3989 (match_operand:SI 2 "const_int_operand" "i,i"))
3990 (match_operand:SI 3 "mask_operand" "n,n"))
3991 (const_int 0)))
3992 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3993 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3994 "includes_rshift_p (operands[2], operands[3])"
3995 "@
3996 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
3997 #"
3998 [(set_attr "type" "delayed_compare")
3999 (set_attr "length" "4,8")])
4001 (define_split
4002 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4003 (compare:CC
4004 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4005 (match_operand:SI 2 "const_int_operand" ""))
4006 (match_operand:SI 3 "mask_operand" ""))
4007 (const_int 0)))
4008 (set (match_operand:SI 0 "gpc_reg_operand" "")
4009 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4010 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4011 [(set (match_dup 0)
4012 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4013 (set (match_dup 4)
4014 (compare:CC (match_dup 0)
4015 (const_int 0)))]
4016 "")
4018 (define_insn ""
4019 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4020 (zero_extend:SI
4021 (subreg:QI
4022 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4023 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4024 "includes_rshift_p (operands[2], GEN_INT (255))"
4025 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4027 (define_insn ""
4028 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4029 (compare:CC
4030 (zero_extend:SI
4031 (subreg:QI
4032 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4033 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4034 (const_int 0)))
4035 (clobber (match_scratch:SI 3 "=r,r"))]
4036 "includes_rshift_p (operands[2], GEN_INT (255))"
4037 "@
4038 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4039 #"
4040 [(set_attr "type" "delayed_compare")
4041 (set_attr "length" "4,8")])
4043 (define_split
4044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4045 (compare:CC
4046 (zero_extend:SI
4047 (subreg:QI
4048 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4049 (match_operand:SI 2 "const_int_operand" "")) 0))
4050 (const_int 0)))
4051 (clobber (match_scratch:SI 3 ""))]
4052 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4053 [(set (match_dup 3)
4054 (zero_extend:SI (subreg:QI
4055 (lshiftrt:SI (match_dup 1)
4056 (match_dup 2)) 0)))
4057 (set (match_dup 0)
4058 (compare:CC (match_dup 3)
4059 (const_int 0)))]
4060 "")
4062 (define_insn ""
4063 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4064 (compare:CC
4065 (zero_extend:SI
4066 (subreg:QI
4067 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4068 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4069 (const_int 0)))
4070 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4071 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4072 "includes_rshift_p (operands[2], GEN_INT (255))"
4073 "@
4074 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4075 #"
4076 [(set_attr "type" "delayed_compare")
4077 (set_attr "length" "4,8")])
4079 (define_split
4080 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4081 (compare:CC
4082 (zero_extend:SI
4083 (subreg:QI
4084 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4085 (match_operand:SI 2 "const_int_operand" "")) 0))
4086 (const_int 0)))
4087 (set (match_operand:SI 0 "gpc_reg_operand" "")
4088 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4089 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4090 [(set (match_dup 0)
4091 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4092 (set (match_dup 3)
4093 (compare:CC (match_dup 0)
4094 (const_int 0)))]
4095 "")
4097 (define_insn ""
4098 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4099 (zero_extend:SI
4100 (subreg:HI
4101 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4102 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4103 "includes_rshift_p (operands[2], GEN_INT (65535))"
4104 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4106 (define_insn ""
4107 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4108 (compare:CC
4109 (zero_extend:SI
4110 (subreg:HI
4111 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4112 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4113 (const_int 0)))
4114 (clobber (match_scratch:SI 3 "=r,r"))]
4115 "includes_rshift_p (operands[2], GEN_INT (65535))"
4116 "@
4117 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4118 #"
4119 [(set_attr "type" "delayed_compare")
4120 (set_attr "length" "4,8")])
4122 (define_split
4123 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4124 (compare:CC
4125 (zero_extend:SI
4126 (subreg:HI
4127 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4128 (match_operand:SI 2 "const_int_operand" "")) 0))
4129 (const_int 0)))
4130 (clobber (match_scratch:SI 3 ""))]
4131 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4132 [(set (match_dup 3)
4133 (zero_extend:SI (subreg:HI
4134 (lshiftrt:SI (match_dup 1)
4135 (match_dup 2)) 0)))
4136 (set (match_dup 0)
4137 (compare:CC (match_dup 3)
4138 (const_int 0)))]
4139 "")
4141 (define_insn ""
4142 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4143 (compare:CC
4144 (zero_extend:SI
4145 (subreg:HI
4146 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4147 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4148 (const_int 0)))
4149 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4150 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4151 "includes_rshift_p (operands[2], GEN_INT (65535))"
4152 "@
4153 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4154 #"
4155 [(set_attr "type" "delayed_compare")
4156 (set_attr "length" "4,8")])
4158 (define_split
4159 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4160 (compare:CC
4161 (zero_extend:SI
4162 (subreg:HI
4163 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4164 (match_operand:SI 2 "const_int_operand" "")) 0))
4165 (const_int 0)))
4166 (set (match_operand:SI 0 "gpc_reg_operand" "")
4167 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4168 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4169 [(set (match_dup 0)
4170 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4171 (set (match_dup 3)
4172 (compare:CC (match_dup 0)
4173 (const_int 0)))]
4174 "")
4176 (define_insn ""
4177 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4178 (const_int 1)
4179 (match_operand:SI 1 "gpc_reg_operand" "r"))
4180 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4181 (const_int 31)))]
4182 "TARGET_POWER"
4183 "rrib %0,%1,%2")
4185 (define_insn ""
4186 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4187 (const_int 1)
4188 (match_operand:SI 1 "gpc_reg_operand" "r"))
4189 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4190 (const_int 31)))]
4191 "TARGET_POWER"
4192 "rrib %0,%1,%2")
4194 (define_insn ""
4195 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4196 (const_int 1)
4197 (match_operand:SI 1 "gpc_reg_operand" "r"))
4198 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4199 (const_int 1)
4200 (const_int 0)))]
4201 "TARGET_POWER"
4202 "rrib %0,%1,%2")
4204 (define_expand "ashrsi3"
4205 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4206 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4207 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4208 ""
4209 "
4210 {
4211 if (TARGET_POWER)
4212 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4213 else
4214 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4215 DONE;
4216 }")
4218 (define_insn "ashrsi3_power"
4219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4220 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4221 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4222 (clobber (match_scratch:SI 3 "=q,X"))]
4223 "TARGET_POWER"
4224 "@
4225 srea %0,%1,%2
4226 {srai|srawi} %0,%1,%h2")
4228 (define_insn "ashrsi3_no_power"
4229 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4230 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4231 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4232 "! TARGET_POWER"
4233 "{sra|sraw}%I2 %0,%1,%h2")
4235 (define_insn ""
4236 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4237 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4238 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4239 (const_int 0)))
4240 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4241 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4242 "TARGET_POWER"
4243 "@
4244 srea. %3,%1,%2
4245 {srai.|srawi.} %3,%1,%h2
4246 #
4247 #"
4248 [(set_attr "type" "delayed_compare")
4249 (set_attr "length" "4,4,8,8")])
4251 (define_split
4252 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4253 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4254 (match_operand:SI 2 "reg_or_cint_operand" ""))
4255 (const_int 0)))
4256 (clobber (match_scratch:SI 3 ""))
4257 (clobber (match_scratch:SI 4 ""))]
4258 "TARGET_POWER && reload_completed"
4259 [(parallel [(set (match_dup 3)
4260 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4261 (clobber (match_dup 4))])
4262 (set (match_dup 0)
4263 (compare:CC (match_dup 3)
4264 (const_int 0)))]
4265 "")
4267 (define_insn ""
4268 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4269 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4270 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4271 (const_int 0)))
4272 (clobber (match_scratch:SI 3 "=r,r"))]
4273 "! TARGET_POWER"
4274 "@
4275 {sra|sraw}%I2. %3,%1,%h2
4276 #"
4277 [(set_attr "type" "delayed_compare")
4278 (set_attr "length" "4,8")])
4280 (define_split
4281 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4282 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4283 (match_operand:SI 2 "reg_or_cint_operand" ""))
4284 (const_int 0)))
4285 (clobber (match_scratch:SI 3 ""))]
4286 "! TARGET_POWER && reload_completed"
4287 [(set (match_dup 3)
4288 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4289 (set (match_dup 0)
4290 (compare:CC (match_dup 3)
4291 (const_int 0)))]
4292 "")
4294 (define_insn ""
4295 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4296 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4297 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4298 (const_int 0)))
4299 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4300 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4301 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4302 "TARGET_POWER"
4303 "@
4304 srea. %0,%1,%2
4305 {srai.|srawi.} %0,%1,%h2
4306 #
4307 #"
4308 [(set_attr "type" "delayed_compare")
4309 (set_attr "length" "4,4,8,8")])
4311 (define_split
4312 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4313 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4314 (match_operand:SI 2 "reg_or_cint_operand" ""))
4315 (const_int 0)))
4316 (set (match_operand:SI 0 "gpc_reg_operand" "")
4317 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4318 (clobber (match_scratch:SI 4 ""))]
4319 "TARGET_POWER && reload_completed"
4320 [(parallel [(set (match_dup 0)
4321 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4322 (clobber (match_dup 4))])
4323 (set (match_dup 3)
4324 (compare:CC (match_dup 0)
4325 (const_int 0)))]
4326 "")
4328 (define_insn ""
4329 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4330 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4331 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4332 (const_int 0)))
4333 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4334 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4335 "! TARGET_POWER"
4336 "@
4337 {sra|sraw}%I2. %0,%1,%h2
4338 #"
4339 [(set_attr "type" "delayed_compare")
4340 (set_attr "length" "4,8")])
4341 \f
4342 (define_split
4343 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4344 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4345 (match_operand:SI 2 "reg_or_cint_operand" ""))
4346 (const_int 0)))
4347 (set (match_operand:SI 0 "gpc_reg_operand" "")
4348 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4349 "! TARGET_POWER && reload_completed"
4350 [(set (match_dup 0)
4351 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4352 (set (match_dup 3)
4353 (compare:CC (match_dup 0)
4354 (const_int 0)))]
4355 "")
4357 ;; Floating-point insns, excluding normal data motion.
4358 ;;
4359 ;; PowerPC has a full set of single-precision floating point instructions.
4360 ;;
4361 ;; For the POWER architecture, we pretend that we have both SFmode and
4362 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4363 ;; The only conversions we will do will be when storing to memory. In that
4364 ;; case, we will use the "frsp" instruction before storing.
4365 ;;
4366 ;; Note that when we store into a single-precision memory location, we need to
4367 ;; use the frsp insn first. If the register being stored isn't dead, we
4368 ;; need a scratch register for the frsp. But this is difficult when the store
4369 ;; is done by reload. It is not incorrect to do the frsp on the register in
4370 ;; this case, we just lose precision that we would have otherwise gotten but
4371 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4373 (define_insn "extendsfdf2"
4374 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4375 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4376 "TARGET_HARD_FLOAT && TARGET_FPRS"
4377 "*
4378 {
4379 if (REGNO (operands[0]) == REGNO (operands[1]))
4380 return \"\";
4381 else
4382 return \"fmr %0,%1\";
4383 }"
4384 [(set_attr "type" "fp")])
4386 (define_insn "truncdfsf2"
4387 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4388 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4389 "TARGET_HARD_FLOAT && TARGET_FPRS"
4390 "frsp %0,%1"
4391 [(set_attr "type" "fp")])
4393 (define_insn "aux_truncdfsf2"
4394 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4395 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4396 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4397 "frsp %0,%1"
4398 [(set_attr "type" "fp")])
4400 (define_expand "negsf2"
4401 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4402 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4403 "TARGET_HARD_FLOAT"
4404 "")
4406 (define_insn "*negsf2"
4407 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4408 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4409 "TARGET_HARD_FLOAT && TARGET_FPRS"
4410 "fneg %0,%1"
4411 [(set_attr "type" "fp")])
4413 (define_expand "abssf2"
4414 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4415 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4416 "TARGET_HARD_FLOAT"
4417 "")
4419 (define_insn "*abssf2"
4420 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4421 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4422 "TARGET_HARD_FLOAT && TARGET_FPRS"
4423 "fabs %0,%1"
4424 [(set_attr "type" "fp")])
4426 (define_insn ""
4427 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4428 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4429 "TARGET_HARD_FLOAT && TARGET_FPRS"
4430 "fnabs %0,%1"
4431 [(set_attr "type" "fp")])
4433 (define_expand "addsf3"
4434 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4435 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4436 (match_operand:SF 2 "gpc_reg_operand" "")))]
4437 "TARGET_HARD_FLOAT"
4438 "")
4440 (define_insn ""
4441 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4442 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4443 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4444 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4445 "fadds %0,%1,%2"
4446 [(set_attr "type" "fp")])
4448 (define_insn ""
4449 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4450 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4451 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4452 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4453 "{fa|fadd} %0,%1,%2"
4454 [(set_attr "type" "fp")])
4456 (define_expand "subsf3"
4457 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4458 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4459 (match_operand:SF 2 "gpc_reg_operand" "")))]
4460 "TARGET_HARD_FLOAT"
4461 "")
4463 (define_insn ""
4464 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4465 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4466 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4467 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4468 "fsubs %0,%1,%2"
4469 [(set_attr "type" "fp")])
4471 (define_insn ""
4472 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4473 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4474 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4475 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4476 "{fs|fsub} %0,%1,%2"
4477 [(set_attr "type" "fp")])
4479 (define_expand "mulsf3"
4480 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4481 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4482 (match_operand:SF 2 "gpc_reg_operand" "")))]
4483 "TARGET_HARD_FLOAT"
4484 "")
4486 (define_insn ""
4487 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4488 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4489 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4490 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4491 "fmuls %0,%1,%2"
4492 [(set_attr "type" "fp")])
4494 (define_insn ""
4495 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4496 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4497 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4498 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4499 "{fm|fmul} %0,%1,%2"
4500 [(set_attr "type" "dmul")])
4502 (define_expand "divsf3"
4503 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4504 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4505 (match_operand:SF 2 "gpc_reg_operand" "")))]
4506 "TARGET_HARD_FLOAT"
4507 "")
4509 (define_insn ""
4510 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4511 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4512 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4513 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4514 "fdivs %0,%1,%2"
4515 [(set_attr "type" "sdiv")])
4517 (define_insn ""
4518 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4519 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4520 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4521 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4522 "{fd|fdiv} %0,%1,%2"
4523 [(set_attr "type" "ddiv")])
4525 (define_insn ""
4526 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4527 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4528 (match_operand:SF 2 "gpc_reg_operand" "f"))
4529 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4530 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4531 "fmadds %0,%1,%2,%3"
4532 [(set_attr "type" "fp")])
4534 (define_insn ""
4535 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4536 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4537 (match_operand:SF 2 "gpc_reg_operand" "f"))
4538 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4539 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4540 "{fma|fmadd} %0,%1,%2,%3"
4541 [(set_attr "type" "dmul")])
4543 (define_insn ""
4544 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4545 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4546 (match_operand:SF 2 "gpc_reg_operand" "f"))
4547 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4548 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4549 "fmsubs %0,%1,%2,%3"
4550 [(set_attr "type" "fp")])
4552 (define_insn ""
4553 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4554 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4555 (match_operand:SF 2 "gpc_reg_operand" "f"))
4556 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4557 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4558 "{fms|fmsub} %0,%1,%2,%3"
4559 [(set_attr "type" "dmul")])
4561 (define_insn ""
4562 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4563 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4564 (match_operand:SF 2 "gpc_reg_operand" "f"))
4565 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4566 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4567 && HONOR_SIGNED_ZEROS (SFmode)"
4568 "fnmadds %0,%1,%2,%3"
4569 [(set_attr "type" "fp")])
4571 (define_insn ""
4572 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4573 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4574 (match_operand:SF 2 "gpc_reg_operand" "f"))
4575 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4576 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4577 && ! HONOR_SIGNED_ZEROS (SFmode)"
4578 "fnmadds %0,%1,%2,%3"
4579 [(set_attr "type" "fp")])
4581 (define_insn ""
4582 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4583 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4584 (match_operand:SF 2 "gpc_reg_operand" "f"))
4585 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4586 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4587 "{fnma|fnmadd} %0,%1,%2,%3"
4588 [(set_attr "type" "dmul")])
4590 (define_insn ""
4591 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4592 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4593 (match_operand:SF 2 "gpc_reg_operand" "f"))
4594 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4595 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4596 && ! HONOR_SIGNED_ZEROS (SFmode)"
4597 "{fnma|fnmadd} %0,%1,%2,%3"
4598 [(set_attr "type" "dmul")])
4600 (define_insn ""
4601 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4602 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4603 (match_operand:SF 2 "gpc_reg_operand" "f"))
4604 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4605 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4606 && HONOR_SIGNED_ZEROS (SFmode)"
4607 "fnmsubs %0,%1,%2,%3"
4608 [(set_attr "type" "fp")])
4610 (define_insn ""
4611 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4612 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4613 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4614 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4615 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4616 && ! HONOR_SIGNED_ZEROS (SFmode)"
4617 "fnmsubs %0,%1,%2,%3"
4618 [(set_attr "type" "fp")])
4620 (define_insn ""
4621 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4622 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4623 (match_operand:SF 2 "gpc_reg_operand" "f"))
4624 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4625 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4626 "{fnms|fnmsub} %0,%1,%2,%3"
4627 [(set_attr "type" "dmul")])
4629 (define_insn ""
4630 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4631 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4632 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4633 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4634 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4635 && ! HONOR_SIGNED_ZEROS (SFmode)"
4636 "{fnms|fnmsub} %0,%1,%2,%3"
4637 [(set_attr "type" "fp")])
4639 (define_expand "sqrtsf2"
4640 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4641 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4642 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4643 "")
4645 (define_insn ""
4646 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4647 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4648 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4649 "fsqrts %0,%1"
4650 [(set_attr "type" "ssqrt")])
4652 (define_insn ""
4653 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4654 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4655 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4656 "fsqrt %0,%1"
4657 [(set_attr "type" "dsqrt")])
4659 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4660 ;; fsel instruction and some auxiliary computations. Then we just have a
4661 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4662 ;; combine.
4663 (define_expand "maxsf3"
4664 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4665 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4666 (match_operand:SF 2 "gpc_reg_operand" ""))
4667 (match_dup 1)
4668 (match_dup 2)))]
4669 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4670 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4672 (define_expand "minsf3"
4673 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4674 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4675 (match_operand:SF 2 "gpc_reg_operand" ""))
4676 (match_dup 2)
4677 (match_dup 1)))]
4678 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4679 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4681 (define_split
4682 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4683 (match_operator:SF 3 "min_max_operator"
4684 [(match_operand:SF 1 "gpc_reg_operand" "")
4685 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4686 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4687 [(const_int 0)]
4688 "
4689 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4690 operands[1], operands[2]);
4691 DONE;
4692 }")
4694 (define_expand "movsicc"
4695 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4696 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4697 (match_operand:SI 2 "gpc_reg_operand" "")
4698 (match_operand:SI 3 "gpc_reg_operand" "")))]
4699 "TARGET_ISEL"
4700 "
4701 {
4702 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4703 DONE;
4704 else
4705 FAIL;
4706 }")
4708 ;; We use the BASE_REGS for the isel input operands because, if rA is
4709 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4710 ;; because we may switch the operands and rB may end up being rA.
4711 ;;
4712 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4713 ;; leave out the mode in operand 4 and use one pattern, but reload can
4714 ;; change the mode underneath our feet and then gets confused trying
4715 ;; to reload the value.
4716 (define_insn "isel_signed"
4717 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4718 (if_then_else:SI
4719 (match_operator 1 "comparison_operator"
4720 [(match_operand:CC 4 "cc_reg_operand" "y")
4721 (const_int 0)])
4722 (match_operand:SI 2 "gpc_reg_operand" "b")
4723 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4724 "TARGET_ISEL"
4725 "*
4726 { return output_isel (operands); }"
4727 [(set_attr "length" "4")])
4729 (define_insn "isel_unsigned"
4730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4731 (if_then_else:SI
4732 (match_operator 1 "comparison_operator"
4733 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4734 (const_int 0)])
4735 (match_operand:SI 2 "gpc_reg_operand" "b")
4736 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4737 "TARGET_ISEL"
4738 "*
4739 { return output_isel (operands); }"
4740 [(set_attr "length" "4")])
4742 (define_expand "movsfcc"
4743 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4744 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4745 (match_operand:SF 2 "gpc_reg_operand" "")
4746 (match_operand:SF 3 "gpc_reg_operand" "")))]
4747 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4748 "
4749 {
4750 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4751 DONE;
4752 else
4753 FAIL;
4754 }")
4756 (define_insn "*fselsfsf4"
4757 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4758 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4759 (match_operand:SF 4 "zero_fp_constant" "F"))
4760 (match_operand:SF 2 "gpc_reg_operand" "f")
4761 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4762 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4763 "fsel %0,%1,%2,%3"
4764 [(set_attr "type" "fp")])
4766 (define_insn "*fseldfsf4"
4767 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4768 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4769 (match_operand:DF 4 "zero_fp_constant" "F"))
4770 (match_operand:SF 2 "gpc_reg_operand" "f")
4771 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4772 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4773 "fsel %0,%1,%2,%3"
4774 [(set_attr "type" "fp")])
4776 (define_insn "negdf2"
4777 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4778 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4779 "TARGET_HARD_FLOAT && TARGET_FPRS"
4780 "fneg %0,%1"
4781 [(set_attr "type" "fp")])
4783 (define_insn "absdf2"
4784 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4785 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4786 "TARGET_HARD_FLOAT && TARGET_FPRS"
4787 "fabs %0,%1"
4788 [(set_attr "type" "fp")])
4790 (define_insn ""
4791 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4792 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4793 "TARGET_HARD_FLOAT && TARGET_FPRS"
4794 "fnabs %0,%1"
4795 [(set_attr "type" "fp")])
4797 (define_insn "adddf3"
4798 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4799 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4800 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4801 "TARGET_HARD_FLOAT && TARGET_FPRS"
4802 "{fa|fadd} %0,%1,%2"
4803 [(set_attr "type" "fp")])
4805 (define_insn "subdf3"
4806 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4807 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4808 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4809 "TARGET_HARD_FLOAT && TARGET_FPRS"
4810 "{fs|fsub} %0,%1,%2"
4811 [(set_attr "type" "fp")])
4813 (define_insn "muldf3"
4814 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4815 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4816 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4817 "TARGET_HARD_FLOAT && TARGET_FPRS"
4818 "{fm|fmul} %0,%1,%2"
4819 [(set_attr "type" "dmul")])
4821 (define_insn "divdf3"
4822 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4823 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4824 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4825 "TARGET_HARD_FLOAT && TARGET_FPRS"
4826 "{fd|fdiv} %0,%1,%2"
4827 [(set_attr "type" "ddiv")])
4829 (define_insn ""
4830 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4831 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4832 (match_operand:DF 2 "gpc_reg_operand" "f"))
4833 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4834 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4835 "{fma|fmadd} %0,%1,%2,%3"
4836 [(set_attr "type" "dmul")])
4838 (define_insn ""
4839 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4840 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4841 (match_operand:DF 2 "gpc_reg_operand" "f"))
4842 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4843 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4844 "{fms|fmsub} %0,%1,%2,%3"
4845 [(set_attr "type" "dmul")])
4847 (define_insn ""
4848 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4849 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4850 (match_operand:DF 2 "gpc_reg_operand" "f"))
4851 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4852 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4853 && HONOR_SIGNED_ZEROS (DFmode)"
4854 "{fnma|fnmadd} %0,%1,%2,%3"
4855 [(set_attr "type" "dmul")])
4857 (define_insn ""
4858 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4859 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4860 (match_operand:DF 2 "gpc_reg_operand" "f"))
4861 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4862 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4863 && ! HONOR_SIGNED_ZEROS (DFmode)"
4864 "{fnma|fnmadd} %0,%1,%2,%3"
4865 [(set_attr "type" "dmul")])
4867 (define_insn ""
4868 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4869 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4870 (match_operand:DF 2 "gpc_reg_operand" "f"))
4871 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4872 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4873 && HONOR_SIGNED_ZEROS (DFmode)"
4874 "{fnms|fnmsub} %0,%1,%2,%3"
4875 [(set_attr "type" "dmul")])
4877 (define_insn ""
4878 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4879 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4880 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4881 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4882 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4883 && ! HONOR_SIGNED_ZEROS (DFmode)"
4884 "{fnms|fnmsub} %0,%1,%2,%3"
4885 [(set_attr "type" "dmul")])
4887 (define_insn "sqrtdf2"
4888 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4889 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4890 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4891 "fsqrt %0,%1"
4892 [(set_attr "type" "dsqrt")])
4894 ;; The conditional move instructions allow us to perform max and min
4895 ;; operations even when
4897 (define_expand "maxdf3"
4898 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4899 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4900 (match_operand:DF 2 "gpc_reg_operand" ""))
4901 (match_dup 1)
4902 (match_dup 2)))]
4903 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4904 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4906 (define_expand "mindf3"
4907 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4908 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4909 (match_operand:DF 2 "gpc_reg_operand" ""))
4910 (match_dup 2)
4911 (match_dup 1)))]
4912 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4913 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4915 (define_split
4916 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4917 (match_operator:DF 3 "min_max_operator"
4918 [(match_operand:DF 1 "gpc_reg_operand" "")
4919 (match_operand:DF 2 "gpc_reg_operand" "")]))]
4920 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4921 [(const_int 0)]
4922 "
4923 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4924 operands[1], operands[2]);
4925 DONE;
4926 }")
4928 (define_expand "movdfcc"
4929 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4930 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4931 (match_operand:DF 2 "gpc_reg_operand" "")
4932 (match_operand:DF 3 "gpc_reg_operand" "")))]
4933 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4934 "
4935 {
4936 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4937 DONE;
4938 else
4939 FAIL;
4940 }")
4942 (define_insn "*fseldfdf4"
4943 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4944 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4945 (match_operand:DF 4 "zero_fp_constant" "F"))
4946 (match_operand:DF 2 "gpc_reg_operand" "f")
4947 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4948 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4949 "fsel %0,%1,%2,%3"
4950 [(set_attr "type" "fp")])
4952 (define_insn "*fselsfdf4"
4953 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4954 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4955 (match_operand:SF 4 "zero_fp_constant" "F"))
4956 (match_operand:DF 2 "gpc_reg_operand" "f")
4957 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4958 "TARGET_PPC_GFXOPT"
4959 "fsel %0,%1,%2,%3"
4960 [(set_attr "type" "fp")])
4961 \f
4962 ;; Conversions to and from floating-point.
4964 (define_expand "fixuns_truncsfsi2"
4965 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4966 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4967 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4968 "")
4970 (define_expand "fix_truncsfsi2"
4971 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4972 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4973 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4974 "")
4976 ; For each of these conversions, there is a define_expand, a define_insn
4977 ; with a '#' template, and a define_split (with C code). The idea is
4978 ; to allow constant folding with the template of the define_insn,
4979 ; then to have the insns split later (between sched1 and final).
4981 (define_expand "floatsidf2"
4982 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4983 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4984 (use (match_dup 2))
4985 (use (match_dup 3))
4986 (clobber (match_dup 4))
4987 (clobber (match_dup 5))
4988 (clobber (match_dup 6))])]
4989 "TARGET_HARD_FLOAT && TARGET_FPRS"
4990 "
4991 {
4992 if (TARGET_POWERPC64)
4993 {
4994 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
4995 rtx t1 = gen_reg_rtx (DImode);
4996 rtx t2 = gen_reg_rtx (DImode);
4997 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
4998 DONE;
4999 }
5001 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5002 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5003 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5004 operands[5] = gen_reg_rtx (DFmode);
5005 operands[6] = gen_reg_rtx (SImode);
5006 }")
5008 (define_insn "*floatsidf2_internal"
5009 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5010 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5011 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5012 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5013 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5014 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5015 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5016 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5017 "#"
5018 [(set_attr "length" "24")])
5020 (define_split
5021 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5022 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5023 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5024 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5025 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5026 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5027 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5028 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5029 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5030 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5031 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5032 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5033 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5034 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5035 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5036 "
5037 {
5038 rtx lowword, highword;
5039 if (GET_CODE (operands[4]) != MEM)
5040 abort();
5041 highword = XEXP (operands[4], 0);
5042 lowword = plus_constant (highword, 4);
5043 if (! WORDS_BIG_ENDIAN)
5044 {
5045 rtx tmp;
5046 tmp = highword; highword = lowword; lowword = tmp;
5047 }
5049 emit_insn (gen_xorsi3 (operands[6], operands[1],
5050 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5051 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5052 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5053 emit_move_insn (operands[5], operands[4]);
5054 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5055 DONE;
5056 }")
5058 (define_expand "floatunssisf2"
5059 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5060 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5061 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5062 "")
5064 (define_expand "floatunssidf2"
5065 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5066 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5067 (use (match_dup 2))
5068 (use (match_dup 3))
5069 (clobber (match_dup 4))
5070 (clobber (match_dup 5))])]
5071 "TARGET_HARD_FLOAT && TARGET_FPRS"
5072 "
5073 {
5074 if (TARGET_POWERPC64)
5075 {
5076 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5077 rtx t1 = gen_reg_rtx (DImode);
5078 rtx t2 = gen_reg_rtx (DImode);
5079 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5080 t1, t2));
5081 DONE;
5082 }
5084 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5085 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5086 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5087 operands[5] = gen_reg_rtx (DFmode);
5088 }")
5090 (define_insn "*floatunssidf2_internal"
5091 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5092 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5093 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5094 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5095 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5096 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5097 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5098 "#"
5099 [(set_attr "length" "20")])
5101 (define_split
5102 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5103 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5104 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5105 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5106 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5107 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5108 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5109 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5110 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5111 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5112 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5113 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5114 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5115 "
5116 {
5117 rtx lowword, highword;
5118 if (GET_CODE (operands[4]) != MEM)
5119 abort();
5120 highword = XEXP (operands[4], 0);
5121 lowword = plus_constant (highword, 4);
5122 if (! WORDS_BIG_ENDIAN)
5123 {
5124 rtx tmp;
5125 tmp = highword; highword = lowword; lowword = tmp;
5126 }
5128 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5129 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5130 emit_move_insn (operands[5], operands[4]);
5131 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5132 DONE;
5133 }")
5135 (define_expand "fix_truncdfsi2"
5136 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5137 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5138 (clobber (match_dup 2))
5139 (clobber (match_dup 3))])]
5140 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5141 "
5142 {
5143 operands[2] = gen_reg_rtx (DImode);
5144 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5145 }")
5147 (define_insn "*fix_truncdfsi2_internal"
5148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5149 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5150 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5151 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5152 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5153 "#"
5154 [(set_attr "length" "16")])
5156 (define_split
5157 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5158 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5159 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5160 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5161 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5162 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5163 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5164 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5165 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5166 "
5167 {
5168 rtx lowword;
5169 if (GET_CODE (operands[3]) != MEM)
5170 abort();
5171 lowword = XEXP (operands[3], 0);
5172 if (WORDS_BIG_ENDIAN)
5173 lowword = plus_constant (lowword, 4);
5175 emit_insn (gen_fctiwz (operands[2], operands[1]));
5176 emit_move_insn (operands[3], operands[2]);
5177 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5178 DONE;
5179 }")
5181 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5182 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5183 ; because the first makes it clear that operand 0 is not live
5184 ; before the instruction.
5185 (define_insn "fctiwz"
5186 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5187 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5188 UNSPEC_FCTIWZ))]
5189 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5190 "{fcirz|fctiwz} %0,%1"
5191 [(set_attr "type" "fp")])
5193 (define_expand "floatsisf2"
5194 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5195 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5196 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5197 "")
5199 (define_insn "floatdidf2"
5200 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5201 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5202 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5203 "fcfid %0,%1"
5204 [(set_attr "type" "fp")])
5206 (define_insn_and_split "floatsidf_ppc64"
5207 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5208 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5209 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5210 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5211 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5212 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5213 "#"
5214 "&& 1"
5215 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5216 (set (match_dup 2) (match_dup 3))
5217 (set (match_dup 4) (match_dup 2))
5218 (set (match_dup 0) (float:DF (match_dup 4)))]
5219 "")
5221 (define_insn_and_split "floatunssidf_ppc64"
5222 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5223 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5224 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5225 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5226 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5227 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5228 "#"
5229 "&& 1"
5230 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5231 (set (match_dup 2) (match_dup 3))
5232 (set (match_dup 4) (match_dup 2))
5233 (set (match_dup 0) (float:DF (match_dup 4)))]
5234 "")
5236 (define_insn "fix_truncdfdi2"
5237 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5238 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5239 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5240 "fctidz %0,%1"
5241 [(set_attr "type" "fp")])
5243 (define_expand "floatdisf2"
5244 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5245 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5246 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
5247 "
5248 {
5249 if (!flag_unsafe_math_optimizations)
5250 {
5251 rtx label = gen_label_rtx ();
5252 emit_insn (gen_floatdisf2_internal2 (operands[1], label));
5253 emit_label (label);
5254 }
5255 emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
5256 DONE;
5257 }")
5259 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5260 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5261 ;; from double rounding.
5262 (define_insn_and_split "floatdisf2_internal1"
5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5264 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5265 (clobber (match_scratch:DF 2 "=f"))]
5266 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5267 "#"
5268 "&& reload_completed"
5269 [(set (match_dup 2)
5270 (float:DF (match_dup 1)))
5271 (set (match_dup 0)
5272 (float_truncate:SF (match_dup 2)))]
5273 "")
5275 ;; Twiddles bits to avoid double rounding.
5276 ;; Bits that might be truncated when converting to DFmode are replaced
5277 ;; by a bit that won't be lost at that stage, but is below the SFmode
5278 ;; rounding position.
5279 (define_expand "floatdisf2_internal2"
5280 [(parallel [(set (match_dup 4)
5281 (compare:CC (and:DI (match_operand:DI 0 "" "")
5282 (const_int 2047))
5283 (const_int 0)))
5284 (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
5285 (clobber (match_scratch:CC 7 ""))])
5286 (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
5287 (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
5288 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
5289 (label_ref (match_operand:DI 1 "" ""))
5290 (pc)))
5291 (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
5292 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
5293 (label_ref (match_dup 1))
5294 (pc)))
5295 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
5296 (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
5297 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
5298 "
5299 {
5300 operands[2] = gen_reg_rtx (DImode);
5301 operands[3] = gen_reg_rtx (DImode);
5302 operands[4] = gen_reg_rtx (CCmode);
5303 operands[5] = gen_reg_rtx (CCUNSmode);
5304 }")
5305 \f
5306 ;; Define the DImode operations that can be done in a small number
5307 ;; of instructions. The & constraints are to prevent the register
5308 ;; allocator from allocating registers that overlap with the inputs
5309 ;; (for example, having an input in 7,8 and an output in 6,7). We
5310 ;; also allow for the output being the same as one of the inputs.
5312 (define_insn "*adddi3_noppc64"
5313 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5314 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5315 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5316 "! TARGET_POWERPC64"
5317 "*
5318 {
5319 if (WORDS_BIG_ENDIAN)
5320 return (GET_CODE (operands[2])) != CONST_INT
5321 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5322 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5323 else
5324 return (GET_CODE (operands[2])) != CONST_INT
5325 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5326 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5327 }"
5328 [(set_attr "length" "8")])
5330 (define_insn "*subdi3_noppc64"
5331 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5332 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5333 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5334 "! TARGET_POWERPC64"
5335 "*
5336 {
5337 if (WORDS_BIG_ENDIAN)
5338 return (GET_CODE (operands[1]) != CONST_INT)
5339 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5340 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5341 else
5342 return (GET_CODE (operands[1]) != CONST_INT)
5343 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5344 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5345 }"
5346 [(set_attr "length" "8")])
5348 (define_insn "*negdi2_noppc64"
5349 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5350 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5351 "! TARGET_POWERPC64"
5352 "*
5353 {
5354 return (WORDS_BIG_ENDIAN)
5355 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5356 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5357 }"
5358 [(set_attr "length" "8")])
5360 (define_expand "mulsidi3"
5361 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5362 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5363 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5364 "! TARGET_POWERPC64"
5365 "
5366 {
5367 if (! TARGET_POWER && ! TARGET_POWERPC)
5368 {
5369 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5370 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5371 emit_insn (gen_mull_call ());
5372 if (WORDS_BIG_ENDIAN)
5373 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5374 else
5375 {
5376 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5377 gen_rtx_REG (SImode, 3));
5378 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5379 gen_rtx_REG (SImode, 4));
5380 }
5381 DONE;
5382 }
5383 else if (TARGET_POWER)
5384 {
5385 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5386 DONE;
5387 }
5388 }")
5390 (define_insn "mulsidi3_mq"
5391 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5392 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5393 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5394 (clobber (match_scratch:SI 3 "=q"))]
5395 "TARGET_POWER"
5396 "mul %0,%1,%2\;mfmq %L0"
5397 [(set_attr "type" "imul")
5398 (set_attr "length" "8")])
5400 (define_insn "*mulsidi3_no_mq"
5401 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5402 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5403 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5404 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5405 "*
5406 {
5407 return (WORDS_BIG_ENDIAN)
5408 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5409 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5410 }"
5411 [(set_attr "type" "imul")
5412 (set_attr "length" "8")])
5414 (define_split
5415 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5416 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5417 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5418 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5419 [(set (match_dup 3)
5420 (truncate:SI
5421 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5422 (sign_extend:DI (match_dup 2)))
5423 (const_int 32))))
5424 (set (match_dup 4)
5425 (mult:SI (match_dup 1)
5426 (match_dup 2)))]
5427 "
5428 {
5429 int endian = (WORDS_BIG_ENDIAN == 0);
5430 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5431 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5432 }")
5434 (define_expand "umulsidi3"
5435 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5436 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5437 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5438 "TARGET_POWERPC && ! TARGET_POWERPC64"
5439 "
5440 {
5441 if (TARGET_POWER)
5442 {
5443 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5444 DONE;
5445 }
5446 }")
5448 (define_insn "umulsidi3_mq"
5449 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5450 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5451 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5452 (clobber (match_scratch:SI 3 "=q"))]
5453 "TARGET_POWERPC && TARGET_POWER"
5454 "*
5455 {
5456 return (WORDS_BIG_ENDIAN)
5457 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5458 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5459 }"
5460 [(set_attr "type" "imul")
5461 (set_attr "length" "8")])
5463 (define_insn "*umulsidi3_no_mq"
5464 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5465 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5466 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5467 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5468 "*
5469 {
5470 return (WORDS_BIG_ENDIAN)
5471 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5472 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5473 }"
5474 [(set_attr "type" "imul")
5475 (set_attr "length" "8")])
5477 (define_split
5478 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5479 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5480 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5481 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5482 [(set (match_dup 3)
5483 (truncate:SI
5484 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5485 (zero_extend:DI (match_dup 2)))
5486 (const_int 32))))
5487 (set (match_dup 4)
5488 (mult:SI (match_dup 1)
5489 (match_dup 2)))]
5490 "
5491 {
5492 int endian = (WORDS_BIG_ENDIAN == 0);
5493 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5494 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5495 }")
5497 (define_expand "smulsi3_highpart"
5498 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5499 (truncate:SI
5500 (lshiftrt:DI (mult:DI (sign_extend:DI
5501 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5502 (sign_extend:DI
5503 (match_operand:SI 2 "gpc_reg_operand" "r")))
5504 (const_int 32))))]
5505 ""
5506 "
5507 {
5508 if (! TARGET_POWER && ! TARGET_POWERPC)
5509 {
5510 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5511 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5512 emit_insn (gen_mulh_call ());
5513 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5514 DONE;
5515 }
5516 else if (TARGET_POWER)
5517 {
5518 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5519 DONE;
5520 }
5521 }")
5523 (define_insn "smulsi3_highpart_mq"
5524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5525 (truncate:SI
5526 (lshiftrt:DI (mult:DI (sign_extend:DI
5527 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5528 (sign_extend:DI
5529 (match_operand:SI 2 "gpc_reg_operand" "r")))
5530 (const_int 32))))
5531 (clobber (match_scratch:SI 3 "=q"))]
5532 "TARGET_POWER"
5533 "mul %0,%1,%2"
5534 [(set_attr "type" "imul")])
5536 (define_insn "*smulsi3_highpart_no_mq"
5537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5538 (truncate:SI
5539 (lshiftrt:DI (mult:DI (sign_extend:DI
5540 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5541 (sign_extend:DI
5542 (match_operand:SI 2 "gpc_reg_operand" "r")))
5543 (const_int 32))))]
5544 "TARGET_POWERPC && ! TARGET_POWER"
5545 "mulhw %0,%1,%2"
5546 [(set_attr "type" "imul")])
5548 (define_expand "umulsi3_highpart"
5549 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5550 (truncate:SI
5551 (lshiftrt:DI (mult:DI (zero_extend:DI
5552 (match_operand:SI 1 "gpc_reg_operand" ""))
5553 (zero_extend:DI
5554 (match_operand:SI 2 "gpc_reg_operand" "")))
5555 (const_int 32))))]
5556 "TARGET_POWERPC"
5557 "
5558 {
5559 if (TARGET_POWER)
5560 {
5561 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5562 DONE;
5563 }
5564 }")
5566 (define_insn "umulsi3_highpart_mq"
5567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5568 (truncate:SI
5569 (lshiftrt:DI (mult:DI (zero_extend:DI
5570 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5571 (zero_extend:DI
5572 (match_operand:SI 2 "gpc_reg_operand" "r")))
5573 (const_int 32))))
5574 (clobber (match_scratch:SI 3 "=q"))]
5575 "TARGET_POWERPC && TARGET_POWER"
5576 "mulhwu %0,%1,%2"
5577 [(set_attr "type" "imul")])
5579 (define_insn "*umulsi3_highpart_no_mq"
5580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5581 (truncate:SI
5582 (lshiftrt:DI (mult:DI (zero_extend:DI
5583 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5584 (zero_extend:DI
5585 (match_operand:SI 2 "gpc_reg_operand" "r")))
5586 (const_int 32))))]
5587 "TARGET_POWERPC && ! TARGET_POWER"
5588 "mulhwu %0,%1,%2"
5589 [(set_attr "type" "imul")])
5591 ;; If operands 0 and 2 are in the same register, we have a problem. But
5592 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5593 ;; why we have the strange constraints below.
5594 (define_insn "ashldi3_power"
5595 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5596 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5597 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5598 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5599 "TARGET_POWER"
5600 "@
5601 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5602 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5603 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5604 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5605 [(set_attr "length" "8")])
5607 (define_insn "lshrdi3_power"
5608 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5609 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5610 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5611 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5612 "TARGET_POWER"
5613 "@
5614 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5615 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5616 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5617 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5618 [(set_attr "length" "8")])
5620 ;; Shift by a variable amount is too complex to be worth open-coding. We
5621 ;; just handle shifts by constants.
5622 (define_insn "ashrdi3_power"
5623 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5624 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5625 (match_operand:SI 2 "const_int_operand" "M,i")))
5626 (clobber (match_scratch:SI 3 "=X,q"))]
5627 "TARGET_POWER"
5628 "@
5629 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5630 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5631 [(set_attr "length" "8")])
5633 (define_insn "ashrdi3_no_power"
5634 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5635 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5636 (match_operand:SI 2 "const_int_operand" "M,i")))]
5637 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5638 "@
5639 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5640 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5641 [(set_attr "length" "8,12")])
5643 (define_insn "*ashrdisi3_noppc64"
5644 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5645 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5646 (const_int 32)) 4))]
5647 "TARGET_32BIT && !TARGET_POWERPC64"
5648 "*
5649 {
5650 if (REGNO (operands[0]) == REGNO (operands[1]))
5651 return \"\";
5652 else
5653 return \"mr %0,%1\";
5654 }"
5655 [(set_attr "length" "4")])
5657 \f
5658 ;; PowerPC64 DImode operations.
5660 (define_expand "adddi3"
5661 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5662 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5663 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5664 ""
5665 "
5666 {
5667 if (! TARGET_POWERPC64)
5668 {
5669 if (non_short_cint_operand (operands[2], DImode))
5670 FAIL;
5671 }
5672 else
5673 if (GET_CODE (operands[2]) == CONST_INT
5674 && ! add_operand (operands[2], DImode))
5675 {
5676 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5677 ? operands[0] : gen_reg_rtx (DImode));
5679 HOST_WIDE_INT val = INTVAL (operands[2]);
5680 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5681 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5683 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5684 FAIL;
5686 /* The ordering here is important for the prolog expander.
5687 When space is allocated from the stack, adding 'low' first may
5688 produce a temporary deallocation (which would be bad). */
5689 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5690 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5691 DONE;
5692 }
5693 }")
5695 ;; Discourage ai/addic because of carry but provide it in an alternative
5696 ;; allowing register zero as source.
5698 (define_insn "*adddi3_internal1"
5699 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5700 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5701 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5702 "TARGET_POWERPC64"
5703 "@
5704 add %0,%1,%2
5705 addi %0,%1,%2
5706 addic %0,%1,%2
5707 addis %0,%1,%v2")
5709 (define_insn "*adddi3_internal2"
5710 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5711 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5712 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5713 (const_int 0)))
5714 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5715 "TARGET_64BIT"
5716 "@
5717 add. %3,%1,%2
5718 addic. %3,%1,%2
5719 #
5720 #"
5721 [(set_attr "type" "fast_compare,compare,compare,compare")
5722 (set_attr "length" "4,4,8,8")])
5724 (define_split
5725 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5726 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5727 (match_operand:DI 2 "reg_or_short_operand" ""))
5728 (const_int 0)))
5729 (clobber (match_scratch:DI 3 ""))]
5730 "TARGET_POWERPC64 && reload_completed"
5731 [(set (match_dup 3)
5732 (plus:DI (match_dup 1) (match_dup 2)))
5733 (set (match_dup 0)
5734 (compare:CC (match_dup 3)
5735 (const_int 0)))]
5736 "")
5738 (define_insn "*adddi3_internal3"
5739 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5740 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5741 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5742 (const_int 0)))
5743 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5744 (plus:DI (match_dup 1) (match_dup 2)))]
5745 "TARGET_64BIT"
5746 "@
5747 add. %0,%1,%2
5748 addic. %0,%1,%2
5749 #
5750 #"
5751 [(set_attr "type" "fast_compare,compare,compare,compare")
5752 (set_attr "length" "4,4,8,8")])
5754 (define_split
5755 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5756 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5757 (match_operand:DI 2 "reg_or_short_operand" ""))
5758 (const_int 0)))
5759 (set (match_operand:DI 0 "gpc_reg_operand" "")
5760 (plus:DI (match_dup 1) (match_dup 2)))]
5761 "TARGET_POWERPC64 && reload_completed"
5762 [(set (match_dup 0)
5763 (plus:DI (match_dup 1) (match_dup 2)))
5764 (set (match_dup 3)
5765 (compare:CC (match_dup 0)
5766 (const_int 0)))]
5767 "")
5769 ;; Split an add that we can't do in one insn into two insns, each of which
5770 ;; does one 16-bit part. This is used by combine. Note that the low-order
5771 ;; add should be last in case the result gets used in an address.
5773 (define_split
5774 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5775 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5776 (match_operand:DI 2 "non_add_cint_operand" "")))]
5777 "TARGET_POWERPC64"
5778 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5779 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5780 "
5781 {
5782 HOST_WIDE_INT val = INTVAL (operands[2]);
5783 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5784 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5786 operands[4] = GEN_INT (low);
5787 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5788 operands[3] = GEN_INT (rest);
5789 else if (! no_new_pseudos)
5790 {
5791 operands[3] = gen_reg_rtx (DImode);
5792 emit_move_insn (operands[3], operands[2]);
5793 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5794 DONE;
5795 }
5796 else
5797 FAIL;
5798 }")
5800 (define_insn "one_cmpldi2"
5801 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5802 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5803 "TARGET_POWERPC64"
5804 "nor %0,%1,%1")
5806 (define_insn ""
5807 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5808 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5809 (const_int 0)))
5810 (clobber (match_scratch:DI 2 "=r,r"))]
5811 "TARGET_64BIT"
5812 "@
5813 nor. %2,%1,%1
5814 #"
5815 [(set_attr "type" "compare")
5816 (set_attr "length" "4,8")])
5818 (define_split
5819 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5820 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5821 (const_int 0)))
5822 (clobber (match_scratch:DI 2 ""))]
5823 "TARGET_POWERPC64 && reload_completed"
5824 [(set (match_dup 2)
5825 (not:DI (match_dup 1)))
5826 (set (match_dup 0)
5827 (compare:CC (match_dup 2)
5828 (const_int 0)))]
5829 "")
5831 (define_insn ""
5832 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5833 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5834 (const_int 0)))
5835 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5836 (not:DI (match_dup 1)))]
5837 "TARGET_64BIT"
5838 "@
5839 nor. %0,%1,%1
5840 #"
5841 [(set_attr "type" "compare")
5842 (set_attr "length" "4,8")])
5844 (define_split
5845 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5846 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5847 (const_int 0)))
5848 (set (match_operand:DI 0 "gpc_reg_operand" "")
5849 (not:DI (match_dup 1)))]
5850 "TARGET_POWERPC64 && reload_completed"
5851 [(set (match_dup 0)
5852 (not:DI (match_dup 1)))
5853 (set (match_dup 2)
5854 (compare:CC (match_dup 0)
5855 (const_int 0)))]
5856 "")
5858 (define_insn ""
5859 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5860 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5861 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5862 "TARGET_POWERPC64"
5863 "@
5864 subf %0,%2,%1
5865 subfic %0,%2,%1")
5867 (define_insn ""
5868 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5869 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5870 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5871 (const_int 0)))
5872 (clobber (match_scratch:DI 3 "=r,r"))]
5873 "TARGET_64BIT"
5874 "@
5875 subf. %3,%2,%1
5876 #"
5877 [(set_attr "type" "fast_compare")
5878 (set_attr "length" "4,8")])
5880 (define_split
5881 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5882 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5883 (match_operand:DI 2 "gpc_reg_operand" ""))
5884 (const_int 0)))
5885 (clobber (match_scratch:DI 3 ""))]
5886 "TARGET_POWERPC64 && reload_completed"
5887 [(set (match_dup 3)
5888 (minus:DI (match_dup 1) (match_dup 2)))
5889 (set (match_dup 0)
5890 (compare:CC (match_dup 3)
5891 (const_int 0)))]
5892 "")
5894 (define_insn ""
5895 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5896 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5897 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5898 (const_int 0)))
5899 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5900 (minus:DI (match_dup 1) (match_dup 2)))]
5901 "TARGET_64BIT"
5902 "@
5903 subf. %0,%2,%1
5904 #"
5905 [(set_attr "type" "fast_compare")
5906 (set_attr "length" "4,8")])
5908 (define_split
5909 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5910 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5911 (match_operand:DI 2 "gpc_reg_operand" ""))
5912 (const_int 0)))
5913 (set (match_operand:DI 0 "gpc_reg_operand" "")
5914 (minus:DI (match_dup 1) (match_dup 2)))]
5915 "TARGET_POWERPC64 && reload_completed"
5916 [(set (match_dup 0)
5917 (minus:DI (match_dup 1) (match_dup 2)))
5918 (set (match_dup 3)
5919 (compare:CC (match_dup 0)
5920 (const_int 0)))]
5921 "")
5923 (define_expand "subdi3"
5924 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5925 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
5926 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
5927 ""
5928 "
5929 {
5930 if (GET_CODE (operands[2]) == CONST_INT)
5931 {
5932 emit_insn (gen_adddi3 (operands[0], operands[1],
5933 negate_rtx (DImode, operands[2])));
5934 DONE;
5935 }
5936 }")
5938 (define_insn_and_split "absdi2"
5939 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5940 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5941 (clobber (match_scratch:DI 2 "=&r,&r"))]
5942 "TARGET_POWERPC64"
5943 "#"
5944 "&& reload_completed"
5945 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5946 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5947 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5948 "")
5950 (define_insn_and_split "*nabsdi2"
5951 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5952 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5953 (clobber (match_scratch:DI 2 "=&r,&r"))]
5954 "TARGET_POWERPC64"
5955 "#"
5956 "&& reload_completed"
5957 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5958 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5959 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5960 "")
5962 (define_expand "negdi2"
5963 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5964 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5965 ""
5966 "")
5968 (define_insn ""
5969 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5970 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5971 "TARGET_POWERPC64"
5972 "neg %0,%1")
5974 (define_insn ""
5975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5976 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5977 (const_int 0)))
5978 (clobber (match_scratch:DI 2 "=r,r"))]
5979 "TARGET_64BIT"
5980 "@
5981 neg. %2,%1
5982 #"
5983 [(set_attr "type" "fast_compare")
5984 (set_attr "length" "4,8")])
5986 (define_split
5987 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5988 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5989 (const_int 0)))
5990 (clobber (match_scratch:DI 2 ""))]
5991 "TARGET_POWERPC64 && reload_completed"
5992 [(set (match_dup 2)
5993 (neg:DI (match_dup 1)))
5994 (set (match_dup 0)
5995 (compare:CC (match_dup 2)
5996 (const_int 0)))]
5997 "")
5999 (define_insn ""
6000 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6001 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6002 (const_int 0)))
6003 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6004 (neg:DI (match_dup 1)))]
6005 "TARGET_64BIT"
6006 "@
6007 neg. %0,%1
6008 #"
6009 [(set_attr "type" "fast_compare")
6010 (set_attr "length" "4,8")])
6012 (define_split
6013 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6014 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6015 (const_int 0)))
6016 (set (match_operand:DI 0 "gpc_reg_operand" "")
6017 (neg:DI (match_dup 1)))]
6018 "TARGET_POWERPC64 && reload_completed"
6019 [(set (match_dup 0)
6020 (neg:DI (match_dup 1)))
6021 (set (match_dup 2)
6022 (compare:CC (match_dup 0)
6023 (const_int 0)))]
6024 "")
6026 (define_insn "clzdi2"
6027 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6028 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6029 "TARGET_POWERPC64"
6030 "cntlzd %0,%1")
6032 (define_expand "ctzdi2"
6033 [(set (match_dup 2)
6034 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6035 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6036 (match_dup 2)))
6037 (clobber (scratch:CC))])
6038 (set (match_dup 4) (clz:DI (match_dup 3)))
6039 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6040 (minus:DI (const_int 63) (match_dup 4)))]
6041 "TARGET_POWERPC64"
6042 {
6043 operands[2] = gen_reg_rtx (DImode);
6044 operands[3] = gen_reg_rtx (DImode);
6045 operands[4] = gen_reg_rtx (DImode);
6046 })
6048 (define_expand "ffsdi2"
6049 [(set (match_dup 2)
6050 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6051 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6052 (match_dup 2)))
6053 (clobber (scratch:CC))])
6054 (set (match_dup 4) (clz:DI (match_dup 3)))
6055 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6056 (minus:DI (const_int 64) (match_dup 4)))]
6057 "TARGET_POWERPC64"
6058 {
6059 operands[2] = gen_reg_rtx (DImode);
6060 operands[3] = gen_reg_rtx (DImode);
6061 operands[4] = gen_reg_rtx (DImode);
6062 })
6064 (define_insn "muldi3"
6065 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6066 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6067 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6068 "TARGET_POWERPC64"
6069 "mulld %0,%1,%2"
6070 [(set_attr "type" "lmul")])
6072 (define_insn "*muldi3_internal1"
6073 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6074 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6075 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6076 (const_int 0)))
6077 (clobber (match_scratch:DI 3 "=r,r"))]
6078 "TARGET_POWERPC64"
6079 "@
6080 mulld. %3,%1,%2
6081 #"
6082 [(set_attr "type" "lmul_compare")
6083 (set_attr "length" "4,8")])
6085 (define_split
6086 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6087 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6088 (match_operand:DI 2 "gpc_reg_operand" ""))
6089 (const_int 0)))
6090 (clobber (match_scratch:DI 3 ""))]
6091 "TARGET_POWERPC64 && reload_completed"
6092 [(set (match_dup 3)
6093 (mult:DI (match_dup 1) (match_dup 2)))
6094 (set (match_dup 0)
6095 (compare:CC (match_dup 3)
6096 (const_int 0)))]
6097 "")
6099 (define_insn "*muldi3_internal2"
6100 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6101 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6102 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6103 (const_int 0)))
6104 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6105 (mult:DI (match_dup 1) (match_dup 2)))]
6106 "TARGET_POWERPC64"
6107 "@
6108 mulld. %0,%1,%2
6109 #"
6110 [(set_attr "type" "lmul_compare")
6111 (set_attr "length" "4,8")])
6113 (define_split
6114 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6115 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6116 (match_operand:DI 2 "gpc_reg_operand" ""))
6117 (const_int 0)))
6118 (set (match_operand:DI 0 "gpc_reg_operand" "")
6119 (mult:DI (match_dup 1) (match_dup 2)))]
6120 "TARGET_POWERPC64 && reload_completed"
6121 [(set (match_dup 0)
6122 (mult:DI (match_dup 1) (match_dup 2)))
6123 (set (match_dup 3)
6124 (compare:CC (match_dup 0)
6125 (const_int 0)))]
6126 "")
6128 (define_insn "smuldi3_highpart"
6129 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6130 (truncate:DI
6131 (lshiftrt:TI (mult:TI (sign_extend:TI
6132 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6133 (sign_extend:TI
6134 (match_operand:DI 2 "gpc_reg_operand" "r")))
6135 (const_int 64))))]
6136 "TARGET_POWERPC64"
6137 "mulhd %0,%1,%2"
6138 [(set_attr "type" "lmul")])
6140 (define_insn "umuldi3_highpart"
6141 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6142 (truncate:DI
6143 (lshiftrt:TI (mult:TI (zero_extend:TI
6144 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6145 (zero_extend:TI
6146 (match_operand:DI 2 "gpc_reg_operand" "r")))
6147 (const_int 64))))]
6148 "TARGET_POWERPC64"
6149 "mulhdu %0,%1,%2"
6150 [(set_attr "type" "lmul")])
6152 (define_expand "divdi3"
6153 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6154 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6155 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6156 "TARGET_POWERPC64"
6157 "
6158 {
6159 if (GET_CODE (operands[2]) == CONST_INT
6160 && INTVAL (operands[2]) > 0
6161 && exact_log2 (INTVAL (operands[2])) >= 0)
6162 ;
6163 else
6164 operands[2] = force_reg (DImode, operands[2]);
6165 }")
6167 (define_expand "moddi3"
6168 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6169 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6170 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6171 "TARGET_POWERPC64"
6172 "
6173 {
6174 int i;
6175 rtx temp1;
6176 rtx temp2;
6178 if (GET_CODE (operands[2]) != CONST_INT
6179 || INTVAL (operands[2]) <= 0
6180 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6181 FAIL;
6183 temp1 = gen_reg_rtx (DImode);
6184 temp2 = gen_reg_rtx (DImode);
6186 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6187 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6188 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6189 DONE;
6190 }")
6192 (define_insn ""
6193 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6194 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6195 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6196 "TARGET_POWERPC64"
6197 "sradi %0,%1,%p2\;addze %0,%0"
6198 [(set_attr "length" "8")])
6200 (define_insn ""
6201 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6202 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6203 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6204 (const_int 0)))
6205 (clobber (match_scratch:DI 3 "=r,r"))]
6206 "TARGET_64BIT"
6207 "@
6208 sradi %3,%1,%p2\;addze. %3,%3
6209 #"
6210 [(set_attr "type" "compare")
6211 (set_attr "length" "8,12")])
6213 (define_split
6214 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6215 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6216 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6217 (const_int 0)))
6218 (clobber (match_scratch:DI 3 ""))]
6219 "TARGET_POWERPC64 && reload_completed"
6220 [(set (match_dup 3)
6221 (div:DI (match_dup 1) (match_dup 2)))
6222 (set (match_dup 0)
6223 (compare:CC (match_dup 3)
6224 (const_int 0)))]
6225 "")
6227 (define_insn ""
6228 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6229 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6230 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6231 (const_int 0)))
6232 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6233 (div:DI (match_dup 1) (match_dup 2)))]
6234 "TARGET_64BIT"
6235 "@
6236 sradi %0,%1,%p2\;addze. %0,%0
6237 #"
6238 [(set_attr "type" "compare")
6239 (set_attr "length" "8,12")])
6241 (define_split
6242 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6243 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6244 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6245 (const_int 0)))
6246 (set (match_operand:DI 0 "gpc_reg_operand" "")
6247 (div:DI (match_dup 1) (match_dup 2)))]
6248 "TARGET_POWERPC64 && reload_completed"
6249 [(set (match_dup 0)
6250 (div:DI (match_dup 1) (match_dup 2)))
6251 (set (match_dup 3)
6252 (compare:CC (match_dup 0)
6253 (const_int 0)))]
6254 "")
6256 (define_insn ""
6257 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6258 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6259 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6260 "TARGET_POWERPC64"
6261 "divd %0,%1,%2"
6262 [(set_attr "type" "ldiv")])
6264 (define_insn "udivdi3"
6265 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6266 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6267 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6268 "TARGET_POWERPC64"
6269 "divdu %0,%1,%2"
6270 [(set_attr "type" "ldiv")])
6272 (define_insn "rotldi3"
6273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6274 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6275 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6276 "TARGET_POWERPC64"
6277 "rld%I2cl %0,%1,%H2,0")
6279 (define_insn "*rotldi3_internal2"
6280 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6281 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6282 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6283 (const_int 0)))
6284 (clobber (match_scratch:DI 3 "=r,r"))]
6285 "TARGET_64BIT"
6286 "@
6287 rld%I2cl. %3,%1,%H2,0
6288 #"
6289 [(set_attr "type" "delayed_compare")
6290 (set_attr "length" "4,8")])
6292 (define_split
6293 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6294 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6295 (match_operand:DI 2 "reg_or_cint_operand" ""))
6296 (const_int 0)))
6297 (clobber (match_scratch:DI 3 ""))]
6298 "TARGET_POWERPC64 && reload_completed"
6299 [(set (match_dup 3)
6300 (rotate:DI (match_dup 1) (match_dup 2)))
6301 (set (match_dup 0)
6302 (compare:CC (match_dup 3)
6303 (const_int 0)))]
6304 "")
6306 (define_insn "*rotldi3_internal3"
6307 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6308 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6309 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6310 (const_int 0)))
6311 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6312 (rotate:DI (match_dup 1) (match_dup 2)))]
6313 "TARGET_64BIT"
6314 "@
6315 rld%I2cl. %0,%1,%H2,0
6316 #"
6317 [(set_attr "type" "delayed_compare")
6318 (set_attr "length" "4,8")])
6320 (define_split
6321 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6322 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6323 (match_operand:DI 2 "reg_or_cint_operand" ""))
6324 (const_int 0)))
6325 (set (match_operand:DI 0 "gpc_reg_operand" "")
6326 (rotate:DI (match_dup 1) (match_dup 2)))]
6327 "TARGET_POWERPC64 && reload_completed"
6328 [(set (match_dup 0)
6329 (rotate:DI (match_dup 1) (match_dup 2)))
6330 (set (match_dup 3)
6331 (compare:CC (match_dup 0)
6332 (const_int 0)))]
6333 "")
6335 (define_insn "*rotldi3_internal4"
6336 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6337 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6338 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6339 (match_operand:DI 3 "mask64_operand" "n")))]
6340 "TARGET_POWERPC64"
6341 "rld%I2c%B3 %0,%1,%H2,%S3")
6343 (define_insn "*rotldi3_internal5"
6344 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6345 (compare:CC (and:DI
6346 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6347 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6348 (match_operand:DI 3 "mask64_operand" "n,n"))
6349 (const_int 0)))
6350 (clobber (match_scratch:DI 4 "=r,r"))]
6351 "TARGET_64BIT"
6352 "@
6353 rld%I2c%B3. %4,%1,%H2,%S3
6354 #"
6355 [(set_attr "type" "delayed_compare")
6356 (set_attr "length" "4,8")])
6358 (define_split
6359 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6360 (compare:CC (and:DI
6361 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6362 (match_operand:DI 2 "reg_or_cint_operand" ""))
6363 (match_operand:DI 3 "mask64_operand" ""))
6364 (const_int 0)))
6365 (clobber (match_scratch:DI 4 ""))]
6366 "TARGET_POWERPC64 && reload_completed"
6367 [(set (match_dup 4)
6368 (and:DI (rotate:DI (match_dup 1)
6369 (match_dup 2))
6370 (match_dup 3)))
6371 (set (match_dup 0)
6372 (compare:CC (match_dup 4)
6373 (const_int 0)))]
6374 "")
6376 (define_insn "*rotldi3_internal6"
6377 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6378 (compare:CC (and:DI
6379 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6380 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6381 (match_operand:DI 3 "mask64_operand" "n,n"))
6382 (const_int 0)))
6383 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6384 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6385 "TARGET_64BIT"
6386 "@
6387 rld%I2c%B3. %0,%1,%H2,%S3
6388 #"
6389 [(set_attr "type" "delayed_compare")
6390 (set_attr "length" "4,8")])
6392 (define_split
6393 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6394 (compare:CC (and:DI
6395 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6396 (match_operand:DI 2 "reg_or_cint_operand" ""))
6397 (match_operand:DI 3 "mask64_operand" ""))
6398 (const_int 0)))
6399 (set (match_operand:DI 0 "gpc_reg_operand" "")
6400 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6401 "TARGET_POWERPC64 && reload_completed"
6402 [(set (match_dup 0)
6403 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6404 (set (match_dup 4)
6405 (compare:CC (match_dup 0)
6406 (const_int 0)))]
6407 "")
6409 (define_insn "*rotldi3_internal7"
6410 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6411 (zero_extend:DI
6412 (subreg:QI
6413 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6414 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6415 "TARGET_POWERPC64"
6416 "rld%I2cl %0,%1,%H2,56")
6418 (define_insn "*rotldi3_internal8"
6419 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6420 (compare:CC (zero_extend:DI
6421 (subreg:QI
6422 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6423 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6424 (const_int 0)))
6425 (clobber (match_scratch:DI 3 "=r,r"))]
6426 "TARGET_64BIT"
6427 "@
6428 rld%I2cl. %3,%1,%H2,56
6429 #"
6430 [(set_attr "type" "delayed_compare")
6431 (set_attr "length" "4,8")])
6433 (define_split
6434 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6435 (compare:CC (zero_extend:DI
6436 (subreg:QI
6437 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6438 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6439 (const_int 0)))
6440 (clobber (match_scratch:DI 3 ""))]
6441 "TARGET_POWERPC64 && reload_completed"
6442 [(set (match_dup 3)
6443 (zero_extend:DI (subreg:QI
6444 (rotate:DI (match_dup 1)
6445 (match_dup 2)) 0)))
6446 (set (match_dup 0)
6447 (compare:CC (match_dup 3)
6448 (const_int 0)))]
6449 "")
6451 (define_insn "*rotldi3_internal9"
6452 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6453 (compare:CC (zero_extend:DI
6454 (subreg:QI
6455 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6456 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6457 (const_int 0)))
6458 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6459 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6460 "TARGET_64BIT"
6461 "@
6462 rld%I2cl. %0,%1,%H2,56
6463 #"
6464 [(set_attr "type" "delayed_compare")
6465 (set_attr "length" "4,8")])
6467 (define_split
6468 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6469 (compare:CC (zero_extend:DI
6470 (subreg:QI
6471 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6472 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6473 (const_int 0)))
6474 (set (match_operand:DI 0 "gpc_reg_operand" "")
6475 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6476 "TARGET_POWERPC64 && reload_completed"
6477 [(set (match_dup 0)
6478 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6479 (set (match_dup 3)
6480 (compare:CC (match_dup 0)
6481 (const_int 0)))]
6482 "")
6484 (define_insn "*rotldi3_internal10"
6485 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6486 (zero_extend:DI
6487 (subreg:HI
6488 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6489 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6490 "TARGET_POWERPC64"
6491 "rld%I2cl %0,%1,%H2,48")
6493 (define_insn "*rotldi3_internal11"
6494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6495 (compare:CC (zero_extend:DI
6496 (subreg:HI
6497 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6498 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6499 (const_int 0)))
6500 (clobber (match_scratch:DI 3 "=r,r"))]
6501 "TARGET_64BIT"
6502 "@
6503 rld%I2cl. %3,%1,%H2,48
6504 #"
6505 [(set_attr "type" "delayed_compare")
6506 (set_attr "length" "4,8")])
6508 (define_split
6509 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6510 (compare:CC (zero_extend:DI
6511 (subreg:HI
6512 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6513 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6514 (const_int 0)))
6515 (clobber (match_scratch:DI 3 ""))]
6516 "TARGET_POWERPC64 && reload_completed"
6517 [(set (match_dup 3)
6518 (zero_extend:DI (subreg:HI
6519 (rotate:DI (match_dup 1)
6520 (match_dup 2)) 0)))
6521 (set (match_dup 0)
6522 (compare:CC (match_dup 3)
6523 (const_int 0)))]
6524 "")
6526 (define_insn "*rotldi3_internal12"
6527 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6528 (compare:CC (zero_extend:DI
6529 (subreg:HI
6530 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6531 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6532 (const_int 0)))
6533 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6534 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6535 "TARGET_64BIT"
6536 "@
6537 rld%I2cl. %0,%1,%H2,48
6538 #"
6539 [(set_attr "type" "delayed_compare")
6540 (set_attr "length" "4,8")])
6542 (define_split
6543 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6544 (compare:CC (zero_extend:DI
6545 (subreg:HI
6546 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6547 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6548 (const_int 0)))
6549 (set (match_operand:DI 0 "gpc_reg_operand" "")
6550 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6551 "TARGET_POWERPC64 && reload_completed"
6552 [(set (match_dup 0)
6553 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6554 (set (match_dup 3)
6555 (compare:CC (match_dup 0)
6556 (const_int 0)))]
6557 "")
6559 (define_insn "*rotldi3_internal13"
6560 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6561 (zero_extend:DI
6562 (subreg:SI
6563 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6564 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6565 "TARGET_POWERPC64"
6566 "rld%I2cl %0,%1,%H2,32")
6568 (define_insn "*rotldi3_internal14"
6569 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6570 (compare:CC (zero_extend:DI
6571 (subreg:SI
6572 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6573 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6574 (const_int 0)))
6575 (clobber (match_scratch:DI 3 "=r,r"))]
6576 "TARGET_64BIT"
6577 "@
6578 rld%I2cl. %3,%1,%H2,32
6579 #"
6580 [(set_attr "type" "delayed_compare")
6581 (set_attr "length" "4,8")])
6583 (define_split
6584 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6585 (compare:CC (zero_extend:DI
6586 (subreg:SI
6587 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6588 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6589 (const_int 0)))
6590 (clobber (match_scratch:DI 3 ""))]
6591 "TARGET_POWERPC64 && reload_completed"
6592 [(set (match_dup 3)
6593 (zero_extend:DI (subreg:SI
6594 (rotate:DI (match_dup 1)
6595 (match_dup 2)) 0)))
6596 (set (match_dup 0)
6597 (compare:CC (match_dup 3)
6598 (const_int 0)))]
6599 "")
6601 (define_insn "*rotldi3_internal15"
6602 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6603 (compare:CC (zero_extend:DI
6604 (subreg:SI
6605 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6606 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6607 (const_int 0)))
6608 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6609 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6610 "TARGET_64BIT"
6611 "@
6612 rld%I2cl. %0,%1,%H2,32
6613 #"
6614 [(set_attr "type" "delayed_compare")
6615 (set_attr "length" "4,8")])
6617 (define_split
6618 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6619 (compare:CC (zero_extend:DI
6620 (subreg:SI
6621 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6622 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6623 (const_int 0)))
6624 (set (match_operand:DI 0 "gpc_reg_operand" "")
6625 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6626 "TARGET_POWERPC64 && reload_completed"
6627 [(set (match_dup 0)
6628 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6629 (set (match_dup 3)
6630 (compare:CC (match_dup 0)
6631 (const_int 0)))]
6632 "")
6634 (define_expand "ashldi3"
6635 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6636 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6637 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6638 "TARGET_POWERPC64 || TARGET_POWER"
6639 "
6640 {
6641 if (TARGET_POWERPC64)
6642 ;
6643 else if (TARGET_POWER)
6644 {
6645 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6646 DONE;
6647 }
6648 else
6649 FAIL;
6650 }")
6652 (define_insn "*ashldi3_internal1"
6653 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6654 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6655 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6656 "TARGET_POWERPC64"
6657 "sld%I2 %0,%1,%H2"
6658 [(set_attr "length" "8")])
6660 (define_insn "*ashldi3_internal2"
6661 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6662 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6663 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6664 (const_int 0)))
6665 (clobber (match_scratch:DI 3 "=r,r"))]
6666 "TARGET_64BIT"
6667 "@
6668 sld%I2. %3,%1,%H2
6669 #"
6670 [(set_attr "type" "delayed_compare")
6671 (set_attr "length" "4,8")])
6673 (define_split
6674 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6675 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6676 (match_operand:SI 2 "reg_or_cint_operand" ""))
6677 (const_int 0)))
6678 (clobber (match_scratch:DI 3 ""))]
6679 "TARGET_POWERPC64 && reload_completed"
6680 [(set (match_dup 3)
6681 (ashift:DI (match_dup 1) (match_dup 2)))
6682 (set (match_dup 0)
6683 (compare:CC (match_dup 3)
6684 (const_int 0)))]
6685 "")
6687 (define_insn "*ashldi3_internal3"
6688 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6689 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6690 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6691 (const_int 0)))
6692 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6693 (ashift:DI (match_dup 1) (match_dup 2)))]
6694 "TARGET_64BIT"
6695 "@
6696 sld%I2. %0,%1,%H2
6697 #"
6698 [(set_attr "type" "delayed_compare")
6699 (set_attr "length" "4,8")])
6701 (define_split
6702 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6703 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6704 (match_operand:SI 2 "reg_or_cint_operand" ""))
6705 (const_int 0)))
6706 (set (match_operand:DI 0 "gpc_reg_operand" "")
6707 (ashift:DI (match_dup 1) (match_dup 2)))]
6708 "TARGET_POWERPC64 && reload_completed"
6709 [(set (match_dup 0)
6710 (ashift:DI (match_dup 1) (match_dup 2)))
6711 (set (match_dup 3)
6712 (compare:CC (match_dup 0)
6713 (const_int 0)))]
6714 "")
6716 (define_insn "*ashldi3_internal4"
6717 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6718 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6719 (match_operand:SI 2 "const_int_operand" "i"))
6720 (match_operand:DI 3 "const_int_operand" "n")))]
6721 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6722 "rldic %0,%1,%H2,%W3")
6724 (define_insn "ashldi3_internal5"
6725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6726 (compare:CC
6727 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6728 (match_operand:SI 2 "const_int_operand" "i,i"))
6729 (match_operand:DI 3 "const_int_operand" "n,n"))
6730 (const_int 0)))
6731 (clobber (match_scratch:DI 4 "=r,r"))]
6732 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6733 "@
6734 rldic. %4,%1,%H2,%W3
6735 #"
6736 [(set_attr "type" "delayed_compare")
6737 (set_attr "length" "4,8")])
6739 (define_split
6740 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6741 (compare:CC
6742 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6743 (match_operand:SI 2 "const_int_operand" ""))
6744 (match_operand:DI 3 "const_int_operand" ""))
6745 (const_int 0)))
6746 (clobber (match_scratch:DI 4 ""))]
6747 "TARGET_POWERPC64 && reload_completed
6748 && includes_rldic_lshift_p (operands[2], operands[3])"
6749 [(set (match_dup 4)
6750 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6751 (match_dup 3)))
6752 (set (match_dup 0)
6753 (compare:CC (match_dup 4)
6754 (const_int 0)))]
6755 "")
6757 (define_insn "*ashldi3_internal6"
6758 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6759 (compare:CC
6760 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6761 (match_operand:SI 2 "const_int_operand" "i,i"))
6762 (match_operand:DI 3 "const_int_operand" "n,n"))
6763 (const_int 0)))
6764 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6765 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6766 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6767 "@
6768 rldic. %0,%1,%H2,%W3
6769 #"
6770 [(set_attr "type" "delayed_compare")
6771 (set_attr "length" "4,8")])
6773 (define_split
6774 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6775 (compare:CC
6776 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6777 (match_operand:SI 2 "const_int_operand" ""))
6778 (match_operand:DI 3 "const_int_operand" ""))
6779 (const_int 0)))
6780 (set (match_operand:DI 0 "gpc_reg_operand" "")
6781 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6782 "TARGET_POWERPC64 && reload_completed
6783 && includes_rldic_lshift_p (operands[2], operands[3])"
6784 [(set (match_dup 0)
6785 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6786 (match_dup 3)))
6787 (set (match_dup 4)
6788 (compare:CC (match_dup 0)
6789 (const_int 0)))]
6790 "")
6792 (define_insn "*ashldi3_internal7"
6793 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6794 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6795 (match_operand:SI 2 "const_int_operand" "i"))
6796 (match_operand:DI 3 "mask64_operand" "n")))]
6797 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6798 "rldicr %0,%1,%H2,%S3")
6800 (define_insn "ashldi3_internal8"
6801 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6802 (compare:CC
6803 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6804 (match_operand:SI 2 "const_int_operand" "i,i"))
6805 (match_operand:DI 3 "mask64_operand" "n,n"))
6806 (const_int 0)))
6807 (clobber (match_scratch:DI 4 "=r,r"))]
6808 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6809 "@
6810 rldicr. %4,%1,%H2,%S3
6811 #"
6812 [(set_attr "type" "delayed_compare")
6813 (set_attr "length" "4,8")])
6815 (define_split
6816 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6817 (compare:CC
6818 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6819 (match_operand:SI 2 "const_int_operand" ""))
6820 (match_operand:DI 3 "mask64_operand" ""))
6821 (const_int 0)))
6822 (clobber (match_scratch:DI 4 ""))]
6823 "TARGET_POWERPC64 && reload_completed
6824 && includes_rldicr_lshift_p (operands[2], operands[3])"
6825 [(set (match_dup 4)
6826 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6827 (match_dup 3)))
6828 (set (match_dup 0)
6829 (compare:CC (match_dup 4)
6830 (const_int 0)))]
6831 "")
6833 (define_insn "*ashldi3_internal9"
6834 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6835 (compare:CC
6836 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6837 (match_operand:SI 2 "const_int_operand" "i,i"))
6838 (match_operand:DI 3 "mask64_operand" "n,n"))
6839 (const_int 0)))
6840 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6841 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6842 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6843 "@
6844 rldicr. %0,%1,%H2,%S3
6845 #"
6846 [(set_attr "type" "delayed_compare")
6847 (set_attr "length" "4,8")])
6849 (define_split
6850 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6851 (compare:CC
6852 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6853 (match_operand:SI 2 "const_int_operand" ""))
6854 (match_operand:DI 3 "mask64_operand" ""))
6855 (const_int 0)))
6856 (set (match_operand:DI 0 "gpc_reg_operand" "")
6857 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6858 "TARGET_POWERPC64 && reload_completed
6859 && includes_rldicr_lshift_p (operands[2], operands[3])"
6860 [(set (match_dup 0)
6861 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6862 (match_dup 3)))
6863 (set (match_dup 4)
6864 (compare:CC (match_dup 0)
6865 (const_int 0)))]
6866 "")
6868 (define_expand "lshrdi3"
6869 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6870 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6871 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6872 "TARGET_POWERPC64 || TARGET_POWER"
6873 "
6874 {
6875 if (TARGET_POWERPC64)
6876 ;
6877 else if (TARGET_POWER)
6878 {
6879 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6880 DONE;
6881 }
6882 else
6883 FAIL;
6884 }")
6886 (define_insn "*lshrdi3_internal1"
6887 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6888 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6889 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6890 "TARGET_POWERPC64"
6891 "srd%I2 %0,%1,%H2")
6893 (define_insn "*lshrdi3_internal2"
6894 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6895 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6896 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6897 (const_int 0)))
6898 (clobber (match_scratch:DI 3 "=r,r"))]
6899 "TARGET_64BIT "
6900 "@
6901 srd%I2. %3,%1,%H2
6902 #"
6903 [(set_attr "type" "delayed_compare")
6904 (set_attr "length" "4,8")])
6906 (define_split
6907 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6908 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6909 (match_operand:SI 2 "reg_or_cint_operand" ""))
6910 (const_int 0)))
6911 (clobber (match_scratch:DI 3 ""))]
6912 "TARGET_POWERPC64 && reload_completed"
6913 [(set (match_dup 3)
6914 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6915 (set (match_dup 0)
6916 (compare:CC (match_dup 3)
6917 (const_int 0)))]
6918 "")
6920 (define_insn "*lshrdi3_internal3"
6921 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6922 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6923 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6924 (const_int 0)))
6925 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6926 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6927 "TARGET_64BIT"
6928 "@
6929 srd%I2. %0,%1,%H2
6930 #"
6931 [(set_attr "type" "delayed_compare")
6932 (set_attr "length" "4,8")])
6934 (define_split
6935 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6936 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6937 (match_operand:SI 2 "reg_or_cint_operand" ""))
6938 (const_int 0)))
6939 (set (match_operand:DI 0 "gpc_reg_operand" "")
6940 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6941 "TARGET_POWERPC64 && reload_completed"
6942 [(set (match_dup 0)
6943 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6944 (set (match_dup 3)
6945 (compare:CC (match_dup 0)
6946 (const_int 0)))]
6947 "")
6949 (define_expand "ashrdi3"
6950 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6951 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6952 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6953 "WORDS_BIG_ENDIAN"
6954 "
6955 {
6956 if (TARGET_POWERPC64)
6957 ;
6958 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6959 {
6960 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6961 DONE;
6962 }
6963 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6964 && WORDS_BIG_ENDIAN)
6965 {
6966 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6967 DONE;
6968 }
6969 else
6970 FAIL;
6971 }")
6973 (define_insn "*ashrdi3_internal1"
6974 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6975 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6976 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6977 "TARGET_POWERPC64"
6978 "srad%I2 %0,%1,%H2")
6980 (define_insn "*ashrdi3_internal2"
6981 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6982 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6983 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6984 (const_int 0)))
6985 (clobber (match_scratch:DI 3 "=r,r"))]
6986 "TARGET_64BIT"
6987 "@
6988 srad%I2. %3,%1,%H2
6989 #"
6990 [(set_attr "type" "delayed_compare")
6991 (set_attr "length" "4,8")])
6993 (define_split
6994 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6995 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6996 (match_operand:SI 2 "reg_or_cint_operand" ""))
6997 (const_int 0)))
6998 (clobber (match_scratch:DI 3 ""))]
6999 "TARGET_POWERPC64 && reload_completed"
7000 [(set (match_dup 3)
7001 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7002 (set (match_dup 0)
7003 (compare:CC (match_dup 3)
7004 (const_int 0)))]
7005 "")
7007 (define_insn "*ashrdi3_internal3"
7008 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7009 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7010 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7011 (const_int 0)))
7012 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7013 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7014 "TARGET_64BIT"
7015 "@
7016 srad%I2. %0,%1,%H2
7017 #"
7018 [(set_attr "type" "delayed_compare")
7019 (set_attr "length" "4,8")])
7021 (define_split
7022 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7023 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7024 (match_operand:SI 2 "reg_or_cint_operand" ""))
7025 (const_int 0)))
7026 (set (match_operand:DI 0 "gpc_reg_operand" "")
7027 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7028 "TARGET_POWERPC64 && reload_completed"
7029 [(set (match_dup 0)
7030 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7031 (set (match_dup 3)
7032 (compare:CC (match_dup 0)
7033 (const_int 0)))]
7034 "")
7036 (define_insn "anddi3"
7037 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
7038 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
7039 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
7040 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
7041 "TARGET_POWERPC64"
7042 "@
7043 and %0,%1,%2
7044 rldic%B2 %0,%1,0,%S2
7045 andi. %0,%1,%b2
7046 andis. %0,%1,%u2
7047 #"
7048 [(set_attr "length" "4,4,4,4,8")])
7050 (define_split
7051 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7052 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7053 (match_operand:DI 2 "mask64_2_operand" "")))
7054 (clobber (match_scratch:CC 3 ""))]
7055 "TARGET_POWERPC64
7056 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7057 && !mask64_operand (operands[2], DImode)"
7058 [(set (match_dup 0)
7059 (and:DI (rotate:DI (match_dup 1)
7060 (match_dup 4))
7061 (match_dup 5)))
7062 (set (match_dup 0)
7063 (and:DI (rotate:DI (match_dup 0)
7064 (match_dup 6))
7065 (match_dup 7)))]
7066 "
7067 {
7068 build_mask64_2_operands (operands[2], &operands[4]);
7069 }")
7071 (define_insn "*anddi3_internal2"
7072 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7073 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7074 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7075 (const_int 0)))
7076 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7077 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7078 "TARGET_64BIT"
7079 "@
7080 and. %3,%1,%2
7081 rldic%B2. %3,%1,0,%S2
7082 andi. %3,%1,%b2
7083 andis. %3,%1,%u2
7084 #
7085 #
7086 #
7087 #
7088 #
7089 #"
7090 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7091 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7093 (define_split
7094 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7095 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7096 (match_operand:DI 2 "and64_operand" ""))
7097 (const_int 0)))
7098 (clobber (match_scratch:DI 3 ""))
7099 (clobber (match_scratch:CC 4 ""))]
7100 "TARGET_POWERPC64 && reload_completed"
7101 [(parallel [(set (match_dup 3)
7102 (and:DI (match_dup 1)
7103 (match_dup 2)))
7104 (clobber (match_dup 4))])
7105 (set (match_dup 0)
7106 (compare:CC (match_dup 3)
7107 (const_int 0)))]
7108 "")
7110 (define_split
7111 [(set (match_operand:CC 0 "cc_reg_operand" "")
7112 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7113 (match_operand:DI 2 "mask64_2_operand" ""))
7114 (const_int 0)))
7115 (clobber (match_scratch:DI 3 ""))
7116 (clobber (match_scratch:CC 4 ""))]
7117 "TARGET_POWERPC64 && reload_completed
7118 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7119 && !mask64_operand (operands[2], DImode)"
7120 [(set (match_dup 3)
7121 (and:DI (rotate:DI (match_dup 1)
7122 (match_dup 5))
7123 (match_dup 6)))
7124 (parallel [(set (match_dup 0)
7125 (compare:CC (and:DI (rotate:DI (match_dup 3)
7126 (match_dup 7))
7127 (match_dup 8))
7128 (const_int 0)))
7129 (clobber (match_dup 3))])]
7130 "
7131 {
7132 build_mask64_2_operands (operands[2], &operands[5]);
7133 }")
7135 (define_insn "*anddi3_internal3"
7136 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7137 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7138 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7139 (const_int 0)))
7140 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7141 (and:DI (match_dup 1) (match_dup 2)))
7142 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7143 "TARGET_64BIT"
7144 "@
7145 and. %0,%1,%2
7146 rldic%B2. %0,%1,0,%S2
7147 andi. %0,%1,%b2
7148 andis. %0,%1,%u2
7149 #
7150 #
7151 #
7152 #
7153 #
7154 #"
7155 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7156 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7158 (define_split
7159 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7160 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7161 (match_operand:DI 2 "and64_operand" ""))
7162 (const_int 0)))
7163 (set (match_operand:DI 0 "gpc_reg_operand" "")
7164 (and:DI (match_dup 1) (match_dup 2)))
7165 (clobber (match_scratch:CC 4 ""))]
7166 "TARGET_POWERPC64 && reload_completed"
7167 [(parallel [(set (match_dup 0)
7168 (and:DI (match_dup 1) (match_dup 2)))
7169 (clobber (match_dup 4))])
7170 (set (match_dup 3)
7171 (compare:CC (match_dup 0)
7172 (const_int 0)))]
7173 "")
7175 (define_split
7176 [(set (match_operand:CC 3 "cc_reg_operand" "")
7177 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7178 (match_operand:DI 2 "mask64_2_operand" ""))
7179 (const_int 0)))
7180 (set (match_operand:DI 0 "gpc_reg_operand" "")
7181 (and:DI (match_dup 1) (match_dup 2)))
7182 (clobber (match_scratch:CC 4 ""))]
7183 "TARGET_POWERPC64 && reload_completed
7184 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7185 && !mask64_operand (operands[2], DImode)"
7186 [(set (match_dup 0)
7187 (and:DI (rotate:DI (match_dup 1)
7188 (match_dup 5))
7189 (match_dup 6)))
7190 (parallel [(set (match_dup 3)
7191 (compare:CC (and:DI (rotate:DI (match_dup 0)
7192 (match_dup 7))
7193 (match_dup 8))
7194 (const_int 0)))
7195 (set (match_dup 0)
7196 (and:DI (rotate:DI (match_dup 0)
7197 (match_dup 7))
7198 (match_dup 8)))])]
7199 "
7200 {
7201 build_mask64_2_operands (operands[2], &operands[5]);
7202 }")
7204 (define_expand "iordi3"
7205 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7206 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7207 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7208 "TARGET_POWERPC64"
7209 "
7210 {
7211 if (non_logical_cint_operand (operands[2], DImode))
7212 {
7213 HOST_WIDE_INT value;
7214 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7215 ? operands[0] : gen_reg_rtx (DImode));
7217 if (GET_CODE (operands[2]) == CONST_INT)
7218 {
7219 value = INTVAL (operands[2]);
7220 emit_insn (gen_iordi3 (tmp, operands[1],
7221 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7222 }
7223 else
7224 {
7225 value = CONST_DOUBLE_LOW (operands[2]);
7226 emit_insn (gen_iordi3 (tmp, operands[1],
7227 immed_double_const (value
7228 & (~ (HOST_WIDE_INT) 0xffff),
7229 0, DImode)));
7230 }
7232 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7233 DONE;
7234 }
7235 }")
7237 (define_expand "xordi3"
7238 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7239 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7240 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7241 "TARGET_POWERPC64"
7242 "
7243 {
7244 if (non_logical_cint_operand (operands[2], DImode))
7245 {
7246 HOST_WIDE_INT value;
7247 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7248 ? operands[0] : gen_reg_rtx (DImode));
7250 if (GET_CODE (operands[2]) == CONST_INT)
7251 {
7252 value = INTVAL (operands[2]);
7253 emit_insn (gen_xordi3 (tmp, operands[1],
7254 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7255 }
7256 else
7257 {
7258 value = CONST_DOUBLE_LOW (operands[2]);
7259 emit_insn (gen_xordi3 (tmp, operands[1],
7260 immed_double_const (value
7261 & (~ (HOST_WIDE_INT) 0xffff),
7262 0, DImode)));
7263 }
7265 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7266 DONE;
7267 }
7268 }")
7270 (define_insn "*booldi3_internal1"
7271 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7272 (match_operator:DI 3 "boolean_or_operator"
7273 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7274 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7275 "TARGET_POWERPC64"
7276 "@
7277 %q3 %0,%1,%2
7278 %q3i %0,%1,%b2
7279 %q3is %0,%1,%u2")
7281 (define_insn "*booldi3_internal2"
7282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7283 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7284 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7285 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7286 (const_int 0)))
7287 (clobber (match_scratch:DI 3 "=r,r"))]
7288 "TARGET_64BIT"
7289 "@
7290 %q4. %3,%1,%2
7291 #"
7292 [(set_attr "type" "compare")
7293 (set_attr "length" "4,8")])
7295 (define_split
7296 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7297 (compare:CC (match_operator:DI 4 "boolean_operator"
7298 [(match_operand:DI 1 "gpc_reg_operand" "")
7299 (match_operand:DI 2 "gpc_reg_operand" "")])
7300 (const_int 0)))
7301 (clobber (match_scratch:DI 3 ""))]
7302 "TARGET_POWERPC64 && reload_completed"
7303 [(set (match_dup 3) (match_dup 4))
7304 (set (match_dup 0)
7305 (compare:CC (match_dup 3)
7306 (const_int 0)))]
7307 "")
7309 (define_insn "*booldi3_internal3"
7310 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7311 (compare:CC (match_operator:DI 4 "boolean_operator"
7312 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7313 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7314 (const_int 0)))
7315 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7316 (match_dup 4))]
7317 "TARGET_64BIT"
7318 "@
7319 %q4. %0,%1,%2
7320 #"
7321 [(set_attr "type" "compare")
7322 (set_attr "length" "4,8")])
7324 (define_split
7325 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7326 (compare:CC (match_operator:DI 4 "boolean_operator"
7327 [(match_operand:DI 1 "gpc_reg_operand" "")
7328 (match_operand:DI 2 "gpc_reg_operand" "")])
7329 (const_int 0)))
7330 (set (match_operand:DI 0 "gpc_reg_operand" "")
7331 (match_dup 4))]
7332 "TARGET_POWERPC64 && reload_completed"
7333 [(set (match_dup 0) (match_dup 4))
7334 (set (match_dup 3)
7335 (compare:CC (match_dup 0)
7336 (const_int 0)))]
7337 "")
7339 ;; Split a logical operation that we can't do in one insn into two insns,
7340 ;; each of which does one 16-bit part. This is used by combine.
7342 (define_split
7343 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7344 (match_operator:DI 3 "boolean_or_operator"
7345 [(match_operand:DI 1 "gpc_reg_operand" "")
7346 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7347 "TARGET_POWERPC64"
7348 [(set (match_dup 0) (match_dup 4))
7349 (set (match_dup 0) (match_dup 5))]
7350 "
7351 {
7352 rtx i3,i4;
7354 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7355 {
7356 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7357 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7358 0, DImode);
7359 i4 = GEN_INT (value & 0xffff);
7360 }
7361 else
7362 {
7363 i3 = GEN_INT (INTVAL (operands[2])
7364 & (~ (HOST_WIDE_INT) 0xffff));
7365 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7366 }
7367 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
7368 operands[1], i3);
7369 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
7370 operands[0], i4);
7371 }")
7373 (define_insn "*boolcdi3_internal1"
7374 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7375 (match_operator:DI 3 "boolean_operator"
7376 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7377 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7378 "TARGET_POWERPC64"
7379 "%q3 %0,%2,%1")
7381 (define_insn "*boolcdi3_internal2"
7382 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7383 (compare:CC (match_operator:DI 4 "boolean_operator"
7384 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7385 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7386 (const_int 0)))
7387 (clobber (match_scratch:DI 3 "=r,r"))]
7388 "TARGET_64BIT"
7389 "@
7390 %q4. %3,%2,%1
7391 #"
7392 [(set_attr "type" "compare")
7393 (set_attr "length" "4,8")])
7395 (define_split
7396 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7397 (compare:CC (match_operator:DI 4 "boolean_operator"
7398 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7399 (match_operand:DI 2 "gpc_reg_operand" "")])
7400 (const_int 0)))
7401 (clobber (match_scratch:DI 3 ""))]
7402 "TARGET_POWERPC64 && reload_completed"
7403 [(set (match_dup 3) (match_dup 4))
7404 (set (match_dup 0)
7405 (compare:CC (match_dup 3)
7406 (const_int 0)))]
7407 "")
7409 (define_insn "*boolcdi3_internal3"
7410 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7411 (compare:CC (match_operator:DI 4 "boolean_operator"
7412 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7413 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7414 (const_int 0)))
7415 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7416 (match_dup 4))]
7417 "TARGET_64BIT"
7418 "@
7419 %q4. %0,%2,%1
7420 #"
7421 [(set_attr "type" "compare")
7422 (set_attr "length" "4,8")])
7424 (define_split
7425 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7426 (compare:CC (match_operator:DI 4 "boolean_operator"
7427 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7428 (match_operand:DI 2 "gpc_reg_operand" "")])
7429 (const_int 0)))
7430 (set (match_operand:DI 0 "gpc_reg_operand" "")
7431 (match_dup 4))]
7432 "TARGET_POWERPC64 && reload_completed"
7433 [(set (match_dup 0) (match_dup 4))
7434 (set (match_dup 3)
7435 (compare:CC (match_dup 0)
7436 (const_int 0)))]
7437 "")
7439 (define_insn "*boolccdi3_internal1"
7440 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7441 (match_operator:DI 3 "boolean_operator"
7442 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7443 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7444 "TARGET_POWERPC64"
7445 "%q3 %0,%1,%2")
7447 (define_insn "*boolccdi3_internal2"
7448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7449 (compare:CC (match_operator:DI 4 "boolean_operator"
7450 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7451 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7452 (const_int 0)))
7453 (clobber (match_scratch:DI 3 "=r,r"))]
7454 "TARGET_64BIT"
7455 "@
7456 %q4. %3,%1,%2
7457 #"
7458 [(set_attr "type" "compare")
7459 (set_attr "length" "4,8")])
7461 (define_split
7462 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7463 (compare:CC (match_operator:DI 4 "boolean_operator"
7464 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7465 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7466 (const_int 0)))
7467 (clobber (match_scratch:DI 3 ""))]
7468 "TARGET_POWERPC64 && reload_completed"
7469 [(set (match_dup 3) (match_dup 4))
7470 (set (match_dup 0)
7471 (compare:CC (match_dup 3)
7472 (const_int 0)))]
7473 "")
7475 (define_insn "*boolccdi3_internal3"
7476 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7477 (compare:CC (match_operator:DI 4 "boolean_operator"
7478 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7479 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7480 (const_int 0)))
7481 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7482 (match_dup 4))]
7483 "TARGET_64BIT"
7484 "@
7485 %q4. %0,%1,%2
7486 #"
7487 [(set_attr "type" "compare")
7488 (set_attr "length" "4,8")])
7490 (define_split
7491 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7492 (compare:CC (match_operator:DI 4 "boolean_operator"
7493 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7494 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7495 (const_int 0)))
7496 (set (match_operand:DI 0 "gpc_reg_operand" "")
7497 (match_dup 4))]
7498 "TARGET_POWERPC64 && reload_completed"
7499 [(set (match_dup 0) (match_dup 4))
7500 (set (match_dup 3)
7501 (compare:CC (match_dup 0)
7502 (const_int 0)))]
7503 "")
7504 \f
7505 ;; Now define ways of moving data around.
7507 ;; Elf specific ways of loading addresses for non-PIC code.
7508 ;; The output of this could be r0, but we make a very strong
7509 ;; preference for a base register because it will usually
7510 ;; be needed there.
7511 (define_insn "elf_high"
7512 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7513 (high:SI (match_operand 1 "" "")))]
7514 "TARGET_ELF && ! TARGET_64BIT"
7515 "{liu|lis} %0,%1@ha")
7517 (define_insn "elf_low"
7518 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7519 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7520 (match_operand 2 "" "")))]
7521 "TARGET_ELF && ! TARGET_64BIT"
7522 "@
7523 {cal|la} %0,%2@l(%1)
7524 {ai|addic} %0,%1,%K2")
7526 ;; Mach-O PIC trickery.
7527 (define_insn "macho_high"
7528 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7529 (high:SI (match_operand 1 "" "")))]
7530 "TARGET_MACHO && ! TARGET_64BIT"
7531 "{liu|lis} %0,ha16(%1)")
7533 (define_insn "macho_low"
7534 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7535 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7536 (match_operand 2 "" "")))]
7537 "TARGET_MACHO && ! TARGET_64BIT"
7538 "@
7539 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7540 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7542 ;; Set up a register with a value from the GOT table
7544 (define_expand "movsi_got"
7545 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7546 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7547 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7548 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7549 "
7550 {
7551 if (GET_CODE (operands[1]) == CONST)
7552 {
7553 rtx offset = const0_rtx;
7554 HOST_WIDE_INT value;
7556 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7557 value = INTVAL (offset);
7558 if (value != 0)
7559 {
7560 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7561 emit_insn (gen_movsi_got (tmp, operands[1]));
7562 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7563 DONE;
7564 }
7565 }
7567 operands[2] = rs6000_got_register (operands[1]);
7568 }")
7570 (define_insn "*movsi_got_internal"
7571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7572 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7573 (match_operand:SI 2 "gpc_reg_operand" "b")]
7574 UNSPEC_MOVSI_GOT))]
7575 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7576 "{l|lwz} %0,%a1@got(%2)"
7577 [(set_attr "type" "load")])
7579 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7580 ;; didn't get allocated to a hard register.
7581 (define_split
7582 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7583 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7584 (match_operand:SI 2 "memory_operand" "")]
7585 UNSPEC_MOVSI_GOT))]
7586 "DEFAULT_ABI == ABI_V4
7587 && flag_pic == 1
7588 && (reload_in_progress || reload_completed)"
7589 [(set (match_dup 0) (match_dup 2))
7590 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7591 UNSPEC_MOVSI_GOT))]
7592 "")
7594 ;; For SI, we special-case integers that can't be loaded in one insn. We
7595 ;; do the load 16-bits at a time. We could do this by loading from memory,
7596 ;; and this is even supposed to be faster, but it is simpler not to get
7597 ;; integers in the TOC.
7598 (define_expand "movsi"
7599 [(set (match_operand:SI 0 "general_operand" "")
7600 (match_operand:SI 1 "any_operand" ""))]
7601 ""
7602 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7604 (define_insn "movsi_low"
7605 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7606 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7607 (match_operand 2 "" ""))))]
7608 "TARGET_MACHO && ! TARGET_64BIT"
7609 "{l|lwz} %0,lo16(%2)(%1)"
7610 [(set_attr "type" "load")
7611 (set_attr "length" "4")])
7613 (define_insn "movsi_low_st"
7614 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7615 (match_operand 2 "" "")))
7616 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7617 "TARGET_MACHO && ! TARGET_64BIT"
7618 "{st|stw} %0,lo16(%2)(%1)"
7619 [(set_attr "type" "store")
7620 (set_attr "length" "4")])
7622 (define_insn "movdf_low"
7623 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
7624 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7625 (match_operand 2 "" ""))))]
7626 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7627 "*
7628 {
7629 switch (which_alternative)
7630 {
7631 case 0:
7632 return \"lfd %0,lo16(%2)(%1)\";
7633 case 1:
7634 {
7635 rtx operands2[4];
7636 operands2[0] = operands[0];
7637 operands2[1] = operands[1];
7638 operands2[2] = operands[2];
7639 if (TARGET_POWERPC64 && TARGET_32BIT)
7640 /* Note, old assemblers didn't support relocation here. */
7641 return \"ld %0,lo16(%2)(%1)\";
7642 else
7643 {
7644 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7645 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7646 #if TARGET_MACHO
7647 if (MACHO_DYNAMIC_NO_PIC_P)
7648 output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
7649 else
7650 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7651 although in practice it almost always is. */
7652 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
7653 #endif
7654 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7655 }
7656 }
7657 default:
7658 abort();
7659 }
7660 }"
7661 [(set_attr "type" "load")
7662 (set_attr "length" "4,12")])
7664 (define_insn "movdf_low_st"
7665 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7666 (match_operand 2 "" "")))
7667 (match_operand:DF 0 "gpc_reg_operand" "f"))]
7668 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7669 "stfd %0,lo16(%2)(%1)"
7670 [(set_attr "type" "store")
7671 (set_attr "length" "4")])
7673 (define_insn "movsf_low"
7674 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
7675 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7676 (match_operand 2 "" ""))))]
7677 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7678 "@
7679 lfs %0,lo16(%2)(%1)
7680 {l|lwz} %0,lo16(%2)(%1)"
7681 [(set_attr "type" "load")
7682 (set_attr "length" "4")])
7684 (define_insn "movsf_low_st"
7685 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7686 (match_operand 2 "" "")))
7687 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
7688 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7689 "@
7690 stfs %0,lo16(%2)(%1)
7691 {st|stw} %0,lo16(%2)(%1)"
7692 [(set_attr "type" "store")
7693 (set_attr "length" "4")])
7695 (define_insn "*movsi_internal1"
7696 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7697 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7698 "gpc_reg_operand (operands[0], SImode)
7699 || gpc_reg_operand (operands[1], SImode)"
7700 "@
7701 mr %0,%1
7702 {cal|la} %0,%a1
7703 {l%U1%X1|lwz%U1%X1} %0,%1
7704 {st%U0%X0|stw%U0%X0} %1,%0
7705 {lil|li} %0,%1
7706 {liu|lis} %0,%v1
7707 #
7708 {cal|la} %0,%a1
7709 mf%1 %0
7710 mt%0 %1
7711 mt%0 %1
7712 mt%0 %1
7713 {cror 0,0,0|nop}"
7714 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7715 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7717 ;; Split a load of a large constant into the appropriate two-insn
7718 ;; sequence.
7720 (define_split
7721 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7722 (match_operand:SI 1 "const_int_operand" ""))]
7723 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7724 && (INTVAL (operands[1]) & 0xffff) != 0"
7725 [(set (match_dup 0)
7726 (match_dup 2))
7727 (set (match_dup 0)
7728 (ior:SI (match_dup 0)
7729 (match_dup 3)))]
7730 "
7731 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7733 if (tem == operands[0])
7734 DONE;
7735 else
7736 FAIL;
7737 }")
7739 (define_insn "*movsi_internal2"
7740 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7741 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7742 (const_int 0)))
7743 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7744 "TARGET_32BIT"
7745 "@
7746 {cmpi|cmpwi} %2,%0,0
7747 mr. %0,%1
7748 #"
7749 [(set_attr "type" "cmp,compare,cmp")
7750 (set_attr "length" "4,4,8")])
7752 (define_split
7753 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7754 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7755 (const_int 0)))
7756 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7757 "TARGET_32BIT && reload_completed"
7758 [(set (match_dup 0) (match_dup 1))
7759 (set (match_dup 2)
7760 (compare:CC (match_dup 0)
7761 (const_int 0)))]
7762 "")
7763 \f
7764 (define_expand "movhi"
7765 [(set (match_operand:HI 0 "general_operand" "")
7766 (match_operand:HI 1 "any_operand" ""))]
7767 ""
7768 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7770 (define_insn "*movhi_internal"
7771 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7772 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7773 "gpc_reg_operand (operands[0], HImode)
7774 || gpc_reg_operand (operands[1], HImode)"
7775 "@
7776 mr %0,%1
7777 lhz%U1%X1 %0,%1
7778 sth%U0%X0 %1,%0
7779 {lil|li} %0,%w1
7780 mf%1 %0
7781 mt%0 %1
7782 mt%0 %1
7783 {cror 0,0,0|nop}"
7784 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7786 (define_expand "movqi"
7787 [(set (match_operand:QI 0 "general_operand" "")
7788 (match_operand:QI 1 "any_operand" ""))]
7789 ""
7790 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7792 (define_insn "*movqi_internal"
7793 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7794 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7795 "gpc_reg_operand (operands[0], QImode)
7796 || gpc_reg_operand (operands[1], QImode)"
7797 "@
7798 mr %0,%1
7799 lbz%U1%X1 %0,%1
7800 stb%U0%X0 %1,%0
7801 {lil|li} %0,%1
7802 mf%1 %0
7803 mt%0 %1
7804 mt%0 %1
7805 {cror 0,0,0|nop}"
7806 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7807 \f
7808 ;; Here is how to move condition codes around. When we store CC data in
7809 ;; an integer register or memory, we store just the high-order 4 bits.
7810 ;; This lets us not shift in the most common case of CR0.
7811 (define_expand "movcc"
7812 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7813 (match_operand:CC 1 "nonimmediate_operand" ""))]
7814 ""
7815 "")
7817 (define_insn "*movcc_internal1"
7818 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7819 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7820 "register_operand (operands[0], CCmode)
7821 || register_operand (operands[1], CCmode)"
7822 "@
7823 mcrf %0,%1
7824 mtcrf 128,%1
7825 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7826 mfcr %0%Q1
7827 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7828 mr %0,%1
7829 mf%1 %0
7830 mt%0 %1
7831 mt%0 %1
7832 {l%U1%X1|lwz%U1%X1} %0,%1
7833 {st%U0%U1|stw%U0%U1} %1,%0"
7834 [(set (attr "type")
7835 (cond [(eq_attr "alternative" "0")
7836 (const_string "cr_logical")
7837 (eq_attr "alternative" "1,2")
7838 (const_string "mtcr")
7839 (eq_attr "alternative" "5,7")
7840 (const_string "integer")
7841 (eq_attr "alternative" "6")
7842 (const_string "mfjmpr")
7843 (eq_attr "alternative" "8")
7844 (const_string "mtjmpr")
7845 (eq_attr "alternative" "9")
7846 (const_string "load")
7847 (eq_attr "alternative" "10")
7848 (const_string "store")
7849 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7850 (const_string "mfcrf")
7851 ]
7852 (const_string "mfcr")))
7853 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7854 \f
7855 ;; For floating-point, we normally deal with the floating-point registers
7856 ;; unless -msoft-float is used. The sole exception is that parameter passing
7857 ;; can produce floating-point values in fixed-point registers. Unless the
7858 ;; value is a simple constant or already in memory, we deal with this by
7859 ;; allocating memory and copying the value explicitly via that memory location.
7860 (define_expand "movsf"
7861 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7862 (match_operand:SF 1 "any_operand" ""))]
7863 ""
7864 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7866 (define_split
7867 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7868 (match_operand:SF 1 "const_double_operand" ""))]
7869 "reload_completed
7870 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7871 || (GET_CODE (operands[0]) == SUBREG
7872 && GET_CODE (SUBREG_REG (operands[0])) == REG
7873 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7874 [(set (match_dup 2) (match_dup 3))]
7875 "
7876 {
7877 long l;
7878 REAL_VALUE_TYPE rv;
7880 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7881 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7883 if (! TARGET_POWERPC64)
7884 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7885 else
7886 operands[2] = gen_lowpart (SImode, operands[0]);
7888 operands[3] = gen_int_mode (l, SImode);
7889 }")
7891 (define_insn "*movsf_hardfloat"
7892 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r")
7893 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))]
7894 "(gpc_reg_operand (operands[0], SFmode)
7895 || gpc_reg_operand (operands[1], SFmode))
7896 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7897 "@
7898 mr %0,%1
7899 {l%U1%X1|lwz%U1%X1} %0,%1
7900 {st%U0%X0|stw%U0%X0} %1,%0
7901 fmr %0,%1
7902 lfs%U1%X1 %0,%1
7903 stfs%U0%X0 %1,%0
7904 mt%0 %1
7905 mt%0 %1
7906 mf%1 %0
7907 #
7908 #"
7909 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*")
7910 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
7912 (define_insn "*movsf_softfloat"
7913 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7914 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7915 "(gpc_reg_operand (operands[0], SFmode)
7916 || gpc_reg_operand (operands[1], SFmode))
7917 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7918 "@
7919 mr %0,%1
7920 mt%0 %1
7921 mt%0 %1
7922 mf%1 %0
7923 {l%U1%X1|lwz%U1%X1} %0,%1
7924 {st%U0%X0|stw%U0%X0} %1,%0
7925 {lil|li} %0,%1
7926 {liu|lis} %0,%v1
7927 {cal|la} %0,%a1
7928 #
7929 #
7930 {cror 0,0,0|nop}"
7931 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7932 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7934 \f
7935 (define_expand "movdf"
7936 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7937 (match_operand:DF 1 "any_operand" ""))]
7938 ""
7939 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7941 (define_split
7942 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7943 (match_operand:DF 1 "const_int_operand" ""))]
7944 "! TARGET_POWERPC64 && reload_completed
7945 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7946 || (GET_CODE (operands[0]) == SUBREG
7947 && GET_CODE (SUBREG_REG (operands[0])) == REG
7948 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7949 [(set (match_dup 2) (match_dup 4))
7950 (set (match_dup 3) (match_dup 1))]
7951 "
7952 {
7953 int endian = (WORDS_BIG_ENDIAN == 0);
7954 HOST_WIDE_INT value = INTVAL (operands[1]);
7956 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7957 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7958 #if HOST_BITS_PER_WIDE_INT == 32
7959 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7960 #else
7961 operands[4] = GEN_INT (value >> 32);
7962 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7963 #endif
7964 }")
7966 (define_split
7967 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7968 (match_operand:DF 1 "const_double_operand" ""))]
7969 "! TARGET_POWERPC64 && reload_completed
7970 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7971 || (GET_CODE (operands[0]) == SUBREG
7972 && GET_CODE (SUBREG_REG (operands[0])) == REG
7973 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7974 [(set (match_dup 2) (match_dup 4))
7975 (set (match_dup 3) (match_dup 5))]
7976 "
7977 {
7978 int endian = (WORDS_BIG_ENDIAN == 0);
7979 long l[2];
7980 REAL_VALUE_TYPE rv;
7982 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7983 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7985 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7986 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7987 operands[4] = gen_int_mode (l[endian], SImode);
7988 operands[5] = gen_int_mode (l[1 - endian], SImode);
7989 }")
7991 (define_split
7992 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7993 (match_operand:DF 1 "easy_fp_constant" ""))]
7994 "TARGET_POWERPC64 && reload_completed
7995 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7996 || (GET_CODE (operands[0]) == SUBREG
7997 && GET_CODE (SUBREG_REG (operands[0])) == REG
7998 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7999 [(set (match_dup 2) (match_dup 3))]
8000 "
8001 {
8002 int endian = (WORDS_BIG_ENDIAN == 0);
8003 long l[2];
8004 REAL_VALUE_TYPE rv;
8005 #if HOST_BITS_PER_WIDE_INT >= 64
8006 HOST_WIDE_INT val;
8007 #endif
8009 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8010 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8012 operands[2] = gen_lowpart (DImode, operands[0]);
8013 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8014 #if HOST_BITS_PER_WIDE_INT >= 64
8015 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8016 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8018 operands[3] = gen_int_mode (val, DImode);
8019 #else
8020 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8021 #endif
8022 }")
8024 ;; Don't have reload use general registers to load a constant. First,
8025 ;; it might not work if the output operand is the equivalent of
8026 ;; a non-offsettable memref, but also it is less efficient than loading
8027 ;; the constant into an FP register, since it will probably be used there.
8028 ;; The "??" is a kludge until we can figure out a more reasonable way
8029 ;; of handling these non-offsettable values.
8030 (define_insn "*movdf_hardfloat32"
8031 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8032 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8033 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8034 && (gpc_reg_operand (operands[0], DFmode)
8035 || gpc_reg_operand (operands[1], DFmode))"
8036 "*
8037 {
8038 switch (which_alternative)
8039 {
8040 default:
8041 abort ();
8042 case 0:
8043 /* We normally copy the low-numbered register first. However, if
8044 the first register operand 0 is the same as the second register
8045 of operand 1, we must copy in the opposite order. */
8046 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8047 return \"mr %L0,%L1\;mr %0,%1\";
8048 else
8049 return \"mr %0,%1\;mr %L0,%L1\";
8050 case 1:
8051 if (offsettable_memref_p (operands[1])
8052 || (GET_CODE (operands[1]) == MEM
8053 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8054 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8055 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8056 {
8057 /* If the low-address word is used in the address, we must load
8058 it last. Otherwise, load it first. Note that we cannot have
8059 auto-increment in that case since the address register is
8060 known to be dead. */
8061 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8062 operands[1], 0))
8063 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8064 else
8065 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8066 }
8067 else
8068 {
8069 rtx addreg;
8071 addreg = find_addr_reg (XEXP (operands[1], 0));
8072 if (refers_to_regno_p (REGNO (operands[0]),
8073 REGNO (operands[0]) + 1,
8074 operands[1], 0))
8075 {
8076 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8077 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8078 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8079 return \"{lx|lwzx} %0,%1\";
8080 }
8081 else
8082 {
8083 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8084 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8085 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8086 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8087 return \"\";
8088 }
8089 }
8090 case 2:
8091 if (offsettable_memref_p (operands[0])
8092 || (GET_CODE (operands[0]) == MEM
8093 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8094 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8095 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8096 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8097 else
8098 {
8099 rtx addreg;
8101 addreg = find_addr_reg (XEXP (operands[0], 0));
8102 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8103 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8104 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8105 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8106 return \"\";
8107 }
8108 case 3:
8109 return \"fmr %0,%1\";
8110 case 4:
8111 return \"lfd%U1%X1 %0,%1\";
8112 case 5:
8113 return \"stfd%U0%X0 %1,%0\";
8114 case 6:
8115 case 7:
8116 case 8:
8117 return \"#\";
8118 }
8119 }"
8120 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
8121 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8123 (define_insn "*movdf_softfloat32"
8124 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8125 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8126 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8127 && (gpc_reg_operand (operands[0], DFmode)
8128 || gpc_reg_operand (operands[1], DFmode))"
8129 "*
8130 {
8131 switch (which_alternative)
8132 {
8133 default:
8134 abort ();
8135 case 0:
8136 /* We normally copy the low-numbered register first. However, if
8137 the first register operand 0 is the same as the second register of
8138 operand 1, we must copy in the opposite order. */
8139 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8140 return \"mr %L0,%L1\;mr %0,%1\";
8141 else
8142 return \"mr %0,%1\;mr %L0,%L1\";
8143 case 1:
8144 /* If the low-address word is used in the address, we must load
8145 it last. Otherwise, load it first. Note that we cannot have
8146 auto-increment in that case since the address register is
8147 known to be dead. */
8148 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8149 operands[1], 0))
8150 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8151 else
8152 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8153 case 2:
8154 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8155 case 3:
8156 case 4:
8157 case 5:
8158 return \"#\";
8159 }
8160 }"
8161 [(set_attr "type" "*,load,store,*,*,*")
8162 (set_attr "length" "8,8,8,8,12,16")])
8164 ; ld/std require word-aligned displacements -> 'Y' constraint.
8165 ; List Y->r and r->Y before r->r for reload.
8166 (define_insn "*movdf_hardfloat64"
8167 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,b,!r,f,f,m,!cl,!r,!r,!r,!r")
8168 (match_operand:DF 1 "input_operand" "r,Y,m,r,f,m,f,r,h,G,H,F"))]
8169 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8170 && (gpc_reg_operand (operands[0], DFmode)
8171 || gpc_reg_operand (operands[1], DFmode))"
8172 "@
8173 std%U0%X0 %1,%0
8174 ld%U1%X1 %0,%1
8175 #
8176 mr %0,%1
8177 fmr %0,%1
8178 lfd%U1%X1 %0,%1
8179 stfd%U0%X0 %1,%0
8180 mt%0 %1
8181 mf%1 %0
8182 #
8183 #
8184 #"
8185 [(set_attr "type" "store,load,load,*,fp,fpload,fpstore,mtjmpr,*,*,*,*")
8186 (set_attr "length" "4,4,8,4,4,4,4,4,4,8,12,16")])
8188 (define_split
8189 [(set (match_operand:DF 0 "base_reg_operand" "")
8190 (match_operand:DF 1 "invalid_gpr_mem" ""))]
8191 "TARGET_POWERPC64 && no_new_pseudos"
8192 [(set (match_dup 2) (match_dup 3))
8193 (set (match_dup 0) (match_dup 4))]
8194 "
8195 {
8196 operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
8197 operands[3] = XEXP (operands[1], 0);
8198 operands[4] = replace_equiv_address (operands[1], operands[2]);
8199 }")
8201 (define_expand "reload_outdf"
8202 [(parallel [(match_operand:DF 0 "invalid_gpr_mem" "")
8203 (match_operand:DF 1 "register_operand" "")
8204 (match_operand:DI 2 "register_operand" "=&b")])]
8205 "TARGET_POWERPC64"
8206 {
8207 if (!TARGET_64BIT)
8208 operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
8209 emit_move_insn (operands[2], XEXP (operands[0], 0));
8210 operands[0] = replace_equiv_address (operands[0], operands[2]);
8211 emit_move_insn (operands[0], operands[1]);
8212 DONE;
8213 })
8215 (define_expand "reload_indf"
8216 [(parallel [(match_operand:DF 0 "register_operand" "")
8217 (match_operand:DF 1 "invalid_gpr_mem" "")
8218 (match_operand:DI 2 "register_operand" "=&b")])]
8219 "TARGET_POWERPC64"
8220 {
8221 if (!TARGET_64BIT)
8222 operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
8223 emit_move_insn (operands[2], XEXP (operands[1], 0));
8224 operands[1] = replace_equiv_address (operands[1], operands[2]);
8225 emit_move_insn (operands[0], operands[1]);
8226 DONE;
8227 })
8229 (define_insn "*movdf_softfloat64"
8230 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8231 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8232 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8233 && (gpc_reg_operand (operands[0], DFmode)
8234 || gpc_reg_operand (operands[1], DFmode))"
8235 "@
8236 ld%U1%X1 %0,%1
8237 std%U0%X0 %1,%0
8238 mr %0,%1
8239 mt%0 %1
8240 mf%1 %0
8241 #
8242 #
8243 #
8244 nop"
8245 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
8246 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8247 \f
8248 (define_expand "movtf"
8249 [(set (match_operand:TF 0 "general_operand" "")
8250 (match_operand:TF 1 "any_operand" ""))]
8251 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8252 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8253 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8255 ; It's important to list the o->f and f->o moves before f->f because
8256 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8257 ; which doesn't make progress.
8258 (define_insn_and_split "*movtf_internal"
8259 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,rm,r")
8260 (match_operand:TF 1 "input_operand" "f,o,f,r,mGHF"))]
8261 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8262 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8263 && (gpc_reg_operand (operands[0], TFmode)
8264 || gpc_reg_operand (operands[1], TFmode))"
8265 "#"
8266 "&& reload_completed"
8267 [(pc)]
8268 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8269 [(set_attr "length" "8,8,8,20,20")])
8271 (define_expand "extenddftf2"
8272 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8273 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8274 (use (match_dup 2))])]
8275 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8276 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8277 {
8278 operands[2] = CONST0_RTX (DFmode);
8279 })
8281 (define_insn_and_split "*extenddftf2_internal"
8282 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8283 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8284 (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))]
8285 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8286 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8287 "#"
8288 "&& reload_completed"
8289 [(pc)]
8290 {
8291 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8292 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8293 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8294 operands[1]);
8295 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8296 operands[2]);
8297 DONE;
8298 })
8300 (define_expand "extendsftf2"
8301 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8302 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8303 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8304 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8305 {
8306 rtx tmp = gen_reg_rtx (DFmode);
8307 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8308 emit_insn (gen_extenddftf2 (operands[0], tmp));
8309 DONE;
8310 })
8312 (define_insn "trunctfdf2"
8313 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8314 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8315 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8316 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8317 "fadd %0,%1,%L1"
8318 [(set_attr "type" "fp")
8319 (set_attr "length" "4")])
8321 (define_insn_and_split "trunctfsf2"
8322 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8323 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8324 (clobber (match_scratch:DF 2 "=f"))]
8325 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8326 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8327 "#"
8328 "&& reload_completed"
8329 [(set (match_dup 2)
8330 (float_truncate:DF (match_dup 1)))
8331 (set (match_dup 0)
8332 (float_truncate:SF (match_dup 2)))]
8333 "")
8335 (define_expand "floatsitf2"
8336 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8337 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8338 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8339 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8340 {
8341 rtx tmp = gen_reg_rtx (DFmode);
8342 expand_float (tmp, operands[1], false);
8343 emit_insn (gen_extenddftf2 (operands[0], tmp));
8344 DONE;
8345 })
8347 ; fadd, but rounding towards zero.
8348 ; This is probably not the optimal code sequence.
8349 (define_insn "fix_trunc_helper"
8350 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8351 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8352 UNSPEC_FIX_TRUNC_TF))
8353 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8354 "TARGET_HARD_FLOAT && TARGET_FPRS"
8355 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8356 [(set_attr "type" "fp")
8357 (set_attr "length" "20")])
8359 (define_expand "fix_trunctfsi2"
8360 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8361 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8362 (clobber (match_dup 2))
8363 (clobber (match_dup 3))
8364 (clobber (match_dup 4))
8365 (clobber (match_dup 5))])]
8366 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8367 && (TARGET_POWER2 || TARGET_POWERPC)
8368 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8369 {
8370 operands[2] = gen_reg_rtx (DFmode);
8371 operands[3] = gen_reg_rtx (DFmode);
8372 operands[4] = gen_reg_rtx (DImode);
8373 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8374 })
8376 (define_insn_and_split "*fix_trunctfsi2_internal"
8377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8378 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8379 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8380 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8381 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8382 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8383 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8384 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8385 "#"
8386 "&& reload_completed"
8387 [(pc)]
8388 {
8389 rtx lowword;
8390 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8392 if (GET_CODE (operands[5]) != MEM)
8393 abort();
8394 lowword = XEXP (operands[5], 0);
8395 if (WORDS_BIG_ENDIAN)
8396 lowword = plus_constant (lowword, 4);
8398 emit_insn (gen_fctiwz (operands[4], operands[2]));
8399 emit_move_insn (operands[5], operands[4]);
8400 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
8401 DONE;
8402 })
8404 (define_insn "negtf2"
8405 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8406 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8407 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8408 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8409 "*
8410 {
8411 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8412 return \"fneg %L0,%L1\;fneg %0,%1\";
8413 else
8414 return \"fneg %0,%1\;fneg %L0,%L1\";
8415 }"
8416 [(set_attr "type" "fp")
8417 (set_attr "length" "8")])
8419 (define_expand "abstf2"
8420 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8421 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8422 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8423 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8424 "
8425 {
8426 rtx label = gen_label_rtx ();
8427 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8428 emit_label (label);
8429 DONE;
8430 }")
8432 (define_expand "abstf2_internal"
8433 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8434 (match_operand:TF 1 "gpc_reg_operand" "f"))
8435 (set (match_dup 3) (match_dup 5))
8436 (set (match_dup 5) (abs:DF (match_dup 5)))
8437 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8438 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8439 (label_ref (match_operand 2 "" ""))
8440 (pc)))
8441 (set (match_dup 6) (neg:DF (match_dup 6)))]
8442 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8443 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8444 "
8445 {
8446 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8447 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8448 operands[3] = gen_reg_rtx (DFmode);
8449 operands[4] = gen_reg_rtx (CCFPmode);
8450 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8451 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8452 }")
8453 \f
8454 ;; Next come the multi-word integer load and store and the load and store
8455 ;; multiple insns.
8456 (define_expand "movdi"
8457 [(set (match_operand:DI 0 "general_operand" "")
8458 (match_operand:DI 1 "any_operand" ""))]
8459 ""
8460 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8462 (define_insn "*movdi_internal32"
8463 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8464 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
8465 "! TARGET_POWERPC64
8466 && (gpc_reg_operand (operands[0], DImode)
8467 || gpc_reg_operand (operands[1], DImode))"
8468 "*
8469 {
8470 switch (which_alternative)
8471 {
8472 default:
8473 abort ();
8474 case 0:
8475 case 1:
8476 case 2:
8477 return \"#\";
8478 case 3:
8479 return \"fmr %0,%1\";
8480 case 4:
8481 return \"lfd%U1%X1 %0,%1\";
8482 case 5:
8483 return \"stfd%U0%X0 %1,%0\";
8484 case 6:
8485 case 7:
8486 case 8:
8487 case 9:
8488 case 10:
8489 return \"#\";
8490 }
8491 }"
8492 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")])
8494 (define_split
8495 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8496 (match_operand:DI 1 "const_int_operand" ""))]
8497 "! TARGET_POWERPC64 && reload_completed"
8498 [(set (match_dup 2) (match_dup 4))
8499 (set (match_dup 3) (match_dup 1))]
8500 "
8501 {
8502 HOST_WIDE_INT value = INTVAL (operands[1]);
8503 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8504 DImode);
8505 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8506 DImode);
8507 #if HOST_BITS_PER_WIDE_INT == 32
8508 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8509 #else
8510 operands[4] = GEN_INT (value >> 32);
8511 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8512 #endif
8513 }")
8515 (define_split
8516 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8517 (match_operand:DI 1 "input_operand" ""))]
8518 "reload_completed && !TARGET_POWERPC64
8519 && gpr_or_gpr_p (operands[0], operands[1])"
8520 [(pc)]
8521 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8523 (define_split
8524 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8525 (match_operand:TI 1 "const_double_operand" ""))]
8526 "TARGET_POWERPC64"
8527 [(set (match_dup 2) (match_dup 4))
8528 (set (match_dup 3) (match_dup 5))]
8529 "
8530 {
8531 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8532 TImode);
8533 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8534 TImode);
8535 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8536 {
8537 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8538 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8539 }
8540 else if (GET_CODE (operands[1]) == CONST_INT)
8541 {
8542 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8543 operands[5] = operands[1];
8544 }
8545 else
8546 FAIL;
8547 }")
8549 (define_insn "*movdi_internal64"
8550 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,b,r,r,r,r,r,?f,f,m,r,*h,*h")
8551 (match_operand:DI 1 "input_operand" "r,Y,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8552 "TARGET_POWERPC64
8553 && (gpc_reg_operand (operands[0], DImode)
8554 || gpc_reg_operand (operands[1], DImode))"
8555 "@
8556 std%U0%X0 %1,%0
8557 ld%U1%X1 %0,%1
8558 #
8559 mr %0,%1
8560 li %0,%1
8561 lis %0,%v1
8562 #
8563 {cal|la} %0,%a1
8564 fmr %0,%1
8565 lfd%U1%X1 %0,%1
8566 stfd%U0%X0 %1,%0
8567 mf%1 %0
8568 mt%0 %1
8569 {cror 0,0,0|nop}"
8570 [(set_attr "type" "store,load,load,*,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8571 (set_attr "length" "4,4,8,4,4,4,20,4,4,4,4,4,4,4")])
8573 (define_split
8574 [(set (match_operand:DI 0 "base_reg_operand" "")
8575 (match_operand:DI 1 "invalid_gpr_mem" ""))]
8576 "TARGET_POWERPC64 && no_new_pseudos"
8577 [(set (match_dup 2) (match_dup 3))
8578 (set (match_dup 0) (match_dup 4))]
8579 "
8580 {
8581 operands[2] = operands[0];
8582 if (!TARGET_64BIT)
8583 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));
8584 operands[3] = XEXP (operands[1], 0);
8585 operands[4] = replace_equiv_address (operands[1], operands[2]);
8586 }")
8588 (define_expand "reload_outdi"
8589 [(parallel [(match_operand:DI 0 "invalid_gpr_mem" "")
8590 (match_operand:DI 1 "register_operand" "")
8591 (match_operand:DI 2 "register_operand" "=&b")])]
8592 "TARGET_POWERPC64"
8593 {
8594 if (!TARGET_64BIT)
8595 operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
8596 emit_move_insn (operands[2], XEXP (operands[0], 0));
8597 operands[0] = replace_equiv_address (operands[0], operands[2]);
8598 emit_move_insn (operands[0], operands[1]);
8599 DONE;
8600 })
8602 (define_expand "reload_indi"
8603 [(parallel [(match_operand:DI 0 "register_operand" "")
8604 (match_operand:DI 1 "invalid_gpr_mem" "")
8605 (match_operand:DI 2 "register_operand" "=&b")])]
8606 "TARGET_POWERPC64"
8607 {
8608 if (!TARGET_64BIT)
8609 operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
8610 emit_move_insn (operands[2], XEXP (operands[1], 0));
8611 operands[1] = replace_equiv_address (operands[1], operands[2]);
8612 emit_move_insn (operands[0], operands[1]);
8613 DONE;
8614 })
8616 ;; immediate value valid for a single instruction hiding in a const_double
8617 (define_insn ""
8618 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8619 (match_operand:DI 1 "const_double_operand" "F"))]
8620 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8621 && GET_CODE (operands[1]) == CONST_DOUBLE
8622 && num_insns_constant (operands[1], DImode) == 1"
8623 "*
8624 {
8625 return ((unsigned HOST_WIDE_INT)
8626 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8627 ? \"li %0,%1\" : \"lis %0,%v1\";
8628 }")
8630 ;; Generate all one-bits and clear left or right.
8631 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8632 (define_split
8633 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8634 (match_operand:DI 1 "mask64_operand" ""))]
8635 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8636 [(set (match_dup 0) (const_int -1))
8637 (set (match_dup 0)
8638 (and:DI (rotate:DI (match_dup 0)
8639 (const_int 0))
8640 (match_dup 1)))]
8641 "")
8643 ;; Split a load of a large constant into the appropriate five-instruction
8644 ;; sequence. Handle anything in a constant number of insns.
8645 ;; When non-easy constants can go in the TOC, this should use
8646 ;; easy_fp_constant predicate.
8647 (define_split
8648 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8649 (match_operand:DI 1 "const_int_operand" ""))]
8650 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8651 [(set (match_dup 0) (match_dup 2))
8652 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8653 "
8654 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8656 if (tem == operands[0])
8657 DONE;
8658 else
8659 FAIL;
8660 }")
8662 (define_split
8663 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8664 (match_operand:DI 1 "const_double_operand" ""))]
8665 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8666 [(set (match_dup 0) (match_dup 2))
8667 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8668 "
8669 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8671 if (tem == operands[0])
8672 DONE;
8673 else
8674 FAIL;
8675 }")
8677 (define_insn "*movdi_internal2"
8678 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8679 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8680 (const_int 0)))
8681 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8682 "TARGET_64BIT"
8683 "@
8684 cmpdi %2,%0,0
8685 mr. %0,%1
8686 #"
8687 [(set_attr "type" "cmp,compare,cmp")
8688 (set_attr "length" "4,4,8")])
8690 (define_split
8691 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8692 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8693 (const_int 0)))
8694 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8695 "TARGET_POWERPC64 && reload_completed"
8696 [(set (match_dup 0) (match_dup 1))
8697 (set (match_dup 2)
8698 (compare:CC (match_dup 0)
8699 (const_int 0)))]
8700 "")
8701 \f
8702 ;; TImode is similar, except that we usually want to compute the address into
8703 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8704 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8705 (define_expand "movti"
8706 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8707 (match_operand:TI 1 "general_operand" ""))
8708 (clobber (scratch:SI))])]
8709 ""
8710 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8712 ;; We say that MQ is clobbered in the last alternative because the first
8713 ;; alternative would never get used otherwise since it would need a reload
8714 ;; while the 2nd alternative would not. We put memory cases first so they
8715 ;; are preferred. Otherwise, we'd try to reload the output instead of
8716 ;; giving the SCRATCH mq.
8718 (define_insn "*movti_power"
8719 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8720 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8721 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8722 "TARGET_POWER && ! TARGET_POWERPC64
8723 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8724 "*
8725 {
8726 switch (which_alternative)
8727 {
8728 default:
8729 abort ();
8731 case 0:
8732 if (TARGET_STRING)
8733 return \"{stsi|stswi} %1,%P0,16\";
8734 case 1:
8735 case 2:
8736 return \"#\";
8737 case 3:
8738 /* If the address is not used in the output, we can use lsi. Otherwise,
8739 fall through to generating four loads. */
8740 if (TARGET_STRING
8741 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8742 return \"{lsi|lswi} %0,%P1,16\";
8743 /* ... fall through ... */
8744 case 4:
8745 return \"#\";
8746 }
8747 }"
8748 [(set_attr "type" "store,store,*,load,load")])
8750 (define_insn "*movti_string"
8751 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8752 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
8753 "! TARGET_POWER && ! TARGET_POWERPC64
8754 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8755 "*
8756 {
8757 switch (which_alternative)
8758 {
8759 default:
8760 abort ();
8761 case 0:
8762 if (TARGET_STRING)
8763 return \"{stsi|stswi} %1,%P0,16\";
8764 case 1:
8765 case 2:
8766 return \"#\";
8767 case 3:
8768 /* If the address is not used in the output, we can use lsi. Otherwise,
8769 fall through to generating four loads. */
8770 if (TARGET_STRING
8771 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8772 return \"{lsi|lswi} %0,%P1,16\";
8773 /* ... fall through ... */
8774 case 4:
8775 return \"#\";
8776 }
8777 }"
8778 [(set_attr "type" "store,store,*,load,load")])
8780 (define_insn "*movti_ppc64"
8781 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,m,r")
8782 (match_operand:TI 1 "input_operand" "r,r,o"))]
8783 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8784 || gpc_reg_operand (operands[1], TImode))"
8785 "@
8786 #
8787 #
8788 #"
8789 [(set_attr "type" "*,load,store")])
8791 (define_split
8792 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8793 (match_operand:TI 1 "input_operand" ""))]
8794 "reload_completed
8795 && gpr_or_gpr_p (operands[0], operands[1])"
8796 [(pc)]
8797 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8798 \f
8799 (define_expand "load_multiple"
8800 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8801 (match_operand:SI 1 "" ""))
8802 (use (match_operand:SI 2 "" ""))])]
8803 "TARGET_STRING && !TARGET_POWERPC64"
8804 "
8805 {
8806 int regno;
8807 int count;
8808 rtx op1;
8809 int i;
8811 /* Support only loading a constant number of fixed-point registers from
8812 memory and only bother with this if more than two; the machine
8813 doesn't support more than eight. */
8814 if (GET_CODE (operands[2]) != CONST_INT
8815 || INTVAL (operands[2]) <= 2
8816 || INTVAL (operands[2]) > 8
8817 || GET_CODE (operands[1]) != MEM
8818 || GET_CODE (operands[0]) != REG
8819 || REGNO (operands[0]) >= 32)
8820 FAIL;
8822 count = INTVAL (operands[2]);
8823 regno = REGNO (operands[0]);
8825 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8826 op1 = replace_equiv_address (operands[1],
8827 force_reg (SImode, XEXP (operands[1], 0)));
8829 for (i = 0; i < count; i++)
8830 XVECEXP (operands[3], 0, i)
8831 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8832 adjust_address_nv (op1, SImode, i * 4));
8833 }")
8835 (define_insn "*ldmsi8"
8836 [(match_parallel 0 "load_multiple_operation"
8837 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8838 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8839 (set (match_operand:SI 3 "gpc_reg_operand" "")
8840 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8841 (set (match_operand:SI 4 "gpc_reg_operand" "")
8842 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8843 (set (match_operand:SI 5 "gpc_reg_operand" "")
8844 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8845 (set (match_operand:SI 6 "gpc_reg_operand" "")
8846 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8847 (set (match_operand:SI 7 "gpc_reg_operand" "")
8848 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8849 (set (match_operand:SI 8 "gpc_reg_operand" "")
8850 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8851 (set (match_operand:SI 9 "gpc_reg_operand" "")
8852 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8853 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8854 "*
8855 { return rs6000_output_load_multiple (operands); }"
8856 [(set_attr "type" "load")
8857 (set_attr "length" "32")])
8859 (define_insn "*ldmsi7"
8860 [(match_parallel 0 "load_multiple_operation"
8861 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8862 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8863 (set (match_operand:SI 3 "gpc_reg_operand" "")
8864 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8865 (set (match_operand:SI 4 "gpc_reg_operand" "")
8866 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8867 (set (match_operand:SI 5 "gpc_reg_operand" "")
8868 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8869 (set (match_operand:SI 6 "gpc_reg_operand" "")
8870 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8871 (set (match_operand:SI 7 "gpc_reg_operand" "")
8872 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8873 (set (match_operand:SI 8 "gpc_reg_operand" "")
8874 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8875 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8876 "*
8877 { return rs6000_output_load_multiple (operands); }"
8878 [(set_attr "type" "load")
8879 (set_attr "length" "32")])
8881 (define_insn "*ldmsi6"
8882 [(match_parallel 0 "load_multiple_operation"
8883 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8884 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8885 (set (match_operand:SI 3 "gpc_reg_operand" "")
8886 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8887 (set (match_operand:SI 4 "gpc_reg_operand" "")
8888 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8889 (set (match_operand:SI 5 "gpc_reg_operand" "")
8890 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8891 (set (match_operand:SI 6 "gpc_reg_operand" "")
8892 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8893 (set (match_operand:SI 7 "gpc_reg_operand" "")
8894 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8895 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8896 "*
8897 { return rs6000_output_load_multiple (operands); }"
8898 [(set_attr "type" "load")
8899 (set_attr "length" "32")])
8901 (define_insn "*ldmsi5"
8902 [(match_parallel 0 "load_multiple_operation"
8903 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8904 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8905 (set (match_operand:SI 3 "gpc_reg_operand" "")
8906 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8907 (set (match_operand:SI 4 "gpc_reg_operand" "")
8908 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8909 (set (match_operand:SI 5 "gpc_reg_operand" "")
8910 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8911 (set (match_operand:SI 6 "gpc_reg_operand" "")
8912 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8913 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8914 "*
8915 { return rs6000_output_load_multiple (operands); }"
8916 [(set_attr "type" "load")
8917 (set_attr "length" "32")])
8919 (define_insn "*ldmsi4"
8920 [(match_parallel 0 "load_multiple_operation"
8921 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8922 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8923 (set (match_operand:SI 3 "gpc_reg_operand" "")
8924 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8925 (set (match_operand:SI 4 "gpc_reg_operand" "")
8926 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8927 (set (match_operand:SI 5 "gpc_reg_operand" "")
8928 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8929 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8930 "*
8931 { return rs6000_output_load_multiple (operands); }"
8932 [(set_attr "type" "load")
8933 (set_attr "length" "32")])
8935 (define_insn "*ldmsi3"
8936 [(match_parallel 0 "load_multiple_operation"
8937 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8938 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8939 (set (match_operand:SI 3 "gpc_reg_operand" "")
8940 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8941 (set (match_operand:SI 4 "gpc_reg_operand" "")
8942 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8943 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8944 "*
8945 { return rs6000_output_load_multiple (operands); }"
8946 [(set_attr "type" "load")
8947 (set_attr "length" "32")])
8949 (define_expand "store_multiple"
8950 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8951 (match_operand:SI 1 "" ""))
8952 (clobber (scratch:SI))
8953 (use (match_operand:SI 2 "" ""))])]
8954 "TARGET_STRING && !TARGET_POWERPC64"
8955 "
8956 {
8957 int regno;
8958 int count;
8959 rtx to;
8960 rtx op0;
8961 int i;
8963 /* Support only storing a constant number of fixed-point registers to
8964 memory and only bother with this if more than two; the machine
8965 doesn't support more than eight. */
8966 if (GET_CODE (operands[2]) != CONST_INT
8967 || INTVAL (operands[2]) <= 2
8968 || INTVAL (operands[2]) > 8
8969 || GET_CODE (operands[0]) != MEM
8970 || GET_CODE (operands[1]) != REG
8971 || REGNO (operands[1]) >= 32)
8972 FAIL;
8974 count = INTVAL (operands[2]);
8975 regno = REGNO (operands[1]);
8977 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8978 to = force_reg (SImode, XEXP (operands[0], 0));
8979 op0 = replace_equiv_address (operands[0], to);
8981 XVECEXP (operands[3], 0, 0)
8982 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8983 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8984 gen_rtx_SCRATCH (SImode));
8986 for (i = 1; i < count; i++)
8987 XVECEXP (operands[3], 0, i + 1)
8988 = gen_rtx_SET (VOIDmode,
8989 adjust_address_nv (op0, SImode, i * 4),
8990 gen_rtx_REG (SImode, regno + i));
8991 }")
8993 (define_insn "*store_multiple_power"
8994 [(match_parallel 0 "store_multiple_operation"
8995 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8996 (match_operand:SI 2 "gpc_reg_operand" "r"))
8997 (clobber (match_scratch:SI 3 "=q"))])]
8998 "TARGET_STRING && TARGET_POWER"
8999 "{stsi|stswi} %2,%P1,%O0"
9000 [(set_attr "type" "store")])
9002 (define_insn "*stmsi8"
9003 [(match_parallel 0 "store_multiple_operation"
9004 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9005 (match_operand:SI 2 "gpc_reg_operand" "r"))
9006 (clobber (match_scratch:SI 3 "X"))
9007 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9008 (match_operand:SI 4 "gpc_reg_operand" "r"))
9009 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9010 (match_operand:SI 5 "gpc_reg_operand" "r"))
9011 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9012 (match_operand:SI 6 "gpc_reg_operand" "r"))
9013 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9014 (match_operand:SI 7 "gpc_reg_operand" "r"))
9015 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9016 (match_operand:SI 8 "gpc_reg_operand" "r"))
9017 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9018 (match_operand:SI 9 "gpc_reg_operand" "r"))
9019 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9020 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9021 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9022 "{stsi|stswi} %2,%1,%O0"
9023 [(set_attr "type" "store")])
9025 (define_insn "*stmsi7"
9026 [(match_parallel 0 "store_multiple_operation"
9027 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9028 (match_operand:SI 2 "gpc_reg_operand" "r"))
9029 (clobber (match_scratch:SI 3 "X"))
9030 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9031 (match_operand:SI 4 "gpc_reg_operand" "r"))
9032 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9033 (match_operand:SI 5 "gpc_reg_operand" "r"))
9034 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9035 (match_operand:SI 6 "gpc_reg_operand" "r"))
9036 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9037 (match_operand:SI 7 "gpc_reg_operand" "r"))
9038 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9039 (match_operand:SI 8 "gpc_reg_operand" "r"))
9040 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9041 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9042 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9043 "{stsi|stswi} %2,%1,%O0"
9044 [(set_attr "type" "store")])
9046 (define_insn "*stmsi6"
9047 [(match_parallel 0 "store_multiple_operation"
9048 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9049 (match_operand:SI 2 "gpc_reg_operand" "r"))
9050 (clobber (match_scratch:SI 3 "X"))
9051 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9052 (match_operand:SI 4 "gpc_reg_operand" "r"))
9053 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9054 (match_operand:SI 5 "gpc_reg_operand" "r"))
9055 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9056 (match_operand:SI 6 "gpc_reg_operand" "r"))
9057 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9058 (match_operand:SI 7 "gpc_reg_operand" "r"))
9059 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9060 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9061 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9062 "{stsi|stswi} %2,%1,%O0"
9063 [(set_attr "type" "store")])
9065 (define_insn "*stmsi5"
9066 [(match_parallel 0 "store_multiple_operation"
9067 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9068 (match_operand:SI 2 "gpc_reg_operand" "r"))
9069 (clobber (match_scratch:SI 3 "X"))
9070 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9071 (match_operand:SI 4 "gpc_reg_operand" "r"))
9072 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9073 (match_operand:SI 5 "gpc_reg_operand" "r"))
9074 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9075 (match_operand:SI 6 "gpc_reg_operand" "r"))
9076 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9077 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9078 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9079 "{stsi|stswi} %2,%1,%O0"
9080 [(set_attr "type" "store")])
9082 (define_insn "*stmsi4"
9083 [(match_parallel 0 "store_multiple_operation"
9084 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9085 (match_operand:SI 2 "gpc_reg_operand" "r"))
9086 (clobber (match_scratch:SI 3 "X"))
9087 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9088 (match_operand:SI 4 "gpc_reg_operand" "r"))
9089 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9090 (match_operand:SI 5 "gpc_reg_operand" "r"))
9091 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9092 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9093 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9094 "{stsi|stswi} %2,%1,%O0"
9095 [(set_attr "type" "store")])
9097 (define_insn "*stmsi3"
9098 [(match_parallel 0 "store_multiple_operation"
9099 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9100 (match_operand:SI 2 "gpc_reg_operand" "r"))
9101 (clobber (match_scratch:SI 3 "X"))
9102 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9103 (match_operand:SI 4 "gpc_reg_operand" "r"))
9104 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9105 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9106 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9107 "{stsi|stswi} %2,%1,%O0"
9108 [(set_attr "type" "store")])
9109 \f
9110 ;; String/block move insn.
9111 ;; Argument 0 is the destination
9112 ;; Argument 1 is the source
9113 ;; Argument 2 is the length
9114 ;; Argument 3 is the alignment
9116 (define_expand "movstrsi"
9117 [(parallel [(set (match_operand:BLK 0 "" "")
9118 (match_operand:BLK 1 "" ""))
9119 (use (match_operand:SI 2 "" ""))
9120 (use (match_operand:SI 3 "" ""))])]
9121 ""
9122 "
9123 {
9124 if (expand_block_move (operands))
9125 DONE;
9126 else
9127 FAIL;
9128 }")
9130 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9131 ;; register allocator doesn't have a clue about allocating 8 word registers.
9132 ;; rD/rS = r5 is preferred, efficient form.
9133 (define_expand "movstrsi_8reg"
9134 [(parallel [(set (match_operand 0 "" "")
9135 (match_operand 1 "" ""))
9136 (use (match_operand 2 "" ""))
9137 (use (match_operand 3 "" ""))
9138 (clobber (reg:SI 5))
9139 (clobber (reg:SI 6))
9140 (clobber (reg:SI 7))
9141 (clobber (reg:SI 8))
9142 (clobber (reg:SI 9))
9143 (clobber (reg:SI 10))
9144 (clobber (reg:SI 11))
9145 (clobber (reg:SI 12))
9146 (clobber (match_scratch:SI 4 ""))])]
9147 "TARGET_STRING"
9148 "")
9150 (define_insn ""
9151 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9152 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9153 (use (match_operand:SI 2 "immediate_operand" "i"))
9154 (use (match_operand:SI 3 "immediate_operand" "i"))
9155 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9156 (clobber (reg:SI 6))
9157 (clobber (reg:SI 7))
9158 (clobber (reg:SI 8))
9159 (clobber (reg:SI 9))
9160 (clobber (reg:SI 10))
9161 (clobber (reg:SI 11))
9162 (clobber (reg:SI 12))
9163 (clobber (match_scratch:SI 5 "=q"))]
9164 "TARGET_STRING && TARGET_POWER
9165 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9166 || INTVAL (operands[2]) == 0)
9167 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9168 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9169 && REGNO (operands[4]) == 5"
9170 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9171 [(set_attr "type" "load")
9172 (set_attr "length" "8")])
9174 (define_insn ""
9175 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9176 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9177 (use (match_operand:SI 2 "immediate_operand" "i"))
9178 (use (match_operand:SI 3 "immediate_operand" "i"))
9179 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9180 (clobber (reg:SI 6))
9181 (clobber (reg:SI 7))
9182 (clobber (reg:SI 8))
9183 (clobber (reg:SI 9))
9184 (clobber (reg:SI 10))
9185 (clobber (reg:SI 11))
9186 (clobber (reg:SI 12))
9187 (clobber (match_scratch:SI 5 "X"))]
9188 "TARGET_STRING && ! TARGET_POWER
9189 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9190 || INTVAL (operands[2]) == 0)
9191 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9192 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9193 && REGNO (operands[4]) == 5"
9194 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9195 [(set_attr "type" "load")
9196 (set_attr "length" "8")])
9198 (define_insn ""
9199 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9200 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9201 (use (match_operand:SI 2 "immediate_operand" "i"))
9202 (use (match_operand:SI 3 "immediate_operand" "i"))
9203 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9204 (clobber (reg:SI 6))
9205 (clobber (reg:SI 7))
9206 (clobber (reg:SI 8))
9207 (clobber (reg:SI 9))
9208 (clobber (reg:SI 10))
9209 (clobber (reg:SI 11))
9210 (clobber (reg:SI 12))
9211 (clobber (match_scratch:SI 5 "X"))]
9212 "TARGET_STRING && TARGET_POWERPC64
9213 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9214 || INTVAL (operands[2]) == 0)
9215 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9216 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9217 && REGNO (operands[4]) == 5"
9218 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9219 [(set_attr "type" "load")
9220 (set_attr "length" "8")])
9222 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9223 ;; register allocator doesn't have a clue about allocating 6 word registers.
9224 ;; rD/rS = r5 is preferred, efficient form.
9225 (define_expand "movstrsi_6reg"
9226 [(parallel [(set (match_operand 0 "" "")
9227 (match_operand 1 "" ""))
9228 (use (match_operand 2 "" ""))
9229 (use (match_operand 3 "" ""))
9230 (clobber (reg:SI 5))
9231 (clobber (reg:SI 6))
9232 (clobber (reg:SI 7))
9233 (clobber (reg:SI 8))
9234 (clobber (reg:SI 9))
9235 (clobber (reg:SI 10))
9236 (clobber (match_scratch:SI 4 ""))])]
9237 "TARGET_STRING"
9238 "")
9240 (define_insn ""
9241 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9242 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9243 (use (match_operand:SI 2 "immediate_operand" "i"))
9244 (use (match_operand:SI 3 "immediate_operand" "i"))
9245 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9246 (clobber (reg:SI 6))
9247 (clobber (reg:SI 7))
9248 (clobber (reg:SI 8))
9249 (clobber (reg:SI 9))
9250 (clobber (reg:SI 10))
9251 (clobber (match_scratch:SI 5 "=q"))]
9252 "TARGET_STRING && TARGET_POWER
9253 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9254 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9255 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9256 && REGNO (operands[4]) == 5"
9257 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9258 [(set_attr "type" "load")
9259 (set_attr "length" "8")])
9261 (define_insn ""
9262 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9263 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9264 (use (match_operand:SI 2 "immediate_operand" "i"))
9265 (use (match_operand:SI 3 "immediate_operand" "i"))
9266 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9267 (clobber (reg:SI 6))
9268 (clobber (reg:SI 7))
9269 (clobber (reg:SI 8))
9270 (clobber (reg:SI 9))
9271 (clobber (reg:SI 10))
9272 (clobber (match_scratch:SI 5 "X"))]
9273 "TARGET_STRING && ! TARGET_POWER
9274 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9275 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9276 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9277 && REGNO (operands[4]) == 5"
9278 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9279 [(set_attr "type" "load")
9280 (set_attr "length" "8")])
9282 (define_insn ""
9283 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9284 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9285 (use (match_operand:SI 2 "immediate_operand" "i"))
9286 (use (match_operand:SI 3 "immediate_operand" "i"))
9287 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9288 (clobber (reg:SI 6))
9289 (clobber (reg:SI 7))
9290 (clobber (reg:SI 8))
9291 (clobber (reg:SI 9))
9292 (clobber (reg:SI 10))
9293 (clobber (match_scratch:SI 5 "X"))]
9294 "TARGET_STRING && TARGET_POWERPC64
9295 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9296 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9297 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9298 && REGNO (operands[4]) == 5"
9299 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9300 [(set_attr "type" "load")
9301 (set_attr "length" "8")])
9303 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9304 ;; problems with TImode.
9305 ;; rD/rS = r5 is preferred, efficient form.
9306 (define_expand "movstrsi_4reg"
9307 [(parallel [(set (match_operand 0 "" "")
9308 (match_operand 1 "" ""))
9309 (use (match_operand 2 "" ""))
9310 (use (match_operand 3 "" ""))
9311 (clobber (reg:SI 5))
9312 (clobber (reg:SI 6))
9313 (clobber (reg:SI 7))
9314 (clobber (reg:SI 8))
9315 (clobber (match_scratch:SI 4 ""))])]
9316 "TARGET_STRING"
9317 "")
9319 (define_insn ""
9320 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9321 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9322 (use (match_operand:SI 2 "immediate_operand" "i"))
9323 (use (match_operand:SI 3 "immediate_operand" "i"))
9324 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9325 (clobber (reg:SI 6))
9326 (clobber (reg:SI 7))
9327 (clobber (reg:SI 8))
9328 (clobber (match_scratch:SI 5 "=q"))]
9329 "TARGET_STRING && TARGET_POWER
9330 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9331 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9332 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9333 && REGNO (operands[4]) == 5"
9334 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9335 [(set_attr "type" "load")
9336 (set_attr "length" "8")])
9338 (define_insn ""
9339 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9340 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9341 (use (match_operand:SI 2 "immediate_operand" "i"))
9342 (use (match_operand:SI 3 "immediate_operand" "i"))
9343 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9344 (clobber (reg:SI 6))
9345 (clobber (reg:SI 7))
9346 (clobber (reg:SI 8))
9347 (clobber (match_scratch:SI 5 "X"))]
9348 "TARGET_STRING && ! TARGET_POWER
9349 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9350 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9351 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9352 && REGNO (operands[4]) == 5"
9353 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9354 [(set_attr "type" "load")
9355 (set_attr "length" "8")])
9357 (define_insn ""
9358 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9359 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9360 (use (match_operand:SI 2 "immediate_operand" "i"))
9361 (use (match_operand:SI 3 "immediate_operand" "i"))
9362 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9363 (clobber (reg:SI 6))
9364 (clobber (reg:SI 7))
9365 (clobber (reg:SI 8))
9366 (clobber (match_scratch:SI 5 "X"))]
9367 "TARGET_STRING && TARGET_POWERPC64
9368 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9369 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9370 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9371 && REGNO (operands[4]) == 5"
9372 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9373 [(set_attr "type" "load")
9374 (set_attr "length" "8")])
9376 ;; Move up to 8 bytes at a time.
9377 (define_expand "movstrsi_2reg"
9378 [(parallel [(set (match_operand 0 "" "")
9379 (match_operand 1 "" ""))
9380 (use (match_operand 2 "" ""))
9381 (use (match_operand 3 "" ""))
9382 (clobber (match_scratch:DI 4 ""))
9383 (clobber (match_scratch:SI 5 ""))])]
9384 "TARGET_STRING && ! TARGET_POWERPC64"
9385 "")
9387 (define_insn ""
9388 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9389 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9390 (use (match_operand:SI 2 "immediate_operand" "i"))
9391 (use (match_operand:SI 3 "immediate_operand" "i"))
9392 (clobber (match_scratch:DI 4 "=&r"))
9393 (clobber (match_scratch:SI 5 "=q"))]
9394 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9395 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9396 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9397 [(set_attr "type" "load")
9398 (set_attr "length" "8")])
9400 (define_insn ""
9401 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9402 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9403 (use (match_operand:SI 2 "immediate_operand" "i"))
9404 (use (match_operand:SI 3 "immediate_operand" "i"))
9405 (clobber (match_scratch:DI 4 "=&r"))
9406 (clobber (match_scratch:SI 5 "X"))]
9407 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9408 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9409 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9410 [(set_attr "type" "load")
9411 (set_attr "length" "8")])
9413 ;; Move up to 4 bytes at a time.
9414 (define_expand "movstrsi_1reg"
9415 [(parallel [(set (match_operand 0 "" "")
9416 (match_operand 1 "" ""))
9417 (use (match_operand 2 "" ""))
9418 (use (match_operand 3 "" ""))
9419 (clobber (match_scratch:SI 4 ""))
9420 (clobber (match_scratch:SI 5 ""))])]
9421 "TARGET_STRING"
9422 "")
9424 (define_insn ""
9425 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9426 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9427 (use (match_operand:SI 2 "immediate_operand" "i"))
9428 (use (match_operand:SI 3 "immediate_operand" "i"))
9429 (clobber (match_scratch:SI 4 "=&r"))
9430 (clobber (match_scratch:SI 5 "=q"))]
9431 "TARGET_STRING && TARGET_POWER
9432 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9433 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9434 [(set_attr "type" "load")
9435 (set_attr "length" "8")])
9437 (define_insn ""
9438 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9439 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9440 (use (match_operand:SI 2 "immediate_operand" "i"))
9441 (use (match_operand:SI 3 "immediate_operand" "i"))
9442 (clobber (match_scratch:SI 4 "=&r"))
9443 (clobber (match_scratch:SI 5 "X"))]
9444 "TARGET_STRING && ! TARGET_POWER
9445 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9446 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9447 [(set_attr "type" "load")
9448 (set_attr "length" "8")])
9450 (define_insn ""
9451 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9452 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9453 (use (match_operand:SI 2 "immediate_operand" "i"))
9454 (use (match_operand:SI 3 "immediate_operand" "i"))
9455 (clobber (match_scratch:SI 4 "=&r"))
9456 (clobber (match_scratch:SI 5 "X"))]
9457 "TARGET_STRING && TARGET_POWERPC64
9458 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9459 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9460 [(set_attr "type" "load")
9461 (set_attr "length" "8")])
9463 \f
9464 ;; Define insns that do load or store with update. Some of these we can
9465 ;; get by using pre-decrement or pre-increment, but the hardware can also
9466 ;; do cases where the increment is not the size of the object.
9467 ;;
9468 ;; In all these cases, we use operands 0 and 1 for the register being
9469 ;; incremented because those are the operands that local-alloc will
9470 ;; tie and these are the pair most likely to be tieable (and the ones
9471 ;; that will benefit the most).
9473 (define_insn "*movdi_update1"
9474 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9475 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9476 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9477 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9478 (plus:DI (match_dup 1) (match_dup 2)))]
9479 "TARGET_POWERPC64 && TARGET_UPDATE"
9480 "@
9481 ldux %3,%0,%2
9482 ldu %3,%2(%0)"
9483 [(set_attr "type" "load_ux,load_u")])
9485 (define_insn "movdi_update"
9486 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9487 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
9488 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9489 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9490 (plus:DI (match_dup 1) (match_dup 2)))]
9491 "TARGET_POWERPC64 && TARGET_UPDATE"
9492 "@
9493 stdux %3,%0,%2
9494 stdu %3,%2(%0)"
9495 [(set_attr "type" "store_ux,store_u")])
9497 (define_insn "*movsi_update1"
9498 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9499 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9500 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9501 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9502 (plus:SI (match_dup 1) (match_dup 2)))]
9503 "TARGET_UPDATE"
9504 "@
9505 {lux|lwzux} %3,%0,%2
9506 {lu|lwzu} %3,%2(%0)"
9507 [(set_attr "type" "load_ux,load_u")])
9509 (define_insn "*movsi_update2"
9510 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9511 (sign_extend:DI
9512 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9513 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9514 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9515 (plus:DI (match_dup 1) (match_dup 2)))]
9516 "TARGET_POWERPC64"
9517 "lwaux %3,%0,%2"
9518 [(set_attr "type" "load_ext_ux")])
9520 (define_insn "movsi_update"
9521 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9522 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9523 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9524 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9525 (plus:SI (match_dup 1) (match_dup 2)))]
9526 "TARGET_UPDATE"
9527 "@
9528 {stux|stwux} %3,%0,%2
9529 {stu|stwu} %3,%2(%0)"
9530 [(set_attr "type" "store_ux,store_u")])
9532 (define_insn "*movhi_update1"
9533 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9534 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9535 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9536 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9537 (plus:SI (match_dup 1) (match_dup 2)))]
9538 "TARGET_UPDATE"
9539 "@
9540 lhzux %3,%0,%2
9541 lhzu %3,%2(%0)"
9542 [(set_attr "type" "load_ux,load_u")])
9544 (define_insn "*movhi_update2"
9545 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9546 (zero_extend:SI
9547 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9548 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9549 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9550 (plus:SI (match_dup 1) (match_dup 2)))]
9551 "TARGET_UPDATE"
9552 "@
9553 lhzux %3,%0,%2
9554 lhzu %3,%2(%0)"
9555 [(set_attr "type" "load_ux,load_u")])
9557 (define_insn "*movhi_update3"
9558 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9559 (sign_extend:SI
9560 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9561 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9562 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9563 (plus:SI (match_dup 1) (match_dup 2)))]
9564 "TARGET_UPDATE"
9565 "@
9566 lhaux %3,%0,%2
9567 lhau %3,%2(%0)"
9568 [(set_attr "type" "load_ext_ux,load_ext_u")])
9570 (define_insn "*movhi_update4"
9571 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9572 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9573 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9574 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9575 (plus:SI (match_dup 1) (match_dup 2)))]
9576 "TARGET_UPDATE"
9577 "@
9578 sthux %3,%0,%2
9579 sthu %3,%2(%0)"
9580 [(set_attr "type" "store_ux,store_u")])
9582 (define_insn "*movqi_update1"
9583 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9584 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9585 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9586 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9587 (plus:SI (match_dup 1) (match_dup 2)))]
9588 "TARGET_UPDATE"
9589 "@
9590 lbzux %3,%0,%2
9591 lbzu %3,%2(%0)"
9592 [(set_attr "type" "load_ux,load_u")])
9594 (define_insn "*movqi_update2"
9595 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9596 (zero_extend:SI
9597 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9598 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9599 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9600 (plus:SI (match_dup 1) (match_dup 2)))]
9601 "TARGET_UPDATE"
9602 "@
9603 lbzux %3,%0,%2
9604 lbzu %3,%2(%0)"
9605 [(set_attr "type" "load_ux,load_u")])
9607 (define_insn "*movqi_update3"
9608 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9609 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9610 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9611 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9612 (plus:SI (match_dup 1) (match_dup 2)))]
9613 "TARGET_UPDATE"
9614 "@
9615 stbux %3,%0,%2
9616 stbu %3,%2(%0)"
9617 [(set_attr "type" "store_ux,store_u")])
9619 (define_insn "*movsf_update1"
9620 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9621 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9622 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9623 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9624 (plus:SI (match_dup 1) (match_dup 2)))]
9625 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9626 "@
9627 lfsux %3,%0,%2
9628 lfsu %3,%2(%0)"
9629 [(set_attr "type" "fpload_ux,fpload_u")])
9631 (define_insn "*movsf_update2"
9632 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9633 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9634 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9635 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9636 (plus:SI (match_dup 1) (match_dup 2)))]
9637 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9638 "@
9639 stfsux %3,%0,%2
9640 stfsu %3,%2(%0)"
9641 [(set_attr "type" "fpstore_ux,fpstore_u")])
9643 (define_insn "*movsf_update3"
9644 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9645 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9646 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9647 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9648 (plus:SI (match_dup 1) (match_dup 2)))]
9649 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9650 "@
9651 {lux|lwzux} %3,%0,%2
9652 {lu|lwzu} %3,%2(%0)"
9653 [(set_attr "type" "load_ux,load_u")])
9655 (define_insn "*movsf_update4"
9656 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9657 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9658 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9659 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9660 (plus:SI (match_dup 1) (match_dup 2)))]
9661 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9662 "@
9663 {stux|stwux} %3,%0,%2
9664 {stu|stwu} %3,%2(%0)"
9665 [(set_attr "type" "store_ux,store_u")])
9667 (define_insn "*movdf_update1"
9668 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9669 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9670 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9671 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9672 (plus:SI (match_dup 1) (match_dup 2)))]
9673 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9674 "@
9675 lfdux %3,%0,%2
9676 lfdu %3,%2(%0)"
9677 [(set_attr "type" "fpload_ux,fpload_u")])
9679 (define_insn "*movdf_update2"
9680 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9681 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9682 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9683 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9684 (plus:SI (match_dup 1) (match_dup 2)))]
9685 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9686 "@
9687 stfdux %3,%0,%2
9688 stfdu %3,%2(%0)"
9689 [(set_attr "type" "fpstore_ux,fpstore_u")])
9691 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9693 (define_peephole
9694 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9695 (match_operand:DF 1 "memory_operand" ""))
9696 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9697 (match_operand:DF 3 "memory_operand" ""))]
9698 "TARGET_POWER2
9699 && TARGET_HARD_FLOAT && TARGET_FPRS
9700 && registers_ok_for_quad_peep (operands[0], operands[2])
9701 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9702 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9703 "lfq%U1%X1 %0,%1")
9705 (define_peephole
9706 [(set (match_operand:DF 0 "memory_operand" "")
9707 (match_operand:DF 1 "gpc_reg_operand" "f"))
9708 (set (match_operand:DF 2 "memory_operand" "")
9709 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9710 "TARGET_POWER2
9711 && TARGET_HARD_FLOAT && TARGET_FPRS
9712 && registers_ok_for_quad_peep (operands[1], operands[3])
9713 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9714 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9715 "stfq%U0%X0 %1,%0")
9716 \f
9717 ;; TLS support.
9719 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9720 (define_insn "tls_gd_32"
9721 [(set (match_operand:SI 0 "register_operand" "=b")
9722 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9723 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9724 UNSPEC_TLSGD))]
9725 "HAVE_AS_TLS && !TARGET_64BIT"
9726 "addi %0,%1,%2@got@tlsgd")
9728 (define_insn "tls_gd_64"
9729 [(set (match_operand:DI 0 "register_operand" "=b")
9730 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9731 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9732 UNSPEC_TLSGD))]
9733 "HAVE_AS_TLS && TARGET_64BIT"
9734 "addi %0,%1,%2@got@tlsgd")
9736 (define_insn "tls_ld_32"
9737 [(set (match_operand:SI 0 "register_operand" "=b")
9738 (unspec:SI [(match_operand:SI 1 "register_operand" "b")]
9739 UNSPEC_TLSLD))]
9740 "HAVE_AS_TLS && !TARGET_64BIT"
9741 "addi %0,%1,%&@got@tlsld")
9743 (define_insn "tls_ld_64"
9744 [(set (match_operand:DI 0 "register_operand" "=b")
9745 (unspec:DI [(match_operand:DI 1 "register_operand" "b")]
9746 UNSPEC_TLSLD))]
9747 "HAVE_AS_TLS && TARGET_64BIT"
9748 "addi %0,%1,%&@got@tlsld")
9750 (define_insn "tls_dtprel_32"
9751 [(set (match_operand:SI 0 "register_operand" "=r")
9752 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9753 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9754 UNSPEC_TLSDTPREL))]
9755 "HAVE_AS_TLS && !TARGET_64BIT"
9756 "addi %0,%1,%2@dtprel")
9758 (define_insn "tls_dtprel_64"
9759 [(set (match_operand:DI 0 "register_operand" "=r")
9760 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9761 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9762 UNSPEC_TLSDTPREL))]
9763 "HAVE_AS_TLS && TARGET_64BIT"
9764 "addi %0,%1,%2@dtprel")
9766 (define_insn "tls_dtprel_ha_32"
9767 [(set (match_operand:SI 0 "register_operand" "=r")
9768 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9769 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9770 UNSPEC_TLSDTPRELHA))]
9771 "HAVE_AS_TLS && !TARGET_64BIT"
9772 "addis %0,%1,%2@dtprel@ha")
9774 (define_insn "tls_dtprel_ha_64"
9775 [(set (match_operand:DI 0 "register_operand" "=r")
9776 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9777 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9778 UNSPEC_TLSDTPRELHA))]
9779 "HAVE_AS_TLS && TARGET_64BIT"
9780 "addis %0,%1,%2@dtprel@ha")
9782 (define_insn "tls_dtprel_lo_32"
9783 [(set (match_operand:SI 0 "register_operand" "=r")
9784 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9785 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9786 UNSPEC_TLSDTPRELLO))]
9787 "HAVE_AS_TLS && !TARGET_64BIT"
9788 "addi %0,%1,%2@dtprel@l")
9790 (define_insn "tls_dtprel_lo_64"
9791 [(set (match_operand:DI 0 "register_operand" "=r")
9792 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9793 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9794 UNSPEC_TLSDTPRELLO))]
9795 "HAVE_AS_TLS && TARGET_64BIT"
9796 "addi %0,%1,%2@dtprel@l")
9798 (define_insn "tls_got_dtprel_32"
9799 [(set (match_operand:SI 0 "register_operand" "=r")
9800 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9801 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9802 UNSPEC_TLSGOTDTPREL))]
9803 "HAVE_AS_TLS && !TARGET_64BIT"
9804 "lwz %0,%2@got@dtprel(%1)")
9806 (define_insn "tls_got_dtprel_64"
9807 [(set (match_operand:DI 0 "register_operand" "=r")
9808 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9809 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9810 UNSPEC_TLSGOTDTPREL))]
9811 "HAVE_AS_TLS && TARGET_64BIT"
9812 "ld %0,%2@got@dtprel(%1)")
9814 (define_insn "tls_tprel_32"
9815 [(set (match_operand:SI 0 "register_operand" "=r")
9816 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9817 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9818 UNSPEC_TLSTPREL))]
9819 "HAVE_AS_TLS && !TARGET_64BIT"
9820 "addi %0,%1,%2@tprel")
9822 (define_insn "tls_tprel_64"
9823 [(set (match_operand:DI 0 "register_operand" "=r")
9824 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9825 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9826 UNSPEC_TLSTPREL))]
9827 "HAVE_AS_TLS && TARGET_64BIT"
9828 "addi %0,%1,%2@tprel")
9830 (define_insn "tls_tprel_ha_32"
9831 [(set (match_operand:SI 0 "register_operand" "=r")
9832 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9833 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9834 UNSPEC_TLSTPRELHA))]
9835 "HAVE_AS_TLS && !TARGET_64BIT"
9836 "addis %0,%1,%2@tprel@ha")
9838 (define_insn "tls_tprel_ha_64"
9839 [(set (match_operand:DI 0 "register_operand" "=r")
9840 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9841 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9842 UNSPEC_TLSTPRELHA))]
9843 "HAVE_AS_TLS && TARGET_64BIT"
9844 "addis %0,%1,%2@tprel@ha")
9846 (define_insn "tls_tprel_lo_32"
9847 [(set (match_operand:SI 0 "register_operand" "=r")
9848 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9849 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9850 UNSPEC_TLSTPRELLO))]
9851 "HAVE_AS_TLS && !TARGET_64BIT"
9852 "addi %0,%1,%2@tprel@l")
9854 (define_insn "tls_tprel_lo_64"
9855 [(set (match_operand:DI 0 "register_operand" "=r")
9856 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9857 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9858 UNSPEC_TLSTPRELLO))]
9859 "HAVE_AS_TLS && TARGET_64BIT"
9860 "addi %0,%1,%2@tprel@l")
9862 ;; "b" output constraint here and on tls_tls input to support linker tls
9863 ;; optimization. The linker may edit the instructions emitted by a
9864 ;; tls_got_tprel/tls_tls pair to addis,addi.
9865 (define_insn "tls_got_tprel_32"
9866 [(set (match_operand:SI 0 "register_operand" "=b")
9867 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9868 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9869 UNSPEC_TLSGOTTPREL))]
9870 "HAVE_AS_TLS && !TARGET_64BIT"
9871 "lwz %0,%2@got@tprel(%1)")
9873 (define_insn "tls_got_tprel_64"
9874 [(set (match_operand:DI 0 "register_operand" "=b")
9875 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9876 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9877 UNSPEC_TLSGOTTPREL))]
9878 "HAVE_AS_TLS && TARGET_64BIT"
9879 "ld %0,%2@got@tprel(%1)")
9881 (define_insn "tls_tls_32"
9882 [(set (match_operand:SI 0 "register_operand" "=r")
9883 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9884 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9885 UNSPEC_TLSTLS))]
9886 "HAVE_AS_TLS && !TARGET_64BIT"
9887 "add %0,%1,%2@tls")
9889 (define_insn "tls_tls_64"
9890 [(set (match_operand:DI 0 "register_operand" "=r")
9891 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9892 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9893 UNSPEC_TLSTLS))]
9894 "HAVE_AS_TLS && TARGET_64BIT"
9895 "add %0,%1,%2@tls")
9896 \f
9897 ;; Next come insns related to the calling sequence.
9898 ;;
9899 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9900 ;; We move the back-chain and decrement the stack pointer.
9902 (define_expand "allocate_stack"
9903 [(set (match_operand 0 "gpc_reg_operand" "=r")
9904 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9905 (set (reg 1)
9906 (minus (reg 1) (match_dup 1)))]
9907 ""
9908 "
9909 { rtx chain = gen_reg_rtx (Pmode);
9910 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9911 rtx neg_op0;
9913 emit_move_insn (chain, stack_bot);
9915 /* Check stack bounds if necessary. */
9916 if (current_function_limit_stack)
9917 {
9918 rtx available;
9919 available = expand_binop (Pmode, sub_optab,
9920 stack_pointer_rtx, stack_limit_rtx,
9921 NULL_RTX, 1, OPTAB_WIDEN);
9922 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9923 }
9925 if (GET_CODE (operands[1]) != CONST_INT
9926 || INTVAL (operands[1]) < -32767
9927 || INTVAL (operands[1]) > 32768)
9928 {
9929 neg_op0 = gen_reg_rtx (Pmode);
9930 if (TARGET_32BIT)
9931 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9932 else
9933 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9934 }
9935 else
9936 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9938 if (TARGET_UPDATE)
9939 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9940 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9942 else
9943 {
9944 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9945 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9946 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9947 }
9949 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9950 DONE;
9951 }")
9953 ;; These patterns say how to save and restore the stack pointer. We need not
9954 ;; save the stack pointer at function level since we are careful to
9955 ;; preserve the backchain. At block level, we have to restore the backchain
9956 ;; when we restore the stack pointer.
9957 ;;
9958 ;; For nonlocal gotos, we must save both the stack pointer and its
9959 ;; backchain and restore both. Note that in the nonlocal case, the
9960 ;; save area is a memory location.
9962 (define_expand "save_stack_function"
9963 [(match_operand 0 "any_operand" "")
9964 (match_operand 1 "any_operand" "")]
9965 ""
9966 "DONE;")
9968 (define_expand "restore_stack_function"
9969 [(match_operand 0 "any_operand" "")
9970 (match_operand 1 "any_operand" "")]
9971 ""
9972 "DONE;")
9974 (define_expand "restore_stack_block"
9975 [(use (match_operand 0 "register_operand" ""))
9976 (set (match_dup 2) (match_dup 3))
9977 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9978 (set (match_dup 3) (match_dup 2))]
9979 ""
9980 "
9981 {
9982 operands[2] = gen_reg_rtx (Pmode);
9983 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9984 }")
9986 (define_expand "save_stack_nonlocal"
9987 [(match_operand 0 "memory_operand" "")
9988 (match_operand 1 "register_operand" "")]
9989 ""
9990 "
9991 {
9992 rtx temp = gen_reg_rtx (Pmode);
9994 /* Copy the backchain to the first word, sp to the second. */
9995 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9996 emit_move_insn (operand_subword (operands[0], 0, 0,
9997 (TARGET_32BIT ? DImode : TImode)),
9998 temp);
9999 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
10000 operands[1]);
10001 DONE;
10002 }")
10004 (define_expand "restore_stack_nonlocal"
10005 [(match_operand 0 "register_operand" "")
10006 (match_operand 1 "memory_operand" "")]
10007 ""
10008 "
10009 {
10010 rtx temp = gen_reg_rtx (Pmode);
10012 /* Restore the backchain from the first word, sp from the second. */
10013 emit_move_insn (temp,
10014 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
10015 emit_move_insn (operands[0],
10016 operand_subword (operands[1], 1, 0,
10017 (TARGET_32BIT ? DImode : TImode)));
10018 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
10019 DONE;
10020 }")
10021 \f
10022 ;; TOC register handling.
10024 ;; Code to initialize the TOC register...
10026 (define_insn "load_toc_aix_si"
10027 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10028 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10029 (use (reg:SI 2))])]
10030 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10031 "*
10032 {
10033 char buf[30];
10034 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10035 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10036 operands[2] = gen_rtx_REG (Pmode, 2);
10037 return \"{l|lwz} %0,%1(%2)\";
10038 }"
10039 [(set_attr "type" "load")])
10041 (define_insn "load_toc_aix_di"
10042 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10043 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10044 (use (reg:DI 2))])]
10045 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10046 "*
10047 {
10048 char buf[30];
10049 #ifdef TARGET_RELOCATABLE
10050 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10051 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10052 #else
10053 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10054 #endif
10055 if (TARGET_ELF)
10056 strcat (buf, \"@toc\");
10057 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10058 operands[2] = gen_rtx_REG (Pmode, 2);
10059 return \"ld %0,%1(%2)\";
10060 }"
10061 [(set_attr "type" "load")])
10063 (define_insn "load_toc_v4_pic_si"
10064 [(set (match_operand:SI 0 "register_operand" "=l")
10065 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10066 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10067 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10068 [(set_attr "type" "branch")
10069 (set_attr "length" "4")])
10071 (define_insn "load_toc_v4_PIC_1"
10072 [(set (match_operand:SI 0 "register_operand" "=l")
10073 (match_operand:SI 1 "immediate_operand" "s"))
10074 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10075 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10076 "bcl 20,31,%1\\n%1:"
10077 [(set_attr "type" "branch")
10078 (set_attr "length" "4")])
10080 (define_insn "load_toc_v4_PIC_1b"
10081 [(set (match_operand:SI 0 "register_operand" "=l")
10082 (match_operand:SI 1 "immediate_operand" "s"))
10083 (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
10084 UNSPEC_TOCPTR))]
10085 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10086 "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1"
10087 [(set_attr "type" "branch")
10088 (set_attr "length" "8")])
10090 (define_insn "load_toc_v4_PIC_2"
10091 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10092 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10093 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10094 (match_operand:SI 3 "immediate_operand" "s")))))]
10095 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10096 "{l|lwz} %0,%2-%3(%1)"
10097 [(set_attr "type" "load")])
10099 (define_insn "load_macho_picbase"
10100 [(set (match_operand:SI 0 "register_operand" "=l")
10101 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10102 UNSPEC_LD_MPIC))]
10103 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
10104 "bcl 20,31,%1\\n%1:"
10105 [(set_attr "type" "branch")
10106 (set_attr "length" "4")])
10108 (define_insn "macho_correct_pic"
10109 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10110 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10111 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
10112 (match_operand:SI 3 "immediate_operand" "s")]
10113 UNSPEC_MPIC_CORRECT)))]
10114 "DEFAULT_ABI == ABI_DARWIN"
10115 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
10116 [(set_attr "length" "8")])
10118 ;; If the TOC is shared over a translation unit, as happens with all
10119 ;; the kinds of PIC that we support, we need to restore the TOC
10120 ;; pointer only when jumping over units of translation.
10121 ;; On Darwin, we need to reload the picbase.
10123 (define_expand "builtin_setjmp_receiver"
10124 [(use (label_ref (match_operand 0 "" "")))]
10125 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10126 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10127 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10128 "
10129 {
10130 #if TARGET_MACHO
10131 if (DEFAULT_ABI == ABI_DARWIN)
10132 {
10133 const char *picbase = machopic_function_base_name ();
10134 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10135 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10136 rtx tmplabrtx;
10137 char tmplab[20];
10139 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10140 CODE_LABEL_NUMBER (operands[0]));
10141 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10143 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10144 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10145 }
10146 else
10147 #endif
10148 rs6000_emit_load_toc_table (FALSE);
10149 DONE;
10150 }")
10151 \f
10152 ;; A function pointer under AIX is a pointer to a data area whose first word
10153 ;; contains the actual address of the function, whose second word contains a
10154 ;; pointer to its TOC, and whose third word contains a value to place in the
10155 ;; static chain register (r11). Note that if we load the static chain, our
10156 ;; "trampoline" need not have any executable code.
10158 (define_expand "call_indirect_aix32"
10159 [(set (match_dup 2)
10160 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10161 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10162 (reg:SI 2))
10163 (set (reg:SI 2)
10164 (mem:SI (plus:SI (match_dup 0)
10165 (const_int 4))))
10166 (set (reg:SI 11)
10167 (mem:SI (plus:SI (match_dup 0)
10168 (const_int 8))))
10169 (parallel [(call (mem:SI (match_dup 2))
10170 (match_operand 1 "" ""))
10171 (use (reg:SI 2))
10172 (use (reg:SI 11))
10173 (set (reg:SI 2)
10174 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10175 (clobber (scratch:SI))])]
10176 "TARGET_32BIT"
10177 "
10178 { operands[2] = gen_reg_rtx (SImode); }")
10180 (define_expand "call_indirect_aix64"
10181 [(set (match_dup 2)
10182 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10183 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10184 (reg:DI 2))
10185 (set (reg:DI 2)
10186 (mem:DI (plus:DI (match_dup 0)
10187 (const_int 8))))
10188 (set (reg:DI 11)
10189 (mem:DI (plus:DI (match_dup 0)
10190 (const_int 16))))
10191 (parallel [(call (mem:SI (match_dup 2))
10192 (match_operand 1 "" ""))
10193 (use (reg:DI 2))
10194 (use (reg:DI 11))
10195 (set (reg:DI 2)
10196 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10197 (clobber (scratch:SI))])]
10198 "TARGET_64BIT"
10199 "
10200 { operands[2] = gen_reg_rtx (DImode); }")
10202 (define_expand "call_value_indirect_aix32"
10203 [(set (match_dup 3)
10204 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10205 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10206 (reg:SI 2))
10207 (set (reg:SI 2)
10208 (mem:SI (plus:SI (match_dup 1)
10209 (const_int 4))))
10210 (set (reg:SI 11)
10211 (mem:SI (plus:SI (match_dup 1)
10212 (const_int 8))))
10213 (parallel [(set (match_operand 0 "" "")
10214 (call (mem:SI (match_dup 3))
10215 (match_operand 2 "" "")))
10216 (use (reg:SI 2))
10217 (use (reg:SI 11))
10218 (set (reg:SI 2)
10219 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10220 (clobber (scratch:SI))])]
10221 "TARGET_32BIT"
10222 "
10223 { operands[3] = gen_reg_rtx (SImode); }")
10225 (define_expand "call_value_indirect_aix64"
10226 [(set (match_dup 3)
10227 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10228 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10229 (reg:DI 2))
10230 (set (reg:DI 2)
10231 (mem:DI (plus:DI (match_dup 1)
10232 (const_int 8))))
10233 (set (reg:DI 11)
10234 (mem:DI (plus:DI (match_dup 1)
10235 (const_int 16))))
10236 (parallel [(set (match_operand 0 "" "")
10237 (call (mem:SI (match_dup 3))
10238 (match_operand 2 "" "")))
10239 (use (reg:DI 2))
10240 (use (reg:DI 11))
10241 (set (reg:DI 2)
10242 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10243 (clobber (scratch:SI))])]
10244 "TARGET_64BIT"
10245 "
10246 { operands[3] = gen_reg_rtx (DImode); }")
10248 ;; Now the definitions for the call and call_value insns
10249 (define_expand "call"
10250 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10251 (match_operand 1 "" ""))
10252 (use (match_operand 2 "" ""))
10253 (clobber (scratch:SI))])]
10254 ""
10255 "
10256 {
10257 #if TARGET_MACHO
10258 if (MACHOPIC_INDIRECT)
10259 operands[0] = machopic_indirect_call_target (operands[0]);
10260 #endif
10262 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10263 abort ();
10265 operands[0] = XEXP (operands[0], 0);
10267 if (GET_CODE (operands[0]) != SYMBOL_REF
10268 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10269 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10270 {
10271 if (INTVAL (operands[2]) & CALL_LONG)
10272 operands[0] = rs6000_longcall_ref (operands[0]);
10274 if (DEFAULT_ABI == ABI_V4
10275 || DEFAULT_ABI == ABI_DARWIN)
10276 operands[0] = force_reg (Pmode, operands[0]);
10278 else if (DEFAULT_ABI == ABI_AIX)
10279 {
10280 /* AIX function pointers are really pointers to a three word
10281 area. */
10282 emit_call_insn (TARGET_32BIT
10283 ? gen_call_indirect_aix32 (force_reg (SImode,
10284 operands[0]),
10285 operands[1])
10286 : gen_call_indirect_aix64 (force_reg (DImode,
10287 operands[0]),
10288 operands[1]));
10289 DONE;
10290 }
10291 else
10292 abort ();
10293 }
10294 }")
10296 (define_expand "call_value"
10297 [(parallel [(set (match_operand 0 "" "")
10298 (call (mem:SI (match_operand 1 "address_operand" ""))
10299 (match_operand 2 "" "")))
10300 (use (match_operand 3 "" ""))
10301 (clobber (scratch:SI))])]
10302 ""
10303 "
10304 {
10305 #if TARGET_MACHO
10306 if (MACHOPIC_INDIRECT)
10307 operands[1] = machopic_indirect_call_target (operands[1]);
10308 #endif
10310 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10311 abort ();
10313 operands[1] = XEXP (operands[1], 0);
10315 if (GET_CODE (operands[1]) != SYMBOL_REF
10316 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10317 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10318 {
10319 if (INTVAL (operands[3]) & CALL_LONG)
10320 operands[1] = rs6000_longcall_ref (operands[1]);
10322 if (DEFAULT_ABI == ABI_V4
10323 || DEFAULT_ABI == ABI_DARWIN)
10324 operands[1] = force_reg (Pmode, operands[1]);
10326 else if (DEFAULT_ABI == ABI_AIX)
10327 {
10328 /* AIX function pointers are really pointers to a three word
10329 area. */
10330 emit_call_insn (TARGET_32BIT
10331 ? gen_call_value_indirect_aix32 (operands[0],
10332 force_reg (SImode,
10333 operands[1]),
10334 operands[2])
10335 : gen_call_value_indirect_aix64 (operands[0],
10336 force_reg (DImode,
10337 operands[1]),
10338 operands[2]));
10339 DONE;
10340 }
10341 else
10342 abort ();
10343 }
10344 }")
10346 ;; Call to function in current module. No TOC pointer reload needed.
10347 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10348 ;; either the function was not prototyped, or it was prototyped as a
10349 ;; variable argument function. It is > 0 if FP registers were passed
10350 ;; and < 0 if they were not.
10352 (define_insn "*call_local32"
10353 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10354 (match_operand 1 "" "g,g"))
10355 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10356 (clobber (match_scratch:SI 3 "=l,l"))]
10357 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10358 "*
10359 {
10360 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10361 output_asm_insn (\"crxor 6,6,6\", operands);
10363 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10364 output_asm_insn (\"creqv 6,6,6\", operands);
10366 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10367 }"
10368 [(set_attr "type" "branch")
10369 (set_attr "length" "4,8")])
10371 (define_insn "*call_local64"
10372 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10373 (match_operand 1 "" "g,g"))
10374 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10375 (clobber (match_scratch:SI 3 "=l,l"))]
10376 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10377 "*
10378 {
10379 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10380 output_asm_insn (\"crxor 6,6,6\", operands);
10382 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10383 output_asm_insn (\"creqv 6,6,6\", operands);
10385 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10386 }"
10387 [(set_attr "type" "branch")
10388 (set_attr "length" "4,8")])
10390 (define_insn "*call_value_local32"
10391 [(set (match_operand 0 "" "")
10392 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10393 (match_operand 2 "" "g,g")))
10394 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10395 (clobber (match_scratch:SI 4 "=l,l"))]
10396 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10397 "*
10398 {
10399 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10400 output_asm_insn (\"crxor 6,6,6\", operands);
10402 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10403 output_asm_insn (\"creqv 6,6,6\", operands);
10405 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10406 }"
10407 [(set_attr "type" "branch")
10408 (set_attr "length" "4,8")])
10411 (define_insn "*call_value_local64"
10412 [(set (match_operand 0 "" "")
10413 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10414 (match_operand 2 "" "g,g")))
10415 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10416 (clobber (match_scratch:SI 4 "=l,l"))]
10417 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10418 "*
10419 {
10420 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10421 output_asm_insn (\"crxor 6,6,6\", operands);
10423 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10424 output_asm_insn (\"creqv 6,6,6\", operands);
10426 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10427 }"
10428 [(set_attr "type" "branch")
10429 (set_attr "length" "4,8")])
10431 ;; Call to function which may be in another module. Restore the TOC
10432 ;; pointer (r2) after the call unless this is System V.
10433 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10434 ;; either the function was not prototyped, or it was prototyped as a
10435 ;; variable argument function. It is > 0 if FP registers were passed
10436 ;; and < 0 if they were not.
10438 (define_insn "*call_indirect_nonlocal_aix32"
10439 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10440 (match_operand 1 "" "g"))
10441 (use (reg:SI 2))
10442 (use (reg:SI 11))
10443 (set (reg:SI 2)
10444 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10445 (clobber (match_scratch:SI 2 "=l"))]
10446 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10447 "b%T0l\;{l|lwz} 2,20(1)"
10448 [(set_attr "type" "jmpreg")
10449 (set_attr "length" "8")])
10451 (define_insn "*call_nonlocal_aix32"
10452 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10453 (match_operand 1 "" "g"))
10454 (use (match_operand:SI 2 "immediate_operand" "O"))
10455 (clobber (match_scratch:SI 3 "=l"))]
10456 "TARGET_32BIT
10457 && DEFAULT_ABI == ABI_AIX
10458 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10459 "bl %z0\;%."
10460 [(set_attr "type" "branch")
10461 (set_attr "length" "8")])
10463 (define_insn "*call_indirect_nonlocal_aix64"
10464 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10465 (match_operand 1 "" "g"))
10466 (use (reg:DI 2))
10467 (use (reg:DI 11))
10468 (set (reg:DI 2)
10469 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10470 (clobber (match_scratch:SI 2 "=l"))]
10471 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10472 "b%T0l\;ld 2,40(1)"
10473 [(set_attr "type" "jmpreg")
10474 (set_attr "length" "8")])
10476 (define_insn "*call_nonlocal_aix64"
10477 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10478 (match_operand 1 "" "g"))
10479 (use (match_operand:SI 2 "immediate_operand" "O"))
10480 (clobber (match_scratch:SI 3 "=l"))]
10481 "TARGET_64BIT
10482 && DEFAULT_ABI == ABI_AIX
10483 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10484 "bl %z0\;%."
10485 [(set_attr "type" "branch")
10486 (set_attr "length" "8")])
10488 (define_insn "*call_value_indirect_nonlocal_aix32"
10489 [(set (match_operand 0 "" "")
10490 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10491 (match_operand 2 "" "g")))
10492 (use (reg:SI 2))
10493 (use (reg:SI 11))
10494 (set (reg:SI 2)
10495 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10496 (clobber (match_scratch:SI 3 "=l"))]
10497 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10498 "b%T1l\;{l|lwz} 2,20(1)"
10499 [(set_attr "type" "jmpreg")
10500 (set_attr "length" "8")])
10502 (define_insn "*call_value_nonlocal_aix32"
10503 [(set (match_operand 0 "" "")
10504 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10505 (match_operand 2 "" "g")))
10506 (use (match_operand:SI 3 "immediate_operand" "O"))
10507 (clobber (match_scratch:SI 4 "=l"))]
10508 "TARGET_32BIT
10509 && DEFAULT_ABI == ABI_AIX
10510 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10511 "bl %z1\;%."
10512 [(set_attr "type" "branch")
10513 (set_attr "length" "8")])
10515 (define_insn "*call_value_indirect_nonlocal_aix64"
10516 [(set (match_operand 0 "" "")
10517 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10518 (match_operand 2 "" "g")))
10519 (use (reg:DI 2))
10520 (use (reg:DI 11))
10521 (set (reg:DI 2)
10522 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10523 (clobber (match_scratch:SI 3 "=l"))]
10524 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10525 "b%T1l\;ld 2,40(1)"
10526 [(set_attr "type" "jmpreg")
10527 (set_attr "length" "8")])
10529 (define_insn "*call_value_nonlocal_aix64"
10530 [(set (match_operand 0 "" "")
10531 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10532 (match_operand 2 "" "g")))
10533 (use (match_operand:SI 3 "immediate_operand" "O"))
10534 (clobber (match_scratch:SI 4 "=l"))]
10535 "TARGET_64BIT
10536 && DEFAULT_ABI == ABI_AIX
10537 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10538 "bl %z1\;%."
10539 [(set_attr "type" "branch")
10540 (set_attr "length" "8")])
10542 ;; A function pointer under System V is just a normal pointer
10543 ;; operands[0] is the function pointer
10544 ;; operands[1] is the stack size to clean up
10545 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10546 ;; which indicates how to set cr1
10548 (define_insn "*call_indirect_nonlocal_sysv"
10549 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10550 (match_operand 1 "" "g,g"))
10551 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10552 (clobber (match_scratch:SI 3 "=l,l"))]
10553 "DEFAULT_ABI == ABI_V4
10554 || DEFAULT_ABI == ABI_DARWIN"
10555 {
10556 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10557 output_asm_insn ("crxor 6,6,6", operands);
10559 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10560 output_asm_insn ("creqv 6,6,6", operands);
10562 return "b%T0l";
10563 }
10564 [(set_attr "type" "jmpreg,jmpreg")
10565 (set_attr "length" "4,8")])
10567 (define_insn "*call_nonlocal_sysv"
10568 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10569 (match_operand 1 "" "g,g"))
10570 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10571 (clobber (match_scratch:SI 3 "=l,l"))]
10572 "(DEFAULT_ABI == ABI_DARWIN
10573 || (DEFAULT_ABI == ABI_V4
10574 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10575 {
10576 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10577 output_asm_insn ("crxor 6,6,6", operands);
10579 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10580 output_asm_insn ("creqv 6,6,6", operands);
10582 #if TARGET_MACHO
10583 return output_call(insn, operands, 0, 2);
10584 #else
10585 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10586 #endif
10587 }
10588 [(set_attr "type" "branch,branch")
10589 (set_attr "length" "4,8")])
10591 (define_insn "*call_value_indirect_nonlocal_sysv"
10592 [(set (match_operand 0 "" "")
10593 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10594 (match_operand 2 "" "g,g")))
10595 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10596 (clobber (match_scratch:SI 4 "=l,l"))]
10597 "DEFAULT_ABI == ABI_V4
10598 || DEFAULT_ABI == ABI_DARWIN"
10599 {
10600 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10601 output_asm_insn ("crxor 6,6,6", operands);
10603 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10604 output_asm_insn ("creqv 6,6,6", operands);
10606 return "b%T1l";
10607 }
10608 [(set_attr "type" "jmpreg,jmpreg")
10609 (set_attr "length" "4,8")])
10611 (define_insn "*call_value_nonlocal_sysv"
10612 [(set (match_operand 0 "" "")
10613 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10614 (match_operand 2 "" "g,g")))
10615 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10616 (clobber (match_scratch:SI 4 "=l,l"))]
10617 "(DEFAULT_ABI == ABI_DARWIN
10618 || (DEFAULT_ABI == ABI_V4
10619 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10620 {
10621 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10622 output_asm_insn ("crxor 6,6,6", operands);
10624 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10625 output_asm_insn ("creqv 6,6,6", operands);
10627 #if TARGET_MACHO
10628 return output_call(insn, operands, 1, 3);
10629 #else
10630 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10631 #endif
10632 }
10633 [(set_attr "type" "branch,branch")
10634 (set_attr "length" "4,8")])
10636 ;; Call subroutine returning any type.
10637 (define_expand "untyped_call"
10638 [(parallel [(call (match_operand 0 "" "")
10639 (const_int 0))
10640 (match_operand 1 "" "")
10641 (match_operand 2 "" "")])]
10642 ""
10643 "
10644 {
10645 int i;
10647 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10649 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10650 {
10651 rtx set = XVECEXP (operands[2], 0, i);
10652 emit_move_insn (SET_DEST (set), SET_SRC (set));
10653 }
10655 /* The optimizer does not know that the call sets the function value
10656 registers we stored in the result block. We avoid problems by
10657 claiming that all hard registers are used and clobbered at this
10658 point. */
10659 emit_insn (gen_blockage ());
10661 DONE;
10662 }")
10664 ;; sibling call patterns
10665 (define_expand "sibcall"
10666 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10667 (match_operand 1 "" ""))
10668 (use (match_operand 2 "" ""))
10669 (use (match_operand 3 "" ""))
10670 (return)])]
10671 ""
10672 "
10673 {
10674 #if TARGET_MACHO
10675 if (MACHOPIC_INDIRECT)
10676 operands[0] = machopic_indirect_call_target (operands[0]);
10677 #endif
10679 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10680 abort ();
10682 operands[0] = XEXP (operands[0], 0);
10683 operands[3] = gen_reg_rtx (SImode);
10685 }")
10687 ;; this and similar patterns must be marked as using LR, otherwise
10688 ;; dataflow will try to delete the store into it. This is true
10689 ;; even when the actual reg to jump to is in CTR, when LR was
10690 ;; saved and restored around the PIC-setting BCL.
10691 (define_insn "*sibcall_local32"
10692 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10693 (match_operand 1 "" "g,g"))
10694 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10695 (use (match_operand:SI 3 "register_operand" "l,l"))
10696 (return)]
10697 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10698 "*
10699 {
10700 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10701 output_asm_insn (\"crxor 6,6,6\", operands);
10703 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10704 output_asm_insn (\"creqv 6,6,6\", operands);
10706 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10707 }"
10708 [(set_attr "type" "branch")
10709 (set_attr "length" "4,8")])
10711 (define_insn "*sibcall_local64"
10712 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10713 (match_operand 1 "" "g,g"))
10714 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10715 (use (match_operand:SI 3 "register_operand" "l,l"))
10716 (return)]
10717 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10718 "*
10719 {
10720 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10721 output_asm_insn (\"crxor 6,6,6\", operands);
10723 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10724 output_asm_insn (\"creqv 6,6,6\", operands);
10726 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10727 }"
10728 [(set_attr "type" "branch")
10729 (set_attr "length" "4,8")])
10731 (define_insn "*sibcall_value_local32"
10732 [(set (match_operand 0 "" "")
10733 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10734 (match_operand 2 "" "g,g")))
10735 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10736 (use (match_operand:SI 4 "register_operand" "l,l"))
10737 (return)]
10738 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10739 "*
10740 {
10741 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10742 output_asm_insn (\"crxor 6,6,6\", operands);
10744 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10745 output_asm_insn (\"creqv 6,6,6\", operands);
10747 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10748 }"
10749 [(set_attr "type" "branch")
10750 (set_attr "length" "4,8")])
10753 (define_insn "*sibcall_value_local64"
10754 [(set (match_operand 0 "" "")
10755 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10756 (match_operand 2 "" "g,g")))
10757 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10758 (use (match_operand:SI 4 "register_operand" "l,l"))
10759 (return)]
10760 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10761 "*
10762 {
10763 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10764 output_asm_insn (\"crxor 6,6,6\", operands);
10766 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10767 output_asm_insn (\"creqv 6,6,6\", operands);
10769 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10770 }"
10771 [(set_attr "type" "branch")
10772 (set_attr "length" "4,8")])
10774 (define_insn "*sibcall_nonlocal_aix32"
10775 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10776 (match_operand 1 "" "g"))
10777 (use (match_operand:SI 2 "immediate_operand" "O"))
10778 (use (match_operand:SI 3 "register_operand" "l"))
10779 (return)]
10780 "TARGET_32BIT
10781 && DEFAULT_ABI == ABI_AIX
10782 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10783 "b %z0"
10784 [(set_attr "type" "branch")
10785 (set_attr "length" "4")])
10787 (define_insn "*sibcall_nonlocal_aix64"
10788 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10789 (match_operand 1 "" "g"))
10790 (use (match_operand:SI 2 "immediate_operand" "O"))
10791 (use (match_operand:SI 3 "register_operand" "l"))
10792 (return)]
10793 "TARGET_64BIT
10794 && DEFAULT_ABI == ABI_AIX
10795 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10796 "b %z0"
10797 [(set_attr "type" "branch")
10798 (set_attr "length" "4")])
10800 (define_insn "*sibcall_value_nonlocal_aix32"
10801 [(set (match_operand 0 "" "")
10802 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10803 (match_operand 2 "" "g")))
10804 (use (match_operand:SI 3 "immediate_operand" "O"))
10805 (use (match_operand:SI 4 "register_operand" "l"))
10806 (return)]
10807 "TARGET_32BIT
10808 && DEFAULT_ABI == ABI_AIX
10809 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10810 "b %z1"
10811 [(set_attr "type" "branch")
10812 (set_attr "length" "4")])
10814 (define_insn "*sibcall_value_nonlocal_aix64"
10815 [(set (match_operand 0 "" "")
10816 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10817 (match_operand 2 "" "g")))
10818 (use (match_operand:SI 3 "immediate_operand" "O"))
10819 (use (match_operand:SI 4 "register_operand" "l"))
10820 (return)]
10821 "TARGET_64BIT
10822 && DEFAULT_ABI == ABI_AIX
10823 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10824 "b %z1"
10825 [(set_attr "type" "branch")
10826 (set_attr "length" "4")])
10828 (define_insn "*sibcall_nonlocal_sysv"
10829 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10830 (match_operand 1 "" ""))
10831 (use (match_operand 2 "immediate_operand" "O,n"))
10832 (use (match_operand:SI 3 "register_operand" "l,l"))
10833 (return)]
10834 "(DEFAULT_ABI == ABI_DARWIN
10835 || DEFAULT_ABI == ABI_V4)
10836 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10837 "*
10838 {
10839 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10840 output_asm_insn (\"crxor 6,6,6\", operands);
10842 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10843 output_asm_insn (\"creqv 6,6,6\", operands);
10845 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10846 }"
10847 [(set_attr "type" "branch,branch")
10848 (set_attr "length" "4,8")])
10850 (define_expand "sibcall_value"
10851 [(parallel [(set (match_operand 0 "register_operand" "")
10852 (call (mem:SI (match_operand 1 "address_operand" ""))
10853 (match_operand 2 "" "")))
10854 (use (match_operand 3 "" ""))
10855 (use (match_operand 4 "" ""))
10856 (return)])]
10857 ""
10858 "
10859 {
10860 #if TARGET_MACHO
10861 if (MACHOPIC_INDIRECT)
10862 operands[1] = machopic_indirect_call_target (operands[1]);
10863 #endif
10865 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10866 abort ();
10868 operands[1] = XEXP (operands[1], 0);
10869 operands[4] = gen_reg_rtx (SImode);
10871 }")
10873 (define_insn "*sibcall_value_nonlocal_sysv"
10874 [(set (match_operand 0 "" "")
10875 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10876 (match_operand 2 "" "")))
10877 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10878 (use (match_operand:SI 4 "register_operand" "l,l"))
10879 (return)]
10880 "(DEFAULT_ABI == ABI_DARWIN
10881 || DEFAULT_ABI == ABI_V4)
10882 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10883 "*
10884 {
10885 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10886 output_asm_insn (\"crxor 6,6,6\", operands);
10888 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10889 output_asm_insn (\"creqv 6,6,6\", operands);
10891 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10892 }"
10893 [(set_attr "type" "branch,branch")
10894 (set_attr "length" "4,8")])
10896 (define_expand "sibcall_epilogue"
10897 [(use (const_int 0))]
10898 "TARGET_SCHED_PROLOG"
10899 "
10900 {
10901 rs6000_emit_epilogue (TRUE);
10902 DONE;
10903 }")
10905 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10906 ;; all of memory. This blocks insns from being moved across this point.
10908 (define_insn "blockage"
10909 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10910 ""
10911 "")
10912 \f
10913 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10914 ;; signed & unsigned, and one type of branch.
10915 ;;
10916 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10917 ;; insns, and branches. We store the operands of compares until we see
10918 ;; how it is used.
10919 (define_expand "cmpsi"
10920 [(set (cc0)
10921 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10922 (match_operand:SI 1 "reg_or_short_operand" "")))]
10923 ""
10924 "
10925 {
10926 /* Take care of the possibility that operands[1] might be negative but
10927 this might be a logical operation. That insn doesn't exist. */
10928 if (GET_CODE (operands[1]) == CONST_INT
10929 && INTVAL (operands[1]) < 0)
10930 operands[1] = force_reg (SImode, operands[1]);
10932 rs6000_compare_op0 = operands[0];
10933 rs6000_compare_op1 = operands[1];
10934 rs6000_compare_fp_p = 0;
10935 DONE;
10936 }")
10938 (define_expand "cmpdi"
10939 [(set (cc0)
10940 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10941 (match_operand:DI 1 "reg_or_short_operand" "")))]
10942 "TARGET_POWERPC64"
10943 "
10944 {
10945 /* Take care of the possibility that operands[1] might be negative but
10946 this might be a logical operation. That insn doesn't exist. */
10947 if (GET_CODE (operands[1]) == CONST_INT
10948 && INTVAL (operands[1]) < 0)
10949 operands[1] = force_reg (DImode, operands[1]);
10951 rs6000_compare_op0 = operands[0];
10952 rs6000_compare_op1 = operands[1];
10953 rs6000_compare_fp_p = 0;
10954 DONE;
10955 }")
10957 (define_expand "cmpsf"
10958 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10959 (match_operand:SF 1 "gpc_reg_operand" "")))]
10960 "TARGET_HARD_FLOAT"
10961 "
10962 {
10963 rs6000_compare_op0 = operands[0];
10964 rs6000_compare_op1 = operands[1];
10965 rs6000_compare_fp_p = 1;
10966 DONE;
10967 }")
10969 (define_expand "cmpdf"
10970 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10971 (match_operand:DF 1 "gpc_reg_operand" "")))]
10972 "TARGET_HARD_FLOAT && TARGET_FPRS"
10973 "
10974 {
10975 rs6000_compare_op0 = operands[0];
10976 rs6000_compare_op1 = operands[1];
10977 rs6000_compare_fp_p = 1;
10978 DONE;
10979 }")
10981 (define_expand "cmptf"
10982 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10983 (match_operand:TF 1 "gpc_reg_operand" "")))]
10984 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10985 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10986 "
10987 {
10988 rs6000_compare_op0 = operands[0];
10989 rs6000_compare_op1 = operands[1];
10990 rs6000_compare_fp_p = 1;
10991 DONE;
10992 }")
10994 (define_expand "beq"
10995 [(use (match_operand 0 "" ""))]
10996 ""
10997 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10999 (define_expand "bne"
11000 [(use (match_operand 0 "" ""))]
11001 ""
11002 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11004 (define_expand "bge"
11005 [(use (match_operand 0 "" ""))]
11006 ""
11007 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11009 (define_expand "bgt"
11010 [(use (match_operand 0 "" ""))]
11011 ""
11012 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11014 (define_expand "ble"
11015 [(use (match_operand 0 "" ""))]
11016 ""
11017 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11019 (define_expand "blt"
11020 [(use (match_operand 0 "" ""))]
11021 ""
11022 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11024 (define_expand "bgeu"
11025 [(use (match_operand 0 "" ""))]
11026 ""
11027 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11029 (define_expand "bgtu"
11030 [(use (match_operand 0 "" ""))]
11031 ""
11032 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11034 (define_expand "bleu"
11035 [(use (match_operand 0 "" ""))]
11036 ""
11037 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11039 (define_expand "bltu"
11040 [(use (match_operand 0 "" ""))]
11041 ""
11042 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11044 (define_expand "bunordered"
11045 [(use (match_operand 0 "" ""))]
11046 ""
11047 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11049 (define_expand "bordered"
11050 [(use (match_operand 0 "" ""))]
11051 ""
11052 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11054 (define_expand "buneq"
11055 [(use (match_operand 0 "" ""))]
11056 ""
11057 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11059 (define_expand "bunge"
11060 [(use (match_operand 0 "" ""))]
11061 ""
11062 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11064 (define_expand "bungt"
11065 [(use (match_operand 0 "" ""))]
11066 ""
11067 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11069 (define_expand "bunle"
11070 [(use (match_operand 0 "" ""))]
11071 ""
11072 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11074 (define_expand "bunlt"
11075 [(use (match_operand 0 "" ""))]
11076 ""
11077 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11079 (define_expand "bltgt"
11080 [(use (match_operand 0 "" ""))]
11081 ""
11082 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11084 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11085 ;; For SEQ, likewise, except that comparisons with zero should be done
11086 ;; with an scc insns. However, due to the order that combine see the
11087 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11088 ;; the cases we don't want to handle.
11089 (define_expand "seq"
11090 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11091 ""
11092 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11094 (define_expand "sne"
11095 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11096 ""
11097 "
11098 {
11099 if (! rs6000_compare_fp_p)
11100 FAIL;
11102 rs6000_emit_sCOND (NE, operands[0]);
11103 DONE;
11104 }")
11106 ;; A >= 0 is best done the portable way for A an integer.
11107 (define_expand "sge"
11108 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11109 ""
11110 "
11111 {
11112 if (! rs6000_compare_fp_p
11113 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11114 FAIL;
11116 rs6000_emit_sCOND (GE, operands[0]);
11117 DONE;
11118 }")
11120 ;; A > 0 is best done using the portable sequence, so fail in that case.
11121 (define_expand "sgt"
11122 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11123 ""
11124 "
11125 {
11126 if (! rs6000_compare_fp_p
11127 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11128 FAIL;
11130 rs6000_emit_sCOND (GT, operands[0]);
11131 DONE;
11132 }")
11134 ;; A <= 0 is best done the portable way for A an integer.
11135 (define_expand "sle"
11136 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11137 ""
11138 "
11139 {
11140 if (! rs6000_compare_fp_p
11141 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11142 FAIL;
11144 rs6000_emit_sCOND (LE, operands[0]);
11145 DONE;
11146 }")
11148 ;; A < 0 is best done in the portable way for A an integer.
11149 (define_expand "slt"
11150 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11151 ""
11152 "
11153 {
11154 if (! rs6000_compare_fp_p
11155 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11156 FAIL;
11158 rs6000_emit_sCOND (LT, operands[0]);
11159 DONE;
11160 }")
11162 (define_expand "sgeu"
11163 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11164 ""
11165 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11167 (define_expand "sgtu"
11168 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11169 ""
11170 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11172 (define_expand "sleu"
11173 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11174 ""
11175 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11177 (define_expand "sltu"
11178 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11179 ""
11180 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11182 (define_expand "sunordered"
11183 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11184 ""
11185 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11187 (define_expand "sordered"
11188 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11189 ""
11190 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11192 (define_expand "suneq"
11193 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11194 ""
11195 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11197 (define_expand "sunge"
11198 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11199 ""
11200 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11202 (define_expand "sungt"
11203 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11204 ""
11205 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11207 (define_expand "sunle"
11208 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11209 ""
11210 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11212 (define_expand "sunlt"
11213 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11214 ""
11215 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11217 (define_expand "sltgt"
11218 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11219 ""
11220 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11222 \f
11223 ;; Here are the actual compare insns.
11224 (define_insn "*cmpsi_internal1"
11225 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11226 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11227 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11228 ""
11229 "{cmp%I2|cmpw%I2} %0,%1,%2"
11230 [(set_attr "type" "cmp")])
11232 (define_insn "*cmpdi_internal1"
11233 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11234 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11235 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11236 "TARGET_POWERPC64"
11237 "cmpd%I2 %0,%1,%2"
11238 [(set_attr "type" "cmp")])
11240 ;; If we are comparing a register for equality with a large constant,
11241 ;; we can do this with an XOR followed by a compare. But we need a scratch
11242 ;; register for the result of the XOR.
11244 (define_split
11245 [(set (match_operand:CC 0 "cc_reg_operand" "")
11246 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11247 (match_operand:SI 2 "non_short_cint_operand" "")))
11248 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11249 "find_single_use (operands[0], insn, 0)
11250 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11251 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11252 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11253 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11254 "
11255 {
11256 /* Get the constant we are comparing against, C, and see what it looks like
11257 sign-extended to 16 bits. Then see what constant could be XOR'ed
11258 with C to get the sign-extended value. */
11260 HOST_WIDE_INT c = INTVAL (operands[2]);
11261 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11262 HOST_WIDE_INT xorv = c ^ sextc;
11264 operands[4] = GEN_INT (xorv);
11265 operands[5] = GEN_INT (sextc);
11266 }")
11268 (define_insn "*cmpsi_internal2"
11269 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11270 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11271 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11272 ""
11273 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11274 [(set_attr "type" "cmp")])
11276 (define_insn "*cmpdi_internal2"
11277 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11278 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11279 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11280 ""
11281 "cmpld%I2 %0,%1,%b2"
11282 [(set_attr "type" "cmp")])
11284 ;; The following two insns don't exist as single insns, but if we provide
11285 ;; them, we can swap an add and compare, which will enable us to overlap more
11286 ;; of the required delay between a compare and branch. We generate code for
11287 ;; them by splitting.
11289 (define_insn ""
11290 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11291 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11292 (match_operand:SI 2 "short_cint_operand" "i")))
11293 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11294 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11295 ""
11296 "#"
11297 [(set_attr "length" "8")])
11299 (define_insn ""
11300 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11301 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11302 (match_operand:SI 2 "u_short_cint_operand" "i")))
11303 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11304 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11305 ""
11306 "#"
11307 [(set_attr "length" "8")])
11309 (define_split
11310 [(set (match_operand:CC 3 "cc_reg_operand" "")
11311 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11312 (match_operand:SI 2 "short_cint_operand" "")))
11313 (set (match_operand:SI 0 "gpc_reg_operand" "")
11314 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11315 ""
11316 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11317 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11319 (define_split
11320 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11321 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11322 (match_operand:SI 2 "u_short_cint_operand" "")))
11323 (set (match_operand:SI 0 "gpc_reg_operand" "")
11324 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11325 ""
11326 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11327 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11329 (define_insn "*cmpsf_internal1"
11330 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11331 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11332 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11333 "TARGET_HARD_FLOAT && TARGET_FPRS"
11334 "fcmpu %0,%1,%2"
11335 [(set_attr "type" "fpcompare")])
11337 (define_insn "*cmpdf_internal1"
11338 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11339 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11340 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11341 "TARGET_HARD_FLOAT && TARGET_FPRS"
11342 "fcmpu %0,%1,%2"
11343 [(set_attr "type" "fpcompare")])
11345 ;; Only need to compare second words if first words equal
11346 (define_insn "*cmptf_internal1"
11347 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11348 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11349 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11350 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11351 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11352 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11353 [(set_attr "type" "fpcompare")
11354 (set_attr "length" "12")])
11355 \f
11356 ;; Now we have the scc insns. We can do some combinations because of the
11357 ;; way the machine works.
11358 ;;
11359 ;; Note that this is probably faster if we can put an insn between the
11360 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11361 ;; cases the insns below which don't use an intermediate CR field will
11362 ;; be used instead.
11363 (define_insn ""
11364 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11365 (match_operator:SI 1 "scc_comparison_operator"
11366 [(match_operand 2 "cc_reg_operand" "y")
11367 (const_int 0)]))]
11368 ""
11369 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11370 [(set (attr "type")
11371 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11372 (const_string "mfcrf")
11373 ]
11374 (const_string "mfcr")))
11375 (set_attr "length" "12")])
11377 ;; Same as above, but get the OV/ORDERED bit.
11378 (define_insn "move_from_CR_ov_bit"
11379 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11380 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11381 "TARGET_ISEL"
11382 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11383 [(set_attr "type" "mfcr")
11384 (set_attr "length" "12")])
11386 (define_insn ""
11387 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11388 (match_operator:DI 1 "scc_comparison_operator"
11389 [(match_operand 2 "cc_reg_operand" "y")
11390 (const_int 0)]))]
11391 "TARGET_POWERPC64"
11392 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11393 [(set (attr "type")
11394 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11395 (const_string "mfcrf")
11396 ]
11397 (const_string "mfcr")))
11398 (set_attr "length" "12")])
11400 (define_insn ""
11401 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11402 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11403 [(match_operand 2 "cc_reg_operand" "y,y")
11404 (const_int 0)])
11405 (const_int 0)))
11406 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11407 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11408 "TARGET_32BIT"
11409 "@
11410 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11411 #"
11412 [(set_attr "type" "delayed_compare")
11413 (set_attr "length" "12,16")])
11415 (define_split
11416 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11417 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11418 [(match_operand 2 "cc_reg_operand" "")
11419 (const_int 0)])
11420 (const_int 0)))
11421 (set (match_operand:SI 3 "gpc_reg_operand" "")
11422 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11423 "TARGET_32BIT && reload_completed"
11424 [(set (match_dup 3)
11425 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11426 (set (match_dup 0)
11427 (compare:CC (match_dup 3)
11428 (const_int 0)))]
11429 "")
11431 (define_insn ""
11432 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11433 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11434 [(match_operand 2 "cc_reg_operand" "y")
11435 (const_int 0)])
11436 (match_operand:SI 3 "const_int_operand" "n")))]
11437 ""
11438 "*
11439 {
11440 int is_bit = ccr_bit (operands[1], 1);
11441 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11442 int count;
11444 if (is_bit >= put_bit)
11445 count = is_bit - put_bit;
11446 else
11447 count = 32 - (put_bit - is_bit);
11449 operands[4] = GEN_INT (count);
11450 operands[5] = GEN_INT (put_bit);
11452 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11453 }"
11454 [(set (attr "type")
11455 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11456 (const_string "mfcrf")
11457 ]
11458 (const_string "mfcr")))
11459 (set_attr "length" "12")])
11461 (define_insn ""
11462 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11463 (compare:CC
11464 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11465 [(match_operand 2 "cc_reg_operand" "y,y")
11466 (const_int 0)])
11467 (match_operand:SI 3 "const_int_operand" "n,n"))
11468 (const_int 0)))
11469 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11470 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11471 (match_dup 3)))]
11472 ""
11473 "*
11474 {
11475 int is_bit = ccr_bit (operands[1], 1);
11476 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11477 int count;
11479 /* Force split for non-cc0 compare. */
11480 if (which_alternative == 1)
11481 return \"#\";
11483 if (is_bit >= put_bit)
11484 count = is_bit - put_bit;
11485 else
11486 count = 32 - (put_bit - is_bit);
11488 operands[5] = GEN_INT (count);
11489 operands[6] = GEN_INT (put_bit);
11491 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11492 }"
11493 [(set_attr "type" "delayed_compare")
11494 (set_attr "length" "12,16")])
11496 (define_split
11497 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11498 (compare:CC
11499 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11500 [(match_operand 2 "cc_reg_operand" "")
11501 (const_int 0)])
11502 (match_operand:SI 3 "const_int_operand" ""))
11503 (const_int 0)))
11504 (set (match_operand:SI 4 "gpc_reg_operand" "")
11505 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11506 (match_dup 3)))]
11507 "reload_completed"
11508 [(set (match_dup 4)
11509 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11510 (match_dup 3)))
11511 (set (match_dup 0)
11512 (compare:CC (match_dup 4)
11513 (const_int 0)))]
11514 "")
11516 ;; There is a 3 cycle delay between consecutive mfcr instructions
11517 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11519 (define_peephole
11520 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11521 (match_operator:SI 1 "scc_comparison_operator"
11522 [(match_operand 2 "cc_reg_operand" "y")
11523 (const_int 0)]))
11524 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11525 (match_operator:SI 4 "scc_comparison_operator"
11526 [(match_operand 5 "cc_reg_operand" "y")
11527 (const_int 0)]))]
11528 "REGNO (operands[2]) != REGNO (operands[5])"
11529 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11530 [(set_attr "type" "mfcr")
11531 (set_attr "length" "20")])
11533 (define_peephole
11534 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11535 (match_operator:DI 1 "scc_comparison_operator"
11536 [(match_operand 2 "cc_reg_operand" "y")
11537 (const_int 0)]))
11538 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11539 (match_operator:DI 4 "scc_comparison_operator"
11540 [(match_operand 5 "cc_reg_operand" "y")
11541 (const_int 0)]))]
11542 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11543 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11544 [(set_attr "type" "mfcr")
11545 (set_attr "length" "20")])
11547 ;; There are some scc insns that can be done directly, without a compare.
11548 ;; These are faster because they don't involve the communications between
11549 ;; the FXU and branch units. In fact, we will be replacing all of the
11550 ;; integer scc insns here or in the portable methods in emit_store_flag.
11551 ;;
11552 ;; Also support (neg (scc ..)) since that construct is used to replace
11553 ;; branches, (plus (scc ..) ..) since that construct is common and
11554 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11555 ;; cases where it is no more expensive than (neg (scc ..)).
11557 ;; Have reload force a constant into a register for the simple insns that
11558 ;; otherwise won't accept constants. We do this because it is faster than
11559 ;; the cmp/mfcr sequence we would otherwise generate.
11561 (define_insn ""
11562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11563 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11564 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11565 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11566 "TARGET_32BIT"
11567 "@
11568 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11569 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11570 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11571 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11572 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11573 [(set_attr "length" "12,8,12,12,12")])
11575 (define_insn ""
11576 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11577 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11578 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11579 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11580 "TARGET_64BIT"
11581 "@
11582 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11583 subfic %3,%1,0\;adde %0,%3,%1
11584 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11585 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11586 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11587 [(set_attr "length" "12,8,12,12,12")])
11589 (define_insn ""
11590 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11591 (compare:CC
11592 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11593 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11594 (const_int 0)))
11595 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11596 (eq:SI (match_dup 1) (match_dup 2)))
11597 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11598 "TARGET_32BIT"
11599 "@
11600 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11601 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11602 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11603 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11604 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11605 #
11606 #
11607 #
11608 #
11609 #"
11610 [(set_attr "type" "compare")
11611 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11613 (define_split
11614 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11615 (compare:CC
11616 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11617 (match_operand:SI 2 "reg_or_cint_operand" ""))
11618 (const_int 0)))
11619 (set (match_operand:SI 0 "gpc_reg_operand" "")
11620 (eq:SI (match_dup 1) (match_dup 2)))
11621 (clobber (match_scratch:SI 3 ""))]
11622 "TARGET_32BIT && reload_completed"
11623 [(parallel [(set (match_dup 0)
11624 (eq:SI (match_dup 1) (match_dup 2)))
11625 (clobber (match_dup 3))])
11626 (set (match_dup 4)
11627 (compare:CC (match_dup 0)
11628 (const_int 0)))]
11629 "")
11631 (define_insn ""
11632 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11633 (compare:CC
11634 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11635 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11636 (const_int 0)))
11637 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11638 (eq:DI (match_dup 1) (match_dup 2)))
11639 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11640 "TARGET_64BIT"
11641 "@
11642 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11643 subfic %3,%1,0\;adde. %0,%3,%1
11644 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11645 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11646 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11647 #
11648 #
11649 #
11650 #
11651 #"
11652 [(set_attr "type" "compare")
11653 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11655 (define_split
11656 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11657 (compare:CC
11658 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11659 (match_operand:DI 2 "reg_or_cint_operand" ""))
11660 (const_int 0)))
11661 (set (match_operand:DI 0 "gpc_reg_operand" "")
11662 (eq:DI (match_dup 1) (match_dup 2)))
11663 (clobber (match_scratch:DI 3 ""))]
11664 "TARGET_64BIT && reload_completed"
11665 [(parallel [(set (match_dup 0)
11666 (eq:DI (match_dup 1) (match_dup 2)))
11667 (clobber (match_dup 3))])
11668 (set (match_dup 4)
11669 (compare:CC (match_dup 0)
11670 (const_int 0)))]
11671 "")
11673 ;; We have insns of the form shown by the first define_insn below. If
11674 ;; there is something inside the comparison operation, we must split it.
11675 (define_split
11676 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11677 (plus:SI (match_operator 1 "comparison_operator"
11678 [(match_operand:SI 2 "" "")
11679 (match_operand:SI 3
11680 "reg_or_cint_operand" "")])
11681 (match_operand:SI 4 "gpc_reg_operand" "")))
11682 (clobber (match_operand:SI 5 "register_operand" ""))]
11683 "! gpc_reg_operand (operands[2], SImode)"
11684 [(set (match_dup 5) (match_dup 2))
11685 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11686 (match_dup 4)))])
11688 (define_insn ""
11689 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11690 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11691 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11692 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11693 "TARGET_32BIT"
11694 "@
11695 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11696 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11697 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11698 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11699 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11700 [(set_attr "length" "12,8,12,12,12")])
11702 (define_insn ""
11703 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11704 (compare:CC
11705 (plus:SI
11706 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11707 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11708 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11709 (const_int 0)))
11710 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11711 "TARGET_32BIT"
11712 "@
11713 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11714 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11715 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11716 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11717 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11718 #
11719 #
11720 #
11721 #
11722 #"
11723 [(set_attr "type" "compare")
11724 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11726 (define_split
11727 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11728 (compare:CC
11729 (plus:SI
11730 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11731 (match_operand:SI 2 "reg_or_cint_operand" ""))
11732 (match_operand:SI 3 "gpc_reg_operand" ""))
11733 (const_int 0)))
11734 (clobber (match_scratch:SI 4 ""))]
11735 "TARGET_32BIT && reload_completed"
11736 [(set (match_dup 4)
11737 (plus:SI (eq:SI (match_dup 1)
11738 (match_dup 2))
11739 (match_dup 3)))
11740 (set (match_dup 0)
11741 (compare:CC (match_dup 4)
11742 (const_int 0)))]
11743 "")
11745 (define_insn ""
11746 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11747 (compare:CC
11748 (plus:SI
11749 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11750 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11751 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11752 (const_int 0)))
11753 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11754 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11755 "TARGET_32BIT"
11756 "@
11757 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11758 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11759 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11760 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11761 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11762 #
11763 #
11764 #
11765 #
11766 #"
11767 [(set_attr "type" "compare")
11768 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11770 (define_split
11771 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11772 (compare:CC
11773 (plus:SI
11774 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11775 (match_operand:SI 2 "reg_or_cint_operand" ""))
11776 (match_operand:SI 3 "gpc_reg_operand" ""))
11777 (const_int 0)))
11778 (set (match_operand:SI 0 "gpc_reg_operand" "")
11779 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11780 "TARGET_32BIT && reload_completed"
11781 [(set (match_dup 0)
11782 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11783 (set (match_dup 4)
11784 (compare:CC (match_dup 0)
11785 (const_int 0)))]
11786 "")
11788 (define_insn ""
11789 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11790 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11791 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11792 "TARGET_32BIT"
11793 "@
11794 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11795 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11796 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11797 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11798 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11799 [(set_attr "length" "12,8,12,12,12")])
11801 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11802 ;; since it nabs/sr is just as fast.
11803 (define_insn "*ne0"
11804 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11805 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11806 (const_int 31)))
11807 (clobber (match_scratch:SI 2 "=&r"))]
11808 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11809 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11810 [(set_attr "length" "8")])
11812 (define_insn ""
11813 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11814 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11815 (const_int 63)))
11816 (clobber (match_scratch:DI 2 "=&r"))]
11817 "TARGET_64BIT"
11818 "addic %2,%1,-1\;subfe %0,%2,%1"
11819 [(set_attr "length" "8")])
11821 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11822 (define_insn ""
11823 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11824 (plus:SI (lshiftrt:SI
11825 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11826 (const_int 31))
11827 (match_operand:SI 2 "gpc_reg_operand" "r")))
11828 (clobber (match_scratch:SI 3 "=&r"))]
11829 "TARGET_32BIT"
11830 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11831 [(set_attr "length" "8")])
11833 (define_insn ""
11834 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11835 (plus:DI (lshiftrt:DI
11836 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11837 (const_int 63))
11838 (match_operand:DI 2 "gpc_reg_operand" "r")))
11839 (clobber (match_scratch:DI 3 "=&r"))]
11840 "TARGET_64BIT"
11841 "addic %3,%1,-1\;addze %0,%2"
11842 [(set_attr "length" "8")])
11844 (define_insn ""
11845 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11846 (compare:CC
11847 (plus:SI (lshiftrt:SI
11848 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11849 (const_int 31))
11850 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11851 (const_int 0)))
11852 (clobber (match_scratch:SI 3 "=&r,&r"))
11853 (clobber (match_scratch:SI 4 "=X,&r"))]
11854 "TARGET_32BIT"
11855 "@
11856 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11857 #"
11858 [(set_attr "type" "compare")
11859 (set_attr "length" "8,12")])
11861 (define_split
11862 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11863 (compare:CC
11864 (plus:SI (lshiftrt:SI
11865 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11866 (const_int 31))
11867 (match_operand:SI 2 "gpc_reg_operand" ""))
11868 (const_int 0)))
11869 (clobber (match_scratch:SI 3 ""))
11870 (clobber (match_scratch:SI 4 ""))]
11871 "TARGET_32BIT && reload_completed"
11872 [(parallel [(set (match_dup 3)
11873 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11874 (const_int 31))
11875 (match_dup 2)))
11876 (clobber (match_dup 4))])
11877 (set (match_dup 0)
11878 (compare:CC (match_dup 3)
11879 (const_int 0)))]
11880 "")
11882 (define_insn ""
11883 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11884 (compare:CC
11885 (plus:DI (lshiftrt:DI
11886 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11887 (const_int 63))
11888 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11889 (const_int 0)))
11890 (clobber (match_scratch:DI 3 "=&r,&r"))]
11891 "TARGET_64BIT"
11892 "@
11893 addic %3,%1,-1\;addze. %3,%2
11894 #"
11895 [(set_attr "type" "compare")
11896 (set_attr "length" "8,12")])
11898 (define_split
11899 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11900 (compare:CC
11901 (plus:DI (lshiftrt:DI
11902 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11903 (const_int 63))
11904 (match_operand:DI 2 "gpc_reg_operand" ""))
11905 (const_int 0)))
11906 (clobber (match_scratch:DI 3 ""))]
11907 "TARGET_64BIT && reload_completed"
11908 [(set (match_dup 3)
11909 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11910 (const_int 63))
11911 (match_dup 2)))
11912 (set (match_dup 0)
11913 (compare:CC (match_dup 3)
11914 (const_int 0)))]
11915 "")
11917 (define_insn ""
11918 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11919 (compare:CC
11920 (plus:SI (lshiftrt:SI
11921 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11922 (const_int 31))
11923 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11924 (const_int 0)))
11925 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11926 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11927 (match_dup 2)))
11928 (clobber (match_scratch:SI 3 "=&r,&r"))]
11929 "TARGET_32BIT"
11930 "@
11931 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11932 #"
11933 [(set_attr "type" "compare")
11934 (set_attr "length" "8,12")])
11936 (define_split
11937 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11938 (compare:CC
11939 (plus:SI (lshiftrt:SI
11940 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11941 (const_int 31))
11942 (match_operand:SI 2 "gpc_reg_operand" ""))
11943 (const_int 0)))
11944 (set (match_operand:SI 0 "gpc_reg_operand" "")
11945 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11946 (match_dup 2)))
11947 (clobber (match_scratch:SI 3 ""))]
11948 "TARGET_32BIT && reload_completed"
11949 [(parallel [(set (match_dup 0)
11950 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11951 (match_dup 2)))
11952 (clobber (match_dup 3))])
11953 (set (match_dup 4)
11954 (compare:CC (match_dup 0)
11955 (const_int 0)))]
11956 "")
11958 (define_insn ""
11959 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11960 (compare:CC
11961 (plus:DI (lshiftrt:DI
11962 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11963 (const_int 63))
11964 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11965 (const_int 0)))
11966 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11967 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11968 (match_dup 2)))
11969 (clobber (match_scratch:DI 3 "=&r,&r"))]
11970 "TARGET_64BIT"
11971 "@
11972 addic %3,%1,-1\;addze. %0,%2
11973 #"
11974 [(set_attr "type" "compare")
11975 (set_attr "length" "8,12")])
11977 (define_split
11978 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11979 (compare:CC
11980 (plus:DI (lshiftrt:DI
11981 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11982 (const_int 63))
11983 (match_operand:DI 2 "gpc_reg_operand" ""))
11984 (const_int 0)))
11985 (set (match_operand:DI 0 "gpc_reg_operand" "")
11986 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11987 (match_dup 2)))
11988 (clobber (match_scratch:DI 3 ""))]
11989 "TARGET_64BIT && reload_completed"
11990 [(parallel [(set (match_dup 0)
11991 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11992 (match_dup 2)))
11993 (clobber (match_dup 3))])
11994 (set (match_dup 4)
11995 (compare:CC (match_dup 0)
11996 (const_int 0)))]
11997 "")
11999 (define_insn ""
12000 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12001 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12002 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12003 (clobber (match_scratch:SI 3 "=r,X"))]
12004 "TARGET_POWER"
12005 "@
12006 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12007 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12008 [(set_attr "length" "12")])
12010 (define_insn ""
12011 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12012 (compare:CC
12013 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12014 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12015 (const_int 0)))
12016 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12017 (le:SI (match_dup 1) (match_dup 2)))
12018 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12019 "TARGET_POWER"
12020 "@
12021 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12022 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12023 #
12024 #"
12025 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12026 (set_attr "length" "12,12,16,16")])
12028 (define_split
12029 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12030 (compare:CC
12031 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12032 (match_operand:SI 2 "reg_or_short_operand" ""))
12033 (const_int 0)))
12034 (set (match_operand:SI 0 "gpc_reg_operand" "")
12035 (le:SI (match_dup 1) (match_dup 2)))
12036 (clobber (match_scratch:SI 3 ""))]
12037 "TARGET_POWER && reload_completed"
12038 [(parallel [(set (match_dup 0)
12039 (le:SI (match_dup 1) (match_dup 2)))
12040 (clobber (match_dup 3))])
12041 (set (match_dup 4)
12042 (compare:CC (match_dup 0)
12043 (const_int 0)))]
12044 "")
12046 (define_insn ""
12047 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12048 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12049 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12050 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12051 "TARGET_POWER"
12052 "@
12053 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12054 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12055 [(set_attr "length" "12")])
12057 (define_insn ""
12058 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12059 (compare:CC
12060 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12061 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12062 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12063 (const_int 0)))
12064 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12065 "TARGET_POWER"
12066 "@
12067 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12068 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12069 #
12070 #"
12071 [(set_attr "type" "compare")
12072 (set_attr "length" "12,12,16,16")])
12074 (define_split
12075 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12076 (compare:CC
12077 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12078 (match_operand:SI 2 "reg_or_short_operand" ""))
12079 (match_operand:SI 3 "gpc_reg_operand" ""))
12080 (const_int 0)))
12081 (clobber (match_scratch:SI 4 ""))]
12082 "TARGET_POWER && reload_completed"
12083 [(set (match_dup 4)
12084 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12085 (match_dup 3)))
12086 (set (match_dup 0)
12087 (compare:CC (match_dup 4)
12088 (const_int 0)))]
12089 "")
12091 (define_insn ""
12092 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12093 (compare:CC
12094 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12095 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12096 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12097 (const_int 0)))
12098 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12099 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12100 "TARGET_POWER"
12101 "@
12102 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12103 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12104 #
12105 #"
12106 [(set_attr "type" "compare")
12107 (set_attr "length" "12,12,16,16")])
12109 (define_split
12110 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12111 (compare:CC
12112 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12113 (match_operand:SI 2 "reg_or_short_operand" ""))
12114 (match_operand:SI 3 "gpc_reg_operand" ""))
12115 (const_int 0)))
12116 (set (match_operand:SI 0 "gpc_reg_operand" "")
12117 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12118 "TARGET_POWER && reload_completed"
12119 [(set (match_dup 0)
12120 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12121 (set (match_dup 4)
12122 (compare:CC (match_dup 0)
12123 (const_int 0)))]
12124 "")
12126 (define_insn ""
12127 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12128 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12129 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12130 "TARGET_POWER"
12131 "@
12132 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12133 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12134 [(set_attr "length" "12")])
12136 (define_insn ""
12137 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12138 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12139 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12140 "TARGET_32BIT"
12141 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12142 [(set_attr "length" "12")])
12144 (define_insn ""
12145 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12146 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12147 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12148 "TARGET_64BIT"
12149 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12150 [(set_attr "length" "12")])
12152 (define_insn ""
12153 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12154 (compare:CC
12155 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12156 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12157 (const_int 0)))
12158 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12159 (leu:DI (match_dup 1) (match_dup 2)))]
12160 "TARGET_64BIT"
12161 "@
12162 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12163 #"
12164 [(set_attr "type" "compare")
12165 (set_attr "length" "12,16")])
12167 (define_split
12168 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12169 (compare:CC
12170 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12171 (match_operand:DI 2 "reg_or_short_operand" ""))
12172 (const_int 0)))
12173 (set (match_operand:DI 0 "gpc_reg_operand" "")
12174 (leu:DI (match_dup 1) (match_dup 2)))]
12175 "TARGET_64BIT && reload_completed"
12176 [(set (match_dup 0)
12177 (leu:DI (match_dup 1) (match_dup 2)))
12178 (set (match_dup 3)
12179 (compare:CC (match_dup 0)
12180 (const_int 0)))]
12181 "")
12183 (define_insn ""
12184 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12185 (compare:CC
12186 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12187 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12188 (const_int 0)))
12189 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12190 (leu:SI (match_dup 1) (match_dup 2)))]
12191 "TARGET_32BIT"
12192 "@
12193 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12194 #"
12195 [(set_attr "type" "compare")
12196 (set_attr "length" "12,16")])
12198 (define_split
12199 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12200 (compare:CC
12201 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12202 (match_operand:SI 2 "reg_or_short_operand" ""))
12203 (const_int 0)))
12204 (set (match_operand:SI 0 "gpc_reg_operand" "")
12205 (leu:SI (match_dup 1) (match_dup 2)))]
12206 "TARGET_32BIT && reload_completed"
12207 [(set (match_dup 0)
12208 (leu:SI (match_dup 1) (match_dup 2)))
12209 (set (match_dup 3)
12210 (compare:CC (match_dup 0)
12211 (const_int 0)))]
12212 "")
12214 (define_insn ""
12215 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12216 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12217 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12218 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12219 "TARGET_32BIT"
12220 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12221 [(set_attr "length" "8")])
12223 (define_insn ""
12224 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12225 (compare:CC
12226 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12227 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12228 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12229 (const_int 0)))
12230 (clobber (match_scratch:SI 4 "=&r,&r"))]
12231 "TARGET_32BIT"
12232 "@
12233 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12234 #"
12235 [(set_attr "type" "compare")
12236 (set_attr "length" "8,12")])
12238 (define_split
12239 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12240 (compare:CC
12241 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12242 (match_operand:SI 2 "reg_or_short_operand" ""))
12243 (match_operand:SI 3 "gpc_reg_operand" ""))
12244 (const_int 0)))
12245 (clobber (match_scratch:SI 4 ""))]
12246 "TARGET_32BIT && reload_completed"
12247 [(set (match_dup 4)
12248 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12249 (match_dup 3)))
12250 (set (match_dup 0)
12251 (compare:CC (match_dup 4)
12252 (const_int 0)))]
12253 "")
12255 (define_insn ""
12256 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12257 (compare:CC
12258 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12259 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12260 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12261 (const_int 0)))
12262 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12263 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12264 "TARGET_32BIT"
12265 "@
12266 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12267 #"
12268 [(set_attr "type" "compare")
12269 (set_attr "length" "8,12")])
12271 (define_split
12272 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12273 (compare:CC
12274 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12275 (match_operand:SI 2 "reg_or_short_operand" ""))
12276 (match_operand:SI 3 "gpc_reg_operand" ""))
12277 (const_int 0)))
12278 (set (match_operand:SI 0 "gpc_reg_operand" "")
12279 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12280 "TARGET_32BIT && reload_completed"
12281 [(set (match_dup 0)
12282 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12283 (set (match_dup 4)
12284 (compare:CC (match_dup 0)
12285 (const_int 0)))]
12286 "")
12288 (define_insn ""
12289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12290 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12291 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12292 "TARGET_32BIT"
12293 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12294 [(set_attr "length" "12")])
12296 (define_insn ""
12297 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12298 (and:SI (neg:SI
12299 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12300 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12301 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12302 "TARGET_32BIT"
12303 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12304 [(set_attr "length" "12")])
12306 (define_insn ""
12307 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12308 (compare:CC
12309 (and:SI (neg:SI
12310 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12311 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12312 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12313 (const_int 0)))
12314 (clobber (match_scratch:SI 4 "=&r,&r"))]
12315 "TARGET_32BIT"
12316 "@
12317 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12318 #"
12319 [(set_attr "type" "compare")
12320 (set_attr "length" "12,16")])
12322 (define_split
12323 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12324 (compare:CC
12325 (and:SI (neg:SI
12326 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12327 (match_operand:SI 2 "reg_or_short_operand" "")))
12328 (match_operand:SI 3 "gpc_reg_operand" ""))
12329 (const_int 0)))
12330 (clobber (match_scratch:SI 4 ""))]
12331 "TARGET_32BIT && reload_completed"
12332 [(set (match_dup 4)
12333 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12334 (match_dup 3)))
12335 (set (match_dup 0)
12336 (compare:CC (match_dup 4)
12337 (const_int 0)))]
12338 "")
12340 (define_insn ""
12341 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12342 (compare:CC
12343 (and:SI (neg:SI
12344 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12345 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12346 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12347 (const_int 0)))
12348 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12349 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12350 "TARGET_32BIT"
12351 "@
12352 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12353 #"
12354 [(set_attr "type" "compare")
12355 (set_attr "length" "12,16")])
12357 (define_split
12358 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12359 (compare:CC
12360 (and:SI (neg:SI
12361 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12362 (match_operand:SI 2 "reg_or_short_operand" "")))
12363 (match_operand:SI 3 "gpc_reg_operand" ""))
12364 (const_int 0)))
12365 (set (match_operand:SI 0 "gpc_reg_operand" "")
12366 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12367 "TARGET_32BIT && reload_completed"
12368 [(set (match_dup 0)
12369 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12370 (match_dup 3)))
12371 (set (match_dup 4)
12372 (compare:CC (match_dup 0)
12373 (const_int 0)))]
12374 "")
12376 (define_insn ""
12377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12378 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12379 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12380 "TARGET_POWER"
12381 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12382 [(set_attr "length" "12")])
12384 (define_insn ""
12385 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12386 (compare:CC
12387 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12388 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12389 (const_int 0)))
12390 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12391 (lt:SI (match_dup 1) (match_dup 2)))]
12392 "TARGET_POWER"
12393 "@
12394 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12395 #"
12396 [(set_attr "type" "delayed_compare")
12397 (set_attr "length" "12,16")])
12399 (define_split
12400 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12401 (compare:CC
12402 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12403 (match_operand:SI 2 "reg_or_short_operand" ""))
12404 (const_int 0)))
12405 (set (match_operand:SI 0 "gpc_reg_operand" "")
12406 (lt:SI (match_dup 1) (match_dup 2)))]
12407 "TARGET_POWER && reload_completed"
12408 [(set (match_dup 0)
12409 (lt:SI (match_dup 1) (match_dup 2)))
12410 (set (match_dup 3)
12411 (compare:CC (match_dup 0)
12412 (const_int 0)))]
12413 "")
12415 (define_insn ""
12416 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12417 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12418 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12419 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12420 "TARGET_POWER"
12421 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12422 [(set_attr "length" "12")])
12424 (define_insn ""
12425 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12426 (compare:CC
12427 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12428 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12429 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12430 (const_int 0)))
12431 (clobber (match_scratch:SI 4 "=&r,&r"))]
12432 "TARGET_POWER"
12433 "@
12434 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12435 #"
12436 [(set_attr "type" "compare")
12437 (set_attr "length" "12,16")])
12439 (define_split
12440 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12441 (compare:CC
12442 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12443 (match_operand:SI 2 "reg_or_short_operand" ""))
12444 (match_operand:SI 3 "gpc_reg_operand" ""))
12445 (const_int 0)))
12446 (clobber (match_scratch:SI 4 ""))]
12447 "TARGET_POWER && reload_completed"
12448 [(set (match_dup 4)
12449 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12450 (match_dup 3)))
12451 (set (match_dup 0)
12452 (compare:CC (match_dup 4)
12453 (const_int 0)))]
12454 "")
12456 (define_insn ""
12457 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12458 (compare:CC
12459 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12460 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12461 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12462 (const_int 0)))
12463 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12464 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12465 "TARGET_POWER"
12466 "@
12467 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12468 #"
12469 [(set_attr "type" "compare")
12470 (set_attr "length" "12,16")])
12472 (define_split
12473 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12474 (compare:CC
12475 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12476 (match_operand:SI 2 "reg_or_short_operand" ""))
12477 (match_operand:SI 3 "gpc_reg_operand" ""))
12478 (const_int 0)))
12479 (set (match_operand:SI 0 "gpc_reg_operand" "")
12480 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12481 "TARGET_POWER && reload_completed"
12482 [(set (match_dup 0)
12483 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12484 (set (match_dup 4)
12485 (compare:CC (match_dup 0)
12486 (const_int 0)))]
12487 "")
12489 (define_insn ""
12490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12491 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12492 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12493 "TARGET_POWER"
12494 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12495 [(set_attr "length" "12")])
12497 (define_insn ""
12498 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12499 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12500 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12501 "TARGET_32BIT"
12502 "@
12503 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12504 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12505 [(set_attr "length" "12")])
12507 (define_insn ""
12508 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12509 (compare:CC
12510 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12511 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12512 (const_int 0)))
12513 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12514 (ltu:SI (match_dup 1) (match_dup 2)))]
12515 "TARGET_32BIT"
12516 "@
12517 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12518 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12519 #
12520 #"
12521 [(set_attr "type" "compare")
12522 (set_attr "length" "12,12,16,16")])
12524 (define_split
12525 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12526 (compare:CC
12527 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12528 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12529 (const_int 0)))
12530 (set (match_operand:SI 0 "gpc_reg_operand" "")
12531 (ltu:SI (match_dup 1) (match_dup 2)))]
12532 "TARGET_32BIT && reload_completed"
12533 [(set (match_dup 0)
12534 (ltu:SI (match_dup 1) (match_dup 2)))
12535 (set (match_dup 3)
12536 (compare:CC (match_dup 0)
12537 (const_int 0)))]
12538 "")
12540 (define_insn ""
12541 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12542 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12543 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12544 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12545 "TARGET_32BIT"
12546 "@
12547 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12548 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
12549 [(set_attr "length" "12")])
12551 (define_insn ""
12552 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12553 (compare:CC
12554 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12555 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12556 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12557 (const_int 0)))
12558 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12559 "TARGET_32BIT"
12560 "@
12561 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12562 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12563 #
12564 #"
12565 [(set_attr "type" "compare")
12566 (set_attr "length" "12,12,16,16")])
12568 (define_split
12569 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12570 (compare:CC
12571 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12572 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12573 (match_operand:SI 3 "gpc_reg_operand" ""))
12574 (const_int 0)))
12575 (clobber (match_scratch:SI 4 ""))]
12576 "TARGET_32BIT && reload_completed"
12577 [(set (match_dup 4)
12578 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12579 (match_dup 3)))
12580 (set (match_dup 0)
12581 (compare:CC (match_dup 4)
12582 (const_int 0)))]
12583 "")
12585 (define_insn ""
12586 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12587 (compare:CC
12588 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12589 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12590 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12591 (const_int 0)))
12592 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12593 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12594 "TARGET_32BIT"
12595 "@
12596 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12597 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12598 #
12599 #"
12600 [(set_attr "type" "compare")
12601 (set_attr "length" "12,12,16,16")])
12603 (define_split
12604 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12605 (compare:CC
12606 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12607 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12608 (match_operand:SI 3 "gpc_reg_operand" ""))
12609 (const_int 0)))
12610 (set (match_operand:SI 0 "gpc_reg_operand" "")
12611 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12612 "TARGET_32BIT && reload_completed"
12613 [(set (match_dup 0)
12614 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12615 (set (match_dup 4)
12616 (compare:CC (match_dup 0)
12617 (const_int 0)))]
12618 "")
12620 (define_insn ""
12621 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12622 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12623 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12624 "TARGET_32BIT"
12625 "@
12626 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12627 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12628 [(set_attr "length" "8")])
12630 (define_insn ""
12631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12632 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12633 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12634 (clobber (match_scratch:SI 3 "=r"))]
12635 "TARGET_POWER"
12636 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12637 [(set_attr "length" "12")])
12639 (define_insn ""
12640 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12641 (compare:CC
12642 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12643 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12644 (const_int 0)))
12645 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12646 (ge:SI (match_dup 1) (match_dup 2)))
12647 (clobber (match_scratch:SI 3 "=r,r"))]
12648 "TARGET_POWER"
12649 "@
12650 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12651 #"
12652 [(set_attr "type" "compare")
12653 (set_attr "length" "12,16")])
12655 (define_split
12656 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12657 (compare:CC
12658 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12659 (match_operand:SI 2 "reg_or_short_operand" ""))
12660 (const_int 0)))
12661 (set (match_operand:SI 0 "gpc_reg_operand" "")
12662 (ge:SI (match_dup 1) (match_dup 2)))
12663 (clobber (match_scratch:SI 3 ""))]
12664 "TARGET_POWER && reload_completed"
12665 [(parallel [(set (match_dup 0)
12666 (ge:SI (match_dup 1) (match_dup 2)))
12667 (clobber (match_dup 3))])
12668 (set (match_dup 4)
12669 (compare:CC (match_dup 0)
12670 (const_int 0)))]
12671 "")
12673 (define_insn ""
12674 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12675 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12676 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12677 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12678 "TARGET_POWER"
12679 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12680 [(set_attr "length" "12")])
12682 (define_insn ""
12683 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12684 (compare:CC
12685 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12686 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12687 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12688 (const_int 0)))
12689 (clobber (match_scratch:SI 4 "=&r,&r"))]
12690 "TARGET_POWER"
12691 "@
12692 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12693 #"
12694 [(set_attr "type" "compare")
12695 (set_attr "length" "12,16")])
12697 (define_split
12698 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12699 (compare:CC
12700 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12701 (match_operand:SI 2 "reg_or_short_operand" ""))
12702 (match_operand:SI 3 "gpc_reg_operand" ""))
12703 (const_int 0)))
12704 (clobber (match_scratch:SI 4 ""))]
12705 "TARGET_POWER && reload_completed"
12706 [(set (match_dup 4)
12707 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12708 (match_dup 3)))
12709 (set (match_dup 0)
12710 (compare:CC (match_dup 4)
12711 (const_int 0)))]
12712 "")
12714 (define_insn ""
12715 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12716 (compare:CC
12717 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12718 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12719 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12720 (const_int 0)))
12721 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12722 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12723 "TARGET_POWER"
12724 "@
12725 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12726 #"
12727 [(set_attr "type" "compare")
12728 (set_attr "length" "12,16")])
12730 (define_split
12731 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12732 (compare:CC
12733 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12734 (match_operand:SI 2 "reg_or_short_operand" ""))
12735 (match_operand:SI 3 "gpc_reg_operand" ""))
12736 (const_int 0)))
12737 (set (match_operand:SI 0 "gpc_reg_operand" "")
12738 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12739 "TARGET_POWER && reload_completed"
12740 [(set (match_dup 0)
12741 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12742 (set (match_dup 4)
12743 (compare:CC (match_dup 0)
12744 (const_int 0)))]
12745 "")
12747 (define_insn ""
12748 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12749 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12750 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12751 "TARGET_POWER"
12752 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12753 [(set_attr "length" "12")])
12755 (define_insn ""
12756 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12757 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12758 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12759 "TARGET_32BIT"
12760 "@
12761 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12762 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12763 [(set_attr "length" "12")])
12765 (define_insn ""
12766 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12767 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12768 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12769 "TARGET_64BIT"
12770 "@
12771 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12772 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12773 [(set_attr "length" "12")])
12775 (define_insn ""
12776 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12777 (compare:CC
12778 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12779 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12780 (const_int 0)))
12781 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12782 (geu:SI (match_dup 1) (match_dup 2)))]
12783 "TARGET_32BIT"
12784 "@
12785 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12786 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12787 #
12788 #"
12789 [(set_attr "type" "compare")
12790 (set_attr "length" "12,12,16,16")])
12792 (define_split
12793 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12794 (compare:CC
12795 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12796 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12797 (const_int 0)))
12798 (set (match_operand:SI 0 "gpc_reg_operand" "")
12799 (geu:SI (match_dup 1) (match_dup 2)))]
12800 "TARGET_32BIT && reload_completed"
12801 [(set (match_dup 0)
12802 (geu:SI (match_dup 1) (match_dup 2)))
12803 (set (match_dup 3)
12804 (compare:CC (match_dup 0)
12805 (const_int 0)))]
12806 "")
12808 (define_insn ""
12809 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12810 (compare:CC
12811 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12812 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12813 (const_int 0)))
12814 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12815 (geu:DI (match_dup 1) (match_dup 2)))]
12816 "TARGET_64BIT"
12817 "@
12818 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12819 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12820 #
12821 #"
12822 [(set_attr "type" "compare")
12823 (set_attr "length" "12,12,16,16")])
12825 (define_split
12826 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12827 (compare:CC
12828 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12829 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12830 (const_int 0)))
12831 (set (match_operand:DI 0 "gpc_reg_operand" "")
12832 (geu:DI (match_dup 1) (match_dup 2)))]
12833 "TARGET_64BIT && reload_completed"
12834 [(set (match_dup 0)
12835 (geu:DI (match_dup 1) (match_dup 2)))
12836 (set (match_dup 3)
12837 (compare:CC (match_dup 0)
12838 (const_int 0)))]
12839 "")
12841 (define_insn ""
12842 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12843 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12844 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12845 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12846 "TARGET_32BIT"
12847 "@
12848 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12849 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12850 [(set_attr "length" "8")])
12852 (define_insn ""
12853 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12854 (compare:CC
12855 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12856 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12857 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12858 (const_int 0)))
12859 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12860 "TARGET_32BIT"
12861 "@
12862 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12863 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12864 #
12865 #"
12866 [(set_attr "type" "compare")
12867 (set_attr "length" "8,8,12,12")])
12869 (define_split
12870 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12871 (compare:CC
12872 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12873 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12874 (match_operand:SI 3 "gpc_reg_operand" ""))
12875 (const_int 0)))
12876 (clobber (match_scratch:SI 4 ""))]
12877 "TARGET_32BIT && reload_completed"
12878 [(set (match_dup 4)
12879 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12880 (match_dup 3)))
12881 (set (match_dup 0)
12882 (compare:CC (match_dup 4)
12883 (const_int 0)))]
12884 "")
12886 (define_insn ""
12887 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12888 (compare:CC
12889 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12890 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12891 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12892 (const_int 0)))
12893 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12894 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12895 "TARGET_32BIT"
12896 "@
12897 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12898 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12899 #
12900 #"
12901 [(set_attr "type" "compare")
12902 (set_attr "length" "8,8,12,12")])
12904 (define_split
12905 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12906 (compare:CC
12907 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12908 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12909 (match_operand:SI 3 "gpc_reg_operand" ""))
12910 (const_int 0)))
12911 (set (match_operand:SI 0 "gpc_reg_operand" "")
12912 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12913 "TARGET_32BIT && reload_completed"
12914 [(set (match_dup 0)
12915 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12916 (set (match_dup 4)
12917 (compare:CC (match_dup 0)
12918 (const_int 0)))]
12919 "")
12921 (define_insn ""
12922 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12923 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12924 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12925 "TARGET_32BIT"
12926 "@
12927 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12928 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12929 [(set_attr "length" "12")])
12931 (define_insn ""
12932 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12933 (and:SI (neg:SI
12934 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12935 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12936 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12937 "TARGET_32BIT"
12938 "@
12939 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12940 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12941 [(set_attr "length" "12")])
12943 (define_insn ""
12944 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12945 (compare:CC
12946 (and:SI (neg:SI
12947 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12948 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12949 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12950 (const_int 0)))
12951 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12952 "TARGET_32BIT"
12953 "@
12954 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12955 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12956 #
12957 #"
12958 [(set_attr "type" "compare")
12959 (set_attr "length" "12,12,16,16")])
12961 (define_split
12962 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12963 (compare:CC
12964 (and:SI (neg:SI
12965 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12966 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12967 (match_operand:SI 3 "gpc_reg_operand" ""))
12968 (const_int 0)))
12969 (clobber (match_scratch:SI 4 ""))]
12970 "TARGET_32BIT && reload_completed"
12971 [(set (match_dup 4)
12972 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12973 (match_dup 3)))
12974 (set (match_dup 0)
12975 (compare:CC (match_dup 4)
12976 (const_int 0)))]
12977 "")
12979 (define_insn ""
12980 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12981 (compare:CC
12982 (and:SI (neg:SI
12983 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12984 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12985 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12986 (const_int 0)))
12987 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12988 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12989 "TARGET_32BIT"
12990 "@
12991 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12992 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12993 #
12994 #"
12995 [(set_attr "type" "compare")
12996 (set_attr "length" "12,12,16,16")])
12998 (define_split
12999 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13000 (compare:CC
13001 (and:SI (neg:SI
13002 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13003 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13004 (match_operand:SI 3 "gpc_reg_operand" ""))
13005 (const_int 0)))
13006 (set (match_operand:SI 0 "gpc_reg_operand" "")
13007 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13008 "TARGET_32BIT && reload_completed"
13009 [(set (match_dup 0)
13010 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13011 (set (match_dup 4)
13012 (compare:CC (match_dup 0)
13013 (const_int 0)))]
13014 "")
13016 (define_insn ""
13017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13018 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13019 (const_int 0)))]
13020 "TARGET_32BIT"
13021 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
13022 [(set_attr "length" "12")])
13024 (define_insn ""
13025 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13026 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13027 (const_int 0)))]
13028 "TARGET_64BIT"
13029 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
13030 [(set_attr "length" "12")])
13032 (define_insn ""
13033 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13034 (compare:CC
13035 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13036 (const_int 0))
13037 (const_int 0)))
13038 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13039 (gt:SI (match_dup 1) (const_int 0)))]
13040 "TARGET_32BIT"
13041 "@
13042 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
13043 #"
13044 [(set_attr "type" "delayed_compare")
13045 (set_attr "length" "12,16")])
13047 (define_split
13048 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13049 (compare:CC
13050 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13051 (const_int 0))
13052 (const_int 0)))
13053 (set (match_operand:SI 0 "gpc_reg_operand" "")
13054 (gt:SI (match_dup 1) (const_int 0)))]
13055 "TARGET_32BIT && reload_completed"
13056 [(set (match_dup 0)
13057 (gt:SI (match_dup 1) (const_int 0)))
13058 (set (match_dup 2)
13059 (compare:CC (match_dup 0)
13060 (const_int 0)))]
13061 "")
13063 (define_insn ""
13064 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13065 (compare:CC
13066 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13067 (const_int 0))
13068 (const_int 0)))
13069 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13070 (gt:DI (match_dup 1) (const_int 0)))]
13071 "TARGET_64BIT"
13072 "@
13073 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13074 #"
13075 [(set_attr "type" "delayed_compare")
13076 (set_attr "length" "12,16")])
13078 (define_split
13079 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13080 (compare:CC
13081 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13082 (const_int 0))
13083 (const_int 0)))
13084 (set (match_operand:DI 0 "gpc_reg_operand" "")
13085 (gt:DI (match_dup 1) (const_int 0)))]
13086 "TARGET_64BIT && reload_completed"
13087 [(set (match_dup 0)
13088 (gt:DI (match_dup 1) (const_int 0)))
13089 (set (match_dup 2)
13090 (compare:CC (match_dup 0)
13091 (const_int 0)))]
13092 "")
13094 (define_insn ""
13095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13096 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13097 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13098 "TARGET_POWER"
13099 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13100 [(set_attr "length" "12")])
13102 (define_insn ""
13103 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13104 (compare:CC
13105 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13106 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13107 (const_int 0)))
13108 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13109 (gt:SI (match_dup 1) (match_dup 2)))]
13110 "TARGET_POWER"
13111 "@
13112 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13113 #"
13114 [(set_attr "type" "delayed_compare")
13115 (set_attr "length" "12,16")])
13117 (define_split
13118 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13119 (compare:CC
13120 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13121 (match_operand:SI 2 "reg_or_short_operand" ""))
13122 (const_int 0)))
13123 (set (match_operand:SI 0 "gpc_reg_operand" "")
13124 (gt:SI (match_dup 1) (match_dup 2)))]
13125 "TARGET_POWER && reload_completed"
13126 [(set (match_dup 0)
13127 (gt:SI (match_dup 1) (match_dup 2)))
13128 (set (match_dup 3)
13129 (compare:CC (match_dup 0)
13130 (const_int 0)))]
13131 "")
13133 (define_insn ""
13134 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13135 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13136 (const_int 0))
13137 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13138 "TARGET_32BIT"
13139 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13140 [(set_attr "length" "12")])
13142 (define_insn ""
13143 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13144 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13145 (const_int 0))
13146 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13147 "TARGET_64BIT"
13148 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13149 [(set_attr "length" "12")])
13151 (define_insn ""
13152 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13153 (compare:CC
13154 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13155 (const_int 0))
13156 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13157 (const_int 0)))
13158 (clobber (match_scratch:SI 3 "=&r,&r"))]
13159 "TARGET_32BIT"
13160 "@
13161 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13162 #"
13163 [(set_attr "type" "compare")
13164 (set_attr "length" "12,16")])
13166 (define_split
13167 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13168 (compare:CC
13169 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13170 (const_int 0))
13171 (match_operand:SI 2 "gpc_reg_operand" ""))
13172 (const_int 0)))
13173 (clobber (match_scratch:SI 3 ""))]
13174 "TARGET_32BIT && reload_completed"
13175 [(set (match_dup 3)
13176 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13177 (match_dup 2)))
13178 (set (match_dup 0)
13179 (compare:CC (match_dup 3)
13180 (const_int 0)))]
13181 "")
13183 (define_insn ""
13184 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13185 (compare:CC
13186 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13187 (const_int 0))
13188 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13189 (const_int 0)))
13190 (clobber (match_scratch:DI 3 "=&r,&r"))]
13191 "TARGET_64BIT"
13192 "@
13193 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13194 #"
13195 [(set_attr "type" "compare")
13196 (set_attr "length" "12,16")])
13198 (define_split
13199 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13200 (compare:CC
13201 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13202 (const_int 0))
13203 (match_operand:DI 2 "gpc_reg_operand" ""))
13204 (const_int 0)))
13205 (clobber (match_scratch:DI 3 ""))]
13206 "TARGET_64BIT && reload_completed"
13207 [(set (match_dup 3)
13208 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13209 (match_dup 2)))
13210 (set (match_dup 0)
13211 (compare:CC (match_dup 3)
13212 (const_int 0)))]
13213 "")
13215 (define_insn ""
13216 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13217 (compare:CC
13218 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13219 (const_int 0))
13220 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13221 (const_int 0)))
13222 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13223 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13224 "TARGET_32BIT"
13225 "@
13226 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13227 #"
13228 [(set_attr "type" "compare")
13229 (set_attr "length" "12,16")])
13231 (define_split
13232 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13233 (compare:CC
13234 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13235 (const_int 0))
13236 (match_operand:SI 2 "gpc_reg_operand" ""))
13237 (const_int 0)))
13238 (set (match_operand:SI 0 "gpc_reg_operand" "")
13239 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13240 "TARGET_32BIT && reload_completed"
13241 [(set (match_dup 0)
13242 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13243 (set (match_dup 3)
13244 (compare:CC (match_dup 0)
13245 (const_int 0)))]
13246 "")
13248 (define_insn ""
13249 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13250 (compare:CC
13251 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13252 (const_int 0))
13253 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13254 (const_int 0)))
13255 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13256 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13257 "TARGET_64BIT"
13258 "@
13259 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13260 #"
13261 [(set_attr "type" "compare")
13262 (set_attr "length" "12,16")])
13264 (define_split
13265 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13266 (compare:CC
13267 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13268 (const_int 0))
13269 (match_operand:DI 2 "gpc_reg_operand" ""))
13270 (const_int 0)))
13271 (set (match_operand:DI 0 "gpc_reg_operand" "")
13272 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13273 "TARGET_64BIT && reload_completed"
13274 [(set (match_dup 0)
13275 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13276 (set (match_dup 3)
13277 (compare:CC (match_dup 0)
13278 (const_int 0)))]
13279 "")
13281 (define_insn ""
13282 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13283 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13284 (match_operand:SI 2 "reg_or_short_operand" "r"))
13285 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13286 "TARGET_POWER"
13287 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13288 [(set_attr "length" "12")])
13290 (define_insn ""
13291 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13292 (compare:CC
13293 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13294 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13295 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13296 (const_int 0)))
13297 (clobber (match_scratch:SI 4 "=&r,&r"))]
13298 "TARGET_POWER"
13299 "@
13300 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13301 #"
13302 [(set_attr "type" "compare")
13303 (set_attr "length" "12,16")])
13305 (define_split
13306 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13307 (compare:CC
13308 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13309 (match_operand:SI 2 "reg_or_short_operand" ""))
13310 (match_operand:SI 3 "gpc_reg_operand" ""))
13311 (const_int 0)))
13312 (clobber (match_scratch:SI 4 ""))]
13313 "TARGET_POWER && reload_completed"
13314 [(set (match_dup 4)
13315 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13316 (set (match_dup 0)
13317 (compare:CC (match_dup 4)
13318 (const_int 0)))]
13319 "")
13321 (define_insn ""
13322 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13323 (compare:CC
13324 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13325 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13326 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13327 (const_int 0)))
13328 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13329 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13330 "TARGET_POWER"
13331 "@
13332 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13333 #"
13334 [(set_attr "type" "compare")
13335 (set_attr "length" "12,16")])
13337 (define_split
13338 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13339 (compare:CC
13340 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13341 (match_operand:SI 2 "reg_or_short_operand" ""))
13342 (match_operand:SI 3 "gpc_reg_operand" ""))
13343 (const_int 0)))
13344 (set (match_operand:SI 0 "gpc_reg_operand" "")
13345 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13346 "TARGET_POWER && reload_completed"
13347 [(set (match_dup 0)
13348 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13349 (set (match_dup 4)
13350 (compare:CC (match_dup 0)
13351 (const_int 0)))]
13352 "")
13354 (define_insn ""
13355 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13356 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13357 (const_int 0))))]
13358 "TARGET_32BIT"
13359 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13360 [(set_attr "length" "12")])
13362 (define_insn ""
13363 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13364 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13365 (const_int 0))))]
13366 "TARGET_64BIT"
13367 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13368 [(set_attr "length" "12")])
13370 (define_insn ""
13371 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13372 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13373 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13374 "TARGET_POWER"
13375 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13376 [(set_attr "length" "12")])
13378 (define_insn ""
13379 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13380 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13381 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13382 "TARGET_32BIT"
13383 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
13384 [(set_attr "length" "12")])
13386 (define_insn ""
13387 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13388 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13389 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13390 "TARGET_64BIT"
13391 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13392 [(set_attr "length" "12")])
13394 (define_insn ""
13395 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13396 (compare:CC
13397 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13398 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13399 (const_int 0)))
13400 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13401 (gtu:SI (match_dup 1) (match_dup 2)))]
13402 "TARGET_32BIT"
13403 "@
13404 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13405 #"
13406 [(set_attr "type" "compare")
13407 (set_attr "length" "12,16")])
13409 (define_split
13410 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13411 (compare:CC
13412 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13413 (match_operand:SI 2 "reg_or_short_operand" ""))
13414 (const_int 0)))
13415 (set (match_operand:SI 0 "gpc_reg_operand" "")
13416 (gtu:SI (match_dup 1) (match_dup 2)))]
13417 "TARGET_32BIT && reload_completed"
13418 [(set (match_dup 0)
13419 (gtu:SI (match_dup 1) (match_dup 2)))
13420 (set (match_dup 3)
13421 (compare:CC (match_dup 0)
13422 (const_int 0)))]
13423 "")
13425 (define_insn ""
13426 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13427 (compare:CC
13428 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13429 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13430 (const_int 0)))
13431 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13432 (gtu:DI (match_dup 1) (match_dup 2)))]
13433 "TARGET_64BIT"
13434 "@
13435 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13436 #"
13437 [(set_attr "type" "compare")
13438 (set_attr "length" "12,16")])
13440 (define_split
13441 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13442 (compare:CC
13443 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13444 (match_operand:DI 2 "reg_or_short_operand" ""))
13445 (const_int 0)))
13446 (set (match_operand:DI 0 "gpc_reg_operand" "")
13447 (gtu:DI (match_dup 1) (match_dup 2)))]
13448 "TARGET_64BIT && reload_completed"
13449 [(set (match_dup 0)
13450 (gtu:DI (match_dup 1) (match_dup 2)))
13451 (set (match_dup 3)
13452 (compare:CC (match_dup 0)
13453 (const_int 0)))]
13454 "")
13456 (define_insn ""
13457 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13458 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13459 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
13460 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
13461 "TARGET_32BIT"
13462 "@
13463 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13464 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
13465 [(set_attr "length" "8,12")])
13467 (define_insn ""
13468 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13469 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13470 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
13471 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
13472 "TARGET_64BIT"
13473 "@
13474 addic %0,%1,%k2\;addze %0,%3
13475 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
13476 [(set_attr "length" "8,12")])
13478 (define_insn ""
13479 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13480 (compare:CC
13481 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13482 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13483 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13484 (const_int 0)))
13485 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13486 "TARGET_32BIT"
13487 "@
13488 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13489 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13490 #
13491 #"
13492 [(set_attr "type" "compare")
13493 (set_attr "length" "8,12,12,16")])
13495 (define_split
13496 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13497 (compare:CC
13498 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13499 (match_operand:SI 2 "reg_or_short_operand" ""))
13500 (match_operand:SI 3 "gpc_reg_operand" ""))
13501 (const_int 0)))
13502 (clobber (match_scratch:SI 4 ""))]
13503 "TARGET_32BIT && reload_completed"
13504 [(set (match_dup 4)
13505 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13506 (match_dup 3)))
13507 (set (match_dup 0)
13508 (compare:CC (match_dup 4)
13509 (const_int 0)))]
13510 "")
13512 (define_insn ""
13513 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13514 (compare:CC
13515 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13516 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13517 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13518 (const_int 0)))
13519 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13520 "TARGET_64BIT"
13521 "@
13522 addic %4,%1,%k2\;addze. %4,%3
13523 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13524 #
13525 #"
13526 [(set_attr "type" "compare")
13527 (set_attr "length" "8,12,12,16")])
13529 (define_split
13530 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13531 (compare:CC
13532 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13533 (match_operand:DI 2 "reg_or_short_operand" ""))
13534 (match_operand:DI 3 "gpc_reg_operand" ""))
13535 (const_int 0)))
13536 (clobber (match_scratch:DI 4 ""))]
13537 "TARGET_64BIT && reload_completed"
13538 [(set (match_dup 4)
13539 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13540 (match_dup 3)))
13541 (set (match_dup 0)
13542 (compare:CC (match_dup 4)
13543 (const_int 0)))]
13544 "")
13546 (define_insn ""
13547 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13548 (compare:CC
13549 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13550 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13551 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13552 (const_int 0)))
13553 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13554 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13555 "TARGET_32BIT"
13556 "@
13557 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13558 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
13559 #
13560 #"
13561 [(set_attr "type" "compare")
13562 (set_attr "length" "8,12,12,16")])
13564 (define_split
13565 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13566 (compare:CC
13567 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13568 (match_operand:SI 2 "reg_or_short_operand" ""))
13569 (match_operand:SI 3 "gpc_reg_operand" ""))
13570 (const_int 0)))
13571 (set (match_operand:SI 0 "gpc_reg_operand" "")
13572 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13573 "TARGET_32BIT && reload_completed"
13574 [(set (match_dup 0)
13575 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13576 (set (match_dup 4)
13577 (compare:CC (match_dup 0)
13578 (const_int 0)))]
13579 "")
13581 (define_insn ""
13582 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13583 (compare:CC
13584 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13585 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13586 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13587 (const_int 0)))
13588 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13589 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13590 "TARGET_64BIT"
13591 "@
13592 addic %0,%1,%k2\;addze. %0,%3
13593 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
13594 #
13595 #"
13596 [(set_attr "type" "compare")
13597 (set_attr "length" "8,12,12,16")])
13599 (define_split
13600 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13601 (compare:CC
13602 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13603 (match_operand:DI 2 "reg_or_short_operand" ""))
13604 (match_operand:DI 3 "gpc_reg_operand" ""))
13605 (const_int 0)))
13606 (set (match_operand:DI 0 "gpc_reg_operand" "")
13607 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13608 "TARGET_64BIT && reload_completed"
13609 [(set (match_dup 0)
13610 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13611 (set (match_dup 4)
13612 (compare:CC (match_dup 0)
13613 (const_int 0)))]
13614 "")
13616 (define_insn ""
13617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13618 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13619 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13620 "TARGET_32BIT"
13621 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13622 [(set_attr "length" "8")])
13624 (define_insn ""
13625 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13626 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13627 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13628 "TARGET_64BIT"
13629 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13630 [(set_attr "length" "8")])
13631 \f
13632 ;; Define both directions of branch and return. If we need a reload
13633 ;; register, we'd rather use CR0 since it is much easier to copy a
13634 ;; register CC value to there.
13636 (define_insn ""
13637 [(set (pc)
13638 (if_then_else (match_operator 1 "branch_comparison_operator"
13639 [(match_operand 2
13640 "cc_reg_operand" "y")
13641 (const_int 0)])
13642 (label_ref (match_operand 0 "" ""))
13643 (pc)))]
13644 ""
13645 "*
13646 {
13647 return output_cbranch (operands[1], \"%l0\", 0, insn);
13648 }"
13649 [(set_attr "type" "branch")])
13651 (define_insn ""
13652 [(set (pc)
13653 (if_then_else (match_operator 0 "branch_comparison_operator"
13654 [(match_operand 1
13655 "cc_reg_operand" "y")
13656 (const_int 0)])
13657 (return)
13658 (pc)))]
13659 "direct_return ()"
13660 "*
13661 {
13662 return output_cbranch (operands[0], NULL, 0, insn);
13663 }"
13664 [(set_attr "type" "branch")
13665 (set_attr "length" "4")])
13667 (define_insn ""
13668 [(set (pc)
13669 (if_then_else (match_operator 1 "branch_comparison_operator"
13670 [(match_operand 2
13671 "cc_reg_operand" "y")
13672 (const_int 0)])
13673 (pc)
13674 (label_ref (match_operand 0 "" ""))))]
13675 ""
13676 "*
13677 {
13678 return output_cbranch (operands[1], \"%l0\", 1, insn);
13679 }"
13680 [(set_attr "type" "branch")])
13682 (define_insn ""
13683 [(set (pc)
13684 (if_then_else (match_operator 0 "branch_comparison_operator"
13685 [(match_operand 1
13686 "cc_reg_operand" "y")
13687 (const_int 0)])
13688 (pc)
13689 (return)))]
13690 "direct_return ()"
13691 "*
13692 {
13693 return output_cbranch (operands[0], NULL, 1, insn);
13694 }"
13695 [(set_attr "type" "branch")
13696 (set_attr "length" "4")])
13698 ;; Logic on condition register values.
13700 ; This pattern matches things like
13701 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13702 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13703 ; (const_int 1)))
13704 ; which are generated by the branch logic.
13705 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13707 (define_insn ""
13708 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13709 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13710 [(match_operator:SI 2
13711 "branch_positive_comparison_operator"
13712 [(match_operand 3
13713 "cc_reg_operand" "y,y")
13714 (const_int 0)])
13715 (match_operator:SI 4
13716 "branch_positive_comparison_operator"
13717 [(match_operand 5
13718 "cc_reg_operand" "0,y")
13719 (const_int 0)])])
13720 (const_int 1)))]
13721 ""
13722 "cr%q1 %E0,%j2,%j4"
13723 [(set_attr "type" "cr_logical,delayed_cr")])
13725 ; Why is the constant -1 here, but 1 in the previous pattern?
13726 ; Because ~1 has all but the low bit set.
13727 (define_insn ""
13728 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13729 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13730 [(not:SI (match_operator:SI 2
13731 "branch_positive_comparison_operator"
13732 [(match_operand 3
13733 "cc_reg_operand" "y,y")
13734 (const_int 0)]))
13735 (match_operator:SI 4
13736 "branch_positive_comparison_operator"
13737 [(match_operand 5
13738 "cc_reg_operand" "0,y")
13739 (const_int 0)])])
13740 (const_int -1)))]
13741 ""
13742 "cr%q1 %E0,%j2,%j4"
13743 [(set_attr "type" "cr_logical,delayed_cr")])
13745 (define_insn ""
13746 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13747 (compare:CCEQ (match_operator:SI 1
13748 "branch_positive_comparison_operator"
13749 [(match_operand 2
13750 "cc_reg_operand" "0,y")
13751 (const_int 0)])
13752 (const_int 0)))]
13753 "!TARGET_SPE"
13754 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13755 [(set_attr "type" "cr_logical,delayed_cr")])
13757 ;; If we are comparing the result of two comparisons, this can be done
13758 ;; using creqv or crxor.
13760 (define_insn_and_split ""
13761 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13762 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13763 [(match_operand 2 "cc_reg_operand" "y")
13764 (const_int 0)])
13765 (match_operator 3 "branch_comparison_operator"
13766 [(match_operand 4 "cc_reg_operand" "y")
13767 (const_int 0)])))]
13768 ""
13769 "#"
13770 ""
13771 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13772 (match_dup 5)))]
13773 "
13774 {
13775 int positive_1, positive_2;
13777 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13778 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13780 if (! positive_1)
13781 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]),
13782 GET_CODE (operands[1])),
13783 SImode,
13784 operands[2], const0_rtx);
13785 else if (GET_MODE (operands[1]) != SImode)
13786 operands[1] = gen_rtx (GET_CODE (operands[1]),
13787 SImode,
13788 operands[2], const0_rtx);
13790 if (! positive_2)
13791 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]),
13792 GET_CODE (operands[3])),
13793 SImode,
13794 operands[4], const0_rtx);
13795 else if (GET_MODE (operands[3]) != SImode)
13796 operands[3] = gen_rtx (GET_CODE (operands[3]),
13797 SImode,
13798 operands[4], const0_rtx);
13800 if (positive_1 == positive_2)
13801 {
13802 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13803 operands[5] = constm1_rtx;
13804 }
13805 else
13806 {
13807 operands[5] = const1_rtx;
13808 }
13809 }")
13811 ;; Unconditional branch and return.
13813 (define_insn "jump"
13814 [(set (pc)
13815 (label_ref (match_operand 0 "" "")))]
13816 ""
13817 "b %l0"
13818 [(set_attr "type" "branch")])
13820 (define_insn "return"
13821 [(return)]
13822 "direct_return ()"
13823 "{br|blr}"
13824 [(set_attr "type" "jmpreg")])
13826 (define_expand "indirect_jump"
13827 [(set (pc) (match_operand 0 "register_operand" ""))]
13828 ""
13829 "
13830 {
13831 if (TARGET_32BIT)
13832 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13833 else
13834 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13835 DONE;
13836 }")
13838 (define_insn "indirect_jumpsi"
13839 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13840 "TARGET_32BIT"
13841 "@
13842 bctr
13843 {br|blr}"
13844 [(set_attr "type" "jmpreg")])
13846 (define_insn "indirect_jumpdi"
13847 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13848 "TARGET_64BIT"
13849 "@
13850 bctr
13851 blr"
13852 [(set_attr "type" "jmpreg")])
13854 ;; Table jump for switch statements:
13855 (define_expand "tablejump"
13856 [(use (match_operand 0 "" ""))
13857 (use (label_ref (match_operand 1 "" "")))]
13858 ""
13859 "
13860 {
13861 if (TARGET_32BIT)
13862 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13863 else
13864 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13865 DONE;
13866 }")
13868 (define_expand "tablejumpsi"
13869 [(set (match_dup 3)
13870 (plus:SI (match_operand:SI 0 "" "")
13871 (match_dup 2)))
13872 (parallel [(set (pc) (match_dup 3))
13873 (use (label_ref (match_operand 1 "" "")))])]
13874 "TARGET_32BIT"
13875 "
13876 { operands[0] = force_reg (SImode, operands[0]);
13877 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13878 operands[3] = gen_reg_rtx (SImode);
13879 }")
13881 (define_expand "tablejumpdi"
13882 [(set (match_dup 4)
13883 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13884 (set (match_dup 3)
13885 (plus:DI (match_dup 4)
13886 (match_dup 2)))
13887 (parallel [(set (pc) (match_dup 3))
13888 (use (label_ref (match_operand 1 "" "")))])]
13889 "TARGET_64BIT"
13890 "
13891 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13892 operands[3] = gen_reg_rtx (DImode);
13893 operands[4] = gen_reg_rtx (DImode);
13894 }")
13896 (define_insn ""
13897 [(set (pc)
13898 (match_operand:SI 0 "register_operand" "c,*l"))
13899 (use (label_ref (match_operand 1 "" "")))]
13900 "TARGET_32BIT"
13901 "@
13902 bctr
13903 {br|blr}"
13904 [(set_attr "type" "jmpreg")])
13906 (define_insn ""
13907 [(set (pc)
13908 (match_operand:DI 0 "register_operand" "c,*l"))
13909 (use (label_ref (match_operand 1 "" "")))]
13910 "TARGET_64BIT"
13911 "@
13912 bctr
13913 blr"
13914 [(set_attr "type" "jmpreg")])
13916 (define_insn "nop"
13917 [(const_int 0)]
13918 ""
13919 "{cror 0,0,0|nop}")
13920 \f
13921 ;; Define the subtract-one-and-jump insns, starting with the template
13922 ;; so loop.c knows what to generate.
13924 (define_expand "doloop_end"
13925 [(use (match_operand 0 "" "")) ; loop pseudo
13926 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13927 (use (match_operand 2 "" "")) ; max iterations
13928 (use (match_operand 3 "" "")) ; loop level
13929 (use (match_operand 4 "" ""))] ; label
13930 ""
13931 "
13932 {
13933 /* Only use this on innermost loops. */
13934 if (INTVAL (operands[3]) > 1)
13935 FAIL;
13936 if (TARGET_64BIT)
13937 {
13938 if (GET_MODE (operands[0]) != DImode)
13939 FAIL;
13940 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13941 }
13942 else
13943 {
13944 if (GET_MODE (operands[0]) != SImode)
13945 FAIL;
13946 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13947 }
13948 DONE;
13949 }")
13951 (define_expand "ctrsi"
13952 [(parallel [(set (pc)
13953 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13954 (const_int 1))
13955 (label_ref (match_operand 1 "" ""))
13956 (pc)))
13957 (set (match_dup 0)
13958 (plus:SI (match_dup 0)
13959 (const_int -1)))
13960 (clobber (match_scratch:CC 2 ""))
13961 (clobber (match_scratch:SI 3 ""))])]
13962 "TARGET_32BIT"
13963 "")
13965 (define_expand "ctrdi"
13966 [(parallel [(set (pc)
13967 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13968 (const_int 1))
13969 (label_ref (match_operand 1 "" ""))
13970 (pc)))
13971 (set (match_dup 0)
13972 (plus:DI (match_dup 0)
13973 (const_int -1)))
13974 (clobber (match_scratch:CC 2 ""))
13975 (clobber (match_scratch:DI 3 ""))])]
13976 "TARGET_64BIT"
13977 "")
13979 ;; We need to be able to do this for any operand, including MEM, or we
13980 ;; will cause reload to blow up since we don't allow output reloads on
13981 ;; JUMP_INSNs.
13982 ;; For the length attribute to be calculated correctly, the
13983 ;; label MUST be operand 0.
13985 (define_insn "*ctrsi_internal1"
13986 [(set (pc)
13987 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13988 (const_int 1))
13989 (label_ref (match_operand 0 "" ""))
13990 (pc)))
13991 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
13992 (plus:SI (match_dup 1)
13993 (const_int -1)))
13994 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13995 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13996 "TARGET_32BIT"
13997 "*
13998 {
13999 if (which_alternative != 0)
14000 return \"#\";
14001 else if (get_attr_length (insn) == 4)
14002 return \"{bdn|bdnz} %l0\";
14003 else
14004 return \"bdz $+8\;b %l0\";
14005 }"
14006 [(set_attr "type" "branch")
14007 (set_attr "length" "*,12,16,16")])
14009 (define_insn "*ctrsi_internal2"
14010 [(set (pc)
14011 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14012 (const_int 1))
14013 (pc)
14014 (label_ref (match_operand 0 "" ""))))
14015 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14016 (plus:SI (match_dup 1)
14017 (const_int -1)))
14018 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14019 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14020 "TARGET_32BIT"
14021 "*
14022 {
14023 if (which_alternative != 0)
14024 return \"#\";
14025 else if (get_attr_length (insn) == 4)
14026 return \"bdz %l0\";
14027 else
14028 return \"{bdn|bdnz} $+8\;b %l0\";
14029 }"
14030 [(set_attr "type" "branch")
14031 (set_attr "length" "*,12,16,16")])
14033 (define_insn "*ctrdi_internal1"
14034 [(set (pc)
14035 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14036 (const_int 1))
14037 (label_ref (match_operand 0 "" ""))
14038 (pc)))
14039 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14040 (plus:DI (match_dup 1)
14041 (const_int -1)))
14042 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14043 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14044 "TARGET_64BIT"
14045 "*
14046 {
14047 if (which_alternative != 0)
14048 return \"#\";
14049 else if (get_attr_length (insn) == 4)
14050 return \"{bdn|bdnz} %l0\";
14051 else
14052 return \"bdz $+8\;b %l0\";
14053 }"
14054 [(set_attr "type" "branch")
14055 (set_attr "length" "*,12,16,16")])
14057 (define_insn "*ctrdi_internal2"
14058 [(set (pc)
14059 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14060 (const_int 1))
14061 (pc)
14062 (label_ref (match_operand 0 "" ""))))
14063 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14064 (plus:DI (match_dup 1)
14065 (const_int -1)))
14066 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14067 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14068 "TARGET_64BIT"
14069 "*
14070 {
14071 if (which_alternative != 0)
14072 return \"#\";
14073 else if (get_attr_length (insn) == 4)
14074 return \"bdz %l0\";
14075 else
14076 return \"{bdn|bdnz} $+8\;b %l0\";
14077 }"
14078 [(set_attr "type" "branch")
14079 (set_attr "length" "*,12,16,16")])
14081 ;; Similar, but we can use GE since we have a REG_NONNEG.
14083 (define_insn "*ctrsi_internal3"
14084 [(set (pc)
14085 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14086 (const_int 0))
14087 (label_ref (match_operand 0 "" ""))
14088 (pc)))
14089 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14090 (plus:SI (match_dup 1)
14091 (const_int -1)))
14092 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14093 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14094 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
14095 "*
14096 {
14097 if (which_alternative != 0)
14098 return \"#\";
14099 else if (get_attr_length (insn) == 4)
14100 return \"{bdn|bdnz} %l0\";
14101 else
14102 return \"bdz $+8\;b %l0\";
14103 }"
14104 [(set_attr "type" "branch")
14105 (set_attr "length" "*,12,16,16")])
14107 (define_insn "*ctrsi_internal4"
14108 [(set (pc)
14109 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14110 (const_int 0))
14111 (pc)
14112 (label_ref (match_operand 0 "" ""))))
14113 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14114 (plus:SI (match_dup 1)
14115 (const_int -1)))
14116 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14117 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14118 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
14119 "*
14120 {
14121 if (which_alternative != 0)
14122 return \"#\";
14123 else if (get_attr_length (insn) == 4)
14124 return \"bdz %l0\";
14125 else
14126 return \"{bdn|bdnz} $+8\;b %l0\";
14127 }"
14128 [(set_attr "type" "branch")
14129 (set_attr "length" "*,12,16,16")])
14131 (define_insn "*ctrdi_internal3"
14132 [(set (pc)
14133 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14134 (const_int 0))
14135 (label_ref (match_operand 0 "" ""))
14136 (pc)))
14137 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14138 (plus:DI (match_dup 1)
14139 (const_int -1)))
14140 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14141 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14142 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
14143 "*
14144 {
14145 if (which_alternative != 0)
14146 return \"#\";
14147 else if (get_attr_length (insn) == 4)
14148 return \"{bdn|bdnz} %l0\";
14149 else
14150 return \"bdz $+8\;b %l0\";
14151 }"
14152 [(set_attr "type" "branch")
14153 (set_attr "length" "*,12,16,16")])
14155 (define_insn "*ctrdi_internal4"
14156 [(set (pc)
14157 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14158 (const_int 0))
14159 (pc)
14160 (label_ref (match_operand 0 "" ""))))
14161 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14162 (plus:DI (match_dup 1)
14163 (const_int -1)))
14164 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14165 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14166 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
14167 "*
14168 {
14169 if (which_alternative != 0)
14170 return \"#\";
14171 else if (get_attr_length (insn) == 4)
14172 return \"bdz %l0\";
14173 else
14174 return \"{bdn|bdnz} $+8\;b %l0\";
14175 }"
14176 [(set_attr "type" "branch")
14177 (set_attr "length" "*,12,16,16")])
14179 ;; Similar but use EQ
14181 (define_insn "*ctrsi_internal5"
14182 [(set (pc)
14183 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14184 (const_int 1))
14185 (label_ref (match_operand 0 "" ""))
14186 (pc)))
14187 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14188 (plus:SI (match_dup 1)
14189 (const_int -1)))
14190 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14191 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14192 "TARGET_32BIT"
14193 "*
14194 {
14195 if (which_alternative != 0)
14196 return \"#\";
14197 else if (get_attr_length (insn) == 4)
14198 return \"bdz %l0\";
14199 else
14200 return \"{bdn|bdnz} $+8\;b %l0\";
14201 }"
14202 [(set_attr "type" "branch")
14203 (set_attr "length" "*,12,16,16")])
14205 (define_insn "*ctrsi_internal6"
14206 [(set (pc)
14207 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14208 (const_int 1))
14209 (pc)
14210 (label_ref (match_operand 0 "" ""))))
14211 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14212 (plus:SI (match_dup 1)
14213 (const_int -1)))
14214 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14215 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14216 "TARGET_32BIT"
14217 "*
14218 {
14219 if (which_alternative != 0)
14220 return \"#\";
14221 else if (get_attr_length (insn) == 4)
14222 return \"{bdn|bdnz} %l0\";
14223 else
14224 return \"bdz $+8\;b %l0\";
14225 }"
14226 [(set_attr "type" "branch")
14227 (set_attr "length" "*,12,16,16")])
14229 (define_insn "*ctrdi_internal5"
14230 [(set (pc)
14231 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14232 (const_int 1))
14233 (label_ref (match_operand 0 "" ""))
14234 (pc)))
14235 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14236 (plus:DI (match_dup 1)
14237 (const_int -1)))
14238 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14239 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14240 "TARGET_64BIT"
14241 "*
14242 {
14243 if (which_alternative != 0)
14244 return \"#\";
14245 else if (get_attr_length (insn) == 4)
14246 return \"bdz %l0\";
14247 else
14248 return \"{bdn|bdnz} $+8\;b %l0\";
14249 }"
14250 [(set_attr "type" "branch")
14251 (set_attr "length" "*,12,16,16")])
14253 (define_insn "*ctrdi_internal6"
14254 [(set (pc)
14255 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14256 (const_int 1))
14257 (pc)
14258 (label_ref (match_operand 0 "" ""))))
14259 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14260 (plus:DI (match_dup 1)
14261 (const_int -1)))
14262 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14263 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14264 "TARGET_64BIT"
14265 "*
14266 {
14267 if (which_alternative != 0)
14268 return \"#\";
14269 else if (get_attr_length (insn) == 4)
14270 return \"{bdn|bdnz} %l0\";
14271 else
14272 return \"bdz $+8\;b %l0\";
14273 }"
14274 [(set_attr "type" "branch")
14275 (set_attr "length" "*,12,16,16")])
14277 ;; Now the splitters if we could not allocate the CTR register
14279 (define_split
14280 [(set (pc)
14281 (if_then_else (match_operator 2 "comparison_operator"
14282 [(match_operand:SI 1 "gpc_reg_operand" "")
14283 (const_int 1)])
14284 (match_operand 5 "" "")
14285 (match_operand 6 "" "")))
14286 (set (match_operand:SI 0 "gpc_reg_operand" "")
14287 (plus:SI (match_dup 1)
14288 (const_int -1)))
14289 (clobber (match_scratch:CC 3 ""))
14290 (clobber (match_scratch:SI 4 ""))]
14291 "TARGET_32BIT && reload_completed"
14292 [(parallel [(set (match_dup 3)
14293 (compare:CC (plus:SI (match_dup 1)
14294 (const_int -1))
14295 (const_int 0)))
14296 (set (match_dup 0)
14297 (plus:SI (match_dup 1)
14298 (const_int -1)))])
14299 (set (pc) (if_then_else (match_dup 7)
14300 (match_dup 5)
14301 (match_dup 6)))]
14302 "
14303 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14304 const0_rtx); }")
14306 (define_split
14307 [(set (pc)
14308 (if_then_else (match_operator 2 "comparison_operator"
14309 [(match_operand:SI 1 "gpc_reg_operand" "")
14310 (const_int 1)])
14311 (match_operand 5 "" "")
14312 (match_operand 6 "" "")))
14313 (set (match_operand:SI 0 "nonimmediate_operand" "")
14314 (plus:SI (match_dup 1) (const_int -1)))
14315 (clobber (match_scratch:CC 3 ""))
14316 (clobber (match_scratch:SI 4 ""))]
14317 "TARGET_32BIT && reload_completed
14318 && ! gpc_reg_operand (operands[0], SImode)"
14319 [(parallel [(set (match_dup 3)
14320 (compare:CC (plus:SI (match_dup 1)
14321 (const_int -1))
14322 (const_int 0)))
14323 (set (match_dup 4)
14324 (plus:SI (match_dup 1)
14325 (const_int -1)))])
14326 (set (match_dup 0)
14327 (match_dup 4))
14328 (set (pc) (if_then_else (match_dup 7)
14329 (match_dup 5)
14330 (match_dup 6)))]
14331 "
14332 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14333 const0_rtx); }")
14334 (define_split
14335 [(set (pc)
14336 (if_then_else (match_operator 2 "comparison_operator"
14337 [(match_operand:DI 1 "gpc_reg_operand" "")
14338 (const_int 1)])
14339 (match_operand 5 "" "")
14340 (match_operand 6 "" "")))
14341 (set (match_operand:DI 0 "gpc_reg_operand" "")
14342 (plus:DI (match_dup 1)
14343 (const_int -1)))
14344 (clobber (match_scratch:CC 3 ""))
14345 (clobber (match_scratch:DI 4 ""))]
14346 "TARGET_64BIT && reload_completed"
14347 [(parallel [(set (match_dup 3)
14348 (compare:CC (plus:DI (match_dup 1)
14349 (const_int -1))
14350 (const_int 0)))
14351 (set (match_dup 0)
14352 (plus:DI (match_dup 1)
14353 (const_int -1)))])
14354 (set (pc) (if_then_else (match_dup 7)
14355 (match_dup 5)
14356 (match_dup 6)))]
14357 "
14358 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14359 const0_rtx); }")
14361 (define_split
14362 [(set (pc)
14363 (if_then_else (match_operator 2 "comparison_operator"
14364 [(match_operand:DI 1 "gpc_reg_operand" "")
14365 (const_int 1)])
14366 (match_operand 5 "" "")
14367 (match_operand 6 "" "")))
14368 (set (match_operand:DI 0 "nonimmediate_operand" "")
14369 (plus:DI (match_dup 1) (const_int -1)))
14370 (clobber (match_scratch:CC 3 ""))
14371 (clobber (match_scratch:DI 4 ""))]
14372 "TARGET_64BIT && reload_completed
14373 && ! gpc_reg_operand (operands[0], DImode)"
14374 [(parallel [(set (match_dup 3)
14375 (compare:CC (plus:DI (match_dup 1)
14376 (const_int -1))
14377 (const_int 0)))
14378 (set (match_dup 4)
14379 (plus:DI (match_dup 1)
14380 (const_int -1)))])
14381 (set (match_dup 0)
14382 (match_dup 4))
14383 (set (pc) (if_then_else (match_dup 7)
14384 (match_dup 5)
14385 (match_dup 6)))]
14386 "
14387 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14388 const0_rtx); }")
14389 \f
14390 (define_insn "trap"
14391 [(trap_if (const_int 1) (const_int 0))]
14392 ""
14393 "{t 31,0,0|trap}")
14395 (define_expand "conditional_trap"
14396 [(trap_if (match_operator 0 "trap_comparison_operator"
14397 [(match_dup 2) (match_dup 3)])
14398 (match_operand 1 "const_int_operand" ""))]
14399 ""
14400 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14401 operands[2] = rs6000_compare_op0;
14402 operands[3] = rs6000_compare_op1;")
14404 (define_insn ""
14405 [(trap_if (match_operator 0 "trap_comparison_operator"
14406 [(match_operand:SI 1 "register_operand" "r")
14407 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14408 (const_int 0))]
14409 ""
14410 "{t|tw}%V0%I2 %1,%2")
14412 (define_insn ""
14413 [(trap_if (match_operator 0 "trap_comparison_operator"
14414 [(match_operand:DI 1 "register_operand" "r")
14415 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14416 (const_int 0))]
14417 "TARGET_POWERPC64"
14418 "td%V0%I2 %1,%2")
14419 \f
14420 ;; Insns related to generating the function prologue and epilogue.
14422 (define_expand "prologue"
14423 [(use (const_int 0))]
14424 "TARGET_SCHED_PROLOG"
14425 "
14426 {
14427 rs6000_emit_prologue ();
14428 DONE;
14429 }")
14431 (define_insn "*movesi_from_cr_one"
14432 [(match_parallel 0 "mfcr_operation"
14433 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14434 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14435 (match_operand 3 "immediate_operand" "n")]
14436 UNSPEC_MOVESI_FROM_CR))])]
14437 "TARGET_MFCRF"
14438 "*
14439 {
14440 int mask = 0;
14441 int i;
14442 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14443 {
14444 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14445 operands[4] = GEN_INT (mask);
14446 output_asm_insn (\"mfcr %1,%4\", operands);
14447 }
14448 return \"\";
14449 }"
14450 [(set_attr "type" "mfcrf")])
14452 (define_insn "movesi_from_cr"
14453 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14454 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14455 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14456 UNSPEC_MOVESI_FROM_CR))]
14457 ""
14458 "mfcr %0"
14459 [(set_attr "type" "mfcr")])
14461 (define_insn "*stmw"
14462 [(match_parallel 0 "stmw_operation"
14463 [(set (match_operand:SI 1 "memory_operand" "=m")
14464 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14465 "TARGET_MULTIPLE"
14466 "{stm|stmw} %2,%1")
14468 (define_insn "*save_fpregs_si"
14469 [(match_parallel 0 "any_operand"
14470 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14471 (use (match_operand:SI 2 "call_operand" "s"))
14472 (set (match_operand:DF 3 "memory_operand" "=m")
14473 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14474 "TARGET_32BIT"
14475 "bl %z2"
14476 [(set_attr "type" "branch")
14477 (set_attr "length" "4")])
14479 (define_insn "*save_fpregs_di"
14480 [(match_parallel 0 "any_operand"
14481 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14482 (use (match_operand:DI 2 "call_operand" "s"))
14483 (set (match_operand:DF 3 "memory_operand" "=m")
14484 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14485 "TARGET_64BIT"
14486 "bl %z2"
14487 [(set_attr "type" "branch")
14488 (set_attr "length" "4")])
14490 ; These are to explain that changes to the stack pointer should
14491 ; not be moved over stores to stack memory.
14492 (define_insn "stack_tie"
14493 [(set (match_operand:BLK 0 "memory_operand" "+m")
14494 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14495 ""
14496 ""
14497 [(set_attr "length" "0")])
14500 (define_expand "epilogue"
14501 [(use (const_int 0))]
14502 "TARGET_SCHED_PROLOG"
14503 "
14504 {
14505 rs6000_emit_epilogue (FALSE);
14506 DONE;
14507 }")
14509 ; On some processors, doing the mtcrf one CC register at a time is
14510 ; faster (like on the 604e). On others, doing them all at once is
14511 ; faster; for instance, on the 601 and 750.
14513 (define_expand "movsi_to_cr_one"
14514 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14515 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14516 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14517 ""
14518 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14520 (define_insn "*movsi_to_cr"
14521 [(match_parallel 0 "mtcrf_operation"
14522 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14523 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14524 (match_operand 3 "immediate_operand" "n")]
14525 UNSPEC_MOVESI_TO_CR))])]
14526 ""
14527 "*
14528 {
14529 int mask = 0;
14530 int i;
14531 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14532 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14533 operands[4] = GEN_INT (mask);
14534 return \"mtcrf %4,%2\";
14535 }"
14536 [(set_attr "type" "mtcr")])
14538 (define_insn "*mtcrfsi"
14539 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14540 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14541 (match_operand 2 "immediate_operand" "n")]
14542 UNSPEC_MOVESI_TO_CR))]
14543 "GET_CODE (operands[0]) == REG
14544 && CR_REGNO_P (REGNO (operands[0]))
14545 && GET_CODE (operands[2]) == CONST_INT
14546 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14547 "mtcrf %R0,%1"
14548 [(set_attr "type" "mtcr")])
14550 ; The load-multiple instructions have similar properties.
14551 ; Note that "load_multiple" is a name known to the machine-independent
14552 ; code that actually corresponds to the powerpc load-string.
14554 (define_insn "*lmw"
14555 [(match_parallel 0 "lmw_operation"
14556 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14557 (match_operand:SI 2 "memory_operand" "m"))])]
14558 "TARGET_MULTIPLE"
14559 "{lm|lmw} %1,%2")
14561 (define_insn "*return_internal_si"
14562 [(return)
14563 (use (match_operand:SI 0 "register_operand" "lc"))]
14564 "TARGET_32BIT"
14565 "b%T0"
14566 [(set_attr "type" "jmpreg")])
14568 (define_insn "*return_internal_di"
14569 [(return)
14570 (use (match_operand:DI 0 "register_operand" "lc"))]
14571 "TARGET_64BIT"
14572 "b%T0"
14573 [(set_attr "type" "jmpreg")])
14575 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14576 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14578 (define_insn "*return_and_restore_fpregs_si"
14579 [(match_parallel 0 "any_operand"
14580 [(return)
14581 (use (match_operand:SI 1 "register_operand" "l"))
14582 (use (match_operand:SI 2 "call_operand" "s"))
14583 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14584 (match_operand:DF 4 "memory_operand" "m"))])]
14585 "TARGET_32BIT"
14586 "b %z2")
14588 (define_insn "*return_and_restore_fpregs_di"
14589 [(match_parallel 0 "any_operand"
14590 [(return)
14591 (use (match_operand:DI 1 "register_operand" "l"))
14592 (use (match_operand:DI 2 "call_operand" "s"))
14593 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14594 (match_operand:DF 4 "memory_operand" "m"))])]
14595 "TARGET_64BIT"
14596 "b %z2")
14598 ; This is used in compiling the unwind routines.
14599 (define_expand "eh_return"
14600 [(use (match_operand 0 "general_operand" ""))]
14601 ""
14602 "
14603 {
14604 if (TARGET_32BIT)
14605 emit_insn (gen_eh_set_lr_si (operands[0]));
14606 else
14607 emit_insn (gen_eh_set_lr_di (operands[0]));
14608 DONE;
14609 }")
14611 ; We can't expand this before we know where the link register is stored.
14612 (define_insn "eh_set_lr_si"
14613 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14614 UNSPECV_EH_RR)
14615 (clobber (match_scratch:SI 1 "=&b"))]
14616 "TARGET_32BIT"
14617 "#")
14619 (define_insn "eh_set_lr_di"
14620 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14621 UNSPECV_EH_RR)
14622 (clobber (match_scratch:DI 1 "=&b"))]
14623 "TARGET_64BIT"
14624 "#")
14626 (define_split
14627 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14628 (clobber (match_scratch 1 ""))]
14629 "reload_completed"
14630 [(const_int 0)]
14631 "
14632 {
14633 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14634 DONE;
14635 }")
14637 (define_insn "prefetch"
14638 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14639 (match_operand:SI 1 "const_int_operand" "n")
14640 (match_operand:SI 2 "const_int_operand" "n"))]
14641 "TARGET_POWERPC"
14642 "*
14643 {
14644 if (GET_CODE (operands[0]) == REG)
14645 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14646 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14647 }"
14648 [(set_attr "type" "load")])
14650 (include "altivec.md")
14651 (include "spe.md")