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This commit was manufactured by cvs2svn to create branch
[official-gcc.git] / gcc / config / mips / mips.h
blob598a7f826fc5411741224a2dc89be092fff263aa
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern int target_flags;
30
31 /* MIPS external variables defined in mips.c. */
32
33 /* comparison type */
34 enum cmp_type {
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
40 };
41
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
46
47 enum processor_type {
48 PROCESSOR_DEFAULT,
49 PROCESSOR_4KC,
50 PROCESSOR_5KC,
51 PROCESSOR_20KC,
52 PROCESSOR_M4K,
53 PROCESSOR_R3000,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4300,
61 PROCESSOR_R4600,
62 PROCESSOR_R4650,
63 PROCESSOR_R5000,
64 PROCESSOR_R5400,
65 PROCESSOR_R5500,
66 PROCESSOR_R7000,
67 PROCESSOR_R8000,
68 PROCESSOR_R9000,
69 PROCESSOR_SB1,
70 PROCESSOR_SR71000
71 };
72
73 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
74 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
75 to work on a 64 bit machine. */
76
77 #define ABI_32 0
78 #define ABI_N32 1
79 #define ABI_64 2
80 #define ABI_EABI 3
81 #define ABI_O64 4
82
83 /* Information about one recognized processor. Defined here for the
84 benefit of TARGET_CPU_CPP_BUILTINS. */
85 struct mips_cpu_info {
86 /* The 'canonical' name of the processor as far as GCC is concerned.
87 It's typically a manufacturer's prefix followed by a numerical
88 designation. It should be lower case. */
89 const char *name;
90
91 /* The internal processor number that most closely matches this
92 entry. Several processors can have the same value, if there's no
93 difference between them from GCC's point of view. */
94 enum processor_type cpu;
95
96 /* The ISA level that the processor implements. */
97 int isa;
98 };
99
100 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
101 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
102 extern const char *current_function_file; /* filename current function is in */
103 extern int num_source_filenames; /* current .file # */
104 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
105 extern int sym_lineno; /* sgi next label # for each stmt */
106 extern int set_noreorder; /* # of nested .set noreorder's */
107 extern int set_nomacro; /* # of nested .set nomacro's */
108 extern int set_noat; /* # of nested .set noat's */
109 extern int set_volatile; /* # of nested .set volatile's */
110 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
111 extern int mips_dbx_regno[]; /* Map register # to debug register # */
112 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
113 extern enum cmp_type branch_type; /* what type of branch to use */
114 extern enum processor_type mips_arch; /* which cpu to codegen for */
115 extern enum processor_type mips_tune; /* which cpu to schedule for */
116 extern int mips_isa; /* architectural level */
117 extern int mips_abi; /* which ABI to use */
118 extern int mips16_hard_float; /* mips16 without -msoft-float */
119 extern int mips_entry; /* generate entry/exit for mips16 */
120 extern const char *mips_arch_string; /* for -march=<xxx> */
121 extern const char *mips_tune_string; /* for -mtune=<xxx> */
122 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
123 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
124 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
125 extern int mips_string_length; /* length of strings for mips16 */
126 extern const struct mips_cpu_info mips_cpu_info_table[];
127 extern const struct mips_cpu_info *mips_arch_info;
128 extern const struct mips_cpu_info *mips_tune_info;
129
130 /* Macros to silence warnings about numbers being signed in traditional
131 C and unsigned in ISO C when compiled on 32-bit hosts. */
132
133 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
134 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
135 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
136
137 \f
138 /* Run-time compilation parameters selecting different hardware subsets. */
139
140 /* Macros used in the machine description to test the flags. */
141
142 /* Bits for real switches */
143 #define MASK_INT64 0x00000001 /* ints are 64 bits */
144 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
145 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
146 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
147 multiply-add operations. */
148 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
149 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
150 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
151 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
152 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
153 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
154 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
155 #define MASK_XGOT 0x00000800 /* emit big-got PIC */
156 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
157 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
158 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
159 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
160 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
161 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
162 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
163 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
164 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
165 #define MASK_NO_CHECK_ZERO_DIV \
166 0x00200000 /* divide by zero checking */
167 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
168 instructions. */
169 #define MASK_UNINIT_CONST_IN_RODATA \
170 0x00800000 /* Store uninitialized
171 consts in rodata */
172 #define MASK_FIX_SB1 0x01000000 /* Work around SB-1 errata. */
173
174 /* Debug switches, not documented */
175 #define MASK_DEBUG 0 /* unused */
176 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
177 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
178 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
179 #define MASK_DEBUG_D 0 /* don't do define_split's */
180 #define MASK_DEBUG_E 0 /* function_arg debug */
181 #define MASK_DEBUG_F 0 /* ??? */
182 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
183 #define MASK_DEBUG_I 0 /* unused */
184
185 /* Dummy switches used only in specs */
186 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
187
188 /* r4000 64 bit sizes */
189 #define TARGET_INT64 (target_flags & MASK_INT64)
190 #define TARGET_LONG64 (target_flags & MASK_LONG64)
191 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
192 #define TARGET_64BIT (target_flags & MASK_64BIT)
193
194 /* Mips vs. GNU linker */
195 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
196
197 /* Mips vs. GNU assembler */
198 #define TARGET_GAS (target_flags & MASK_GAS)
199 #define TARGET_MIPS_AS (!TARGET_GAS)
200
201 /* Debug Modes */
202 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
203 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
204 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
205 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
206 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
207 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
208 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
209 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
210 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
211
212 /* Reg. Naming in .s ($21 vs. $a0) */
213 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
214
215 /* call memcpy instead of inline code */
216 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
217
218 /* .abicalls, etc from Pyramid V.4 */
219 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
220 #define TARGET_XGOT (target_flags & MASK_XGOT)
221
222 /* software floating point */
223 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
224 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
225
226 /* always call through a register */
227 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
228
229 /* generate embedded PIC code;
230 requires gas. */
231 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
232
233 /* for embedded systems, optimize for
234 reduced RAM space instead of for
235 fastest code. */
236 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
237
238 /* always store uninitialized const
239 variables in rodata, requires
240 TARGET_EMBEDDED_DATA. */
241 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
242
243 /* generate big endian code. */
244 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
245
246 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
247 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
248
249 #define TARGET_MAD (target_flags & MASK_MAD)
250
251 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
252
253 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
254
255 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
256
257 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
258
259 #define TARGET_FIX_SB1 (target_flags & MASK_FIX_SB1)
260
261 /* True if we should use NewABI-style relocation operators for
262 symbolic addresses. This is never true for mips16 code,
263 which has its own conventions. */
264
265 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
266
267
268 /* True if the call patterns should be split into a jalr followed by
269 an instruction to restore $gp. This is only ever true for SVR4 PIC,
270 in which $gp is call-clobbered. It is only safe to split the load
271 from the call when every use of $gp is explicit. */
272
273 #define TARGET_SPLIT_CALLS \
274 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
275
276 /* True if we can optimize sibling calls. For simplicity, we only
277 handle cases in which call_insn_operand will reject invalid
278 sibcall addresses. There are two cases in which this isn't true:
279
280 - TARGET_MIPS16. call_insn_operand accepts constant addresses
281 but there is no direct jump instruction. It isn't worth
282 using sibling calls in this case anyway; they would usually
283 be longer than normal calls.
284
285 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
286 accepts global constants, but "jr $25" is the only allowed
287 sibcall. */
288
289 #define TARGET_SIBCALLS \
290 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
291
292 /* True if .gpword or .gpdword should be used for switch tables.
293 There are some problems with using these directives with the
294 native IRIX tools:
295
296 - It has been reported that some versions of the native n32
297 assembler mishandle .gpword, complaining that symbols are
298 global when they are in fact local.
299
300 - The native assemblers don't understand .gpdword.
301
302 - Although GAS does understand .gpdword, the native linker
303 mishandles the relocations GAS generates (R_MIPS_GPREL32
304 followed by R_MIPS_64).
305
306 We therefore disable GP-relative switch tables for n32 and n64
307 on IRIX targets. */
308 #define TARGET_GPWORD (TARGET_ABICALLS && !(TARGET_NEWABI && TARGET_IRIX))
309
310 /* Generate mips16 code */
311 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
312
313 /* Generic ISA defines. */
314 #define ISA_MIPS1 (mips_isa == 1)
315 #define ISA_MIPS2 (mips_isa == 2)
316 #define ISA_MIPS3 (mips_isa == 3)
317 #define ISA_MIPS4 (mips_isa == 4)
318 #define ISA_MIPS32 (mips_isa == 32)
319 #define ISA_MIPS32R2 (mips_isa == 33)
320 #define ISA_MIPS64 (mips_isa == 64)
321
322 /* Architecture target defines. */
323 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
324 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
325 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
326 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
327 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
328 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
329 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
330 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
331 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
332 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
333 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
334 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
335 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
336
337 /* Scheduling target defines. */
338 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
339 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
340 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
341 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
342 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
343 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
344 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
345 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
346 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
347 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
348 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
349
350 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
351
352 /* IRIX specific stuff. */
353 #define TARGET_IRIX 0
354 #define TARGET_IRIX5 0
355 #define TARGET_SGI_O32_AS (TARGET_IRIX && mips_abi == ABI_32 && !TARGET_GAS)
356
357 /* Define preprocessor macros for the -march and -mtune options.
358 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
359 processor. If INFO's canonical name is "foo", define PREFIX to
360 be "foo", and define an additional macro PREFIX_FOO. */
361 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
362 do \
363 { \
364 char *macro, *p; \
365 \
366 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
367 for (p = macro; *p != 0; p++) \
368 *p = TOUPPER (*p); \
369 \
370 builtin_define (macro); \
371 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
372 free (macro); \
373 } \
374 while (0)
375
376 /* Target CPU builtins. */
377 #define TARGET_CPU_CPP_BUILTINS() \
378 do \
379 { \
380 builtin_assert ("cpu=mips"); \
381 builtin_define ("__mips__"); \
382 builtin_define ("_mips"); \
383 \
384 /* We do this here because __mips is defined below \
385 and so we can't use builtin_define_std. */ \
386 if (!flag_iso) \
387 builtin_define ("mips"); \
388 \
389 /* Treat _R3000 and _R4000 like register-size defines, \
390 which is how they've historically been used. */ \
391 if (TARGET_64BIT) \
392 { \
393 builtin_define ("__mips64"); \
394 builtin_define_std ("R4000"); \
395 builtin_define ("_R4000"); \
396 } \
397 else \
398 { \
399 builtin_define_std ("R3000"); \
400 builtin_define ("_R3000"); \
401 } \
402 if (TARGET_FLOAT64) \
403 builtin_define ("__mips_fpr=64"); \
404 else \
405 builtin_define ("__mips_fpr=32"); \
406 \
407 if (TARGET_MIPS16) \
408 builtin_define ("__mips16"); \
409 \
410 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
411 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
412 \
413 if (ISA_MIPS1) \
414 { \
415 builtin_define ("__mips=1"); \
416 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
417 } \
418 else if (ISA_MIPS2) \
419 { \
420 builtin_define ("__mips=2"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
422 } \
423 else if (ISA_MIPS3) \
424 { \
425 builtin_define ("__mips=3"); \
426 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
427 } \
428 else if (ISA_MIPS4) \
429 { \
430 builtin_define ("__mips=4"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
432 } \
433 else if (ISA_MIPS32) \
434 { \
435 builtin_define ("__mips=32"); \
436 builtin_define ("__mips_isa_rev=1"); \
437 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
438 } \
439 else if (ISA_MIPS32R2) \
440 { \
441 builtin_define ("__mips=32"); \
442 builtin_define ("__mips_isa_rev=2"); \
443 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
444 } \
445 else if (ISA_MIPS64) \
446 { \
447 builtin_define ("__mips=64"); \
448 builtin_define ("__mips_isa_rev=1"); \
449 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
450 } \
451 \
452 if (TARGET_HARD_FLOAT) \
453 builtin_define ("__mips_hard_float"); \
454 else if (TARGET_SOFT_FLOAT) \
455 builtin_define ("__mips_soft_float"); \
456 \
457 if (TARGET_SINGLE_FLOAT) \
458 builtin_define ("__mips_single_float"); \
459 \
460 if (TARGET_BIG_ENDIAN) \
461 { \
462 builtin_define_std ("MIPSEB"); \
463 builtin_define ("_MIPSEB"); \
464 } \
465 else \
466 { \
467 builtin_define_std ("MIPSEL"); \
468 builtin_define ("_MIPSEL"); \
469 } \
470 \
471 /* Macros dependent on the C dialect. */ \
472 if (preprocessing_asm_p ()) \
473 { \
474 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
475 builtin_define ("_LANGUAGE_ASSEMBLY"); \
476 } \
477 else if (c_dialect_cxx ()) \
478 { \
479 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
480 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
481 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
482 } \
483 else \
484 { \
485 builtin_define_std ("LANGUAGE_C"); \
486 builtin_define ("_LANGUAGE_C"); \
487 } \
488 if (c_dialect_objc ()) \
489 { \
490 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
491 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
492 /* Bizarre, but needed at least for Irix. */ \
493 builtin_define_std ("LANGUAGE_C"); \
494 builtin_define ("_LANGUAGE_C"); \
495 } \
496 \
497 if (mips_abi == ABI_EABI) \
498 builtin_define ("__mips_eabi"); \
499 \
500 } while (0)
501
502
503
504 /* Macro to define tables used to set the flags.
505 This is a list in braces of pairs in braces,
506 each pair being { "NAME", VALUE }
507 where VALUE is the bits to set or minus the bits to clear.
508 An empty string NAME is used to identify the default VALUE. */
509
510 #define TARGET_SWITCHES \
511 { \
512 SUBTARGET_TARGET_SWITCHES \
513 {"int64", MASK_INT64 | MASK_LONG64, \
514 N_("Use 64-bit int type")}, \
515 {"long64", MASK_LONG64, \
516 N_("Use 64-bit long type")}, \
517 {"long32", -(MASK_LONG64 | MASK_INT64), \
518 N_("Use 32-bit long type")}, \
519 {"split-addresses", MASK_SPLIT_ADDR, \
520 N_("Optimize lui/addiu address loads")}, \
521 {"no-split-addresses", -MASK_SPLIT_ADDR, \
522 N_("Don't optimize lui/addiu address loads")}, \
523 {"mips-as", -MASK_GAS, \
524 N_("Use MIPS as")}, \
525 {"gas", MASK_GAS, \
526 N_("Use GNU as")}, \
527 {"rnames", MASK_NAME_REGS, \
528 N_("Use symbolic register names")}, \
529 {"no-rnames", -MASK_NAME_REGS, \
530 N_("Don't use symbolic register names")}, \
531 {"gpOPT", 0, \
532 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
533 {"gpopt", 0, \
534 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
535 {"no-gpOPT", 0, \
536 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
537 {"no-gpopt", 0, \
538 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
539 {"stats", 0, \
540 N_("Output compiler statistics (now ignored)")}, \
541 {"no-stats", 0, \
542 N_("Don't output compiler statistics")}, \
543 {"memcpy", MASK_MEMCPY, \
544 N_("Don't optimize block moves")}, \
545 {"no-memcpy", -MASK_MEMCPY, \
546 N_("Optimize block moves")}, \
547 {"mips-tfile", MASK_MIPS_TFILE, \
548 N_("Use mips-tfile asm postpass")}, \
549 {"no-mips-tfile", -MASK_MIPS_TFILE, \
550 N_("Don't use mips-tfile asm postpass")}, \
551 {"soft-float", MASK_SOFT_FLOAT, \
552 N_("Use software floating point")}, \
553 {"hard-float", -MASK_SOFT_FLOAT, \
554 N_("Use hardware floating point")}, \
555 {"fp64", MASK_FLOAT64, \
556 N_("Use 64-bit FP registers")}, \
557 {"fp32", -MASK_FLOAT64, \
558 N_("Use 32-bit FP registers")}, \
559 {"gp64", MASK_64BIT, \
560 N_("Use 64-bit general registers")}, \
561 {"gp32", -MASK_64BIT, \
562 N_("Use 32-bit general registers")}, \
563 {"abicalls", MASK_ABICALLS, \
564 N_("Use Irix PIC")}, \
565 {"no-abicalls", -MASK_ABICALLS, \
566 N_("Don't use Irix PIC")}, \
567 {"long-calls", MASK_LONG_CALLS, \
568 N_("Use indirect calls")}, \
569 {"no-long-calls", -MASK_LONG_CALLS, \
570 N_("Don't use indirect calls")}, \
571 {"embedded-pic", MASK_EMBEDDED_PIC, \
572 N_("Use embedded PIC")}, \
573 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
574 N_("Don't use embedded PIC")}, \
575 {"embedded-data", MASK_EMBEDDED_DATA, \
576 N_("Use ROM instead of RAM")}, \
577 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
578 N_("Don't use ROM instead of RAM")}, \
579 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
580 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
581 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
582 N_("Don't put uninitialized constants in ROM")}, \
583 {"eb", MASK_BIG_ENDIAN, \
584 N_("Use big-endian byte order")}, \
585 {"el", -MASK_BIG_ENDIAN, \
586 N_("Use little-endian byte order")}, \
587 {"single-float", MASK_SINGLE_FLOAT, \
588 N_("Use single (32-bit) FP only")}, \
589 {"double-float", -MASK_SINGLE_FLOAT, \
590 N_("Don't use single (32-bit) FP only")}, \
591 {"mad", MASK_MAD, \
592 N_("Use multiply accumulate")}, \
593 {"no-mad", -MASK_MAD, \
594 N_("Don't use multiply accumulate")}, \
595 {"no-fused-madd", MASK_NO_FUSED_MADD, \
596 N_("Don't generate fused multiply/add instructions")}, \
597 {"fused-madd", -MASK_NO_FUSED_MADD, \
598 N_("Generate fused multiply/add instructions")}, \
599 {"fix4300", MASK_4300_MUL_FIX, \
600 N_("Work around early 4300 hardware bug")}, \
601 {"no-fix4300", -MASK_4300_MUL_FIX, \
602 N_("Don't work around early 4300 hardware bug")}, \
603 {"fix-sb1", MASK_FIX_SB1, \
604 N_("Work around errata for early SB-1 revision 2 cores")}, \
605 {"no-fix-sb1", -MASK_FIX_SB1, \
606 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
607 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
608 N_("Trap on integer divide by zero")}, \
609 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
610 N_("Don't trap on integer divide by zero")}, \
611 { "branch-likely", MASK_BRANCHLIKELY, \
612 N_("Use Branch Likely instructions, overriding default for arch")}, \
613 { "no-branch-likely", -MASK_BRANCHLIKELY, \
614 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
615 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
616 N_("Use NewABI-style %reloc() assembly operators")}, \
617 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
618 N_("Use assembler macros instead of relocation operators")}, \
619 {"ips16", MASK_MIPS16, \
620 N_("Generate mips16 code") }, \
621 {"no-mips16", -MASK_MIPS16, \
622 N_("Generate normal-mode code") }, \
623 {"xgot", MASK_XGOT, \
624 N_("Lift restrictions on GOT size") }, \
625 {"no-xgot", -MASK_XGOT, \
626 N_("Do not lift restrictions on GOT size") }, \
627 {"debug", MASK_DEBUG, \
628 NULL}, \
629 {"debuga", MASK_DEBUG_A, \
630 NULL}, \
631 {"debugb", MASK_DEBUG_B, \
632 NULL}, \
633 {"debugc", MASK_DEBUG_C, \
634 NULL}, \
635 {"debugd", MASK_DEBUG_D, \
636 NULL}, \
637 {"debuge", MASK_DEBUG_E, \
638 NULL}, \
639 {"debugf", MASK_DEBUG_F, \
640 NULL}, \
641 {"debugg", MASK_DEBUG_G, \
642 NULL}, \
643 {"debugi", MASK_DEBUG_I, \
644 NULL}, \
645 {"", (TARGET_DEFAULT \
646 | TARGET_CPU_DEFAULT \
647 | TARGET_ENDIAN_DEFAULT), \
648 NULL}, \
649 }
650
651 /* Default target_flags if no switches are specified */
652
653 #ifndef TARGET_DEFAULT
654 #define TARGET_DEFAULT 0
655 #endif
656
657 #ifndef TARGET_CPU_DEFAULT
658 #define TARGET_CPU_DEFAULT 0
659 #endif
660
661 #ifndef TARGET_ENDIAN_DEFAULT
662 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
663 #endif
664
665 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
666 #ifndef MIPS_ISA_DEFAULT
667 #ifndef MIPS_CPU_STRING_DEFAULT
668 #define MIPS_CPU_STRING_DEFAULT "from-abi"
669 #endif
670 #endif
671
672 #ifdef IN_LIBGCC2
673 #undef TARGET_64BIT
674 /* Make this compile time constant for libgcc2 */
675 #ifdef __mips64
676 #define TARGET_64BIT 1
677 #else
678 #define TARGET_64BIT 0
679 #endif
680 #endif /* IN_LIBGCC2 */
681
682 #ifndef MULTILIB_ENDIAN_DEFAULT
683 #if TARGET_ENDIAN_DEFAULT == 0
684 #define MULTILIB_ENDIAN_DEFAULT "EL"
685 #else
686 #define MULTILIB_ENDIAN_DEFAULT "EB"
687 #endif
688 #endif
689
690 #ifndef MULTILIB_ISA_DEFAULT
691 # if MIPS_ISA_DEFAULT == 1
692 # define MULTILIB_ISA_DEFAULT "mips1"
693 # else
694 # if MIPS_ISA_DEFAULT == 2
695 # define MULTILIB_ISA_DEFAULT "mips2"
696 # else
697 # if MIPS_ISA_DEFAULT == 3
698 # define MULTILIB_ISA_DEFAULT "mips3"
699 # else
700 # if MIPS_ISA_DEFAULT == 4
701 # define MULTILIB_ISA_DEFAULT "mips4"
702 # else
703 # if MIPS_ISA_DEFAULT == 32
704 # define MULTILIB_ISA_DEFAULT "mips32"
705 # else
706 # if MIPS_ISA_DEFAULT == 33
707 # define MULTILIB_ISA_DEFAULT "mips32r2"
708 # else
709 # if MIPS_ISA_DEFAULT == 64
710 # define MULTILIB_ISA_DEFAULT "mips64"
711 # else
712 # define MULTILIB_ISA_DEFAULT "mips1"
713 # endif
714 # endif
715 # endif
716 # endif
717 # endif
718 # endif
719 # endif
720 #endif
721
722 #ifndef MULTILIB_DEFAULTS
723 #define MULTILIB_DEFAULTS \
724 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
725 #endif
726
727 /* We must pass -EL to the linker by default for little endian embedded
728 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
729 linker will default to using big-endian output files. The OUTPUT_FORMAT
730 line must be in the linker script, otherwise -EB/-EL will not work. */
731
732 #ifndef ENDIAN_SPEC
733 #if TARGET_ENDIAN_DEFAULT == 0
734 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
735 #else
736 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
737 #endif
738 #endif
739
740 #define TARGET_OPTIONS \
741 { \
742 SUBTARGET_TARGET_OPTIONS \
743 { "tune=", &mips_tune_string, \
744 N_("Specify CPU for scheduling purposes"), 0}, \
745 { "arch=", &mips_arch_string, \
746 N_("Specify CPU for code generation purposes"), 0}, \
747 { "abi=", &mips_abi_string, \
748 N_("Specify an ABI"), 0}, \
749 { "ips", &mips_isa_string, \
750 N_("Specify a Standard MIPS ISA"), 0}, \
751 { "no-flush-func", &mips_cache_flush_func, \
752 N_("Don't call any cache flush functions"), 0}, \
753 { "flush-func=", &mips_cache_flush_func, \
754 N_("Specify cache flush function"), 0}, \
755 }
756
757 /* This is meant to be redefined in the host dependent files. */
758 #define SUBTARGET_TARGET_OPTIONS
759
760 /* Support for a compile-time default CPU, et cetera. The rules are:
761 --with-arch is ignored if -march is specified or a -mips is specified
762 (other than -mips16).
763 --with-tune is ignored if -mtune is specified.
764 --with-abi is ignored if -mabi is specified.
765 --with-float is ignored if -mhard-float or -msoft-float are
766 specified. */
767 #define OPTION_DEFAULT_SPECS \
768 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
769 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
770 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
771 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
772
773
774 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
775 && !TARGET_SR71K \
776 && !TARGET_MIPS16)
777
778 /* Generate three-operand multiply instructions for SImode. */
779 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
780 || TARGET_MIPS5400 \
781 || TARGET_MIPS5500 \
782 || TARGET_MIPS7000 \
783 || TARGET_MIPS9000 \
784 || ISA_MIPS32 \
785 || ISA_MIPS32R2 \
786 || ISA_MIPS64) \
787 && !TARGET_MIPS16)
788
789 /* Generate three-operand multiply instructions for DImode. */
790 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
791 && !TARGET_MIPS16)
792
793 /* Macros to decide whether certain features are available or not,
794 depending on the instruction set architecture level. */
795
796 #define HAVE_SQRT_P() (!ISA_MIPS1)
797
798 /* True if the ABI can only work with 64-bit integer registers. We
799 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
800 otherwise floating-point registers must also be 64-bit. */
801 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
802 || mips_abi == ABI_O64 \
803 || mips_abi == ABI_N32)
804
805 /* Likewise for 32-bit regs. */
806 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
807
808 /* True if symbols are 64 bits wide. At present, n64 is the only
809 ABI for which this is true. */
810 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
811
812 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
813 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
814 || ISA_MIPS4 \
815 || ISA_MIPS64)
816
817 /* ISA has branch likely instructions (eg. mips2). */
818 /* Disable branchlikely for tx39 until compare rewrite. They haven't
819 been generated up to this point. */
820 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
821 && !TARGET_MIPS5500)
822
823 /* ISA has the conditional move instructions introduced in mips4. */
824 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
825 || ISA_MIPS32 \
826 || ISA_MIPS32R2 \
827 || ISA_MIPS64) \
828 && !TARGET_MIPS5500 \
829 && !TARGET_MIPS16)
830
831 /* ISA has just the integer condition move instructions (movn,movz) */
832 #define ISA_HAS_INT_CONDMOVE 0
833
834 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
835 branch on CC, and move (both FP and non-FP) on CC. */
836 #define ISA_HAS_8CC (ISA_MIPS4 \
837 || ISA_MIPS32 \
838 || ISA_MIPS32R2 \
839 || ISA_MIPS64)
840
841 /* This is a catch all for other mips4 instructions: indexed load, the
842 FP madd and msub instructions, and the FP recip and recip sqrt
843 instructions. */
844 #define ISA_HAS_FP4 ((ISA_MIPS4 \
845 || ISA_MIPS64) \
846 && !TARGET_MIPS16)
847
848 /* ISA has conditional trap instructions. */
849 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
850 && !TARGET_MIPS16)
851
852 /* ISA has integer multiply-accumulate instructions, madd and msub. */
853 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
854 || ISA_MIPS32R2 \
855 || ISA_MIPS64 \
856 ) && !TARGET_MIPS16)
857
858 /* ISA has floating-point nmadd and nmsub instructions. */
859 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
860 || ISA_MIPS64) \
861 && (!TARGET_MIPS5400 || TARGET_MAD) \
862 && ! TARGET_MIPS16)
863
864 /* ISA has count leading zeroes/ones instruction (not implemented). */
865 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
866 || ISA_MIPS32R2 \
867 || ISA_MIPS64 \
868 ) && !TARGET_MIPS16)
869
870 /* ISA has double-word count leading zeroes/ones instruction (not
871 implemented). */
872 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
873 && !TARGET_MIPS16)
874
875 /* ISA has three operand multiply instructions that put
876 the high part in an accumulator: mulhi or mulhiu. */
877 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
878 || TARGET_MIPS5500 \
879 || TARGET_SR71K \
880 )
881
882 /* ISA has three operand multiply instructions that
883 negates the result and puts the result in an accumulator. */
884 #define ISA_HAS_MULS (TARGET_MIPS5400 \
885 || TARGET_MIPS5500 \
886 || TARGET_SR71K \
887 )
888
889 /* ISA has three operand multiply instructions that subtracts the
890 result from a 4th operand and puts the result in an accumulator. */
891 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
892 || TARGET_MIPS5500 \
893 || TARGET_SR71K \
894 )
895 /* ISA has three operand multiply instructions that the result
896 from a 4th operand and puts the result in an accumulator. */
897 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
898 || TARGET_MIPS5400 \
899 || TARGET_MIPS5500 \
900 || TARGET_SR71K \
901 )
902
903 /* ISA has 32-bit rotate right instruction. */
904 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
905 && (ISA_MIPS32R2 \
906 || TARGET_MIPS5400 \
907 || TARGET_MIPS5500 \
908 || TARGET_SR71K \
909 ))
910
911 /* ISA has 64-bit rotate right instruction. */
912 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
913 && !TARGET_MIPS16 \
914 && (TARGET_MIPS5400 \
915 || TARGET_MIPS5500 \
916 || TARGET_SR71K \
917 ))
918
919 /* ISA has data prefetch instructions. This controls use of 'pref'. */
920 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
921 || ISA_MIPS32 \
922 || ISA_MIPS32R2 \
923 || ISA_MIPS64) \
924 && !TARGET_MIPS16)
925
926 /* ISA has data indexed prefetch instructions. This controls use of
927 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
928 (prefx is a cop1x instruction, so can only be used if FP is
929 enabled.) */
930 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
931 || ISA_MIPS64) \
932 && !TARGET_MIPS16)
933
934 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
935 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
936 also requires TARGET_DOUBLE_FLOAT. */
937 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
938
939 /* ISA includes the MIPS32r2 seb and seh instructions. */
940 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
941 && (ISA_MIPS32R2 \
942 ))
943
944 /* True if the result of a load is not available to the next instruction.
945 A nop will then be needed between instructions like "lw $4,..."
946 and "addiu $4,$4,1". */
947 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
948 && !TARGET_MIPS3900 \
949 && !TARGET_MIPS16)
950
951 /* Likewise mtc1 and mfc1. */
952 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
953
954 /* Likewise floating-point comparisons. */
955 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
956
957 /* True if mflo and mfhi can be immediately followed by instructions
958 which write to the HI and LO registers. Most targets require a
959 two-instruction gap. */
960 #define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
961 \f
962 /* Add -G xx support. */
963
964 #undef SWITCH_TAKES_ARG
965 #define SWITCH_TAKES_ARG(CHAR) \
966 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
967
968 #define OVERRIDE_OPTIONS override_options ()
969
970 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
971
972 /* Show we can debug even without a frame pointer. */
973 #define CAN_DEBUG_WITHOUT_FP
974 \f
975 /* Tell collect what flags to pass to nm. */
976 #ifndef NM_FLAGS
977 #define NM_FLAGS "-Bn"
978 #endif
979
980 \f
981 /* Assembler specs. */
982
983 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
984 than gas. */
985
986 #define MIPS_AS_ASM_SPEC "\
987 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
988 %{pipe: %e-pipe is not supported} \
989 %{K} %(subtarget_mips_as_asm_spec)"
990
991 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
992 rather than gas. It may be overridden by subtargets. */
993
994 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
995 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
996 #endif
997
998 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
999 assembler. */
1000
1001 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1002
1003 #define SUBTARGET_TARGET_SWITCHES
1004
1005 #ifndef MIPS_ABI_DEFAULT
1006 #define MIPS_ABI_DEFAULT ABI_32
1007 #endif
1008
1009 /* Use the most portable ABI flag for the ASM specs. */
1010
1011 #if MIPS_ABI_DEFAULT == ABI_32
1012 #define MULTILIB_ABI_DEFAULT "mabi=32"
1013 #define ASM_ABI_DEFAULT_SPEC "-32"
1014 #endif
1015
1016 #if MIPS_ABI_DEFAULT == ABI_O64
1017 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1018 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1019 #endif
1020
1021 #if MIPS_ABI_DEFAULT == ABI_N32
1022 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1023 #define ASM_ABI_DEFAULT_SPEC "-n32"
1024 #endif
1025
1026 #if MIPS_ABI_DEFAULT == ABI_64
1027 #define MULTILIB_ABI_DEFAULT "mabi=64"
1028 #define ASM_ABI_DEFAULT_SPEC "-64"
1029 #endif
1030
1031 #if MIPS_ABI_DEFAULT == ABI_EABI
1032 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1033 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1034 #endif
1035
1036 /* Only ELF targets can switch the ABI. */
1037 #ifndef OBJECT_FORMAT_ELF
1038 #undef ASM_ABI_DEFAULT_SPEC
1039 #define ASM_ABI_DEFAULT_SPEC ""
1040 #endif
1041
1042 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1043 GAS_ASM_SPEC as the default, depending upon the value of
1044 TARGET_DEFAULT. */
1045
1046 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1047 /* GAS */
1048
1049 #define TARGET_ASM_SPEC "\
1050 %{mmips-as: %(mips_as_asm_spec)} \
1051 %{!mmips-as: %(gas_asm_spec)}"
1052
1053 #else /* not GAS */
1054
1055 #define TARGET_ASM_SPEC "\
1056 %{!mgas: %(mips_as_asm_spec)} \
1057 %{mgas: %(gas_asm_spec)}"
1058
1059 #endif /* not GAS */
1060
1061 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1062 to the assembler. It may be overridden by subtargets. */
1063 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1064 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1065 %{noasmopt:-O0} \
1066 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1067 #endif
1068
1069 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1070 the assembler. It may be overridden by subtargets. */
1071 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1072 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1073 %{g} %{g0} %{g1} %{g2} %{g3} \
1074 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1075 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1076 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1077 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1078 %(mdebug_asm_spec)"
1079 #endif
1080
1081 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1082 debugging info. */
1083 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1084 /* GAS */
1085 #define MDEBUG_ASM_SPEC "%{gcoff*:-mdebug} \
1086 %{!gcoff*:-no-mdebug}"
1087 #else /* not GAS */
1088 #define MDEBUG_ASM_SPEC ""
1089 #endif /* not GAS */
1090
1091 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1092 overridden by subtargets. */
1093
1094 #ifndef SUBTARGET_ASM_SPEC
1095 #define SUBTARGET_ASM_SPEC ""
1096 #endif
1097
1098 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1099 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1100 whether we're using GAS. These options can only be used properly
1101 with GAS, and it is better to get an error from a non-GAS assembler
1102 than to silently generate bad code. */
1103
1104 #undef ASM_SPEC
1105 #define ASM_SPEC "\
1106 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1107 %{mips32} %{mips32r2} %{mips64} \
1108 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1109 %(subtarget_asm_optimizing_spec) \
1110 %(subtarget_asm_debugging_spec) \
1111 %{membedded-pic} \
1112 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1113 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1114 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1115 %(target_asm_spec) \
1116 %(subtarget_asm_spec)"
1117
1118 /* Extra switches sometimes passed to the linker. */
1119 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1120 will interpret it as a -b option. */
1121
1122 #ifndef LINK_SPEC
1123 #define LINK_SPEC "\
1124 %(endian_spec) \
1125 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1126 %{bestGnum} %{shared} %{non_shared}"
1127 #endif /* LINK_SPEC defined */
1128
1129
1130 /* Specs for the compiler proper */
1131
1132 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1133 overridden by subtargets. */
1134 #ifndef SUBTARGET_CC1_SPEC
1135 #define SUBTARGET_CC1_SPEC ""
1136 #endif
1137
1138 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1139
1140 #ifndef CC1_SPEC
1141 #define CC1_SPEC "\
1142 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1143 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1144 %{save-temps: } \
1145 %(subtarget_cc1_spec)"
1146 #endif
1147
1148 /* Preprocessor specs. */
1149
1150 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1151 overridden by subtargets. */
1152 #ifndef SUBTARGET_CPP_SPEC
1153 #define SUBTARGET_CPP_SPEC ""
1154 #endif
1155
1156 #define CPP_SPEC "%(subtarget_cpp_spec)"
1157
1158 /* This macro defines names of additional specifications to put in the specs
1159 that can be used in various specifications like CC1_SPEC. Its definition
1160 is an initializer with a subgrouping for each command option.
1161
1162 Each subgrouping contains a string constant, that defines the
1163 specification name, and a string constant that used by the GCC driver
1164 program.
1165
1166 Do not define this macro if it does not need to do anything. */
1167
1168 #define EXTRA_SPECS \
1169 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1170 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1171 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1172 { "gas_asm_spec", GAS_ASM_SPEC }, \
1173 { "target_asm_spec", TARGET_ASM_SPEC }, \
1174 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1175 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1176 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1177 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1178 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1179 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1180 { "endian_spec", ENDIAN_SPEC }, \
1181 SUBTARGET_EXTRA_SPECS
1182
1183 #ifndef SUBTARGET_EXTRA_SPECS
1184 #define SUBTARGET_EXTRA_SPECS
1185 #endif
1186
1187 /* If defined, this macro is an additional prefix to try after
1188 `STANDARD_EXEC_PREFIX'. */
1189
1190 #ifndef MD_EXEC_PREFIX
1191 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1192 #endif
1193
1194 #ifndef MD_STARTFILE_PREFIX
1195 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1196 #endif
1197
1198 \f
1199 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1200 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1201 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1202
1203 #ifndef PREFERRED_DEBUGGING_TYPE
1204 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1205 #endif
1206
1207 /* By default, turn on GDB extensions. */
1208 #define DEFAULT_GDB_EXTENSIONS 1
1209
1210 /* If we are passing smuggling stabs through the MIPS ECOFF object
1211 format, put a comment in front of the .stab<x> operation so
1212 that the MIPS assembler does not choke. The mips-tfile program
1213 will correctly put the stab into the object file. */
1214
1215 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1216 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1217 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1218
1219 /* Local compiler-generated symbols must have a prefix that the assembler
1220 understands. By default, this is $, although some targets (e.g.,
1221 NetBSD-ELF) need to override this. */
1222
1223 #ifndef LOCAL_LABEL_PREFIX
1224 #define LOCAL_LABEL_PREFIX "$"
1225 #endif
1226
1227 /* By default on the mips, external symbols do not have an underscore
1228 prepended, but some targets (e.g., NetBSD) require this. */
1229
1230 #ifndef USER_LABEL_PREFIX
1231 #define USER_LABEL_PREFIX ""
1232 #endif
1233
1234 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1235 since the length can run past this up to a continuation point. */
1236 #undef DBX_CONTIN_LENGTH
1237 #define DBX_CONTIN_LENGTH 1500
1238
1239 /* How to renumber registers for dbx and gdb. */
1240 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1241
1242 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1243 #define DWARF_FRAME_REGNUM(REG) (REG)
1244
1245 /* The DWARF 2 CFA column which tracks the return address. */
1246 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1247
1248 /* The DWARF 2 CFA column which tracks the return address from a
1249 signal handler context. */
1250 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1251
1252 /* Before the prologue, RA lives in r31. */
1253 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1254
1255 /* Describe how we implement __builtin_eh_return. */
1256 #define EH_RETURN_DATA_REGNO(N) \
1257 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1258
1259 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1260
1261 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1262 The default for this in 64-bit mode is 8, which causes problems with
1263 SFmode register saves. */
1264 #define DWARF_CIE_DATA_ALIGNMENT 4
1265
1266 /* Correct the offset of automatic variables and arguments. Note that
1267 the MIPS debug format wants all automatic variables and arguments
1268 to be in terms of the virtual frame pointer (stack pointer before
1269 any adjustment in the function), while the MIPS 3.0 linker wants
1270 the frame pointer to be the stack pointer after the initial
1271 adjustment. */
1272
1273 #define DEBUGGER_AUTO_OFFSET(X) \
1274 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1275 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1276 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1277 \f
1278 /* Target machine storage layout */
1279
1280 #define BITS_BIG_ENDIAN 0
1281 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1282 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1283
1284 /* Define this to set the endianness to use in libgcc2.c, which can
1285 not depend on target_flags. */
1286 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1287 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1288 #else
1289 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1290 #endif
1291
1292 #define MAX_BITS_PER_WORD 64
1293
1294 /* Width of a word, in units (bytes). */
1295 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1296 #define MIN_UNITS_PER_WORD 4
1297
1298 /* For MIPS, width of a floating point register. */
1299 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1300
1301 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1302 the next available register. */
1303 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1304
1305 /* The largest size of value that can be held in floating-point
1306 registers and moved with a single instruction. */
1307 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1308
1309 /* The largest size of value that can be held in floating-point
1310 registers. */
1311 #define UNITS_PER_FPVALUE \
1312 (TARGET_SOFT_FLOAT ? 0 \
1313 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1314 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1315
1316 /* The number of bytes in a double. */
1317 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1318
1319 /* Tell the preprocessor the maximum size of wchar_t. */
1320 #ifndef MAX_WCHAR_TYPE_SIZE
1321 #ifndef WCHAR_TYPE_SIZE
1322 #define MAX_WCHAR_TYPE_SIZE 64
1323 #endif
1324 #endif
1325
1326 /* Set the sizes of the core types. */
1327 #define SHORT_TYPE_SIZE 16
1328 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1329 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1330 #define LONG_LONG_TYPE_SIZE 64
1331
1332 #define MAX_LONG_TYPE_SIZE 64
1333
1334 #define FLOAT_TYPE_SIZE 32
1335 #define DOUBLE_TYPE_SIZE 64
1336 #define LONG_DOUBLE_TYPE_SIZE \
1337 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1338
1339 /* long double is not a fixed mode, but the idea is that, if we
1340 support long double, we also want a 128-bit integer type. */
1341 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1342
1343 #ifdef IN_LIBGCC2
1344 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1345 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1346 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1347 # else
1348 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1349 # endif
1350 #endif
1351
1352 /* Width in bits of a pointer. */
1353 #ifndef POINTER_SIZE
1354 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1355 #endif
1356
1357 #define POINTERS_EXTEND_UNSIGNED 0
1358
1359 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1360 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1361 || mips_abi == ABI_64 \
1362 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1363
1364
1365 /* Allocation boundary (in *bits*) for the code of a function. */
1366 #define FUNCTION_BOUNDARY 32
1367
1368 /* Alignment of field after `int : 0' in a structure. */
1369 #define EMPTY_FIELD_BOUNDARY 32
1370
1371 /* Every structure's size must be a multiple of this. */
1372 /* 8 is observed right on a DECstation and on riscos 4.02. */
1373 #define STRUCTURE_SIZE_BOUNDARY 8
1374
1375 /* There is no point aligning anything to a rounder boundary than this. */
1376 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1377
1378 /* All accesses must be aligned. */
1379 #define STRICT_ALIGNMENT 1
1380
1381 /* Define this if you wish to imitate the way many other C compilers
1382 handle alignment of bitfields and the structures that contain
1383 them.
1384
1385 The behavior is that the type written for a bit-field (`int',
1386 `short', or other integer type) imposes an alignment for the
1387 entire structure, as if the structure really did contain an
1388 ordinary field of that type. In addition, the bit-field is placed
1389 within the structure so that it would fit within such a field,
1390 not crossing a boundary for it.
1391
1392 Thus, on most machines, a bit-field whose type is written as `int'
1393 would not cross a four-byte boundary, and would force four-byte
1394 alignment for the whole structure. (The alignment used may not
1395 be four bytes; it is controlled by the other alignment
1396 parameters.)
1397
1398 If the macro is defined, its definition should be a C expression;
1399 a nonzero value for the expression enables this behavior. */
1400
1401 #define PCC_BITFIELD_TYPE_MATTERS 1
1402
1403 /* If defined, a C expression to compute the alignment given to a
1404 constant that is being placed in memory. CONSTANT is the constant
1405 and ALIGN is the alignment that the object would ordinarily have.
1406 The value of this macro is used instead of that alignment to align
1407 the object.
1408
1409 If this macro is not defined, then ALIGN is used.
1410
1411 The typical use of this macro is to increase alignment for string
1412 constants to be word aligned so that `strcpy' calls that copy
1413 constants can be done inline. */
1414
1415 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1416 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1417 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1418
1419 /* If defined, a C expression to compute the alignment for a static
1420 variable. TYPE is the data type, and ALIGN is the alignment that
1421 the object would ordinarily have. The value of this macro is used
1422 instead of that alignment to align the object.
1423
1424 If this macro is not defined, then ALIGN is used.
1425
1426 One use of this macro is to increase alignment of medium-size
1427 data to make it all fit in fewer cache lines. Another is to
1428 cause character arrays to be word-aligned so that `strcpy' calls
1429 that copy constants to character arrays can be done inline. */
1430
1431 #undef DATA_ALIGNMENT
1432 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1433 ((((ALIGN) < BITS_PER_WORD) \
1434 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1435 || TREE_CODE (TYPE) == UNION_TYPE \
1436 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1437
1438
1439 #define PAD_VARARGS_DOWN \
1440 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1441
1442 /* Arguments declared as 'char' or 'short' in a prototype should be
1443 passed as 'int's. */
1444 #define PROMOTE_PROTOTYPES 1
1445
1446 /* Define if operations between registers always perform the operation
1447 on the full register even if a narrower mode is specified. */
1448 #define WORD_REGISTER_OPERATIONS
1449
1450 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1451 moves. All other references are zero extended. */
1452 #define LOAD_EXTEND_OP(MODE) \
1453 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1454 ? SIGN_EXTEND : ZERO_EXTEND)
1455
1456 /* Define this macro if it is advisable to hold scalars in registers
1457 in a wider mode than that declared by the program. In such cases,
1458 the value is constrained to be within the bounds of the declared
1459 type, but kept valid in the wider mode. The signedness of the
1460 extension may differ from that of the type. */
1461
1462 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1463 if (GET_MODE_CLASS (MODE) == MODE_INT \
1464 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1465 { \
1466 if ((MODE) == SImode) \
1467 (UNSIGNEDP) = 0; \
1468 (MODE) = Pmode; \
1469 }
1470
1471 /* Define if loading short immediate values into registers sign extends. */
1472 #define SHORT_IMMEDIATES_SIGN_EXTEND
1473
1474
1475 /* Define this if function arguments should also be promoted using the above
1476 procedure. */
1477 #define PROMOTE_FUNCTION_ARGS
1478
1479 /* Likewise, if the function return value is promoted. */
1480 #define PROMOTE_FUNCTION_RETURN
1481
1482 \f
1483 /* Standard register usage. */
1484
1485 /* Number of hardware registers. We have:
1486
1487 - 32 integer registers
1488 - 32 floating point registers
1489 - 8 condition code registers
1490 - 2 accumulator registers (hi and lo)
1491 - 32 registers each for coprocessors 0, 2 and 3
1492 - 3 fake registers:
1493 - ARG_POINTER_REGNUM
1494 - FRAME_POINTER_REGNUM
1495 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1496 - 3 dummy entries that were used at various times in the past. */
1497
1498 #define FIRST_PSEUDO_REGISTER 176
1499
1500 /* By default, fix the kernel registers ($26 and $27), the global
1501 pointer ($28) and the stack pointer ($29). This can change
1502 depending on the command-line options.
1503
1504 Regarding coprocessor registers: without evidence to the contrary,
1505 it's best to assume that each coprocessor register has a unique
1506 use. This can be overridden, in, e.g., override_options() or
1507 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1508 for a particular target. */
1509
1510 #define FIXED_REGISTERS \
1511 { \
1512 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1513 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1514 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1515 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1516 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1517 /* COP0 registers */ \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1520 /* COP2 registers */ \
1521 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1522 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1523 /* COP3 registers */ \
1524 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1525 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1526 }
1527
1528
1529 /* Set up this array for o32 by default.
1530
1531 Note that we don't mark $31 as a call-clobbered register. The idea is
1532 that it's really the call instructions themselves which clobber $31.
1533 We don't care what the called function does with it afterwards.
1534
1535 This approach makes it easier to implement sibcalls. Unlike normal
1536 calls, sibcalls don't clobber $31, so the register reaches the
1537 called function in tact. EPILOGUE_USES says that $31 is useful
1538 to the called function. */
1539
1540 #define CALL_USED_REGISTERS \
1541 { \
1542 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1543 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1544 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1545 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1546 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1547 /* COP0 registers */ \
1548 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1550 /* COP2 registers */ \
1551 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1553 /* COP3 registers */ \
1554 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1556 }
1557
1558
1559 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1560
1561 #define CALL_REALLY_USED_REGISTERS \
1562 { /* General registers. */ \
1563 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1564 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1565 /* Floating-point registers. */ \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1567 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1568 /* Others. */ \
1569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1570 /* COP0 registers */ \
1571 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1572 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1573 /* COP2 registers */ \
1574 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1576 /* COP3 registers */ \
1577 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1578 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1579 }
1580
1581 /* Internal macros to classify a register number as to whether it's a
1582 general purpose register, a floating point register, a
1583 multiply/divide register, or a status register. */
1584
1585 #define GP_REG_FIRST 0
1586 #define GP_REG_LAST 31
1587 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1588 #define GP_DBX_FIRST 0
1589
1590 #define FP_REG_FIRST 32
1591 #define FP_REG_LAST 63
1592 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1593 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1594
1595 #define MD_REG_FIRST 64
1596 #define MD_REG_LAST 65
1597 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1598 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1599
1600 #define ST_REG_FIRST 67
1601 #define ST_REG_LAST 74
1602 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1603
1604
1605 /* FIXME: renumber. */
1606 #define COP0_REG_FIRST 80
1607 #define COP0_REG_LAST 111
1608 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1609
1610 #define COP2_REG_FIRST 112
1611 #define COP2_REG_LAST 143
1612 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1613
1614 #define COP3_REG_FIRST 144
1615 #define COP3_REG_LAST 175
1616 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1617 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1618 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1619
1620 #define AT_REGNUM (GP_REG_FIRST + 1)
1621 #define HI_REGNUM (MD_REG_FIRST + 0)
1622 #define LO_REGNUM (MD_REG_FIRST + 1)
1623
1624 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1625 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1626 should be used instead. */
1627 #define FPSW_REGNUM ST_REG_FIRST
1628
1629 #define GP_REG_P(REGNO) \
1630 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1631 #define M16_REG_P(REGNO) \
1632 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1633 #define FP_REG_P(REGNO) \
1634 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1635 #define MD_REG_P(REGNO) \
1636 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1637 #define ST_REG_P(REGNO) \
1638 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1639 #define COP0_REG_P(REGNO) \
1640 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1641 #define COP2_REG_P(REGNO) \
1642 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1643 #define COP3_REG_P(REGNO) \
1644 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1645 #define ALL_COP_REG_P(REGNO) \
1646 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1647
1648 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1649
1650 /* Return coprocessor number from register number. */
1651
1652 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1653 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1654 : COP3_REG_P (REGNO) ? '3' : '?')
1655
1656
1657 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1658
1659 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1660 array built in override_options. Because machmodes.h is not yet
1661 included before this file is processed, the MODE bound can't be
1662 expressed here. */
1663
1664 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1665
1666 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1667 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1668
1669 /* Value is 1 if it is a good idea to tie two pseudo registers
1670 when one has mode MODE1 and one has mode MODE2.
1671 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1672 for any hard reg, then this must be 0 for correct output. */
1673 #define MODES_TIEABLE_P(MODE1, MODE2) \
1674 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1675 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1676 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1677 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1678
1679 /* Register to use for pushing function arguments. */
1680 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1681
1682 /* These two registers don't really exist: they get eliminated to either
1683 the stack or hard frame pointer. */
1684 #define ARG_POINTER_REGNUM 77
1685 #define FRAME_POINTER_REGNUM 78
1686
1687 /* $30 is not available on the mips16, so we use $17 as the frame
1688 pointer. */
1689 #define HARD_FRAME_POINTER_REGNUM \
1690 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1691
1692 /* Value should be nonzero if functions must have frame pointers.
1693 Zero means the frame pointer need not be set up (and parms
1694 may be accessed via the stack pointer) in functions that seem suitable.
1695 This is computed in `reload', in reload1.c. */
1696 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1697
1698 /* Register in which static-chain is passed to a function. */
1699 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1700
1701 /* Pass structure addresses as an "invisible" first argument. */
1702 #define STRUCT_VALUE 0
1703
1704 /* Registers used as temporaries in prologue/epilogue code. If we're
1705 generating mips16 code, these registers must come from the core set
1706 of 8. The prologue register mustn't conflict with any incoming
1707 arguments, the static chain pointer, or the frame pointer. The
1708 epilogue temporary mustn't conflict with the return registers, the
1709 frame pointer, the EH stack adjustment, or the EH data registers. */
1710
1711 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1712 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1713
1714 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1715 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1716
1717 /* Define this macro if it is as good or better to call a constant
1718 function address than to call an address kept in a register. */
1719 #define NO_FUNCTION_CSE 1
1720
1721 /* Define this macro if it is as good or better for a function to
1722 call itself with an explicit address than to call an address
1723 kept in a register. */
1724 #define NO_RECURSIVE_FUNCTION_CSE 1
1725
1726 /* The ABI-defined global pointer. Sometimes we use a different
1727 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1728 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1729
1730 /* We normally use $28 as the global pointer. However, when generating
1731 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1732 register instead. They can then avoid saving and restoring $28
1733 and perhaps avoid using a frame at all.
1734
1735 When a leaf function uses something other than $28, mips_expand_prologue
1736 will modify pic_offset_table_rtx in place. Take the register number
1737 from there after reload. */
1738 #define PIC_OFFSET_TABLE_REGNUM \
1739 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1740
1741 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1742 \f
1743 /* Define the classes of registers for register constraints in the
1744 machine description. Also define ranges of constants.
1745
1746 One of the classes must always be named ALL_REGS and include all hard regs.
1747 If there is more than one class, another class must be named NO_REGS
1748 and contain no registers.
1749
1750 The name GENERAL_REGS must be the name of a class (or an alias for
1751 another name such as ALL_REGS). This is the class of registers
1752 that is allowed by "g" or "r" in a register constraint.
1753 Also, registers outside this class are allocated only when
1754 instructions express preferences for them.
1755
1756 The classes must be numbered in nondecreasing order; that is,
1757 a larger-numbered class must never be contained completely
1758 in a smaller-numbered class.
1759
1760 For any two classes, it is very desirable that there be another
1761 class that represents their union. */
1762
1763 enum reg_class
1764 {
1765 NO_REGS, /* no registers in set */
1766 M16_NA_REGS, /* mips16 regs not used to pass args */
1767 M16_REGS, /* mips16 directly accessible registers */
1768 T_REG, /* mips16 T register ($24) */
1769 M16_T_REGS, /* mips16 registers plus T register */
1770 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1771 LEA_REGS, /* Every GPR except $25 */
1772 GR_REGS, /* integer registers */
1773 FP_REGS, /* floating point registers */
1774 HI_REG, /* hi register */
1775 LO_REG, /* lo register */
1776 MD_REGS, /* multiply/divide registers (hi/lo) */
1777 COP0_REGS, /* generic coprocessor classes */
1778 COP2_REGS,
1779 COP3_REGS,
1780 HI_AND_GR_REGS, /* union classes */
1781 LO_AND_GR_REGS,
1782 HI_AND_FP_REGS,
1783 COP0_AND_GR_REGS,
1784 COP2_AND_GR_REGS,
1785 COP3_AND_GR_REGS,
1786 ALL_COP_REGS,
1787 ALL_COP_AND_GR_REGS,
1788 ST_REGS, /* status registers (fp status) */
1789 ALL_REGS, /* all registers */
1790 LIM_REG_CLASSES /* max value + 1 */
1791 };
1792
1793 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1794
1795 #define GENERAL_REGS GR_REGS
1796
1797 /* An initializer containing the names of the register classes as C
1798 string constants. These names are used in writing some of the
1799 debugging dumps. */
1800
1801 #define REG_CLASS_NAMES \
1802 { \
1803 "NO_REGS", \
1804 "M16_NA_REGS", \
1805 "M16_REGS", \
1806 "T_REG", \
1807 "M16_T_REGS", \
1808 "PIC_FN_ADDR_REG", \
1809 "LEA_REGS", \
1810 "GR_REGS", \
1811 "FP_REGS", \
1812 "HI_REG", \
1813 "LO_REG", \
1814 "MD_REGS", \
1815 /* coprocessor registers */ \
1816 "COP0_REGS", \
1817 "COP2_REGS", \
1818 "COP3_REGS", \
1819 "HI_AND_GR_REGS", \
1820 "LO_AND_GR_REGS", \
1821 "HI_AND_FP_REGS", \
1822 "COP0_AND_GR_REGS", \
1823 "COP2_AND_GR_REGS", \
1824 "COP3_AND_GR_REGS", \
1825 "ALL_COP_REGS", \
1826 "ALL_COP_AND_GR_REGS", \
1827 "ST_REGS", \
1828 "ALL_REGS" \
1829 }
1830
1831 /* An initializer containing the contents of the register classes,
1832 as integers which are bit masks. The Nth integer specifies the
1833 contents of class N. The way the integer MASK is interpreted is
1834 that register R is in the class if `MASK & (1 << R)' is 1.
1835
1836 When the machine has more than 32 registers, an integer does not
1837 suffice. Then the integers are replaced by sub-initializers,
1838 braced groupings containing several integers. Each
1839 sub-initializer must be suitable as an initializer for the type
1840 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1841
1842 #define REG_CLASS_CONTENTS \
1843 { \
1844 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1845 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1846 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1847 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1848 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1849 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1850 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1851 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1852 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1853 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1854 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1855 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1856 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1857 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1858 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1859 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1860 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1861 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1862 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1863 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1864 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1865 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1866 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1867 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1868 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1869 }
1870
1871
1872 /* A C expression whose value is a register class containing hard
1873 register REGNO. In general there is more that one such class;
1874 choose a class which is "minimal", meaning that no smaller class
1875 also contains the register. */
1876
1877 extern const enum reg_class mips_regno_to_class[];
1878
1879 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1880
1881 /* A macro whose definition is the name of the class to which a
1882 valid base register must belong. A base register is one used in
1883 an address which is the register value plus a displacement. */
1884
1885 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1886
1887 /* A macro whose definition is the name of the class to which a
1888 valid index register must belong. An index register is one used
1889 in an address where its value is either multiplied by a scale
1890 factor or added to another register (as well as added to a
1891 displacement). */
1892
1893 #define INDEX_REG_CLASS NO_REGS
1894
1895 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1896 registers explicitly used in the rtl to be used as spill registers
1897 but prevents the compiler from extending the lifetime of these
1898 registers. */
1899
1900 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1901
1902 /* This macro is used later on in the file. */
1903 #define GR_REG_CLASS_P(CLASS) \
1904 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1905 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1906 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1907
1908 /* This macro is also used later on in the file. */
1909 #define COP_REG_CLASS_P(CLASS) \
1910 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1911
1912 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1913 is the default value (allocate the registers in numeric order). We
1914 define it just so that we can override it for the mips16 target in
1915 ORDER_REGS_FOR_LOCAL_ALLOC. */
1916
1917 #define REG_ALLOC_ORDER \
1918 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1919 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1920 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1921 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1922 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1923 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1924 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1925 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1926 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1927 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1928 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1929 }
1930
1931 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1932 to be rearranged based on a particular function. On the mips16, we
1933 want to allocate $24 (T_REG) before other registers for
1934 instructions for which it is possible. */
1935
1936 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1937
1938 /* REGISTER AND CONSTANT CLASSES */
1939
1940 /* Get reg_class from a letter such as appears in the machine
1941 description.
1942
1943 DEFINED REGISTER CLASSES:
1944
1945 'd' General (aka integer) registers
1946 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1947 'y' General registers (in both mips16 and non mips16 mode)
1948 'e' mips16 non argument registers (M16_NA_REGS)
1949 't' mips16 temporary register ($24)
1950 'f' Floating point registers
1951 'h' Hi register
1952 'l' Lo register
1953 'x' Multiply/divide registers
1954 'z' FP Status register
1955 'B' Cop0 register
1956 'C' Cop2 register
1957 'D' Cop3 register
1958 'b' All registers */
1959
1960 extern enum reg_class mips_char_to_class[256];
1961
1962 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1963
1964 /* True if VALUE is a signed 16-bit number. */
1965
1966 #define SMALL_OPERAND(VALUE) \
1967 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1968
1969 /* True if VALUE is an unsigned 16-bit number. */
1970
1971 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1972 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1973
1974 /* True if VALUE can be loaded into a register using LUI. */
1975
1976 #define LUI_OPERAND(VALUE) \
1977 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1978 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1979
1980 /* Return a value X with the low 16 bits clear, and such that
1981 VALUE - X is a signed 16-bit value. */
1982
1983 #define CONST_HIGH_PART(VALUE) \
1984 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1985
1986 #define CONST_LOW_PART(VALUE) \
1987 ((VALUE) - CONST_HIGH_PART (VALUE))
1988
1989 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1990 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1991 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1992
1993 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1994 string can be used to stand for particular ranges of immediate
1995 operands. This macro defines what the ranges are. C is the
1996 letter, and VALUE is a constant value. Return 1 if VALUE is
1997 in the range specified by C. */
1998
1999 /* For MIPS:
2000
2001 `I' is used for the range of constants an arithmetic insn can
2002 actually contain (16 bits signed integers).
2003
2004 `J' is used for the range which is just zero (ie, $r0).
2005
2006 `K' is used for the range of constants a logical insn can actually
2007 contain (16 bit zero-extended integers).
2008
2009 `L' is used for the range of constants that be loaded with lui
2010 (ie, the bottom 16 bits are zero).
2011
2012 `M' is used for the range of constants that take two words to load
2013 (ie, not matched by `I', `K', and `L').
2014
2015 `N' is used for negative 16 bit constants other than -65536.
2016
2017 `O' is a 15 bit signed integer.
2018
2019 `P' is used for positive 16 bit constants. */
2020
2021 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2022 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2023 : (C) == 'J' ? ((VALUE) == 0) \
2024 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2025 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2026 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2027 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2028 && !LUI_OPERAND (VALUE)) \
2029 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2030 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2031 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2032 : 0)
2033
2034 /* Similar, but for floating constants, and defining letters G and H.
2035 Here VALUE is the CONST_DOUBLE rtx itself. */
2036
2037 /* For Mips
2038
2039 'G' : Floating point 0 */
2040
2041 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2042 ((C) == 'G' \
2043 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2044
2045 /* Letters in the range `Q' through `U' may be defined in a
2046 machine-dependent fashion to stand for arbitrary operand types.
2047 The machine description macro `EXTRA_CONSTRAINT' is passed the
2048 operand as its first argument and the constraint letter as its
2049 second operand.
2050
2051 `Q' is for signed 16-bit constants.
2052 `R' is for single-instruction memory references. Note that this
2053 constraint has often been used in linux and glibc code.
2054 `S' is for legitimate constant call addresses.
2055 `T' is for constant move_operands that cannot be safely loaded into $25.
2056 `U' is for constant move_operands that can be safely loaded into $25.
2057 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2058 This is true for all non-mips16 references (although it can somtimes
2059 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2060 stack and constant-pool references. */
2061
2062 #define EXTRA_CONSTRAINT(OP,CODE) \
2063 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2064 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2065 && mips_fetch_insns (OP) == 1) \
2066 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2067 && call_insn_operand (OP, VOIDmode)) \
2068 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2069 && move_operand (OP, VOIDmode) \
2070 && mips_dangerous_for_la25_p (OP)) \
2071 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2072 && move_operand (OP, VOIDmode) \
2073 && !mips_dangerous_for_la25_p (OP)) \
2074 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2075 && memory_operand (OP, VOIDmode) \
2076 && (!TARGET_MIPS16 \
2077 || (!stack_operand (OP, VOIDmode) \
2078 && !CONSTANT_P (XEXP (OP, 0))))) \
2079 : FALSE)
2080
2081 /* Say which of the above are memory constraints. */
2082 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2083
2084 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2085 mips_preferred_reload_class (X, CLASS)
2086
2087 /* Certain machines have the property that some registers cannot be
2088 copied to some other registers without using memory. Define this
2089 macro on those machines to be a C expression that is nonzero if
2090 objects of mode MODE in registers of CLASS1 can only be copied to
2091 registers of class CLASS2 by storing a register of CLASS1 into
2092 memory and loading that memory location into a register of CLASS2.
2093
2094 Do not define this macro if its value would always be zero. */
2095 #if 0
2096 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2097 ((!TARGET_DEBUG_H_MODE \
2098 && GET_MODE_CLASS (MODE) == MODE_INT \
2099 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2100 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2101 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2102 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2103 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2104 #endif
2105 /* The HI and LO registers can only be reloaded via the general
2106 registers. Condition code registers can only be loaded to the
2107 general registers, and from the floating point registers. */
2108
2109 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2110 mips_secondary_reload_class (CLASS, MODE, X, 1)
2111 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2112 mips_secondary_reload_class (CLASS, MODE, X, 0)
2113
2114 /* Return the maximum number of consecutive registers
2115 needed to represent mode MODE in a register of class CLASS. */
2116
2117 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2118
2119 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2120 mips_cannot_change_mode_class (FROM, TO, CLASS)
2121 \f
2122 /* Stack layout; function entry, exit and calling. */
2123
2124 #define STACK_GROWS_DOWNWARD
2125
2126 /* The offset of the first local variable from the beginning of the frame.
2127 See compute_frame_size for details about the frame layout. */
2128 #define STARTING_FRAME_OFFSET \
2129 (current_function_outgoing_args_size \
2130 + (TARGET_ABICALLS && !TARGET_NEWABI \
2131 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2132
2133 #define RETURN_ADDR_RTX mips_return_addr
2134
2135 /* Since the mips16 ISA mode is encoded in the least-significant bit
2136 of the address, mask it off return addresses for purposes of
2137 finding exception handling regions. */
2138
2139 #define MASK_RETURN_ADDR GEN_INT (-2)
2140
2141
2142 /* Similarly, don't use the least-significant bit to tell pointers to
2143 code from vtable index. */
2144
2145 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2146
2147 /* The eliminations to $17 are only used for mips16 code. See the
2148 definition of HARD_FRAME_POINTER_REGNUM. */
2149
2150 #define ELIMINABLE_REGS \
2151 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2152 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2153 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2154 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2155 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2156 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2157
2158 /* We can always eliminate to the hard frame pointer. We can eliminate
2159 to the stack pointer unless a frame pointer is needed.
2160
2161 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2162 reload may be unable to compute the address of a local variable,
2163 since there is no way to add a large constant to the stack pointer
2164 without using a temporary register. */
2165 #define CAN_ELIMINATE(FROM, TO) \
2166 ((TO) == HARD_FRAME_POINTER_REGNUM \
2167 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2168 && (!TARGET_MIPS16 \
2169 || compute_frame_size (get_frame_size ()) < 32768)))
2170
2171 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2172 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2173
2174 /* Allocate stack space for arguments at the beginning of each function. */
2175 #define ACCUMULATE_OUTGOING_ARGS 1
2176
2177 /* The argument pointer always points to the first argument. */
2178 #define FIRST_PARM_OFFSET(FNDECL) 0
2179
2180 /* o32 and o64 reserve stack space for all argument registers. */
2181 #define REG_PARM_STACK_SPACE(FNDECL) \
2182 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2183 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2184 : 0)
2185
2186 /* Define this if it is the responsibility of the caller to
2187 allocate the area reserved for arguments passed in registers.
2188 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2189 of this macro is to determine whether the space is included in
2190 `current_function_outgoing_args_size'. */
2191 #define OUTGOING_REG_PARM_STACK_SPACE
2192
2193 #define STACK_BOUNDARY \
2194 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2195 ? 64 : 128)
2196
2197 \f
2198 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2199
2200 /* Symbolic macros for the registers used to return integer and floating
2201 point values. */
2202
2203 #define GP_RETURN (GP_REG_FIRST + 2)
2204 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2205
2206 #define MAX_ARGS_IN_REGISTERS \
2207 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2208
2209 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2210
2211 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2212
2213 /* Symbolic macros for the first/last argument registers. */
2214
2215 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2216 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2217 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2218 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2219
2220 #define LIBCALL_VALUE(MODE) \
2221 mips_function_value (NULL_TREE, NULL, (MODE))
2222
2223 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2224 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2225
2226 /* 1 if N is a possible register number for a function value.
2227 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2228 Currently, R2 and F0 are only implemented here (C has no complex type) */
2229
2230 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2231 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2232 && (N) == FP_RETURN + 2))
2233
2234 /* 1 if N is a possible register number for function argument passing.
2235 We have no FP argument registers when soft-float. When FP registers
2236 are 32 bits, we can't directly reference the odd numbered ones. */
2237
2238 #define FUNCTION_ARG_REGNO_P(N) \
2239 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2240 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2241 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2242 && !fixed_regs[N])
2243
2244 #define RETURN_IN_MEMORY(TYPE) mips_return_in_memory (TYPE)
2245
2246 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2247 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2248 (TYPE), (NO_RTL))
2249 \f
2250 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2251
2252 /* This structure has to cope with two different argument allocation
2253 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2254 first N words go in registers and the rest go on the stack. If I < N,
2255 the Ith word might go in Ith integer argument register or the
2256 Ith floating-point one. For these ABIs, we only need to remember
2257 the number of words passed so far.
2258
2259 The EABI instead allocates the integer and floating-point arguments
2260 separately. The first N words of FP arguments go in FP registers,
2261 the rest go on the stack. Likewise, the first N words of the other
2262 arguments go in integer registers, and the rest go on the stack. We
2263 need to maintain three counts: the number of integer registers used,
2264 the number of floating-point registers used, and the number of words
2265 passed on the stack.
2266
2267 We could keep separate information for the two ABIs (a word count for
2268 the standard ABIs, and three separate counts for the EABI). But it
2269 seems simpler to view the standard ABIs as forms of EABI that do not
2270 allocate floating-point registers.
2271
2272 So for the standard ABIs, the first N words are allocated to integer
2273 registers, and function_arg decides on an argument-by-argument basis
2274 whether that argument should really go in an integer register, or in
2275 a floating-point one. */
2276
2277 typedef struct mips_args {
2278 /* Always true for varargs functions. Otherwise true if at least
2279 one argument has been passed in an integer register. */
2280 int gp_reg_found;
2281
2282 /* The number of arguments seen so far. */
2283 unsigned int arg_number;
2284
2285 /* For EABI, the number of integer registers used so far. For other
2286 ABIs, the number of words passed in registers (whether integer
2287 or floating-point). */
2288 unsigned int num_gprs;
2289
2290 /* For EABI, the number of floating-point registers used so far. */
2291 unsigned int num_fprs;
2292
2293 /* The number of words passed on the stack. */
2294 unsigned int stack_words;
2295
2296 /* On the mips16, we need to keep track of which floating point
2297 arguments were passed in general registers, but would have been
2298 passed in the FP regs if this were a 32 bit function, so that we
2299 can move them to the FP regs if we wind up calling a 32 bit
2300 function. We record this information in fp_code, encoded in base
2301 four. A zero digit means no floating point argument, a one digit
2302 means an SFmode argument, and a two digit means a DFmode argument,
2303 and a three digit is not used. The low order digit is the first
2304 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2305 an SFmode argument. ??? A more sophisticated approach will be
2306 needed if MIPS_ABI != ABI_32. */
2307 int fp_code;
2308
2309 /* True if the function has a prototype. */
2310 int prototype;
2311 } CUMULATIVE_ARGS;
2312
2313 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2314 for a call to a function whose data type is FNTYPE.
2315 For a library call, FNTYPE is 0. */
2316
2317 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2318 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2319
2320 /* Update the data in CUM to advance over an argument
2321 of mode MODE and data type TYPE.
2322 (TYPE is null for libcalls where that information may not be available.) */
2323
2324 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2325 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2326
2327 /* Determine where to put an argument to a function.
2328 Value is zero to push the argument on the stack,
2329 or a hard register in which to store the argument.
2330
2331 MODE is the argument's machine mode.
2332 TYPE is the data type of the argument (as a tree).
2333 This is null for libcalls where that information may
2334 not be available.
2335 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2336 the preceding args and about the function being called.
2337 NAMED is nonzero if this argument is a named parameter
2338 (otherwise it is an extra parameter matching an ellipsis). */
2339
2340 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2341 function_arg( &CUM, MODE, TYPE, NAMED)
2342
2343 /* For an arg passed partly in registers and partly in memory,
2344 this is the number of registers used.
2345 For args passed entirely in registers or entirely in memory, zero. */
2346
2347 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2348 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2349
2350 /* If defined, a C expression that gives the alignment boundary, in
2351 bits, of an argument with the specified mode and type. If it is
2352 not defined, `PARM_BOUNDARY' is used for all arguments. */
2353
2354 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2355 (((TYPE) != 0) \
2356 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2357 ? PARM_BOUNDARY \
2358 : TYPE_ALIGN(TYPE)) \
2359 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2360 ? PARM_BOUNDARY \
2361 : GET_MODE_ALIGNMENT(MODE)))
2362
2363 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2364 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2365
2366 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2367 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2368
2369 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2370 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2371
2372 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2373 (mips_abi == ABI_EABI && (NAMED) \
2374 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2375
2376 /* Modified version of the macro in expr.h. Only return true if
2377 the type has a variable size or if the front end requires it
2378 to be passed by reference. */
2379 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2380 ((TYPE) != 0 \
2381 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2382 || TREE_ADDRESSABLE (TYPE)))
2383
2384 /* True if using EABI and varargs can be passed in floating-point
2385 registers. Under these conditions, we need a more complex form
2386 of va_list, which tracks GPR, FPR and stack arguments separately. */
2387 #define EABI_FLOAT_VARARGS_P \
2388 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2389
2390 \f
2391 /* Say that the epilogue uses the return address register. Note that
2392 in the case of sibcalls, the values "used by the epilogue" are
2393 considered live at the start of the called function. */
2394 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2395
2396 /* Treat LOC as a byte offset from the stack pointer and round it up
2397 to the next fully-aligned offset. */
2398 #define MIPS_STACK_ALIGN(LOC) \
2399 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2400 ? ((LOC) + 7) & ~7 \
2401 : ((LOC) + 15) & ~15)
2402
2403 \f
2404 /* Implement `va_start' for varargs and stdarg. */
2405 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2406 mips_va_start (valist, nextarg)
2407
2408 /* Implement `va_arg'. */
2409 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2410 mips_va_arg (valist, type)
2411 \f
2412 /* Output assembler code to FILE to increment profiler label # LABELNO
2413 for profiling a function entry. */
2414
2415 #define FUNCTION_PROFILER(FILE, LABELNO) \
2416 { \
2417 if (TARGET_MIPS16) \
2418 sorry ("mips16 function profiling"); \
2419 fprintf (FILE, "\t.set\tnoat\n"); \
2420 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2421 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2422 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2423 { \
2424 fprintf (FILE, \
2425 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2426 TARGET_64BIT ? "dsubu" : "subu", \
2427 reg_names[STACK_POINTER_REGNUM], \
2428 reg_names[STACK_POINTER_REGNUM], \
2429 Pmode == DImode ? 16 : 8); \
2430 } \
2431 fprintf (FILE, "\tjal\t_mcount\n"); \
2432 fprintf (FILE, "\t.set\tat\n"); \
2433 }
2434
2435 /* Define this macro if the code for function profiling should come
2436 before the function prologue. Normally, the profiling code comes
2437 after. */
2438
2439 /* #define PROFILE_BEFORE_PROLOGUE */
2440
2441 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2442 the stack pointer does not matter. The value is tested only in
2443 functions that have frame pointers.
2444 No definition is equivalent to always zero. */
2445
2446 #define EXIT_IGNORE_STACK 1
2447
2448 \f
2449 /* A C statement to output, on the stream FILE, assembler code for a
2450 block of data that contains the constant parts of a trampoline.
2451 This code should not include a label--the label is taken care of
2452 automatically. */
2453
2454 #define TRAMPOLINE_TEMPLATE(STREAM) \
2455 { \
2456 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2457 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2458 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2459 if (ptr_mode == DImode) \
2460 { \
2461 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2462 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2463 } \
2464 else \
2465 { \
2466 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2467 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2468 } \
2469 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2470 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2471 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2472 if (ptr_mode == DImode) \
2473 { \
2474 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2475 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2476 } \
2477 else \
2478 { \
2479 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2480 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2481 } \
2482 }
2483
2484 /* A C expression for the size in bytes of the trampoline, as an
2485 integer. */
2486
2487 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2488
2489 /* Alignment required for trampolines, in bits. */
2490
2491 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2492
2493 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2494 program and data caches. */
2495
2496 #ifndef CACHE_FLUSH_FUNC
2497 #define CACHE_FLUSH_FUNC "_flush_cache"
2498 #endif
2499
2500 /* A C statement to initialize the variable parts of a trampoline.
2501 ADDR is an RTX for the address of the trampoline; FNADDR is an
2502 RTX for the address of the nested function; STATIC_CHAIN is an
2503 RTX for the static chain value that should be passed to the
2504 function when it is called. */
2505
2506 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2507 { \
2508 rtx func_addr, chain_addr; \
2509 \
2510 func_addr = plus_constant (ADDR, 32); \
2511 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2512 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2513 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2514 \
2515 /* Flush both caches. We need to flush the data cache in case \
2516 the system has a write-back cache. */ \
2517 /* ??? Should check the return value for errors. */ \
2518 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2519 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2520 0, VOIDmode, 3, ADDR, Pmode, \
2521 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2522 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2523 }
2524 \f
2525 /* Addressing modes, and classification of registers for them. */
2526
2527 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2528 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2529 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2530
2531 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2532 and check its validity for a certain class.
2533 We have two alternate definitions for each of them.
2534 The usual definition accepts all pseudo regs; the other rejects them all.
2535 The symbol REG_OK_STRICT causes the latter definition to be used.
2536
2537 Most source files want to accept pseudo regs in the hope that
2538 they will get allocated to the class that the insn wants them to be in.
2539 Some source files that are used after register allocation
2540 need to be strict. */
2541
2542 #ifndef REG_OK_STRICT
2543 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2544 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2545 #else
2546 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2547 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2548 #endif
2549
2550 #define REG_OK_FOR_INDEX_P(X) 0
2551
2552 \f
2553 /* Maximum number of registers that can appear in a valid memory address. */
2554
2555 #define MAX_REGS_PER_ADDRESS 1
2556
2557 /* A C compound statement with a conditional `goto LABEL;' executed
2558 if X (an RTX) is a legitimate memory address on the target
2559 machine for a memory operand of mode MODE. */
2560
2561 #if 1
2562 #define GO_PRINTF(x) fprintf(stderr, (x))
2563 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2564 #define GO_DEBUG_RTX(x) debug_rtx(x)
2565
2566 #else
2567 #define GO_PRINTF(x)
2568 #define GO_PRINTF2(x,y)
2569 #define GO_DEBUG_RTX(x)
2570 #endif
2571
2572 #ifdef REG_OK_STRICT
2573 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2574 { \
2575 if (mips_legitimate_address_p (MODE, X, 1)) \
2576 goto ADDR; \
2577 }
2578 #else
2579 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2580 { \
2581 if (mips_legitimate_address_p (MODE, X, 0)) \
2582 goto ADDR; \
2583 }
2584 #endif
2585
2586 /* Check for constness inline but use mips_legitimate_address_p
2587 to check whether a constant really is an address. */
2588
2589 #define CONSTANT_ADDRESS_P(X) \
2590 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2591
2592 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2593
2594 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2595 do { \
2596 if (mips_legitimize_address (&(X), MODE)) \
2597 goto WIN; \
2598 } while (0)
2599
2600
2601 /* A C statement or compound statement with a conditional `goto
2602 LABEL;' executed if memory address X (an RTX) can have different
2603 meanings depending on the machine mode of the memory reference it
2604 is used for.
2605
2606 Autoincrement and autodecrement addresses typically have
2607 mode-dependent effects because the amount of the increment or
2608 decrement is the size of the operand being addressed. Some
2609 machines have other mode-dependent addresses. Many RISC machines
2610 have no mode-dependent addresses.
2611
2612 You may assume that ADDR is a valid address for the machine. */
2613
2614 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2615
2616 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2617 'the start of the function that this code is output in'. */
2618
2619 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2620 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2621 asm_fprintf ((FILE), "%U%s", \
2622 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2623 else \
2624 asm_fprintf ((FILE), "%U%s", (NAME))
2625
2626 /* The mips16 wants the constant pool to be after the function,
2627 because the PC relative load instructions use unsigned offsets. */
2628
2629 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
2630
2631 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
2632 mips_string_length = 0;
2633 \f
2634 /* Specify the machine mode that this machine uses
2635 for the index in the tablejump instruction.
2636 ??? Using HImode in mips16 mode can cause overflow. */
2637 #define CASE_VECTOR_MODE \
2638 (TARGET_MIPS16 ? HImode : ptr_mode)
2639
2640 /* Define as C expression which evaluates to nonzero if the tablejump
2641 instruction expects the table to contain offsets from the address of the
2642 table.
2643 Do not define this if the table should contain absolute addresses. */
2644 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2645
2646 /* Define this as 1 if `char' should by default be signed; else as 0. */
2647 #ifndef DEFAULT_SIGNED_CHAR
2648 #define DEFAULT_SIGNED_CHAR 1
2649 #endif
2650
2651 /* Max number of bytes we can move from memory to memory
2652 in one reasonably fast instruction. */
2653 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2654 #define MAX_MOVE_MAX 8
2655
2656 /* Define this macro as a C expression which is nonzero if
2657 accessing less than a word of memory (i.e. a `char' or a
2658 `short') is no faster than accessing a word of memory, i.e., if
2659 such access require more than one instruction or if there is no
2660 difference in cost between byte and (aligned) word loads.
2661
2662 On RISC machines, it tends to generate better code to define
2663 this as 1, since it avoids making a QI or HI mode register. */
2664 #define SLOW_BYTE_ACCESS 1
2665
2666 /* Define this to be nonzero if shift instructions ignore all but the low-order
2667 few bits. */
2668 #define SHIFT_COUNT_TRUNCATED 1
2669
2670 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2671 is done just by pretending it is already truncated. */
2672 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2673 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2674
2675
2676 /* Specify the machine mode that pointers have.
2677 After generation of rtl, the compiler makes no further distinction
2678 between pointers and any other objects of this machine mode. */
2679
2680 #ifndef Pmode
2681 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2682 #endif
2683
2684 /* Give call MEMs SImode since it is the "most permissive" mode
2685 for both 32-bit and 64-bit targets. */
2686
2687 #define FUNCTION_MODE SImode
2688
2689 \f
2690 /* The cost of loading values from the constant pool. It should be
2691 larger than the cost of any constant we want to synthesize in-line. */
2692
2693 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2694
2695 /* A C expression for the cost of moving data from a register in
2696 class FROM to one in class TO. The classes are expressed using
2697 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2698 the default; other values are interpreted relative to that.
2699
2700 It is not required that the cost always equal 2 when FROM is the
2701 same as TO; on some machines it is expensive to move between
2702 registers if they are not general registers.
2703
2704 If reload sees an insn consisting of a single `set' between two
2705 hard registers, and if `REGISTER_MOVE_COST' applied to their
2706 classes returns a value of 2, reload does not check to ensure
2707 that the constraints of the insn are met. Setting a cost of
2708 other than 2 will allow reload to verify that the constraints are
2709 met. You should do this if the `movM' pattern's constraints do
2710 not allow such copying. */
2711
2712 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2713 mips_register_move_cost (MODE, FROM, TO)
2714
2715 /* ??? Fix this to be right for the R8000. */
2716 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2717 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2718 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2719
2720 /* Define if copies to/from condition code registers should be avoided.
2721
2722 This is needed for the MIPS because reload_outcc is not complete;
2723 it needs to handle cases where the source is a general or another
2724 condition code register. */
2725 #define AVOID_CCMODE_COPIES
2726
2727 /* A C expression for the cost of a branch instruction. A value of
2728 1 is the default; other values are interpreted relative to that. */
2729
2730 /* ??? Fix this to be right for the R8000. */
2731 #define BRANCH_COST \
2732 ((! TARGET_MIPS16 \
2733 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2734 ? 2 : 1)
2735
2736 /* If defined, modifies the length assigned to instruction INSN as a
2737 function of the context in which it is used. LENGTH is an lvalue
2738 that contains the initially computed length of the insn and should
2739 be updated with the correct length of the insn. */
2740 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2741 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2742
2743 \f
2744 /* Optionally define this if you have added predicates to
2745 `MACHINE.c'. This macro is called within an initializer of an
2746 array of structures. The first field in the structure is the
2747 name of a predicate and the second field is an array of rtl
2748 codes. For each predicate, list all rtl codes that can be in
2749 expressions matched by the predicate. The list should have a
2750 trailing comma. Here is an example of two entries in the list
2751 for a typical RISC machine:
2752
2753 #define PREDICATE_CODES \
2754 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2755 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2756
2757 Defining this macro does not affect the generated code (however,
2758 incorrect definitions that omit an rtl code that may be matched
2759 by the predicate can cause the compiler to malfunction).
2760 Instead, it allows the table built by `genrecog' to be more
2761 compact and efficient, thus speeding up the compiler. The most
2762 important predicates to include in the list specified by this
2763 macro are thoses used in the most insn patterns. */
2764
2765 #define PREDICATE_CODES \
2766 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
2767 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2768 {"global_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2769 {"local_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2770 {"const_arith_operand", { CONST_INT }}, \
2771 {"small_data_pattern", { SET, PARALLEL, UNSPEC, \
2772 UNSPEC_VOLATILE }}, \
2773 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
2774 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
2775 {"small_int", { CONST_INT }}, \
2776 {"mips_const_double_ok", { CONST_DOUBLE }}, \
2777 {"const_float_1_operand", { CONST_DOUBLE }}, \
2778 {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
2779 {"simple_memory_operand", { MEM, SUBREG }}, \
2780 {"equality_op", { EQ, NE }}, \
2781 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2782 LTU, LEU }}, \
2783 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
2784 {"pc_or_label_operand", { PC, LABEL_REF }}, \
2785 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
2786 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
2787 SYMBOL_REF, LABEL_REF, SUBREG, \
2788 REG, MEM}}, \
2789 {"stack_operand", { MEM }}, \
2790 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
2791 CONST_DOUBLE, CONST }}, \
2792 {"fcc_register_operand", { REG, SUBREG }}, \
2793 {"hilo_operand", { REG }}, \
2794 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
2795
2796 /* A list of predicates that do special things with modes, and so
2797 should not elicit warnings for VOIDmode match_operand. */
2798
2799 #define SPECIAL_MODE_PREDICATES \
2800 "pc_or_label_operand",
2801 \f
2802 /* Control the assembler format that we output. */
2803
2804 /* Output to assembler file text saying following lines
2805 may contain character constants, extra white space, comments, etc. */
2806
2807 #ifndef ASM_APP_ON
2808 #define ASM_APP_ON " #APP\n"
2809 #endif
2810
2811 /* Output to assembler file text saying following lines
2812 no longer contain unusual constructs. */
2813
2814 #ifndef ASM_APP_OFF
2815 #define ASM_APP_OFF " #NO_APP\n"
2816 #endif
2817
2818 /* How to refer to registers in assembler output.
2819 This sequence is indexed by compiler's hard-register-number (see above).
2820
2821 In order to support the two different conventions for register names,
2822 we use the name of a table set up in mips.c, which is overwritten
2823 if -mrnames is used. */
2824
2825 #define REGISTER_NAMES \
2826 { \
2827 &mips_reg_names[ 0][0], \
2828 &mips_reg_names[ 1][0], \
2829 &mips_reg_names[ 2][0], \
2830 &mips_reg_names[ 3][0], \
2831 &mips_reg_names[ 4][0], \
2832 &mips_reg_names[ 5][0], \
2833 &mips_reg_names[ 6][0], \
2834 &mips_reg_names[ 7][0], \
2835 &mips_reg_names[ 8][0], \
2836 &mips_reg_names[ 9][0], \
2837 &mips_reg_names[10][0], \
2838 &mips_reg_names[11][0], \
2839 &mips_reg_names[12][0], \
2840 &mips_reg_names[13][0], \
2841 &mips_reg_names[14][0], \
2842 &mips_reg_names[15][0], \
2843 &mips_reg_names[16][0], \
2844 &mips_reg_names[17][0], \
2845 &mips_reg_names[18][0], \
2846 &mips_reg_names[19][0], \
2847 &mips_reg_names[20][0], \
2848 &mips_reg_names[21][0], \
2849 &mips_reg_names[22][0], \
2850 &mips_reg_names[23][0], \
2851 &mips_reg_names[24][0], \
2852 &mips_reg_names[25][0], \
2853 &mips_reg_names[26][0], \
2854 &mips_reg_names[27][0], \
2855 &mips_reg_names[28][0], \
2856 &mips_reg_names[29][0], \
2857 &mips_reg_names[30][0], \
2858 &mips_reg_names[31][0], \
2859 &mips_reg_names[32][0], \
2860 &mips_reg_names[33][0], \
2861 &mips_reg_names[34][0], \
2862 &mips_reg_names[35][0], \
2863 &mips_reg_names[36][0], \
2864 &mips_reg_names[37][0], \
2865 &mips_reg_names[38][0], \
2866 &mips_reg_names[39][0], \
2867 &mips_reg_names[40][0], \
2868 &mips_reg_names[41][0], \
2869 &mips_reg_names[42][0], \
2870 &mips_reg_names[43][0], \
2871 &mips_reg_names[44][0], \
2872 &mips_reg_names[45][0], \
2873 &mips_reg_names[46][0], \
2874 &mips_reg_names[47][0], \
2875 &mips_reg_names[48][0], \
2876 &mips_reg_names[49][0], \
2877 &mips_reg_names[50][0], \
2878 &mips_reg_names[51][0], \
2879 &mips_reg_names[52][0], \
2880 &mips_reg_names[53][0], \
2881 &mips_reg_names[54][0], \
2882 &mips_reg_names[55][0], \
2883 &mips_reg_names[56][0], \
2884 &mips_reg_names[57][0], \
2885 &mips_reg_names[58][0], \
2886 &mips_reg_names[59][0], \
2887 &mips_reg_names[60][0], \
2888 &mips_reg_names[61][0], \
2889 &mips_reg_names[62][0], \
2890 &mips_reg_names[63][0], \
2891 &mips_reg_names[64][0], \
2892 &mips_reg_names[65][0], \
2893 &mips_reg_names[66][0], \
2894 &mips_reg_names[67][0], \
2895 &mips_reg_names[68][0], \
2896 &mips_reg_names[69][0], \
2897 &mips_reg_names[70][0], \
2898 &mips_reg_names[71][0], \
2899 &mips_reg_names[72][0], \
2900 &mips_reg_names[73][0], \
2901 &mips_reg_names[74][0], \
2902 &mips_reg_names[75][0], \
2903 &mips_reg_names[76][0], \
2904 &mips_reg_names[77][0], \
2905 &mips_reg_names[78][0], \
2906 &mips_reg_names[79][0], \
2907 &mips_reg_names[80][0], \
2908 &mips_reg_names[81][0], \
2909 &mips_reg_names[82][0], \
2910 &mips_reg_names[83][0], \
2911 &mips_reg_names[84][0], \
2912 &mips_reg_names[85][0], \
2913 &mips_reg_names[86][0], \
2914 &mips_reg_names[87][0], \
2915 &mips_reg_names[88][0], \
2916 &mips_reg_names[89][0], \
2917 &mips_reg_names[90][0], \
2918 &mips_reg_names[91][0], \
2919 &mips_reg_names[92][0], \
2920 &mips_reg_names[93][0], \
2921 &mips_reg_names[94][0], \
2922 &mips_reg_names[95][0], \
2923 &mips_reg_names[96][0], \
2924 &mips_reg_names[97][0], \
2925 &mips_reg_names[98][0], \
2926 &mips_reg_names[99][0], \
2927 &mips_reg_names[100][0], \
2928 &mips_reg_names[101][0], \
2929 &mips_reg_names[102][0], \
2930 &mips_reg_names[103][0], \
2931 &mips_reg_names[104][0], \
2932 &mips_reg_names[105][0], \
2933 &mips_reg_names[106][0], \
2934 &mips_reg_names[107][0], \
2935 &mips_reg_names[108][0], \
2936 &mips_reg_names[109][0], \
2937 &mips_reg_names[110][0], \
2938 &mips_reg_names[111][0], \
2939 &mips_reg_names[112][0], \
2940 &mips_reg_names[113][0], \
2941 &mips_reg_names[114][0], \
2942 &mips_reg_names[115][0], \
2943 &mips_reg_names[116][0], \
2944 &mips_reg_names[117][0], \
2945 &mips_reg_names[118][0], \
2946 &mips_reg_names[119][0], \
2947 &mips_reg_names[120][0], \
2948 &mips_reg_names[121][0], \
2949 &mips_reg_names[122][0], \
2950 &mips_reg_names[123][0], \
2951 &mips_reg_names[124][0], \
2952 &mips_reg_names[125][0], \
2953 &mips_reg_names[126][0], \
2954 &mips_reg_names[127][0], \
2955 &mips_reg_names[128][0], \
2956 &mips_reg_names[129][0], \
2957 &mips_reg_names[130][0], \
2958 &mips_reg_names[131][0], \
2959 &mips_reg_names[132][0], \
2960 &mips_reg_names[133][0], \
2961 &mips_reg_names[134][0], \
2962 &mips_reg_names[135][0], \
2963 &mips_reg_names[136][0], \
2964 &mips_reg_names[137][0], \
2965 &mips_reg_names[138][0], \
2966 &mips_reg_names[139][0], \
2967 &mips_reg_names[140][0], \
2968 &mips_reg_names[141][0], \
2969 &mips_reg_names[142][0], \
2970 &mips_reg_names[143][0], \
2971 &mips_reg_names[144][0], \
2972 &mips_reg_names[145][0], \
2973 &mips_reg_names[146][0], \
2974 &mips_reg_names[147][0], \
2975 &mips_reg_names[148][0], \
2976 &mips_reg_names[149][0], \
2977 &mips_reg_names[150][0], \
2978 &mips_reg_names[151][0], \
2979 &mips_reg_names[152][0], \
2980 &mips_reg_names[153][0], \
2981 &mips_reg_names[154][0], \
2982 &mips_reg_names[155][0], \
2983 &mips_reg_names[156][0], \
2984 &mips_reg_names[157][0], \
2985 &mips_reg_names[158][0], \
2986 &mips_reg_names[159][0], \
2987 &mips_reg_names[160][0], \
2988 &mips_reg_names[161][0], \
2989 &mips_reg_names[162][0], \
2990 &mips_reg_names[163][0], \
2991 &mips_reg_names[164][0], \
2992 &mips_reg_names[165][0], \
2993 &mips_reg_names[166][0], \
2994 &mips_reg_names[167][0], \
2995 &mips_reg_names[168][0], \
2996 &mips_reg_names[169][0], \
2997 &mips_reg_names[170][0], \
2998 &mips_reg_names[171][0], \
2999 &mips_reg_names[172][0], \
3000 &mips_reg_names[173][0], \
3001 &mips_reg_names[174][0], \
3002 &mips_reg_names[175][0] \
3003 }
3004
3005 /* If defined, a C initializer for an array of structures
3006 containing a name and a register number. This macro defines
3007 additional names for hard registers, thus allowing the `asm'
3008 option in declarations to refer to registers using alternate
3009 names.
3010
3011 We define both names for the integer registers here. */
3012
3013 #define ADDITIONAL_REGISTER_NAMES \
3014 { \
3015 { "$0", 0 + GP_REG_FIRST }, \
3016 { "$1", 1 + GP_REG_FIRST }, \
3017 { "$2", 2 + GP_REG_FIRST }, \
3018 { "$3", 3 + GP_REG_FIRST }, \
3019 { "$4", 4 + GP_REG_FIRST }, \
3020 { "$5", 5 + GP_REG_FIRST }, \
3021 { "$6", 6 + GP_REG_FIRST }, \
3022 { "$7", 7 + GP_REG_FIRST }, \
3023 { "$8", 8 + GP_REG_FIRST }, \
3024 { "$9", 9 + GP_REG_FIRST }, \
3025 { "$10", 10 + GP_REG_FIRST }, \
3026 { "$11", 11 + GP_REG_FIRST }, \
3027 { "$12", 12 + GP_REG_FIRST }, \
3028 { "$13", 13 + GP_REG_FIRST }, \
3029 { "$14", 14 + GP_REG_FIRST }, \
3030 { "$15", 15 + GP_REG_FIRST }, \
3031 { "$16", 16 + GP_REG_FIRST }, \
3032 { "$17", 17 + GP_REG_FIRST }, \
3033 { "$18", 18 + GP_REG_FIRST }, \
3034 { "$19", 19 + GP_REG_FIRST }, \
3035 { "$20", 20 + GP_REG_FIRST }, \
3036 { "$21", 21 + GP_REG_FIRST }, \
3037 { "$22", 22 + GP_REG_FIRST }, \
3038 { "$23", 23 + GP_REG_FIRST }, \
3039 { "$24", 24 + GP_REG_FIRST }, \
3040 { "$25", 25 + GP_REG_FIRST }, \
3041 { "$26", 26 + GP_REG_FIRST }, \
3042 { "$27", 27 + GP_REG_FIRST }, \
3043 { "$28", 28 + GP_REG_FIRST }, \
3044 { "$29", 29 + GP_REG_FIRST }, \
3045 { "$30", 30 + GP_REG_FIRST }, \
3046 { "$31", 31 + GP_REG_FIRST }, \
3047 { "$sp", 29 + GP_REG_FIRST }, \
3048 { "$fp", 30 + GP_REG_FIRST }, \
3049 { "at", 1 + GP_REG_FIRST }, \
3050 { "v0", 2 + GP_REG_FIRST }, \
3051 { "v1", 3 + GP_REG_FIRST }, \
3052 { "a0", 4 + GP_REG_FIRST }, \
3053 { "a1", 5 + GP_REG_FIRST }, \
3054 { "a2", 6 + GP_REG_FIRST }, \
3055 { "a3", 7 + GP_REG_FIRST }, \
3056 { "t0", 8 + GP_REG_FIRST }, \
3057 { "t1", 9 + GP_REG_FIRST }, \
3058 { "t2", 10 + GP_REG_FIRST }, \
3059 { "t3", 11 + GP_REG_FIRST }, \
3060 { "t4", 12 + GP_REG_FIRST }, \
3061 { "t5", 13 + GP_REG_FIRST }, \
3062 { "t6", 14 + GP_REG_FIRST }, \
3063 { "t7", 15 + GP_REG_FIRST }, \
3064 { "s0", 16 + GP_REG_FIRST }, \
3065 { "s1", 17 + GP_REG_FIRST }, \
3066 { "s2", 18 + GP_REG_FIRST }, \
3067 { "s3", 19 + GP_REG_FIRST }, \
3068 { "s4", 20 + GP_REG_FIRST }, \
3069 { "s5", 21 + GP_REG_FIRST }, \
3070 { "s6", 22 + GP_REG_FIRST }, \
3071 { "s7", 23 + GP_REG_FIRST }, \
3072 { "t8", 24 + GP_REG_FIRST }, \
3073 { "t9", 25 + GP_REG_FIRST }, \
3074 { "k0", 26 + GP_REG_FIRST }, \
3075 { "k1", 27 + GP_REG_FIRST }, \
3076 { "gp", 28 + GP_REG_FIRST }, \
3077 { "sp", 29 + GP_REG_FIRST }, \
3078 { "fp", 30 + GP_REG_FIRST }, \
3079 { "ra", 31 + GP_REG_FIRST }, \
3080 { "$sp", 29 + GP_REG_FIRST }, \
3081 { "$fp", 30 + GP_REG_FIRST } \
3082 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3083 }
3084
3085 /* This is meant to be redefined in the host dependent files. It is a
3086 set of alternative names and regnums for mips coprocessors. */
3087
3088 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3089
3090 /* A C compound statement to output to stdio stream STREAM the
3091 assembler syntax for an instruction operand X. X is an RTL
3092 expression.
3093
3094 CODE is a value that can be used to specify one of several ways
3095 of printing the operand. It is used when identical operands
3096 must be printed differently depending on the context. CODE
3097 comes from the `%' specification that was used to request
3098 printing of the operand. If the specification was just `%DIGIT'
3099 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3100 is the ASCII code for LTR.
3101
3102 If X is a register, this macro should print the register's name.
3103 The names can be found in an array `reg_names' whose type is
3104 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3105
3106 When the machine description has a specification `%PUNCT' (a `%'
3107 followed by a punctuation character), this macro is called with
3108 a null pointer for X and the punctuation character for CODE.
3109
3110 See mips.c for the MIPS specific codes. */
3111
3112 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3113
3114 /* A C expression which evaluates to true if CODE is a valid
3115 punctuation character for use in the `PRINT_OPERAND' macro. If
3116 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3117 punctuation characters (except for the standard one, `%') are
3118 used in this way. */
3119
3120 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3121
3122 /* A C compound statement to output to stdio stream STREAM the
3123 assembler syntax for an instruction operand that is a memory
3124 reference whose address is ADDR. ADDR is an RTL expression. */
3125
3126 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3127
3128
3129 /* A C statement, to be executed after all slot-filler instructions
3130 have been output. If necessary, call `dbr_sequence_length' to
3131 determine the number of slots filled in a sequence (zero if not
3132 currently outputting a sequence), to decide how many no-ops to
3133 output, or whatever.
3134
3135 Don't define this macro if it has nothing to do, but it is
3136 helpful in reading assembly output if the extent of the delay
3137 sequence is made explicit (e.g. with white space).
3138
3139 Note that output routines for instructions with delay slots must
3140 be prepared to deal with not being output as part of a sequence
3141 (i.e. when the scheduling pass is not run, or when no slot
3142 fillers could be found.) The variable `final_sequence' is null
3143 when not processing a sequence, otherwise it contains the
3144 `sequence' rtx being output. */
3145
3146 #define DBR_OUTPUT_SEQEND(STREAM) \
3147 do \
3148 { \
3149 if (set_nomacro > 0 && --set_nomacro == 0) \
3150 fputs ("\t.set\tmacro\n", STREAM); \
3151 \
3152 if (set_noreorder > 0 && --set_noreorder == 0) \
3153 fputs ("\t.set\treorder\n", STREAM); \
3154 \
3155 fputs ("\n", STREAM); \
3156 } \
3157 while (0)
3158
3159
3160 /* How to tell the debugger about changes of source files. */
3161
3162 #ifndef SET_FILE_NUMBER
3163 #define SET_FILE_NUMBER() ++num_source_filenames
3164 #endif
3165
3166 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3167 mips_output_filename (STREAM, NAME)
3168
3169 /* This is defined so that it can be overridden in iris6.h. */
3170 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3171 do \
3172 { \
3173 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3174 output_quoted_string (STREAM, NAME); \
3175 fputs ("\n", STREAM); \
3176 } \
3177 while (0)
3178
3179 /* This is how to output a note the debugger telling it the line number
3180 to which the following sequence of instructions corresponds.
3181 Silicon graphics puts a label after each .loc. */
3182
3183 #ifndef LABEL_AFTER_LOC
3184 #define LABEL_AFTER_LOC(STREAM)
3185 #endif
3186
3187 #ifndef ASM_OUTPUT_SOURCE_LINE
3188 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3189 mips_output_lineno (STREAM, LINE)
3190 #endif
3191
3192 /* The MIPS implementation uses some labels for its own purpose. The
3193 following lists what labels are created, and are all formed by the
3194 pattern $L[a-z].*. The machine independent portion of GCC creates
3195 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3196
3197 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3198 $Lb[0-9]+ Begin blocks for MIPS debug support
3199 $Lc[0-9]+ Label for use in s<xx> operation.
3200 $Le[0-9]+ End blocks for MIPS debug support */
3201
3202 #undef ASM_DECLARE_OBJECT_NAME
3203 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3204 mips_declare_object (STREAM, NAME, "", ":\n", 0)
3205
3206 /* Globalizing directive for a label. */
3207 #define GLOBAL_ASM_OP "\t.globl\t"
3208
3209 /* This says how to define a global common symbol. */
3210
3211 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
3212
3213 /* This says how to define a local common symbol (ie, not visible to
3214 linker). */
3215
3216 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3217 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3218
3219
3220 /* This says how to output an external. It would be possible not to
3221 output anything and let undefined symbol become external. However
3222 the assembler uses length information on externals to allocate in
3223 data/sdata bss/sbss, thereby saving exec time. */
3224
3225 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3226 mips_output_external(STREAM,DECL,NAME)
3227
3228 /* This is how to declare a function name. The actual work of
3229 emitting the label is moved to function_prologue, so that we can
3230 get the line number correctly emitted before the .ent directive,
3231 and after any .file directives. Define as empty so that the function
3232 is not declared before the .ent directive elsewhere. */
3233
3234 #undef ASM_DECLARE_FUNCTION_NAME
3235 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3236
3237 #ifndef FUNCTION_NAME_ALREADY_DECLARED
3238 #define FUNCTION_NAME_ALREADY_DECLARED 0
3239 #endif
3240
3241 /* This is how to store into the string LABEL
3242 the symbol_ref name of an internal numbered label where
3243 PREFIX is the class of label and NUM is the number within the class.
3244 This is suitable for output with `assemble_name'. */
3245
3246 #undef ASM_GENERATE_INTERNAL_LABEL
3247 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3248 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3249
3250 /* This is how to output an element of a case-vector that is absolute. */
3251
3252 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3253 fprintf (STREAM, "\t%s\t%sL%d\n", \
3254 ptr_mode == DImode ? ".dword" : ".word", \
3255 LOCAL_LABEL_PREFIX, \
3256 VALUE)
3257
3258 /* This is how to output an element of a case-vector that is relative.
3259 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3260 TARGET_EMBEDDED_PIC). */
3261
3262 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3263 do { \
3264 if (TARGET_MIPS16) \
3265 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3266 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3267 else if (TARGET_EMBEDDED_PIC) \
3268 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3269 ptr_mode == DImode ? ".dword" : ".word", \
3270 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3271 else if (TARGET_GPWORD) \
3272 fprintf (STREAM, "\t%s\t%sL%d\n", \
3273 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3274 LOCAL_LABEL_PREFIX, VALUE); \
3275 else \
3276 fprintf (STREAM, "\t%s\t%sL%d\n", \
3277 ptr_mode == DImode ? ".dword" : ".word", \
3278 LOCAL_LABEL_PREFIX, VALUE); \
3279 } while (0)
3280
3281 /* When generating embedded PIC or mips16 code we want to put the jump
3282 table in the .text section. In all other cases, we want to put the
3283 jump table in the .rdata section. Unfortunately, we can't use
3284 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3285 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3286 section if appropriate. */
3287 #undef ASM_OUTPUT_CASE_LABEL
3288 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3289 do { \
3290 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3291 function_section (current_function_decl); \
3292 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3293 } while (0)
3294
3295 /* This is how to output an assembler line
3296 that says to advance the location counter
3297 to a multiple of 2**LOG bytes. */
3298
3299 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3300 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3301
3302 /* This is how to output an assembler line to advance the location
3303 counter by SIZE bytes. */
3304
3305 #undef ASM_OUTPUT_SKIP
3306 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3307 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3308
3309 /* This is how to output a string. */
3310 #undef ASM_OUTPUT_ASCII
3311 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3312 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
3313
3314 /* Output #ident as a in the read-only data section. */
3315 #undef ASM_OUTPUT_IDENT
3316 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3317 { \
3318 const char *p = STRING; \
3319 int size = strlen (p) + 1; \
3320 readonly_data_section (); \
3321 assemble_string (p, size); \
3322 }
3323 \f
3324 /* Default to -G 8 */
3325 #ifndef MIPS_DEFAULT_GVALUE
3326 #define MIPS_DEFAULT_GVALUE 8
3327 #endif
3328
3329 /* Define the strings to put out for each section in the object file. */
3330 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3331 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3332 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3333
3334 #undef READONLY_DATA_SECTION_ASM_OP
3335 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3336
3337 /* Given a decl node or constant node, choose the section to output it in
3338 and select that section. */
3339
3340 #undef TARGET_ASM_SELECT_SECTION
3341 #define TARGET_ASM_SELECT_SECTION mips_select_section
3342 \f
3343 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3344 do \
3345 { \
3346 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3347 TARGET_64BIT ? "dsubu" : "subu", \
3348 reg_names[STACK_POINTER_REGNUM], \
3349 reg_names[STACK_POINTER_REGNUM], \
3350 TARGET_64BIT ? "sd" : "sw", \
3351 reg_names[REGNO], \
3352 reg_names[STACK_POINTER_REGNUM]); \
3353 } \
3354 while (0)
3355
3356 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3357 do \
3358 { \
3359 if (! set_noreorder) \
3360 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3361 \
3362 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3363 TARGET_64BIT ? "ld" : "lw", \
3364 reg_names[REGNO], \
3365 reg_names[STACK_POINTER_REGNUM], \
3366 TARGET_64BIT ? "daddu" : "addu", \
3367 reg_names[STACK_POINTER_REGNUM], \
3368 reg_names[STACK_POINTER_REGNUM]); \
3369 \
3370 if (! set_noreorder) \
3371 fprintf (STREAM, "\t.set\treorder\n"); \
3372 } \
3373 while (0)
3374
3375 /* How to start an assembler comment.
3376 The leading space is important (the mips native assembler requires it). */
3377 #ifndef ASM_COMMENT_START
3378 #define ASM_COMMENT_START " #"
3379 #endif
3380 \f
3381 /* Default definitions for size_t and ptrdiff_t. We must override the
3382 definitions from ../svr4.h on mips-*-linux-gnu. */
3383
3384 #undef SIZE_TYPE
3385 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3386
3387 #undef PTRDIFF_TYPE
3388 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3389
3390 /* See mips_expand_prologue's use of loadgp for when this should be
3391 true. */
3392
3393 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
3394 && mips_abi != ABI_32 \
3395 && mips_abi != ABI_O64)
3396 \f
3397
3398 #define DFMODE_NAN \
3399 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
3400 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
3401 #define SFMODE_NAN \
3402 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
3403 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
3404
3405 /* Generate calls to memcpy, etc., not bcopy, etc. */
3406 #define TARGET_MEM_FUNCTIONS
3407
3408 #ifndef __mips16
3409 /* Since the bits of the _init and _fini function is spread across
3410 many object files, each potentially with its own GP, we must assume
3411 we need to load our GP. We don't preserve $gp or $ra, since each
3412 init/fini chunk is supposed to initialize $gp, and crti/crtn
3413 already take care of preserving $ra and, when appropriate, $gp. */
3414 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3415 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3416 asm (SECTION_OP "\n\
3417 .set noreorder\n\
3418 bal 1f\n\
3419 nop\n\
3420 1: .cpload $31\n\
3421 .set reorder\n\
3422 jal " USER_LABEL_PREFIX #FUNC "\n\
3423 " TEXT_SECTION_ASM_OP);
3424 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3425 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3426 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3427 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3428 asm (SECTION_OP "\n\
3429 .set noreorder\n\
3430 bal 1f\n\
3431 nop\n\
3432 1: .set reorder\n\
3433 .cpsetup $31, $2, 1b\n\
3434 jal " USER_LABEL_PREFIX #FUNC "\n\
3435 " TEXT_SECTION_ASM_OP);
3436 #endif
3437 #endif
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