1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
31 ;; constraint letters.
33 ;; The special asm out single letter directives following a '%' are:
34 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
36 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
37 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
38 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
39 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
40 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
41 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
42 ;; 'J' Print the appropriate jump operand.
44 ;; 'b' Print the QImode name of the register for the indicated operand.
45 ;; %b0 would print %al if operands[0] is reg 0.
46 ;; 'w' Likewise, print the HImode name of the register.
47 ;; 'k' Likewise, print the SImode name of the register.
48 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
49 ;; 'y' Print "st(0)" instead of "st" as a register.
54 [; Relocation specifiers
66 (UNSPEC_STACK_PROBE 10)
67 (UNSPEC_STACK_ALLOC 11)
69 (UNSPEC_SSE_PROLOGUE_SAVE 13)
74 (UNSPEC_TLS_LD_BASE 17)
76 ; Other random patterns
86 ; For SSE/MMX support:
97 (UNSPEC_NOP 45) ; prevents combiner cleverness
129 [(UNSPECV_BLOCKAGE 0)
130 (UNSPECV_EH_RETURN 13)
141 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
144 ;; In C guard expressions, put expressions which may be compile-time
145 ;; constants first. This allows for better optimization. For
146 ;; example, write "TARGET_64BIT && reload_completed", not
147 ;; "reload_completed && TARGET_64BIT".
150 ;; Processor type. This attribute must exactly match the processor_type
151 ;; enumeration in i386.h.
152 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8"
153 (const (symbol_ref "ix86_tune")))
155 ;; A basic instruction type. Refinements due to arguments to be
156 ;; provided in other attributes.
159 alu,alu1,negnot,imov,imovx,lea,
160 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
161 icmp,test,ibr,setcc,icmov,
162 push,pop,call,callv,leave,
164 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
165 sselog,sseiadd,sseishft,sseimul,
166 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
167 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
168 (const_string "other"))
170 ;; Main data type used by the insn
172 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF"
173 (const_string "unknown"))
175 ;; The CPU unit operations uses.
176 (define_attr "unit" "integer,i387,sse,mmx,unknown"
177 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
178 (const_string "i387")
179 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
180 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
182 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
184 (eq_attr "type" "other")
185 (const_string "unknown")]
186 (const_string "integer")))
188 ;; The (bounding maximum) length of an instruction immediate.
189 (define_attr "length_immediate" ""
190 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
192 (eq_attr "unit" "i387,sse,mmx")
194 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
196 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
197 (eq_attr "type" "imov,test")
198 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
199 (eq_attr "type" "call")
200 (if_then_else (match_operand 0 "constant_call_address_operand" "")
203 (eq_attr "type" "callv")
204 (if_then_else (match_operand 1 "constant_call_address_operand" "")
207 ;; We don't know the size before shorten_branches. Expect
208 ;; the instruction to fit for better scheduling.
209 (eq_attr "type" "ibr")
212 (symbol_ref "/* Update immediate_length and other attributes! */
215 ;; The (bounding maximum) length of an instruction address.
216 (define_attr "length_address" ""
217 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
219 (and (eq_attr "type" "call")
220 (match_operand 0 "constant_call_address_operand" ""))
222 (and (eq_attr "type" "callv")
223 (match_operand 1 "constant_call_address_operand" ""))
226 (symbol_ref "ix86_attr_length_address_default (insn)")))
228 ;; Set when length prefix is used.
229 (define_attr "prefix_data16" ""
230 (if_then_else (ior (eq_attr "mode" "HI")
231 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
235 ;; Set when string REP prefix is used.
236 (define_attr "prefix_rep" ""
237 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
241 ;; Set when 0f opcode prefix is used.
242 (define_attr "prefix_0f" ""
244 (ior (eq_attr "type" "imovx,setcc,icmov")
245 (eq_attr "unit" "sse,mmx"))
249 ;; Set when 0f opcode prefix is used.
250 (define_attr "prefix_rex" ""
251 (cond [(and (eq_attr "mode" "DI")
252 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
254 (and (eq_attr "mode" "QI")
255 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
258 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
264 ;; Set when modrm byte is used.
265 (define_attr "modrm" ""
266 (cond [(eq_attr "type" "str,cld,leave")
268 (eq_attr "unit" "i387")
270 (and (eq_attr "type" "incdec")
271 (ior (match_operand:SI 1 "register_operand" "")
272 (match_operand:HI 1 "register_operand" "")))
274 (and (eq_attr "type" "push")
275 (not (match_operand 1 "memory_operand" "")))
277 (and (eq_attr "type" "pop")
278 (not (match_operand 0 "memory_operand" "")))
280 (and (eq_attr "type" "imov")
281 (and (match_operand 0 "register_operand" "")
282 (match_operand 1 "immediate_operand" "")))
284 (and (eq_attr "type" "call")
285 (match_operand 0 "constant_call_address_operand" ""))
287 (and (eq_attr "type" "callv")
288 (match_operand 1 "constant_call_address_operand" ""))
293 ;; The (bounding maximum) length of an instruction in bytes.
294 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
295 ;; to split it and compute proper length as for other insns.
296 (define_attr "length" ""
297 (cond [(eq_attr "type" "other,multi,fistp")
299 (eq_attr "type" "fcmp")
301 (eq_attr "unit" "i387")
303 (plus (attr "prefix_data16")
304 (attr "length_address")))]
305 (plus (plus (attr "modrm")
306 (plus (attr "prefix_0f")
307 (plus (attr "prefix_rex")
309 (plus (attr "prefix_rep")
310 (plus (attr "prefix_data16")
311 (plus (attr "length_immediate")
312 (attr "length_address")))))))
314 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
315 ;; `store' if there is a simple memory reference therein, or `unknown'
316 ;; if the instruction is complex.
318 (define_attr "memory" "none,load,store,both,unknown"
319 (cond [(eq_attr "type" "other,multi,str")
320 (const_string "unknown")
321 (eq_attr "type" "lea,fcmov,fpspc,cld")
322 (const_string "none")
323 (eq_attr "type" "fistp,leave")
324 (const_string "both")
325 (eq_attr "type" "push")
326 (if_then_else (match_operand 1 "memory_operand" "")
327 (const_string "both")
328 (const_string "store"))
329 (eq_attr "type" "pop")
330 (if_then_else (match_operand 0 "memory_operand" "")
331 (const_string "both")
332 (const_string "load"))
333 (eq_attr "type" "setcc")
334 (if_then_else (match_operand 0 "memory_operand" "")
335 (const_string "store")
336 (const_string "none"))
337 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
338 (if_then_else (ior (match_operand 0 "memory_operand" "")
339 (match_operand 1 "memory_operand" ""))
340 (const_string "load")
341 (const_string "none"))
342 (eq_attr "type" "ibr")
343 (if_then_else (match_operand 0 "memory_operand" "")
344 (const_string "load")
345 (const_string "none"))
346 (eq_attr "type" "call")
347 (if_then_else (match_operand 0 "constant_call_address_operand" "")
348 (const_string "none")
349 (const_string "load"))
350 (eq_attr "type" "callv")
351 (if_then_else (match_operand 1 "constant_call_address_operand" "")
352 (const_string "none")
353 (const_string "load"))
354 (and (eq_attr "type" "alu1,negnot,ishift1")
355 (match_operand 1 "memory_operand" ""))
356 (const_string "both")
357 (and (match_operand 0 "memory_operand" "")
358 (match_operand 1 "memory_operand" ""))
359 (const_string "both")
360 (match_operand 0 "memory_operand" "")
361 (const_string "store")
362 (match_operand 1 "memory_operand" "")
363 (const_string "load")
365 "!alu1,negnot,ishift1,
366 imov,imovx,icmp,test,
368 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
369 mmx,mmxmov,mmxcmp,mmxcvt")
370 (match_operand 2 "memory_operand" ""))
371 (const_string "load")
372 (and (eq_attr "type" "icmov")
373 (match_operand 3 "memory_operand" ""))
374 (const_string "load")
376 (const_string "none")))
378 ;; Indicates if an instruction has both an immediate and a displacement.
380 (define_attr "imm_disp" "false,true,unknown"
381 (cond [(eq_attr "type" "other,multi")
382 (const_string "unknown")
383 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
384 (and (match_operand 0 "memory_displacement_operand" "")
385 (match_operand 1 "immediate_operand" "")))
386 (const_string "true")
387 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
388 (and (match_operand 0 "memory_displacement_operand" "")
389 (match_operand 2 "immediate_operand" "")))
390 (const_string "true")
392 (const_string "false")))
394 ;; Indicates if an FP operation has an integer source.
396 (define_attr "fp_int_src" "false,true"
397 (const_string "false"))
399 ;; Describe a user's asm statement.
400 (define_asm_attributes
401 [(set_attr "length" "128")
402 (set_attr "type" "multi")])
404 (include "pentium.md")
407 (include "athlon.md")
409 ;; Compare instructions.
411 ;; All compare insns have expanders that save the operands away without
412 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
413 ;; after the cmp) will actually emit the cmpM.
415 (define_expand "cmpdi"
417 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
418 (match_operand:DI 1 "x86_64_general_operand" "")))]
421 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
422 operands[0] = force_reg (DImode, operands[0]);
423 ix86_compare_op0 = operands[0];
424 ix86_compare_op1 = operands[1];
428 (define_expand "cmpsi"
430 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
431 (match_operand:SI 1 "general_operand" "")))]
434 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
435 operands[0] = force_reg (SImode, operands[0]);
436 ix86_compare_op0 = operands[0];
437 ix86_compare_op1 = operands[1];
441 (define_expand "cmphi"
443 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
444 (match_operand:HI 1 "general_operand" "")))]
447 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
448 operands[0] = force_reg (HImode, operands[0]);
449 ix86_compare_op0 = operands[0];
450 ix86_compare_op1 = operands[1];
454 (define_expand "cmpqi"
456 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
457 (match_operand:QI 1 "general_operand" "")))]
460 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
461 operands[0] = force_reg (QImode, operands[0]);
462 ix86_compare_op0 = operands[0];
463 ix86_compare_op1 = operands[1];
467 (define_insn "cmpdi_ccno_1_rex64"
469 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
470 (match_operand:DI 1 "const0_operand" "n,n")))]
471 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
473 test{q}\t{%0, %0|%0, %0}
474 cmp{q}\t{%1, %0|%0, %1}"
475 [(set_attr "type" "test,icmp")
476 (set_attr "length_immediate" "0,1")
477 (set_attr "mode" "DI")])
479 (define_insn "*cmpdi_minus_1_rex64"
481 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
482 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
484 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
485 "cmp{q}\t{%1, %0|%0, %1}"
486 [(set_attr "type" "icmp")
487 (set_attr "mode" "DI")])
489 (define_expand "cmpdi_1_rex64"
491 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
492 (match_operand:DI 1 "general_operand" "")))]
496 (define_insn "cmpdi_1_insn_rex64"
498 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
499 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
500 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
501 "cmp{q}\t{%1, %0|%0, %1}"
502 [(set_attr "type" "icmp")
503 (set_attr "mode" "DI")])
506 (define_insn "*cmpsi_ccno_1"
508 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
509 (match_operand:SI 1 "const0_operand" "n,n")))]
510 "ix86_match_ccmode (insn, CCNOmode)"
512 test{l}\t{%0, %0|%0, %0}
513 cmp{l}\t{%1, %0|%0, %1}"
514 [(set_attr "type" "test,icmp")
515 (set_attr "length_immediate" "0,1")
516 (set_attr "mode" "SI")])
518 (define_insn "*cmpsi_minus_1"
520 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
521 (match_operand:SI 1 "general_operand" "ri,mr"))
523 "ix86_match_ccmode (insn, CCGOCmode)"
524 "cmp{l}\t{%1, %0|%0, %1}"
525 [(set_attr "type" "icmp")
526 (set_attr "mode" "SI")])
528 (define_expand "cmpsi_1"
530 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
531 (match_operand:SI 1 "general_operand" "ri,mr")))]
535 (define_insn "*cmpsi_1_insn"
537 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
538 (match_operand:SI 1 "general_operand" "ri,mr")))]
539 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
540 && ix86_match_ccmode (insn, CCmode)"
541 "cmp{l}\t{%1, %0|%0, %1}"
542 [(set_attr "type" "icmp")
543 (set_attr "mode" "SI")])
545 (define_insn "*cmphi_ccno_1"
547 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
548 (match_operand:HI 1 "const0_operand" "n,n")))]
549 "ix86_match_ccmode (insn, CCNOmode)"
551 test{w}\t{%0, %0|%0, %0}
552 cmp{w}\t{%1, %0|%0, %1}"
553 [(set_attr "type" "test,icmp")
554 (set_attr "length_immediate" "0,1")
555 (set_attr "mode" "HI")])
557 (define_insn "*cmphi_minus_1"
559 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
560 (match_operand:HI 1 "general_operand" "ri,mr"))
562 "ix86_match_ccmode (insn, CCGOCmode)"
563 "cmp{w}\t{%1, %0|%0, %1}"
564 [(set_attr "type" "icmp")
565 (set_attr "mode" "HI")])
567 (define_insn "*cmphi_1"
569 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
570 (match_operand:HI 1 "general_operand" "ri,mr")))]
571 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
572 && ix86_match_ccmode (insn, CCmode)"
573 "cmp{w}\t{%1, %0|%0, %1}"
574 [(set_attr "type" "icmp")
575 (set_attr "mode" "HI")])
577 (define_insn "*cmpqi_ccno_1"
579 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
580 (match_operand:QI 1 "const0_operand" "n,n")))]
581 "ix86_match_ccmode (insn, CCNOmode)"
583 test{b}\t{%0, %0|%0, %0}
584 cmp{b}\t{$0, %0|%0, 0}"
585 [(set_attr "type" "test,icmp")
586 (set_attr "length_immediate" "0,1")
587 (set_attr "mode" "QI")])
589 (define_insn "*cmpqi_1"
591 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
592 (match_operand:QI 1 "general_operand" "qi,mq")))]
593 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
594 && ix86_match_ccmode (insn, CCmode)"
595 "cmp{b}\t{%1, %0|%0, %1}"
596 [(set_attr "type" "icmp")
597 (set_attr "mode" "QI")])
599 (define_insn "*cmpqi_minus_1"
601 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
602 (match_operand:QI 1 "general_operand" "qi,mq"))
604 "ix86_match_ccmode (insn, CCGOCmode)"
605 "cmp{b}\t{%1, %0|%0, %1}"
606 [(set_attr "type" "icmp")
607 (set_attr "mode" "QI")])
609 (define_insn "*cmpqi_ext_1"
612 (match_operand:QI 0 "general_operand" "Qm")
615 (match_operand 1 "ext_register_operand" "Q")
618 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
619 "cmp{b}\t{%h1, %0|%0, %h1}"
620 [(set_attr "type" "icmp")
621 (set_attr "mode" "QI")])
623 (define_insn "*cmpqi_ext_1_rex64"
626 (match_operand:QI 0 "register_operand" "Q")
629 (match_operand 1 "ext_register_operand" "Q")
632 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
633 "cmp{b}\t{%h1, %0|%0, %h1}"
634 [(set_attr "type" "icmp")
635 (set_attr "mode" "QI")])
637 (define_insn "*cmpqi_ext_2"
642 (match_operand 0 "ext_register_operand" "Q")
645 (match_operand:QI 1 "const0_operand" "n")))]
646 "ix86_match_ccmode (insn, CCNOmode)"
648 [(set_attr "type" "test")
649 (set_attr "length_immediate" "0")
650 (set_attr "mode" "QI")])
652 (define_expand "cmpqi_ext_3"
657 (match_operand 0 "ext_register_operand" "")
660 (match_operand:QI 1 "general_operand" "")))]
664 (define_insn "cmpqi_ext_3_insn"
669 (match_operand 0 "ext_register_operand" "Q")
672 (match_operand:QI 1 "general_operand" "Qmn")))]
673 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
674 "cmp{b}\t{%1, %h0|%h0, %1}"
675 [(set_attr "type" "icmp")
676 (set_attr "mode" "QI")])
678 (define_insn "cmpqi_ext_3_insn_rex64"
683 (match_operand 0 "ext_register_operand" "Q")
686 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
687 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
688 "cmp{b}\t{%1, %h0|%h0, %1}"
689 [(set_attr "type" "icmp")
690 (set_attr "mode" "QI")])
692 (define_insn "*cmpqi_ext_4"
697 (match_operand 0 "ext_register_operand" "Q")
702 (match_operand 1 "ext_register_operand" "Q")
705 "ix86_match_ccmode (insn, CCmode)"
706 "cmp{b}\t{%h1, %h0|%h0, %h1}"
707 [(set_attr "type" "icmp")
708 (set_attr "mode" "QI")])
710 ;; These implement float point compares.
711 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
712 ;; which would allow mix and match FP modes on the compares. Which is what
713 ;; the old patterns did, but with many more of them.
715 (define_expand "cmpxf"
717 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
718 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
721 ix86_compare_op0 = operands[0];
722 ix86_compare_op1 = operands[1];
726 (define_expand "cmpdf"
728 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
729 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
730 "TARGET_80387 || TARGET_SSE2"
732 ix86_compare_op0 = operands[0];
733 ix86_compare_op1 = operands[1];
737 (define_expand "cmpsf"
739 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
740 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
741 "TARGET_80387 || TARGET_SSE"
743 ix86_compare_op0 = operands[0];
744 ix86_compare_op1 = operands[1];
748 ;; FP compares, step 1:
749 ;; Set the FP condition codes.
751 ;; CCFPmode compare with exceptions
752 ;; CCFPUmode compare with no exceptions
754 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
755 ;; and that fp moves clobber the condition codes, and that there is
756 ;; currently no way to describe this fact to reg-stack. So there are
757 ;; no splitters yet for this.
759 ;; %%% YIKES! This scheme does not retain a strong connection between
760 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
761 ;; work! Only allow tos/mem with tos in op 0.
763 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
764 ;; things aren't as bad as they sound...
766 (define_insn "*cmpfp_0"
767 [(set (match_operand:HI 0 "register_operand" "=a")
769 [(compare:CCFP (match_operand 1 "register_operand" "f")
770 (match_operand 2 "const0_operand" "X"))]
773 && FLOAT_MODE_P (GET_MODE (operands[1]))
774 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
776 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
777 return "ftst\;fnstsw\t%0\;fstp\t%y0";
779 return "ftst\;fnstsw\t%0";
781 [(set_attr "type" "multi")
783 (cond [(match_operand:SF 1 "" "")
785 (match_operand:DF 1 "" "")
788 (const_string "XF")))])
790 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
791 ;; used to manage the reg stack popping would not be preserved.
793 (define_insn "*cmpfp_2_sf"
796 (match_operand:SF 0 "register_operand" "f")
797 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
799 "* return output_fp_compare (insn, operands, 0, 0);"
800 [(set_attr "type" "fcmp")
801 (set_attr "mode" "SF")])
803 (define_insn "*cmpfp_2_sf_1"
804 [(set (match_operand:HI 0 "register_operand" "=a")
807 (match_operand:SF 1 "register_operand" "f")
808 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
811 "* return output_fp_compare (insn, operands, 2, 0);"
812 [(set_attr "type" "fcmp")
813 (set_attr "mode" "SF")])
815 (define_insn "*cmpfp_2_df"
818 (match_operand:DF 0 "register_operand" "f")
819 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
821 "* return output_fp_compare (insn, operands, 0, 0);"
822 [(set_attr "type" "fcmp")
823 (set_attr "mode" "DF")])
825 (define_insn "*cmpfp_2_df_1"
826 [(set (match_operand:HI 0 "register_operand" "=a")
829 (match_operand:DF 1 "register_operand" "f")
830 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
833 "* return output_fp_compare (insn, operands, 2, 0);"
834 [(set_attr "type" "multi")
835 (set_attr "mode" "DF")])
837 (define_insn "*cmpfp_2_xf"
840 (match_operand:XF 0 "register_operand" "f")
841 (match_operand:XF 1 "register_operand" "f")))]
843 "* return output_fp_compare (insn, operands, 0, 0);"
844 [(set_attr "type" "fcmp")
845 (set_attr "mode" "XF")])
847 (define_insn "*cmpfp_2_xf_1"
848 [(set (match_operand:HI 0 "register_operand" "=a")
851 (match_operand:XF 1 "register_operand" "f")
852 (match_operand:XF 2 "register_operand" "f"))]
855 "* return output_fp_compare (insn, operands, 2, 0);"
856 [(set_attr "type" "multi")
857 (set_attr "mode" "XF")])
859 (define_insn "*cmpfp_2u"
862 (match_operand 0 "register_operand" "f")
863 (match_operand 1 "register_operand" "f")))]
865 && FLOAT_MODE_P (GET_MODE (operands[0]))
866 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
867 "* return output_fp_compare (insn, operands, 0, 1);"
868 [(set_attr "type" "fcmp")
870 (cond [(match_operand:SF 1 "" "")
872 (match_operand:DF 1 "" "")
875 (const_string "XF")))])
877 (define_insn "*cmpfp_2u_1"
878 [(set (match_operand:HI 0 "register_operand" "=a")
881 (match_operand 1 "register_operand" "f")
882 (match_operand 2 "register_operand" "f"))]
885 && FLOAT_MODE_P (GET_MODE (operands[1]))
886 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
887 "* return output_fp_compare (insn, operands, 2, 1);"
888 [(set_attr "type" "multi")
890 (cond [(match_operand:SF 1 "" "")
892 (match_operand:DF 1 "" "")
895 (const_string "XF")))])
897 ;; Patterns to match the SImode-in-memory ficom instructions.
899 ;; %%% Play games with accepting gp registers, as otherwise we have to
900 ;; force them to memory during rtl generation, which is no good. We
901 ;; can get rid of this once we teach reload to do memory input reloads
904 (define_insn "*ficom_1"
907 (match_operand 0 "register_operand" "f,f")
908 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
909 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
910 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
913 ;; Split the not-really-implemented gp register case into a
914 ;; push-op-pop sequence.
916 ;; %%% This is most efficient, but am I gonna get in trouble
917 ;; for separating cc0_setter and cc0_user?
922 (match_operand:SF 0 "register_operand" "")
923 (float (match_operand:SI 1 "register_operand" ""))))]
924 "0 && TARGET_80387 && reload_completed"
925 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
926 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
927 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
928 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
929 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
930 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
932 ;; FP compares, step 2
933 ;; Move the fpsw to ax.
935 (define_insn "*x86_fnstsw_1"
936 [(set (match_operand:HI 0 "register_operand" "=a")
937 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
940 [(set_attr "length" "2")
941 (set_attr "mode" "SI")
942 (set_attr "unit" "i387")
943 (set_attr "ppro_uops" "few")])
945 ;; FP compares, step 3
946 ;; Get ax into flags, general case.
948 (define_insn "x86_sahf_1"
950 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
953 [(set_attr "length" "1")
954 (set_attr "athlon_decode" "vector")
955 (set_attr "mode" "SI")
956 (set_attr "ppro_uops" "one")])
958 ;; Pentium Pro can do steps 1 through 3 in one go.
960 (define_insn "*cmpfp_i"
962 (compare:CCFP (match_operand 0 "register_operand" "f")
963 (match_operand 1 "register_operand" "f")))]
964 "TARGET_80387 && TARGET_CMOVE
965 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
966 && FLOAT_MODE_P (GET_MODE (operands[0]))
967 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
968 "* return output_fp_compare (insn, operands, 1, 0);"
969 [(set_attr "type" "fcmp")
971 (cond [(match_operand:SF 1 "" "")
973 (match_operand:DF 1 "" "")
976 (const_string "XF")))
977 (set_attr "athlon_decode" "vector")])
979 (define_insn "*cmpfp_i_sse"
981 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
982 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
984 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
985 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
986 "* return output_fp_compare (insn, operands, 1, 0);"
987 [(set_attr "type" "fcmp,ssecomi")
989 (if_then_else (match_operand:SF 1 "" "")
991 (const_string "DF")))
992 (set_attr "athlon_decode" "vector")])
994 (define_insn "*cmpfp_i_sse_only"
996 (compare:CCFP (match_operand 0 "register_operand" "x")
997 (match_operand 1 "nonimmediate_operand" "xm")))]
998 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
999 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1000 "* return output_fp_compare (insn, operands, 1, 0);"
1001 [(set_attr "type" "ssecomi")
1003 (if_then_else (match_operand:SF 1 "" "")
1005 (const_string "DF")))
1006 (set_attr "athlon_decode" "vector")])
1008 (define_insn "*cmpfp_iu"
1009 [(set (reg:CCFPU 17)
1010 (compare:CCFPU (match_operand 0 "register_operand" "f")
1011 (match_operand 1 "register_operand" "f")))]
1012 "TARGET_80387 && TARGET_CMOVE
1013 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1014 && FLOAT_MODE_P (GET_MODE (operands[0]))
1015 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1016 "* return output_fp_compare (insn, operands, 1, 1);"
1017 [(set_attr "type" "fcmp")
1019 (cond [(match_operand:SF 1 "" "")
1021 (match_operand:DF 1 "" "")
1024 (const_string "XF")))
1025 (set_attr "athlon_decode" "vector")])
1027 (define_insn "*cmpfp_iu_sse"
1028 [(set (reg:CCFPU 17)
1029 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1030 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1032 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1033 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1034 "* return output_fp_compare (insn, operands, 1, 1);"
1035 [(set_attr "type" "fcmp,ssecomi")
1037 (if_then_else (match_operand:SF 1 "" "")
1039 (const_string "DF")))
1040 (set_attr "athlon_decode" "vector")])
1042 (define_insn "*cmpfp_iu_sse_only"
1043 [(set (reg:CCFPU 17)
1044 (compare:CCFPU (match_operand 0 "register_operand" "x")
1045 (match_operand 1 "nonimmediate_operand" "xm")))]
1046 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1047 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1048 "* return output_fp_compare (insn, operands, 1, 1);"
1049 [(set_attr "type" "ssecomi")
1051 (if_then_else (match_operand:SF 1 "" "")
1053 (const_string "DF")))
1054 (set_attr "athlon_decode" "vector")])
1056 ;; Move instructions.
1058 ;; General case of fullword move.
1060 (define_expand "movsi"
1061 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1062 (match_operand:SI 1 "general_operand" ""))]
1064 "ix86_expand_move (SImode, operands); DONE;")
1066 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1069 ;; %%% We don't use a post-inc memory reference because x86 is not a
1070 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1071 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1072 ;; targets without our curiosities, and it is just as easy to represent
1073 ;; this differently.
1075 (define_insn "*pushsi2"
1076 [(set (match_operand:SI 0 "push_operand" "=<")
1077 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1080 [(set_attr "type" "push")
1081 (set_attr "mode" "SI")])
1083 ;; For 64BIT abi we always round up to 8 bytes.
1084 (define_insn "*pushsi2_rex64"
1085 [(set (match_operand:SI 0 "push_operand" "=X")
1086 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1089 [(set_attr "type" "push")
1090 (set_attr "mode" "SI")])
1092 (define_insn "*pushsi2_prologue"
1093 [(set (match_operand:SI 0 "push_operand" "=<")
1094 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1095 (clobber (mem:BLK (scratch)))]
1098 [(set_attr "type" "push")
1099 (set_attr "mode" "SI")])
1101 (define_insn "*popsi1_epilogue"
1102 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1103 (mem:SI (reg:SI 7)))
1105 (plus:SI (reg:SI 7) (const_int 4)))
1106 (clobber (mem:BLK (scratch)))]
1109 [(set_attr "type" "pop")
1110 (set_attr "mode" "SI")])
1112 (define_insn "popsi1"
1113 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1114 (mem:SI (reg:SI 7)))
1116 (plus:SI (reg:SI 7) (const_int 4)))]
1119 [(set_attr "type" "pop")
1120 (set_attr "mode" "SI")])
1122 (define_insn "*movsi_xor"
1123 [(set (match_operand:SI 0 "register_operand" "=r")
1124 (match_operand:SI 1 "const0_operand" "i"))
1125 (clobber (reg:CC 17))]
1126 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1127 "xor{l}\t{%0, %0|%0, %0}"
1128 [(set_attr "type" "alu1")
1129 (set_attr "mode" "SI")
1130 (set_attr "length_immediate" "0")])
1132 (define_insn "*movsi_or"
1133 [(set (match_operand:SI 0 "register_operand" "=r")
1134 (match_operand:SI 1 "immediate_operand" "i"))
1135 (clobber (reg:CC 17))]
1137 && operands[1] == constm1_rtx
1138 && (TARGET_PENTIUM || optimize_size)"
1140 operands[1] = constm1_rtx;
1141 return "or{l}\t{%1, %0|%0, %1}";
1143 [(set_attr "type" "alu1")
1144 (set_attr "mode" "SI")
1145 (set_attr "length_immediate" "1")])
1147 (define_insn "*movsi_1"
1148 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1149 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
1150 "(TARGET_INTER_UNIT_MOVES || optimize_size)
1151 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1153 switch (get_attr_type (insn))
1156 if (get_attr_mode (insn) == MODE_TI)
1157 return "movdqa\t{%1, %0|%0, %1}";
1158 return "movd\t{%1, %0|%0, %1}";
1161 if (get_attr_mode (insn) == MODE_DI)
1162 return "movq\t{%1, %0|%0, %1}";
1163 return "movd\t{%1, %0|%0, %1}";
1166 return "lea{l}\t{%1, %0|%0, %1}";
1169 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1171 return "mov{l}\t{%1, %0|%0, %1}";
1175 (cond [(eq_attr "alternative" "2,3,4")
1176 (const_string "mmxmov")
1177 (eq_attr "alternative" "5,6,7")
1178 (const_string "ssemov")
1179 (and (ne (symbol_ref "flag_pic") (const_int 0))
1180 (match_operand:SI 1 "symbolic_operand" ""))
1181 (const_string "lea")
1183 (const_string "imov")))
1184 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1186 (define_insn "*movsi_1_nointernunit"
1187 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y")
1188 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))]
1189 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
1190 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1192 switch (get_attr_type (insn))
1195 if (get_attr_mode (insn) == MODE_TI)
1196 return "movdqa\t{%1, %0|%0, %1}";
1197 return "movd\t{%1, %0|%0, %1}";
1200 if (get_attr_mode (insn) == MODE_DI)
1201 return "movq\t{%1, %0|%0, %1}";
1202 return "movd\t{%1, %0|%0, %1}";
1205 return "lea{l}\t{%1, %0|%0, %1}";
1208 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1210 return "mov{l}\t{%1, %0|%0, %1}";
1214 (cond [(eq_attr "alternative" "2,3,4")
1215 (const_string "mmxmov")
1216 (eq_attr "alternative" "5,6,7")
1217 (const_string "ssemov")
1218 (and (ne (symbol_ref "flag_pic") (const_int 0))
1219 (match_operand:SI 1 "symbolic_operand" ""))
1220 (const_string "lea")
1222 (const_string "imov")))
1223 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1225 ;; Stores and loads of ax to arbitrary constant address.
1226 ;; We fake an second form of instruction to force reload to load address
1227 ;; into register when rax is not available
1228 (define_insn "*movabssi_1_rex64"
1229 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1230 (match_operand:SI 1 "nonmemory_operand" "a,er"))]
1231 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1233 movabs{l}\t{%1, %P0|%P0, %1}
1234 mov{l}\t{%1, %a0|%a0, %1}"
1235 [(set_attr "type" "imov")
1236 (set_attr "modrm" "0,*")
1237 (set_attr "length_address" "8,0")
1238 (set_attr "length_immediate" "0,*")
1239 (set_attr "memory" "store")
1240 (set_attr "mode" "SI")])
1242 (define_insn "*movabssi_2_rex64"
1243 [(set (match_operand:SI 0 "register_operand" "=a,r")
1244 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1245 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1247 movabs{l}\t{%P1, %0|%0, %P1}
1248 mov{l}\t{%a1, %0|%0, %a1}"
1249 [(set_attr "type" "imov")
1250 (set_attr "modrm" "0,*")
1251 (set_attr "length_address" "8,0")
1252 (set_attr "length_immediate" "0")
1253 (set_attr "memory" "load")
1254 (set_attr "mode" "SI")])
1256 (define_insn "*swapsi"
1257 [(set (match_operand:SI 0 "register_operand" "+r")
1258 (match_operand:SI 1 "register_operand" "+r"))
1263 [(set_attr "type" "imov")
1264 (set_attr "pent_pair" "np")
1265 (set_attr "athlon_decode" "vector")
1266 (set_attr "mode" "SI")
1267 (set_attr "modrm" "0")
1268 (set_attr "ppro_uops" "few")])
1270 (define_expand "movhi"
1271 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1272 (match_operand:HI 1 "general_operand" ""))]
1274 "ix86_expand_move (HImode, operands); DONE;")
1276 (define_insn "*pushhi2"
1277 [(set (match_operand:HI 0 "push_operand" "=<,<")
1278 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1281 push{w}\t{|WORD PTR }%1
1283 [(set_attr "type" "push")
1284 (set_attr "mode" "HI")])
1286 ;; For 64BIT abi we always round up to 8 bytes.
1287 (define_insn "*pushhi2_rex64"
1288 [(set (match_operand:HI 0 "push_operand" "=X")
1289 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1292 [(set_attr "type" "push")
1293 (set_attr "mode" "QI")])
1295 (define_insn "*movhi_1"
1296 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1297 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1298 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1300 switch (get_attr_type (insn))
1303 /* movzwl is faster than movw on p2 due to partial word stalls,
1304 though not as fast as an aligned movl. */
1305 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1307 if (get_attr_mode (insn) == MODE_SI)
1308 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1310 return "mov{w}\t{%1, %0|%0, %1}";
1314 (cond [(and (eq_attr "alternative" "0")
1315 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1317 (eq (symbol_ref "TARGET_HIMODE_MATH")
1319 (const_string "imov")
1320 (and (eq_attr "alternative" "1,2")
1321 (match_operand:HI 1 "aligned_operand" ""))
1322 (const_string "imov")
1323 (and (ne (symbol_ref "TARGET_MOVX")
1325 (eq_attr "alternative" "0,2"))
1326 (const_string "imovx")
1328 (const_string "imov")))
1330 (cond [(eq_attr "type" "imovx")
1332 (and (eq_attr "alternative" "1,2")
1333 (match_operand:HI 1 "aligned_operand" ""))
1335 (and (eq_attr "alternative" "0")
1336 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1338 (eq (symbol_ref "TARGET_HIMODE_MATH")
1342 (const_string "HI")))])
1344 ;; Stores and loads of ax to arbitrary constant address.
1345 ;; We fake an second form of instruction to force reload to load address
1346 ;; into register when rax is not available
1347 (define_insn "*movabshi_1_rex64"
1348 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1349 (match_operand:HI 1 "nonmemory_operand" "a,er"))]
1350 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1352 movabs{w}\t{%1, %P0|%P0, %1}
1353 mov{w}\t{%1, %a0|%a0, %1}"
1354 [(set_attr "type" "imov")
1355 (set_attr "modrm" "0,*")
1356 (set_attr "length_address" "8,0")
1357 (set_attr "length_immediate" "0,*")
1358 (set_attr "memory" "store")
1359 (set_attr "mode" "HI")])
1361 (define_insn "*movabshi_2_rex64"
1362 [(set (match_operand:HI 0 "register_operand" "=a,r")
1363 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1364 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1366 movabs{w}\t{%P1, %0|%0, %P1}
1367 mov{w}\t{%a1, %0|%0, %a1}"
1368 [(set_attr "type" "imov")
1369 (set_attr "modrm" "0,*")
1370 (set_attr "length_address" "8,0")
1371 (set_attr "length_immediate" "0")
1372 (set_attr "memory" "load")
1373 (set_attr "mode" "HI")])
1375 (define_insn "*swaphi_1"
1376 [(set (match_operand:HI 0 "register_operand" "+r")
1377 (match_operand:HI 1 "register_operand" "+r"))
1380 "TARGET_PARTIAL_REG_STALL"
1382 [(set_attr "type" "imov")
1383 (set_attr "pent_pair" "np")
1384 (set_attr "mode" "HI")
1385 (set_attr "modrm" "0")
1386 (set_attr "ppro_uops" "few")])
1388 (define_insn "*swaphi_2"
1389 [(set (match_operand:HI 0 "register_operand" "+r")
1390 (match_operand:HI 1 "register_operand" "+r"))
1393 "! TARGET_PARTIAL_REG_STALL"
1395 [(set_attr "type" "imov")
1396 (set_attr "pent_pair" "np")
1397 (set_attr "mode" "SI")
1398 (set_attr "modrm" "0")
1399 (set_attr "ppro_uops" "few")])
1401 (define_expand "movstricthi"
1402 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1403 (match_operand:HI 1 "general_operand" ""))]
1404 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1406 /* Don't generate memory->memory moves, go through a register */
1407 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1408 operands[1] = force_reg (HImode, operands[1]);
1411 (define_insn "*movstricthi_1"
1412 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1413 (match_operand:HI 1 "general_operand" "rn,m"))]
1414 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1415 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1416 "mov{w}\t{%1, %0|%0, %1}"
1417 [(set_attr "type" "imov")
1418 (set_attr "mode" "HI")])
1420 (define_insn "*movstricthi_xor"
1421 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1422 (match_operand:HI 1 "const0_operand" "i"))
1423 (clobber (reg:CC 17))]
1425 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1426 "xor{w}\t{%0, %0|%0, %0}"
1427 [(set_attr "type" "alu1")
1428 (set_attr "mode" "HI")
1429 (set_attr "length_immediate" "0")])
1431 (define_expand "movqi"
1432 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1433 (match_operand:QI 1 "general_operand" ""))]
1435 "ix86_expand_move (QImode, operands); DONE;")
1437 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1438 ;; "push a byte". But actually we use pushw, which has the effect
1439 ;; of rounding the amount pushed up to a halfword.
1441 (define_insn "*pushqi2"
1442 [(set (match_operand:QI 0 "push_operand" "=X,X")
1443 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1446 push{w}\t{|word ptr }%1
1448 [(set_attr "type" "push")
1449 (set_attr "mode" "HI")])
1451 ;; For 64BIT abi we always round up to 8 bytes.
1452 (define_insn "*pushqi2_rex64"
1453 [(set (match_operand:QI 0 "push_operand" "=X")
1454 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1457 [(set_attr "type" "push")
1458 (set_attr "mode" "QI")])
1460 ;; Situation is quite tricky about when to choose full sized (SImode) move
1461 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1462 ;; partial register dependency machines (such as AMD Athlon), where QImode
1463 ;; moves issue extra dependency and for partial register stalls machines
1464 ;; that don't use QImode patterns (and QImode move cause stall on the next
1467 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1468 ;; register stall machines with, where we use QImode instructions, since
1469 ;; partial register stall can be caused there. Then we use movzx.
1470 (define_insn "*movqi_1"
1471 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1472 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1473 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1475 switch (get_attr_type (insn))
1478 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1480 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1482 if (get_attr_mode (insn) == MODE_SI)
1483 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1485 return "mov{b}\t{%1, %0|%0, %1}";
1489 (cond [(and (eq_attr "alternative" "3")
1490 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1492 (eq (symbol_ref "TARGET_QIMODE_MATH")
1494 (const_string "imov")
1495 (eq_attr "alternative" "3,5")
1496 (const_string "imovx")
1497 (and (ne (symbol_ref "TARGET_MOVX")
1499 (eq_attr "alternative" "2"))
1500 (const_string "imovx")
1502 (const_string "imov")))
1504 (cond [(eq_attr "alternative" "3,4,5")
1506 (eq_attr "alternative" "6")
1508 (eq_attr "type" "imovx")
1510 (and (eq_attr "type" "imov")
1511 (and (eq_attr "alternative" "0,1,2")
1512 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1515 ;; Avoid partial register stalls when not using QImode arithmetic
1516 (and (eq_attr "type" "imov")
1517 (and (eq_attr "alternative" "0,1,2")
1518 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1520 (eq (symbol_ref "TARGET_QIMODE_MATH")
1524 (const_string "QI")))])
1526 (define_expand "reload_outqi"
1527 [(parallel [(match_operand:QI 0 "" "=m")
1528 (match_operand:QI 1 "register_operand" "r")
1529 (match_operand:QI 2 "register_operand" "=&q")])]
1533 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1535 if (reg_overlap_mentioned_p (op2, op0))
1537 if (! q_regs_operand (op1, QImode))
1539 emit_insn (gen_movqi (op2, op1));
1542 emit_insn (gen_movqi (op0, op1));
1546 (define_insn "*swapqi"
1547 [(set (match_operand:QI 0 "register_operand" "+r")
1548 (match_operand:QI 1 "register_operand" "+r"))
1553 [(set_attr "type" "imov")
1554 (set_attr "pent_pair" "np")
1555 (set_attr "mode" "QI")
1556 (set_attr "modrm" "0")
1557 (set_attr "ppro_uops" "few")])
1559 (define_expand "movstrictqi"
1560 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1561 (match_operand:QI 1 "general_operand" ""))]
1562 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1564 /* Don't generate memory->memory moves, go through a register. */
1565 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1566 operands[1] = force_reg (QImode, operands[1]);
1569 (define_insn "*movstrictqi_1"
1570 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1571 (match_operand:QI 1 "general_operand" "*qn,m"))]
1572 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1573 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1574 "mov{b}\t{%1, %0|%0, %1}"
1575 [(set_attr "type" "imov")
1576 (set_attr "mode" "QI")])
1578 (define_insn "*movstrictqi_xor"
1579 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1580 (match_operand:QI 1 "const0_operand" "i"))
1581 (clobber (reg:CC 17))]
1582 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1583 "xor{b}\t{%0, %0|%0, %0}"
1584 [(set_attr "type" "alu1")
1585 (set_attr "mode" "QI")
1586 (set_attr "length_immediate" "0")])
1588 (define_insn "*movsi_extv_1"
1589 [(set (match_operand:SI 0 "register_operand" "=R")
1590 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1594 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1595 [(set_attr "type" "imovx")
1596 (set_attr "mode" "SI")])
1598 (define_insn "*movhi_extv_1"
1599 [(set (match_operand:HI 0 "register_operand" "=R")
1600 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1604 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1605 [(set_attr "type" "imovx")
1606 (set_attr "mode" "SI")])
1608 (define_insn "*movqi_extv_1"
1609 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1610 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1615 switch (get_attr_type (insn))
1618 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1620 return "mov{b}\t{%h1, %0|%0, %h1}";
1624 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1625 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1626 (ne (symbol_ref "TARGET_MOVX")
1628 (const_string "imovx")
1629 (const_string "imov")))
1631 (if_then_else (eq_attr "type" "imovx")
1633 (const_string "QI")))])
1635 (define_insn "*movqi_extv_1_rex64"
1636 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1637 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1642 switch (get_attr_type (insn))
1645 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1647 return "mov{b}\t{%h1, %0|%0, %h1}";
1651 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1652 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1653 (ne (symbol_ref "TARGET_MOVX")
1655 (const_string "imovx")
1656 (const_string "imov")))
1658 (if_then_else (eq_attr "type" "imovx")
1660 (const_string "QI")))])
1662 ;; Stores and loads of ax to arbitrary constant address.
1663 ;; We fake an second form of instruction to force reload to load address
1664 ;; into register when rax is not available
1665 (define_insn "*movabsqi_1_rex64"
1666 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1667 (match_operand:QI 1 "nonmemory_operand" "a,er"))]
1668 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1670 movabs{b}\t{%1, %P0|%P0, %1}
1671 mov{b}\t{%1, %a0|%a0, %1}"
1672 [(set_attr "type" "imov")
1673 (set_attr "modrm" "0,*")
1674 (set_attr "length_address" "8,0")
1675 (set_attr "length_immediate" "0,*")
1676 (set_attr "memory" "store")
1677 (set_attr "mode" "QI")])
1679 (define_insn "*movabsqi_2_rex64"
1680 [(set (match_operand:QI 0 "register_operand" "=a,r")
1681 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1682 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1684 movabs{b}\t{%P1, %0|%0, %P1}
1685 mov{b}\t{%a1, %0|%0, %a1}"
1686 [(set_attr "type" "imov")
1687 (set_attr "modrm" "0,*")
1688 (set_attr "length_address" "8,0")
1689 (set_attr "length_immediate" "0")
1690 (set_attr "memory" "load")
1691 (set_attr "mode" "QI")])
1693 (define_insn "*movsi_extzv_1"
1694 [(set (match_operand:SI 0 "register_operand" "=R")
1695 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1699 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1700 [(set_attr "type" "imovx")
1701 (set_attr "mode" "SI")])
1703 (define_insn "*movqi_extzv_2"
1704 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1705 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1710 switch (get_attr_type (insn))
1713 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1715 return "mov{b}\t{%h1, %0|%0, %h1}";
1719 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1720 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1721 (ne (symbol_ref "TARGET_MOVX")
1723 (const_string "imovx")
1724 (const_string "imov")))
1726 (if_then_else (eq_attr "type" "imovx")
1728 (const_string "QI")))])
1730 (define_insn "*movqi_extzv_2_rex64"
1731 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1732 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1737 switch (get_attr_type (insn))
1740 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1742 return "mov{b}\t{%h1, %0|%0, %h1}";
1746 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1747 (ne (symbol_ref "TARGET_MOVX")
1749 (const_string "imovx")
1750 (const_string "imov")))
1752 (if_then_else (eq_attr "type" "imovx")
1754 (const_string "QI")))])
1756 (define_insn "movsi_insv_1"
1757 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1760 (match_operand:SI 1 "general_operand" "Qmn"))]
1762 "mov{b}\t{%b1, %h0|%h0, %b1}"
1763 [(set_attr "type" "imov")
1764 (set_attr "mode" "QI")])
1766 (define_insn "*movsi_insv_1_rex64"
1767 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1770 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
1772 "mov{b}\t{%b1, %h0|%h0, %b1}"
1773 [(set_attr "type" "imov")
1774 (set_attr "mode" "QI")])
1776 (define_insn "*movqi_insv_2"
1777 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1780 (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1783 "mov{b}\t{%h1, %h0|%h0, %h1}"
1784 [(set_attr "type" "imov")
1785 (set_attr "mode" "QI")])
1787 (define_expand "movdi"
1788 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1789 (match_operand:DI 1 "general_operand" ""))]
1791 "ix86_expand_move (DImode, operands); DONE;")
1793 (define_insn "*pushdi"
1794 [(set (match_operand:DI 0 "push_operand" "=<")
1795 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1799 (define_insn "pushdi2_rex64"
1800 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1801 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1806 [(set_attr "type" "push,multi")
1807 (set_attr "mode" "DI")])
1809 ;; Convert impossible pushes of immediate to existing instructions.
1810 ;; First try to get scratch register and go through it. In case this
1811 ;; fails, push sign extended lower part first and then overwrite
1812 ;; upper part by 32bit move.
1814 [(match_scratch:DI 2 "r")
1815 (set (match_operand:DI 0 "push_operand" "")
1816 (match_operand:DI 1 "immediate_operand" ""))]
1817 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1818 && !x86_64_immediate_operand (operands[1], DImode)"
1819 [(set (match_dup 2) (match_dup 1))
1820 (set (match_dup 0) (match_dup 2))]
1823 ;; We need to define this as both peepholer and splitter for case
1824 ;; peephole2 pass is not run.
1826 [(set (match_operand:DI 0 "push_operand" "")
1827 (match_operand:DI 1 "immediate_operand" ""))]
1828 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1829 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1830 [(set (match_dup 0) (match_dup 1))
1831 (set (match_dup 2) (match_dup 3))]
1832 "split_di (operands + 1, 1, operands + 2, operands + 3);
1833 operands[1] = gen_lowpart (DImode, operands[2]);
1834 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1839 [(set (match_operand:DI 0 "push_operand" "")
1840 (match_operand:DI 1 "immediate_operand" ""))]
1841 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1842 && !symbolic_operand (operands[1], DImode)
1843 && !x86_64_immediate_operand (operands[1], DImode)"
1844 [(set (match_dup 0) (match_dup 1))
1845 (set (match_dup 2) (match_dup 3))]
1846 "split_di (operands + 1, 1, operands + 2, operands + 3);
1847 operands[1] = gen_lowpart (DImode, operands[2]);
1848 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1852 (define_insn "*pushdi2_prologue_rex64"
1853 [(set (match_operand:DI 0 "push_operand" "=<")
1854 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1855 (clobber (mem:BLK (scratch)))]
1858 [(set_attr "type" "push")
1859 (set_attr "mode" "DI")])
1861 (define_insn "*popdi1_epilogue_rex64"
1862 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1863 (mem:DI (reg:DI 7)))
1865 (plus:DI (reg:DI 7) (const_int 8)))
1866 (clobber (mem:BLK (scratch)))]
1869 [(set_attr "type" "pop")
1870 (set_attr "mode" "DI")])
1872 (define_insn "popdi1"
1873 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1874 (mem:DI (reg:DI 7)))
1876 (plus:DI (reg:DI 7) (const_int 8)))]
1879 [(set_attr "type" "pop")
1880 (set_attr "mode" "DI")])
1882 (define_insn "*movdi_xor_rex64"
1883 [(set (match_operand:DI 0 "register_operand" "=r")
1884 (match_operand:DI 1 "const0_operand" "i"))
1885 (clobber (reg:CC 17))]
1886 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1887 && reload_completed"
1888 "xor{l}\t{%k0, %k0|%k0, %k0}"
1889 [(set_attr "type" "alu1")
1890 (set_attr "mode" "SI")
1891 (set_attr "length_immediate" "0")])
1893 (define_insn "*movdi_or_rex64"
1894 [(set (match_operand:DI 0 "register_operand" "=r")
1895 (match_operand:DI 1 "const_int_operand" "i"))
1896 (clobber (reg:CC 17))]
1897 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1899 && operands[1] == constm1_rtx"
1901 operands[1] = constm1_rtx;
1902 return "or{q}\t{%1, %0|%0, %1}";
1904 [(set_attr "type" "alu1")
1905 (set_attr "mode" "DI")
1906 (set_attr "length_immediate" "1")])
1908 (define_insn "*movdi_2"
1909 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1910 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1912 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1916 movq\t{%1, %0|%0, %1}
1917 movq\t{%1, %0|%0, %1}
1918 movq\t{%1, %0|%0, %1}
1919 movdqa\t{%1, %0|%0, %1}
1920 movq\t{%1, %0|%0, %1}"
1921 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1922 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1925 [(set (match_operand:DI 0 "push_operand" "")
1926 (match_operand:DI 1 "general_operand" ""))]
1927 "!TARGET_64BIT && reload_completed
1928 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1930 "ix86_split_long_move (operands); DONE;")
1932 ;; %%% This multiword shite has got to go.
1934 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1935 (match_operand:DI 1 "general_operand" ""))]
1936 "!TARGET_64BIT && reload_completed
1937 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1938 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1940 "ix86_split_long_move (operands); DONE;")
1942 (define_insn "*movdi_1_rex64"
1943 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y")
1944 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm"))]
1946 && (TARGET_INTER_UNIT_MOVES || optimize_size)
1947 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1949 switch (get_attr_type (insn))
1952 if (get_attr_mode (insn) == MODE_TI)
1953 return "movdqa\t{%1, %0|%0, %1}";
1956 /* Moves from and into integer register is done using movd opcode with
1958 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1959 return "movd\t{%1, %0|%0, %1}";
1960 return "movq\t{%1, %0|%0, %1}";
1964 return "lea{q}\t{%a1, %0|%0, %a1}";
1966 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1968 if (get_attr_mode (insn) == MODE_SI)
1969 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1970 else if (which_alternative == 2)
1971 return "movabs{q}\t{%1, %0|%0, %1}";
1973 return "mov{q}\t{%1, %0|%0, %1}";
1977 (cond [(eq_attr "alternative" "5,6,7")
1978 (const_string "mmxmov")
1979 (eq_attr "alternative" "8,9,10")
1980 (const_string "ssemov")
1981 (eq_attr "alternative" "4")
1982 (const_string "multi")
1983 (and (ne (symbol_ref "flag_pic") (const_int 0))
1984 (match_operand:DI 1 "symbolic_operand" ""))
1985 (const_string "lea")
1987 (const_string "imov")))
1988 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
1989 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
1990 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
1992 (define_insn "*movdi_1_rex64_nointerunit"
1993 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
1994 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,m,*Y,*Y,m"))]
1996 && (!TARGET_INTER_UNIT_MOVES && !optimize_size)
1997 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1999 switch (get_attr_type (insn))
2002 if (get_attr_mode (insn) == MODE_TI)
2003 return "movdqa\t{%1, %0|%0, %1}";
2006 return "movq\t{%1, %0|%0, %1}";
2010 return "lea{q}\t{%a1, %0|%0, %a1}";
2012 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2014 if (get_attr_mode (insn) == MODE_SI)
2015 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2016 else if (which_alternative == 2)
2017 return "movabs{q}\t{%1, %0|%0, %1}";
2019 return "mov{q}\t{%1, %0|%0, %1}";
2023 (cond [(eq_attr "alternative" "5,6,7")
2024 (const_string "mmxmov")
2025 (eq_attr "alternative" "8,9,10")
2026 (const_string "ssemov")
2027 (eq_attr "alternative" "4")
2028 (const_string "multi")
2029 (and (ne (symbol_ref "flag_pic") (const_int 0))
2030 (match_operand:DI 1 "symbolic_operand" ""))
2031 (const_string "lea")
2033 (const_string "imov")))
2034 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2035 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2036 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2038 ;; Stores and loads of ax to arbitrary constant address.
2039 ;; We fake an second form of instruction to force reload to load address
2040 ;; into register when rax is not available
2041 (define_insn "*movabsdi_1_rex64"
2042 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
2043 (match_operand:DI 1 "nonmemory_operand" "a,er"))]
2044 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
2046 movabs{q}\t{%1, %P0|%P0, %1}
2047 mov{q}\t{%1, %a0|%a0, %1}"
2048 [(set_attr "type" "imov")
2049 (set_attr "modrm" "0,*")
2050 (set_attr "length_address" "8,0")
2051 (set_attr "length_immediate" "0,*")
2052 (set_attr "memory" "store")
2053 (set_attr "mode" "DI")])
2055 (define_insn "*movabsdi_2_rex64"
2056 [(set (match_operand:DI 0 "register_operand" "=a,r")
2057 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2058 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
2060 movabs{q}\t{%P1, %0|%0, %P1}
2061 mov{q}\t{%a1, %0|%0, %a1}"
2062 [(set_attr "type" "imov")
2063 (set_attr "modrm" "0,*")
2064 (set_attr "length_address" "8,0")
2065 (set_attr "length_immediate" "0")
2066 (set_attr "memory" "load")
2067 (set_attr "mode" "DI")])
2069 ;; Convert impossible stores of immediate to existing instructions.
2070 ;; First try to get scratch register and go through it. In case this
2071 ;; fails, move by 32bit parts.
2073 [(match_scratch:DI 2 "r")
2074 (set (match_operand:DI 0 "memory_operand" "")
2075 (match_operand:DI 1 "immediate_operand" ""))]
2076 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2077 && !x86_64_immediate_operand (operands[1], DImode)"
2078 [(set (match_dup 2) (match_dup 1))
2079 (set (match_dup 0) (match_dup 2))]
2082 ;; We need to define this as both peepholer and splitter for case
2083 ;; peephole2 pass is not run.
2085 [(set (match_operand:DI 0 "memory_operand" "")
2086 (match_operand:DI 1 "immediate_operand" ""))]
2087 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2088 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2089 [(set (match_dup 2) (match_dup 3))
2090 (set (match_dup 4) (match_dup 5))]
2091 "split_di (operands, 2, operands + 2, operands + 4);")
2094 [(set (match_operand:DI 0 "memory_operand" "")
2095 (match_operand:DI 1 "immediate_operand" ""))]
2096 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2097 && !symbolic_operand (operands[1], DImode)
2098 && !x86_64_immediate_operand (operands[1], DImode)"
2099 [(set (match_dup 2) (match_dup 3))
2100 (set (match_dup 4) (match_dup 5))]
2101 "split_di (operands, 2, operands + 2, operands + 4);")
2103 (define_insn "*swapdi_rex64"
2104 [(set (match_operand:DI 0 "register_operand" "+r")
2105 (match_operand:DI 1 "register_operand" "+r"))
2110 [(set_attr "type" "imov")
2111 (set_attr "pent_pair" "np")
2112 (set_attr "athlon_decode" "vector")
2113 (set_attr "mode" "DI")
2114 (set_attr "modrm" "0")
2115 (set_attr "ppro_uops" "few")])
2118 (define_expand "movsf"
2119 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2120 (match_operand:SF 1 "general_operand" ""))]
2122 "ix86_expand_move (SFmode, operands); DONE;")
2124 (define_insn "*pushsf"
2125 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2126 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2129 switch (which_alternative)
2132 return "push{l}\t%1";
2135 /* This insn should be already split before reg-stack. */
2139 [(set_attr "type" "multi,push,multi")
2140 (set_attr "mode" "SF,SI,SF")])
2142 (define_insn "*pushsf_rex64"
2143 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2144 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2147 switch (which_alternative)
2150 return "push{q}\t%q1";
2153 /* This insn should be already split before reg-stack. */
2157 [(set_attr "type" "multi,push,multi")
2158 (set_attr "mode" "SF,DI,SF")])
2161 [(set (match_operand:SF 0 "push_operand" "")
2162 (match_operand:SF 1 "memory_operand" ""))]
2164 && GET_CODE (operands[1]) == MEM
2165 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2166 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2169 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2172 ;; %%% Kill this when call knows how to work this out.
2174 [(set (match_operand:SF 0 "push_operand" "")
2175 (match_operand:SF 1 "any_fp_register_operand" ""))]
2177 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2178 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2181 [(set (match_operand:SF 0 "push_operand" "")
2182 (match_operand:SF 1 "any_fp_register_operand" ""))]
2184 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2185 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2187 (define_insn "*movsf_1"
2188 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2189 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
2190 "(TARGET_INTER_UNIT_MOVES || optimize_size)
2191 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2192 && (reload_in_progress || reload_completed
2193 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2194 || GET_CODE (operands[1]) != CONST_DOUBLE
2195 || memory_operand (operands[0], SFmode))"
2197 switch (which_alternative)
2200 if (REG_P (operands[1])
2201 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2203 else if (STACK_TOP_P (operands[0]))
2204 return "fld%z1\t%y1";
2209 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2210 return "fstp%z0\t%y0";
2212 return "fst%z0\t%y0";
2215 return standard_80387_constant_opcode (operands[1]);
2219 return "mov{l}\t{%1, %0|%0, %1}";
2221 if (get_attr_mode (insn) == MODE_TI)
2222 return "pxor\t%0, %0";
2224 return "xorps\t%0, %0";
2226 if (get_attr_mode (insn) == MODE_V4SF)
2227 return "movaps\t{%1, %0|%0, %1}";
2229 return "movss\t{%1, %0|%0, %1}";
2232 return "movss\t{%1, %0|%0, %1}";
2236 return "movd\t{%1, %0|%0, %1}";
2239 return "movq\t{%1, %0|%0, %1}";
2245 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2247 (cond [(eq_attr "alternative" "3,4,9,10")
2249 (eq_attr "alternative" "5")
2251 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2253 (ne (symbol_ref "TARGET_SSE2")
2255 (eq (symbol_ref "optimize_size")
2258 (const_string "V4SF"))
2259 /* For architectures resolving dependencies on
2260 whole SSE registers use APS move to break dependency
2261 chains, otherwise use short move to avoid extra work.
2263 Do the same for architectures resolving dependencies on
2264 the parts. While in DF mode it is better to always handle
2265 just register parts, the SF mode is different due to lack
2266 of instructions to load just part of the register. It is
2267 better to maintain the whole registers in single format
2268 to avoid problems on using packed logical operations. */
2269 (eq_attr "alternative" "6")
2271 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2273 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2275 (const_string "V4SF")
2276 (const_string "SF"))
2277 (eq_attr "alternative" "11")
2278 (const_string "DI")]
2279 (const_string "SF")))])
2281 (define_insn "*movsf_1_nointerunit"
2282 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!m,!*y")
2283 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,m,*y,*y"))]
2284 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
2285 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2286 && (reload_in_progress || reload_completed
2287 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2288 || GET_CODE (operands[1]) != CONST_DOUBLE
2289 || memory_operand (operands[0], SFmode))"
2291 switch (which_alternative)
2294 if (REG_P (operands[1])
2295 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2297 if (REGNO (operands[0]) == FIRST_STACK_REG
2298 && TARGET_USE_FFREEP)
2299 return "ffreep\t%y0";
2302 else if (STACK_TOP_P (operands[0]))
2303 return "fld%z1\t%y1";
2308 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2309 return "fstp%z0\t%y0";
2311 return "fst%z0\t%y0";
2314 return standard_80387_constant_opcode (operands[1]);
2318 return "mov{l}\t{%1, %0|%0, %1}";
2320 if (get_attr_mode (insn) == MODE_TI)
2321 return "pxor\t%0, %0";
2323 return "xorps\t%0, %0";
2325 if (get_attr_mode (insn) == MODE_V4SF)
2326 return "movaps\t{%1, %0|%0, %1}";
2328 return "movss\t{%1, %0|%0, %1}";
2331 return "movss\t{%1, %0|%0, %1}";
2335 return "movd\t{%1, %0|%0, %1}";
2338 return "movq\t{%1, %0|%0, %1}";
2344 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2346 (cond [(eq_attr "alternative" "3,4,9,10")
2348 (eq_attr "alternative" "5")
2350 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2352 (ne (symbol_ref "TARGET_SSE2")
2354 (eq (symbol_ref "optimize_size")
2357 (const_string "V4SF"))
2358 /* For architectures resolving dependencies on
2359 whole SSE registers use APS move to break dependency
2360 chains, otherwise use short move to avoid extra work.
2362 Do the same for architectures resolving dependencies on
2363 the parts. While in DF mode it is better to always handle
2364 just register parts, the SF mode is different due to lack
2365 of instructions to load just part of the register. It is
2366 better to maintain the whole registers in single format
2367 to avoid problems on using packed logical operations. */
2368 (eq_attr "alternative" "6")
2370 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2372 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2374 (const_string "V4SF")
2375 (const_string "SF"))
2376 (eq_attr "alternative" "11")
2377 (const_string "DI")]
2378 (const_string "SF")))])
2380 (define_insn "*swapsf"
2381 [(set (match_operand:SF 0 "register_operand" "+f")
2382 (match_operand:SF 1 "register_operand" "+f"))
2385 "reload_completed || !TARGET_SSE"
2387 if (STACK_TOP_P (operands[0]))
2392 [(set_attr "type" "fxch")
2393 (set_attr "mode" "SF")])
2395 (define_expand "movdf"
2396 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2397 (match_operand:DF 1 "general_operand" ""))]
2399 "ix86_expand_move (DFmode, operands); DONE;")
2401 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2402 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2403 ;; On the average, pushdf using integers can be still shorter. Allow this
2404 ;; pattern for optimize_size too.
2406 (define_insn "*pushdf_nointeger"
2407 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2408 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2409 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2411 /* This insn should be already split before reg-stack. */
2414 [(set_attr "type" "multi")
2415 (set_attr "mode" "DF,SI,SI,DF")])
2417 (define_insn "*pushdf_integer"
2418 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2419 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2420 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2422 /* This insn should be already split before reg-stack. */
2425 [(set_attr "type" "multi")
2426 (set_attr "mode" "DF,SI,DF")])
2428 ;; %%% Kill this when call knows how to work this out.
2430 [(set (match_operand:DF 0 "push_operand" "")
2431 (match_operand:DF 1 "any_fp_register_operand" ""))]
2432 "!TARGET_64BIT && reload_completed"
2433 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2434 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2438 [(set (match_operand:DF 0 "push_operand" "")
2439 (match_operand:DF 1 "any_fp_register_operand" ""))]
2440 "TARGET_64BIT && reload_completed"
2441 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2442 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2446 [(set (match_operand:DF 0 "push_operand" "")
2447 (match_operand:DF 1 "general_operand" ""))]
2450 "ix86_split_long_move (operands); DONE;")
2452 ;; Moving is usually shorter when only FP registers are used. This separate
2453 ;; movdf pattern avoids the use of integer registers for FP operations
2454 ;; when optimizing for size.
2456 (define_insn "*movdf_nointeger"
2457 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2458 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
2459 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2460 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2461 && (reload_in_progress || reload_completed
2462 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2463 || GET_CODE (operands[1]) != CONST_DOUBLE
2464 || memory_operand (operands[0], DFmode))"
2466 switch (which_alternative)
2469 if (REG_P (operands[1])
2470 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2472 if (REGNO (operands[0]) == FIRST_STACK_REG
2473 && TARGET_USE_FFREEP)
2474 return "ffreep\t%y0";
2477 else if (STACK_TOP_P (operands[0]))
2478 return "fld%z1\t%y1";
2483 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2484 return "fstp%z0\t%y0";
2486 return "fst%z0\t%y0";
2489 return standard_80387_constant_opcode (operands[1]);
2495 switch (get_attr_mode (insn))
2498 return "xorps\t%0, %0";
2500 return "xorpd\t%0, %0";
2502 return "pxor\t%0, %0";
2507 switch (get_attr_mode (insn))
2510 return "movaps\t{%1, %0|%0, %1}";
2512 return "movapd\t{%1, %0|%0, %1}";
2514 return "movsd\t{%1, %0|%0, %1}";
2519 if (get_attr_mode (insn) == MODE_V2DF)
2520 return "movlpd\t{%1, %0|%0, %1}";
2522 return "movsd\t{%1, %0|%0, %1}";
2524 return "movsd\t{%1, %0|%0, %1}";
2530 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2532 (cond [(eq_attr "alternative" "3,4")
2534 /* xorps is one byte shorter. */
2535 (eq_attr "alternative" "5")
2536 (cond [(ne (symbol_ref "optimize_size")
2538 (const_string "V4SF")
2539 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2541 (const_string "TI")]
2542 (const_string "V2DF"))
2543 /* For architectures resolving dependencies on
2544 whole SSE registers use APD move to break dependency
2545 chains, otherwise use short move to avoid extra work.
2547 movaps encodes one byte shorter. */
2548 (eq_attr "alternative" "6")
2550 [(ne (symbol_ref "optimize_size")
2552 (const_string "V4SF")
2553 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2555 (const_string "V2DF")]
2556 (const_string "DF"))
2557 /* For architectures resolving dependencies on register
2558 parts we may avoid extra work to zero out upper part
2560 (eq_attr "alternative" "7")
2562 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2564 (const_string "V2DF")
2565 (const_string "DF"))]
2566 (const_string "DF")))])
2568 (define_insn "*movdf_integer"
2569 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2570 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
2571 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2572 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2573 && (reload_in_progress || reload_completed
2574 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2575 || GET_CODE (operands[1]) != CONST_DOUBLE
2576 || memory_operand (operands[0], DFmode))"
2578 switch (which_alternative)
2581 if (REG_P (operands[1])
2582 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2584 if (REGNO (operands[0]) == FIRST_STACK_REG
2585 && TARGET_USE_FFREEP)
2586 return "ffreep\t%y0";
2589 else if (STACK_TOP_P (operands[0]))
2590 return "fld%z1\t%y1";
2595 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2596 return "fstp%z0\t%y0";
2598 return "fst%z0\t%y0";
2601 return standard_80387_constant_opcode (operands[1]);
2608 switch (get_attr_mode (insn))
2611 return "xorps\t%0, %0";
2613 return "xorpd\t%0, %0";
2615 return "pxor\t%0, %0";
2620 switch (get_attr_mode (insn))
2623 return "movaps\t{%1, %0|%0, %1}";
2625 return "movapd\t{%1, %0|%0, %1}";
2627 return "movsd\t{%1, %0|%0, %1}";
2632 if (get_attr_mode (insn) == MODE_V2DF)
2633 return "movlpd\t{%1, %0|%0, %1}";
2635 return "movsd\t{%1, %0|%0, %1}";
2637 return "movsd\t{%1, %0|%0, %1}";
2643 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2645 (cond [(eq_attr "alternative" "3,4")
2647 /* xorps is one byte shorter. */
2648 (eq_attr "alternative" "5")
2649 (cond [(ne (symbol_ref "optimize_size")
2651 (const_string "V4SF")
2652 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2654 (const_string "TI")]
2655 (const_string "V2DF"))
2656 /* For architectures resolving dependencies on
2657 whole SSE registers use APD move to break dependency
2658 chains, otherwise use short move to avoid extra work.
2660 movaps encodes one byte shorter. */
2661 (eq_attr "alternative" "6")
2663 [(ne (symbol_ref "optimize_size")
2665 (const_string "V4SF")
2666 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2668 (const_string "V2DF")]
2669 (const_string "DF"))
2670 /* For architectures resolving dependencies on register
2671 parts we may avoid extra work to zero out upper part
2673 (eq_attr "alternative" "7")
2675 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2677 (const_string "V2DF")
2678 (const_string "DF"))]
2679 (const_string "DF")))])
2682 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2683 (match_operand:DF 1 "general_operand" ""))]
2685 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2686 && ! (ANY_FP_REG_P (operands[0]) ||
2687 (GET_CODE (operands[0]) == SUBREG
2688 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2689 && ! (ANY_FP_REG_P (operands[1]) ||
2690 (GET_CODE (operands[1]) == SUBREG
2691 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2693 "ix86_split_long_move (operands); DONE;")
2695 (define_insn "*swapdf"
2696 [(set (match_operand:DF 0 "register_operand" "+f")
2697 (match_operand:DF 1 "register_operand" "+f"))
2700 "reload_completed || !TARGET_SSE2"
2702 if (STACK_TOP_P (operands[0]))
2707 [(set_attr "type" "fxch")
2708 (set_attr "mode" "DF")])
2710 (define_expand "movxf"
2711 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2712 (match_operand:XF 1 "general_operand" ""))]
2714 "ix86_expand_move (XFmode, operands); DONE;")
2716 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2717 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2718 ;; Pushing using integer instructions is longer except for constants
2719 ;; and direct memory references.
2720 ;; (assuming that any given constant is pushed only once, but this ought to be
2721 ;; handled elsewhere).
2723 (define_insn "*pushxf_nointeger"
2724 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2725 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2728 /* This insn should be already split before reg-stack. */
2731 [(set_attr "type" "multi")
2732 (set_attr "mode" "XF,SI,SI")])
2734 (define_insn "*pushxf_integer"
2735 [(set (match_operand:XF 0 "push_operand" "=<,<")
2736 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2739 /* This insn should be already split before reg-stack. */
2742 [(set_attr "type" "multi")
2743 (set_attr "mode" "XF,SI")])
2746 [(set (match_operand 0 "push_operand" "")
2747 (match_operand 1 "general_operand" ""))]
2749 && (GET_MODE (operands[0]) == XFmode
2750 || GET_MODE (operands[0]) == DFmode)
2751 && !ANY_FP_REG_P (operands[1])"
2753 "ix86_split_long_move (operands); DONE;")
2756 [(set (match_operand:XF 0 "push_operand" "")
2757 (match_operand:XF 1 "any_fp_register_operand" ""))]
2759 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
2760 (set (mem:XF (reg:SI 7)) (match_dup 1))]
2761 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2764 [(set (match_operand:XF 0 "push_operand" "")
2765 (match_operand:XF 1 "any_fp_register_operand" ""))]
2767 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
2768 (set (mem:XF (reg:DI 7)) (match_dup 1))]
2769 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2771 ;; Do not use integer registers when optimizing for size
2772 (define_insn "*movxf_nointeger"
2773 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2774 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2776 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2777 && (reload_in_progress || reload_completed
2778 || GET_CODE (operands[1]) != CONST_DOUBLE
2779 || memory_operand (operands[0], XFmode))"
2781 switch (which_alternative)
2784 if (REG_P (operands[1])
2785 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2787 if (REGNO (operands[0]) == FIRST_STACK_REG
2788 && TARGET_USE_FFREEP)
2789 return "ffreep\t%y0";
2792 else if (STACK_TOP_P (operands[0]))
2793 return "fld%z1\t%y1";
2798 /* There is no non-popping store to memory for XFmode. So if
2799 we need one, follow the store with a load. */
2800 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2801 return "fstp%z0\t%y0\;fld%z0\t%y0";
2803 return "fstp%z0\t%y0";
2806 return standard_80387_constant_opcode (operands[1]);
2813 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2814 (set_attr "mode" "XF,XF,XF,SI,SI")])
2816 (define_insn "*movxf_integer"
2817 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2818 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2820 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2821 && (reload_in_progress || reload_completed
2822 || GET_CODE (operands[1]) != CONST_DOUBLE
2823 || memory_operand (operands[0], XFmode))"
2825 switch (which_alternative)
2828 if (REG_P (operands[1])
2829 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2831 if (REGNO (operands[0]) == FIRST_STACK_REG
2832 && TARGET_USE_FFREEP)
2833 return "ffreep\t%y0";
2836 else if (STACK_TOP_P (operands[0]))
2837 return "fld%z1\t%y1";
2842 /* There is no non-popping store to memory for XFmode. So if
2843 we need one, follow the store with a load. */
2844 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2845 return "fstp%z0\t%y0\;fld%z0\t%y0";
2847 return "fstp%z0\t%y0";
2850 return standard_80387_constant_opcode (operands[1]);
2857 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2858 (set_attr "mode" "XF,XF,XF,SI,SI")])
2861 [(set (match_operand 0 "nonimmediate_operand" "")
2862 (match_operand 1 "general_operand" ""))]
2864 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2865 && GET_MODE (operands[0]) == XFmode
2866 && ! (ANY_FP_REG_P (operands[0]) ||
2867 (GET_CODE (operands[0]) == SUBREG
2868 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2869 && ! (ANY_FP_REG_P (operands[1]) ||
2870 (GET_CODE (operands[1]) == SUBREG
2871 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2873 "ix86_split_long_move (operands); DONE;")
2876 [(set (match_operand 0 "register_operand" "")
2877 (match_operand 1 "memory_operand" ""))]
2879 && GET_CODE (operands[1]) == MEM
2880 && (GET_MODE (operands[0]) == XFmode
2881 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2882 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2883 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2884 [(set (match_dup 0) (match_dup 1))]
2886 rtx c = get_pool_constant (XEXP (operands[1], 0));
2887 rtx r = operands[0];
2889 if (GET_CODE (r) == SUBREG)
2894 if (!standard_sse_constant_p (c))
2897 else if (FP_REG_P (r))
2899 if (!standard_80387_constant_p (c))
2902 else if (MMX_REG_P (r))
2908 (define_insn "swapxf"
2909 [(set (match_operand:XF 0 "register_operand" "+f")
2910 (match_operand:XF 1 "register_operand" "+f"))
2915 if (STACK_TOP_P (operands[0]))
2920 [(set_attr "type" "fxch")
2921 (set_attr "mode" "XF")])
2923 ;; Zero extension instructions
2925 (define_expand "zero_extendhisi2"
2926 [(set (match_operand:SI 0 "register_operand" "")
2927 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2930 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2932 operands[1] = force_reg (HImode, operands[1]);
2933 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2938 (define_insn "zero_extendhisi2_and"
2939 [(set (match_operand:SI 0 "register_operand" "=r")
2940 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2941 (clobber (reg:CC 17))]
2942 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2944 [(set_attr "type" "alu1")
2945 (set_attr "mode" "SI")])
2948 [(set (match_operand:SI 0 "register_operand" "")
2949 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
2950 (clobber (reg:CC 17))]
2951 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2952 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
2953 (clobber (reg:CC 17))])]
2956 (define_insn "*zero_extendhisi2_movzwl"
2957 [(set (match_operand:SI 0 "register_operand" "=r")
2958 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2959 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2960 "movz{wl|x}\t{%1, %0|%0, %1}"
2961 [(set_attr "type" "imovx")
2962 (set_attr "mode" "SI")])
2964 (define_expand "zero_extendqihi2"
2966 [(set (match_operand:HI 0 "register_operand" "")
2967 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2968 (clobber (reg:CC 17))])]
2972 (define_insn "*zero_extendqihi2_and"
2973 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
2974 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2975 (clobber (reg:CC 17))]
2976 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2978 [(set_attr "type" "alu1")
2979 (set_attr "mode" "HI")])
2981 (define_insn "*zero_extendqihi2_movzbw_and"
2982 [(set (match_operand:HI 0 "register_operand" "=r,r")
2983 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2984 (clobber (reg:CC 17))]
2985 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2987 [(set_attr "type" "imovx,alu1")
2988 (set_attr "mode" "HI")])
2990 (define_insn "*zero_extendqihi2_movzbw"
2991 [(set (match_operand:HI 0 "register_operand" "=r")
2992 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2993 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2994 "movz{bw|x}\t{%1, %0|%0, %1}"
2995 [(set_attr "type" "imovx")
2996 (set_attr "mode" "HI")])
2998 ;; For the movzbw case strip only the clobber
3000 [(set (match_operand:HI 0 "register_operand" "")
3001 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3002 (clobber (reg:CC 17))]
3004 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3005 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3006 [(set (match_operand:HI 0 "register_operand" "")
3007 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3009 ;; When source and destination does not overlap, clear destination
3010 ;; first and then do the movb
3012 [(set (match_operand:HI 0 "register_operand" "")
3013 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3014 (clobber (reg:CC 17))]
3016 && ANY_QI_REG_P (operands[0])
3017 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3018 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3019 [(set (match_dup 0) (const_int 0))
3020 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3021 "operands[2] = gen_lowpart (QImode, operands[0]);")
3023 ;; Rest is handled by single and.
3025 [(set (match_operand:HI 0 "register_operand" "")
3026 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3027 (clobber (reg:CC 17))]
3029 && true_regnum (operands[0]) == true_regnum (operands[1])"
3030 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3031 (clobber (reg:CC 17))])]
3034 (define_expand "zero_extendqisi2"
3036 [(set (match_operand:SI 0 "register_operand" "")
3037 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3038 (clobber (reg:CC 17))])]
3042 (define_insn "*zero_extendqisi2_and"
3043 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3044 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3045 (clobber (reg:CC 17))]
3046 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3048 [(set_attr "type" "alu1")
3049 (set_attr "mode" "SI")])
3051 (define_insn "*zero_extendqisi2_movzbw_and"
3052 [(set (match_operand:SI 0 "register_operand" "=r,r")
3053 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3054 (clobber (reg:CC 17))]
3055 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3057 [(set_attr "type" "imovx,alu1")
3058 (set_attr "mode" "SI")])
3060 (define_insn "*zero_extendqisi2_movzbw"
3061 [(set (match_operand:SI 0 "register_operand" "=r")
3062 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3063 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3064 "movz{bl|x}\t{%1, %0|%0, %1}"
3065 [(set_attr "type" "imovx")
3066 (set_attr "mode" "SI")])
3068 ;; For the movzbl case strip only the clobber
3070 [(set (match_operand:SI 0 "register_operand" "")
3071 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3072 (clobber (reg:CC 17))]
3074 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3075 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3077 (zero_extend:SI (match_dup 1)))])
3079 ;; When source and destination does not overlap, clear destination
3080 ;; first and then do the movb
3082 [(set (match_operand:SI 0 "register_operand" "")
3083 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3084 (clobber (reg:CC 17))]
3086 && ANY_QI_REG_P (operands[0])
3087 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3088 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3089 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3090 [(set (match_dup 0) (const_int 0))
3091 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3092 "operands[2] = gen_lowpart (QImode, operands[0]);")
3094 ;; Rest is handled by single and.
3096 [(set (match_operand:SI 0 "register_operand" "")
3097 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3098 (clobber (reg:CC 17))]
3100 && true_regnum (operands[0]) == true_regnum (operands[1])"
3101 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3102 (clobber (reg:CC 17))])]
3105 ;; %%% Kill me once multi-word ops are sane.
3106 (define_expand "zero_extendsidi2"
3107 [(set (match_operand:DI 0 "register_operand" "=r")
3108 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3112 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3117 (define_insn "zero_extendsidi2_32"
3118 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3119 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m")))
3120 (clobber (reg:CC 17))]
3121 "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3126 movd\t{%1, %0|%0, %1}
3127 movd\t{%1, %0|%0, %1}"
3128 [(set_attr "mode" "SI,SI,SI,DI,TI")
3129 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3131 (define_insn "*zero_extendsidi2_32_1"
3132 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3133 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
3134 (clobber (reg:CC 17))]
3135 "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3140 movd\t{%1, %0|%0, %1}
3141 movd\t{%1, %0|%0, %1}"
3142 [(set_attr "mode" "SI,SI,SI,DI,TI")
3143 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3145 (define_insn "zero_extendsidi2_rex64"
3146 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y")
3147 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))]
3148 "TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3150 mov\t{%k1, %k0|%k0, %k1}
3152 movd\t{%1, %0|%0, %1}
3153 movd\t{%1, %0|%0, %1}"
3154 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3155 (set_attr "mode" "SI,DI,DI,TI")])
3157 (define_insn "*zero_extendsidi2_rex64_1"
3158 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!*?")
3159 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))]
3160 "TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3162 mov\t{%k1, %k0|%k0, %k1}
3164 movd\t{%1, %0|%0, %1}
3165 movd\t{%1, %0|%0, %1}"
3166 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3167 (set_attr "mode" "SI,DI,SI,SI")])
3170 [(set (match_operand:DI 0 "memory_operand" "")
3171 (zero_extend:DI (match_dup 0)))]
3173 [(set (match_dup 4) (const_int 0))]
3174 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3177 [(set (match_operand:DI 0 "register_operand" "")
3178 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3179 (clobber (reg:CC 17))]
3180 "!TARGET_64BIT && reload_completed
3181 && true_regnum (operands[0]) == true_regnum (operands[1])"
3182 [(set (match_dup 4) (const_int 0))]
3183 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3186 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3187 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3188 (clobber (reg:CC 17))]
3189 "!TARGET_64BIT && reload_completed
3190 && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
3191 [(set (match_dup 3) (match_dup 1))
3192 (set (match_dup 4) (const_int 0))]
3193 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3195 (define_insn "zero_extendhidi2"
3196 [(set (match_operand:DI 0 "register_operand" "=r,r")
3197 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3200 movz{wl|x}\t{%1, %k0|%k0, %1}
3201 movz{wq|x}\t{%1, %0|%0, %1}"
3202 [(set_attr "type" "imovx")
3203 (set_attr "mode" "SI,DI")])
3205 (define_insn "zero_extendqidi2"
3206 [(set (match_operand:DI 0 "register_operand" "=r,r")
3207 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3210 movz{bl|x}\t{%1, %k0|%k0, %1}
3211 movz{bq|x}\t{%1, %0|%0, %1}"
3212 [(set_attr "type" "imovx")
3213 (set_attr "mode" "SI,DI")])
3215 ;; Sign extension instructions
3217 (define_expand "extendsidi2"
3218 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3219 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3220 (clobber (reg:CC 17))
3221 (clobber (match_scratch:SI 2 ""))])]
3226 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3231 (define_insn "*extendsidi2_1"
3232 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3233 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3234 (clobber (reg:CC 17))
3235 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3239 (define_insn "extendsidi2_rex64"
3240 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3241 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3245 movs{lq|x}\t{%1,%0|%0, %1}"
3246 [(set_attr "type" "imovx")
3247 (set_attr "mode" "DI")
3248 (set_attr "prefix_0f" "0")
3249 (set_attr "modrm" "0,1")])
3251 (define_insn "extendhidi2"
3252 [(set (match_operand:DI 0 "register_operand" "=r")
3253 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3255 "movs{wq|x}\t{%1,%0|%0, %1}"
3256 [(set_attr "type" "imovx")
3257 (set_attr "mode" "DI")])
3259 (define_insn "extendqidi2"
3260 [(set (match_operand:DI 0 "register_operand" "=r")
3261 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3263 "movs{bq|x}\t{%1,%0|%0, %1}"
3264 [(set_attr "type" "imovx")
3265 (set_attr "mode" "DI")])
3267 ;; Extend to memory case when source register does die.
3269 [(set (match_operand:DI 0 "memory_operand" "")
3270 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3271 (clobber (reg:CC 17))
3272 (clobber (match_operand:SI 2 "register_operand" ""))]
3274 && dead_or_set_p (insn, operands[1])
3275 && !reg_mentioned_p (operands[1], operands[0]))"
3276 [(set (match_dup 3) (match_dup 1))
3277 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3278 (clobber (reg:CC 17))])
3279 (set (match_dup 4) (match_dup 1))]
3280 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3282 ;; Extend to memory case when source register does not die.
3284 [(set (match_operand:DI 0 "memory_operand" "")
3285 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3286 (clobber (reg:CC 17))
3287 (clobber (match_operand:SI 2 "register_operand" ""))]
3291 split_di (&operands[0], 1, &operands[3], &operands[4]);
3293 emit_move_insn (operands[3], operands[1]);
3295 /* Generate a cltd if possible and doing so it profitable. */
3296 if (true_regnum (operands[1]) == 0
3297 && true_regnum (operands[2]) == 1
3298 && (optimize_size || TARGET_USE_CLTD))
3300 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3304 emit_move_insn (operands[2], operands[1]);
3305 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3307 emit_move_insn (operands[4], operands[2]);
3311 ;; Extend to register case. Optimize case where source and destination
3312 ;; registers match and cases where we can use cltd.
3314 [(set (match_operand:DI 0 "register_operand" "")
3315 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3316 (clobber (reg:CC 17))
3317 (clobber (match_scratch:SI 2 ""))]
3321 split_di (&operands[0], 1, &operands[3], &operands[4]);
3323 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3324 emit_move_insn (operands[3], operands[1]);
3326 /* Generate a cltd if possible and doing so it profitable. */
3327 if (true_regnum (operands[3]) == 0
3328 && (optimize_size || TARGET_USE_CLTD))
3330 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3334 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3335 emit_move_insn (operands[4], operands[1]);
3337 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3341 (define_insn "extendhisi2"
3342 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3343 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3346 switch (get_attr_prefix_0f (insn))
3349 return "{cwtl|cwde}";
3351 return "movs{wl|x}\t{%1,%0|%0, %1}";
3354 [(set_attr "type" "imovx")
3355 (set_attr "mode" "SI")
3356 (set (attr "prefix_0f")
3357 ;; movsx is short decodable while cwtl is vector decoded.
3358 (if_then_else (and (eq_attr "cpu" "!k6")
3359 (eq_attr "alternative" "0"))
3361 (const_string "1")))
3363 (if_then_else (eq_attr "prefix_0f" "0")
3365 (const_string "1")))])
3367 (define_insn "*extendhisi2_zext"
3368 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3370 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3373 switch (get_attr_prefix_0f (insn))
3376 return "{cwtl|cwde}";
3378 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3381 [(set_attr "type" "imovx")
3382 (set_attr "mode" "SI")
3383 (set (attr "prefix_0f")
3384 ;; movsx is short decodable while cwtl is vector decoded.
3385 (if_then_else (and (eq_attr "cpu" "!k6")
3386 (eq_attr "alternative" "0"))
3388 (const_string "1")))
3390 (if_then_else (eq_attr "prefix_0f" "0")
3392 (const_string "1")))])
3394 (define_insn "extendqihi2"
3395 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3396 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3399 switch (get_attr_prefix_0f (insn))
3402 return "{cbtw|cbw}";
3404 return "movs{bw|x}\t{%1,%0|%0, %1}";
3407 [(set_attr "type" "imovx")
3408 (set_attr "mode" "HI")
3409 (set (attr "prefix_0f")
3410 ;; movsx is short decodable while cwtl is vector decoded.
3411 (if_then_else (and (eq_attr "cpu" "!k6")
3412 (eq_attr "alternative" "0"))
3414 (const_string "1")))
3416 (if_then_else (eq_attr "prefix_0f" "0")
3418 (const_string "1")))])
3420 (define_insn "extendqisi2"
3421 [(set (match_operand:SI 0 "register_operand" "=r")
3422 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3424 "movs{bl|x}\t{%1,%0|%0, %1}"
3425 [(set_attr "type" "imovx")
3426 (set_attr "mode" "SI")])
3428 (define_insn "*extendqisi2_zext"
3429 [(set (match_operand:DI 0 "register_operand" "=r")
3431 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3433 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3434 [(set_attr "type" "imovx")
3435 (set_attr "mode" "SI")])
3437 ;; Conversions between float and double.
3439 ;; These are all no-ops in the model used for the 80387. So just
3442 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3443 (define_insn "*dummy_extendsfdf2"
3444 [(set (match_operand:DF 0 "push_operand" "=<")
3445 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3450 [(set (match_operand:DF 0 "push_operand" "")
3451 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3453 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3454 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3457 [(set (match_operand:DF 0 "push_operand" "")
3458 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3460 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3461 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3463 (define_insn "*dummy_extendsfxf2"
3464 [(set (match_operand:XF 0 "push_operand" "=<")
3465 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3470 [(set (match_operand:XF 0 "push_operand" "")
3471 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3473 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
3474 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
3475 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3478 [(set (match_operand:XF 0 "push_operand" "")
3479 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3481 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
3482 (set (mem:DF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
3483 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3486 [(set (match_operand:XF 0 "push_operand" "")
3487 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3489 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
3490 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
3491 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3494 [(set (match_operand:XF 0 "push_operand" "")
3495 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3497 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
3498 (set (mem:XF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
3499 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3501 (define_expand "extendsfdf2"
3502 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3503 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3504 "TARGET_80387 || TARGET_SSE2"
3506 /* ??? Needed for compress_float_constant since all fp constants
3507 are LEGITIMATE_CONSTANT_P. */
3508 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3509 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3510 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3511 operands[1] = force_reg (SFmode, operands[1]);
3514 (define_insn "*extendsfdf2_1"
3515 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3516 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3517 "(TARGET_80387 || TARGET_SSE2)
3518 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3520 switch (which_alternative)
3523 if (REG_P (operands[1])
3524 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3526 else if (STACK_TOP_P (operands[0]))
3527 return "fld%z1\t%y1";
3532 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3533 return "fstp%z0\t%y0";
3536 return "fst%z0\t%y0";
3538 return "cvtss2sd\t{%1, %0|%0, %1}";
3544 [(set_attr "type" "fmov,fmov,ssecvt")
3545 (set_attr "mode" "SF,XF,DF")])
3547 (define_insn "*extendsfdf2_1_sse_only"
3548 [(set (match_operand:DF 0 "register_operand" "=Y")
3549 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3550 "!TARGET_80387 && TARGET_SSE2
3551 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3552 "cvtss2sd\t{%1, %0|%0, %1}"
3553 [(set_attr "type" "ssecvt")
3554 (set_attr "mode" "DF")])
3556 (define_expand "extendsfxf2"
3557 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3558 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3561 /* ??? Needed for compress_float_constant since all fp constants
3562 are LEGITIMATE_CONSTANT_P. */
3563 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3564 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3565 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3566 operands[1] = force_reg (SFmode, operands[1]);
3569 (define_insn "*extendsfxf2_1"
3570 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3571 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3573 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3575 switch (which_alternative)
3578 if (REG_P (operands[1])
3579 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3581 else if (STACK_TOP_P (operands[0]))
3582 return "fld%z1\t%y1";
3587 /* There is no non-popping store to memory for XFmode. So if
3588 we need one, follow the store with a load. */
3589 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3590 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3592 return "fstp%z0\t%y0";
3598 [(set_attr "type" "fmov")
3599 (set_attr "mode" "SF,XF")])
3601 (define_expand "extenddfxf2"
3602 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3603 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3606 /* ??? Needed for compress_float_constant since all fp constants
3607 are LEGITIMATE_CONSTANT_P. */
3608 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3609 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3610 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3611 operands[1] = force_reg (DFmode, operands[1]);
3614 (define_insn "*extenddfxf2_1"
3615 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3616 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3618 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3620 switch (which_alternative)
3623 if (REG_P (operands[1])
3624 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3626 else if (STACK_TOP_P (operands[0]))
3627 return "fld%z1\t%y1";
3632 /* There is no non-popping store to memory for XFmode. So if
3633 we need one, follow the store with a load. */
3634 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3635 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3637 return "fstp%z0\t%y0";
3643 [(set_attr "type" "fmov")
3644 (set_attr "mode" "DF,XF")])
3646 ;; %%% This seems bad bad news.
3647 ;; This cannot output into an f-reg because there is no way to be sure
3648 ;; of truncating in that case. Otherwise this is just like a simple move
3649 ;; insn. So we pretend we can output to a reg in order to get better
3650 ;; register preferencing, but we really use a stack slot.
3652 (define_expand "truncdfsf2"
3653 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3655 (match_operand:DF 1 "register_operand" "")))
3656 (clobber (match_dup 2))])]
3657 "TARGET_80387 || TARGET_SSE2"
3660 operands[2] = assign_386_stack_local (SFmode, 0);
3663 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3668 (define_insn "*truncdfsf2_1"
3669 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3671 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3672 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3673 "TARGET_80387 && !TARGET_SSE2"
3675 switch (which_alternative)
3678 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3679 return "fstp%z0\t%y0";
3681 return "fst%z0\t%y0";
3686 [(set_attr "type" "fmov,multi,multi,multi")
3687 (set_attr "mode" "SF,SF,SF,SF")])
3689 (define_insn "*truncdfsf2_1_sse"
3690 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr")
3692 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3693 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3694 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3696 switch (which_alternative)
3699 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3700 return "fstp%z0\t%y0";
3702 return "fst%z0\t%y0";
3709 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3710 (set_attr "mode" "SF,SF,SF,SF,DF")])
3712 (define_insn "*truncdfsf2_1_sse_nooverlap"
3713 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
3715 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3716 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3717 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3719 switch (which_alternative)
3722 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3723 return "fstp%z0\t%y0";
3725 return "fst%z0\t%y0";
3732 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3733 (set_attr "mode" "SF,SF,SF,SF,DF")])
3735 (define_insn "*truncdfsf2_2"
3736 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
3738 (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
3739 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3740 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3742 switch (which_alternative)
3746 return "cvtsd2ss\t{%1, %0|%0, %1}";
3748 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3749 return "fstp%z0\t%y0";
3751 return "fst%z0\t%y0";
3756 [(set_attr "type" "ssecvt,ssecvt,fmov")
3757 (set_attr "athlon_decode" "vector,double,*")
3758 (set_attr "mode" "SF,SF,SF")])
3760 (define_insn "*truncdfsf2_2_nooverlap"
3761 [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
3763 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3764 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3765 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3767 switch (which_alternative)
3772 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3773 return "fstp%z0\t%y0";
3775 return "fst%z0\t%y0";
3780 [(set_attr "type" "ssecvt,fmov")
3781 (set_attr "mode" "DF,SF")])
3783 (define_insn "*truncdfsf2_3"
3784 [(set (match_operand:SF 0 "memory_operand" "=m")
3786 (match_operand:DF 1 "register_operand" "f")))]
3789 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3790 return "fstp%z0\t%y0";
3792 return "fst%z0\t%y0";
3794 [(set_attr "type" "fmov")
3795 (set_attr "mode" "SF")])
3797 (define_insn "truncdfsf2_sse_only"
3798 [(set (match_operand:SF 0 "register_operand" "=Y,Y")
3800 (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
3801 "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3802 "cvtsd2ss\t{%1, %0|%0, %1}"
3803 [(set_attr "type" "ssecvt")
3804 (set_attr "athlon_decode" "vector,double")
3805 (set_attr "mode" "SF")])
3807 (define_insn "*truncdfsf2_sse_only_nooverlap"
3808 [(set (match_operand:SF 0 "register_operand" "=&Y")
3810 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
3811 "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3813 [(set_attr "type" "ssecvt")
3814 (set_attr "mode" "DF")])
3817 [(set (match_operand:SF 0 "memory_operand" "")
3819 (match_operand:DF 1 "register_operand" "")))
3820 (clobber (match_operand:SF 2 "memory_operand" ""))]
3822 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3825 ; Avoid possible reformatting penalty on the destination by first
3828 [(set (match_operand:SF 0 "register_operand" "")
3830 (match_operand:DF 1 "nonimmediate_operand" "")))
3831 (clobber (match_operand 2 "" ""))]
3832 "TARGET_80387 && reload_completed
3833 && SSE_REG_P (operands[0])
3834 && !STACK_REG_P (operands[1])"
3838 if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
3839 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3842 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3843 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3844 /* simplify_gen_subreg refuses to widen memory references. */
3845 if (GET_CODE (src) == SUBREG)
3846 alter_subreg (&src);
3847 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3849 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3850 emit_insn (gen_cvtsd2ss (dest, dest, src));
3856 [(set (match_operand:SF 0 "register_operand" "")
3858 (match_operand:DF 1 "nonimmediate_operand" "")))]
3859 "TARGET_80387 && reload_completed
3860 && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3864 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
3865 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
3866 /* simplify_gen_subreg refuses to widen memory references. */
3867 if (GET_CODE (src) == SUBREG)
3868 alter_subreg (&src);
3869 if (reg_overlap_mentioned_p (operands[0], operands[1]))
3871 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
3872 emit_insn (gen_cvtsd2ss (dest, dest, src));
3877 [(set (match_operand:SF 0 "register_operand" "")
3879 (match_operand:DF 1 "fp_register_operand" "")))
3880 (clobber (match_operand:SF 2 "memory_operand" ""))]
3881 "TARGET_80387 && reload_completed"
3882 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3883 (set (match_dup 0) (match_dup 2))]
3886 (define_expand "truncxfsf2"
3887 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3889 (match_operand:XF 1 "register_operand" "")))
3890 (clobber (match_dup 2))])]
3892 "operands[2] = assign_386_stack_local (SFmode, 0);")
3894 (define_insn "*truncxfsf2_1"
3895 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3897 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3898 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3901 switch (which_alternative)
3904 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3905 return "fstp%z0\t%y0";
3907 return "fst%z0\t%y0";
3912 [(set_attr "type" "fmov,multi,multi,multi")
3913 (set_attr "mode" "SF")])
3915 (define_insn "*truncxfsf2_2"
3916 [(set (match_operand:SF 0 "memory_operand" "=m")
3918 (match_operand:XF 1 "register_operand" "f")))]
3921 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3922 return "fstp%z0\t%y0";
3924 return "fst%z0\t%y0";
3926 [(set_attr "type" "fmov")
3927 (set_attr "mode" "SF")])
3930 [(set (match_operand:SF 0 "memory_operand" "")
3932 (match_operand:XF 1 "register_operand" "")))
3933 (clobber (match_operand:SF 2 "memory_operand" ""))]
3935 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3939 [(set (match_operand:SF 0 "register_operand" "")
3941 (match_operand:XF 1 "register_operand" "")))
3942 (clobber (match_operand:SF 2 "memory_operand" ""))]
3943 "TARGET_80387 && reload_completed"
3944 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3945 (set (match_dup 0) (match_dup 2))]
3948 (define_expand "truncxfdf2"
3949 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3951 (match_operand:XF 1 "register_operand" "")))
3952 (clobber (match_dup 2))])]
3954 "operands[2] = assign_386_stack_local (DFmode, 0);")
3956 (define_insn "*truncxfdf2_1"
3957 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3959 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3960 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
3963 switch (which_alternative)
3966 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3967 return "fstp%z0\t%y0";
3969 return "fst%z0\t%y0";
3975 [(set_attr "type" "fmov,multi,multi,multi")
3976 (set_attr "mode" "DF")])
3978 (define_insn "*truncxfdf2_2"
3979 [(set (match_operand:DF 0 "memory_operand" "=m")
3981 (match_operand:XF 1 "register_operand" "f")))]
3984 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3985 return "fstp%z0\t%y0";
3987 return "fst%z0\t%y0";
3989 [(set_attr "type" "fmov")
3990 (set_attr "mode" "DF")])
3993 [(set (match_operand:DF 0 "memory_operand" "")
3995 (match_operand:XF 1 "register_operand" "")))
3996 (clobber (match_operand:DF 2 "memory_operand" ""))]
3998 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4002 [(set (match_operand:DF 0 "register_operand" "")
4004 (match_operand:XF 1 "register_operand" "")))
4005 (clobber (match_operand:DF 2 "memory_operand" ""))]
4006 "TARGET_80387 && reload_completed"
4007 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4008 (set (match_dup 0) (match_dup 2))]
4012 ;; %%% Break up all these bad boys.
4014 ;; Signed conversion to DImode.
4016 (define_expand "fix_truncxfdi2"
4017 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4018 (fix:DI (match_operand:XF 1 "register_operand" "")))]
4022 (define_expand "fix_truncdfdi2"
4023 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4024 (fix:DI (match_operand:DF 1 "register_operand" "")))]
4025 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4027 if (TARGET_64BIT && TARGET_SSE2)
4029 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4030 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4031 if (out != operands[0])
4032 emit_move_insn (operands[0], out);
4037 (define_expand "fix_truncsfdi2"
4038 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4039 (fix:DI (match_operand:SF 1 "register_operand" "")))]
4040 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4042 if (TARGET_SSE && TARGET_64BIT)
4044 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4045 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4046 if (out != operands[0])
4047 emit_move_insn (operands[0], out);
4052 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4053 ;; of the machinery.
4054 (define_insn_and_split "*fix_truncdi_1"
4055 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4056 (fix:DI (match_operand 1 "register_operand" "f,f")))]
4057 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4058 && !reload_completed && !reload_in_progress
4059 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4064 ix86_optimize_mode_switching = 1;
4065 operands[2] = assign_386_stack_local (HImode, 1);
4066 operands[3] = assign_386_stack_local (HImode, 2);
4067 if (memory_operand (operands[0], VOIDmode))
4068 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4069 operands[2], operands[3]));
4072 operands[4] = assign_386_stack_local (DImode, 0);
4073 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4074 operands[2], operands[3],
4079 [(set_attr "type" "fistp")
4080 (set_attr "mode" "DI")])
4082 (define_insn "fix_truncdi_nomemory"
4083 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4084 (fix:DI (match_operand 1 "register_operand" "f,f")))
4085 (use (match_operand:HI 2 "memory_operand" "m,m"))
4086 (use (match_operand:HI 3 "memory_operand" "m,m"))
4087 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4088 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4089 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4090 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4092 [(set_attr "type" "fistp")
4093 (set_attr "mode" "DI")])
4095 (define_insn "fix_truncdi_memory"
4096 [(set (match_operand:DI 0 "memory_operand" "=m")
4097 (fix:DI (match_operand 1 "register_operand" "f")))
4098 (use (match_operand:HI 2 "memory_operand" "m"))
4099 (use (match_operand:HI 3 "memory_operand" "m"))
4100 (clobber (match_scratch:DF 4 "=&1f"))]
4101 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4102 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4103 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4104 [(set_attr "type" "fistp")
4105 (set_attr "mode" "DI")])
4108 [(set (match_operand:DI 0 "register_operand" "")
4109 (fix:DI (match_operand 1 "register_operand" "")))
4110 (use (match_operand:HI 2 "memory_operand" ""))
4111 (use (match_operand:HI 3 "memory_operand" ""))
4112 (clobber (match_operand:DI 4 "memory_operand" ""))
4113 (clobber (match_scratch 5 ""))]
4115 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4118 (clobber (match_dup 5))])
4119 (set (match_dup 0) (match_dup 4))]
4123 [(set (match_operand:DI 0 "memory_operand" "")
4124 (fix:DI (match_operand 1 "register_operand" "")))
4125 (use (match_operand:HI 2 "memory_operand" ""))
4126 (use (match_operand:HI 3 "memory_operand" ""))
4127 (clobber (match_operand:DI 4 "memory_operand" ""))
4128 (clobber (match_scratch 5 ""))]
4130 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4133 (clobber (match_dup 5))])]
4136 ;; When SSE available, it is always faster to use it!
4137 (define_insn "fix_truncsfdi_sse"
4138 [(set (match_operand:DI 0 "register_operand" "=r,r")
4139 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4140 "TARGET_64BIT && TARGET_SSE"
4141 "cvttss2si{q}\t{%1, %0|%0, %1}"
4142 [(set_attr "type" "sseicvt")
4143 (set_attr "mode" "SF")
4144 (set_attr "athlon_decode" "double,vector")])
4146 ;; Avoid vector decoded form of the instruction.
4148 [(match_scratch:SF 2 "x")
4149 (set (match_operand:DI 0 "register_operand" "")
4150 (fix:DI (match_operand:SF 1 "memory_operand" "")))]
4151 "TARGET_K8 && !optimize_size"
4152 [(set (match_dup 2) (match_dup 1))
4153 (set (match_dup 0) (fix:DI (match_dup 2)))]
4156 (define_insn "fix_truncdfdi_sse"
4157 [(set (match_operand:DI 0 "register_operand" "=r,r")
4158 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4159 "TARGET_64BIT && TARGET_SSE2"
4160 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4161 [(set_attr "type" "sseicvt,sseicvt")
4162 (set_attr "mode" "DF")
4163 (set_attr "athlon_decode" "double,vector")])
4165 ;; Avoid vector decoded form of the instruction.
4167 [(match_scratch:DF 2 "Y")
4168 (set (match_operand:DI 0 "register_operand" "")
4169 (fix:DI (match_operand:DF 1 "memory_operand" "")))]
4170 "TARGET_K8 && !optimize_size"
4171 [(set (match_dup 2) (match_dup 1))
4172 (set (match_dup 0) (fix:DI (match_dup 2)))]
4175 ;; Signed conversion to SImode.
4177 (define_expand "fix_truncxfsi2"
4178 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4179 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4183 (define_expand "fix_truncdfsi2"
4184 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4185 (fix:SI (match_operand:DF 1 "register_operand" "")))]
4186 "TARGET_80387 || TARGET_SSE2"
4190 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4191 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4192 if (out != operands[0])
4193 emit_move_insn (operands[0], out);
4198 (define_expand "fix_truncsfsi2"
4199 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4200 (fix:SI (match_operand:SF 1 "register_operand" "")))]
4201 "TARGET_80387 || TARGET_SSE"
4205 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4206 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4207 if (out != operands[0])
4208 emit_move_insn (operands[0], out);
4213 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4214 ;; of the machinery.
4215 (define_insn_and_split "*fix_truncsi_1"
4216 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4217 (fix:SI (match_operand 1 "register_operand" "f,f")))]
4218 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4219 && !reload_completed && !reload_in_progress
4220 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4225 ix86_optimize_mode_switching = 1;
4226 operands[2] = assign_386_stack_local (HImode, 1);
4227 operands[3] = assign_386_stack_local (HImode, 2);
4228 if (memory_operand (operands[0], VOIDmode))
4229 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4230 operands[2], operands[3]));
4233 operands[4] = assign_386_stack_local (SImode, 0);
4234 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4235 operands[2], operands[3],
4240 [(set_attr "type" "fistp")
4241 (set_attr "mode" "SI")])
4243 (define_insn "fix_truncsi_nomemory"
4244 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4245 (fix:SI (match_operand 1 "register_operand" "f,f")))
4246 (use (match_operand:HI 2 "memory_operand" "m,m"))
4247 (use (match_operand:HI 3 "memory_operand" "m,m"))
4248 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4249 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4250 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4252 [(set_attr "type" "fistp")
4253 (set_attr "mode" "SI")])
4255 (define_insn "fix_truncsi_memory"
4256 [(set (match_operand:SI 0 "memory_operand" "=m")
4257 (fix:SI (match_operand 1 "register_operand" "f")))
4258 (use (match_operand:HI 2 "memory_operand" "m"))
4259 (use (match_operand:HI 3 "memory_operand" "m"))]
4260 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4261 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4262 "* return output_fix_trunc (insn, operands);"
4263 [(set_attr "type" "fistp")
4264 (set_attr "mode" "SI")])
4266 ;; When SSE available, it is always faster to use it!
4267 (define_insn "fix_truncsfsi_sse"
4268 [(set (match_operand:SI 0 "register_operand" "=r,r")
4269 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4271 "cvttss2si\t{%1, %0|%0, %1}"
4272 [(set_attr "type" "sseicvt")
4273 (set_attr "mode" "DF")
4274 (set_attr "athlon_decode" "double,vector")])
4276 ;; Avoid vector decoded form of the instruction.
4278 [(match_scratch:SF 2 "x")
4279 (set (match_operand:SI 0 "register_operand" "")
4280 (fix:SI (match_operand:SF 1 "memory_operand" "")))]
4281 "TARGET_K8 && !optimize_size"
4282 [(set (match_dup 2) (match_dup 1))
4283 (set (match_dup 0) (fix:SI (match_dup 2)))]
4286 (define_insn "fix_truncdfsi_sse"
4287 [(set (match_operand:SI 0 "register_operand" "=r,r")
4288 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4290 "cvttsd2si\t{%1, %0|%0, %1}"
4291 [(set_attr "type" "sseicvt")
4292 (set_attr "mode" "DF")
4293 (set_attr "athlon_decode" "double,vector")])
4295 ;; Avoid vector decoded form of the instruction.
4297 [(match_scratch:DF 2 "Y")
4298 (set (match_operand:SI 0 "register_operand" "")
4299 (fix:SI (match_operand:DF 1 "memory_operand" "")))]
4300 "TARGET_K8 && !optimize_size"
4301 [(set (match_dup 2) (match_dup 1))
4302 (set (match_dup 0) (fix:SI (match_dup 2)))]
4306 [(set (match_operand:SI 0 "register_operand" "")
4307 (fix:SI (match_operand 1 "register_operand" "")))
4308 (use (match_operand:HI 2 "memory_operand" ""))
4309 (use (match_operand:HI 3 "memory_operand" ""))
4310 (clobber (match_operand:SI 4 "memory_operand" ""))]
4312 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4314 (use (match_dup 3))])
4315 (set (match_dup 0) (match_dup 4))]
4319 [(set (match_operand:SI 0 "memory_operand" "")
4320 (fix:SI (match_operand 1 "register_operand" "")))
4321 (use (match_operand:HI 2 "memory_operand" ""))
4322 (use (match_operand:HI 3 "memory_operand" ""))
4323 (clobber (match_operand:SI 4 "memory_operand" ""))]
4325 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4327 (use (match_dup 3))])]
4330 ;; Signed conversion to HImode.
4332 (define_expand "fix_truncxfhi2"
4333 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4334 (fix:HI (match_operand:XF 1 "register_operand" "")))]
4338 (define_expand "fix_truncdfhi2"
4339 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4340 (fix:HI (match_operand:DF 1 "register_operand" "")))]
4341 "TARGET_80387 && !TARGET_SSE2"
4344 (define_expand "fix_truncsfhi2"
4345 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4346 (fix:HI (match_operand:SF 1 "register_operand" "")))]
4347 "TARGET_80387 && !TARGET_SSE"
4350 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4351 ;; of the machinery.
4352 (define_insn_and_split "*fix_trunchi_1"
4353 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4354 (fix:HI (match_operand 1 "register_operand" "f,f")))]
4355 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4356 && !reload_completed && !reload_in_progress
4357 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4362 ix86_optimize_mode_switching = 1;
4363 operands[2] = assign_386_stack_local (HImode, 1);
4364 operands[3] = assign_386_stack_local (HImode, 2);
4365 if (memory_operand (operands[0], VOIDmode))
4366 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4367 operands[2], operands[3]));
4370 operands[4] = assign_386_stack_local (HImode, 0);
4371 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4372 operands[2], operands[3],
4377 [(set_attr "type" "fistp")
4378 (set_attr "mode" "HI")])
4380 (define_insn "fix_trunchi_nomemory"
4381 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4382 (fix:HI (match_operand 1 "register_operand" "f,f")))
4383 (use (match_operand:HI 2 "memory_operand" "m,m"))
4384 (use (match_operand:HI 3 "memory_operand" "m,m"))
4385 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4386 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4387 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4389 [(set_attr "type" "fistp")
4390 (set_attr "mode" "HI")])
4392 (define_insn "fix_trunchi_memory"
4393 [(set (match_operand:HI 0 "memory_operand" "=m")
4394 (fix:HI (match_operand 1 "register_operand" "f")))
4395 (use (match_operand:HI 2 "memory_operand" "m"))
4396 (use (match_operand:HI 3 "memory_operand" "m"))]
4397 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4398 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4399 "* return output_fix_trunc (insn, operands);"
4400 [(set_attr "type" "fistp")
4401 (set_attr "mode" "HI")])
4404 [(set (match_operand:HI 0 "memory_operand" "")
4405 (fix:HI (match_operand 1 "register_operand" "")))
4406 (use (match_operand:HI 2 "memory_operand" ""))
4407 (use (match_operand:HI 3 "memory_operand" ""))
4408 (clobber (match_operand:HI 4 "memory_operand" ""))]
4410 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4412 (use (match_dup 3))])]
4416 [(set (match_operand:HI 0 "register_operand" "")
4417 (fix:HI (match_operand 1 "register_operand" "")))
4418 (use (match_operand:HI 2 "memory_operand" ""))
4419 (use (match_operand:HI 3 "memory_operand" ""))
4420 (clobber (match_operand:HI 4 "memory_operand" ""))]
4422 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4425 (clobber (match_dup 4))])
4426 (set (match_dup 0) (match_dup 4))]
4430 (define_insn "x86_fnstcw_1"
4431 [(set (match_operand:HI 0 "memory_operand" "=m")
4432 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
4435 [(set_attr "length" "2")
4436 (set_attr "mode" "HI")
4437 (set_attr "unit" "i387")
4438 (set_attr "ppro_uops" "few")])
4440 (define_insn "x86_fldcw_1"
4442 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4445 [(set_attr "length" "2")
4446 (set_attr "mode" "HI")
4447 (set_attr "unit" "i387")
4448 (set_attr "athlon_decode" "vector")
4449 (set_attr "ppro_uops" "few")])
4451 ;; Conversion between fixed point and floating point.
4453 ;; Even though we only accept memory inputs, the backend _really_
4454 ;; wants to be able to do this between registers.
4456 (define_expand "floathisf2"
4457 [(set (match_operand:SF 0 "register_operand" "")
4458 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4459 "TARGET_SSE || TARGET_80387"
4461 if (TARGET_SSE && TARGET_SSE_MATH)
4463 emit_insn (gen_floatsisf2 (operands[0],
4464 convert_to_mode (SImode, operands[1], 0)));
4469 (define_insn "*floathisf2_1"
4470 [(set (match_operand:SF 0 "register_operand" "=f,f")
4471 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4472 "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
4476 [(set_attr "type" "fmov,multi")
4477 (set_attr "mode" "SF")
4478 (set_attr "fp_int_src" "true")])
4480 (define_expand "floatsisf2"
4481 [(set (match_operand:SF 0 "register_operand" "")
4482 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4483 "TARGET_SSE || TARGET_80387"
4486 (define_insn "*floatsisf2_i387"
4487 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4488 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4489 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4493 cvtsi2ss\t{%1, %0|%0, %1}
4494 cvtsi2ss\t{%1, %0|%0, %1}"
4495 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4496 (set_attr "mode" "SF")
4497 (set_attr "athlon_decode" "*,*,vector,double")
4498 (set_attr "fp_int_src" "true")])
4500 (define_insn "*floatsisf2_sse"
4501 [(set (match_operand:SF 0 "register_operand" "=x,x")
4502 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4504 "cvtsi2ss\t{%1, %0|%0, %1}"
4505 [(set_attr "type" "sseicvt")
4506 (set_attr "mode" "SF")
4507 (set_attr "athlon_decode" "vector,double")
4508 (set_attr "fp_int_src" "true")])
4510 ; Avoid possible reformatting penalty on the destination by first
4513 [(set (match_operand:SF 0 "register_operand" "")
4514 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4515 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4516 && SSE_REG_P (operands[0])"
4520 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4521 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4522 emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
4526 (define_expand "floatdisf2"
4527 [(set (match_operand:SF 0 "register_operand" "")
4528 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4529 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4532 (define_insn "*floatdisf2_i387_only"
4533 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4534 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4535 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4539 [(set_attr "type" "fmov,multi")
4540 (set_attr "mode" "SF")
4541 (set_attr "fp_int_src" "true")])
4543 (define_insn "*floatdisf2_i387"
4544 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4545 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4546 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4550 cvtsi2ss{q}\t{%1, %0|%0, %1}
4551 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4552 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4553 (set_attr "mode" "SF")
4554 (set_attr "athlon_decode" "*,*,vector,double")
4555 (set_attr "fp_int_src" "true")])
4557 (define_insn "*floatdisf2_sse"
4558 [(set (match_operand:SF 0 "register_operand" "=x,x")
4559 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4560 "TARGET_64BIT && TARGET_SSE"
4561 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4562 [(set_attr "type" "sseicvt")
4563 (set_attr "mode" "SF")
4564 (set_attr "athlon_decode" "vector,double")
4565 (set_attr "fp_int_src" "true")])
4567 ; Avoid possible reformatting penalty on the destination by first
4570 [(set (match_operand:SF 0 "register_operand" "")
4571 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4572 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4573 && SSE_REG_P (operands[0])"
4577 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4578 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4579 emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
4583 (define_expand "floathidf2"
4584 [(set (match_operand:DF 0 "register_operand" "")
4585 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4586 "TARGET_SSE2 || TARGET_80387"
4588 if (TARGET_SSE && TARGET_SSE_MATH)
4590 emit_insn (gen_floatsidf2 (operands[0],
4591 convert_to_mode (SImode, operands[1], 0)));
4596 (define_insn "*floathidf2_1"
4597 [(set (match_operand:DF 0 "register_operand" "=f,f")
4598 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4599 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
4603 [(set_attr "type" "fmov,multi")
4604 (set_attr "mode" "DF")
4605 (set_attr "fp_int_src" "true")])
4607 (define_expand "floatsidf2"
4608 [(set (match_operand:DF 0 "register_operand" "")
4609 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4610 "TARGET_80387 || TARGET_SSE2"
4613 (define_insn "*floatsidf2_i387"
4614 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4615 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4616 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4620 cvtsi2sd\t{%1, %0|%0, %1}
4621 cvtsi2sd\t{%1, %0|%0, %1}"
4622 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4623 (set_attr "mode" "DF")
4624 (set_attr "athlon_decode" "*,*,double,direct")
4625 (set_attr "fp_int_src" "true")])
4627 (define_insn "*floatsidf2_sse"
4628 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4629 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4631 "cvtsi2sd\t{%1, %0|%0, %1}"
4632 [(set_attr "type" "sseicvt")
4633 (set_attr "mode" "DF")
4634 (set_attr "athlon_decode" "double,direct")
4635 (set_attr "fp_int_src" "true")])
4637 (define_expand "floatdidf2"
4638 [(set (match_operand:DF 0 "register_operand" "")
4639 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4640 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
4643 (define_insn "*floatdidf2_i387_only"
4644 [(set (match_operand:DF 0 "register_operand" "=f,?f")
4645 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4646 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
4650 [(set_attr "type" "fmov,multi")
4651 (set_attr "mode" "DF")
4652 (set_attr "fp_int_src" "true")])
4654 (define_insn "*floatdidf2_i387"
4655 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4656 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4657 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4661 cvtsi2sd{q}\t{%1, %0|%0, %1}
4662 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4663 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4664 (set_attr "mode" "DF")
4665 (set_attr "athlon_decode" "*,*,double,direct")
4666 (set_attr "fp_int_src" "true")])
4668 (define_insn "*floatdidf2_sse"
4669 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4670 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4672 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4673 [(set_attr "type" "sseicvt")
4674 (set_attr "mode" "DF")
4675 (set_attr "athlon_decode" "double,direct")
4676 (set_attr "fp_int_src" "true")])
4678 (define_insn "floathixf2"
4679 [(set (match_operand:XF 0 "register_operand" "=f,f")
4680 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4685 [(set_attr "type" "fmov,multi")
4686 (set_attr "mode" "XF")
4687 (set_attr "fp_int_src" "true")])
4689 (define_insn "floatsixf2"
4690 [(set (match_operand:XF 0 "register_operand" "=f,f")
4691 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4696 [(set_attr "type" "fmov,multi")
4697 (set_attr "mode" "XF")
4698 (set_attr "fp_int_src" "true")])
4700 (define_insn "floatdixf2"
4701 [(set (match_operand:XF 0 "register_operand" "=f,f")
4702 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4707 [(set_attr "type" "fmov,multi")
4708 (set_attr "mode" "XF")
4709 (set_attr "fp_int_src" "true")])
4711 ;; %%% Kill these when reload knows how to do it.
4713 [(set (match_operand 0 "fp_register_operand" "")
4714 (float (match_operand 1 "register_operand" "")))]
4715 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
4718 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4719 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4720 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4721 ix86_free_from_memory (GET_MODE (operands[1]));
4725 (define_expand "floatunssisf2"
4726 [(use (match_operand:SF 0 "register_operand" ""))
4727 (use (match_operand:SI 1 "register_operand" ""))]
4728 "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
4729 "x86_emit_floatuns (operands); DONE;")
4731 (define_expand "floatunsdisf2"
4732 [(use (match_operand:SF 0 "register_operand" ""))
4733 (use (match_operand:DI 1 "register_operand" ""))]
4734 "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
4735 "x86_emit_floatuns (operands); DONE;")
4737 (define_expand "floatunsdidf2"
4738 [(use (match_operand:DF 0 "register_operand" ""))
4739 (use (match_operand:DI 1 "register_operand" ""))]
4740 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
4741 "x86_emit_floatuns (operands); DONE;")
4743 ;; SSE extract/set expanders
4745 (define_expand "vec_setv2df"
4746 [(match_operand:V2DF 0 "register_operand" "")
4747 (match_operand:DF 1 "register_operand" "")
4748 (match_operand 2 "const_int_operand" "")]
4751 switch (INTVAL (operands[2]))
4754 emit_insn (gen_sse2_movsd (operands[0], operands[0],
4755 simplify_gen_subreg (V2DFmode, operands[1],
4760 rtx op1 = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4762 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], op1));
4771 (define_expand "vec_extractv2df"
4772 [(match_operand:DF 0 "register_operand" "")
4773 (match_operand:V2DF 1 "register_operand" "")
4774 (match_operand 2 "const_int_operand" "")]
4777 switch (INTVAL (operands[2]))
4780 emit_move_insn (operands[0], gen_lowpart (DFmode, operands[1]));
4784 rtx dest = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
4786 emit_insn (gen_sse2_unpckhpd (dest, operands[1], operands[1]));
4795 (define_expand "vec_initv2df"
4796 [(match_operand:V2DF 0 "register_operand" "")
4797 (match_operand 1 "" "")]
4800 ix86_expand_vector_init (operands[0], operands[1]);
4804 (define_expand "vec_setv4sf"
4805 [(match_operand:V4SF 0 "register_operand" "")
4806 (match_operand:SF 1 "register_operand" "")
4807 (match_operand 2 "const_int_operand" "")]
4810 switch (INTVAL (operands[2]))
4813 emit_insn (gen_sse_movss (operands[0], operands[0],
4814 simplify_gen_subreg (V4SFmode, operands[1],
4819 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4820 rtx tmp = gen_reg_rtx (V4SFmode);
4822 emit_move_insn (tmp, operands[0]);
4823 emit_insn (gen_sse_unpcklps (operands[0], operands[0], operands[0]));
4824 emit_insn (gen_sse_movss (operands[0], operands[0], op1));
4825 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4826 GEN_INT (1 + (0<<2) + (2<<4) + (3<<6))));
4830 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4831 rtx tmp = gen_reg_rtx (V4SFmode);
4833 emit_move_insn (tmp, operands[0]);
4834 emit_insn (gen_sse_movss (tmp, tmp, op1));
4835 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4836 GEN_INT (0 + (1<<2) + (0<<4) + (3<<6))));
4841 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4842 rtx tmp = gen_reg_rtx (V4SFmode);
4844 emit_move_insn (tmp, operands[0]);
4845 emit_insn (gen_sse_movss (tmp, tmp, op1));
4846 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4847 GEN_INT (0 + (1<<2) + (2<<4) + (0<<6))));
4856 (define_expand "vec_extractv4sf"
4857 [(match_operand:SF 0 "register_operand" "")
4858 (match_operand:V4SF 1 "register_operand" "")
4859 (match_operand 2 "const_int_operand" "")]
4862 switch (INTVAL (operands[2]))
4865 emit_move_insn (operands[0], gen_lowpart (SFmode, operands[1]));
4869 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4870 rtx tmp = gen_reg_rtx (V4SFmode);
4872 emit_move_insn (tmp, operands[1]);
4873 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4878 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4879 rtx tmp = gen_reg_rtx (V4SFmode);
4881 emit_move_insn (tmp, operands[1]);
4882 emit_insn (gen_sse_unpckhps (op0, tmp, tmp));
4886 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4887 rtx tmp = gen_reg_rtx (V4SFmode);
4889 emit_move_insn (tmp, operands[1]);
4890 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4899 (define_expand "vec_initv4sf"
4900 [(match_operand:V4SF 0 "register_operand" "")
4901 (match_operand 1 "" "")]
4904 ix86_expand_vector_init (operands[0], operands[1]);
4910 ;; %%% splits for addsidi3
4911 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4912 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4913 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4915 (define_expand "adddi3"
4916 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4917 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4918 (match_operand:DI 2 "x86_64_general_operand" "")))
4919 (clobber (reg:CC 17))]
4921 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4923 (define_insn "*adddi3_1"
4924 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4925 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4926 (match_operand:DI 2 "general_operand" "roiF,riF")))
4927 (clobber (reg:CC 17))]
4928 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4932 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4933 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4934 (match_operand:DI 2 "general_operand" "")))
4935 (clobber (reg:CC 17))]
4936 "!TARGET_64BIT && reload_completed"
4937 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
4939 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4940 (parallel [(set (match_dup 3)
4941 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4944 (clobber (reg:CC 17))])]
4945 "split_di (operands+0, 1, operands+0, operands+3);
4946 split_di (operands+1, 1, operands+1, operands+4);
4947 split_di (operands+2, 1, operands+2, operands+5);")
4949 (define_insn "adddi3_carry_rex64"
4950 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4951 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
4952 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
4953 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
4954 (clobber (reg:CC 17))]
4955 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4956 "adc{q}\t{%2, %0|%0, %2}"
4957 [(set_attr "type" "alu")
4958 (set_attr "pent_pair" "pu")
4959 (set_attr "mode" "DI")
4960 (set_attr "ppro_uops" "few")])
4962 (define_insn "*adddi3_cc_rex64"
4964 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
4965 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
4967 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4968 (plus:DI (match_dup 1) (match_dup 2)))]
4969 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4970 "add{q}\t{%2, %0|%0, %2}"
4971 [(set_attr "type" "alu")
4972 (set_attr "mode" "DI")])
4974 (define_insn "addqi3_carry"
4975 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4976 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
4977 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
4978 (match_operand:QI 2 "general_operand" "qi,qm")))
4979 (clobber (reg:CC 17))]
4980 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4981 "adc{b}\t{%2, %0|%0, %2}"
4982 [(set_attr "type" "alu")
4983 (set_attr "pent_pair" "pu")
4984 (set_attr "mode" "QI")
4985 (set_attr "ppro_uops" "few")])
4987 (define_insn "addhi3_carry"
4988 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
4989 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
4990 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
4991 (match_operand:HI 2 "general_operand" "ri,rm")))
4992 (clobber (reg:CC 17))]
4993 "ix86_binary_operator_ok (PLUS, HImode, operands)"
4994 "adc{w}\t{%2, %0|%0, %2}"
4995 [(set_attr "type" "alu")
4996 (set_attr "pent_pair" "pu")
4997 (set_attr "mode" "HI")
4998 (set_attr "ppro_uops" "few")])
5000 (define_insn "addsi3_carry"
5001 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5002 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5003 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5004 (match_operand:SI 2 "general_operand" "ri,rm")))
5005 (clobber (reg:CC 17))]
5006 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5007 "adc{l}\t{%2, %0|%0, %2}"
5008 [(set_attr "type" "alu")
5009 (set_attr "pent_pair" "pu")
5010 (set_attr "mode" "SI")
5011 (set_attr "ppro_uops" "few")])
5013 (define_insn "*addsi3_carry_zext"
5014 [(set (match_operand:DI 0 "register_operand" "=r")
5016 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5017 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5018 (match_operand:SI 2 "general_operand" "rim"))))
5019 (clobber (reg:CC 17))]
5020 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5021 "adc{l}\t{%2, %k0|%k0, %2}"
5022 [(set_attr "type" "alu")
5023 (set_attr "pent_pair" "pu")
5024 (set_attr "mode" "SI")
5025 (set_attr "ppro_uops" "few")])
5027 (define_insn "*addsi3_cc"
5029 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5030 (match_operand:SI 2 "general_operand" "ri,rm")]
5032 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5033 (plus:SI (match_dup 1) (match_dup 2)))]
5034 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5035 "add{l}\t{%2, %0|%0, %2}"
5036 [(set_attr "type" "alu")
5037 (set_attr "mode" "SI")])
5039 (define_insn "addqi3_cc"
5041 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5042 (match_operand:QI 2 "general_operand" "qi,qm")]
5044 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5045 (plus:QI (match_dup 1) (match_dup 2)))]
5046 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5047 "add{b}\t{%2, %0|%0, %2}"
5048 [(set_attr "type" "alu")
5049 (set_attr "mode" "QI")])
5051 (define_expand "addsi3"
5052 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5053 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5054 (match_operand:SI 2 "general_operand" "")))
5055 (clobber (reg:CC 17))])]
5057 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5059 (define_insn "*lea_1"
5060 [(set (match_operand:SI 0 "register_operand" "=r")
5061 (match_operand:SI 1 "no_seg_address_operand" "p"))]
5063 "lea{l}\t{%a1, %0|%0, %a1}"
5064 [(set_attr "type" "lea")
5065 (set_attr "mode" "SI")])
5067 (define_insn "*lea_1_rex64"
5068 [(set (match_operand:SI 0 "register_operand" "=r")
5069 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
5071 "lea{l}\t{%a1, %0|%0, %a1}"
5072 [(set_attr "type" "lea")
5073 (set_attr "mode" "SI")])
5075 (define_insn "*lea_1_zext"
5076 [(set (match_operand:DI 0 "register_operand" "=r")
5078 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
5080 "lea{l}\t{%a1, %k0|%k0, %a1}"
5081 [(set_attr "type" "lea")
5082 (set_attr "mode" "SI")])
5084 (define_insn "*lea_2_rex64"
5085 [(set (match_operand:DI 0 "register_operand" "=r")
5086 (match_operand:DI 1 "no_seg_address_operand" "p"))]
5088 "lea{q}\t{%a1, %0|%0, %a1}"
5089 [(set_attr "type" "lea")
5090 (set_attr "mode" "DI")])
5092 ;; The lea patterns for non-Pmodes needs to be matched by several
5093 ;; insns converted to real lea by splitters.
5095 (define_insn_and_split "*lea_general_1"
5096 [(set (match_operand 0 "register_operand" "=r")
5097 (plus (plus (match_operand 1 "index_register_operand" "r")
5098 (match_operand 2 "register_operand" "r"))
5099 (match_operand 3 "immediate_operand" "i")))]
5100 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5101 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5102 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5103 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5104 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5105 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5106 || GET_MODE (operands[3]) == VOIDmode)"
5108 "&& reload_completed"
5112 operands[0] = gen_lowpart (SImode, operands[0]);
5113 operands[1] = gen_lowpart (Pmode, operands[1]);
5114 operands[2] = gen_lowpart (Pmode, operands[2]);
5115 operands[3] = gen_lowpart (Pmode, operands[3]);
5116 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5118 if (Pmode != SImode)
5119 pat = gen_rtx_SUBREG (SImode, pat, 0);
5120 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5123 [(set_attr "type" "lea")
5124 (set_attr "mode" "SI")])
5126 (define_insn_and_split "*lea_general_1_zext"
5127 [(set (match_operand:DI 0 "register_operand" "=r")
5129 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
5130 (match_operand:SI 2 "register_operand" "r"))
5131 (match_operand:SI 3 "immediate_operand" "i"))))]
5134 "&& reload_completed"
5136 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5138 (match_dup 3)) 0)))]
5140 operands[1] = gen_lowpart (Pmode, operands[1]);
5141 operands[2] = gen_lowpart (Pmode, operands[2]);
5142 operands[3] = gen_lowpart (Pmode, operands[3]);
5144 [(set_attr "type" "lea")
5145 (set_attr "mode" "SI")])
5147 (define_insn_and_split "*lea_general_2"
5148 [(set (match_operand 0 "register_operand" "=r")
5149 (plus (mult (match_operand 1 "index_register_operand" "r")
5150 (match_operand 2 "const248_operand" "i"))
5151 (match_operand 3 "nonmemory_operand" "ri")))]
5152 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5153 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5154 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5155 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5156 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5157 || GET_MODE (operands[3]) == VOIDmode)"
5159 "&& reload_completed"
5163 operands[0] = gen_lowpart (SImode, operands[0]);
5164 operands[1] = gen_lowpart (Pmode, operands[1]);
5165 operands[3] = gen_lowpart (Pmode, operands[3]);
5166 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5168 if (Pmode != SImode)
5169 pat = gen_rtx_SUBREG (SImode, pat, 0);
5170 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5173 [(set_attr "type" "lea")
5174 (set_attr "mode" "SI")])
5176 (define_insn_and_split "*lea_general_2_zext"
5177 [(set (match_operand:DI 0 "register_operand" "=r")
5179 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5180 (match_operand:SI 2 "const248_operand" "n"))
5181 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5184 "&& reload_completed"
5186 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5188 (match_dup 3)) 0)))]
5190 operands[1] = gen_lowpart (Pmode, operands[1]);
5191 operands[3] = gen_lowpart (Pmode, operands[3]);
5193 [(set_attr "type" "lea")
5194 (set_attr "mode" "SI")])
5196 (define_insn_and_split "*lea_general_3"
5197 [(set (match_operand 0 "register_operand" "=r")
5198 (plus (plus (mult (match_operand 1 "index_register_operand" "r")
5199 (match_operand 2 "const248_operand" "i"))
5200 (match_operand 3 "register_operand" "r"))
5201 (match_operand 4 "immediate_operand" "i")))]
5202 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5203 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5204 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5205 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5206 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5208 "&& reload_completed"
5212 operands[0] = gen_lowpart (SImode, operands[0]);
5213 operands[1] = gen_lowpart (Pmode, operands[1]);
5214 operands[3] = gen_lowpart (Pmode, operands[3]);
5215 operands[4] = gen_lowpart (Pmode, operands[4]);
5216 pat = gen_rtx_PLUS (Pmode,
5217 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5221 if (Pmode != SImode)
5222 pat = gen_rtx_SUBREG (SImode, pat, 0);
5223 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5226 [(set_attr "type" "lea")
5227 (set_attr "mode" "SI")])
5229 (define_insn_and_split "*lea_general_3_zext"
5230 [(set (match_operand:DI 0 "register_operand" "=r")
5232 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5233 (match_operand:SI 2 "const248_operand" "n"))
5234 (match_operand:SI 3 "register_operand" "r"))
5235 (match_operand:SI 4 "immediate_operand" "i"))))]
5238 "&& reload_completed"
5240 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5243 (match_dup 4)) 0)))]
5245 operands[1] = gen_lowpart (Pmode, operands[1]);
5246 operands[3] = gen_lowpart (Pmode, operands[3]);
5247 operands[4] = gen_lowpart (Pmode, operands[4]);
5249 [(set_attr "type" "lea")
5250 (set_attr "mode" "SI")])
5252 (define_insn "*adddi_1_rex64"
5253 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5254 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5255 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5256 (clobber (reg:CC 17))]
5257 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5259 switch (get_attr_type (insn))
5262 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5263 return "lea{q}\t{%a2, %0|%0, %a2}";
5266 if (! rtx_equal_p (operands[0], operands[1]))
5268 if (operands[2] == const1_rtx)
5269 return "inc{q}\t%0";
5270 else if (operands[2] == constm1_rtx)
5271 return "dec{q}\t%0";
5276 if (! rtx_equal_p (operands[0], operands[1]))
5279 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5280 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5281 if (GET_CODE (operands[2]) == CONST_INT
5282 /* Avoid overflows. */
5283 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5284 && (INTVAL (operands[2]) == 128
5285 || (INTVAL (operands[2]) < 0
5286 && INTVAL (operands[2]) != -128)))
5288 operands[2] = GEN_INT (-INTVAL (operands[2]));
5289 return "sub{q}\t{%2, %0|%0, %2}";
5291 return "add{q}\t{%2, %0|%0, %2}";
5295 (cond [(eq_attr "alternative" "2")
5296 (const_string "lea")
5297 ; Current assemblers are broken and do not allow @GOTOFF in
5298 ; ought but a memory context.
5299 (match_operand:DI 2 "pic_symbolic_operand" "")
5300 (const_string "lea")
5301 (match_operand:DI 2 "incdec_operand" "")
5302 (const_string "incdec")
5304 (const_string "alu")))
5305 (set_attr "mode" "DI")])
5307 ;; Convert lea to the lea pattern to avoid flags dependency.
5309 [(set (match_operand:DI 0 "register_operand" "")
5310 (plus:DI (match_operand:DI 1 "register_operand" "")
5311 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5312 (clobber (reg:CC 17))]
5313 "TARGET_64BIT && reload_completed
5314 && true_regnum (operands[0]) != true_regnum (operands[1])"
5316 (plus:DI (match_dup 1)
5320 (define_insn "*adddi_2_rex64"
5323 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5324 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5326 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5327 (plus:DI (match_dup 1) (match_dup 2)))]
5328 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5329 && ix86_binary_operator_ok (PLUS, DImode, operands)
5330 /* Current assemblers are broken and do not allow @GOTOFF in
5331 ought but a memory context. */
5332 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5334 switch (get_attr_type (insn))
5337 if (! rtx_equal_p (operands[0], operands[1]))
5339 if (operands[2] == const1_rtx)
5340 return "inc{q}\t%0";
5341 else if (operands[2] == constm1_rtx)
5342 return "dec{q}\t%0";
5347 if (! rtx_equal_p (operands[0], operands[1]))
5349 /* ???? We ought to handle there the 32bit case too
5350 - do we need new constraint? */
5351 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5352 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5353 if (GET_CODE (operands[2]) == CONST_INT
5354 /* Avoid overflows. */
5355 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5356 && (INTVAL (operands[2]) == 128
5357 || (INTVAL (operands[2]) < 0
5358 && INTVAL (operands[2]) != -128)))
5360 operands[2] = GEN_INT (-INTVAL (operands[2]));
5361 return "sub{q}\t{%2, %0|%0, %2}";
5363 return "add{q}\t{%2, %0|%0, %2}";
5367 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5368 (const_string "incdec")
5369 (const_string "alu")))
5370 (set_attr "mode" "DI")])
5372 (define_insn "*adddi_3_rex64"
5374 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5375 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5376 (clobber (match_scratch:DI 0 "=r"))]
5378 && ix86_match_ccmode (insn, CCZmode)
5379 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5380 /* Current assemblers are broken and do not allow @GOTOFF in
5381 ought but a memory context. */
5382 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5384 switch (get_attr_type (insn))
5387 if (! rtx_equal_p (operands[0], operands[1]))
5389 if (operands[2] == const1_rtx)
5390 return "inc{q}\t%0";
5391 else if (operands[2] == constm1_rtx)
5392 return "dec{q}\t%0";
5397 if (! rtx_equal_p (operands[0], operands[1]))
5399 /* ???? We ought to handle there the 32bit case too
5400 - do we need new constraint? */
5401 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5402 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5403 if (GET_CODE (operands[2]) == CONST_INT
5404 /* Avoid overflows. */
5405 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5406 && (INTVAL (operands[2]) == 128
5407 || (INTVAL (operands[2]) < 0
5408 && INTVAL (operands[2]) != -128)))
5410 operands[2] = GEN_INT (-INTVAL (operands[2]));
5411 return "sub{q}\t{%2, %0|%0, %2}";
5413 return "add{q}\t{%2, %0|%0, %2}";
5417 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5418 (const_string "incdec")
5419 (const_string "alu")))
5420 (set_attr "mode" "DI")])
5422 ; For comparisons against 1, -1 and 128, we may generate better code
5423 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5424 ; is matched then. We can't accept general immediate, because for
5425 ; case of overflows, the result is messed up.
5426 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5428 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5429 ; only for comparisons not depending on it.
5430 (define_insn "*adddi_4_rex64"
5432 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5433 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5434 (clobber (match_scratch:DI 0 "=rm"))]
5436 && ix86_match_ccmode (insn, CCGCmode)"
5438 switch (get_attr_type (insn))
5441 if (operands[2] == constm1_rtx)
5442 return "inc{q}\t%0";
5443 else if (operands[2] == const1_rtx)
5444 return "dec{q}\t%0";
5449 if (! rtx_equal_p (operands[0], operands[1]))
5451 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5452 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5453 if ((INTVAL (operands[2]) == -128
5454 || (INTVAL (operands[2]) > 0
5455 && INTVAL (operands[2]) != 128))
5456 /* Avoid overflows. */
5457 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5458 return "sub{q}\t{%2, %0|%0, %2}";
5459 operands[2] = GEN_INT (-INTVAL (operands[2]));
5460 return "add{q}\t{%2, %0|%0, %2}";
5464 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5465 (const_string "incdec")
5466 (const_string "alu")))
5467 (set_attr "mode" "DI")])
5469 (define_insn "*adddi_5_rex64"
5472 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5473 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5475 (clobber (match_scratch:DI 0 "=r"))]
5477 && ix86_match_ccmode (insn, CCGOCmode)
5478 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5479 /* Current assemblers are broken and do not allow @GOTOFF in
5480 ought but a memory context. */
5481 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5483 switch (get_attr_type (insn))
5486 if (! rtx_equal_p (operands[0], operands[1]))
5488 if (operands[2] == const1_rtx)
5489 return "inc{q}\t%0";
5490 else if (operands[2] == constm1_rtx)
5491 return "dec{q}\t%0";
5496 if (! rtx_equal_p (operands[0], operands[1]))
5498 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5499 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5500 if (GET_CODE (operands[2]) == CONST_INT
5501 /* Avoid overflows. */
5502 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5503 && (INTVAL (operands[2]) == 128
5504 || (INTVAL (operands[2]) < 0
5505 && INTVAL (operands[2]) != -128)))
5507 operands[2] = GEN_INT (-INTVAL (operands[2]));
5508 return "sub{q}\t{%2, %0|%0, %2}";
5510 return "add{q}\t{%2, %0|%0, %2}";
5514 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5515 (const_string "incdec")
5516 (const_string "alu")))
5517 (set_attr "mode" "DI")])
5520 (define_insn "*addsi_1"
5521 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5522 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5523 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5524 (clobber (reg:CC 17))]
5525 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5527 switch (get_attr_type (insn))
5530 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5531 return "lea{l}\t{%a2, %0|%0, %a2}";
5534 if (! rtx_equal_p (operands[0], operands[1]))
5536 if (operands[2] == const1_rtx)
5537 return "inc{l}\t%0";
5538 else if (operands[2] == constm1_rtx)
5539 return "dec{l}\t%0";
5544 if (! rtx_equal_p (operands[0], operands[1]))
5547 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5548 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5549 if (GET_CODE (operands[2]) == CONST_INT
5550 && (INTVAL (operands[2]) == 128
5551 || (INTVAL (operands[2]) < 0
5552 && INTVAL (operands[2]) != -128)))
5554 operands[2] = GEN_INT (-INTVAL (operands[2]));
5555 return "sub{l}\t{%2, %0|%0, %2}";
5557 return "add{l}\t{%2, %0|%0, %2}";
5561 (cond [(eq_attr "alternative" "2")
5562 (const_string "lea")
5563 ; Current assemblers are broken and do not allow @GOTOFF in
5564 ; ought but a memory context.
5565 (match_operand:SI 2 "pic_symbolic_operand" "")
5566 (const_string "lea")
5567 (match_operand:SI 2 "incdec_operand" "")
5568 (const_string "incdec")
5570 (const_string "alu")))
5571 (set_attr "mode" "SI")])
5573 ;; Convert lea to the lea pattern to avoid flags dependency.
5575 [(set (match_operand 0 "register_operand" "")
5576 (plus (match_operand 1 "register_operand" "")
5577 (match_operand 2 "nonmemory_operand" "")))
5578 (clobber (reg:CC 17))]
5580 && true_regnum (operands[0]) != true_regnum (operands[1])"
5584 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5585 may confuse gen_lowpart. */
5586 if (GET_MODE (operands[0]) != Pmode)
5588 operands[1] = gen_lowpart (Pmode, operands[1]);
5589 operands[2] = gen_lowpart (Pmode, operands[2]);
5591 operands[0] = gen_lowpart (SImode, operands[0]);
5592 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5593 if (Pmode != SImode)
5594 pat = gen_rtx_SUBREG (SImode, pat, 0);
5595 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5599 ;; It may seem that nonimmediate operand is proper one for operand 1.
5600 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5601 ;; we take care in ix86_binary_operator_ok to not allow two memory
5602 ;; operands so proper swapping will be done in reload. This allow
5603 ;; patterns constructed from addsi_1 to match.
5604 (define_insn "addsi_1_zext"
5605 [(set (match_operand:DI 0 "register_operand" "=r,r")
5607 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5608 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5609 (clobber (reg:CC 17))]
5610 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5612 switch (get_attr_type (insn))
5615 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5616 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5619 if (operands[2] == const1_rtx)
5620 return "inc{l}\t%k0";
5621 else if (operands[2] == constm1_rtx)
5622 return "dec{l}\t%k0";
5627 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5628 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5629 if (GET_CODE (operands[2]) == CONST_INT
5630 && (INTVAL (operands[2]) == 128
5631 || (INTVAL (operands[2]) < 0
5632 && INTVAL (operands[2]) != -128)))
5634 operands[2] = GEN_INT (-INTVAL (operands[2]));
5635 return "sub{l}\t{%2, %k0|%k0, %2}";
5637 return "add{l}\t{%2, %k0|%k0, %2}";
5641 (cond [(eq_attr "alternative" "1")
5642 (const_string "lea")
5643 ; Current assemblers are broken and do not allow @GOTOFF in
5644 ; ought but a memory context.
5645 (match_operand:SI 2 "pic_symbolic_operand" "")
5646 (const_string "lea")
5647 (match_operand:SI 2 "incdec_operand" "")
5648 (const_string "incdec")
5650 (const_string "alu")))
5651 (set_attr "mode" "SI")])
5653 ;; Convert lea to the lea pattern to avoid flags dependency.
5655 [(set (match_operand:DI 0 "register_operand" "")
5657 (plus:SI (match_operand:SI 1 "register_operand" "")
5658 (match_operand:SI 2 "nonmemory_operand" ""))))
5659 (clobber (reg:CC 17))]
5660 "TARGET_64BIT && reload_completed
5661 && true_regnum (operands[0]) != true_regnum (operands[1])"
5663 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5665 operands[1] = gen_lowpart (Pmode, operands[1]);
5666 operands[2] = gen_lowpart (Pmode, operands[2]);
5669 (define_insn "*addsi_2"
5672 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5673 (match_operand:SI 2 "general_operand" "rmni,rni"))
5675 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5676 (plus:SI (match_dup 1) (match_dup 2)))]
5677 "ix86_match_ccmode (insn, CCGOCmode)
5678 && ix86_binary_operator_ok (PLUS, SImode, operands)
5679 /* Current assemblers are broken and do not allow @GOTOFF in
5680 ought but a memory context. */
5681 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5683 switch (get_attr_type (insn))
5686 if (! rtx_equal_p (operands[0], operands[1]))
5688 if (operands[2] == const1_rtx)
5689 return "inc{l}\t%0";
5690 else if (operands[2] == constm1_rtx)
5691 return "dec{l}\t%0";
5696 if (! rtx_equal_p (operands[0], operands[1]))
5698 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5699 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5700 if (GET_CODE (operands[2]) == CONST_INT
5701 && (INTVAL (operands[2]) == 128
5702 || (INTVAL (operands[2]) < 0
5703 && INTVAL (operands[2]) != -128)))
5705 operands[2] = GEN_INT (-INTVAL (operands[2]));
5706 return "sub{l}\t{%2, %0|%0, %2}";
5708 return "add{l}\t{%2, %0|%0, %2}";
5712 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5713 (const_string "incdec")
5714 (const_string "alu")))
5715 (set_attr "mode" "SI")])
5717 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5718 (define_insn "*addsi_2_zext"
5721 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5722 (match_operand:SI 2 "general_operand" "rmni"))
5724 (set (match_operand:DI 0 "register_operand" "=r")
5725 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5726 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5727 && ix86_binary_operator_ok (PLUS, SImode, operands)
5728 /* Current assemblers are broken and do not allow @GOTOFF in
5729 ought but a memory context. */
5730 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5732 switch (get_attr_type (insn))
5735 if (operands[2] == const1_rtx)
5736 return "inc{l}\t%k0";
5737 else if (operands[2] == constm1_rtx)
5738 return "dec{l}\t%k0";
5743 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5744 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5745 if (GET_CODE (operands[2]) == CONST_INT
5746 && (INTVAL (operands[2]) == 128
5747 || (INTVAL (operands[2]) < 0
5748 && INTVAL (operands[2]) != -128)))
5750 operands[2] = GEN_INT (-INTVAL (operands[2]));
5751 return "sub{l}\t{%2, %k0|%k0, %2}";
5753 return "add{l}\t{%2, %k0|%k0, %2}";
5757 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5758 (const_string "incdec")
5759 (const_string "alu")))
5760 (set_attr "mode" "SI")])
5762 (define_insn "*addsi_3"
5764 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5765 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5766 (clobber (match_scratch:SI 0 "=r"))]
5767 "ix86_match_ccmode (insn, CCZmode)
5768 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5769 /* Current assemblers are broken and do not allow @GOTOFF in
5770 ought but a memory context. */
5771 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5773 switch (get_attr_type (insn))
5776 if (! rtx_equal_p (operands[0], operands[1]))
5778 if (operands[2] == const1_rtx)
5779 return "inc{l}\t%0";
5780 else if (operands[2] == constm1_rtx)
5781 return "dec{l}\t%0";
5786 if (! rtx_equal_p (operands[0], operands[1]))
5788 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5789 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5790 if (GET_CODE (operands[2]) == CONST_INT
5791 && (INTVAL (operands[2]) == 128
5792 || (INTVAL (operands[2]) < 0
5793 && INTVAL (operands[2]) != -128)))
5795 operands[2] = GEN_INT (-INTVAL (operands[2]));
5796 return "sub{l}\t{%2, %0|%0, %2}";
5798 return "add{l}\t{%2, %0|%0, %2}";
5802 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5803 (const_string "incdec")
5804 (const_string "alu")))
5805 (set_attr "mode" "SI")])
5807 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5808 (define_insn "*addsi_3_zext"
5810 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5811 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5812 (set (match_operand:DI 0 "register_operand" "=r")
5813 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5814 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5815 && ix86_binary_operator_ok (PLUS, SImode, operands)
5816 /* Current assemblers are broken and do not allow @GOTOFF in
5817 ought but a memory context. */
5818 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5820 switch (get_attr_type (insn))
5823 if (operands[2] == const1_rtx)
5824 return "inc{l}\t%k0";
5825 else if (operands[2] == constm1_rtx)
5826 return "dec{l}\t%k0";
5831 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5832 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5833 if (GET_CODE (operands[2]) == CONST_INT
5834 && (INTVAL (operands[2]) == 128
5835 || (INTVAL (operands[2]) < 0
5836 && INTVAL (operands[2]) != -128)))
5838 operands[2] = GEN_INT (-INTVAL (operands[2]));
5839 return "sub{l}\t{%2, %k0|%k0, %2}";
5841 return "add{l}\t{%2, %k0|%k0, %2}";
5845 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5846 (const_string "incdec")
5847 (const_string "alu")))
5848 (set_attr "mode" "SI")])
5850 ; For comparisons against 1, -1 and 128, we may generate better code
5851 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5852 ; is matched then. We can't accept general immediate, because for
5853 ; case of overflows, the result is messed up.
5854 ; This pattern also don't hold of 0x80000000, since the value overflows
5856 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5857 ; only for comparisons not depending on it.
5858 (define_insn "*addsi_4"
5860 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5861 (match_operand:SI 2 "const_int_operand" "n")))
5862 (clobber (match_scratch:SI 0 "=rm"))]
5863 "ix86_match_ccmode (insn, CCGCmode)
5864 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5866 switch (get_attr_type (insn))
5869 if (operands[2] == constm1_rtx)
5870 return "inc{l}\t%0";
5871 else if (operands[2] == const1_rtx)
5872 return "dec{l}\t%0";
5877 if (! rtx_equal_p (operands[0], operands[1]))
5879 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5880 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5881 if ((INTVAL (operands[2]) == -128
5882 || (INTVAL (operands[2]) > 0
5883 && INTVAL (operands[2]) != 128)))
5884 return "sub{l}\t{%2, %0|%0, %2}";
5885 operands[2] = GEN_INT (-INTVAL (operands[2]));
5886 return "add{l}\t{%2, %0|%0, %2}";
5890 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5891 (const_string "incdec")
5892 (const_string "alu")))
5893 (set_attr "mode" "SI")])
5895 (define_insn "*addsi_5"
5898 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5899 (match_operand:SI 2 "general_operand" "rmni"))
5901 (clobber (match_scratch:SI 0 "=r"))]
5902 "ix86_match_ccmode (insn, CCGOCmode)
5903 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5904 /* Current assemblers are broken and do not allow @GOTOFF in
5905 ought but a memory context. */
5906 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5908 switch (get_attr_type (insn))
5911 if (! rtx_equal_p (operands[0], operands[1]))
5913 if (operands[2] == const1_rtx)
5914 return "inc{l}\t%0";
5915 else if (operands[2] == constm1_rtx)
5916 return "dec{l}\t%0";
5921 if (! rtx_equal_p (operands[0], operands[1]))
5923 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5924 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5925 if (GET_CODE (operands[2]) == CONST_INT
5926 && (INTVAL (operands[2]) == 128
5927 || (INTVAL (operands[2]) < 0
5928 && INTVAL (operands[2]) != -128)))
5930 operands[2] = GEN_INT (-INTVAL (operands[2]));
5931 return "sub{l}\t{%2, %0|%0, %2}";
5933 return "add{l}\t{%2, %0|%0, %2}";
5937 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5938 (const_string "incdec")
5939 (const_string "alu")))
5940 (set_attr "mode" "SI")])
5942 (define_expand "addhi3"
5943 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5944 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5945 (match_operand:HI 2 "general_operand" "")))
5946 (clobber (reg:CC 17))])]
5947 "TARGET_HIMODE_MATH"
5948 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5950 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5951 ;; type optimizations enabled by define-splits. This is not important
5952 ;; for PII, and in fact harmful because of partial register stalls.
5954 (define_insn "*addhi_1_lea"
5955 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
5956 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
5957 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
5958 (clobber (reg:CC 17))]
5959 "!TARGET_PARTIAL_REG_STALL
5960 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5962 switch (get_attr_type (insn))
5967 if (operands[2] == const1_rtx)
5968 return "inc{w}\t%0";
5969 else if (operands[2] == constm1_rtx)
5970 return "dec{w}\t%0";
5974 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5975 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5976 if (GET_CODE (operands[2]) == CONST_INT
5977 && (INTVAL (operands[2]) == 128
5978 || (INTVAL (operands[2]) < 0
5979 && INTVAL (operands[2]) != -128)))
5981 operands[2] = GEN_INT (-INTVAL (operands[2]));
5982 return "sub{w}\t{%2, %0|%0, %2}";
5984 return "add{w}\t{%2, %0|%0, %2}";
5988 (if_then_else (eq_attr "alternative" "2")
5989 (const_string "lea")
5990 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5991 (const_string "incdec")
5992 (const_string "alu"))))
5993 (set_attr "mode" "HI,HI,SI")])
5995 (define_insn "*addhi_1"
5996 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5997 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5998 (match_operand:HI 2 "general_operand" "ri,rm")))
5999 (clobber (reg:CC 17))]
6000 "TARGET_PARTIAL_REG_STALL
6001 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6003 switch (get_attr_type (insn))
6006 if (operands[2] == const1_rtx)
6007 return "inc{w}\t%0";
6008 else if (operands[2] == constm1_rtx)
6009 return "dec{w}\t%0";
6013 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6014 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6015 if (GET_CODE (operands[2]) == CONST_INT
6016 && (INTVAL (operands[2]) == 128
6017 || (INTVAL (operands[2]) < 0
6018 && INTVAL (operands[2]) != -128)))
6020 operands[2] = GEN_INT (-INTVAL (operands[2]));
6021 return "sub{w}\t{%2, %0|%0, %2}";
6023 return "add{w}\t{%2, %0|%0, %2}";
6027 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6028 (const_string "incdec")
6029 (const_string "alu")))
6030 (set_attr "mode" "HI")])
6032 (define_insn "*addhi_2"
6035 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6036 (match_operand:HI 2 "general_operand" "rmni,rni"))
6038 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6039 (plus:HI (match_dup 1) (match_dup 2)))]
6040 "ix86_match_ccmode (insn, CCGOCmode)
6041 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6043 switch (get_attr_type (insn))
6046 if (operands[2] == const1_rtx)
6047 return "inc{w}\t%0";
6048 else if (operands[2] == constm1_rtx)
6049 return "dec{w}\t%0";
6053 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6054 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6055 if (GET_CODE (operands[2]) == CONST_INT
6056 && (INTVAL (operands[2]) == 128
6057 || (INTVAL (operands[2]) < 0
6058 && INTVAL (operands[2]) != -128)))
6060 operands[2] = GEN_INT (-INTVAL (operands[2]));
6061 return "sub{w}\t{%2, %0|%0, %2}";
6063 return "add{w}\t{%2, %0|%0, %2}";
6067 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6068 (const_string "incdec")
6069 (const_string "alu")))
6070 (set_attr "mode" "HI")])
6072 (define_insn "*addhi_3"
6074 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6075 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6076 (clobber (match_scratch:HI 0 "=r"))]
6077 "ix86_match_ccmode (insn, CCZmode)
6078 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6080 switch (get_attr_type (insn))
6083 if (operands[2] == const1_rtx)
6084 return "inc{w}\t%0";
6085 else if (operands[2] == constm1_rtx)
6086 return "dec{w}\t%0";
6090 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6091 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6092 if (GET_CODE (operands[2]) == CONST_INT
6093 && (INTVAL (operands[2]) == 128
6094 || (INTVAL (operands[2]) < 0
6095 && INTVAL (operands[2]) != -128)))
6097 operands[2] = GEN_INT (-INTVAL (operands[2]));
6098 return "sub{w}\t{%2, %0|%0, %2}";
6100 return "add{w}\t{%2, %0|%0, %2}";
6104 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6105 (const_string "incdec")
6106 (const_string "alu")))
6107 (set_attr "mode" "HI")])
6109 ; See comments above addsi_3_imm for details.
6110 (define_insn "*addhi_4"
6112 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6113 (match_operand:HI 2 "const_int_operand" "n")))
6114 (clobber (match_scratch:HI 0 "=rm"))]
6115 "ix86_match_ccmode (insn, CCGCmode)
6116 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6118 switch (get_attr_type (insn))
6121 if (operands[2] == constm1_rtx)
6122 return "inc{w}\t%0";
6123 else if (operands[2] == const1_rtx)
6124 return "dec{w}\t%0";
6129 if (! rtx_equal_p (operands[0], operands[1]))
6131 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6132 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6133 if ((INTVAL (operands[2]) == -128
6134 || (INTVAL (operands[2]) > 0
6135 && INTVAL (operands[2]) != 128)))
6136 return "sub{w}\t{%2, %0|%0, %2}";
6137 operands[2] = GEN_INT (-INTVAL (operands[2]));
6138 return "add{w}\t{%2, %0|%0, %2}";
6142 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6143 (const_string "incdec")
6144 (const_string "alu")))
6145 (set_attr "mode" "SI")])
6148 (define_insn "*addhi_5"
6151 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6152 (match_operand:HI 2 "general_operand" "rmni"))
6154 (clobber (match_scratch:HI 0 "=r"))]
6155 "ix86_match_ccmode (insn, CCGOCmode)
6156 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6158 switch (get_attr_type (insn))
6161 if (operands[2] == const1_rtx)
6162 return "inc{w}\t%0";
6163 else if (operands[2] == constm1_rtx)
6164 return "dec{w}\t%0";
6168 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6169 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6170 if (GET_CODE (operands[2]) == CONST_INT
6171 && (INTVAL (operands[2]) == 128
6172 || (INTVAL (operands[2]) < 0
6173 && INTVAL (operands[2]) != -128)))
6175 operands[2] = GEN_INT (-INTVAL (operands[2]));
6176 return "sub{w}\t{%2, %0|%0, %2}";
6178 return "add{w}\t{%2, %0|%0, %2}";
6182 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6183 (const_string "incdec")
6184 (const_string "alu")))
6185 (set_attr "mode" "HI")])
6187 (define_expand "addqi3"
6188 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6189 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6190 (match_operand:QI 2 "general_operand" "")))
6191 (clobber (reg:CC 17))])]
6192 "TARGET_QIMODE_MATH"
6193 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6195 ;; %%% Potential partial reg stall on alternative 2. What to do?
6196 (define_insn "*addqi_1_lea"
6197 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6198 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6199 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6200 (clobber (reg:CC 17))]
6201 "!TARGET_PARTIAL_REG_STALL
6202 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6204 int widen = (which_alternative == 2);
6205 switch (get_attr_type (insn))
6210 if (operands[2] == const1_rtx)
6211 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6212 else if (operands[2] == constm1_rtx)
6213 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6217 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6218 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6219 if (GET_CODE (operands[2]) == CONST_INT
6220 && (INTVAL (operands[2]) == 128
6221 || (INTVAL (operands[2]) < 0
6222 && INTVAL (operands[2]) != -128)))
6224 operands[2] = GEN_INT (-INTVAL (operands[2]));
6226 return "sub{l}\t{%2, %k0|%k0, %2}";
6228 return "sub{b}\t{%2, %0|%0, %2}";
6231 return "add{l}\t{%k2, %k0|%k0, %k2}";
6233 return "add{b}\t{%2, %0|%0, %2}";
6237 (if_then_else (eq_attr "alternative" "3")
6238 (const_string "lea")
6239 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6240 (const_string "incdec")
6241 (const_string "alu"))))
6242 (set_attr "mode" "QI,QI,SI,SI")])
6244 (define_insn "*addqi_1"
6245 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6246 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6247 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6248 (clobber (reg:CC 17))]
6249 "TARGET_PARTIAL_REG_STALL
6250 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6252 int widen = (which_alternative == 2);
6253 switch (get_attr_type (insn))
6256 if (operands[2] == const1_rtx)
6257 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6258 else if (operands[2] == constm1_rtx)
6259 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6263 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6264 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6265 if (GET_CODE (operands[2]) == CONST_INT
6266 && (INTVAL (operands[2]) == 128
6267 || (INTVAL (operands[2]) < 0
6268 && INTVAL (operands[2]) != -128)))
6270 operands[2] = GEN_INT (-INTVAL (operands[2]));
6272 return "sub{l}\t{%2, %k0|%k0, %2}";
6274 return "sub{b}\t{%2, %0|%0, %2}";
6277 return "add{l}\t{%k2, %k0|%k0, %k2}";
6279 return "add{b}\t{%2, %0|%0, %2}";
6283 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6284 (const_string "incdec")
6285 (const_string "alu")))
6286 (set_attr "mode" "QI,QI,SI")])
6288 (define_insn "*addqi_1_slp"
6289 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6290 (plus:QI (match_dup 0)
6291 (match_operand:QI 1 "general_operand" "qn,qnm")))
6292 (clobber (reg:CC 17))]
6293 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6294 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6296 switch (get_attr_type (insn))
6299 if (operands[1] == const1_rtx)
6300 return "inc{b}\t%0";
6301 else if (operands[1] == constm1_rtx)
6302 return "dec{b}\t%0";
6306 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6307 if (GET_CODE (operands[1]) == CONST_INT
6308 && INTVAL (operands[1]) < 0)
6310 operands[1] = GEN_INT (-INTVAL (operands[1]));
6311 return "sub{b}\t{%1, %0|%0, %1}";
6313 return "add{b}\t{%1, %0|%0, %1}";
6317 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6318 (const_string "incdec")
6319 (const_string "alu1")))
6320 (set_attr "mode" "QI")])
6322 (define_insn "*addqi_2"
6325 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6326 (match_operand:QI 2 "general_operand" "qmni,qni"))
6328 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6329 (plus:QI (match_dup 1) (match_dup 2)))]
6330 "ix86_match_ccmode (insn, CCGOCmode)
6331 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6333 switch (get_attr_type (insn))
6336 if (operands[2] == const1_rtx)
6337 return "inc{b}\t%0";
6338 else if (operands[2] == constm1_rtx
6339 || (GET_CODE (operands[2]) == CONST_INT
6340 && INTVAL (operands[2]) == 255))
6341 return "dec{b}\t%0";
6345 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6346 if (GET_CODE (operands[2]) == CONST_INT
6347 && INTVAL (operands[2]) < 0)
6349 operands[2] = GEN_INT (-INTVAL (operands[2]));
6350 return "sub{b}\t{%2, %0|%0, %2}";
6352 return "add{b}\t{%2, %0|%0, %2}";
6356 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6357 (const_string "incdec")
6358 (const_string "alu")))
6359 (set_attr "mode" "QI")])
6361 (define_insn "*addqi_3"
6363 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6364 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6365 (clobber (match_scratch:QI 0 "=q"))]
6366 "ix86_match_ccmode (insn, CCZmode)
6367 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6369 switch (get_attr_type (insn))
6372 if (operands[2] == const1_rtx)
6373 return "inc{b}\t%0";
6374 else if (operands[2] == constm1_rtx
6375 || (GET_CODE (operands[2]) == CONST_INT
6376 && INTVAL (operands[2]) == 255))
6377 return "dec{b}\t%0";
6381 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6382 if (GET_CODE (operands[2]) == CONST_INT
6383 && INTVAL (operands[2]) < 0)
6385 operands[2] = GEN_INT (-INTVAL (operands[2]));
6386 return "sub{b}\t{%2, %0|%0, %2}";
6388 return "add{b}\t{%2, %0|%0, %2}";
6392 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6393 (const_string "incdec")
6394 (const_string "alu")))
6395 (set_attr "mode" "QI")])
6397 ; See comments above addsi_3_imm for details.
6398 (define_insn "*addqi_4"
6400 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6401 (match_operand:QI 2 "const_int_operand" "n")))
6402 (clobber (match_scratch:QI 0 "=qm"))]
6403 "ix86_match_ccmode (insn, CCGCmode)
6404 && (INTVAL (operands[2]) & 0xff) != 0x80"
6406 switch (get_attr_type (insn))
6409 if (operands[2] == constm1_rtx
6410 || (GET_CODE (operands[2]) == CONST_INT
6411 && INTVAL (operands[2]) == 255))
6412 return "inc{b}\t%0";
6413 else if (operands[2] == const1_rtx)
6414 return "dec{b}\t%0";
6419 if (! rtx_equal_p (operands[0], operands[1]))
6421 if (INTVAL (operands[2]) < 0)
6423 operands[2] = GEN_INT (-INTVAL (operands[2]));
6424 return "add{b}\t{%2, %0|%0, %2}";
6426 return "sub{b}\t{%2, %0|%0, %2}";
6430 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6431 (const_string "incdec")
6432 (const_string "alu")))
6433 (set_attr "mode" "QI")])
6436 (define_insn "*addqi_5"
6439 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6440 (match_operand:QI 2 "general_operand" "qmni"))
6442 (clobber (match_scratch:QI 0 "=q"))]
6443 "ix86_match_ccmode (insn, CCGOCmode)
6444 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6446 switch (get_attr_type (insn))
6449 if (operands[2] == const1_rtx)
6450 return "inc{b}\t%0";
6451 else if (operands[2] == constm1_rtx
6452 || (GET_CODE (operands[2]) == CONST_INT
6453 && INTVAL (operands[2]) == 255))
6454 return "dec{b}\t%0";
6458 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6459 if (GET_CODE (operands[2]) == CONST_INT
6460 && INTVAL (operands[2]) < 0)
6462 operands[2] = GEN_INT (-INTVAL (operands[2]));
6463 return "sub{b}\t{%2, %0|%0, %2}";
6465 return "add{b}\t{%2, %0|%0, %2}";
6469 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6470 (const_string "incdec")
6471 (const_string "alu")))
6472 (set_attr "mode" "QI")])
6475 (define_insn "addqi_ext_1"
6476 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6481 (match_operand 1 "ext_register_operand" "0")
6484 (match_operand:QI 2 "general_operand" "Qmn")))
6485 (clobber (reg:CC 17))]
6488 switch (get_attr_type (insn))
6491 if (operands[2] == const1_rtx)
6492 return "inc{b}\t%h0";
6493 else if (operands[2] == constm1_rtx
6494 || (GET_CODE (operands[2]) == CONST_INT
6495 && INTVAL (operands[2]) == 255))
6496 return "dec{b}\t%h0";
6500 return "add{b}\t{%2, %h0|%h0, %2}";
6504 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6505 (const_string "incdec")
6506 (const_string "alu")))
6507 (set_attr "mode" "QI")])
6509 (define_insn "*addqi_ext_1_rex64"
6510 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6515 (match_operand 1 "ext_register_operand" "0")
6518 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6519 (clobber (reg:CC 17))]
6522 switch (get_attr_type (insn))
6525 if (operands[2] == const1_rtx)
6526 return "inc{b}\t%h0";
6527 else if (operands[2] == constm1_rtx
6528 || (GET_CODE (operands[2]) == CONST_INT
6529 && INTVAL (operands[2]) == 255))
6530 return "dec{b}\t%h0";
6534 return "add{b}\t{%2, %h0|%h0, %2}";
6538 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6539 (const_string "incdec")
6540 (const_string "alu")))
6541 (set_attr "mode" "QI")])
6543 (define_insn "*addqi_ext_2"
6544 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6549 (match_operand 1 "ext_register_operand" "%0")
6553 (match_operand 2 "ext_register_operand" "Q")
6556 (clobber (reg:CC 17))]
6558 "add{b}\t{%h2, %h0|%h0, %h2}"
6559 [(set_attr "type" "alu")
6560 (set_attr "mode" "QI")])
6562 ;; The patterns that match these are at the end of this file.
6564 (define_expand "addxf3"
6565 [(set (match_operand:XF 0 "register_operand" "")
6566 (plus:XF (match_operand:XF 1 "register_operand" "")
6567 (match_operand:XF 2 "register_operand" "")))]
6571 (define_expand "adddf3"
6572 [(set (match_operand:DF 0 "register_operand" "")
6573 (plus:DF (match_operand:DF 1 "register_operand" "")
6574 (match_operand:DF 2 "nonimmediate_operand" "")))]
6575 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6578 (define_expand "addsf3"
6579 [(set (match_operand:SF 0 "register_operand" "")
6580 (plus:SF (match_operand:SF 1 "register_operand" "")
6581 (match_operand:SF 2 "nonimmediate_operand" "")))]
6582 "TARGET_80387 || TARGET_SSE_MATH"
6585 ;; Subtract instructions
6587 ;; %%% splits for subsidi3
6589 (define_expand "subdi3"
6590 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6591 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6592 (match_operand:DI 2 "x86_64_general_operand" "")))
6593 (clobber (reg:CC 17))])]
6595 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6597 (define_insn "*subdi3_1"
6598 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6599 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6600 (match_operand:DI 2 "general_operand" "roiF,riF")))
6601 (clobber (reg:CC 17))]
6602 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6606 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6607 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6608 (match_operand:DI 2 "general_operand" "")))
6609 (clobber (reg:CC 17))]
6610 "!TARGET_64BIT && reload_completed"
6611 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6612 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6613 (parallel [(set (match_dup 3)
6614 (minus:SI (match_dup 4)
6615 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6617 (clobber (reg:CC 17))])]
6618 "split_di (operands+0, 1, operands+0, operands+3);
6619 split_di (operands+1, 1, operands+1, operands+4);
6620 split_di (operands+2, 1, operands+2, operands+5);")
6622 (define_insn "subdi3_carry_rex64"
6623 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6624 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6625 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6626 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6627 (clobber (reg:CC 17))]
6628 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6629 "sbb{q}\t{%2, %0|%0, %2}"
6630 [(set_attr "type" "alu")
6631 (set_attr "pent_pair" "pu")
6632 (set_attr "ppro_uops" "few")
6633 (set_attr "mode" "DI")])
6635 (define_insn "*subdi_1_rex64"
6636 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6637 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6638 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6639 (clobber (reg:CC 17))]
6640 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6641 "sub{q}\t{%2, %0|%0, %2}"
6642 [(set_attr "type" "alu")
6643 (set_attr "mode" "DI")])
6645 (define_insn "*subdi_2_rex64"
6648 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6649 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6651 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6652 (minus:DI (match_dup 1) (match_dup 2)))]
6653 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6654 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6655 "sub{q}\t{%2, %0|%0, %2}"
6656 [(set_attr "type" "alu")
6657 (set_attr "mode" "DI")])
6659 (define_insn "*subdi_3_rex63"
6661 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6662 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6663 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6664 (minus:DI (match_dup 1) (match_dup 2)))]
6665 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6666 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6667 "sub{q}\t{%2, %0|%0, %2}"
6668 [(set_attr "type" "alu")
6669 (set_attr "mode" "DI")])
6671 (define_insn "subqi3_carry"
6672 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6673 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6674 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6675 (match_operand:QI 2 "general_operand" "qi,qm"))))
6676 (clobber (reg:CC 17))]
6677 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6678 "sbb{b}\t{%2, %0|%0, %2}"
6679 [(set_attr "type" "alu")
6680 (set_attr "pent_pair" "pu")
6681 (set_attr "ppro_uops" "few")
6682 (set_attr "mode" "QI")])
6684 (define_insn "subhi3_carry"
6685 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6686 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6687 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6688 (match_operand:HI 2 "general_operand" "ri,rm"))))
6689 (clobber (reg:CC 17))]
6690 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6691 "sbb{w}\t{%2, %0|%0, %2}"
6692 [(set_attr "type" "alu")
6693 (set_attr "pent_pair" "pu")
6694 (set_attr "ppro_uops" "few")
6695 (set_attr "mode" "HI")])
6697 (define_insn "subsi3_carry"
6698 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6699 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6700 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6701 (match_operand:SI 2 "general_operand" "ri,rm"))))
6702 (clobber (reg:CC 17))]
6703 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6704 "sbb{l}\t{%2, %0|%0, %2}"
6705 [(set_attr "type" "alu")
6706 (set_attr "pent_pair" "pu")
6707 (set_attr "ppro_uops" "few")
6708 (set_attr "mode" "SI")])
6710 (define_insn "subsi3_carry_zext"
6711 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6713 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6714 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6715 (match_operand:SI 2 "general_operand" "ri,rm")))))
6716 (clobber (reg:CC 17))]
6717 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6718 "sbb{l}\t{%2, %k0|%k0, %2}"
6719 [(set_attr "type" "alu")
6720 (set_attr "pent_pair" "pu")
6721 (set_attr "ppro_uops" "few")
6722 (set_attr "mode" "SI")])
6724 (define_expand "subsi3"
6725 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6726 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6727 (match_operand:SI 2 "general_operand" "")))
6728 (clobber (reg:CC 17))])]
6730 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6732 (define_insn "*subsi_1"
6733 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6734 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6735 (match_operand:SI 2 "general_operand" "ri,rm")))
6736 (clobber (reg:CC 17))]
6737 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6738 "sub{l}\t{%2, %0|%0, %2}"
6739 [(set_attr "type" "alu")
6740 (set_attr "mode" "SI")])
6742 (define_insn "*subsi_1_zext"
6743 [(set (match_operand:DI 0 "register_operand" "=r")
6745 (minus:SI (match_operand:SI 1 "register_operand" "0")
6746 (match_operand:SI 2 "general_operand" "rim"))))
6747 (clobber (reg:CC 17))]
6748 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6749 "sub{l}\t{%2, %k0|%k0, %2}"
6750 [(set_attr "type" "alu")
6751 (set_attr "mode" "SI")])
6753 (define_insn "*subsi_2"
6756 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6757 (match_operand:SI 2 "general_operand" "ri,rm"))
6759 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6760 (minus:SI (match_dup 1) (match_dup 2)))]
6761 "ix86_match_ccmode (insn, CCGOCmode)
6762 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6763 "sub{l}\t{%2, %0|%0, %2}"
6764 [(set_attr "type" "alu")
6765 (set_attr "mode" "SI")])
6767 (define_insn "*subsi_2_zext"
6770 (minus:SI (match_operand:SI 1 "register_operand" "0")
6771 (match_operand:SI 2 "general_operand" "rim"))
6773 (set (match_operand:DI 0 "register_operand" "=r")
6775 (minus:SI (match_dup 1)
6777 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6778 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6779 "sub{l}\t{%2, %k0|%k0, %2}"
6780 [(set_attr "type" "alu")
6781 (set_attr "mode" "SI")])
6783 (define_insn "*subsi_3"
6785 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6786 (match_operand:SI 2 "general_operand" "ri,rm")))
6787 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6788 (minus:SI (match_dup 1) (match_dup 2)))]
6789 "ix86_match_ccmode (insn, CCmode)
6790 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6791 "sub{l}\t{%2, %0|%0, %2}"
6792 [(set_attr "type" "alu")
6793 (set_attr "mode" "SI")])
6795 (define_insn "*subsi_3_zext"
6797 (compare (match_operand:SI 1 "register_operand" "0")
6798 (match_operand:SI 2 "general_operand" "rim")))
6799 (set (match_operand:DI 0 "register_operand" "=r")
6801 (minus:SI (match_dup 1)
6803 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6804 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6805 "sub{q}\t{%2, %0|%0, %2}"
6806 [(set_attr "type" "alu")
6807 (set_attr "mode" "DI")])
6809 (define_expand "subhi3"
6810 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6811 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6812 (match_operand:HI 2 "general_operand" "")))
6813 (clobber (reg:CC 17))])]
6814 "TARGET_HIMODE_MATH"
6815 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6817 (define_insn "*subhi_1"
6818 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6819 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6820 (match_operand:HI 2 "general_operand" "ri,rm")))
6821 (clobber (reg:CC 17))]
6822 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6823 "sub{w}\t{%2, %0|%0, %2}"
6824 [(set_attr "type" "alu")
6825 (set_attr "mode" "HI")])
6827 (define_insn "*subhi_2"
6830 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6831 (match_operand:HI 2 "general_operand" "ri,rm"))
6833 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6834 (minus:HI (match_dup 1) (match_dup 2)))]
6835 "ix86_match_ccmode (insn, CCGOCmode)
6836 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6837 "sub{w}\t{%2, %0|%0, %2}"
6838 [(set_attr "type" "alu")
6839 (set_attr "mode" "HI")])
6841 (define_insn "*subhi_3"
6843 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6844 (match_operand:HI 2 "general_operand" "ri,rm")))
6845 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6846 (minus:HI (match_dup 1) (match_dup 2)))]
6847 "ix86_match_ccmode (insn, CCmode)
6848 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6849 "sub{w}\t{%2, %0|%0, %2}"
6850 [(set_attr "type" "alu")
6851 (set_attr "mode" "HI")])
6853 (define_expand "subqi3"
6854 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6855 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6856 (match_operand:QI 2 "general_operand" "")))
6857 (clobber (reg:CC 17))])]
6858 "TARGET_QIMODE_MATH"
6859 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6861 (define_insn "*subqi_1"
6862 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6863 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6864 (match_operand:QI 2 "general_operand" "qn,qmn")))
6865 (clobber (reg:CC 17))]
6866 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6867 "sub{b}\t{%2, %0|%0, %2}"
6868 [(set_attr "type" "alu")
6869 (set_attr "mode" "QI")])
6871 (define_insn "*subqi_1_slp"
6872 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6873 (minus:QI (match_dup 0)
6874 (match_operand:QI 1 "general_operand" "qn,qmn")))
6875 (clobber (reg:CC 17))]
6876 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6877 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6878 "sub{b}\t{%1, %0|%0, %1}"
6879 [(set_attr "type" "alu1")
6880 (set_attr "mode" "QI")])
6882 (define_insn "*subqi_2"
6885 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6886 (match_operand:QI 2 "general_operand" "qi,qm"))
6888 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6889 (minus:HI (match_dup 1) (match_dup 2)))]
6890 "ix86_match_ccmode (insn, CCGOCmode)
6891 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6892 "sub{b}\t{%2, %0|%0, %2}"
6893 [(set_attr "type" "alu")
6894 (set_attr "mode" "QI")])
6896 (define_insn "*subqi_3"
6898 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6899 (match_operand:QI 2 "general_operand" "qi,qm")))
6900 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6901 (minus:HI (match_dup 1) (match_dup 2)))]
6902 "ix86_match_ccmode (insn, CCmode)
6903 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6904 "sub{b}\t{%2, %0|%0, %2}"
6905 [(set_attr "type" "alu")
6906 (set_attr "mode" "QI")])
6908 ;; The patterns that match these are at the end of this file.
6910 (define_expand "subxf3"
6911 [(set (match_operand:XF 0 "register_operand" "")
6912 (minus:XF (match_operand:XF 1 "register_operand" "")
6913 (match_operand:XF 2 "register_operand" "")))]
6917 (define_expand "subdf3"
6918 [(set (match_operand:DF 0 "register_operand" "")
6919 (minus:DF (match_operand:DF 1 "register_operand" "")
6920 (match_operand:DF 2 "nonimmediate_operand" "")))]
6921 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6924 (define_expand "subsf3"
6925 [(set (match_operand:SF 0 "register_operand" "")
6926 (minus:SF (match_operand:SF 1 "register_operand" "")
6927 (match_operand:SF 2 "nonimmediate_operand" "")))]
6928 "TARGET_80387 || TARGET_SSE_MATH"
6931 ;; Multiply instructions
6933 (define_expand "muldi3"
6934 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6935 (mult:DI (match_operand:DI 1 "register_operand" "")
6936 (match_operand:DI 2 "x86_64_general_operand" "")))
6937 (clobber (reg:CC 17))])]
6941 (define_insn "*muldi3_1_rex64"
6942 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6943 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
6944 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6945 (clobber (reg:CC 17))]
6947 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6949 imul{q}\t{%2, %1, %0|%0, %1, %2}
6950 imul{q}\t{%2, %1, %0|%0, %1, %2}
6951 imul{q}\t{%2, %0|%0, %2}"
6952 [(set_attr "type" "imul")
6953 (set_attr "prefix_0f" "0,0,1")
6954 (set (attr "athlon_decode")
6955 (cond [(eq_attr "cpu" "athlon")
6956 (const_string "vector")
6957 (eq_attr "alternative" "1")
6958 (const_string "vector")
6959 (and (eq_attr "alternative" "2")
6960 (match_operand 1 "memory_operand" ""))
6961 (const_string "vector")]
6962 (const_string "direct")))
6963 (set_attr "mode" "DI")])
6965 (define_expand "mulsi3"
6966 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6967 (mult:SI (match_operand:SI 1 "register_operand" "")
6968 (match_operand:SI 2 "general_operand" "")))
6969 (clobber (reg:CC 17))])]
6973 (define_insn "*mulsi3_1"
6974 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
6975 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
6976 (match_operand:SI 2 "general_operand" "K,i,mr")))
6977 (clobber (reg:CC 17))]
6978 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6980 imul{l}\t{%2, %1, %0|%0, %1, %2}
6981 imul{l}\t{%2, %1, %0|%0, %1, %2}
6982 imul{l}\t{%2, %0|%0, %2}"
6983 [(set_attr "type" "imul")
6984 (set_attr "prefix_0f" "0,0,1")
6985 (set (attr "athlon_decode")
6986 (cond [(eq_attr "cpu" "athlon")
6987 (const_string "vector")
6988 (eq_attr "alternative" "1")
6989 (const_string "vector")
6990 (and (eq_attr "alternative" "2")
6991 (match_operand 1 "memory_operand" ""))
6992 (const_string "vector")]
6993 (const_string "direct")))
6994 (set_attr "mode" "SI")])
6996 (define_insn "*mulsi3_1_zext"
6997 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6999 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7000 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7001 (clobber (reg:CC 17))]
7003 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7005 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7006 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7007 imul{l}\t{%2, %k0|%k0, %2}"
7008 [(set_attr "type" "imul")
7009 (set_attr "prefix_0f" "0,0,1")
7010 (set (attr "athlon_decode")
7011 (cond [(eq_attr "cpu" "athlon")
7012 (const_string "vector")
7013 (eq_attr "alternative" "1")
7014 (const_string "vector")
7015 (and (eq_attr "alternative" "2")
7016 (match_operand 1 "memory_operand" ""))
7017 (const_string "vector")]
7018 (const_string "direct")))
7019 (set_attr "mode" "SI")])
7021 (define_expand "mulhi3"
7022 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7023 (mult:HI (match_operand:HI 1 "register_operand" "")
7024 (match_operand:HI 2 "general_operand" "")))
7025 (clobber (reg:CC 17))])]
7026 "TARGET_HIMODE_MATH"
7029 (define_insn "*mulhi3_1"
7030 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7031 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7032 (match_operand:HI 2 "general_operand" "K,i,mr")))
7033 (clobber (reg:CC 17))]
7034 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7036 imul{w}\t{%2, %1, %0|%0, %1, %2}
7037 imul{w}\t{%2, %1, %0|%0, %1, %2}
7038 imul{w}\t{%2, %0|%0, %2}"
7039 [(set_attr "type" "imul")
7040 (set_attr "prefix_0f" "0,0,1")
7041 (set (attr "athlon_decode")
7042 (cond [(eq_attr "cpu" "athlon")
7043 (const_string "vector")
7044 (eq_attr "alternative" "1,2")
7045 (const_string "vector")]
7046 (const_string "direct")))
7047 (set_attr "mode" "HI")])
7049 (define_expand "mulqi3"
7050 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7051 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7052 (match_operand:QI 2 "register_operand" "")))
7053 (clobber (reg:CC 17))])]
7054 "TARGET_QIMODE_MATH"
7057 (define_insn "*mulqi3_1"
7058 [(set (match_operand:QI 0 "register_operand" "=a")
7059 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7060 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7061 (clobber (reg:CC 17))]
7063 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7065 [(set_attr "type" "imul")
7066 (set_attr "length_immediate" "0")
7067 (set (attr "athlon_decode")
7068 (if_then_else (eq_attr "cpu" "athlon")
7069 (const_string "vector")
7070 (const_string "direct")))
7071 (set_attr "mode" "QI")])
7073 (define_expand "umulqihi3"
7074 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7075 (mult:HI (zero_extend:HI
7076 (match_operand:QI 1 "nonimmediate_operand" ""))
7078 (match_operand:QI 2 "register_operand" ""))))
7079 (clobber (reg:CC 17))])]
7080 "TARGET_QIMODE_MATH"
7083 (define_insn "*umulqihi3_1"
7084 [(set (match_operand:HI 0 "register_operand" "=a")
7085 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7086 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7087 (clobber (reg:CC 17))]
7089 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7091 [(set_attr "type" "imul")
7092 (set_attr "length_immediate" "0")
7093 (set (attr "athlon_decode")
7094 (if_then_else (eq_attr "cpu" "athlon")
7095 (const_string "vector")
7096 (const_string "direct")))
7097 (set_attr "mode" "QI")])
7099 (define_expand "mulqihi3"
7100 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7101 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7102 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7103 (clobber (reg:CC 17))])]
7104 "TARGET_QIMODE_MATH"
7107 (define_insn "*mulqihi3_insn"
7108 [(set (match_operand:HI 0 "register_operand" "=a")
7109 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7110 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7111 (clobber (reg:CC 17))]
7113 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7115 [(set_attr "type" "imul")
7116 (set_attr "length_immediate" "0")
7117 (set (attr "athlon_decode")
7118 (if_then_else (eq_attr "cpu" "athlon")
7119 (const_string "vector")
7120 (const_string "direct")))
7121 (set_attr "mode" "QI")])
7123 (define_expand "umulditi3"
7124 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7125 (mult:TI (zero_extend:TI
7126 (match_operand:DI 1 "nonimmediate_operand" ""))
7128 (match_operand:DI 2 "register_operand" ""))))
7129 (clobber (reg:CC 17))])]
7133 (define_insn "*umulditi3_insn"
7134 [(set (match_operand:TI 0 "register_operand" "=A")
7135 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7136 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7137 (clobber (reg:CC 17))]
7139 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7141 [(set_attr "type" "imul")
7142 (set_attr "ppro_uops" "few")
7143 (set_attr "length_immediate" "0")
7144 (set (attr "athlon_decode")
7145 (if_then_else (eq_attr "cpu" "athlon")
7146 (const_string "vector")
7147 (const_string "double")))
7148 (set_attr "mode" "DI")])
7150 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7151 (define_expand "umulsidi3"
7152 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7153 (mult:DI (zero_extend:DI
7154 (match_operand:SI 1 "nonimmediate_operand" ""))
7156 (match_operand:SI 2 "register_operand" ""))))
7157 (clobber (reg:CC 17))])]
7161 (define_insn "*umulsidi3_insn"
7162 [(set (match_operand:DI 0 "register_operand" "=A")
7163 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7164 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7165 (clobber (reg:CC 17))]
7167 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7169 [(set_attr "type" "imul")
7170 (set_attr "ppro_uops" "few")
7171 (set_attr "length_immediate" "0")
7172 (set (attr "athlon_decode")
7173 (if_then_else (eq_attr "cpu" "athlon")
7174 (const_string "vector")
7175 (const_string "double")))
7176 (set_attr "mode" "SI")])
7178 (define_expand "mulditi3"
7179 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7180 (mult:TI (sign_extend:TI
7181 (match_operand:DI 1 "nonimmediate_operand" ""))
7183 (match_operand:DI 2 "register_operand" ""))))
7184 (clobber (reg:CC 17))])]
7188 (define_insn "*mulditi3_insn"
7189 [(set (match_operand:TI 0 "register_operand" "=A")
7190 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7191 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7192 (clobber (reg:CC 17))]
7194 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7196 [(set_attr "type" "imul")
7197 (set_attr "length_immediate" "0")
7198 (set (attr "athlon_decode")
7199 (if_then_else (eq_attr "cpu" "athlon")
7200 (const_string "vector")
7201 (const_string "double")))
7202 (set_attr "mode" "DI")])
7204 (define_expand "mulsidi3"
7205 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7206 (mult:DI (sign_extend:DI
7207 (match_operand:SI 1 "nonimmediate_operand" ""))
7209 (match_operand:SI 2 "register_operand" ""))))
7210 (clobber (reg:CC 17))])]
7214 (define_insn "*mulsidi3_insn"
7215 [(set (match_operand:DI 0 "register_operand" "=A")
7216 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7217 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7218 (clobber (reg:CC 17))]
7220 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7222 [(set_attr "type" "imul")
7223 (set_attr "length_immediate" "0")
7224 (set (attr "athlon_decode")
7225 (if_then_else (eq_attr "cpu" "athlon")
7226 (const_string "vector")
7227 (const_string "double")))
7228 (set_attr "mode" "SI")])
7230 (define_expand "umuldi3_highpart"
7231 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7234 (mult:TI (zero_extend:TI
7235 (match_operand:DI 1 "nonimmediate_operand" ""))
7237 (match_operand:DI 2 "register_operand" "")))
7239 (clobber (match_scratch:DI 3 ""))
7240 (clobber (reg:CC 17))])]
7244 (define_insn "*umuldi3_highpart_rex64"
7245 [(set (match_operand:DI 0 "register_operand" "=d")
7248 (mult:TI (zero_extend:TI
7249 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7251 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7253 (clobber (match_scratch:DI 3 "=1"))
7254 (clobber (reg:CC 17))]
7256 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7258 [(set_attr "type" "imul")
7259 (set_attr "ppro_uops" "few")
7260 (set_attr "length_immediate" "0")
7261 (set (attr "athlon_decode")
7262 (if_then_else (eq_attr "cpu" "athlon")
7263 (const_string "vector")
7264 (const_string "double")))
7265 (set_attr "mode" "DI")])
7267 (define_expand "umulsi3_highpart"
7268 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7271 (mult:DI (zero_extend:DI
7272 (match_operand:SI 1 "nonimmediate_operand" ""))
7274 (match_operand:SI 2 "register_operand" "")))
7276 (clobber (match_scratch:SI 3 ""))
7277 (clobber (reg:CC 17))])]
7281 (define_insn "*umulsi3_highpart_insn"
7282 [(set (match_operand:SI 0 "register_operand" "=d")
7285 (mult:DI (zero_extend:DI
7286 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7288 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7290 (clobber (match_scratch:SI 3 "=1"))
7291 (clobber (reg:CC 17))]
7292 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7294 [(set_attr "type" "imul")
7295 (set_attr "ppro_uops" "few")
7296 (set_attr "length_immediate" "0")
7297 (set (attr "athlon_decode")
7298 (if_then_else (eq_attr "cpu" "athlon")
7299 (const_string "vector")
7300 (const_string "double")))
7301 (set_attr "mode" "SI")])
7303 (define_insn "*umulsi3_highpart_zext"
7304 [(set (match_operand:DI 0 "register_operand" "=d")
7305 (zero_extend:DI (truncate:SI
7307 (mult:DI (zero_extend:DI
7308 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7310 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7312 (clobber (match_scratch:SI 3 "=1"))
7313 (clobber (reg:CC 17))]
7315 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7317 [(set_attr "type" "imul")
7318 (set_attr "ppro_uops" "few")
7319 (set_attr "length_immediate" "0")
7320 (set (attr "athlon_decode")
7321 (if_then_else (eq_attr "cpu" "athlon")
7322 (const_string "vector")
7323 (const_string "double")))
7324 (set_attr "mode" "SI")])
7326 (define_expand "smuldi3_highpart"
7327 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7330 (mult:TI (sign_extend:TI
7331 (match_operand:DI 1 "nonimmediate_operand" ""))
7333 (match_operand:DI 2 "register_operand" "")))
7335 (clobber (match_scratch:DI 3 ""))
7336 (clobber (reg:CC 17))])]
7340 (define_insn "*smuldi3_highpart_rex64"
7341 [(set (match_operand:DI 0 "register_operand" "=d")
7344 (mult:TI (sign_extend:TI
7345 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7347 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7349 (clobber (match_scratch:DI 3 "=1"))
7350 (clobber (reg:CC 17))]
7352 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7354 [(set_attr "type" "imul")
7355 (set_attr "ppro_uops" "few")
7356 (set (attr "athlon_decode")
7357 (if_then_else (eq_attr "cpu" "athlon")
7358 (const_string "vector")
7359 (const_string "double")))
7360 (set_attr "mode" "DI")])
7362 (define_expand "smulsi3_highpart"
7363 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7366 (mult:DI (sign_extend:DI
7367 (match_operand:SI 1 "nonimmediate_operand" ""))
7369 (match_operand:SI 2 "register_operand" "")))
7371 (clobber (match_scratch:SI 3 ""))
7372 (clobber (reg:CC 17))])]
7376 (define_insn "*smulsi3_highpart_insn"
7377 [(set (match_operand:SI 0 "register_operand" "=d")
7380 (mult:DI (sign_extend:DI
7381 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7383 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7385 (clobber (match_scratch:SI 3 "=1"))
7386 (clobber (reg:CC 17))]
7387 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7389 [(set_attr "type" "imul")
7390 (set_attr "ppro_uops" "few")
7391 (set (attr "athlon_decode")
7392 (if_then_else (eq_attr "cpu" "athlon")
7393 (const_string "vector")
7394 (const_string "double")))
7395 (set_attr "mode" "SI")])
7397 (define_insn "*smulsi3_highpart_zext"
7398 [(set (match_operand:DI 0 "register_operand" "=d")
7399 (zero_extend:DI (truncate:SI
7401 (mult:DI (sign_extend:DI
7402 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7404 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7406 (clobber (match_scratch:SI 3 "=1"))
7407 (clobber (reg:CC 17))]
7409 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7411 [(set_attr "type" "imul")
7412 (set_attr "ppro_uops" "few")
7413 (set (attr "athlon_decode")
7414 (if_then_else (eq_attr "cpu" "athlon")
7415 (const_string "vector")
7416 (const_string "double")))
7417 (set_attr "mode" "SI")])
7419 ;; The patterns that match these are at the end of this file.
7421 (define_expand "mulxf3"
7422 [(set (match_operand:XF 0 "register_operand" "")
7423 (mult:XF (match_operand:XF 1 "register_operand" "")
7424 (match_operand:XF 2 "register_operand" "")))]
7428 (define_expand "muldf3"
7429 [(set (match_operand:DF 0 "register_operand" "")
7430 (mult:DF (match_operand:DF 1 "register_operand" "")
7431 (match_operand:DF 2 "nonimmediate_operand" "")))]
7432 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7435 (define_expand "mulsf3"
7436 [(set (match_operand:SF 0 "register_operand" "")
7437 (mult:SF (match_operand:SF 1 "register_operand" "")
7438 (match_operand:SF 2 "nonimmediate_operand" "")))]
7439 "TARGET_80387 || TARGET_SSE_MATH"
7442 ;; Divide instructions
7444 (define_insn "divqi3"
7445 [(set (match_operand:QI 0 "register_operand" "=a")
7446 (div:QI (match_operand:HI 1 "register_operand" "0")
7447 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7448 (clobber (reg:CC 17))]
7449 "TARGET_QIMODE_MATH"
7451 [(set_attr "type" "idiv")
7452 (set_attr "mode" "QI")
7453 (set_attr "ppro_uops" "few")])
7455 (define_insn "udivqi3"
7456 [(set (match_operand:QI 0 "register_operand" "=a")
7457 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7458 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7459 (clobber (reg:CC 17))]
7460 "TARGET_QIMODE_MATH"
7462 [(set_attr "type" "idiv")
7463 (set_attr "mode" "QI")
7464 (set_attr "ppro_uops" "few")])
7466 ;; The patterns that match these are at the end of this file.
7468 (define_expand "divxf3"
7469 [(set (match_operand:XF 0 "register_operand" "")
7470 (div:XF (match_operand:XF 1 "register_operand" "")
7471 (match_operand:XF 2 "register_operand" "")))]
7475 (define_expand "divdf3"
7476 [(set (match_operand:DF 0 "register_operand" "")
7477 (div:DF (match_operand:DF 1 "register_operand" "")
7478 (match_operand:DF 2 "nonimmediate_operand" "")))]
7479 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7482 (define_expand "divsf3"
7483 [(set (match_operand:SF 0 "register_operand" "")
7484 (div:SF (match_operand:SF 1 "register_operand" "")
7485 (match_operand:SF 2 "nonimmediate_operand" "")))]
7486 "TARGET_80387 || TARGET_SSE_MATH"
7489 ;; Remainder instructions.
7491 (define_expand "divmoddi4"
7492 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7493 (div:DI (match_operand:DI 1 "register_operand" "")
7494 (match_operand:DI 2 "nonimmediate_operand" "")))
7495 (set (match_operand:DI 3 "register_operand" "")
7496 (mod:DI (match_dup 1) (match_dup 2)))
7497 (clobber (reg:CC 17))])]
7501 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7502 ;; Penalize eax case slightly because it results in worse scheduling
7504 (define_insn "*divmoddi4_nocltd_rex64"
7505 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7506 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7507 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7508 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7509 (mod:DI (match_dup 2) (match_dup 3)))
7510 (clobber (reg:CC 17))]
7511 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7513 [(set_attr "type" "multi")])
7515 (define_insn "*divmoddi4_cltd_rex64"
7516 [(set (match_operand:DI 0 "register_operand" "=a")
7517 (div:DI (match_operand:DI 2 "register_operand" "a")
7518 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7519 (set (match_operand:DI 1 "register_operand" "=&d")
7520 (mod:DI (match_dup 2) (match_dup 3)))
7521 (clobber (reg:CC 17))]
7522 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7524 [(set_attr "type" "multi")])
7526 (define_insn "*divmoddi_noext_rex64"
7527 [(set (match_operand:DI 0 "register_operand" "=a")
7528 (div:DI (match_operand:DI 1 "register_operand" "0")
7529 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7530 (set (match_operand:DI 3 "register_operand" "=d")
7531 (mod:DI (match_dup 1) (match_dup 2)))
7532 (use (match_operand:DI 4 "register_operand" "3"))
7533 (clobber (reg:CC 17))]
7536 [(set_attr "type" "idiv")
7537 (set_attr "mode" "DI")
7538 (set_attr "ppro_uops" "few")])
7541 [(set (match_operand:DI 0 "register_operand" "")
7542 (div:DI (match_operand:DI 1 "register_operand" "")
7543 (match_operand:DI 2 "nonimmediate_operand" "")))
7544 (set (match_operand:DI 3 "register_operand" "")
7545 (mod:DI (match_dup 1) (match_dup 2)))
7546 (clobber (reg:CC 17))]
7547 "TARGET_64BIT && reload_completed"
7548 [(parallel [(set (match_dup 3)
7549 (ashiftrt:DI (match_dup 4) (const_int 63)))
7550 (clobber (reg:CC 17))])
7551 (parallel [(set (match_dup 0)
7552 (div:DI (reg:DI 0) (match_dup 2)))
7554 (mod:DI (reg:DI 0) (match_dup 2)))
7556 (clobber (reg:CC 17))])]
7558 /* Avoid use of cltd in favor of a mov+shift. */
7559 if (!TARGET_USE_CLTD && !optimize_size)
7561 if (true_regnum (operands[1]))
7562 emit_move_insn (operands[0], operands[1]);
7564 emit_move_insn (operands[3], operands[1]);
7565 operands[4] = operands[3];
7569 if (true_regnum (operands[1]))
7571 operands[4] = operands[1];
7576 (define_expand "divmodsi4"
7577 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7578 (div:SI (match_operand:SI 1 "register_operand" "")
7579 (match_operand:SI 2 "nonimmediate_operand" "")))
7580 (set (match_operand:SI 3 "register_operand" "")
7581 (mod:SI (match_dup 1) (match_dup 2)))
7582 (clobber (reg:CC 17))])]
7586 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7587 ;; Penalize eax case slightly because it results in worse scheduling
7589 (define_insn "*divmodsi4_nocltd"
7590 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7591 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7592 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7593 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7594 (mod:SI (match_dup 2) (match_dup 3)))
7595 (clobber (reg:CC 17))]
7596 "!optimize_size && !TARGET_USE_CLTD"
7598 [(set_attr "type" "multi")])
7600 (define_insn "*divmodsi4_cltd"
7601 [(set (match_operand:SI 0 "register_operand" "=a")
7602 (div:SI (match_operand:SI 2 "register_operand" "a")
7603 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7604 (set (match_operand:SI 1 "register_operand" "=&d")
7605 (mod:SI (match_dup 2) (match_dup 3)))
7606 (clobber (reg:CC 17))]
7607 "optimize_size || TARGET_USE_CLTD"
7609 [(set_attr "type" "multi")])
7611 (define_insn "*divmodsi_noext"
7612 [(set (match_operand:SI 0 "register_operand" "=a")
7613 (div:SI (match_operand:SI 1 "register_operand" "0")
7614 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7615 (set (match_operand:SI 3 "register_operand" "=d")
7616 (mod:SI (match_dup 1) (match_dup 2)))
7617 (use (match_operand:SI 4 "register_operand" "3"))
7618 (clobber (reg:CC 17))]
7621 [(set_attr "type" "idiv")
7622 (set_attr "mode" "SI")
7623 (set_attr "ppro_uops" "few")])
7626 [(set (match_operand:SI 0 "register_operand" "")
7627 (div:SI (match_operand:SI 1 "register_operand" "")
7628 (match_operand:SI 2 "nonimmediate_operand" "")))
7629 (set (match_operand:SI 3 "register_operand" "")
7630 (mod:SI (match_dup 1) (match_dup 2)))
7631 (clobber (reg:CC 17))]
7633 [(parallel [(set (match_dup 3)
7634 (ashiftrt:SI (match_dup 4) (const_int 31)))
7635 (clobber (reg:CC 17))])
7636 (parallel [(set (match_dup 0)
7637 (div:SI (reg:SI 0) (match_dup 2)))
7639 (mod:SI (reg:SI 0) (match_dup 2)))
7641 (clobber (reg:CC 17))])]
7643 /* Avoid use of cltd in favor of a mov+shift. */
7644 if (!TARGET_USE_CLTD && !optimize_size)
7646 if (true_regnum (operands[1]))
7647 emit_move_insn (operands[0], operands[1]);
7649 emit_move_insn (operands[3], operands[1]);
7650 operands[4] = operands[3];
7654 if (true_regnum (operands[1]))
7656 operands[4] = operands[1];
7660 (define_insn "divmodhi4"
7661 [(set (match_operand:HI 0 "register_operand" "=a")
7662 (div:HI (match_operand:HI 1 "register_operand" "0")
7663 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7664 (set (match_operand:HI 3 "register_operand" "=&d")
7665 (mod:HI (match_dup 1) (match_dup 2)))
7666 (clobber (reg:CC 17))]
7667 "TARGET_HIMODE_MATH"
7669 [(set_attr "type" "multi")
7670 (set_attr "length_immediate" "0")
7671 (set_attr "mode" "SI")])
7673 (define_insn "udivmoddi4"
7674 [(set (match_operand:DI 0 "register_operand" "=a")
7675 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7676 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7677 (set (match_operand:DI 3 "register_operand" "=&d")
7678 (umod:DI (match_dup 1) (match_dup 2)))
7679 (clobber (reg:CC 17))]
7681 "xor{q}\t%3, %3\;div{q}\t%2"
7682 [(set_attr "type" "multi")
7683 (set_attr "length_immediate" "0")
7684 (set_attr "mode" "DI")])
7686 (define_insn "*udivmoddi4_noext"
7687 [(set (match_operand:DI 0 "register_operand" "=a")
7688 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7689 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7690 (set (match_operand:DI 3 "register_operand" "=d")
7691 (umod:DI (match_dup 1) (match_dup 2)))
7693 (clobber (reg:CC 17))]
7696 [(set_attr "type" "idiv")
7697 (set_attr "ppro_uops" "few")
7698 (set_attr "mode" "DI")])
7701 [(set (match_operand:DI 0 "register_operand" "")
7702 (udiv:DI (match_operand:DI 1 "register_operand" "")
7703 (match_operand:DI 2 "nonimmediate_operand" "")))
7704 (set (match_operand:DI 3 "register_operand" "")
7705 (umod:DI (match_dup 1) (match_dup 2)))
7706 (clobber (reg:CC 17))]
7707 "TARGET_64BIT && reload_completed"
7708 [(set (match_dup 3) (const_int 0))
7709 (parallel [(set (match_dup 0)
7710 (udiv:DI (match_dup 1) (match_dup 2)))
7712 (umod:DI (match_dup 1) (match_dup 2)))
7714 (clobber (reg:CC 17))])]
7717 (define_insn "udivmodsi4"
7718 [(set (match_operand:SI 0 "register_operand" "=a")
7719 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7720 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7721 (set (match_operand:SI 3 "register_operand" "=&d")
7722 (umod:SI (match_dup 1) (match_dup 2)))
7723 (clobber (reg:CC 17))]
7725 "xor{l}\t%3, %3\;div{l}\t%2"
7726 [(set_attr "type" "multi")
7727 (set_attr "length_immediate" "0")
7728 (set_attr "mode" "SI")])
7730 (define_insn "*udivmodsi4_noext"
7731 [(set (match_operand:SI 0 "register_operand" "=a")
7732 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7733 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7734 (set (match_operand:SI 3 "register_operand" "=d")
7735 (umod:SI (match_dup 1) (match_dup 2)))
7737 (clobber (reg:CC 17))]
7740 [(set_attr "type" "idiv")
7741 (set_attr "ppro_uops" "few")
7742 (set_attr "mode" "SI")])
7745 [(set (match_operand:SI 0 "register_operand" "")
7746 (udiv:SI (match_operand:SI 1 "register_operand" "")
7747 (match_operand:SI 2 "nonimmediate_operand" "")))
7748 (set (match_operand:SI 3 "register_operand" "")
7749 (umod:SI (match_dup 1) (match_dup 2)))
7750 (clobber (reg:CC 17))]
7752 [(set (match_dup 3) (const_int 0))
7753 (parallel [(set (match_dup 0)
7754 (udiv:SI (match_dup 1) (match_dup 2)))
7756 (umod:SI (match_dup 1) (match_dup 2)))
7758 (clobber (reg:CC 17))])]
7761 (define_expand "udivmodhi4"
7762 [(set (match_dup 4) (const_int 0))
7763 (parallel [(set (match_operand:HI 0 "register_operand" "")
7764 (udiv:HI (match_operand:HI 1 "register_operand" "")
7765 (match_operand:HI 2 "nonimmediate_operand" "")))
7766 (set (match_operand:HI 3 "register_operand" "")
7767 (umod:HI (match_dup 1) (match_dup 2)))
7769 (clobber (reg:CC 17))])]
7770 "TARGET_HIMODE_MATH"
7771 "operands[4] = gen_reg_rtx (HImode);")
7773 (define_insn "*udivmodhi_noext"
7774 [(set (match_operand:HI 0 "register_operand" "=a")
7775 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7776 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7777 (set (match_operand:HI 3 "register_operand" "=d")
7778 (umod:HI (match_dup 1) (match_dup 2)))
7779 (use (match_operand:HI 4 "register_operand" "3"))
7780 (clobber (reg:CC 17))]
7783 [(set_attr "type" "idiv")
7784 (set_attr "mode" "HI")
7785 (set_attr "ppro_uops" "few")])
7787 ;; We can not use div/idiv for double division, because it causes
7788 ;; "division by zero" on the overflow and that's not what we expect
7789 ;; from truncate. Because true (non truncating) double division is
7790 ;; never generated, we can't create this insn anyway.
7793 ; [(set (match_operand:SI 0 "register_operand" "=a")
7795 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7797 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7798 ; (set (match_operand:SI 3 "register_operand" "=d")
7800 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7801 ; (clobber (reg:CC 17))]
7803 ; "div{l}\t{%2, %0|%0, %2}"
7804 ; [(set_attr "type" "idiv")
7805 ; (set_attr "ppro_uops" "few")])
7807 ;;- Logical AND instructions
7809 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7810 ;; Note that this excludes ah.
7812 (define_insn "*testdi_1_rex64"
7815 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
7816 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
7818 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7819 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7821 test{l}\t{%k1, %k0|%k0, %k1}
7822 test{l}\t{%k1, %k0|%k0, %k1}
7823 test{q}\t{%1, %0|%0, %1}
7824 test{q}\t{%1, %0|%0, %1}
7825 test{q}\t{%1, %0|%0, %1}"
7826 [(set_attr "type" "test")
7827 (set_attr "modrm" "0,1,0,1,1")
7828 (set_attr "mode" "SI,SI,DI,DI,DI")
7829 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7831 (define_insn "testsi_1"
7834 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
7835 (match_operand:SI 1 "general_operand" "in,in,rin"))
7837 "ix86_match_ccmode (insn, CCNOmode)
7838 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7839 "test{l}\t{%1, %0|%0, %1}"
7840 [(set_attr "type" "test")
7841 (set_attr "modrm" "0,1,1")
7842 (set_attr "mode" "SI")
7843 (set_attr "pent_pair" "uv,np,uv")])
7845 (define_expand "testsi_ccno_1"
7848 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7849 (match_operand:SI 1 "nonmemory_operand" ""))
7854 (define_insn "*testhi_1"
7856 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
7857 (match_operand:HI 1 "general_operand" "n,n,rn"))
7859 "ix86_match_ccmode (insn, CCNOmode)
7860 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7861 "test{w}\t{%1, %0|%0, %1}"
7862 [(set_attr "type" "test")
7863 (set_attr "modrm" "0,1,1")
7864 (set_attr "mode" "HI")
7865 (set_attr "pent_pair" "uv,np,uv")])
7867 (define_expand "testqi_ccz_1"
7869 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7870 (match_operand:QI 1 "nonmemory_operand" ""))
7875 (define_insn "*testqi_1"
7877 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
7878 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
7880 "ix86_match_ccmode (insn, CCNOmode)
7881 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7883 if (which_alternative == 3)
7885 if (GET_CODE (operands[1]) == CONST_INT
7886 && (INTVAL (operands[1]) & 0xffffff00))
7887 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7888 return "test{l}\t{%1, %k0|%k0, %1}";
7890 return "test{b}\t{%1, %0|%0, %1}";
7892 [(set_attr "type" "test")
7893 (set_attr "modrm" "0,1,1,1")
7894 (set_attr "mode" "QI,QI,QI,SI")
7895 (set_attr "pent_pair" "uv,np,uv,np")])
7897 (define_expand "testqi_ext_ccno_0"
7902 (match_operand 0 "ext_register_operand" "")
7905 (match_operand 1 "const_int_operand" ""))
7910 (define_insn "*testqi_ext_0"
7915 (match_operand 0 "ext_register_operand" "Q")
7918 (match_operand 1 "const_int_operand" "n"))
7920 "ix86_match_ccmode (insn, CCNOmode)"
7921 "test{b}\t{%1, %h0|%h0, %1}"
7922 [(set_attr "type" "test")
7923 (set_attr "mode" "QI")
7924 (set_attr "length_immediate" "1")
7925 (set_attr "pent_pair" "np")])
7927 (define_insn "*testqi_ext_1"
7932 (match_operand 0 "ext_register_operand" "Q")
7936 (match_operand:QI 1 "general_operand" "Qm")))
7938 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7939 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7940 "test{b}\t{%1, %h0|%h0, %1}"
7941 [(set_attr "type" "test")
7942 (set_attr "mode" "QI")])
7944 (define_insn "*testqi_ext_1_rex64"
7949 (match_operand 0 "ext_register_operand" "Q")
7953 (match_operand:QI 1 "register_operand" "Q")))
7955 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7956 "test{b}\t{%1, %h0|%h0, %1}"
7957 [(set_attr "type" "test")
7958 (set_attr "mode" "QI")])
7960 (define_insn "*testqi_ext_2"
7965 (match_operand 0 "ext_register_operand" "Q")
7969 (match_operand 1 "ext_register_operand" "Q")
7973 "ix86_match_ccmode (insn, CCNOmode)"
7974 "test{b}\t{%h1, %h0|%h0, %h1}"
7975 [(set_attr "type" "test")
7976 (set_attr "mode" "QI")])
7978 ;; Combine likes to form bit extractions for some tests. Humor it.
7979 (define_insn "*testqi_ext_3"
7981 (compare (zero_extract:SI
7982 (match_operand 0 "nonimmediate_operand" "rm")
7983 (match_operand:SI 1 "const_int_operand" "")
7984 (match_operand:SI 2 "const_int_operand" ""))
7986 "ix86_match_ccmode (insn, CCNOmode)
7987 && (GET_MODE (operands[0]) == SImode
7988 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
7989 || GET_MODE (operands[0]) == HImode
7990 || GET_MODE (operands[0]) == QImode)"
7993 (define_insn "*testqi_ext_3_rex64"
7995 (compare (zero_extract:DI
7996 (match_operand 0 "nonimmediate_operand" "rm")
7997 (match_operand:DI 1 "const_int_operand" "")
7998 (match_operand:DI 2 "const_int_operand" ""))
8001 && ix86_match_ccmode (insn, CCNOmode)
8002 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
8003 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
8004 /* Ensure that resulting mask is zero or sign extended operand. */
8005 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8006 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8007 && INTVAL (operands[1]) > 32))
8008 && (GET_MODE (operands[0]) == SImode
8009 || GET_MODE (operands[0]) == DImode
8010 || GET_MODE (operands[0]) == HImode
8011 || GET_MODE (operands[0]) == QImode)"
8016 (compare (zero_extract
8017 (match_operand 0 "nonimmediate_operand" "")
8018 (match_operand 1 "const_int_operand" "")
8019 (match_operand 2 "const_int_operand" ""))
8021 "ix86_match_ccmode (insn, CCNOmode)"
8022 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8024 HOST_WIDE_INT len = INTVAL (operands[1]);
8025 HOST_WIDE_INT pos = INTVAL (operands[2]);
8027 enum machine_mode mode, submode;
8029 mode = GET_MODE (operands[0]);
8030 if (GET_CODE (operands[0]) == MEM)
8032 /* ??? Combine likes to put non-volatile mem extractions in QImode
8033 no matter the size of the test. So find a mode that works. */
8034 if (! MEM_VOLATILE_P (operands[0]))
8036 mode = smallest_mode_for_size (pos + len, MODE_INT);
8037 operands[0] = adjust_address (operands[0], mode, 0);
8040 else if (GET_CODE (operands[0]) == SUBREG
8041 && (submode = GET_MODE (SUBREG_REG (operands[0])),
8042 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8043 && pos + len <= GET_MODE_BITSIZE (submode))
8045 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8047 operands[0] = SUBREG_REG (operands[0]);
8049 else if (mode == HImode && pos + len <= 8)
8051 /* Small HImode tests can be converted to QImode. */
8053 operands[0] = gen_lowpart (QImode, operands[0]);
8056 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8057 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8059 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
8062 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8063 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8064 ;; this is relatively important trick.
8065 ;; Do the conversion only post-reload to avoid limiting of the register class
8070 (and (match_operand 0 "register_operand" "")
8071 (match_operand 1 "const_int_operand" ""))
8074 && QI_REG_P (operands[0])
8075 && ((ix86_match_ccmode (insn, CCZmode)
8076 && !(INTVAL (operands[1]) & ~(255 << 8)))
8077 || (ix86_match_ccmode (insn, CCNOmode)
8078 && !(INTVAL (operands[1]) & ~(127 << 8))))
8079 && GET_MODE (operands[0]) != QImode"
8082 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8085 "operands[0] = gen_lowpart (SImode, operands[0]);
8086 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
8091 (and (match_operand 0 "nonimmediate_operand" "")
8092 (match_operand 1 "const_int_operand" ""))
8095 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
8096 && ((ix86_match_ccmode (insn, CCZmode)
8097 && !(INTVAL (operands[1]) & ~255))
8098 || (ix86_match_ccmode (insn, CCNOmode)
8099 && !(INTVAL (operands[1]) & ~127)))
8100 && GET_MODE (operands[0]) != QImode"
8103 (and:QI (match_dup 0)
8106 "operands[0] = gen_lowpart (QImode, operands[0]);
8107 operands[1] = gen_lowpart (QImode, operands[1]);")
8110 ;; %%% This used to optimize known byte-wide and operations to memory,
8111 ;; and sometimes to QImode registers. If this is considered useful,
8112 ;; it should be done with splitters.
8114 (define_expand "anddi3"
8115 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8116 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8117 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8118 (clobber (reg:CC 17))]
8120 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8122 (define_insn "*anddi_1_rex64"
8123 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8124 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8125 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8126 (clobber (reg:CC 17))]
8127 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8129 switch (get_attr_type (insn))
8133 enum machine_mode mode;
8135 if (GET_CODE (operands[2]) != CONST_INT)
8137 if (INTVAL (operands[2]) == 0xff)
8139 else if (INTVAL (operands[2]) == 0xffff)
8144 operands[1] = gen_lowpart (mode, operands[1]);
8146 return "movz{bq|x}\t{%1,%0|%0, %1}";
8148 return "movz{wq|x}\t{%1,%0|%0, %1}";
8152 if (! rtx_equal_p (operands[0], operands[1]))
8154 if (get_attr_mode (insn) == MODE_SI)
8155 return "and{l}\t{%k2, %k0|%k0, %k2}";
8157 return "and{q}\t{%2, %0|%0, %2}";
8160 [(set_attr "type" "alu,alu,alu,imovx")
8161 (set_attr "length_immediate" "*,*,*,0")
8162 (set_attr "mode" "SI,DI,DI,DI")])
8164 (define_insn "*anddi_2"
8166 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8167 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8169 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8170 (and:DI (match_dup 1) (match_dup 2)))]
8171 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8172 && ix86_binary_operator_ok (AND, DImode, operands)"
8174 and{l}\t{%k2, %k0|%k0, %k2}
8175 and{q}\t{%2, %0|%0, %2}
8176 and{q}\t{%2, %0|%0, %2}"
8177 [(set_attr "type" "alu")
8178 (set_attr "mode" "SI,DI,DI")])
8180 (define_expand "andsi3"
8181 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8182 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8183 (match_operand:SI 2 "general_operand" "")))
8184 (clobber (reg:CC 17))]
8186 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8188 (define_insn "*andsi_1"
8189 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8190 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8191 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8192 (clobber (reg:CC 17))]
8193 "ix86_binary_operator_ok (AND, SImode, operands)"
8195 switch (get_attr_type (insn))
8199 enum machine_mode mode;
8201 if (GET_CODE (operands[2]) != CONST_INT)
8203 if (INTVAL (operands[2]) == 0xff)
8205 else if (INTVAL (operands[2]) == 0xffff)
8210 operands[1] = gen_lowpart (mode, operands[1]);
8212 return "movz{bl|x}\t{%1,%0|%0, %1}";
8214 return "movz{wl|x}\t{%1,%0|%0, %1}";
8218 if (! rtx_equal_p (operands[0], operands[1]))
8220 return "and{l}\t{%2, %0|%0, %2}";
8223 [(set_attr "type" "alu,alu,imovx")
8224 (set_attr "length_immediate" "*,*,0")
8225 (set_attr "mode" "SI")])
8228 [(set (match_operand 0 "register_operand" "")
8230 (const_int -65536)))
8231 (clobber (reg:CC 17))]
8232 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8233 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8234 "operands[1] = gen_lowpart (HImode, operands[0]);")
8237 [(set (match_operand 0 "ext_register_operand" "")
8240 (clobber (reg:CC 17))]
8241 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8242 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8243 "operands[1] = gen_lowpart (QImode, operands[0]);")
8246 [(set (match_operand 0 "ext_register_operand" "")
8248 (const_int -65281)))
8249 (clobber (reg:CC 17))]
8250 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8251 [(parallel [(set (zero_extract:SI (match_dup 0)
8255 (zero_extract:SI (match_dup 0)
8258 (zero_extract:SI (match_dup 0)
8261 (clobber (reg:CC 17))])]
8262 "operands[0] = gen_lowpart (SImode, operands[0]);")
8264 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8265 (define_insn "*andsi_1_zext"
8266 [(set (match_operand:DI 0 "register_operand" "=r")
8268 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8269 (match_operand:SI 2 "general_operand" "rim"))))
8270 (clobber (reg:CC 17))]
8271 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8272 "and{l}\t{%2, %k0|%k0, %2}"
8273 [(set_attr "type" "alu")
8274 (set_attr "mode" "SI")])
8276 (define_insn "*andsi_2"
8278 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8279 (match_operand:SI 2 "general_operand" "rim,ri"))
8281 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8282 (and:SI (match_dup 1) (match_dup 2)))]
8283 "ix86_match_ccmode (insn, CCNOmode)
8284 && ix86_binary_operator_ok (AND, SImode, operands)"
8285 "and{l}\t{%2, %0|%0, %2}"
8286 [(set_attr "type" "alu")
8287 (set_attr "mode" "SI")])
8289 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8290 (define_insn "*andsi_2_zext"
8292 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8293 (match_operand:SI 2 "general_operand" "rim"))
8295 (set (match_operand:DI 0 "register_operand" "=r")
8296 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8297 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8298 && ix86_binary_operator_ok (AND, SImode, operands)"
8299 "and{l}\t{%2, %k0|%k0, %2}"
8300 [(set_attr "type" "alu")
8301 (set_attr "mode" "SI")])
8303 (define_expand "andhi3"
8304 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8305 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8306 (match_operand:HI 2 "general_operand" "")))
8307 (clobber (reg:CC 17))]
8308 "TARGET_HIMODE_MATH"
8309 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8311 (define_insn "*andhi_1"
8312 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8313 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8314 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8315 (clobber (reg:CC 17))]
8316 "ix86_binary_operator_ok (AND, HImode, operands)"
8318 switch (get_attr_type (insn))
8321 if (GET_CODE (operands[2]) != CONST_INT)
8323 if (INTVAL (operands[2]) == 0xff)
8324 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8328 if (! rtx_equal_p (operands[0], operands[1]))
8331 return "and{w}\t{%2, %0|%0, %2}";
8334 [(set_attr "type" "alu,alu,imovx")
8335 (set_attr "length_immediate" "*,*,0")
8336 (set_attr "mode" "HI,HI,SI")])
8338 (define_insn "*andhi_2"
8340 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8341 (match_operand:HI 2 "general_operand" "rim,ri"))
8343 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8344 (and:HI (match_dup 1) (match_dup 2)))]
8345 "ix86_match_ccmode (insn, CCNOmode)
8346 && ix86_binary_operator_ok (AND, HImode, operands)"
8347 "and{w}\t{%2, %0|%0, %2}"
8348 [(set_attr "type" "alu")
8349 (set_attr "mode" "HI")])
8351 (define_expand "andqi3"
8352 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8353 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8354 (match_operand:QI 2 "general_operand" "")))
8355 (clobber (reg:CC 17))]
8356 "TARGET_QIMODE_MATH"
8357 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8359 ;; %%% Potential partial reg stall on alternative 2. What to do?
8360 (define_insn "*andqi_1"
8361 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8362 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8363 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8364 (clobber (reg:CC 17))]
8365 "ix86_binary_operator_ok (AND, QImode, operands)"
8367 and{b}\t{%2, %0|%0, %2}
8368 and{b}\t{%2, %0|%0, %2}
8369 and{l}\t{%k2, %k0|%k0, %k2}"
8370 [(set_attr "type" "alu")
8371 (set_attr "mode" "QI,QI,SI")])
8373 (define_insn "*andqi_1_slp"
8374 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8375 (and:QI (match_dup 0)
8376 (match_operand:QI 1 "general_operand" "qi,qmi")))
8377 (clobber (reg:CC 17))]
8378 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8379 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8380 "and{b}\t{%1, %0|%0, %1}"
8381 [(set_attr "type" "alu1")
8382 (set_attr "mode" "QI")])
8384 (define_insn "*andqi_2"
8387 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8388 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8390 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8391 (and:QI (match_dup 1) (match_dup 2)))]
8392 "ix86_match_ccmode (insn, CCNOmode)
8393 && ix86_binary_operator_ok (AND, QImode, operands)"
8395 if (which_alternative == 2)
8397 if (GET_CODE (operands[2]) == CONST_INT
8398 && (INTVAL (operands[2]) & 0xffffff00))
8399 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8400 return "and{l}\t{%2, %k0|%k0, %2}";
8402 return "and{b}\t{%2, %0|%0, %2}";
8404 [(set_attr "type" "alu")
8405 (set_attr "mode" "QI,QI,SI")])
8407 (define_insn "*andqi_2_slp"
8410 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8411 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8413 (set (strict_low_part (match_dup 0))
8414 (and:QI (match_dup 0) (match_dup 1)))]
8415 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8416 && ix86_match_ccmode (insn, CCNOmode)
8417 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8418 "and{b}\t{%1, %0|%0, %1}"
8419 [(set_attr "type" "alu1")
8420 (set_attr "mode" "QI")])
8422 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8423 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8424 ;; for a QImode operand, which of course failed.
8426 (define_insn "andqi_ext_0"
8427 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8432 (match_operand 1 "ext_register_operand" "0")
8435 (match_operand 2 "const_int_operand" "n")))
8436 (clobber (reg:CC 17))]
8438 "and{b}\t{%2, %h0|%h0, %2}"
8439 [(set_attr "type" "alu")
8440 (set_attr "length_immediate" "1")
8441 (set_attr "mode" "QI")])
8443 ;; Generated by peephole translating test to and. This shows up
8444 ;; often in fp comparisons.
8446 (define_insn "*andqi_ext_0_cc"
8451 (match_operand 1 "ext_register_operand" "0")
8454 (match_operand 2 "const_int_operand" "n"))
8456 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8465 "ix86_match_ccmode (insn, CCNOmode)"
8466 "and{b}\t{%2, %h0|%h0, %2}"
8467 [(set_attr "type" "alu")
8468 (set_attr "length_immediate" "1")
8469 (set_attr "mode" "QI")])
8471 (define_insn "*andqi_ext_1"
8472 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8477 (match_operand 1 "ext_register_operand" "0")
8481 (match_operand:QI 2 "general_operand" "Qm"))))
8482 (clobber (reg:CC 17))]
8484 "and{b}\t{%2, %h0|%h0, %2}"
8485 [(set_attr "type" "alu")
8486 (set_attr "length_immediate" "0")
8487 (set_attr "mode" "QI")])
8489 (define_insn "*andqi_ext_1_rex64"
8490 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8495 (match_operand 1 "ext_register_operand" "0")
8499 (match_operand 2 "ext_register_operand" "Q"))))
8500 (clobber (reg:CC 17))]
8502 "and{b}\t{%2, %h0|%h0, %2}"
8503 [(set_attr "type" "alu")
8504 (set_attr "length_immediate" "0")
8505 (set_attr "mode" "QI")])
8507 (define_insn "*andqi_ext_2"
8508 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8513 (match_operand 1 "ext_register_operand" "%0")
8517 (match_operand 2 "ext_register_operand" "Q")
8520 (clobber (reg:CC 17))]
8522 "and{b}\t{%h2, %h0|%h0, %h2}"
8523 [(set_attr "type" "alu")
8524 (set_attr "length_immediate" "0")
8525 (set_attr "mode" "QI")])
8527 ;; Convert wide AND instructions with immediate operand to shorter QImode
8528 ;; equivalents when possible.
8529 ;; Don't do the splitting with memory operands, since it introduces risk
8530 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8531 ;; for size, but that can (should?) be handled by generic code instead.
8533 [(set (match_operand 0 "register_operand" "")
8534 (and (match_operand 1 "register_operand" "")
8535 (match_operand 2 "const_int_operand" "")))
8536 (clobber (reg:CC 17))]
8538 && QI_REG_P (operands[0])
8539 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8540 && !(~INTVAL (operands[2]) & ~(255 << 8))
8541 && GET_MODE (operands[0]) != QImode"
8542 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8543 (and:SI (zero_extract:SI (match_dup 1)
8544 (const_int 8) (const_int 8))
8546 (clobber (reg:CC 17))])]
8547 "operands[0] = gen_lowpart (SImode, operands[0]);
8548 operands[1] = gen_lowpart (SImode, operands[1]);
8549 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8551 ;; Since AND can be encoded with sign extended immediate, this is only
8552 ;; profitable when 7th bit is not set.
8554 [(set (match_operand 0 "register_operand" "")
8555 (and (match_operand 1 "general_operand" "")
8556 (match_operand 2 "const_int_operand" "")))
8557 (clobber (reg:CC 17))]
8559 && ANY_QI_REG_P (operands[0])
8560 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8561 && !(~INTVAL (operands[2]) & ~255)
8562 && !(INTVAL (operands[2]) & 128)
8563 && GET_MODE (operands[0]) != QImode"
8564 [(parallel [(set (strict_low_part (match_dup 0))
8565 (and:QI (match_dup 1)
8567 (clobber (reg:CC 17))])]
8568 "operands[0] = gen_lowpart (QImode, operands[0]);
8569 operands[1] = gen_lowpart (QImode, operands[1]);
8570 operands[2] = gen_lowpart (QImode, operands[2]);")
8572 ;; Logical inclusive OR instructions
8574 ;; %%% This used to optimize known byte-wide and operations to memory.
8575 ;; If this is considered useful, it should be done with splitters.
8577 (define_expand "iordi3"
8578 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8579 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8580 (match_operand:DI 2 "x86_64_general_operand" "")))
8581 (clobber (reg:CC 17))]
8583 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8585 (define_insn "*iordi_1_rex64"
8586 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8587 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8588 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8589 (clobber (reg:CC 17))]
8591 && ix86_binary_operator_ok (IOR, DImode, operands)"
8592 "or{q}\t{%2, %0|%0, %2}"
8593 [(set_attr "type" "alu")
8594 (set_attr "mode" "DI")])
8596 (define_insn "*iordi_2_rex64"
8598 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8599 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8601 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8602 (ior:DI (match_dup 1) (match_dup 2)))]
8604 && ix86_match_ccmode (insn, CCNOmode)
8605 && ix86_binary_operator_ok (IOR, DImode, operands)"
8606 "or{q}\t{%2, %0|%0, %2}"
8607 [(set_attr "type" "alu")
8608 (set_attr "mode" "DI")])
8610 (define_insn "*iordi_3_rex64"
8612 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8613 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8615 (clobber (match_scratch:DI 0 "=r"))]
8617 && ix86_match_ccmode (insn, CCNOmode)
8618 && ix86_binary_operator_ok (IOR, DImode, operands)"
8619 "or{q}\t{%2, %0|%0, %2}"
8620 [(set_attr "type" "alu")
8621 (set_attr "mode" "DI")])
8624 (define_expand "iorsi3"
8625 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8626 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8627 (match_operand:SI 2 "general_operand" "")))
8628 (clobber (reg:CC 17))]
8630 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8632 (define_insn "*iorsi_1"
8633 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8634 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8635 (match_operand:SI 2 "general_operand" "ri,rmi")))
8636 (clobber (reg:CC 17))]
8637 "ix86_binary_operator_ok (IOR, SImode, operands)"
8638 "or{l}\t{%2, %0|%0, %2}"
8639 [(set_attr "type" "alu")
8640 (set_attr "mode" "SI")])
8642 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8643 (define_insn "*iorsi_1_zext"
8644 [(set (match_operand:DI 0 "register_operand" "=rm")
8646 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8647 (match_operand:SI 2 "general_operand" "rim"))))
8648 (clobber (reg:CC 17))]
8649 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8650 "or{l}\t{%2, %k0|%k0, %2}"
8651 [(set_attr "type" "alu")
8652 (set_attr "mode" "SI")])
8654 (define_insn "*iorsi_1_zext_imm"
8655 [(set (match_operand:DI 0 "register_operand" "=rm")
8656 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8657 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8658 (clobber (reg:CC 17))]
8660 "or{l}\t{%2, %k0|%k0, %2}"
8661 [(set_attr "type" "alu")
8662 (set_attr "mode" "SI")])
8664 (define_insn "*iorsi_2"
8666 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8667 (match_operand:SI 2 "general_operand" "rim,ri"))
8669 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8670 (ior:SI (match_dup 1) (match_dup 2)))]
8671 "ix86_match_ccmode (insn, CCNOmode)
8672 && ix86_binary_operator_ok (IOR, SImode, operands)"
8673 "or{l}\t{%2, %0|%0, %2}"
8674 [(set_attr "type" "alu")
8675 (set_attr "mode" "SI")])
8677 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8678 ;; ??? Special case for immediate operand is missing - it is tricky.
8679 (define_insn "*iorsi_2_zext"
8681 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8682 (match_operand:SI 2 "general_operand" "rim"))
8684 (set (match_operand:DI 0 "register_operand" "=r")
8685 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8686 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8687 && ix86_binary_operator_ok (IOR, SImode, operands)"
8688 "or{l}\t{%2, %k0|%k0, %2}"
8689 [(set_attr "type" "alu")
8690 (set_attr "mode" "SI")])
8692 (define_insn "*iorsi_2_zext_imm"
8694 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8695 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8697 (set (match_operand:DI 0 "register_operand" "=r")
8698 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8699 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8700 && ix86_binary_operator_ok (IOR, SImode, operands)"
8701 "or{l}\t{%2, %k0|%k0, %2}"
8702 [(set_attr "type" "alu")
8703 (set_attr "mode" "SI")])
8705 (define_insn "*iorsi_3"
8707 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8708 (match_operand:SI 2 "general_operand" "rim"))
8710 (clobber (match_scratch:SI 0 "=r"))]
8711 "ix86_match_ccmode (insn, CCNOmode)
8712 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8713 "or{l}\t{%2, %0|%0, %2}"
8714 [(set_attr "type" "alu")
8715 (set_attr "mode" "SI")])
8717 (define_expand "iorhi3"
8718 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8719 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8720 (match_operand:HI 2 "general_operand" "")))
8721 (clobber (reg:CC 17))]
8722 "TARGET_HIMODE_MATH"
8723 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8725 (define_insn "*iorhi_1"
8726 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8727 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8728 (match_operand:HI 2 "general_operand" "rmi,ri")))
8729 (clobber (reg:CC 17))]
8730 "ix86_binary_operator_ok (IOR, HImode, operands)"
8731 "or{w}\t{%2, %0|%0, %2}"
8732 [(set_attr "type" "alu")
8733 (set_attr "mode" "HI")])
8735 (define_insn "*iorhi_2"
8737 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8738 (match_operand:HI 2 "general_operand" "rim,ri"))
8740 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8741 (ior:HI (match_dup 1) (match_dup 2)))]
8742 "ix86_match_ccmode (insn, CCNOmode)
8743 && ix86_binary_operator_ok (IOR, HImode, operands)"
8744 "or{w}\t{%2, %0|%0, %2}"
8745 [(set_attr "type" "alu")
8746 (set_attr "mode" "HI")])
8748 (define_insn "*iorhi_3"
8750 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8751 (match_operand:HI 2 "general_operand" "rim"))
8753 (clobber (match_scratch:HI 0 "=r"))]
8754 "ix86_match_ccmode (insn, CCNOmode)
8755 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8756 "or{w}\t{%2, %0|%0, %2}"
8757 [(set_attr "type" "alu")
8758 (set_attr "mode" "HI")])
8760 (define_expand "iorqi3"
8761 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8762 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8763 (match_operand:QI 2 "general_operand" "")))
8764 (clobber (reg:CC 17))]
8765 "TARGET_QIMODE_MATH"
8766 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8768 ;; %%% Potential partial reg stall on alternative 2. What to do?
8769 (define_insn "*iorqi_1"
8770 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8771 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8772 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8773 (clobber (reg:CC 17))]
8774 "ix86_binary_operator_ok (IOR, QImode, operands)"
8776 or{b}\t{%2, %0|%0, %2}
8777 or{b}\t{%2, %0|%0, %2}
8778 or{l}\t{%k2, %k0|%k0, %k2}"
8779 [(set_attr "type" "alu")
8780 (set_attr "mode" "QI,QI,SI")])
8782 (define_insn "*iorqi_1_slp"
8783 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8784 (ior:QI (match_dup 0)
8785 (match_operand:QI 1 "general_operand" "qmi,qi")))
8786 (clobber (reg:CC 17))]
8787 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8788 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8789 "or{b}\t{%1, %0|%0, %1}"
8790 [(set_attr "type" "alu1")
8791 (set_attr "mode" "QI")])
8793 (define_insn "*iorqi_2"
8795 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8796 (match_operand:QI 2 "general_operand" "qim,qi"))
8798 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8799 (ior:QI (match_dup 1) (match_dup 2)))]
8800 "ix86_match_ccmode (insn, CCNOmode)
8801 && ix86_binary_operator_ok (IOR, QImode, operands)"
8802 "or{b}\t{%2, %0|%0, %2}"
8803 [(set_attr "type" "alu")
8804 (set_attr "mode" "QI")])
8806 (define_insn "*iorqi_2_slp"
8808 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8809 (match_operand:QI 1 "general_operand" "qim,qi"))
8811 (set (strict_low_part (match_dup 0))
8812 (ior:QI (match_dup 0) (match_dup 1)))]
8813 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8814 && ix86_match_ccmode (insn, CCNOmode)
8815 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8816 "or{b}\t{%1, %0|%0, %1}"
8817 [(set_attr "type" "alu1")
8818 (set_attr "mode" "QI")])
8820 (define_insn "*iorqi_3"
8822 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8823 (match_operand:QI 2 "general_operand" "qim"))
8825 (clobber (match_scratch:QI 0 "=q"))]
8826 "ix86_match_ccmode (insn, CCNOmode)
8827 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8828 "or{b}\t{%2, %0|%0, %2}"
8829 [(set_attr "type" "alu")
8830 (set_attr "mode" "QI")])
8832 (define_insn "iorqi_ext_0"
8833 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8838 (match_operand 1 "ext_register_operand" "0")
8841 (match_operand 2 "const_int_operand" "n")))
8842 (clobber (reg:CC 17))]
8843 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8844 "or{b}\t{%2, %h0|%h0, %2}"
8845 [(set_attr "type" "alu")
8846 (set_attr "length_immediate" "1")
8847 (set_attr "mode" "QI")])
8849 (define_insn "*iorqi_ext_1"
8850 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8855 (match_operand 1 "ext_register_operand" "0")
8859 (match_operand:QI 2 "general_operand" "Qm"))))
8860 (clobber (reg:CC 17))]
8862 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8863 "or{b}\t{%2, %h0|%h0, %2}"
8864 [(set_attr "type" "alu")
8865 (set_attr "length_immediate" "0")
8866 (set_attr "mode" "QI")])
8868 (define_insn "*iorqi_ext_1_rex64"
8869 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8874 (match_operand 1 "ext_register_operand" "0")
8878 (match_operand 2 "ext_register_operand" "Q"))))
8879 (clobber (reg:CC 17))]
8881 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8882 "or{b}\t{%2, %h0|%h0, %2}"
8883 [(set_attr "type" "alu")
8884 (set_attr "length_immediate" "0")
8885 (set_attr "mode" "QI")])
8887 (define_insn "*iorqi_ext_2"
8888 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8892 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8895 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8898 (clobber (reg:CC 17))]
8899 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8900 "ior{b}\t{%h2, %h0|%h0, %h2}"
8901 [(set_attr "type" "alu")
8902 (set_attr "length_immediate" "0")
8903 (set_attr "mode" "QI")])
8906 [(set (match_operand 0 "register_operand" "")
8907 (ior (match_operand 1 "register_operand" "")
8908 (match_operand 2 "const_int_operand" "")))
8909 (clobber (reg:CC 17))]
8911 && QI_REG_P (operands[0])
8912 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8913 && !(INTVAL (operands[2]) & ~(255 << 8))
8914 && GET_MODE (operands[0]) != QImode"
8915 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8916 (ior:SI (zero_extract:SI (match_dup 1)
8917 (const_int 8) (const_int 8))
8919 (clobber (reg:CC 17))])]
8920 "operands[0] = gen_lowpart (SImode, operands[0]);
8921 operands[1] = gen_lowpart (SImode, operands[1]);
8922 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8924 ;; Since OR can be encoded with sign extended immediate, this is only
8925 ;; profitable when 7th bit is set.
8927 [(set (match_operand 0 "register_operand" "")
8928 (ior (match_operand 1 "general_operand" "")
8929 (match_operand 2 "const_int_operand" "")))
8930 (clobber (reg:CC 17))]
8932 && ANY_QI_REG_P (operands[0])
8933 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8934 && !(INTVAL (operands[2]) & ~255)
8935 && (INTVAL (operands[2]) & 128)
8936 && GET_MODE (operands[0]) != QImode"
8937 [(parallel [(set (strict_low_part (match_dup 0))
8938 (ior:QI (match_dup 1)
8940 (clobber (reg:CC 17))])]
8941 "operands[0] = gen_lowpart (QImode, operands[0]);
8942 operands[1] = gen_lowpart (QImode, operands[1]);
8943 operands[2] = gen_lowpart (QImode, operands[2]);")
8945 ;; Logical XOR instructions
8947 ;; %%% This used to optimize known byte-wide and operations to memory.
8948 ;; If this is considered useful, it should be done with splitters.
8950 (define_expand "xordi3"
8951 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8952 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8953 (match_operand:DI 2 "x86_64_general_operand" "")))
8954 (clobber (reg:CC 17))]
8956 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8958 (define_insn "*xordi_1_rex64"
8959 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8960 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8961 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8962 (clobber (reg:CC 17))]
8964 && ix86_binary_operator_ok (XOR, DImode, operands)"
8966 xor{q}\t{%2, %0|%0, %2}
8967 xor{q}\t{%2, %0|%0, %2}"
8968 [(set_attr "type" "alu")
8969 (set_attr "mode" "DI,DI")])
8971 (define_insn "*xordi_2_rex64"
8973 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8974 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8976 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8977 (xor:DI (match_dup 1) (match_dup 2)))]
8979 && ix86_match_ccmode (insn, CCNOmode)
8980 && ix86_binary_operator_ok (XOR, DImode, operands)"
8982 xor{q}\t{%2, %0|%0, %2}
8983 xor{q}\t{%2, %0|%0, %2}"
8984 [(set_attr "type" "alu")
8985 (set_attr "mode" "DI,DI")])
8987 (define_insn "*xordi_3_rex64"
8989 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8990 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8992 (clobber (match_scratch:DI 0 "=r"))]
8994 && ix86_match_ccmode (insn, CCNOmode)
8995 && ix86_binary_operator_ok (XOR, DImode, operands)"
8996 "xor{q}\t{%2, %0|%0, %2}"
8997 [(set_attr "type" "alu")
8998 (set_attr "mode" "DI")])
9000 (define_expand "xorsi3"
9001 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9002 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
9003 (match_operand:SI 2 "general_operand" "")))
9004 (clobber (reg:CC 17))]
9006 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9008 (define_insn "*xorsi_1"
9009 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9010 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9011 (match_operand:SI 2 "general_operand" "ri,rm")))
9012 (clobber (reg:CC 17))]
9013 "ix86_binary_operator_ok (XOR, SImode, operands)"
9014 "xor{l}\t{%2, %0|%0, %2}"
9015 [(set_attr "type" "alu")
9016 (set_attr "mode" "SI")])
9018 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9019 ;; Add speccase for immediates
9020 (define_insn "*xorsi_1_zext"
9021 [(set (match_operand:DI 0 "register_operand" "=r")
9023 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9024 (match_operand:SI 2 "general_operand" "rim"))))
9025 (clobber (reg:CC 17))]
9026 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9027 "xor{l}\t{%2, %k0|%k0, %2}"
9028 [(set_attr "type" "alu")
9029 (set_attr "mode" "SI")])
9031 (define_insn "*xorsi_1_zext_imm"
9032 [(set (match_operand:DI 0 "register_operand" "=r")
9033 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9034 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9035 (clobber (reg:CC 17))]
9036 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9037 "xor{l}\t{%2, %k0|%k0, %2}"
9038 [(set_attr "type" "alu")
9039 (set_attr "mode" "SI")])
9041 (define_insn "*xorsi_2"
9043 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9044 (match_operand:SI 2 "general_operand" "rim,ri"))
9046 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9047 (xor:SI (match_dup 1) (match_dup 2)))]
9048 "ix86_match_ccmode (insn, CCNOmode)
9049 && ix86_binary_operator_ok (XOR, SImode, operands)"
9050 "xor{l}\t{%2, %0|%0, %2}"
9051 [(set_attr "type" "alu")
9052 (set_attr "mode" "SI")])
9054 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9055 ;; ??? Special case for immediate operand is missing - it is tricky.
9056 (define_insn "*xorsi_2_zext"
9058 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9059 (match_operand:SI 2 "general_operand" "rim"))
9061 (set (match_operand:DI 0 "register_operand" "=r")
9062 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9063 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9064 && ix86_binary_operator_ok (XOR, SImode, operands)"
9065 "xor{l}\t{%2, %k0|%k0, %2}"
9066 [(set_attr "type" "alu")
9067 (set_attr "mode" "SI")])
9069 (define_insn "*xorsi_2_zext_imm"
9071 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9072 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9074 (set (match_operand:DI 0 "register_operand" "=r")
9075 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9076 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9077 && ix86_binary_operator_ok (XOR, SImode, operands)"
9078 "xor{l}\t{%2, %k0|%k0, %2}"
9079 [(set_attr "type" "alu")
9080 (set_attr "mode" "SI")])
9082 (define_insn "*xorsi_3"
9084 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9085 (match_operand:SI 2 "general_operand" "rim"))
9087 (clobber (match_scratch:SI 0 "=r"))]
9088 "ix86_match_ccmode (insn, CCNOmode)
9089 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9090 "xor{l}\t{%2, %0|%0, %2}"
9091 [(set_attr "type" "alu")
9092 (set_attr "mode" "SI")])
9094 (define_expand "xorhi3"
9095 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9096 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9097 (match_operand:HI 2 "general_operand" "")))
9098 (clobber (reg:CC 17))]
9099 "TARGET_HIMODE_MATH"
9100 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9102 (define_insn "*xorhi_1"
9103 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9104 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9105 (match_operand:HI 2 "general_operand" "rmi,ri")))
9106 (clobber (reg:CC 17))]
9107 "ix86_binary_operator_ok (XOR, HImode, operands)"
9108 "xor{w}\t{%2, %0|%0, %2}"
9109 [(set_attr "type" "alu")
9110 (set_attr "mode" "HI")])
9112 (define_insn "*xorhi_2"
9114 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9115 (match_operand:HI 2 "general_operand" "rim,ri"))
9117 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9118 (xor:HI (match_dup 1) (match_dup 2)))]
9119 "ix86_match_ccmode (insn, CCNOmode)
9120 && ix86_binary_operator_ok (XOR, HImode, operands)"
9121 "xor{w}\t{%2, %0|%0, %2}"
9122 [(set_attr "type" "alu")
9123 (set_attr "mode" "HI")])
9125 (define_insn "*xorhi_3"
9127 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9128 (match_operand:HI 2 "general_operand" "rim"))
9130 (clobber (match_scratch:HI 0 "=r"))]
9131 "ix86_match_ccmode (insn, CCNOmode)
9132 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9133 "xor{w}\t{%2, %0|%0, %2}"
9134 [(set_attr "type" "alu")
9135 (set_attr "mode" "HI")])
9137 (define_expand "xorqi3"
9138 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9139 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9140 (match_operand:QI 2 "general_operand" "")))
9141 (clobber (reg:CC 17))]
9142 "TARGET_QIMODE_MATH"
9143 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9145 ;; %%% Potential partial reg stall on alternative 2. What to do?
9146 (define_insn "*xorqi_1"
9147 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9148 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9149 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9150 (clobber (reg:CC 17))]
9151 "ix86_binary_operator_ok (XOR, QImode, operands)"
9153 xor{b}\t{%2, %0|%0, %2}
9154 xor{b}\t{%2, %0|%0, %2}
9155 xor{l}\t{%k2, %k0|%k0, %k2}"
9156 [(set_attr "type" "alu")
9157 (set_attr "mode" "QI,QI,SI")])
9159 (define_insn "*xorqi_1_slp"
9160 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9161 (xor:QI (match_dup 0)
9162 (match_operand:QI 1 "general_operand" "qi,qmi")))
9163 (clobber (reg:CC 17))]
9164 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9165 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9166 "xor{b}\t{%1, %0|%0, %1}"
9167 [(set_attr "type" "alu1")
9168 (set_attr "mode" "QI")])
9170 (define_insn "xorqi_ext_0"
9171 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9176 (match_operand 1 "ext_register_operand" "0")
9179 (match_operand 2 "const_int_operand" "n")))
9180 (clobber (reg:CC 17))]
9181 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9182 "xor{b}\t{%2, %h0|%h0, %2}"
9183 [(set_attr "type" "alu")
9184 (set_attr "length_immediate" "1")
9185 (set_attr "mode" "QI")])
9187 (define_insn "*xorqi_ext_1"
9188 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9193 (match_operand 1 "ext_register_operand" "0")
9197 (match_operand:QI 2 "general_operand" "Qm"))))
9198 (clobber (reg:CC 17))]
9200 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9201 "xor{b}\t{%2, %h0|%h0, %2}"
9202 [(set_attr "type" "alu")
9203 (set_attr "length_immediate" "0")
9204 (set_attr "mode" "QI")])
9206 (define_insn "*xorqi_ext_1_rex64"
9207 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9212 (match_operand 1 "ext_register_operand" "0")
9216 (match_operand 2 "ext_register_operand" "Q"))))
9217 (clobber (reg:CC 17))]
9219 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9220 "xor{b}\t{%2, %h0|%h0, %2}"
9221 [(set_attr "type" "alu")
9222 (set_attr "length_immediate" "0")
9223 (set_attr "mode" "QI")])
9225 (define_insn "*xorqi_ext_2"
9226 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9230 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9233 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9236 (clobber (reg:CC 17))]
9237 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9238 "xor{b}\t{%h2, %h0|%h0, %h2}"
9239 [(set_attr "type" "alu")
9240 (set_attr "length_immediate" "0")
9241 (set_attr "mode" "QI")])
9243 (define_insn "*xorqi_cc_1"
9246 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9247 (match_operand:QI 2 "general_operand" "qim,qi"))
9249 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9250 (xor:QI (match_dup 1) (match_dup 2)))]
9251 "ix86_match_ccmode (insn, CCNOmode)
9252 && ix86_binary_operator_ok (XOR, QImode, operands)"
9253 "xor{b}\t{%2, %0|%0, %2}"
9254 [(set_attr "type" "alu")
9255 (set_attr "mode" "QI")])
9257 (define_insn "*xorqi_2_slp"
9259 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9260 (match_operand:QI 1 "general_operand" "qim,qi"))
9262 (set (strict_low_part (match_dup 0))
9263 (xor:QI (match_dup 0) (match_dup 1)))]
9264 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9265 && ix86_match_ccmode (insn, CCNOmode)
9266 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9267 "xor{b}\t{%1, %0|%0, %1}"
9268 [(set_attr "type" "alu1")
9269 (set_attr "mode" "QI")])
9271 (define_insn "*xorqi_cc_2"
9274 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9275 (match_operand:QI 2 "general_operand" "qim"))
9277 (clobber (match_scratch:QI 0 "=q"))]
9278 "ix86_match_ccmode (insn, CCNOmode)
9279 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9280 "xor{b}\t{%2, %0|%0, %2}"
9281 [(set_attr "type" "alu")
9282 (set_attr "mode" "QI")])
9284 (define_insn "*xorqi_cc_ext_1"
9289 (match_operand 1 "ext_register_operand" "0")
9292 (match_operand:QI 2 "general_operand" "qmn"))
9294 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9298 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9300 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9301 "xor{b}\t{%2, %h0|%h0, %2}"
9302 [(set_attr "type" "alu")
9303 (set_attr "mode" "QI")])
9305 (define_insn "*xorqi_cc_ext_1_rex64"
9310 (match_operand 1 "ext_register_operand" "0")
9313 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9315 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9319 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9321 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9322 "xor{b}\t{%2, %h0|%h0, %2}"
9323 [(set_attr "type" "alu")
9324 (set_attr "mode" "QI")])
9326 (define_expand "xorqi_cc_ext_1"
9332 (match_operand 1 "ext_register_operand" "")
9335 (match_operand:QI 2 "general_operand" ""))
9337 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9341 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9347 [(set (match_operand 0 "register_operand" "")
9348 (xor (match_operand 1 "register_operand" "")
9349 (match_operand 2 "const_int_operand" "")))
9350 (clobber (reg:CC 17))]
9352 && QI_REG_P (operands[0])
9353 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9354 && !(INTVAL (operands[2]) & ~(255 << 8))
9355 && GET_MODE (operands[0]) != QImode"
9356 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9357 (xor:SI (zero_extract:SI (match_dup 1)
9358 (const_int 8) (const_int 8))
9360 (clobber (reg:CC 17))])]
9361 "operands[0] = gen_lowpart (SImode, operands[0]);
9362 operands[1] = gen_lowpart (SImode, operands[1]);
9363 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9365 ;; Since XOR can be encoded with sign extended immediate, this is only
9366 ;; profitable when 7th bit is set.
9368 [(set (match_operand 0 "register_operand" "")
9369 (xor (match_operand 1 "general_operand" "")
9370 (match_operand 2 "const_int_operand" "")))
9371 (clobber (reg:CC 17))]
9373 && ANY_QI_REG_P (operands[0])
9374 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9375 && !(INTVAL (operands[2]) & ~255)
9376 && (INTVAL (operands[2]) & 128)
9377 && GET_MODE (operands[0]) != QImode"
9378 [(parallel [(set (strict_low_part (match_dup 0))
9379 (xor:QI (match_dup 1)
9381 (clobber (reg:CC 17))])]
9382 "operands[0] = gen_lowpart (QImode, operands[0]);
9383 operands[1] = gen_lowpart (QImode, operands[1]);
9384 operands[2] = gen_lowpart (QImode, operands[2]);")
9386 ;; Negation instructions
9388 (define_expand "negdi2"
9389 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9390 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9391 (clobber (reg:CC 17))])]
9393 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9395 (define_insn "*negdi2_1"
9396 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9397 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9398 (clobber (reg:CC 17))]
9400 && ix86_unary_operator_ok (NEG, DImode, operands)"
9404 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9405 (neg:DI (match_operand:DI 1 "general_operand" "")))
9406 (clobber (reg:CC 17))]
9407 "!TARGET_64BIT && reload_completed"
9410 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9411 (set (match_dup 0) (neg:SI (match_dup 2)))])
9414 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9417 (clobber (reg:CC 17))])
9420 (neg:SI (match_dup 1)))
9421 (clobber (reg:CC 17))])]
9422 "split_di (operands+1, 1, operands+2, operands+3);
9423 split_di (operands+0, 1, operands+0, operands+1);")
9425 (define_insn "*negdi2_1_rex64"
9426 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9427 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9428 (clobber (reg:CC 17))]
9429 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9431 [(set_attr "type" "negnot")
9432 (set_attr "mode" "DI")])
9434 ;; The problem with neg is that it does not perform (compare x 0),
9435 ;; it really performs (compare 0 x), which leaves us with the zero
9436 ;; flag being the only useful item.
9438 (define_insn "*negdi2_cmpz_rex64"
9440 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9442 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9443 (neg:DI (match_dup 1)))]
9444 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9446 [(set_attr "type" "negnot")
9447 (set_attr "mode" "DI")])
9450 (define_expand "negsi2"
9451 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9452 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9453 (clobber (reg:CC 17))])]
9455 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9457 (define_insn "*negsi2_1"
9458 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9459 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9460 (clobber (reg:CC 17))]
9461 "ix86_unary_operator_ok (NEG, SImode, operands)"
9463 [(set_attr "type" "negnot")
9464 (set_attr "mode" "SI")])
9466 ;; Combine is quite creative about this pattern.
9467 (define_insn "*negsi2_1_zext"
9468 [(set (match_operand:DI 0 "register_operand" "=r")
9469 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9472 (clobber (reg:CC 17))]
9473 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9475 [(set_attr "type" "negnot")
9476 (set_attr "mode" "SI")])
9478 ;; The problem with neg is that it does not perform (compare x 0),
9479 ;; it really performs (compare 0 x), which leaves us with the zero
9480 ;; flag being the only useful item.
9482 (define_insn "*negsi2_cmpz"
9484 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9486 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9487 (neg:SI (match_dup 1)))]
9488 "ix86_unary_operator_ok (NEG, SImode, operands)"
9490 [(set_attr "type" "negnot")
9491 (set_attr "mode" "SI")])
9493 (define_insn "*negsi2_cmpz_zext"
9495 (compare:CCZ (lshiftrt:DI
9497 (match_operand:DI 1 "register_operand" "0")
9501 (set (match_operand:DI 0 "register_operand" "=r")
9502 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9505 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9507 [(set_attr "type" "negnot")
9508 (set_attr "mode" "SI")])
9510 (define_expand "neghi2"
9511 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9512 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9513 (clobber (reg:CC 17))])]
9514 "TARGET_HIMODE_MATH"
9515 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9517 (define_insn "*neghi2_1"
9518 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9519 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9520 (clobber (reg:CC 17))]
9521 "ix86_unary_operator_ok (NEG, HImode, operands)"
9523 [(set_attr "type" "negnot")
9524 (set_attr "mode" "HI")])
9526 (define_insn "*neghi2_cmpz"
9528 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9530 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9531 (neg:HI (match_dup 1)))]
9532 "ix86_unary_operator_ok (NEG, HImode, operands)"
9534 [(set_attr "type" "negnot")
9535 (set_attr "mode" "HI")])
9537 (define_expand "negqi2"
9538 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9539 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9540 (clobber (reg:CC 17))])]
9541 "TARGET_QIMODE_MATH"
9542 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9544 (define_insn "*negqi2_1"
9545 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9546 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9547 (clobber (reg:CC 17))]
9548 "ix86_unary_operator_ok (NEG, QImode, operands)"
9550 [(set_attr "type" "negnot")
9551 (set_attr "mode" "QI")])
9553 (define_insn "*negqi2_cmpz"
9555 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9557 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9558 (neg:QI (match_dup 1)))]
9559 "ix86_unary_operator_ok (NEG, QImode, operands)"
9561 [(set_attr "type" "negnot")
9562 (set_attr "mode" "QI")])
9564 ;; Changing of sign for FP values is doable using integer unit too.
9566 (define_expand "negsf2"
9567 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9568 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9569 (clobber (reg:CC 17))])]
9573 /* In case operand is in memory, we will not use SSE. */
9574 if (memory_operand (operands[0], VOIDmode)
9575 && rtx_equal_p (operands[0], operands[1]))
9576 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9579 /* Using SSE is tricky, since we need bitwise negation of -0
9581 rtx reg = gen_reg_rtx (SFmode);
9582 rtx dest = operands[0];
9583 rtx imm = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
9585 operands[1] = force_reg (SFmode, operands[1]);
9586 operands[0] = force_reg (SFmode, operands[0]);
9587 reg = force_reg (V4SFmode,
9588 gen_rtx_CONST_VECTOR (V4SFmode,
9589 gen_rtvec (4, imm, CONST0_RTX (SFmode),
9590 CONST0_RTX (SFmode),
9591 CONST0_RTX (SFmode))));
9592 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9593 if (dest != operands[0])
9594 emit_move_insn (dest, operands[0]);
9598 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9600 (define_insn "negsf2_memory"
9601 [(set (match_operand:SF 0 "memory_operand" "=m")
9602 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9603 (clobber (reg:CC 17))]
9604 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9607 (define_insn "negsf2_ifs"
9608 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9609 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9610 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
9611 (clobber (reg:CC 17))]
9613 && (reload_in_progress || reload_completed
9614 || (register_operand (operands[0], VOIDmode)
9615 && register_operand (operands[1], VOIDmode)))"
9619 [(set (match_operand:SF 0 "memory_operand" "")
9620 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9621 (use (match_operand:SF 2 "" ""))
9622 (clobber (reg:CC 17))]
9624 [(parallel [(set (match_dup 0)
9625 (neg:SF (match_dup 1)))
9626 (clobber (reg:CC 17))])])
9629 [(set (match_operand:SF 0 "register_operand" "")
9630 (neg:SF (match_operand:SF 1 "register_operand" "")))
9631 (use (match_operand:V4SF 2 "" ""))
9632 (clobber (reg:CC 17))]
9633 "reload_completed && !SSE_REG_P (operands[0])"
9634 [(parallel [(set (match_dup 0)
9635 (neg:SF (match_dup 1)))
9636 (clobber (reg:CC 17))])])
9639 [(set (match_operand:SF 0 "register_operand" "")
9640 (neg:SF (match_operand:SF 1 "register_operand" "")))
9641 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
9642 (clobber (reg:CC 17))]
9643 "reload_completed && SSE_REG_P (operands[0])"
9644 [(set (subreg:TI (match_dup 0) 0)
9645 (xor:TI (match_dup 1)
9648 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
9649 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
9650 if (operands_match_p (operands[0], operands[2]))
9654 operands[1] = operands[2];
9660 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9661 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9663 (define_insn "*negsf2_if"
9664 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9665 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9666 (clobber (reg:CC 17))]
9667 "TARGET_80387 && !TARGET_SSE
9668 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9672 [(set (match_operand:SF 0 "fp_register_operand" "")
9673 (neg:SF (match_operand:SF 1 "register_operand" "")))
9674 (clobber (reg:CC 17))]
9675 "TARGET_80387 && reload_completed"
9677 (neg:SF (match_dup 1)))]
9681 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9682 (neg:SF (match_operand:SF 1 "register_operand" "")))
9683 (clobber (reg:CC 17))]
9684 "TARGET_80387 && reload_completed"
9685 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9686 (clobber (reg:CC 17))])]
9687 "operands[1] = gen_int_mode (0x80000000, SImode);
9688 operands[0] = gen_lowpart (SImode, operands[0]);")
9691 [(set (match_operand 0 "memory_operand" "")
9692 (neg (match_operand 1 "memory_operand" "")))
9693 (clobber (reg:CC 17))]
9694 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9695 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9696 (clobber (reg:CC 17))])]
9698 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9700 if (GET_MODE (operands[1]) == XFmode)
9702 operands[0] = adjust_address (operands[0], QImode, size - 1);
9703 operands[1] = gen_int_mode (0x80, QImode);
9706 (define_expand "negdf2"
9707 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9708 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9709 (clobber (reg:CC 17))])]
9713 /* In case operand is in memory, we will not use SSE. */
9714 if (memory_operand (operands[0], VOIDmode)
9715 && rtx_equal_p (operands[0], operands[1]))
9716 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9719 /* Using SSE is tricky, since we need bitwise negation of -0
9722 #if HOST_BITS_PER_WIDE_INT >= 64
9723 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
9725 rtx imm = immed_double_const (0, 0x80000000, DImode);
9727 rtx dest = operands[0];
9729 operands[1] = force_reg (DFmode, operands[1]);
9730 operands[0] = force_reg (DFmode, operands[0]);
9731 imm = gen_lowpart (DFmode, imm);
9732 reg = force_reg (V2DFmode,
9733 gen_rtx_CONST_VECTOR (V2DFmode,
9734 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
9735 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
9736 if (dest != operands[0])
9737 emit_move_insn (dest, operands[0]);
9741 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
9743 (define_insn "negdf2_memory"
9744 [(set (match_operand:DF 0 "memory_operand" "=m")
9745 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
9746 (clobber (reg:CC 17))]
9747 "ix86_unary_operator_ok (NEG, DFmode, operands)"
9750 (define_insn "negdf2_ifs"
9751 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9752 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
9753 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
9754 (clobber (reg:CC 17))]
9755 "!TARGET_64BIT && TARGET_SSE2
9756 && (reload_in_progress || reload_completed
9757 || (register_operand (operands[0], VOIDmode)
9758 && register_operand (operands[1], VOIDmode)))"
9761 (define_insn "*negdf2_ifs_rex64"
9762 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
9763 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
9764 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
9765 (clobber (reg:CC 17))]
9766 "TARGET_64BIT && TARGET_SSE2
9767 && (reload_in_progress || reload_completed
9768 || (register_operand (operands[0], VOIDmode)
9769 && register_operand (operands[1], VOIDmode)))"
9773 [(set (match_operand:DF 0 "memory_operand" "")
9774 (neg:DF (match_operand:DF 1 "memory_operand" "")))
9775 (use (match_operand:V2DF 2 "" ""))
9776 (clobber (reg:CC 17))]
9778 [(parallel [(set (match_dup 0)
9779 (neg:DF (match_dup 1)))
9780 (clobber (reg:CC 17))])])
9783 [(set (match_operand:DF 0 "register_operand" "")
9784 (neg:DF (match_operand:DF 1 "register_operand" "")))
9785 (use (match_operand:V2DF 2 "" ""))
9786 (clobber (reg:CC 17))]
9787 "reload_completed && !SSE_REG_P (operands[0])
9788 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
9789 [(parallel [(set (match_dup 0)
9790 (neg:DF (match_dup 1)))
9791 (clobber (reg:CC 17))])])
9794 [(set (match_operand:DF 0 "register_operand" "")
9795 (neg:DF (match_operand:DF 1 "register_operand" "")))
9796 (use (match_operand:V2DF 2 "" ""))
9797 (clobber (reg:CC 17))]
9798 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
9799 [(parallel [(set (match_dup 0)
9800 (xor:DI (match_dup 1) (match_dup 2)))
9801 (clobber (reg:CC 17))])]
9802 "operands[0] = gen_lowpart (DImode, operands[0]);
9803 operands[1] = gen_lowpart (DImode, operands[1]);
9804 operands[2] = gen_lowpart (DImode, operands[2]);")
9807 [(set (match_operand:DF 0 "register_operand" "")
9808 (neg:DF (match_operand:DF 1 "register_operand" "")))
9809 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
9810 (clobber (reg:CC 17))]
9811 "reload_completed && SSE_REG_P (operands[0])"
9812 [(set (subreg:TI (match_dup 0) 0)
9813 (xor:TI (match_dup 1)
9816 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
9817 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
9818 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
9819 /* Avoid possible reformatting on the operands. */
9820 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
9821 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
9822 if (operands_match_p (operands[0], operands[2]))
9826 operands[1] = operands[2];
9831 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9832 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9834 (define_insn "*negdf2_if"
9835 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9836 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9837 (clobber (reg:CC 17))]
9838 "!TARGET_64BIT && TARGET_80387
9839 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9842 ;; FIXME: We should to allow integer registers here. Problem is that
9843 ;; we need another scratch register to get constant from.
9844 ;; Forcing constant to mem if no register available in peep2 should be
9845 ;; safe even for PIC mode, because of RIP relative addressing.
9846 (define_insn "*negdf2_if_rex64"
9847 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
9848 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
9849 (clobber (reg:CC 17))]
9850 "TARGET_64BIT && TARGET_80387
9851 && ix86_unary_operator_ok (NEG, DFmode, operands)"
9855 [(set (match_operand:DF 0 "fp_register_operand" "")
9856 (neg:DF (match_operand:DF 1 "register_operand" "")))
9857 (clobber (reg:CC 17))]
9858 "TARGET_80387 && reload_completed"
9860 (neg:DF (match_dup 1)))]
9864 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
9865 (neg:DF (match_operand:DF 1 "register_operand" "")))
9866 (clobber (reg:CC 17))]
9867 "!TARGET_64BIT && TARGET_80387 && reload_completed"
9868 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
9869 (clobber (reg:CC 17))])]
9870 "operands[4] = gen_int_mode (0x80000000, SImode);
9871 split_di (operands+0, 1, operands+2, operands+3);")
9873 (define_expand "negxf2"
9874 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
9875 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
9876 (clobber (reg:CC 17))])]
9878 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
9880 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9881 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9883 (define_insn "*negxf2_if"
9884 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9885 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
9886 (clobber (reg:CC 17))]
9888 && ix86_unary_operator_ok (NEG, XFmode, operands)"
9892 [(set (match_operand:XF 0 "fp_register_operand" "")
9893 (neg:XF (match_operand:XF 1 "register_operand" "")))
9894 (clobber (reg:CC 17))]
9895 "TARGET_80387 && reload_completed"
9897 (neg:XF (match_dup 1)))]
9901 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
9902 (neg:XF (match_operand:XF 1 "register_operand" "")))
9903 (clobber (reg:CC 17))]
9904 "TARGET_80387 && reload_completed"
9905 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9906 (clobber (reg:CC 17))])]
9907 "operands[1] = GEN_INT (0x8000);
9908 operands[0] = gen_rtx_REG (SImode,
9909 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
9911 ;; Conditionalize these after reload. If they matches before reload, we
9912 ;; lose the clobber and ability to use integer instructions.
9914 (define_insn "*negsf2_1"
9915 [(set (match_operand:SF 0 "register_operand" "=f")
9916 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9917 "TARGET_80387 && reload_completed"
9919 [(set_attr "type" "fsgn")
9920 (set_attr "mode" "SF")
9921 (set_attr "ppro_uops" "few")])
9923 (define_insn "*negdf2_1"
9924 [(set (match_operand:DF 0 "register_operand" "=f")
9925 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9926 "TARGET_80387 && reload_completed"
9928 [(set_attr "type" "fsgn")
9929 (set_attr "mode" "DF")
9930 (set_attr "ppro_uops" "few")])
9932 (define_insn "*negextendsfdf2"
9933 [(set (match_operand:DF 0 "register_operand" "=f")
9934 (neg:DF (float_extend:DF
9935 (match_operand:SF 1 "register_operand" "0"))))]
9938 [(set_attr "type" "fsgn")
9939 (set_attr "mode" "DF")
9940 (set_attr "ppro_uops" "few")])
9942 (define_insn "*negxf2_1"
9943 [(set (match_operand:XF 0 "register_operand" "=f")
9944 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9945 "TARGET_80387 && reload_completed"
9947 [(set_attr "type" "fsgn")
9948 (set_attr "mode" "XF")
9949 (set_attr "ppro_uops" "few")])
9951 (define_insn "*negextenddfxf2"
9952 [(set (match_operand:XF 0 "register_operand" "=f")
9953 (neg:XF (float_extend:XF
9954 (match_operand:DF 1 "register_operand" "0"))))]
9957 [(set_attr "type" "fsgn")
9958 (set_attr "mode" "XF")
9959 (set_attr "ppro_uops" "few")])
9961 (define_insn "*negextendsfxf2"
9962 [(set (match_operand:XF 0 "register_operand" "=f")
9963 (neg:XF (float_extend:XF
9964 (match_operand:SF 1 "register_operand" "0"))))]
9967 [(set_attr "type" "fsgn")
9968 (set_attr "mode" "XF")
9969 (set_attr "ppro_uops" "few")])
9971 ;; Absolute value instructions
9973 (define_expand "abssf2"
9974 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9975 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9976 (clobber (reg:CC 17))])]
9980 /* In case operand is in memory, we will not use SSE. */
9981 if (memory_operand (operands[0], VOIDmode)
9982 && rtx_equal_p (operands[0], operands[1]))
9983 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
9986 /* Using SSE is tricky, since we need bitwise negation of -0
9988 rtx reg = gen_reg_rtx (V4SFmode);
9989 rtx dest = operands[0];
9992 operands[1] = force_reg (SFmode, operands[1]);
9993 operands[0] = force_reg (SFmode, operands[0]);
9994 imm = gen_lowpart (SFmode, gen_int_mode(~0x80000000, SImode));
9995 reg = force_reg (V4SFmode,
9996 gen_rtx_CONST_VECTOR (V4SFmode,
9997 gen_rtvec (4, imm, CONST0_RTX (SFmode),
9998 CONST0_RTX (SFmode),
9999 CONST0_RTX (SFmode))));
10000 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
10001 if (dest != operands[0])
10002 emit_move_insn (dest, operands[0]);
10006 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
10008 (define_insn "abssf2_memory"
10009 [(set (match_operand:SF 0 "memory_operand" "=m")
10010 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
10011 (clobber (reg:CC 17))]
10012 "ix86_unary_operator_ok (ABS, SFmode, operands)"
10015 (define_insn "abssf2_ifs"
10016 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
10017 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
10018 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
10019 (clobber (reg:CC 17))]
10021 && (reload_in_progress || reload_completed
10022 || (register_operand (operands[0], VOIDmode)
10023 && register_operand (operands[1], VOIDmode)))"
10027 [(set (match_operand:SF 0 "memory_operand" "")
10028 (abs:SF (match_operand:SF 1 "memory_operand" "")))
10029 (use (match_operand:V4SF 2 "" ""))
10030 (clobber (reg:CC 17))]
10032 [(parallel [(set (match_dup 0)
10033 (abs:SF (match_dup 1)))
10034 (clobber (reg:CC 17))])])
10037 [(set (match_operand:SF 0 "register_operand" "")
10038 (abs:SF (match_operand:SF 1 "register_operand" "")))
10039 (use (match_operand:V4SF 2 "" ""))
10040 (clobber (reg:CC 17))]
10041 "reload_completed && !SSE_REG_P (operands[0])"
10042 [(parallel [(set (match_dup 0)
10043 (abs:SF (match_dup 1)))
10044 (clobber (reg:CC 17))])])
10047 [(set (match_operand:SF 0 "register_operand" "")
10048 (abs:SF (match_operand:SF 1 "register_operand" "")))
10049 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
10050 (clobber (reg:CC 17))]
10051 "reload_completed && SSE_REG_P (operands[0])"
10052 [(set (subreg:TI (match_dup 0) 0)
10053 (and:TI (match_dup 1)
10056 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
10057 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
10058 if (operands_match_p (operands[0], operands[2]))
10062 operands[1] = operands[2];
10067 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10068 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10070 (define_insn "*abssf2_if"
10071 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
10072 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
10073 (clobber (reg:CC 17))]
10074 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
10078 [(set (match_operand:SF 0 "fp_register_operand" "")
10079 (abs:SF (match_operand:SF 1 "register_operand" "")))
10080 (clobber (reg:CC 17))]
10081 "TARGET_80387 && reload_completed"
10082 [(set (match_dup 0)
10083 (abs:SF (match_dup 1)))]
10087 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
10088 (abs:SF (match_operand:SF 1 "register_operand" "")))
10089 (clobber (reg:CC 17))]
10090 "TARGET_80387 && reload_completed"
10091 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10092 (clobber (reg:CC 17))])]
10093 "operands[1] = gen_int_mode (~0x80000000, SImode);
10094 operands[0] = gen_lowpart (SImode, operands[0]);")
10097 [(set (match_operand 0 "memory_operand" "")
10098 (abs (match_operand 1 "memory_operand" "")))
10099 (clobber (reg:CC 17))]
10100 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
10101 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
10102 (clobber (reg:CC 17))])]
10104 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
10106 if (GET_MODE (operands[1]) == XFmode)
10108 operands[0] = adjust_address (operands[0], QImode, size - 1);
10109 operands[1] = gen_int_mode (~0x80, QImode);
10112 (define_expand "absdf2"
10113 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
10114 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
10115 (clobber (reg:CC 17))])]
10119 /* In case operand is in memory, we will not use SSE. */
10120 if (memory_operand (operands[0], VOIDmode)
10121 && rtx_equal_p (operands[0], operands[1]))
10122 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
10125 /* Using SSE is tricky, since we need bitwise negation of -0
10127 rtx reg = gen_reg_rtx (V2DFmode);
10128 #if HOST_BITS_PER_WIDE_INT >= 64
10129 rtx imm = gen_int_mode (~(((HOST_WIDE_INT)1) << 63), DImode);
10131 rtx imm = immed_double_const (~0, ~0x80000000, DImode);
10133 rtx dest = operands[0];
10135 operands[1] = force_reg (DFmode, operands[1]);
10136 operands[0] = force_reg (DFmode, operands[0]);
10138 /* Produce LONG_DOUBLE with the proper immediate argument. */
10139 imm = gen_lowpart (DFmode, imm);
10140 reg = force_reg (V2DFmode,
10141 gen_rtx_CONST_VECTOR (V2DFmode,
10142 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10143 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
10144 if (dest != operands[0])
10145 emit_move_insn (dest, operands[0]);
10149 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
10151 (define_insn "absdf2_memory"
10152 [(set (match_operand:DF 0 "memory_operand" "=m")
10153 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
10154 (clobber (reg:CC 17))]
10155 "ix86_unary_operator_ok (ABS, DFmode, operands)"
10158 (define_insn "absdf2_ifs"
10159 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf")
10160 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10161 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10162 (clobber (reg:CC 17))]
10163 "!TARGET_64BIT && TARGET_SSE2
10164 && (reload_in_progress || reload_completed
10165 || (register_operand (operands[0], VOIDmode)
10166 && register_operand (operands[1], VOIDmode)))"
10169 (define_insn "*absdf2_ifs_rex64"
10170 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr")
10171 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10172 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10173 (clobber (reg:CC 17))]
10174 "TARGET_64BIT && TARGET_SSE2
10175 && (reload_in_progress || reload_completed
10176 || (register_operand (operands[0], VOIDmode)
10177 && register_operand (operands[1], VOIDmode)))"
10181 [(set (match_operand:DF 0 "memory_operand" "")
10182 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10183 (use (match_operand:V2DF 2 "" ""))
10184 (clobber (reg:CC 17))]
10186 [(parallel [(set (match_dup 0)
10187 (abs:DF (match_dup 1)))
10188 (clobber (reg:CC 17))])])
10191 [(set (match_operand:DF 0 "register_operand" "")
10192 (abs:DF (match_operand:DF 1 "register_operand" "")))
10193 (use (match_operand:V2DF 2 "" ""))
10194 (clobber (reg:CC 17))]
10195 "reload_completed && !SSE_REG_P (operands[0])"
10196 [(parallel [(set (match_dup 0)
10197 (abs:DF (match_dup 1)))
10198 (clobber (reg:CC 17))])])
10201 [(set (match_operand:DF 0 "register_operand" "")
10202 (abs:DF (match_operand:DF 1 "register_operand" "")))
10203 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10204 (clobber (reg:CC 17))]
10205 "reload_completed && SSE_REG_P (operands[0])"
10206 [(set (subreg:TI (match_dup 0) 0)
10207 (and:TI (match_dup 1)
10210 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10211 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10212 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10213 /* Avoid possible reformatting on the operands. */
10214 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10215 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10216 if (operands_match_p (operands[0], operands[2]))
10220 operands[1] = operands[2];
10226 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10227 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10229 (define_insn "*absdf2_if"
10230 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10231 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10232 (clobber (reg:CC 17))]
10233 "!TARGET_64BIT && TARGET_80387
10234 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10237 ;; FIXME: We should to allow integer registers here. Problem is that
10238 ;; we need another scratch register to get constant from.
10239 ;; Forcing constant to mem if no register available in peep2 should be
10240 ;; safe even for PIC mode, because of RIP relative addressing.
10241 (define_insn "*absdf2_if_rex64"
10242 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10243 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10244 (clobber (reg:CC 17))]
10245 "TARGET_64BIT && TARGET_80387
10246 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10250 [(set (match_operand:DF 0 "fp_register_operand" "")
10251 (abs:DF (match_operand:DF 1 "register_operand" "")))
10252 (clobber (reg:CC 17))]
10253 "TARGET_80387 && reload_completed"
10254 [(set (match_dup 0)
10255 (abs:DF (match_dup 1)))]
10259 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10260 (abs:DF (match_operand:DF 1 "register_operand" "")))
10261 (clobber (reg:CC 17))]
10262 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10263 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10264 (clobber (reg:CC 17))])]
10265 "operands[4] = gen_int_mode (~0x80000000, SImode);
10266 split_di (operands+0, 1, operands+2, operands+3);")
10268 (define_expand "absxf2"
10269 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10270 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10271 (clobber (reg:CC 17))])]
10273 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10275 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10276 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10278 (define_insn "*absxf2_if"
10279 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10280 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10281 (clobber (reg:CC 17))]
10283 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10287 [(set (match_operand:XF 0 "fp_register_operand" "")
10288 (abs:XF (match_operand:XF 1 "register_operand" "")))
10289 (clobber (reg:CC 17))]
10290 "TARGET_80387 && reload_completed"
10291 [(set (match_dup 0)
10292 (abs:XF (match_dup 1)))]
10296 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10297 (abs:XF (match_operand:XF 1 "register_operand" "")))
10298 (clobber (reg:CC 17))]
10299 "TARGET_80387 && reload_completed"
10300 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10301 (clobber (reg:CC 17))])]
10302 "operands[1] = GEN_INT (~0x8000);
10303 operands[0] = gen_rtx_REG (SImode,
10304 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10306 (define_insn "*abssf2_1"
10307 [(set (match_operand:SF 0 "register_operand" "=f")
10308 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10309 "TARGET_80387 && reload_completed"
10311 [(set_attr "type" "fsgn")
10312 (set_attr "mode" "SF")])
10314 (define_insn "*absdf2_1"
10315 [(set (match_operand:DF 0 "register_operand" "=f")
10316 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10317 "TARGET_80387 && reload_completed"
10319 [(set_attr "type" "fsgn")
10320 (set_attr "mode" "DF")])
10322 (define_insn "*absextendsfdf2"
10323 [(set (match_operand:DF 0 "register_operand" "=f")
10324 (abs:DF (float_extend:DF
10325 (match_operand:SF 1 "register_operand" "0"))))]
10328 [(set_attr "type" "fsgn")
10329 (set_attr "mode" "DF")])
10331 (define_insn "*absxf2_1"
10332 [(set (match_operand:XF 0 "register_operand" "=f")
10333 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10334 "TARGET_80387 && reload_completed"
10336 [(set_attr "type" "fsgn")
10337 (set_attr "mode" "DF")])
10339 (define_insn "*absextenddfxf2"
10340 [(set (match_operand:XF 0 "register_operand" "=f")
10341 (abs:XF (float_extend:XF
10342 (match_operand:DF 1 "register_operand" "0"))))]
10345 [(set_attr "type" "fsgn")
10346 (set_attr "mode" "XF")])
10348 (define_insn "*absextendsfxf2"
10349 [(set (match_operand:XF 0 "register_operand" "=f")
10350 (abs:XF (float_extend:XF
10351 (match_operand:SF 1 "register_operand" "0"))))]
10354 [(set_attr "type" "fsgn")
10355 (set_attr "mode" "XF")])
10357 ;; One complement instructions
10359 (define_expand "one_cmpldi2"
10360 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10361 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10363 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10365 (define_insn "*one_cmpldi2_1_rex64"
10366 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10367 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10368 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10370 [(set_attr "type" "negnot")
10371 (set_attr "mode" "DI")])
10373 (define_insn "*one_cmpldi2_2_rex64"
10375 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10377 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10378 (not:DI (match_dup 1)))]
10379 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10380 && ix86_unary_operator_ok (NOT, DImode, operands)"
10382 [(set_attr "type" "alu1")
10383 (set_attr "mode" "DI")])
10387 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10389 (set (match_operand:DI 0 "nonimmediate_operand" "")
10390 (not:DI (match_dup 1)))]
10391 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10392 [(parallel [(set (reg:CCNO 17)
10393 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10396 (xor:DI (match_dup 1) (const_int -1)))])]
10399 (define_expand "one_cmplsi2"
10400 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10401 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10403 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10405 (define_insn "*one_cmplsi2_1"
10406 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10407 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10408 "ix86_unary_operator_ok (NOT, SImode, operands)"
10410 [(set_attr "type" "negnot")
10411 (set_attr "mode" "SI")])
10413 ;; ??? Currently never generated - xor is used instead.
10414 (define_insn "*one_cmplsi2_1_zext"
10415 [(set (match_operand:DI 0 "register_operand" "=r")
10416 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10417 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10419 [(set_attr "type" "negnot")
10420 (set_attr "mode" "SI")])
10422 (define_insn "*one_cmplsi2_2"
10424 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10426 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10427 (not:SI (match_dup 1)))]
10428 "ix86_match_ccmode (insn, CCNOmode)
10429 && ix86_unary_operator_ok (NOT, SImode, operands)"
10431 [(set_attr "type" "alu1")
10432 (set_attr "mode" "SI")])
10436 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10438 (set (match_operand:SI 0 "nonimmediate_operand" "")
10439 (not:SI (match_dup 1)))]
10440 "ix86_match_ccmode (insn, CCNOmode)"
10441 [(parallel [(set (reg:CCNO 17)
10442 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10445 (xor:SI (match_dup 1) (const_int -1)))])]
10448 ;; ??? Currently never generated - xor is used instead.
10449 (define_insn "*one_cmplsi2_2_zext"
10451 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10453 (set (match_operand:DI 0 "register_operand" "=r")
10454 (zero_extend:DI (not:SI (match_dup 1))))]
10455 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10456 && ix86_unary_operator_ok (NOT, SImode, operands)"
10458 [(set_attr "type" "alu1")
10459 (set_attr "mode" "SI")])
10463 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10465 (set (match_operand:DI 0 "register_operand" "")
10466 (zero_extend:DI (not:SI (match_dup 1))))]
10467 "ix86_match_ccmode (insn, CCNOmode)"
10468 [(parallel [(set (reg:CCNO 17)
10469 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10472 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10475 (define_expand "one_cmplhi2"
10476 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10477 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10478 "TARGET_HIMODE_MATH"
10479 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10481 (define_insn "*one_cmplhi2_1"
10482 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10483 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10484 "ix86_unary_operator_ok (NOT, HImode, operands)"
10486 [(set_attr "type" "negnot")
10487 (set_attr "mode" "HI")])
10489 (define_insn "*one_cmplhi2_2"
10491 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10493 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10494 (not:HI (match_dup 1)))]
10495 "ix86_match_ccmode (insn, CCNOmode)
10496 && ix86_unary_operator_ok (NEG, HImode, operands)"
10498 [(set_attr "type" "alu1")
10499 (set_attr "mode" "HI")])
10503 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10505 (set (match_operand:HI 0 "nonimmediate_operand" "")
10506 (not:HI (match_dup 1)))]
10507 "ix86_match_ccmode (insn, CCNOmode)"
10508 [(parallel [(set (reg:CCNO 17)
10509 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10512 (xor:HI (match_dup 1) (const_int -1)))])]
10515 ;; %%% Potential partial reg stall on alternative 1. What to do?
10516 (define_expand "one_cmplqi2"
10517 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10518 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10519 "TARGET_QIMODE_MATH"
10520 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10522 (define_insn "*one_cmplqi2_1"
10523 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10524 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10525 "ix86_unary_operator_ok (NOT, QImode, operands)"
10529 [(set_attr "type" "negnot")
10530 (set_attr "mode" "QI,SI")])
10532 (define_insn "*one_cmplqi2_2"
10534 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10536 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10537 (not:QI (match_dup 1)))]
10538 "ix86_match_ccmode (insn, CCNOmode)
10539 && ix86_unary_operator_ok (NOT, QImode, operands)"
10541 [(set_attr "type" "alu1")
10542 (set_attr "mode" "QI")])
10546 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10548 (set (match_operand:QI 0 "nonimmediate_operand" "")
10549 (not:QI (match_dup 1)))]
10550 "ix86_match_ccmode (insn, CCNOmode)"
10551 [(parallel [(set (reg:CCNO 17)
10552 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10555 (xor:QI (match_dup 1) (const_int -1)))])]
10558 ;; Arithmetic shift instructions
10560 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10561 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10562 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10563 ;; from the assembler input.
10565 ;; This instruction shifts the target reg/mem as usual, but instead of
10566 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10567 ;; is a left shift double, bits are taken from the high order bits of
10568 ;; reg, else if the insn is a shift right double, bits are taken from the
10569 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10570 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10572 ;; Since sh[lr]d does not change the `reg' operand, that is done
10573 ;; separately, making all shifts emit pairs of shift double and normal
10574 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10575 ;; support a 63 bit shift, each shift where the count is in a reg expands
10576 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10578 ;; If the shift count is a constant, we need never emit more than one
10579 ;; shift pair, instead using moves and sign extension for counts greater
10582 (define_expand "ashldi3"
10583 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10584 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10585 (match_operand:QI 2 "nonmemory_operand" "")))
10586 (clobber (reg:CC 17))])]
10589 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10591 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10594 ix86_expand_binary_operator (ASHIFT, DImode, operands);
10598 (define_insn "*ashldi3_1_rex64"
10599 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10600 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
10601 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10602 (clobber (reg:CC 17))]
10603 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10605 switch (get_attr_type (insn))
10608 if (operands[2] != const1_rtx)
10610 if (!rtx_equal_p (operands[0], operands[1]))
10612 return "add{q}\t{%0, %0|%0, %0}";
10615 if (GET_CODE (operands[2]) != CONST_INT
10616 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10618 operands[1] = gen_rtx_MULT (DImode, operands[1],
10619 GEN_INT (1 << INTVAL (operands[2])));
10620 return "lea{q}\t{%a1, %0|%0, %a1}";
10623 if (REG_P (operands[2]))
10624 return "sal{q}\t{%b2, %0|%0, %b2}";
10625 else if (GET_CODE (operands[2]) == CONST_INT
10626 && INTVAL (operands[2]) == 1
10627 && (TARGET_SHIFT1 || optimize_size))
10628 return "sal{q}\t%0";
10630 return "sal{q}\t{%2, %0|%0, %2}";
10633 [(set (attr "type")
10634 (cond [(eq_attr "alternative" "1")
10635 (const_string "lea")
10636 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10638 (match_operand 0 "register_operand" ""))
10639 (match_operand 2 "const1_operand" ""))
10640 (const_string "alu")
10642 (const_string "ishift")))
10643 (set_attr "mode" "DI")])
10645 ;; Convert lea to the lea pattern to avoid flags dependency.
10647 [(set (match_operand:DI 0 "register_operand" "")
10648 (ashift:DI (match_operand:DI 1 "register_operand" "")
10649 (match_operand:QI 2 "immediate_operand" "")))
10650 (clobber (reg:CC 17))]
10651 "TARGET_64BIT && reload_completed
10652 && true_regnum (operands[0]) != true_regnum (operands[1])"
10653 [(set (match_dup 0)
10654 (mult:DI (match_dup 1)
10656 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10658 ;; This pattern can't accept a variable shift count, since shifts by
10659 ;; zero don't affect the flags. We assume that shifts by constant
10660 ;; zero are optimized away.
10661 (define_insn "*ashldi3_cmp_rex64"
10664 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10665 (match_operand:QI 2 "immediate_operand" "e"))
10667 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10668 (ashift:DI (match_dup 1) (match_dup 2)))]
10669 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10670 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10672 switch (get_attr_type (insn))
10675 if (operands[2] != const1_rtx)
10677 return "add{q}\t{%0, %0|%0, %0}";
10680 if (REG_P (operands[2]))
10681 return "sal{q}\t{%b2, %0|%0, %b2}";
10682 else if (GET_CODE (operands[2]) == CONST_INT
10683 && INTVAL (operands[2]) == 1
10684 && (TARGET_SHIFT1 || optimize_size))
10685 return "sal{q}\t%0";
10687 return "sal{q}\t{%2, %0|%0, %2}";
10690 [(set (attr "type")
10691 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10693 (match_operand 0 "register_operand" ""))
10694 (match_operand 2 "const1_operand" ""))
10695 (const_string "alu")
10697 (const_string "ishift")))
10698 (set_attr "mode" "DI")])
10700 (define_insn "ashldi3_1"
10701 [(set (match_operand:DI 0 "register_operand" "=r")
10702 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10703 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10704 (clobber (match_scratch:SI 3 "=&r"))
10705 (clobber (reg:CC 17))]
10706 "!TARGET_64BIT && TARGET_CMOVE"
10708 [(set_attr "type" "multi")])
10710 (define_insn "*ashldi3_2"
10711 [(set (match_operand:DI 0 "register_operand" "=r")
10712 (ashift:DI (match_operand:DI 1 "register_operand" "0")
10713 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10714 (clobber (reg:CC 17))]
10717 [(set_attr "type" "multi")])
10720 [(set (match_operand:DI 0 "register_operand" "")
10721 (ashift:DI (match_operand:DI 1 "register_operand" "")
10722 (match_operand:QI 2 "nonmemory_operand" "")))
10723 (clobber (match_scratch:SI 3 ""))
10724 (clobber (reg:CC 17))]
10725 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
10727 "ix86_split_ashldi (operands, operands[3]); DONE;")
10730 [(set (match_operand:DI 0 "register_operand" "")
10731 (ashift:DI (match_operand:DI 1 "register_operand" "")
10732 (match_operand:QI 2 "nonmemory_operand" "")))
10733 (clobber (reg:CC 17))]
10734 "!TARGET_64BIT && reload_completed"
10736 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10738 (define_insn "x86_shld_1"
10739 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10740 (ior:SI (ashift:SI (match_dup 0)
10741 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10742 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10743 (minus:QI (const_int 32) (match_dup 2)))))
10744 (clobber (reg:CC 17))]
10747 shld{l}\t{%2, %1, %0|%0, %1, %2}
10748 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10749 [(set_attr "type" "ishift")
10750 (set_attr "prefix_0f" "1")
10751 (set_attr "mode" "SI")
10752 (set_attr "pent_pair" "np")
10753 (set_attr "athlon_decode" "vector")
10754 (set_attr "ppro_uops" "few")])
10756 (define_expand "x86_shift_adj_1"
10758 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10761 (set (match_operand:SI 0 "register_operand" "")
10762 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10763 (match_operand:SI 1 "register_operand" "")
10766 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
10767 (match_operand:SI 3 "register_operand" "r")
10772 (define_expand "x86_shift_adj_2"
10773 [(use (match_operand:SI 0 "register_operand" ""))
10774 (use (match_operand:SI 1 "register_operand" ""))
10775 (use (match_operand:QI 2 "register_operand" ""))]
10778 rtx label = gen_label_rtx ();
10781 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10783 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10784 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10785 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10786 gen_rtx_LABEL_REF (VOIDmode, label),
10788 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10789 JUMP_LABEL (tmp) = label;
10791 emit_move_insn (operands[0], operands[1]);
10792 emit_move_insn (operands[1], const0_rtx);
10794 emit_label (label);
10795 LABEL_NUSES (label) = 1;
10800 (define_expand "ashlsi3"
10801 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10802 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10803 (match_operand:QI 2 "nonmemory_operand" "")))
10804 (clobber (reg:CC 17))]
10806 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10808 (define_insn "*ashlsi3_1"
10809 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10810 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
10811 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10812 (clobber (reg:CC 17))]
10813 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10815 switch (get_attr_type (insn))
10818 if (operands[2] != const1_rtx)
10820 if (!rtx_equal_p (operands[0], operands[1]))
10822 return "add{l}\t{%0, %0|%0, %0}";
10828 if (REG_P (operands[2]))
10829 return "sal{l}\t{%b2, %0|%0, %b2}";
10830 else if (GET_CODE (operands[2]) == CONST_INT
10831 && INTVAL (operands[2]) == 1
10832 && (TARGET_SHIFT1 || optimize_size))
10833 return "sal{l}\t%0";
10835 return "sal{l}\t{%2, %0|%0, %2}";
10838 [(set (attr "type")
10839 (cond [(eq_attr "alternative" "1")
10840 (const_string "lea")
10841 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10843 (match_operand 0 "register_operand" ""))
10844 (match_operand 2 "const1_operand" ""))
10845 (const_string "alu")
10847 (const_string "ishift")))
10848 (set_attr "mode" "SI")])
10850 ;; Convert lea to the lea pattern to avoid flags dependency.
10852 [(set (match_operand 0 "register_operand" "")
10853 (ashift (match_operand 1 "index_register_operand" "")
10854 (match_operand:QI 2 "const_int_operand" "")))
10855 (clobber (reg:CC 17))]
10857 && true_regnum (operands[0]) != true_regnum (operands[1])"
10861 operands[0] = gen_lowpart (SImode, operands[0]);
10862 operands[1] = gen_lowpart (Pmode, operands[1]);
10863 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10864 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10865 if (Pmode != SImode)
10866 pat = gen_rtx_SUBREG (SImode, pat, 0);
10867 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10871 ;; Rare case of shifting RSP is handled by generating move and shift
10873 [(set (match_operand 0 "register_operand" "")
10874 (ashift (match_operand 1 "register_operand" "")
10875 (match_operand:QI 2 "const_int_operand" "")))
10876 (clobber (reg:CC 17))]
10878 && true_regnum (operands[0]) != true_regnum (operands[1])"
10882 emit_move_insn (operands[1], operands[0]);
10883 pat = gen_rtx_SET (VOIDmode, operands[0],
10884 gen_rtx_ASHIFT (GET_MODE (operands[0]),
10885 operands[0], operands[2]));
10886 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10887 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
10891 (define_insn "*ashlsi3_1_zext"
10892 [(set (match_operand:DI 0 "register_operand" "=r,r")
10893 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
10894 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10895 (clobber (reg:CC 17))]
10896 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10898 switch (get_attr_type (insn))
10901 if (operands[2] != const1_rtx)
10903 return "add{l}\t{%k0, %k0|%k0, %k0}";
10909 if (REG_P (operands[2]))
10910 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10911 else if (GET_CODE (operands[2]) == CONST_INT
10912 && INTVAL (operands[2]) == 1
10913 && (TARGET_SHIFT1 || optimize_size))
10914 return "sal{l}\t%k0";
10916 return "sal{l}\t{%2, %k0|%k0, %2}";
10919 [(set (attr "type")
10920 (cond [(eq_attr "alternative" "1")
10921 (const_string "lea")
10922 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10924 (match_operand 2 "const1_operand" ""))
10925 (const_string "alu")
10927 (const_string "ishift")))
10928 (set_attr "mode" "SI")])
10930 ;; Convert lea to the lea pattern to avoid flags dependency.
10932 [(set (match_operand:DI 0 "register_operand" "")
10933 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10934 (match_operand:QI 2 "const_int_operand" ""))))
10935 (clobber (reg:CC 17))]
10936 "TARGET_64BIT && reload_completed
10937 && true_regnum (operands[0]) != true_regnum (operands[1])"
10938 [(set (match_dup 0) (zero_extend:DI
10939 (subreg:SI (mult:SI (match_dup 1)
10940 (match_dup 2)) 0)))]
10942 operands[1] = gen_lowpart (Pmode, operands[1]);
10943 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10946 ;; This pattern can't accept a variable shift count, since shifts by
10947 ;; zero don't affect the flags. We assume that shifts by constant
10948 ;; zero are optimized away.
10949 (define_insn "*ashlsi3_cmp"
10952 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10953 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10955 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10956 (ashift:SI (match_dup 1) (match_dup 2)))]
10957 "ix86_match_ccmode (insn, CCGOCmode)
10958 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10960 switch (get_attr_type (insn))
10963 if (operands[2] != const1_rtx)
10965 return "add{l}\t{%0, %0|%0, %0}";
10968 if (REG_P (operands[2]))
10969 return "sal{l}\t{%b2, %0|%0, %b2}";
10970 else if (GET_CODE (operands[2]) == CONST_INT
10971 && INTVAL (operands[2]) == 1
10972 && (TARGET_SHIFT1 || optimize_size))
10973 return "sal{l}\t%0";
10975 return "sal{l}\t{%2, %0|%0, %2}";
10978 [(set (attr "type")
10979 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10981 (match_operand 0 "register_operand" ""))
10982 (match_operand 2 "const1_operand" ""))
10983 (const_string "alu")
10985 (const_string "ishift")))
10986 (set_attr "mode" "SI")])
10988 (define_insn "*ashlsi3_cmp_zext"
10991 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10992 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10994 (set (match_operand:DI 0 "register_operand" "=r")
10995 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10996 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10997 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10999 switch (get_attr_type (insn))
11002 if (operands[2] != const1_rtx)
11004 return "add{l}\t{%k0, %k0|%k0, %k0}";
11007 if (REG_P (operands[2]))
11008 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11009 else if (GET_CODE (operands[2]) == CONST_INT
11010 && INTVAL (operands[2]) == 1
11011 && (TARGET_SHIFT1 || optimize_size))
11012 return "sal{l}\t%k0";
11014 return "sal{l}\t{%2, %k0|%k0, %2}";
11017 [(set (attr "type")
11018 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11020 (match_operand 2 "const1_operand" ""))
11021 (const_string "alu")
11023 (const_string "ishift")))
11024 (set_attr "mode" "SI")])
11026 (define_expand "ashlhi3"
11027 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11028 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
11029 (match_operand:QI 2 "nonmemory_operand" "")))
11030 (clobber (reg:CC 17))]
11031 "TARGET_HIMODE_MATH"
11032 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
11034 (define_insn "*ashlhi3_1_lea"
11035 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
11036 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
11037 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11038 (clobber (reg:CC 17))]
11039 "!TARGET_PARTIAL_REG_STALL
11040 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11042 switch (get_attr_type (insn))
11047 if (operands[2] != const1_rtx)
11049 return "add{w}\t{%0, %0|%0, %0}";
11052 if (REG_P (operands[2]))
11053 return "sal{w}\t{%b2, %0|%0, %b2}";
11054 else if (GET_CODE (operands[2]) == CONST_INT
11055 && INTVAL (operands[2]) == 1
11056 && (TARGET_SHIFT1 || optimize_size))
11057 return "sal{w}\t%0";
11059 return "sal{w}\t{%2, %0|%0, %2}";
11062 [(set (attr "type")
11063 (cond [(eq_attr "alternative" "1")
11064 (const_string "lea")
11065 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11067 (match_operand 0 "register_operand" ""))
11068 (match_operand 2 "const1_operand" ""))
11069 (const_string "alu")
11071 (const_string "ishift")))
11072 (set_attr "mode" "HI,SI")])
11074 (define_insn "*ashlhi3_1"
11075 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11076 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11077 (match_operand:QI 2 "nonmemory_operand" "cI")))
11078 (clobber (reg:CC 17))]
11079 "TARGET_PARTIAL_REG_STALL
11080 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11082 switch (get_attr_type (insn))
11085 if (operands[2] != const1_rtx)
11087 return "add{w}\t{%0, %0|%0, %0}";
11090 if (REG_P (operands[2]))
11091 return "sal{w}\t{%b2, %0|%0, %b2}";
11092 else if (GET_CODE (operands[2]) == CONST_INT
11093 && INTVAL (operands[2]) == 1
11094 && (TARGET_SHIFT1 || optimize_size))
11095 return "sal{w}\t%0";
11097 return "sal{w}\t{%2, %0|%0, %2}";
11100 [(set (attr "type")
11101 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11103 (match_operand 0 "register_operand" ""))
11104 (match_operand 2 "const1_operand" ""))
11105 (const_string "alu")
11107 (const_string "ishift")))
11108 (set_attr "mode" "HI")])
11110 ;; This pattern can't accept a variable shift count, since shifts by
11111 ;; zero don't affect the flags. We assume that shifts by constant
11112 ;; zero are optimized away.
11113 (define_insn "*ashlhi3_cmp"
11116 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11117 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11119 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11120 (ashift:HI (match_dup 1) (match_dup 2)))]
11121 "ix86_match_ccmode (insn, CCGOCmode)
11122 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11124 switch (get_attr_type (insn))
11127 if (operands[2] != const1_rtx)
11129 return "add{w}\t{%0, %0|%0, %0}";
11132 if (REG_P (operands[2]))
11133 return "sal{w}\t{%b2, %0|%0, %b2}";
11134 else if (GET_CODE (operands[2]) == CONST_INT
11135 && INTVAL (operands[2]) == 1
11136 && (TARGET_SHIFT1 || optimize_size))
11137 return "sal{w}\t%0";
11139 return "sal{w}\t{%2, %0|%0, %2}";
11142 [(set (attr "type")
11143 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11145 (match_operand 0 "register_operand" ""))
11146 (match_operand 2 "const1_operand" ""))
11147 (const_string "alu")
11149 (const_string "ishift")))
11150 (set_attr "mode" "HI")])
11152 (define_expand "ashlqi3"
11153 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11154 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11155 (match_operand:QI 2 "nonmemory_operand" "")))
11156 (clobber (reg:CC 17))]
11157 "TARGET_QIMODE_MATH"
11158 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11160 ;; %%% Potential partial reg stall on alternative 2. What to do?
11162 (define_insn "*ashlqi3_1_lea"
11163 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11164 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11165 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11166 (clobber (reg:CC 17))]
11167 "!TARGET_PARTIAL_REG_STALL
11168 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11170 switch (get_attr_type (insn))
11175 if (operands[2] != const1_rtx)
11177 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11178 return "add{l}\t{%k0, %k0|%k0, %k0}";
11180 return "add{b}\t{%0, %0|%0, %0}";
11183 if (REG_P (operands[2]))
11185 if (get_attr_mode (insn) == MODE_SI)
11186 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11188 return "sal{b}\t{%b2, %0|%0, %b2}";
11190 else if (GET_CODE (operands[2]) == CONST_INT
11191 && INTVAL (operands[2]) == 1
11192 && (TARGET_SHIFT1 || optimize_size))
11194 if (get_attr_mode (insn) == MODE_SI)
11195 return "sal{l}\t%0";
11197 return "sal{b}\t%0";
11201 if (get_attr_mode (insn) == MODE_SI)
11202 return "sal{l}\t{%2, %k0|%k0, %2}";
11204 return "sal{b}\t{%2, %0|%0, %2}";
11208 [(set (attr "type")
11209 (cond [(eq_attr "alternative" "2")
11210 (const_string "lea")
11211 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11213 (match_operand 0 "register_operand" ""))
11214 (match_operand 2 "const1_operand" ""))
11215 (const_string "alu")
11217 (const_string "ishift")))
11218 (set_attr "mode" "QI,SI,SI")])
11220 (define_insn "*ashlqi3_1"
11221 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11222 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11223 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11224 (clobber (reg:CC 17))]
11225 "TARGET_PARTIAL_REG_STALL
11226 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11228 switch (get_attr_type (insn))
11231 if (operands[2] != const1_rtx)
11233 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11234 return "add{l}\t{%k0, %k0|%k0, %k0}";
11236 return "add{b}\t{%0, %0|%0, %0}";
11239 if (REG_P (operands[2]))
11241 if (get_attr_mode (insn) == MODE_SI)
11242 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11244 return "sal{b}\t{%b2, %0|%0, %b2}";
11246 else if (GET_CODE (operands[2]) == CONST_INT
11247 && INTVAL (operands[2]) == 1
11248 && (TARGET_SHIFT1 || optimize_size))
11250 if (get_attr_mode (insn) == MODE_SI)
11251 return "sal{l}\t%0";
11253 return "sal{b}\t%0";
11257 if (get_attr_mode (insn) == MODE_SI)
11258 return "sal{l}\t{%2, %k0|%k0, %2}";
11260 return "sal{b}\t{%2, %0|%0, %2}";
11264 [(set (attr "type")
11265 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11267 (match_operand 0 "register_operand" ""))
11268 (match_operand 2 "const1_operand" ""))
11269 (const_string "alu")
11271 (const_string "ishift")))
11272 (set_attr "mode" "QI,SI")])
11274 ;; This pattern can't accept a variable shift count, since shifts by
11275 ;; zero don't affect the flags. We assume that shifts by constant
11276 ;; zero are optimized away.
11277 (define_insn "*ashlqi3_cmp"
11280 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11281 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11283 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11284 (ashift:QI (match_dup 1) (match_dup 2)))]
11285 "ix86_match_ccmode (insn, CCGOCmode)
11286 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11288 switch (get_attr_type (insn))
11291 if (operands[2] != const1_rtx)
11293 return "add{b}\t{%0, %0|%0, %0}";
11296 if (REG_P (operands[2]))
11297 return "sal{b}\t{%b2, %0|%0, %b2}";
11298 else if (GET_CODE (operands[2]) == CONST_INT
11299 && INTVAL (operands[2]) == 1
11300 && (TARGET_SHIFT1 || optimize_size))
11301 return "sal{b}\t%0";
11303 return "sal{b}\t{%2, %0|%0, %2}";
11306 [(set (attr "type")
11307 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11309 (match_operand 0 "register_operand" ""))
11310 (match_operand 2 "const1_operand" ""))
11311 (const_string "alu")
11313 (const_string "ishift")))
11314 (set_attr "mode" "QI")])
11316 ;; See comment above `ashldi3' about how this works.
11318 (define_expand "ashrdi3"
11319 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11320 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11321 (match_operand:QI 2 "nonmemory_operand" "")))
11322 (clobber (reg:CC 17))])]
11325 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11327 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11330 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11334 (define_insn "ashrdi3_63_rex64"
11335 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11336 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11337 (match_operand:DI 2 "const_int_operand" "i,i")))
11338 (clobber (reg:CC 17))]
11339 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11340 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11343 sar{q}\t{%2, %0|%0, %2}"
11344 [(set_attr "type" "imovx,ishift")
11345 (set_attr "prefix_0f" "0,*")
11346 (set_attr "length_immediate" "0,*")
11347 (set_attr "modrm" "0,1")
11348 (set_attr "mode" "DI")])
11350 (define_insn "*ashrdi3_1_one_bit_rex64"
11351 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11352 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11353 (match_operand:QI 2 "const1_operand" "")))
11354 (clobber (reg:CC 17))]
11355 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11356 && (TARGET_SHIFT1 || optimize_size)"
11358 [(set_attr "type" "ishift")
11359 (set (attr "length")
11360 (if_then_else (match_operand:DI 0 "register_operand" "")
11362 (const_string "*")))])
11364 (define_insn "*ashrdi3_1_rex64"
11365 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11366 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11367 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11368 (clobber (reg:CC 17))]
11369 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11371 sar{q}\t{%2, %0|%0, %2}
11372 sar{q}\t{%b2, %0|%0, %b2}"
11373 [(set_attr "type" "ishift")
11374 (set_attr "mode" "DI")])
11376 ;; This pattern can't accept a variable shift count, since shifts by
11377 ;; zero don't affect the flags. We assume that shifts by constant
11378 ;; zero are optimized away.
11379 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11382 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11383 (match_operand:QI 2 "const1_operand" ""))
11385 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11386 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11387 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11388 && (TARGET_SHIFT1 || optimize_size)
11389 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11391 [(set_attr "type" "ishift")
11392 (set (attr "length")
11393 (if_then_else (match_operand:DI 0 "register_operand" "")
11395 (const_string "*")))])
11397 ;; This pattern can't accept a variable shift count, since shifts by
11398 ;; zero don't affect the flags. We assume that shifts by constant
11399 ;; zero are optimized away.
11400 (define_insn "*ashrdi3_cmp_rex64"
11403 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11404 (match_operand:QI 2 "const_int_operand" "n"))
11406 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11407 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11408 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11409 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11410 "sar{q}\t{%2, %0|%0, %2}"
11411 [(set_attr "type" "ishift")
11412 (set_attr "mode" "DI")])
11415 (define_insn "ashrdi3_1"
11416 [(set (match_operand:DI 0 "register_operand" "=r")
11417 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11418 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11419 (clobber (match_scratch:SI 3 "=&r"))
11420 (clobber (reg:CC 17))]
11421 "!TARGET_64BIT && TARGET_CMOVE"
11423 [(set_attr "type" "multi")])
11425 (define_insn "*ashrdi3_2"
11426 [(set (match_operand:DI 0 "register_operand" "=r")
11427 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11428 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11429 (clobber (reg:CC 17))]
11432 [(set_attr "type" "multi")])
11435 [(set (match_operand:DI 0 "register_operand" "")
11436 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11437 (match_operand:QI 2 "nonmemory_operand" "")))
11438 (clobber (match_scratch:SI 3 ""))
11439 (clobber (reg:CC 17))]
11440 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11442 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11445 [(set (match_operand:DI 0 "register_operand" "")
11446 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11447 (match_operand:QI 2 "nonmemory_operand" "")))
11448 (clobber (reg:CC 17))]
11449 "!TARGET_64BIT && reload_completed"
11451 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11453 (define_insn "x86_shrd_1"
11454 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11455 (ior:SI (ashiftrt:SI (match_dup 0)
11456 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11457 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11458 (minus:QI (const_int 32) (match_dup 2)))))
11459 (clobber (reg:CC 17))]
11462 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11463 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11464 [(set_attr "type" "ishift")
11465 (set_attr "prefix_0f" "1")
11466 (set_attr "pent_pair" "np")
11467 (set_attr "ppro_uops" "few")
11468 (set_attr "mode" "SI")])
11470 (define_expand "x86_shift_adj_3"
11471 [(use (match_operand:SI 0 "register_operand" ""))
11472 (use (match_operand:SI 1 "register_operand" ""))
11473 (use (match_operand:QI 2 "register_operand" ""))]
11476 rtx label = gen_label_rtx ();
11479 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11481 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11482 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11483 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11484 gen_rtx_LABEL_REF (VOIDmode, label),
11486 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11487 JUMP_LABEL (tmp) = label;
11489 emit_move_insn (operands[0], operands[1]);
11490 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11492 emit_label (label);
11493 LABEL_NUSES (label) = 1;
11498 (define_insn "ashrsi3_31"
11499 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11500 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11501 (match_operand:SI 2 "const_int_operand" "i,i")))
11502 (clobber (reg:CC 17))]
11503 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11504 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11507 sar{l}\t{%2, %0|%0, %2}"
11508 [(set_attr "type" "imovx,ishift")
11509 (set_attr "prefix_0f" "0,*")
11510 (set_attr "length_immediate" "0,*")
11511 (set_attr "modrm" "0,1")
11512 (set_attr "mode" "SI")])
11514 (define_insn "*ashrsi3_31_zext"
11515 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11516 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11517 (match_operand:SI 2 "const_int_operand" "i,i"))))
11518 (clobber (reg:CC 17))]
11519 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11520 && INTVAL (operands[2]) == 31
11521 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11524 sar{l}\t{%2, %k0|%k0, %2}"
11525 [(set_attr "type" "imovx,ishift")
11526 (set_attr "prefix_0f" "0,*")
11527 (set_attr "length_immediate" "0,*")
11528 (set_attr "modrm" "0,1")
11529 (set_attr "mode" "SI")])
11531 (define_expand "ashrsi3"
11532 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11533 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11534 (match_operand:QI 2 "nonmemory_operand" "")))
11535 (clobber (reg:CC 17))]
11537 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11539 (define_insn "*ashrsi3_1_one_bit"
11540 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11541 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11542 (match_operand:QI 2 "const1_operand" "")))
11543 (clobber (reg:CC 17))]
11544 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11545 && (TARGET_SHIFT1 || optimize_size)"
11547 [(set_attr "type" "ishift")
11548 (set (attr "length")
11549 (if_then_else (match_operand:SI 0 "register_operand" "")
11551 (const_string "*")))])
11553 (define_insn "*ashrsi3_1_one_bit_zext"
11554 [(set (match_operand:DI 0 "register_operand" "=r")
11555 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11556 (match_operand:QI 2 "const1_operand" ""))))
11557 (clobber (reg:CC 17))]
11558 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11559 && (TARGET_SHIFT1 || optimize_size)"
11561 [(set_attr "type" "ishift")
11562 (set_attr "length" "2")])
11564 (define_insn "*ashrsi3_1"
11565 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11566 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11567 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11568 (clobber (reg:CC 17))]
11569 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11571 sar{l}\t{%2, %0|%0, %2}
11572 sar{l}\t{%b2, %0|%0, %b2}"
11573 [(set_attr "type" "ishift")
11574 (set_attr "mode" "SI")])
11576 (define_insn "*ashrsi3_1_zext"
11577 [(set (match_operand:DI 0 "register_operand" "=r,r")
11578 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11579 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11580 (clobber (reg:CC 17))]
11581 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11583 sar{l}\t{%2, %k0|%k0, %2}
11584 sar{l}\t{%b2, %k0|%k0, %b2}"
11585 [(set_attr "type" "ishift")
11586 (set_attr "mode" "SI")])
11588 ;; This pattern can't accept a variable shift count, since shifts by
11589 ;; zero don't affect the flags. We assume that shifts by constant
11590 ;; zero are optimized away.
11591 (define_insn "*ashrsi3_one_bit_cmp"
11594 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11595 (match_operand:QI 2 "const1_operand" ""))
11597 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11598 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11599 "ix86_match_ccmode (insn, CCGOCmode)
11600 && (TARGET_SHIFT1 || optimize_size)
11601 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11603 [(set_attr "type" "ishift")
11604 (set (attr "length")
11605 (if_then_else (match_operand:SI 0 "register_operand" "")
11607 (const_string "*")))])
11609 (define_insn "*ashrsi3_one_bit_cmp_zext"
11612 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11613 (match_operand:QI 2 "const1_operand" ""))
11615 (set (match_operand:DI 0 "register_operand" "=r")
11616 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11617 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11618 && (TARGET_SHIFT1 || optimize_size)
11619 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11621 [(set_attr "type" "ishift")
11622 (set_attr "length" "2")])
11624 ;; This pattern can't accept a variable shift count, since shifts by
11625 ;; zero don't affect the flags. We assume that shifts by constant
11626 ;; zero are optimized away.
11627 (define_insn "*ashrsi3_cmp"
11630 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11631 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11633 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11634 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11635 "ix86_match_ccmode (insn, CCGOCmode)
11636 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11637 "sar{l}\t{%2, %0|%0, %2}"
11638 [(set_attr "type" "ishift")
11639 (set_attr "mode" "SI")])
11641 (define_insn "*ashrsi3_cmp_zext"
11644 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11645 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11647 (set (match_operand:DI 0 "register_operand" "=r")
11648 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11649 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11650 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11651 "sar{l}\t{%2, %k0|%k0, %2}"
11652 [(set_attr "type" "ishift")
11653 (set_attr "mode" "SI")])
11655 (define_expand "ashrhi3"
11656 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11657 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11658 (match_operand:QI 2 "nonmemory_operand" "")))
11659 (clobber (reg:CC 17))]
11660 "TARGET_HIMODE_MATH"
11661 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11663 (define_insn "*ashrhi3_1_one_bit"
11664 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11665 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11666 (match_operand:QI 2 "const1_operand" "")))
11667 (clobber (reg:CC 17))]
11668 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11669 && (TARGET_SHIFT1 || optimize_size)"
11671 [(set_attr "type" "ishift")
11672 (set (attr "length")
11673 (if_then_else (match_operand 0 "register_operand" "")
11675 (const_string "*")))])
11677 (define_insn "*ashrhi3_1"
11678 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11679 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11680 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11681 (clobber (reg:CC 17))]
11682 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11684 sar{w}\t{%2, %0|%0, %2}
11685 sar{w}\t{%b2, %0|%0, %b2}"
11686 [(set_attr "type" "ishift")
11687 (set_attr "mode" "HI")])
11689 ;; This pattern can't accept a variable shift count, since shifts by
11690 ;; zero don't affect the flags. We assume that shifts by constant
11691 ;; zero are optimized away.
11692 (define_insn "*ashrhi3_one_bit_cmp"
11695 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11696 (match_operand:QI 2 "const1_operand" ""))
11698 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11699 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11700 "ix86_match_ccmode (insn, CCGOCmode)
11701 && (TARGET_SHIFT1 || optimize_size)
11702 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11704 [(set_attr "type" "ishift")
11705 (set (attr "length")
11706 (if_then_else (match_operand 0 "register_operand" "")
11708 (const_string "*")))])
11710 ;; This pattern can't accept a variable shift count, since shifts by
11711 ;; zero don't affect the flags. We assume that shifts by constant
11712 ;; zero are optimized away.
11713 (define_insn "*ashrhi3_cmp"
11716 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11717 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11719 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11720 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11721 "ix86_match_ccmode (insn, CCGOCmode)
11722 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11723 "sar{w}\t{%2, %0|%0, %2}"
11724 [(set_attr "type" "ishift")
11725 (set_attr "mode" "HI")])
11727 (define_expand "ashrqi3"
11728 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11729 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11730 (match_operand:QI 2 "nonmemory_operand" "")))
11731 (clobber (reg:CC 17))]
11732 "TARGET_QIMODE_MATH"
11733 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11735 (define_insn "*ashrqi3_1_one_bit"
11736 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11737 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11738 (match_operand:QI 2 "const1_operand" "")))
11739 (clobber (reg:CC 17))]
11740 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11741 && (TARGET_SHIFT1 || optimize_size)"
11743 [(set_attr "type" "ishift")
11744 (set (attr "length")
11745 (if_then_else (match_operand 0 "register_operand" "")
11747 (const_string "*")))])
11749 (define_insn "*ashrqi3_1_one_bit_slp"
11750 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11751 (ashiftrt:QI (match_dup 0)
11752 (match_operand:QI 1 "const1_operand" "")))
11753 (clobber (reg:CC 17))]
11754 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11755 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11756 && (TARGET_SHIFT1 || optimize_size)"
11758 [(set_attr "type" "ishift1")
11759 (set (attr "length")
11760 (if_then_else (match_operand 0 "register_operand" "")
11762 (const_string "*")))])
11764 (define_insn "*ashrqi3_1"
11765 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11766 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11767 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11768 (clobber (reg:CC 17))]
11769 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11771 sar{b}\t{%2, %0|%0, %2}
11772 sar{b}\t{%b2, %0|%0, %b2}"
11773 [(set_attr "type" "ishift")
11774 (set_attr "mode" "QI")])
11776 (define_insn "*ashrqi3_1_slp"
11777 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11778 (ashiftrt:QI (match_dup 0)
11779 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11780 (clobber (reg:CC 17))]
11781 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11782 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11784 sar{b}\t{%1, %0|%0, %1}
11785 sar{b}\t{%b1, %0|%0, %b1}"
11786 [(set_attr "type" "ishift1")
11787 (set_attr "mode" "QI")])
11789 ;; This pattern can't accept a variable shift count, since shifts by
11790 ;; zero don't affect the flags. We assume that shifts by constant
11791 ;; zero are optimized away.
11792 (define_insn "*ashrqi3_one_bit_cmp"
11795 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11796 (match_operand:QI 2 "const1_operand" "I"))
11798 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11799 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11800 "ix86_match_ccmode (insn, CCGOCmode)
11801 && (TARGET_SHIFT1 || optimize_size)
11802 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11804 [(set_attr "type" "ishift")
11805 (set (attr "length")
11806 (if_then_else (match_operand 0 "register_operand" "")
11808 (const_string "*")))])
11810 ;; This pattern can't accept a variable shift count, since shifts by
11811 ;; zero don't affect the flags. We assume that shifts by constant
11812 ;; zero are optimized away.
11813 (define_insn "*ashrqi3_cmp"
11816 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11817 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11819 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11820 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11821 "ix86_match_ccmode (insn, CCGOCmode)
11822 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11823 "sar{b}\t{%2, %0|%0, %2}"
11824 [(set_attr "type" "ishift")
11825 (set_attr "mode" "QI")])
11827 ;; Logical shift instructions
11829 ;; See comment above `ashldi3' about how this works.
11831 (define_expand "lshrdi3"
11832 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11833 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11834 (match_operand:QI 2 "nonmemory_operand" "")))
11835 (clobber (reg:CC 17))])]
11838 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11840 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
11843 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
11847 (define_insn "*lshrdi3_1_one_bit_rex64"
11848 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11849 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11850 (match_operand:QI 2 "const1_operand" "")))
11851 (clobber (reg:CC 17))]
11852 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11853 && (TARGET_SHIFT1 || optimize_size)"
11855 [(set_attr "type" "ishift")
11856 (set (attr "length")
11857 (if_then_else (match_operand:DI 0 "register_operand" "")
11859 (const_string "*")))])
11861 (define_insn "*lshrdi3_1_rex64"
11862 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11863 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11864 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11865 (clobber (reg:CC 17))]
11866 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11868 shr{q}\t{%2, %0|%0, %2}
11869 shr{q}\t{%b2, %0|%0, %b2}"
11870 [(set_attr "type" "ishift")
11871 (set_attr "mode" "DI")])
11873 ;; This pattern can't accept a variable shift count, since shifts by
11874 ;; zero don't affect the flags. We assume that shifts by constant
11875 ;; zero are optimized away.
11876 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11879 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11880 (match_operand:QI 2 "const1_operand" ""))
11882 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11883 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11884 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11885 && (TARGET_SHIFT1 || optimize_size)
11886 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11888 [(set_attr "type" "ishift")
11889 (set (attr "length")
11890 (if_then_else (match_operand:DI 0 "register_operand" "")
11892 (const_string "*")))])
11894 ;; This pattern can't accept a variable shift count, since shifts by
11895 ;; zero don't affect the flags. We assume that shifts by constant
11896 ;; zero are optimized away.
11897 (define_insn "*lshrdi3_cmp_rex64"
11900 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11901 (match_operand:QI 2 "const_int_operand" "e"))
11903 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11904 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11905 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11906 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11907 "shr{q}\t{%2, %0|%0, %2}"
11908 [(set_attr "type" "ishift")
11909 (set_attr "mode" "DI")])
11911 (define_insn "lshrdi3_1"
11912 [(set (match_operand:DI 0 "register_operand" "=r")
11913 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11914 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11915 (clobber (match_scratch:SI 3 "=&r"))
11916 (clobber (reg:CC 17))]
11917 "!TARGET_64BIT && TARGET_CMOVE"
11919 [(set_attr "type" "multi")])
11921 (define_insn "*lshrdi3_2"
11922 [(set (match_operand:DI 0 "register_operand" "=r")
11923 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11924 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11925 (clobber (reg:CC 17))]
11928 [(set_attr "type" "multi")])
11931 [(set (match_operand:DI 0 "register_operand" "")
11932 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11933 (match_operand:QI 2 "nonmemory_operand" "")))
11934 (clobber (match_scratch:SI 3 ""))
11935 (clobber (reg:CC 17))]
11936 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11938 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11941 [(set (match_operand:DI 0 "register_operand" "")
11942 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11943 (match_operand:QI 2 "nonmemory_operand" "")))
11944 (clobber (reg:CC 17))]
11945 "!TARGET_64BIT && reload_completed"
11947 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11949 (define_expand "lshrsi3"
11950 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11951 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11952 (match_operand:QI 2 "nonmemory_operand" "")))
11953 (clobber (reg:CC 17))]
11955 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11957 (define_insn "*lshrsi3_1_one_bit"
11958 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11959 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11960 (match_operand:QI 2 "const1_operand" "")))
11961 (clobber (reg:CC 17))]
11962 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11963 && (TARGET_SHIFT1 || optimize_size)"
11965 [(set_attr "type" "ishift")
11966 (set (attr "length")
11967 (if_then_else (match_operand:SI 0 "register_operand" "")
11969 (const_string "*")))])
11971 (define_insn "*lshrsi3_1_one_bit_zext"
11972 [(set (match_operand:DI 0 "register_operand" "=r")
11973 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11974 (match_operand:QI 2 "const1_operand" "")))
11975 (clobber (reg:CC 17))]
11976 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11977 && (TARGET_SHIFT1 || optimize_size)"
11979 [(set_attr "type" "ishift")
11980 (set_attr "length" "2")])
11982 (define_insn "*lshrsi3_1"
11983 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11984 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11985 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11986 (clobber (reg:CC 17))]
11987 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11989 shr{l}\t{%2, %0|%0, %2}
11990 shr{l}\t{%b2, %0|%0, %b2}"
11991 [(set_attr "type" "ishift")
11992 (set_attr "mode" "SI")])
11994 (define_insn "*lshrsi3_1_zext"
11995 [(set (match_operand:DI 0 "register_operand" "=r,r")
11997 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11998 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11999 (clobber (reg:CC 17))]
12000 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12002 shr{l}\t{%2, %k0|%k0, %2}
12003 shr{l}\t{%b2, %k0|%k0, %b2}"
12004 [(set_attr "type" "ishift")
12005 (set_attr "mode" "SI")])
12007 ;; This pattern can't accept a variable shift count, since shifts by
12008 ;; zero don't affect the flags. We assume that shifts by constant
12009 ;; zero are optimized away.
12010 (define_insn "*lshrsi3_one_bit_cmp"
12013 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12014 (match_operand:QI 2 "const1_operand" ""))
12016 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12017 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12018 "ix86_match_ccmode (insn, CCGOCmode)
12019 && (TARGET_SHIFT1 || optimize_size)
12020 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12022 [(set_attr "type" "ishift")
12023 (set (attr "length")
12024 (if_then_else (match_operand:SI 0 "register_operand" "")
12026 (const_string "*")))])
12028 (define_insn "*lshrsi3_cmp_one_bit_zext"
12031 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12032 (match_operand:QI 2 "const1_operand" ""))
12034 (set (match_operand:DI 0 "register_operand" "=r")
12035 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12036 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12037 && (TARGET_SHIFT1 || optimize_size)
12038 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12040 [(set_attr "type" "ishift")
12041 (set_attr "length" "2")])
12043 ;; This pattern can't accept a variable shift count, since shifts by
12044 ;; zero don't affect the flags. We assume that shifts by constant
12045 ;; zero are optimized away.
12046 (define_insn "*lshrsi3_cmp"
12049 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12050 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12052 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12053 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12054 "ix86_match_ccmode (insn, CCGOCmode)
12055 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12056 "shr{l}\t{%2, %0|%0, %2}"
12057 [(set_attr "type" "ishift")
12058 (set_attr "mode" "SI")])
12060 (define_insn "*lshrsi3_cmp_zext"
12063 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12064 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12066 (set (match_operand:DI 0 "register_operand" "=r")
12067 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12068 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12069 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12070 "shr{l}\t{%2, %k0|%k0, %2}"
12071 [(set_attr "type" "ishift")
12072 (set_attr "mode" "SI")])
12074 (define_expand "lshrhi3"
12075 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12076 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12077 (match_operand:QI 2 "nonmemory_operand" "")))
12078 (clobber (reg:CC 17))]
12079 "TARGET_HIMODE_MATH"
12080 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
12082 (define_insn "*lshrhi3_1_one_bit"
12083 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12084 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12085 (match_operand:QI 2 "const1_operand" "")))
12086 (clobber (reg:CC 17))]
12087 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12088 && (TARGET_SHIFT1 || optimize_size)"
12090 [(set_attr "type" "ishift")
12091 (set (attr "length")
12092 (if_then_else (match_operand 0 "register_operand" "")
12094 (const_string "*")))])
12096 (define_insn "*lshrhi3_1"
12097 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12098 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12099 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12100 (clobber (reg:CC 17))]
12101 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12103 shr{w}\t{%2, %0|%0, %2}
12104 shr{w}\t{%b2, %0|%0, %b2}"
12105 [(set_attr "type" "ishift")
12106 (set_attr "mode" "HI")])
12108 ;; This pattern can't accept a variable shift count, since shifts by
12109 ;; zero don't affect the flags. We assume that shifts by constant
12110 ;; zero are optimized away.
12111 (define_insn "*lshrhi3_one_bit_cmp"
12114 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12115 (match_operand:QI 2 "const1_operand" ""))
12117 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12118 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12119 "ix86_match_ccmode (insn, CCGOCmode)
12120 && (TARGET_SHIFT1 || optimize_size)
12121 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12123 [(set_attr "type" "ishift")
12124 (set (attr "length")
12125 (if_then_else (match_operand:SI 0 "register_operand" "")
12127 (const_string "*")))])
12129 ;; This pattern can't accept a variable shift count, since shifts by
12130 ;; zero don't affect the flags. We assume that shifts by constant
12131 ;; zero are optimized away.
12132 (define_insn "*lshrhi3_cmp"
12135 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12136 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12138 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12139 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12140 "ix86_match_ccmode (insn, CCGOCmode)
12141 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12142 "shr{w}\t{%2, %0|%0, %2}"
12143 [(set_attr "type" "ishift")
12144 (set_attr "mode" "HI")])
12146 (define_expand "lshrqi3"
12147 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12148 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12149 (match_operand:QI 2 "nonmemory_operand" "")))
12150 (clobber (reg:CC 17))]
12151 "TARGET_QIMODE_MATH"
12152 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
12154 (define_insn "*lshrqi3_1_one_bit"
12155 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12156 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12157 (match_operand:QI 2 "const1_operand" "")))
12158 (clobber (reg:CC 17))]
12159 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
12160 && (TARGET_SHIFT1 || optimize_size)"
12162 [(set_attr "type" "ishift")
12163 (set (attr "length")
12164 (if_then_else (match_operand 0 "register_operand" "")
12166 (const_string "*")))])
12168 (define_insn "*lshrqi3_1_one_bit_slp"
12169 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12170 (lshiftrt:QI (match_dup 0)
12171 (match_operand:QI 1 "const1_operand" "")))
12172 (clobber (reg:CC 17))]
12173 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12174 && (TARGET_SHIFT1 || optimize_size)"
12176 [(set_attr "type" "ishift1")
12177 (set (attr "length")
12178 (if_then_else (match_operand 0 "register_operand" "")
12180 (const_string "*")))])
12182 (define_insn "*lshrqi3_1"
12183 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12184 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12185 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12186 (clobber (reg:CC 17))]
12187 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12189 shr{b}\t{%2, %0|%0, %2}
12190 shr{b}\t{%b2, %0|%0, %b2}"
12191 [(set_attr "type" "ishift")
12192 (set_attr "mode" "QI")])
12194 (define_insn "*lshrqi3_1_slp"
12195 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12196 (lshiftrt:QI (match_dup 0)
12197 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12198 (clobber (reg:CC 17))]
12199 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12200 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12202 shr{b}\t{%1, %0|%0, %1}
12203 shr{b}\t{%b1, %0|%0, %b1}"
12204 [(set_attr "type" "ishift1")
12205 (set_attr "mode" "QI")])
12207 ;; This pattern can't accept a variable shift count, since shifts by
12208 ;; zero don't affect the flags. We assume that shifts by constant
12209 ;; zero are optimized away.
12210 (define_insn "*lshrqi2_one_bit_cmp"
12213 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12214 (match_operand:QI 2 "const1_operand" ""))
12216 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12217 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12218 "ix86_match_ccmode (insn, CCGOCmode)
12219 && (TARGET_SHIFT1 || optimize_size)
12220 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12222 [(set_attr "type" "ishift")
12223 (set (attr "length")
12224 (if_then_else (match_operand:SI 0 "register_operand" "")
12226 (const_string "*")))])
12228 ;; This pattern can't accept a variable shift count, since shifts by
12229 ;; zero don't affect the flags. We assume that shifts by constant
12230 ;; zero are optimized away.
12231 (define_insn "*lshrqi2_cmp"
12234 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12235 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12237 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12238 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12239 "ix86_match_ccmode (insn, CCGOCmode)
12240 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12241 "shr{b}\t{%2, %0|%0, %2}"
12242 [(set_attr "type" "ishift")
12243 (set_attr "mode" "QI")])
12245 ;; Rotate instructions
12247 (define_expand "rotldi3"
12248 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12249 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12250 (match_operand:QI 2 "nonmemory_operand" "")))
12251 (clobber (reg:CC 17))]
12253 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12255 (define_insn "*rotlsi3_1_one_bit_rex64"
12256 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12257 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12258 (match_operand:QI 2 "const1_operand" "")))
12259 (clobber (reg:CC 17))]
12260 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12261 && (TARGET_SHIFT1 || optimize_size)"
12263 [(set_attr "type" "rotate")
12264 (set (attr "length")
12265 (if_then_else (match_operand:DI 0 "register_operand" "")
12267 (const_string "*")))])
12269 (define_insn "*rotldi3_1_rex64"
12270 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12271 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12272 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12273 (clobber (reg:CC 17))]
12274 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12276 rol{q}\t{%2, %0|%0, %2}
12277 rol{q}\t{%b2, %0|%0, %b2}"
12278 [(set_attr "type" "rotate")
12279 (set_attr "mode" "DI")])
12281 (define_expand "rotlsi3"
12282 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12283 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12284 (match_operand:QI 2 "nonmemory_operand" "")))
12285 (clobber (reg:CC 17))]
12287 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12289 (define_insn "*rotlsi3_1_one_bit"
12290 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12291 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12292 (match_operand:QI 2 "const1_operand" "")))
12293 (clobber (reg:CC 17))]
12294 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12295 && (TARGET_SHIFT1 || optimize_size)"
12297 [(set_attr "type" "rotate")
12298 (set (attr "length")
12299 (if_then_else (match_operand:SI 0 "register_operand" "")
12301 (const_string "*")))])
12303 (define_insn "*rotlsi3_1_one_bit_zext"
12304 [(set (match_operand:DI 0 "register_operand" "=r")
12306 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12307 (match_operand:QI 2 "const1_operand" ""))))
12308 (clobber (reg:CC 17))]
12309 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12310 && (TARGET_SHIFT1 || optimize_size)"
12312 [(set_attr "type" "rotate")
12313 (set_attr "length" "2")])
12315 (define_insn "*rotlsi3_1"
12316 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12317 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12318 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12319 (clobber (reg:CC 17))]
12320 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12322 rol{l}\t{%2, %0|%0, %2}
12323 rol{l}\t{%b2, %0|%0, %b2}"
12324 [(set_attr "type" "rotate")
12325 (set_attr "mode" "SI")])
12327 (define_insn "*rotlsi3_1_zext"
12328 [(set (match_operand:DI 0 "register_operand" "=r,r")
12330 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12331 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12332 (clobber (reg:CC 17))]
12333 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12335 rol{l}\t{%2, %k0|%k0, %2}
12336 rol{l}\t{%b2, %k0|%k0, %b2}"
12337 [(set_attr "type" "rotate")
12338 (set_attr "mode" "SI")])
12340 (define_expand "rotlhi3"
12341 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12342 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12343 (match_operand:QI 2 "nonmemory_operand" "")))
12344 (clobber (reg:CC 17))]
12345 "TARGET_HIMODE_MATH"
12346 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12348 (define_insn "*rotlhi3_1_one_bit"
12349 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12350 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12351 (match_operand:QI 2 "const1_operand" "")))
12352 (clobber (reg:CC 17))]
12353 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12354 && (TARGET_SHIFT1 || optimize_size)"
12356 [(set_attr "type" "rotate")
12357 (set (attr "length")
12358 (if_then_else (match_operand 0 "register_operand" "")
12360 (const_string "*")))])
12362 (define_insn "*rotlhi3_1"
12363 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12364 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12365 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12366 (clobber (reg:CC 17))]
12367 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12369 rol{w}\t{%2, %0|%0, %2}
12370 rol{w}\t{%b2, %0|%0, %b2}"
12371 [(set_attr "type" "rotate")
12372 (set_attr "mode" "HI")])
12374 (define_expand "rotlqi3"
12375 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12376 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12377 (match_operand:QI 2 "nonmemory_operand" "")))
12378 (clobber (reg:CC 17))]
12379 "TARGET_QIMODE_MATH"
12380 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12382 (define_insn "*rotlqi3_1_one_bit_slp"
12383 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12384 (rotate:QI (match_dup 0)
12385 (match_operand:QI 1 "const1_operand" "")))
12386 (clobber (reg:CC 17))]
12387 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12388 && (TARGET_SHIFT1 || optimize_size)"
12390 [(set_attr "type" "rotate1")
12391 (set (attr "length")
12392 (if_then_else (match_operand 0 "register_operand" "")
12394 (const_string "*")))])
12396 (define_insn "*rotlqi3_1_one_bit"
12397 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12398 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12399 (match_operand:QI 2 "const1_operand" "")))
12400 (clobber (reg:CC 17))]
12401 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12402 && (TARGET_SHIFT1 || optimize_size)"
12404 [(set_attr "type" "rotate")
12405 (set (attr "length")
12406 (if_then_else (match_operand 0 "register_operand" "")
12408 (const_string "*")))])
12410 (define_insn "*rotlqi3_1_slp"
12411 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12412 (rotate:QI (match_dup 0)
12413 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12414 (clobber (reg:CC 17))]
12415 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12416 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12418 rol{b}\t{%1, %0|%0, %1}
12419 rol{b}\t{%b1, %0|%0, %b1}"
12420 [(set_attr "type" "rotate1")
12421 (set_attr "mode" "QI")])
12423 (define_insn "*rotlqi3_1"
12424 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12425 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12426 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12427 (clobber (reg:CC 17))]
12428 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12430 rol{b}\t{%2, %0|%0, %2}
12431 rol{b}\t{%b2, %0|%0, %b2}"
12432 [(set_attr "type" "rotate")
12433 (set_attr "mode" "QI")])
12435 (define_expand "rotrdi3"
12436 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12437 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12438 (match_operand:QI 2 "nonmemory_operand" "")))
12439 (clobber (reg:CC 17))]
12441 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12443 (define_insn "*rotrdi3_1_one_bit_rex64"
12444 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12445 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12446 (match_operand:QI 2 "const1_operand" "")))
12447 (clobber (reg:CC 17))]
12448 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12449 && (TARGET_SHIFT1 || optimize_size)"
12451 [(set_attr "type" "rotate")
12452 (set (attr "length")
12453 (if_then_else (match_operand:DI 0 "register_operand" "")
12455 (const_string "*")))])
12457 (define_insn "*rotrdi3_1_rex64"
12458 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12459 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12460 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12461 (clobber (reg:CC 17))]
12462 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12464 ror{q}\t{%2, %0|%0, %2}
12465 ror{q}\t{%b2, %0|%0, %b2}"
12466 [(set_attr "type" "rotate")
12467 (set_attr "mode" "DI")])
12469 (define_expand "rotrsi3"
12470 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12471 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12472 (match_operand:QI 2 "nonmemory_operand" "")))
12473 (clobber (reg:CC 17))]
12475 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12477 (define_insn "*rotrsi3_1_one_bit"
12478 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12479 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12480 (match_operand:QI 2 "const1_operand" "")))
12481 (clobber (reg:CC 17))]
12482 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12483 && (TARGET_SHIFT1 || optimize_size)"
12485 [(set_attr "type" "rotate")
12486 (set (attr "length")
12487 (if_then_else (match_operand:SI 0 "register_operand" "")
12489 (const_string "*")))])
12491 (define_insn "*rotrsi3_1_one_bit_zext"
12492 [(set (match_operand:DI 0 "register_operand" "=r")
12494 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12495 (match_operand:QI 2 "const1_operand" ""))))
12496 (clobber (reg:CC 17))]
12497 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12498 && (TARGET_SHIFT1 || optimize_size)"
12500 [(set_attr "type" "rotate")
12501 (set (attr "length")
12502 (if_then_else (match_operand:SI 0 "register_operand" "")
12504 (const_string "*")))])
12506 (define_insn "*rotrsi3_1"
12507 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12508 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12509 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12510 (clobber (reg:CC 17))]
12511 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12513 ror{l}\t{%2, %0|%0, %2}
12514 ror{l}\t{%b2, %0|%0, %b2}"
12515 [(set_attr "type" "rotate")
12516 (set_attr "mode" "SI")])
12518 (define_insn "*rotrsi3_1_zext"
12519 [(set (match_operand:DI 0 "register_operand" "=r,r")
12521 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12522 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12523 (clobber (reg:CC 17))]
12524 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12526 ror{l}\t{%2, %k0|%k0, %2}
12527 ror{l}\t{%b2, %k0|%k0, %b2}"
12528 [(set_attr "type" "rotate")
12529 (set_attr "mode" "SI")])
12531 (define_expand "rotrhi3"
12532 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12533 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12534 (match_operand:QI 2 "nonmemory_operand" "")))
12535 (clobber (reg:CC 17))]
12536 "TARGET_HIMODE_MATH"
12537 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12539 (define_insn "*rotrhi3_one_bit"
12540 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12541 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12542 (match_operand:QI 2 "const1_operand" "")))
12543 (clobber (reg:CC 17))]
12544 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12545 && (TARGET_SHIFT1 || optimize_size)"
12547 [(set_attr "type" "rotate")
12548 (set (attr "length")
12549 (if_then_else (match_operand 0 "register_operand" "")
12551 (const_string "*")))])
12553 (define_insn "*rotrhi3"
12554 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12555 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12556 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12557 (clobber (reg:CC 17))]
12558 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12560 ror{w}\t{%2, %0|%0, %2}
12561 ror{w}\t{%b2, %0|%0, %b2}"
12562 [(set_attr "type" "rotate")
12563 (set_attr "mode" "HI")])
12565 (define_expand "rotrqi3"
12566 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12567 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12568 (match_operand:QI 2 "nonmemory_operand" "")))
12569 (clobber (reg:CC 17))]
12570 "TARGET_QIMODE_MATH"
12571 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12573 (define_insn "*rotrqi3_1_one_bit"
12574 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12575 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12576 (match_operand:QI 2 "const1_operand" "")))
12577 (clobber (reg:CC 17))]
12578 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12579 && (TARGET_SHIFT1 || optimize_size)"
12581 [(set_attr "type" "rotate")
12582 (set (attr "length")
12583 (if_then_else (match_operand 0 "register_operand" "")
12585 (const_string "*")))])
12587 (define_insn "*rotrqi3_1_one_bit_slp"
12588 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12589 (rotatert:QI (match_dup 0)
12590 (match_operand:QI 1 "const1_operand" "")))
12591 (clobber (reg:CC 17))]
12592 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12593 && (TARGET_SHIFT1 || optimize_size)"
12595 [(set_attr "type" "rotate1")
12596 (set (attr "length")
12597 (if_then_else (match_operand 0 "register_operand" "")
12599 (const_string "*")))])
12601 (define_insn "*rotrqi3_1"
12602 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12603 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12604 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12605 (clobber (reg:CC 17))]
12606 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12608 ror{b}\t{%2, %0|%0, %2}
12609 ror{b}\t{%b2, %0|%0, %b2}"
12610 [(set_attr "type" "rotate")
12611 (set_attr "mode" "QI")])
12613 (define_insn "*rotrqi3_1_slp"
12614 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12615 (rotatert:QI (match_dup 0)
12616 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12617 (clobber (reg:CC 17))]
12618 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12619 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12621 ror{b}\t{%1, %0|%0, %1}
12622 ror{b}\t{%b1, %0|%0, %b1}"
12623 [(set_attr "type" "rotate1")
12624 (set_attr "mode" "QI")])
12626 ;; Bit set / bit test instructions
12628 (define_expand "extv"
12629 [(set (match_operand:SI 0 "register_operand" "")
12630 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12631 (match_operand:SI 2 "immediate_operand" "")
12632 (match_operand:SI 3 "immediate_operand" "")))]
12635 /* Handle extractions from %ah et al. */
12636 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12639 /* From mips.md: extract_bit_field doesn't verify that our source
12640 matches the predicate, so check it again here. */
12641 if (! register_operand (operands[1], VOIDmode))
12645 (define_expand "extzv"
12646 [(set (match_operand:SI 0 "register_operand" "")
12647 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12648 (match_operand:SI 2 "immediate_operand" "")
12649 (match_operand:SI 3 "immediate_operand" "")))]
12652 /* Handle extractions from %ah et al. */
12653 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12656 /* From mips.md: extract_bit_field doesn't verify that our source
12657 matches the predicate, so check it again here. */
12658 if (! register_operand (operands[1], VOIDmode))
12662 (define_expand "insv"
12663 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
12664 (match_operand:SI 1 "immediate_operand" "")
12665 (match_operand:SI 2 "immediate_operand" ""))
12666 (match_operand:SI 3 "register_operand" ""))]
12669 /* Handle extractions from %ah et al. */
12670 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12673 /* From mips.md: insert_bit_field doesn't verify that our source
12674 matches the predicate, so check it again here. */
12675 if (! register_operand (operands[0], VOIDmode))
12679 ;; %%% bts, btr, btc, bt.
12681 ;; Store-flag instructions.
12683 ;; For all sCOND expanders, also expand the compare or test insn that
12684 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12686 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12687 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12688 ;; way, which can later delete the movzx if only QImode is needed.
12690 (define_expand "seq"
12691 [(set (match_operand:QI 0 "register_operand" "")
12692 (eq:QI (reg:CC 17) (const_int 0)))]
12694 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12696 (define_expand "sne"
12697 [(set (match_operand:QI 0 "register_operand" "")
12698 (ne:QI (reg:CC 17) (const_int 0)))]
12700 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12702 (define_expand "sgt"
12703 [(set (match_operand:QI 0 "register_operand" "")
12704 (gt:QI (reg:CC 17) (const_int 0)))]
12706 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12708 (define_expand "sgtu"
12709 [(set (match_operand:QI 0 "register_operand" "")
12710 (gtu:QI (reg:CC 17) (const_int 0)))]
12712 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12714 (define_expand "slt"
12715 [(set (match_operand:QI 0 "register_operand" "")
12716 (lt:QI (reg:CC 17) (const_int 0)))]
12718 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12720 (define_expand "sltu"
12721 [(set (match_operand:QI 0 "register_operand" "")
12722 (ltu:QI (reg:CC 17) (const_int 0)))]
12724 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12726 (define_expand "sge"
12727 [(set (match_operand:QI 0 "register_operand" "")
12728 (ge:QI (reg:CC 17) (const_int 0)))]
12730 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12732 (define_expand "sgeu"
12733 [(set (match_operand:QI 0 "register_operand" "")
12734 (geu:QI (reg:CC 17) (const_int 0)))]
12736 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12738 (define_expand "sle"
12739 [(set (match_operand:QI 0 "register_operand" "")
12740 (le:QI (reg:CC 17) (const_int 0)))]
12742 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12744 (define_expand "sleu"
12745 [(set (match_operand:QI 0 "register_operand" "")
12746 (leu:QI (reg:CC 17) (const_int 0)))]
12748 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12750 (define_expand "sunordered"
12751 [(set (match_operand:QI 0 "register_operand" "")
12752 (unordered:QI (reg:CC 17) (const_int 0)))]
12753 "TARGET_80387 || TARGET_SSE"
12754 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12756 (define_expand "sordered"
12757 [(set (match_operand:QI 0 "register_operand" "")
12758 (ordered:QI (reg:CC 17) (const_int 0)))]
12760 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12762 (define_expand "suneq"
12763 [(set (match_operand:QI 0 "register_operand" "")
12764 (uneq:QI (reg:CC 17) (const_int 0)))]
12765 "TARGET_80387 || TARGET_SSE"
12766 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12768 (define_expand "sunge"
12769 [(set (match_operand:QI 0 "register_operand" "")
12770 (unge:QI (reg:CC 17) (const_int 0)))]
12771 "TARGET_80387 || TARGET_SSE"
12772 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12774 (define_expand "sungt"
12775 [(set (match_operand:QI 0 "register_operand" "")
12776 (ungt:QI (reg:CC 17) (const_int 0)))]
12777 "TARGET_80387 || TARGET_SSE"
12778 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12780 (define_expand "sunle"
12781 [(set (match_operand:QI 0 "register_operand" "")
12782 (unle:QI (reg:CC 17) (const_int 0)))]
12783 "TARGET_80387 || TARGET_SSE"
12784 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12786 (define_expand "sunlt"
12787 [(set (match_operand:QI 0 "register_operand" "")
12788 (unlt:QI (reg:CC 17) (const_int 0)))]
12789 "TARGET_80387 || TARGET_SSE"
12790 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12792 (define_expand "sltgt"
12793 [(set (match_operand:QI 0 "register_operand" "")
12794 (ltgt:QI (reg:CC 17) (const_int 0)))]
12795 "TARGET_80387 || TARGET_SSE"
12796 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12798 (define_insn "*setcc_1"
12799 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12800 (match_operator:QI 1 "ix86_comparison_operator"
12801 [(reg 17) (const_int 0)]))]
12804 [(set_attr "type" "setcc")
12805 (set_attr "mode" "QI")])
12807 (define_insn "setcc_2"
12808 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12809 (match_operator:QI 1 "ix86_comparison_operator"
12810 [(reg 17) (const_int 0)]))]
12813 [(set_attr "type" "setcc")
12814 (set_attr "mode" "QI")])
12816 ;; In general it is not safe to assume too much about CCmode registers,
12817 ;; so simplify-rtx stops when it sees a second one. Under certain
12818 ;; conditions this is safe on x86, so help combine not create
12825 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12826 (ne:QI (match_operator 1 "ix86_comparison_operator"
12827 [(reg 17) (const_int 0)])
12830 [(set (match_dup 0) (match_dup 1))]
12832 PUT_MODE (operands[1], QImode);
12836 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12837 (ne:QI (match_operator 1 "ix86_comparison_operator"
12838 [(reg 17) (const_int 0)])
12841 [(set (match_dup 0) (match_dup 1))]
12843 PUT_MODE (operands[1], QImode);
12847 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12848 (eq:QI (match_operator 1 "ix86_comparison_operator"
12849 [(reg 17) (const_int 0)])
12852 [(set (match_dup 0) (match_dup 1))]
12854 rtx new_op1 = copy_rtx (operands[1]);
12855 operands[1] = new_op1;
12856 PUT_MODE (new_op1, QImode);
12857 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12858 GET_MODE (XEXP (new_op1, 0))));
12860 /* Make sure that (a) the CCmode we have for the flags is strong
12861 enough for the reversed compare or (b) we have a valid FP compare. */
12862 if (! ix86_comparison_operator (new_op1, VOIDmode))
12867 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12868 (eq:QI (match_operator 1 "ix86_comparison_operator"
12869 [(reg 17) (const_int 0)])
12872 [(set (match_dup 0) (match_dup 1))]
12874 rtx new_op1 = copy_rtx (operands[1]);
12875 operands[1] = new_op1;
12876 PUT_MODE (new_op1, QImode);
12877 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
12878 GET_MODE (XEXP (new_op1, 0))));
12880 /* Make sure that (a) the CCmode we have for the flags is strong
12881 enough for the reversed compare or (b) we have a valid FP compare. */
12882 if (! ix86_comparison_operator (new_op1, VOIDmode))
12886 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12887 ;; subsequent logical operations are used to imitate conditional moves.
12888 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12889 ;; it directly. Further holding this value in pseudo register might bring
12890 ;; problem in implicit normalization in spill code.
12891 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12892 ;; instructions after reload by splitting the conditional move patterns.
12894 (define_insn "*sse_setccsf"
12895 [(set (match_operand:SF 0 "register_operand" "=x")
12896 (match_operator:SF 1 "sse_comparison_operator"
12897 [(match_operand:SF 2 "register_operand" "0")
12898 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12899 "TARGET_SSE && reload_completed"
12900 "cmp%D1ss\t{%3, %0|%0, %3}"
12901 [(set_attr "type" "ssecmp")
12902 (set_attr "mode" "SF")])
12904 (define_insn "*sse_setccdf"
12905 [(set (match_operand:DF 0 "register_operand" "=Y")
12906 (match_operator:DF 1 "sse_comparison_operator"
12907 [(match_operand:DF 2 "register_operand" "0")
12908 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12909 "TARGET_SSE2 && reload_completed"
12910 "cmp%D1sd\t{%3, %0|%0, %3}"
12911 [(set_attr "type" "ssecmp")
12912 (set_attr "mode" "DF")])
12914 ;; Basic conditional jump instructions.
12915 ;; We ignore the overflow flag for signed branch instructions.
12917 ;; For all bCOND expanders, also expand the compare or test insn that
12918 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
12920 (define_expand "beq"
12922 (if_then_else (match_dup 1)
12923 (label_ref (match_operand 0 "" ""))
12926 "ix86_expand_branch (EQ, operands[0]); DONE;")
12928 (define_expand "bne"
12930 (if_then_else (match_dup 1)
12931 (label_ref (match_operand 0 "" ""))
12934 "ix86_expand_branch (NE, operands[0]); DONE;")
12936 (define_expand "bgt"
12938 (if_then_else (match_dup 1)
12939 (label_ref (match_operand 0 "" ""))
12942 "ix86_expand_branch (GT, operands[0]); DONE;")
12944 (define_expand "bgtu"
12946 (if_then_else (match_dup 1)
12947 (label_ref (match_operand 0 "" ""))
12950 "ix86_expand_branch (GTU, operands[0]); DONE;")
12952 (define_expand "blt"
12954 (if_then_else (match_dup 1)
12955 (label_ref (match_operand 0 "" ""))
12958 "ix86_expand_branch (LT, operands[0]); DONE;")
12960 (define_expand "bltu"
12962 (if_then_else (match_dup 1)
12963 (label_ref (match_operand 0 "" ""))
12966 "ix86_expand_branch (LTU, operands[0]); DONE;")
12968 (define_expand "bge"
12970 (if_then_else (match_dup 1)
12971 (label_ref (match_operand 0 "" ""))
12974 "ix86_expand_branch (GE, operands[0]); DONE;")
12976 (define_expand "bgeu"
12978 (if_then_else (match_dup 1)
12979 (label_ref (match_operand 0 "" ""))
12982 "ix86_expand_branch (GEU, operands[0]); DONE;")
12984 (define_expand "ble"
12986 (if_then_else (match_dup 1)
12987 (label_ref (match_operand 0 "" ""))
12990 "ix86_expand_branch (LE, operands[0]); DONE;")
12992 (define_expand "bleu"
12994 (if_then_else (match_dup 1)
12995 (label_ref (match_operand 0 "" ""))
12998 "ix86_expand_branch (LEU, operands[0]); DONE;")
13000 (define_expand "bunordered"
13002 (if_then_else (match_dup 1)
13003 (label_ref (match_operand 0 "" ""))
13005 "TARGET_80387 || TARGET_SSE"
13006 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
13008 (define_expand "bordered"
13010 (if_then_else (match_dup 1)
13011 (label_ref (match_operand 0 "" ""))
13013 "TARGET_80387 || TARGET_SSE"
13014 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
13016 (define_expand "buneq"
13018 (if_then_else (match_dup 1)
13019 (label_ref (match_operand 0 "" ""))
13021 "TARGET_80387 || TARGET_SSE"
13022 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
13024 (define_expand "bunge"
13026 (if_then_else (match_dup 1)
13027 (label_ref (match_operand 0 "" ""))
13029 "TARGET_80387 || TARGET_SSE"
13030 "ix86_expand_branch (UNGE, operands[0]); DONE;")
13032 (define_expand "bungt"
13034 (if_then_else (match_dup 1)
13035 (label_ref (match_operand 0 "" ""))
13037 "TARGET_80387 || TARGET_SSE"
13038 "ix86_expand_branch (UNGT, operands[0]); DONE;")
13040 (define_expand "bunle"
13042 (if_then_else (match_dup 1)
13043 (label_ref (match_operand 0 "" ""))
13045 "TARGET_80387 || TARGET_SSE"
13046 "ix86_expand_branch (UNLE, operands[0]); DONE;")
13048 (define_expand "bunlt"
13050 (if_then_else (match_dup 1)
13051 (label_ref (match_operand 0 "" ""))
13053 "TARGET_80387 || TARGET_SSE"
13054 "ix86_expand_branch (UNLT, operands[0]); DONE;")
13056 (define_expand "bltgt"
13058 (if_then_else (match_dup 1)
13059 (label_ref (match_operand 0 "" ""))
13061 "TARGET_80387 || TARGET_SSE"
13062 "ix86_expand_branch (LTGT, operands[0]); DONE;")
13064 (define_insn "*jcc_1"
13066 (if_then_else (match_operator 1 "ix86_comparison_operator"
13067 [(reg 17) (const_int 0)])
13068 (label_ref (match_operand 0 "" ""))
13072 [(set_attr "type" "ibr")
13073 (set_attr "modrm" "0")
13074 (set (attr "length")
13075 (if_then_else (and (ge (minus (match_dup 0) (pc))
13077 (lt (minus (match_dup 0) (pc))
13082 (define_insn "*jcc_2"
13084 (if_then_else (match_operator 1 "ix86_comparison_operator"
13085 [(reg 17) (const_int 0)])
13087 (label_ref (match_operand 0 "" ""))))]
13090 [(set_attr "type" "ibr")
13091 (set_attr "modrm" "0")
13092 (set (attr "length")
13093 (if_then_else (and (ge (minus (match_dup 0) (pc))
13095 (lt (minus (match_dup 0) (pc))
13100 ;; In general it is not safe to assume too much about CCmode registers,
13101 ;; so simplify-rtx stops when it sees a second one. Under certain
13102 ;; conditions this is safe on x86, so help combine not create
13110 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
13111 [(reg 17) (const_int 0)])
13113 (label_ref (match_operand 1 "" ""))
13117 (if_then_else (match_dup 0)
13118 (label_ref (match_dup 1))
13121 PUT_MODE (operands[0], VOIDmode);
13126 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
13127 [(reg 17) (const_int 0)])
13129 (label_ref (match_operand 1 "" ""))
13133 (if_then_else (match_dup 0)
13134 (label_ref (match_dup 1))
13137 rtx new_op0 = copy_rtx (operands[0]);
13138 operands[0] = new_op0;
13139 PUT_MODE (new_op0, VOIDmode);
13140 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
13141 GET_MODE (XEXP (new_op0, 0))));
13143 /* Make sure that (a) the CCmode we have for the flags is strong
13144 enough for the reversed compare or (b) we have a valid FP compare. */
13145 if (! ix86_comparison_operator (new_op0, VOIDmode))
13149 ;; Define combination compare-and-branch fp compare instructions to use
13150 ;; during early optimization. Splitting the operation apart early makes
13151 ;; for bad code when we want to reverse the operation.
13153 (define_insn "*fp_jcc_1"
13155 (if_then_else (match_operator 0 "comparison_operator"
13156 [(match_operand 1 "register_operand" "f")
13157 (match_operand 2 "register_operand" "f")])
13158 (label_ref (match_operand 3 "" ""))
13160 (clobber (reg:CCFP 18))
13161 (clobber (reg:CCFP 17))]
13162 "TARGET_CMOVE && TARGET_80387
13163 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13164 && FLOAT_MODE_P (GET_MODE (operands[1]))
13165 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13166 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13169 (define_insn "*fp_jcc_1_sse"
13171 (if_then_else (match_operator 0 "comparison_operator"
13172 [(match_operand 1 "register_operand" "f#x,x#f")
13173 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13174 (label_ref (match_operand 3 "" ""))
13176 (clobber (reg:CCFP 18))
13177 (clobber (reg:CCFP 17))]
13179 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13180 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13181 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13184 (define_insn "*fp_jcc_1_sse_only"
13186 (if_then_else (match_operator 0 "comparison_operator"
13187 [(match_operand 1 "register_operand" "x")
13188 (match_operand 2 "nonimmediate_operand" "xm")])
13189 (label_ref (match_operand 3 "" ""))
13191 (clobber (reg:CCFP 18))
13192 (clobber (reg:CCFP 17))]
13193 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13194 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13195 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13198 (define_insn "*fp_jcc_2"
13200 (if_then_else (match_operator 0 "comparison_operator"
13201 [(match_operand 1 "register_operand" "f")
13202 (match_operand 2 "register_operand" "f")])
13204 (label_ref (match_operand 3 "" ""))))
13205 (clobber (reg:CCFP 18))
13206 (clobber (reg:CCFP 17))]
13207 "TARGET_CMOVE && TARGET_80387
13208 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13209 && FLOAT_MODE_P (GET_MODE (operands[1]))
13210 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13211 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13214 (define_insn "*fp_jcc_2_sse"
13216 (if_then_else (match_operator 0 "comparison_operator"
13217 [(match_operand 1 "register_operand" "f#x,x#f")
13218 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13220 (label_ref (match_operand 3 "" ""))))
13221 (clobber (reg:CCFP 18))
13222 (clobber (reg:CCFP 17))]
13224 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13225 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13226 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13229 (define_insn "*fp_jcc_2_sse_only"
13231 (if_then_else (match_operator 0 "comparison_operator"
13232 [(match_operand 1 "register_operand" "x")
13233 (match_operand 2 "nonimmediate_operand" "xm")])
13235 (label_ref (match_operand 3 "" ""))))
13236 (clobber (reg:CCFP 18))
13237 (clobber (reg:CCFP 17))]
13238 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13239 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13240 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13243 (define_insn "*fp_jcc_3"
13245 (if_then_else (match_operator 0 "comparison_operator"
13246 [(match_operand 1 "register_operand" "f")
13247 (match_operand 2 "nonimmediate_operand" "fm")])
13248 (label_ref (match_operand 3 "" ""))
13250 (clobber (reg:CCFP 18))
13251 (clobber (reg:CCFP 17))
13252 (clobber (match_scratch:HI 4 "=a"))]
13254 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13255 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13256 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13257 && SELECT_CC_MODE (GET_CODE (operands[0]),
13258 operands[1], operands[2]) == CCFPmode
13259 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13262 (define_insn "*fp_jcc_4"
13264 (if_then_else (match_operator 0 "comparison_operator"
13265 [(match_operand 1 "register_operand" "f")
13266 (match_operand 2 "nonimmediate_operand" "fm")])
13268 (label_ref (match_operand 3 "" ""))))
13269 (clobber (reg:CCFP 18))
13270 (clobber (reg:CCFP 17))
13271 (clobber (match_scratch:HI 4 "=a"))]
13273 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13274 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13275 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13276 && SELECT_CC_MODE (GET_CODE (operands[0]),
13277 operands[1], operands[2]) == CCFPmode
13278 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13281 (define_insn "*fp_jcc_5"
13283 (if_then_else (match_operator 0 "comparison_operator"
13284 [(match_operand 1 "register_operand" "f")
13285 (match_operand 2 "register_operand" "f")])
13286 (label_ref (match_operand 3 "" ""))
13288 (clobber (reg:CCFP 18))
13289 (clobber (reg:CCFP 17))
13290 (clobber (match_scratch:HI 4 "=a"))]
13292 && FLOAT_MODE_P (GET_MODE (operands[1]))
13293 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13294 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13297 (define_insn "*fp_jcc_6"
13299 (if_then_else (match_operator 0 "comparison_operator"
13300 [(match_operand 1 "register_operand" "f")
13301 (match_operand 2 "register_operand" "f")])
13303 (label_ref (match_operand 3 "" ""))))
13304 (clobber (reg:CCFP 18))
13305 (clobber (reg:CCFP 17))
13306 (clobber (match_scratch:HI 4 "=a"))]
13308 && FLOAT_MODE_P (GET_MODE (operands[1]))
13309 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13310 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13315 (if_then_else (match_operator 0 "comparison_operator"
13316 [(match_operand 1 "register_operand" "")
13317 (match_operand 2 "nonimmediate_operand" "")])
13318 (match_operand 3 "" "")
13319 (match_operand 4 "" "")))
13320 (clobber (reg:CCFP 18))
13321 (clobber (reg:CCFP 17))]
13325 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13326 operands[3], operands[4], NULL_RTX);
13332 (if_then_else (match_operator 0 "comparison_operator"
13333 [(match_operand 1 "register_operand" "")
13334 (match_operand 2 "nonimmediate_operand" "")])
13335 (match_operand 3 "" "")
13336 (match_operand 4 "" "")))
13337 (clobber (reg:CCFP 18))
13338 (clobber (reg:CCFP 17))
13339 (clobber (match_scratch:HI 5 "=a"))]
13342 (if_then_else (match_dup 6)
13346 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13347 operands[3], operands[4], operands[5]);
13351 ;; Unconditional and other jump instructions
13353 (define_insn "jump"
13355 (label_ref (match_operand 0 "" "")))]
13358 [(set_attr "type" "ibr")
13359 (set (attr "length")
13360 (if_then_else (and (ge (minus (match_dup 0) (pc))
13362 (lt (minus (match_dup 0) (pc))
13366 (set_attr "modrm" "0")])
13368 (define_expand "indirect_jump"
13369 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13373 (define_insn "*indirect_jump"
13374 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13377 [(set_attr "type" "ibr")
13378 (set_attr "length_immediate" "0")])
13380 (define_insn "*indirect_jump_rtx64"
13381 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13384 [(set_attr "type" "ibr")
13385 (set_attr "length_immediate" "0")])
13387 (define_expand "tablejump"
13388 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13389 (use (label_ref (match_operand 1 "" "")))])]
13392 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13393 relative. Convert the relative address to an absolute address. */
13397 enum rtx_code code;
13403 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13405 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13409 op1 = pic_offset_table_rtx;
13414 op0 = pic_offset_table_rtx;
13418 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13423 (define_insn "*tablejump_1"
13424 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13425 (use (label_ref (match_operand 1 "" "")))]
13428 [(set_attr "type" "ibr")
13429 (set_attr "length_immediate" "0")])
13431 (define_insn "*tablejump_1_rtx64"
13432 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13433 (use (label_ref (match_operand 1 "" "")))]
13436 [(set_attr "type" "ibr")
13437 (set_attr "length_immediate" "0")])
13439 ;; Loop instruction
13441 ;; This is all complicated by the fact that since this is a jump insn
13442 ;; we must handle our own reloads.
13444 (define_expand "doloop_end"
13445 [(use (match_operand 0 "" "")) ; loop pseudo
13446 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13447 (use (match_operand 2 "" "")) ; max iterations
13448 (use (match_operand 3 "" "")) ; loop level
13449 (use (match_operand 4 "" ""))] ; label
13450 "!TARGET_64BIT && TARGET_USE_LOOP"
13453 /* Only use cloop on innermost loops. */
13454 if (INTVAL (operands[3]) > 1)
13456 if (GET_MODE (operands[0]) != SImode)
13458 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13463 (define_insn "doloop_end_internal"
13465 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13467 (label_ref (match_operand 0 "" ""))
13469 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13470 (plus:SI (match_dup 1)
13472 (clobber (match_scratch:SI 3 "=X,X,r"))
13473 (clobber (reg:CC 17))]
13474 "!TARGET_64BIT && TARGET_USE_LOOP"
13476 if (which_alternative != 0)
13478 if (get_attr_length (insn) == 2)
13479 return "%+loop\t%l0";
13481 return "dec{l}\t%1\;%+jne\t%l0";
13483 [(set_attr "ppro_uops" "many")
13484 (set (attr "length")
13485 (if_then_else (and (eq_attr "alternative" "0")
13486 (and (ge (minus (match_dup 0) (pc))
13488 (lt (minus (match_dup 0) (pc))
13492 ;; We don't know the type before shorten branches. Optimistically expect
13493 ;; the loop instruction to match.
13494 (set (attr "type") (const_string "ibr"))])
13498 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13500 (match_operand 0 "" "")
13503 (plus:SI (match_dup 1)
13505 (clobber (match_scratch:SI 2 ""))
13506 (clobber (reg:CC 17))]
13507 "!TARGET_64BIT && TARGET_USE_LOOP
13508 && reload_completed
13509 && REGNO (operands[1]) != 2"
13510 [(parallel [(set (reg:CCZ 17)
13511 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13513 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13514 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13521 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13523 (match_operand 0 "" "")
13525 (set (match_operand:SI 2 "nonimmediate_operand" "")
13526 (plus:SI (match_dup 1)
13528 (clobber (match_scratch:SI 3 ""))
13529 (clobber (reg:CC 17))]
13530 "!TARGET_64BIT && TARGET_USE_LOOP
13531 && reload_completed
13532 && (! REG_P (operands[2])
13533 || ! rtx_equal_p (operands[1], operands[2]))"
13534 [(set (match_dup 3) (match_dup 1))
13535 (parallel [(set (reg:CCZ 17)
13536 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13538 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13539 (set (match_dup 2) (match_dup 3))
13540 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13545 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13548 [(set (reg 17) (match_operand 0 "" ""))
13549 (set (match_operand:QI 1 "register_operand" "")
13550 (match_operator:QI 2 "ix86_comparison_operator"
13551 [(reg 17) (const_int 0)]))
13552 (set (match_operand 3 "q_regs_operand" "")
13553 (zero_extend (match_dup 1)))]
13554 "(peep2_reg_dead_p (3, operands[1])
13555 || operands_match_p (operands[1], operands[3]))
13556 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13557 [(set (match_dup 4) (match_dup 0))
13558 (set (strict_low_part (match_dup 5))
13561 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13562 operands[5] = gen_lowpart (QImode, operands[3]);
13563 ix86_expand_clear (operands[3]);
13566 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13569 [(set (reg 17) (match_operand 0 "" ""))
13570 (set (match_operand:QI 1 "register_operand" "")
13571 (match_operator:QI 2 "ix86_comparison_operator"
13572 [(reg 17) (const_int 0)]))
13573 (parallel [(set (match_operand 3 "q_regs_operand" "")
13574 (zero_extend (match_dup 1)))
13575 (clobber (reg:CC 17))])]
13576 "(peep2_reg_dead_p (3, operands[1])
13577 || operands_match_p (operands[1], operands[3]))
13578 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13579 [(set (match_dup 4) (match_dup 0))
13580 (set (strict_low_part (match_dup 5))
13583 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13584 operands[5] = gen_lowpart (QImode, operands[3]);
13585 ix86_expand_clear (operands[3]);
13588 ;; Call instructions.
13590 ;; The predicates normally associated with named expanders are not properly
13591 ;; checked for calls. This is a bug in the generic code, but it isn't that
13592 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13594 ;; Call subroutine returning no value.
13596 (define_expand "call_pop"
13597 [(parallel [(call (match_operand:QI 0 "" "")
13598 (match_operand:SI 1 "" ""))
13600 (plus:SI (reg:SI 7)
13601 (match_operand:SI 3 "" "")))])]
13604 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
13608 (define_insn "*call_pop_0"
13609 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13610 (match_operand:SI 1 "" ""))
13611 (set (reg:SI 7) (plus:SI (reg:SI 7)
13612 (match_operand:SI 2 "immediate_operand" "")))]
13615 if (SIBLING_CALL_P (insn))
13618 return "call\t%P0";
13620 [(set_attr "type" "call")])
13622 (define_insn "*call_pop_1"
13623 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13624 (match_operand:SI 1 "" ""))
13625 (set (reg:SI 7) (plus:SI (reg:SI 7)
13626 (match_operand:SI 2 "immediate_operand" "i")))]
13629 if (constant_call_address_operand (operands[0], Pmode))
13631 if (SIBLING_CALL_P (insn))
13634 return "call\t%P0";
13636 if (SIBLING_CALL_P (insn))
13639 return "call\t%A0";
13641 [(set_attr "type" "call")])
13643 (define_expand "call"
13644 [(call (match_operand:QI 0 "" "")
13645 (match_operand 1 "" ""))
13646 (use (match_operand 2 "" ""))]
13649 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
13653 (define_expand "sibcall"
13654 [(call (match_operand:QI 0 "" "")
13655 (match_operand 1 "" ""))
13656 (use (match_operand 2 "" ""))]
13659 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
13663 (define_insn "*call_0"
13664 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13665 (match_operand 1 "" ""))]
13668 if (SIBLING_CALL_P (insn))
13671 return "call\t%P0";
13673 [(set_attr "type" "call")])
13675 (define_insn "*call_1"
13676 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13677 (match_operand 1 "" ""))]
13678 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
13680 if (constant_call_address_operand (operands[0], QImode))
13681 return "call\t%P0";
13682 return "call\t%A0";
13684 [(set_attr "type" "call")])
13686 (define_insn "*sibcall_1"
13687 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
13688 (match_operand 1 "" ""))]
13689 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
13691 if (constant_call_address_operand (operands[0], QImode))
13695 [(set_attr "type" "call")])
13697 (define_insn "*call_1_rex64"
13698 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13699 (match_operand 1 "" ""))]
13700 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
13702 if (constant_call_address_operand (operands[0], QImode))
13703 return "call\t%P0";
13704 return "call\t%A0";
13706 [(set_attr "type" "call")])
13708 (define_insn "*sibcall_1_rex64"
13709 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
13710 (match_operand 1 "" ""))]
13711 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13713 [(set_attr "type" "call")])
13715 (define_insn "*sibcall_1_rex64_v"
13716 [(call (mem:QI (reg:DI 40))
13717 (match_operand 0 "" ""))]
13718 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13720 [(set_attr "type" "call")])
13723 ;; Call subroutine, returning value in operand 0
13725 (define_expand "call_value_pop"
13726 [(parallel [(set (match_operand 0 "" "")
13727 (call (match_operand:QI 1 "" "")
13728 (match_operand:SI 2 "" "")))
13730 (plus:SI (reg:SI 7)
13731 (match_operand:SI 4 "" "")))])]
13734 ix86_expand_call (operands[0], operands[1], operands[2],
13735 operands[3], operands[4], 0);
13739 (define_expand "call_value"
13740 [(set (match_operand 0 "" "")
13741 (call (match_operand:QI 1 "" "")
13742 (match_operand:SI 2 "" "")))
13743 (use (match_operand:SI 3 "" ""))]
13744 ;; Operand 2 not used on the i386.
13747 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
13751 (define_expand "sibcall_value"
13752 [(set (match_operand 0 "" "")
13753 (call (match_operand:QI 1 "" "")
13754 (match_operand:SI 2 "" "")))
13755 (use (match_operand:SI 3 "" ""))]
13756 ;; Operand 2 not used on the i386.
13759 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
13763 ;; Call subroutine returning any type.
13765 (define_expand "untyped_call"
13766 [(parallel [(call (match_operand 0 "" "")
13768 (match_operand 1 "" "")
13769 (match_operand 2 "" "")])]
13774 /* In order to give reg-stack an easier job in validating two
13775 coprocessor registers as containing a possible return value,
13776 simply pretend the untyped call returns a complex long double
13779 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13780 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13781 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13784 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13786 rtx set = XVECEXP (operands[2], 0, i);
13787 emit_move_insn (SET_DEST (set), SET_SRC (set));
13790 /* The optimizer does not know that the call sets the function value
13791 registers we stored in the result block. We avoid problems by
13792 claiming that all hard registers are used and clobbered at this
13794 emit_insn (gen_blockage (const0_rtx));
13799 ;; Prologue and epilogue instructions
13801 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13802 ;; all of memory. This blocks insns from being moved across this point.
13804 (define_insn "blockage"
13805 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13808 [(set_attr "length" "0")])
13810 ;; Insn emitted into the body of a function to return from a function.
13811 ;; This is only done if the function's epilogue is known to be simple.
13812 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13814 (define_expand "return"
13816 "ix86_can_use_return_insn_p ()"
13818 if (current_function_pops_args)
13820 rtx popc = GEN_INT (current_function_pops_args);
13821 emit_jump_insn (gen_return_pop_internal (popc));
13826 (define_insn "return_internal"
13830 [(set_attr "length" "1")
13831 (set_attr "length_immediate" "0")
13832 (set_attr "modrm" "0")])
13834 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
13835 ;; instruction Athlon and K8 have.
13837 (define_insn "return_internal_long"
13839 (unspec [(const_int 0)] UNSPEC_REP)]
13842 [(set_attr "length" "1")
13843 (set_attr "length_immediate" "0")
13844 (set_attr "prefix_rep" "1")
13845 (set_attr "modrm" "0")])
13847 (define_insn "return_pop_internal"
13849 (use (match_operand:SI 0 "const_int_operand" ""))]
13852 [(set_attr "length" "3")
13853 (set_attr "length_immediate" "2")
13854 (set_attr "modrm" "0")])
13856 (define_insn "return_indirect_internal"
13858 (use (match_operand:SI 0 "register_operand" "r"))]
13861 [(set_attr "type" "ibr")
13862 (set_attr "length_immediate" "0")])
13868 [(set_attr "length" "1")
13869 (set_attr "length_immediate" "0")
13870 (set_attr "modrm" "0")
13871 (set_attr "ppro_uops" "one")])
13873 ;; Align to 16-byte boundary, max skip in op0. Used to avoid
13874 ;; branch prediction penalty for the third jump in a 16-byte
13877 (define_insn "align"
13878 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
13881 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
13882 ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
13884 /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
13885 The align insn is used to avoid 3 jump instructions in the row to improve
13886 branch prediction and the benefits hardly outweight the cost of extra 8
13887 nops on the average inserted by full alignment pseudo operation. */
13891 [(set_attr "length" "16")])
13893 (define_expand "prologue"
13896 "ix86_expand_prologue (); DONE;")
13898 (define_insn "set_got"
13899 [(set (match_operand:SI 0 "register_operand" "=r")
13900 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13901 (clobber (reg:CC 17))]
13903 { return output_set_got (operands[0]); }
13904 [(set_attr "type" "multi")
13905 (set_attr "length" "12")])
13907 (define_expand "epilogue"
13910 "ix86_expand_epilogue (1); DONE;")
13912 (define_expand "sibcall_epilogue"
13915 "ix86_expand_epilogue (0); DONE;")
13917 (define_expand "eh_return"
13918 [(use (match_operand 0 "register_operand" ""))]
13921 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
13923 /* Tricky bit: we write the address of the handler to which we will
13924 be returning into someone else's stack frame, one word below the
13925 stack address we wish to restore. */
13926 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13927 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13928 tmp = gen_rtx_MEM (Pmode, tmp);
13929 emit_move_insn (tmp, ra);
13931 if (Pmode == SImode)
13932 emit_insn (gen_eh_return_si (sa));
13934 emit_insn (gen_eh_return_di (sa));
13939 (define_insn_and_split "eh_return_si"
13940 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
13941 UNSPECV_EH_RETURN)]
13946 "ix86_expand_epilogue (2); DONE;")
13948 (define_insn_and_split "eh_return_di"
13949 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
13950 UNSPECV_EH_RETURN)]
13955 "ix86_expand_epilogue (2); DONE;")
13957 (define_insn "leave"
13958 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
13959 (set (reg:SI 6) (mem:SI (reg:SI 6)))
13960 (clobber (mem:BLK (scratch)))]
13963 [(set_attr "type" "leave")])
13965 (define_insn "leave_rex64"
13966 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
13967 (set (reg:DI 6) (mem:DI (reg:DI 6)))
13968 (clobber (mem:BLK (scratch)))]
13971 [(set_attr "type" "leave")])
13973 (define_expand "ffssi2"
13975 [(set (match_operand:SI 0 "register_operand" "")
13976 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
13977 (clobber (match_scratch:SI 2 ""))
13978 (clobber (reg:CC 17))])]
13982 (define_insn_and_split "*ffs_cmove"
13983 [(set (match_operand:SI 0 "register_operand" "=r")
13984 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13985 (clobber (match_scratch:SI 2 "=&r"))
13986 (clobber (reg:CC 17))]
13989 "&& reload_completed"
13990 [(set (match_dup 2) (const_int -1))
13991 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
13992 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13993 (set (match_dup 0) (if_then_else:SI
13994 (eq (reg:CCZ 17) (const_int 0))
13997 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
13998 (clobber (reg:CC 17))])]
14001 (define_insn_and_split "*ffs_no_cmove"
14002 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
14003 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14004 (clobber (match_scratch:SI 2 "=&q"))
14005 (clobber (reg:CC 17))]
14009 [(parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14010 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14011 (set (strict_low_part (match_dup 3))
14012 (eq:QI (reg:CCZ 17) (const_int 0)))
14013 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
14014 (clobber (reg:CC 17))])
14015 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
14016 (clobber (reg:CC 17))])
14017 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14018 (clobber (reg:CC 17))])]
14020 operands[3] = gen_lowpart (QImode, operands[2]);
14021 ix86_expand_clear (operands[2]);
14024 (define_insn "*ffssi_1"
14026 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
14028 (set (match_operand:SI 0 "register_operand" "=r")
14029 (ctz:SI (match_dup 1)))]
14031 "bsf{l}\t{%1, %0|%0, %1}"
14032 [(set_attr "prefix_0f" "1")
14033 (set_attr "ppro_uops" "few")])
14035 (define_insn "ctzsi2"
14036 [(set (match_operand:SI 0 "register_operand" "=r")
14037 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14038 (clobber (reg:CC 17))]
14040 "bsf{l}\t{%1, %0|%0, %1}"
14041 [(set_attr "prefix_0f" "1")
14042 (set_attr "ppro_uops" "few")])
14044 (define_expand "clzsi2"
14046 [(set (match_operand:SI 0 "register_operand" "")
14047 (minus:SI (const_int 31)
14048 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
14049 (clobber (reg:CC 17))])
14051 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
14052 (clobber (reg:CC 17))])]
14056 (define_insn "*bsr"
14057 [(set (match_operand:SI 0 "register_operand" "=r")
14058 (minus:SI (const_int 31)
14059 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
14060 (clobber (reg:CC 17))]
14062 "bsr{l}\t{%1, %0|%0, %1}"
14063 [(set_attr "prefix_0f" "1")
14064 (set_attr "ppro_uops" "few")])
14066 ;; Thread-local storage patterns for ELF.
14068 ;; Note that these code sequences must appear exactly as shown
14069 ;; in order to allow linker relaxation.
14071 (define_insn "*tls_global_dynamic_32_gnu"
14072 [(set (match_operand:SI 0 "register_operand" "=a")
14073 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14074 (match_operand:SI 2 "tls_symbolic_operand" "")
14075 (match_operand:SI 3 "call_insn_operand" "")]
14077 (clobber (match_scratch:SI 4 "=d"))
14078 (clobber (match_scratch:SI 5 "=c"))
14079 (clobber (reg:CC 17))]
14080 "!TARGET_64BIT && TARGET_GNU_TLS"
14081 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
14082 [(set_attr "type" "multi")
14083 (set_attr "length" "12")])
14085 (define_insn "*tls_global_dynamic_32_sun"
14086 [(set (match_operand:SI 0 "register_operand" "=a")
14087 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14088 (match_operand:SI 2 "tls_symbolic_operand" "")
14089 (match_operand:SI 3 "call_insn_operand" "")]
14091 (clobber (match_scratch:SI 4 "=d"))
14092 (clobber (match_scratch:SI 5 "=c"))
14093 (clobber (reg:CC 17))]
14094 "!TARGET_64BIT && TARGET_SUN_TLS"
14095 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
14096 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
14097 [(set_attr "type" "multi")
14098 (set_attr "length" "14")])
14100 (define_expand "tls_global_dynamic_32"
14101 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14104 (match_operand:SI 1 "tls_symbolic_operand" "")
14107 (clobber (match_scratch:SI 4 ""))
14108 (clobber (match_scratch:SI 5 ""))
14109 (clobber (reg:CC 17))])]
14113 operands[2] = pic_offset_table_rtx;
14116 operands[2] = gen_reg_rtx (Pmode);
14117 emit_insn (gen_set_got (operands[2]));
14119 operands[3] = ix86_tls_get_addr ();
14122 (define_insn "*tls_global_dynamic_64"
14123 [(set (match_operand:DI 0 "register_operand" "=a")
14124 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
14125 (match_operand:DI 3 "" "")))
14126 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14129 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
14130 [(set_attr "type" "multi")
14131 (set_attr "length" "16")])
14133 (define_expand "tls_global_dynamic_64"
14134 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14135 (call (mem:QI (match_dup 2)) (const_int 0)))
14136 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14140 operands[2] = ix86_tls_get_addr ();
14143 (define_insn "*tls_local_dynamic_base_32_gnu"
14144 [(set (match_operand:SI 0 "register_operand" "=a")
14145 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14146 (match_operand:SI 2 "call_insn_operand" "")]
14147 UNSPEC_TLS_LD_BASE))
14148 (clobber (match_scratch:SI 3 "=d"))
14149 (clobber (match_scratch:SI 4 "=c"))
14150 (clobber (reg:CC 17))]
14151 "!TARGET_64BIT && TARGET_GNU_TLS"
14152 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
14153 [(set_attr "type" "multi")
14154 (set_attr "length" "11")])
14156 (define_insn "*tls_local_dynamic_base_32_sun"
14157 [(set (match_operand:SI 0 "register_operand" "=a")
14158 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14159 (match_operand:SI 2 "call_insn_operand" "")]
14160 UNSPEC_TLS_LD_BASE))
14161 (clobber (match_scratch:SI 3 "=d"))
14162 (clobber (match_scratch:SI 4 "=c"))
14163 (clobber (reg:CC 17))]
14164 "!TARGET_64BIT && TARGET_SUN_TLS"
14165 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
14166 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
14167 [(set_attr "type" "multi")
14168 (set_attr "length" "13")])
14170 (define_expand "tls_local_dynamic_base_32"
14171 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14172 (unspec:SI [(match_dup 1) (match_dup 2)]
14173 UNSPEC_TLS_LD_BASE))
14174 (clobber (match_scratch:SI 3 ""))
14175 (clobber (match_scratch:SI 4 ""))
14176 (clobber (reg:CC 17))])]
14180 operands[1] = pic_offset_table_rtx;
14183 operands[1] = gen_reg_rtx (Pmode);
14184 emit_insn (gen_set_got (operands[1]));
14186 operands[2] = ix86_tls_get_addr ();
14189 (define_insn "*tls_local_dynamic_base_64"
14190 [(set (match_operand:DI 0 "register_operand" "=a")
14191 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14192 (match_operand:DI 2 "" "")))
14193 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14195 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14196 [(set_attr "type" "multi")
14197 (set_attr "length" "12")])
14199 (define_expand "tls_local_dynamic_base_64"
14200 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14201 (call (mem:QI (match_dup 1)) (const_int 0)))
14202 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14205 operands[1] = ix86_tls_get_addr ();
14208 ;; Local dynamic of a single variable is a lose. Show combine how
14209 ;; to convert that back to global dynamic.
14211 (define_insn_and_split "*tls_local_dynamic_32_once"
14212 [(set (match_operand:SI 0 "register_operand" "=a")
14213 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14214 (match_operand:SI 2 "call_insn_operand" "")]
14215 UNSPEC_TLS_LD_BASE)
14216 (const:SI (unspec:SI
14217 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14219 (clobber (match_scratch:SI 4 "=d"))
14220 (clobber (match_scratch:SI 5 "=c"))
14221 (clobber (reg:CC 17))]
14225 [(parallel [(set (match_dup 0)
14226 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14228 (clobber (match_dup 4))
14229 (clobber (match_dup 5))
14230 (clobber (reg:CC 17))])]
14233 ;; Load and add the thread base pointer from %gs:0.
14235 (define_insn "*load_tp_si"
14236 [(set (match_operand:SI 0 "register_operand" "=r")
14237 (unspec:SI [(const_int 0)] UNSPEC_TP))]
14239 "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14240 [(set_attr "type" "imov")
14241 (set_attr "modrm" "0")
14242 (set_attr "length" "7")
14243 (set_attr "memory" "load")
14244 (set_attr "imm_disp" "false")])
14246 (define_insn "*add_tp_si"
14247 [(set (match_operand:SI 0 "register_operand" "=r")
14248 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
14249 (match_operand:SI 1 "register_operand" "0")))
14250 (clobber (reg:CC 17))]
14252 "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14253 [(set_attr "type" "alu")
14254 (set_attr "modrm" "0")
14255 (set_attr "length" "7")
14256 (set_attr "memory" "load")
14257 (set_attr "imm_disp" "false")])
14259 (define_insn "*load_tp_di"
14260 [(set (match_operand:DI 0 "register_operand" "=r")
14261 (unspec:DI [(const_int 0)] UNSPEC_TP))]
14263 "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14264 [(set_attr "type" "imov")
14265 (set_attr "modrm" "0")
14266 (set_attr "length" "7")
14267 (set_attr "memory" "load")
14268 (set_attr "imm_disp" "false")])
14270 (define_insn "*add_tp_di"
14271 [(set (match_operand:DI 0 "register_operand" "=r")
14272 (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
14273 (match_operand:DI 1 "register_operand" "0")))
14274 (clobber (reg:CC 17))]
14276 "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14277 [(set_attr "type" "alu")
14278 (set_attr "modrm" "0")
14279 (set_attr "length" "7")
14280 (set_attr "memory" "load")
14281 (set_attr "imm_disp" "false")])
14283 ;; These patterns match the binary 387 instructions for addM3, subM3,
14284 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14285 ;; SFmode. The first is the normal insn, the second the same insn but
14286 ;; with one operand a conversion, and the third the same insn but with
14287 ;; the other operand a conversion. The conversion may be SFmode or
14288 ;; SImode if the target mode DFmode, but only SImode if the target mode
14291 ;; Gcc is slightly more smart about handling normal two address instructions
14292 ;; so use special patterns for add and mull.
14293 (define_insn "*fop_sf_comm_nosse"
14294 [(set (match_operand:SF 0 "register_operand" "=f")
14295 (match_operator:SF 3 "binary_fp_operator"
14296 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14297 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14298 "TARGET_80387 && !TARGET_SSE_MATH
14299 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14300 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14301 "* return output_387_binary_op (insn, operands);"
14302 [(set (attr "type")
14303 (if_then_else (match_operand:SF 3 "mult_operator" "")
14304 (const_string "fmul")
14305 (const_string "fop")))
14306 (set_attr "mode" "SF")])
14308 (define_insn "*fop_sf_comm"
14309 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14310 (match_operator:SF 3 "binary_fp_operator"
14311 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14312 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14313 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14314 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14315 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14316 "* return output_387_binary_op (insn, operands);"
14317 [(set (attr "type")
14318 (if_then_else (eq_attr "alternative" "1")
14319 (if_then_else (match_operand:SF 3 "mult_operator" "")
14320 (const_string "ssemul")
14321 (const_string "sseadd"))
14322 (if_then_else (match_operand:SF 3 "mult_operator" "")
14323 (const_string "fmul")
14324 (const_string "fop"))))
14325 (set_attr "mode" "SF")])
14327 (define_insn "*fop_sf_comm_sse"
14328 [(set (match_operand:SF 0 "register_operand" "=x")
14329 (match_operator:SF 3 "binary_fp_operator"
14330 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14331 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14332 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14333 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14334 "* return output_387_binary_op (insn, operands);"
14335 [(set (attr "type")
14336 (if_then_else (match_operand:SF 3 "mult_operator" "")
14337 (const_string "ssemul")
14338 (const_string "sseadd")))
14339 (set_attr "mode" "SF")])
14341 (define_insn "*fop_df_comm_nosse"
14342 [(set (match_operand:DF 0 "register_operand" "=f")
14343 (match_operator:DF 3 "binary_fp_operator"
14344 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14345 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14346 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14347 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14348 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14349 "* return output_387_binary_op (insn, operands);"
14350 [(set (attr "type")
14351 (if_then_else (match_operand:SF 3 "mult_operator" "")
14352 (const_string "fmul")
14353 (const_string "fop")))
14354 (set_attr "mode" "DF")])
14356 (define_insn "*fop_df_comm"
14357 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14358 (match_operator:DF 3 "binary_fp_operator"
14359 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14360 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14361 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14362 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14363 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14364 "* return output_387_binary_op (insn, operands);"
14365 [(set (attr "type")
14366 (if_then_else (eq_attr "alternative" "1")
14367 (if_then_else (match_operand:SF 3 "mult_operator" "")
14368 (const_string "ssemul")
14369 (const_string "sseadd"))
14370 (if_then_else (match_operand:SF 3 "mult_operator" "")
14371 (const_string "fmul")
14372 (const_string "fop"))))
14373 (set_attr "mode" "DF")])
14375 (define_insn "*fop_df_comm_sse"
14376 [(set (match_operand:DF 0 "register_operand" "=Y")
14377 (match_operator:DF 3 "binary_fp_operator"
14378 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14379 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14380 "TARGET_SSE2 && TARGET_SSE_MATH
14381 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14382 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14383 "* return output_387_binary_op (insn, operands);"
14384 [(set (attr "type")
14385 (if_then_else (match_operand:SF 3 "mult_operator" "")
14386 (const_string "ssemul")
14387 (const_string "sseadd")))
14388 (set_attr "mode" "DF")])
14390 (define_insn "*fop_xf_comm"
14391 [(set (match_operand:XF 0 "register_operand" "=f")
14392 (match_operator:XF 3 "binary_fp_operator"
14393 [(match_operand:XF 1 "register_operand" "%0")
14394 (match_operand:XF 2 "register_operand" "f")]))]
14396 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14397 "* return output_387_binary_op (insn, operands);"
14398 [(set (attr "type")
14399 (if_then_else (match_operand:XF 3 "mult_operator" "")
14400 (const_string "fmul")
14401 (const_string "fop")))
14402 (set_attr "mode" "XF")])
14404 (define_insn "*fop_sf_1_nosse"
14405 [(set (match_operand:SF 0 "register_operand" "=f,f")
14406 (match_operator:SF 3 "binary_fp_operator"
14407 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14408 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14409 "TARGET_80387 && !TARGET_SSE_MATH
14410 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14411 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14412 "* return output_387_binary_op (insn, operands);"
14413 [(set (attr "type")
14414 (cond [(match_operand:SF 3 "mult_operator" "")
14415 (const_string "fmul")
14416 (match_operand:SF 3 "div_operator" "")
14417 (const_string "fdiv")
14419 (const_string "fop")))
14420 (set_attr "mode" "SF")])
14422 (define_insn "*fop_sf_1"
14423 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14424 (match_operator:SF 3 "binary_fp_operator"
14425 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14426 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14427 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14428 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14429 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14430 "* return output_387_binary_op (insn, operands);"
14431 [(set (attr "type")
14432 (cond [(and (eq_attr "alternative" "2")
14433 (match_operand:SF 3 "mult_operator" ""))
14434 (const_string "ssemul")
14435 (and (eq_attr "alternative" "2")
14436 (match_operand:SF 3 "div_operator" ""))
14437 (const_string "ssediv")
14438 (eq_attr "alternative" "2")
14439 (const_string "sseadd")
14440 (match_operand:SF 3 "mult_operator" "")
14441 (const_string "fmul")
14442 (match_operand:SF 3 "div_operator" "")
14443 (const_string "fdiv")
14445 (const_string "fop")))
14446 (set_attr "mode" "SF")])
14448 (define_insn "*fop_sf_1_sse"
14449 [(set (match_operand:SF 0 "register_operand" "=x")
14450 (match_operator:SF 3 "binary_fp_operator"
14451 [(match_operand:SF 1 "register_operand" "0")
14452 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14454 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14455 "* return output_387_binary_op (insn, operands);"
14456 [(set (attr "type")
14457 (cond [(match_operand:SF 3 "mult_operator" "")
14458 (const_string "ssemul")
14459 (match_operand:SF 3 "div_operator" "")
14460 (const_string "ssediv")
14462 (const_string "sseadd")))
14463 (set_attr "mode" "SF")])
14465 ;; ??? Add SSE splitters for these!
14466 (define_insn "*fop_sf_2"
14467 [(set (match_operand:SF 0 "register_operand" "=f,f")
14468 (match_operator:SF 3 "binary_fp_operator"
14469 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14470 (match_operand:SF 2 "register_operand" "0,0")]))]
14471 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14472 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14473 [(set (attr "type")
14474 (cond [(match_operand:SF 3 "mult_operator" "")
14475 (const_string "fmul")
14476 (match_operand:SF 3 "div_operator" "")
14477 (const_string "fdiv")
14479 (const_string "fop")))
14480 (set_attr "fp_int_src" "true")
14481 (set_attr "ppro_uops" "many")
14482 (set_attr "mode" "SI")])
14484 (define_insn "*fop_sf_3"
14485 [(set (match_operand:SF 0 "register_operand" "=f,f")
14486 (match_operator:SF 3 "binary_fp_operator"
14487 [(match_operand:SF 1 "register_operand" "0,0")
14488 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14489 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14490 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14491 [(set (attr "type")
14492 (cond [(match_operand:SF 3 "mult_operator" "")
14493 (const_string "fmul")
14494 (match_operand:SF 3 "div_operator" "")
14495 (const_string "fdiv")
14497 (const_string "fop")))
14498 (set_attr "fp_int_src" "true")
14499 (set_attr "ppro_uops" "many")
14500 (set_attr "mode" "SI")])
14502 (define_insn "*fop_df_1_nosse"
14503 [(set (match_operand:DF 0 "register_operand" "=f,f")
14504 (match_operator:DF 3 "binary_fp_operator"
14505 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14506 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14507 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14508 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14509 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14510 "* return output_387_binary_op (insn, operands);"
14511 [(set (attr "type")
14512 (cond [(match_operand:DF 3 "mult_operator" "")
14513 (const_string "fmul")
14514 (match_operand:DF 3 "div_operator" "")
14515 (const_string "fdiv")
14517 (const_string "fop")))
14518 (set_attr "mode" "DF")])
14521 (define_insn "*fop_df_1"
14522 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14523 (match_operator:DF 3 "binary_fp_operator"
14524 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14525 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14526 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14527 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14528 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14529 "* return output_387_binary_op (insn, operands);"
14530 [(set (attr "type")
14531 (cond [(and (eq_attr "alternative" "2")
14532 (match_operand:SF 3 "mult_operator" ""))
14533 (const_string "ssemul")
14534 (and (eq_attr "alternative" "2")
14535 (match_operand:SF 3 "div_operator" ""))
14536 (const_string "ssediv")
14537 (eq_attr "alternative" "2")
14538 (const_string "sseadd")
14539 (match_operand:DF 3 "mult_operator" "")
14540 (const_string "fmul")
14541 (match_operand:DF 3 "div_operator" "")
14542 (const_string "fdiv")
14544 (const_string "fop")))
14545 (set_attr "mode" "DF")])
14547 (define_insn "*fop_df_1_sse"
14548 [(set (match_operand:DF 0 "register_operand" "=Y")
14549 (match_operator:DF 3 "binary_fp_operator"
14550 [(match_operand:DF 1 "register_operand" "0")
14551 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14552 "TARGET_SSE2 && TARGET_SSE_MATH
14553 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14554 "* return output_387_binary_op (insn, operands);"
14555 [(set_attr "mode" "DF")
14557 (cond [(match_operand:SF 3 "mult_operator" "")
14558 (const_string "ssemul")
14559 (match_operand:SF 3 "div_operator" "")
14560 (const_string "ssediv")
14562 (const_string "sseadd")))])
14564 ;; ??? Add SSE splitters for these!
14565 (define_insn "*fop_df_2"
14566 [(set (match_operand:DF 0 "register_operand" "=f,f")
14567 (match_operator:DF 3 "binary_fp_operator"
14568 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14569 (match_operand:DF 2 "register_operand" "0,0")]))]
14570 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14571 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14572 [(set (attr "type")
14573 (cond [(match_operand:DF 3 "mult_operator" "")
14574 (const_string "fmul")
14575 (match_operand:DF 3 "div_operator" "")
14576 (const_string "fdiv")
14578 (const_string "fop")))
14579 (set_attr "fp_int_src" "true")
14580 (set_attr "ppro_uops" "many")
14581 (set_attr "mode" "SI")])
14583 (define_insn "*fop_df_3"
14584 [(set (match_operand:DF 0 "register_operand" "=f,f")
14585 (match_operator:DF 3 "binary_fp_operator"
14586 [(match_operand:DF 1 "register_operand" "0,0")
14587 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14588 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14589 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14590 [(set (attr "type")
14591 (cond [(match_operand:DF 3 "mult_operator" "")
14592 (const_string "fmul")
14593 (match_operand:DF 3 "div_operator" "")
14594 (const_string "fdiv")
14596 (const_string "fop")))
14597 (set_attr "fp_int_src" "true")
14598 (set_attr "ppro_uops" "many")
14599 (set_attr "mode" "SI")])
14601 (define_insn "*fop_df_4"
14602 [(set (match_operand:DF 0 "register_operand" "=f,f")
14603 (match_operator:DF 3 "binary_fp_operator"
14604 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14605 (match_operand:DF 2 "register_operand" "0,f")]))]
14606 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14607 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14608 "* return output_387_binary_op (insn, operands);"
14609 [(set (attr "type")
14610 (cond [(match_operand:DF 3 "mult_operator" "")
14611 (const_string "fmul")
14612 (match_operand:DF 3 "div_operator" "")
14613 (const_string "fdiv")
14615 (const_string "fop")))
14616 (set_attr "mode" "SF")])
14618 (define_insn "*fop_df_5"
14619 [(set (match_operand:DF 0 "register_operand" "=f,f")
14620 (match_operator:DF 3 "binary_fp_operator"
14621 [(match_operand:DF 1 "register_operand" "0,f")
14623 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14624 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14625 "* return output_387_binary_op (insn, operands);"
14626 [(set (attr "type")
14627 (cond [(match_operand:DF 3 "mult_operator" "")
14628 (const_string "fmul")
14629 (match_operand:DF 3 "div_operator" "")
14630 (const_string "fdiv")
14632 (const_string "fop")))
14633 (set_attr "mode" "SF")])
14635 (define_insn "*fop_df_6"
14636 [(set (match_operand:DF 0 "register_operand" "=f,f")
14637 (match_operator:DF 3 "binary_fp_operator"
14639 (match_operand:SF 1 "register_operand" "0,f"))
14641 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14642 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14643 "* return output_387_binary_op (insn, operands);"
14644 [(set (attr "type")
14645 (cond [(match_operand:DF 3 "mult_operator" "")
14646 (const_string "fmul")
14647 (match_operand:DF 3 "div_operator" "")
14648 (const_string "fdiv")
14650 (const_string "fop")))
14651 (set_attr "mode" "SF")])
14653 (define_insn "*fop_xf_1"
14654 [(set (match_operand:XF 0 "register_operand" "=f,f")
14655 (match_operator:XF 3 "binary_fp_operator"
14656 [(match_operand:XF 1 "register_operand" "0,f")
14657 (match_operand:XF 2 "register_operand" "f,0")]))]
14659 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14660 "* return output_387_binary_op (insn, operands);"
14661 [(set (attr "type")
14662 (cond [(match_operand:XF 3 "mult_operator" "")
14663 (const_string "fmul")
14664 (match_operand:XF 3 "div_operator" "")
14665 (const_string "fdiv")
14667 (const_string "fop")))
14668 (set_attr "mode" "XF")])
14670 (define_insn "*fop_xf_2"
14671 [(set (match_operand:XF 0 "register_operand" "=f,f")
14672 (match_operator:XF 3 "binary_fp_operator"
14673 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14674 (match_operand:XF 2 "register_operand" "0,0")]))]
14675 "TARGET_80387 && TARGET_USE_FIOP"
14676 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14677 [(set (attr "type")
14678 (cond [(match_operand:XF 3 "mult_operator" "")
14679 (const_string "fmul")
14680 (match_operand:XF 3 "div_operator" "")
14681 (const_string "fdiv")
14683 (const_string "fop")))
14684 (set_attr "fp_int_src" "true")
14685 (set_attr "mode" "SI")
14686 (set_attr "ppro_uops" "many")])
14688 (define_insn "*fop_xf_3"
14689 [(set (match_operand:XF 0 "register_operand" "=f,f")
14690 (match_operator:XF 3 "binary_fp_operator"
14691 [(match_operand:XF 1 "register_operand" "0,0")
14692 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14693 "TARGET_80387 && TARGET_USE_FIOP"
14694 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14695 [(set (attr "type")
14696 (cond [(match_operand:XF 3 "mult_operator" "")
14697 (const_string "fmul")
14698 (match_operand:XF 3 "div_operator" "")
14699 (const_string "fdiv")
14701 (const_string "fop")))
14702 (set_attr "fp_int_src" "true")
14703 (set_attr "mode" "SI")
14704 (set_attr "ppro_uops" "many")])
14706 (define_insn "*fop_xf_4"
14707 [(set (match_operand:XF 0 "register_operand" "=f,f")
14708 (match_operator:XF 3 "binary_fp_operator"
14709 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
14710 (match_operand:XF 2 "register_operand" "0,f")]))]
14712 "* return output_387_binary_op (insn, operands);"
14713 [(set (attr "type")
14714 (cond [(match_operand:XF 3 "mult_operator" "")
14715 (const_string "fmul")
14716 (match_operand:XF 3 "div_operator" "")
14717 (const_string "fdiv")
14719 (const_string "fop")))
14720 (set_attr "mode" "SF")])
14722 (define_insn "*fop_xf_5"
14723 [(set (match_operand:XF 0 "register_operand" "=f,f")
14724 (match_operator:XF 3 "binary_fp_operator"
14725 [(match_operand:XF 1 "register_operand" "0,f")
14727 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14729 "* return output_387_binary_op (insn, operands);"
14730 [(set (attr "type")
14731 (cond [(match_operand:XF 3 "mult_operator" "")
14732 (const_string "fmul")
14733 (match_operand:XF 3 "div_operator" "")
14734 (const_string "fdiv")
14736 (const_string "fop")))
14737 (set_attr "mode" "SF")])
14739 (define_insn "*fop_xf_6"
14740 [(set (match_operand:XF 0 "register_operand" "=f,f")
14741 (match_operator:XF 3 "binary_fp_operator"
14743 (match_operand 1 "register_operand" "0,f"))
14745 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14747 "* return output_387_binary_op (insn, operands);"
14748 [(set (attr "type")
14749 (cond [(match_operand:XF 3 "mult_operator" "")
14750 (const_string "fmul")
14751 (match_operand:XF 3 "div_operator" "")
14752 (const_string "fdiv")
14754 (const_string "fop")))
14755 (set_attr "mode" "SF")])
14758 [(set (match_operand 0 "register_operand" "")
14759 (match_operator 3 "binary_fp_operator"
14760 [(float (match_operand:SI 1 "register_operand" ""))
14761 (match_operand 2 "register_operand" "")]))]
14762 "TARGET_80387 && reload_completed
14763 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14766 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14767 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14768 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14769 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14770 GET_MODE (operands[3]),
14773 ix86_free_from_memory (GET_MODE (operands[1]));
14778 [(set (match_operand 0 "register_operand" "")
14779 (match_operator 3 "binary_fp_operator"
14780 [(match_operand 1 "register_operand" "")
14781 (float (match_operand:SI 2 "register_operand" ""))]))]
14782 "TARGET_80387 && reload_completed
14783 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14786 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14787 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14788 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14789 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14790 GET_MODE (operands[3]),
14793 ix86_free_from_memory (GET_MODE (operands[2]));
14797 ;; FPU special functions.
14799 (define_expand "sqrtsf2"
14800 [(set (match_operand:SF 0 "register_operand" "")
14801 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14802 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
14804 if (!TARGET_SSE_MATH)
14805 operands[1] = force_reg (SFmode, operands[1]);
14808 (define_insn "sqrtsf2_1"
14809 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14810 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14811 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14812 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14815 sqrtss\t{%1, %0|%0, %1}"
14816 [(set_attr "type" "fpspc,sse")
14817 (set_attr "mode" "SF,SF")
14818 (set_attr "athlon_decode" "direct,*")])
14820 (define_insn "sqrtsf2_1_sse_only"
14821 [(set (match_operand:SF 0 "register_operand" "=x")
14822 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14823 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14824 "sqrtss\t{%1, %0|%0, %1}"
14825 [(set_attr "type" "sse")
14826 (set_attr "mode" "SF")
14827 (set_attr "athlon_decode" "*")])
14829 (define_insn "sqrtsf2_i387"
14830 [(set (match_operand:SF 0 "register_operand" "=f")
14831 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14832 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14833 && !TARGET_SSE_MATH"
14835 [(set_attr "type" "fpspc")
14836 (set_attr "mode" "SF")
14837 (set_attr "athlon_decode" "direct")])
14839 (define_expand "sqrtdf2"
14840 [(set (match_operand:DF 0 "register_operand" "")
14841 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14842 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
14843 || (TARGET_SSE2 && TARGET_SSE_MATH)"
14845 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
14846 operands[1] = force_reg (DFmode, operands[1]);
14849 (define_insn "sqrtdf2_1"
14850 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14851 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14852 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14853 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
14856 sqrtsd\t{%1, %0|%0, %1}"
14857 [(set_attr "type" "fpspc,sse")
14858 (set_attr "mode" "DF,DF")
14859 (set_attr "athlon_decode" "direct,*")])
14861 (define_insn "sqrtdf2_1_sse_only"
14862 [(set (match_operand:DF 0 "register_operand" "=Y")
14863 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14864 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
14865 "sqrtsd\t{%1, %0|%0, %1}"
14866 [(set_attr "type" "sse")
14867 (set_attr "mode" "DF")
14868 (set_attr "athlon_decode" "*")])
14870 (define_insn "sqrtdf2_i387"
14871 [(set (match_operand:DF 0 "register_operand" "=f")
14872 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14873 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14874 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
14876 [(set_attr "type" "fpspc")
14877 (set_attr "mode" "DF")
14878 (set_attr "athlon_decode" "direct")])
14880 (define_insn "*sqrtextendsfdf2"
14881 [(set (match_operand:DF 0 "register_operand" "=f")
14882 (sqrt:DF (float_extend:DF
14883 (match_operand:SF 1 "register_operand" "0"))))]
14884 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14885 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14887 [(set_attr "type" "fpspc")
14888 (set_attr "mode" "DF")
14889 (set_attr "athlon_decode" "direct")])
14891 (define_insn "sqrtxf2"
14892 [(set (match_operand:XF 0 "register_operand" "=f")
14893 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14894 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14895 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14897 [(set_attr "type" "fpspc")
14898 (set_attr "mode" "XF")
14899 (set_attr "athlon_decode" "direct")])
14901 (define_insn "*sqrtextenddfxf2"
14902 [(set (match_operand:XF 0 "register_operand" "=f")
14903 (sqrt:XF (float_extend:XF
14904 (match_operand:DF 1 "register_operand" "0"))))]
14905 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14907 [(set_attr "type" "fpspc")
14908 (set_attr "mode" "XF")
14909 (set_attr "athlon_decode" "direct")])
14911 (define_insn "*sqrtextendsfxf2"
14912 [(set (match_operand:XF 0 "register_operand" "=f")
14913 (sqrt:XF (float_extend:XF
14914 (match_operand:SF 1 "register_operand" "0"))))]
14915 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
14917 [(set_attr "type" "fpspc")
14918 (set_attr "mode" "XF")
14919 (set_attr "athlon_decode" "direct")])
14921 (define_insn "sindf2"
14922 [(set (match_operand:DF 0 "register_operand" "=f")
14923 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
14924 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14925 && flag_unsafe_math_optimizations"
14927 [(set_attr "type" "fpspc")
14928 (set_attr "mode" "DF")])
14930 (define_insn "sinsf2"
14931 [(set (match_operand:SF 0 "register_operand" "=f")
14932 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
14933 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14934 && flag_unsafe_math_optimizations"
14936 [(set_attr "type" "fpspc")
14937 (set_attr "mode" "SF")])
14939 (define_insn "*sinextendsfdf2"
14940 [(set (match_operand:DF 0 "register_operand" "=f")
14941 (unspec:DF [(float_extend:DF
14942 (match_operand:SF 1 "register_operand" "0"))]
14944 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14945 && flag_unsafe_math_optimizations"
14947 [(set_attr "type" "fpspc")
14948 (set_attr "mode" "DF")])
14950 (define_insn "sinxf2"
14951 [(set (match_operand:XF 0 "register_operand" "=f")
14952 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
14953 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
14954 && flag_unsafe_math_optimizations"
14956 [(set_attr "type" "fpspc")
14957 (set_attr "mode" "XF")])
14959 (define_insn "cosdf2"
14960 [(set (match_operand:DF 0 "register_operand" "=f")
14961 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
14962 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14963 && flag_unsafe_math_optimizations"
14965 [(set_attr "type" "fpspc")
14966 (set_attr "mode" "DF")])
14968 (define_insn "cossf2"
14969 [(set (match_operand:SF 0 "register_operand" "=f")
14970 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
14971 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14972 && flag_unsafe_math_optimizations"
14974 [(set_attr "type" "fpspc")
14975 (set_attr "mode" "SF")])
14977 (define_insn "*cosextendsfdf2"
14978 [(set (match_operand:DF 0 "register_operand" "=f")
14979 (unspec:DF [(float_extend:DF
14980 (match_operand:SF 1 "register_operand" "0"))]
14982 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14983 && flag_unsafe_math_optimizations"
14985 [(set_attr "type" "fpspc")
14986 (set_attr "mode" "DF")])
14988 (define_insn "cosxf2"
14989 [(set (match_operand:XF 0 "register_operand" "=f")
14990 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
14991 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
14992 && flag_unsafe_math_optimizations"
14994 [(set_attr "type" "fpspc")
14995 (set_attr "mode" "XF")])
14997 (define_insn "atan2df3_1"
14998 [(set (match_operand:DF 0 "register_operand" "=f")
14999 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15000 (match_operand:DF 1 "register_operand" "u")]
15002 (clobber (match_scratch:DF 3 "=1"))]
15003 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15004 && flag_unsafe_math_optimizations"
15006 [(set_attr "type" "fpspc")
15007 (set_attr "mode" "DF")])
15009 (define_expand "atan2df3"
15010 [(use (match_operand:DF 0 "register_operand" "=f"))
15011 (use (match_operand:DF 2 "register_operand" "0"))
15012 (use (match_operand:DF 1 "register_operand" "u"))]
15013 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15014 && flag_unsafe_math_optimizations"
15016 rtx copy = gen_reg_rtx (DFmode);
15017 emit_move_insn (copy, operands[1]);
15018 emit_insn (gen_atan2df3_1 (operands[0], copy, operands[2]));
15022 (define_insn "atan2sf3_1"
15023 [(set (match_operand:SF 0 "register_operand" "=f")
15024 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15025 (match_operand:SF 1 "register_operand" "u")]
15027 (clobber (match_scratch:SF 3 "=1"))]
15028 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15029 && flag_unsafe_math_optimizations"
15031 [(set_attr "type" "fpspc")
15032 (set_attr "mode" "SF")])
15034 (define_expand "atan2sf3"
15035 [(use (match_operand:SF 0 "register_operand" "=f"))
15036 (use (match_operand:SF 2 "register_operand" "0"))
15037 (use (match_operand:SF 1 "register_operand" "u"))]
15038 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15039 && flag_unsafe_math_optimizations"
15041 rtx copy = gen_reg_rtx (SFmode);
15042 emit_move_insn (copy, operands[1]);
15043 emit_insn (gen_atan2sf3_1 (operands[0], copy, operands[2]));
15047 (define_insn "atan2xf3_1"
15048 [(set (match_operand:XF 0 "register_operand" "=f")
15049 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15050 (match_operand:XF 1 "register_operand" "u")]
15052 (clobber (match_scratch:XF 3 "=1"))]
15053 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15054 && flag_unsafe_math_optimizations"
15056 [(set_attr "type" "fpspc")
15057 (set_attr "mode" "XF")])
15059 (define_expand "atan2xf3"
15060 [(use (match_operand:XF 0 "register_operand" "=f"))
15061 (use (match_operand:XF 2 "register_operand" "0"))
15062 (use (match_operand:XF 1 "register_operand" "u"))]
15063 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15064 && flag_unsafe_math_optimizations"
15066 rtx copy = gen_reg_rtx (XFmode);
15067 emit_move_insn (copy, operands[1]);
15068 emit_insn (gen_atan2xf3_1 (operands[0], copy, operands[2]));
15072 (define_insn "*fyl2x_sfxf3"
15073 [(set (match_operand:SF 0 "register_operand" "=f")
15074 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15075 (match_operand:XF 1 "register_operand" "u")]
15077 (clobber (match_scratch:SF 3 "=1"))]
15078 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15079 && flag_unsafe_math_optimizations"
15081 [(set_attr "type" "fpspc")
15082 (set_attr "mode" "SF")])
15084 (define_insn "*fyl2x_dfxf3"
15085 [(set (match_operand:DF 0 "register_operand" "=f")
15086 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15087 (match_operand:XF 1 "register_operand" "u")]
15089 (clobber (match_scratch:DF 3 "=1"))]
15090 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15091 && flag_unsafe_math_optimizations"
15093 [(set_attr "type" "fpspc")
15094 (set_attr "mode" "DF")])
15096 (define_insn "*fyl2x_xf3"
15097 [(set (match_operand:XF 0 "register_operand" "=f")
15098 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15099 (match_operand:XF 1 "register_operand" "u")]
15101 (clobber (match_scratch:XF 3 "=1"))]
15102 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15103 && flag_unsafe_math_optimizations"
15105 [(set_attr "type" "fpspc")
15106 (set_attr "mode" "XF")])
15108 (define_expand "logsf2"
15109 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15110 (unspec:SF [(match_operand:SF 1 "register_operand" "")
15111 (match_dup 2)] UNSPEC_FYL2X))
15112 (clobber (match_scratch:SF 3 ""))])]
15113 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15114 && flag_unsafe_math_optimizations"
15118 operands[2] = gen_reg_rtx (XFmode);
15119 temp = standard_80387_constant_rtx (4); /* fldln2 */
15120 emit_move_insn (operands[2], temp);
15123 (define_expand "logdf2"
15124 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15125 (unspec:DF [(match_operand:DF 1 "register_operand" "")
15126 (match_dup 2)] UNSPEC_FYL2X))
15127 (clobber (match_scratch:DF 3 ""))])]
15128 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15129 && flag_unsafe_math_optimizations"
15133 operands[2] = gen_reg_rtx (XFmode);
15134 temp = standard_80387_constant_rtx (4); /* fldln2 */
15135 emit_move_insn (operands[2], temp);
15138 (define_expand "logxf2"
15139 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15140 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15141 (match_dup 2)] UNSPEC_FYL2X))
15142 (clobber (match_scratch:XF 3 ""))])]
15143 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15144 && flag_unsafe_math_optimizations"
15148 operands[2] = gen_reg_rtx (XFmode);
15149 temp = standard_80387_constant_rtx (4); /* fldln2 */
15150 emit_move_insn (operands[2], temp);
15153 (define_insn "*fscale_sfxf3"
15154 [(set (match_operand:SF 0 "register_operand" "=f")
15155 (unspec:SF [(match_operand:XF 2 "register_operand" "0")
15156 (match_operand:XF 1 "register_operand" "u")]
15158 (clobber (match_scratch:SF 3 "=1"))]
15159 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15160 && flag_unsafe_math_optimizations"
15161 "fscale\;fstp\t%y1"
15162 [(set_attr "type" "fpspc")
15163 (set_attr "mode" "SF")])
15165 (define_insn "*fscale_dfxf3"
15166 [(set (match_operand:DF 0 "register_operand" "=f")
15167 (unspec:DF [(match_operand:XF 2 "register_operand" "0")
15168 (match_operand:XF 1 "register_operand" "u")]
15170 (clobber (match_scratch:DF 3 "=1"))]
15171 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15172 && flag_unsafe_math_optimizations"
15173 "fscale\;fstp\t%y1"
15174 [(set_attr "type" "fpspc")
15175 (set_attr "mode" "DF")])
15177 (define_insn "*fscale_xf3"
15178 [(set (match_operand:XF 0 "register_operand" "=f")
15179 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15180 (match_operand:XF 1 "register_operand" "u")]
15182 (clobber (match_scratch:XF 3 "=1"))]
15183 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15184 && flag_unsafe_math_optimizations"
15185 "fscale\;fstp\t%y1"
15186 [(set_attr "type" "fpspc")
15187 (set_attr "mode" "XF")])
15189 (define_insn "*frndintxf2"
15190 [(set (match_operand:XF 0 "register_operand" "=f")
15191 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15193 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15194 && flag_unsafe_math_optimizations"
15196 [(set_attr "type" "fpspc")
15197 (set_attr "mode" "XF")])
15199 (define_insn "*f2xm1xf2"
15200 [(set (match_operand:XF 0 "register_operand" "=f")
15201 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15203 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15204 && flag_unsafe_math_optimizations"
15206 [(set_attr "type" "fpspc")
15207 (set_attr "mode" "XF")])
15209 (define_expand "expsf2"
15210 [(set (match_dup 2)
15211 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15212 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15213 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15214 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15215 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15216 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15217 (parallel [(set (match_operand:SF 0 "register_operand" "")
15218 (unspec:SF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
15219 (clobber (match_scratch:SF 5 ""))])]
15220 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15221 && flag_unsafe_math_optimizations"
15226 for (i=2; i<10; i++)
15227 operands[i] = gen_reg_rtx (XFmode);
15228 temp = standard_80387_constant_rtx (5); /* fldl2e */
15229 emit_move_insn (operands[3], temp);
15230 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15233 (define_expand "expdf2"
15234 [(set (match_dup 2)
15235 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15236 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15237 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15238 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15239 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15240 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15241 (parallel [(set (match_operand:DF 0 "register_operand" "")
15242 (unspec:DF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
15243 (clobber (match_scratch:DF 5 ""))])]
15244 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15245 && flag_unsafe_math_optimizations"
15250 for (i=2; i<10; i++)
15251 operands[i] = gen_reg_rtx (XFmode);
15252 temp = standard_80387_constant_rtx (5); /* fldl2e */
15253 emit_move_insn (operands[3], temp);
15254 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15257 (define_expand "expxf2"
15258 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
15260 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
15261 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
15262 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
15263 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
15264 (parallel [(set (match_operand:XF 0 "register_operand" "")
15265 (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
15266 (clobber (match_scratch:XF 5 ""))])]
15267 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15268 && flag_unsafe_math_optimizations"
15273 for (i=2; i<9; i++)
15274 operands[i] = gen_reg_rtx (XFmode);
15275 temp = standard_80387_constant_rtx (5); /* fldl2e */
15276 emit_move_insn (operands[2], temp);
15277 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
15280 (define_expand "atansf2"
15281 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15282 (unspec:SF [(match_dup 2)
15283 (match_operand:SF 1 "register_operand" "")]
15285 (clobber (match_scratch:SF 3 ""))])]
15286 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15287 && flag_unsafe_math_optimizations"
15289 operands[2] = gen_reg_rtx (SFmode);
15290 emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
15293 (define_expand "atandf2"
15294 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15295 (unspec:DF [(match_dup 2)
15296 (match_operand:DF 1 "register_operand" "")]
15298 (clobber (match_scratch:DF 3 ""))])]
15299 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15300 && flag_unsafe_math_optimizations"
15302 operands[2] = gen_reg_rtx (DFmode);
15303 emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
15306 (define_expand "atanxf2"
15307 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15308 (unspec:XF [(match_dup 2)
15309 (match_operand:XF 1 "register_operand" "")]
15311 (clobber (match_scratch:XF 3 ""))])]
15312 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15313 && flag_unsafe_math_optimizations"
15315 operands[2] = gen_reg_rtx (XFmode);
15316 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15319 ;; Block operation instructions
15322 [(set (reg:SI 19) (const_int 0))]
15325 [(set_attr "type" "cld")])
15327 (define_expand "movstrsi"
15328 [(use (match_operand:BLK 0 "memory_operand" ""))
15329 (use (match_operand:BLK 1 "memory_operand" ""))
15330 (use (match_operand:SI 2 "nonmemory_operand" ""))
15331 (use (match_operand:SI 3 "const_int_operand" ""))]
15334 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15340 (define_expand "movstrdi"
15341 [(use (match_operand:BLK 0 "memory_operand" ""))
15342 (use (match_operand:BLK 1 "memory_operand" ""))
15343 (use (match_operand:DI 2 "nonmemory_operand" ""))
15344 (use (match_operand:DI 3 "const_int_operand" ""))]
15347 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15353 ;; Most CPUs don't like single string operations
15354 ;; Handle this case here to simplify previous expander.
15356 (define_expand "strmov"
15357 [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
15358 (set (match_operand 1 "memory_operand" "") (match_dup 4))
15359 (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
15360 (clobber (reg:CC 17))])
15361 (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
15362 (clobber (reg:CC 17))])]
15365 rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1])));
15367 /* If .md ever supports :P for Pmode, these can be directly
15368 in the pattern above. */
15369 operands[5] = gen_rtx_PLUS (Pmode, operands[0], adjust);
15370 operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
15372 if (TARGET_SINGLE_STRINGOP || optimize_size)
15374 emit_insn (gen_strmov_singleop (operands[0], operands[1],
15375 operands[2], operands[3],
15376 operands[5], operands[6]));
15380 operands[4] = gen_reg_rtx (GET_MODE (operands[1]));
15383 (define_expand "strmov_singleop"
15384 [(parallel [(set (match_operand 1 "memory_operand" "")
15385 (match_operand 3 "memory_operand" ""))
15386 (set (match_operand 0 "register_operand" "")
15387 (match_operand 4 "" ""))
15388 (set (match_operand 2 "register_operand" "")
15389 (match_operand 5 "" ""))
15390 (use (reg:SI 19))])]
15391 "TARGET_SINGLE_STRINGOP || optimize_size"
15394 (define_insn "*strmovdi_rex_1"
15395 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
15396 (mem:DI (match_operand:DI 3 "register_operand" "1")))
15397 (set (match_operand:DI 0 "register_operand" "=D")
15398 (plus:DI (match_dup 2)
15400 (set (match_operand:DI 1 "register_operand" "=S")
15401 (plus:DI (match_dup 3)
15404 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15406 [(set_attr "type" "str")
15407 (set_attr "mode" "DI")
15408 (set_attr "memory" "both")])
15410 (define_insn "*strmovsi_1"
15411 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
15412 (mem:SI (match_operand:SI 3 "register_operand" "1")))
15413 (set (match_operand:SI 0 "register_operand" "=D")
15414 (plus:SI (match_dup 2)
15416 (set (match_operand:SI 1 "register_operand" "=S")
15417 (plus:SI (match_dup 3)
15420 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15422 [(set_attr "type" "str")
15423 (set_attr "mode" "SI")
15424 (set_attr "memory" "both")])
15426 (define_insn "*strmovsi_rex_1"
15427 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
15428 (mem:SI (match_operand:DI 3 "register_operand" "1")))
15429 (set (match_operand:DI 0 "register_operand" "=D")
15430 (plus:DI (match_dup 2)
15432 (set (match_operand:DI 1 "register_operand" "=S")
15433 (plus:DI (match_dup 3)
15436 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15438 [(set_attr "type" "str")
15439 (set_attr "mode" "SI")
15440 (set_attr "memory" "both")])
15442 (define_insn "*strmovhi_1"
15443 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
15444 (mem:HI (match_operand:SI 3 "register_operand" "1")))
15445 (set (match_operand:SI 0 "register_operand" "=D")
15446 (plus:SI (match_dup 2)
15448 (set (match_operand:SI 1 "register_operand" "=S")
15449 (plus:SI (match_dup 3)
15452 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15454 [(set_attr "type" "str")
15455 (set_attr "memory" "both")
15456 (set_attr "mode" "HI")])
15458 (define_insn "*strmovhi_rex_1"
15459 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
15460 (mem:HI (match_operand:DI 3 "register_operand" "1")))
15461 (set (match_operand:DI 0 "register_operand" "=D")
15462 (plus:DI (match_dup 2)
15464 (set (match_operand:DI 1 "register_operand" "=S")
15465 (plus:DI (match_dup 3)
15468 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15470 [(set_attr "type" "str")
15471 (set_attr "memory" "both")
15472 (set_attr "mode" "HI")])
15474 (define_insn "*strmovqi_1"
15475 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
15476 (mem:QI (match_operand:SI 3 "register_operand" "1")))
15477 (set (match_operand:SI 0 "register_operand" "=D")
15478 (plus:SI (match_dup 2)
15480 (set (match_operand:SI 1 "register_operand" "=S")
15481 (plus:SI (match_dup 3)
15484 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15486 [(set_attr "type" "str")
15487 (set_attr "memory" "both")
15488 (set_attr "mode" "QI")])
15490 (define_insn "*strmovqi_rex_1"
15491 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
15492 (mem:QI (match_operand:DI 3 "register_operand" "1")))
15493 (set (match_operand:DI 0 "register_operand" "=D")
15494 (plus:DI (match_dup 2)
15496 (set (match_operand:DI 1 "register_operand" "=S")
15497 (plus:DI (match_dup 3)
15500 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15502 [(set_attr "type" "str")
15503 (set_attr "memory" "both")
15504 (set_attr "mode" "QI")])
15506 (define_expand "rep_mov"
15507 [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
15508 (set (match_operand 0 "register_operand" "")
15509 (match_operand 5 "" ""))
15510 (set (match_operand 2 "register_operand" "")
15511 (match_operand 6 "" ""))
15512 (set (match_operand 1 "memory_operand" "")
15513 (match_operand 3 "memory_operand" ""))
15514 (use (match_dup 4))
15515 (use (reg:SI 19))])]
15519 (define_insn "*rep_movdi_rex64"
15520 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15521 (set (match_operand:DI 0 "register_operand" "=D")
15522 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15524 (match_operand:DI 3 "register_operand" "0")))
15525 (set (match_operand:DI 1 "register_operand" "=S")
15526 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
15527 (match_operand:DI 4 "register_operand" "1")))
15528 (set (mem:BLK (match_dup 3))
15529 (mem:BLK (match_dup 4)))
15530 (use (match_dup 5))
15533 "{rep\;movsq|rep movsq}"
15534 [(set_attr "type" "str")
15535 (set_attr "prefix_rep" "1")
15536 (set_attr "memory" "both")
15537 (set_attr "mode" "DI")])
15539 (define_insn "*rep_movsi"
15540 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15541 (set (match_operand:SI 0 "register_operand" "=D")
15542 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
15544 (match_operand:SI 3 "register_operand" "0")))
15545 (set (match_operand:SI 1 "register_operand" "=S")
15546 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
15547 (match_operand:SI 4 "register_operand" "1")))
15548 (set (mem:BLK (match_dup 3))
15549 (mem:BLK (match_dup 4)))
15550 (use (match_dup 5))
15553 "{rep\;movsl|rep movsd}"
15554 [(set_attr "type" "str")
15555 (set_attr "prefix_rep" "1")
15556 (set_attr "memory" "both")
15557 (set_attr "mode" "SI")])
15559 (define_insn "*rep_movsi_rex64"
15560 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15561 (set (match_operand:DI 0 "register_operand" "=D")
15562 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15564 (match_operand:DI 3 "register_operand" "0")))
15565 (set (match_operand:DI 1 "register_operand" "=S")
15566 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
15567 (match_operand:DI 4 "register_operand" "1")))
15568 (set (mem:BLK (match_dup 3))
15569 (mem:BLK (match_dup 4)))
15570 (use (match_dup 5))
15573 "{rep\;movsl|rep movsd}"
15574 [(set_attr "type" "str")
15575 (set_attr "prefix_rep" "1")
15576 (set_attr "memory" "both")
15577 (set_attr "mode" "SI")])
15579 (define_insn "*rep_movqi"
15580 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15581 (set (match_operand:SI 0 "register_operand" "=D")
15582 (plus:SI (match_operand:SI 3 "register_operand" "0")
15583 (match_operand:SI 5 "register_operand" "2")))
15584 (set (match_operand:SI 1 "register_operand" "=S")
15585 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
15586 (set (mem:BLK (match_dup 3))
15587 (mem:BLK (match_dup 4)))
15588 (use (match_dup 5))
15591 "{rep\;movsb|rep movsb}"
15592 [(set_attr "type" "str")
15593 (set_attr "prefix_rep" "1")
15594 (set_attr "memory" "both")
15595 (set_attr "mode" "SI")])
15597 (define_insn "*rep_movqi_rex64"
15598 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15599 (set (match_operand:DI 0 "register_operand" "=D")
15600 (plus:DI (match_operand:DI 3 "register_operand" "0")
15601 (match_operand:DI 5 "register_operand" "2")))
15602 (set (match_operand:DI 1 "register_operand" "=S")
15603 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
15604 (set (mem:BLK (match_dup 3))
15605 (mem:BLK (match_dup 4)))
15606 (use (match_dup 5))
15609 "{rep\;movsb|rep movsb}"
15610 [(set_attr "type" "str")
15611 (set_attr "prefix_rep" "1")
15612 (set_attr "memory" "both")
15613 (set_attr "mode" "SI")])
15615 (define_expand "clrstrsi"
15616 [(use (match_operand:BLK 0 "memory_operand" ""))
15617 (use (match_operand:SI 1 "nonmemory_operand" ""))
15618 (use (match_operand 2 "const_int_operand" ""))]
15621 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15627 (define_expand "clrstrdi"
15628 [(use (match_operand:BLK 0 "memory_operand" ""))
15629 (use (match_operand:DI 1 "nonmemory_operand" ""))
15630 (use (match_operand 2 "const_int_operand" ""))]
15633 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15639 ;; Most CPUs don't like single string operations
15640 ;; Handle this case here to simplify previous expander.
15642 (define_expand "strset"
15643 [(set (match_operand 1 "memory_operand" "")
15644 (match_operand 2 "register_operand" ""))
15645 (parallel [(set (match_operand 0 "register_operand" "")
15647 (clobber (reg:CC 17))])]
15650 if (GET_MODE (operands[1]) != GET_MODE (operands[2]))
15651 operands[1] = adjust_address_nv (operands[1], GET_MODE (operands[2]), 0);
15653 /* If .md ever supports :P for Pmode, this can be directly
15654 in the pattern above. */
15655 operands[3] = gen_rtx_PLUS (Pmode, operands[0],
15656 GEN_INT (GET_MODE_SIZE (GET_MODE
15658 if (TARGET_SINGLE_STRINGOP || optimize_size)
15660 emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
15666 (define_expand "strset_singleop"
15667 [(parallel [(set (match_operand 1 "memory_operand" "")
15668 (match_operand 2 "register_operand" ""))
15669 (set (match_operand 0 "register_operand" "")
15670 (match_operand 3 "" ""))
15671 (use (reg:SI 19))])]
15672 "TARGET_SINGLE_STRINGOP || optimize_size"
15675 (define_insn "*strsetdi_rex_1"
15676 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15677 (match_operand:SI 2 "register_operand" "a"))
15678 (set (match_operand:DI 0 "register_operand" "=D")
15679 (plus:DI (match_dup 1)
15682 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15684 [(set_attr "type" "str")
15685 (set_attr "memory" "store")
15686 (set_attr "mode" "DI")])
15688 (define_insn "*strsetsi_1"
15689 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
15690 (match_operand:SI 2 "register_operand" "a"))
15691 (set (match_operand:SI 0 "register_operand" "=D")
15692 (plus:SI (match_dup 1)
15695 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15697 [(set_attr "type" "str")
15698 (set_attr "memory" "store")
15699 (set_attr "mode" "SI")])
15701 (define_insn "*strsetsi_rex_1"
15702 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
15703 (match_operand:SI 2 "register_operand" "a"))
15704 (set (match_operand:DI 0 "register_operand" "=D")
15705 (plus:DI (match_dup 1)
15708 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15710 [(set_attr "type" "str")
15711 (set_attr "memory" "store")
15712 (set_attr "mode" "SI")])
15714 (define_insn "*strsethi_1"
15715 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
15716 (match_operand:HI 2 "register_operand" "a"))
15717 (set (match_operand:SI 0 "register_operand" "=D")
15718 (plus:SI (match_dup 1)
15721 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15723 [(set_attr "type" "str")
15724 (set_attr "memory" "store")
15725 (set_attr "mode" "HI")])
15727 (define_insn "*strsethi_rex_1"
15728 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
15729 (match_operand:HI 2 "register_operand" "a"))
15730 (set (match_operand:DI 0 "register_operand" "=D")
15731 (plus:DI (match_dup 1)
15734 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15736 [(set_attr "type" "str")
15737 (set_attr "memory" "store")
15738 (set_attr "mode" "HI")])
15740 (define_insn "*strsetqi_1"
15741 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
15742 (match_operand:QI 2 "register_operand" "a"))
15743 (set (match_operand:SI 0 "register_operand" "=D")
15744 (plus:SI (match_dup 1)
15747 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15749 [(set_attr "type" "str")
15750 (set_attr "memory" "store")
15751 (set_attr "mode" "QI")])
15753 (define_insn "*strsetqi_rex_1"
15754 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
15755 (match_operand:QI 2 "register_operand" "a"))
15756 (set (match_operand:DI 0 "register_operand" "=D")
15757 (plus:DI (match_dup 1)
15760 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15762 [(set_attr "type" "str")
15763 (set_attr "memory" "store")
15764 (set_attr "mode" "QI")])
15766 (define_expand "rep_stos"
15767 [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
15768 (set (match_operand 0 "register_operand" "")
15769 (match_operand 4 "" ""))
15770 (set (match_operand 2 "memory_operand" "") (const_int 0))
15771 (use (match_operand 3 "register_operand" ""))
15772 (use (match_dup 1))
15773 (use (reg:SI 19))])]
15777 (define_insn "*rep_stosdi_rex64"
15778 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15779 (set (match_operand:DI 0 "register_operand" "=D")
15780 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15782 (match_operand:DI 3 "register_operand" "0")))
15783 (set (mem:BLK (match_dup 3))
15785 (use (match_operand:DI 2 "register_operand" "a"))
15786 (use (match_dup 4))
15789 "{rep\;stosq|rep stosq}"
15790 [(set_attr "type" "str")
15791 (set_attr "prefix_rep" "1")
15792 (set_attr "memory" "store")
15793 (set_attr "mode" "DI")])
15795 (define_insn "*rep_stossi"
15796 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15797 (set (match_operand:SI 0 "register_operand" "=D")
15798 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
15800 (match_operand:SI 3 "register_operand" "0")))
15801 (set (mem:BLK (match_dup 3))
15803 (use (match_operand:SI 2 "register_operand" "a"))
15804 (use (match_dup 4))
15807 "{rep\;stosl|rep stosd}"
15808 [(set_attr "type" "str")
15809 (set_attr "prefix_rep" "1")
15810 (set_attr "memory" "store")
15811 (set_attr "mode" "SI")])
15813 (define_insn "*rep_stossi_rex64"
15814 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15815 (set (match_operand:DI 0 "register_operand" "=D")
15816 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
15818 (match_operand:DI 3 "register_operand" "0")))
15819 (set (mem:BLK (match_dup 3))
15821 (use (match_operand:SI 2 "register_operand" "a"))
15822 (use (match_dup 4))
15825 "{rep\;stosl|rep stosd}"
15826 [(set_attr "type" "str")
15827 (set_attr "prefix_rep" "1")
15828 (set_attr "memory" "store")
15829 (set_attr "mode" "SI")])
15831 (define_insn "*rep_stosqi"
15832 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
15833 (set (match_operand:SI 0 "register_operand" "=D")
15834 (plus:SI (match_operand:SI 3 "register_operand" "0")
15835 (match_operand:SI 4 "register_operand" "1")))
15836 (set (mem:BLK (match_dup 3))
15838 (use (match_operand:QI 2 "register_operand" "a"))
15839 (use (match_dup 4))
15842 "{rep\;stosb|rep stosb}"
15843 [(set_attr "type" "str")
15844 (set_attr "prefix_rep" "1")
15845 (set_attr "memory" "store")
15846 (set_attr "mode" "QI")])
15848 (define_insn "*rep_stosqi_rex64"
15849 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
15850 (set (match_operand:DI 0 "register_operand" "=D")
15851 (plus:DI (match_operand:DI 3 "register_operand" "0")
15852 (match_operand:DI 4 "register_operand" "1")))
15853 (set (mem:BLK (match_dup 3))
15855 (use (match_operand:QI 2 "register_operand" "a"))
15856 (use (match_dup 4))
15859 "{rep\;stosb|rep stosb}"
15860 [(set_attr "type" "str")
15861 (set_attr "prefix_rep" "1")
15862 (set_attr "memory" "store")
15863 (set_attr "mode" "QI")])
15865 (define_expand "cmpstrsi"
15866 [(set (match_operand:SI 0 "register_operand" "")
15867 (compare:SI (match_operand:BLK 1 "general_operand" "")
15868 (match_operand:BLK 2 "general_operand" "")))
15869 (use (match_operand 3 "general_operand" ""))
15870 (use (match_operand 4 "immediate_operand" ""))]
15871 "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
15873 rtx addr1, addr2, out, outlow, count, countreg, align;
15875 /* Can't use this if the user has appropriated esi or edi. */
15876 if (global_regs[4] || global_regs[5])
15880 if (GET_CODE (out) != REG)
15881 out = gen_reg_rtx (SImode);
15883 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
15884 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
15885 if (addr1 != XEXP (operands[1], 0))
15886 operands[1] = replace_equiv_address_nv (operands[1], addr1);
15887 if (addr2 != XEXP (operands[2], 0))
15888 operands[2] = replace_equiv_address_nv (operands[2], addr2);
15890 count = operands[3];
15891 countreg = ix86_zero_extend_to_Pmode (count);
15893 /* %%% Iff we are testing strict equality, we can use known alignment
15894 to good advantage. This may be possible with combine, particularly
15895 once cc0 is dead. */
15896 align = operands[4];
15898 emit_insn (gen_cld ());
15899 if (GET_CODE (count) == CONST_INT)
15901 if (INTVAL (count) == 0)
15903 emit_move_insn (operands[0], const0_rtx);
15906 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
15907 operands[1], operands[2]));
15912 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
15914 emit_insn (gen_cmpsi_1 (countreg, countreg));
15915 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
15916 operands[1], operands[2]));
15919 outlow = gen_lowpart (QImode, out);
15920 emit_insn (gen_cmpintqi (outlow));
15921 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
15923 if (operands[0] != out)
15924 emit_move_insn (operands[0], out);
15929 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
15931 (define_expand "cmpintqi"
15932 [(set (match_dup 1)
15933 (gtu:QI (reg:CC 17) (const_int 0)))
15935 (ltu:QI (reg:CC 17) (const_int 0)))
15936 (parallel [(set (match_operand:QI 0 "register_operand" "")
15937 (minus:QI (match_dup 1)
15939 (clobber (reg:CC 17))])]
15941 "operands[1] = gen_reg_rtx (QImode);
15942 operands[2] = gen_reg_rtx (QImode);")
15944 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
15945 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
15947 (define_expand "cmpstrqi_nz_1"
15948 [(parallel [(set (reg:CC 17)
15949 (compare:CC (match_operand 4 "memory_operand" "")
15950 (match_operand 5 "memory_operand" "")))
15951 (use (match_operand 2 "register_operand" ""))
15952 (use (match_operand:SI 3 "immediate_operand" ""))
15954 (clobber (match_operand 0 "register_operand" ""))
15955 (clobber (match_operand 1 "register_operand" ""))
15956 (clobber (match_dup 2))])]
15960 (define_insn "*cmpstrqi_nz_1"
15962 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
15963 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
15964 (use (match_operand:SI 6 "register_operand" "2"))
15965 (use (match_operand:SI 3 "immediate_operand" "i"))
15967 (clobber (match_operand:SI 0 "register_operand" "=S"))
15968 (clobber (match_operand:SI 1 "register_operand" "=D"))
15969 (clobber (match_operand:SI 2 "register_operand" "=c"))]
15972 [(set_attr "type" "str")
15973 (set_attr "mode" "QI")
15974 (set_attr "prefix_rep" "1")])
15976 (define_insn "*cmpstrqi_nz_rex_1"
15978 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
15979 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
15980 (use (match_operand:DI 6 "register_operand" "2"))
15981 (use (match_operand:SI 3 "immediate_operand" "i"))
15983 (clobber (match_operand:DI 0 "register_operand" "=S"))
15984 (clobber (match_operand:DI 1 "register_operand" "=D"))
15985 (clobber (match_operand:DI 2 "register_operand" "=c"))]
15988 [(set_attr "type" "str")
15989 (set_attr "mode" "QI")
15990 (set_attr "prefix_rep" "1")])
15992 ;; The same, but the count is not known to not be zero.
15994 (define_expand "cmpstrqi_1"
15995 [(parallel [(set (reg:CC 17)
15996 (if_then_else:CC (ne (match_operand 2 "register_operand" "")
15998 (compare:CC (match_operand 4 "memory_operand" "")
15999 (match_operand 5 "memory_operand" ""))
16001 (use (match_operand:SI 3 "immediate_operand" ""))
16004 (clobber (match_operand 0 "register_operand" ""))
16005 (clobber (match_operand 1 "register_operand" ""))
16006 (clobber (match_dup 2))])]
16010 (define_insn "*cmpstrqi_1"
16012 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
16014 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16015 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
16017 (use (match_operand:SI 3 "immediate_operand" "i"))
16020 (clobber (match_operand:SI 0 "register_operand" "=S"))
16021 (clobber (match_operand:SI 1 "register_operand" "=D"))
16022 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16025 [(set_attr "type" "str")
16026 (set_attr "mode" "QI")
16027 (set_attr "prefix_rep" "1")])
16029 (define_insn "*cmpstrqi_rex_1"
16031 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
16033 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16034 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
16036 (use (match_operand:SI 3 "immediate_operand" "i"))
16039 (clobber (match_operand:DI 0 "register_operand" "=S"))
16040 (clobber (match_operand:DI 1 "register_operand" "=D"))
16041 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16044 [(set_attr "type" "str")
16045 (set_attr "mode" "QI")
16046 (set_attr "prefix_rep" "1")])
16048 (define_expand "strlensi"
16049 [(set (match_operand:SI 0 "register_operand" "")
16050 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
16051 (match_operand:QI 2 "immediate_operand" "")
16052 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16055 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16061 (define_expand "strlendi"
16062 [(set (match_operand:DI 0 "register_operand" "")
16063 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
16064 (match_operand:QI 2 "immediate_operand" "")
16065 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16068 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16074 (define_expand "strlenqi_1"
16075 [(parallel [(set (match_operand 0 "register_operand" "") (match_operand 2 "" ""))
16077 (clobber (match_operand 1 "register_operand" ""))
16078 (clobber (reg:CC 17))])]
16082 (define_insn "*strlenqi_1"
16083 [(set (match_operand:SI 0 "register_operand" "=&c")
16084 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
16085 (match_operand:QI 2 "register_operand" "a")
16086 (match_operand:SI 3 "immediate_operand" "i")
16087 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
16089 (clobber (match_operand:SI 1 "register_operand" "=D"))
16090 (clobber (reg:CC 17))]
16093 [(set_attr "type" "str")
16094 (set_attr "mode" "QI")
16095 (set_attr "prefix_rep" "1")])
16097 (define_insn "*strlenqi_rex_1"
16098 [(set (match_operand:DI 0 "register_operand" "=&c")
16099 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
16100 (match_operand:QI 2 "register_operand" "a")
16101 (match_operand:DI 3 "immediate_operand" "i")
16102 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
16104 (clobber (match_operand:DI 1 "register_operand" "=D"))
16105 (clobber (reg:CC 17))]
16108 [(set_attr "type" "str")
16109 (set_attr "mode" "QI")
16110 (set_attr "prefix_rep" "1")])
16112 ;; Peephole optimizations to clean up after cmpstr*. This should be
16113 ;; handled in combine, but it is not currently up to the task.
16114 ;; When used for their truth value, the cmpstr* expanders generate
16123 ;; The intermediate three instructions are unnecessary.
16125 ;; This one handles cmpstr*_nz_1...
16129 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16130 (mem:BLK (match_operand 5 "register_operand" ""))))
16131 (use (match_operand 6 "register_operand" ""))
16132 (use (match_operand:SI 3 "immediate_operand" ""))
16134 (clobber (match_operand 0 "register_operand" ""))
16135 (clobber (match_operand 1 "register_operand" ""))
16136 (clobber (match_operand 2 "register_operand" ""))])
16137 (set (match_operand:QI 7 "register_operand" "")
16138 (gtu:QI (reg:CC 17) (const_int 0)))
16139 (set (match_operand:QI 8 "register_operand" "")
16140 (ltu:QI (reg:CC 17) (const_int 0)))
16142 (compare (match_dup 7) (match_dup 8)))
16144 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16147 (compare:CC (mem:BLK (match_dup 4))
16148 (mem:BLK (match_dup 5))))
16149 (use (match_dup 6))
16150 (use (match_dup 3))
16152 (clobber (match_dup 0))
16153 (clobber (match_dup 1))
16154 (clobber (match_dup 2))])]
16157 ;; ...and this one handles cmpstr*_1.
16161 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
16163 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16164 (mem:BLK (match_operand 5 "register_operand" "")))
16166 (use (match_operand:SI 3 "immediate_operand" ""))
16169 (clobber (match_operand 0 "register_operand" ""))
16170 (clobber (match_operand 1 "register_operand" ""))
16171 (clobber (match_operand 2 "register_operand" ""))])
16172 (set (match_operand:QI 7 "register_operand" "")
16173 (gtu:QI (reg:CC 17) (const_int 0)))
16174 (set (match_operand:QI 8 "register_operand" "")
16175 (ltu:QI (reg:CC 17) (const_int 0)))
16177 (compare (match_dup 7) (match_dup 8)))
16179 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16182 (if_then_else:CC (ne (match_dup 6)
16184 (compare:CC (mem:BLK (match_dup 4))
16185 (mem:BLK (match_dup 5)))
16187 (use (match_dup 3))
16190 (clobber (match_dup 0))
16191 (clobber (match_dup 1))
16192 (clobber (match_dup 2))])]
16197 ;; Conditional move instructions.
16199 (define_expand "movdicc"
16200 [(set (match_operand:DI 0 "register_operand" "")
16201 (if_then_else:DI (match_operand 1 "comparison_operator" "")
16202 (match_operand:DI 2 "general_operand" "")
16203 (match_operand:DI 3 "general_operand" "")))]
16205 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16207 (define_insn "x86_movdicc_0_m1_rex64"
16208 [(set (match_operand:DI 0 "register_operand" "=r")
16209 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
16212 (clobber (reg:CC 17))]
16215 ; Since we don't have the proper number of operands for an alu insn,
16216 ; fill in all the blanks.
16217 [(set_attr "type" "alu")
16218 (set_attr "pent_pair" "pu")
16219 (set_attr "memory" "none")
16220 (set_attr "imm_disp" "false")
16221 (set_attr "mode" "DI")
16222 (set_attr "length_immediate" "0")])
16224 (define_insn "movdicc_c_rex64"
16225 [(set (match_operand:DI 0 "register_operand" "=r,r")
16226 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
16227 [(reg 17) (const_int 0)])
16228 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
16229 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
16230 "TARGET_64BIT && TARGET_CMOVE
16231 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16233 cmov%O2%C1\t{%2, %0|%0, %2}
16234 cmov%O2%c1\t{%3, %0|%0, %3}"
16235 [(set_attr "type" "icmov")
16236 (set_attr "mode" "DI")])
16238 (define_expand "movsicc"
16239 [(set (match_operand:SI 0 "register_operand" "")
16240 (if_then_else:SI (match_operand 1 "comparison_operator" "")
16241 (match_operand:SI 2 "general_operand" "")
16242 (match_operand:SI 3 "general_operand" "")))]
16244 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16246 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
16247 ;; the register first winds up with `sbbl $0,reg', which is also weird.
16248 ;; So just document what we're doing explicitly.
16250 (define_insn "x86_movsicc_0_m1"
16251 [(set (match_operand:SI 0 "register_operand" "=r")
16252 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
16255 (clobber (reg:CC 17))]
16258 ; Since we don't have the proper number of operands for an alu insn,
16259 ; fill in all the blanks.
16260 [(set_attr "type" "alu")
16261 (set_attr "pent_pair" "pu")
16262 (set_attr "memory" "none")
16263 (set_attr "imm_disp" "false")
16264 (set_attr "mode" "SI")
16265 (set_attr "length_immediate" "0")])
16267 (define_insn "*movsicc_noc"
16268 [(set (match_operand:SI 0 "register_operand" "=r,r")
16269 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
16270 [(reg 17) (const_int 0)])
16271 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
16272 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
16274 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16276 cmov%O2%C1\t{%2, %0|%0, %2}
16277 cmov%O2%c1\t{%3, %0|%0, %3}"
16278 [(set_attr "type" "icmov")
16279 (set_attr "mode" "SI")])
16281 (define_expand "movhicc"
16282 [(set (match_operand:HI 0 "register_operand" "")
16283 (if_then_else:HI (match_operand 1 "comparison_operator" "")
16284 (match_operand:HI 2 "general_operand" "")
16285 (match_operand:HI 3 "general_operand" "")))]
16286 "TARGET_HIMODE_MATH"
16287 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16289 (define_insn "*movhicc_noc"
16290 [(set (match_operand:HI 0 "register_operand" "=r,r")
16291 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
16292 [(reg 17) (const_int 0)])
16293 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
16294 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
16296 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16298 cmov%O2%C1\t{%2, %0|%0, %2}
16299 cmov%O2%c1\t{%3, %0|%0, %3}"
16300 [(set_attr "type" "icmov")
16301 (set_attr "mode" "HI")])
16303 (define_expand "movqicc"
16304 [(set (match_operand:QI 0 "register_operand" "")
16305 (if_then_else:QI (match_operand 1 "comparison_operator" "")
16306 (match_operand:QI 2 "general_operand" "")
16307 (match_operand:QI 3 "general_operand" "")))]
16308 "TARGET_QIMODE_MATH"
16309 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16311 (define_insn_and_split "*movqicc_noc"
16312 [(set (match_operand:QI 0 "register_operand" "=r,r")
16313 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
16314 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16315 (match_operand:QI 2 "register_operand" "r,0")
16316 (match_operand:QI 3 "register_operand" "0,r")))]
16317 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
16319 "&& reload_completed"
16320 [(set (match_dup 0)
16321 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16324 "operands[0] = gen_lowpart (SImode, operands[0]);
16325 operands[2] = gen_lowpart (SImode, operands[2]);
16326 operands[3] = gen_lowpart (SImode, operands[3]);"
16327 [(set_attr "type" "icmov")
16328 (set_attr "mode" "SI")])
16330 (define_expand "movsfcc"
16331 [(set (match_operand:SF 0 "register_operand" "")
16332 (if_then_else:SF (match_operand 1 "comparison_operator" "")
16333 (match_operand:SF 2 "register_operand" "")
16334 (match_operand:SF 3 "register_operand" "")))]
16336 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16338 (define_insn "*movsfcc_1"
16339 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
16340 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16341 [(reg 17) (const_int 0)])
16342 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
16343 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
16345 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16347 fcmov%F1\t{%2, %0|%0, %2}
16348 fcmov%f1\t{%3, %0|%0, %3}
16349 cmov%O2%C1\t{%2, %0|%0, %2}
16350 cmov%O2%c1\t{%3, %0|%0, %3}"
16351 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16352 (set_attr "mode" "SF,SF,SI,SI")])
16354 (define_expand "movdfcc"
16355 [(set (match_operand:DF 0 "register_operand" "")
16356 (if_then_else:DF (match_operand 1 "comparison_operator" "")
16357 (match_operand:DF 2 "register_operand" "")
16358 (match_operand:DF 3 "register_operand" "")))]
16360 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16362 (define_insn "*movdfcc_1"
16363 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
16364 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16365 [(reg 17) (const_int 0)])
16366 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
16367 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
16368 "!TARGET_64BIT && TARGET_CMOVE
16369 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16371 fcmov%F1\t{%2, %0|%0, %2}
16372 fcmov%f1\t{%3, %0|%0, %3}
16375 [(set_attr "type" "fcmov,fcmov,multi,multi")
16376 (set_attr "mode" "DF")])
16378 (define_insn "*movdfcc_1_rex64"
16379 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
16380 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16381 [(reg 17) (const_int 0)])
16382 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
16383 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
16384 "TARGET_64BIT && TARGET_CMOVE
16385 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16387 fcmov%F1\t{%2, %0|%0, %2}
16388 fcmov%f1\t{%3, %0|%0, %3}
16389 cmov%O2%C1\t{%2, %0|%0, %2}
16390 cmov%O2%c1\t{%3, %0|%0, %3}"
16391 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16392 (set_attr "mode" "DF")])
16395 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
16396 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16397 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16398 (match_operand:DF 2 "nonimmediate_operand" "")
16399 (match_operand:DF 3 "nonimmediate_operand" "")))]
16400 "!TARGET_64BIT && reload_completed"
16401 [(set (match_dup 2)
16402 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16406 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16409 "split_di (operands+2, 1, operands+5, operands+6);
16410 split_di (operands+3, 1, operands+7, operands+8);
16411 split_di (operands, 1, operands+2, operands+3);")
16413 (define_expand "movxfcc"
16414 [(set (match_operand:XF 0 "register_operand" "")
16415 (if_then_else:XF (match_operand 1 "comparison_operator" "")
16416 (match_operand:XF 2 "register_operand" "")
16417 (match_operand:XF 3 "register_operand" "")))]
16419 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16421 (define_insn "*movxfcc_1"
16422 [(set (match_operand:XF 0 "register_operand" "=f,f")
16423 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
16424 [(reg 17) (const_int 0)])
16425 (match_operand:XF 2 "register_operand" "f,0")
16426 (match_operand:XF 3 "register_operand" "0,f")))]
16429 fcmov%F1\t{%2, %0|%0, %2}
16430 fcmov%f1\t{%3, %0|%0, %3}"
16431 [(set_attr "type" "fcmov")
16432 (set_attr "mode" "XF")])
16434 (define_expand "minsf3"
16436 (set (match_operand:SF 0 "register_operand" "")
16437 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16438 (match_operand:SF 2 "nonimmediate_operand" ""))
16441 (clobber (reg:CC 17))])]
16445 (define_insn "*minsf"
16446 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16447 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
16448 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16451 (clobber (reg:CC 17))]
16452 "TARGET_SSE && TARGET_IEEE_FP"
16455 (define_insn "*minsf_nonieee"
16456 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16457 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16458 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16461 (clobber (reg:CC 17))]
16462 "TARGET_SSE && !TARGET_IEEE_FP
16463 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16467 [(set (match_operand:SF 0 "register_operand" "")
16468 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16469 (match_operand:SF 2 "nonimmediate_operand" ""))
16470 (match_operand:SF 3 "register_operand" "")
16471 (match_operand:SF 4 "nonimmediate_operand" "")))
16472 (clobber (reg:CC 17))]
16473 "SSE_REG_P (operands[0]) && reload_completed
16474 && ((operands_match_p (operands[1], operands[3])
16475 && operands_match_p (operands[2], operands[4]))
16476 || (operands_match_p (operands[1], operands[4])
16477 && operands_match_p (operands[2], operands[3])))"
16478 [(set (match_dup 0)
16479 (if_then_else:SF (lt (match_dup 1)
16484 ;; Conditional addition patterns
16485 (define_expand "addqicc"
16486 [(match_operand:QI 0 "register_operand" "")
16487 (match_operand 1 "comparison_operator" "")
16488 (match_operand:QI 2 "register_operand" "")
16489 (match_operand:QI 3 "const_int_operand" "")]
16491 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16493 (define_expand "addhicc"
16494 [(match_operand:HI 0 "register_operand" "")
16495 (match_operand 1 "comparison_operator" "")
16496 (match_operand:HI 2 "register_operand" "")
16497 (match_operand:HI 3 "const_int_operand" "")]
16499 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16501 (define_expand "addsicc"
16502 [(match_operand:SI 0 "register_operand" "")
16503 (match_operand 1 "comparison_operator" "")
16504 (match_operand:SI 2 "register_operand" "")
16505 (match_operand:SI 3 "const_int_operand" "")]
16507 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16509 (define_expand "adddicc"
16510 [(match_operand:DI 0 "register_operand" "")
16511 (match_operand 1 "comparison_operator" "")
16512 (match_operand:DI 2 "register_operand" "")
16513 (match_operand:DI 3 "const_int_operand" "")]
16515 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16517 ;; We can't represent the LT test directly. Do this by swapping the operands.
16520 [(set (match_operand:SF 0 "fp_register_operand" "")
16521 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16522 (match_operand:SF 2 "register_operand" ""))
16523 (match_operand:SF 3 "register_operand" "")
16524 (match_operand:SF 4 "register_operand" "")))
16525 (clobber (reg:CC 17))]
16527 && ((operands_match_p (operands[1], operands[3])
16528 && operands_match_p (operands[2], operands[4]))
16529 || (operands_match_p (operands[1], operands[4])
16530 && operands_match_p (operands[2], operands[3])))"
16531 [(set (reg:CCFP 17)
16532 (compare:CCFP (match_dup 2)
16535 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
16539 (define_insn "*minsf_sse"
16540 [(set (match_operand:SF 0 "register_operand" "=x")
16541 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
16542 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16545 "TARGET_SSE && reload_completed"
16546 "minss\t{%2, %0|%0, %2}"
16547 [(set_attr "type" "sse")
16548 (set_attr "mode" "SF")])
16550 (define_expand "mindf3"
16552 (set (match_operand:DF 0 "register_operand" "")
16553 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16554 (match_operand:DF 2 "nonimmediate_operand" ""))
16557 (clobber (reg:CC 17))])]
16558 "TARGET_SSE2 && TARGET_SSE_MATH"
16561 (define_insn "*mindf"
16562 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16563 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16564 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
16567 (clobber (reg:CC 17))]
16568 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
16571 (define_insn "*mindf_nonieee"
16572 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16573 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16574 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16577 (clobber (reg:CC 17))]
16578 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16579 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16583 [(set (match_operand:DF 0 "register_operand" "")
16584 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16585 (match_operand:DF 2 "nonimmediate_operand" ""))
16586 (match_operand:DF 3 "register_operand" "")
16587 (match_operand:DF 4 "nonimmediate_operand" "")))
16588 (clobber (reg:CC 17))]
16589 "SSE_REG_P (operands[0]) && reload_completed
16590 && ((operands_match_p (operands[1], operands[3])
16591 && operands_match_p (operands[2], operands[4]))
16592 || (operands_match_p (operands[1], operands[4])
16593 && operands_match_p (operands[2], operands[3])))"
16594 [(set (match_dup 0)
16595 (if_then_else:DF (lt (match_dup 1)
16600 ;; We can't represent the LT test directly. Do this by swapping the operands.
16602 [(set (match_operand:DF 0 "fp_register_operand" "")
16603 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16604 (match_operand:DF 2 "register_operand" ""))
16605 (match_operand:DF 3 "register_operand" "")
16606 (match_operand:DF 4 "register_operand" "")))
16607 (clobber (reg:CC 17))]
16609 && ((operands_match_p (operands[1], operands[3])
16610 && operands_match_p (operands[2], operands[4]))
16611 || (operands_match_p (operands[1], operands[4])
16612 && operands_match_p (operands[2], operands[3])))"
16613 [(set (reg:CCFP 17)
16614 (compare:CCFP (match_dup 2)
16617 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
16621 (define_insn "*mindf_sse"
16622 [(set (match_operand:DF 0 "register_operand" "=Y")
16623 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
16624 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16627 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
16628 "minsd\t{%2, %0|%0, %2}"
16629 [(set_attr "type" "sse")
16630 (set_attr "mode" "DF")])
16632 (define_expand "maxsf3"
16634 (set (match_operand:SF 0 "register_operand" "")
16635 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16636 (match_operand:SF 2 "nonimmediate_operand" ""))
16639 (clobber (reg:CC 17))])]
16643 (define_insn "*maxsf"
16644 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16645 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
16646 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16649 (clobber (reg:CC 17))]
16650 "TARGET_SSE && TARGET_IEEE_FP"
16653 (define_insn "*maxsf_nonieee"
16654 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16655 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16656 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16659 (clobber (reg:CC 17))]
16660 "TARGET_SSE && !TARGET_IEEE_FP
16661 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16665 [(set (match_operand:SF 0 "register_operand" "")
16666 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16667 (match_operand:SF 2 "nonimmediate_operand" ""))
16668 (match_operand:SF 3 "register_operand" "")
16669 (match_operand:SF 4 "nonimmediate_operand" "")))
16670 (clobber (reg:CC 17))]
16671 "SSE_REG_P (operands[0]) && reload_completed
16672 && ((operands_match_p (operands[1], operands[3])
16673 && operands_match_p (operands[2], operands[4]))
16674 || (operands_match_p (operands[1], operands[4])
16675 && operands_match_p (operands[2], operands[3])))"
16676 [(set (match_dup 0)
16677 (if_then_else:SF (gt (match_dup 1)
16683 [(set (match_operand:SF 0 "fp_register_operand" "")
16684 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
16685 (match_operand:SF 2 "register_operand" ""))
16686 (match_operand:SF 3 "register_operand" "")
16687 (match_operand:SF 4 "register_operand" "")))
16688 (clobber (reg:CC 17))]
16690 && ((operands_match_p (operands[1], operands[3])
16691 && operands_match_p (operands[2], operands[4]))
16692 || (operands_match_p (operands[1], operands[4])
16693 && operands_match_p (operands[2], operands[3])))"
16694 [(set (reg:CCFP 17)
16695 (compare:CCFP (match_dup 1)
16698 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
16702 (define_insn "*maxsf_sse"
16703 [(set (match_operand:SF 0 "register_operand" "=x")
16704 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
16705 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16708 "TARGET_SSE && reload_completed"
16709 "maxss\t{%2, %0|%0, %2}"
16710 [(set_attr "type" "sse")
16711 (set_attr "mode" "SF")])
16713 (define_expand "maxdf3"
16715 (set (match_operand:DF 0 "register_operand" "")
16716 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16717 (match_operand:DF 2 "nonimmediate_operand" ""))
16720 (clobber (reg:CC 17))])]
16721 "TARGET_SSE2 && TARGET_SSE_MATH"
16724 (define_insn "*maxdf"
16725 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16726 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16727 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
16730 (clobber (reg:CC 17))]
16731 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
16734 (define_insn "*maxdf_nonieee"
16735 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16736 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16737 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16740 (clobber (reg:CC 17))]
16741 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16742 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16746 [(set (match_operand:DF 0 "register_operand" "")
16747 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16748 (match_operand:DF 2 "nonimmediate_operand" ""))
16749 (match_operand:DF 3 "register_operand" "")
16750 (match_operand:DF 4 "nonimmediate_operand" "")))
16751 (clobber (reg:CC 17))]
16752 "SSE_REG_P (operands[0]) && reload_completed
16753 && ((operands_match_p (operands[1], operands[3])
16754 && operands_match_p (operands[2], operands[4]))
16755 || (operands_match_p (operands[1], operands[4])
16756 && operands_match_p (operands[2], operands[3])))"
16757 [(set (match_dup 0)
16758 (if_then_else:DF (gt (match_dup 1)
16764 [(set (match_operand:DF 0 "fp_register_operand" "")
16765 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
16766 (match_operand:DF 2 "register_operand" ""))
16767 (match_operand:DF 3 "register_operand" "")
16768 (match_operand:DF 4 "register_operand" "")))
16769 (clobber (reg:CC 17))]
16771 && ((operands_match_p (operands[1], operands[3])
16772 && operands_match_p (operands[2], operands[4]))
16773 || (operands_match_p (operands[1], operands[4])
16774 && operands_match_p (operands[2], operands[3])))"
16775 [(set (reg:CCFP 17)
16776 (compare:CCFP (match_dup 1)
16779 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
16783 (define_insn "*maxdf_sse"
16784 [(set (match_operand:DF 0 "register_operand" "=Y")
16785 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
16786 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
16789 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
16790 "maxsd\t{%2, %0|%0, %2}"
16791 [(set_attr "type" "sse")
16792 (set_attr "mode" "DF")])
16794 ;; Misc patterns (?)
16796 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
16797 ;; Otherwise there will be nothing to keep
16799 ;; [(set (reg ebp) (reg esp))]
16800 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
16801 ;; (clobber (eflags)]
16802 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
16804 ;; in proper program order.
16805 (define_insn "pro_epilogue_adjust_stack_1"
16806 [(set (match_operand:SI 0 "register_operand" "=r,r")
16807 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
16808 (match_operand:SI 2 "immediate_operand" "i,i")))
16809 (clobber (reg:CC 17))
16810 (clobber (mem:BLK (scratch)))]
16813 switch (get_attr_type (insn))
16816 return "mov{l}\t{%1, %0|%0, %1}";
16819 if (GET_CODE (operands[2]) == CONST_INT
16820 && (INTVAL (operands[2]) == 128
16821 || (INTVAL (operands[2]) < 0
16822 && INTVAL (operands[2]) != -128)))
16824 operands[2] = GEN_INT (-INTVAL (operands[2]));
16825 return "sub{l}\t{%2, %0|%0, %2}";
16827 return "add{l}\t{%2, %0|%0, %2}";
16830 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16831 return "lea{l}\t{%a2, %0|%0, %a2}";
16837 [(set (attr "type")
16838 (cond [(eq_attr "alternative" "0")
16839 (const_string "alu")
16840 (match_operand:SI 2 "const0_operand" "")
16841 (const_string "imov")
16843 (const_string "lea")))
16844 (set_attr "mode" "SI")])
16846 (define_insn "pro_epilogue_adjust_stack_rex64"
16847 [(set (match_operand:DI 0 "register_operand" "=r,r")
16848 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16849 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
16850 (clobber (reg:CC 17))
16851 (clobber (mem:BLK (scratch)))]
16854 switch (get_attr_type (insn))
16857 return "mov{q}\t{%1, %0|%0, %1}";
16860 if (GET_CODE (operands[2]) == CONST_INT
16861 /* Avoid overflows. */
16862 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
16863 && (INTVAL (operands[2]) == 128
16864 || (INTVAL (operands[2]) < 0
16865 && INTVAL (operands[2]) != -128)))
16867 operands[2] = GEN_INT (-INTVAL (operands[2]));
16868 return "sub{q}\t{%2, %0|%0, %2}";
16870 return "add{q}\t{%2, %0|%0, %2}";
16873 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
16874 return "lea{q}\t{%a2, %0|%0, %a2}";
16880 [(set (attr "type")
16881 (cond [(eq_attr "alternative" "0")
16882 (const_string "alu")
16883 (match_operand:DI 2 "const0_operand" "")
16884 (const_string "imov")
16886 (const_string "lea")))
16887 (set_attr "mode" "DI")])
16889 (define_insn "pro_epilogue_adjust_stack_rex64_2"
16890 [(set (match_operand:DI 0 "register_operand" "=r,r")
16891 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
16892 (match_operand:DI 3 "immediate_operand" "i,i")))
16893 (use (match_operand:DI 2 "register_operand" "r,r"))
16894 (clobber (reg:CC 17))
16895 (clobber (mem:BLK (scratch)))]
16898 switch (get_attr_type (insn))
16901 return "add{q}\t{%2, %0|%0, %2}";
16904 operands[2] = gen_rtx_PLUS (DImode, operands[1], operands[2]);
16905 return "lea{q}\t{%a2, %0|%0, %a2}";
16911 [(set_attr "type" "alu,lea")
16912 (set_attr "mode" "DI")])
16914 ;; Placeholder for the conditional moves. This one is split either to SSE
16915 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
16916 ;; fact is that compares supported by the cmp??ss instructions are exactly
16917 ;; swapped of those supported by cmove sequence.
16918 ;; The EQ/NE comparisons also needs bit care, since they are not directly
16919 ;; supported by i387 comparisons and we do need to emit two conditional moves
16922 (define_insn "sse_movsfcc"
16923 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
16924 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
16925 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
16926 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
16927 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
16928 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
16929 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16930 (clobber (reg:CC 17))]
16932 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16933 /* Avoid combine from being smart and converting min/max
16934 instruction patterns into conditional moves. */
16935 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
16936 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
16937 || !rtx_equal_p (operands[4], operands[2])
16938 || !rtx_equal_p (operands[5], operands[3]))
16939 && (!TARGET_IEEE_FP
16940 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16943 (define_insn "sse_movsfcc_eq"
16944 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
16945 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
16946 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
16947 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
16948 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
16949 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
16950 (clobber (reg:CC 17))]
16952 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16955 (define_insn "sse_movdfcc"
16956 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
16957 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
16958 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
16959 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
16960 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
16961 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
16962 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
16963 (clobber (reg:CC 17))]
16965 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
16966 /* Avoid combine from being smart and converting min/max
16967 instruction patterns into conditional moves. */
16968 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
16969 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
16970 || !rtx_equal_p (operands[4], operands[2])
16971 || !rtx_equal_p (operands[5], operands[3]))
16972 && (!TARGET_IEEE_FP
16973 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
16976 (define_insn "sse_movdfcc_eq"
16977 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
16978 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
16979 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
16980 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
16981 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
16982 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
16983 (clobber (reg:CC 17))]
16985 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16988 ;; For non-sse moves just expand the usual cmove sequence.
16990 [(set (match_operand 0 "register_operand" "")
16991 (if_then_else (match_operator 1 "comparison_operator"
16992 [(match_operand 4 "nonimmediate_operand" "")
16993 (match_operand 5 "register_operand" "")])
16994 (match_operand 2 "nonimmediate_operand" "")
16995 (match_operand 3 "nonimmediate_operand" "")))
16996 (clobber (match_operand 6 "" ""))
16997 (clobber (reg:CC 17))]
16998 "!SSE_REG_P (operands[0]) && reload_completed
16999 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
17002 ix86_compare_op0 = operands[5];
17003 ix86_compare_op1 = operands[4];
17004 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
17005 VOIDmode, operands[5], operands[4]);
17006 ix86_expand_fp_movcc (operands);
17010 ;; Split SSE based conditional move into sequence:
17011 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
17012 ;; and op2, op0 - zero op2 if comparison was false
17013 ;; nand op0, op3 - load op3 to op0 if comparison was false
17014 ;; or op2, op0 - get the nonzero one into the result.
17016 [(set (match_operand 0 "register_operand" "")
17017 (if_then_else (match_operator 1 "sse_comparison_operator"
17018 [(match_operand 4 "register_operand" "")
17019 (match_operand 5 "nonimmediate_operand" "")])
17020 (match_operand 2 "register_operand" "")
17021 (match_operand 3 "register_operand" "")))
17022 (clobber (match_operand 6 "" ""))
17023 (clobber (reg:CC 17))]
17024 "SSE_REG_P (operands[0]) && reload_completed"
17025 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
17026 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
17027 (subreg:TI (match_dup 4) 0)))
17028 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
17029 (subreg:TI (match_dup 3) 0)))
17030 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
17031 (subreg:TI (match_dup 7) 0)))]
17033 if (GET_MODE (operands[2]) == DFmode
17034 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
17036 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17037 emit_insn (gen_sse2_unpcklpd (op, op, op));
17038 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17039 emit_insn (gen_sse2_unpcklpd (op, op, op));
17042 /* If op2 == op3, op3 would be clobbered before it is used. */
17043 if (operands_match_p (operands[2], operands[3]))
17045 emit_move_insn (operands[0], operands[2]);
17049 PUT_MODE (operands[1], GET_MODE (operands[0]));
17050 if (operands_match_p (operands[0], operands[4]))
17051 operands[6] = operands[4], operands[7] = operands[2];
17053 operands[6] = operands[2], operands[7] = operands[4];
17056 ;; Special case of conditional move we can handle effectively.
17057 ;; Do not brother with the integer/floating point case, since these are
17058 ;; bot considerably slower, unlike in the generic case.
17059 (define_insn "*sse_movsfcc_const0_1"
17060 [(set (match_operand:SF 0 "register_operand" "=&x")
17061 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17062 [(match_operand:SF 4 "register_operand" "0")
17063 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17064 (match_operand:SF 2 "register_operand" "x")
17065 (match_operand:SF 3 "const0_operand" "X")))]
17069 (define_insn "*sse_movsfcc_const0_2"
17070 [(set (match_operand:SF 0 "register_operand" "=&x")
17071 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17072 [(match_operand:SF 4 "register_operand" "0")
17073 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17074 (match_operand:SF 2 "const0_operand" "X")
17075 (match_operand:SF 3 "register_operand" "x")))]
17079 (define_insn "*sse_movsfcc_const0_3"
17080 [(set (match_operand:SF 0 "register_operand" "=&x")
17081 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17082 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17083 (match_operand:SF 5 "register_operand" "0")])
17084 (match_operand:SF 2 "register_operand" "x")
17085 (match_operand:SF 3 "const0_operand" "X")))]
17089 (define_insn "*sse_movsfcc_const0_4"
17090 [(set (match_operand:SF 0 "register_operand" "=&x")
17091 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17092 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17093 (match_operand:SF 5 "register_operand" "0")])
17094 (match_operand:SF 2 "const0_operand" "X")
17095 (match_operand:SF 3 "register_operand" "x")))]
17099 (define_insn "*sse_movdfcc_const0_1"
17100 [(set (match_operand:DF 0 "register_operand" "=&Y")
17101 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17102 [(match_operand:DF 4 "register_operand" "0")
17103 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17104 (match_operand:DF 2 "register_operand" "Y")
17105 (match_operand:DF 3 "const0_operand" "X")))]
17109 (define_insn "*sse_movdfcc_const0_2"
17110 [(set (match_operand:DF 0 "register_operand" "=&Y")
17111 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17112 [(match_operand:DF 4 "register_operand" "0")
17113 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17114 (match_operand:DF 2 "const0_operand" "X")
17115 (match_operand:DF 3 "register_operand" "Y")))]
17119 (define_insn "*sse_movdfcc_const0_3"
17120 [(set (match_operand:DF 0 "register_operand" "=&Y")
17121 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17122 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17123 (match_operand:DF 5 "register_operand" "0")])
17124 (match_operand:DF 2 "register_operand" "Y")
17125 (match_operand:DF 3 "const0_operand" "X")))]
17129 (define_insn "*sse_movdfcc_const0_4"
17130 [(set (match_operand:DF 0 "register_operand" "=&Y")
17131 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17132 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17133 (match_operand:DF 5 "register_operand" "0")])
17134 (match_operand:DF 2 "const0_operand" "X")
17135 (match_operand:DF 3 "register_operand" "Y")))]
17140 [(set (match_operand 0 "register_operand" "")
17141 (if_then_else (match_operator 1 "comparison_operator"
17142 [(match_operand 4 "nonimmediate_operand" "")
17143 (match_operand 5 "nonimmediate_operand" "")])
17144 (match_operand 2 "nonmemory_operand" "")
17145 (match_operand 3 "nonmemory_operand" "")))]
17146 "SSE_REG_P (operands[0]) && reload_completed
17147 && (const0_operand (operands[2], GET_MODE (operands[0]))
17148 || const0_operand (operands[3], GET_MODE (operands[0])))"
17149 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
17150 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
17153 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
17154 && GET_MODE (operands[2]) == DFmode)
17156 if (REG_P (operands[2]))
17158 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17159 emit_insn (gen_sse2_unpcklpd (op, op, op));
17161 if (REG_P (operands[3]))
17163 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17164 emit_insn (gen_sse2_unpcklpd (op, op, op));
17167 PUT_MODE (operands[1], GET_MODE (operands[0]));
17168 if (!sse_comparison_operator (operands[1], VOIDmode)
17169 || !rtx_equal_p (operands[0], operands[4]))
17171 rtx tmp = operands[5];
17172 operands[5] = operands[4];
17174 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
17176 if (!rtx_equal_p (operands[0], operands[4]))
17178 if (const0_operand (operands[2], GET_MODE (operands[0])))
17180 operands[7] = operands[3];
17181 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
17186 operands[7] = operands[2];
17187 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
17189 operands[7] = simplify_gen_subreg (TImode, operands[7],
17190 GET_MODE (operands[7]), 0);
17193 (define_expand "allocate_stack_worker"
17194 [(match_operand:SI 0 "register_operand" "")]
17195 "TARGET_STACK_PROBE"
17197 if (reload_completed)
17200 emit_insn (gen_allocate_stack_worker_rex64_postreload (operands[0]));
17202 emit_insn (gen_allocate_stack_worker_postreload (operands[0]));
17207 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
17209 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
17214 (define_insn "allocate_stack_worker_1"
17215 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17216 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
17217 (clobber (match_scratch:SI 1 "=0"))
17218 (clobber (reg:CC 17))]
17219 "!TARGET_64BIT && TARGET_STACK_PROBE"
17221 [(set_attr "type" "multi")
17222 (set_attr "length" "5")])
17224 (define_expand "allocate_stack_worker_postreload"
17225 [(parallel [(unspec:SI [(match_operand:SI 0 "register_operand" "a")]
17226 UNSPEC_STACK_PROBE)
17227 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
17228 (clobber (match_dup 0))
17229 (clobber (reg:CC 17))])]
17233 (define_insn "allocate_stack_worker_rex64"
17234 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17235 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
17236 (clobber (match_scratch:DI 1 "=0"))
17237 (clobber (reg:CC 17))]
17238 "TARGET_64BIT && TARGET_STACK_PROBE"
17240 [(set_attr "type" "multi")
17241 (set_attr "length" "5")])
17243 (define_expand "allocate_stack_worker_rex64_postreload"
17244 [(parallel [(unspec:DI [(match_operand:DI 0 "register_operand" "a")]
17245 UNSPEC_STACK_PROBE)
17246 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
17247 (clobber (match_dup 0))
17248 (clobber (reg:CC 17))])]
17252 (define_expand "allocate_stack"
17253 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
17254 (minus:SI (reg:SI 7)
17255 (match_operand:SI 1 "general_operand" "")))
17256 (clobber (reg:CC 17))])
17257 (parallel [(set (reg:SI 7)
17258 (minus:SI (reg:SI 7) (match_dup 1)))
17259 (clobber (reg:CC 17))])]
17260 "TARGET_STACK_PROBE"
17262 #ifdef CHECK_STACK_LIMIT
17263 if (GET_CODE (operands[1]) == CONST_INT
17264 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
17265 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
17269 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
17272 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
17276 (define_expand "builtin_setjmp_receiver"
17277 [(label_ref (match_operand 0 "" ""))]
17278 "!TARGET_64BIT && flag_pic"
17280 emit_insn (gen_set_got (pic_offset_table_rtx));
17284 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
17287 [(set (match_operand 0 "register_operand" "")
17288 (match_operator 3 "promotable_binary_operator"
17289 [(match_operand 1 "register_operand" "")
17290 (match_operand 2 "aligned_operand" "")]))
17291 (clobber (reg:CC 17))]
17292 "! TARGET_PARTIAL_REG_STALL && reload_completed
17293 && ((GET_MODE (operands[0]) == HImode
17294 && ((!optimize_size && !TARGET_FAST_PREFIX)
17295 || GET_CODE (operands[2]) != CONST_INT
17296 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
17297 || (GET_MODE (operands[0]) == QImode
17298 && (TARGET_PROMOTE_QImode || optimize_size)))"
17299 [(parallel [(set (match_dup 0)
17300 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17301 (clobber (reg:CC 17))])]
17302 "operands[0] = gen_lowpart (SImode, operands[0]);
17303 operands[1] = gen_lowpart (SImode, operands[1]);
17304 if (GET_CODE (operands[3]) != ASHIFT)
17305 operands[2] = gen_lowpart (SImode, operands[2]);
17306 PUT_MODE (operands[3], SImode);")
17308 ; Promote the QImode tests, as i386 has encoding of the AND
17309 ; instruction with 32-bit sign-extended immediate and thus the
17310 ; instruction size is unchanged, except in the %eax case for
17311 ; which it is increased by one byte, hence the ! optimize_size.
17314 (compare (and (match_operand 1 "aligned_operand" "")
17315 (match_operand 2 "const_int_operand" ""))
17317 (set (match_operand 0 "register_operand" "")
17318 (and (match_dup 1) (match_dup 2)))]
17319 "! TARGET_PARTIAL_REG_STALL && reload_completed
17320 /* Ensure that the operand will remain sign-extended immediate. */
17321 && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)
17323 && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
17324 || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
17325 [(parallel [(set (reg:CCNO 17)
17326 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
17329 (and:SI (match_dup 1) (match_dup 2)))])]
17331 = gen_int_mode (INTVAL (operands[2])
17332 & GET_MODE_MASK (GET_MODE (operands[0])),
17334 operands[0] = gen_lowpart (SImode, operands[0]);
17335 operands[1] = gen_lowpart (SImode, operands[1]);")
17337 ; Don't promote the QImode tests, as i386 doesn't have encoding of
17338 ; the TEST instruction with 32-bit sign-extended immediate and thus
17339 ; the instruction size would at least double, which is not what we
17340 ; want even with ! optimize_size.
17343 (compare (and (match_operand:HI 0 "aligned_operand" "")
17344 (match_operand:HI 1 "const_int_operand" ""))
17346 "! TARGET_PARTIAL_REG_STALL && reload_completed
17347 /* Ensure that the operand will remain sign-extended immediate. */
17348 && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
17349 && ! TARGET_FAST_PREFIX
17350 && ! optimize_size"
17351 [(set (reg:CCNO 17)
17352 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
17355 = gen_int_mode (INTVAL (operands[1])
17356 & GET_MODE_MASK (GET_MODE (operands[0])),
17358 operands[0] = gen_lowpart (SImode, operands[0]);")
17361 [(set (match_operand 0 "register_operand" "")
17362 (neg (match_operand 1 "register_operand" "")))
17363 (clobber (reg:CC 17))]
17364 "! TARGET_PARTIAL_REG_STALL && reload_completed
17365 && (GET_MODE (operands[0]) == HImode
17366 || (GET_MODE (operands[0]) == QImode
17367 && (TARGET_PROMOTE_QImode || optimize_size)))"
17368 [(parallel [(set (match_dup 0)
17369 (neg:SI (match_dup 1)))
17370 (clobber (reg:CC 17))])]
17371 "operands[0] = gen_lowpart (SImode, operands[0]);
17372 operands[1] = gen_lowpart (SImode, operands[1]);")
17375 [(set (match_operand 0 "register_operand" "")
17376 (not (match_operand 1 "register_operand" "")))]
17377 "! TARGET_PARTIAL_REG_STALL && reload_completed
17378 && (GET_MODE (operands[0]) == HImode
17379 || (GET_MODE (operands[0]) == QImode
17380 && (TARGET_PROMOTE_QImode || optimize_size)))"
17381 [(set (match_dup 0)
17382 (not:SI (match_dup 1)))]
17383 "operands[0] = gen_lowpart (SImode, operands[0]);
17384 operands[1] = gen_lowpart (SImode, operands[1]);")
17387 [(set (match_operand 0 "register_operand" "")
17388 (if_then_else (match_operator 1 "comparison_operator"
17389 [(reg 17) (const_int 0)])
17390 (match_operand 2 "register_operand" "")
17391 (match_operand 3 "register_operand" "")))]
17392 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
17393 && (GET_MODE (operands[0]) == HImode
17394 || (GET_MODE (operands[0]) == QImode
17395 && (TARGET_PROMOTE_QImode || optimize_size)))"
17396 [(set (match_dup 0)
17397 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
17398 "operands[0] = gen_lowpart (SImode, operands[0]);
17399 operands[2] = gen_lowpart (SImode, operands[2]);
17400 operands[3] = gen_lowpart (SImode, operands[3]);")
17403 ;; RTL Peephole optimizations, run before sched2. These primarily look to
17404 ;; transform a complex memory operation into two memory to register operations.
17406 ;; Don't push memory operands
17408 [(set (match_operand:SI 0 "push_operand" "")
17409 (match_operand:SI 1 "memory_operand" ""))
17410 (match_scratch:SI 2 "r")]
17411 "! optimize_size && ! TARGET_PUSH_MEMORY"
17412 [(set (match_dup 2) (match_dup 1))
17413 (set (match_dup 0) (match_dup 2))]
17417 [(set (match_operand:DI 0 "push_operand" "")
17418 (match_operand:DI 1 "memory_operand" ""))
17419 (match_scratch:DI 2 "r")]
17420 "! optimize_size && ! TARGET_PUSH_MEMORY"
17421 [(set (match_dup 2) (match_dup 1))
17422 (set (match_dup 0) (match_dup 2))]
17425 ;; We need to handle SFmode only, because DFmode and XFmode is split to
17428 [(set (match_operand:SF 0 "push_operand" "")
17429 (match_operand:SF 1 "memory_operand" ""))
17430 (match_scratch:SF 2 "r")]
17431 "! optimize_size && ! TARGET_PUSH_MEMORY"
17432 [(set (match_dup 2) (match_dup 1))
17433 (set (match_dup 0) (match_dup 2))]
17437 [(set (match_operand:HI 0 "push_operand" "")
17438 (match_operand:HI 1 "memory_operand" ""))
17439 (match_scratch:HI 2 "r")]
17440 "! optimize_size && ! TARGET_PUSH_MEMORY"
17441 [(set (match_dup 2) (match_dup 1))
17442 (set (match_dup 0) (match_dup 2))]
17446 [(set (match_operand:QI 0 "push_operand" "")
17447 (match_operand:QI 1 "memory_operand" ""))
17448 (match_scratch:QI 2 "q")]
17449 "! optimize_size && ! TARGET_PUSH_MEMORY"
17450 [(set (match_dup 2) (match_dup 1))
17451 (set (match_dup 0) (match_dup 2))]
17454 ;; Don't move an immediate directly to memory when the instruction
17457 [(match_scratch:SI 1 "r")
17458 (set (match_operand:SI 0 "memory_operand" "")
17461 && ! TARGET_USE_MOV0
17462 && TARGET_SPLIT_LONG_MOVES
17463 && get_attr_length (insn) >= ix86_cost->large_insn
17464 && peep2_regno_dead_p (0, FLAGS_REG)"
17465 [(parallel [(set (match_dup 1) (const_int 0))
17466 (clobber (reg:CC 17))])
17467 (set (match_dup 0) (match_dup 1))]
17471 [(match_scratch:HI 1 "r")
17472 (set (match_operand:HI 0 "memory_operand" "")
17475 && ! TARGET_USE_MOV0
17476 && TARGET_SPLIT_LONG_MOVES
17477 && get_attr_length (insn) >= ix86_cost->large_insn
17478 && peep2_regno_dead_p (0, FLAGS_REG)"
17479 [(parallel [(set (match_dup 2) (const_int 0))
17480 (clobber (reg:CC 17))])
17481 (set (match_dup 0) (match_dup 1))]
17482 "operands[2] = gen_lowpart (SImode, operands[1]);")
17485 [(match_scratch:QI 1 "q")
17486 (set (match_operand:QI 0 "memory_operand" "")
17489 && ! TARGET_USE_MOV0
17490 && TARGET_SPLIT_LONG_MOVES
17491 && get_attr_length (insn) >= ix86_cost->large_insn
17492 && peep2_regno_dead_p (0, FLAGS_REG)"
17493 [(parallel [(set (match_dup 2) (const_int 0))
17494 (clobber (reg:CC 17))])
17495 (set (match_dup 0) (match_dup 1))]
17496 "operands[2] = gen_lowpart (SImode, operands[1]);")
17499 [(match_scratch:SI 2 "r")
17500 (set (match_operand:SI 0 "memory_operand" "")
17501 (match_operand:SI 1 "immediate_operand" ""))]
17503 && get_attr_length (insn) >= ix86_cost->large_insn
17504 && TARGET_SPLIT_LONG_MOVES"
17505 [(set (match_dup 2) (match_dup 1))
17506 (set (match_dup 0) (match_dup 2))]
17510 [(match_scratch:HI 2 "r")
17511 (set (match_operand:HI 0 "memory_operand" "")
17512 (match_operand:HI 1 "immediate_operand" ""))]
17513 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17514 && TARGET_SPLIT_LONG_MOVES"
17515 [(set (match_dup 2) (match_dup 1))
17516 (set (match_dup 0) (match_dup 2))]
17520 [(match_scratch:QI 2 "q")
17521 (set (match_operand:QI 0 "memory_operand" "")
17522 (match_operand:QI 1 "immediate_operand" ""))]
17523 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17524 && TARGET_SPLIT_LONG_MOVES"
17525 [(set (match_dup 2) (match_dup 1))
17526 (set (match_dup 0) (match_dup 2))]
17529 ;; Don't compare memory with zero, load and use a test instead.
17532 (compare (match_operand:SI 0 "memory_operand" "")
17534 (match_scratch:SI 3 "r")]
17535 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
17536 [(set (match_dup 3) (match_dup 0))
17537 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
17540 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
17541 ;; Don't split NOTs with a displacement operand, because resulting XOR
17542 ;; will not be pairable anyway.
17544 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
17545 ;; represented using a modRM byte. The XOR replacement is long decoded,
17546 ;; so this split helps here as well.
17548 ;; Note: Can't do this as a regular split because we can't get proper
17549 ;; lifetime information then.
17552 [(set (match_operand:SI 0 "nonimmediate_operand" "")
17553 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
17555 && peep2_regno_dead_p (0, FLAGS_REG)
17556 && ((TARGET_PENTIUM
17557 && (GET_CODE (operands[0]) != MEM
17558 || !memory_displacement_operand (operands[0], SImode)))
17559 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
17560 [(parallel [(set (match_dup 0)
17561 (xor:SI (match_dup 1) (const_int -1)))
17562 (clobber (reg:CC 17))])]
17566 [(set (match_operand:HI 0 "nonimmediate_operand" "")
17567 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
17569 && peep2_regno_dead_p (0, FLAGS_REG)
17570 && ((TARGET_PENTIUM
17571 && (GET_CODE (operands[0]) != MEM
17572 || !memory_displacement_operand (operands[0], HImode)))
17573 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
17574 [(parallel [(set (match_dup 0)
17575 (xor:HI (match_dup 1) (const_int -1)))
17576 (clobber (reg:CC 17))])]
17580 [(set (match_operand:QI 0 "nonimmediate_operand" "")
17581 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
17583 && peep2_regno_dead_p (0, FLAGS_REG)
17584 && ((TARGET_PENTIUM
17585 && (GET_CODE (operands[0]) != MEM
17586 || !memory_displacement_operand (operands[0], QImode)))
17587 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
17588 [(parallel [(set (match_dup 0)
17589 (xor:QI (match_dup 1) (const_int -1)))
17590 (clobber (reg:CC 17))])]
17593 ;; Non pairable "test imm, reg" instructions can be translated to
17594 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
17595 ;; byte opcode instead of two, have a short form for byte operands),
17596 ;; so do it for other CPUs as well. Given that the value was dead,
17597 ;; this should not create any new dependencies. Pass on the sub-word
17598 ;; versions if we're concerned about partial register stalls.
17602 (compare (and:SI (match_operand:SI 0 "register_operand" "")
17603 (match_operand:SI 1 "immediate_operand" ""))
17605 "ix86_match_ccmode (insn, CCNOmode)
17606 && (true_regnum (operands[0]) != 0
17607 || (GET_CODE (operands[1]) == CONST_INT
17608 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
17609 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17611 [(set (reg:CCNO 17)
17612 (compare:CCNO (and:SI (match_dup 0)
17616 (and:SI (match_dup 0) (match_dup 1)))])]
17619 ;; We don't need to handle HImode case, because it will be promoted to SImode
17620 ;; on ! TARGET_PARTIAL_REG_STALL
17624 (compare (and:QI (match_operand:QI 0 "register_operand" "")
17625 (match_operand:QI 1 "immediate_operand" ""))
17627 "! TARGET_PARTIAL_REG_STALL
17628 && ix86_match_ccmode (insn, CCNOmode)
17629 && true_regnum (operands[0]) != 0
17630 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17632 [(set (reg:CCNO 17)
17633 (compare:CCNO (and:QI (match_dup 0)
17637 (and:QI (match_dup 0) (match_dup 1)))])]
17645 (match_operand 0 "ext_register_operand" "")
17648 (match_operand 1 "const_int_operand" ""))
17650 "! TARGET_PARTIAL_REG_STALL
17651 && ix86_match_ccmode (insn, CCNOmode)
17652 && true_regnum (operands[0]) != 0
17653 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17654 [(parallel [(set (reg:CCNO 17)
17663 (set (zero_extract:SI (match_dup 0)
17674 ;; Don't do logical operations with memory inputs.
17676 [(match_scratch:SI 2 "r")
17677 (parallel [(set (match_operand:SI 0 "register_operand" "")
17678 (match_operator:SI 3 "arith_or_logical_operator"
17680 (match_operand:SI 1 "memory_operand" "")]))
17681 (clobber (reg:CC 17))])]
17682 "! optimize_size && ! TARGET_READ_MODIFY"
17683 [(set (match_dup 2) (match_dup 1))
17684 (parallel [(set (match_dup 0)
17685 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
17686 (clobber (reg:CC 17))])]
17690 [(match_scratch:SI 2 "r")
17691 (parallel [(set (match_operand:SI 0 "register_operand" "")
17692 (match_operator:SI 3 "arith_or_logical_operator"
17693 [(match_operand:SI 1 "memory_operand" "")
17695 (clobber (reg:CC 17))])]
17696 "! optimize_size && ! TARGET_READ_MODIFY"
17697 [(set (match_dup 2) (match_dup 1))
17698 (parallel [(set (match_dup 0)
17699 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
17700 (clobber (reg:CC 17))])]
17703 ; Don't do logical operations with memory outputs
17705 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
17706 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
17707 ; the same decoder scheduling characteristics as the original.
17710 [(match_scratch:SI 2 "r")
17711 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17712 (match_operator:SI 3 "arith_or_logical_operator"
17714 (match_operand:SI 1 "nonmemory_operand" "")]))
17715 (clobber (reg:CC 17))])]
17716 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17717 [(set (match_dup 2) (match_dup 0))
17718 (parallel [(set (match_dup 2)
17719 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
17720 (clobber (reg:CC 17))])
17721 (set (match_dup 0) (match_dup 2))]
17725 [(match_scratch:SI 2 "r")
17726 (parallel [(set (match_operand:SI 0 "memory_operand" "")
17727 (match_operator:SI 3 "arith_or_logical_operator"
17728 [(match_operand:SI 1 "nonmemory_operand" "")
17730 (clobber (reg:CC 17))])]
17731 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
17732 [(set (match_dup 2) (match_dup 0))
17733 (parallel [(set (match_dup 2)
17734 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17735 (clobber (reg:CC 17))])
17736 (set (match_dup 0) (match_dup 2))]
17739 ;; Attempt to always use XOR for zeroing registers.
17741 [(set (match_operand 0 "register_operand" "")
17743 "(GET_MODE (operands[0]) == QImode
17744 || GET_MODE (operands[0]) == HImode
17745 || GET_MODE (operands[0]) == SImode
17746 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17747 && (! TARGET_USE_MOV0 || optimize_size)
17748 && peep2_regno_dead_p (0, FLAGS_REG)"
17749 [(parallel [(set (match_dup 0) (const_int 0))
17750 (clobber (reg:CC 17))])]
17751 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17755 [(set (strict_low_part (match_operand 0 "register_operand" ""))
17757 "(GET_MODE (operands[0]) == QImode
17758 || GET_MODE (operands[0]) == HImode)
17759 && (! TARGET_USE_MOV0 || optimize_size)
17760 && peep2_regno_dead_p (0, FLAGS_REG)"
17761 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
17762 (clobber (reg:CC 17))])])
17764 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
17766 [(set (match_operand 0 "register_operand" "")
17768 "(GET_MODE (operands[0]) == HImode
17769 || GET_MODE (operands[0]) == SImode
17770 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
17771 && (optimize_size || TARGET_PENTIUM)
17772 && peep2_regno_dead_p (0, FLAGS_REG)"
17773 [(parallel [(set (match_dup 0) (const_int -1))
17774 (clobber (reg:CC 17))])]
17775 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
17778 ;; Attempt to convert simple leas to adds. These can be created by
17781 [(set (match_operand:SI 0 "register_operand" "")
17782 (plus:SI (match_dup 0)
17783 (match_operand:SI 1 "nonmemory_operand" "")))]
17784 "peep2_regno_dead_p (0, FLAGS_REG)"
17785 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
17786 (clobber (reg:CC 17))])]
17790 [(set (match_operand:SI 0 "register_operand" "")
17791 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
17792 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
17793 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
17794 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
17795 (clobber (reg:CC 17))])]
17796 "operands[2] = gen_lowpart (SImode, operands[2]);")
17799 [(set (match_operand:DI 0 "register_operand" "")
17800 (plus:DI (match_dup 0)
17801 (match_operand:DI 1 "x86_64_general_operand" "")))]
17802 "peep2_regno_dead_p (0, FLAGS_REG)"
17803 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
17804 (clobber (reg:CC 17))])]
17808 [(set (match_operand:SI 0 "register_operand" "")
17809 (mult:SI (match_dup 0)
17810 (match_operand:SI 1 "const_int_operand" "")))]
17811 "exact_log2 (INTVAL (operands[1])) >= 0
17812 && peep2_regno_dead_p (0, FLAGS_REG)"
17813 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17814 (clobber (reg:CC 17))])]
17815 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17818 [(set (match_operand:DI 0 "register_operand" "")
17819 (mult:DI (match_dup 0)
17820 (match_operand:DI 1 "const_int_operand" "")))]
17821 "exact_log2 (INTVAL (operands[1])) >= 0
17822 && peep2_regno_dead_p (0, FLAGS_REG)"
17823 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
17824 (clobber (reg:CC 17))])]
17825 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
17828 [(set (match_operand:SI 0 "register_operand" "")
17829 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
17830 (match_operand:DI 2 "const_int_operand" "")) 0))]
17831 "exact_log2 (INTVAL (operands[2])) >= 0
17832 && REGNO (operands[0]) == REGNO (operands[1])
17833 && peep2_regno_dead_p (0, FLAGS_REG)"
17834 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
17835 (clobber (reg:CC 17))])]
17836 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
17838 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
17839 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
17840 ;; many CPUs it is also faster, since special hardware to avoid esp
17841 ;; dependencies is present.
17843 ;; While some of these conversions may be done using splitters, we use peepholes
17844 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
17846 ;; Convert prologue esp subtractions to push.
17847 ;; We need register to push. In order to keep verify_flow_info happy we have
17849 ;; - use scratch and clobber it in order to avoid dependencies
17850 ;; - use already live register
17851 ;; We can't use the second way right now, since there is no reliable way how to
17852 ;; verify that given register is live. First choice will also most likely in
17853 ;; fewer dependencies. On the place of esp adjustments it is very likely that
17854 ;; call clobbered registers are dead. We may want to use base pointer as an
17855 ;; alternative when no register is available later.
17858 [(match_scratch:SI 0 "r")
17859 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17860 (clobber (reg:CC 17))
17861 (clobber (mem:BLK (scratch)))])]
17862 "optimize_size || !TARGET_SUB_ESP_4"
17863 [(clobber (match_dup 0))
17864 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17865 (clobber (mem:BLK (scratch)))])])
17868 [(match_scratch:SI 0 "r")
17869 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17870 (clobber (reg:CC 17))
17871 (clobber (mem:BLK (scratch)))])]
17872 "optimize_size || !TARGET_SUB_ESP_8"
17873 [(clobber (match_dup 0))
17874 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17875 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17876 (clobber (mem:BLK (scratch)))])])
17878 ;; Convert esp subtractions to push.
17880 [(match_scratch:SI 0 "r")
17881 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
17882 (clobber (reg:CC 17))])]
17883 "optimize_size || !TARGET_SUB_ESP_4"
17884 [(clobber (match_dup 0))
17885 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17888 [(match_scratch:SI 0 "r")
17889 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
17890 (clobber (reg:CC 17))])]
17891 "optimize_size || !TARGET_SUB_ESP_8"
17892 [(clobber (match_dup 0))
17893 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
17894 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
17896 ;; Convert epilogue deallocator to pop.
17898 [(match_scratch:SI 0 "r")
17899 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17900 (clobber (reg:CC 17))
17901 (clobber (mem:BLK (scratch)))])]
17902 "optimize_size || !TARGET_ADD_ESP_4"
17903 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17904 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17905 (clobber (mem:BLK (scratch)))])]
17908 ;; Two pops case is tricky, since pop causes dependency on destination register.
17909 ;; We use two registers if available.
17911 [(match_scratch:SI 0 "r")
17912 (match_scratch:SI 1 "r")
17913 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17914 (clobber (reg:CC 17))
17915 (clobber (mem:BLK (scratch)))])]
17916 "optimize_size || !TARGET_ADD_ESP_8"
17917 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17918 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17919 (clobber (mem:BLK (scratch)))])
17920 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17921 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17925 [(match_scratch:SI 0 "r")
17926 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17927 (clobber (reg:CC 17))
17928 (clobber (mem:BLK (scratch)))])]
17930 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17931 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17932 (clobber (mem:BLK (scratch)))])
17933 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17934 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17937 ;; Convert esp additions to pop.
17939 [(match_scratch:SI 0 "r")
17940 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
17941 (clobber (reg:CC 17))])]
17943 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17944 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17947 ;; Two pops case is tricky, since pop causes dependency on destination register.
17948 ;; We use two registers if available.
17950 [(match_scratch:SI 0 "r")
17951 (match_scratch:SI 1 "r")
17952 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17953 (clobber (reg:CC 17))])]
17955 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17956 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17957 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
17958 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17962 [(match_scratch:SI 0 "r")
17963 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
17964 (clobber (reg:CC 17))])]
17966 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17967 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
17968 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
17969 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
17972 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
17973 ;; required and register dies.
17976 (compare (match_operand:SI 0 "register_operand" "")
17977 (match_operand:SI 1 "incdec_operand" "")))]
17978 "ix86_match_ccmode (insn, CCGCmode)
17979 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17980 [(parallel [(set (reg:CCGC 17)
17981 (compare:CCGC (match_dup 0)
17983 (clobber (match_dup 0))])]
17988 (compare (match_operand:HI 0 "register_operand" "")
17989 (match_operand:HI 1 "incdec_operand" "")))]
17990 "ix86_match_ccmode (insn, CCGCmode)
17991 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17992 [(parallel [(set (reg:CCGC 17)
17993 (compare:CCGC (match_dup 0)
17995 (clobber (match_dup 0))])]
18000 (compare (match_operand:QI 0 "register_operand" "")
18001 (match_operand:QI 1 "incdec_operand" "")))]
18002 "ix86_match_ccmode (insn, CCGCmode)
18003 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18004 [(parallel [(set (reg:CCGC 17)
18005 (compare:CCGC (match_dup 0)
18007 (clobber (match_dup 0))])]
18010 ;; Convert compares with 128 to shorter add -128
18013 (compare (match_operand:SI 0 "register_operand" "")
18015 "ix86_match_ccmode (insn, CCGCmode)
18016 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18017 [(parallel [(set (reg:CCGC 17)
18018 (compare:CCGC (match_dup 0)
18020 (clobber (match_dup 0))])]
18025 (compare (match_operand:HI 0 "register_operand" "")
18027 "ix86_match_ccmode (insn, CCGCmode)
18028 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18029 [(parallel [(set (reg:CCGC 17)
18030 (compare:CCGC (match_dup 0)
18032 (clobber (match_dup 0))])]
18036 [(match_scratch:DI 0 "r")
18037 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18038 (clobber (reg:CC 17))
18039 (clobber (mem:BLK (scratch)))])]
18040 "optimize_size || !TARGET_SUB_ESP_4"
18041 [(clobber (match_dup 0))
18042 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18043 (clobber (mem:BLK (scratch)))])])
18046 [(match_scratch:DI 0 "r")
18047 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18048 (clobber (reg:CC 17))
18049 (clobber (mem:BLK (scratch)))])]
18050 "optimize_size || !TARGET_SUB_ESP_8"
18051 [(clobber (match_dup 0))
18052 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18053 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18054 (clobber (mem:BLK (scratch)))])])
18056 ;; Convert esp subtractions to push.
18058 [(match_scratch:DI 0 "r")
18059 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18060 (clobber (reg:CC 17))])]
18061 "optimize_size || !TARGET_SUB_ESP_4"
18062 [(clobber (match_dup 0))
18063 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18066 [(match_scratch:DI 0 "r")
18067 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18068 (clobber (reg:CC 17))])]
18069 "optimize_size || !TARGET_SUB_ESP_8"
18070 [(clobber (match_dup 0))
18071 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18072 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18074 ;; Convert epilogue deallocator to pop.
18076 [(match_scratch:DI 0 "r")
18077 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18078 (clobber (reg:CC 17))
18079 (clobber (mem:BLK (scratch)))])]
18080 "optimize_size || !TARGET_ADD_ESP_4"
18081 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18082 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18083 (clobber (mem:BLK (scratch)))])]
18086 ;; Two pops case is tricky, since pop causes dependency on destination register.
18087 ;; We use two registers if available.
18089 [(match_scratch:DI 0 "r")
18090 (match_scratch:DI 1 "r")
18091 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18092 (clobber (reg:CC 17))
18093 (clobber (mem:BLK (scratch)))])]
18094 "optimize_size || !TARGET_ADD_ESP_8"
18095 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18096 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18097 (clobber (mem:BLK (scratch)))])
18098 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18099 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18103 [(match_scratch:DI 0 "r")
18104 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18105 (clobber (reg:CC 17))
18106 (clobber (mem:BLK (scratch)))])]
18108 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18109 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18110 (clobber (mem:BLK (scratch)))])
18111 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18112 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18115 ;; Convert esp additions to pop.
18117 [(match_scratch:DI 0 "r")
18118 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18119 (clobber (reg:CC 17))])]
18121 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18122 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18125 ;; Two pops case is tricky, since pop causes dependency on destination register.
18126 ;; We use two registers if available.
18128 [(match_scratch:DI 0 "r")
18129 (match_scratch:DI 1 "r")
18130 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18131 (clobber (reg:CC 17))])]
18133 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18134 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18135 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18136 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18140 [(match_scratch:DI 0 "r")
18141 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18142 (clobber (reg:CC 17))])]
18144 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18145 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18146 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18147 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18150 ;; Imul $32bit_imm, mem, reg is vector decoded, while
18151 ;; imul $32bit_imm, reg, reg is direct decoded.
18153 [(match_scratch:DI 3 "r")
18154 (parallel [(set (match_operand:DI 0 "register_operand" "")
18155 (mult:DI (match_operand:DI 1 "memory_operand" "")
18156 (match_operand:DI 2 "immediate_operand" "")))
18157 (clobber (reg:CC 17))])]
18158 "TARGET_K8 && !optimize_size
18159 && (GET_CODE (operands[2]) != CONST_INT
18160 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18161 [(set (match_dup 3) (match_dup 1))
18162 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
18163 (clobber (reg:CC 17))])]
18167 [(match_scratch:SI 3 "r")
18168 (parallel [(set (match_operand:SI 0 "register_operand" "")
18169 (mult:SI (match_operand:SI 1 "memory_operand" "")
18170 (match_operand:SI 2 "immediate_operand" "")))
18171 (clobber (reg:CC 17))])]
18172 "TARGET_K8 && !optimize_size
18173 && (GET_CODE (operands[2]) != CONST_INT
18174 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18175 [(set (match_dup 3) (match_dup 1))
18176 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
18177 (clobber (reg:CC 17))])]
18181 [(match_scratch:SI 3 "r")
18182 (parallel [(set (match_operand:DI 0 "register_operand" "")
18184 (mult:SI (match_operand:SI 1 "memory_operand" "")
18185 (match_operand:SI 2 "immediate_operand" ""))))
18186 (clobber (reg:CC 17))])]
18187 "TARGET_K8 && !optimize_size
18188 && (GET_CODE (operands[2]) != CONST_INT
18189 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18190 [(set (match_dup 3) (match_dup 1))
18191 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
18192 (clobber (reg:CC 17))])]
18195 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
18196 ;; Convert it into imul reg, reg
18197 ;; It would be better to force assembler to encode instruction using long
18198 ;; immediate, but there is apparently no way to do so.
18200 [(parallel [(set (match_operand:DI 0 "register_operand" "")
18201 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
18202 (match_operand:DI 2 "const_int_operand" "")))
18203 (clobber (reg:CC 17))])
18204 (match_scratch:DI 3 "r")]
18205 "TARGET_K8 && !optimize_size
18206 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18207 [(set (match_dup 3) (match_dup 2))
18208 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
18209 (clobber (reg:CC 17))])]
18211 if (!rtx_equal_p (operands[0], operands[1]))
18212 emit_move_insn (operands[0], operands[1]);
18216 [(parallel [(set (match_operand:SI 0 "register_operand" "")
18217 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
18218 (match_operand:SI 2 "const_int_operand" "")))
18219 (clobber (reg:CC 17))])
18220 (match_scratch:SI 3 "r")]
18221 "TARGET_K8 && !optimize_size
18222 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18223 [(set (match_dup 3) (match_dup 2))
18224 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
18225 (clobber (reg:CC 17))])]
18227 if (!rtx_equal_p (operands[0], operands[1]))
18228 emit_move_insn (operands[0], operands[1]);
18232 [(parallel [(set (match_operand:HI 0 "register_operand" "")
18233 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
18234 (match_operand:HI 2 "immediate_operand" "")))
18235 (clobber (reg:CC 17))])
18236 (match_scratch:HI 3 "r")]
18237 "TARGET_K8 && !optimize_size"
18238 [(set (match_dup 3) (match_dup 2))
18239 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
18240 (clobber (reg:CC 17))])]
18242 if (!rtx_equal_p (operands[0], operands[1]))
18243 emit_move_insn (operands[0], operands[1]);
18246 ;; Call-value patterns last so that the wildcard operand does not
18247 ;; disrupt insn-recog's switch tables.
18249 (define_insn "*call_value_pop_0"
18250 [(set (match_operand 0 "" "")
18251 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18252 (match_operand:SI 2 "" "")))
18253 (set (reg:SI 7) (plus:SI (reg:SI 7)
18254 (match_operand:SI 3 "immediate_operand" "")))]
18257 if (SIBLING_CALL_P (insn))
18260 return "call\t%P1";
18262 [(set_attr "type" "callv")])
18264 (define_insn "*call_value_pop_1"
18265 [(set (match_operand 0 "" "")
18266 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18267 (match_operand:SI 2 "" "")))
18268 (set (reg:SI 7) (plus:SI (reg:SI 7)
18269 (match_operand:SI 3 "immediate_operand" "i")))]
18272 if (constant_call_address_operand (operands[1], QImode))
18274 if (SIBLING_CALL_P (insn))
18277 return "call\t%P1";
18279 if (SIBLING_CALL_P (insn))
18282 return "call\t%A1";
18284 [(set_attr "type" "callv")])
18286 (define_insn "*call_value_0"
18287 [(set (match_operand 0 "" "")
18288 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18289 (match_operand:SI 2 "" "")))]
18292 if (SIBLING_CALL_P (insn))
18295 return "call\t%P1";
18297 [(set_attr "type" "callv")])
18299 (define_insn "*call_value_0_rex64"
18300 [(set (match_operand 0 "" "")
18301 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18302 (match_operand:DI 2 "const_int_operand" "")))]
18305 if (SIBLING_CALL_P (insn))
18308 return "call\t%P1";
18310 [(set_attr "type" "callv")])
18312 (define_insn "*call_value_1"
18313 [(set (match_operand 0 "" "")
18314 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18315 (match_operand:SI 2 "" "")))]
18316 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
18318 if (constant_call_address_operand (operands[1], QImode))
18319 return "call\t%P1";
18320 return "call\t%*%1";
18322 [(set_attr "type" "callv")])
18324 (define_insn "*sibcall_value_1"
18325 [(set (match_operand 0 "" "")
18326 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
18327 (match_operand:SI 2 "" "")))]
18328 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
18330 if (constant_call_address_operand (operands[1], QImode))
18332 return "jmp\t%*%1";
18334 [(set_attr "type" "callv")])
18336 (define_insn "*call_value_1_rex64"
18337 [(set (match_operand 0 "" "")
18338 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
18339 (match_operand:DI 2 "" "")))]
18340 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
18342 if (constant_call_address_operand (operands[1], QImode))
18343 return "call\t%P1";
18344 return "call\t%A1";
18346 [(set_attr "type" "callv")])
18348 (define_insn "*sibcall_value_1_rex64"
18349 [(set (match_operand 0 "" "")
18350 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18351 (match_operand:DI 2 "" "")))]
18352 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18354 [(set_attr "type" "callv")])
18356 (define_insn "*sibcall_value_1_rex64_v"
18357 [(set (match_operand 0 "" "")
18358 (call (mem:QI (reg:DI 40))
18359 (match_operand:DI 1 "" "")))]
18360 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18362 [(set_attr "type" "callv")])
18364 (define_insn "trap"
18365 [(trap_if (const_int 1) (const_int 5))]
18369 ;;; ix86 doesn't have conditional trap instructions, but we fake them
18370 ;;; for the sake of bounds checking. By emitting bounds checks as
18371 ;;; conditional traps rather than as conditional jumps around
18372 ;;; unconditional traps we avoid introducing spurious basic-block
18373 ;;; boundaries and facilitate elimination of redundant checks. In
18374 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
18377 ;;; FIXME: Static branch prediction rules for ix86 are such that
18378 ;;; forward conditional branches predict as untaken. As implemented
18379 ;;; below, pseudo conditional traps violate that rule. We should use
18380 ;;; .pushsection/.popsection to place all of the `int 5's in a special
18381 ;;; section loaded at the end of the text segment and branch forward
18382 ;;; there on bounds-failure, and then jump back immediately (in case
18383 ;;; the system chooses to ignore bounds violations, or to report
18384 ;;; violations and continue execution).
18386 (define_expand "conditional_trap"
18387 [(trap_if (match_operator 0 "comparison_operator"
18388 [(match_dup 2) (const_int 0)])
18389 (match_operand 1 "const_int_operand" ""))]
18392 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
18393 ix86_expand_compare (GET_CODE (operands[0]),
18399 (define_insn "*conditional_trap_1"
18400 [(trap_if (match_operator 0 "comparison_operator"
18401 [(reg 17) (const_int 0)])
18402 (match_operand 1 "const_int_operand" ""))]
18405 operands[2] = gen_label_rtx ();
18406 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
18407 (*targetm.asm_out.internal_label) (asm_out_file, "L",
18408 CODE_LABEL_NUMBER (operands[2]));
18412 ;; Pentium III SIMD instructions.
18414 ;; Moves for SSE/MMX regs.
18416 (define_insn "movv4sf_internal"
18417 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
18418 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
18422 movaps\t{%1, %0|%0, %1}
18423 movaps\t{%1, %0|%0, %1}"
18424 [(set_attr "type" "ssemov")
18425 (set_attr "mode" "V4SF")])
18428 [(set (match_operand:V4SF 0 "register_operand" "")
18429 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
18431 [(set (match_dup 0)
18433 (vec_duplicate:V4SF (match_dup 1))
18437 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
18438 operands[2] = CONST0_RTX (V4SFmode);
18441 (define_insn "movv4si_internal"
18442 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
18443 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
18446 switch (which_alternative)
18449 if (get_attr_mode (insn) == MODE_V4SF)
18450 return "xorps\t%0, %0";
18452 return "pxor\t%0, %0";
18455 if (get_attr_mode (insn) == MODE_V4SF)
18456 return "movaps\t{%1, %0|%0, %1}";
18458 return "movdqa\t{%1, %0|%0, %1}";
18463 [(set_attr "type" "ssemov")
18465 (cond [(eq_attr "alternative" "0,1")
18467 (ne (symbol_ref "optimize_size")
18469 (const_string "V4SF")
18470 (const_string "TI"))
18471 (eq_attr "alternative" "2")
18473 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18475 (ne (symbol_ref "optimize_size")
18477 (const_string "V4SF")
18478 (const_string "TI"))]
18479 (const_string "TI")))])
18481 (define_insn "movv2di_internal"
18482 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
18483 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
18486 switch (which_alternative)
18489 if (get_attr_mode (insn) == MODE_V4SF)
18490 return "xorps\t%0, %0";
18492 return "pxor\t%0, %0";
18495 if (get_attr_mode (insn) == MODE_V4SF)
18496 return "movaps\t{%1, %0|%0, %1}";
18498 return "movdqa\t{%1, %0|%0, %1}";
18503 [(set_attr "type" "ssemov")
18505 (cond [(eq_attr "alternative" "0,1")
18507 (ne (symbol_ref "optimize_size")
18509 (const_string "V4SF")
18510 (const_string "TI"))
18511 (eq_attr "alternative" "2")
18513 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18515 (ne (symbol_ref "optimize_size")
18517 (const_string "V4SF")
18518 (const_string "TI"))]
18519 (const_string "TI")))])
18522 [(set (match_operand:V2DF 0 "register_operand" "")
18523 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
18525 [(set (match_dup 0)
18527 (vec_duplicate:V2DF (match_dup 1))
18531 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
18532 operands[2] = CONST0_RTX (V2DFmode);
18535 (define_insn "movv8qi_internal"
18536 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m")
18537 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))]
18539 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18542 movq\t{%1, %0|%0, %1}
18543 movq\t{%1, %0|%0, %1}"
18544 [(set_attr "type" "mmxmov")
18545 (set_attr "mode" "DI")])
18547 (define_insn "movv4hi_internal"
18548 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m")
18549 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))]
18551 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18554 movq\t{%1, %0|%0, %1}
18555 movq\t{%1, %0|%0, %1}"
18556 [(set_attr "type" "mmxmov")
18557 (set_attr "mode" "DI")])
18559 (define_insn "movv2si_internal"
18560 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m")
18561 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))]
18563 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18566 movq\t{%1, %0|%0, %1}
18567 movq\t{%1, %0|%0, %1}"
18568 [(set_attr "type" "mmxcvt")
18569 (set_attr "mode" "DI")])
18571 (define_insn "movv2sf_internal"
18572 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m")
18573 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))]
18575 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18578 movq\t{%1, %0|%0, %1}
18579 movq\t{%1, %0|%0, %1}"
18580 [(set_attr "type" "mmxcvt")
18581 (set_attr "mode" "DI")])
18583 (define_expand "movti"
18584 [(set (match_operand:TI 0 "nonimmediate_operand" "")
18585 (match_operand:TI 1 "nonimmediate_operand" ""))]
18586 "TARGET_SSE || TARGET_64BIT"
18589 ix86_expand_move (TImode, operands);
18591 ix86_expand_vector_move (TImode, operands);
18595 (define_expand "movtf"
18596 [(set (match_operand:TF 0 "nonimmediate_operand" "")
18597 (match_operand:TF 1 "nonimmediate_operand" ""))]
18601 ix86_expand_move (TFmode, operands);
18603 ix86_expand_vector_move (TFmode, operands);
18607 (define_insn "movv2df_internal"
18608 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
18609 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
18611 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18613 switch (which_alternative)
18616 if (get_attr_mode (insn) == MODE_V4SF)
18617 return "xorps\t%0, %0";
18619 return "xorpd\t%0, %0";
18622 if (get_attr_mode (insn) == MODE_V4SF)
18623 return "movaps\t{%1, %0|%0, %1}";
18625 return "movapd\t{%1, %0|%0, %1}";
18630 [(set_attr "type" "ssemov")
18632 (cond [(eq_attr "alternative" "0,1")
18634 (ne (symbol_ref "optimize_size")
18636 (const_string "V4SF")
18637 (const_string "V2DF"))
18638 (eq_attr "alternative" "2")
18640 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18642 (ne (symbol_ref "optimize_size")
18644 (const_string "V4SF")
18645 (const_string "V2DF"))]
18646 (const_string "V2DF")))])
18648 (define_insn "movv8hi_internal"
18649 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
18650 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
18652 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18654 switch (which_alternative)
18657 if (get_attr_mode (insn) == MODE_V4SF)
18658 return "xorps\t%0, %0";
18660 return "pxor\t%0, %0";
18663 if (get_attr_mode (insn) == MODE_V4SF)
18664 return "movaps\t{%1, %0|%0, %1}";
18666 return "movdqa\t{%1, %0|%0, %1}";
18671 [(set_attr "type" "ssemov")
18673 (cond [(eq_attr "alternative" "0,1")
18675 (ne (symbol_ref "optimize_size")
18677 (const_string "V4SF")
18678 (const_string "TI"))
18679 (eq_attr "alternative" "2")
18681 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18683 (ne (symbol_ref "optimize_size")
18685 (const_string "V4SF")
18686 (const_string "TI"))]
18687 (const_string "TI")))])
18689 (define_insn "movv16qi_internal"
18690 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
18691 (match_operand:V16QI 1 "nonimmediate_operand" "C,xm,x"))]
18693 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18695 switch (which_alternative)
18698 if (get_attr_mode (insn) == MODE_V4SF)
18699 return "xorps\t%0, %0";
18701 return "pxor\t%0, %0";
18704 if (get_attr_mode (insn) == MODE_V4SF)
18705 return "movaps\t{%1, %0|%0, %1}";
18707 return "movdqa\t{%1, %0|%0, %1}";
18712 [(set_attr "type" "ssemov")
18714 (cond [(eq_attr "alternative" "0,1")
18716 (ne (symbol_ref "optimize_size")
18718 (const_string "V4SF")
18719 (const_string "TI"))
18720 (eq_attr "alternative" "2")
18722 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18724 (ne (symbol_ref "optimize_size")
18726 (const_string "V4SF")
18727 (const_string "TI"))]
18728 (const_string "TI")))])
18730 (define_expand "movv2df"
18731 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
18732 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
18735 ix86_expand_vector_move (V2DFmode, operands);
18739 (define_expand "movv8hi"
18740 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
18741 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
18744 ix86_expand_vector_move (V8HImode, operands);
18748 (define_expand "movv16qi"
18749 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
18750 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
18753 ix86_expand_vector_move (V16QImode, operands);
18757 (define_expand "movv4sf"
18758 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
18759 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
18762 ix86_expand_vector_move (V4SFmode, operands);
18766 (define_expand "movv4si"
18767 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
18768 (match_operand:V4SI 1 "nonimmediate_operand" ""))]
18771 ix86_expand_vector_move (V4SImode, operands);
18775 (define_expand "movv2di"
18776 [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
18777 (match_operand:V2DI 1 "nonimmediate_operand" ""))]
18780 ix86_expand_vector_move (V2DImode, operands);
18784 (define_expand "movv2si"
18785 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
18786 (match_operand:V2SI 1 "nonimmediate_operand" ""))]
18789 ix86_expand_vector_move (V2SImode, operands);
18793 (define_expand "movv4hi"
18794 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
18795 (match_operand:V4HI 1 "nonimmediate_operand" ""))]
18798 ix86_expand_vector_move (V4HImode, operands);
18802 (define_expand "movv8qi"
18803 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
18804 (match_operand:V8QI 1 "nonimmediate_operand" ""))]
18807 ix86_expand_vector_move (V8QImode, operands);
18811 (define_expand "movv2sf"
18812 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
18813 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
18816 ix86_expand_vector_move (V2SFmode, operands);
18820 (define_insn "*pushti"
18821 [(set (match_operand:TI 0 "push_operand" "=<")
18822 (match_operand:TI 1 "register_operand" "x"))]
18826 (define_insn "*pushv2df"
18827 [(set (match_operand:V2DF 0 "push_operand" "=<")
18828 (match_operand:V2DF 1 "register_operand" "x"))]
18832 (define_insn "*pushv2di"
18833 [(set (match_operand:V2DI 0 "push_operand" "=<")
18834 (match_operand:V2DI 1 "register_operand" "x"))]
18838 (define_insn "*pushv8hi"
18839 [(set (match_operand:V8HI 0 "push_operand" "=<")
18840 (match_operand:V8HI 1 "register_operand" "x"))]
18844 (define_insn "*pushv16qi"
18845 [(set (match_operand:V16QI 0 "push_operand" "=<")
18846 (match_operand:V16QI 1 "register_operand" "x"))]
18850 (define_insn "*pushv4sf"
18851 [(set (match_operand:V4SF 0 "push_operand" "=<")
18852 (match_operand:V4SF 1 "register_operand" "x"))]
18856 (define_insn "*pushv4si"
18857 [(set (match_operand:V4SI 0 "push_operand" "=<")
18858 (match_operand:V4SI 1 "register_operand" "x"))]
18862 (define_insn "*pushv2si"
18863 [(set (match_operand:V2SI 0 "push_operand" "=<")
18864 (match_operand:V2SI 1 "register_operand" "y"))]
18868 (define_insn "*pushv4hi"
18869 [(set (match_operand:V4HI 0 "push_operand" "=<")
18870 (match_operand:V4HI 1 "register_operand" "y"))]
18874 (define_insn "*pushv8qi"
18875 [(set (match_operand:V8QI 0 "push_operand" "=<")
18876 (match_operand:V8QI 1 "register_operand" "y"))]
18880 (define_insn "*pushv2sf"
18881 [(set (match_operand:V2SF 0 "push_operand" "=<")
18882 (match_operand:V2SF 1 "register_operand" "y"))]
18887 [(set (match_operand 0 "push_operand" "")
18888 (match_operand 1 "register_operand" ""))]
18889 "!TARGET_64BIT && reload_completed
18890 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
18891 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))
18892 (set (match_dup 2) (match_dup 1))]
18893 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
18894 stack_pointer_rtx);
18895 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
18898 [(set (match_operand 0 "push_operand" "")
18899 (match_operand 1 "register_operand" ""))]
18900 "TARGET_64BIT && reload_completed
18901 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
18902 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
18903 (set (match_dup 2) (match_dup 1))]
18904 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
18905 stack_pointer_rtx);
18906 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
18909 (define_insn "movti_internal"
18910 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
18911 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
18912 "TARGET_SSE && !TARGET_64BIT
18913 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18915 switch (which_alternative)
18918 if (get_attr_mode (insn) == MODE_V4SF)
18919 return "xorps\t%0, %0";
18921 return "pxor\t%0, %0";
18924 if (get_attr_mode (insn) == MODE_V4SF)
18925 return "movaps\t{%1, %0|%0, %1}";
18927 return "movdqa\t{%1, %0|%0, %1}";
18932 [(set_attr "type" "ssemov,ssemov,ssemov")
18934 (cond [(eq_attr "alternative" "0,1")
18936 (ne (symbol_ref "optimize_size")
18938 (const_string "V4SF")
18939 (const_string "TI"))
18940 (eq_attr "alternative" "2")
18942 (ne (symbol_ref "optimize_size")
18944 (const_string "V4SF")
18945 (const_string "TI"))]
18946 (const_string "TI")))])
18948 (define_insn "*movti_rex64"
18949 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
18950 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
18952 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18954 switch (which_alternative)
18960 if (get_attr_mode (insn) == MODE_V4SF)
18961 return "xorps\t%0, %0";
18963 return "pxor\t%0, %0";
18966 if (get_attr_mode (insn) == MODE_V4SF)
18967 return "movaps\t{%1, %0|%0, %1}";
18969 return "movdqa\t{%1, %0|%0, %1}";
18974 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
18976 (cond [(eq_attr "alternative" "2,3")
18978 (ne (symbol_ref "optimize_size")
18980 (const_string "V4SF")
18981 (const_string "TI"))
18982 (eq_attr "alternative" "4")
18984 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18986 (ne (symbol_ref "optimize_size")
18988 (const_string "V4SF")
18989 (const_string "TI"))]
18990 (const_string "DI")))])
18992 (define_insn "*movtf_rex64"
18993 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
18994 (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
18996 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18998 switch (which_alternative)
19004 if (get_attr_mode (insn) == MODE_V4SF)
19005 return "xorps\t%0, %0";
19007 return "pxor\t%0, %0";
19010 if (get_attr_mode (insn) == MODE_V4SF)
19011 return "movaps\t{%1, %0|%0, %1}";
19013 return "movdqa\t{%1, %0|%0, %1}";
19018 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
19020 (cond [(eq_attr "alternative" "2,3")
19022 (ne (symbol_ref "optimize_size")
19024 (const_string "V4SF")
19025 (const_string "TI"))
19026 (eq_attr "alternative" "4")
19028 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19030 (ne (symbol_ref "optimize_size")
19032 (const_string "V4SF")
19033 (const_string "TI"))]
19034 (const_string "DI")))])
19037 [(set (match_operand:TI 0 "nonimmediate_operand" "")
19038 (match_operand:TI 1 "general_operand" ""))]
19039 "reload_completed && !SSE_REG_P (operands[0])
19040 && !SSE_REG_P (operands[1])"
19042 "ix86_split_long_move (operands); DONE;")
19045 [(set (match_operand:TF 0 "nonimmediate_operand" "")
19046 (match_operand:TF 1 "general_operand" ""))]
19047 "reload_completed && !SSE_REG_P (operands[0])
19048 && !SSE_REG_P (operands[1])"
19050 "ix86_split_long_move (operands); DONE;")
19052 ;; These two patterns are useful for specifying exactly whether to use
19053 ;; movaps or movups
19054 (define_expand "sse_movaps"
19055 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
19056 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
19060 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
19062 rtx tmp = gen_reg_rtx (V4SFmode);
19063 emit_insn (gen_sse_movaps (tmp, operands[1]));
19064 emit_move_insn (operands[0], tmp);
19069 (define_insn "*sse_movaps_1"
19070 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19071 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19074 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19075 "movaps\t{%1, %0|%0, %1}"
19076 [(set_attr "type" "ssemov,ssemov")
19077 (set_attr "mode" "V4SF")])
19079 (define_expand "sse_movups"
19080 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
19081 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
19085 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
19087 rtx tmp = gen_reg_rtx (V4SFmode);
19088 emit_insn (gen_sse_movups (tmp, operands[1]));
19089 emit_move_insn (operands[0], tmp);
19094 (define_insn "*sse_movups_1"
19095 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19096 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19099 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19100 "movups\t{%1, %0|%0, %1}"
19101 [(set_attr "type" "ssecvt,ssecvt")
19102 (set_attr "mode" "V4SF")])
19104 ;; SSE Strange Moves.
19106 (define_insn "sse_movmskps"
19107 [(set (match_operand:SI 0 "register_operand" "=r")
19108 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
19111 "movmskps\t{%1, %0|%0, %1}"
19112 [(set_attr "type" "ssecvt")
19113 (set_attr "mode" "V4SF")])
19115 (define_insn "mmx_pmovmskb"
19116 [(set (match_operand:SI 0 "register_operand" "=r")
19117 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
19119 "TARGET_SSE || TARGET_3DNOW_A"
19120 "pmovmskb\t{%1, %0|%0, %1}"
19121 [(set_attr "type" "ssecvt")
19122 (set_attr "mode" "V4SF")])
19125 (define_insn "mmx_maskmovq"
19126 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
19127 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19128 (match_operand:V8QI 2 "register_operand" "y")]
19130 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
19131 ;; @@@ check ordering of operands in intel/nonintel syntax
19132 "maskmovq\t{%2, %1|%1, %2}"
19133 [(set_attr "type" "mmxcvt")
19134 (set_attr "mode" "DI")])
19136 (define_insn "mmx_maskmovq_rex"
19137 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
19138 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19139 (match_operand:V8QI 2 "register_operand" "y")]
19141 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
19142 ;; @@@ check ordering of operands in intel/nonintel syntax
19143 "maskmovq\t{%2, %1|%1, %2}"
19144 [(set_attr "type" "mmxcvt")
19145 (set_attr "mode" "DI")])
19147 (define_insn "sse_movntv4sf"
19148 [(set (match_operand:V4SF 0 "memory_operand" "=m")
19149 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
19152 "movntps\t{%1, %0|%0, %1}"
19153 [(set_attr "type" "ssemov")
19154 (set_attr "mode" "V4SF")])
19156 (define_insn "sse_movntdi"
19157 [(set (match_operand:DI 0 "memory_operand" "=m")
19158 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
19160 "TARGET_SSE || TARGET_3DNOW_A"
19161 "movntq\t{%1, %0|%0, %1}"
19162 [(set_attr "type" "mmxmov")
19163 (set_attr "mode" "DI")])
19165 (define_insn "sse_movhlps"
19166 [(set (match_operand:V4SF 0 "register_operand" "=x")
19168 (match_operand:V4SF 1 "register_operand" "0")
19169 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19170 (parallel [(const_int 2)
19176 "movhlps\t{%2, %0|%0, %2}"
19177 [(set_attr "type" "ssecvt")
19178 (set_attr "mode" "V4SF")])
19180 (define_insn "sse_movlhps"
19181 [(set (match_operand:V4SF 0 "register_operand" "=x")
19183 (match_operand:V4SF 1 "register_operand" "0")
19184 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19185 (parallel [(const_int 2)
19191 "movlhps\t{%2, %0|%0, %2}"
19192 [(set_attr "type" "ssecvt")
19193 (set_attr "mode" "V4SF")])
19195 (define_insn "sse_movhps"
19196 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19198 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19199 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19202 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19203 "movhps\t{%2, %0|%0, %2}"
19204 [(set_attr "type" "ssecvt")
19205 (set_attr "mode" "V4SF")])
19207 (define_insn "sse_movlps"
19208 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19210 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19211 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19214 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19215 "movlps\t{%2, %0|%0, %2}"
19216 [(set_attr "type" "ssecvt")
19217 (set_attr "mode" "V4SF")])
19219 (define_expand "sse_loadss"
19220 [(match_operand:V4SF 0 "register_operand" "")
19221 (match_operand:SF 1 "memory_operand" "")]
19224 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
19225 CONST0_RTX (V4SFmode)));
19229 (define_insn "sse_loadss_1"
19230 [(set (match_operand:V4SF 0 "register_operand" "=x")
19232 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
19233 (match_operand:V4SF 2 "const0_operand" "X")
19236 "movss\t{%1, %0|%0, %1}"
19237 [(set_attr "type" "ssemov")
19238 (set_attr "mode" "SF")])
19240 (define_insn "sse_movss"
19241 [(set (match_operand:V4SF 0 "register_operand" "=x")
19243 (match_operand:V4SF 1 "register_operand" "0")
19244 (match_operand:V4SF 2 "register_operand" "x")
19247 "movss\t{%2, %0|%0, %2}"
19248 [(set_attr "type" "ssemov")
19249 (set_attr "mode" "SF")])
19251 (define_insn "sse_storess"
19252 [(set (match_operand:SF 0 "memory_operand" "=m")
19254 (match_operand:V4SF 1 "register_operand" "x")
19255 (parallel [(const_int 0)])))]
19257 "movss\t{%1, %0|%0, %1}"
19258 [(set_attr "type" "ssemov")
19259 (set_attr "mode" "SF")])
19261 (define_insn "sse_shufps"
19262 [(set (match_operand:V4SF 0 "register_operand" "=x")
19263 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
19264 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
19265 (match_operand:SI 3 "immediate_operand" "i")]
19268 ;; @@@ check operand order for intel/nonintel syntax
19269 "shufps\t{%3, %2, %0|%0, %2, %3}"
19270 [(set_attr "type" "ssecvt")
19271 (set_attr "mode" "V4SF")])
19276 (define_insn "addv4sf3"
19277 [(set (match_operand:V4SF 0 "register_operand" "=x")
19278 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19279 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19281 "addps\t{%2, %0|%0, %2}"
19282 [(set_attr "type" "sseadd")
19283 (set_attr "mode" "V4SF")])
19285 (define_insn "vmaddv4sf3"
19286 [(set (match_operand:V4SF 0 "register_operand" "=x")
19288 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19289 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19293 "addss\t{%2, %0|%0, %2}"
19294 [(set_attr "type" "sseadd")
19295 (set_attr "mode" "SF")])
19297 (define_insn "subv4sf3"
19298 [(set (match_operand:V4SF 0 "register_operand" "=x")
19299 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19300 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19302 "subps\t{%2, %0|%0, %2}"
19303 [(set_attr "type" "sseadd")
19304 (set_attr "mode" "V4SF")])
19306 (define_insn "vmsubv4sf3"
19307 [(set (match_operand:V4SF 0 "register_operand" "=x")
19309 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19310 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19314 "subss\t{%2, %0|%0, %2}"
19315 [(set_attr "type" "sseadd")
19316 (set_attr "mode" "SF")])
19318 (define_insn "mulv4sf3"
19319 [(set (match_operand:V4SF 0 "register_operand" "=x")
19320 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19321 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19323 "mulps\t{%2, %0|%0, %2}"
19324 [(set_attr "type" "ssemul")
19325 (set_attr "mode" "V4SF")])
19327 (define_insn "vmmulv4sf3"
19328 [(set (match_operand:V4SF 0 "register_operand" "=x")
19330 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19331 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19335 "mulss\t{%2, %0|%0, %2}"
19336 [(set_attr "type" "ssemul")
19337 (set_attr "mode" "SF")])
19339 (define_insn "divv4sf3"
19340 [(set (match_operand:V4SF 0 "register_operand" "=x")
19341 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19342 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19344 "divps\t{%2, %0|%0, %2}"
19345 [(set_attr "type" "ssediv")
19346 (set_attr "mode" "V4SF")])
19348 (define_insn "vmdivv4sf3"
19349 [(set (match_operand:V4SF 0 "register_operand" "=x")
19351 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19352 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19356 "divss\t{%2, %0|%0, %2}"
19357 [(set_attr "type" "ssediv")
19358 (set_attr "mode" "SF")])
19361 ;; SSE square root/reciprocal
19363 (define_insn "rcpv4sf2"
19364 [(set (match_operand:V4SF 0 "register_operand" "=x")
19366 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
19368 "rcpps\t{%1, %0|%0, %1}"
19369 [(set_attr "type" "sse")
19370 (set_attr "mode" "V4SF")])
19372 (define_insn "vmrcpv4sf2"
19373 [(set (match_operand:V4SF 0 "register_operand" "=x")
19375 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19377 (match_operand:V4SF 2 "register_operand" "0")
19380 "rcpss\t{%1, %0|%0, %1}"
19381 [(set_attr "type" "sse")
19382 (set_attr "mode" "SF")])
19384 (define_insn "rsqrtv4sf2"
19385 [(set (match_operand:V4SF 0 "register_operand" "=x")
19387 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
19389 "rsqrtps\t{%1, %0|%0, %1}"
19390 [(set_attr "type" "sse")
19391 (set_attr "mode" "V4SF")])
19393 (define_insn "vmrsqrtv4sf2"
19394 [(set (match_operand:V4SF 0 "register_operand" "=x")
19396 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19398 (match_operand:V4SF 2 "register_operand" "0")
19401 "rsqrtss\t{%1, %0|%0, %1}"
19402 [(set_attr "type" "sse")
19403 (set_attr "mode" "SF")])
19405 (define_insn "sqrtv4sf2"
19406 [(set (match_operand:V4SF 0 "register_operand" "=x")
19407 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
19409 "sqrtps\t{%1, %0|%0, %1}"
19410 [(set_attr "type" "sse")
19411 (set_attr "mode" "V4SF")])
19413 (define_insn "vmsqrtv4sf2"
19414 [(set (match_operand:V4SF 0 "register_operand" "=x")
19416 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
19417 (match_operand:V4SF 2 "register_operand" "0")
19420 "sqrtss\t{%1, %0|%0, %1}"
19421 [(set_attr "type" "sse")
19422 (set_attr "mode" "SF")])
19424 ;; SSE logical operations.
19426 ;; SSE defines logical operations on floating point values. This brings
19427 ;; interesting challenge to RTL representation where logicals are only valid
19428 ;; on integral types. We deal with this by representing the floating point
19429 ;; logical as logical on arguments casted to TImode as this is what hardware
19430 ;; really does. Unfortunately hardware requires the type information to be
19431 ;; present and thus we must avoid subregs from being simplified and eliminated
19432 ;; in later compilation phases.
19434 ;; We have following variants from each instruction:
19435 ;; sse_andsf3 - the operation taking V4SF vector operands
19436 ;; and doing TImode cast on them
19437 ;; *sse_andsf3_memory - the operation taking one memory operand casted to
19438 ;; TImode, since backend insist on eliminating casts
19439 ;; on memory operands
19440 ;; sse_andti3_sf_1 - the operation taking SF scalar operands.
19441 ;; We can not accept memory operand here as instruction reads
19442 ;; whole scalar. This is generated only post reload by GCC
19443 ;; scalar float operations that expands to logicals (fabs)
19444 ;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
19445 ;; memory operand. Eventually combine can be able
19446 ;; to synthesize these using splitter.
19447 ;; sse2_anddf3, *sse2_anddf3_memory
19450 ;; These are not called andti3 etc. because we really really don't want
19451 ;; the compiler to widen DImode ands to TImode ands and then try to move
19452 ;; into DImode subregs of SSE registers, and them together, and move out
19453 ;; of DImode subregs again!
19454 ;; SSE1 single precision floating point logical operation
19455 (define_expand "sse_andv4sf3"
19456 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19457 (and:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19458 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19462 (define_insn "*sse_andv4sf3"
19463 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19464 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19465 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19467 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19468 "andps\t{%2, %0|%0, %2}"
19469 [(set_attr "type" "sselog")
19470 (set_attr "mode" "V4SF")])
19472 (define_insn "*sse_andsf3"
19473 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19474 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19475 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19477 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19478 "andps\t{%2, %0|%0, %2}"
19479 [(set_attr "type" "sselog")
19480 (set_attr "mode" "V4SF")])
19482 (define_expand "sse_nandv4sf3"
19483 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19484 (and:TI (not:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0))
19485 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19489 (define_insn "*sse_nandv4sf3"
19490 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19491 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19492 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19494 "andnps\t{%2, %0|%0, %2}"
19495 [(set_attr "type" "sselog")
19496 (set_attr "mode" "V4SF")])
19498 (define_insn "*sse_nandsf3"
19499 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19500 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19501 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19503 "andnps\t{%2, %0|%0, %2}"
19504 [(set_attr "type" "sselog")
19505 (set_attr "mode" "V4SF")])
19507 (define_expand "sse_iorv4sf3"
19508 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19509 (ior:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19510 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19514 (define_insn "*sse_iorv4sf3"
19515 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19516 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19517 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19519 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19520 "orps\t{%2, %0|%0, %2}"
19521 [(set_attr "type" "sselog")
19522 (set_attr "mode" "V4SF")])
19524 (define_insn "*sse_iorsf3"
19525 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19526 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19527 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19529 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19530 "orps\t{%2, %0|%0, %2}"
19531 [(set_attr "type" "sselog")
19532 (set_attr "mode" "V4SF")])
19534 (define_expand "sse_xorv4sf3"
19535 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19536 (xor:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19537 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19539 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19542 (define_insn "*sse_xorv4sf3"
19543 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19544 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19545 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19547 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19548 "xorps\t{%2, %0|%0, %2}"
19549 [(set_attr "type" "sselog")
19550 (set_attr "mode" "V4SF")])
19552 (define_insn "*sse_xorsf3"
19553 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19554 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19555 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19557 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19558 "xorps\t{%2, %0|%0, %2}"
19559 [(set_attr "type" "sselog")
19560 (set_attr "mode" "V4SF")])
19562 ;; SSE2 double precision floating point logical operation
19564 (define_expand "sse2_andv2df3"
19565 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19566 (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19567 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19571 (define_insn "*sse2_andv2df3"
19572 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19573 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19574 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19576 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19577 "andpd\t{%2, %0|%0, %2}"
19578 [(set_attr "type" "sselog")
19579 (set_attr "mode" "V2DF")])
19581 (define_insn "*sse2_andv2df3"
19582 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19583 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19584 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19586 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19587 "andpd\t{%2, %0|%0, %2}"
19588 [(set_attr "type" "sselog")
19589 (set_attr "mode" "V2DF")])
19591 (define_expand "sse2_nandv2df3"
19592 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19593 (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0))
19594 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19598 (define_insn "*sse2_nandv2df3"
19599 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19600 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19601 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19603 "andnpd\t{%2, %0|%0, %2}"
19604 [(set_attr "type" "sselog")
19605 (set_attr "mode" "V2DF")])
19607 (define_insn "*sse_nandti3_df"
19608 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
19609 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19610 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
19612 "andnpd\t{%2, %0|%0, %2}"
19613 [(set_attr "type" "sselog")
19614 (set_attr "mode" "V2DF")])
19616 (define_expand "sse2_iorv2df3"
19617 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19618 (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19619 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19623 (define_insn "*sse2_iorv2df3"
19624 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19625 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19626 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19628 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19629 "orpd\t{%2, %0|%0, %2}"
19630 [(set_attr "type" "sselog")
19631 (set_attr "mode" "V2DF")])
19633 (define_insn "*sse2_iordf3"
19634 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19635 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19636 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19638 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19639 "orpd\t{%2, %0|%0, %2}"
19640 [(set_attr "type" "sselog")
19641 (set_attr "mode" "V2DF")])
19643 (define_expand "sse2_xorv2df3"
19644 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19645 (xor:TI (subreg:TI (match_operand:V2DF 1 "nonimmediate_operand" "") 0)
19646 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19650 (define_insn "*sse2_xorv2df3"
19651 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19652 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19653 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19655 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19656 "xorpd\t{%2, %0|%0, %2}"
19657 [(set_attr "type" "sselog")
19658 (set_attr "mode" "V2DF")])
19660 (define_insn "*sse2_xordf3"
19661 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19662 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19663 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19665 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19666 "xorpd\t{%2, %0|%0, %2}"
19667 [(set_attr "type" "sselog")
19668 (set_attr "mode" "V2DF")])
19670 ;; SSE2 integral logicals. These patterns must always come after floating
19671 ;; point ones since we don't want compiler to use integer opcodes on floating
19672 ;; point SSE values to avoid matching of subregs in the match_operand.
19673 (define_insn "*sse2_andti3"
19674 [(set (match_operand:TI 0 "register_operand" "=x")
19675 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19676 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19678 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19679 "pand\t{%2, %0|%0, %2}"
19680 [(set_attr "type" "sselog")
19681 (set_attr "mode" "TI")])
19683 (define_insn "sse2_andv2di3"
19684 [(set (match_operand:V2DI 0 "register_operand" "=x")
19685 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19686 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19688 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19689 "pand\t{%2, %0|%0, %2}"
19690 [(set_attr "type" "sselog")
19691 (set_attr "mode" "TI")])
19693 (define_insn "*sse2_nandti3"
19694 [(set (match_operand:TI 0 "register_operand" "=x")
19695 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19696 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19698 "pandn\t{%2, %0|%0, %2}"
19699 [(set_attr "type" "sselog")
19700 (set_attr "mode" "TI")])
19702 (define_insn "sse2_nandv2di3"
19703 [(set (match_operand:V2DI 0 "register_operand" "=x")
19704 (and:V2DI (not:V2DI (match_operand:V2DI 1 "register_operand" "0"))
19705 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19707 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19708 "pandn\t{%2, %0|%0, %2}"
19709 [(set_attr "type" "sselog")
19710 (set_attr "mode" "TI")])
19712 (define_insn "*sse2_iorti3"
19713 [(set (match_operand:TI 0 "register_operand" "=x")
19714 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19715 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19717 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19718 "por\t{%2, %0|%0, %2}"
19719 [(set_attr "type" "sselog")
19720 (set_attr "mode" "TI")])
19722 (define_insn "sse2_iorv2di3"
19723 [(set (match_operand:V2DI 0 "register_operand" "=x")
19724 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19725 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19727 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19728 "por\t{%2, %0|%0, %2}"
19729 [(set_attr "type" "sselog")
19730 (set_attr "mode" "TI")])
19732 (define_insn "*sse2_xorti3"
19733 [(set (match_operand:TI 0 "register_operand" "=x")
19734 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19735 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19737 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19738 "pxor\t{%2, %0|%0, %2}"
19739 [(set_attr "type" "sselog")
19740 (set_attr "mode" "TI")])
19742 (define_insn "sse2_xorv2di3"
19743 [(set (match_operand:V2DI 0 "register_operand" "=x")
19744 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19745 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19747 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19748 "pxor\t{%2, %0|%0, %2}"
19749 [(set_attr "type" "sselog")
19750 (set_attr "mode" "TI")])
19752 ;; Use xor, but don't show input operands so they aren't live before
19754 (define_insn "sse_clrv4sf"
19755 [(set (match_operand:V4SF 0 "register_operand" "=x")
19756 (match_operand:V4SF 1 "const0_operand" "X"))]
19759 if (get_attr_mode (insn) == MODE_TI)
19760 return "pxor\t{%0, %0|%0, %0}";
19762 return "xorps\t{%0, %0|%0, %0}";
19764 [(set_attr "type" "sselog")
19765 (set_attr "memory" "none")
19768 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
19770 (ne (symbol_ref "TARGET_SSE2")
19772 (eq (symbol_ref "optimize_size")
19774 (const_string "TI")
19775 (const_string "V4SF")))])
19777 ;; Use xor, but don't show input operands so they aren't live before
19779 (define_insn "sse_clrv2df"
19780 [(set (match_operand:V2DF 0 "register_operand" "=x")
19781 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
19783 "xorpd\t{%0, %0|%0, %0}"
19784 [(set_attr "type" "sselog")
19785 (set_attr "memory" "none")
19786 (set_attr "mode" "V4SF")])
19788 ;; SSE mask-generating compares
19790 (define_insn "maskcmpv4sf3"
19791 [(set (match_operand:V4SI 0 "register_operand" "=x")
19792 (match_operator:V4SI 3 "sse_comparison_operator"
19793 [(match_operand:V4SF 1 "register_operand" "0")
19794 (match_operand:V4SF 2 "register_operand" "x")]))]
19796 "cmp%D3ps\t{%2, %0|%0, %2}"
19797 [(set_attr "type" "ssecmp")
19798 (set_attr "mode" "V4SF")])
19800 (define_insn "maskncmpv4sf3"
19801 [(set (match_operand:V4SI 0 "register_operand" "=x")
19803 (match_operator:V4SI 3 "sse_comparison_operator"
19804 [(match_operand:V4SF 1 "register_operand" "0")
19805 (match_operand:V4SF 2 "register_operand" "x")])))]
19808 if (GET_CODE (operands[3]) == UNORDERED)
19809 return "cmpordps\t{%2, %0|%0, %2}";
19811 return "cmpn%D3ps\t{%2, %0|%0, %2}";
19813 [(set_attr "type" "ssecmp")
19814 (set_attr "mode" "V4SF")])
19816 (define_insn "vmmaskcmpv4sf3"
19817 [(set (match_operand:V4SI 0 "register_operand" "=x")
19819 (match_operator:V4SI 3 "sse_comparison_operator"
19820 [(match_operand:V4SF 1 "register_operand" "0")
19821 (match_operand:V4SF 2 "register_operand" "x")])
19822 (subreg:V4SI (match_dup 1) 0)
19825 "cmp%D3ss\t{%2, %0|%0, %2}"
19826 [(set_attr "type" "ssecmp")
19827 (set_attr "mode" "SF")])
19829 (define_insn "vmmaskncmpv4sf3"
19830 [(set (match_operand:V4SI 0 "register_operand" "=x")
19833 (match_operator:V4SI 3 "sse_comparison_operator"
19834 [(match_operand:V4SF 1 "register_operand" "0")
19835 (match_operand:V4SF 2 "register_operand" "x")]))
19836 (subreg:V4SI (match_dup 1) 0)
19840 if (GET_CODE (operands[3]) == UNORDERED)
19841 return "cmpordss\t{%2, %0|%0, %2}";
19843 return "cmpn%D3ss\t{%2, %0|%0, %2}";
19845 [(set_attr "type" "ssecmp")
19846 (set_attr "mode" "SF")])
19848 (define_insn "sse_comi"
19849 [(set (reg:CCFP 17)
19850 (compare:CCFP (vec_select:SF
19851 (match_operand:V4SF 0 "register_operand" "x")
19852 (parallel [(const_int 0)]))
19854 (match_operand:V4SF 1 "register_operand" "x")
19855 (parallel [(const_int 0)]))))]
19857 "comiss\t{%1, %0|%0, %1}"
19858 [(set_attr "type" "ssecomi")
19859 (set_attr "mode" "SF")])
19861 (define_insn "sse_ucomi"
19862 [(set (reg:CCFPU 17)
19863 (compare:CCFPU (vec_select:SF
19864 (match_operand:V4SF 0 "register_operand" "x")
19865 (parallel [(const_int 0)]))
19867 (match_operand:V4SF 1 "register_operand" "x")
19868 (parallel [(const_int 0)]))))]
19870 "ucomiss\t{%1, %0|%0, %1}"
19871 [(set_attr "type" "ssecomi")
19872 (set_attr "mode" "SF")])
19877 (define_insn "sse_unpckhps"
19878 [(set (match_operand:V4SF 0 "register_operand" "=x")
19880 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
19881 (parallel [(const_int 2)
19885 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19886 (parallel [(const_int 0)
19892 "unpckhps\t{%2, %0|%0, %2}"
19893 [(set_attr "type" "ssecvt")
19894 (set_attr "mode" "V4SF")])
19896 (define_insn "sse_unpcklps"
19897 [(set (match_operand:V4SF 0 "register_operand" "=x")
19899 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
19900 (parallel [(const_int 0)
19904 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19905 (parallel [(const_int 2)
19911 "unpcklps\t{%2, %0|%0, %2}"
19912 [(set_attr "type" "ssecvt")
19913 (set_attr "mode" "V4SF")])
19918 (define_insn "smaxv4sf3"
19919 [(set (match_operand:V4SF 0 "register_operand" "=x")
19920 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
19921 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19923 "maxps\t{%2, %0|%0, %2}"
19924 [(set_attr "type" "sse")
19925 (set_attr "mode" "V4SF")])
19927 (define_insn "vmsmaxv4sf3"
19928 [(set (match_operand:V4SF 0 "register_operand" "=x")
19930 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
19931 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19935 "maxss\t{%2, %0|%0, %2}"
19936 [(set_attr "type" "sse")
19937 (set_attr "mode" "SF")])
19939 (define_insn "sminv4sf3"
19940 [(set (match_operand:V4SF 0 "register_operand" "=x")
19941 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
19942 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19944 "minps\t{%2, %0|%0, %2}"
19945 [(set_attr "type" "sse")
19946 (set_attr "mode" "V4SF")])
19948 (define_insn "vmsminv4sf3"
19949 [(set (match_operand:V4SF 0 "register_operand" "=x")
19951 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
19952 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19956 "minss\t{%2, %0|%0, %2}"
19957 [(set_attr "type" "sse")
19958 (set_attr "mode" "SF")])
19960 ;; SSE <-> integer/MMX conversions
19962 (define_insn "cvtpi2ps"
19963 [(set (match_operand:V4SF 0 "register_operand" "=x")
19965 (match_operand:V4SF 1 "register_operand" "0")
19966 (vec_duplicate:V4SF
19967 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
19970 "cvtpi2ps\t{%2, %0|%0, %2}"
19971 [(set_attr "type" "ssecvt")
19972 (set_attr "mode" "V4SF")])
19974 (define_insn "cvtps2pi"
19975 [(set (match_operand:V2SI 0 "register_operand" "=y")
19977 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
19978 (parallel [(const_int 0) (const_int 1)])))]
19980 "cvtps2pi\t{%1, %0|%0, %1}"
19981 [(set_attr "type" "ssecvt")
19982 (set_attr "mode" "V4SF")])
19984 (define_insn "cvttps2pi"
19985 [(set (match_operand:V2SI 0 "register_operand" "=y")
19987 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19989 (parallel [(const_int 0) (const_int 1)])))]
19991 "cvttps2pi\t{%1, %0|%0, %1}"
19992 [(set_attr "type" "ssecvt")
19993 (set_attr "mode" "SF")])
19995 (define_insn "cvtsi2ss"
19996 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
19998 (match_operand:V4SF 1 "register_operand" "0,0")
19999 (vec_duplicate:V4SF
20000 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
20003 "cvtsi2ss\t{%2, %0|%0, %2}"
20004 [(set_attr "type" "sseicvt")
20005 (set_attr "athlon_decode" "vector,double")
20006 (set_attr "mode" "SF")])
20008 (define_insn "cvtsi2ssq"
20009 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
20011 (match_operand:V4SF 1 "register_operand" "0,0")
20012 (vec_duplicate:V4SF
20013 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
20015 "TARGET_SSE && TARGET_64BIT"
20016 "cvtsi2ssq\t{%2, %0|%0, %2}"
20017 [(set_attr "type" "sseicvt")
20018 (set_attr "athlon_decode" "vector,double")
20019 (set_attr "mode" "SF")])
20021 (define_insn "cvtss2si"
20022 [(set (match_operand:SI 0 "register_operand" "=r,r")
20024 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20025 (parallel [(const_int 0)])))]
20027 "cvtss2si\t{%1, %0|%0, %1}"
20028 [(set_attr "type" "sseicvt")
20029 (set_attr "athlon_decode" "double,vector")
20030 (set_attr "mode" "SI")])
20032 (define_insn "cvtss2siq"
20033 [(set (match_operand:DI 0 "register_operand" "=r,r")
20035 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20036 (parallel [(const_int 0)])))]
20038 "cvtss2siq\t{%1, %0|%0, %1}"
20039 [(set_attr "type" "sseicvt")
20040 (set_attr "athlon_decode" "double,vector")
20041 (set_attr "mode" "DI")])
20043 (define_insn "cvttss2si"
20044 [(set (match_operand:SI 0 "register_operand" "=r,r")
20046 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20048 (parallel [(const_int 0)])))]
20050 "cvttss2si\t{%1, %0|%0, %1}"
20051 [(set_attr "type" "sseicvt")
20052 (set_attr "mode" "SF")
20053 (set_attr "athlon_decode" "double,vector")])
20055 (define_insn "cvttss2siq"
20056 [(set (match_operand:DI 0 "register_operand" "=r,r")
20058 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20060 (parallel [(const_int 0)])))]
20061 "TARGET_SSE && TARGET_64BIT"
20062 "cvttss2siq\t{%1, %0|%0, %1}"
20063 [(set_attr "type" "sseicvt")
20064 (set_attr "mode" "SF")
20065 (set_attr "athlon_decode" "double,vector")])
20072 (define_insn "addv8qi3"
20073 [(set (match_operand:V8QI 0 "register_operand" "=y")
20074 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20075 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20077 "paddb\t{%2, %0|%0, %2}"
20078 [(set_attr "type" "mmxadd")
20079 (set_attr "mode" "DI")])
20081 (define_insn "addv4hi3"
20082 [(set (match_operand:V4HI 0 "register_operand" "=y")
20083 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20084 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20086 "paddw\t{%2, %0|%0, %2}"
20087 [(set_attr "type" "mmxadd")
20088 (set_attr "mode" "DI")])
20090 (define_insn "addv2si3"
20091 [(set (match_operand:V2SI 0 "register_operand" "=y")
20092 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
20093 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20095 "paddd\t{%2, %0|%0, %2}"
20096 [(set_attr "type" "mmxadd")
20097 (set_attr "mode" "DI")])
20099 (define_insn "mmx_adddi3"
20100 [(set (match_operand:DI 0 "register_operand" "=y")
20102 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
20103 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20106 "paddq\t{%2, %0|%0, %2}"
20107 [(set_attr "type" "mmxadd")
20108 (set_attr "mode" "DI")])
20110 (define_insn "ssaddv8qi3"
20111 [(set (match_operand:V8QI 0 "register_operand" "=y")
20112 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20113 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20115 "paddsb\t{%2, %0|%0, %2}"
20116 [(set_attr "type" "mmxadd")
20117 (set_attr "mode" "DI")])
20119 (define_insn "ssaddv4hi3"
20120 [(set (match_operand:V4HI 0 "register_operand" "=y")
20121 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20122 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20124 "paddsw\t{%2, %0|%0, %2}"
20125 [(set_attr "type" "mmxadd")
20126 (set_attr "mode" "DI")])
20128 (define_insn "usaddv8qi3"
20129 [(set (match_operand:V8QI 0 "register_operand" "=y")
20130 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20131 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20133 "paddusb\t{%2, %0|%0, %2}"
20134 [(set_attr "type" "mmxadd")
20135 (set_attr "mode" "DI")])
20137 (define_insn "usaddv4hi3"
20138 [(set (match_operand:V4HI 0 "register_operand" "=y")
20139 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20140 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20142 "paddusw\t{%2, %0|%0, %2}"
20143 [(set_attr "type" "mmxadd")
20144 (set_attr "mode" "DI")])
20146 (define_insn "subv8qi3"
20147 [(set (match_operand:V8QI 0 "register_operand" "=y")
20148 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20149 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20151 "psubb\t{%2, %0|%0, %2}"
20152 [(set_attr "type" "mmxadd")
20153 (set_attr "mode" "DI")])
20155 (define_insn "subv4hi3"
20156 [(set (match_operand:V4HI 0 "register_operand" "=y")
20157 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20158 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20160 "psubw\t{%2, %0|%0, %2}"
20161 [(set_attr "type" "mmxadd")
20162 (set_attr "mode" "DI")])
20164 (define_insn "subv2si3"
20165 [(set (match_operand:V2SI 0 "register_operand" "=y")
20166 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
20167 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20169 "psubd\t{%2, %0|%0, %2}"
20170 [(set_attr "type" "mmxadd")
20171 (set_attr "mode" "DI")])
20173 (define_insn "mmx_subdi3"
20174 [(set (match_operand:DI 0 "register_operand" "=y")
20176 [(minus:DI (match_operand:DI 1 "register_operand" "0")
20177 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20180 "psubq\t{%2, %0|%0, %2}"
20181 [(set_attr "type" "mmxadd")
20182 (set_attr "mode" "DI")])
20184 (define_insn "sssubv8qi3"
20185 [(set (match_operand:V8QI 0 "register_operand" "=y")
20186 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20187 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20189 "psubsb\t{%2, %0|%0, %2}"
20190 [(set_attr "type" "mmxadd")
20191 (set_attr "mode" "DI")])
20193 (define_insn "sssubv4hi3"
20194 [(set (match_operand:V4HI 0 "register_operand" "=y")
20195 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20196 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20198 "psubsw\t{%2, %0|%0, %2}"
20199 [(set_attr "type" "mmxadd")
20200 (set_attr "mode" "DI")])
20202 (define_insn "ussubv8qi3"
20203 [(set (match_operand:V8QI 0 "register_operand" "=y")
20204 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20205 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20207 "psubusb\t{%2, %0|%0, %2}"
20208 [(set_attr "type" "mmxadd")
20209 (set_attr "mode" "DI")])
20211 (define_insn "ussubv4hi3"
20212 [(set (match_operand:V4HI 0 "register_operand" "=y")
20213 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20214 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20216 "psubusw\t{%2, %0|%0, %2}"
20217 [(set_attr "type" "mmxadd")
20218 (set_attr "mode" "DI")])
20220 (define_insn "mulv4hi3"
20221 [(set (match_operand:V4HI 0 "register_operand" "=y")
20222 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
20223 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20225 "pmullw\t{%2, %0|%0, %2}"
20226 [(set_attr "type" "mmxmul")
20227 (set_attr "mode" "DI")])
20229 (define_insn "smulv4hi3_highpart"
20230 [(set (match_operand:V4HI 0 "register_operand" "=y")
20233 (mult:V4SI (sign_extend:V4SI
20234 (match_operand:V4HI 1 "register_operand" "0"))
20236 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20239 "pmulhw\t{%2, %0|%0, %2}"
20240 [(set_attr "type" "mmxmul")
20241 (set_attr "mode" "DI")])
20243 (define_insn "umulv4hi3_highpart"
20244 [(set (match_operand:V4HI 0 "register_operand" "=y")
20247 (mult:V4SI (zero_extend:V4SI
20248 (match_operand:V4HI 1 "register_operand" "0"))
20250 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20252 "TARGET_SSE || TARGET_3DNOW_A"
20253 "pmulhuw\t{%2, %0|%0, %2}"
20254 [(set_attr "type" "mmxmul")
20255 (set_attr "mode" "DI")])
20257 (define_insn "mmx_pmaddwd"
20258 [(set (match_operand:V2SI 0 "register_operand" "=y")
20262 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
20263 (parallel [(const_int 0) (const_int 2)])))
20265 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
20266 (parallel [(const_int 0) (const_int 2)]))))
20268 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
20269 (parallel [(const_int 1)
20271 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
20272 (parallel [(const_int 1)
20273 (const_int 3)]))))))]
20275 "pmaddwd\t{%2, %0|%0, %2}"
20276 [(set_attr "type" "mmxmul")
20277 (set_attr "mode" "DI")])
20280 ;; MMX logical operations
20281 ;; Note we don't want to declare these as regular iordi3 insns to prevent
20282 ;; normal code that also wants to use the FPU from getting broken.
20283 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
20284 (define_insn "mmx_iordi3"
20285 [(set (match_operand:DI 0 "register_operand" "=y")
20287 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
20288 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20291 "por\t{%2, %0|%0, %2}"
20292 [(set_attr "type" "mmxadd")
20293 (set_attr "mode" "DI")])
20295 (define_insn "mmx_xordi3"
20296 [(set (match_operand:DI 0 "register_operand" "=y")
20298 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
20299 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20302 "pxor\t{%2, %0|%0, %2}"
20303 [(set_attr "type" "mmxadd")
20304 (set_attr "mode" "DI")
20305 (set_attr "memory" "none")])
20307 ;; Same as pxor, but don't show input operands so that we don't think
20309 (define_insn "mmx_clrdi"
20310 [(set (match_operand:DI 0 "register_operand" "=y")
20311 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
20313 "pxor\t{%0, %0|%0, %0}"
20314 [(set_attr "type" "mmxadd")
20315 (set_attr "mode" "DI")
20316 (set_attr "memory" "none")])
20318 (define_insn "mmx_anddi3"
20319 [(set (match_operand:DI 0 "register_operand" "=y")
20321 [(and:DI (match_operand:DI 1 "register_operand" "%0")
20322 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20325 "pand\t{%2, %0|%0, %2}"
20326 [(set_attr "type" "mmxadd")
20327 (set_attr "mode" "DI")])
20329 (define_insn "mmx_nanddi3"
20330 [(set (match_operand:DI 0 "register_operand" "=y")
20332 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
20333 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20336 "pandn\t{%2, %0|%0, %2}"
20337 [(set_attr "type" "mmxadd")
20338 (set_attr "mode" "DI")])
20341 ;; MMX unsigned averages/sum of absolute differences
20343 (define_insn "mmx_uavgv8qi3"
20344 [(set (match_operand:V8QI 0 "register_operand" "=y")
20346 (plus:V8QI (plus:V8QI
20347 (match_operand:V8QI 1 "register_operand" "0")
20348 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
20349 (const_vector:V8QI [(const_int 1)
20358 "TARGET_SSE || TARGET_3DNOW_A"
20359 "pavgb\t{%2, %0|%0, %2}"
20360 [(set_attr "type" "mmxshft")
20361 (set_attr "mode" "DI")])
20363 (define_insn "mmx_uavgv4hi3"
20364 [(set (match_operand:V4HI 0 "register_operand" "=y")
20366 (plus:V4HI (plus:V4HI
20367 (match_operand:V4HI 1 "register_operand" "0")
20368 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
20369 (const_vector:V4HI [(const_int 1)
20374 "TARGET_SSE || TARGET_3DNOW_A"
20375 "pavgw\t{%2, %0|%0, %2}"
20376 [(set_attr "type" "mmxshft")
20377 (set_attr "mode" "DI")])
20379 (define_insn "mmx_psadbw"
20380 [(set (match_operand:DI 0 "register_operand" "=y")
20381 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
20382 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
20384 "TARGET_SSE || TARGET_3DNOW_A"
20385 "psadbw\t{%2, %0|%0, %2}"
20386 [(set_attr "type" "mmxshft")
20387 (set_attr "mode" "DI")])
20390 ;; MMX insert/extract/shuffle
20392 (define_insn "mmx_pinsrw"
20393 [(set (match_operand:V4HI 0 "register_operand" "=y")
20394 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
20395 (vec_duplicate:V4HI
20396 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
20397 (match_operand:SI 3 "const_0_to_15_operand" "N")))]
20398 "TARGET_SSE || TARGET_3DNOW_A"
20399 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
20400 [(set_attr "type" "mmxcvt")
20401 (set_attr "mode" "DI")])
20403 (define_insn "mmx_pextrw"
20404 [(set (match_operand:SI 0 "register_operand" "=r")
20405 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
20407 [(match_operand:SI 2 "const_0_to_3_operand" "N")]))))]
20408 "TARGET_SSE || TARGET_3DNOW_A"
20409 "pextrw\t{%2, %1, %0|%0, %1, %2}"
20410 [(set_attr "type" "mmxcvt")
20411 (set_attr "mode" "DI")])
20413 (define_insn "mmx_pshufw"
20414 [(set (match_operand:V4HI 0 "register_operand" "=y")
20415 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
20416 (match_operand:SI 2 "immediate_operand" "i")]
20418 "TARGET_SSE || TARGET_3DNOW_A"
20419 "pshufw\t{%2, %1, %0|%0, %1, %2}"
20420 [(set_attr "type" "mmxcvt")
20421 (set_attr "mode" "DI")])
20424 ;; MMX mask-generating comparisons
20426 (define_insn "eqv8qi3"
20427 [(set (match_operand:V8QI 0 "register_operand" "=y")
20428 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
20429 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20431 "pcmpeqb\t{%2, %0|%0, %2}"
20432 [(set_attr "type" "mmxcmp")
20433 (set_attr "mode" "DI")])
20435 (define_insn "eqv4hi3"
20436 [(set (match_operand:V4HI 0 "register_operand" "=y")
20437 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
20438 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20440 "pcmpeqw\t{%2, %0|%0, %2}"
20441 [(set_attr "type" "mmxcmp")
20442 (set_attr "mode" "DI")])
20444 (define_insn "eqv2si3"
20445 [(set (match_operand:V2SI 0 "register_operand" "=y")
20446 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
20447 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20449 "pcmpeqd\t{%2, %0|%0, %2}"
20450 [(set_attr "type" "mmxcmp")
20451 (set_attr "mode" "DI")])
20453 (define_insn "gtv8qi3"
20454 [(set (match_operand:V8QI 0 "register_operand" "=y")
20455 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
20456 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20458 "pcmpgtb\t{%2, %0|%0, %2}"
20459 [(set_attr "type" "mmxcmp")
20460 (set_attr "mode" "DI")])
20462 (define_insn "gtv4hi3"
20463 [(set (match_operand:V4HI 0 "register_operand" "=y")
20464 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20465 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20467 "pcmpgtw\t{%2, %0|%0, %2}"
20468 [(set_attr "type" "mmxcmp")
20469 (set_attr "mode" "DI")])
20471 (define_insn "gtv2si3"
20472 [(set (match_operand:V2SI 0 "register_operand" "=y")
20473 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20474 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20476 "pcmpgtd\t{%2, %0|%0, %2}"
20477 [(set_attr "type" "mmxcmp")
20478 (set_attr "mode" "DI")])
20481 ;; MMX max/min insns
20483 (define_insn "umaxv8qi3"
20484 [(set (match_operand:V8QI 0 "register_operand" "=y")
20485 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
20486 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20487 "TARGET_SSE || TARGET_3DNOW_A"
20488 "pmaxub\t{%2, %0|%0, %2}"
20489 [(set_attr "type" "mmxadd")
20490 (set_attr "mode" "DI")])
20492 (define_insn "smaxv4hi3"
20493 [(set (match_operand:V4HI 0 "register_operand" "=y")
20494 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
20495 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20496 "TARGET_SSE || TARGET_3DNOW_A"
20497 "pmaxsw\t{%2, %0|%0, %2}"
20498 [(set_attr "type" "mmxadd")
20499 (set_attr "mode" "DI")])
20501 (define_insn "uminv8qi3"
20502 [(set (match_operand:V8QI 0 "register_operand" "=y")
20503 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
20504 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20505 "TARGET_SSE || TARGET_3DNOW_A"
20506 "pminub\t{%2, %0|%0, %2}"
20507 [(set_attr "type" "mmxadd")
20508 (set_attr "mode" "DI")])
20510 (define_insn "sminv4hi3"
20511 [(set (match_operand:V4HI 0 "register_operand" "=y")
20512 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
20513 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20514 "TARGET_SSE || TARGET_3DNOW_A"
20515 "pminsw\t{%2, %0|%0, %2}"
20516 [(set_attr "type" "mmxadd")
20517 (set_attr "mode" "DI")])
20522 (define_insn "ashrv4hi3"
20523 [(set (match_operand:V4HI 0 "register_operand" "=y")
20524 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20525 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20527 "psraw\t{%2, %0|%0, %2}"
20528 [(set_attr "type" "mmxshft")
20529 (set_attr "mode" "DI")])
20531 (define_insn "ashrv2si3"
20532 [(set (match_operand:V2SI 0 "register_operand" "=y")
20533 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20534 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20536 "psrad\t{%2, %0|%0, %2}"
20537 [(set_attr "type" "mmxshft")
20538 (set_attr "mode" "DI")])
20540 (define_insn "lshrv4hi3"
20541 [(set (match_operand:V4HI 0 "register_operand" "=y")
20542 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20543 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20545 "psrlw\t{%2, %0|%0, %2}"
20546 [(set_attr "type" "mmxshft")
20547 (set_attr "mode" "DI")])
20549 (define_insn "lshrv2si3"
20550 [(set (match_operand:V2SI 0 "register_operand" "=y")
20551 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20552 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20554 "psrld\t{%2, %0|%0, %2}"
20555 [(set_attr "type" "mmxshft")
20556 (set_attr "mode" "DI")])
20558 ;; See logical MMX insns.
20559 (define_insn "mmx_lshrdi3"
20560 [(set (match_operand:DI 0 "register_operand" "=y")
20562 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
20563 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20566 "psrlq\t{%2, %0|%0, %2}"
20567 [(set_attr "type" "mmxshft")
20568 (set_attr "mode" "DI")])
20570 (define_insn "ashlv4hi3"
20571 [(set (match_operand:V4HI 0 "register_operand" "=y")
20572 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
20573 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20575 "psllw\t{%2, %0|%0, %2}"
20576 [(set_attr "type" "mmxshft")
20577 (set_attr "mode" "DI")])
20579 (define_insn "ashlv2si3"
20580 [(set (match_operand:V2SI 0 "register_operand" "=y")
20581 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
20582 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20584 "pslld\t{%2, %0|%0, %2}"
20585 [(set_attr "type" "mmxshft")
20586 (set_attr "mode" "DI")])
20588 ;; See logical MMX insns.
20589 (define_insn "mmx_ashldi3"
20590 [(set (match_operand:DI 0 "register_operand" "=y")
20592 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
20593 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20596 "psllq\t{%2, %0|%0, %2}"
20597 [(set_attr "type" "mmxshft")
20598 (set_attr "mode" "DI")])
20601 ;; MMX pack/unpack insns.
20603 (define_insn "mmx_packsswb"
20604 [(set (match_operand:V8QI 0 "register_operand" "=y")
20606 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20607 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20609 "packsswb\t{%2, %0|%0, %2}"
20610 [(set_attr "type" "mmxshft")
20611 (set_attr "mode" "DI")])
20613 (define_insn "mmx_packssdw"
20614 [(set (match_operand:V4HI 0 "register_operand" "=y")
20616 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
20617 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
20619 "packssdw\t{%2, %0|%0, %2}"
20620 [(set_attr "type" "mmxshft")
20621 (set_attr "mode" "DI")])
20623 (define_insn "mmx_packuswb"
20624 [(set (match_operand:V8QI 0 "register_operand" "=y")
20626 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20627 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20629 "packuswb\t{%2, %0|%0, %2}"
20630 [(set_attr "type" "mmxshft")
20631 (set_attr "mode" "DI")])
20633 (define_insn "mmx_punpckhbw"
20634 [(set (match_operand:V8QI 0 "register_operand" "=y")
20636 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
20637 (parallel [(const_int 4)
20645 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
20646 (parallel [(const_int 0)
20656 "punpckhbw\t{%2, %0|%0, %2}"
20657 [(set_attr "type" "mmxcvt")
20658 (set_attr "mode" "DI")])
20660 (define_insn "mmx_punpckhwd"
20661 [(set (match_operand:V4HI 0 "register_operand" "=y")
20663 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
20664 (parallel [(const_int 0)
20668 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
20669 (parallel [(const_int 2)
20675 "punpckhwd\t{%2, %0|%0, %2}"
20676 [(set_attr "type" "mmxcvt")
20677 (set_attr "mode" "DI")])
20679 (define_insn "mmx_punpckhdq"
20680 [(set (match_operand:V2SI 0 "register_operand" "=y")
20682 (match_operand:V2SI 1 "register_operand" "0")
20683 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
20684 (parallel [(const_int 1)
20688 "punpckhdq\t{%2, %0|%0, %2}"
20689 [(set_attr "type" "mmxcvt")
20690 (set_attr "mode" "DI")])
20692 (define_insn "mmx_punpcklbw"
20693 [(set (match_operand:V8QI 0 "register_operand" "=y")
20695 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
20696 (parallel [(const_int 0)
20704 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
20705 (parallel [(const_int 4)
20715 "punpcklbw\t{%2, %0|%0, %2}"
20716 [(set_attr "type" "mmxcvt")
20717 (set_attr "mode" "DI")])
20719 (define_insn "mmx_punpcklwd"
20720 [(set (match_operand:V4HI 0 "register_operand" "=y")
20722 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
20723 (parallel [(const_int 2)
20727 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
20728 (parallel [(const_int 0)
20734 "punpcklwd\t{%2, %0|%0, %2}"
20735 [(set_attr "type" "mmxcvt")
20736 (set_attr "mode" "DI")])
20738 (define_insn "mmx_punpckldq"
20739 [(set (match_operand:V2SI 0 "register_operand" "=y")
20741 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
20742 (parallel [(const_int 1)
20744 (match_operand:V2SI 2 "register_operand" "y")
20747 "punpckldq\t{%2, %0|%0, %2}"
20748 [(set_attr "type" "mmxcvt")
20749 (set_attr "mode" "DI")])
20752 ;; Miscellaneous stuff
20754 (define_insn "emms"
20755 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
20756 (clobber (reg:XF 8))
20757 (clobber (reg:XF 9))
20758 (clobber (reg:XF 10))
20759 (clobber (reg:XF 11))
20760 (clobber (reg:XF 12))
20761 (clobber (reg:XF 13))
20762 (clobber (reg:XF 14))
20763 (clobber (reg:XF 15))
20764 (clobber (reg:DI 29))
20765 (clobber (reg:DI 30))
20766 (clobber (reg:DI 31))
20767 (clobber (reg:DI 32))
20768 (clobber (reg:DI 33))
20769 (clobber (reg:DI 34))
20770 (clobber (reg:DI 35))
20771 (clobber (reg:DI 36))]
20774 [(set_attr "type" "mmx")
20775 (set_attr "memory" "unknown")])
20777 (define_insn "ldmxcsr"
20778 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
20782 [(set_attr "type" "sse")
20783 (set_attr "memory" "load")])
20785 (define_insn "stmxcsr"
20786 [(set (match_operand:SI 0 "memory_operand" "=m")
20787 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
20790 [(set_attr "type" "sse")
20791 (set_attr "memory" "store")])
20793 (define_expand "sfence"
20794 [(set (match_dup 0)
20795 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
20796 "TARGET_SSE || TARGET_3DNOW_A"
20798 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
20799 MEM_VOLATILE_P (operands[0]) = 1;
20802 (define_insn "*sfence_insn"
20803 [(set (match_operand:BLK 0 "" "")
20804 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
20805 "TARGET_SSE || TARGET_3DNOW_A"
20807 [(set_attr "type" "sse")
20808 (set_attr "memory" "unknown")])
20810 (define_expand "sse_prologue_save"
20811 [(parallel [(set (match_operand:BLK 0 "" "")
20812 (unspec:BLK [(reg:DI 21)
20819 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
20820 (use (match_operand:DI 1 "register_operand" ""))
20821 (use (match_operand:DI 2 "immediate_operand" ""))
20822 (use (label_ref:DI (match_operand 3 "" "")))])]
20826 (define_insn "*sse_prologue_save_insn"
20827 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
20828 (match_operand:DI 4 "const_int_operand" "n")))
20829 (unspec:BLK [(reg:DI 21)
20836 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
20837 (use (match_operand:DI 1 "register_operand" "r"))
20838 (use (match_operand:DI 2 "const_int_operand" "i"))
20839 (use (label_ref:DI (match_operand 3 "" "X")))]
20841 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
20842 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
20846 operands[0] = gen_rtx_MEM (Pmode,
20847 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
20848 output_asm_insn (\"jmp\\t%A1\", operands);
20849 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
20851 operands[4] = adjust_address (operands[0], DImode, i*16);
20852 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
20853 PUT_MODE (operands[4], TImode);
20854 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
20855 output_asm_insn (\"rex\", operands);
20856 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
20858 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
20859 CODE_LABEL_NUMBER (operands[3]));
20863 [(set_attr "type" "other")
20864 (set_attr "length_immediate" "0")
20865 (set_attr "length_address" "0")
20866 (set_attr "length" "135")
20867 (set_attr "memory" "store")
20868 (set_attr "modrm" "0")
20869 (set_attr "mode" "DI")])
20871 ;; 3Dnow! instructions
20873 (define_insn "addv2sf3"
20874 [(set (match_operand:V2SF 0 "register_operand" "=y")
20875 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
20876 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20878 "pfadd\\t{%2, %0|%0, %2}"
20879 [(set_attr "type" "mmxadd")
20880 (set_attr "mode" "V2SF")])
20882 (define_insn "subv2sf3"
20883 [(set (match_operand:V2SF 0 "register_operand" "=y")
20884 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
20885 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20887 "pfsub\\t{%2, %0|%0, %2}"
20888 [(set_attr "type" "mmxadd")
20889 (set_attr "mode" "V2SF")])
20891 (define_insn "subrv2sf3"
20892 [(set (match_operand:V2SF 0 "register_operand" "=y")
20893 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
20894 (match_operand:V2SF 1 "register_operand" "0")))]
20896 "pfsubr\\t{%2, %0|%0, %2}"
20897 [(set_attr "type" "mmxadd")
20898 (set_attr "mode" "V2SF")])
20900 (define_insn "gtv2sf3"
20901 [(set (match_operand:V2SI 0 "register_operand" "=y")
20902 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
20903 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20905 "pfcmpgt\\t{%2, %0|%0, %2}"
20906 [(set_attr "type" "mmxcmp")
20907 (set_attr "mode" "V2SF")])
20909 (define_insn "gev2sf3"
20910 [(set (match_operand:V2SI 0 "register_operand" "=y")
20911 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
20912 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20914 "pfcmpge\\t{%2, %0|%0, %2}"
20915 [(set_attr "type" "mmxcmp")
20916 (set_attr "mode" "V2SF")])
20918 (define_insn "eqv2sf3"
20919 [(set (match_operand:V2SI 0 "register_operand" "=y")
20920 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
20921 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20923 "pfcmpeq\\t{%2, %0|%0, %2}"
20924 [(set_attr "type" "mmxcmp")
20925 (set_attr "mode" "V2SF")])
20927 (define_insn "pfmaxv2sf3"
20928 [(set (match_operand:V2SF 0 "register_operand" "=y")
20929 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
20930 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20932 "pfmax\\t{%2, %0|%0, %2}"
20933 [(set_attr "type" "mmxadd")
20934 (set_attr "mode" "V2SF")])
20936 (define_insn "pfminv2sf3"
20937 [(set (match_operand:V2SF 0 "register_operand" "=y")
20938 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
20939 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20941 "pfmin\\t{%2, %0|%0, %2}"
20942 [(set_attr "type" "mmxadd")
20943 (set_attr "mode" "V2SF")])
20945 (define_insn "mulv2sf3"
20946 [(set (match_operand:V2SF 0 "register_operand" "=y")
20947 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
20948 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
20950 "pfmul\\t{%2, %0|%0, %2}"
20951 [(set_attr "type" "mmxmul")
20952 (set_attr "mode" "V2SF")])
20954 (define_insn "femms"
20955 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
20956 (clobber (reg:XF 8))
20957 (clobber (reg:XF 9))
20958 (clobber (reg:XF 10))
20959 (clobber (reg:XF 11))
20960 (clobber (reg:XF 12))
20961 (clobber (reg:XF 13))
20962 (clobber (reg:XF 14))
20963 (clobber (reg:XF 15))
20964 (clobber (reg:DI 29))
20965 (clobber (reg:DI 30))
20966 (clobber (reg:DI 31))
20967 (clobber (reg:DI 32))
20968 (clobber (reg:DI 33))
20969 (clobber (reg:DI 34))
20970 (clobber (reg:DI 35))
20971 (clobber (reg:DI 36))]
20974 [(set_attr "type" "mmx")
20975 (set_attr "memory" "none")])
20977 (define_insn "pf2id"
20978 [(set (match_operand:V2SI 0 "register_operand" "=y")
20979 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
20981 "pf2id\\t{%1, %0|%0, %1}"
20982 [(set_attr "type" "mmxcvt")
20983 (set_attr "mode" "V2SF")])
20985 (define_insn "pf2iw"
20986 [(set (match_operand:V2SI 0 "register_operand" "=y")
20989 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
20991 "pf2iw\\t{%1, %0|%0, %1}"
20992 [(set_attr "type" "mmxcvt")
20993 (set_attr "mode" "V2SF")])
20995 (define_insn "pfacc"
20996 [(set (match_operand:V2SF 0 "register_operand" "=y")
20999 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21000 (parallel [(const_int 0)]))
21001 (vec_select:SF (match_dup 1)
21002 (parallel [(const_int 1)])))
21004 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21005 (parallel [(const_int 0)]))
21006 (vec_select:SF (match_dup 2)
21007 (parallel [(const_int 1)])))))]
21009 "pfacc\\t{%2, %0|%0, %2}"
21010 [(set_attr "type" "mmxadd")
21011 (set_attr "mode" "V2SF")])
21013 (define_insn "pfnacc"
21014 [(set (match_operand:V2SF 0 "register_operand" "=y")
21017 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21018 (parallel [(const_int 0)]))
21019 (vec_select:SF (match_dup 1)
21020 (parallel [(const_int 1)])))
21022 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21023 (parallel [(const_int 0)]))
21024 (vec_select:SF (match_dup 2)
21025 (parallel [(const_int 1)])))))]
21027 "pfnacc\\t{%2, %0|%0, %2}"
21028 [(set_attr "type" "mmxadd")
21029 (set_attr "mode" "V2SF")])
21031 (define_insn "pfpnacc"
21032 [(set (match_operand:V2SF 0 "register_operand" "=y")
21035 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21036 (parallel [(const_int 0)]))
21037 (vec_select:SF (match_dup 1)
21038 (parallel [(const_int 1)])))
21040 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21041 (parallel [(const_int 0)]))
21042 (vec_select:SF (match_dup 2)
21043 (parallel [(const_int 1)])))))]
21045 "pfpnacc\\t{%2, %0|%0, %2}"
21046 [(set_attr "type" "mmxadd")
21047 (set_attr "mode" "V2SF")])
21049 (define_insn "pi2fw"
21050 [(set (match_operand:V2SF 0 "register_operand" "=y")
21055 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21056 (parallel [(const_int 0)]))))
21059 (vec_select:SI (match_dup 1)
21060 (parallel [(const_int 1)])))))))]
21062 "pi2fw\\t{%1, %0|%0, %1}"
21063 [(set_attr "type" "mmxcvt")
21064 (set_attr "mode" "V2SF")])
21066 (define_insn "floatv2si2"
21067 [(set (match_operand:V2SF 0 "register_operand" "=y")
21068 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
21070 "pi2fd\\t{%1, %0|%0, %1}"
21071 [(set_attr "type" "mmxcvt")
21072 (set_attr "mode" "V2SF")])
21074 ;; This insn is identical to pavgb in operation, but the opcode is
21075 ;; different. To avoid accidentally matching pavgb, use an unspec.
21077 (define_insn "pavgusb"
21078 [(set (match_operand:V8QI 0 "register_operand" "=y")
21080 [(match_operand:V8QI 1 "register_operand" "0")
21081 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
21084 "pavgusb\\t{%2, %0|%0, %2}"
21085 [(set_attr "type" "mmxshft")
21086 (set_attr "mode" "TI")])
21088 ;; 3DNow reciprocal and sqrt
21090 (define_insn "pfrcpv2sf2"
21091 [(set (match_operand:V2SF 0 "register_operand" "=y")
21092 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21095 "pfrcp\\t{%1, %0|%0, %1}"
21096 [(set_attr "type" "mmx")
21097 (set_attr "mode" "TI")])
21099 (define_insn "pfrcpit1v2sf3"
21100 [(set (match_operand:V2SF 0 "register_operand" "=y")
21101 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21102 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21105 "pfrcpit1\\t{%2, %0|%0, %2}"
21106 [(set_attr "type" "mmx")
21107 (set_attr "mode" "TI")])
21109 (define_insn "pfrcpit2v2sf3"
21110 [(set (match_operand:V2SF 0 "register_operand" "=y")
21111 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21112 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21115 "pfrcpit2\\t{%2, %0|%0, %2}"
21116 [(set_attr "type" "mmx")
21117 (set_attr "mode" "TI")])
21119 (define_insn "pfrsqrtv2sf2"
21120 [(set (match_operand:V2SF 0 "register_operand" "=y")
21121 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21124 "pfrsqrt\\t{%1, %0|%0, %1}"
21125 [(set_attr "type" "mmx")
21126 (set_attr "mode" "TI")])
21128 (define_insn "pfrsqit1v2sf3"
21129 [(set (match_operand:V2SF 0 "register_operand" "=y")
21130 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21131 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21134 "pfrsqit1\\t{%2, %0|%0, %2}"
21135 [(set_attr "type" "mmx")
21136 (set_attr "mode" "TI")])
21138 (define_insn "pmulhrwv4hi3"
21139 [(set (match_operand:V4HI 0 "register_operand" "=y")
21145 (match_operand:V4HI 1 "register_operand" "0"))
21147 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21148 (const_vector:V4SI [(const_int 32768)
21151 (const_int 32768)]))
21154 "pmulhrw\\t{%2, %0|%0, %2}"
21155 [(set_attr "type" "mmxmul")
21156 (set_attr "mode" "TI")])
21158 (define_insn "pswapdv2si2"
21159 [(set (match_operand:V2SI 0 "register_operand" "=y")
21160 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21161 (parallel [(const_int 1) (const_int 0)])))]
21163 "pswapd\\t{%1, %0|%0, %1}"
21164 [(set_attr "type" "mmxcvt")
21165 (set_attr "mode" "TI")])
21167 (define_insn "pswapdv2sf2"
21168 [(set (match_operand:V2SF 0 "register_operand" "=y")
21169 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
21170 (parallel [(const_int 1) (const_int 0)])))]
21172 "pswapd\\t{%1, %0|%0, %1}"
21173 [(set_attr "type" "mmxcvt")
21174 (set_attr "mode" "TI")])
21176 (define_expand "prefetch"
21177 [(prefetch (match_operand 0 "address_operand" "")
21178 (match_operand:SI 1 "const_int_operand" "")
21179 (match_operand:SI 2 "const_int_operand" ""))]
21180 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
21182 int rw = INTVAL (operands[1]);
21183 int locality = INTVAL (operands[2]);
21185 if (rw != 0 && rw != 1)
21187 if (locality < 0 || locality > 3)
21189 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
21192 /* Use 3dNOW prefetch in case we are asking for write prefetch not
21193 suported by SSE counterpart or the SSE prefetch is not available
21194 (K6 machines). Otherwise use SSE prefetch as it allows specifying
21196 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
21197 operands[2] = GEN_INT (3);
21199 operands[1] = const0_rtx;
21202 (define_insn "*prefetch_sse"
21203 [(prefetch (match_operand:SI 0 "address_operand" "p")
21205 (match_operand:SI 1 "const_int_operand" ""))]
21206 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
21208 static const char * const patterns[4] = {
21209 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21212 int locality = INTVAL (operands[1]);
21213 if (locality < 0 || locality > 3)
21216 return patterns[locality];
21218 [(set_attr "type" "sse")
21219 (set_attr "memory" "none")])
21221 (define_insn "*prefetch_sse_rex"
21222 [(prefetch (match_operand:DI 0 "address_operand" "p")
21224 (match_operand:SI 1 "const_int_operand" ""))]
21225 "TARGET_PREFETCH_SSE && TARGET_64BIT"
21227 static const char * const patterns[4] = {
21228 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21231 int locality = INTVAL (operands[1]);
21232 if (locality < 0 || locality > 3)
21235 return patterns[locality];
21237 [(set_attr "type" "sse")
21238 (set_attr "memory" "none")])
21240 (define_insn "*prefetch_3dnow"
21241 [(prefetch (match_operand:SI 0 "address_operand" "p")
21242 (match_operand:SI 1 "const_int_operand" "n")
21244 "TARGET_3DNOW && !TARGET_64BIT"
21246 if (INTVAL (operands[1]) == 0)
21247 return "prefetch\t%a0";
21249 return "prefetchw\t%a0";
21251 [(set_attr "type" "mmx")
21252 (set_attr "memory" "none")])
21254 (define_insn "*prefetch_3dnow_rex"
21255 [(prefetch (match_operand:DI 0 "address_operand" "p")
21256 (match_operand:SI 1 "const_int_operand" "n")
21258 "TARGET_3DNOW && TARGET_64BIT"
21260 if (INTVAL (operands[1]) == 0)
21261 return "prefetch\t%a0";
21263 return "prefetchw\t%a0";
21265 [(set_attr "type" "mmx")
21266 (set_attr "memory" "none")])
21270 (define_insn "addv2df3"
21271 [(set (match_operand:V2DF 0 "register_operand" "=x")
21272 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21273 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21275 "addpd\t{%2, %0|%0, %2}"
21276 [(set_attr "type" "sseadd")
21277 (set_attr "mode" "V2DF")])
21279 (define_insn "vmaddv2df3"
21280 [(set (match_operand:V2DF 0 "register_operand" "=x")
21281 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21282 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21286 "addsd\t{%2, %0|%0, %2}"
21287 [(set_attr "type" "sseadd")
21288 (set_attr "mode" "DF")])
21290 (define_insn "subv2df3"
21291 [(set (match_operand:V2DF 0 "register_operand" "=x")
21292 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21293 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21295 "subpd\t{%2, %0|%0, %2}"
21296 [(set_attr "type" "sseadd")
21297 (set_attr "mode" "V2DF")])
21299 (define_insn "vmsubv2df3"
21300 [(set (match_operand:V2DF 0 "register_operand" "=x")
21301 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21302 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21306 "subsd\t{%2, %0|%0, %2}"
21307 [(set_attr "type" "sseadd")
21308 (set_attr "mode" "DF")])
21310 (define_insn "mulv2df3"
21311 [(set (match_operand:V2DF 0 "register_operand" "=x")
21312 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21313 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21315 "mulpd\t{%2, %0|%0, %2}"
21316 [(set_attr "type" "ssemul")
21317 (set_attr "mode" "V2DF")])
21319 (define_insn "vmmulv2df3"
21320 [(set (match_operand:V2DF 0 "register_operand" "=x")
21321 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21322 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21326 "mulsd\t{%2, %0|%0, %2}"
21327 [(set_attr "type" "ssemul")
21328 (set_attr "mode" "DF")])
21330 (define_insn "divv2df3"
21331 [(set (match_operand:V2DF 0 "register_operand" "=x")
21332 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21333 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21335 "divpd\t{%2, %0|%0, %2}"
21336 [(set_attr "type" "ssediv")
21337 (set_attr "mode" "V2DF")])
21339 (define_insn "vmdivv2df3"
21340 [(set (match_operand:V2DF 0 "register_operand" "=x")
21341 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21342 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21346 "divsd\t{%2, %0|%0, %2}"
21347 [(set_attr "type" "ssediv")
21348 (set_attr "mode" "DF")])
21352 (define_insn "smaxv2df3"
21353 [(set (match_operand:V2DF 0 "register_operand" "=x")
21354 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21355 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21357 "maxpd\t{%2, %0|%0, %2}"
21358 [(set_attr "type" "sseadd")
21359 (set_attr "mode" "V2DF")])
21361 (define_insn "vmsmaxv2df3"
21362 [(set (match_operand:V2DF 0 "register_operand" "=x")
21363 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21364 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21368 "maxsd\t{%2, %0|%0, %2}"
21369 [(set_attr "type" "sseadd")
21370 (set_attr "mode" "DF")])
21372 (define_insn "sminv2df3"
21373 [(set (match_operand:V2DF 0 "register_operand" "=x")
21374 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21375 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21377 "minpd\t{%2, %0|%0, %2}"
21378 [(set_attr "type" "sseadd")
21379 (set_attr "mode" "V2DF")])
21381 (define_insn "vmsminv2df3"
21382 [(set (match_operand:V2DF 0 "register_operand" "=x")
21383 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21384 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21388 "minsd\t{%2, %0|%0, %2}"
21389 [(set_attr "type" "sseadd")
21390 (set_attr "mode" "DF")])
21391 ;; SSE2 square root. There doesn't appear to be an extension for the
21392 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
21394 (define_insn "sqrtv2df2"
21395 [(set (match_operand:V2DF 0 "register_operand" "=x")
21396 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
21398 "sqrtpd\t{%1, %0|%0, %1}"
21399 [(set_attr "type" "sse")
21400 (set_attr "mode" "V2DF")])
21402 (define_insn "vmsqrtv2df2"
21403 [(set (match_operand:V2DF 0 "register_operand" "=x")
21404 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
21405 (match_operand:V2DF 2 "register_operand" "0")
21408 "sqrtsd\t{%1, %0|%0, %1}"
21409 [(set_attr "type" "sse")
21410 (set_attr "mode" "SF")])
21412 ;; SSE mask-generating compares
21414 (define_insn "maskcmpv2df3"
21415 [(set (match_operand:V2DI 0 "register_operand" "=x")
21416 (match_operator:V2DI 3 "sse_comparison_operator"
21417 [(match_operand:V2DF 1 "register_operand" "0")
21418 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
21420 "cmp%D3pd\t{%2, %0|%0, %2}"
21421 [(set_attr "type" "ssecmp")
21422 (set_attr "mode" "V2DF")])
21424 (define_insn "maskncmpv2df3"
21425 [(set (match_operand:V2DI 0 "register_operand" "=x")
21427 (match_operator:V2DI 3 "sse_comparison_operator"
21428 [(match_operand:V2DF 1 "register_operand" "0")
21429 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
21432 if (GET_CODE (operands[3]) == UNORDERED)
21433 return "cmpordps\t{%2, %0|%0, %2}";
21435 return "cmpn%D3pd\t{%2, %0|%0, %2}";
21437 [(set_attr "type" "ssecmp")
21438 (set_attr "mode" "V2DF")])
21440 (define_insn "vmmaskcmpv2df3"
21441 [(set (match_operand:V2DI 0 "register_operand" "=x")
21443 (match_operator:V2DI 3 "sse_comparison_operator"
21444 [(match_operand:V2DF 1 "register_operand" "0")
21445 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
21446 (subreg:V2DI (match_dup 1) 0)
21449 "cmp%D3sd\t{%2, %0|%0, %2}"
21450 [(set_attr "type" "ssecmp")
21451 (set_attr "mode" "DF")])
21453 (define_insn "vmmaskncmpv2df3"
21454 [(set (match_operand:V2DI 0 "register_operand" "=x")
21457 (match_operator:V2DI 3 "sse_comparison_operator"
21458 [(match_operand:V2DF 1 "register_operand" "0")
21459 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
21460 (subreg:V2DI (match_dup 1) 0)
21464 if (GET_CODE (operands[3]) == UNORDERED)
21465 return "cmpordsd\t{%2, %0|%0, %2}";
21467 return "cmpn%D3sd\t{%2, %0|%0, %2}";
21469 [(set_attr "type" "ssecmp")
21470 (set_attr "mode" "DF")])
21472 (define_insn "sse2_comi"
21473 [(set (reg:CCFP 17)
21474 (compare:CCFP (vec_select:DF
21475 (match_operand:V2DF 0 "register_operand" "x")
21476 (parallel [(const_int 0)]))
21478 (match_operand:V2DF 1 "register_operand" "x")
21479 (parallel [(const_int 0)]))))]
21481 "comisd\t{%1, %0|%0, %1}"
21482 [(set_attr "type" "ssecomi")
21483 (set_attr "mode" "DF")])
21485 (define_insn "sse2_ucomi"
21486 [(set (reg:CCFPU 17)
21487 (compare:CCFPU (vec_select:DF
21488 (match_operand:V2DF 0 "register_operand" "x")
21489 (parallel [(const_int 0)]))
21491 (match_operand:V2DF 1 "register_operand" "x")
21492 (parallel [(const_int 0)]))))]
21494 "ucomisd\t{%1, %0|%0, %1}"
21495 [(set_attr "type" "ssecomi")
21496 (set_attr "mode" "DF")])
21498 ;; SSE Strange Moves.
21500 (define_insn "sse2_movmskpd"
21501 [(set (match_operand:SI 0 "register_operand" "=r")
21502 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
21505 "movmskpd\t{%1, %0|%0, %1}"
21506 [(set_attr "type" "ssecvt")
21507 (set_attr "mode" "V2DF")])
21509 (define_insn "sse2_pmovmskb"
21510 [(set (match_operand:SI 0 "register_operand" "=r")
21511 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
21514 "pmovmskb\t{%1, %0|%0, %1}"
21515 [(set_attr "type" "ssecvt")
21516 (set_attr "mode" "V2DF")])
21518 (define_insn "sse2_maskmovdqu"
21519 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
21520 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21521 (match_operand:V16QI 2 "register_operand" "x")]
21524 ;; @@@ check ordering of operands in intel/nonintel syntax
21525 "maskmovdqu\t{%2, %1|%1, %2}"
21526 [(set_attr "type" "ssecvt")
21527 (set_attr "mode" "TI")])
21529 (define_insn "sse2_maskmovdqu_rex64"
21530 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
21531 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21532 (match_operand:V16QI 2 "register_operand" "x")]
21535 ;; @@@ check ordering of operands in intel/nonintel syntax
21536 "maskmovdqu\t{%2, %1|%1, %2}"
21537 [(set_attr "type" "ssecvt")
21538 (set_attr "mode" "TI")])
21540 (define_insn "sse2_movntv2df"
21541 [(set (match_operand:V2DF 0 "memory_operand" "=m")
21542 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
21545 "movntpd\t{%1, %0|%0, %1}"
21546 [(set_attr "type" "ssecvt")
21547 (set_attr "mode" "V2DF")])
21549 (define_insn "sse2_movntv2di"
21550 [(set (match_operand:V2DI 0 "memory_operand" "=m")
21551 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
21554 "movntdq\t{%1, %0|%0, %1}"
21555 [(set_attr "type" "ssecvt")
21556 (set_attr "mode" "TI")])
21558 (define_insn "sse2_movntsi"
21559 [(set (match_operand:SI 0 "memory_operand" "=m")
21560 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
21563 "movnti\t{%1, %0|%0, %1}"
21564 [(set_attr "type" "ssecvt")
21565 (set_attr "mode" "V2DF")])
21567 ;; SSE <-> integer/MMX conversions
21569 ;; Conversions between SI and SF
21571 (define_insn "cvtdq2ps"
21572 [(set (match_operand:V4SF 0 "register_operand" "=x")
21573 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
21575 "cvtdq2ps\t{%1, %0|%0, %1}"
21576 [(set_attr "type" "ssecvt")
21577 (set_attr "mode" "V2DF")])
21579 (define_insn "cvtps2dq"
21580 [(set (match_operand:V4SI 0 "register_operand" "=x")
21581 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
21583 "cvtps2dq\t{%1, %0|%0, %1}"
21584 [(set_attr "type" "ssecvt")
21585 (set_attr "mode" "TI")])
21587 (define_insn "cvttps2dq"
21588 [(set (match_operand:V4SI 0 "register_operand" "=x")
21589 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
21592 "cvttps2dq\t{%1, %0|%0, %1}"
21593 [(set_attr "type" "ssecvt")
21594 (set_attr "mode" "TI")])
21596 ;; Conversions between SI and DF
21598 (define_insn "cvtdq2pd"
21599 [(set (match_operand:V2DF 0 "register_operand" "=x")
21600 (float:V2DF (vec_select:V2SI
21601 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
21604 (const_int 1)]))))]
21606 "cvtdq2pd\t{%1, %0|%0, %1}"
21607 [(set_attr "type" "ssecvt")
21608 (set_attr "mode" "V2DF")])
21610 (define_insn "cvtpd2dq"
21611 [(set (match_operand:V4SI 0 "register_operand" "=x")
21613 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
21614 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
21616 "cvtpd2dq\t{%1, %0|%0, %1}"
21617 [(set_attr "type" "ssecvt")
21618 (set_attr "mode" "TI")])
21620 (define_insn "cvttpd2dq"
21621 [(set (match_operand:V4SI 0 "register_operand" "=x")
21623 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
21625 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
21627 "cvttpd2dq\t{%1, %0|%0, %1}"
21628 [(set_attr "type" "ssecvt")
21629 (set_attr "mode" "TI")])
21631 (define_insn "cvtpd2pi"
21632 [(set (match_operand:V2SI 0 "register_operand" "=y")
21633 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
21635 "cvtpd2pi\t{%1, %0|%0, %1}"
21636 [(set_attr "type" "ssecvt")
21637 (set_attr "mode" "TI")])
21639 (define_insn "cvttpd2pi"
21640 [(set (match_operand:V2SI 0 "register_operand" "=y")
21641 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
21644 "cvttpd2pi\t{%1, %0|%0, %1}"
21645 [(set_attr "type" "ssecvt")
21646 (set_attr "mode" "TI")])
21648 (define_insn "cvtpi2pd"
21649 [(set (match_operand:V2DF 0 "register_operand" "=x")
21650 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
21652 "cvtpi2pd\t{%1, %0|%0, %1}"
21653 [(set_attr "type" "ssecvt")
21654 (set_attr "mode" "TI")])
21656 ;; Conversions between SI and DF
21658 (define_insn "cvtsd2si"
21659 [(set (match_operand:SI 0 "register_operand" "=r,r")
21660 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
21661 (parallel [(const_int 0)]))))]
21663 "cvtsd2si\t{%1, %0|%0, %1}"
21664 [(set_attr "type" "sseicvt")
21665 (set_attr "athlon_decode" "double,vector")
21666 (set_attr "mode" "SI")])
21668 (define_insn "cvtsd2siq"
21669 [(set (match_operand:DI 0 "register_operand" "=r,r")
21670 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
21671 (parallel [(const_int 0)]))))]
21672 "TARGET_SSE2 && TARGET_64BIT"
21673 "cvtsd2siq\t{%1, %0|%0, %1}"
21674 [(set_attr "type" "sseicvt")
21675 (set_attr "athlon_decode" "double,vector")
21676 (set_attr "mode" "DI")])
21678 (define_insn "cvttsd2si"
21679 [(set (match_operand:SI 0 "register_operand" "=r,r")
21680 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
21681 (parallel [(const_int 0)]))] UNSPEC_FIX))]
21683 "cvttsd2si\t{%1, %0|%0, %1}"
21684 [(set_attr "type" "sseicvt")
21685 (set_attr "mode" "SI")
21686 (set_attr "athlon_decode" "double,vector")])
21688 (define_insn "cvttsd2siq"
21689 [(set (match_operand:DI 0 "register_operand" "=r,r")
21690 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
21691 (parallel [(const_int 0)]))] UNSPEC_FIX))]
21692 "TARGET_SSE2 && TARGET_64BIT"
21693 "cvttsd2siq\t{%1, %0|%0, %1}"
21694 [(set_attr "type" "sseicvt")
21695 (set_attr "mode" "DI")
21696 (set_attr "athlon_decode" "double,vector")])
21698 (define_insn "cvtsi2sd"
21699 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
21700 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
21701 (vec_duplicate:V2DF
21703 (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
21706 "cvtsi2sd\t{%2, %0|%0, %2}"
21707 [(set_attr "type" "sseicvt")
21708 (set_attr "mode" "DF")
21709 (set_attr "athlon_decode" "double,direct")])
21711 (define_insn "cvtsi2sdq"
21712 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
21713 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
21714 (vec_duplicate:V2DF
21716 (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
21718 "TARGET_SSE2 && TARGET_64BIT"
21719 "cvtsi2sdq\t{%2, %0|%0, %2}"
21720 [(set_attr "type" "sseicvt")
21721 (set_attr "mode" "DF")
21722 (set_attr "athlon_decode" "double,direct")])
21724 ;; Conversions between SF and DF
21726 (define_insn "cvtsd2ss"
21727 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21728 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
21729 (vec_duplicate:V4SF
21730 (float_truncate:V2SF
21731 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
21734 "cvtsd2ss\t{%2, %0|%0, %2}"
21735 [(set_attr "type" "ssecvt")
21736 (set_attr "athlon_decode" "vector,double")
21737 (set_attr "mode" "SF")])
21739 (define_insn "cvtss2sd"
21740 [(set (match_operand:V2DF 0 "register_operand" "=x")
21741 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
21744 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
21745 (parallel [(const_int 0)
21749 "cvtss2sd\t{%2, %0|%0, %2}"
21750 [(set_attr "type" "ssecvt")
21751 (set_attr "mode" "DF")])
21753 (define_insn "cvtpd2ps"
21754 [(set (match_operand:V4SF 0 "register_operand" "=x")
21757 (subreg:V2SI (float_truncate:V2SF
21758 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
21759 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
21761 "cvtpd2ps\t{%1, %0|%0, %1}"
21762 [(set_attr "type" "ssecvt")
21763 (set_attr "mode" "V4SF")])
21765 (define_insn "cvtps2pd"
21766 [(set (match_operand:V2DF 0 "register_operand" "=x")
21768 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
21769 (parallel [(const_int 0)
21770 (const_int 1)]))))]
21772 "cvtps2pd\t{%1, %0|%0, %1}"
21773 [(set_attr "type" "ssecvt")
21774 (set_attr "mode" "V2DF")])
21776 ;; SSE2 variants of MMX insns
21780 (define_insn "addv16qi3"
21781 [(set (match_operand:V16QI 0 "register_operand" "=x")
21782 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
21783 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21785 "paddb\t{%2, %0|%0, %2}"
21786 [(set_attr "type" "sseiadd")
21787 (set_attr "mode" "TI")])
21789 (define_insn "addv8hi3"
21790 [(set (match_operand:V8HI 0 "register_operand" "=x")
21791 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
21792 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21794 "paddw\t{%2, %0|%0, %2}"
21795 [(set_attr "type" "sseiadd")
21796 (set_attr "mode" "TI")])
21798 (define_insn "addv4si3"
21799 [(set (match_operand:V4SI 0 "register_operand" "=x")
21800 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
21801 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21803 "paddd\t{%2, %0|%0, %2}"
21804 [(set_attr "type" "sseiadd")
21805 (set_attr "mode" "TI")])
21807 (define_insn "addv2di3"
21808 [(set (match_operand:V2DI 0 "register_operand" "=x")
21809 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
21810 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21812 "paddq\t{%2, %0|%0, %2}"
21813 [(set_attr "type" "sseiadd")
21814 (set_attr "mode" "TI")])
21816 (define_insn "ssaddv16qi3"
21817 [(set (match_operand:V16QI 0 "register_operand" "=x")
21818 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
21819 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21821 "paddsb\t{%2, %0|%0, %2}"
21822 [(set_attr "type" "sseiadd")
21823 (set_attr "mode" "TI")])
21825 (define_insn "ssaddv8hi3"
21826 [(set (match_operand:V8HI 0 "register_operand" "=x")
21827 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
21828 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21830 "paddsw\t{%2, %0|%0, %2}"
21831 [(set_attr "type" "sseiadd")
21832 (set_attr "mode" "TI")])
21834 (define_insn "usaddv16qi3"
21835 [(set (match_operand:V16QI 0 "register_operand" "=x")
21836 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
21837 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21839 "paddusb\t{%2, %0|%0, %2}"
21840 [(set_attr "type" "sseiadd")
21841 (set_attr "mode" "TI")])
21843 (define_insn "usaddv8hi3"
21844 [(set (match_operand:V8HI 0 "register_operand" "=x")
21845 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
21846 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21848 "paddusw\t{%2, %0|%0, %2}"
21849 [(set_attr "type" "sseiadd")
21850 (set_attr "mode" "TI")])
21852 (define_insn "subv16qi3"
21853 [(set (match_operand:V16QI 0 "register_operand" "=x")
21854 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21855 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21857 "psubb\t{%2, %0|%0, %2}"
21858 [(set_attr "type" "sseiadd")
21859 (set_attr "mode" "TI")])
21861 (define_insn "subv8hi3"
21862 [(set (match_operand:V8HI 0 "register_operand" "=x")
21863 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21864 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21866 "psubw\t{%2, %0|%0, %2}"
21867 [(set_attr "type" "sseiadd")
21868 (set_attr "mode" "TI")])
21870 (define_insn "subv4si3"
21871 [(set (match_operand:V4SI 0 "register_operand" "=x")
21872 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
21873 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
21875 "psubd\t{%2, %0|%0, %2}"
21876 [(set_attr "type" "sseiadd")
21877 (set_attr "mode" "TI")])
21879 (define_insn "subv2di3"
21880 [(set (match_operand:V2DI 0 "register_operand" "=x")
21881 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
21882 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
21884 "psubq\t{%2, %0|%0, %2}"
21885 [(set_attr "type" "sseiadd")
21886 (set_attr "mode" "TI")])
21888 (define_insn "sssubv16qi3"
21889 [(set (match_operand:V16QI 0 "register_operand" "=x")
21890 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21891 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21893 "psubsb\t{%2, %0|%0, %2}"
21894 [(set_attr "type" "sseiadd")
21895 (set_attr "mode" "TI")])
21897 (define_insn "sssubv8hi3"
21898 [(set (match_operand:V8HI 0 "register_operand" "=x")
21899 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21900 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21902 "psubsw\t{%2, %0|%0, %2}"
21903 [(set_attr "type" "sseiadd")
21904 (set_attr "mode" "TI")])
21906 (define_insn "ussubv16qi3"
21907 [(set (match_operand:V16QI 0 "register_operand" "=x")
21908 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
21909 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
21911 "psubusb\t{%2, %0|%0, %2}"
21912 [(set_attr "type" "sseiadd")
21913 (set_attr "mode" "TI")])
21915 (define_insn "ussubv8hi3"
21916 [(set (match_operand:V8HI 0 "register_operand" "=x")
21917 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
21918 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21920 "psubusw\t{%2, %0|%0, %2}"
21921 [(set_attr "type" "sseiadd")
21922 (set_attr "mode" "TI")])
21924 (define_insn "mulv8hi3"
21925 [(set (match_operand:V8HI 0 "register_operand" "=x")
21926 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
21927 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
21929 "pmullw\t{%2, %0|%0, %2}"
21930 [(set_attr "type" "sseimul")
21931 (set_attr "mode" "TI")])
21933 (define_insn "smulv8hi3_highpart"
21934 [(set (match_operand:V8HI 0 "register_operand" "=x")
21937 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
21938 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
21941 "pmulhw\t{%2, %0|%0, %2}"
21942 [(set_attr "type" "sseimul")
21943 (set_attr "mode" "TI")])
21945 (define_insn "umulv8hi3_highpart"
21946 [(set (match_operand:V8HI 0 "register_operand" "=x")
21949 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
21950 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
21953 "pmulhuw\t{%2, %0|%0, %2}"
21954 [(set_attr "type" "sseimul")
21955 (set_attr "mode" "TI")])
21957 (define_insn "sse2_umulsidi3"
21958 [(set (match_operand:DI 0 "register_operand" "=y")
21959 (mult:DI (zero_extend:DI (vec_select:SI
21960 (match_operand:V2SI 1 "register_operand" "0")
21961 (parallel [(const_int 0)])))
21962 (zero_extend:DI (vec_select:SI
21963 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
21964 (parallel [(const_int 0)])))))]
21966 "pmuludq\t{%2, %0|%0, %2}"
21967 [(set_attr "type" "sseimul")
21968 (set_attr "mode" "TI")])
21970 (define_insn "sse2_umulv2siv2di3"
21971 [(set (match_operand:V2DI 0 "register_operand" "=x")
21972 (mult:V2DI (zero_extend:V2DI
21974 (match_operand:V4SI 1 "register_operand" "0")
21975 (parallel [(const_int 0) (const_int 2)])))
21978 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
21979 (parallel [(const_int 0) (const_int 2)])))))]
21981 "pmuludq\t{%2, %0|%0, %2}"
21982 [(set_attr "type" "sseimul")
21983 (set_attr "mode" "TI")])
21985 (define_insn "sse2_pmaddwd"
21986 [(set (match_operand:V4SI 0 "register_operand" "=x")
21989 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
21990 (parallel [(const_int 0)
21994 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
21995 (parallel [(const_int 0)
22000 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
22001 (parallel [(const_int 1)
22005 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
22006 (parallel [(const_int 1)
22009 (const_int 7)]))))))]
22011 "pmaddwd\t{%2, %0|%0, %2}"
22012 [(set_attr "type" "sseiadd")
22013 (set_attr "mode" "TI")])
22015 ;; Same as pxor, but don't show input operands so that we don't think
22017 (define_insn "sse2_clrti"
22018 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
22021 if (get_attr_mode (insn) == MODE_TI)
22022 return "pxor\t%0, %0";
22024 return "xorps\t%0, %0";
22026 [(set_attr "type" "ssemov")
22027 (set_attr "memory" "none")
22030 (ne (symbol_ref "optimize_size")
22032 (const_string "V4SF")
22033 (const_string "TI")))])
22035 ;; MMX unsigned averages/sum of absolute differences
22037 (define_insn "sse2_uavgv16qi3"
22038 [(set (match_operand:V16QI 0 "register_operand" "=x")
22040 (plus:V16QI (plus:V16QI
22041 (match_operand:V16QI 1 "register_operand" "0")
22042 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
22043 (const_vector:V16QI [(const_int 1) (const_int 1)
22044 (const_int 1) (const_int 1)
22045 (const_int 1) (const_int 1)
22046 (const_int 1) (const_int 1)
22047 (const_int 1) (const_int 1)
22048 (const_int 1) (const_int 1)
22049 (const_int 1) (const_int 1)
22050 (const_int 1) (const_int 1)]))
22053 "pavgb\t{%2, %0|%0, %2}"
22054 [(set_attr "type" "sseiadd")
22055 (set_attr "mode" "TI")])
22057 (define_insn "sse2_uavgv8hi3"
22058 [(set (match_operand:V8HI 0 "register_operand" "=x")
22060 (plus:V8HI (plus:V8HI
22061 (match_operand:V8HI 1 "register_operand" "0")
22062 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
22063 (const_vector:V8HI [(const_int 1) (const_int 1)
22064 (const_int 1) (const_int 1)
22065 (const_int 1) (const_int 1)
22066 (const_int 1) (const_int 1)]))
22069 "pavgw\t{%2, %0|%0, %2}"
22070 [(set_attr "type" "sseiadd")
22071 (set_attr "mode" "TI")])
22073 ;; @@@ this isn't the right representation.
22074 (define_insn "sse2_psadbw"
22075 [(set (match_operand:V2DI 0 "register_operand" "=x")
22076 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
22077 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
22080 "psadbw\t{%2, %0|%0, %2}"
22081 [(set_attr "type" "sseiadd")
22082 (set_attr "mode" "TI")])
22085 ;; MMX insert/extract/shuffle
22087 (define_insn "sse2_pinsrw"
22088 [(set (match_operand:V8HI 0 "register_operand" "=x")
22089 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
22090 (vec_duplicate:V8HI
22092 (match_operand:SI 2 "nonimmediate_operand" "rm")))
22093 (match_operand:SI 3 "const_0_to_255_operand" "N")))]
22095 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
22096 [(set_attr "type" "ssecvt")
22097 (set_attr "mode" "TI")])
22099 (define_insn "sse2_pextrw"
22100 [(set (match_operand:SI 0 "register_operand" "=r")
22102 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
22104 [(match_operand:SI 2 "const_0_to_7_operand" "N")]))))]
22106 "pextrw\t{%2, %1, %0|%0, %1, %2}"
22107 [(set_attr "type" "ssecvt")
22108 (set_attr "mode" "TI")])
22110 (define_insn "sse2_pshufd"
22111 [(set (match_operand:V4SI 0 "register_operand" "=x")
22112 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
22113 (match_operand:SI 2 "immediate_operand" "i")]
22116 "pshufd\t{%2, %1, %0|%0, %1, %2}"
22117 [(set_attr "type" "ssecvt")
22118 (set_attr "mode" "TI")])
22120 (define_insn "sse2_pshuflw"
22121 [(set (match_operand:V8HI 0 "register_operand" "=x")
22122 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22123 (match_operand:SI 2 "immediate_operand" "i")]
22126 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
22127 [(set_attr "type" "ssecvt")
22128 (set_attr "mode" "TI")])
22130 (define_insn "sse2_pshufhw"
22131 [(set (match_operand:V8HI 0 "register_operand" "=x")
22132 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22133 (match_operand:SI 2 "immediate_operand" "i")]
22136 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
22137 [(set_attr "type" "ssecvt")
22138 (set_attr "mode" "TI")])
22140 ;; MMX mask-generating comparisons
22142 (define_insn "eqv16qi3"
22143 [(set (match_operand:V16QI 0 "register_operand" "=x")
22144 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
22145 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22147 "pcmpeqb\t{%2, %0|%0, %2}"
22148 [(set_attr "type" "ssecmp")
22149 (set_attr "mode" "TI")])
22151 (define_insn "eqv8hi3"
22152 [(set (match_operand:V8HI 0 "register_operand" "=x")
22153 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
22154 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22156 "pcmpeqw\t{%2, %0|%0, %2}"
22157 [(set_attr "type" "ssecmp")
22158 (set_attr "mode" "TI")])
22160 (define_insn "eqv4si3"
22161 [(set (match_operand:V4SI 0 "register_operand" "=x")
22162 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
22163 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22165 "pcmpeqd\t{%2, %0|%0, %2}"
22166 [(set_attr "type" "ssecmp")
22167 (set_attr "mode" "TI")])
22169 (define_insn "gtv16qi3"
22170 [(set (match_operand:V16QI 0 "register_operand" "=x")
22171 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
22172 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22174 "pcmpgtb\t{%2, %0|%0, %2}"
22175 [(set_attr "type" "ssecmp")
22176 (set_attr "mode" "TI")])
22178 (define_insn "gtv8hi3"
22179 [(set (match_operand:V8HI 0 "register_operand" "=x")
22180 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22181 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22183 "pcmpgtw\t{%2, %0|%0, %2}"
22184 [(set_attr "type" "ssecmp")
22185 (set_attr "mode" "TI")])
22187 (define_insn "gtv4si3"
22188 [(set (match_operand:V4SI 0 "register_operand" "=x")
22189 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22190 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22192 "pcmpgtd\t{%2, %0|%0, %2}"
22193 [(set_attr "type" "ssecmp")
22194 (set_attr "mode" "TI")])
22197 ;; MMX max/min insns
22199 (define_insn "umaxv16qi3"
22200 [(set (match_operand:V16QI 0 "register_operand" "=x")
22201 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
22202 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22204 "pmaxub\t{%2, %0|%0, %2}"
22205 [(set_attr "type" "sseiadd")
22206 (set_attr "mode" "TI")])
22208 (define_insn "smaxv8hi3"
22209 [(set (match_operand:V8HI 0 "register_operand" "=x")
22210 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
22211 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22213 "pmaxsw\t{%2, %0|%0, %2}"
22214 [(set_attr "type" "sseiadd")
22215 (set_attr "mode" "TI")])
22217 (define_insn "uminv16qi3"
22218 [(set (match_operand:V16QI 0 "register_operand" "=x")
22219 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
22220 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22222 "pminub\t{%2, %0|%0, %2}"
22223 [(set_attr "type" "sseiadd")
22224 (set_attr "mode" "TI")])
22226 (define_insn "sminv8hi3"
22227 [(set (match_operand:V8HI 0 "register_operand" "=x")
22228 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
22229 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22231 "pminsw\t{%2, %0|%0, %2}"
22232 [(set_attr "type" "sseiadd")
22233 (set_attr "mode" "TI")])
22238 (define_insn "ashrv8hi3"
22239 [(set (match_operand:V8HI 0 "register_operand" "=x")
22240 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22241 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22243 "psraw\t{%2, %0|%0, %2}"
22244 [(set_attr "type" "sseishft")
22245 (set_attr "mode" "TI")])
22247 (define_insn "ashrv4si3"
22248 [(set (match_operand:V4SI 0 "register_operand" "=x")
22249 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22250 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22252 "psrad\t{%2, %0|%0, %2}"
22253 [(set_attr "type" "sseishft")
22254 (set_attr "mode" "TI")])
22256 (define_insn "lshrv8hi3"
22257 [(set (match_operand:V8HI 0 "register_operand" "=x")
22258 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22259 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22261 "psrlw\t{%2, %0|%0, %2}"
22262 [(set_attr "type" "sseishft")
22263 (set_attr "mode" "TI")])
22265 (define_insn "lshrv4si3"
22266 [(set (match_operand:V4SI 0 "register_operand" "=x")
22267 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22268 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22270 "psrld\t{%2, %0|%0, %2}"
22271 [(set_attr "type" "sseishft")
22272 (set_attr "mode" "TI")])
22274 (define_insn "lshrv2di3"
22275 [(set (match_operand:V2DI 0 "register_operand" "=x")
22276 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22277 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22279 "psrlq\t{%2, %0|%0, %2}"
22280 [(set_attr "type" "sseishft")
22281 (set_attr "mode" "TI")])
22283 (define_insn "ashlv8hi3"
22284 [(set (match_operand:V8HI 0 "register_operand" "=x")
22285 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22286 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22288 "psllw\t{%2, %0|%0, %2}"
22289 [(set_attr "type" "sseishft")
22290 (set_attr "mode" "TI")])
22292 (define_insn "ashlv4si3"
22293 [(set (match_operand:V4SI 0 "register_operand" "=x")
22294 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22295 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22297 "pslld\t{%2, %0|%0, %2}"
22298 [(set_attr "type" "sseishft")
22299 (set_attr "mode" "TI")])
22301 (define_insn "ashlv2di3"
22302 [(set (match_operand:V2DI 0 "register_operand" "=x")
22303 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22304 (match_operand:SI 2 "nonmemory_operand" "xi")))]
22306 "psllq\t{%2, %0|%0, %2}"
22307 [(set_attr "type" "sseishft")
22308 (set_attr "mode" "TI")])
22310 (define_insn "ashrv8hi3_ti"
22311 [(set (match_operand:V8HI 0 "register_operand" "=x")
22312 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22313 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22315 "psraw\t{%2, %0|%0, %2}"
22316 [(set_attr "type" "sseishft")
22317 (set_attr "mode" "TI")])
22319 (define_insn "ashrv4si3_ti"
22320 [(set (match_operand:V4SI 0 "register_operand" "=x")
22321 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22322 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22324 "psrad\t{%2, %0|%0, %2}"
22325 [(set_attr "type" "sseishft")
22326 (set_attr "mode" "TI")])
22328 (define_insn "lshrv8hi3_ti"
22329 [(set (match_operand:V8HI 0 "register_operand" "=x")
22330 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22331 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22333 "psrlw\t{%2, %0|%0, %2}"
22334 [(set_attr "type" "sseishft")
22335 (set_attr "mode" "TI")])
22337 (define_insn "lshrv4si3_ti"
22338 [(set (match_operand:V4SI 0 "register_operand" "=x")
22339 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22340 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22342 "psrld\t{%2, %0|%0, %2}"
22343 [(set_attr "type" "sseishft")
22344 (set_attr "mode" "TI")])
22346 (define_insn "lshrv2di3_ti"
22347 [(set (match_operand:V2DI 0 "register_operand" "=x")
22348 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22349 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22351 "psrlq\t{%2, %0|%0, %2}"
22352 [(set_attr "type" "sseishft")
22353 (set_attr "mode" "TI")])
22355 (define_insn "ashlv8hi3_ti"
22356 [(set (match_operand:V8HI 0 "register_operand" "=x")
22357 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22358 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22360 "psllw\t{%2, %0|%0, %2}"
22361 [(set_attr "type" "sseishft")
22362 (set_attr "mode" "TI")])
22364 (define_insn "ashlv4si3_ti"
22365 [(set (match_operand:V4SI 0 "register_operand" "=x")
22366 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22367 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22369 "pslld\t{%2, %0|%0, %2}"
22370 [(set_attr "type" "sseishft")
22371 (set_attr "mode" "TI")])
22373 (define_insn "ashlv2di3_ti"
22374 [(set (match_operand:V2DI 0 "register_operand" "=x")
22375 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22376 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22378 "psllq\t{%2, %0|%0, %2}"
22379 [(set_attr "type" "sseishft")
22380 (set_attr "mode" "TI")])
22382 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
22383 ;; we wouldn't need here it since we never generate TImode arithmetic.
22385 ;; There has to be some kind of prize for the weirdest new instruction...
22386 (define_insn "sse2_ashlti3"
22387 [(set (match_operand:TI 0 "register_operand" "=x")
22389 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
22390 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22391 (const_int 8)))] UNSPEC_NOP))]
22393 "pslldq\t{%2, %0|%0, %2}"
22394 [(set_attr "type" "sseishft")
22395 (set_attr "mode" "TI")])
22397 (define_insn "sse2_lshrti3"
22398 [(set (match_operand:TI 0 "register_operand" "=x")
22400 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
22401 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22402 (const_int 8)))] UNSPEC_NOP))]
22404 "psrldq\t{%2, %0|%0, %2}"
22405 [(set_attr "type" "sseishft")
22406 (set_attr "mode" "TI")])
22410 (define_insn "sse2_unpckhpd"
22411 [(set (match_operand:V2DF 0 "register_operand" "=x")
22413 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22414 (parallel [(const_int 1)]))
22415 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22416 (parallel [(const_int 1)]))))]
22418 "unpckhpd\t{%2, %0|%0, %2}"
22419 [(set_attr "type" "ssecvt")
22420 (set_attr "mode" "V2DF")])
22422 (define_insn "sse2_unpcklpd"
22423 [(set (match_operand:V2DF 0 "register_operand" "=x")
22425 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22426 (parallel [(const_int 0)]))
22427 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22428 (parallel [(const_int 0)]))))]
22430 "unpcklpd\t{%2, %0|%0, %2}"
22431 [(set_attr "type" "ssecvt")
22432 (set_attr "mode" "V2DF")])
22434 ;; MMX pack/unpack insns.
22436 (define_insn "sse2_packsswb"
22437 [(set (match_operand:V16QI 0 "register_operand" "=x")
22439 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22440 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22442 "packsswb\t{%2, %0|%0, %2}"
22443 [(set_attr "type" "ssecvt")
22444 (set_attr "mode" "TI")])
22446 (define_insn "sse2_packssdw"
22447 [(set (match_operand:V8HI 0 "register_operand" "=x")
22449 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
22450 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
22452 "packssdw\t{%2, %0|%0, %2}"
22453 [(set_attr "type" "ssecvt")
22454 (set_attr "mode" "TI")])
22456 (define_insn "sse2_packuswb"
22457 [(set (match_operand:V16QI 0 "register_operand" "=x")
22459 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22460 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22462 "packuswb\t{%2, %0|%0, %2}"
22463 [(set_attr "type" "ssecvt")
22464 (set_attr "mode" "TI")])
22466 (define_insn "sse2_punpckhbw"
22467 [(set (match_operand:V16QI 0 "register_operand" "=x")
22469 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22470 (parallel [(const_int 8) (const_int 0)
22471 (const_int 9) (const_int 1)
22472 (const_int 10) (const_int 2)
22473 (const_int 11) (const_int 3)
22474 (const_int 12) (const_int 4)
22475 (const_int 13) (const_int 5)
22476 (const_int 14) (const_int 6)
22477 (const_int 15) (const_int 7)]))
22478 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22479 (parallel [(const_int 0) (const_int 8)
22480 (const_int 1) (const_int 9)
22481 (const_int 2) (const_int 10)
22482 (const_int 3) (const_int 11)
22483 (const_int 4) (const_int 12)
22484 (const_int 5) (const_int 13)
22485 (const_int 6) (const_int 14)
22486 (const_int 7) (const_int 15)]))
22487 (const_int 21845)))]
22489 "punpckhbw\t{%2, %0|%0, %2}"
22490 [(set_attr "type" "ssecvt")
22491 (set_attr "mode" "TI")])
22493 (define_insn "sse2_punpckhwd"
22494 [(set (match_operand:V8HI 0 "register_operand" "=x")
22496 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22497 (parallel [(const_int 4) (const_int 0)
22498 (const_int 5) (const_int 1)
22499 (const_int 6) (const_int 2)
22500 (const_int 7) (const_int 3)]))
22501 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22502 (parallel [(const_int 0) (const_int 4)
22503 (const_int 1) (const_int 5)
22504 (const_int 2) (const_int 6)
22505 (const_int 3) (const_int 7)]))
22508 "punpckhwd\t{%2, %0|%0, %2}"
22509 [(set_attr "type" "ssecvt")
22510 (set_attr "mode" "TI")])
22512 (define_insn "sse2_punpckhdq"
22513 [(set (match_operand:V4SI 0 "register_operand" "=x")
22515 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22516 (parallel [(const_int 2) (const_int 0)
22517 (const_int 3) (const_int 1)]))
22518 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22519 (parallel [(const_int 0) (const_int 2)
22520 (const_int 1) (const_int 3)]))
22523 "punpckhdq\t{%2, %0|%0, %2}"
22524 [(set_attr "type" "ssecvt")
22525 (set_attr "mode" "TI")])
22527 (define_insn "sse2_punpcklbw"
22528 [(set (match_operand:V16QI 0 "register_operand" "=x")
22530 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22531 (parallel [(const_int 0) (const_int 8)
22532 (const_int 1) (const_int 9)
22533 (const_int 2) (const_int 10)
22534 (const_int 3) (const_int 11)
22535 (const_int 4) (const_int 12)
22536 (const_int 5) (const_int 13)
22537 (const_int 6) (const_int 14)
22538 (const_int 7) (const_int 15)]))
22539 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22540 (parallel [(const_int 8) (const_int 0)
22541 (const_int 9) (const_int 1)
22542 (const_int 10) (const_int 2)
22543 (const_int 11) (const_int 3)
22544 (const_int 12) (const_int 4)
22545 (const_int 13) (const_int 5)
22546 (const_int 14) (const_int 6)
22547 (const_int 15) (const_int 7)]))
22548 (const_int 21845)))]
22550 "punpcklbw\t{%2, %0|%0, %2}"
22551 [(set_attr "type" "ssecvt")
22552 (set_attr "mode" "TI")])
22554 (define_insn "sse2_punpcklwd"
22555 [(set (match_operand:V8HI 0 "register_operand" "=x")
22557 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22558 (parallel [(const_int 0) (const_int 4)
22559 (const_int 1) (const_int 5)
22560 (const_int 2) (const_int 6)
22561 (const_int 3) (const_int 7)]))
22562 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22563 (parallel [(const_int 4) (const_int 0)
22564 (const_int 5) (const_int 1)
22565 (const_int 6) (const_int 2)
22566 (const_int 7) (const_int 3)]))
22569 "punpcklwd\t{%2, %0|%0, %2}"
22570 [(set_attr "type" "ssecvt")
22571 (set_attr "mode" "TI")])
22573 (define_insn "sse2_punpckldq"
22574 [(set (match_operand:V4SI 0 "register_operand" "=x")
22576 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22577 (parallel [(const_int 0) (const_int 2)
22578 (const_int 1) (const_int 3)]))
22579 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22580 (parallel [(const_int 2) (const_int 0)
22581 (const_int 3) (const_int 1)]))
22584 "punpckldq\t{%2, %0|%0, %2}"
22585 [(set_attr "type" "ssecvt")
22586 (set_attr "mode" "TI")])
22588 (define_insn "sse2_punpcklqdq"
22589 [(set (match_operand:V2DI 0 "register_operand" "=x")
22591 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
22592 (parallel [(const_int 1)
22594 (match_operand:V2DI 1 "register_operand" "0")
22597 "punpcklqdq\t{%2, %0|%0, %2}"
22598 [(set_attr "type" "ssecvt")
22599 (set_attr "mode" "TI")])
22601 (define_insn "sse2_punpckhqdq"
22602 [(set (match_operand:V2DI 0 "register_operand" "=x")
22604 (match_operand:V2DI 1 "register_operand" "0")
22605 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
22606 (parallel [(const_int 1)
22610 "punpckhqdq\t{%2, %0|%0, %2}"
22611 [(set_attr "type" "ssecvt")
22612 (set_attr "mode" "TI")])
22616 (define_insn "sse2_movapd"
22617 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22618 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
22621 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22622 "movapd\t{%1, %0|%0, %1}"
22623 [(set_attr "type" "ssemov")
22624 (set_attr "mode" "V2DF")])
22626 (define_insn "sse2_movupd"
22627 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22628 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
22631 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22632 "movupd\t{%1, %0|%0, %1}"
22633 [(set_attr "type" "ssecvt")
22634 (set_attr "mode" "V2DF")])
22636 (define_insn "sse2_movdqa"
22637 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
22638 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
22641 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22642 "movdqa\t{%1, %0|%0, %1}"
22643 [(set_attr "type" "ssemov")
22644 (set_attr "mode" "TI")])
22646 (define_insn "sse2_movdqu"
22647 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
22648 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
22651 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22652 "movdqu\t{%1, %0|%0, %1}"
22653 [(set_attr "type" "ssecvt")
22654 (set_attr "mode" "TI")])
22656 (define_insn "sse2_movdq2q"
22657 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
22658 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
22659 (parallel [(const_int 0)])))]
22660 "TARGET_SSE2 && !TARGET_64BIT"
22662 movq\t{%1, %0|%0, %1}
22663 movdq2q\t{%1, %0|%0, %1}"
22664 [(set_attr "type" "ssecvt")
22665 (set_attr "mode" "TI")])
22667 (define_insn "sse2_movdq2q_rex64"
22668 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
22669 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
22670 (parallel [(const_int 0)])))]
22671 "TARGET_SSE2 && TARGET_64BIT"
22673 movq\t{%1, %0|%0, %1}
22674 movdq2q\t{%1, %0|%0, %1}
22675 movd\t{%1, %0|%0, %1}"
22676 [(set_attr "type" "ssecvt")
22677 (set_attr "mode" "TI")])
22679 (define_insn "sse2_movq2dq"
22680 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
22681 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
22683 "TARGET_SSE2 && !TARGET_64BIT"
22685 movq\t{%1, %0|%0, %1}
22686 movq2dq\t{%1, %0|%0, %1}"
22687 [(set_attr "type" "ssecvt,ssemov")
22688 (set_attr "mode" "TI")])
22690 (define_insn "sse2_movq2dq_rex64"
22691 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
22692 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
22694 "TARGET_SSE2 && TARGET_64BIT"
22696 movq\t{%1, %0|%0, %1}
22697 movq2dq\t{%1, %0|%0, %1}
22698 movd\t{%1, %0|%0, %1}"
22699 [(set_attr "type" "ssecvt,ssemov,ssecvt")
22700 (set_attr "mode" "TI")])
22702 (define_insn "sse2_movq"
22703 [(set (match_operand:V2DI 0 "register_operand" "=x")
22704 (vec_concat:V2DI (vec_select:DI
22705 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
22706 (parallel [(const_int 0)]))
22709 "movq\t{%1, %0|%0, %1}"
22710 [(set_attr "type" "ssemov")
22711 (set_attr "mode" "TI")])
22713 (define_insn "sse2_loadd"
22714 [(set (match_operand:V4SI 0 "register_operand" "=x")
22716 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
22717 (const_vector:V4SI [(const_int 0)
22723 "movd\t{%1, %0|%0, %1}"
22724 [(set_attr "type" "ssemov")
22725 (set_attr "mode" "TI")])
22727 (define_insn "sse2_stored"
22728 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
22730 (match_operand:V4SI 1 "register_operand" "x")
22731 (parallel [(const_int 0)])))]
22733 "movd\t{%1, %0|%0, %1}"
22734 [(set_attr "type" "ssemov")
22735 (set_attr "mode" "TI")])
22737 (define_insn "sse2_movhpd"
22738 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22740 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
22741 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
22743 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
22744 "movhpd\t{%2, %0|%0, %2}"
22745 [(set_attr "type" "ssecvt")
22746 (set_attr "mode" "V2DF")])
22748 (define_expand "sse2_loadsd"
22749 [(match_operand:V2DF 0 "register_operand" "")
22750 (match_operand:DF 1 "memory_operand" "")]
22753 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
22754 CONST0_RTX (V2DFmode)));
22758 (define_insn "sse2_loadsd_1"
22759 [(set (match_operand:V2DF 0 "register_operand" "=x")
22761 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
22762 (match_operand:V2DF 2 "const0_operand" "X")
22765 "movsd\t{%1, %0|%0, %1}"
22766 [(set_attr "type" "ssecvt")
22767 (set_attr "mode" "DF")])
22769 (define_insn "sse2_movsd"
22770 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
22772 (match_operand:V2DF 1 "nonimmediate_operand" "0,0,0")
22773 (match_operand:V2DF 2 "nonimmediate_operand" "x,m,x")
22775 "TARGET_SSE2 && ix86_binary_operator_ok (UNKNOWN, V2DFmode, operands)"
22776 "@movsd\t{%2, %0|%0, %2}
22777 movlpd\t{%2, %0|%0, %2}
22778 movlpd\t{%2, %0|%0, %2}"
22779 [(set_attr "type" "ssecvt")
22780 (set_attr "mode" "DF,V2DF,V2DF")])
22782 (define_insn "sse2_storesd"
22783 [(set (match_operand:DF 0 "memory_operand" "=m")
22785 (match_operand:V2DF 1 "register_operand" "x")
22786 (parallel [(const_int 0)])))]
22788 "movsd\t{%1, %0|%0, %1}"
22789 [(set_attr "type" "ssecvt")
22790 (set_attr "mode" "DF")])
22792 (define_insn "sse2_shufpd"
22793 [(set (match_operand:V2DF 0 "register_operand" "=x")
22794 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
22795 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
22796 (match_operand:SI 3 "immediate_operand" "i")]
22799 ;; @@@ check operand order for intel/nonintel syntax
22800 "shufpd\t{%3, %2, %0|%0, %2, %3}"
22801 [(set_attr "type" "ssecvt")
22802 (set_attr "mode" "V2DF")])
22804 (define_insn "sse2_clflush"
22805 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
22809 [(set_attr "type" "sse")
22810 (set_attr "memory" "unknown")])
22812 (define_expand "sse2_mfence"
22813 [(set (match_dup 0)
22814 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
22817 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
22818 MEM_VOLATILE_P (operands[0]) = 1;
22821 (define_insn "*mfence_insn"
22822 [(set (match_operand:BLK 0 "" "")
22823 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
22826 [(set_attr "type" "sse")
22827 (set_attr "memory" "unknown")])
22829 (define_expand "sse2_lfence"
22830 [(set (match_dup 0)
22831 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
22834 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
22835 MEM_VOLATILE_P (operands[0]) = 1;
22838 (define_insn "*lfence_insn"
22839 [(set (match_operand:BLK 0 "" "")
22840 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
22843 [(set_attr "type" "sse")
22844 (set_attr "memory" "unknown")])
22848 (define_insn "mwait"
22849 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
22850 (match_operand:SI 1 "register_operand" "c")]
22854 [(set_attr "length" "3")])
22856 (define_insn "monitor"
22857 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
22858 (match_operand:SI 1 "register_operand" "c")
22859 (match_operand:SI 2 "register_operand" "d")]
22862 "monitor\t%0, %1, %2"
22863 [(set_attr "length" "3")])
22867 (define_insn "addsubv4sf3"
22868 [(set (match_operand:V4SF 0 "register_operand" "=x")
22869 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
22870 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
22873 "addsubps\t{%2, %0|%0, %2}"
22874 [(set_attr "type" "sseadd")
22875 (set_attr "mode" "V4SF")])
22877 (define_insn "addsubv2df3"
22878 [(set (match_operand:V2DF 0 "register_operand" "=x")
22879 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
22880 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
22883 "addsubpd\t{%2, %0|%0, %2}"
22884 [(set_attr "type" "sseadd")
22885 (set_attr "mode" "V2DF")])
22887 (define_insn "haddv4sf3"
22888 [(set (match_operand:V4SF 0 "register_operand" "=x")
22889 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
22890 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
22893 "haddps\t{%2, %0|%0, %2}"
22894 [(set_attr "type" "sseadd")
22895 (set_attr "mode" "V4SF")])
22897 (define_insn "haddv2df3"
22898 [(set (match_operand:V2DF 0 "register_operand" "=x")
22899 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
22900 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
22903 "haddpd\t{%2, %0|%0, %2}"
22904 [(set_attr "type" "sseadd")
22905 (set_attr "mode" "V2DF")])
22907 (define_insn "hsubv4sf3"
22908 [(set (match_operand:V4SF 0 "register_operand" "=x")
22909 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
22910 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
22913 "hsubps\t{%2, %0|%0, %2}"
22914 [(set_attr "type" "sseadd")
22915 (set_attr "mode" "V4SF")])
22917 (define_insn "hsubv2df3"
22918 [(set (match_operand:V2DF 0 "register_operand" "=x")
22919 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
22920 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
22923 "hsubpd\t{%2, %0|%0, %2}"
22924 [(set_attr "type" "sseadd")
22925 (set_attr "mode" "V2DF")])
22927 (define_insn "movshdup"
22928 [(set (match_operand:V4SF 0 "register_operand" "=x")
22930 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))]
22932 "movshdup\t{%1, %0|%0, %1}"
22933 [(set_attr "type" "sse")
22934 (set_attr "mode" "V4SF")])
22936 (define_insn "movsldup"
22937 [(set (match_operand:V4SF 0 "register_operand" "=x")
22939 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))]
22941 "movsldup\t{%1, %0|%0, %1}"
22942 [(set_attr "type" "sse")
22943 (set_attr "mode" "V4SF")])
22945 (define_insn "lddqu"
22946 [(set (match_operand:V16QI 0 "register_operand" "=x")
22947 (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
22950 "lddqu\t{%1, %0|%0, %1}"
22951 [(set_attr "type" "ssecvt")
22952 (set_attr "mode" "TI")])
22954 (define_insn "loadddup"
22955 [(set (match_operand:V2DF 0 "register_operand" "=x")
22956 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))]
22958 "movddup\t{%1, %0|%0, %1}"
22959 [(set_attr "type" "ssecvt")
22960 (set_attr "mode" "DF")])
22962 (define_insn "movddup"
22963 [(set (match_operand:V2DF 0 "register_operand" "=x")
22964 (vec_duplicate:V2DF
22965 (vec_select:DF (match_operand:V2DF 1 "register_operand" "x")
22966 (parallel [(const_int 0)]))))]
22968 "movddup\t{%1, %0|%0, %1}"
22969 [(set_attr "type" "ssecvt")
22970 (set_attr "mode" "DF")])