| blob | bf39eec28a96685093bf306f793faec8a5ea3e74 |
1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
53 #include <splay-tree.h>
56 /* Specify which cpu to schedule for. */
60 {
62 };
64 /* Specify how accurate floating-point traps need to be. */
68 /* Specify the floating-point rounding mode. */
72 /* Specify which things cause traps. */
76 /* Specify bit size of immediate TLS offsets. */
80 /* Strings decoded into the above options. */
90 /* Save information from a "cmpxx" operation until the branch or scc is
91 emitted. */
95 /* Nonzero if inside of a function, because the Alpha asm can't
96 handle .files inside of functions. */
100 /* The number of cycles of latency we should assume on memory reads. */
104 /* Whether the function needs the GP. */
108 /* The alias set for prologue/epilogue register save/restore. */
112 /* The assembler name of the current function. */
116 /* The next explicit relocation sequence number. */
120 /* The literal and gpdisp sequence numbers for this insn, as printed
121 by %# and %* respectively. */
127 /* Costs of various operations on the different architectures. */
129 struct alpha_rtx_cost_data
130 {
139 };
142 {
152 },
162 },
172 },
173 };
175 /* Get the number of args of a function in one of two ways. */
176 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
177 #define NUM_ARGS current_function_args_info.num_args
178 #else
179 #define NUM_ARGS current_function_args_info
180 #endif
182 #define REG_PV 27
183 #define REG_RA 26
185 /* Declarations of static functions. */
189 #if TARGET_ABI_OPEN_VMS
191 #endif
197 \f
198 /* Parse target option strings. */
200 void
202 {
209 #define EV5_MASK (MASK_CPU_EV5)
210 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
226 };
228 /* Unicos/Mk doesn't have shared libraries. */
230 {
234 }
236 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
237 floating-point instructions. Make that the default for this target. */
240 else
246 /* We cannot use su and sui qualifiers for conversion instructions on
247 Unicos/Mk. I'm not sure if this is due to assembler or hardware
248 limitations. Right now, we issue a warning if -mieee is specified
249 and then ignore it; eventually, we should either get it right or
250 disable the option altogether. */
253 {
256 else
257 {
260 }
261 }
264 {
267 else
268 {
271 }
272 }
275 {
282 else
284 }
287 {
296 else
298 alpha_fprm_string);
299 }
302 {
311 else
313 }
316 {
323 else
325 }
327 alpha_cpu
332 {
335 {
341 }
344 }
347 {
350 {
353 }
356 }
358 /* Do some sanity checks on the above options. */
361 {
364 }
368 {
371 }
374 {
375 /* Except for EV6 pass 1 (not released), we always have precise
376 arithmetic traps. Which means we can do software completion
377 without minding trap shadows. */
379 }
382 {
384 {
387 }
389 {
392 }
396 }
398 {
407 ;
411 {
413 {
417 };
421 {
425 }
426 else
428 }
430 {
431 /* Most current memories have about 370ns latency. This is
432 a reasonable guess for a fast cpu. */
434 }
435 else
436 {
439 }
442 }
444 /* Default the definition of "small data" to 8 bytes. */
448 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
454 /* Align labels and loops for optimal branching. */
455 /* ??? Kludge these by not doing anything if we don't optimize and also if
456 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
458 {
463 }
467 /* Acquire a unique set number for our register saves and restores. */
470 /* Register variables and functions with the garbage collector. */
472 /* Set up function hooks. */
475 /* Tell the compiler when we're using VAX floating point. */
477 {
481 }
482 }
483 \f
484 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
486 int
488 {
497 }
499 /* Returns 1 if OP is either the constant zero or a register. If a
500 register, it must be in the proper mode unless MODE is VOIDmode. */
502 int
504 {
506 }
508 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
509 any register. */
511 int
513 {
517 }
520 /* Return 1 if OP is an 8-bit constant or any register. */
522 int
524 {
528 }
530 /* Return 1 if OP is a constant or any register. */
532 int
534 {
536 }
538 /* Return 1 if OP is an 8-bit constant. */
540 int
542 {
545 }
547 /* Return 1 if the operand is a valid second operand to an add insn. */
549 int
551 {
553 /* Constraints I, J, O and P are covered by K. */
558 }
560 /* Return 1 if the operand is a valid second operand to a sign-extending
561 add insn. */
563 int
565 {
571 }
573 /* Return 1 if OP is the constant 4 or 8. */
575 int
577 {
580 }
582 /* Return 1 if OP is a valid first operand to an AND insn. */
584 int
586 {
597 }
599 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
601 int
603 {
609 }
611 /* Return 1 if OP is a constant that is the width, in bits, of an integral
612 mode smaller than DImode. */
614 int
616 {
620 }
622 /* Return 1 if OP is a constant that is the width of an integral machine mode
623 smaller than an integer. */
625 int
627 {
629 {
640 }
642 {
645 }
648 }
650 /* Return 1 if OP is a multiple of 8 less than 64. */
652 int
654 {
658 }
660 /* Return 1 if OP is the zero constant for MODE. */
662 int
664 {
666 }
668 /* Return 1 if OP is a hard floating-point register. */
670 int
672 {
679 }
681 /* Return 1 if OP is a hard general register. */
683 int
685 {
692 }
694 /* Return 1 if OP is a register or a constant integer. */
697 int
699 {
702 }
704 /* Return 1 if OP is something that can be reloaded into a register;
705 if it is a MEM, it need not be valid. */
707 int
709 {
714 {
731 }
734 }
736 /* Likewise, but don't accept constants. */
738 int
740 {
748 }
750 /* Return 1 if OP is a valid operand for the source of a move insn. */
752 int
754 {
762 {
767 {
768 /* We don't split symbolic operands into something unintelligable
769 until after reload, but we do not wish non-small, non-global
770 symbolic operands to be reconstructed from their high/lo_sum
771 form. */
776 }
778 /* This handles both the Windows/NT and OSF cases. */
792 /* ... fall through ... */
809 }
812 }
814 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
815 file, and in the same section as the current function. */
817 int
819 {
823 /* Easy test for recursion. */
827 /* Functions that are not local can be overridden, and thus may
828 not share the same gp. */
832 /* If -msmall-data is in effect, assume that there is only one GP
833 for the module, and so any local symbol has this property. We
834 need explicit relocations to be able to enforce this for symbols
835 not defined in this unit of translation, however. */
839 /* Functions that are not external are defined in this UoT,
840 and thus must share the same gp. */
842 }
844 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
846 int
848 {
851 /* Must share the same GP. */
855 /* If profiling is implemented via linker tricks, we can't jump
856 to the nogp alternate entry point. Note that current_function_profile
857 would not be correct, since that doesn't indicate if the target
858 function uses profiling. */
859 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
860 but is approximately correct for the OSF ABIs. Don't know
861 what to do for VMS, NT, or UMK. */
865 /* Must be a function. In some cases folks create thunks in static
866 data structures and then make calls to them. If we allow the
867 direct call, we'll get an error from the linker about !samegp reloc
868 against a symbol without a .prologue directive. */
872 /* Must be "near" so that the branch is assumed to reach. With
873 -msmall-text, this is assumed true of all local symbols. Since
874 we've already checked samegp, locality is already assured. */
878 /* Otherwise, a decl is "near" if it is defined in the same section. */
893 }
895 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
896 a (non-tls) variable known to be defined in this file. */
898 int
900 {
916 }
918 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
919 known to be defined in this file in the small data area. */
921 int
923 {
938 /* ??? There's no encode_section_info equivalent for the rtl
939 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
946 }
948 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
949 not known (or known not) to be defined in this file. */
951 int
953 {
966 }
968 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
970 int
972 {
977 {
979 {
980 /* Disallow virtual registers to cope with pathological test cases
981 such as compile/930117-1.c in which the virtual reg decomposes
982 to the frame pointer. Which is a hard reg that is not $27. */
984 }
985 else
987 }
994 }
996 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
997 possibly with an offset. */
999 int
1001 {
1012 }
1014 /* Return true if OP is valid for a particular TLS relocation. */
1016 static int
1018 {
1034 {
1037 }
1038 else
1039 {
1042 }
1045 {
1054 }
1055 }
1057 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1059 int
1061 {
1063 }
1065 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1067 int
1069 {
1071 }
1073 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1075 int
1077 {
1079 }
1081 /* Return true if OP is valid for 16-bit TP relative relocations. */
1083 int
1085 {
1087 }
1089 /* Return true if OP is valid for 32-bit TP relative relocations. */
1091 int
1093 {
1095 }
1097 /* Return true if OP is valid for 64-bit TP relative relocations. */
1099 int
1101 {
1103 }
1105 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1106 comparisons are valid in which insn. */
1108 int
1110 {
1118 }
1120 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1121 Here we know which comparisons are valid in which insn. */
1123 int
1125 {
1133 }
1135 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1137 int
1139 {
1149 }
1151 /* Return 1 if OP is a signed comparison operation. */
1153 int
1155 {
1164 }
1166 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1167 Here we know which comparisons are valid in which insn. */
1169 int
1171 {
1178 }
1180 /* Return 1 if this is a divide or modulus operator. */
1182 int
1184 {
1188 }
1190 /* Return 1 if this is a float->int conversion operator. */
1192 int
1194 {
1198 }
1200 /* Return 1 if this memory address is a known aligned register plus
1201 a constant. It must be a valid address. This means that we can do
1202 this as an aligned reference plus some offset.
1204 Take into account what reload will do. */
1206 int
1208 {
1209 rtx base;
1212 {
1218 {
1222 }
1223 }
1231 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1232 sorts of constructs. Dig for the real base register. */
1237 else
1238 {
1242 }
1245 }
1247 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1249 int
1251 {
1252 rtx base;
1255 {
1261 {
1265 }
1266 }
1274 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1275 sorts of constructs. Dig for the real base register. */
1280 else
1281 {
1285 }
1288 }
1290 /* Return 1 if OP is either a register or an unaligned memory location. */
1292 int
1294 {
1296 }
1298 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1300 int
1302 {
1310 }
1312 /* Returns 1 if OP is not an eliminable register.
1314 This exists to cure a pathological abort in the s8addq (et al) patterns,
1316 long foo () { long t; bar(); return (long) &t * 26107; }
1318 which run afoul of a hack in reload to cure a (presumably) similar
1319 problem with lea-type instructions on other targets. But there is
1320 one of us and many of them, so work around the problem by selectively
1321 preventing combine from making the optimization. */
1323 int
1325 {
1333 }
1335 /* Return 1 is OP is a memory location that is not a reference (using
1336 an AND) to an unaligned location. Take into account what reload
1337 will do. */
1339 int
1341 {
1343 {
1349 {
1352 /* This may not have been assigned an equivalent address if it will
1353 be eliminated. In that case, it doesn't matter what we do. */
1356 }
1357 }
1360 }
1362 /* Accept a register, but not a subreg of any kind. This allows us to
1363 avoid pathological cases in reload wrt data movement common in
1364 int->fp conversion. */
1366 int
1368 {
1372 }
1374 /* Recognize an addition operation that includes a constant. Used to
1375 convince reload to canonize (plus (plus reg c1) c2) during register
1376 elimination. */
1378 int
1380 {
1389 }
1391 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1392 the range defined for C in [I-P]. */
1394 bool
1396 {
1398 {
1400 /* An unsigned 8 bit constant. */
1403 /* The constant zero. */
1406 /* A signed 16 bit constant. */
1409 /* A shifted signed 16 bit constant appropriate for LDAH. */
1413 /* A constant that can be AND'ed with using a ZAP insn. */
1416 /* A complemented unsigned 8 bit constant. */
1419 /* A negated unsigned 8 bit constant. */
1422 /* The constant 1, 2 or 3. */
1427 }
1428 }
1430 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1431 matches for C in [GH]. */
1433 bool
1435 {
1437 {
1439 /* The floating point zero constant. */
1444 /* A valid operand of a ZAP insn. */
1451 }
1452 }
1454 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1455 matches for C. */
1457 bool
1459 {
1461 {
1478 }
1479 }
1481 /* Return 1 if this function can directly return via $26. */
1483 int
1485 {
1487 && reload_completed
1492 }
1494 /* Return the ADDR_VEC associated with a tablejump insn. */
1496 rtx
1498 {
1499 rtx tmp;
1511 }
1513 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1515 rtx
1517 {
1521 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1522 there for edge frequency counts from profile data. */
1525 {
1531 {
1537 count++;
1541 }
1542 }
1545 }
1547 /* Return the TLS model to use for SYMBOL. */
1549 static enum tls_model
1551 {
1558 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1563 }
1564 \f
1565 /* Return true if the function DECL will share the same GP as any
1566 function in the current unit of translation. */
1568 static bool
1570 {
1571 /* Functions that are not local can be overridden, and thus may
1572 not share the same gp. */
1576 /* If -msmall-data is in effect, assume that there is only one GP
1577 for the module, and so any local symbol has this property. We
1578 need explicit relocations to be able to enforce this for symbols
1579 not defined in this unit of translation, however. */
1583 /* Functions that are not external are defined in this UoT. */
1584 /* ??? Irritatingly, static functions not yet emitted are still
1585 marked "external". Apply this to non-static functions only. */
1587 }
1589 /* Return true if EXP should be placed in the small data section. */
1591 static bool
1593 {
1594 /* We want to merge strings, so we never consider them small data. */
1598 /* Functions are never in the small data area. Duh. */
1603 {
1608 }
1609 else
1610 {
1613 /* If this is an incomplete type with size 0, then we can't put it
1614 in sdata because it might be too big when completed. */
1617 }
1620 }
1622 #if TARGET_ABI_OPEN_VMS
1623 static bool
1625 {
1632 }
1634 #define LINKAGE_SYMBOL_REF_P(X) \
1635 ((GET_CODE (X) == SYMBOL_REF \
1636 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1637 || (GET_CODE (X) == CONST \
1638 && GET_CODE (XEXP (X, 0)) == PLUS \
1639 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1640 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1641 #endif
1643 /* legitimate_address_p recognizes an RTL expression that is a valid
1644 memory address for an instruction. The MODE argument is the
1645 machine mode for the MEM expression that wants to use this address.
1647 For Alpha, we have either a constant address or the sum of a
1648 register and a constant address, or just a register. For DImode,
1649 any of those forms can be surrounded with an AND that clear the
1650 low-order three bits; this is an "unaligned" access. */
1652 bool
1654 {
1655 /* If this is an ldq_u type address, discard the outer AND. */
1662 /* Discard non-paradoxical subregs. */
1668 /* Unadorned general registers are valid. */
1670 && (strict
1675 /* Constant addresses (i.e. +/- 32k) are valid. */
1679 #if TARGET_ABI_OPEN_VMS
1682 #endif
1684 /* Register plus a small constant offset is valid. */
1686 {
1690 /* Discard non-paradoxical subregs. */
1697 {
1707 }
1711 }
1713 /* If we're managing explicit relocations, LO_SUM is valid, as
1714 are small data symbols. */
1716 {
1721 {
1725 /* Discard non-paradoxical subregs. */
1731 /* Must have a valid base register. */
1733 && (strict
1738 /* The symbol must be local. */
1743 }
1744 }
1747 }
1749 /* Build the SYMBOL_REF for __tls_get_addr. */
1753 static rtx
1755 {
1759 }
1761 /* Try machine-dependent ways of modifying an illegitimate address
1762 to be legitimate. If we find one, return the new, valid address. */
1764 rtx
1767 {
1768 HOST_WIDE_INT addend;
1770 /* If the address is (plus reg const_int) and the CONST_INT is not a
1771 valid offset, compute the high part of the constant and add it to
1772 the register. Then our address is (plus temp low-part-const). */
1777 {
1781 }
1783 /* If the address is (const (plus FOO const_int)), find the low-order
1784 part of the CONST_INT. Then load FOO plus any high-order part of the
1785 CONST_INT into a register. Our address is (plus reg low-part-const).
1786 This is done to reduce the number of GOT entries. */
1791 {
1795 }
1797 /* If we have a (plus reg const), emit the load as in (2), then add
1798 the two registers, and finally generate (plus reg low-part-const) as
1799 our address. */
1806 {
1812 }
1814 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1816 {
1820 {
1861 UNSPEC_TLSLDM_CALL);
1868 {
1873 }
1875 {
1880 }
1902 {
1907 }
1909 }
1912 {
1915 else
1916 {
1922 }
1923 }
1924 }
1928 split_addend:
1929 {
1947 }
1948 }
1950 /* We do not allow indirect calls to be optimized into sibling calls, nor
1951 can we allow a call to a function with a different GP to be optimized
1952 into a sibcall. */
1954 static bool
1956 {
1957 /* Can't do indirect tail calls, since we don't know if the target
1958 uses the same GP. */
1962 /* Otherwise, we can make a tail call if the target function shares
1963 the same GP. */
1965 }
1967 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1968 small symbolic operand until after reload. At which point we need
1969 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1970 so that sched2 has the proper dependency information. */
1972 static int
1974 {
1977 /* Don't re-split. */
1982 }
1984 int
1986 {
1988 }
1990 static int
1992 {
1995 /* Don't re-split. */
2000 {
2004 }
2007 }
2009 rtx
2011 {
2015 }
2017 /* Indicate that INSN cannot be duplicated. This is true for any insn
2018 that we've marked with gpdisp relocs, since those have to stay in
2019 1-1 correspondence with one another.
2021 Technically we could copy them if we could set up a mapping from one
2022 sequence number to another, across the set of insns to be duplicated.
2023 This seems overly complicated and error-prone since interblock motion
2024 from sched-ebb could move one of the pair of insns to a different block.
2026 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
2027 then they'll be in a different block from their ldgp. Which could lead
2028 the bb reorder code to think that it would be ok to copy just the block
2029 containing the call and branch to the block containing the ldgp. */
2031 static bool
2033 {
2038 else
2040 }
2043 /* Try a machine-dependent way of reloading an illegitimate address
2044 operand. If we find one, push the reload and return the new rtx. */
2046 rtx
2051 {
2052 /* We must recognize output that we have already generated ourselves. */
2058 {
2063 }
2065 /* We wish to handle large displacements off a base register by
2066 splitting the addend across an ldah and the mem insn. This
2067 cuts number of extra insns needed from 3 to 1. */
2073 {
2076 HOST_WIDE_INT high
2079 /* Check for 32-bit overflow. */
2083 /* Reload the high part into a base reg; leave the low part
2084 in the mem directly. */
2094 }
2097 }
2098 \f
2099 /* Compute a (partial) cost for rtx X. Return true if the complete
2100 cost has been computed, and false if subexpressions should be
2101 scanned. In either case, *TOTAL contains the cost result. */
2103 static bool
2105 {
2110 {
2111 /* If this is an 8-bit constant, return zero since it can be used
2112 nearly anywhere with no cost. If it is a valid operand for an
2113 ADD or AND, likewise return 0 if we know it will be used in that
2114 context. Otherwise, return 2 since it might be used there later.
2115 All other constants take at least two insns. */
2118 {
2121 }
2122 /* FALLTHRU */
2132 else
2144 /* Estimate of cost for call_pal rduniq. */
2146 else
2147 /* Otherwise we do a load from the GOT. */
2157 {
2161 }
2169 else
2176 {
2179 }
2180 /* FALLTHRU */
2190 else
2202 else
2212 {
2215 }
2216 /* FALLTHRU */
2220 {
2223 }
2224 /* FALLTHRU */
2237 }
2238 }
2239 \f
2240 /* REF is an alignable memory location. Place an aligned SImode
2241 reference into *PALIGNED_MEM and the number of bits to shift into
2242 *PBITNUM. SCRATCH is a free register for use in reloading out
2243 of range stack slots. */
2245 void
2247 {
2248 rtx base;
2256 {
2261 }
2262 else
2263 {
2265 }
2270 *paligned_mem
2276 else
2278 }
2280 /* Similar, but just get the address. Handle the two reload cases.
2281 Add EXTRA_OFFSET to the address we return. */
2283 rtx
2285 {
2286 rtx base;
2294 {
2299 }
2300 else
2301 {
2303 }
2309 }
2311 /* On the Alpha, all (non-symbolic) constants except zero go into
2312 a floating-point register via memory. Note that we cannot
2313 return anything that is not a subset of CLASS, and that some
2314 symbolic constants cannot be dropped to memory. */
2316 enum reg_class
2318 {
2319 /* Zero is present in any register class. */
2323 /* These sorts of constants we can easily drop to memory. */
2325 {
2331 }
2333 /* All other kinds of constants should not (and in the case of HIGH
2334 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2335 secondary reload. */
2340 }
2342 /* Loading and storing HImode or QImode values to and from memory
2343 usually requires a scratch register. The exceptions are loading
2344 QImode and HImode from an aligned address to a general register
2345 unless byte instructions are permitted.
2347 We also cannot load an unaligned address or a paradoxical SUBREG
2348 into an FP register.
2350 We also cannot do integral arithmetic into FP regs, as might result
2351 from register elimination into a DImode fp register. */
2353 enum reg_class
2356 {
2358 {
2365 {
2368 }
2369 }
2372 {
2384 }
2387 }
2388 \f
2389 /* Subfunction of the following function. Update the flags of any MEM
2390 found in part of X. */
2392 static void
2394 {
2398 {
2405 unchanging_p);
2410 unchanging_p);
2415 unchanging_p);
2417 unchanging_p);
2424 /* Sadly, we cannot use alias sets because the extra aliasing
2425 produced by the AND interferes. Given that two-byte quantities
2426 are the only thing we would be able to differentiate anyway,
2427 there does not seem to be any point in convoluting the early
2428 out of the alias check. */
2433 }
2434 }
2436 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2437 generated to perform a memory operation, look for any MEMs in either
2438 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2439 volatile flags from REF into each of the MEMs found. If REF is not
2440 a MEM, don't do anything. */
2442 void
2444 {
2454 /* This is only called from alpha.md, after having had something
2455 generated from one of the insn patterns. So if everything is
2456 zero, the pattern is already up-to-date. */
2461 }
2462 \f
2463 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2465 static rtx
2468 {
2471 /* Use a pseudo if highly optimizing and still generating RTL. */
2472 rtx subtarget
2476 /* If this is a sign-extended 32-bit constant, we can do this in at most
2477 three insns, so do it if we have enough insns left. We always have
2478 a sign-extended 32-bit constant when compiling on a narrow machine. */
2482 {
2488 /* If HIGH will be interpreted as negative but the constant is
2489 positive, we must adjust it to do two ldha insns. */
2492 {
2496 }
2499 {
2500 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2501 but that meant that we can't handle INT_MIN on 32-bit machines
2502 (like NT/Alpha), because we recurse indefinitely through
2503 emit_move_insn to gen_movdi. So instead, since we know exactly
2504 what we want, create it explicitly. */
2510 }
2512 {
2514 {
2517 }
2518 else
2522 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2523 This means that if we go through expand_binop, we'll try to
2524 generate extensions, etc, which will require new pseudos, which
2525 will fail during some split phases. The SImode add patterns
2526 still exist, but are not named. So build the insns by hand. */
2529 {
2536 }
2544 }
2545 }
2547 /* If we couldn't do it that way, try some other methods. But if we have
2548 no instructions left, don't bother. Likewise, if this is SImode and
2549 we can't make pseudos, we can't do anything since the expand_binop
2550 and expand_unop calls will widen and try to make pseudos. */
2555 /* Next, see if we can load a related constant and then shift and possibly
2556 negate it to get the constant we want. Try this once each increasing
2557 numbers of insns. */
2560 {
2561 /* First, see if minus some low bits, we've an easy load of
2562 high bits. */
2570 /* Next try complementing. */
2574 /* Next try to form a constant and do a left shift. We can do this
2575 if some low-order bits are zero; the exact_log2 call below tells
2576 us that information. The bits we are shifting out could be any
2577 value, but here we'll just try the 0- and sign-extended forms of
2578 the constant. To try to increase the chance of having the same
2579 constant in more than one insn, start at the highest number of
2580 bits to shift, but try all possibilities in case a ZAPNOT will
2581 be useful. */
2594 /* Now try high-order zero bits. Here we try the shifted-in bits as
2595 all zero and all ones. Be careful to avoid shifting outside the
2596 mode and to avoid shifting outside the host wide int size. */
2597 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2598 confuse the recursive call and set all of the high 32 bits. */
2608 i)))
2613 /* Now try high-order 1 bits. We get that with a sign-extension.
2614 But one bit isn't enough here. Be careful to avoid shifting outside
2615 the mode and to avoid shifting outside the host wide int size. */
2625 i)))
2629 }
2631 #if HOST_BITS_PER_WIDE_INT == 64
2632 /* Finally, see if can load a value into the target that is the same as the
2633 constant except that all bytes that are 0 are changed to be 0xff. If we
2634 can, then we can do a ZAPNOT to obtain the desired constant. */
2641 /* We are only called for SImode and DImode. If this is SImode, ensure that
2642 we are sign extended to a full word. */
2651 #endif
2654 }
2656 /* Try to output insns to set TARGET equal to the constant C if it can be
2657 done in less than N insns. Do all computations in MODE. Returns the place
2658 where the output has been placed if it can be done and the insns have been
2659 emitted. If it would take more than N insns, zero is returned and no
2660 insns and emitted. */
2662 rtx
2665 {
2670 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2671 can't load this constant in one insn, do this in DImode. */
2675 {
2678 }
2680 /* Try 1 insn, then 2, then up to N. */
2682 {
2685 {
2691 }
2692 }
2694 /* Allow for the case where we changed the mode of TARGET. */
2699 }
2701 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2702 fall back to a straight forward decomposition. We do this to avoid
2703 exponential run times encountered when looking for longer sequences
2704 with alpha_emit_set_const. */
2706 rtx
2708 {
2711 /* Decompose the entire word */
2712 #if HOST_BITS_PER_WIDE_INT >= 64
2724 #else
2736 #endif
2738 /* Construct the high word */
2740 {
2744 }
2745 else
2748 /* Shift it into place */
2751 /* Add in the low bits. */
2758 }
2760 /* Expand a move instruction; return true if all work is done.
2761 We don't handle non-bwx subword loads here. */
2763 bool
2765 {
2766 /* If the output is not a register, the input must be. */
2771 /* Allow legitimize_address to perform some simplifications. */
2773 {
2774 rtx tmp;
2776 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2777 compiled at the end of compilation. In the meantime, someone can
2778 re-encode-section-info on some symbol changing it e.g. from global
2779 to local-not-small. If this happens, we'd have emitted a plain
2780 load rather than a high+losum load and not recognize the insn.
2782 So if rtl inlining is in effect, we delay the global/not-global
2783 decision until rest_of_compilation by wrapping it in an
2784 UNSPEC_SYMBOL. */
2786 && rtx_equal_function_value_matters
2788 {
2791 }
2795 {
2800 }
2801 }
2803 /* Early out for non-constants and valid constants. */
2807 /* Split large integers. */
2810 {
2815 {
2818 }
2820 {
2823 }
2824 else
2825 {
2828 }
2837 {
2842 }
2843 }
2845 /* Otherwise we've nothing left but to drop the thing to memory. */
2848 {
2852 }
2853 else
2856 }
2858 /* Expand a non-bwx QImode or HImode move instruction;
2859 return true if all work is done. */
2861 bool
2863 {
2864 /* If the output is not a register, the input must be. */
2868 /* Handle four memory cases, unaligned and aligned for either the input
2869 or the output. The only case where we can be called during reload is
2870 for aligned loads; all other cases require temporaries. */
2880 {
2882 {
2884 {
2886 ? gen_reload_inqi_help
2890 }
2891 else
2892 {
2895 rtx subtarget;
2903 else
2907 ? gen_aligned_loadqi
2913 }
2914 }
2915 else
2916 {
2917 /* Don't pass these as parameters since that makes the generated
2918 code depend on parameter evaluation order which will cause
2919 bootstrap failures. */
2930 else
2934 ? gen_unaligned_loadqi
2943 }
2945 }
2955 {
2957 {
2966 }
2967 else
2968 {
2973 ? gen_unaligned_storeqi
2980 }
2982 }
2985 }
2987 /* Generate an unsigned DImode to FP conversion. This is the same code
2988 optabs would emit if we didn't have TFmode patterns.
2990 For SFmode, this is the only construction I've found that can pass
2991 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2992 intermediates will work, because you'll get intermediate rounding
2993 that ruins the end result. Some of this could be fixed by turning
2994 on round-to-positive-infinity, but that requires diddling the fpsr,
2995 which kills performance. I tried turning this around and converting
2996 to a negative number, so that I could turn on /m, but either I did
2997 it wrong or there's something else cause I wound up with the exact
2998 same single-bit error. There is a branch-less form of this same code:
3000 srl $16,1,$1
3001 and $16,1,$2
3002 cmplt $16,0,$3
3003 or $1,$2,$2
3004 cmovge $16,$16,$2
3005 itoft $3,$f10
3006 itoft $2,$f11
3007 cvtqs $f11,$f11
3008 adds $f11,$f11,$f0
3009 fcmoveq $f10,$f11,$f0
3011 I'm not using it because it's the same number of instructions as
3012 this branch-full form, and it has more serialized long latency
3013 instructions on the critical path.
3015 For DFmode, we can avoid rounding errors by breaking up the word
3016 into two pieces, converting them separately, and adding them back:
3018 LC0: .long 0,0x5f800000
3020 itoft $16,$f11
3021 lda $2,LC0
3022 cmplt $16,0,$1
3023 cpyse $f11,$f31,$f10
3024 cpyse $f31,$f11,$f11
3025 s4addq $1,$2,$1
3026 lds $f12,0($1)
3027 cvtqt $f10,$f10
3028 cvtqt $f11,$f11
3029 addt $f12,$f10,$f0
3030 addt $f0,$f11,$f0
3032 This doesn't seem to be a clear-cut win over the optabs form.
3033 It probably all depends on the distribution of numbers being
3034 converted -- in the optabs form, all but high-bit-set has a
3035 much lower minimum execution time. */
3037 void
3039 {
3067 }
3069 /* Generate the comparison for a conditional branch. */
3071 rtx
3073 {
3077 rtx tem;
3080 {
3084 /* X_floating library comparison functions return
3085 -1 unordered
3086 0 false
3087 1 true
3088 Convert the compare against the raw return value. */
3091 {
3108 }
3113 }
3115 /* The general case: fold the comparison code to the types of compares
3116 that we have, choosing the branch as necessary. */
3118 {
3121 /* We have these compares: */
3127 /* These must be reversed. */
3132 /* For FP, we swap them, for INT, we reverse them. */
3134 {
3138 }
3139 else
3140 {
3143 }
3148 }
3151 {
3154 {
3155 /* When we are not as concerned about non-finite values, and we
3156 are comparing against zero, we can branch directly. */
3160 {
3161 /* Undo the swap we probably did just above. */
3165 }
3166 }
3167 else
3168 {
3169 /* ??? We mark the branch mode to be CCmode to prevent the
3170 compare and branch from being combined, since the compare
3171 insn follows IEEE rules that the branch does not. */
3173 }
3174 }
3175 else
3176 {
3179 /* The following optimizations are only for signed compares. */
3181 {
3182 /* Whee. Compare and branch against 0 directly. */
3186 /* If the constants doesn't fit into an immediate, but can
3187 be generated by lda/ldah, we adjust the argument and
3188 compare against zero, so we can use beq/bne directly. */
3190 {
3196 {
3199 }
3200 }
3201 }
3207 }
3209 /* Emit an initial compare instruction, if necessary. */
3212 {
3215 }
3217 /* Zero the operands. */
3220 /* Return the branch comparison. */
3222 }
3224 /* Certain simplifications can be done to make invalid setcc operations
3225 valid. Return the final comparison, or NULL if we can't work. */
3227 rtx
3229 {
3233 rtx tmp;
3235 /* Zero the operands. */
3239 {
3243 /* X_floating library comparison functions return
3244 -1 unordered
3245 0 false
3246 1 true
3247 Convert the compare against the raw return value. */
3251 else
3262 else
3264 }
3269 /* The general case: fold the comparison code to the types of compares
3270 that we have, choosing the branch as necessary. */
3274 {
3277 /* We have these compares. */
3285 /* FALLTHRU */
3293 /* These normally need swapping, but for integer zero we have
3294 special patterns that recognize swapped operands. */
3305 }
3308 {
3313 }
3315 /* Emit an initial compare instruction, if necessary. */
3317 {
3326 }
3328 /* Return the setcc comparison. */
3330 }
3333 /* Rewrite a comparison against zero CMP of the form
3334 (CODE (cc0) (const_int 0)) so it can be written validly in
3335 a conditional move (if_then_else CMP ...).
3336 If both of the operands that set cc0 are nonzero we must emit
3337 an insn to perform the compare (it can't be done within
3338 the conditional move). */
3340 rtx
3342 {
3348 enum machine_mode cmp_mode
3353 rtx tem;
3355 /* Zero the operands. */
3359 {
3365 /* If we have fp<->int register move instructions, do a cmov by
3366 performing the comparison in fp registers, and move the
3367 zero/nonzero value to integer registers, where we can then
3368 use a normal cmov, or vice-versa. */
3371 {
3373 /* We have these compares. */
3378 /* This must be reversed. */
3383 /* These normally need swapping, but for integer zero we have
3384 special patterns that recognize swapped operands. */
3387 else
3388 {
3392 }
3397 }
3409 }
3411 /* We may be able to use a conditional move directly.
3412 This avoids emitting spurious compares. */
3418 /* We can't put the comparison inside the conditional move;
3419 emit a compare instruction and put that inside the
3420 conditional move. Make sure we emit only comparisons we have;
3421 swap or reverse as necessary. */
3427 {
3429 /* We have these compares: */
3433 /* This must be reversed. */
3439 /* These must be swapped. */
3441 {
3444 }
3449 }
3452 {
3457 }
3459 /* ??? We mark the branch mode to be CCmode to prevent the compare
3460 and cmov from being combined, since the compare insn follows IEEE
3461 rules that the cmov does not. */
3468 }
3470 /* Simplify a conditional move of two constants into a setcc with
3471 arithmetic. This is done with a splitter since combine would
3472 just undo the work if done during code generation. It also catches
3473 cases we wouldn't have before cse. */
3475 int
3478 {
3490 {
3494 }
3498 {
3502 else
3504 }
3505 /* Below, we must be careful to use copy_rtx on target and subtarget
3506 in intermediate insns, as they may be a subreg rtx, which may not
3507 be shared. */
3510 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3511 viable over a longer latency cmove. On EV5, the E0 slot is a
3512 scarce resource, and on EV4 shift has the same latency as a cmove. */
3514 {
3521 }
3523 {
3528 }
3530 {
3531 rtx add_op;
3538 else
3539 {
3542 {
3547 }
3548 else
3550 }
3551 }
3552 else
3556 }
3557 \f
3558 /* Look up the function X_floating library function name for the
3559 given operation. */
3563 {
3564 struct xfloating_op
3565 {
3568 };
3571 {
3587 };
3590 {
3606 };
3612 /* How irritating. Nothing to key off for the table. Hardcode
3613 knowledge of the G_floating routines. */
3615 {
3617 {
3622 }
3623 else
3624 {
3629 }
3630 }
3634 else
3642 }
3644 /* Most X_floating operations take the rounding mode as an argument.
3645 Compute that here. */
3647 static int
3650 {
3654 {
3670 /* XXX For reference, round to +inf is mode = 3. */
3671 }
3677 }
3679 /* Emit an X_floating library function call.
3681 Note that these functions do not follow normal calling conventions:
3682 TFmode arguments are passed in two integer registers (as opposed to
3683 indirect); TFmode return values appear in R16+R17.
3685 FUNC is the function name to call.
3686 TARGET is where the output belongs.
3687 OPERANDS are the inputs.
3688 NOPERANDS is the count of inputs.
3689 EQUIV is the expression equivalent for the function.
3690 */
3692 static void
3695 {
3702 {
3704 {
3718 /* FALLTHRU */
3726 }
3730 }
3733 {
3745 }
3756 }
3758 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3760 void
3762 {
3776 }
3778 /* Emit an X_floating library function call for a comparison. */
3780 static rtx
3782 {
3792 /* ??? Strange mode for equiv because what's actually returned
3793 is -1,0,1, not a proper boolean value. */
3798 }
3800 /* Emit an X_floating library function call for a conversion. */
3802 void
3804 {
3818 {
3831 }
3837 }
3839 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3840 OP[0] into OP[0,1]. Naturally, output operand ordering is
3841 little-endian. */
3843 void
3845 {
3847 {
3850 }
3852 {
3855 }
3858 else
3862 {
3865 }
3867 {
3870 }
3871 else
3873 }
3875 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3876 op2 is a register containing the sign bit, operation is the
3877 logical operation to be performed. */
3879 void
3881 {
3883 rtx scratch;
3888 /* Detect three flavors of operand overlap. */
3893 {
3896 else
3898 }
3903 /* ??? If the destination overlaps both source tf and high_bit, then
3904 assume source tf is dead in its entirety and use the other half
3905 for a scratch register. Otherwise "scratch" is just the proper
3906 destination register. */
3912 {
3916 }
3917 }
3918 \f
3919 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3920 unaligned data:
3922 unsigned: signed:
3923 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3924 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3925 lda r3,X(r11) lda r3,X+2(r11)
3926 extwl r1,r3,r1 extql r1,r3,r1
3927 extwh r2,r3,r2 extqh r2,r3,r2
3928 or r1.r2.r1 or r1,r2,r1
3929 sra r1,48,r1
3931 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3932 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3933 lda r3,X(r11) lda r3,X(r11)
3934 extll r1,r3,r1 extll r1,r3,r1
3935 extlh r2,r3,r2 extlh r2,r3,r2
3936 or r1.r2.r1 addl r1,r2,r1
3938 quad: ldq_u r1,X(r11)
3939 ldq_u r2,X+7(r11)
3940 lda r3,X(r11)
3941 extql r1,r3,r1
3942 extqh r2,r3,r2
3943 or r1.r2.r1
3944 */
3946 void
3949 {
3963 /* AND addresses cannot be in any alias set, since they may implicitly
3964 alias surrounding code. Ideally we'd have some alias set that
3965 covered all types except those with alignment 8 or higher. */
3982 {
3991 }
3993 {
3999 /* We must use tgt here for the target. Alpha-vms port fails if we use
4000 addr for the target, because addr is marked as a pointer and combine
4001 knows that pointers are always sign-extended 32 bit values. */
4005 }
4006 else
4007 {
4009 {
4012 {
4030 }
4032 }
4033 else
4034 {
4038 {
4056 }
4057 }
4062 }
4066 }
4068 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4070 void
4073 {
4085 /* AND addresses cannot be in any alias set, since they may implicitly
4086 alias surrounding code. Ideally we'd have some alias set that
4087 covered all types except those with alignment 8 or higher. */
4104 {
4108 {
4110 {
4120 }
4123 }
4126 {
4131 {
4135 }
4139 }
4142 }
4143 else
4144 {
4148 {
4153 {
4163 }
4164 }
4169 {
4174 {
4178 }
4182 }
4183 }
4186 {
4189 }
4192 {
4195 }
4196 else
4197 {
4198 /* Must store high before low for degenerate case of aligned. */
4201 }
4202 }
4204 /* The block move code tries to maximize speed by separating loads and
4205 stores at the expense of register pressure: we load all of the data
4206 before we store it back out. There are two secondary effects worth
4207 mentioning, that this speeds copying to/from aligned and unaligned
4208 buffers, and that it makes the code significantly easier to write. */
4210 #define MAX_MOVE_WORDS 8
4212 /* Load an integral number of consecutive unaligned quadwords. */
4214 static void
4217 {
4222 HOST_WIDE_INT i;
4228 /* Generate all the tmp registers we need. */
4230 {
4233 }
4239 /* Load up all of the source data. */
4241 {
4245 im8));
4248 }
4253 im8));
4257 /* Extract the half-word fragments. Unfortunately DEC decided to make
4258 extxh with offset zero a noop instead of zeroing the register, so
4259 we must take care of that edge condition ourselves with cmov. */
4267 {
4269 {
4272 }
4273 else
4274 {
4277 }
4281 const0_rtx),
4283 }
4285 /* Merge the half-words into whole words. */
4287 {
4290 }
4291 }
4293 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4294 may be NULL to store zeros. */
4296 static void
4299 {
4305 HOST_WIDE_INT i;
4311 /* Generate all the tmp registers we need. */
4324 im8));
4331 /* Load up the destination end bits. */
4335 /* Shift the input data into place. */
4340 {
4342 {
4344 {
4347 }
4348 else
4349 {
4352 }
4353 }
4355 {
4358 OPTAB_WIDEN);
4359 }
4360 }
4362 /* Split and merge the ends with the destination data. */
4364 {
4367 }
4368 else
4369 {
4372 }
4375 {
4380 }
4382 /* Store it all. */
4385 else
4388 {
4393 im8));
4396 }
4399 else
4401 }
4404 /* Expand string/block move operations.
4406 operands[0] is the pointer to the destination.
4407 operands[1] is the pointer to the source.
4408 operands[2] is the number of bytes to move.
4409 operands[3] is the alignment. */
4411 int
4413 {
4423 rtx tmp;
4431 /* Look for additional alignment information from recorded register info. */
4439 {
4444 {
4451 }
4452 }
4460 {
4465 {
4472 }
4473 }
4475 /* Load the entire block into registers. */
4477 {
4482 /* Don't use the existing register if we're reading more than
4483 is held in the register. Nor if there is not a mode that
4484 handles the exact size. */
4489 {
4491 {
4495 }
4496 else
4500 }
4502 /* No appropriate mode; fall back on memory. */
4506 }
4510 {
4523 }
4526 {
4539 }
4542 {
4554 }
4557 {
4562 }
4565 {
4567 {
4574 }
4576 {
4581 }
4582 }
4585 {
4590 }
4592 src_done:
4597 /* Now save it back out again. */
4602 {
4608 {
4610 {
4614 }
4617 {
4618 /* Undo the subregging done above when copying between
4619 two TImode registers. */
4623 else
4624 {
4625 rtx seq;
4635 }
4639 }
4640 }
4642 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4643 /* ??? Optimize mode < dst_mode with strict_low_part. */
4645 /* No appropriate mode; fall back on memory. We can speed things
4646 up by recognizing extra alignment information. */
4650 }
4652 /* Write out the data in whatever chunks reading the source allowed. */
4654 {
4656 {
4660 i++;
4661 }
4662 }
4665 {
4666 /* If the source has remaining DImode regs, write them out in
4667 two pieces. */
4669 {
4678 i++;
4679 }
4682 {
4686 i++;
4687 }
4688 }
4691 {
4692 /* Write out a remaining block of words using unaligned methods. */
4700 else
4706 }
4708 /* Due to the above, this won't be aligned. */
4709 /* ??? If we have more than one of these, consider constructing full
4710 words in registers and using alpha_expand_unaligned_store_words. */
4712 {
4715 i++;
4716 }
4720 {
4722 i++;
4724 }
4725 else
4727 {
4729 i++;
4731 }
4734 {
4736 i++;
4738 }
4740 dst_done:
4746 }
4748 int
4750 {
4758 rtx tmp;
4766 /* Look for stricter alignment. */
4773 {
4778 {
4785 }
4786 }
4788 {
4793 {
4796 }
4798 /* No appropriate mode; fall back on memory. */
4801 }
4803 /* Handle an unaligned prefix first. */
4806 {
4807 #if HOST_BITS_PER_WIDE_INT >= 64
4808 /* Given that alignofs is bounded by align, the only time BWX could
4809 generate three stores is for a 7 byte fill. Prefer two individual
4810 stores over a load/mask/store sequence. */
4814 {
4818 HOST_WIDE_INT mask;
4825 {
4829 }
4830 else
4831 {
4834 }
4841 }
4842 #endif
4845 {
4850 }
4852 {
4857 }
4859 {
4864 }
4866 /* If we've not used the extra lead alignment information by now,
4867 we won't be able to. Downgrade align to match what's left over. */
4869 {
4872 }
4873 }
4875 /* Handle a block of contiguous long-words. */
4878 {
4883 const0_rtx);
4887 }
4889 /* If the block is large and appropriately aligned, emit a single
4890 store followed by a sequence of stq_u insns. */
4893 {
4894 rtx orig_dsta;
4906 {
4907 rtx mem
4914 }
4916 /* Depending on the alignment, the first stq_u may have overlapped
4917 with the initial stl, which means that the last stq_u didn't
4918 write as much as it would appear. Leave those questionable bytes
4919 unaccounted for. */
4922 }
4924 /* Handle a smaller block of aligned words. */
4928 {
4933 const0_rtx);
4937 }
4939 /* An unaligned block uses stq_u stores for as many as possible. */
4942 {
4949 }
4951 /* Next clean up any trailing pieces. */
4953 #if HOST_BITS_PER_WIDE_INT >= 64
4954 /* Count the number of bits in BYTES for which aligned stores could
4955 be emitted. */
4961 /* If we have appropriate alignment (and it wouldn't take too many
4962 instructions otherwise), mask out the bytes we need. */
4964 {
4966 {
4968 HOST_WIDE_INT mask;
4980 }
4982 {
4984 HOST_WIDE_INT mask;
4996 }
4997 }
4998 #endif
5001 {
5005 }
5008 {
5010 {
5013 const0_rtx);
5017 }
5019 {
5023 }
5024 }
5027 {
5031 }
5034 }
5036 /* Returns a mask so that zap(x, value) == x & mask. */
5038 rtx
5040 {
5041 rtx result;
5045 {
5049 {
5053 }
5056 }
5058 {
5062 {
5066 }
5069 {
5073 }
5076 }
5077 else
5081 }
5083 void
5087 {
5092 else
5097 else
5101 }
5102 \f
5103 /* Adjust the cost of a scheduling dependency. Return the new cost of
5104 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5106 static int
5108 {
5111 /* If the dependence is an anti-dependence, there is no cost. For an
5112 output dependence, there is sometimes a cost, but it doesn't seem
5113 worth handling those few cases. */
5117 /* If we can't recognize the insns, we can't really do anything. */
5124 /* Bring in the user-defined memory latency. */
5130 /* Everything else handled in DFA bypasses now. */
5133 }
5135 /* The number of instructions that can be issued per cycle. */
5137 static int
5139 {
5141 }
5143 static int
5145 {
5147 }
5149 /* How many alternative schedules to try. This should be as wide as the
5150 scheduling freedom in the DFA, but no wider. Making this value too
5151 large results extra work for the scheduler.
5153 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5154 alternative schedules. For EV5, we can choose between E0/E1 and
5155 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5157 static int
5159 {
5161 }
5162 \f
5163 /* Machine-specific function data. */
5166 {
5167 /* For unicosmk. */
5168 /* List of call information words for calls from this function. */
5173 /* List of deferred case vectors. */
5176 /* For OSF. */
5178 };
5180 /* How to allocate a 'struct machine_function'. */
5184 {
5187 }
5189 /* Functions to save and restore alpha_return_addr_rtx. */
5191 /* Start the ball rolling with RETURN_ADDR_RTX. */
5193 rtx
5195 {
5200 }
5202 /* Return or create a pseudo containing the gp value for the current
5203 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5205 rtx
5207 {
5212 }
5214 static int
5216 {
5217 rtx top;
5227 }
5229 \f
5230 /* Return the trap mode suffix applicable to the current
5231 instruction, or NULL. */
5235 {
5239 {
5255 {
5263 }
5268 {
5277 }
5282 {
5291 }
5293 }
5295 }
5297 /* Return the rounding mode suffix applicable to the current
5298 instruction, or NULL. */
5302 {
5306 {
5311 {
5320 }
5325 }
5327 }
5329 /* Locate some local-dynamic symbol still in use by this function
5330 so that we can print its name in some movdi_er_tlsldm pattern. */
5332 static int
5334 {
5339 {
5342 }
5345 }
5349 {
5350 rtx insn;
5361 }
5363 /* Print an operand. Recognize special options, documented below. */
5365 void
5367 {
5371 {
5373 /* Print the assembler name of the current function. */
5382 {
5390 }
5393 /* Generates single precision instruction suffix. */
5398 /* Generates double precision instruction suffix. */
5403 /* Generates a nop after a noreturn call at the very end of the
5404 function. */
5424 else
5429 {
5433 {
5436 }
5438 {
5441 }
5444 else
5445 {
5448 }
5452 }
5456 /* If this operand is the constant zero, write it as "$31". */
5461 else
5466 /* Similar, but for floating-point. */
5471 else
5476 /* Write the 1's complement of a constant. */
5484 /* Write 1 << C, for a constant C. */
5492 /* Write the high-order 16 bits of a constant, sign-extended. */
5500 /* Write the low-order 16 bits of a constant, sign-extended. */
5509 /* Write mask for ZAP insn. */
5511 {
5513 HOST_WIDE_INT value;
5528 }
5531 {
5539 }
5540 else
5545 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5559 /* Similar, except do it from the mask. */
5561 {
5565 {
5568 }
5570 {
5573 }
5575 {
5578 }
5580 {
5583 }
5584 }
5589 {
5592 }
5597 /* Write the constant value divided by 8 for little-endian mode or
5598 (56 - value) / 8 for big-endian mode. */
5608 WORDS_BIG_ENDIAN
5614 /* Same, except compute (64 - c) / 8 */
5625 {
5626 /* On Unicos/Mk systems: use a DEX expression if the symbol
5627 clashes with a register name. */
5631 else
5633 }
5637 /* Write out comparison name. */
5638 {
5657 else
5659 }
5663 /* Write the divide or modulus operator. */
5665 {
5681 }
5685 /* Write "_u" for unaligned access. */
5696 {
5698 {
5706 }
5707 }
5708 else
5714 }
5715 }
5717 void
5719 {
5728 {
5731 }
5734 {
5739 {
5742 {
5754 }
5757 }
5758 else
5759 {
5763 }
5774 else
5780 }
5790 #if TARGET_ABI_OPEN_VMS
5792 {
5795 }
5799 {
5804 }
5805 #endif
5807 else
5811 }
5812 \f
5813 /* Emit RTL insns to initialize the variable parts of a trampoline at
5814 TRAMP. FNADDR is an RTX for the address of the function's pure
5815 code. CXT is an RTX for the static chain value for the function.
5817 The three offset parameters are for the individual template's
5818 layout. A JMPOFS < 0 indicates that the trampoline does not
5819 contain instructions at all.
5821 We assume here that a function will be called many more times than
5822 its address is taken (e.g., it might be passed to qsort), so we
5823 take the trouble to initialize the "hint" field in the JMP insn.
5824 Note that the hint field is PC (new) + 4 * bits 13:0. */
5826 void
5829 {
5831 /* VMS really uses DImode pointers in memory at this point. */
5834 #ifdef POINTERS_EXTEND_UNSIGNED
5837 #endif
5839 /* Store function address and CXT. */
5845 /* This has been disabled since the hint only has a 32k range, and in
5846 no existing OS is the stack within 32k of the text segment. */
5848 {
5849 /* Compute hint value. */
5852 OPTAB_WIDEN);
5858 /* Merge in the hint. */
5863 OPTAB_WIDEN);
5865 }
5867 #ifdef TRANSFER_FROM_TRAMPOLINE
5870 #endif
5874 }
5875 \f
5876 /* Determine where to put an argument to a function.
5877 Value is zero to push the argument on the stack,
5878 or a hard register in which to store the argument.
5880 MODE is the argument's machine mode.
5881 TYPE is the data type of the argument (as a tree).
5882 This is null for libcalls where that information may
5883 not be available.
5884 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5885 the preceding args and about the function being called.
5886 NAMED is nonzero if this argument is a named parameter
5887 (otherwise it is an extra parameter matching an ellipsis).
5889 On Alpha the first 6 words of args are normally in registers
5890 and the rest are pushed. */
5892 rtx
5895 {
5899 /* Don't get confused and pass small structures in FP registers. */
5902 else
5903 {
5904 #ifdef ENABLE_CHECKING
5905 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5906 values here. */
5909 #endif
5911 /* Set up defaults for FP operands passed in FP registers, and
5912 integral operands passed in integer registers. */
5915 else
5917 }
5919 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5920 the three platforms, so we can't avoid conditional compilation. */
5921 #if TARGET_ABI_OPEN_VMS
5922 {
5929 }
5930 #elif TARGET_ABI_UNICOSMK
5931 {
5934 /* If this is the last argument, generate the call info word (CIW). */
5935 /* ??? We don't include the caller's line number in the CIW because
5936 I don't know how to determine it if debug infos are turned off. */
5938 {
5940 HOST_WIDE_INT lo;
5941 HOST_WIDE_INT hi;
5942 rtx ciw;
5952 else
5955 #if HOST_BITS_PER_WIDE_INT == 32
5957 #else
5961 #endif
5965 UNSPEC_UMK_LOAD_CIW);
5966 }
5974 {
5980 /* The argument fits in two registers. Note that we still need to
5981 reserve a register for empty structures. */
5986 else
5987 {
5991 }
5992 }
5993 }
5994 #elif TARGET_ABI_OSF
5995 {
6000 /* VOID is passed as a special flag for "last argument". */
6007 }
6008 #else
6009 #error Unhandled ABI
6010 #endif
6013 }
6015 /* Return true if TYPE must be returned in memory, instead of in registers. */
6017 static bool
6019 {
6024 {
6027 /* All aggregates are returned in memory. */
6030 }
6034 {
6036 /* Pass all float vectors in memory, like an aggregate. */
6040 /* We judge complex floats on the size of their element,
6041 not the size of the whole type. */
6052 /* ??? We get called on all sorts of random stuff from
6053 aggregate_value_p. We can't abort, but it's not clear
6054 what's safe to return. Pretend it's a struct I guess. */
6056 }
6058 /* Otherwise types must fit in one register. */
6060 }
6062 /* Define how to find the value returned by a function. VALTYPE is the
6063 data type of the value (as a tree). If the precise function being
6064 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
6065 MODE is set instead of VALTYPE for libcalls.
6067 On Alpha the value is found in $0 for integer functions and
6068 $f0 for floating-point functions. */
6070 rtx
6073 {
6077 #ifdef ENABLE_CHECKING
6080 #endif
6087 {
6089 /* Do the same thing as PROMOTE_MODE. */
6091 /* FALLTHRU */
6103 {
6106 return gen_rtx_PARALLEL
6113 }
6117 }
6120 }
6122 /* TCmode complex values are passed by invisible reference. We
6123 should not split these values. */
6125 static bool
6127 {
6129 }
6131 static tree
6133 {
6144 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6146 /* Dummy field to prevent alignment warnings. */
6153 integer_type_node);
6158 ptr_type_node);
6166 }
6168 /* Perform any needed actions needed for a function that is receiving a
6169 variable number of arguments. */
6171 static void
6174 tree type ATTRIBUTE_UNUSED,
6176 {
6177 #if TARGET_ABI_UNICOSMK
6178 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6179 arguments on the stack. Unfortunately, it doesn't always store the first
6180 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6181 with stdargs as we always have at least one named argument there. */
6184 {
6186 {
6189 }
6191 }
6192 #elif TARGET_ABI_OPEN_VMS
6193 /* For VMS, we allocate space for all 6 arg registers plus a count.
6195 However, if NO registers need to be saved, don't allocate any space.
6196 This is not only because we won't need the space, but because AP
6197 includes the current_pretend_args_size and we don't want to mess up
6198 any ap-relative addresses already made. */
6200 {
6202 {
6205 }
6207 }
6208 #else
6209 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6210 only push those that are remaining. However, if NO registers need to
6211 be saved, don't allocate any space. This is not only because we won't
6212 need the space, but because AP includes the current_pretend_args_size
6213 and we don't want to mess up any ap-relative addresses already made.
6215 If we are not to use the floating-point registers, save the integer
6216 registers where we would put the floating-point registers. This is
6217 not the most efficient way to implement varargs with just one register
6218 class, but it isn't worth doing anything more efficient in this rare
6219 case. */
6226 {
6228 rtx tmp;
6242 }
6244 #endif
6245 }
6247 void
6249 {
6250 HOST_WIDE_INT offset;
6259 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6260 up by 48, storing fp arg registers in the first 48 bytes, and the
6261 integer arg registers in the next 48 bytes. This is only done,
6262 however, if any integer registers need to be stored.
6264 If no integer registers need be stored, then we must subtract 48
6265 in order to account for the integer arg registers which are counted
6266 in argsize above, but which are not actually stored on the stack.
6267 Must further be careful here about structures straddling the last
6268 integer argument register; that futzes with pretend_args_size,
6269 which changes the meaning of AP. */
6273 else
6277 {
6285 }
6286 else
6287 {
6306 }
6307 }
6309 rtx
6311 {
6312 rtx addr;
6325 else
6329 type_size,
6342 /* If the type could not be passed in registers, skip the block
6343 reserved for the registers. */
6345 {
6351 }
6359 {
6362 }
6364 {
6370 /* ??? Most irritatingly, we're not returning the value here,
6371 but the address. Since real_part and imag_part are not
6372 necessarily contiguous, we must copy to local storage. */
6382 }
6384 {
6395 }
6410 {
6413 }
6416 }
6417 \f
6418 /* Builtins. */
6420 enum alpha_builtin
6421 {
6422 ALPHA_BUILTIN_CMPBGE,
6423 ALPHA_BUILTIN_EXTBL,
6424 ALPHA_BUILTIN_EXTWL,
6425 ALPHA_BUILTIN_EXTLL,
6426 ALPHA_BUILTIN_EXTQL,
6427 ALPHA_BUILTIN_EXTWH,
6428 ALPHA_BUILTIN_EXTLH,
6429 ALPHA_BUILTIN_EXTQH,
6430 ALPHA_BUILTIN_INSBL,
6431 ALPHA_BUILTIN_INSWL,
6432 ALPHA_BUILTIN_INSLL,
6433 ALPHA_BUILTIN_INSQL,
6434 ALPHA_BUILTIN_INSWH,
6435 ALPHA_BUILTIN_INSLH,
6436 ALPHA_BUILTIN_INSQH,
6437 ALPHA_BUILTIN_MSKBL,
6438 ALPHA_BUILTIN_MSKWL,
6439 ALPHA_BUILTIN_MSKLL,
6440 ALPHA_BUILTIN_MSKQL,
6441 ALPHA_BUILTIN_MSKWH,
6442 ALPHA_BUILTIN_MSKLH,
6443 ALPHA_BUILTIN_MSKQH,
6444 ALPHA_BUILTIN_UMULH,
6445 ALPHA_BUILTIN_ZAP,
6446 ALPHA_BUILTIN_ZAPNOT,
6447 ALPHA_BUILTIN_AMASK,
6448 ALPHA_BUILTIN_IMPLVER,
6449 ALPHA_BUILTIN_RPCC,
6450 ALPHA_BUILTIN_THREAD_POINTER,
6451 ALPHA_BUILTIN_SET_THREAD_POINTER,
6453 /* TARGET_MAX */
6454 ALPHA_BUILTIN_MINUB8,
6455 ALPHA_BUILTIN_MINSB8,
6456 ALPHA_BUILTIN_MINUW4,
6457 ALPHA_BUILTIN_MINSW4,
6458 ALPHA_BUILTIN_MAXUB8,
6459 ALPHA_BUILTIN_MAXSB8,
6460 ALPHA_BUILTIN_MAXUW4,
6461 ALPHA_BUILTIN_MAXSW4,
6462 ALPHA_BUILTIN_PERR,
6463 ALPHA_BUILTIN_PKLB,
6464 ALPHA_BUILTIN_PKWB,
6465 ALPHA_BUILTIN_UNPKBL,
6466 ALPHA_BUILTIN_UNPKBW,
6468 /* TARGET_CIX */
6469 ALPHA_BUILTIN_CTTZ,
6470 ALPHA_BUILTIN_CTLZ,
6471 ALPHA_BUILTIN_CTPOP,
6473 ALPHA_BUILTIN_max
6474 };
6477 CODE_FOR_builtin_cmpbge,
6478 CODE_FOR_builtin_extbl,
6479 CODE_FOR_builtin_extwl,
6480 CODE_FOR_builtin_extll,
6481 CODE_FOR_builtin_extql,
6482 CODE_FOR_builtin_extwh,
6483 CODE_FOR_builtin_extlh,
6484 CODE_FOR_builtin_extqh,
6485 CODE_FOR_builtin_insbl,
6486 CODE_FOR_builtin_inswl,
6487 CODE_FOR_builtin_insll,
6488 CODE_FOR_builtin_insql,
6489 CODE_FOR_builtin_inswh,
6490 CODE_FOR_builtin_inslh,
6491 CODE_FOR_builtin_insqh,
6492 CODE_FOR_builtin_mskbl,
6493 CODE_FOR_builtin_mskwl,
6494 CODE_FOR_builtin_mskll,
6495 CODE_FOR_builtin_mskql,
6496 CODE_FOR_builtin_mskwh,
6497 CODE_FOR_builtin_msklh,
6498 CODE_FOR_builtin_mskqh,
6499 CODE_FOR_umuldi3_highpart,
6500 CODE_FOR_builtin_zap,
6501 CODE_FOR_builtin_zapnot,
6502 CODE_FOR_builtin_amask,
6503 CODE_FOR_builtin_implver,
6504 CODE_FOR_builtin_rpcc,
6505 CODE_FOR_load_tp,
6506 CODE_FOR_set_tp,
6508 /* TARGET_MAX */
6509 CODE_FOR_builtin_minub8,
6510 CODE_FOR_builtin_minsb8,
6511 CODE_FOR_builtin_minuw4,
6512 CODE_FOR_builtin_minsw4,
6513 CODE_FOR_builtin_maxub8,
6514 CODE_FOR_builtin_maxsb8,
6515 CODE_FOR_builtin_maxuw4,
6516 CODE_FOR_builtin_maxsw4,
6517 CODE_FOR_builtin_perr,
6518 CODE_FOR_builtin_pklb,
6519 CODE_FOR_builtin_pkwb,
6520 CODE_FOR_builtin_unpkbl,
6521 CODE_FOR_builtin_unpkbw,
6523 /* TARGET_CIX */
6524 CODE_FOR_builtin_cttz,
6525 CODE_FOR_builtin_ctlz,
6526 CODE_FOR_builtin_ctpop
6527 };
6529 struct alpha_builtin_def
6530 {
6534 };
6539 };
6550 };
6587 };
6589 static void
6591 {
6593 tree ftype;
6614 long_integer_type_node,
6632 }
6634 /* Expand an expression EXP that calls a built-in function,
6635 with result going to TARGET if that's convenient
6636 (and in mode MODE if that's convenient).
6637 SUBTARGET may be used as the target for computing one of EXP's operands.
6638 IGNORE is nonzero if the value is to be ignored. */
6640 static rtx
6642 rtx subtarget ATTRIBUTE_UNUSED,
6645 {
6646 #define MAX_ARGS 2
6665 arglist;
6667 {
6682 }
6685 {
6691 }
6694 {
6701 else
6709 }
6716 else
6718 }
6719 \f
6720 /* This page contains routines that are used to determine what the function
6721 prologue and epilogue code will do and write them out. */
6723 /* Compute the size of the save area in the stack. */
6725 /* These variables are used for communication between the following functions.
6726 They indicate various things about the current function being compiled
6727 that are used to tell what kind of prologue, epilogue and procedure
6728 descriptor to generate. */
6730 /* Nonzero if we need a stack procedure. */
6734 /* Register number (either FP or SP) that is used to unwind the frame. */
6737 /* Register number used to save FP. We need not have one for RA since
6738 we don't modify it for register procedures. This is only defined
6739 for register frame procedures. */
6742 /* Register number used to reference objects off our PV. */
6745 /* Compute register masks for saved registers. */
6747 static void
6749 {
6754 /* When outputting a thunk, we don't have valid register life info,
6755 but assemble_start_function wants to output .frame and .mask
6756 directives. */
6758 {
6762 }
6767 /* One for every register we have to save. */
6772 {
6775 else
6777 }
6779 /* We need to restore these for the handler. */
6781 {
6783 {
6788 }
6790 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6791 avoid hackery in unwind-dw2.c, we need to actively store a
6792 zero in the prologue of _Unwind_RaiseException et al. */
6794 }
6796 /* If any register spilled, then spill the return address also. */
6797 /* ??? This is required by the Digital stack unwind specification
6798 and isn't needed if we're doing Dwarf2 unwinding. */
6804 }
6806 int
6808 {
6816 {
6819 }
6820 else
6821 {
6825 sa_size++;
6826 }
6829 {
6830 /* We might not need to generate a frame if we don't make any calls
6831 (including calls to __T3E_MISMATCH if this is a vararg function),
6832 don't have any local variables which require stack slots, don't
6833 use alloca and have not determined that we need a frame for other
6834 reasons. */
6836 alpha_procedure_type
6838 || current_function_outgoing_args_size
6843 /* Always reserve space for saving callee-saved registers if we
6844 need a frame as required by the calling convention. */
6847 }
6849 {
6850 /* Start by assuming we can use a register procedure if we don't
6851 make any calls (REG_RA not used) or need to save any
6852 registers and a stack procedure if we do. */
6857 else
6860 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6861 made the final decision on stack procedure vs register procedure. */
6865 /* Decide whether to refer to objects off our PV via FP or PV.
6866 If we need FP for something else or if we receive a nonlocal
6867 goto (which expects PV to contain the value), we must use PV.
6868 Otherwise, start by assuming we can use FP. */
6870 vms_base_regno
6871 = (frame_pointer_needed
6872 || current_function_has_nonlocal_label
6877 /* If we want to copy PV into FP, we need to find some register
6878 in which to save FP. */
6891 /* Stack unwinding should be done via FP unless we use it for PV. */
6895 /* If this is a stack procedure, allow space for saving FP and RA. */
6898 }
6899 else
6900 {
6901 /* Our size must be even (multiple of 16 bytes). */
6903 sa_size++;
6904 }
6907 }
6909 /* Define the offset between two registers, one to be eliminated,
6910 and the other its replacement, at the start of a routine. */
6912 HOST_WIDE_INT
6915 {
6916 HOST_WIDE_INT ret;
6922 ;
6927 else
6931 }
6933 int
6935 {
6938 }
6940 int
6942 {
6945 }
6947 #if TARGET_ABI_OPEN_VMS
6950 {
6951 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6956 };
6958 #endif
6960 static int
6962 {
6964 }
6966 int
6968 {
6970 }
6972 static int
6974 {
6975 rtx insn;
6977 /* The GP being variable is an OSF abi thing. */
6981 /* We need the gp to load the address of __mcount. */
6985 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
6989 /* The nonlocal receiver pattern assumes that the gp is valid for
6990 the nested function. Reasonable because it's almost always set
6991 correctly already. For the cases where that's wrong, make sure
6992 the nested function loads its gp on entry. */
6996 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6997 Even if we are a static function, we still need to do this in case
6998 our address is taken and passed to something like qsort. */
7012 }
7014 \f
7015 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7016 sequences. */
7018 static rtx
7020 {
7022 rtx insn;
7030 {
7033 {
7036 }
7038 }
7039 else
7040 {
7043 }
7045 }
7047 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7049 /* Write function prologue. */
7051 /* On vms we have two kinds of functions:
7053 - stack frame (PROC_STACK)
7054 these are 'normal' functions with local vars and which are
7055 calling other functions
7056 - register frame (PROC_REGISTER)
7057 keeps all data in registers, needs no stack
7059 We must pass this to the assembler so it can generate the
7060 proper pdsc (procedure descriptor)
7061 This is done with the '.pdesc' command.
7063 On not-vms, we don't really differentiate between the two, as we can
7064 simply allocate stack without saving registers. */
7066 void
7068 {
7069 /* Registers to save. */
7072 /* Stack space needed for pushing registers clobbered by us. */
7073 HOST_WIDE_INT sa_size;
7074 /* Complete stack size needed. */
7075 HOST_WIDE_INT frame_size;
7076 /* Offset from base reg to register save area. */
7077 HOST_WIDE_INT reg_offset;
7087 + frame_size
7090 /* We have to allocate space for the DSIB if we generate a frame. */
7095 else
7097 + sa_size
7103 else
7108 /* Emit an insn to reload GP, if needed. */
7110 {
7114 }
7116 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7117 the call to mcount ourselves, rather than having the linker do it
7118 magically in response to -pg. Since _mcount has special linkage,
7119 don't represent the call as a call. */
7126 /* Adjust the stack by the frame size. If the frame size is > 4096
7127 bytes, we need to be sure we probe somewhere in the first and last
7128 4096 bytes (we can probably get away without the latter test) and
7129 every 8192 bytes in between. If the frame size is > 32768, we
7130 do this in a loop. Otherwise, we generate the explicit probe
7131 instructions.
7133 Note that we are only allowed to adjust sp once in the prologue. */
7136 {
7138 {
7141 do
7147 /* We only have to do this probe if we aren't saving registers. */
7150 }
7157 }
7158 else
7159 {
7160 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7161 number of 8192 byte blocks to probe. We then probe each block
7162 in the loop and then set SP to the proper location. If the
7163 amount remaining is > 4096, we have to do one more probe if we
7164 are not saving any registers. */
7170 rtx seq;
7176 /* Because of the difficulty in emitting a new basic block this
7177 late in the compilation, generate the loop as a single insn. */
7181 {
7185 }
7188 {
7189 /* For NT stack unwind (done by 'reverse execution'), it's
7190 not OK to take the result of a loop, even though the value
7191 is already in ptr, so we reload it via a single operation
7192 and subtract it to sp.
7194 Yes, that's correct -- we have to reload the whole constant
7195 into a temporary via ldah+lda then subtract from sp. */
7204 ptr));
7205 }
7206 else
7207 {
7210 }
7212 /* This alternative is special, because the DWARF code cannot
7213 possibly intuit through the loop above. So we invent this
7214 note it looks at instead. */
7224 }
7227 {
7228 /* Cope with very large offsets to the register save area. */
7231 {
7233 HOST_WIDE_INT bias;
7237 else
7243 }
7245 /* Save regs in stack order. Beginning with VMS PV. */
7247 {
7251 }
7253 /* Save register RA next. */
7255 {
7261 }
7263 /* Now save any other registers required to be saved. */
7266 {
7271 }
7273 /* Store a zero if requested for unwinding. */
7275 {
7289 }
7293 {
7298 }
7299 }
7301 {
7302 /* The standard frame on the T3E includes space for saving registers.
7303 We just have to use it. We don't have to save the return address and
7304 the old frame pointer here - they are saved in the DSIB. */
7309 {
7311 reg_offset));
7315 }
7318 {
7320 reg_offset));
7324 }
7325 }
7328 {
7330 /* Register frame procedures save the fp.
7331 ?? Ought to have a dwarf2 save for this. */
7333 hard_frame_pointer_rtx);
7343 /* If we have to allocate space for outgoing args, do it now. */
7345 {
7346 rtx seq
7348 plus_constant
7350 - (ALPHA_ROUND
7353 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7354 if ! frame_pointer_needed. Setting the bit will change the CFA
7355 computation rule to use sp again, which would be wrong if we had
7356 frame_pointer_needed, as this means sp might move unpredictably
7357 later on.
7359 Also, note that
7360 frame_pointer_needed
7361 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7362 and
7363 current_function_outgoing_args_size != 0
7364 => alpha_procedure_type != PT_NULL,
7366 so when we are not setting the bit here, we are guaranteed to
7367 have emitted an FRP frame pointer update just before. */
7369 }
7370 }
7372 {
7373 /* If we need a frame pointer, set it from the stack pointer. */
7375 {
7378 else
7379 /* This must always be the last instruction in the
7380 prologue, thus we emit a special move + clobber. */
7383 }
7384 }
7386 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7387 the prologue, for exception handling reasons, we cannot do this for
7388 any insn that might fault. We could prevent this for mems with a
7389 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7390 have to prevent all such scheduling with a blockage.
7392 Linux, on the other hand, never bothered to implement OSF/1's
7393 exception handling, and so doesn't care about such things. Anyone
7394 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7398 }
7400 /* Output the textual info surrounding the prologue. */
7402 void
7404 tree decl ATTRIBUTE_UNUSED)
7405 {
7408 /* Stack space needed for pushing registers clobbered by us. */
7409 HOST_WIDE_INT sa_size;
7410 /* Complete stack size needed. */
7412 /* Offset from base reg to register save area. */
7413 HOST_WIDE_INT reg_offset;
7417 /* Don't emit an extern directive for functions defined in the same file. */
7419 {
7420 tree name_tree;
7423 }
7432 + frame_size
7439 else
7441 + sa_size
7447 else
7452 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7453 We have to do that before the .ent directive as we cannot switch
7454 files within procedures with native ecoff because line numbers are
7455 linked to procedure descriptors.
7456 Outputting the lineno helps debugging of one line functions as they
7457 would otherwise get no line number at all. Please note that we would
7458 like to put out last_linenum from final.c, but it is not accessible. */
7461 {
7462 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7465 #endif
7466 #ifdef ASM_OUTPUT_SOURCE_LINE
7470 #endif
7471 }
7473 /* Issue function start and label. */
7476 {
7481 /* If the function needs GP, we'll write the "..ng" label there.
7482 Otherwise, do it here. */
7484 && ! alpha_function_needs_gp
7486 {
7490 }
7491 }
7497 /* For public functions, the label must be globalized by appending an
7498 additional colon. */
7510 {
7511 /* Set flags in procedure descriptor to request IEEE-conformant
7512 math-library routines. The value we set it to is PDSC_EXC_IEEE
7513 (/usr/include/pdsc.h). */
7515 }
7517 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7521 /* Describe our frame. If the frame size is larger than an integer,
7522 print it as zero to avoid an assembler error. We won't be
7523 properly describing such a frame, but that's the best we can do. */
7525 ;
7529 vms_unwind_regno,
7531 reg_offset);
7534 (frame_pointer_needed
7537 current_function_pretend_args_size);
7539 /* Describe which registers were spilled. */
7541 ;
7543 {
7545 /* ??? Does VMS care if mask contains ra? The old code didn't
7546 set it, so I don't here. */
7552 }
7554 {
7556 {
7563 }
7568 }
7570 #if TARGET_ABI_OPEN_VMS
7571 /* Ifdef'ed cause link_section are only available then. */
7580 #endif
7581 }
7583 /* Emit the .prologue note at the scheduled end of the prologue. */
7585 static void
7587 {
7589 ;
7597 }
7599 /* Write function epilogue. */
7601 /* ??? At some point we will want to support full unwind, and so will
7602 need to mark the epilogue as well. At the moment, we just confuse
7603 dwarf2out. */
7604 #undef FRP
7605 #define FRP(exp) exp
7607 void
7609 {
7610 /* Registers to save. */
7613 /* Stack space needed for pushing registers clobbered by us. */
7614 HOST_WIDE_INT sa_size;
7615 /* Complete stack size needed. */
7616 HOST_WIDE_INT frame_size;
7617 /* Offset from base reg to register save area. */
7618 HOST_WIDE_INT reg_offset;
7622 rtx eh_ofs;
7631 + frame_size
7638 else
7640 + sa_size
7645 {
7648 else
7650 }
7651 else
7656 fp_is_frame_pointer
7664 else
7668 {
7669 /* If we have a frame pointer, restore SP from it. */
7675 /* Cope with very large offsets to the register save area. */
7677 {
7679 HOST_WIDE_INT bias;
7683 else
7690 }
7692 /* Restore registers in order, excepting a true frame pointer. */
7704 {
7707 else
7708 {
7712 }
7714 }
7721 {
7726 }
7727 }
7729 {
7730 /* Restore callee-saved general-purpose registers. */
7736 {
7738 reg_offset));
7742 }
7746 {
7748 reg_offset));
7752 }
7754 /* Restore the return address from the DSIB. */
7759 }
7762 {
7766 {
7770 }
7772 /* If the stack size is large, begin computation into a temporary
7773 register so as not to interfere with a potential fp restore,
7774 which must be consecutive with an SP restore. */
7779 {
7783 }
7785 {
7791 else
7792 {
7795 }
7797 }
7798 else
7799 {
7803 {
7804 /* We can't drop new things to memory this late, afaik,
7805 so build it up by pieces. */
7810 }
7811 }
7813 /* From now on, things must be in order. So emit blockages. */
7815 /* Restore the frame pointer. */
7817 {
7823 }
7825 {
7830 }
7832 {
7836 }
7838 /* Restore the stack pointer. */
7842 else
7845 }
7846 else
7847 {
7849 {
7853 }
7855 {
7856 /* Decrement the frame pointer if the function does not have a
7857 frame. */
7862 }
7863 }
7864 }
7865 \f
7866 /* Output the rest of the textual info surrounding the epilogue. */
7868 void
7870 {
7871 /* End the function. */
7873 {
7877 }
7880 #if TARGET_ABI_OPEN_VMS
7882 #endif
7884 /* Output jump tables and the static subroutine information block. */
7886 {
7889 }
7890 }
7892 #if TARGET_ABI_OSF
7893 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7895 In order to avoid the hordes of differences between generated code
7896 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7897 lots of code loading up large constants, generate rtl and emit it
7898 instead of going straight to text.
7900 Not sure why this idea hasn't been explored before... */
7902 static void
7905 tree function)
7906 {
7910 /* We always require a valid GP. */
7914 /* Find the "this" pointer. If the function returns a structure,
7915 the structure return pointer is in $16. */
7918 else
7921 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7922 entire constant for the add. */
7926 {
7931 }
7932 else
7933 {
7937 }
7939 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7941 {
7950 {
7953 }
7954 else
7955 {
7960 }
7963 else
7968 }
7970 /* Generate a tail call to the target function. */
7972 {
7975 }
7981 /* Run just enough of rest_of_compilation to get the insns emitted.
7982 There's not really enough bulk here to make other passes such as
7983 instruction scheduling worth while. Note that use_thunk calls
7984 assemble_start_function and assemble_end_function. */
7991 }
7993 \f
7994 /* Debugging support. */
7998 /* Count the number of sdb related labels are generated (to find block
7999 start and end boundaries). */
8003 /* Next label # for each statement. */
8007 /* Count the number of .file directives, so that .loc is up to date. */
8011 /* Name of the file containing the current function. */
8015 /* Offsets to alpha virtual arg/local debugging pointers. */
8019 \f
8020 /* Emit a new filename to a stream. */
8022 void
8024 {
8029 {
8038 }
8041 {
8046 }
8050 {
8053 else
8054 {
8058 }
8062 }
8063 }
8065 /* Emit a linenumber to a stream. */
8067 void
8069 {
8071 {
8072 /* mips-tfile doesn't understand .stabd directives. */
8076 }
8077 else
8079 }
8080 \f
8081 /* Structure to show the current status of registers and memory. */
8083 struct shadow_summary
8084 {
8090 };
8092 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8093 to the summary structure. SET is nonzero if the insn is setting the
8094 object, otherwise zero. */
8096 static void
8098 {
8106 {
8107 /* ??? Note that this case would be incorrect if the Alpha had a
8108 ZERO_EXTRACT in SET_DEST. */
8137 {
8145 {
8148 else
8150 }
8151 else
8152 {
8155 else
8157 }
8158 }
8164 else
8167 /* Find the regs used in memory address computation: */
8176 /* Handle common unary and binary ops for efficiency. */
8198 {
8213 }
8214 }
8215 }
8217 /* Ensure a sufficient number of `trapb' insns are in the code when
8218 the user requests code with a trap precision of functions or
8219 instructions.
8221 In naive mode, when the user requests a trap-precision of
8222 "instruction", a trapb is needed after every instruction that may
8223 generate a trap. This ensures that the code is resumption safe but
8224 it is also slow.
8226 When optimizations are turned on, we delay issuing a trapb as long
8227 as possible. In this context, a trap shadow is the sequence of
8228 instructions that starts with a (potentially) trap generating
8229 instruction and extends to the next trapb or call_pal instruction
8230 (but GCC never generates call_pal by itself). We can delay (and
8231 therefore sometimes omit) a trapb subject to the following
8232 conditions:
8234 (a) On entry to the trap shadow, if any Alpha register or memory
8235 location contains a value that is used as an operand value by some
8236 instruction in the trap shadow (live on entry), then no instruction
8237 in the trap shadow may modify the register or memory location.
8239 (b) Within the trap shadow, the computation of the base register
8240 for a memory load or store instruction may not involve using the
8241 result of an instruction that might generate an UNPREDICTABLE
8242 result.
8244 (c) Within the trap shadow, no register may be used more than once
8245 as a destination register. (This is to make life easier for the
8246 trap-handler.)
8248 (d) The trap shadow may not include any branch instructions. */
8250 static void
8252 {
8265 {
8267 {
8269 {
8271 exception_nesting++;
8277 exception_nesting--;
8286 }
8287 }
8289 {
8291 {
8295 }
8297 {
8299 {
8308 {
8310 /* Annoyingly, get_attr_trap will abort on these. */
8319 {
8320 /* (c) would be violated */
8322 }
8324 /* Combine shadow with summary of current insn: */
8335 {
8336 /* (a) would be violated (also takes care of (b)) */
8343 }
8353 }
8354 }
8355 else
8356 {
8357 close_shadow:
8366 }
8367 }
8368 }
8375 {
8379 }
8380 }
8381 }
8382 \f
8383 /* Alpha can only issue instruction groups simultaneously if they are
8384 suitably aligned. This is very processor-specific. */
8391 };
8402 };
8404 static enum alphaev4_pipe
8406 {
8413 {
8443 }
8444 }
8446 static enum alphaev5_pipe
8448 {
8455 {
8492 }
8493 }
8495 /* IN_USE is a mask of the slots currently filled within the insn group.
8496 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8497 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8499 LEN is, of course, the length of the group in bytes. */
8501 static rtx
8503 {
8514 {
8519 {
8521 /* Force complex instructions to start new groups. */
8525 /* If this is a completely unrecognized insn, its an asm.
8526 We don't know how long it is, so record length as -1 to
8527 signal a needed realignment. */
8530 else
8536 {
8540 }
8541 else
8547 {
8551 }
8563 }
8566 /* Haifa doesn't do well scheduling branches. */
8570 next:
8576 /* Let Haifa tell us where it thinks insn group boundaries are. */
8582 }
8584 next_and_done:
8587 done:
8591 }
8593 /* IN_USE is a mask of the slots currently filled within the insn group.
8594 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8595 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8597 LEN is, of course, the length of the group in bytes. */
8599 static rtx
8601 {
8612 {
8617 {
8619 /* Force complex instructions to start new groups. */
8623 /* If this is a completely unrecognized insn, its an asm.
8624 We don't know how long it is, so record length as -1 to
8625 signal a needed realignment. */
8628 else
8632 /* ??? Most of the places below, we would like to abort, as
8633 it would indicate an error either in Haifa, or in the
8634 scheduling description. Unfortunately, Haifa never
8635 schedules the last instruction of the BB, so we don't
8636 have an accurate TI bit to go off. */
8639 {
8643 }
8644 else
8650 {
8654 }
8666 {
8670 }
8671 else
8692 }
8695 /* Haifa doesn't do well scheduling branches. */
8696 /* ??? If this is predicted not-taken, slotting continues, except
8697 that no more IBR, FBR, or JSR insns may be slotted. */
8701 next:
8707 /* Let Haifa tell us where it thinks insn group boundaries are. */
8713 }
8715 next_and_done:
8718 done:
8722 }
8724 static rtx
8726 {
8728 rtx nop;
8731 {
8734 }
8736 {
8739 }
8741 {
8744 }
8745 else
8750 }
8752 static rtx
8754 {
8756 rtx nop;
8759 {
8762 }
8764 {
8767 }
8769 {
8772 }
8773 else
8778 }
8780 /* The instruction group alignment main loop. */
8782 static void
8786 {
8787 /* ALIGN is the known alignment for the insn group. */
8789 /* OFS is the offset of the current insn in the insn group. */
8794 /* Let shorten branches care for assigning alignments to code labels. */
8801 else
8810 {
8813 /* When we see a label, resync alignment etc. */
8815 {
8819 {
8822 }
8828 }
8830 /* Handle complex instructions special. */
8832 {
8833 /* Asms will have length < 0. This is a signal that we have
8834 lost alignment knowledge. Assume, however, that the asm
8835 will not mis-align instructions. */
8837 {
8841 }
8842 }
8844 /* If the known alignment is smaller than the recognized insn group,
8845 realign the output. */
8847 {
8855 /* Can't realign between a call and its gp reload. */
8858 {
8862 }
8863 }
8865 /* If the group won't fit in the same INT16 as the previous,
8866 we need to add padding to keep the group together. Rather
8867 than simply leaving the insn filling to the assembler, we
8868 can make use of the knowledge of what sorts of instructions
8869 were issued in the previous group to make sure that all of
8870 the added nops are really free. */
8872 {
8874 rtx where;
8876 /* Insert nops before labels, branches, and calls to truly merge
8877 the execution of the nops with the previous instruction group. */
8880 {
8882 {
8886 }
8889 }
8890 else
8893 do
8897 }
8902 }
8903 }
8904 \f
8905 /* Machine dependent reorg pass. */
8907 static void
8909 {
8913 /* Due to the number of extra trapb insns, don't bother fixing up
8914 alignment when trap precision is instruction. Moreover, we can
8915 only do our job when sched2 is run. */
8919 {
8924 }
8925 }
8926 \f
8927 #if !TARGET_ABI_UNICOSMK
8929 #ifdef HAVE_STAMP_H
8930 #include <stamp.h>
8931 #endif
8933 static void
8935 {
8936 #ifdef OBJECT_FORMAT_ELF
8937 /* If emitting dwarf2 debug information, we cannot generate a .file
8938 directive to start the file, as it will conflict with dwarf2out
8939 file numbers. So it's only useful when emitting mdebug output. */
8941 #endif
8944 #ifdef MS_STAMP
8946 #endif
8958 : (TARGET_CPU_EV5
8961 }
8962 #endif
8964 #ifdef OBJECT_FORMAT_ELF
8966 /* Switch to the section to which we should output X. The only thing
8967 special we do here is to honor small data. */
8969 static void
8972 {
8974 /* ??? Consider using mergeable sdata sections. */
8976 else
8978 }
8981 \f
8982 /* Structure to collect function names for final output in link section. */
8983 /* Note that items marked with GTY can't be ifdef'ed out. */
8989 {
8991 rtx linkage;
8994 };
8997 {
9000 links;
9001 };
9004 splay_tree alpha_links_tree;
9006 splay_tree alpha_funcs_tree;
9010 #if TARGET_ABI_OPEN_VMS
9012 /* Return the VMS argument type corresponding to MODE. */
9014 enum avms_arg_type
9016 {
9018 {
9025 }
9026 }
9028 /* Return an rtx for an integer representing the VMS Argument Information
9029 register value. */
9031 rtx
9033 {
9041 }
9042 \f
9043 /* Make (or fake) .linkage entry for function call.
9045 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9047 Return an SYMBOL_REF rtx for the linkage. */
9049 rtx
9051 {
9052 splay_tree_node node;
9056 name++;
9059 {
9064 splay_tree_compare_pointers);
9074 }
9077 {
9078 /* Is this name already defined? */
9082 {
9085 {
9086 /* Defined here but external assumed. */
9089 }
9090 else
9091 {
9092 /* Used here but unused assumed. */
9095 }
9097 }
9098 }
9099 else
9105 /* Assume external if no definition. */
9108 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9111 /* Construct a SYMBOL_REF for us to call. */
9112 {
9120 }
9126 }
9128 rtx
9130 {
9131 splay_tree_node cfunnode;
9143 {
9144 splay_tree_node lnode;
9146 /* Is this name already defined? */
9151 }
9152 else
9156 {
9165 name++;
9174 {
9177 }
9189 }
9193 else
9198 else
9200 }
9202 static int
9204 {
9211 {
9213 {
9214 /* Local and used */
9216 }
9217 else
9218 {
9219 /* External and used, request code address. */
9221 }
9222 }
9223 else
9224 {
9226 {
9227 /* Local and used, build linkage pair. */
9230 }
9231 else
9232 {
9233 /* External and used, request linkage pair. */
9235 }
9236 }
9239 }
9241 static void
9243 {
9244 splay_tree_node node;
9263 {
9265 /* splay_tree_delete (func->links); */
9266 }
9267 }
9269 /* Given a decl, a section name, and whether the decl initializer
9270 has relocs, choose attributes for the section. */
9272 #define SECTION_VMS_OVERLAY SECTION_FORGET
9273 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9274 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9276 static unsigned int
9278 {
9292 }
9294 /* Switch to an arbitrary section NAME with attributes as specified
9295 by FLAGS. ALIGN specifies any known alignment requirements for
9296 the section; 0 if the default should be used. */
9298 static void
9300 {
9314 }
9316 /* Record an element in the table of global constructors. SYMBOL is
9317 a SYMBOL_REF of the function to be called; PRIORITY is a number
9318 between 0 and MAX_INIT_PRIORITY.
9320 Differs from default_ctors_section_asm_out_constructor in that the
9321 width of the .ctors entry is always 64 bits, rather than the 32 bits
9322 used by a normal pointer. */
9324 static void
9326 {
9330 }
9332 static void
9334 {
9338 }
9339 #else
9341 rtx
9344 {
9346 }
9348 rtx
9350 tree cfundecl ATTRIBUTE_UNUSED,
9353 {
9355 }
9358 \f
9359 #if TARGET_ABI_UNICOSMK
9361 /* Define the offset between two registers, one to be eliminated, and the
9362 other its replacement, at the start of a routine. */
9364 int
9366 {
9384 else
9386 }
9388 /* Output the module name for .ident and .end directives. We have to strip
9389 directories and add make sure that the module name starts with a letter
9390 or '$'. */
9392 static void
9394 {
9400 /* CAM only accepts module names that start with a letter or '$'. We
9401 prefix the module name with a '$' if necessary. */
9408 }
9410 /* Output the definition of a common variable. */
9412 void
9414 {
9415 tree name_tree;
9424 /* Mark the symbol as defined in this module. */
9427 }
9429 #define SECTION_PUBLIC SECTION_MACH_DEP
9430 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9433 static unsigned int
9436 {
9443 {
9450 }
9451 else
9458 }
9460 /* Generate a section name for decl and associate it with the
9461 declaration. */
9463 static void
9465 {
9477 {
9480 /* It is essential that we prefix the section name here because
9481 otherwise the section names generated for constructors and
9482 destructors confuse collect2. */
9487 }
9490 else
9491 {
9497 }
9498 }
9500 /* Switch to an arbitrary section NAME with attributes as specified
9501 by FLAGS. ALIGN specifies any known alignment requirements for
9502 the section; 0 if the default should be used. */
9504 static void
9506 {
9509 /* Close the previous section. */
9513 /* Find out what kind of section we are opening. */
9522 else
9528 else
9530 }
9532 static void
9534 {
9538 }
9540 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9541 in code sections because .align fill unused space with zeroes. */
9543 void
9545 {
9548 else
9550 }
9552 /* Add a case vector to the current function's list of deferred case
9553 vectors. Case vectors have to be put into a separate section because CAM
9554 does not allow data definitions in code sections. */
9556 void
9558 {
9564 }
9566 /* Output a case vector. */
9568 static void
9570 {
9579 {
9580 ASM_OUTPUT_ADDR_VEC_ELT
9582 }
9583 }
9585 /* Output current function's deferred case vectors. */
9587 static void
9589 {
9591 rtx t;
9599 }
9601 /* Generate the name of the SSIB section for the current function. */
9604 #define SSIB_PREFIX_LEN 7
9608 {
9609 /* This is ok since CAM won't be able to deal with names longer than that
9610 anyway. */
9614 rtx x;
9635 }
9637 /* Set up the dynamic subprogram information block (DSIB) and update the
9638 frame pointer register ($15) for subroutines which have a frame. If the
9639 subroutine doesn't have a frame, simply increment $15. */
9641 static void
9643 {
9645 {
9647 rtx mem;
9649 /* Allocate 64 bytes for the DSIB. */
9655 /* Save the return address. */
9662 /* Save the old frame pointer. */
9671 /* Store the SSIB pointer. */
9681 /* Save the CIW index. */
9689 /* Set the new frame pointer. */
9694 }
9695 else
9696 {
9697 /* Increment the frame pointer register to indicate that we do not
9698 have a frame. */
9702 }
9703 }
9705 /* Output the static subroutine information block for the current
9706 function. */
9708 static void
9710 {
9713 rtx x;
9714 rtx ciw;
9721 /* Some required stuff and the function name length. */
9726 /* Saved registers
9727 ??? We don't do that yet. */
9731 /* Function address. */
9740 /* Function name.
9741 ??? We do it the same way Cray CC does it but this could be
9742 simplified. */
9748 else
9751 /* All call information words used in the function. */
9754 {
9756 #if HOST_BITS_PER_WIDE_INT == 32
9759 #else
9761 #endif
9762 }
9763 }
9765 /* Add a call information word (CIW) to the list of the current function's
9766 CIWs and return its index.
9768 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9770 rtx
9772 {
9773 rtx node;
9779 else
9787 }
9793 {
9796 count++);
9798 }
9802 {
9805 count++);
9807 }
9809 /* The Cray assembler doesn't accept extern declarations for symbols which
9810 are defined in the same file. We have to keep track of all global
9811 symbols which are referenced and/or defined in a source file and output
9812 extern declarations for those which are referenced but not defined at
9813 the end of file. */
9815 /* List of identifiers for which an extern declaration might have to be
9816 emitted. */
9817 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9819 struct unicosmk_extern_list
9820 {
9823 };
9827 /* Output extern declarations which are required for every asm file. */
9829 static void
9831 {
9842 }
9844 /* Output extern declarations for global symbols which are have been
9845 referenced but not defined. */
9847 static void
9849 {
9853 tree name_tree;
9857 {
9858 /* We have to strip the encoding and possibly remove user_label_prefix
9859 from the identifier in order to handle -fleading-underscore and
9860 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9868 {
9873 }
9874 }
9875 }
9877 /* Record an extern. */
9879 void
9881 {
9889 }
9891 /* The Cray assembler generates incorrect code if identifiers which
9892 conflict with register names are used as instruction operands. We have
9893 to replace such identifiers with DEX expressions. */
9895 /* Structure to collect identifiers which have been replaced by DEX
9896 expressions. */
9897 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9902 };
9904 /* List of identifiers which have been replaced by DEX expressions. The DEX
9905 number is determined by the position in the list. */
9909 /* The number of elements in the DEX list. */
9913 /* Check if NAME must be replaced by a DEX expression. */
9915 static int
9917 {
9928 {
9938 }
9939 }
9941 /* Return the DEX number if X must be replaced by a DEX expression and 0
9942 otherwise. */
9944 static int
9946 {
9960 {
9964 }
9973 }
9975 /* Output the DEX definitions for this file. */
9977 static void
9979 {
9990 {
9995 }
9998 }
10000 /* Output text that to appear at the beginning of an assembler file. */
10002 static void
10004 {
10011 /* The Unicos/Mk assembler uses different register names. Instead of trying
10012 to support them, we simply use micro definitions. */
10014 /* CAM has different register names: rN for the integer register N and fN
10015 for the floating-point register N. Instead of trying to use these in
10016 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10017 register. */
10027 /* The .align directive fill unused space with zeroes which does not work
10028 in code sections. We define the macro 'gcc@code@align' which uses nops
10029 instead. Note that it assumes that code sections always have the
10030 biggest possible alignment since . refers to the current offset from
10031 the beginning of the section. */
10043 /* Output extern declarations which should always be visible. */
10046 /* Open a dummy section. We always need to be inside a section for the
10047 section-switching code to work correctly.
10048 ??? This should be a module id or something like that. I still have to
10049 figure out what the rules for those are. */
10051 }
10053 /* Output text to appear at the end of an assembler file. This includes all
10054 pending extern declarations and DEX expressions. */
10056 static void
10058 {
10061 /* Output all pending externs. */
10065 /* Output dex definitions used for functions whose names conflict with
10066 register names. */
10073 }
10075 #else
10077 static void
10079 {}
10081 static void
10083 {}
10085 static void
10088 {}
10090 rtx
10092 {
10094 }
10096 static int
10098 {
10100 }
10104 static void
10106 {
10108 {
10109 /* Prevent gcc from generating calls to __divsi3. */
10113 /* Use the functions provided by the system library
10114 for DImode integer division. */
10117 }
10119 {
10120 /* Use the VMS runtime library functions for division and
10121 remainder. */
10130 }
10131 }
10133 \f
10134 /* Initialize the GCC target structure. */
10135 #if TARGET_ABI_OPEN_VMS
10136 # undef TARGET_ATTRIBUTE_TABLE
10137 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10138 # undef TARGET_SECTION_TYPE_FLAGS
10139 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10140 #endif
10142 #undef TARGET_IN_SMALL_DATA_P
10143 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10145 #if TARGET_ABI_UNICOSMK
10146 # undef TARGET_INSERT_ATTRIBUTES
10147 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10148 # undef TARGET_SECTION_TYPE_FLAGS
10149 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10150 # undef TARGET_ASM_UNIQUE_SECTION
10151 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10152 # undef TARGET_ASM_GLOBALIZE_LABEL
10153 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10154 #endif
10156 #undef TARGET_ASM_ALIGNED_HI_OP
10158 #undef TARGET_ASM_ALIGNED_DI_OP
10161 /* Default unaligned ops are provided for ELF systems. To get unaligned
10162 data for non-ELF systems, we have to turn off auto alignment. */
10163 #ifndef OBJECT_FORMAT_ELF
10164 #undef TARGET_ASM_UNALIGNED_HI_OP
10166 #undef TARGET_ASM_UNALIGNED_SI_OP
10168 #undef TARGET_ASM_UNALIGNED_DI_OP
10170 #endif
10172 #ifdef OBJECT_FORMAT_ELF
10173 #undef TARGET_ASM_SELECT_RTX_SECTION
10174 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10175 #endif
10177 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10178 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10180 #undef TARGET_INIT_LIBFUNCS
10181 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10183 #if TARGET_ABI_UNICOSMK
10184 #undef TARGET_ASM_FILE_START
10185 #define TARGET_ASM_FILE_START unicosmk_file_start
10186 #undef TARGET_ASM_FILE_END
10187 #define TARGET_ASM_FILE_END unicosmk_file_end
10188 #else
10189 #undef TARGET_ASM_FILE_START
10190 #define TARGET_ASM_FILE_START alpha_file_start
10191 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10192 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10193 #endif
10195 #undef TARGET_SCHED_ADJUST_COST
10196 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10197 #undef TARGET_SCHED_ISSUE_RATE
10198 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10199 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10200 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
10201 alpha_use_dfa_pipeline_interface
10202 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10203 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10204 alpha_multipass_dfa_lookahead
10206 #undef TARGET_HAVE_TLS
10207 #define TARGET_HAVE_TLS HAVE_AS_TLS
10209 #undef TARGET_INIT_BUILTINS
10210 #define TARGET_INIT_BUILTINS alpha_init_builtins
10211 #undef TARGET_EXPAND_BUILTIN
10212 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10214 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10215 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10216 #undef TARGET_CANNOT_COPY_INSN_P
10217 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10219 #if TARGET_ABI_OSF
10220 #undef TARGET_ASM_OUTPUT_MI_THUNK
10221 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10222 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10223 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10224 #endif
10226 #undef TARGET_RTX_COSTS
10227 #define TARGET_RTX_COSTS alpha_rtx_costs
10228 #undef TARGET_ADDRESS_COST
10229 #define TARGET_ADDRESS_COST hook_int_rtx_0
10231 #undef TARGET_MACHINE_DEPENDENT_REORG
10232 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10234 #undef TARGET_PROMOTE_FUNCTION_ARGS
10235 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10236 #undef TARGET_PROMOTE_FUNCTION_RETURN
10237 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10238 #undef TARGET_PROMOTE_PROTOTYPES
10239 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10240 #undef TARGET_STRUCT_VALUE_RTX
10241 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
10242 #undef TARGET_RETURN_IN_MEMORY
10243 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10244 #undef TARGET_SETUP_INCOMING_VARARGS
10245 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10246 #undef TARGET_STRICT_ARGUMENT_NAMING
10247 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10248 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10249 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10250 #undef TARGET_SPLIT_COMPLEX_ARG
10251 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
10253 #undef TARGET_BUILD_BUILTIN_VA_LIST
10254 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10258 \f