1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode
;
57 typedef struct minipool_fixup Mfix
;
59 const struct attribute_spec arm_attribute_table
[];
61 /* Forward function declarations. */
62 static arm_stack_offsets
*arm_get_frame_offsets (void);
63 static void arm_add_gc_roots (void);
64 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
65 HOST_WIDE_INT
, rtx
, rtx
, int, int);
66 static unsigned bit_count (unsigned long);
67 static int arm_address_register_rtx_p (rtx
, int);
68 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
69 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
70 inline static int thumb_index_register_rtx_p (rtx
, int);
71 static int thumb_far_jump_used_p (void);
72 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
73 static rtx
emit_multi_reg_push (int);
74 static rtx
emit_sfm (int, int);
76 static bool arm_assemble_integer (rtx
, unsigned int, int);
78 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
79 static arm_cc
get_arm_condition_code (rtx
);
80 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
81 static rtx
is_jump_table (rtx
);
82 static const char *output_multi_immediate (rtx
*, const char *, const char *,
84 static void print_multi_reg (FILE *, const char *, int, int);
85 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
86 static struct machine_function
*arm_init_machine_status (void);
87 static int number_of_first_bit_set (int);
88 static void replace_symbols_in_block (tree
, rtx
, rtx
);
89 static void thumb_exit (FILE *, int, rtx
);
90 static void thumb_pushpop (FILE *, int, int, int *, int);
91 static rtx
is_jump_table (rtx
);
92 static HOST_WIDE_INT
get_jump_table_size (rtx
);
93 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_forward_ref (Mfix
*);
95 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
96 static Mnode
*add_minipool_backward_ref (Mfix
*);
97 static void assign_minipool_offsets (Mfix
*);
98 static void arm_print_value (FILE *, rtx
);
99 static void dump_minipool (rtx
);
100 static int arm_barrier_cost (rtx
);
101 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
102 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
103 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
107 static int current_file_function_operand (rtx
);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree
);
111 static unsigned long arm_compute_func_type (void);
112 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
113 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
114 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
115 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
116 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static int arm_comp_type_attributes (tree
, tree
);
118 static void arm_set_default_type_attributes (tree
);
119 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
120 static int arm_use_dfa_pipeline_interface (void);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
129 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
131 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
132 static int arm_address_cost (rtx
);
133 static bool arm_memory_load_p (rtx
);
134 static bool arm_cirrus_insn_p (rtx
);
135 static void cirrus_reorg (rtx
);
136 static void arm_init_builtins (void);
137 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
138 static void arm_init_iwmmxt_builtins (void);
139 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
140 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
141 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
142 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
143 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 #ifdef OBJECT_FORMAT_ELF
146 static void arm_elf_asm_named_section (const char *, unsigned int);
149 static void arm_encode_section_info (tree
, rtx
, int);
152 static void aof_globalize_label (FILE *, const char *);
153 static void aof_dump_imports (FILE *);
154 static void aof_dump_pic_table (FILE *);
155 static void aof_file_start (void);
156 static void aof_file_end (void);
158 static rtx
arm_struct_value_rtx (tree
, int);
159 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
161 static bool arm_promote_prototypes (tree
);
162 static bool arm_default_short_enums (void);
165 /* Initialize the GCC target structure. */
166 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
167 #undef TARGET_MERGE_DECL_ATTRIBUTES
168 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
171 #undef TARGET_ATTRIBUTE_TABLE
172 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
175 #undef TARGET_ASM_BYTE_OP
176 #define TARGET_ASM_BYTE_OP "\tDCB\t"
177 #undef TARGET_ASM_ALIGNED_HI_OP
178 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
179 #undef TARGET_ASM_ALIGNED_SI_OP
180 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
181 #undef TARGET_ASM_GLOBALIZE_LABEL
182 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
183 #undef TARGET_ASM_FILE_START
184 #define TARGET_ASM_FILE_START aof_file_start
185 #undef TARGET_ASM_FILE_END
186 #define TARGET_ASM_FILE_END aof_file_end
188 #undef TARGET_ASM_ALIGNED_SI_OP
189 #define TARGET_ASM_ALIGNED_SI_OP NULL
190 #undef TARGET_ASM_INTEGER
191 #define TARGET_ASM_INTEGER arm_assemble_integer
194 #undef TARGET_ASM_FUNCTION_PROLOGUE
195 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
197 #undef TARGET_ASM_FUNCTION_EPILOGUE
198 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
200 #undef TARGET_COMP_TYPE_ATTRIBUTES
201 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
203 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
204 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
206 #undef TARGET_SCHED_ADJUST_COST
207 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
209 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
210 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
212 #undef TARGET_ENCODE_SECTION_INFO
214 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
216 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
219 #undef TARGET_STRIP_NAME_ENCODING
220 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
222 #undef TARGET_ASM_INTERNAL_LABEL
223 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
225 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
226 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
228 #undef TARGET_ASM_OUTPUT_MI_THUNK
229 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
230 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
231 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
233 /* This will be overridden in arm_override_options. */
234 #undef TARGET_RTX_COSTS
235 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
236 #undef TARGET_ADDRESS_COST
237 #define TARGET_ADDRESS_COST arm_address_cost
239 #undef TARGET_MACHINE_DEPENDENT_REORG
240 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
242 #undef TARGET_INIT_BUILTINS
243 #define TARGET_INIT_BUILTINS arm_init_builtins
244 #undef TARGET_EXPAND_BUILTIN
245 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
247 #undef TARGET_PROMOTE_FUNCTION_ARGS
248 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
249 #undef TARGET_PROMOTE_FUNCTION_RETURN
250 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
251 #undef TARGET_PROMOTE_PROTOTYPES
252 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
254 #undef TARGET_STRUCT_VALUE_RTX
255 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
257 #undef TARGET_SETUP_INCOMING_VARARGS
258 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
260 #undef TARGET_DEFAULT_SHORT_ENUMS
261 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
263 struct gcc_target targetm
= TARGET_INITIALIZER
;
265 /* Obstack for minipool constant handling. */
266 static struct obstack minipool_obstack
;
267 static char * minipool_startobj
;
269 /* The maximum number of insns skipped which
270 will be conditionalised if possible. */
271 static int max_insns_skipped
= 5;
273 extern FILE * asm_out_file
;
275 /* True if we are currently building a constant table. */
276 int making_const_table
;
278 /* Define the information needed to generate branch insns. This is
279 stored from the compare operation. */
280 rtx arm_compare_op0
, arm_compare_op1
;
282 /* The processor for which instructions should be scheduled. */
283 enum processor_type arm_tune
= arm_none
;
285 /* Which floating point model to use. */
286 enum arm_fp_model arm_fp_model
;
288 /* Which floating point hardware is available. */
289 enum fputype arm_fpu_arch
;
291 /* Which floating point hardware to schedule for. */
292 enum fputype arm_fpu_tune
;
294 /* Whether to use floating point hardware. */
295 enum float_abi_type arm_float_abi
;
297 /* Which ABI to use. */
298 enum arm_abi_type arm_abi
;
300 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
301 enum prog_mode_type arm_prgmode
;
303 /* Set by the -mfpu=... option. */
304 const char * target_fpu_name
= NULL
;
306 /* Set by the -mfpe=... option. */
307 const char * target_fpe_name
= NULL
;
309 /* Set by the -mfloat-abi=... option. */
310 const char * target_float_abi_name
= NULL
;
312 /* Set by the -mabi=... option. */
313 const char * target_abi_name
= NULL
;
315 /* Used to parse -mstructure_size_boundary command line option. */
316 const char * structure_size_string
= NULL
;
317 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
319 /* Bit values used to identify processor capabilities. */
320 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
321 #define FL_ARCH3M (1 << 1) /* Extended multiply */
322 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
323 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
324 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
325 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
326 #define FL_THUMB (1 << 6) /* Thumb aware */
327 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
328 #define FL_STRONG (1 << 8) /* StrongARM */
329 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
330 #define FL_XSCALE (1 << 10) /* XScale */
331 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
332 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
333 media instructions. */
334 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
336 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
338 #define FL_FOR_ARCH2 0
339 #define FL_FOR_ARCH3 FL_MODE32
340 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
341 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
342 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
343 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
344 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
345 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
346 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
347 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
348 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
349 #define FL_FOR_ARCH6J FL_FOR_ARCH6
351 /* The bits in this mask specify which
352 instructions we are allowed to generate. */
353 static unsigned long insn_flags
= 0;
355 /* The bits in this mask specify which instruction scheduling options should
357 static unsigned long tune_flags
= 0;
359 /* The following are used in the arm.md file as equivalents to bits
360 in the above two flag variables. */
362 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
365 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
368 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
371 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
374 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
377 /* Nonzero if this chip can benefit from load scheduling. */
378 int arm_ld_sched
= 0;
380 /* Nonzero if this chip is a StrongARM. */
381 int arm_is_strong
= 0;
383 /* Nonzero if this chip is a Cirrus variant. */
384 int arm_arch_cirrus
= 0;
386 /* Nonzero if this chip supports Intel Wireless MMX technology. */
387 int arm_arch_iwmmxt
= 0;
389 /* Nonzero if this chip is an XScale. */
390 int arm_arch_xscale
= 0;
392 /* Nonzero if tuning for XScale */
393 int arm_tune_xscale
= 0;
395 /* Nonzero if this chip is an ARM6 or an ARM7. */
396 int arm_is_6_or_7
= 0;
398 /* Nonzero if generating Thumb instructions. */
401 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
402 must report the mode of the memory reference from PRINT_OPERAND to
403 PRINT_OPERAND_ADDRESS. */
404 enum machine_mode output_memory_reference_mode
;
406 /* The register number to be used for the PIC offset register. */
407 const char * arm_pic_register_string
= NULL
;
408 int arm_pic_register
= INVALID_REGNUM
;
410 /* Set to 1 when a return insn is output, this means that the epilogue
412 int return_used_this_function
;
414 /* Set to 1 after arm_reorg has started. Reset to start at the start of
415 the next function. */
416 static int after_arm_reorg
= 0;
418 /* The maximum number of insns to be used when loading a constant. */
419 static int arm_constant_limit
= 3;
421 /* For an explanation of these variables, see final_prescan_insn below. */
423 enum arm_cond_code arm_current_cc
;
425 int arm_target_label
;
427 /* The condition codes of the ARM, and the inverse function. */
428 static const char * const arm_condition_codes
[] =
430 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
431 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
434 #define streq(string1, string2) (strcmp (string1, string2) == 0)
436 /* Initialization code. */
440 const char *const name
;
441 enum processor_type core
;
443 const unsigned long flags
;
444 bool (* rtx_costs
) (rtx
, int, int, int *);
447 /* Not all of these give usefully different compilation alternatives,
448 but there is no simple way of generalizing them. */
449 static const struct processors all_cores
[] =
452 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
453 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
454 #include "arm-cores.def"
456 {NULL
, arm_none
, NULL
, 0, NULL
}
459 static const struct processors all_architectures
[] =
461 /* ARM Architectures */
462 /* We don't specify rtx_costs here as it will be figured out
465 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
466 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
467 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
468 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
469 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
470 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
471 implementations that support it, so we will leave it out for now. */
472 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
473 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
474 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
475 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
476 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
477 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
478 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
479 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
480 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
481 {NULL
, arm_none
, NULL
, 0 , NULL
}
484 /* This is a magic structure. The 'string' field is magically filled in
485 with a pointer to the value specified by the user on the command line
486 assuming that the user has specified such a value. */
488 struct arm_cpu_select arm_select
[] =
490 /* string name processors */
491 { NULL
, "-mcpu=", all_cores
},
492 { NULL
, "-march=", all_architectures
},
493 { NULL
, "-mtune=", all_cores
}
497 /* The name of the proprocessor macro to define for this architecture. */
499 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
508 /* Available values for for -mfpu=. */
510 static const struct fpu_desc all_fpus
[] =
512 {"fpa", FPUTYPE_FPA
},
513 {"fpe2", FPUTYPE_FPA_EMU2
},
514 {"fpe3", FPUTYPE_FPA_EMU2
},
515 {"maverick", FPUTYPE_MAVERICK
},
520 /* Floating point models used by the different hardware.
521 See fputype in arm.h. */
523 static const enum fputype fp_model_for_fpu
[] =
525 /* No FP hardware. */
526 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
527 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
528 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
529 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
530 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
531 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
538 enum float_abi_type abi_type
;
542 /* Available values for -mfloat-abi=. */
544 static const struct float_abi all_float_abis
[] =
546 {"soft", ARM_FLOAT_ABI_SOFT
},
547 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
548 {"hard", ARM_FLOAT_ABI_HARD
}
555 enum arm_abi_type abi_type
;
559 /* Available values for -mabi=. */
561 static const struct abi_name arm_all_abis
[] =
563 {"apcs-gnu", ARM_ABI_APCS
},
564 {"atpcs", ARM_ABI_ATPCS
},
565 {"aapcs", ARM_ABI_AAPCS
},
566 {"iwmmxt", ARM_ABI_IWMMXT
}
569 /* Return the number of bits set in VALUE. */
571 bit_count (unsigned long value
)
573 unsigned long count
= 0;
578 value
&= value
- 1; /* Clear the least-significant set bit. */
584 /* Fix up any incompatible options that the user has specified.
585 This has now turned into a maze. */
587 arm_override_options (void)
591 /* Set up the flags based on the cpu/architecture selected by the user. */
592 for (i
= ARRAY_SIZE (arm_select
); i
--;)
594 struct arm_cpu_select
* ptr
= arm_select
+ i
;
596 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
598 const struct processors
* sel
;
600 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
601 if (streq (ptr
->string
, sel
->name
))
603 /* Set the architecture define. */
605 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
607 /* Determine the processor core for which we should
608 tune code-generation. */
609 if (/* -mcpu= is a sensible default. */
611 /* If -march= is used, and -mcpu= has not been used,
612 assume that we should tune for a representative
613 CPU from that architecture. */
615 /* -mtune= overrides -mcpu= and -march=. */
617 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
621 /* If we have been given an architecture and a processor
622 make sure that they are compatible. We only generate
623 a warning though, and we prefer the CPU over the
625 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
626 warning ("switch -mcpu=%s conflicts with -march= switch",
629 insn_flags
= sel
->flags
;
635 if (sel
->name
== NULL
)
636 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
640 /* If the user did not specify a processor, choose one for them. */
643 const struct processors
* sel
;
645 enum processor_type cpu
;
647 cpu
= TARGET_CPU_DEFAULT
;
650 #ifdef SUBTARGET_CPU_DEFAULT
651 /* Use the subtarget default CPU if none was specified by
653 cpu
= SUBTARGET_CPU_DEFAULT
;
655 /* Default to ARM6. */
659 sel
= &all_cores
[cpu
];
661 insn_flags
= sel
->flags
;
663 /* Now check to see if the user has specified some command line
664 switch that require certain abilities from the cpu. */
667 if (TARGET_INTERWORK
|| TARGET_THUMB
)
669 sought
|= (FL_THUMB
| FL_MODE32
);
671 /* Force apcs-32 to be used for interworking. */
672 target_flags
|= ARM_FLAG_APCS_32
;
674 /* There are no ARM processors that support both APCS-26 and
675 interworking. Therefore we force FL_MODE26 to be removed
676 from insn_flags here (if it was set), so that the search
677 below will always be able to find a compatible processor. */
678 insn_flags
&= ~FL_MODE26
;
680 else if (!TARGET_APCS_32
)
683 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
685 /* Try to locate a CPU type that supports all of the abilities
686 of the default CPU, plus the extra abilities requested by
688 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
689 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
692 if (sel
->name
== NULL
)
694 unsigned current_bit_count
= 0;
695 const struct processors
* best_fit
= NULL
;
697 /* Ideally we would like to issue an error message here
698 saying that it was not possible to find a CPU compatible
699 with the default CPU, but which also supports the command
700 line options specified by the programmer, and so they
701 ought to use the -mcpu=<name> command line option to
702 override the default CPU type.
704 Unfortunately this does not work with multilibing. We
705 need to be able to support multilibs for -mapcs-26 and for
706 -mthumb-interwork and there is no CPU that can support both
707 options. Instead if we cannot find a cpu that has both the
708 characteristics of the default cpu and the given command line
709 options we scan the array again looking for a best match. */
710 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
711 if ((sel
->flags
& sought
) == sought
)
715 count
= bit_count (sel
->flags
& insn_flags
);
717 if (count
>= current_bit_count
)
720 current_bit_count
= count
;
724 if (best_fit
== NULL
)
730 insn_flags
= sel
->flags
;
732 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
733 if (arm_tune
== arm_none
)
734 arm_tune
= (enum processor_type
) (sel
- all_cores
);
737 /* The processor for which we should tune should now have been
739 if (arm_tune
== arm_none
)
742 tune_flags
= all_cores
[(int)arm_tune
].flags
;
743 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
745 /* Make sure that the processor choice does not conflict with any of the
746 other command line choices. */
747 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
749 /* If APCS-32 was not the default then it must have been set by the
750 user, so issue a warning message. If the user has specified
751 "-mapcs-32 -mcpu=arm2" then we loose here. */
752 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
753 warning ("target CPU does not support APCS-32" );
754 target_flags
&= ~ARM_FLAG_APCS_32
;
756 else if (!TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
758 warning ("target CPU does not support APCS-26" );
759 target_flags
|= ARM_FLAG_APCS_32
;
762 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
764 warning ("target CPU does not support interworking" );
765 target_flags
&= ~ARM_FLAG_INTERWORK
;
768 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
770 warning ("target CPU does not support THUMB instructions");
771 target_flags
&= ~ARM_FLAG_THUMB
;
774 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
776 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
777 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
780 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
781 from here where no function is being compiled currently. */
782 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
784 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
786 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
787 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
789 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
790 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
792 /* If interworking is enabled then APCS-32 must be selected as well. */
793 if (TARGET_INTERWORK
)
796 warning ("interworking forces APCS-32 to be used" );
797 target_flags
|= ARM_FLAG_APCS_32
;
800 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
802 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
803 target_flags
|= ARM_FLAG_APCS_FRAME
;
806 if (TARGET_POKE_FUNCTION_NAME
)
807 target_flags
|= ARM_FLAG_APCS_FRAME
;
809 if (TARGET_APCS_REENT
&& flag_pic
)
810 error ("-fpic and -mapcs-reent are incompatible");
812 if (TARGET_APCS_REENT
)
813 warning ("APCS reentrant code not supported. Ignored");
815 /* If this target is normally configured to use APCS frames, warn if they
816 are turned off and debugging is turned on. */
818 && write_symbols
!= NO_DEBUG
819 && !TARGET_APCS_FRAME
820 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
821 warning ("-g with -mno-apcs-frame may not give sensible debugging");
823 /* If stack checking is disabled, we can use r10 as the PIC register,
824 which keeps r9 available. */
826 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
828 if (TARGET_APCS_FLOAT
)
829 warning ("passing floating point arguments in fp regs not yet supported");
831 /* Initialize boolean versions of the flags, for use in the arm.md file. */
832 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
833 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
834 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
835 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
836 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
837 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
838 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
840 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
841 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
842 thumb_code
= (TARGET_ARM
== 0);
843 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
844 && !(tune_flags
& FL_ARCH4
))) != 0;
845 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
846 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
850 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
852 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
854 arm_abi
= arm_all_abis
[i
].abi_type
;
858 if (i
== ARRAY_SIZE (arm_all_abis
))
859 error ("invalid ABI option: -mabi=%s", target_abi_name
);
862 arm_abi
= ARM_DEFAULT_ABI
;
864 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
865 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
867 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
868 error ("iwmmxt abi requires an iwmmxt capable cpu");
870 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
871 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
873 if (streq (target_fpe_name
, "2"))
874 target_fpu_name
= "fpe2";
875 else if (streq (target_fpe_name
, "3"))
876 target_fpu_name
= "fpe3";
878 error ("invalid floating point emulation option: -mfpe=%s",
881 if (target_fpu_name
!= NULL
)
883 /* The user specified a FPU. */
884 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
886 if (streq (all_fpus
[i
].name
, target_fpu_name
))
888 arm_fpu_arch
= all_fpus
[i
].fpu
;
889 arm_fpu_tune
= arm_fpu_arch
;
890 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
894 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
895 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
899 #ifdef FPUTYPE_DEFAULT
900 /* Use the default if it is specified for this platform. */
901 arm_fpu_arch
= FPUTYPE_DEFAULT
;
902 arm_fpu_tune
= FPUTYPE_DEFAULT
;
904 /* Pick one based on CPU type. */
905 /* ??? Some targets assume FPA is the default.
906 if ((insn_flags & FL_VFP) != 0)
907 arm_fpu_arch = FPUTYPE_VFP;
911 arm_fpu_arch
= FPUTYPE_MAVERICK
;
913 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
915 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
916 arm_fpu_tune
= FPUTYPE_FPA
;
918 arm_fpu_tune
= arm_fpu_arch
;
919 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
920 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
924 if (target_float_abi_name
!= NULL
)
926 /* The user specified a FP ABI. */
927 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
929 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
931 arm_float_abi
= all_float_abis
[i
].abi_type
;
935 if (i
== ARRAY_SIZE (all_float_abis
))
936 error ("invalid floating point abi: -mfloat-abi=%s",
937 target_float_abi_name
);
941 /* Use soft-float target flag. */
942 if (target_flags
& ARM_FLAG_SOFT_FLOAT
)
943 arm_float_abi
= ARM_FLOAT_ABI_SOFT
;
945 arm_float_abi
= ARM_FLOAT_ABI_HARD
;
948 if (arm_float_abi
== ARM_FLOAT_ABI_SOFTFP
)
949 sorry ("-mfloat-abi=softfp");
950 /* If soft-float is specified then don't use FPU. */
951 if (TARGET_SOFT_FLOAT
)
952 arm_fpu_arch
= FPUTYPE_NONE
;
954 /* For arm2/3 there is no need to do any scheduling if there is only
955 a floating point emulator, or we are doing software floating-point. */
956 if ((TARGET_SOFT_FLOAT
957 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
958 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
959 && (tune_flags
& FL_MODE32
) == 0)
960 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
962 arm_prgmode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
964 /* Override the default structure alignment for AAPCS ABI. */
965 if (arm_abi
== ARM_ABI_AAPCS
)
966 arm_structure_size_boundary
= 8;
968 if (structure_size_string
!= NULL
)
970 int size
= strtol (structure_size_string
, NULL
, 0);
972 if (size
== 8 || size
== 32
973 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
974 arm_structure_size_boundary
= size
;
976 warning ("structure size boundary can only be set to %s",
977 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
980 if (arm_pic_register_string
!= NULL
)
982 int pic_register
= decode_reg_name (arm_pic_register_string
);
985 warning ("-mpic-register= is useless without -fpic");
987 /* Prevent the user from choosing an obviously stupid PIC register. */
988 else if (pic_register
< 0 || call_used_regs
[pic_register
]
989 || pic_register
== HARD_FRAME_POINTER_REGNUM
990 || pic_register
== STACK_POINTER_REGNUM
991 || pic_register
>= PC_REGNUM
)
992 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
994 arm_pic_register
= pic_register
;
997 if (TARGET_THUMB
&& flag_schedule_insns
)
999 /* Don't warn since it's on by default in -O2. */
1000 flag_schedule_insns
= 0;
1005 /* There's some dispute as to whether this should be 1 or 2. However,
1006 experiments seem to show that in pathological cases a setting of
1007 1 degrades less severely than a setting of 2. This could change if
1008 other parts of the compiler change their behavior. */
1009 arm_constant_limit
= 1;
1011 /* If optimizing for size, bump the number of instructions that we
1012 are prepared to conditionally execute (even on a StrongARM). */
1013 max_insns_skipped
= 6;
1017 /* For processors with load scheduling, it never costs more than
1018 2 cycles to load a constant, and the load scheduler may well
1019 reduce that to 1. */
1020 if (tune_flags
& FL_LDSCHED
)
1021 arm_constant_limit
= 1;
1023 /* On XScale the longer latency of a load makes it more difficult
1024 to achieve a good schedule, so it's faster to synthesize
1025 constants that can be done in two insns. */
1026 if (arm_tune_xscale
)
1027 arm_constant_limit
= 2;
1029 /* StrongARM has early execution of branches, so a sequence
1030 that is worth skipping is shorter. */
1032 max_insns_skipped
= 3;
1035 /* Register global variables with the garbage collector. */
1036 arm_add_gc_roots ();
1040 arm_add_gc_roots (void)
1042 gcc_obstack_init(&minipool_obstack
);
1043 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1046 /* A table of known ARM exception types.
1047 For use with the interrupt function attribute. */
1051 const char *const arg
;
1052 const unsigned long return_value
;
1056 static const isr_attribute_arg isr_attribute_args
[] =
1058 { "IRQ", ARM_FT_ISR
},
1059 { "irq", ARM_FT_ISR
},
1060 { "FIQ", ARM_FT_FIQ
},
1061 { "fiq", ARM_FT_FIQ
},
1062 { "ABORT", ARM_FT_ISR
},
1063 { "abort", ARM_FT_ISR
},
1064 { "ABORT", ARM_FT_ISR
},
1065 { "abort", ARM_FT_ISR
},
1066 { "UNDEF", ARM_FT_EXCEPTION
},
1067 { "undef", ARM_FT_EXCEPTION
},
1068 { "SWI", ARM_FT_EXCEPTION
},
1069 { "swi", ARM_FT_EXCEPTION
},
1070 { NULL
, ARM_FT_NORMAL
}
1073 /* Returns the (interrupt) function type of the current
1074 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1076 static unsigned long
1077 arm_isr_value (tree argument
)
1079 const isr_attribute_arg
* ptr
;
1082 /* No argument - default to IRQ. */
1083 if (argument
== NULL_TREE
)
1086 /* Get the value of the argument. */
1087 if (TREE_VALUE (argument
) == NULL_TREE
1088 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1089 return ARM_FT_UNKNOWN
;
1091 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1093 /* Check it against the list of known arguments. */
1094 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1095 if (streq (arg
, ptr
->arg
))
1096 return ptr
->return_value
;
1098 /* An unrecognized interrupt type. */
1099 return ARM_FT_UNKNOWN
;
1102 /* Computes the type of the current function. */
1104 static unsigned long
1105 arm_compute_func_type (void)
1107 unsigned long type
= ARM_FT_UNKNOWN
;
1111 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
1114 /* Decide if the current function is volatile. Such functions
1115 never return, and many memory cycles can be saved by not storing
1116 register values that will never be needed again. This optimization
1117 was added to speed up context switching in a kernel application. */
1119 && current_function_nothrow
1120 && TREE_THIS_VOLATILE (current_function_decl
))
1121 type
|= ARM_FT_VOLATILE
;
1123 if (cfun
->static_chain_decl
!= NULL
)
1124 type
|= ARM_FT_NESTED
;
1126 attr
= DECL_ATTRIBUTES (current_function_decl
);
1128 a
= lookup_attribute ("naked", attr
);
1130 type
|= ARM_FT_NAKED
;
1132 if (cfun
->machine
->eh_epilogue_sp_ofs
!= NULL_RTX
)
1133 type
|= ARM_FT_EXCEPTION_HANDLER
;
1136 a
= lookup_attribute ("isr", attr
);
1138 a
= lookup_attribute ("interrupt", attr
);
1141 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1143 type
|= arm_isr_value (TREE_VALUE (a
));
1149 /* Returns the type of the current function. */
1152 arm_current_func_type (void)
1154 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1155 cfun
->machine
->func_type
= arm_compute_func_type ();
1157 return cfun
->machine
->func_type
;
1160 /* Return 1 if it is possible to return using a single instruction.
1161 If SIBLING is non-null, this is a test for a return before a sibling
1162 call. SIBLING is the call insn, so we can examine its register usage. */
1165 use_return_insn (int iscond
, rtx sibling
)
1168 unsigned int func_type
;
1169 unsigned long saved_int_regs
;
1170 unsigned HOST_WIDE_INT stack_adjust
;
1171 arm_stack_offsets
*offsets
;
1173 /* Never use a return instruction before reload has run. */
1174 if (!reload_completed
)
1177 func_type
= arm_current_func_type ();
1179 /* Naked functions and volatile functions need special
1181 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1184 /* So do interrupt functions that use the frame pointer. */
1185 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1188 offsets
= arm_get_frame_offsets ();
1189 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1191 /* As do variadic functions. */
1192 if (current_function_pretend_args_size
1193 || cfun
->machine
->uses_anonymous_args
1194 /* Or if the function calls __builtin_eh_return () */
1195 || ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
1196 /* Or if the function calls alloca */
1197 || current_function_calls_alloca
1198 /* Or if there is a stack adjustment. However, if the stack pointer
1199 is saved on the stack, we can use a pre-incrementing stack load. */
1200 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1203 saved_int_regs
= arm_compute_save_reg_mask ();
1205 /* Unfortunately, the insn
1207 ldmib sp, {..., sp, ...}
1209 triggers a bug on most SA-110 based devices, such that the stack
1210 pointer won't be correctly restored if the instruction takes a
1211 page fault. We work around this problem by popping r3 along with
1212 the other registers, since that is never slower than executing
1213 another instruction.
1215 We test for !arm_arch5 here, because code for any architecture
1216 less than this could potentially be run on one of the buggy
1218 if (stack_adjust
== 4 && !arm_arch5
)
1220 /* Validate that r3 is a call-clobbered register (always true in
1221 the default abi) ... */
1222 if (!call_used_regs
[3])
1225 /* ... that it isn't being used for a return value (always true
1226 until we implement return-in-regs), or for a tail-call
1230 if (GET_CODE (sibling
) != CALL_INSN
)
1233 if (find_regno_fusage (sibling
, USE
, 3))
1237 /* ... and that there are no call-saved registers in r0-r2
1238 (always true in the default ABI). */
1239 if (saved_int_regs
& 0x7)
1243 /* Can't be done if interworking with Thumb, and any registers have been
1245 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1248 /* On StrongARM, conditional returns are expensive if they aren't
1249 taken and multiple registers have been stacked. */
1250 if (iscond
&& arm_is_strong
)
1252 /* Conditional return when just the LR is stored is a simple
1253 conditional-load instruction, that's not expensive. */
1254 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1257 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1261 /* If there are saved registers but the LR isn't saved, then we need
1262 two instructions for the return. */
1263 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1266 /* Can't be done if any of the FPA regs are pushed,
1267 since this also requires an insn. */
1268 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1269 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1270 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1273 /* Likewise VFP regs. */
1274 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1275 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1276 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1279 if (TARGET_REALLY_IWMMXT
)
1280 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1281 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1287 /* Return TRUE if int I is a valid immediate ARM constant. */
1290 const_ok_for_arm (HOST_WIDE_INT i
)
1292 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
1294 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1295 be all zero, or all one. */
1296 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1297 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1298 != ((~(unsigned HOST_WIDE_INT
) 0)
1299 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1302 /* Fast return for 0 and powers of 2 */
1303 if ((i
& (i
- 1)) == 0)
1308 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
1311 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
1312 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
1314 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
1319 /* Return true if I is a valid constant for the operation CODE. */
1321 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1323 if (const_ok_for_arm (i
))
1329 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1331 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1337 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1344 /* Emit a sequence of insns to handle a large constant.
1345 CODE is the code of the operation required, it can be any of SET, PLUS,
1346 IOR, AND, XOR, MINUS;
1347 MODE is the mode in which the operation is being performed;
1348 VAL is the integer to operate on;
1349 SOURCE is the other operand (a register, or a null-pointer for SET);
1350 SUBTARGETS means it is safe to create scratch registers if that will
1351 either produce a simpler sequence, or we will want to cse the values.
1352 Return value is the number of insns emitted. */
1355 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1356 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1360 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1361 cond
= COND_EXEC_TEST (PATTERN (insn
));
1365 if (subtargets
|| code
== SET
1366 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1367 && REGNO (target
) != REGNO (source
)))
1369 /* After arm_reorg has been called, we can't fix up expensive
1370 constants by pushing them into memory so we must synthesize
1371 them in-line, regardless of the cost. This is only likely to
1372 be more costly on chips that have load delay slots and we are
1373 compiling without running the scheduler (so no splitting
1374 occurred before the final instruction emission).
1376 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1378 if (!after_arm_reorg
1380 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1382 > arm_constant_limit
+ (code
!= SET
)))
1386 /* Currently SET is the only monadic value for CODE, all
1387 the rest are diadic. */
1388 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1393 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1395 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1396 /* For MINUS, the value is subtracted from, since we never
1397 have subtraction of a constant. */
1399 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1400 gen_rtx_MINUS (mode
, temp
, source
)));
1402 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1403 gen_rtx_fmt_ee (code
, mode
, source
, temp
)));
1409 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1414 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1416 HOST_WIDE_INT temp1
;
1424 if (remainder
& (3 << (i
- 2)))
1429 temp1
= remainder
& ((0x0ff << end
)
1430 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1431 remainder
&= ~temp1
;
1436 } while (remainder
);
1440 /* Emit an instruction with the indicated PATTERN. If COND is
1441 non-NULL, conditionalize the execution of the instruction on COND
1445 emit_constant_insn (rtx cond
, rtx pattern
)
1448 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1449 emit_insn (pattern
);
1452 /* As above, but extra parameter GENERATE which, if clear, suppresses
1456 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1457 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1462 int can_negate_initial
= 0;
1465 int num_bits_set
= 0;
1466 int set_sign_bit_copies
= 0;
1467 int clear_sign_bit_copies
= 0;
1468 int clear_zero_bit_copies
= 0;
1469 int set_zero_bit_copies
= 0;
1471 unsigned HOST_WIDE_INT temp1
, temp2
;
1472 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1474 /* Find out which operations are safe for a given CODE. Also do a quick
1475 check for degenerate cases; these can occur when DImode operations
1487 can_negate_initial
= 1;
1491 if (remainder
== 0xffffffff)
1494 emit_constant_insn (cond
,
1495 gen_rtx_SET (VOIDmode
, target
,
1496 GEN_INT (ARM_SIGN_EXTEND (val
))));
1501 if (reload_completed
&& rtx_equal_p (target
, source
))
1504 emit_constant_insn (cond
,
1505 gen_rtx_SET (VOIDmode
, target
, source
));
1514 emit_constant_insn (cond
,
1515 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1518 if (remainder
== 0xffffffff)
1520 if (reload_completed
&& rtx_equal_p (target
, source
))
1523 emit_constant_insn (cond
,
1524 gen_rtx_SET (VOIDmode
, target
, source
));
1533 if (reload_completed
&& rtx_equal_p (target
, source
))
1536 emit_constant_insn (cond
,
1537 gen_rtx_SET (VOIDmode
, target
, source
));
1540 if (remainder
== 0xffffffff)
1543 emit_constant_insn (cond
,
1544 gen_rtx_SET (VOIDmode
, target
,
1545 gen_rtx_NOT (mode
, source
)));
1549 /* We don't know how to handle this yet below. */
1553 /* We treat MINUS as (val - source), since (source - val) is always
1554 passed as (source + (-val)). */
1558 emit_constant_insn (cond
,
1559 gen_rtx_SET (VOIDmode
, target
,
1560 gen_rtx_NEG (mode
, source
)));
1563 if (const_ok_for_arm (val
))
1566 emit_constant_insn (cond
,
1567 gen_rtx_SET (VOIDmode
, target
,
1568 gen_rtx_MINUS (mode
, GEN_INT (val
),
1580 /* If we can do it in one insn get out quickly. */
1581 if (const_ok_for_arm (val
)
1582 || (can_negate_initial
&& const_ok_for_arm (-val
))
1583 || (can_invert
&& const_ok_for_arm (~val
)))
1586 emit_constant_insn (cond
,
1587 gen_rtx_SET (VOIDmode
, target
,
1589 ? gen_rtx_fmt_ee (code
, mode
, source
,
1595 /* Calculate a few attributes that may be useful for specific
1597 for (i
= 31; i
>= 0; i
--)
1599 if ((remainder
& (1 << i
)) == 0)
1600 clear_sign_bit_copies
++;
1605 for (i
= 31; i
>= 0; i
--)
1607 if ((remainder
& (1 << i
)) != 0)
1608 set_sign_bit_copies
++;
1613 for (i
= 0; i
<= 31; i
++)
1615 if ((remainder
& (1 << i
)) == 0)
1616 clear_zero_bit_copies
++;
1621 for (i
= 0; i
<= 31; i
++)
1623 if ((remainder
& (1 << i
)) != 0)
1624 set_zero_bit_copies
++;
1632 /* See if we can do this by sign_extending a constant that is known
1633 to be negative. This is a good, way of doing it, since the shift
1634 may well merge into a subsequent insn. */
1635 if (set_sign_bit_copies
> 1)
1637 if (const_ok_for_arm
1638 (temp1
= ARM_SIGN_EXTEND (remainder
1639 << (set_sign_bit_copies
- 1))))
1643 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1644 emit_constant_insn (cond
,
1645 gen_rtx_SET (VOIDmode
, new_src
,
1647 emit_constant_insn (cond
,
1648 gen_ashrsi3 (target
, new_src
,
1649 GEN_INT (set_sign_bit_copies
- 1)));
1653 /* For an inverted constant, we will need to set the low bits,
1654 these will be shifted out of harm's way. */
1655 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1656 if (const_ok_for_arm (~temp1
))
1660 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1661 emit_constant_insn (cond
,
1662 gen_rtx_SET (VOIDmode
, new_src
,
1664 emit_constant_insn (cond
,
1665 gen_ashrsi3 (target
, new_src
,
1666 GEN_INT (set_sign_bit_copies
- 1)));
1672 /* See if we can generate this by setting the bottom (or the top)
1673 16 bits, and then shifting these into the other half of the
1674 word. We only look for the simplest cases, to do more would cost
1675 too much. Be careful, however, not to generate this when the
1676 alternative would take fewer insns. */
1677 if (val
& 0xffff0000)
1679 temp1
= remainder
& 0xffff0000;
1680 temp2
= remainder
& 0x0000ffff;
1682 /* Overlaps outside this range are best done using other methods. */
1683 for (i
= 9; i
< 24; i
++)
1685 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1686 && !const_ok_for_arm (temp2
))
1688 rtx new_src
= (subtargets
1689 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1691 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
1692 source
, subtargets
, generate
);
1700 gen_rtx_ASHIFT (mode
, source
,
1707 /* Don't duplicate cases already considered. */
1708 for (i
= 17; i
< 24; i
++)
1710 if (((temp1
| (temp1
>> i
)) == remainder
)
1711 && !const_ok_for_arm (temp1
))
1713 rtx new_src
= (subtargets
1714 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1716 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
1717 source
, subtargets
, generate
);
1722 gen_rtx_SET (VOIDmode
, target
,
1725 gen_rtx_LSHIFTRT (mode
, source
,
1736 /* If we have IOR or XOR, and the constant can be loaded in a
1737 single instruction, and we can find a temporary to put it in,
1738 then this can be done in two instructions instead of 3-4. */
1740 /* TARGET can't be NULL if SUBTARGETS is 0 */
1741 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1743 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1747 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1749 emit_constant_insn (cond
,
1750 gen_rtx_SET (VOIDmode
, sub
,
1752 emit_constant_insn (cond
,
1753 gen_rtx_SET (VOIDmode
, target
,
1754 gen_rtx_fmt_ee (code
, mode
,
1764 if (set_sign_bit_copies
> 8
1765 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1769 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1770 rtx shift
= GEN_INT (set_sign_bit_copies
);
1774 gen_rtx_SET (VOIDmode
, sub
,
1776 gen_rtx_ASHIFT (mode
,
1781 gen_rtx_SET (VOIDmode
, target
,
1783 gen_rtx_LSHIFTRT (mode
, sub
,
1789 if (set_zero_bit_copies
> 8
1790 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1794 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1795 rtx shift
= GEN_INT (set_zero_bit_copies
);
1799 gen_rtx_SET (VOIDmode
, sub
,
1801 gen_rtx_LSHIFTRT (mode
,
1806 gen_rtx_SET (VOIDmode
, target
,
1808 gen_rtx_ASHIFT (mode
, sub
,
1814 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1818 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1819 emit_constant_insn (cond
,
1820 gen_rtx_SET (VOIDmode
, sub
,
1821 gen_rtx_NOT (mode
, source
)));
1824 sub
= gen_reg_rtx (mode
);
1825 emit_constant_insn (cond
,
1826 gen_rtx_SET (VOIDmode
, sub
,
1827 gen_rtx_AND (mode
, source
,
1829 emit_constant_insn (cond
,
1830 gen_rtx_SET (VOIDmode
, target
,
1831 gen_rtx_NOT (mode
, sub
)));
1838 /* See if two shifts will do 2 or more insn's worth of work. */
1839 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1841 HOST_WIDE_INT shift_mask
= ((0xffffffff
1842 << (32 - clear_sign_bit_copies
))
1845 if ((remainder
| shift_mask
) != 0xffffffff)
1849 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1850 insns
= arm_gen_constant (AND
, mode
, cond
,
1851 remainder
| shift_mask
,
1852 new_src
, source
, subtargets
, 1);
1857 rtx targ
= subtargets
? NULL_RTX
: target
;
1858 insns
= arm_gen_constant (AND
, mode
, cond
,
1859 remainder
| shift_mask
,
1860 targ
, source
, subtargets
, 0);
1866 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1867 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1869 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1870 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1876 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1878 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1880 if ((remainder
| shift_mask
) != 0xffffffff)
1884 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1886 insns
= arm_gen_constant (AND
, mode
, cond
,
1887 remainder
| shift_mask
,
1888 new_src
, source
, subtargets
, 1);
1893 rtx targ
= subtargets
? NULL_RTX
: target
;
1895 insns
= arm_gen_constant (AND
, mode
, cond
,
1896 remainder
| shift_mask
,
1897 targ
, source
, subtargets
, 0);
1903 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1904 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1906 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1907 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1919 for (i
= 0; i
< 32; i
++)
1920 if (remainder
& (1 << i
))
1923 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1924 remainder
= (~remainder
) & 0xffffffff;
1925 else if (code
== PLUS
&& num_bits_set
> 16)
1926 remainder
= (-remainder
) & 0xffffffff;
1933 /* Now try and find a way of doing the job in either two or three
1935 We start by looking for the largest block of zeros that are aligned on
1936 a 2-bit boundary, we then fill up the temps, wrapping around to the
1937 top of the word when we drop off the bottom.
1938 In the worst case this code should produce no more than four insns. */
1941 int best_consecutive_zeros
= 0;
1943 for (i
= 0; i
< 32; i
+= 2)
1945 int consecutive_zeros
= 0;
1947 if (!(remainder
& (3 << i
)))
1949 while ((i
< 32) && !(remainder
& (3 << i
)))
1951 consecutive_zeros
+= 2;
1954 if (consecutive_zeros
> best_consecutive_zeros
)
1956 best_consecutive_zeros
= consecutive_zeros
;
1957 best_start
= i
- consecutive_zeros
;
1963 /* So long as it won't require any more insns to do so, it's
1964 desirable to emit a small constant (in bits 0...9) in the last
1965 insn. This way there is more chance that it can be combined with
1966 a later addressing insn to form a pre-indexed load or store
1967 operation. Consider:
1969 *((volatile int *)0xe0000100) = 1;
1970 *((volatile int *)0xe0000110) = 2;
1972 We want this to wind up as:
1976 str rB, [rA, #0x100]
1978 str rB, [rA, #0x110]
1980 rather than having to synthesize both large constants from scratch.
1982 Therefore, we calculate how many insns would be required to emit
1983 the constant starting from `best_start', and also starting from
1984 zero (ie with bit 31 first to be output). If `best_start' doesn't
1985 yield a shorter sequence, we may as well use zero. */
1987 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
1988 && (count_insns_for_constant (remainder
, 0) <=
1989 count_insns_for_constant (remainder
, best_start
)))
1992 /* Now start emitting the insns. */
2000 if (remainder
& (3 << (i
- 2)))
2005 temp1
= remainder
& ((0x0ff << end
)
2006 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2007 remainder
&= ~temp1
;
2011 rtx new_src
, temp1_rtx
;
2013 if (code
== SET
|| code
== MINUS
)
2015 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2016 if (can_invert
&& code
!= MINUS
)
2021 if (remainder
&& subtargets
)
2022 new_src
= gen_reg_rtx (mode
);
2027 else if (can_negate
)
2031 temp1
= trunc_int_for_mode (temp1
, mode
);
2032 temp1_rtx
= GEN_INT (temp1
);
2036 else if (code
== MINUS
)
2037 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2039 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2041 emit_constant_insn (cond
,
2042 gen_rtx_SET (VOIDmode
, new_src
,
2052 else if (code
== MINUS
)
2066 /* Canonicalize a comparison so that we are more likely to recognize it.
2067 This can be done for a few constant compares, where we can make the
2068 immediate value easier to load. */
2071 arm_canonicalize_comparison (enum rtx_code code
, rtx
* op1
)
2073 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2083 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
2084 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2086 *op1
= GEN_INT (i
+ 1);
2087 return code
== GT
? GE
: LT
;
2093 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
2094 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2096 *op1
= GEN_INT (i
- 1);
2097 return code
== GE
? GT
: LE
;
2103 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2104 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2106 *op1
= GEN_INT (i
+ 1);
2107 return code
== GTU
? GEU
: LTU
;
2114 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2116 *op1
= GEN_INT (i
- 1);
2117 return code
== GEU
? GTU
: LEU
;
2129 /* Define how to find the value returned by a function. */
2131 rtx
arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2133 enum machine_mode mode
;
2134 int unsignedp ATTRIBUTE_UNUSED
;
2135 rtx r ATTRIBUTE_UNUSED
;
2138 mode
= TYPE_MODE (type
);
2139 /* Promote integer types. */
2140 if (INTEGRAL_TYPE_P (type
))
2141 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2142 return LIBCALL_VALUE(mode
);
2146 /* Decide whether a type should be returned in memory (true)
2147 or in a register (false). This is called by the macro
2148 RETURN_IN_MEMORY. */
2150 arm_return_in_memory (tree type
)
2154 if (!AGGREGATE_TYPE_P (type
))
2155 /* All simple types are returned in registers. */
2158 size
= int_size_in_bytes (type
);
2160 if (arm_abi
!= ARM_ABI_APCS
)
2162 /* ATPCS and later return aggregate types in memory only if they are
2163 larger than a word (or are variable size). */
2164 return (size
< 0 || size
> UNITS_PER_WORD
);
2167 /* For the arm-wince targets we choose to be compatible with Microsoft's
2168 ARM and Thumb compilers, which always return aggregates in memory. */
2170 /* All structures/unions bigger than one word are returned in memory.
2171 Also catch the case where int_size_in_bytes returns -1. In this case
2172 the aggregate is either huge or of variable size, and in either case
2173 we will want to return it via memory and not in a register. */
2174 if (size
< 0 || size
> UNITS_PER_WORD
)
2177 if (TREE_CODE (type
) == RECORD_TYPE
)
2181 /* For a struct the APCS says that we only return in a register
2182 if the type is 'integer like' and every addressable element
2183 has an offset of zero. For practical purposes this means
2184 that the structure can have at most one non bit-field element
2185 and that this element must be the first one in the structure. */
2187 /* Find the first field, ignoring non FIELD_DECL things which will
2188 have been created by C++. */
2189 for (field
= TYPE_FIELDS (type
);
2190 field
&& TREE_CODE (field
) != FIELD_DECL
;
2191 field
= TREE_CHAIN (field
))
2195 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2197 /* Check that the first field is valid for returning in a register. */
2199 /* ... Floats are not allowed */
2200 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2203 /* ... Aggregates that are not themselves valid for returning in
2204 a register are not allowed. */
2205 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2208 /* Now check the remaining fields, if any. Only bitfields are allowed,
2209 since they are not addressable. */
2210 for (field
= TREE_CHAIN (field
);
2212 field
= TREE_CHAIN (field
))
2214 if (TREE_CODE (field
) != FIELD_DECL
)
2217 if (!DECL_BIT_FIELD_TYPE (field
))
2224 if (TREE_CODE (type
) == UNION_TYPE
)
2228 /* Unions can be returned in registers if every element is
2229 integral, or can be returned in an integer register. */
2230 for (field
= TYPE_FIELDS (type
);
2232 field
= TREE_CHAIN (field
))
2234 if (TREE_CODE (field
) != FIELD_DECL
)
2237 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2240 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2246 #endif /* not ARM_WINCE */
2248 /* Return all other types in memory. */
2252 /* Indicate whether or not words of a double are in big-endian order. */
2255 arm_float_words_big_endian (void)
2257 if (TARGET_MAVERICK
)
2260 /* For FPA, float words are always big-endian. For VFP, floats words
2261 follow the memory system mode. */
2269 return (TARGET_BIG_END
? 1 : 0);
2274 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2275 for a call to a function whose data type is FNTYPE.
2276 For a library call, FNTYPE is NULL. */
2278 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2279 rtx libname ATTRIBUTE_UNUSED
,
2280 tree fndecl ATTRIBUTE_UNUSED
)
2282 /* On the ARM, the offset starts at 0. */
2283 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2284 pcum
->iwmmxt_nregs
= 0;
2285 pcum
->can_split
= true;
2287 pcum
->call_cookie
= CALL_NORMAL
;
2289 if (TARGET_LONG_CALLS
)
2290 pcum
->call_cookie
= CALL_LONG
;
2292 /* Check for long call/short call attributes. The attributes
2293 override any command line option. */
2296 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2297 pcum
->call_cookie
= CALL_SHORT
;
2298 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2299 pcum
->call_cookie
= CALL_LONG
;
2302 /* Varargs vectors are treated the same as long long.
2303 named_count avoids having to change the way arm handles 'named' */
2304 pcum
->named_count
= 0;
2307 if (TARGET_REALLY_IWMMXT
&& fntype
)
2311 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2313 fn_arg
= TREE_CHAIN (fn_arg
))
2314 pcum
->named_count
+= 1;
2316 if (! pcum
->named_count
)
2317 pcum
->named_count
= INT_MAX
;
2322 /* Return true if mode/type need doubleword alignment. */
2324 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2326 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2327 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2331 /* Determine where to put an argument to a function.
2332 Value is zero to push the argument on the stack,
2333 or a hard register in which to store the argument.
2335 MODE is the argument's machine mode.
2336 TYPE is the data type of the argument (as a tree).
2337 This is null for libcalls where that information may
2339 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2340 the preceding args and about the function being called.
2341 NAMED is nonzero if this argument is a named parameter
2342 (otherwise it is an extra parameter matching an ellipsis). */
2345 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2346 tree type
, int named
)
2350 /* Varargs vectors are treated the same as long long.
2351 named_count avoids having to change the way arm handles 'named' */
2352 if (TARGET_IWMMXT_ABI
2353 && VECTOR_MODE_SUPPORTED_P (mode
)
2354 && pcum
->named_count
> pcum
->nargs
+ 1)
2356 if (pcum
->iwmmxt_nregs
<= 9)
2357 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2360 pcum
->can_split
= false;
2365 /* Put doubleword aligned quantities in even register pairs. */
2367 && ARM_DOUBLEWORD_ALIGN
2368 && arm_needs_doubleword_align (mode
, type
))
2371 if (mode
== VOIDmode
)
2372 /* Compute operand 2 of the call insn. */
2373 return GEN_INT (pcum
->call_cookie
);
2375 /* Only allow splitting an arg between regs and memory if all preceding
2376 args were allocated to regs. For args passed by reference we only count
2377 the reference pointer. */
2378 if (pcum
->can_split
)
2381 nregs
= ARM_NUM_REGS2 (mode
, type
);
2383 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2386 return gen_rtx_REG (mode
, pcum
->nregs
);
2389 /* Variable sized types are passed by reference. This is a GCC
2390 extension to the ARM ABI. */
2393 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2394 enum machine_mode mode ATTRIBUTE_UNUSED
,
2395 tree type
, int named ATTRIBUTE_UNUSED
)
2397 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2400 /* Implement va_arg. */
2403 arm_va_arg (tree valist
, tree type
)
2407 /* Variable sized types are passed by reference. */
2408 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
2410 rtx addr
= std_expand_builtin_va_arg (valist
, build_pointer_type (type
));
2411 return gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, addr
));
2414 align
= FUNCTION_ARG_BOUNDARY (TYPE_MODE (type
), type
);
2415 if (align
> PARM_BOUNDARY
)
2420 /* Maintain 64-bit alignment of the valist pointer by
2421 constructing: valist = ((valist + (8 - 1)) & -8). */
2422 mask
= build_int_2 (- (align
/ BITS_PER_UNIT
), -1);
2423 t
= build_int_2 ((align
/ BITS_PER_UNIT
) - 1, 0);
2424 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
, t
);
2425 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, mask
);
2426 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
2427 TREE_SIDE_EFFECTS (t
) = 1;
2428 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2430 /* This is to stop the combine pass optimizing
2431 away the alignment adjustment. */
2432 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
2435 return std_expand_builtin_va_arg (valist
, type
);
2438 /* Encode the current state of the #pragma [no_]long_calls. */
2441 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2442 LONG
, /* #pragma long_calls is in effect. */
2443 SHORT
/* #pragma no_long_calls is in effect. */
2446 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2449 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2451 arm_pragma_long_calls
= LONG
;
2455 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2457 arm_pragma_long_calls
= SHORT
;
2461 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2463 arm_pragma_long_calls
= OFF
;
2466 /* Table of machine attributes. */
2467 const struct attribute_spec arm_attribute_table
[] =
2469 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2470 /* Function calls made to this symbol must be done indirectly, because
2471 it may lie outside of the 26 bit addressing range of a normal function
2473 { "long_call", 0, 0, false, true, true, NULL
},
2474 /* Whereas these functions are always known to reside within the 26 bit
2475 addressing range. */
2476 { "short_call", 0, 0, false, true, true, NULL
},
2477 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2478 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2479 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2480 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2482 /* ARM/PE has three new attributes:
2484 dllexport - for exporting a function/variable that will live in a dll
2485 dllimport - for importing a function/variable from a dll
2487 Microsoft allows multiple declspecs in one __declspec, separating
2488 them with spaces. We do NOT support this. Instead, use __declspec
2491 { "dllimport", 0, 0, true, false, false, NULL
},
2492 { "dllexport", 0, 0, true, false, false, NULL
},
2493 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2495 { NULL
, 0, 0, false, false, false, NULL
}
2498 /* Handle an attribute requiring a FUNCTION_DECL;
2499 arguments as in struct attribute_spec.handler. */
2501 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2502 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2504 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2506 warning ("`%s' attribute only applies to functions",
2507 IDENTIFIER_POINTER (name
));
2508 *no_add_attrs
= true;
2514 /* Handle an "interrupt" or "isr" attribute;
2515 arguments as in struct attribute_spec.handler. */
2517 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2522 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2524 warning ("`%s' attribute only applies to functions",
2525 IDENTIFIER_POINTER (name
));
2526 *no_add_attrs
= true;
2528 /* FIXME: the argument if any is checked for type attributes;
2529 should it be checked for decl ones? */
2533 if (TREE_CODE (*node
) == FUNCTION_TYPE
2534 || TREE_CODE (*node
) == METHOD_TYPE
)
2536 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2538 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2539 *no_add_attrs
= true;
2542 else if (TREE_CODE (*node
) == POINTER_TYPE
2543 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2544 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2545 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2547 *node
= build_type_copy (*node
);
2548 TREE_TYPE (*node
) = build_type_attribute_variant
2550 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2551 *no_add_attrs
= true;
2555 /* Possibly pass this attribute on from the type to a decl. */
2556 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2557 | (int) ATTR_FLAG_FUNCTION_NEXT
2558 | (int) ATTR_FLAG_ARRAY_NEXT
))
2560 *no_add_attrs
= true;
2561 return tree_cons (name
, args
, NULL_TREE
);
2565 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2573 /* Return 0 if the attributes for two types are incompatible, 1 if they
2574 are compatible, and 2 if they are nearly compatible (which causes a
2575 warning to be generated). */
2577 arm_comp_type_attributes (tree type1
, tree type2
)
2581 /* Check for mismatch of non-default calling convention. */
2582 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2585 /* Check for mismatched call attributes. */
2586 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2587 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2588 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2589 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2591 /* Only bother to check if an attribute is defined. */
2592 if (l1
| l2
| s1
| s2
)
2594 /* If one type has an attribute, the other must have the same attribute. */
2595 if ((l1
!= l2
) || (s1
!= s2
))
2598 /* Disallow mixed attributes. */
2599 if ((l1
& s2
) || (l2
& s1
))
2603 /* Check for mismatched ISR attribute. */
2604 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2606 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2607 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2609 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2616 /* Encode long_call or short_call attribute by prefixing
2617 symbol name in DECL with a special character FLAG. */
2619 arm_encode_call_attribute (tree decl
, int flag
)
2621 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2622 int len
= strlen (str
);
2625 /* Do not allow weak functions to be treated as short call. */
2626 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2629 newstr
= alloca (len
+ 2);
2631 strcpy (newstr
+ 1, str
);
2633 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2634 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2637 /* Assigns default attributes to newly defined type. This is used to
2638 set short_call/long_call attributes for function types of
2639 functions defined inside corresponding #pragma scopes. */
2641 arm_set_default_type_attributes (tree type
)
2643 /* Add __attribute__ ((long_call)) to all functions, when
2644 inside #pragma long_calls or __attribute__ ((short_call)),
2645 when inside #pragma no_long_calls. */
2646 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2648 tree type_attr_list
, attr_name
;
2649 type_attr_list
= TYPE_ATTRIBUTES (type
);
2651 if (arm_pragma_long_calls
== LONG
)
2652 attr_name
= get_identifier ("long_call");
2653 else if (arm_pragma_long_calls
== SHORT
)
2654 attr_name
= get_identifier ("short_call");
2658 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2659 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2663 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2664 defined within the current compilation unit. If this cannot be
2665 determined, then 0 is returned. */
2667 current_file_function_operand (rtx sym_ref
)
2669 /* This is a bit of a fib. A function will have a short call flag
2670 applied to its name if it has the short call attribute, or it has
2671 already been defined within the current compilation unit. */
2672 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2675 /* The current function is always defined within the current compilation
2676 unit. if it s a weak definition however, then this may not be the real
2677 definition of the function, and so we have to say no. */
2678 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2679 && !DECL_WEAK (current_function_decl
))
2682 /* We cannot make the determination - default to returning 0. */
2686 /* Return nonzero if a 32 bit "long_call" should be generated for
2687 this call. We generate a long_call if the function:
2689 a. has an __attribute__((long call))
2690 or b. is within the scope of a #pragma long_calls
2691 or c. the -mlong-calls command line switch has been specified
2693 However we do not generate a long call if the function:
2695 d. has an __attribute__ ((short_call))
2696 or e. is inside the scope of a #pragma no_long_calls
2697 or f. has an __attribute__ ((section))
2698 or g. is defined within the current compilation unit.
2700 This function will be called by C fragments contained in the machine
2701 description file. CALL_REF and CALL_COOKIE correspond to the matched
2702 rtl operands. CALL_SYMBOL is used to distinguish between
2703 two different callers of the function. It is set to 1 in the
2704 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2705 and "call_value" patterns. This is because of the difference in the
2706 SYM_REFs passed by these patterns. */
2708 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
2712 if (GET_CODE (sym_ref
) != MEM
)
2715 sym_ref
= XEXP (sym_ref
, 0);
2718 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2721 if (call_cookie
& CALL_SHORT
)
2724 if (TARGET_LONG_CALLS
&& flag_function_sections
)
2727 if (current_file_function_operand (sym_ref
))
2730 return (call_cookie
& CALL_LONG
)
2731 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2732 || TARGET_LONG_CALLS
;
2735 /* Return nonzero if it is ok to make a tail-call to DECL. */
2737 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
2739 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2741 if (cfun
->machine
->sibcall_blocked
)
2744 /* Never tailcall something for which we have no decl, or if we
2745 are in Thumb mode. */
2746 if (decl
== NULL
|| TARGET_THUMB
)
2749 /* Get the calling method. */
2750 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2751 call_type
= CALL_SHORT
;
2752 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2753 call_type
= CALL_LONG
;
2755 /* Cannot tail-call to long calls, since these are out of range of
2756 a branch instruction. However, if not compiling PIC, we know
2757 we can reach the symbol if it is in this compilation unit. */
2758 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2761 /* If we are interworking and the function is not declared static
2762 then we can't tail-call it unless we know that it exists in this
2763 compilation unit (since it might be a Thumb routine). */
2764 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2767 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2768 if (IS_INTERRUPT (arm_current_func_type ()))
2771 /* Everything else is ok. */
2776 /* Addressing mode support functions. */
2778 /* Return nonzero if X is a legitimate immediate operand when compiling
2781 legitimate_pic_operand_p (rtx x
)
2785 && (GET_CODE (x
) == SYMBOL_REF
2786 || (GET_CODE (x
) == CONST
2787 && GET_CODE (XEXP (x
, 0)) == PLUS
2788 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2795 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
2797 if (GET_CODE (orig
) == SYMBOL_REF
2798 || GET_CODE (orig
) == LABEL_REF
)
2800 #ifndef AOF_ASSEMBLER
2801 rtx pic_ref
, address
;
2811 reg
= gen_reg_rtx (Pmode
);
2816 #ifdef AOF_ASSEMBLER
2817 /* The AOF assembler can generate relocations for these directly, and
2818 understands that the PIC register has to be added into the offset. */
2819 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2822 address
= gen_reg_rtx (Pmode
);
2827 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2829 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2831 if ((GET_CODE (orig
) == LABEL_REF
2832 || (GET_CODE (orig
) == SYMBOL_REF
&&
2833 SYMBOL_REF_LOCAL_P (orig
)))
2835 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2838 pic_ref
= gen_rtx_MEM (Pmode
,
2839 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2841 RTX_UNCHANGING_P (pic_ref
) = 1;
2844 insn
= emit_move_insn (reg
, pic_ref
);
2846 current_function_uses_pic_offset_table
= 1;
2847 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2849 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2853 else if (GET_CODE (orig
) == CONST
)
2857 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2858 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2866 reg
= gen_reg_rtx (Pmode
);
2869 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2871 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2872 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2873 base
== reg
? 0 : reg
);
2878 if (GET_CODE (offset
) == CONST_INT
)
2880 /* The base register doesn't really matter, we only want to
2881 test the index for the appropriate mode. */
2882 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
2884 if (!no_new_pseudos
)
2885 offset
= force_reg (Pmode
, offset
);
2890 if (GET_CODE (offset
) == CONST_INT
)
2891 return plus_constant (base
, INTVAL (offset
));
2894 if (GET_MODE_SIZE (mode
) > 4
2895 && (GET_MODE_CLASS (mode
) == MODE_INT
2896 || TARGET_SOFT_FLOAT
))
2898 emit_insn (gen_addsi3 (reg
, base
, offset
));
2902 return gen_rtx_PLUS (Pmode
, base
, offset
);
2908 /* Generate code to load the PIC register. PROLOGUE is true if
2909 called from arm_expand_prologue (in which case we want the
2910 generated insns at the start of the function); false if called
2911 by an exception receiver that needs the PIC register reloaded
2912 (in which case the insns are just dumped at the current location). */
2914 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED
)
2916 #ifndef AOF_ASSEMBLER
2917 rtx l1
, pic_tmp
, pic_tmp2
, seq
, pic_rtx
;
2918 rtx global_offset_table
;
2920 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
2927 l1
= gen_label_rtx ();
2929 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2930 /* On the ARM the PC register contains 'dot + 8' at the time of the
2931 addition, on the Thumb it is 'dot + 4'. */
2932 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
2934 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
2935 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
2937 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
2939 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
2943 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
2944 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
2948 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
2949 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
2955 emit_insn_after (seq
, get_insns ());
2959 /* Need to emit this whether or not we obey regdecls,
2960 since setjmp/longjmp can cause life info to screw up. */
2961 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2962 #endif /* AOF_ASSEMBLER */
2965 /* Return nonzero if X is valid as an ARM state addressing register. */
2967 arm_address_register_rtx_p (rtx x
, int strict_p
)
2971 if (GET_CODE (x
) != REG
)
2977 return ARM_REGNO_OK_FOR_BASE_P (regno
);
2979 return (regno
<= LAST_ARM_REGNUM
2980 || regno
>= FIRST_PSEUDO_REGISTER
2981 || regno
== FRAME_POINTER_REGNUM
2982 || regno
== ARG_POINTER_REGNUM
);
2985 /* Return nonzero if X is a valid ARM state address operand. */
2987 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
2991 enum rtx_code code
= GET_CODE (x
);
2993 if (arm_address_register_rtx_p (x
, strict_p
))
2996 use_ldrd
= (TARGET_LDRD
2998 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3000 if (code
== POST_INC
|| code
== PRE_DEC
3001 || ((code
== PRE_INC
|| code
== POST_DEC
)
3002 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3003 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3005 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3006 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3007 && GET_CODE (XEXP (x
, 1)) == PLUS
3008 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3010 rtx addend
= XEXP (XEXP (x
, 1), 1);
3012 /* Don't allow ldrd post increment by register becuase it's hard
3013 to fixup invalid register choices. */
3015 && GET_CODE (x
) == POST_MODIFY
3016 && GET_CODE (addend
) == REG
)
3019 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3020 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3023 /* After reload constants split into minipools will have addresses
3024 from a LABEL_REF. */
3025 else if (reload_completed
3026 && (code
== LABEL_REF
3028 && GET_CODE (XEXP (x
, 0)) == PLUS
3029 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3030 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3033 else if (mode
== TImode
)
3036 else if (code
== PLUS
)
3038 rtx xop0
= XEXP (x
, 0);
3039 rtx xop1
= XEXP (x
, 1);
3041 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3042 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3043 || (arm_address_register_rtx_p (xop1
, strict_p
)
3044 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3048 /* Reload currently can't handle MINUS, so disable this for now */
3049 else if (GET_CODE (x
) == MINUS
)
3051 rtx xop0
= XEXP (x
, 0);
3052 rtx xop1
= XEXP (x
, 1);
3054 return (arm_address_register_rtx_p (xop0
, strict_p
)
3055 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3059 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3060 && code
== SYMBOL_REF
3061 && CONSTANT_POOL_ADDRESS_P (x
)
3063 && symbol_mentioned_p (get_pool_constant (x
))))
3069 /* Return nonzero if INDEX is valid for an address index operand in
3072 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3075 HOST_WIDE_INT range
;
3076 enum rtx_code code
= GET_CODE (index
);
3078 /* Standard coprocessor addressing modes. */
3079 if (TARGET_HARD_FLOAT
3080 && (TARGET_FPA
|| TARGET_MAVERICK
)
3081 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3082 || (TARGET_MAVERICK
&& mode
== DImode
)))
3083 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3084 && INTVAL (index
) > -1024
3085 && (INTVAL (index
) & 3) == 0);
3087 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3088 return (code
== CONST_INT
3089 && INTVAL (index
) < 1024
3090 && INTVAL (index
) > -1024
3091 && (INTVAL (index
) & 3) == 0);
3093 if (arm_address_register_rtx_p (index
, strict_p
)
3094 && (GET_MODE_SIZE (mode
) <= 4))
3097 if (mode
== DImode
|| mode
== DFmode
)
3099 if (code
== CONST_INT
)
3101 HOST_WIDE_INT val
= INTVAL (index
);
3104 return val
> -256 && val
< 256;
3106 return val
== 4 || val
== -4 || val
== -8;
3109 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3112 if (GET_MODE_SIZE (mode
) <= 4
3115 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3119 rtx xiop0
= XEXP (index
, 0);
3120 rtx xiop1
= XEXP (index
, 1);
3122 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3123 && power_of_two_operand (xiop1
, SImode
))
3124 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3125 && power_of_two_operand (xiop0
, SImode
)));
3127 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3128 || code
== ASHIFT
|| code
== ROTATERT
)
3130 rtx op
= XEXP (index
, 1);
3132 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3133 && GET_CODE (op
) == CONST_INT
3135 && INTVAL (op
) <= 31);
3139 /* For ARM v4 we may be doing a sign-extend operation during the
3143 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3149 range
= (mode
== HImode
) ? 4095 : 4096;
3151 return (code
== CONST_INT
3152 && INTVAL (index
) < range
3153 && INTVAL (index
) > -range
);
3156 /* Return nonzero if X is valid as a Thumb state base register. */
3158 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3162 if (GET_CODE (x
) != REG
)
3168 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3170 return (regno
<= LAST_LO_REGNUM
3171 || regno
> LAST_VIRTUAL_REGISTER
3172 || regno
== FRAME_POINTER_REGNUM
3173 || (GET_MODE_SIZE (mode
) >= 4
3174 && (regno
== STACK_POINTER_REGNUM
3175 || regno
>= FIRST_PSEUDO_REGISTER
3176 || x
== hard_frame_pointer_rtx
3177 || x
== arg_pointer_rtx
)));
3180 /* Return nonzero if x is a legitimate index register. This is the case
3181 for any base register that can access a QImode object. */
3183 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3185 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3188 /* Return nonzero if x is a legitimate Thumb-state address.
3190 The AP may be eliminated to either the SP or the FP, so we use the
3191 least common denominator, e.g. SImode, and offsets from 0 to 64.
3193 ??? Verify whether the above is the right approach.
3195 ??? Also, the FP may be eliminated to the SP, so perhaps that
3196 needs special handling also.
3198 ??? Look at how the mips16 port solves this problem. It probably uses
3199 better ways to solve some of these problems.
3201 Although it is not incorrect, we don't accept QImode and HImode
3202 addresses based on the frame pointer or arg pointer until the
3203 reload pass starts. This is so that eliminating such addresses
3204 into stack based ones won't produce impossible code. */
3206 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3208 /* ??? Not clear if this is right. Experiment. */
3209 if (GET_MODE_SIZE (mode
) < 4
3210 && !(reload_in_progress
|| reload_completed
)
3211 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3212 || reg_mentioned_p (arg_pointer_rtx
, x
)
3213 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3214 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3215 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3216 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3219 /* Accept any base register. SP only in SImode or larger. */
3220 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3223 /* This is PC relative data before arm_reorg runs. */
3224 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3225 && GET_CODE (x
) == SYMBOL_REF
3226 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
3229 /* This is PC relative data after arm_reorg runs. */
3230 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3231 && (GET_CODE (x
) == LABEL_REF
3232 || (GET_CODE (x
) == CONST
3233 && GET_CODE (XEXP (x
, 0)) == PLUS
3234 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3235 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3238 /* Post-inc indexing only supported for SImode and larger. */
3239 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3240 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3243 else if (GET_CODE (x
) == PLUS
)
3245 /* REG+REG address can be any two index registers. */
3246 /* We disallow FRAME+REG addressing since we know that FRAME
3247 will be replaced with STACK, and SP relative addressing only
3248 permits SP+OFFSET. */
3249 if (GET_MODE_SIZE (mode
) <= 4
3250 && XEXP (x
, 0) != frame_pointer_rtx
3251 && XEXP (x
, 1) != frame_pointer_rtx
3252 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3253 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3256 /* REG+const has 5-7 bit offset for non-SP registers. */
3257 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3258 || XEXP (x
, 0) == arg_pointer_rtx
)
3259 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3260 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3263 /* REG+const has 10 bit offset for SP, but only SImode and
3264 larger is supported. */
3265 /* ??? Should probably check for DI/DFmode overflow here
3266 just like GO_IF_LEGITIMATE_OFFSET does. */
3267 else if (GET_CODE (XEXP (x
, 0)) == REG
3268 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3269 && GET_MODE_SIZE (mode
) >= 4
3270 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3271 && INTVAL (XEXP (x
, 1)) >= 0
3272 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3273 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3276 else if (GET_CODE (XEXP (x
, 0)) == REG
3277 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3278 && GET_MODE_SIZE (mode
) >= 4
3279 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3280 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3284 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3285 && GET_MODE_SIZE (mode
) == 4
3286 && GET_CODE (x
) == SYMBOL_REF
3287 && CONSTANT_POOL_ADDRESS_P (x
)
3289 && symbol_mentioned_p (get_pool_constant (x
))))
3295 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3296 instruction of mode MODE. */
3298 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3300 switch (GET_MODE_SIZE (mode
))
3303 return val
>= 0 && val
< 32;
3306 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3310 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3315 /* Try machine-dependent ways of modifying an illegitimate address
3316 to be legitimate. If we find one, return the new, valid address. */
3318 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3320 if (GET_CODE (x
) == PLUS
)
3322 rtx xop0
= XEXP (x
, 0);
3323 rtx xop1
= XEXP (x
, 1);
3325 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3326 xop0
= force_reg (SImode
, xop0
);
3328 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3329 xop1
= force_reg (SImode
, xop1
);
3331 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3332 && GET_CODE (xop1
) == CONST_INT
)
3334 HOST_WIDE_INT n
, low_n
;
3338 /* VFP addressing modes actually allow greater offsets, but for
3339 now we just stick with the lowest common denominator. */
3341 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
3353 low_n
= ((mode
) == TImode
? 0
3354 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3358 base_reg
= gen_reg_rtx (SImode
);
3359 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3360 GEN_INT (n
)), NULL_RTX
);
3361 emit_move_insn (base_reg
, val
);
3362 x
= (low_n
== 0 ? base_reg
3363 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3365 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3366 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3369 /* XXX We don't allow MINUS any more -- see comment in
3370 arm_legitimate_address_p (). */
3371 else if (GET_CODE (x
) == MINUS
)
3373 rtx xop0
= XEXP (x
, 0);
3374 rtx xop1
= XEXP (x
, 1);
3376 if (CONSTANT_P (xop0
))
3377 xop0
= force_reg (SImode
, xop0
);
3379 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3380 xop1
= force_reg (SImode
, xop1
);
3382 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3383 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3388 /* We need to find and carefully transform any SYMBOL and LABEL
3389 references; so go back to the original address expression. */
3390 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3392 if (new_x
!= orig_x
)
3400 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3401 to be legitimate. If we find one, return the new, valid address. */
3403 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3405 if (GET_CODE (x
) == PLUS
3406 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3407 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
3408 || INTVAL (XEXP (x
, 1)) < 0))
3410 rtx xop0
= XEXP (x
, 0);
3411 rtx xop1
= XEXP (x
, 1);
3412 HOST_WIDE_INT offset
= INTVAL (xop1
);
3414 /* Try and fold the offset into a biasing of the base register and
3415 then offsetting that. Don't do this when optimizing for space
3416 since it can cause too many CSEs. */
3417 if (optimize_size
&& offset
>= 0
3418 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
3420 HOST_WIDE_INT delta
;
3423 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
3424 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
3425 delta
= 31 * GET_MODE_SIZE (mode
);
3427 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
3429 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
3431 x
= plus_constant (xop0
, delta
);
3433 else if (offset
< 0 && offset
> -256)
3434 /* Small negative offsets are best done with a subtract before the
3435 dereference, forcing these into a register normally takes two
3437 x
= force_operand (x
, NULL_RTX
);
3440 /* For the remaining cases, force the constant into a register. */
3441 xop1
= force_reg (SImode
, xop1
);
3442 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3445 else if (GET_CODE (x
) == PLUS
3446 && s_register_operand (XEXP (x
, 1), SImode
)
3447 && !s_register_operand (XEXP (x
, 0), SImode
))
3449 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
3451 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
3456 /* We need to find and carefully transform any SYMBOL and LABEL
3457 references; so go back to the original address expression. */
3458 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3460 if (new_x
!= orig_x
)
3469 #define REG_OR_SUBREG_REG(X) \
3470 (GET_CODE (X) == REG \
3471 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3473 #define REG_OR_SUBREG_RTX(X) \
3474 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3476 #ifndef COSTS_N_INSNS
3477 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3480 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3482 enum machine_mode mode
= GET_MODE (x
);
3495 return COSTS_N_INSNS (1);
3498 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3501 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
3508 return COSTS_N_INSNS (2) + cycles
;
3510 return COSTS_N_INSNS (1) + 16;
3513 return (COSTS_N_INSNS (1)
3514 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
3515 + GET_CODE (SET_DEST (x
)) == MEM
));
3520 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3522 if (thumb_shiftable_const (INTVAL (x
)))
3523 return COSTS_N_INSNS (2);
3524 return COSTS_N_INSNS (3);
3526 else if ((outer
== PLUS
|| outer
== COMPARE
)
3527 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
3529 else if (outer
== AND
3530 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
3531 return COSTS_N_INSNS (1);
3532 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
3533 || outer
== LSHIFTRT
)
3535 return COSTS_N_INSNS (2);
3541 return COSTS_N_INSNS (3);
3560 /* XXX another guess. */
3561 /* Memory costs quite a lot for the first word, but subsequent words
3562 load at the equivalent of a single insn each. */
3563 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3564 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
3569 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3574 /* XXX still guessing. */
3575 switch (GET_MODE (XEXP (x
, 0)))
3578 return (1 + (mode
== DImode
? 4 : 0)
3579 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3582 return (4 + (mode
== DImode
? 4 : 0)
3583 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3586 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3598 /* Worker routine for arm_rtx_costs. */
3600 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3602 enum machine_mode mode
= GET_MODE (x
);
3603 enum rtx_code subcode
;
3609 /* Memory costs quite a lot for the first word, but subsequent words
3610 load at the equivalent of a single insn each. */
3611 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3612 + (GET_CODE (x
) == SYMBOL_REF
3613 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
3619 return optimize_size
? COSTS_N_INSNS (2) : 100;
3622 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
3629 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
3631 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
3632 + ((GET_CODE (XEXP (x
, 0)) == REG
3633 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3634 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3636 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
3637 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3638 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3640 + ((GET_CODE (XEXP (x
, 1)) == REG
3641 || (GET_CODE (XEXP (x
, 1)) == SUBREG
3642 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
3643 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
3648 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
3649 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3650 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
3651 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
3654 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3655 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3656 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3657 && arm_const_double_rtx (XEXP (x
, 1))))
3659 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3660 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
3661 && arm_const_double_rtx (XEXP (x
, 0))))
3664 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
3665 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
3666 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
3667 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
3668 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
3669 || subcode
== ROTATE
|| subcode
== ROTATERT
3671 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3672 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
3673 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
3674 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
3675 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
3676 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
3677 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
3682 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3683 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3684 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3685 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3686 && arm_const_double_rtx (XEXP (x
, 1))))
3690 case AND
: case XOR
: case IOR
:
3693 /* Normally the frame registers will be spilt into reg+const during
3694 reload, so it is a bad idea to combine them with other instructions,
3695 since then they might not be moved outside of loops. As a compromise
3696 we allow integration with ops that have a constant as their second
3698 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3699 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
3700 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3701 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
3702 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
3706 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3707 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3708 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3709 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3712 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
3713 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
3714 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3715 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3716 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3719 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
3720 return (1 + extra_cost
3721 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
3722 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
3723 || subcode
== ROTATE
|| subcode
== ROTATERT
3725 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3726 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
3727 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
3728 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
3729 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
3730 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
3736 /* This should have been handled by the CPU specific routines. */
3740 if (arm_arch3m
&& mode
== SImode
3741 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3742 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
3743 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
3744 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
3745 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
3746 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
3751 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3752 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
3756 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3758 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3761 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3769 return 4 + (mode
== DImode
? 4 : 0);
3772 if (GET_MODE (XEXP (x
, 0)) == QImode
)
3773 return (4 + (mode
== DImode
? 4 : 0)
3774 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3777 switch (GET_MODE (XEXP (x
, 0)))
3780 return (1 + (mode
== DImode
? 4 : 0)
3781 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3784 return (4 + (mode
== DImode
? 4 : 0)
3785 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3788 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3803 if (const_ok_for_arm (INTVAL (x
)))
3804 return outer
== SET
? 2 : -1;
3805 else if (outer
== AND
3806 && const_ok_for_arm (~INTVAL (x
)))
3808 else if ((outer
== COMPARE
3809 || outer
== PLUS
|| outer
== MINUS
)
3810 && const_ok_for_arm (-INTVAL (x
)))
3821 if (arm_const_double_rtx (x
))
3822 return outer
== SET
? 2 : -1;
3823 else if ((outer
== COMPARE
|| outer
== PLUS
)
3824 && neg_const_double_rtx_ok_for_fpa (x
))
3833 /* RTX costs for cores with a slow MUL implementation. */
3836 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3838 enum machine_mode mode
= GET_MODE (x
);
3842 *total
= thumb_rtx_costs (x
, code
, outer_code
);
3849 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3856 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3858 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3859 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3860 int cost
, const_ok
= const_ok_for_arm (i
);
3861 int j
, booth_unit_size
;
3863 /* Tune as appropriate. */
3864 cost
= const_ok
? 4 : 8;
3865 booth_unit_size
= 2;
3866 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
3868 i
>>= booth_unit_size
;
3876 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
3877 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
3881 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
3887 /* RTX cost for cores with a fast multiply unit (M variants). */
3890 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3892 enum machine_mode mode
= GET_MODE (x
);
3896 *total
= thumb_rtx_costs (x
, code
, outer_code
);
3903 /* There is no point basing this on the tuning, since it is always the
3904 fast variant if it exists at all. */
3906 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
3907 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
3908 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
3915 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3922 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3924 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3925 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3926 int cost
, const_ok
= const_ok_for_arm (i
);
3927 int j
, booth_unit_size
;
3929 /* Tune as appropriate. */
3930 cost
= const_ok
? 4 : 8;
3931 booth_unit_size
= 8;
3932 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
3934 i
>>= booth_unit_size
;
3942 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
3943 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
3947 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
3953 /* RTX cost for XScale CPUs. */
3956 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3958 enum machine_mode mode
= GET_MODE (x
);
3962 *total
= thumb_rtx_costs (x
, code
, outer_code
);
3969 /* There is no point basing this on the tuning, since it is always the
3970 fast variant if it exists at all. */
3972 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
3973 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
3974 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
3981 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3988 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3990 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3991 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3992 int cost
, const_ok
= const_ok_for_arm (i
);
3993 unsigned HOST_WIDE_INT masked_const
;
3995 /* The cost will be related to two insns.
3996 First a load of the constant (MOV or LDR), then a multiply. */
3999 cost
+= 1; /* LDR is probably more expensive because
4000 of longer result latency. */
4001 masked_const
= i
& 0xffff8000;
4002 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
4004 masked_const
= i
& 0xf8000000;
4005 if (masked_const
== 0 || masked_const
== 0xf8000000)
4014 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4015 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4019 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4025 /* RTX costs for 9e (and later) cores. */
4028 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4030 enum machine_mode mode
= GET_MODE (x
);
4039 *total
= COSTS_N_INSNS (3);
4043 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4051 /* There is no point basing this on the tuning, since it is always the
4052 fast variant if it exists at all. */
4054 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4055 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4056 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4063 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4080 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
4081 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
4085 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4089 /* All address computations that can be done are free, but rtx cost returns
4090 the same for practically all of them. So we weight the different types
4091 of address here in the order (most pref first):
4092 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4094 arm_arm_address_cost (rtx x
)
4096 enum rtx_code c
= GET_CODE (x
);
4098 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
4100 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
4103 if (c
== PLUS
|| c
== MINUS
)
4105 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
4108 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
4118 arm_thumb_address_cost (rtx x
)
4120 enum rtx_code c
= GET_CODE (x
);
4125 && GET_CODE (XEXP (x
, 0)) == REG
4126 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4133 arm_address_cost (rtx x
)
4135 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
4139 arm_use_dfa_pipeline_interface (void)
4145 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
4149 /* Some true dependencies can have a higher cost depending
4150 on precisely how certain input operands are used. */
4152 && REG_NOTE_KIND (link
) == 0
4153 && recog_memoized (insn
) >= 0
4154 && recog_memoized (dep
) >= 0)
4156 int shift_opnum
= get_attr_shift (insn
);
4157 enum attr_type attr_type
= get_attr_type (dep
);
4159 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4160 operand for INSN. If we have a shifted input operand and the
4161 instruction we depend on is another ALU instruction, then we may
4162 have to account for an additional stall. */
4163 if (shift_opnum
!= 0
4164 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
4166 rtx shifted_operand
;
4169 /* Get the shifted operand. */
4170 extract_insn (insn
);
4171 shifted_operand
= recog_data
.operand
[shift_opnum
];
4173 /* Iterate over all the operands in DEP. If we write an operand
4174 that overlaps with SHIFTED_OPERAND, then we have increase the
4175 cost of this dependency. */
4177 preprocess_constraints ();
4178 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
4180 /* We can ignore strict inputs. */
4181 if (recog_data
.operand_type
[opno
] == OP_IN
)
4184 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
4191 /* XXX This is not strictly true for the FPA. */
4192 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
4193 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
4196 /* Call insns don't incur a stall, even if they follow a load. */
4197 if (REG_NOTE_KIND (link
) == 0
4198 && GET_CODE (insn
) == CALL_INSN
)
4201 if ((i_pat
= single_set (insn
)) != NULL
4202 && GET_CODE (SET_SRC (i_pat
)) == MEM
4203 && (d_pat
= single_set (dep
)) != NULL
4204 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
4206 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
4207 /* This is a load after a store, there is no conflict if the load reads
4208 from a cached area. Assume that loads from the stack, and from the
4209 constant pool are cached, and that others will miss. This is a
4212 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
4213 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
4214 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
4215 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
4222 static int fp_consts_inited
= 0;
4224 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4225 static const char * const strings_fp
[8] =
4228 "4", "5", "0.5", "10"
4231 static REAL_VALUE_TYPE values_fp
[8];
4234 init_fp_table (void)
4240 fp_consts_inited
= 1;
4242 fp_consts_inited
= 8;
4244 for (i
= 0; i
< fp_consts_inited
; i
++)
4246 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
4251 /* Return TRUE if rtx X is a valid immediate FP constant. */
4253 arm_const_double_rtx (rtx x
)
4258 if (!fp_consts_inited
)
4261 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4262 if (REAL_VALUE_MINUS_ZERO (r
))
4265 for (i
= 0; i
< fp_consts_inited
; i
++)
4266 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4272 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4274 neg_const_double_rtx_ok_for_fpa (rtx x
)
4279 if (!fp_consts_inited
)
4282 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4283 r
= REAL_VALUE_NEGATE (r
);
4284 if (REAL_VALUE_MINUS_ZERO (r
))
4287 for (i
= 0; i
< 8; i
++)
4288 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4294 /* Predicates for `match_operand' and `match_operator'. */
4296 /* s_register_operand is the same as register_operand, but it doesn't accept
4299 This function exists because at the time it was put in it led to better
4300 code. SUBREG(MEM) always needs a reload in the places where
4301 s_register_operand is used, and this seemed to lead to excessive
4304 s_register_operand (rtx op
, enum machine_mode mode
)
4306 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4309 if (GET_CODE (op
) == SUBREG
)
4310 op
= SUBREG_REG (op
);
4312 /* We don't consider registers whose class is NO_REGS
4313 to be a register operand. */
4314 /* XXX might have to check for lo regs only for thumb ??? */
4315 return (GET_CODE (op
) == REG
4316 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4317 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
4320 /* A hard register operand (even before reload. */
4322 arm_hard_register_operand (rtx op
, enum machine_mode mode
)
4324 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4327 return (GET_CODE (op
) == REG
4328 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
4331 /* An arm register operand. */
4333 arm_general_register_operand (rtx op
, enum machine_mode mode
)
4335 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4338 if (GET_CODE (op
) == SUBREG
)
4339 op
= SUBREG_REG (op
);
4341 return (GET_CODE (op
) == REG
4342 && (REGNO (op
) <= LAST_ARM_REGNUM
4343 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
));
4346 /* Only accept reg, subreg(reg), const_int. */
4348 reg_or_int_operand (rtx op
, enum machine_mode mode
)
4350 if (GET_CODE (op
) == CONST_INT
)
4353 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4356 if (GET_CODE (op
) == SUBREG
)
4357 op
= SUBREG_REG (op
);
4359 /* We don't consider registers whose class is NO_REGS
4360 to be a register operand. */
4361 return (GET_CODE (op
) == REG
4362 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4363 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
4366 /* Return 1 if OP is an item in memory, given that we are in reload. */
4368 arm_reload_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4370 int regno
= true_regnum (op
);
4372 return (!CONSTANT_P (op
)
4374 || (GET_CODE (op
) == REG
4375 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
4378 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4380 arm_rhs_operand (rtx op
, enum machine_mode mode
)
4382 return (s_register_operand (op
, mode
)
4383 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
4386 /* Return TRUE for valid operands for the
4387 rhs of an ARM instruction, or a load. */
4389 arm_rhsm_operand (rtx op
, enum machine_mode mode
)
4391 return (s_register_operand (op
, mode
)
4392 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
4393 || memory_operand (op
, mode
));
4396 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4397 constant that is valid when negated. */
4399 arm_add_operand (rtx op
, enum machine_mode mode
)
4402 return thumb_cmp_operand (op
, mode
);
4404 return (s_register_operand (op
, mode
)
4405 || (GET_CODE (op
) == CONST_INT
4406 && (const_ok_for_arm (INTVAL (op
))
4407 || const_ok_for_arm (-INTVAL (op
)))));
4410 /* Return TRUE for valid ARM constants (or when valid if negated). */
4412 arm_addimm_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4414 return (GET_CODE (op
) == CONST_INT
4415 && (const_ok_for_arm (INTVAL (op
))
4416 || const_ok_for_arm (-INTVAL (op
))));
4420 arm_not_operand (rtx op
, enum machine_mode mode
)
4422 return (s_register_operand (op
, mode
)
4423 || (GET_CODE (op
) == CONST_INT
4424 && (const_ok_for_arm (INTVAL (op
))
4425 || const_ok_for_arm (~INTVAL (op
)))));
4428 /* Return TRUE if the operand is a memory reference which contains an
4429 offsettable address. */
4431 offsettable_memory_operand (rtx op
, enum machine_mode mode
)
4433 if (mode
== VOIDmode
)
4434 mode
= GET_MODE (op
);
4436 return (mode
== GET_MODE (op
)
4437 && GET_CODE (op
) == MEM
4438 && offsettable_address_p (reload_completed
| reload_in_progress
,
4439 mode
, XEXP (op
, 0)));
4442 /* Return TRUE if the operand is a memory reference which is, or can be
4443 made word aligned by adjusting the offset. */
4445 alignable_memory_operand (rtx op
, enum machine_mode mode
)
4449 if (mode
== VOIDmode
)
4450 mode
= GET_MODE (op
);
4452 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
4457 return ((GET_CODE (reg
= op
) == REG
4458 || (GET_CODE (op
) == SUBREG
4459 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
4460 || (GET_CODE (op
) == PLUS
4461 && GET_CODE (XEXP (op
, 1)) == CONST_INT
4462 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
4463 || (GET_CODE (XEXP (op
, 0)) == SUBREG
4464 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
4465 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
4468 /* Similar to s_register_operand, but does not allow hard integer
4471 f_register_operand (rtx op
, enum machine_mode mode
)
4473 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4476 if (GET_CODE (op
) == SUBREG
)
4477 op
= SUBREG_REG (op
);
4479 /* We don't consider registers whose class is NO_REGS
4480 to be a register operand. */
4481 return (GET_CODE (op
) == REG
4482 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4483 || REGNO_REG_CLASS (REGNO (op
)) == FPA_REGS
));
4486 /* Return TRUE for valid operands for the rhs of an floating point insns.
4487 Allows regs or certain consts on FPA, just regs for everything else. */
4489 arm_float_rhs_operand (rtx op
, enum machine_mode mode
)
4491 if (s_register_operand (op
, mode
))
4494 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4497 if (TARGET_FPA
&& GET_CODE (op
) == CONST_DOUBLE
)
4498 return arm_const_double_rtx (op
);
4504 arm_float_add_operand (rtx op
, enum machine_mode mode
)
4506 if (s_register_operand (op
, mode
))
4509 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4512 if (TARGET_FPA
&& GET_CODE (op
) == CONST_DOUBLE
)
4513 return (arm_const_double_rtx (op
)
4514 || neg_const_double_rtx_ok_for_fpa (op
));
4520 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4521 Depends which fpu we are targeting. */
4524 arm_float_compare_operand (rtx op
, enum machine_mode mode
)
4527 return vfp_compare_operand (op
, mode
);
4529 return arm_float_rhs_operand (op
, mode
);
4533 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4535 cirrus_memory_offset (rtx op
)
4537 /* Reject eliminable registers. */
4538 if (! (reload_in_progress
|| reload_completed
)
4539 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4540 || reg_mentioned_p (arg_pointer_rtx
, op
)
4541 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4542 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4543 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4544 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4547 if (GET_CODE (op
) == MEM
)
4553 /* Match: (mem (reg)). */
4554 if (GET_CODE (ind
) == REG
)
4560 if (GET_CODE (ind
) == PLUS
4561 && GET_CODE (XEXP (ind
, 0)) == REG
4562 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4563 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
4571 arm_extendqisi_mem_op (rtx op
, enum machine_mode mode
)
4573 if (!memory_operand (op
, mode
))
4576 return arm_legitimate_address_p (mode
, XEXP (op
, 0), SIGN_EXTEND
, 0);
4579 /* Return nonzero if OP is a Cirrus or general register. */
4581 cirrus_register_operand (rtx op
, enum machine_mode mode
)
4583 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4586 if (GET_CODE (op
) == SUBREG
)
4587 op
= SUBREG_REG (op
);
4589 return (GET_CODE (op
) == REG
4590 && (REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
4591 || REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
));
4594 /* Return nonzero if OP is a cirrus FP register. */
4596 cirrus_fp_register (rtx op
, enum machine_mode mode
)
4598 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4601 if (GET_CODE (op
) == SUBREG
)
4602 op
= SUBREG_REG (op
);
4604 return (GET_CODE (op
) == REG
4605 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4606 || REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
));
4609 /* Return nonzero if OP is a 6bit constant (0..63). */
4611 cirrus_shift_const (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4613 return (GET_CODE (op
) == CONST_INT
4615 && INTVAL (op
) < 64);
4619 /* Return TRUE if OP is a valid VFP memory address pattern.
4620 WB if true if writeback address modes are allowed. */
4623 arm_coproc_mem_operand (rtx op
, bool wb
)
4627 /* Reject eliminable registers. */
4628 if (! (reload_in_progress
|| reload_completed
)
4629 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4630 || reg_mentioned_p (arg_pointer_rtx
, op
)
4631 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4632 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4633 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4634 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4637 /* Constants are converted into offsets from labels. */
4638 if (GET_CODE (op
) != MEM
)
4643 if (reload_completed
4644 && (GET_CODE (ind
) == LABEL_REF
4645 || (GET_CODE (ind
) == CONST
4646 && GET_CODE (XEXP (ind
, 0)) == PLUS
4647 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
4648 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
4651 /* Match: (mem (reg)). */
4652 if (GET_CODE (ind
) == REG
)
4653 return arm_address_register_rtx_p (ind
, 0);
4655 /* Autoincremment addressing modes. */
4657 && (GET_CODE (ind
) == PRE_INC
4658 || GET_CODE (ind
) == POST_INC
4659 || GET_CODE (ind
) == PRE_DEC
4660 || GET_CODE (ind
) == POST_DEC
))
4661 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
4664 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
4665 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
4666 && GET_CODE (XEXP (ind
, 1)) == PLUS
4667 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
4668 ind
= XEXP (ind
, 1);
4673 if (GET_CODE (ind
) == PLUS
4674 && GET_CODE (XEXP (ind
, 0)) == REG
4675 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4676 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
4677 && INTVAL (XEXP (ind
, 1)) > -1024
4678 && INTVAL (XEXP (ind
, 1)) < 1024
4679 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
4686 /* Return TRUE if OP is a REG or constant zero. */
4688 vfp_compare_operand (rtx op
, enum machine_mode mode
)
4690 if (s_register_operand (op
, mode
))
4693 return (GET_CODE (op
) == CONST_DOUBLE
4694 && arm_const_double_rtx (op
));
4698 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4699 VFP registers. Otherwise return NO_REGS. */
4702 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
4704 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
4707 return GENERAL_REGS
;
4711 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4712 Use by the Cirrus Maverick code which has to workaround
4713 a hardware bug triggered by such instructions. */
4715 arm_memory_load_p (rtx insn
)
4717 rtx body
, lhs
, rhs
;;
4719 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
4722 body
= PATTERN (insn
);
4724 if (GET_CODE (body
) != SET
)
4727 lhs
= XEXP (body
, 0);
4728 rhs
= XEXP (body
, 1);
4730 lhs
= REG_OR_SUBREG_RTX (lhs
);
4732 /* If the destination is not a general purpose
4733 register we do not have to worry. */
4734 if (GET_CODE (lhs
) != REG
4735 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
4738 /* As well as loads from memory we also have to react
4739 to loads of invalid constants which will be turned
4740 into loads from the minipool. */
4741 return (GET_CODE (rhs
) == MEM
4742 || GET_CODE (rhs
) == SYMBOL_REF
4743 || note_invalid_constants (insn
, -1, false));
4746 /* Return TRUE if INSN is a Cirrus instruction. */
4748 arm_cirrus_insn_p (rtx insn
)
4750 enum attr_cirrus attr
;
4752 /* get_attr aborts on USE and CLOBBER. */
4754 || GET_CODE (insn
) != INSN
4755 || GET_CODE (PATTERN (insn
)) == USE
4756 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4759 attr
= get_attr_cirrus (insn
);
4761 return attr
!= CIRRUS_NOT
;
4764 /* Cirrus reorg for invalid instruction combinations. */
4766 cirrus_reorg (rtx first
)
4768 enum attr_cirrus attr
;
4769 rtx body
= PATTERN (first
);
4773 /* Any branch must be followed by 2 non Cirrus instructions. */
4774 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
4777 t
= next_nonnote_insn (first
);
4779 if (arm_cirrus_insn_p (t
))
4782 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4786 emit_insn_after (gen_nop (), first
);
4791 /* (float (blah)) is in parallel with a clobber. */
4792 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
4793 body
= XVECEXP (body
, 0, 0);
4795 if (GET_CODE (body
) == SET
)
4797 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
4799 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4800 be followed by a non Cirrus insn. */
4801 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
4803 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
4804 emit_insn_after (gen_nop (), first
);
4808 else if (arm_memory_load_p (first
))
4810 unsigned int arm_regno
;
4812 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4813 ldr/cfmv64hr combination where the Rd field is the same
4814 in both instructions must be split with a non Cirrus
4821 /* Get Arm register number for ldr insn. */
4822 if (GET_CODE (lhs
) == REG
)
4823 arm_regno
= REGNO (lhs
);
4824 else if (GET_CODE (rhs
) == REG
)
4825 arm_regno
= REGNO (rhs
);
4830 first
= next_nonnote_insn (first
);
4832 if (! arm_cirrus_insn_p (first
))
4835 body
= PATTERN (first
);
4837 /* (float (blah)) is in parallel with a clobber. */
4838 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
4839 body
= XVECEXP (body
, 0, 0);
4841 if (GET_CODE (body
) == FLOAT
)
4842 body
= XEXP (body
, 0);
4844 if (get_attr_cirrus (first
) == CIRRUS_MOVE
4845 && GET_CODE (XEXP (body
, 1)) == REG
4846 && arm_regno
== REGNO (XEXP (body
, 1)))
4847 emit_insn_after (gen_nop (), first
);
4853 /* get_attr aborts on USE and CLOBBER. */
4855 || GET_CODE (first
) != INSN
4856 || GET_CODE (PATTERN (first
)) == USE
4857 || GET_CODE (PATTERN (first
)) == CLOBBER
)
4860 attr
= get_attr_cirrus (first
);
4862 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4863 must be followed by a non-coprocessor instruction. */
4864 if (attr
== CIRRUS_COMPARE
)
4868 t
= next_nonnote_insn (first
);
4870 if (arm_cirrus_insn_p (t
))
4873 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4877 emit_insn_after (gen_nop (), first
);
4883 /* Return nonzero if OP is a constant power of two. */
4885 power_of_two_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4887 if (GET_CODE (op
) == CONST_INT
)
4889 HOST_WIDE_INT value
= INTVAL (op
);
4891 return value
!= 0 && (value
& (value
- 1)) == 0;
4897 /* Return TRUE for a valid operand of a DImode operation.
4898 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4899 Note that this disallows MEM(REG+REG), but allows
4900 MEM(PRE/POST_INC/DEC(REG)). */
4902 di_operand (rtx op
, enum machine_mode mode
)
4904 if (s_register_operand (op
, mode
))
4907 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4910 if (GET_CODE (op
) == SUBREG
)
4911 op
= SUBREG_REG (op
);
4913 switch (GET_CODE (op
))
4920 return memory_address_p (DImode
, XEXP (op
, 0));
4927 /* Like di_operand, but don't accept constants. */
4929 nonimmediate_di_operand (rtx op
, enum machine_mode mode
)
4931 if (s_register_operand (op
, mode
))
4934 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4937 if (GET_CODE (op
) == SUBREG
)
4938 op
= SUBREG_REG (op
);
4940 if (GET_CODE (op
) == MEM
)
4941 return memory_address_p (DImode
, XEXP (op
, 0));
4946 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
4947 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4948 Note that this disallows MEM(REG+REG), but allows
4949 MEM(PRE/POST_INC/DEC(REG)). */
4951 soft_df_operand (rtx op
, enum machine_mode mode
)
4953 if (s_register_operand (op
, mode
))
4956 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4959 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
4962 if (GET_CODE (op
) == SUBREG
)
4963 op
= SUBREG_REG (op
);
4965 switch (GET_CODE (op
))
4971 return memory_address_p (DFmode
, XEXP (op
, 0));
4978 /* Like soft_df_operand, but don't accept constants. */
4980 nonimmediate_soft_df_operand (rtx op
, enum machine_mode mode
)
4982 if (s_register_operand (op
, mode
))
4985 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4988 if (GET_CODE (op
) == SUBREG
)
4989 op
= SUBREG_REG (op
);
4991 if (GET_CODE (op
) == MEM
)
4992 return memory_address_p (DFmode
, XEXP (op
, 0));
4996 /* Return TRUE for valid index operands. */
4998 index_operand (rtx op
, enum machine_mode mode
)
5000 return (s_register_operand (op
, mode
)
5001 || (immediate_operand (op
, mode
)
5002 && (GET_CODE (op
) != CONST_INT
5003 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
5006 /* Return TRUE for valid shifts by a constant. This also accepts any
5007 power of two on the (somewhat overly relaxed) assumption that the
5008 shift operator in this case was a mult. */
5010 const_shift_operand (rtx op
, enum machine_mode mode
)
5012 return (power_of_two_operand (op
, mode
)
5013 || (immediate_operand (op
, mode
)
5014 && (GET_CODE (op
) != CONST_INT
5015 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
5018 /* Return TRUE for arithmetic operators which can be combined with a multiply
5021 shiftable_operator (rtx x
, enum machine_mode mode
)
5025 if (GET_MODE (x
) != mode
)
5028 code
= GET_CODE (x
);
5030 return (code
== PLUS
|| code
== MINUS
5031 || code
== IOR
|| code
== XOR
|| code
== AND
);
5034 /* Return TRUE for binary logical operators. */
5036 logical_binary_operator (rtx x
, enum machine_mode mode
)
5040 if (GET_MODE (x
) != mode
)
5043 code
= GET_CODE (x
);
5045 return (code
== IOR
|| code
== XOR
|| code
== AND
);
5048 /* Return TRUE for shift operators. */
5050 shift_operator (rtx x
,enum machine_mode mode
)
5054 if (GET_MODE (x
) != mode
)
5057 code
= GET_CODE (x
);
5060 return power_of_two_operand (XEXP (x
, 1), mode
);
5062 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
5063 || code
== ROTATERT
);
5066 /* Return TRUE if x is EQ or NE. */
5068 equality_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5070 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
5073 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5075 arm_comparison_operator (rtx x
, enum machine_mode mode
)
5077 return (comparison_operator (x
, mode
)
5078 && GET_CODE (x
) != LTGT
5079 && GET_CODE (x
) != UNEQ
);
5082 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5084 minmax_operator (rtx x
, enum machine_mode mode
)
5086 enum rtx_code code
= GET_CODE (x
);
5088 if (GET_MODE (x
) != mode
)
5091 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
5094 /* Return TRUE if this is the condition code register, if we aren't given
5095 a mode, accept any class CCmode register. */
5097 cc_register (rtx x
, enum machine_mode mode
)
5099 if (mode
== VOIDmode
)
5101 mode
= GET_MODE (x
);
5103 if (GET_MODE_CLASS (mode
) != MODE_CC
)
5107 if ( GET_MODE (x
) == mode
5108 && GET_CODE (x
) == REG
5109 && REGNO (x
) == CC_REGNUM
)
5115 /* Return TRUE if this is the condition code register, if we aren't given
5116 a mode, accept any class CCmode register which indicates a dominance
5119 dominant_cc_register (rtx x
, enum machine_mode mode
)
5121 if (mode
== VOIDmode
)
5123 mode
= GET_MODE (x
);
5125 if (GET_MODE_CLASS (mode
) != MODE_CC
)
5129 if (mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
5130 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
5131 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
5132 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
5133 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
5136 return cc_register (x
, mode
);
5139 /* Return TRUE if X references a SYMBOL_REF. */
5141 symbol_mentioned_p (rtx x
)
5146 if (GET_CODE (x
) == SYMBOL_REF
)
5149 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5151 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5157 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5158 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5161 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5168 /* Return TRUE if X references a LABEL_REF. */
5170 label_mentioned_p (rtx x
)
5175 if (GET_CODE (x
) == LABEL_REF
)
5178 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5179 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5185 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5186 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5189 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5199 enum rtx_code code
= GET_CODE (x
);
5203 else if (code
== SMIN
)
5205 else if (code
== UMIN
)
5207 else if (code
== UMAX
)
5213 /* Return 1 if memory locations are adjacent. */
5215 adjacent_mem_locations (rtx a
, rtx b
)
5217 if ((GET_CODE (XEXP (a
, 0)) == REG
5218 || (GET_CODE (XEXP (a
, 0)) == PLUS
5219 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5220 && (GET_CODE (XEXP (b
, 0)) == REG
5221 || (GET_CODE (XEXP (b
, 0)) == PLUS
5222 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5224 int val0
= 0, val1
= 0;
5227 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5229 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
5230 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5233 reg0
= REGNO (XEXP (a
, 0));
5235 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5237 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
5238 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5241 reg1
= REGNO (XEXP (b
, 0));
5243 /* Don't accept any offset that will require multiple
5244 instructions to handle, since this would cause the
5245 arith_adjacentmem pattern to output an overlong sequence. */
5246 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5249 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
5254 /* Return 1 if OP is a load multiple operation. It is known to be
5255 parallel and the first section will be tested. */
5257 load_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5259 HOST_WIDE_INT count
= XVECLEN (op
, 0);
5262 HOST_WIDE_INT i
= 1, base
= 0;
5266 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5269 /* Check to see if this might be a write-back. */
5270 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
5275 /* Now check it more carefully. */
5276 if (GET_CODE (SET_DEST (elt
)) != REG
5277 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
5278 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
5279 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
5283 /* Perform a quick check so we don't blow up below. */
5285 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
5286 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
5287 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
5290 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
5291 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
5293 for (; i
< count
; i
++)
5295 elt
= XVECEXP (op
, 0, i
);
5297 if (GET_CODE (elt
) != SET
5298 || GET_CODE (SET_DEST (elt
)) != REG
5299 || GET_MODE (SET_DEST (elt
)) != SImode
5300 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
5301 || GET_CODE (SET_SRC (elt
)) != MEM
5302 || GET_MODE (SET_SRC (elt
)) != SImode
5303 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
5304 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
5305 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
5306 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
5313 /* Return 1 if OP is a store multiple operation. It is known to be
5314 parallel and the first section will be tested. */
5316 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5318 HOST_WIDE_INT count
= XVECLEN (op
, 0);
5321 HOST_WIDE_INT i
= 1, base
= 0;
5325 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5328 /* Check to see if this might be a write-back. */
5329 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
5334 /* Now check it more carefully. */
5335 if (GET_CODE (SET_DEST (elt
)) != REG
5336 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
5337 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
5338 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
5342 /* Perform a quick check so we don't blow up below. */
5344 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
5345 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
5346 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
5349 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
5350 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
5352 for (; i
< count
; i
++)
5354 elt
= XVECEXP (op
, 0, i
);
5356 if (GET_CODE (elt
) != SET
5357 || GET_CODE (SET_SRC (elt
)) != REG
5358 || GET_MODE (SET_SRC (elt
)) != SImode
5359 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
5360 || GET_CODE (SET_DEST (elt
)) != MEM
5361 || GET_MODE (SET_DEST (elt
)) != SImode
5362 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
5363 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
5364 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
5365 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
5373 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5374 HOST_WIDE_INT
*load_offset
)
5376 int unsorted_regs
[4];
5377 HOST_WIDE_INT unsorted_offsets
[4];
5382 /* Can only handle 2, 3, or 4 insns at present,
5383 though could be easily extended if required. */
5384 if (nops
< 2 || nops
> 4)
5387 /* Loop over the operands and check that the memory references are
5388 suitable (ie immediate offsets from the same base register). At
5389 the same time, extract the target register, and the memory
5391 for (i
= 0; i
< nops
; i
++)
5396 /* Convert a subreg of a mem into the mem itself. */
5397 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5398 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5400 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
5403 /* Don't reorder volatile memory references; it doesn't seem worth
5404 looking for the case where the order is ok anyway. */
5405 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5408 offset
= const0_rtx
;
5410 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5411 || (GET_CODE (reg
) == SUBREG
5412 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5413 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5414 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5416 || (GET_CODE (reg
) == SUBREG
5417 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5418 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5423 base_reg
= REGNO (reg
);
5424 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5425 ? REGNO (operands
[i
])
5426 : REGNO (SUBREG_REG (operands
[i
])));
5431 if (base_reg
!= (int) REGNO (reg
))
5432 /* Not addressed from the same base register. */
5435 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5436 ? REGNO (operands
[i
])
5437 : REGNO (SUBREG_REG (operands
[i
])));
5438 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5442 /* If it isn't an integer register, or if it overwrites the
5443 base register but isn't the last insn in the list, then
5444 we can't do this. */
5445 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5446 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5449 unsorted_offsets
[i
] = INTVAL (offset
);
5452 /* Not a suitable memory address. */
5456 /* All the useful information has now been extracted from the
5457 operands into unsorted_regs and unsorted_offsets; additionally,
5458 order[0] has been set to the lowest numbered register in the
5459 list. Sort the registers into order, and check that the memory
5460 offsets are ascending and adjacent. */
5462 for (i
= 1; i
< nops
; i
++)
5466 order
[i
] = order
[i
- 1];
5467 for (j
= 0; j
< nops
; j
++)
5468 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5469 && (order
[i
] == order
[i
- 1]
5470 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5473 /* Have we found a suitable register? if not, one must be used more
5475 if (order
[i
] == order
[i
- 1])
5478 /* Is the memory address adjacent and ascending? */
5479 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5487 for (i
= 0; i
< nops
; i
++)
5488 regs
[i
] = unsorted_regs
[order
[i
]];
5490 *load_offset
= unsorted_offsets
[order
[0]];
5493 if (unsorted_offsets
[order
[0]] == 0)
5494 return 1; /* ldmia */
5496 if (unsorted_offsets
[order
[0]] == 4)
5497 return 2; /* ldmib */
5499 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5500 return 3; /* ldmda */
5502 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5503 return 4; /* ldmdb */
5505 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5506 if the offset isn't small enough. The reason 2 ldrs are faster
5507 is because these ARMs are able to do more than one cache access
5508 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5509 whilst the ARM8 has a double bandwidth cache. This means that
5510 these cores can do both an instruction fetch and a data fetch in
5511 a single cycle, so the trick of calculating the address into a
5512 scratch register (one of the result regs) and then doing a load
5513 multiple actually becomes slower (and no smaller in code size).
5514 That is the transformation
5516 ldr rd1, [rbase + offset]
5517 ldr rd2, [rbase + offset + 4]
5521 add rd1, rbase, offset
5522 ldmia rd1, {rd1, rd2}
5524 produces worse code -- '3 cycles + any stalls on rd2' instead of
5525 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5526 access per cycle, the first sequence could never complete in less
5527 than 6 cycles, whereas the ldm sequence would only take 5 and
5528 would make better use of sequential accesses if not hitting the
5531 We cheat here and test 'arm_ld_sched' which we currently know to
5532 only be true for the ARM8, ARM9 and StrongARM. If this ever
5533 changes, then the test below needs to be reworked. */
5534 if (nops
== 2 && arm_ld_sched
)
5537 /* Can't do it without setting up the offset, only do this if it takes
5538 no more than one insn. */
5539 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5540 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5544 emit_ldm_seq (rtx
*operands
, int nops
)
5548 HOST_WIDE_INT offset
;
5552 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5555 strcpy (buf
, "ldm%?ia\t");
5559 strcpy (buf
, "ldm%?ib\t");
5563 strcpy (buf
, "ldm%?da\t");
5567 strcpy (buf
, "ldm%?db\t");
5572 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5573 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5576 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5577 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5579 output_asm_insn (buf
, operands
);
5581 strcpy (buf
, "ldm%?ia\t");
5588 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5589 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5591 for (i
= 1; i
< nops
; i
++)
5592 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5593 reg_names
[regs
[i
]]);
5595 strcat (buf
, "}\t%@ phole ldm");
5597 output_asm_insn (buf
, operands
);
5602 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5603 HOST_WIDE_INT
* load_offset
)
5605 int unsorted_regs
[4];
5606 HOST_WIDE_INT unsorted_offsets
[4];
5611 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5612 extended if required. */
5613 if (nops
< 2 || nops
> 4)
5616 /* Loop over the operands and check that the memory references are
5617 suitable (ie immediate offsets from the same base register). At
5618 the same time, extract the target register, and the memory
5620 for (i
= 0; i
< nops
; i
++)
5625 /* Convert a subreg of a mem into the mem itself. */
5626 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5627 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5629 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
5632 /* Don't reorder volatile memory references; it doesn't seem worth
5633 looking for the case where the order is ok anyway. */
5634 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5637 offset
= const0_rtx
;
5639 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5640 || (GET_CODE (reg
) == SUBREG
5641 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5642 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5643 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5645 || (GET_CODE (reg
) == SUBREG
5646 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5647 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5652 base_reg
= REGNO (reg
);
5653 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5654 ? REGNO (operands
[i
])
5655 : REGNO (SUBREG_REG (operands
[i
])));
5660 if (base_reg
!= (int) REGNO (reg
))
5661 /* Not addressed from the same base register. */
5664 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5665 ? REGNO (operands
[i
])
5666 : REGNO (SUBREG_REG (operands
[i
])));
5667 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5671 /* If it isn't an integer register, then we can't do this. */
5672 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
5675 unsorted_offsets
[i
] = INTVAL (offset
);
5678 /* Not a suitable memory address. */
5682 /* All the useful information has now been extracted from the
5683 operands into unsorted_regs and unsorted_offsets; additionally,
5684 order[0] has been set to the lowest numbered register in the
5685 list. Sort the registers into order, and check that the memory
5686 offsets are ascending and adjacent. */
5688 for (i
= 1; i
< nops
; i
++)
5692 order
[i
] = order
[i
- 1];
5693 for (j
= 0; j
< nops
; j
++)
5694 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5695 && (order
[i
] == order
[i
- 1]
5696 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5699 /* Have we found a suitable register? if not, one must be used more
5701 if (order
[i
] == order
[i
- 1])
5704 /* Is the memory address adjacent and ascending? */
5705 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5713 for (i
= 0; i
< nops
; i
++)
5714 regs
[i
] = unsorted_regs
[order
[i
]];
5716 *load_offset
= unsorted_offsets
[order
[0]];
5719 if (unsorted_offsets
[order
[0]] == 0)
5720 return 1; /* stmia */
5722 if (unsorted_offsets
[order
[0]] == 4)
5723 return 2; /* stmib */
5725 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5726 return 3; /* stmda */
5728 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5729 return 4; /* stmdb */
5735 emit_stm_seq (rtx
*operands
, int nops
)
5739 HOST_WIDE_INT offset
;
5743 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5746 strcpy (buf
, "stm%?ia\t");
5750 strcpy (buf
, "stm%?ib\t");
5754 strcpy (buf
, "stm%?da\t");
5758 strcpy (buf
, "stm%?db\t");
5765 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5766 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5768 for (i
= 1; i
< nops
; i
++)
5769 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5770 reg_names
[regs
[i
]]);
5772 strcat (buf
, "}\t%@ phole stm");
5774 output_asm_insn (buf
, operands
);
5779 multi_register_push (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5781 if (GET_CODE (op
) != PARALLEL
5782 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5783 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
5784 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
5790 /* Routines for use in generating RTL. */
5793 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
5794 int write_back
, int unchanging_p
, int in_struct_p
,
5799 int sign
= up
? 1 : -1;
5802 /* XScale has load-store double instructions, but they have stricter
5803 alignment requirements than load-store multiple, so we can not
5806 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5807 the pipeline until completion.
5815 An ldr instruction takes 1-3 cycles, but does not block the
5824 Best case ldr will always win. However, the more ldr instructions
5825 we issue, the less likely we are to be able to schedule them well.
5826 Using ldr instructions also increases code size.
5828 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5829 for counts of 3 or 4 regs. */
5830 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5836 for (i
= 0; i
< count
; i
++)
5838 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
5839 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5840 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5841 MEM_SCALAR_P (mem
) = scalar_p
;
5842 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
5846 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
5854 result
= gen_rtx_PARALLEL (VOIDmode
,
5855 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5858 XVECEXP (result
, 0, 0)
5859 = gen_rtx_SET (GET_MODE (from
), from
,
5860 plus_constant (from
, count
* 4 * sign
));
5865 for (j
= 0; i
< count
; i
++, j
++)
5867 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
5868 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5869 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5870 MEM_SCALAR_P (mem
) = scalar_p
;
5871 XVECEXP (result
, 0, i
)
5872 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
5879 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
5880 int write_back
, int unchanging_p
, int in_struct_p
,
5885 int sign
= up
? 1 : -1;
5888 /* See arm_gen_load_multiple for discussion of
5889 the pros/cons of ldm/stm usage for XScale. */
5890 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5896 for (i
= 0; i
< count
; i
++)
5898 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
5899 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5900 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5901 MEM_SCALAR_P (mem
) = scalar_p
;
5902 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
5906 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
5914 result
= gen_rtx_PARALLEL (VOIDmode
,
5915 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5918 XVECEXP (result
, 0, 0)
5919 = gen_rtx_SET (GET_MODE (to
), to
,
5920 plus_constant (to
, count
* 4 * sign
));
5925 for (j
= 0; i
< count
; i
++, j
++)
5927 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
5928 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5929 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5930 MEM_SCALAR_P (mem
) = scalar_p
;
5932 XVECEXP (result
, 0, i
)
5933 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
5940 arm_gen_movstrqi (rtx
*operands
)
5942 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
5945 rtx st_src
, st_dst
, fin_src
, fin_dst
;
5946 rtx part_bytes_reg
= NULL
;
5948 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
5949 int dst_scalar_p
, src_scalar_p
;
5951 if (GET_CODE (operands
[2]) != CONST_INT
5952 || GET_CODE (operands
[3]) != CONST_INT
5953 || INTVAL (operands
[2]) > 64
5954 || INTVAL (operands
[3]) & 3)
5957 st_dst
= XEXP (operands
[0], 0);
5958 st_src
= XEXP (operands
[1], 0);
5960 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
5961 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
5962 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
5963 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
5964 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
5965 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
5967 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
5968 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
5970 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
5971 out_words_to_go
= INTVAL (operands
[2]) / 4;
5972 last_bytes
= INTVAL (operands
[2]) & 3;
5974 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
5975 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
5977 for (i
= 0; in_words_to_go
>= 2; i
+=4)
5979 if (in_words_to_go
> 4)
5980 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
5985 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
5986 FALSE
, src_unchanging_p
,
5987 src_in_struct_p
, src_scalar_p
));
5989 if (out_words_to_go
)
5991 if (out_words_to_go
> 4)
5992 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
5996 else if (out_words_to_go
!= 1)
5997 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6006 mem
= gen_rtx_MEM (SImode
, dst
);
6007 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6008 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6009 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6010 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6011 if (last_bytes
!= 0)
6012 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6016 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6017 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6020 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6021 if (out_words_to_go
)
6025 mem
= gen_rtx_MEM (SImode
, src
);
6026 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
6027 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
6028 MEM_SCALAR_P (mem
) = src_scalar_p
;
6029 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
6030 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
6032 mem
= gen_rtx_MEM (SImode
, dst
);
6033 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6034 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6035 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6036 emit_move_insn (mem
, sreg
);
6037 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
6040 if (in_words_to_go
) /* Sanity check */
6046 if (in_words_to_go
< 0)
6049 mem
= gen_rtx_MEM (SImode
, src
);
6050 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
6051 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
6052 MEM_SCALAR_P (mem
) = src_scalar_p
;
6053 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6056 if (last_bytes
&& part_bytes_reg
== NULL
)
6059 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6061 rtx tmp
= gen_reg_rtx (SImode
);
6063 /* The bytes we want are in the top end of the word. */
6064 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6065 GEN_INT (8 * (4 - last_bytes
))));
6066 part_bytes_reg
= tmp
;
6070 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
6071 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6072 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6073 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6074 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6078 tmp
= gen_reg_rtx (SImode
);
6079 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6080 part_bytes_reg
= tmp
;
6089 mem
= gen_rtx_MEM (HImode
, dst
);
6090 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6091 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6092 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6093 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6097 rtx tmp
= gen_reg_rtx (SImode
);
6099 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6100 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6101 part_bytes_reg
= tmp
;
6107 mem
= gen_rtx_MEM (QImode
, dst
);
6108 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6109 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6110 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6111 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6118 /* Generate a memory reference for a half word, such that it will be loaded
6119 into the top 16 bits of the word. We can assume that the address is
6120 known to be alignable and of the form reg, or plus (reg, const). */
6123 arm_gen_rotated_half_load (rtx memref
)
6125 HOST_WIDE_INT offset
= 0;
6126 rtx base
= XEXP (memref
, 0);
6128 if (GET_CODE (base
) == PLUS
)
6130 offset
= INTVAL (XEXP (base
, 1));
6131 base
= XEXP (base
, 0);
6134 /* If we aren't allowed to generate unaligned addresses, then fail. */
6135 if (TARGET_MMU_TRAPS
6136 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
6139 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
6141 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
6144 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
6147 /* Select a dominance comparison mode if possible for a test of the general
6148 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6149 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6150 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6151 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6152 In all cases OP will be either EQ or NE, but we don't need to know which
6153 here. If we are unable to support a dominance comparison we return
6154 CC mode. This will then fail to match for the RTL expressions that
6155 generate this call. */
6157 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6159 enum rtx_code cond1
, cond2
;
6162 /* Currently we will probably get the wrong result if the individual
6163 comparisons are not simple. This also ensures that it is safe to
6164 reverse a comparison if necessary. */
6165 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6167 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6171 /* The if_then_else variant of this tests the second condition if the
6172 first passes, but is true if the first fails. Reverse the first
6173 condition to get a true "inclusive-or" expression. */
6174 if (cond_or
== DOM_CC_NX_OR_Y
)
6175 cond1
= reverse_condition (cond1
);
6177 /* If the comparisons are not equal, and one doesn't dominate the other,
6178 then we can't do this. */
6180 && !comparison_dominates_p (cond1
, cond2
)
6181 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6186 enum rtx_code temp
= cond1
;
6194 if (cond2
== EQ
|| cond_or
== DOM_CC_X_AND_Y
)
6199 case LE
: return CC_DLEmode
;
6200 case LEU
: return CC_DLEUmode
;
6201 case GE
: return CC_DGEmode
;
6202 case GEU
: return CC_DGEUmode
;
6209 if (cond2
== LT
|| cond_or
== DOM_CC_X_AND_Y
)
6218 if (cond2
== GT
|| cond_or
== DOM_CC_X_AND_Y
)
6227 if (cond2
== LTU
|| cond_or
== DOM_CC_X_AND_Y
)
6236 if (cond2
== GTU
|| cond_or
== DOM_CC_X_AND_Y
)
6244 /* The remaining cases only occur when both comparisons are the
6269 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6271 /* All floating point compares return CCFP if it is an equality
6272 comparison, and CCFPE otherwise. */
6273 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6293 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6302 /* A compare with a shifted operand. Because of canonicalization, the
6303 comparison will have to be swapped when we emit the assembler. */
6304 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6305 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6306 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6307 || GET_CODE (x
) == ROTATERT
))
6310 /* This is a special case that is used by combine to allow a
6311 comparison of a shifted byte load to be split into a zero-extend
6312 followed by a comparison of the shifted integer (only valid for
6313 equalities and unsigned inequalities). */
6314 if (GET_MODE (x
) == SImode
6315 && GET_CODE (x
) == ASHIFT
6316 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6317 && GET_CODE (XEXP (x
, 0)) == SUBREG
6318 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6319 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6320 && (op
== EQ
|| op
== NE
6321 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6322 && GET_CODE (y
) == CONST_INT
)
6325 /* A construct for a conditional compare, if the false arm contains
6326 0, then both conditions must be true, otherwise either condition
6327 must be true. Not all conditions are possible, so CCmode is
6328 returned if it can't be done. */
6329 if (GET_CODE (x
) == IF_THEN_ELSE
6330 && (XEXP (x
, 2) == const0_rtx
6331 || XEXP (x
, 2) == const1_rtx
)
6332 && COMPARISON_P (XEXP (x
, 0))
6333 && COMPARISON_P (XEXP (x
, 1)))
6334 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6335 INTVAL (XEXP (x
, 2)));
6337 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6338 if (GET_CODE (x
) == AND
6339 && COMPARISON_P (XEXP (x
, 0))
6340 && COMPARISON_P (XEXP (x
, 1)))
6341 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6344 if (GET_CODE (x
) == IOR
6345 && COMPARISON_P (XEXP (x
, 0))
6346 && COMPARISON_P (XEXP (x
, 1)))
6347 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6350 /* An operation (on Thumb) where we want to test for a single bit.
6351 This is done by shifting that bit up into the top bit of a
6352 scratch register; we can then branch on the sign bit. */
6354 && GET_MODE (x
) == SImode
6355 && (op
== EQ
|| op
== NE
)
6356 && (GET_CODE (x
) == ZERO_EXTRACT
))
6359 /* An operation that sets the condition codes as a side-effect, the
6360 V flag is not set correctly, so we can only use comparisons where
6361 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6363 if (GET_MODE (x
) == SImode
6365 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6366 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6367 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6368 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6369 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6370 || GET_CODE (x
) == LSHIFTRT
6371 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6372 || GET_CODE (x
) == ROTATERT
6373 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6376 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6379 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6380 && GET_CODE (x
) == PLUS
6381 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6387 /* X and Y are two things to compare using CODE. Emit the compare insn and
6388 return the rtx for register 0 in the proper mode. FP means this is a
6389 floating point compare: I don't think that it is needed on the arm. */
6391 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6393 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6394 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6396 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6397 gen_rtx_COMPARE (mode
, x
, y
)));
6402 /* Generate a sequence of insns that will generate the correct return
6403 address mask depending on the physical architecture that the program
6406 arm_gen_return_addr_mask (void)
6408 rtx reg
= gen_reg_rtx (Pmode
);
6410 emit_insn (gen_return_addr_mask (reg
));
6415 arm_reload_in_hi (rtx
*operands
)
6417 rtx ref
= operands
[1];
6419 HOST_WIDE_INT offset
= 0;
6421 if (GET_CODE (ref
) == SUBREG
)
6423 offset
= SUBREG_BYTE (ref
);
6424 ref
= SUBREG_REG (ref
);
6427 if (GET_CODE (ref
) == REG
)
6429 /* We have a pseudo which has been spilt onto the stack; there
6430 are two cases here: the first where there is a simple
6431 stack-slot replacement and a second where the stack-slot is
6432 out of range, or is used as a subreg. */
6433 if (reg_equiv_mem
[REGNO (ref
)])
6435 ref
= reg_equiv_mem
[REGNO (ref
)];
6436 base
= find_replacement (&XEXP (ref
, 0));
6439 /* The slot is out of range, or was dressed up in a SUBREG. */
6440 base
= reg_equiv_address
[REGNO (ref
)];
6443 base
= find_replacement (&XEXP (ref
, 0));
6445 /* Handle the case where the address is too complex to be offset by 1. */
6446 if (GET_CODE (base
) == MINUS
6447 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6449 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6451 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6454 else if (GET_CODE (base
) == PLUS
)
6456 /* The addend must be CONST_INT, or we would have dealt with it above. */
6457 HOST_WIDE_INT hi
, lo
;
6459 offset
+= INTVAL (XEXP (base
, 1));
6460 base
= XEXP (base
, 0);
6462 /* Rework the address into a legal sequence of insns. */
6463 /* Valid range for lo is -4095 -> 4095 */
6466 : -((-offset
) & 0xfff));
6468 /* Corner case, if lo is the max offset then we would be out of range
6469 once we have added the additional 1 below, so bump the msb into the
6470 pre-loading insn(s). */
6474 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6475 ^ (HOST_WIDE_INT
) 0x80000000)
6476 - (HOST_WIDE_INT
) 0x80000000);
6478 if (hi
+ lo
!= offset
)
6483 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6485 /* Get the base address; addsi3 knows how to handle constants
6486 that require more than one insn. */
6487 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6493 /* Operands[2] may overlap operands[0] (though it won't overlap
6494 operands[1]), that's why we asked for a DImode reg -- so we can
6495 use the bit that does not overlap. */
6496 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6497 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6499 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6501 emit_insn (gen_zero_extendqisi2 (scratch
,
6502 gen_rtx_MEM (QImode
,
6503 plus_constant (base
,
6505 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6506 gen_rtx_MEM (QImode
,
6507 plus_constant (base
,
6509 if (!BYTES_BIG_ENDIAN
)
6510 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6511 gen_rtx_IOR (SImode
,
6514 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6518 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6519 gen_rtx_IOR (SImode
,
6520 gen_rtx_ASHIFT (SImode
, scratch
,
6522 gen_rtx_SUBREG (SImode
, operands
[0],
6526 /* Handle storing a half-word to memory during reload by synthesizing as two
6527 byte stores. Take care not to clobber the input values until after we
6528 have moved them somewhere safe. This code assumes that if the DImode
6529 scratch in operands[2] overlaps either the input value or output address
6530 in some way, then that value must die in this insn (we absolutely need
6531 two scratch registers for some corner cases). */
6533 arm_reload_out_hi (rtx
*operands
)
6535 rtx ref
= operands
[0];
6536 rtx outval
= operands
[1];
6538 HOST_WIDE_INT offset
= 0;
6540 if (GET_CODE (ref
) == SUBREG
)
6542 offset
= SUBREG_BYTE (ref
);
6543 ref
= SUBREG_REG (ref
);
6546 if (GET_CODE (ref
) == REG
)
6548 /* We have a pseudo which has been spilt onto the stack; there
6549 are two cases here: the first where there is a simple
6550 stack-slot replacement and a second where the stack-slot is
6551 out of range, or is used as a subreg. */
6552 if (reg_equiv_mem
[REGNO (ref
)])
6554 ref
= reg_equiv_mem
[REGNO (ref
)];
6555 base
= find_replacement (&XEXP (ref
, 0));
6558 /* The slot is out of range, or was dressed up in a SUBREG. */
6559 base
= reg_equiv_address
[REGNO (ref
)];
6562 base
= find_replacement (&XEXP (ref
, 0));
6564 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6566 /* Handle the case where the address is too complex to be offset by 1. */
6567 if (GET_CODE (base
) == MINUS
6568 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6570 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6572 /* Be careful not to destroy OUTVAL. */
6573 if (reg_overlap_mentioned_p (base_plus
, outval
))
6575 /* Updating base_plus might destroy outval, see if we can
6576 swap the scratch and base_plus. */
6577 if (!reg_overlap_mentioned_p (scratch
, outval
))
6580 scratch
= base_plus
;
6585 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6587 /* Be conservative and copy OUTVAL into the scratch now,
6588 this should only be necessary if outval is a subreg
6589 of something larger than a word. */
6590 /* XXX Might this clobber base? I can't see how it can,
6591 since scratch is known to overlap with OUTVAL, and
6592 must be wider than a word. */
6593 emit_insn (gen_movhi (scratch_hi
, outval
));
6594 outval
= scratch_hi
;
6598 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6601 else if (GET_CODE (base
) == PLUS
)
6603 /* The addend must be CONST_INT, or we would have dealt with it above. */
6604 HOST_WIDE_INT hi
, lo
;
6606 offset
+= INTVAL (XEXP (base
, 1));
6607 base
= XEXP (base
, 0);
6609 /* Rework the address into a legal sequence of insns. */
6610 /* Valid range for lo is -4095 -> 4095 */
6613 : -((-offset
) & 0xfff));
6615 /* Corner case, if lo is the max offset then we would be out of range
6616 once we have added the additional 1 below, so bump the msb into the
6617 pre-loading insn(s). */
6621 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6622 ^ (HOST_WIDE_INT
) 0x80000000)
6623 - (HOST_WIDE_INT
) 0x80000000);
6625 if (hi
+ lo
!= offset
)
6630 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6632 /* Be careful not to destroy OUTVAL. */
6633 if (reg_overlap_mentioned_p (base_plus
, outval
))
6635 /* Updating base_plus might destroy outval, see if we
6636 can swap the scratch and base_plus. */
6637 if (!reg_overlap_mentioned_p (scratch
, outval
))
6640 scratch
= base_plus
;
6645 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6647 /* Be conservative and copy outval into scratch now,
6648 this should only be necessary if outval is a
6649 subreg of something larger than a word. */
6650 /* XXX Might this clobber base? I can't see how it
6651 can, since scratch is known to overlap with
6653 emit_insn (gen_movhi (scratch_hi
, outval
));
6654 outval
= scratch_hi
;
6658 /* Get the base address; addsi3 knows how to handle constants
6659 that require more than one insn. */
6660 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6666 if (BYTES_BIG_ENDIAN
)
6668 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6669 plus_constant (base
, offset
+ 1)),
6670 gen_lowpart (QImode
, outval
)));
6671 emit_insn (gen_lshrsi3 (scratch
,
6672 gen_rtx_SUBREG (SImode
, outval
, 0),
6674 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6675 gen_lowpart (QImode
, scratch
)));
6679 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6680 gen_lowpart (QImode
, outval
)));
6681 emit_insn (gen_lshrsi3 (scratch
,
6682 gen_rtx_SUBREG (SImode
, outval
, 0),
6684 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6685 plus_constant (base
, offset
+ 1)),
6686 gen_lowpart (QImode
, scratch
)));
6690 /* Print a symbolic form of X to the debug file, F. */
6692 arm_print_value (FILE *f
, rtx x
)
6694 switch (GET_CODE (x
))
6697 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
6701 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
6709 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
6711 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
6712 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
6720 fprintf (f
, "\"%s\"", XSTR (x
, 0));
6724 fprintf (f
, "`%s'", XSTR (x
, 0));
6728 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
6732 arm_print_value (f
, XEXP (x
, 0));
6736 arm_print_value (f
, XEXP (x
, 0));
6738 arm_print_value (f
, XEXP (x
, 1));
6746 fprintf (f
, "????");
6751 /* Routines for manipulation of the constant pool. */
6753 /* Arm instructions cannot load a large constant directly into a
6754 register; they have to come from a pc relative load. The constant
6755 must therefore be placed in the addressable range of the pc
6756 relative load. Depending on the precise pc relative load
6757 instruction the range is somewhere between 256 bytes and 4k. This
6758 means that we often have to dump a constant inside a function, and
6759 generate code to branch around it.
6761 It is important to minimize this, since the branches will slow
6762 things down and make the code larger.
6764 Normally we can hide the table after an existing unconditional
6765 branch so that there is no interruption of the flow, but in the
6766 worst case the code looks like this:
6784 We fix this by performing a scan after scheduling, which notices
6785 which instructions need to have their operands fetched from the
6786 constant table and builds the table.
6788 The algorithm starts by building a table of all the constants that
6789 need fixing up and all the natural barriers in the function (places
6790 where a constant table can be dropped without breaking the flow).
6791 For each fixup we note how far the pc-relative replacement will be
6792 able to reach and the offset of the instruction into the function.
6794 Having built the table we then group the fixes together to form
6795 tables that are as large as possible (subject to addressing
6796 constraints) and emit each table of constants after the last
6797 barrier that is within range of all the instructions in the group.
6798 If a group does not contain a barrier, then we forcibly create one
6799 by inserting a jump instruction into the flow. Once the table has
6800 been inserted, the insns are then modified to reference the
6801 relevant entry in the pool.
6803 Possible enhancements to the algorithm (not implemented) are:
6805 1) For some processors and object formats, there may be benefit in
6806 aligning the pools to the start of cache lines; this alignment
6807 would need to be taken into account when calculating addressability
6810 /* These typedefs are located at the start of this file, so that
6811 they can be used in the prototypes there. This comment is to
6812 remind readers of that fact so that the following structures
6813 can be understood more easily.
6815 typedef struct minipool_node Mnode;
6816 typedef struct minipool_fixup Mfix; */
6818 struct minipool_node
6820 /* Doubly linked chain of entries. */
6823 /* The maximum offset into the code that this entry can be placed. While
6824 pushing fixes for forward references, all entries are sorted in order
6825 of increasing max_address. */
6826 HOST_WIDE_INT max_address
;
6827 /* Similarly for an entry inserted for a backwards ref. */
6828 HOST_WIDE_INT min_address
;
6829 /* The number of fixes referencing this entry. This can become zero
6830 if we "unpush" an entry. In this case we ignore the entry when we
6831 come to emit the code. */
6833 /* The offset from the start of the minipool. */
6834 HOST_WIDE_INT offset
;
6835 /* The value in table. */
6837 /* The mode of value. */
6838 enum machine_mode mode
;
6839 /* The size of the value. With iWMMXt enabled
6840 sizes > 4 also imply an alignment of 8-bytes. */
6844 struct minipool_fixup
6848 HOST_WIDE_INT address
;
6850 enum machine_mode mode
;
6854 HOST_WIDE_INT forwards
;
6855 HOST_WIDE_INT backwards
;
6858 /* Fixes less than a word need padding out to a word boundary. */
6859 #define MINIPOOL_FIX_SIZE(mode) \
6860 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6862 static Mnode
* minipool_vector_head
;
6863 static Mnode
* minipool_vector_tail
;
6864 static rtx minipool_vector_label
;
6866 /* The linked list of all minipool fixes required for this function. */
6867 Mfix
* minipool_fix_head
;
6868 Mfix
* minipool_fix_tail
;
6869 /* The fix entry for the current minipool, once it has been placed. */
6870 Mfix
* minipool_barrier
;
6872 /* Determines if INSN is the start of a jump table. Returns the end
6873 of the TABLE or NULL_RTX. */
6875 is_jump_table (rtx insn
)
6879 if (GET_CODE (insn
) == JUMP_INSN
6880 && JUMP_LABEL (insn
) != NULL
6881 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
6882 == next_real_insn (insn
))
6884 && GET_CODE (table
) == JUMP_INSN
6885 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
6886 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
6892 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6893 #define JUMP_TABLES_IN_TEXT_SECTION 0
6896 static HOST_WIDE_INT
6897 get_jump_table_size (rtx insn
)
6899 /* ADDR_VECs only take room if read-only data does into the text
6901 if (JUMP_TABLES_IN_TEXT_SECTION
6902 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6907 rtx body
= PATTERN (insn
);
6908 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
6910 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
6916 /* Move a minipool fix MP from its current location to before MAX_MP.
6917 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6918 constraints may need updating. */
6920 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
6921 HOST_WIDE_INT max_address
)
6923 /* This should never be true and the code below assumes these are
6930 if (max_address
< mp
->max_address
)
6931 mp
->max_address
= max_address
;
6935 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6936 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6938 mp
->max_address
= max_address
;
6940 /* Unlink MP from its current position. Since max_mp is non-null,
6941 mp->prev must be non-null. */
6942 mp
->prev
->next
= mp
->next
;
6943 if (mp
->next
!= NULL
)
6944 mp
->next
->prev
= mp
->prev
;
6946 minipool_vector_tail
= mp
->prev
;
6948 /* Re-insert it before MAX_MP. */
6950 mp
->prev
= max_mp
->prev
;
6953 if (mp
->prev
!= NULL
)
6954 mp
->prev
->next
= mp
;
6956 minipool_vector_head
= mp
;
6959 /* Save the new entry. */
6962 /* Scan over the preceding entries and adjust their addresses as
6964 while (mp
->prev
!= NULL
6965 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6967 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6974 /* Add a constant to the minipool for a forward reference. Returns the
6975 node added or NULL if the constant will not fit in this pool. */
6977 add_minipool_forward_ref (Mfix
*fix
)
6979 /* If set, max_mp is the first pool_entry that has a lower
6980 constraint than the one we are trying to add. */
6981 Mnode
* max_mp
= NULL
;
6982 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
6985 /* If this fix's address is greater than the address of the first
6986 entry, then we can't put the fix in this pool. We subtract the
6987 size of the current fix to ensure that if the table is fully
6988 packed we still have enough room to insert this value by suffling
6989 the other fixes forwards. */
6990 if (minipool_vector_head
&&
6991 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
6994 /* Scan the pool to see if a constant with the same value has
6995 already been added. While we are doing this, also note the
6996 location where we must insert the constant if it doesn't already
6998 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7000 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7001 && fix
->mode
== mp
->mode
7002 && (GET_CODE (fix
->value
) != CODE_LABEL
7003 || (CODE_LABEL_NUMBER (fix
->value
)
7004 == CODE_LABEL_NUMBER (mp
->value
)))
7005 && rtx_equal_p (fix
->value
, mp
->value
))
7007 /* More than one fix references this entry. */
7009 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7012 /* Note the insertion point if necessary. */
7014 && mp
->max_address
> max_address
)
7017 /* If we are inserting an 8-bytes aligned quantity and
7018 we have not already found an insertion point, then
7019 make sure that all such 8-byte aligned quantities are
7020 placed at the start of the pool. */
7021 if (ARM_DOUBLEWORD_ALIGN
7023 && fix
->fix_size
== 8
7024 && mp
->fix_size
!= 8)
7027 max_address
= mp
->max_address
;
7031 /* The value is not currently in the minipool, so we need to create
7032 a new entry for it. If MAX_MP is NULL, the entry will be put on
7033 the end of the list since the placement is less constrained than
7034 any existing entry. Otherwise, we insert the new fix before
7035 MAX_MP and, if necessary, adjust the constraints on the other
7037 mp
= xmalloc (sizeof (* mp
));
7038 mp
->fix_size
= fix
->fix_size
;
7039 mp
->mode
= fix
->mode
;
7040 mp
->value
= fix
->value
;
7042 /* Not yet required for a backwards ref. */
7043 mp
->min_address
= -65536;
7047 mp
->max_address
= max_address
;
7049 mp
->prev
= minipool_vector_tail
;
7051 if (mp
->prev
== NULL
)
7053 minipool_vector_head
= mp
;
7054 minipool_vector_label
= gen_label_rtx ();
7057 mp
->prev
->next
= mp
;
7059 minipool_vector_tail
= mp
;
7063 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7064 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7066 mp
->max_address
= max_address
;
7069 mp
->prev
= max_mp
->prev
;
7071 if (mp
->prev
!= NULL
)
7072 mp
->prev
->next
= mp
;
7074 minipool_vector_head
= mp
;
7077 /* Save the new entry. */
7080 /* Scan over the preceding entries and adjust their addresses as
7082 while (mp
->prev
!= NULL
7083 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7085 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7093 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7094 HOST_WIDE_INT min_address
)
7096 HOST_WIDE_INT offset
;
7098 /* This should never be true, and the code below assumes these are
7105 if (min_address
> mp
->min_address
)
7106 mp
->min_address
= min_address
;
7110 /* We will adjust this below if it is too loose. */
7111 mp
->min_address
= min_address
;
7113 /* Unlink MP from its current position. Since min_mp is non-null,
7114 mp->next must be non-null. */
7115 mp
->next
->prev
= mp
->prev
;
7116 if (mp
->prev
!= NULL
)
7117 mp
->prev
->next
= mp
->next
;
7119 minipool_vector_head
= mp
->next
;
7121 /* Reinsert it after MIN_MP. */
7123 mp
->next
= min_mp
->next
;
7125 if (mp
->next
!= NULL
)
7126 mp
->next
->prev
= mp
;
7128 minipool_vector_tail
= mp
;
7134 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7136 mp
->offset
= offset
;
7137 if (mp
->refcount
> 0)
7138 offset
+= mp
->fix_size
;
7140 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7141 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7147 /* Add a constant to the minipool for a backward reference. Returns the
7148 node added or NULL if the constant will not fit in this pool.
7150 Note that the code for insertion for a backwards reference can be
7151 somewhat confusing because the calculated offsets for each fix do
7152 not take into account the size of the pool (which is still under
7155 add_minipool_backward_ref (Mfix
*fix
)
7157 /* If set, min_mp is the last pool_entry that has a lower constraint
7158 than the one we are trying to add. */
7159 Mnode
*min_mp
= NULL
;
7160 /* This can be negative, since it is only a constraint. */
7161 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7164 /* If we can't reach the current pool from this insn, or if we can't
7165 insert this entry at the end of the pool without pushing other
7166 fixes out of range, then we don't try. This ensures that we
7167 can't fail later on. */
7168 if (min_address
>= minipool_barrier
->address
7169 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7170 >= minipool_barrier
->address
))
7173 /* Scan the pool to see if a constant with the same value has
7174 already been added. While we are doing this, also note the
7175 location where we must insert the constant if it doesn't already
7177 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7179 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7180 && fix
->mode
== mp
->mode
7181 && (GET_CODE (fix
->value
) != CODE_LABEL
7182 || (CODE_LABEL_NUMBER (fix
->value
)
7183 == CODE_LABEL_NUMBER (mp
->value
)))
7184 && rtx_equal_p (fix
->value
, mp
->value
)
7185 /* Check that there is enough slack to move this entry to the
7186 end of the table (this is conservative). */
7188 > (minipool_barrier
->address
7189 + minipool_vector_tail
->offset
7190 + minipool_vector_tail
->fix_size
)))
7193 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7197 mp
->min_address
+= fix
->fix_size
;
7200 /* Note the insertion point if necessary. */
7201 if (mp
->min_address
< min_address
)
7203 /* For now, we do not allow the insertion of 8-byte alignment
7204 requiring nodes anywhere but at the start of the pool. */
7205 if (ARM_DOUBLEWORD_ALIGN
7206 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7211 else if (mp
->max_address
7212 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7214 /* Inserting before this entry would push the fix beyond
7215 its maximum address (which can happen if we have
7216 re-located a forwards fix); force the new fix to come
7219 min_address
= mp
->min_address
+ fix
->fix_size
;
7221 /* If we are inserting an 8-bytes aligned quantity and
7222 we have not already found an insertion point, then
7223 make sure that all such 8-byte aligned quantities are
7224 placed at the start of the pool. */
7225 else if (ARM_DOUBLEWORD_ALIGN
7227 && fix
->fix_size
== 8
7228 && mp
->fix_size
< 8)
7231 min_address
= mp
->min_address
+ fix
->fix_size
;
7236 /* We need to create a new entry. */
7237 mp
= xmalloc (sizeof (* mp
));
7238 mp
->fix_size
= fix
->fix_size
;
7239 mp
->mode
= fix
->mode
;
7240 mp
->value
= fix
->value
;
7242 mp
->max_address
= minipool_barrier
->address
+ 65536;
7244 mp
->min_address
= min_address
;
7249 mp
->next
= minipool_vector_head
;
7251 if (mp
->next
== NULL
)
7253 minipool_vector_tail
= mp
;
7254 minipool_vector_label
= gen_label_rtx ();
7257 mp
->next
->prev
= mp
;
7259 minipool_vector_head
= mp
;
7263 mp
->next
= min_mp
->next
;
7267 if (mp
->next
!= NULL
)
7268 mp
->next
->prev
= mp
;
7270 minipool_vector_tail
= mp
;
7273 /* Save the new entry. */
7281 /* Scan over the following entries and adjust their offsets. */
7282 while (mp
->next
!= NULL
)
7284 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7285 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7288 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7290 mp
->next
->offset
= mp
->offset
;
7299 assign_minipool_offsets (Mfix
*barrier
)
7301 HOST_WIDE_INT offset
= 0;
7304 minipool_barrier
= barrier
;
7306 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7308 mp
->offset
= offset
;
7310 if (mp
->refcount
> 0)
7311 offset
+= mp
->fix_size
;
7315 /* Output the literal table */
7317 dump_minipool (rtx scan
)
7323 if (ARM_DOUBLEWORD_ALIGN
)
7324 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7325 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7333 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7334 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7336 scan
= emit_label_after (gen_label_rtx (), scan
);
7337 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7338 scan
= emit_label_after (minipool_vector_label
, scan
);
7340 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7342 if (mp
->refcount
> 0)
7347 ";; Offset %u, min %ld, max %ld ",
7348 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7349 (unsigned long) mp
->max_address
);
7350 arm_print_value (dump_file
, mp
->value
);
7351 fputc ('\n', dump_file
);
7354 switch (mp
->fix_size
)
7356 #ifdef HAVE_consttable_1
7358 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7362 #ifdef HAVE_consttable_2
7364 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7368 #ifdef HAVE_consttable_4
7370 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7374 #ifdef HAVE_consttable_8
7376 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7390 minipool_vector_head
= minipool_vector_tail
= NULL
;
7391 scan
= emit_insn_after (gen_consttable_end (), scan
);
7392 scan
= emit_barrier_after (scan
);
7395 /* Return the cost of forcibly inserting a barrier after INSN. */
7397 arm_barrier_cost (rtx insn
)
7399 /* Basing the location of the pool on the loop depth is preferable,
7400 but at the moment, the basic block information seems to be
7401 corrupt by this stage of the compilation. */
7403 rtx next
= next_nonnote_insn (insn
);
7405 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7408 switch (GET_CODE (insn
))
7411 /* It will always be better to place the table before the label, rather
7420 return base_cost
- 10;
7423 return base_cost
+ 10;
7427 /* Find the best place in the insn stream in the range
7428 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7429 Create the barrier by inserting a jump and add a new fix entry for
7432 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7434 HOST_WIDE_INT count
= 0;
7436 rtx from
= fix
->insn
;
7437 rtx selected
= from
;
7439 HOST_WIDE_INT selected_address
;
7441 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7442 rtx label
= gen_label_rtx ();
7444 selected_cost
= arm_barrier_cost (from
);
7445 selected_address
= fix
->address
;
7447 while (from
&& count
< max_count
)
7452 /* This code shouldn't have been called if there was a natural barrier
7454 if (GET_CODE (from
) == BARRIER
)
7457 /* Count the length of this insn. */
7458 count
+= get_attr_length (from
);
7460 /* If there is a jump table, add its length. */
7461 tmp
= is_jump_table (from
);
7464 count
+= get_jump_table_size (tmp
);
7466 /* Jump tables aren't in a basic block, so base the cost on
7467 the dispatch insn. If we select this location, we will
7468 still put the pool after the table. */
7469 new_cost
= arm_barrier_cost (from
);
7471 if (count
< max_count
&& new_cost
<= selected_cost
)
7474 selected_cost
= new_cost
;
7475 selected_address
= fix
->address
+ count
;
7478 /* Continue after the dispatch table. */
7479 from
= NEXT_INSN (tmp
);
7483 new_cost
= arm_barrier_cost (from
);
7485 if (count
< max_count
&& new_cost
<= selected_cost
)
7488 selected_cost
= new_cost
;
7489 selected_address
= fix
->address
+ count
;
7492 from
= NEXT_INSN (from
);
7495 /* Create a new JUMP_INSN that branches around a barrier. */
7496 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7497 JUMP_LABEL (from
) = label
;
7498 barrier
= emit_barrier_after (from
);
7499 emit_label_after (label
, barrier
);
7501 /* Create a minipool barrier entry for the new barrier. */
7502 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7503 new_fix
->insn
= barrier
;
7504 new_fix
->address
= selected_address
;
7505 new_fix
->next
= fix
->next
;
7506 fix
->next
= new_fix
;
7511 /* Record that there is a natural barrier in the insn stream at
7514 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7516 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7519 fix
->address
= address
;
7522 if (minipool_fix_head
!= NULL
)
7523 minipool_fix_tail
->next
= fix
;
7525 minipool_fix_head
= fix
;
7527 minipool_fix_tail
= fix
;
7530 /* Record INSN, which will need fixing up to load a value from the
7531 minipool. ADDRESS is the offset of the insn since the start of the
7532 function; LOC is a pointer to the part of the insn which requires
7533 fixing; VALUE is the constant that must be loaded, which is of type
7536 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7537 enum machine_mode mode
, rtx value
)
7539 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7541 #ifdef AOF_ASSEMBLER
7542 /* PIC symbol references need to be converted into offsets into the
7544 /* XXX This shouldn't be done here. */
7545 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7546 value
= aof_pic_entry (value
);
7547 #endif /* AOF_ASSEMBLER */
7550 fix
->address
= address
;
7553 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7555 fix
->forwards
= get_attr_pool_range (insn
);
7556 fix
->backwards
= get_attr_neg_pool_range (insn
);
7557 fix
->minipool
= NULL
;
7559 /* If an insn doesn't have a range defined for it, then it isn't
7560 expecting to be reworked by this code. Better to abort now than
7561 to generate duff assembly code. */
7562 if (fix
->forwards
== 0 && fix
->backwards
== 0)
7565 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7566 So there might be an empty word before the start of the pool.
7567 Hence we reduce the forward range by 4 to allow for this
7569 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
7575 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7576 GET_MODE_NAME (mode
),
7577 INSN_UID (insn
), (unsigned long) address
,
7578 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
7579 arm_print_value (dump_file
, fix
->value
);
7580 fprintf (dump_file
, "\n");
7583 /* Add it to the chain of fixes. */
7586 if (minipool_fix_head
!= NULL
)
7587 minipool_fix_tail
->next
= fix
;
7589 minipool_fix_head
= fix
;
7591 minipool_fix_tail
= fix
;
7594 /* Scan INSN and note any of its operands that need fixing.
7595 If DO_PUSHES is false we do not actually push any of the fixups
7596 needed. The function returns TRUE is any fixups were needed/pushed.
7597 This is used by arm_memory_load_p() which needs to know about loads
7598 of constants that will be converted into minipool loads. */
7600 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
7602 bool result
= false;
7605 extract_insn (insn
);
7607 if (!constrain_operands (1))
7608 fatal_insn_not_found (insn
);
7610 if (recog_data
.n_alternatives
== 0)
7613 /* Fill in recog_op_alt with information about the constraints of this insn. */
7614 preprocess_constraints ();
7616 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
7618 /* Things we need to fix can only occur in inputs. */
7619 if (recog_data
.operand_type
[opno
] != OP_IN
)
7622 /* If this alternative is a memory reference, then any mention
7623 of constants in this alternative is really to fool reload
7624 into allowing us to accept one there. We need to fix them up
7625 now so that we output the right code. */
7626 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
7628 rtx op
= recog_data
.operand
[opno
];
7630 if (CONSTANT_P (op
))
7633 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
7634 recog_data
.operand_mode
[opno
], op
);
7637 else if (GET_CODE (op
) == MEM
7638 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
7639 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
7643 rtx cop
= avoid_constant_pool_reference (op
);
7645 /* Casting the address of something to a mode narrower
7646 than a word can cause avoid_constant_pool_reference()
7647 to return the pool reference itself. That's no good to
7648 us here. Lets just hope that we can use the
7649 constant pool value directly. */
7651 cop
= get_pool_constant (XEXP (op
, 0));
7653 push_minipool_fix (insn
, address
,
7654 recog_data
.operand_loc
[opno
],
7655 recog_data
.operand_mode
[opno
], cop
);
7666 /* Gcc puts the pool in the wrong place for ARM, since we can only
7667 load addresses a limited distance around the pc. We do some
7668 special munging to move the constant pool values to the correct
7669 point in the code. */
7674 HOST_WIDE_INT address
= 0;
7677 minipool_fix_head
= minipool_fix_tail
= NULL
;
7679 /* The first insn must always be a note, or the code below won't
7680 scan it properly. */
7681 insn
= get_insns ();
7682 if (GET_CODE (insn
) != NOTE
)
7685 /* Scan all the insns and record the operands that will need fixing. */
7686 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
7688 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7689 && (arm_cirrus_insn_p (insn
)
7690 || GET_CODE (insn
) == JUMP_INSN
7691 || arm_memory_load_p (insn
)))
7692 cirrus_reorg (insn
);
7694 if (GET_CODE (insn
) == BARRIER
)
7695 push_minipool_barrier (insn
, address
);
7696 else if (INSN_P (insn
))
7700 note_invalid_constants (insn
, address
, true);
7701 address
+= get_attr_length (insn
);
7703 /* If the insn is a vector jump, add the size of the table
7704 and skip the table. */
7705 if ((table
= is_jump_table (insn
)) != NULL
)
7707 address
+= get_jump_table_size (table
);
7713 fix
= minipool_fix_head
;
7715 /* Now scan the fixups and perform the required changes. */
7720 Mfix
* last_added_fix
;
7721 Mfix
* last_barrier
= NULL
;
7724 /* Skip any further barriers before the next fix. */
7725 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
7728 /* No more fixes. */
7732 last_added_fix
= NULL
;
7734 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
7736 if (GET_CODE (ftmp
->insn
) == BARRIER
)
7738 if (ftmp
->address
>= minipool_vector_head
->max_address
)
7741 last_barrier
= ftmp
;
7743 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
7746 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
7749 /* If we found a barrier, drop back to that; any fixes that we
7750 could have reached but come after the barrier will now go in
7751 the next mini-pool. */
7752 if (last_barrier
!= NULL
)
7754 /* Reduce the refcount for those fixes that won't go into this
7756 for (fdel
= last_barrier
->next
;
7757 fdel
&& fdel
!= ftmp
;
7760 fdel
->minipool
->refcount
--;
7761 fdel
->minipool
= NULL
;
7764 ftmp
= last_barrier
;
7768 /* ftmp is first fix that we can't fit into this pool and
7769 there no natural barriers that we could use. Insert a
7770 new barrier in the code somewhere between the previous
7771 fix and this one, and arrange to jump around it. */
7772 HOST_WIDE_INT max_address
;
7774 /* The last item on the list of fixes must be a barrier, so
7775 we can never run off the end of the list of fixes without
7776 last_barrier being set. */
7780 max_address
= minipool_vector_head
->max_address
;
7781 /* Check that there isn't another fix that is in range that
7782 we couldn't fit into this pool because the pool was
7783 already too large: we need to put the pool before such an
7785 if (ftmp
->address
< max_address
)
7786 max_address
= ftmp
->address
;
7788 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
7791 assign_minipool_offsets (last_barrier
);
7795 if (GET_CODE (ftmp
->insn
) != BARRIER
7796 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
7803 /* Scan over the fixes we have identified for this pool, fixing them
7804 up and adding the constants to the pool itself. */
7805 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
7806 this_fix
= this_fix
->next
)
7807 if (GET_CODE (this_fix
->insn
) != BARRIER
)
7810 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
7811 minipool_vector_label
),
7812 this_fix
->minipool
->offset
);
7813 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
7816 dump_minipool (last_barrier
->insn
);
7820 /* From now on we must synthesize any constants that we can't handle
7821 directly. This can happen if the RTL gets split during final
7822 instruction generation. */
7823 after_arm_reorg
= 1;
7825 /* Free the minipool memory. */
7826 obstack_free (&minipool_obstack
, minipool_startobj
);
7829 /* Routines to output assembly language. */
7831 /* If the rtx is the correct value then return the string of the number.
7832 In this way we can ensure that valid double constants are generated even
7833 when cross compiling. */
7835 fp_immediate_constant (rtx x
)
7840 if (!fp_consts_inited
)
7843 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7844 for (i
= 0; i
< 8; i
++)
7845 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
7846 return strings_fp
[i
];
7851 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7853 fp_const_from_val (REAL_VALUE_TYPE
*r
)
7857 if (!fp_consts_inited
)
7860 for (i
= 0; i
< 8; i
++)
7861 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
7862 return strings_fp
[i
];
7867 /* Output the operands of a LDM/STM instruction to STREAM.
7868 MASK is the ARM register set mask of which only bits 0-15 are important.
7869 REG is the base register, either the frame pointer or the stack pointer,
7870 INSTR is the possibly suffixed load or store instruction. */
7872 print_multi_reg (FILE *stream
, const char *instr
, int reg
, int mask
)
7875 int not_first
= FALSE
;
7877 fputc ('\t', stream
);
7878 asm_fprintf (stream
, instr
, reg
);
7879 fputs (", {", stream
);
7881 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7882 if (mask
& (1 << i
))
7885 fprintf (stream
, ", ");
7887 asm_fprintf (stream
, "%r", i
);
7891 fprintf (stream
, "}");
7893 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7894 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7895 Strictly speaking the instruction would be unpredictable only if
7896 we were writing back the base register as well, but since we never
7897 want to generate an LDM type 2 instruction (register bank switching)
7898 which is what you get if the PC is not being loaded, we do not need
7899 to check for writeback. */
7900 if (! TARGET_APCS_32
7901 && ((mask
& (1 << PC_REGNUM
)) != 0))
7902 fprintf (stream
, "^");
7904 fprintf (stream
, "\n");
7908 /* Output a FLDMX instruction to STREAM.
7909 BASE if the register containing the address.
7910 REG and COUNT specify the register range.
7911 Extra registers may be added to avoid hardware bugs. */
7914 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
7918 /* Workaround ARM10 VFPr1 bug. */
7919 if (count
== 2 && !arm_arch6
)
7926 fputc ('\t', stream
);
7927 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
7929 for (i
= reg
; i
< reg
+ count
; i
++)
7932 fputs (", ", stream
);
7933 asm_fprintf (stream
, "d%d", i
);
7935 fputs ("}\n", stream
);
7940 /* Output the assembly for a store multiple. */
7943 vfp_output_fstmx (rtx
* operands
)
7950 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
7951 p
= strlen (pattern
);
7953 if (GET_CODE (operands
[1]) != REG
)
7956 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
7957 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
7959 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
7961 strcpy (&pattern
[p
], "}");
7963 output_asm_insn (pattern
, operands
);
7968 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7969 number of bytes pushed. */
7972 vfp_emit_fstmx (int base_reg
, int count
)
7979 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7980 register pairs are stored by a store multiple insn. We avoid this
7981 by pushing an extra pair. */
7982 if (count
== 2 && !arm_arch6
)
7984 if (base_reg
== LAST_VFP_REGNUM
- 3)
7989 /* ??? The frame layout is implementation defined. We describe
7990 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7991 We really need some way of representing the whole block so that the
7992 unwinder can figure it out at runtime. */
7993 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
7994 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
7996 reg
= gen_rtx_REG (DFmode
, base_reg
);
8000 = gen_rtx_SET (VOIDmode
,
8001 gen_rtx_MEM (BLKmode
,
8002 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8003 gen_rtx_UNSPEC (BLKmode
,
8007 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8008 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8009 GEN_INT (-(count
* 8 + 4))));
8010 RTX_FRAME_RELATED_P (tmp
) = 1;
8011 XVECEXP (dwarf
, 0, 0) = tmp
;
8013 tmp
= gen_rtx_SET (VOIDmode
,
8014 gen_rtx_MEM (DFmode
, stack_pointer_rtx
),
8016 RTX_FRAME_RELATED_P (tmp
) = 1;
8017 XVECEXP (dwarf
, 0, 1) = tmp
;
8019 for (i
= 1; i
< count
; i
++)
8021 reg
= gen_rtx_REG (DFmode
, base_reg
);
8023 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8025 tmp
= gen_rtx_SET (VOIDmode
,
8026 gen_rtx_MEM (DFmode
,
8027 gen_rtx_PLUS (SImode
,
8031 RTX_FRAME_RELATED_P (tmp
) = 1;
8032 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8035 par
= emit_insn (par
);
8036 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8038 RTX_FRAME_RELATED_P (par
) = 1;
8040 return count
* 8 + 4;
8044 /* Output a 'call' insn. */
8046 output_call (rtx
*operands
)
8048 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8050 if (REGNO (operands
[0]) == LR_REGNUM
)
8052 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8053 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8056 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8058 if (TARGET_INTERWORK
)
8059 output_asm_insn ("bx%?\t%0", operands
);
8061 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8066 /* Output a 'call' insn that is a reference in memory. */
8068 output_call_mem (rtx
*operands
)
8070 if (TARGET_INTERWORK
)
8072 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8073 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8074 output_asm_insn ("bx%?\t%|ip", operands
);
8076 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8078 /* LR is used in the memory address. We load the address in the
8079 first instruction. It's safe to use IP as the target of the
8080 load since the call will kill it anyway. */
8081 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8082 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8083 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8087 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8088 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8095 /* Output a move from arm registers to an fpa registers.
8096 OPERANDS[0] is an fpa register.
8097 OPERANDS[1] is the first registers of an arm register pair. */
8099 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8101 int arm_reg0
= REGNO (operands
[1]);
8104 if (arm_reg0
== IP_REGNUM
)
8107 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8108 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8109 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8111 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8112 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8117 /* Output a move from an fpa register to arm registers.
8118 OPERANDS[0] is the first registers of an arm register pair.
8119 OPERANDS[1] is an fpa register. */
8121 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8123 int arm_reg0
= REGNO (operands
[0]);
8126 if (arm_reg0
== IP_REGNUM
)
8129 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8130 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8131 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8133 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8134 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8138 /* Output a move from arm registers to arm registers of a long double
8139 OPERANDS[0] is the destination.
8140 OPERANDS[1] is the source. */
8142 output_mov_long_double_arm_from_arm (rtx
*operands
)
8144 /* We have to be careful here because the two might overlap. */
8145 int dest_start
= REGNO (operands
[0]);
8146 int src_start
= REGNO (operands
[1]);
8150 if (dest_start
< src_start
)
8152 for (i
= 0; i
< 3; i
++)
8154 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8155 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8156 output_asm_insn ("mov%?\t%0, %1", ops
);
8161 for (i
= 2; i
>= 0; i
--)
8163 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8164 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8165 output_asm_insn ("mov%?\t%0, %1", ops
);
8173 /* Output a move from arm registers to an fpa registers.
8174 OPERANDS[0] is an fpa register.
8175 OPERANDS[1] is the first registers of an arm register pair. */
8177 output_mov_double_fpa_from_arm (rtx
*operands
)
8179 int arm_reg0
= REGNO (operands
[1]);
8182 if (arm_reg0
== IP_REGNUM
)
8185 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8186 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8187 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8188 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8192 /* Output a move from an fpa register to arm registers.
8193 OPERANDS[0] is the first registers of an arm register pair.
8194 OPERANDS[1] is an fpa register. */
8196 output_mov_double_arm_from_fpa (rtx
*operands
)
8198 int arm_reg0
= REGNO (operands
[0]);
8201 if (arm_reg0
== IP_REGNUM
)
8204 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8205 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8206 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8207 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8211 /* Output a move between double words.
8212 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8213 or MEM<-REG and all MEMs must be offsettable addresses. */
8215 output_move_double (rtx
*operands
)
8217 enum rtx_code code0
= GET_CODE (operands
[0]);
8218 enum rtx_code code1
= GET_CODE (operands
[1]);
8223 int reg0
= REGNO (operands
[0]);
8225 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8229 int reg1
= REGNO (operands
[1]);
8230 if (reg1
== IP_REGNUM
)
8233 /* Ensure the second source is not overwritten. */
8234 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
8235 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
8237 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
8239 else if (code1
== CONST_VECTOR
)
8241 HOST_WIDE_INT hint
= 0;
8243 switch (GET_MODE (operands
[1]))
8246 otherops
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 1)));
8247 operands
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 0)));
8251 if (BYTES_BIG_ENDIAN
)
8253 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8255 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8259 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8261 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8264 otherops
[1] = GEN_INT (hint
);
8267 if (BYTES_BIG_ENDIAN
)
8269 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8271 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8275 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8277 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8280 operands
[1] = GEN_INT (hint
);
8284 if (BYTES_BIG_ENDIAN
)
8286 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
8288 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
8290 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
8292 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
8296 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
8298 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
8300 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
8302 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
8305 otherops
[1] = GEN_INT (hint
);
8308 if (BYTES_BIG_ENDIAN
)
8310 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8312 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8314 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8316 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8320 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8322 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8324 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8326 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8329 operands
[1] = GEN_INT (hint
);
8335 output_mov_immediate (operands
);
8336 output_mov_immediate (otherops
);
8338 else if (code1
== CONST_DOUBLE
)
8340 if (GET_MODE (operands
[1]) == DFmode
)
8345 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
8346 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
8347 otherops
[1] = GEN_INT (l
[1]);
8348 operands
[1] = GEN_INT (l
[0]);
8350 else if (GET_MODE (operands
[1]) != VOIDmode
)
8352 else if (WORDS_BIG_ENDIAN
)
8354 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
8355 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
8359 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
8360 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
8363 output_mov_immediate (operands
);
8364 output_mov_immediate (otherops
);
8366 else if (code1
== CONST_INT
)
8368 #if HOST_BITS_PER_WIDE_INT > 32
8369 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8370 what the upper word is. */
8371 if (WORDS_BIG_ENDIAN
)
8373 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
8374 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
8378 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
8379 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
8382 /* Sign extend the intval into the high-order word. */
8383 if (WORDS_BIG_ENDIAN
)
8385 otherops
[1] = operands
[1];
8386 operands
[1] = (INTVAL (operands
[1]) < 0
8387 ? constm1_rtx
: const0_rtx
);
8390 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
8392 output_mov_immediate (otherops
);
8393 output_mov_immediate (operands
);
8395 else if (code1
== MEM
)
8397 switch (GET_CODE (XEXP (operands
[1], 0)))
8400 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8405 abort (); /* Should never happen now. */
8406 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8410 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8414 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8419 abort (); /* Should never happen now. */
8420 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8425 otherops
[0] = operands
[0];
8426 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8427 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8429 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8431 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8433 /* Registers overlap so split out the increment. */
8434 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8435 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8438 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8442 /* We only allow constant increments, so this is safe. */
8443 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8449 output_asm_insn ("adr%?\t%0, %1", operands
);
8450 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8454 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8455 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8457 otherops
[0] = operands
[0];
8458 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8459 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8461 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8463 if (GET_CODE (otherops
[2]) == CONST_INT
)
8465 switch ((int) INTVAL (otherops
[2]))
8468 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8471 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8474 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8479 && (GET_CODE (otherops
[2]) == REG
8480 || (GET_CODE (otherops
[2]) == CONST_INT
8481 && INTVAL (otherops
[2]) > -256
8482 && INTVAL (otherops
[2]) < 256)))
8484 if (reg_overlap_mentioned_p (otherops
[0],
8487 /* Swap base and index registers over to
8488 avoid a conflict. */
8489 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8490 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8493 /* If both registers conflict, it will usually
8494 have been fixed by a splitter. */
8495 if (reg_overlap_mentioned_p (otherops
[0],
8498 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8499 output_asm_insn ("ldr%?d\t%0, [%1]",
8505 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8510 if (GET_CODE (otherops
[2]) == CONST_INT
)
8512 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8513 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8515 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8518 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8521 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8523 return "ldm%?ia\t%0, %M0";
8527 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8528 /* Take care of overlapping base/data reg. */
8529 if (reg_mentioned_p (operands
[0], operands
[1]))
8531 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8532 output_asm_insn ("ldr%?\t%0, %1", operands
);
8536 output_asm_insn ("ldr%?\t%0, %1", operands
);
8537 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8543 abort (); /* Constraints should prevent this. */
8545 else if (code0
== MEM
&& code1
== REG
)
8547 if (REGNO (operands
[1]) == IP_REGNUM
)
8550 switch (GET_CODE (XEXP (operands
[0], 0)))
8553 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8558 abort (); /* Should never happen now. */
8559 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8563 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8567 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8572 abort (); /* Should never happen now. */
8573 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8578 otherops
[0] = operands
[1];
8579 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8580 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8582 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8583 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8585 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8589 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8590 if (GET_CODE (otherops
[2]) == CONST_INT
)
8592 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8595 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8599 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8603 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8608 && (GET_CODE (otherops
[2]) == REG
8609 || (GET_CODE (otherops
[2]) == CONST_INT
8610 && INTVAL (otherops
[2]) > -256
8611 && INTVAL (otherops
[2]) < 256)))
8613 otherops
[0] = operands
[1];
8614 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8615 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8621 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8622 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8623 output_asm_insn ("str%?\t%1, %0", operands
);
8624 output_asm_insn ("str%?\t%1, %0", otherops
);
8628 /* Constraints should prevent this. */
8635 /* Output an arbitrary MOV reg, #n.
8636 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8638 output_mov_immediate (rtx
*operands
)
8640 HOST_WIDE_INT n
= INTVAL (operands
[1]);
8642 /* Try to use one MOV. */
8643 if (const_ok_for_arm (n
))
8644 output_asm_insn ("mov%?\t%0, %1", operands
);
8646 /* Try to use one MVN. */
8647 else if (const_ok_for_arm (~n
))
8649 operands
[1] = GEN_INT (~n
);
8650 output_asm_insn ("mvn%?\t%0, %1", operands
);
8657 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8658 for (i
= 0; i
< 32; i
++)
8662 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
8663 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n
);
8665 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
8671 /* Output an ADD r, s, #n where n may be too big for one instruction.
8672 If adding zero to one register, output nothing. */
8674 output_add_immediate (rtx
*operands
)
8676 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8678 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8681 output_multi_immediate (operands
,
8682 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8685 output_multi_immediate (operands
,
8686 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8693 /* Output a multiple immediate operation.
8694 OPERANDS is the vector of operands referred to in the output patterns.
8695 INSTR1 is the output pattern to use for the first constant.
8696 INSTR2 is the output pattern to use for subsequent constants.
8697 IMMED_OP is the index of the constant slot in OPERANDS.
8698 N is the constant value. */
8700 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8701 int immed_op
, HOST_WIDE_INT n
)
8703 #if HOST_BITS_PER_WIDE_INT > 32
8709 /* Quick and easy output. */
8710 operands
[immed_op
] = const0_rtx
;
8711 output_asm_insn (instr1
, operands
);
8716 const char * instr
= instr1
;
8718 /* Note that n is never zero here (which would give no output). */
8719 for (i
= 0; i
< 32; i
+= 2)
8723 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8724 output_asm_insn (instr
, operands
);
8734 /* Return the appropriate ARM instruction for the operation code.
8735 The returned result should not be overwritten. OP is the rtx of the
8736 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8739 arithmetic_instr (rtx op
, int shift_first_arg
)
8741 switch (GET_CODE (op
))
8747 return shift_first_arg
? "rsb" : "sub";
8763 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8764 for the operation code. The returned result should not be overwritten.
8765 OP is the rtx code of the shift.
8766 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8769 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
8772 enum rtx_code code
= GET_CODE (op
);
8774 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
8776 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
8777 *amountp
= INTVAL (XEXP (op
, 1));
8800 /* We never have to worry about the amount being other than a
8801 power of 2, since this case can never be reloaded from a reg. */
8803 *amountp
= int_log2 (*amountp
);
8814 /* This is not 100% correct, but follows from the desire to merge
8815 multiplication by a power of 2 with the recognizer for a
8816 shift. >=32 is not a valid shift for "asl", so we must try and
8817 output a shift that produces the correct arithmetical result.
8818 Using lsr #32 is identical except for the fact that the carry bit
8819 is not set correctly if we set the flags; but we never use the
8820 carry bit from such an operation, so we can ignore that. */
8821 if (code
== ROTATERT
)
8822 /* Rotate is just modulo 32. */
8824 else if (*amountp
!= (*amountp
& 31))
8831 /* Shifts of 0 are no-ops. */
8839 /* Obtain the shift from the POWER of two. */
8841 static HOST_WIDE_INT
8842 int_log2 (HOST_WIDE_INT power
)
8844 HOST_WIDE_INT shift
= 0;
8846 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
8856 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8857 /bin/as is horribly restrictive. */
8858 #define MAX_ASCII_LEN 51
8861 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
8866 fputs ("\t.ascii\t\"", stream
);
8868 for (i
= 0; i
< len
; i
++)
8872 if (len_so_far
>= MAX_ASCII_LEN
)
8874 fputs ("\"\n\t.ascii\t\"", stream
);
8881 fputs ("\\t", stream
);
8886 fputs ("\\f", stream
);
8891 fputs ("\\b", stream
);
8896 fputs ("\\r", stream
);
8900 case TARGET_NEWLINE
:
8901 fputs ("\\n", stream
);
8903 if ((c
>= ' ' && c
<= '~')
8905 /* This is a good place for a line break. */
8906 len_so_far
= MAX_ASCII_LEN
;
8913 putc ('\\', stream
);
8918 if (c
>= ' ' && c
<= '~')
8925 fprintf (stream
, "\\%03o", c
);
8932 fputs ("\"\n", stream
);
8935 /* Compute the register sabe mask for registers 0 through 12
8936 inclusive. This code is used by arm_compute_save_reg_mask. */
8937 static unsigned long
8938 arm_compute_save_reg0_reg12_mask (void)
8940 unsigned long func_type
= arm_current_func_type ();
8941 unsigned int save_reg_mask
= 0;
8944 if (IS_INTERRUPT (func_type
))
8946 unsigned int max_reg
;
8947 /* Interrupt functions must not corrupt any registers,
8948 even call clobbered ones. If this is a leaf function
8949 we can just examine the registers used by the RTL, but
8950 otherwise we have to assume that whatever function is
8951 called might clobber anything, and so we have to save
8952 all the call-clobbered registers as well. */
8953 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
8954 /* FIQ handlers have registers r8 - r12 banked, so
8955 we only need to check r0 - r7, Normal ISRs only
8956 bank r14 and r15, so we must check up to r12.
8957 r13 is the stack pointer which is always preserved,
8958 so we do not need to consider it here. */
8963 for (reg
= 0; reg
<= max_reg
; reg
++)
8964 if (regs_ever_live
[reg
]
8965 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
8966 save_reg_mask
|= (1 << reg
);
8970 /* In the normal case we only need to save those registers
8971 which are call saved and which are used by this function. */
8972 for (reg
= 0; reg
<= 10; reg
++)
8973 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8974 save_reg_mask
|= (1 << reg
);
8976 /* Handle the frame pointer as a special case. */
8977 if (! TARGET_APCS_FRAME
8978 && ! frame_pointer_needed
8979 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
8980 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
8981 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
8983 /* If we aren't loading the PIC register,
8984 don't stack it even though it may be live. */
8986 && ! TARGET_SINGLE_PIC_BASE
8987 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
8988 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
8991 return save_reg_mask
;
8994 /* Compute a bit mask of which registers need to be
8995 saved on the stack for the current function. */
8997 static unsigned long
8998 arm_compute_save_reg_mask (void)
9000 unsigned int save_reg_mask
= 0;
9001 unsigned long func_type
= arm_current_func_type ();
9003 if (IS_NAKED (func_type
))
9004 /* This should never really happen. */
9007 /* If we are creating a stack frame, then we must save the frame pointer,
9008 IP (which will hold the old stack pointer), LR and the PC. */
9009 if (frame_pointer_needed
)
9011 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9016 /* Volatile functions do not return, so there
9017 is no need to save any other registers. */
9018 if (IS_VOLATILE (func_type
))
9019 return save_reg_mask
;
9021 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9023 /* Decide if we need to save the link register.
9024 Interrupt routines have their own banked link register,
9025 so they never need to save it.
9026 Otherwise if we do not use the link register we do not need to save
9027 it. If we are pushing other registers onto the stack however, we
9028 can save an instruction in the epilogue by pushing the link register
9029 now and then popping it back into the PC. This incurs extra memory
9030 accesses though, so we only do it when optimizing for size, and only
9031 if we know that we will not need a fancy return sequence. */
9032 if (regs_ever_live
[LR_REGNUM
]
9035 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
))
9036 save_reg_mask
|= 1 << LR_REGNUM
;
9038 if (cfun
->machine
->lr_save_eliminated
)
9039 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9041 if (TARGET_REALLY_IWMMXT
9042 && ((bit_count (save_reg_mask
)
9043 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9047 /* The total number of registers that are going to be pushed
9048 onto the stack is odd. We need to ensure that the stack
9049 is 64-bit aligned before we start to save iWMMXt registers,
9050 and also before we start to create locals. (A local variable
9051 might be a double or long long which we will load/store using
9052 an iWMMXt instruction). Therefore we need to push another
9053 ARM register, so that the stack will be 64-bit aligned. We
9054 try to avoid using the arg registers (r0 -r3) as they might be
9055 used to pass values in a tail call. */
9056 for (reg
= 4; reg
<= 12; reg
++)
9057 if ((save_reg_mask
& (1 << reg
)) == 0)
9061 save_reg_mask
|= (1 << reg
);
9064 cfun
->machine
->sibcall_blocked
= 1;
9065 save_reg_mask
|= (1 << 3);
9069 return save_reg_mask
;
9073 /* Return the number of bytes required to save VFP registers. */
9075 arm_get_vfp_saved_size (void)
9082 /* Space for saved VFP registers. */
9083 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9086 for (regno
= FIRST_VFP_REGNUM
;
9087 regno
< LAST_VFP_REGNUM
;
9090 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9091 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9095 /* Workaround ARM10 VFPr1 bug. */
9096 if (count
== 2 && !arm_arch6
)
9098 saved
+= count
* 8 + 4;
9107 if (count
== 2 && !arm_arch6
)
9109 saved
+= count
* 8 + 4;
9116 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9117 everything bar the final return instruction. */
9119 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9121 char conditional
[10];
9124 unsigned long live_regs_mask
;
9125 unsigned long func_type
;
9126 arm_stack_offsets
*offsets
;
9128 func_type
= arm_current_func_type ();
9130 if (IS_NAKED (func_type
))
9133 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9135 /* If this function was declared non-returning, and we have
9136 found a tail call, then we have to trust that the called
9137 function won't return. */
9142 /* Otherwise, trap an attempted return by aborting. */
9144 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9146 assemble_external_libcall (ops
[1]);
9147 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9153 if (current_function_calls_alloca
&& !really_return
)
9156 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9158 return_used_this_function
= 1;
9160 live_regs_mask
= arm_compute_save_reg_mask ();
9164 const char * return_reg
;
9166 /* If we do not have any special requirements for function exit
9167 (eg interworking, or ISR) then we can load the return address
9168 directly into the PC. Otherwise we must load it into LR. */
9170 && ! TARGET_INTERWORK
)
9171 return_reg
= reg_names
[PC_REGNUM
];
9173 return_reg
= reg_names
[LR_REGNUM
];
9175 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9177 /* There are three possible reasons for the IP register
9178 being saved. 1) a stack frame was created, in which case
9179 IP contains the old stack pointer, or 2) an ISR routine
9180 corrupted it, or 3) it was saved to align the stack on
9181 iWMMXt. In case 1, restore IP into SP, otherwise just
9183 if (frame_pointer_needed
)
9185 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9186 live_regs_mask
|= (1 << SP_REGNUM
);
9190 if (! IS_INTERRUPT (func_type
)
9191 && ! TARGET_REALLY_IWMMXT
)
9196 /* On some ARM architectures it is faster to use LDR rather than
9197 LDM to load a single register. On other architectures, the
9198 cost is the same. In 26 bit mode, or for exception handlers,
9199 we have to use LDM to load the PC so that the CPSR is also
9201 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9203 if (live_regs_mask
== (unsigned int)(1 << reg
))
9206 if (reg
<= LAST_ARM_REGNUM
9207 && (reg
!= LR_REGNUM
9209 || (TARGET_APCS_32
&& ! IS_INTERRUPT (func_type
))))
9211 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9212 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9219 /* Generate the load multiple instruction to restore the
9220 registers. Note we can get here, even if
9221 frame_pointer_needed is true, but only if sp already
9222 points to the base of the saved core registers. */
9223 if (live_regs_mask
& (1 << SP_REGNUM
))
9225 unsigned HOST_WIDE_INT stack_adjust
;
9227 offsets
= arm_get_frame_offsets ();
9228 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9229 if (stack_adjust
!= 0 && stack_adjust
!= 4)
9232 if (stack_adjust
&& arm_arch5
)
9233 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9236 /* If we can't use ldmib (SA110 bug), then try to pop r3
9239 live_regs_mask
|= 1 << 3;
9240 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9244 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9246 p
= instr
+ strlen (instr
);
9248 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9249 if (live_regs_mask
& (1 << reg
))
9251 int l
= strlen (reg_names
[reg
]);
9257 memcpy (p
, ", ", 2);
9261 memcpy (p
, "%|", 2);
9262 memcpy (p
+ 2, reg_names
[reg
], l
);
9266 if (live_regs_mask
& (1 << LR_REGNUM
))
9268 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9269 /* Decide if we need to add the ^ symbol to the end of the
9270 register list. This causes the saved condition codes
9271 register to be copied into the current condition codes
9272 register. We do the copy if we are conforming to the 32-bit
9273 ABI and this is an interrupt function, or if we are
9274 conforming to the 26-bit ABI. There is a special case for
9275 the 26-bit ABI however, which is if we are writing back the
9276 stack pointer but not loading the PC. In this case adding
9277 the ^ symbol would create a type 2 LDM instruction, where
9278 writeback is UNPREDICTABLE. We are safe in leaving the ^
9279 character off in this case however, since the actual return
9280 instruction will be a MOVS which will restore the CPSR. */
9281 if ((TARGET_APCS_32
&& IS_INTERRUPT (func_type
))
9282 || (! TARGET_APCS_32
&& really_return
))
9289 output_asm_insn (instr
, & operand
);
9291 /* See if we need to generate an extra instruction to
9292 perform the actual function return. */
9294 && func_type
!= ARM_FT_INTERWORKED
9295 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9297 /* The return has already been handled
9298 by loading the LR into the PC. */
9305 switch ((int) ARM_FUNC_TYPE (func_type
))
9309 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9312 case ARM_FT_INTERWORKED
:
9313 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9316 case ARM_FT_EXCEPTION
:
9317 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9321 /* ARMv5 implementations always provide BX, so interworking
9322 is the default unless APCS-26 is in use. */
9323 if ((insn_flags
& FL_ARCH5
) != 0 && TARGET_APCS_32
)
9324 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9326 sprintf (instr
, "mov%s%s\t%%|pc, %%|lr",
9327 conditional
, TARGET_APCS_32
? "" : "s");
9331 output_asm_insn (instr
, & operand
);
9337 /* Write the function name into the code section, directly preceding
9338 the function prologue.
9340 Code will be output similar to this:
9342 .ascii "arm_poke_function_name", 0
9345 .word 0xff000000 + (t1 - t0)
9346 arm_poke_function_name
9348 stmfd sp!, {fp, ip, lr, pc}
9351 When performing a stack backtrace, code can inspect the value
9352 of 'pc' stored at 'fp' + 0. If the trace function then looks
9353 at location pc - 12 and the top 8 bits are set, then we know
9354 that there is a function name embedded immediately preceding this
9355 location and has length ((pc[-3]) & 0xff000000).
9357 We assume that pc is declared as a pointer to an unsigned long.
9359 It is of no benefit to output the function name if we are assembling
9360 a leaf function. These function types will not contain a stack
9361 backtrace structure, therefore it is not possible to determine the
9364 arm_poke_function_name (FILE *stream
, const char *name
)
9366 unsigned long alignlength
;
9367 unsigned long length
;
9370 length
= strlen (name
) + 1;
9371 alignlength
= ROUND_UP_WORD (length
);
9373 ASM_OUTPUT_ASCII (stream
, name
, length
);
9374 ASM_OUTPUT_ALIGN (stream
, 2);
9375 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9376 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9379 /* Place some comments into the assembler stream
9380 describing the current function. */
9382 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9384 unsigned long func_type
;
9388 thumb_output_function_prologue (f
, frame_size
);
9393 if (arm_ccfsm_state
|| arm_target_insn
)
9396 func_type
= arm_current_func_type ();
9398 switch ((int) ARM_FUNC_TYPE (func_type
))
9403 case ARM_FT_INTERWORKED
:
9404 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9406 case ARM_FT_EXCEPTION_HANDLER
:
9407 asm_fprintf (f
, "\t%@ C++ Exception Handler.\n");
9410 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9413 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9415 case ARM_FT_EXCEPTION
:
9416 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9420 if (IS_NAKED (func_type
))
9421 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9423 if (IS_VOLATILE (func_type
))
9424 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9426 if (IS_NESTED (func_type
))
9427 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9429 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9430 current_function_args_size
,
9431 current_function_pretend_args_size
, frame_size
);
9433 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9434 frame_pointer_needed
,
9435 cfun
->machine
->uses_anonymous_args
);
9437 if (cfun
->machine
->lr_save_eliminated
)
9438 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9440 #ifdef AOF_ASSEMBLER
9442 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9445 return_used_this_function
= 0;
9449 arm_output_epilogue (rtx sibling
)
9452 unsigned long saved_regs_mask
;
9453 unsigned long func_type
;
9454 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9455 frame that is $fp + 4 for a non-variadic function. */
9456 int floats_offset
= 0;
9458 FILE * f
= asm_out_file
;
9459 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
9460 unsigned int lrm_count
= 0;
9461 int really_return
= (sibling
== NULL
);
9463 arm_stack_offsets
*offsets
;
9465 /* If we have already generated the return instruction
9466 then it is futile to generate anything else. */
9467 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9470 func_type
= arm_current_func_type ();
9472 if (IS_NAKED (func_type
))
9473 /* Naked functions don't have epilogues. */
9476 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9480 /* A volatile function should never return. Call abort. */
9481 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9482 assemble_external_libcall (op
);
9483 output_asm_insn ("bl\t%a0", &op
);
9488 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
9490 /* If we are throwing an exception, then we really must
9491 be doing a return, so we can't tail-call. */
9494 offsets
= arm_get_frame_offsets ();
9495 saved_regs_mask
= arm_compute_save_reg_mask ();
9498 lrm_count
= bit_count (saved_regs_mask
);
9500 floats_offset
= offsets
->saved_args
;
9501 /* Compute how far away the floats will be. */
9502 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9503 if (saved_regs_mask
& (1 << reg
))
9506 if (frame_pointer_needed
)
9508 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9509 int vfp_offset
= offsets
->frame
;
9511 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9513 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9514 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9516 floats_offset
+= 12;
9517 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9518 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9523 start_reg
= LAST_FPA_REGNUM
;
9525 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9527 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9529 floats_offset
+= 12;
9531 /* We can't unstack more than four registers at once. */
9532 if (start_reg
- reg
== 3)
9534 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9535 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9536 start_reg
= reg
- 1;
9541 if (reg
!= start_reg
)
9542 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9543 reg
+ 1, start_reg
- reg
,
9544 FP_REGNUM
, floats_offset
- vfp_offset
);
9545 start_reg
= reg
- 1;
9549 /* Just in case the last register checked also needs unstacking. */
9550 if (reg
!= start_reg
)
9551 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9552 reg
+ 1, start_reg
- reg
,
9553 FP_REGNUM
, floats_offset
- vfp_offset
);
9556 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9560 /* The fldmx insn does not have base+offset addressing modes,
9561 so we use IP to hold the address. */
9562 saved_size
= arm_get_vfp_saved_size ();
9566 floats_offset
+= saved_size
;
9567 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9568 FP_REGNUM
, floats_offset
- vfp_offset
);
9570 start_reg
= FIRST_VFP_REGNUM
;
9571 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9573 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9574 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9576 if (start_reg
!= reg
)
9577 arm_output_fldmx (f
, IP_REGNUM
,
9578 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9579 (reg
- start_reg
) / 2);
9580 start_reg
= reg
+ 2;
9583 if (start_reg
!= reg
)
9584 arm_output_fldmx (f
, IP_REGNUM
,
9585 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9586 (reg
- start_reg
) / 2);
9591 /* The frame pointer is guaranteed to be non-double-word aligned.
9592 This is because it is set to (old_stack_pointer - 4) and the
9593 old_stack_pointer was double word aligned. Thus the offset to
9594 the iWMMXt registers to be loaded must also be non-double-word
9595 sized, so that the resultant address *is* double-word aligned.
9596 We can ignore floats_offset since that was already included in
9597 the live_regs_mask. */
9598 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9600 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9601 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9603 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9604 reg
, FP_REGNUM
, lrm_count
* 4);
9609 /* saved_regs_mask should contain the IP, which at the time of stack
9610 frame generation actually contains the old stack pointer. So a
9611 quick way to unwind the stack is just pop the IP register directly
9612 into the stack pointer. */
9613 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
9615 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9616 saved_regs_mask
|= (1 << SP_REGNUM
);
9618 /* There are two registers left in saved_regs_mask - LR and PC. We
9619 only need to restore the LR register (the return address), but to
9620 save time we can load it directly into the PC, unless we need a
9621 special function exit sequence, or we are not really returning. */
9622 if (really_return
&& ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
9623 /* Delete the LR from the register mask, so that the LR on
9624 the stack is loaded into the PC in the register mask. */
9625 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9627 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9629 /* We must use SP as the base register, because SP is one of the
9630 registers being restored. If an interrupt or page fault
9631 happens in the ldm instruction, the SP might or might not
9632 have been restored. That would be bad, as then SP will no
9633 longer indicate the safe area of stack, and we can get stack
9634 corruption. Using SP as the base register means that it will
9635 be reset correctly to the original value, should an interrupt
9636 occur. If the stack pointer already points at the right
9637 place, then omit the subtraction. */
9638 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9639 || current_function_calls_alloca
)
9640 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9641 4 * bit_count (saved_regs_mask
));
9642 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9644 if (IS_INTERRUPT (func_type
))
9645 /* Interrupt handlers will have pushed the
9646 IP onto the stack, so restore it now. */
9647 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9651 /* Restore stack pointer if necessary. */
9652 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9654 operands
[0] = operands
[1] = stack_pointer_rtx
;
9655 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9656 output_add_immediate (operands
);
9659 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9661 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9662 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9663 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9668 start_reg
= FIRST_FPA_REGNUM
;
9670 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9672 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9674 if (reg
- start_reg
== 3)
9676 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9677 start_reg
, SP_REGNUM
);
9678 start_reg
= reg
+ 1;
9683 if (reg
!= start_reg
)
9684 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9685 start_reg
, reg
- start_reg
,
9688 start_reg
= reg
+ 1;
9692 /* Just in case the last register checked also needs unstacking. */
9693 if (reg
!= start_reg
)
9694 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9695 start_reg
, reg
- start_reg
, SP_REGNUM
);
9698 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9700 start_reg
= FIRST_VFP_REGNUM
;
9701 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9703 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9704 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9706 if (start_reg
!= reg
)
9707 arm_output_fldmx (f
, SP_REGNUM
,
9708 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9709 (reg
- start_reg
) / 2);
9710 start_reg
= reg
+ 2;
9713 if (start_reg
!= reg
)
9714 arm_output_fldmx (f
, SP_REGNUM
,
9715 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9716 (reg
- start_reg
) / 2);
9719 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9720 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9721 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
9723 /* If we can, restore the LR into the PC. */
9724 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9726 && current_function_pretend_args_size
== 0
9727 && saved_regs_mask
& (1 << LR_REGNUM
))
9729 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9730 saved_regs_mask
|= (1 << PC_REGNUM
);
9733 /* Load the registers off the stack. If we only have one register
9734 to load use the LDR instruction - it is faster. */
9735 if (saved_regs_mask
== (1 << LR_REGNUM
))
9737 /* The exception handler ignores the LR, so we do
9738 not really need to load it off the stack. */
9740 asm_fprintf (f
, "\tadd\t%r, %r, #4\n", SP_REGNUM
, SP_REGNUM
);
9742 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
9744 else if (saved_regs_mask
)
9746 if (saved_regs_mask
& (1 << SP_REGNUM
))
9747 /* Note - write back to the stack register is not enabled
9748 (ie "ldmfd sp!..."). We know that the stack pointer is
9749 in the list of registers and if we add writeback the
9750 instruction becomes UNPREDICTABLE. */
9751 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9753 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
9756 if (current_function_pretend_args_size
)
9758 /* Unwind the pre-pushed regs. */
9759 operands
[0] = operands
[1] = stack_pointer_rtx
;
9760 operands
[2] = GEN_INT (current_function_pretend_args_size
);
9761 output_add_immediate (operands
);
9766 || (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9767 && current_function_pretend_args_size
== 0
9768 && saved_regs_mask
& (1 << PC_REGNUM
)))
9771 /* Generate the return instruction. */
9772 switch ((int) ARM_FUNC_TYPE (func_type
))
9774 case ARM_FT_EXCEPTION_HANDLER
:
9775 /* Even in 26-bit mode we do a mov (rather than a movs)
9776 because we don't have the PSR bits set in the address. */
9777 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, EXCEPTION_LR_REGNUM
);
9782 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
9785 case ARM_FT_EXCEPTION
:
9786 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9789 case ARM_FT_INTERWORKED
:
9790 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9794 if (frame_pointer_needed
)
9795 /* If we used the frame pointer then the return address
9796 will have been loaded off the stack directly into the
9797 PC, so there is no need to issue a MOV instruction
9800 else if (current_function_pretend_args_size
== 0
9801 && (saved_regs_mask
& (1 << LR_REGNUM
)))
9802 /* Similarly we may have been able to load LR into the PC
9803 even if we did not create a stack frame. */
9805 else if (TARGET_APCS_32
)
9806 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9808 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9816 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
9817 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
9819 arm_stack_offsets
*offsets
;
9823 /* ??? Probably not safe to set this here, since it assumes that a
9824 function will be emitted as assembly immediately after we generate
9825 RTL for it. This does not happen for inline functions. */
9826 return_used_this_function
= 0;
9830 /* We need to take into account any stack-frame rounding. */
9831 offsets
= arm_get_frame_offsets ();
9833 if (use_return_insn (FALSE
, NULL
)
9834 && return_used_this_function
9835 && offsets
->saved_regs
!= offsets
->outgoing_args
9836 && !frame_pointer_needed
)
9839 /* Reset the ARM-specific per-function variables. */
9840 after_arm_reorg
= 0;
9844 /* Generate and emit an insn that we will recognize as a push_multi.
9845 Unfortunately, since this insn does not reflect very well the actual
9846 semantics of the operation, we need to annotate the insn for the benefit
9847 of DWARF2 frame unwind information. */
9849 emit_multi_reg_push (int mask
)
9856 int dwarf_par_index
;
9859 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9860 if (mask
& (1 << i
))
9863 if (num_regs
== 0 || num_regs
> 16)
9866 /* We don't record the PC in the dwarf frame information. */
9867 num_dwarf_regs
= num_regs
;
9868 if (mask
& (1 << PC_REGNUM
))
9871 /* For the body of the insn we are going to generate an UNSPEC in
9872 parallel with several USEs. This allows the insn to be recognized
9873 by the push_multi pattern in the arm.md file. The insn looks
9874 something like this:
9877 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9878 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9879 (use (reg:SI 11 fp))
9880 (use (reg:SI 12 ip))
9881 (use (reg:SI 14 lr))
9882 (use (reg:SI 15 pc))
9885 For the frame note however, we try to be more explicit and actually
9886 show each register being stored into the stack frame, plus a (single)
9887 decrement of the stack pointer. We do it this way in order to be
9888 friendly to the stack unwinding code, which only wants to see a single
9889 stack decrement per instruction. The RTL we generate for the note looks
9890 something like this:
9893 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9894 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9895 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9896 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9897 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9900 This sequence is used both by the code to support stack unwinding for
9901 exceptions handlers and the code to generate dwarf2 frame debugging. */
9903 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
9904 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
9905 dwarf_par_index
= 1;
9907 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9909 if (mask
& (1 << i
))
9911 reg
= gen_rtx_REG (SImode
, i
);
9914 = gen_rtx_SET (VOIDmode
,
9915 gen_rtx_MEM (BLKmode
,
9916 gen_rtx_PRE_DEC (BLKmode
,
9917 stack_pointer_rtx
)),
9918 gen_rtx_UNSPEC (BLKmode
,
9924 tmp
= gen_rtx_SET (VOIDmode
,
9925 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
9927 RTX_FRAME_RELATED_P (tmp
) = 1;
9928 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
9936 for (j
= 1, i
++; j
< num_regs
; i
++)
9938 if (mask
& (1 << i
))
9940 reg
= gen_rtx_REG (SImode
, i
);
9942 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
9946 tmp
= gen_rtx_SET (VOIDmode
,
9947 gen_rtx_MEM (SImode
,
9948 plus_constant (stack_pointer_rtx
,
9951 RTX_FRAME_RELATED_P (tmp
) = 1;
9952 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
9959 par
= emit_insn (par
);
9961 tmp
= gen_rtx_SET (SImode
,
9963 gen_rtx_PLUS (SImode
,
9965 GEN_INT (-4 * num_regs
)));
9966 RTX_FRAME_RELATED_P (tmp
) = 1;
9967 XVECEXP (dwarf
, 0, 0) = tmp
;
9969 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
9975 emit_sfm (int base_reg
, int count
)
9982 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
9983 dwarf
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
9985 reg
= gen_rtx_REG (XFmode
, base_reg
++);
9988 = gen_rtx_SET (VOIDmode
,
9989 gen_rtx_MEM (BLKmode
,
9990 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
9991 gen_rtx_UNSPEC (BLKmode
,
9995 = gen_rtx_SET (VOIDmode
,
9996 gen_rtx_MEM (XFmode
,
9997 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
9999 RTX_FRAME_RELATED_P (tmp
) = 1;
10000 XVECEXP (dwarf
, 0, count
- 1) = tmp
;
10002 for (i
= 1; i
< count
; i
++)
10004 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10005 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10007 tmp
= gen_rtx_SET (VOIDmode
,
10008 gen_rtx_MEM (XFmode
,
10009 gen_rtx_PRE_DEC (BLKmode
,
10010 stack_pointer_rtx
)),
10012 RTX_FRAME_RELATED_P (tmp
) = 1;
10013 XVECEXP (dwarf
, 0, count
- i
- 1) = tmp
;
10016 par
= emit_insn (par
);
10017 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10023 /* Compute the distance from register FROM to register TO.
10024 These can be the arg pointer (26), the soft frame pointer (25),
10025 the stack pointer (13) or the hard frame pointer (11).
10026 Typical stack layout looks like this:
10028 old stack pointer -> | |
10031 | | saved arguments for
10032 | | vararg functions
10035 hard FP & arg pointer -> | | \
10043 soft frame pointer -> | | /
10053 current stack pointer -> | | /
10056 For a given function some or all of these stack components
10057 may not be needed, giving rise to the possibility of
10058 eliminating some of the registers.
10060 The values returned by this function must reflect the behavior
10061 of arm_expand_prologue() and arm_compute_save_reg_mask().
10063 The sign of the number returned reflects the direction of stack
10064 growth, so the values are positive for all eliminations except
10065 from the soft frame pointer to the hard frame pointer.
10067 SFP may point just inside the local variables block to ensure correct
10071 /* Calculate stack offsets. These are used to calculate register elimination
10072 offsets and in prologue/epilogue code. */
10074 static arm_stack_offsets
*
10075 arm_get_frame_offsets (void)
10077 struct arm_stack_offsets
*offsets
;
10078 unsigned long func_type
;
10081 HOST_WIDE_INT frame_size
;
10083 offsets
= &cfun
->machine
->stack_offsets
;
10085 /* We need to know if we are a leaf function. Unfortunately, it
10086 is possible to be called after start_sequence has been called,
10087 which causes get_insns to return the insns for the sequence,
10088 not the function, which will cause leaf_function_p to return
10089 the incorrect result.
10091 to know about leaf functions once reload has completed, and the
10092 frame size cannot be changed after that time, so we can safely
10093 use the cached value. */
10095 if (reload_completed
)
10098 /* Initially this is the size of the local variables. It will translated
10099 into an offset once we have determined the size of preceding data. */
10100 frame_size
= ROUND_UP_WORD (get_frame_size ());
10102 leaf
= leaf_function_p ();
10104 /* Space for variadic functions. */
10105 offsets
->saved_args
= current_function_pretend_args_size
;
10107 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10111 unsigned int regno
;
10113 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10115 /* We know that SP will be doubleword aligned on entry, and we must
10116 preserve that condition at any subroutine call. We also require the
10117 soft frame pointer to be doubleword aligned. */
10119 if (TARGET_REALLY_IWMMXT
)
10121 /* Check for the call-saved iWMMXt registers. */
10122 for (regno
= FIRST_IWMMXT_REGNUM
;
10123 regno
<= LAST_IWMMXT_REGNUM
;
10125 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10129 func_type
= arm_current_func_type ();
10130 if (! IS_VOLATILE (func_type
))
10132 /* Space for saved FPA registers. */
10133 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10134 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10137 /* Space for saved VFP registers. */
10138 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10139 saved
+= arm_get_vfp_saved_size ();
10142 else /* TARGET_THUMB */
10149 for (reg
= 8; reg
< 13; reg
++)
10150 if (THUMB_REG_PUSHED_P (reg
))
10153 saved
+= 4 * count_regs
;
10155 for (reg
= 0; reg
<= LAST_LO_REGNUM
; reg
++)
10156 if (THUMB_REG_PUSHED_P (reg
))
10158 if (count_regs
|| ! leaf_function_p ()
10159 || thumb_far_jump_used_p ())
10160 saved
+= 4 * (count_regs
+ 1);
10161 if (TARGET_BACKTRACE
)
10163 if ((count_regs
& 0xFF) == 0 && (regs_ever_live
[3] != 0))
10170 /* Saved registers include the stack frame. */
10171 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10172 offsets
->soft_frame
= offsets
->saved_regs
;
10173 /* A leaf function does not need any stack alignment if it has nothing
10175 if (leaf
&& frame_size
== 0)
10177 offsets
->outgoing_args
= offsets
->soft_frame
;
10181 /* Ensure SFP has the correct alignment. */
10182 if (ARM_DOUBLEWORD_ALIGN
10183 && (offsets
->soft_frame
& 7))
10184 offsets
->soft_frame
+= 4;
10186 offsets
->outgoing_args
= offsets
->soft_frame
+ frame_size
10187 + current_function_outgoing_args_size
;
10189 if (ARM_DOUBLEWORD_ALIGN
)
10191 /* Ensure SP remains doubleword aligned. */
10192 if (offsets
->outgoing_args
& 7)
10193 offsets
->outgoing_args
+= 4;
10194 if (offsets
->outgoing_args
& 7)
10202 /* Calculate the relative offsets for the different stack pointers. Positive
10203 offsets are in the direction of stack growth. */
10206 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10208 arm_stack_offsets
*offsets
;
10210 offsets
= arm_get_frame_offsets ();
10212 /* OK, now we have enough information to compute the distances.
10213 There must be an entry in these switch tables for each pair
10214 of registers in ELIMINABLE_REGS, even if some of the entries
10215 seem to be redundant or useless. */
10218 case ARG_POINTER_REGNUM
:
10221 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10224 case FRAME_POINTER_REGNUM
:
10225 /* This is the reverse of the soft frame pointer
10226 to hard frame pointer elimination below. */
10227 return offsets
->soft_frame
- offsets
->saved_args
;
10229 case ARM_HARD_FRAME_POINTER_REGNUM
:
10230 /* If there is no stack frame then the hard
10231 frame pointer and the arg pointer coincide. */
10232 if (offsets
->frame
== offsets
->saved_regs
)
10234 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10235 return (frame_pointer_needed
10236 && cfun
->static_chain_decl
!= NULL
10237 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10239 case STACK_POINTER_REGNUM
:
10240 /* If nothing has been pushed on the stack at all
10241 then this will return -4. This *is* correct! */
10242 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10249 case FRAME_POINTER_REGNUM
:
10252 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10255 case ARM_HARD_FRAME_POINTER_REGNUM
:
10256 /* The hard frame pointer points to the top entry in the
10257 stack frame. The soft frame pointer to the bottom entry
10258 in the stack frame. If there is no stack frame at all,
10259 then they are identical. */
10261 return offsets
->frame
- offsets
->soft_frame
;
10263 case STACK_POINTER_REGNUM
:
10264 return offsets
->outgoing_args
- offsets
->soft_frame
;
10272 /* You cannot eliminate from the stack pointer.
10273 In theory you could eliminate from the hard frame
10274 pointer to the stack pointer, but this will never
10275 happen, since if a stack frame is not needed the
10276 hard frame pointer will never be used. */
10282 /* Generate the prologue instructions for entry into an ARM function. */
10284 arm_expand_prologue (void)
10290 unsigned long live_regs_mask
;
10291 unsigned long func_type
;
10293 int saved_pretend_args
= 0;
10294 int saved_regs
= 0;
10295 unsigned int args_to_push
;
10296 arm_stack_offsets
*offsets
;
10298 func_type
= arm_current_func_type ();
10300 /* Naked functions don't have prologues. */
10301 if (IS_NAKED (func_type
))
10304 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10305 args_to_push
= current_function_pretend_args_size
;
10307 /* Compute which register we will have to save onto the stack. */
10308 live_regs_mask
= arm_compute_save_reg_mask ();
10310 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10312 if (frame_pointer_needed
)
10314 if (IS_INTERRUPT (func_type
))
10316 /* Interrupt functions must not corrupt any registers.
10317 Creating a frame pointer however, corrupts the IP
10318 register, so we must push it first. */
10319 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10321 /* Do not set RTX_FRAME_RELATED_P on this insn.
10322 The dwarf stack unwinding code only wants to see one
10323 stack decrement per function, and this is not it. If
10324 this instruction is labeled as being part of the frame
10325 creation sequence then dwarf2out_frame_debug_expr will
10326 abort when it encounters the assignment of IP to FP
10327 later on, since the use of SP here establishes SP as
10328 the CFA register and not IP.
10330 Anyway this instruction is not really part of the stack
10331 frame creation although it is part of the prologue. */
10333 else if (IS_NESTED (func_type
))
10335 /* The Static chain register is the same as the IP register
10336 used as a scratch register during stack frame creation.
10337 To get around this need to find somewhere to store IP
10338 whilst the frame is being created. We try the following
10341 1. The last argument register.
10342 2. A slot on the stack above the frame. (This only
10343 works if the function is not a varargs function).
10344 3. Register r3, after pushing the argument registers
10347 Note - we only need to tell the dwarf2 backend about the SP
10348 adjustment in the second variant; the static chain register
10349 doesn't need to be unwound, as it doesn't contain a value
10350 inherited from the caller. */
10352 if (regs_ever_live
[3] == 0)
10354 insn
= gen_rtx_REG (SImode
, 3);
10355 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10356 insn
= emit_insn (insn
);
10358 else if (args_to_push
== 0)
10361 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10362 insn
= gen_rtx_MEM (SImode
, insn
);
10363 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
10364 insn
= emit_insn (insn
);
10368 /* Just tell the dwarf backend that we adjusted SP. */
10369 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10370 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
10371 GEN_INT (-fp_offset
)));
10372 RTX_FRAME_RELATED_P (insn
) = 1;
10373 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10374 dwarf
, REG_NOTES (insn
));
10378 /* Store the args on the stack. */
10379 if (cfun
->machine
->uses_anonymous_args
)
10380 insn
= emit_multi_reg_push
10381 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10384 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10385 GEN_INT (- args_to_push
)));
10387 RTX_FRAME_RELATED_P (insn
) = 1;
10389 saved_pretend_args
= 1;
10390 fp_offset
= args_to_push
;
10393 /* Now reuse r3 to preserve IP. */
10394 insn
= gen_rtx_REG (SImode
, 3);
10395 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10396 (void) emit_insn (insn
);
10402 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
10403 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
10406 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
10408 insn
= emit_insn (insn
);
10409 RTX_FRAME_RELATED_P (insn
) = 1;
10414 /* Push the argument registers, or reserve space for them. */
10415 if (cfun
->machine
->uses_anonymous_args
)
10416 insn
= emit_multi_reg_push
10417 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10420 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10421 GEN_INT (- args_to_push
)));
10422 RTX_FRAME_RELATED_P (insn
) = 1;
10425 /* If this is an interrupt service routine, and the link register
10426 is going to be pushed, and we are not creating a stack frame,
10427 (which would involve an extra push of IP and a pop in the epilogue)
10428 subtracting four from LR now will mean that the function return
10429 can be done with a single instruction. */
10430 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10431 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10432 && ! frame_pointer_needed
)
10433 emit_insn (gen_rtx_SET (SImode
,
10434 gen_rtx_REG (SImode
, LR_REGNUM
),
10435 gen_rtx_PLUS (SImode
,
10436 gen_rtx_REG (SImode
, LR_REGNUM
),
10439 if (live_regs_mask
)
10441 insn
= emit_multi_reg_push (live_regs_mask
);
10442 saved_regs
+= bit_count (live_regs_mask
) * 4;
10443 RTX_FRAME_RELATED_P (insn
) = 1;
10447 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10448 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10450 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10451 insn
= gen_rtx_MEM (V2SImode
, insn
);
10452 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10453 gen_rtx_REG (V2SImode
, reg
)));
10454 RTX_FRAME_RELATED_P (insn
) = 1;
10458 if (! IS_VOLATILE (func_type
))
10462 /* Save any floating point call-saved registers used by this
10464 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10466 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10467 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10469 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10470 insn
= gen_rtx_MEM (XFmode
, insn
);
10471 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10472 gen_rtx_REG (XFmode
, reg
)));
10473 RTX_FRAME_RELATED_P (insn
) = 1;
10479 start_reg
= LAST_FPA_REGNUM
;
10481 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10483 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10485 if (start_reg
- reg
== 3)
10487 insn
= emit_sfm (reg
, 4);
10488 RTX_FRAME_RELATED_P (insn
) = 1;
10490 start_reg
= reg
- 1;
10495 if (start_reg
!= reg
)
10497 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10498 RTX_FRAME_RELATED_P (insn
) = 1;
10499 saved_regs
+= (start_reg
- reg
) * 12;
10501 start_reg
= reg
- 1;
10505 if (start_reg
!= reg
)
10507 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10508 saved_regs
+= (start_reg
- reg
) * 12;
10509 RTX_FRAME_RELATED_P (insn
) = 1;
10512 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10514 start_reg
= FIRST_VFP_REGNUM
;
10516 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10518 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10519 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10521 if (start_reg
!= reg
)
10522 saved_regs
+= vfp_emit_fstmx (start_reg
,
10523 (reg
- start_reg
) / 2);
10524 start_reg
= reg
+ 2;
10527 if (start_reg
!= reg
)
10528 saved_regs
+= vfp_emit_fstmx (start_reg
,
10529 (reg
- start_reg
) / 2);
10533 if (frame_pointer_needed
)
10535 /* Create the new frame pointer. */
10536 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10537 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10538 RTX_FRAME_RELATED_P (insn
) = 1;
10540 if (IS_NESTED (func_type
))
10542 /* Recover the static chain register. */
10543 if (regs_ever_live
[3] == 0
10544 || saved_pretend_args
)
10545 insn
= gen_rtx_REG (SImode
, 3);
10546 else /* if (current_function_pretend_args_size == 0) */
10548 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
10550 insn
= gen_rtx_MEM (SImode
, insn
);
10553 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
10554 /* Add a USE to stop propagate_one_insn() from barfing. */
10555 emit_insn (gen_prologue_use (ip_rtx
));
10559 offsets
= arm_get_frame_offsets ();
10560 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10562 /* This add can produce multiple insns for a large constant, so we
10563 need to get tricky. */
10564 rtx last
= get_last_insn ();
10566 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10567 - offsets
->outgoing_args
);
10569 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10573 last
= last
? NEXT_INSN (last
) : get_insns ();
10574 RTX_FRAME_RELATED_P (last
) = 1;
10576 while (last
!= insn
);
10578 /* If the frame pointer is needed, emit a special barrier that
10579 will prevent the scheduler from moving stores to the frame
10580 before the stack adjustment. */
10581 if (frame_pointer_needed
)
10582 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10583 hard_frame_pointer_rtx
));
10586 /* If we are profiling, make sure no instructions are scheduled before
10587 the call to mcount. Similarly if the user has requested no
10588 scheduling in the prolog. */
10589 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
10590 emit_insn (gen_blockage ());
10592 /* If the link register is being kept alive, with the return address in it,
10593 then make sure that it does not get reused by the ce2 pass. */
10594 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10596 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10597 cfun
->machine
->lr_save_eliminated
= 1;
10601 /* If CODE is 'd', then the X is a condition operand and the instruction
10602 should only be executed if the condition is true.
10603 if CODE is 'D', then the X is a condition operand and the instruction
10604 should only be executed if the condition is false: however, if the mode
10605 of the comparison is CCFPEmode, then always execute the instruction -- we
10606 do this because in these circumstances !GE does not necessarily imply LT;
10607 in these cases the instruction pattern will take care to make sure that
10608 an instruction containing %d will follow, thereby undoing the effects of
10609 doing this instruction unconditionally.
10610 If CODE is 'N' then X is a floating point operand that must be negated
10612 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10613 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10615 arm_print_operand (FILE *stream
, rtx x
, int code
)
10620 fputs (ASM_COMMENT_START
, stream
);
10624 fputs (user_label_prefix
, stream
);
10628 fputs (REGISTER_PREFIX
, stream
);
10632 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10634 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
10637 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10639 else if (current_insn_predicate
)
10641 enum arm_cond_code code
;
10646 code
= get_arm_condition_code (current_insn_predicate
);
10647 fputs (arm_condition_codes
[code
], stream
);
10654 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10655 r
= REAL_VALUE_NEGATE (r
);
10656 fprintf (stream
, "%s", fp_const_from_val (&r
));
10661 if (GET_CODE (x
) == CONST_INT
)
10664 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10665 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10669 putc ('~', stream
);
10670 output_addr_const (stream
, x
);
10675 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10678 /* Truncate Cirrus shift counts. */
10680 if (GET_CODE (x
) == CONST_INT
)
10682 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10685 arm_print_operand (stream
, x
, 0);
10689 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10695 const char * shift
= shift_op (x
, &val
);
10699 fprintf (stream
, ", %s ", shift_op (x
, &val
));
10701 arm_print_operand (stream
, XEXP (x
, 1), 0);
10703 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
10708 /* An explanation of the 'Q', 'R' and 'H' register operands:
10710 In a pair of registers containing a DI or DF value the 'Q'
10711 operand returns the register number of the register containing
10712 the least significant part of the value. The 'R' operand returns
10713 the register number of the register containing the most
10714 significant part of the value.
10716 The 'H' operand returns the higher of the two register numbers.
10717 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10718 same as the 'Q' operand, since the most significant part of the
10719 value is held in the lower number register. The reverse is true
10720 on systems where WORDS_BIG_ENDIAN is false.
10722 The purpose of these operands is to distinguish between cases
10723 where the endian-ness of the values is important (for example
10724 when they are added together), and cases where the endian-ness
10725 is irrelevant, but the order of register operations is important.
10726 For example when loading a value from memory into a register
10727 pair, the endian-ness does not matter. Provided that the value
10728 from the lower memory address is put into the lower numbered
10729 register, and the value from the higher address is put into the
10730 higher numbered register, the load will work regardless of whether
10731 the value being loaded is big-wordian or little-wordian. The
10732 order of the two register loads can matter however, if the address
10733 of the memory location is actually held in one of the registers
10734 being overwritten by the load. */
10736 if (REGNO (x
) > LAST_ARM_REGNUM
)
10738 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
10742 if (REGNO (x
) > LAST_ARM_REGNUM
)
10744 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
10748 if (REGNO (x
) > LAST_ARM_REGNUM
)
10750 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
10754 asm_fprintf (stream
, "%r",
10755 GET_CODE (XEXP (x
, 0)) == REG
10756 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
10760 asm_fprintf (stream
, "{%r-%r}",
10762 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
10766 /* CONST_TRUE_RTX means always -- that's the default. */
10767 if (x
== const_true_rtx
)
10770 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
10775 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10776 want to do that. */
10777 if (x
== const_true_rtx
)
10780 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
10781 (get_arm_condition_code (x
))],
10785 /* Cirrus registers can be accessed in a variety of ways:
10786 single floating point (f)
10787 double floating point (d)
10789 64bit integer (dx). */
10790 case 'W': /* Cirrus register in F mode. */
10791 case 'X': /* Cirrus register in D mode. */
10792 case 'Y': /* Cirrus register in FX mode. */
10793 case 'Z': /* Cirrus register in DX mode. */
10794 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10797 fprintf (stream
, "mv%s%s",
10799 : code
== 'X' ? "d"
10800 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
10804 /* Print cirrus register in the mode specified by the register's mode. */
10807 int mode
= GET_MODE (x
);
10809 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10812 fprintf (stream
, "mv%s%s",
10813 mode
== DFmode
? "d"
10814 : mode
== SImode
? "fx"
10815 : mode
== DImode
? "dx"
10816 : "f", reg_names
[REGNO (x
)] + 2);
10822 if (GET_CODE (x
) != REG
10823 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
10824 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
10825 /* Bad value for wCG register number. */
10828 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
10831 /* Print an iWMMXt control register name. */
10833 if (GET_CODE (x
) != CONST_INT
10835 || INTVAL (x
) >= 16)
10836 /* Bad value for wC register number. */
10840 static const char * wc_reg_names
[16] =
10842 "wCID", "wCon", "wCSSF", "wCASF",
10843 "wC4", "wC5", "wC6", "wC7",
10844 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10845 "wC12", "wC13", "wC14", "wC15"
10848 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
10852 /* Print a VFP double precision register name. */
10855 int mode
= GET_MODE (x
);
10858 if (mode
!= DImode
&& mode
!= DFmode
)
10861 if (GET_CODE (x
) != REG
10862 || !IS_VFP_REGNUM (REGNO (x
)))
10865 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
10869 fprintf (stream
, "d%d", num
>> 1);
10877 if (GET_CODE (x
) == REG
)
10878 asm_fprintf (stream
, "%r", REGNO (x
));
10879 else if (GET_CODE (x
) == MEM
)
10881 output_memory_reference_mode
= GET_MODE (x
);
10882 output_address (XEXP (x
, 0));
10884 else if (GET_CODE (x
) == CONST_DOUBLE
)
10885 fprintf (stream
, "#%s", fp_immediate_constant (x
));
10886 else if (GET_CODE (x
) == NEG
)
10887 abort (); /* This should never happen now. */
10890 fputc ('#', stream
);
10891 output_addr_const (stream
, x
);
10896 #ifndef AOF_ASSEMBLER
10897 /* Target hook for assembling integer objects. The ARM version needs to
10898 handle word-sized values specially. */
10900 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
10902 if (size
== UNITS_PER_WORD
&& aligned_p
)
10904 fputs ("\t.word\t", asm_out_file
);
10905 output_addr_const (asm_out_file
, x
);
10907 /* Mark symbols as position independent. We only do this in the
10908 .text segment, not in the .data segment. */
10909 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
10910 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
10912 if (GET_CODE (x
) == SYMBOL_REF
10913 && (CONSTANT_POOL_ADDRESS_P (x
)
10914 || SYMBOL_REF_LOCAL_P (x
)))
10915 fputs ("(GOTOFF)", asm_out_file
);
10916 else if (GET_CODE (x
) == LABEL_REF
)
10917 fputs ("(GOTOFF)", asm_out_file
);
10919 fputs ("(GOT)", asm_out_file
);
10921 fputc ('\n', asm_out_file
);
10925 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x
)))
10929 if (GET_CODE (x
) != CONST_VECTOR
)
10932 units
= CONST_VECTOR_NUNITS (x
);
10934 switch (GET_MODE (x
))
10936 case V2SImode
: size
= 4; break;
10937 case V4HImode
: size
= 2; break;
10938 case V8QImode
: size
= 1; break;
10943 for (i
= 0; i
< units
; i
++)
10947 elt
= CONST_VECTOR_ELT (x
, i
);
10949 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
10955 return default_assemble_integer (x
, size
, aligned_p
);
10959 /* A finite state machine takes care of noticing whether or not instructions
10960 can be conditionally executed, and thus decrease execution time and code
10961 size by deleting branch instructions. The fsm is controlled by
10962 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10964 /* The state of the fsm controlling condition codes are:
10965 0: normal, do nothing special
10966 1: make ASM_OUTPUT_OPCODE not output this instruction
10967 2: make ASM_OUTPUT_OPCODE not output this instruction
10968 3: make instructions conditional
10969 4: make instructions conditional
10971 State transitions (state->state by whom under condition):
10972 0 -> 1 final_prescan_insn if the `target' is a label
10973 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10974 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10975 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10976 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10977 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10978 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10979 (the target insn is arm_target_insn).
10981 If the jump clobbers the conditions then we use states 2 and 4.
10983 A similar thing can be done with conditional return insns.
10985 XXX In case the `target' is an unconditional branch, this conditionalising
10986 of the instructions always reduces code size, but not always execution
10987 time. But then, I want to reduce the code size to somewhere near what
10988 /bin/cc produces. */
10990 /* Returns the index of the ARM condition code string in
10991 `arm_condition_codes'. COMPARISON should be an rtx like
10992 `(eq (...) (...))'. */
10993 static enum arm_cond_code
10994 get_arm_condition_code (rtx comparison
)
10996 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
10998 enum rtx_code comp_code
= GET_CODE (comparison
);
11000 if (GET_MODE_CLASS (mode
) != MODE_CC
)
11001 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
11002 XEXP (comparison
, 1));
11006 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11007 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11008 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11009 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11010 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11011 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11012 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11013 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11014 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11015 case CC_DLTUmode
: code
= ARM_CC
;
11018 if (comp_code
!= EQ
&& comp_code
!= NE
)
11021 if (comp_code
== EQ
)
11022 return ARM_INVERSE_CONDITION_CODE (code
);
11028 case NE
: return ARM_NE
;
11029 case EQ
: return ARM_EQ
;
11030 case GE
: return ARM_PL
;
11031 case LT
: return ARM_MI
;
11038 case NE
: return ARM_NE
;
11039 case EQ
: return ARM_EQ
;
11046 case NE
: return ARM_MI
;
11047 case EQ
: return ARM_PL
;
11053 /* These encodings assume that AC=1 in the FPA system control
11054 byte. This allows us to handle all cases except UNEQ and
11058 case GE
: return ARM_GE
;
11059 case GT
: return ARM_GT
;
11060 case LE
: return ARM_LS
;
11061 case LT
: return ARM_MI
;
11062 case NE
: return ARM_NE
;
11063 case EQ
: return ARM_EQ
;
11064 case ORDERED
: return ARM_VC
;
11065 case UNORDERED
: return ARM_VS
;
11066 case UNLT
: return ARM_LT
;
11067 case UNLE
: return ARM_LE
;
11068 case UNGT
: return ARM_HI
;
11069 case UNGE
: return ARM_PL
;
11070 /* UNEQ and LTGT do not have a representation. */
11071 case UNEQ
: /* Fall through. */
11072 case LTGT
: /* Fall through. */
11079 case NE
: return ARM_NE
;
11080 case EQ
: return ARM_EQ
;
11081 case GE
: return ARM_LE
;
11082 case GT
: return ARM_LT
;
11083 case LE
: return ARM_GE
;
11084 case LT
: return ARM_GT
;
11085 case GEU
: return ARM_LS
;
11086 case GTU
: return ARM_CC
;
11087 case LEU
: return ARM_CS
;
11088 case LTU
: return ARM_HI
;
11095 case LTU
: return ARM_CS
;
11096 case GEU
: return ARM_CC
;
11103 case NE
: return ARM_NE
;
11104 case EQ
: return ARM_EQ
;
11105 case GE
: return ARM_GE
;
11106 case GT
: return ARM_GT
;
11107 case LE
: return ARM_LE
;
11108 case LT
: return ARM_LT
;
11109 case GEU
: return ARM_CS
;
11110 case GTU
: return ARM_HI
;
11111 case LEU
: return ARM_LS
;
11112 case LTU
: return ARM_CC
;
11123 arm_final_prescan_insn (rtx insn
)
11125 /* BODY will hold the body of INSN. */
11126 rtx body
= PATTERN (insn
);
11128 /* This will be 1 if trying to repeat the trick, and things need to be
11129 reversed if it appears to fail. */
11132 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11133 taken are clobbered, even if the rtl suggests otherwise. It also
11134 means that we have to grub around within the jump expression to find
11135 out what the conditions are when the jump isn't taken. */
11136 int jump_clobbers
= 0;
11138 /* If we start with a return insn, we only succeed if we find another one. */
11139 int seeking_return
= 0;
11141 /* START_INSN will hold the insn from where we start looking. This is the
11142 first insn after the following code_label if REVERSE is true. */
11143 rtx start_insn
= insn
;
11145 /* If in state 4, check if the target branch is reached, in order to
11146 change back to state 0. */
11147 if (arm_ccfsm_state
== 4)
11149 if (insn
== arm_target_insn
)
11151 arm_target_insn
= NULL
;
11152 arm_ccfsm_state
= 0;
11157 /* If in state 3, it is possible to repeat the trick, if this insn is an
11158 unconditional branch to a label, and immediately following this branch
11159 is the previous target label which is only used once, and the label this
11160 branch jumps to is not too far off. */
11161 if (arm_ccfsm_state
== 3)
11163 if (simplejump_p (insn
))
11165 start_insn
= next_nonnote_insn (start_insn
);
11166 if (GET_CODE (start_insn
) == BARRIER
)
11168 /* XXX Isn't this always a barrier? */
11169 start_insn
= next_nonnote_insn (start_insn
);
11171 if (GET_CODE (start_insn
) == CODE_LABEL
11172 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11173 && LABEL_NUSES (start_insn
) == 1)
11178 else if (GET_CODE (body
) == RETURN
)
11180 start_insn
= next_nonnote_insn (start_insn
);
11181 if (GET_CODE (start_insn
) == BARRIER
)
11182 start_insn
= next_nonnote_insn (start_insn
);
11183 if (GET_CODE (start_insn
) == CODE_LABEL
11184 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11185 && LABEL_NUSES (start_insn
) == 1)
11188 seeking_return
= 1;
11197 if (arm_ccfsm_state
!= 0 && !reverse
)
11199 if (GET_CODE (insn
) != JUMP_INSN
)
11202 /* This jump might be paralleled with a clobber of the condition codes
11203 the jump should always come first */
11204 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11205 body
= XVECEXP (body
, 0, 0);
11208 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11209 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11212 int fail
= FALSE
, succeed
= FALSE
;
11213 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11214 int then_not_else
= TRUE
;
11215 rtx this_insn
= start_insn
, label
= 0;
11217 /* If the jump cannot be done with one instruction, we cannot
11218 conditionally execute the instruction in the inverse case. */
11219 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11225 /* Register the insn jumped to. */
11228 if (!seeking_return
)
11229 label
= XEXP (SET_SRC (body
), 0);
11231 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11232 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11233 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11235 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11236 then_not_else
= FALSE
;
11238 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11239 seeking_return
= 1;
11240 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11242 seeking_return
= 1;
11243 then_not_else
= FALSE
;
11248 /* See how many insns this branch skips, and what kind of insns. If all
11249 insns are okay, and the label or unconditional branch to the same
11250 label is not too far away, succeed. */
11251 for (insns_skipped
= 0;
11252 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11256 this_insn
= next_nonnote_insn (this_insn
);
11260 switch (GET_CODE (this_insn
))
11263 /* Succeed if it is the target label, otherwise fail since
11264 control falls in from somewhere else. */
11265 if (this_insn
== label
)
11269 arm_ccfsm_state
= 2;
11270 this_insn
= next_nonnote_insn (this_insn
);
11273 arm_ccfsm_state
= 1;
11281 /* Succeed if the following insn is the target label.
11283 If return insns are used then the last insn in a function
11284 will be a barrier. */
11285 this_insn
= next_nonnote_insn (this_insn
);
11286 if (this_insn
&& this_insn
== label
)
11290 arm_ccfsm_state
= 2;
11291 this_insn
= next_nonnote_insn (this_insn
);
11294 arm_ccfsm_state
= 1;
11302 /* If using 32-bit addresses the cc is not preserved over
11304 if (TARGET_APCS_32
)
11306 /* Succeed if the following insn is the target label,
11307 or if the following two insns are a barrier and
11308 the target label. */
11309 this_insn
= next_nonnote_insn (this_insn
);
11310 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11311 this_insn
= next_nonnote_insn (this_insn
);
11313 if (this_insn
&& this_insn
== label
11314 && insns_skipped
< max_insns_skipped
)
11318 arm_ccfsm_state
= 2;
11319 this_insn
= next_nonnote_insn (this_insn
);
11322 arm_ccfsm_state
= 1;
11331 /* If this is an unconditional branch to the same label, succeed.
11332 If it is to another label, do nothing. If it is conditional,
11334 /* XXX Probably, the tests for SET and the PC are
11337 scanbody
= PATTERN (this_insn
);
11338 if (GET_CODE (scanbody
) == SET
11339 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11341 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11342 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11344 arm_ccfsm_state
= 2;
11347 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11350 /* Fail if a conditional return is undesirable (eg on a
11351 StrongARM), but still allow this if optimizing for size. */
11352 else if (GET_CODE (scanbody
) == RETURN
11353 && !use_return_insn (TRUE
, NULL
)
11356 else if (GET_CODE (scanbody
) == RETURN
11359 arm_ccfsm_state
= 2;
11362 else if (GET_CODE (scanbody
) == PARALLEL
)
11364 switch (get_attr_conds (this_insn
))
11374 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
11379 /* Instructions using or affecting the condition codes make it
11381 scanbody
= PATTERN (this_insn
);
11382 if (!(GET_CODE (scanbody
) == SET
11383 || GET_CODE (scanbody
) == PARALLEL
)
11384 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11387 /* A conditional cirrus instruction must be followed by
11388 a non Cirrus instruction. However, since we
11389 conditionalize instructions in this function and by
11390 the time we get here we can't add instructions
11391 (nops), because shorten_branches() has already been
11392 called, we will disable conditionalizing Cirrus
11393 instructions to be safe. */
11394 if (GET_CODE (scanbody
) != USE
11395 && GET_CODE (scanbody
) != CLOBBER
11396 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11406 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11407 arm_target_label
= CODE_LABEL_NUMBER (label
);
11408 else if (seeking_return
|| arm_ccfsm_state
== 2)
11410 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11412 this_insn
= next_nonnote_insn (this_insn
);
11413 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
11414 || GET_CODE (this_insn
) == CODE_LABEL
))
11419 /* Oh, dear! we ran off the end.. give up. */
11420 recog (PATTERN (insn
), insn
, NULL
);
11421 arm_ccfsm_state
= 0;
11422 arm_target_insn
= NULL
;
11425 arm_target_insn
= this_insn
;
11434 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11436 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11437 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11438 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11439 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11443 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11446 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11450 if (reverse
|| then_not_else
)
11451 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11454 /* Restore recog_data (getting the attributes of other insns can
11455 destroy this array, but final.c assumes that it remains intact
11456 across this call; since the insn has been recognized already we
11457 call recog direct). */
11458 recog (PATTERN (insn
), insn
, NULL
);
11462 /* Returns true if REGNO is a valid register
11463 for holding a quantity of tyoe MODE. */
11465 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11467 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11468 return regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
;
11471 /* For the Thumb we only allow values bigger than SImode in
11472 registers 0 - 6, so that there is always a second low
11473 register available to hold the upper part of the value.
11474 We probably we ought to ensure that the register is the
11475 start of an even numbered register pair. */
11476 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11478 if (IS_CIRRUS_REGNUM (regno
))
11479 /* We have outlawed SI values in Cirrus registers because they
11480 reside in the lower 32 bits, but SF values reside in the
11481 upper 32 bits. This causes gcc all sorts of grief. We can't
11482 even split the registers into pairs because Cirrus SI values
11483 get sign extended to 64bits-- aldyh. */
11484 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11486 if (IS_VFP_REGNUM (regno
))
11488 if (mode
== SFmode
|| mode
== SImode
)
11491 /* DFmode values are only valid in even register pairs. */
11492 if (mode
== DFmode
)
11493 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11497 if (IS_IWMMXT_GR_REGNUM (regno
))
11498 return mode
== SImode
;
11500 if (IS_IWMMXT_REGNUM (regno
))
11501 return VALID_IWMMXT_REG_MODE (mode
);
11503 /* We allow any value to be stored in the general registers.
11504 Restrict doubleword quantities to even register pairs so that we can
11506 if (regno
<= LAST_ARM_REGNUM
)
11507 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11509 if ( regno
== FRAME_POINTER_REGNUM
11510 || regno
== ARG_POINTER_REGNUM
)
11511 /* We only allow integers in the fake hard registers. */
11512 return GET_MODE_CLASS (mode
) == MODE_INT
;
11514 /* The only registers left are the FPA registers
11515 which we only allow to hold FP values. */
11516 return GET_MODE_CLASS (mode
) == MODE_FLOAT
11517 && regno
>= FIRST_FPA_REGNUM
11518 && regno
<= LAST_FPA_REGNUM
;
11522 arm_regno_class (int regno
)
11526 if (regno
== STACK_POINTER_REGNUM
)
11528 if (regno
== CC_REGNUM
)
11535 if ( regno
<= LAST_ARM_REGNUM
11536 || regno
== FRAME_POINTER_REGNUM
11537 || regno
== ARG_POINTER_REGNUM
)
11538 return GENERAL_REGS
;
11540 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11543 if (IS_CIRRUS_REGNUM (regno
))
11544 return CIRRUS_REGS
;
11546 if (IS_VFP_REGNUM (regno
))
11549 if (IS_IWMMXT_REGNUM (regno
))
11550 return IWMMXT_REGS
;
11552 if (IS_IWMMXT_GR_REGNUM (regno
))
11553 return IWMMXT_GR_REGS
;
11558 /* Handle a special case when computing the offset
11559 of an argument from the frame pointer. */
11561 arm_debugger_arg_offset (int value
, rtx addr
)
11565 /* We are only interested if dbxout_parms() failed to compute the offset. */
11569 /* We can only cope with the case where the address is held in a register. */
11570 if (GET_CODE (addr
) != REG
)
11573 /* If we are using the frame pointer to point at the argument, then
11574 an offset of 0 is correct. */
11575 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11578 /* If we are using the stack pointer to point at the
11579 argument, then an offset of 0 is correct. */
11580 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11581 && REGNO (addr
) == SP_REGNUM
)
11584 /* Oh dear. The argument is pointed to by a register rather
11585 than being held in a register, or being stored at a known
11586 offset from the frame pointer. Since GDB only understands
11587 those two kinds of argument we must translate the address
11588 held in the register into an offset from the frame pointer.
11589 We do this by searching through the insns for the function
11590 looking to see where this register gets its value. If the
11591 register is initialized from the frame pointer plus an offset
11592 then we are in luck and we can continue, otherwise we give up.
11594 This code is exercised by producing debugging information
11595 for a function with arguments like this:
11597 double func (double a, double b, int c, double d) {return d;}
11599 Without this code the stab for parameter 'd' will be set to
11600 an offset of 0 from the frame pointer, rather than 8. */
11602 /* The if() statement says:
11604 If the insn is a normal instruction
11605 and if the insn is setting the value in a register
11606 and if the register being set is the register holding the address of the argument
11607 and if the address is computing by an addition
11608 that involves adding to a register
11609 which is the frame pointer
11614 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11616 if ( GET_CODE (insn
) == INSN
11617 && GET_CODE (PATTERN (insn
)) == SET
11618 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
11619 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
11620 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
11621 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11622 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
11625 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
11634 warning ("unable to compute real location of stacked parameter");
11635 value
= 8; /* XXX magic hack */
11641 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11644 if ((MASK) & insn_flags) \
11645 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
11649 struct builtin_description
11651 const unsigned int mask
;
11652 const enum insn_code icode
;
11653 const char * const name
;
11654 const enum arm_builtins code
;
11655 const enum rtx_code comparison
;
11656 const unsigned int flag
;
11659 static const struct builtin_description bdesc_2arg
[] =
11661 #define IWMMXT_BUILTIN(code, string, builtin) \
11662 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11663 ARM_BUILTIN_##builtin, 0, 0 },
11665 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
11666 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
11667 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
11668 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
11669 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
11670 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
11671 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
11672 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
11673 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
11674 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
11675 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
11676 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
11677 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
11678 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
11679 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
11680 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
11681 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
11682 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
11683 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
11684 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
11685 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
11686 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
11687 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
11688 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
11689 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
11690 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
11691 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
11692 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
11693 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
11694 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
11695 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
11696 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
11697 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
11698 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
11699 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
11700 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
11701 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
11702 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
11703 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
11704 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
11705 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
11706 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
11707 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
11708 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
11709 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
11710 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
11711 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
11712 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
11713 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
11714 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
11715 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
11716 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
11717 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
11718 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
11719 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
11720 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
11721 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
11722 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
11724 #define IWMMXT_BUILTIN2(code, builtin) \
11725 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11727 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
11728 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
11729 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
11730 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
11731 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
11732 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
11733 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
11734 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
11735 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
11736 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
11737 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
11738 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
11739 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
11740 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
11741 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
11742 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
11743 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
11744 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
11745 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
11746 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
11747 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
11748 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
11749 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
11750 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
11751 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
11752 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
11753 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
11754 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
11755 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
11756 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
11757 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
11758 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
11761 static const struct builtin_description bdesc_1arg
[] =
11763 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
11764 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
11765 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
11766 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
11767 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
11768 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
11769 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
11770 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
11771 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
11772 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
11773 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
11774 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
11775 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
11776 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
11777 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
11778 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
11779 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
11780 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
11783 /* Set up all the iWMMXt builtins. This is
11784 not called if TARGET_IWMMXT is zero. */
11787 arm_init_iwmmxt_builtins (void)
11789 const struct builtin_description
* d
;
11791 tree endlink
= void_list_node
;
11793 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
11794 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
11795 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
11798 = build_function_type (integer_type_node
,
11799 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
11800 tree v8qi_ftype_v8qi_v8qi_int
11801 = build_function_type (V8QI_type_node
,
11802 tree_cons (NULL_TREE
, V8QI_type_node
,
11803 tree_cons (NULL_TREE
, V8QI_type_node
,
11804 tree_cons (NULL_TREE
,
11807 tree v4hi_ftype_v4hi_int
11808 = build_function_type (V4HI_type_node
,
11809 tree_cons (NULL_TREE
, V4HI_type_node
,
11810 tree_cons (NULL_TREE
, integer_type_node
,
11812 tree v2si_ftype_v2si_int
11813 = build_function_type (V2SI_type_node
,
11814 tree_cons (NULL_TREE
, V2SI_type_node
,
11815 tree_cons (NULL_TREE
, integer_type_node
,
11817 tree v2si_ftype_di_di
11818 = build_function_type (V2SI_type_node
,
11819 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11820 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11822 tree di_ftype_di_int
11823 = build_function_type (long_long_integer_type_node
,
11824 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11825 tree_cons (NULL_TREE
, integer_type_node
,
11827 tree di_ftype_di_int_int
11828 = build_function_type (long_long_integer_type_node
,
11829 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11830 tree_cons (NULL_TREE
, integer_type_node
,
11831 tree_cons (NULL_TREE
,
11834 tree int_ftype_v8qi
11835 = build_function_type (integer_type_node
,
11836 tree_cons (NULL_TREE
, V8QI_type_node
,
11838 tree int_ftype_v4hi
11839 = build_function_type (integer_type_node
,
11840 tree_cons (NULL_TREE
, V4HI_type_node
,
11842 tree int_ftype_v2si
11843 = build_function_type (integer_type_node
,
11844 tree_cons (NULL_TREE
, V2SI_type_node
,
11846 tree int_ftype_v8qi_int
11847 = build_function_type (integer_type_node
,
11848 tree_cons (NULL_TREE
, V8QI_type_node
,
11849 tree_cons (NULL_TREE
, integer_type_node
,
11851 tree int_ftype_v4hi_int
11852 = build_function_type (integer_type_node
,
11853 tree_cons (NULL_TREE
, V4HI_type_node
,
11854 tree_cons (NULL_TREE
, integer_type_node
,
11856 tree int_ftype_v2si_int
11857 = build_function_type (integer_type_node
,
11858 tree_cons (NULL_TREE
, V2SI_type_node
,
11859 tree_cons (NULL_TREE
, integer_type_node
,
11861 tree v8qi_ftype_v8qi_int_int
11862 = build_function_type (V8QI_type_node
,
11863 tree_cons (NULL_TREE
, V8QI_type_node
,
11864 tree_cons (NULL_TREE
, integer_type_node
,
11865 tree_cons (NULL_TREE
,
11868 tree v4hi_ftype_v4hi_int_int
11869 = build_function_type (V4HI_type_node
,
11870 tree_cons (NULL_TREE
, V4HI_type_node
,
11871 tree_cons (NULL_TREE
, integer_type_node
,
11872 tree_cons (NULL_TREE
,
11875 tree v2si_ftype_v2si_int_int
11876 = build_function_type (V2SI_type_node
,
11877 tree_cons (NULL_TREE
, V2SI_type_node
,
11878 tree_cons (NULL_TREE
, integer_type_node
,
11879 tree_cons (NULL_TREE
,
11882 /* Miscellaneous. */
11883 tree v8qi_ftype_v4hi_v4hi
11884 = build_function_type (V8QI_type_node
,
11885 tree_cons (NULL_TREE
, V4HI_type_node
,
11886 tree_cons (NULL_TREE
, V4HI_type_node
,
11888 tree v4hi_ftype_v2si_v2si
11889 = build_function_type (V4HI_type_node
,
11890 tree_cons (NULL_TREE
, V2SI_type_node
,
11891 tree_cons (NULL_TREE
, V2SI_type_node
,
11893 tree v2si_ftype_v4hi_v4hi
11894 = build_function_type (V2SI_type_node
,
11895 tree_cons (NULL_TREE
, V4HI_type_node
,
11896 tree_cons (NULL_TREE
, V4HI_type_node
,
11898 tree v2si_ftype_v8qi_v8qi
11899 = build_function_type (V2SI_type_node
,
11900 tree_cons (NULL_TREE
, V8QI_type_node
,
11901 tree_cons (NULL_TREE
, V8QI_type_node
,
11903 tree v4hi_ftype_v4hi_di
11904 = build_function_type (V4HI_type_node
,
11905 tree_cons (NULL_TREE
, V4HI_type_node
,
11906 tree_cons (NULL_TREE
,
11907 long_long_integer_type_node
,
11909 tree v2si_ftype_v2si_di
11910 = build_function_type (V2SI_type_node
,
11911 tree_cons (NULL_TREE
, V2SI_type_node
,
11912 tree_cons (NULL_TREE
,
11913 long_long_integer_type_node
,
11915 tree void_ftype_int_int
11916 = build_function_type (void_type_node
,
11917 tree_cons (NULL_TREE
, integer_type_node
,
11918 tree_cons (NULL_TREE
, integer_type_node
,
11921 = build_function_type (long_long_unsigned_type_node
, endlink
);
11923 = build_function_type (long_long_integer_type_node
,
11924 tree_cons (NULL_TREE
, V8QI_type_node
,
11927 = build_function_type (long_long_integer_type_node
,
11928 tree_cons (NULL_TREE
, V4HI_type_node
,
11931 = build_function_type (long_long_integer_type_node
,
11932 tree_cons (NULL_TREE
, V2SI_type_node
,
11934 tree v2si_ftype_v4hi
11935 = build_function_type (V2SI_type_node
,
11936 tree_cons (NULL_TREE
, V4HI_type_node
,
11938 tree v4hi_ftype_v8qi
11939 = build_function_type (V4HI_type_node
,
11940 tree_cons (NULL_TREE
, V8QI_type_node
,
11943 tree di_ftype_di_v4hi_v4hi
11944 = build_function_type (long_long_unsigned_type_node
,
11945 tree_cons (NULL_TREE
,
11946 long_long_unsigned_type_node
,
11947 tree_cons (NULL_TREE
, V4HI_type_node
,
11948 tree_cons (NULL_TREE
,
11952 tree di_ftype_v4hi_v4hi
11953 = build_function_type (long_long_unsigned_type_node
,
11954 tree_cons (NULL_TREE
, V4HI_type_node
,
11955 tree_cons (NULL_TREE
, V4HI_type_node
,
11958 /* Normal vector binops. */
11959 tree v8qi_ftype_v8qi_v8qi
11960 = build_function_type (V8QI_type_node
,
11961 tree_cons (NULL_TREE
, V8QI_type_node
,
11962 tree_cons (NULL_TREE
, V8QI_type_node
,
11964 tree v4hi_ftype_v4hi_v4hi
11965 = build_function_type (V4HI_type_node
,
11966 tree_cons (NULL_TREE
, V4HI_type_node
,
11967 tree_cons (NULL_TREE
, V4HI_type_node
,
11969 tree v2si_ftype_v2si_v2si
11970 = build_function_type (V2SI_type_node
,
11971 tree_cons (NULL_TREE
, V2SI_type_node
,
11972 tree_cons (NULL_TREE
, V2SI_type_node
,
11974 tree di_ftype_di_di
11975 = build_function_type (long_long_unsigned_type_node
,
11976 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
11977 tree_cons (NULL_TREE
,
11978 long_long_unsigned_type_node
,
11981 /* Add all builtins that are more or less simple operations on two
11983 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
11985 /* Use one of the operands; the target can have a different mode for
11986 mask-generating compares. */
11987 enum machine_mode mode
;
11993 mode
= insn_data
[d
->icode
].operand
[1].mode
;
11998 type
= v8qi_ftype_v8qi_v8qi
;
12001 type
= v4hi_ftype_v4hi_v4hi
;
12004 type
= v2si_ftype_v2si_v2si
;
12007 type
= di_ftype_di_di
;
12014 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12017 /* Add the remaining MMX insns with somewhat more complicated types. */
12018 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12019 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12020 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12022 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12023 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12024 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12025 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12026 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12027 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12029 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12030 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12031 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12032 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12033 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12034 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12036 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12037 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12038 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12039 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12040 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12041 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12043 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12044 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12045 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12046 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12047 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12048 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12050 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12052 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12053 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12054 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12055 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12057 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12058 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12059 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12060 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12061 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12062 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12063 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12064 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12065 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12067 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12068 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12069 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12071 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12072 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12073 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12075 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12076 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12077 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12078 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12079 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12080 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12082 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12083 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12084 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12085 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12086 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12087 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12088 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12089 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12090 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12091 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12092 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12093 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12095 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12096 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12097 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12098 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12100 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12101 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12102 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12103 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12104 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12105 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12106 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12110 arm_init_builtins (void)
12112 if (TARGET_REALLY_IWMMXT
)
12113 arm_init_iwmmxt_builtins ();
12116 /* Errors in the source file can cause expand_expr to return const0_rtx
12117 where we expect a vector. To avoid crashing, use one of the vector
12118 clear instructions. */
12121 safe_vector_operand (rtx x
, enum machine_mode mode
)
12123 if (x
!= const0_rtx
)
12125 x
= gen_reg_rtx (mode
);
12127 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12128 : gen_rtx_SUBREG (DImode
, x
, 0)));
12132 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12135 arm_expand_binop_builtin (enum insn_code icode
,
12136 tree arglist
, rtx target
)
12139 tree arg0
= TREE_VALUE (arglist
);
12140 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12141 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12142 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12143 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12144 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12145 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12147 if (VECTOR_MODE_P (mode0
))
12148 op0
= safe_vector_operand (op0
, mode0
);
12149 if (VECTOR_MODE_P (mode1
))
12150 op1
= safe_vector_operand (op1
, mode1
);
12153 || GET_MODE (target
) != tmode
12154 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12155 target
= gen_reg_rtx (tmode
);
12157 /* In case the insn wants input operands in modes different from
12158 the result, abort. */
12159 if (GET_MODE (op0
) != mode0
|| GET_MODE (op1
) != mode1
)
12162 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12163 op0
= copy_to_mode_reg (mode0
, op0
);
12164 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12165 op1
= copy_to_mode_reg (mode1
, op1
);
12167 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12174 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12177 arm_expand_unop_builtin (enum insn_code icode
,
12178 tree arglist
, rtx target
, int do_load
)
12181 tree arg0
= TREE_VALUE (arglist
);
12182 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12183 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12184 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12187 || GET_MODE (target
) != tmode
12188 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12189 target
= gen_reg_rtx (tmode
);
12191 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12194 if (VECTOR_MODE_P (mode0
))
12195 op0
= safe_vector_operand (op0
, mode0
);
12197 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12198 op0
= copy_to_mode_reg (mode0
, op0
);
12201 pat
= GEN_FCN (icode
) (target
, op0
);
12208 /* Expand an expression EXP that calls a built-in function,
12209 with result going to TARGET if that's convenient
12210 (and in mode MODE if that's convenient).
12211 SUBTARGET may be used as the target for computing one of EXP's operands.
12212 IGNORE is nonzero if the value is to be ignored. */
12215 arm_expand_builtin (tree exp
,
12217 rtx subtarget ATTRIBUTE_UNUSED
,
12218 enum machine_mode mode ATTRIBUTE_UNUSED
,
12219 int ignore ATTRIBUTE_UNUSED
)
12221 const struct builtin_description
* d
;
12222 enum insn_code icode
;
12223 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12224 tree arglist
= TREE_OPERAND (exp
, 1);
12232 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12234 enum machine_mode tmode
;
12235 enum machine_mode mode0
;
12236 enum machine_mode mode1
;
12237 enum machine_mode mode2
;
12241 case ARM_BUILTIN_TEXTRMSB
:
12242 case ARM_BUILTIN_TEXTRMUB
:
12243 case ARM_BUILTIN_TEXTRMSH
:
12244 case ARM_BUILTIN_TEXTRMUH
:
12245 case ARM_BUILTIN_TEXTRMSW
:
12246 case ARM_BUILTIN_TEXTRMUW
:
12247 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12248 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12249 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12250 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12251 : CODE_FOR_iwmmxt_textrmw
);
12253 arg0
= TREE_VALUE (arglist
);
12254 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12255 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12256 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12257 tmode
= insn_data
[icode
].operand
[0].mode
;
12258 mode0
= insn_data
[icode
].operand
[1].mode
;
12259 mode1
= insn_data
[icode
].operand
[2].mode
;
12261 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12262 op0
= copy_to_mode_reg (mode0
, op0
);
12263 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12265 /* @@@ better error message */
12266 error ("selector must be an immediate");
12267 return gen_reg_rtx (tmode
);
12270 || GET_MODE (target
) != tmode
12271 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12272 target
= gen_reg_rtx (tmode
);
12273 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12279 case ARM_BUILTIN_TINSRB
:
12280 case ARM_BUILTIN_TINSRH
:
12281 case ARM_BUILTIN_TINSRW
:
12282 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12283 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12284 : CODE_FOR_iwmmxt_tinsrw
);
12285 arg0
= TREE_VALUE (arglist
);
12286 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12287 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12288 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12289 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12290 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12291 tmode
= insn_data
[icode
].operand
[0].mode
;
12292 mode0
= insn_data
[icode
].operand
[1].mode
;
12293 mode1
= insn_data
[icode
].operand
[2].mode
;
12294 mode2
= insn_data
[icode
].operand
[3].mode
;
12296 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12297 op0
= copy_to_mode_reg (mode0
, op0
);
12298 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12299 op1
= copy_to_mode_reg (mode1
, op1
);
12300 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12302 /* @@@ better error message */
12303 error ("selector must be an immediate");
12307 || GET_MODE (target
) != tmode
12308 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12309 target
= gen_reg_rtx (tmode
);
12310 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12316 case ARM_BUILTIN_SETWCX
:
12317 arg0
= TREE_VALUE (arglist
);
12318 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12319 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12320 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12321 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12324 case ARM_BUILTIN_GETWCX
:
12325 arg0
= TREE_VALUE (arglist
);
12326 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12327 target
= gen_reg_rtx (SImode
);
12328 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12331 case ARM_BUILTIN_WSHUFH
:
12332 icode
= CODE_FOR_iwmmxt_wshufh
;
12333 arg0
= TREE_VALUE (arglist
);
12334 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12335 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12336 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12337 tmode
= insn_data
[icode
].operand
[0].mode
;
12338 mode1
= insn_data
[icode
].operand
[1].mode
;
12339 mode2
= insn_data
[icode
].operand
[2].mode
;
12341 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12342 op0
= copy_to_mode_reg (mode1
, op0
);
12343 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12345 /* @@@ better error message */
12346 error ("mask must be an immediate");
12350 || GET_MODE (target
) != tmode
12351 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12352 target
= gen_reg_rtx (tmode
);
12353 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12359 case ARM_BUILTIN_WSADB
:
12360 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12361 case ARM_BUILTIN_WSADH
:
12362 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12363 case ARM_BUILTIN_WSADBZ
:
12364 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12365 case ARM_BUILTIN_WSADHZ
:
12366 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12368 /* Several three-argument builtins. */
12369 case ARM_BUILTIN_WMACS
:
12370 case ARM_BUILTIN_WMACU
:
12371 case ARM_BUILTIN_WALIGN
:
12372 case ARM_BUILTIN_TMIA
:
12373 case ARM_BUILTIN_TMIAPH
:
12374 case ARM_BUILTIN_TMIATT
:
12375 case ARM_BUILTIN_TMIATB
:
12376 case ARM_BUILTIN_TMIABT
:
12377 case ARM_BUILTIN_TMIABB
:
12378 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12379 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12380 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12381 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12382 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12383 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12384 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12385 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12386 : CODE_FOR_iwmmxt_walign
);
12387 arg0
= TREE_VALUE (arglist
);
12388 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12389 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12390 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12391 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12392 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12393 tmode
= insn_data
[icode
].operand
[0].mode
;
12394 mode0
= insn_data
[icode
].operand
[1].mode
;
12395 mode1
= insn_data
[icode
].operand
[2].mode
;
12396 mode2
= insn_data
[icode
].operand
[3].mode
;
12398 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12399 op0
= copy_to_mode_reg (mode0
, op0
);
12400 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12401 op1
= copy_to_mode_reg (mode1
, op1
);
12402 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12403 op2
= copy_to_mode_reg (mode2
, op2
);
12405 || GET_MODE (target
) != tmode
12406 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12407 target
= gen_reg_rtx (tmode
);
12408 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12414 case ARM_BUILTIN_WZERO
:
12415 target
= gen_reg_rtx (DImode
);
12416 emit_insn (gen_iwmmxt_clrdi (target
));
12423 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12424 if (d
->code
== (const enum arm_builtins
) fcode
)
12425 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12427 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12428 if (d
->code
== (const enum arm_builtins
) fcode
)
12429 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12431 /* @@@ Should really do something sensible here. */
12435 /* Recursively search through all of the blocks in a function
12436 checking to see if any of the variables created in that
12437 function match the RTX called 'orig'. If they do then
12438 replace them with the RTX called 'new'. */
12440 replace_symbols_in_block (tree block
, rtx orig
, rtx
new)
12442 for (; block
; block
= BLOCK_CHAIN (block
))
12446 if (!TREE_USED (block
))
12449 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
12451 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
12452 || DECL_IGNORED_P (sym
)
12453 || TREE_CODE (sym
) != VAR_DECL
12454 || DECL_EXTERNAL (sym
)
12455 || !rtx_equal_p (DECL_RTL (sym
), orig
)
12459 SET_DECL_RTL (sym
, new);
12462 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
12466 /* Return the number (counting from 0) of
12467 the least significant set bit in MASK. */
12470 number_of_first_bit_set (int mask
)
12475 (mask
& (1 << bit
)) == 0;
12482 /* Generate code to return from a thumb function.
12483 If 'reg_containing_return_addr' is -1, then the return address is
12484 actually on the stack, at the stack pointer. */
12486 thumb_exit (FILE *f
, int reg_containing_return_addr
, rtx eh_ofs
)
12488 unsigned regs_available_for_popping
;
12489 unsigned regs_to_pop
;
12491 unsigned available
;
12495 int restore_a4
= FALSE
;
12497 /* Compute the registers we need to pop. */
12501 /* There is an assumption here, that if eh_ofs is not NULL, the
12502 normal return address will have been pushed. */
12503 if (reg_containing_return_addr
== -1 || eh_ofs
)
12505 /* When we are generating a return for __builtin_eh_return,
12506 reg_containing_return_addr must specify the return regno. */
12507 if (eh_ofs
&& reg_containing_return_addr
== -1)
12510 regs_to_pop
|= 1 << LR_REGNUM
;
12514 if (TARGET_BACKTRACE
)
12516 /* Restore the (ARM) frame pointer and stack pointer. */
12517 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12521 /* If there is nothing to pop then just emit the BX instruction and
12523 if (pops_needed
== 0)
12526 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
12528 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12531 /* Otherwise if we are not supporting interworking and we have not created
12532 a backtrace structure and the function was not entered in ARM mode then
12533 just pop the return address straight into the PC. */
12534 else if (!TARGET_INTERWORK
12535 && !TARGET_BACKTRACE
12536 && !is_called_in_ARM_mode (current_function_decl
))
12540 asm_fprintf (f
, "\tadd\t%r, #4\n", SP_REGNUM
);
12541 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
12542 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12545 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
12550 /* Find out how many of the (return) argument registers we can corrupt. */
12551 regs_available_for_popping
= 0;
12553 /* If returning via __builtin_eh_return, the bottom three registers
12554 all contain information needed for the return. */
12560 /* If we can deduce the registers used from the function's
12561 return value. This is more reliable that examining
12562 regs_ever_live[] because that will be set if the register is
12563 ever used in the function, not just if the register is used
12564 to hold a return value. */
12566 if (current_function_return_rtx
!= 0)
12567 mode
= GET_MODE (current_function_return_rtx
);
12570 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
12572 size
= GET_MODE_SIZE (mode
);
12576 /* In a void function we can use any argument register.
12577 In a function that returns a structure on the stack
12578 we can use the second and third argument registers. */
12579 if (mode
== VOIDmode
)
12580 regs_available_for_popping
=
12581 (1 << ARG_REGISTER (1))
12582 | (1 << ARG_REGISTER (2))
12583 | (1 << ARG_REGISTER (3));
12585 regs_available_for_popping
=
12586 (1 << ARG_REGISTER (2))
12587 | (1 << ARG_REGISTER (3));
12589 else if (size
<= 4)
12590 regs_available_for_popping
=
12591 (1 << ARG_REGISTER (2))
12592 | (1 << ARG_REGISTER (3));
12593 else if (size
<= 8)
12594 regs_available_for_popping
=
12595 (1 << ARG_REGISTER (3));
12598 /* Match registers to be popped with registers into which we pop them. */
12599 for (available
= regs_available_for_popping
,
12600 required
= regs_to_pop
;
12601 required
!= 0 && available
!= 0;
12602 available
&= ~(available
& - available
),
12603 required
&= ~(required
& - required
))
12606 /* If we have any popping registers left over, remove them. */
12608 regs_available_for_popping
&= ~available
;
12610 /* Otherwise if we need another popping register we can use
12611 the fourth argument register. */
12612 else if (pops_needed
)
12614 /* If we have not found any free argument registers and
12615 reg a4 contains the return address, we must move it. */
12616 if (regs_available_for_popping
== 0
12617 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
12619 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12620 reg_containing_return_addr
= LR_REGNUM
;
12622 else if (size
> 12)
12624 /* Register a4 is being used to hold part of the return value,
12625 but we have dire need of a free, low register. */
12628 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
12631 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
12633 /* The fourth argument register is available. */
12634 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
12640 /* Pop as many registers as we can. */
12641 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12642 regs_available_for_popping
);
12644 /* Process the registers we popped. */
12645 if (reg_containing_return_addr
== -1)
12647 /* The return address was popped into the lowest numbered register. */
12648 regs_to_pop
&= ~(1 << LR_REGNUM
);
12650 reg_containing_return_addr
=
12651 number_of_first_bit_set (regs_available_for_popping
);
12653 /* Remove this register for the mask of available registers, so that
12654 the return address will not be corrupted by further pops. */
12655 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
12658 /* If we popped other registers then handle them here. */
12659 if (regs_available_for_popping
)
12663 /* Work out which register currently contains the frame pointer. */
12664 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12666 /* Move it into the correct place. */
12667 asm_fprintf (f
, "\tmov\t%r, %r\n",
12668 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
12670 /* (Temporarily) remove it from the mask of popped registers. */
12671 regs_available_for_popping
&= ~(1 << frame_pointer
);
12672 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
12674 if (regs_available_for_popping
)
12678 /* We popped the stack pointer as well,
12679 find the register that contains it. */
12680 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12682 /* Move it into the stack register. */
12683 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
12685 /* At this point we have popped all necessary registers, so
12686 do not worry about restoring regs_available_for_popping
12687 to its correct value:
12689 assert (pops_needed == 0)
12690 assert (regs_available_for_popping == (1 << frame_pointer))
12691 assert (regs_to_pop == (1 << STACK_POINTER)) */
12695 /* Since we have just move the popped value into the frame
12696 pointer, the popping register is available for reuse, and
12697 we know that we still have the stack pointer left to pop. */
12698 regs_available_for_popping
|= (1 << frame_pointer
);
12702 /* If we still have registers left on the stack, but we no longer have
12703 any registers into which we can pop them, then we must move the return
12704 address into the link register and make available the register that
12706 if (regs_available_for_popping
== 0 && pops_needed
> 0)
12708 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
12710 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
12711 reg_containing_return_addr
);
12713 reg_containing_return_addr
= LR_REGNUM
;
12716 /* If we have registers left on the stack then pop some more.
12717 We know that at most we will want to pop FP and SP. */
12718 if (pops_needed
> 0)
12723 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12724 regs_available_for_popping
);
12726 /* We have popped either FP or SP.
12727 Move whichever one it is into the correct register. */
12728 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12729 move_to
= number_of_first_bit_set (regs_to_pop
);
12731 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
12733 regs_to_pop
&= ~(1 << move_to
);
12738 /* If we still have not popped everything then we must have only
12739 had one register available to us and we are now popping the SP. */
12740 if (pops_needed
> 0)
12744 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12745 regs_available_for_popping
);
12747 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12749 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
12751 assert (regs_to_pop == (1 << STACK_POINTER))
12752 assert (pops_needed == 1)
12756 /* If necessary restore the a4 register. */
12759 if (reg_containing_return_addr
!= LR_REGNUM
)
12761 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12762 reg_containing_return_addr
= LR_REGNUM
;
12765 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
12769 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
12771 /* Return to caller. */
12772 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12775 /* Emit code to push or pop registers to or from the stack. F is the
12776 assembly file. MASK is the registers to push or pop. PUSH is
12777 nonzero if we should push, and zero if we should pop. For debugging
12778 output, if pushing, adjust CFA_OFFSET by the amount of space added
12779 to the stack. REAL_REGS should have the same number of bits set as
12780 MASK, and will be used instead (in the same order) to describe which
12781 registers were saved - this is used to mark the save slots when we
12782 push high registers after moving them to low registers. */
12784 thumb_pushpop (FILE *f
, int mask
, int push
, int *cfa_offset
, int real_regs
)
12787 int lo_mask
= mask
& 0xFF;
12788 int pushed_words
= 0;
12790 if (lo_mask
== 0 && !push
&& (mask
& (1 << 15)))
12792 /* Special case. Do not generate a POP PC statement here, do it in
12794 thumb_exit (f
, -1, NULL_RTX
);
12798 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12800 /* Look at the low registers first. */
12801 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12805 asm_fprintf (f
, "%r", regno
);
12807 if ((lo_mask
& ~1) != 0)
12814 if (push
&& (mask
& (1 << LR_REGNUM
)))
12816 /* Catch pushing the LR. */
12820 asm_fprintf (f
, "%r", LR_REGNUM
);
12824 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12826 /* Catch popping the PC. */
12827 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
)
12829 /* The PC is never poped directly, instead
12830 it is popped into r3 and then BX is used. */
12831 fprintf (f
, "}\n");
12833 thumb_exit (f
, -1, NULL_RTX
);
12842 asm_fprintf (f
, "%r", PC_REGNUM
);
12846 fprintf (f
, "}\n");
12848 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12850 char *l
= dwarf2out_cfi_label ();
12851 int pushed_mask
= real_regs
;
12853 *cfa_offset
+= pushed_words
* 4;
12854 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12857 pushed_mask
= real_regs
;
12858 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12860 if (pushed_mask
& 1)
12861 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12867 thumb_final_prescan_insn (rtx insn
)
12869 if (flag_print_asm_name
)
12870 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
12871 INSN_ADDRESSES (INSN_UID (insn
)));
12875 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
12877 unsigned HOST_WIDE_INT mask
= 0xff;
12880 if (val
== 0) /* XXX */
12883 for (i
= 0; i
< 25; i
++)
12884 if ((val
& (mask
<< i
)) == val
)
12890 /* Returns nonzero if the current function contains,
12891 or might contain a far jump. */
12893 thumb_far_jump_used_p (void)
12897 /* This test is only important for leaf functions. */
12898 /* assert (!leaf_function_p ()); */
12900 /* If we have already decided that far jumps may be used,
12901 do not bother checking again, and always return true even if
12902 it turns out that they are not being used. Once we have made
12903 the decision that far jumps are present (and that hence the link
12904 register will be pushed onto the stack) we cannot go back on it. */
12905 if (cfun
->machine
->far_jump_used
)
12908 /* If this function is not being called from the prologue/epilogue
12909 generation code then it must be being called from the
12910 INITIAL_ELIMINATION_OFFSET macro. */
12911 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
12913 /* In this case we know that we are being asked about the elimination
12914 of the arg pointer register. If that register is not being used,
12915 then there are no arguments on the stack, and we do not have to
12916 worry that a far jump might force the prologue to push the link
12917 register, changing the stack offsets. In this case we can just
12918 return false, since the presence of far jumps in the function will
12919 not affect stack offsets.
12921 If the arg pointer is live (or if it was live, but has now been
12922 eliminated and so set to dead) then we do have to test to see if
12923 the function might contain a far jump. This test can lead to some
12924 false negatives, since before reload is completed, then length of
12925 branch instructions is not known, so gcc defaults to returning their
12926 longest length, which in turn sets the far jump attribute to true.
12928 A false negative will not result in bad code being generated, but it
12929 will result in a needless push and pop of the link register. We
12930 hope that this does not occur too often.
12932 If we need doubleword stack alignment this could affect the other
12933 elimination offsets so we can't risk getting it wrong. */
12934 if (regs_ever_live
[ARG_POINTER_REGNUM
])
12935 cfun
->machine
->arg_pointer_live
= 1;
12936 else if (!cfun
->machine
->arg_pointer_live
)
12940 /* Check to see if the function contains a branch
12941 insn with the far jump attribute set. */
12942 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12944 if (GET_CODE (insn
) == JUMP_INSN
12945 /* Ignore tablejump patterns. */
12946 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
12947 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
12948 && get_attr_far_jump (insn
) == FAR_JUMP_YES
12951 /* Record the fact that we have decided that
12952 the function does use far jumps. */
12953 cfun
->machine
->far_jump_used
= 1;
12961 /* Return nonzero if FUNC must be entered in ARM mode. */
12963 is_called_in_ARM_mode (tree func
)
12965 if (TREE_CODE (func
) != FUNCTION_DECL
)
12968 /* Ignore the problem about functions whoes address is taken. */
12969 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
12973 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
12979 /* The bits which aren't usefully expanded as rtl. */
12981 thumb_unexpanded_epilogue (void)
12984 int live_regs_mask
= 0;
12985 int high_regs_pushed
= 0;
12986 int leaf_function
= leaf_function_p ();
12987 int had_to_push_lr
;
12988 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
12990 if (return_used_this_function
)
12993 if (IS_NAKED (arm_current_func_type ()))
12996 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
12997 if (THUMB_REG_PUSHED_P (regno
))
12998 live_regs_mask
|= 1 << regno
;
13000 for (regno
= 8; regno
< 13; regno
++)
13001 if (THUMB_REG_PUSHED_P (regno
))
13002 high_regs_pushed
++;
13004 /* The prolog may have pushed some high registers to use as
13005 work registers. eg the testsuite file:
13006 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13007 compiles to produce:
13008 push {r4, r5, r6, r7, lr}
13012 as part of the prolog. We have to undo that pushing here. */
13014 if (high_regs_pushed
)
13016 int mask
= live_regs_mask
;
13022 /* If we can deduce the registers used from the function's return value.
13023 This is more reliable that examining regs_ever_live[] because that
13024 will be set if the register is ever used in the function, not just if
13025 the register is used to hold a return value. */
13027 if (current_function_return_rtx
!= 0)
13028 mode
= GET_MODE (current_function_return_rtx
);
13031 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
13033 size
= GET_MODE_SIZE (mode
);
13035 /* Unless we are returning a type of size > 12 register r3 is
13041 /* Oh dear! We have no low registers into which we can pop
13044 ("no low registers available for popping high registers");
13046 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13047 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13050 while (high_regs_pushed
)
13052 /* Find lo register(s) into which the high register(s) can
13054 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13056 if (mask
& (1 << regno
))
13057 high_regs_pushed
--;
13058 if (high_regs_pushed
== 0)
13062 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13064 /* Pop the values into the low register(s). */
13065 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13067 /* Move the value(s) into the high registers. */
13068 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13070 if (mask
& (1 << regno
))
13072 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13075 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13076 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13083 had_to_push_lr
= (live_regs_mask
|| !leaf_function
13084 || thumb_far_jump_used_p ());
13086 if (TARGET_BACKTRACE
13087 && ((live_regs_mask
& 0xFF) == 0)
13088 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
13090 /* The stack backtrace structure creation code had to
13091 push R7 in order to get a work register, so we pop
13093 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
13096 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13099 && !is_called_in_ARM_mode (current_function_decl
)
13101 live_regs_mask
|= 1 << PC_REGNUM
;
13103 /* Either no argument registers were pushed or a backtrace
13104 structure was created which includes an adjusted stack
13105 pointer, so just pop everything. */
13106 if (live_regs_mask
)
13107 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13111 thumb_exit (asm_out_file
, 2, eh_ofs
);
13112 /* We have either just popped the return address into the
13113 PC or it is was kept in LR for the entire function or
13114 it is still on the stack because we do not want to
13115 return by doing a pop {pc}. */
13116 else if ((live_regs_mask
& (1 << PC_REGNUM
)) == 0)
13117 thumb_exit (asm_out_file
,
13119 && is_called_in_ARM_mode (current_function_decl
)) ?
13120 -1 : LR_REGNUM
, NULL_RTX
);
13124 /* Pop everything but the return address. */
13125 live_regs_mask
&= ~(1 << PC_REGNUM
);
13127 if (live_regs_mask
)
13128 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13131 if (had_to_push_lr
)
13132 /* Get the return address into a temporary register. */
13133 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13134 1 << LAST_ARG_REGNUM
);
13136 /* Remove the argument registers that were pushed onto the stack. */
13137 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13138 SP_REGNUM
, SP_REGNUM
,
13139 current_function_pretend_args_size
);
13142 thumb_exit (asm_out_file
, 2, eh_ofs
);
13144 thumb_exit (asm_out_file
,
13145 had_to_push_lr
? LAST_ARG_REGNUM
: LR_REGNUM
, NULL_RTX
);
13151 /* Functions to save and restore machine-specific function data. */
13152 static struct machine_function
*
13153 arm_init_machine_status (void)
13155 struct machine_function
*machine
;
13156 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13158 #if ARM_FT_UNKNOWN != 0
13159 machine
->func_type
= ARM_FT_UNKNOWN
;
13164 /* Return an RTX indicating where the return address to the
13165 calling function can be found. */
13167 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13172 if (TARGET_APCS_32
)
13173 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13176 rtx lr
= gen_rtx_AND (Pmode
, gen_rtx_REG (Pmode
, LR_REGNUM
),
13177 GEN_INT (RETURN_ADDR_MASK26
));
13178 return get_func_hard_reg_initial_val (cfun
, lr
);
13182 /* Do anything needed before RTL is emitted for each function. */
13184 arm_init_expanders (void)
13186 /* Arrange to initialize and mark the machine per-function status. */
13187 init_machine_status
= arm_init_machine_status
;
13191 /* Like arm_compute_initial_elimination offset. Simpler because
13192 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13195 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13197 arm_stack_offsets
*offsets
;
13199 offsets
= arm_get_frame_offsets ();
13203 case ARG_POINTER_REGNUM
:
13206 case STACK_POINTER_REGNUM
:
13207 return offsets
->outgoing_args
- offsets
->saved_args
;
13209 case FRAME_POINTER_REGNUM
:
13210 return offsets
->soft_frame
- offsets
->saved_args
;
13212 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13213 case ARM_HARD_FRAME_POINTER_REGNUM
:
13214 return offsets
->saved_regs
- offsets
->saved_args
;
13221 case FRAME_POINTER_REGNUM
:
13224 case STACK_POINTER_REGNUM
:
13225 return offsets
->outgoing_args
- offsets
->soft_frame
;
13227 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13228 case ARM_HARD_FRAME_POINTER_REGNUM
:
13229 return offsets
->saved_regs
- offsets
->soft_frame
;
13242 /* Generate the rest of a function's prologue. */
13244 thumb_expand_prologue (void)
13248 HOST_WIDE_INT amount
;
13249 arm_stack_offsets
*offsets
;
13250 unsigned long func_type
;
13252 func_type
= arm_current_func_type ();
13254 /* Naked functions don't have prologues. */
13255 if (IS_NAKED (func_type
))
13258 if (IS_INTERRUPT (func_type
))
13260 error ("interrupt Service Routines cannot be coded in Thumb mode");
13264 offsets
= arm_get_frame_offsets ();
13266 if (frame_pointer_needed
)
13268 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
13269 stack_pointer_rtx
));
13270 RTX_FRAME_RELATED_P (insn
) = 1;
13273 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13278 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13279 GEN_INT (- amount
)));
13280 RTX_FRAME_RELATED_P (insn
) = 1;
13287 /* The stack decrement is too big for an immediate value in a single
13288 insn. In theory we could issue multiple subtracts, but after
13289 three of them it becomes more space efficient to place the full
13290 value in the constant pool and load into a register. (Also the
13291 ARM debugger really likes to see only one stack decrement per
13292 function). So instead we look for a scratch register into which
13293 we can load the decrement, and then we subtract this from the
13294 stack pointer. Unfortunately on the thumb the only available
13295 scratch registers are the argument registers, and we cannot use
13296 these as they may hold arguments to the function. Instead we
13297 attempt to locate a call preserved register which is used by this
13298 function. If we can find one, then we know that it will have
13299 been pushed at the start of the prologue and so we can corrupt
13301 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13302 if (THUMB_REG_PUSHED_P (regno
)
13303 && !(frame_pointer_needed
13304 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13307 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13309 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13311 /* Choose an arbitrary, non-argument low register. */
13312 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13314 /* Save it by copying it into a high, scratch register. */
13315 emit_insn (gen_movsi (spare
, reg
));
13316 /* Add a USE to stop propagate_one_insn() from barfing. */
13317 emit_insn (gen_prologue_use (spare
));
13319 /* Decrement the stack. */
13320 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13321 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13322 stack_pointer_rtx
, reg
));
13323 RTX_FRAME_RELATED_P (insn
) = 1;
13324 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13325 plus_constant (stack_pointer_rtx
,
13326 GEN_INT (- amount
)));
13327 RTX_FRAME_RELATED_P (dwarf
) = 1;
13329 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13332 /* Restore the low register's original value. */
13333 emit_insn (gen_movsi (reg
, spare
));
13335 /* Emit a USE of the restored scratch register, so that flow
13336 analysis will not consider the restore redundant. The
13337 register won't be used again in this function and isn't
13338 restored by the epilogue. */
13339 emit_insn (gen_prologue_use (reg
));
13343 reg
= gen_rtx_REG (SImode
, regno
);
13345 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13347 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13348 stack_pointer_rtx
, reg
));
13349 RTX_FRAME_RELATED_P (insn
) = 1;
13350 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13351 plus_constant (stack_pointer_rtx
,
13352 GEN_INT (- amount
)));
13353 RTX_FRAME_RELATED_P (dwarf
) = 1;
13355 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13359 /* If the frame pointer is needed, emit a special barrier that
13360 will prevent the scheduler from moving stores to the frame
13361 before the stack adjustment. */
13362 if (frame_pointer_needed
)
13363 emit_insn (gen_stack_tie (stack_pointer_rtx
,
13364 hard_frame_pointer_rtx
));
13367 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
13368 emit_insn (gen_blockage ());
13372 thumb_expand_epilogue (void)
13374 HOST_WIDE_INT amount
;
13375 arm_stack_offsets
*offsets
;
13378 /* Naked functions don't have prologues. */
13379 if (IS_NAKED (arm_current_func_type ()))
13382 offsets
= arm_get_frame_offsets ();
13383 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13385 if (frame_pointer_needed
)
13386 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13390 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13391 GEN_INT (amount
)));
13394 /* r3 is always free in the epilogue. */
13395 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13397 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13398 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13402 /* Emit a USE (stack_pointer_rtx), so that
13403 the stack adjustment will not be deleted. */
13404 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13406 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
13407 emit_insn (gen_blockage ());
13409 /* Emit a clobber for each insn that will be restored in the epilogue,
13410 so that flow2 will get register lifetimes correct. */
13411 for (regno
= 0; regno
< 13; regno
++)
13412 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13413 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13415 if (! regs_ever_live
[LR_REGNUM
])
13416 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13420 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13422 int live_regs_mask
= 0;
13423 int high_regs_pushed
= 0;
13424 int cfa_offset
= 0;
13427 if (IS_NAKED (arm_current_func_type ()))
13430 if (is_called_in_ARM_mode (current_function_decl
))
13434 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
13436 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
13438 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13440 /* Generate code sequence to switch us into Thumb mode. */
13441 /* The .code 32 directive has already been emitted by
13442 ASM_DECLARE_FUNCTION_NAME. */
13443 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13444 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13446 /* Generate a label, so that the debugger will notice the
13447 change in instruction sets. This label is also used by
13448 the assembler to bypass the ARM code when this function
13449 is called from a Thumb encoded function elsewhere in the
13450 same file. Hence the definition of STUB_NAME here must
13451 agree with the definition in gas/config/tc-arm.c. */
13453 #define STUB_NAME ".real_start_of"
13455 fprintf (f
, "\t.code\t16\n");
13457 if (arm_dllexport_name_p (name
))
13458 name
= arm_strip_name_encoding (name
);
13460 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13461 fprintf (f
, "\t.thumb_func\n");
13462 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13465 if (current_function_pretend_args_size
)
13467 if (cfun
->machine
->uses_anonymous_args
)
13471 fprintf (f
, "\tpush\t{");
13473 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13475 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13476 regno
<= LAST_ARG_REGNUM
;
13478 asm_fprintf (f
, "%r%s", regno
,
13479 regno
== LAST_ARG_REGNUM
? "" : ", ");
13481 fprintf (f
, "}\n");
13484 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13485 SP_REGNUM
, SP_REGNUM
,
13486 current_function_pretend_args_size
);
13488 /* We don't need to record the stores for unwinding (would it
13489 help the debugger any if we did?), but record the change in
13490 the stack pointer. */
13491 if (dwarf2out_do_frame ())
13493 char *l
= dwarf2out_cfi_label ();
13494 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13495 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13499 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13500 if (THUMB_REG_PUSHED_P (regno
))
13501 live_regs_mask
|= 1 << regno
;
13503 if (live_regs_mask
|| !leaf_function_p () || thumb_far_jump_used_p ())
13504 live_regs_mask
|= 1 << LR_REGNUM
;
13506 if (TARGET_BACKTRACE
)
13509 int work_register
= 0;
13512 /* We have been asked to create a stack backtrace structure.
13513 The code looks like this:
13517 0 sub SP, #16 Reserve space for 4 registers.
13518 2 push {R7} Get a work register.
13519 4 add R7, SP, #20 Get the stack pointer before the push.
13520 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13521 8 mov R7, PC Get hold of the start of this code plus 12.
13522 10 str R7, [SP, #16] Store it.
13523 12 mov R7, FP Get hold of the current frame pointer.
13524 14 str R7, [SP, #4] Store it.
13525 16 mov R7, LR Get hold of the current return address.
13526 18 str R7, [SP, #12] Store it.
13527 20 add R7, SP, #16 Point at the start of the backtrace structure.
13528 22 mov FP, R7 Put this value into the frame pointer. */
13530 if ((live_regs_mask
& 0xFF) == 0)
13532 /* See if the a4 register is free. */
13534 if (regs_ever_live
[LAST_ARG_REGNUM
] == 0)
13535 work_register
= LAST_ARG_REGNUM
;
13536 else /* We must push a register of our own. */
13537 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
13540 if (work_register
== 0)
13542 /* Select a register from the list that will be pushed to
13543 use as our work register. */
13544 for (work_register
= (LAST_LO_REGNUM
+ 1); work_register
--;)
13545 if ((1 << work_register
) & live_regs_mask
)
13550 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13551 SP_REGNUM
, SP_REGNUM
);
13553 if (dwarf2out_do_frame ())
13555 char *l
= dwarf2out_cfi_label ();
13556 cfa_offset
= cfa_offset
+ 16;
13557 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13560 if (live_regs_mask
)
13561 thumb_pushpop (f
, live_regs_mask
, 1, &cfa_offset
, live_regs_mask
);
13563 for (offset
= 0, wr
= 1 << 15; wr
!= 0; wr
>>= 1)
13564 if (wr
& live_regs_mask
)
13567 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13568 offset
+ 16 + current_function_pretend_args_size
);
13570 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13573 /* Make sure that the instruction fetching the PC is in the right place
13574 to calculate "start of backtrace creation code + 12". */
13575 if (live_regs_mask
)
13577 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13578 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13580 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13581 ARM_HARD_FRAME_POINTER_REGNUM
);
13582 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13587 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13588 ARM_HARD_FRAME_POINTER_REGNUM
);
13589 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13591 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13592 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13596 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13597 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13599 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13601 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13602 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
13604 else if (live_regs_mask
)
13605 thumb_pushpop (f
, live_regs_mask
, 1, &cfa_offset
, live_regs_mask
);
13607 for (regno
= 8; regno
< 13; regno
++)
13608 if (THUMB_REG_PUSHED_P (regno
))
13609 high_regs_pushed
++;
13611 if (high_regs_pushed
)
13613 int pushable_regs
= 0;
13614 int mask
= live_regs_mask
& 0xff;
13617 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
13618 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13621 pushable_regs
= mask
;
13623 if (pushable_regs
== 0)
13625 /* Desperation time -- this probably will never happen. */
13626 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
))
13627 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, LAST_ARG_REGNUM
);
13628 mask
= 1 << LAST_ARG_REGNUM
;
13631 while (high_regs_pushed
> 0)
13633 int real_regs_mask
= 0;
13635 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
13637 if (mask
& (1 << regno
))
13639 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
13641 high_regs_pushed
--;
13642 real_regs_mask
|= (1 << next_hi_reg
);
13644 if (high_regs_pushed
)
13646 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
13648 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13653 mask
&= ~((1 << regno
) - 1);
13659 thumb_pushpop (f
, mask
, 1, &cfa_offset
, real_regs_mask
);
13662 if (pushable_regs
== 0
13663 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
)))
13664 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
13668 /* Handle the case of a double word load into a low register from
13669 a computed memory address. The computed address may involve a
13670 register which is overwritten by the load. */
13672 thumb_load_double_from_address (rtx
*operands
)
13680 if (GET_CODE (operands
[0]) != REG
)
13683 if (GET_CODE (operands
[1]) != MEM
)
13686 /* Get the memory address. */
13687 addr
= XEXP (operands
[1], 0);
13689 /* Work out how the memory address is computed. */
13690 switch (GET_CODE (addr
))
13693 operands
[2] = gen_rtx_MEM (SImode
,
13694 plus_constant (XEXP (operands
[1], 0), 4));
13696 if (REGNO (operands
[0]) == REGNO (addr
))
13698 output_asm_insn ("ldr\t%H0, %2", operands
);
13699 output_asm_insn ("ldr\t%0, %1", operands
);
13703 output_asm_insn ("ldr\t%0, %1", operands
);
13704 output_asm_insn ("ldr\t%H0, %2", operands
);
13709 /* Compute <address> + 4 for the high order load. */
13710 operands
[2] = gen_rtx_MEM (SImode
,
13711 plus_constant (XEXP (operands
[1], 0), 4));
13713 output_asm_insn ("ldr\t%0, %1", operands
);
13714 output_asm_insn ("ldr\t%H0, %2", operands
);
13718 arg1
= XEXP (addr
, 0);
13719 arg2
= XEXP (addr
, 1);
13721 if (CONSTANT_P (arg1
))
13722 base
= arg2
, offset
= arg1
;
13724 base
= arg1
, offset
= arg2
;
13726 if (GET_CODE (base
) != REG
)
13729 /* Catch the case of <address> = <reg> + <reg> */
13730 if (GET_CODE (offset
) == REG
)
13732 int reg_offset
= REGNO (offset
);
13733 int reg_base
= REGNO (base
);
13734 int reg_dest
= REGNO (operands
[0]);
13736 /* Add the base and offset registers together into the
13737 higher destination register. */
13738 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
13739 reg_dest
+ 1, reg_base
, reg_offset
);
13741 /* Load the lower destination register from the address in
13742 the higher destination register. */
13743 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
13744 reg_dest
, reg_dest
+ 1);
13746 /* Load the higher destination register from its own address
13748 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
13749 reg_dest
+ 1, reg_dest
+ 1);
13753 /* Compute <address> + 4 for the high order load. */
13754 operands
[2] = gen_rtx_MEM (SImode
,
13755 plus_constant (XEXP (operands
[1], 0), 4));
13757 /* If the computed address is held in the low order register
13758 then load the high order register first, otherwise always
13759 load the low order register first. */
13760 if (REGNO (operands
[0]) == REGNO (base
))
13762 output_asm_insn ("ldr\t%H0, %2", operands
);
13763 output_asm_insn ("ldr\t%0, %1", operands
);
13767 output_asm_insn ("ldr\t%0, %1", operands
);
13768 output_asm_insn ("ldr\t%H0, %2", operands
);
13774 /* With no registers to worry about we can just load the value
13776 operands
[2] = gen_rtx_MEM (SImode
,
13777 plus_constant (XEXP (operands
[1], 0), 4));
13779 output_asm_insn ("ldr\t%H0, %2", operands
);
13780 output_asm_insn ("ldr\t%0, %1", operands
);
13792 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
13799 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13802 operands
[4] = operands
[5];
13805 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
13806 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
13810 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13813 operands
[4] = operands
[5];
13816 if (REGNO (operands
[5]) > REGNO (operands
[6]))
13819 operands
[5] = operands
[6];
13822 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13825 operands
[4] = operands
[5];
13829 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
13830 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
13840 /* Routines for generating rtl. */
13842 thumb_expand_movstrqi (rtx
*operands
)
13844 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
13845 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
13846 HOST_WIDE_INT len
= INTVAL (operands
[2]);
13847 HOST_WIDE_INT offset
= 0;
13851 emit_insn (gen_movmem12b (out
, in
, out
, in
));
13857 emit_insn (gen_movmem8b (out
, in
, out
, in
));
13863 rtx reg
= gen_reg_rtx (SImode
);
13864 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
13865 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
13872 rtx reg
= gen_reg_rtx (HImode
);
13873 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
13874 plus_constant (in
, offset
))));
13875 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
13883 rtx reg
= gen_reg_rtx (QImode
);
13884 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
13885 plus_constant (in
, offset
))));
13886 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
13892 thumb_cmp_operand (rtx op
, enum machine_mode mode
)
13894 return ((GET_CODE (op
) == CONST_INT
13895 && INTVAL (op
) < 256
13896 && INTVAL (op
) >= 0)
13897 || s_register_operand (op
, mode
));
13901 thumb_cmpneg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
13903 return (GET_CODE (op
) == CONST_INT
13905 && INTVAL (op
) > -256);
13908 /* Return TRUE if a result can be stored in OP without clobbering the
13909 condition code register. Prior to reload we only accept a
13910 register. After reload we have to be able to handle memory as
13911 well, since a pseudo may not get a hard reg and reload cannot
13912 handle output-reloads on jump insns.
13914 We could possibly handle mem before reload as well, but that might
13915 complicate things with the need to handle increment
13919 thumb_cbrch_target_operand (rtx op
, enum machine_mode mode
)
13921 return (s_register_operand (op
, mode
)
13922 || ((reload_in_progress
|| reload_completed
)
13923 && memory_operand (op
, mode
)));
13926 /* Handle storing a half-word to memory during reload. */
13928 thumb_reload_out_hi (rtx
*operands
)
13930 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
13933 /* Handle reading a half-word from memory during reload. */
13935 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
13940 /* Return the length of a function name prefix
13941 that starts with the character 'c'. */
13943 arm_get_strip_length (int c
)
13947 ARM_NAME_ENCODING_LENGTHS
13952 /* Return a pointer to a function's name with any
13953 and all prefix encodings stripped from it. */
13955 arm_strip_name_encoding (const char *name
)
13959 while ((skip
= arm_get_strip_length (* name
)))
13965 /* If there is a '*' anywhere in the name's prefix, then
13966 emit the stripped name verbatim, otherwise prepend an
13967 underscore if leading underscores are being used. */
13969 arm_asm_output_labelref (FILE *stream
, const char *name
)
13974 while ((skip
= arm_get_strip_length (* name
)))
13976 verbatim
|= (*name
== '*');
13981 fputs (name
, stream
);
13983 asm_fprintf (stream
, "%U%s", name
);
13988 #ifdef AOF_ASSEMBLER
13989 /* Special functions only needed when producing AOF syntax assembler. */
13993 struct pic_chain
* next
;
13994 const char * symname
;
13997 static struct pic_chain
* aof_pic_chain
= NULL
;
14000 aof_pic_entry (rtx x
)
14002 struct pic_chain
** chainp
;
14005 if (aof_pic_label
== NULL_RTX
)
14007 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14010 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14011 offset
+= 4, chainp
= &(*chainp
)->next
)
14012 if ((*chainp
)->symname
== XSTR (x
, 0))
14013 return plus_constant (aof_pic_label
, offset
);
14015 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14016 (*chainp
)->next
= NULL
;
14017 (*chainp
)->symname
= XSTR (x
, 0);
14018 return plus_constant (aof_pic_label
, offset
);
14022 aof_dump_pic_table (FILE *f
)
14024 struct pic_chain
* chain
;
14026 if (aof_pic_chain
== NULL
)
14029 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14030 PIC_OFFSET_TABLE_REGNUM
,
14031 PIC_OFFSET_TABLE_REGNUM
);
14032 fputs ("|x$adcons|\n", f
);
14034 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14036 fputs ("\tDCD\t", f
);
14037 assemble_name (f
, chain
->symname
);
14042 int arm_text_section_count
= 1;
14045 aof_text_section (void )
14047 static char buf
[100];
14048 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
14049 arm_text_section_count
++);
14051 strcat (buf
, ", PIC, REENTRANT");
14055 static int arm_data_section_count
= 1;
14058 aof_data_section (void)
14060 static char buf
[100];
14061 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
14065 /* The AOF assembler is religiously strict about declarations of
14066 imported and exported symbols, so that it is impossible to declare
14067 a function as imported near the beginning of the file, and then to
14068 export it later on. It is, however, possible to delay the decision
14069 until all the functions in the file have been compiled. To get
14070 around this, we maintain a list of the imports and exports, and
14071 delete from it any that are subsequently defined. At the end of
14072 compilation we spit the remainder of the list out before the END
14077 struct import
* next
;
14081 static struct import
* imports_list
= NULL
;
14084 aof_add_import (const char *name
)
14086 struct import
* new;
14088 for (new = imports_list
; new; new = new->next
)
14089 if (new->name
== name
)
14092 new = (struct import
*) xmalloc (sizeof (struct import
));
14093 new->next
= imports_list
;
14094 imports_list
= new;
14099 aof_delete_import (const char *name
)
14101 struct import
** old
;
14103 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14105 if ((*old
)->name
== name
)
14107 *old
= (*old
)->next
;
14113 int arm_main_function
= 0;
14116 aof_dump_imports (FILE *f
)
14118 /* The AOF assembler needs this to cause the startup code to be extracted
14119 from the library. Brining in __main causes the whole thing to work
14121 if (arm_main_function
)
14124 fputs ("\tIMPORT __main\n", f
);
14125 fputs ("\tDCD __main\n", f
);
14128 /* Now dump the remaining imports. */
14129 while (imports_list
)
14131 fprintf (f
, "\tIMPORT\t");
14132 assemble_name (f
, imports_list
->name
);
14134 imports_list
= imports_list
->next
;
14139 aof_globalize_label (FILE *stream
, const char *name
)
14141 default_globalize_label (stream
, name
);
14142 if (! strcmp (name
, "main"))
14143 arm_main_function
= 1;
14147 aof_file_start (void)
14149 fputs ("__r0\tRN\t0\n", asm_out_file
);
14150 fputs ("__a1\tRN\t0\n", asm_out_file
);
14151 fputs ("__a2\tRN\t1\n", asm_out_file
);
14152 fputs ("__a3\tRN\t2\n", asm_out_file
);
14153 fputs ("__a4\tRN\t3\n", asm_out_file
);
14154 fputs ("__v1\tRN\t4\n", asm_out_file
);
14155 fputs ("__v2\tRN\t5\n", asm_out_file
);
14156 fputs ("__v3\tRN\t6\n", asm_out_file
);
14157 fputs ("__v4\tRN\t7\n", asm_out_file
);
14158 fputs ("__v5\tRN\t8\n", asm_out_file
);
14159 fputs ("__v6\tRN\t9\n", asm_out_file
);
14160 fputs ("__sl\tRN\t10\n", asm_out_file
);
14161 fputs ("__fp\tRN\t11\n", asm_out_file
);
14162 fputs ("__ip\tRN\t12\n", asm_out_file
);
14163 fputs ("__sp\tRN\t13\n", asm_out_file
);
14164 fputs ("__lr\tRN\t14\n", asm_out_file
);
14165 fputs ("__pc\tRN\t15\n", asm_out_file
);
14166 fputs ("__f0\tFN\t0\n", asm_out_file
);
14167 fputs ("__f1\tFN\t1\n", asm_out_file
);
14168 fputs ("__f2\tFN\t2\n", asm_out_file
);
14169 fputs ("__f3\tFN\t3\n", asm_out_file
);
14170 fputs ("__f4\tFN\t4\n", asm_out_file
);
14171 fputs ("__f5\tFN\t5\n", asm_out_file
);
14172 fputs ("__f6\tFN\t6\n", asm_out_file
);
14173 fputs ("__f7\tFN\t7\n", asm_out_file
);
14178 aof_file_end (void)
14181 aof_dump_pic_table (asm_out_file
);
14182 aof_dump_imports (asm_out_file
);
14183 fputs ("\tEND\n", asm_out_file
);
14185 #endif /* AOF_ASSEMBLER */
14187 #ifdef OBJECT_FORMAT_ELF
14188 /* Switch to an arbitrary section NAME with attributes as specified
14189 by FLAGS. ALIGN specifies any known alignment requirements for
14190 the section; 0 if the default should be used.
14192 Differs from the default elf version only in the prefix character
14193 used before the section type. */
14196 arm_elf_asm_named_section (const char *name
, unsigned int flags
)
14198 char flagchars
[10], *f
= flagchars
;
14200 if (! named_section_first_declaration (name
))
14202 fprintf (asm_out_file
, "\t.section\t%s\n", name
);
14206 if (!(flags
& SECTION_DEBUG
))
14208 if (flags
& SECTION_WRITE
)
14210 if (flags
& SECTION_CODE
)
14212 if (flags
& SECTION_SMALL
)
14214 if (flags
& SECTION_MERGE
)
14216 if (flags
& SECTION_STRINGS
)
14218 if (flags
& SECTION_TLS
)
14222 fprintf (asm_out_file
, "\t.section\t%s,\"%s\"", name
, flagchars
);
14224 if (!(flags
& SECTION_NOTYPE
))
14228 if (flags
& SECTION_BSS
)
14233 fprintf (asm_out_file
, ",%%%s", type
);
14235 if (flags
& SECTION_ENTSIZE
)
14236 fprintf (asm_out_file
, ",%d", flags
& SECTION_ENTSIZE
);
14239 putc ('\n', asm_out_file
);
14244 /* Symbols in the text segment can be accessed without indirecting via the
14245 constant pool; it may take an extra binary operation, but this is still
14246 faster than indirecting via memory. Don't do this when not optimizing,
14247 since we won't be calculating al of the offsets necessary to do this
14251 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14253 /* This doesn't work with AOF syntax, since the string table may be in
14254 a different AREA. */
14255 #ifndef AOF_ASSEMBLER
14256 if (optimize
> 0 && TREE_CONSTANT (decl
))
14257 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14260 /* If we are referencing a function that is weak then encode a long call
14261 flag in the function name, otherwise if the function is static or
14262 or known to be defined in this file then encode a short call flag. */
14263 if (first
&& TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd')
14265 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14266 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14267 else if (! TREE_PUBLIC (decl
))
14268 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14271 #endif /* !ARM_PE */
14274 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14276 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14277 && !strcmp (prefix
, "L"))
14279 arm_ccfsm_state
= 0;
14280 arm_target_insn
= NULL
;
14282 default_internal_label (stream
, prefix
, labelno
);
14285 /* Output code to add DELTA to the first argument, and then jump
14286 to FUNCTION. Used for C++ multiple inheritance. */
14288 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14289 HOST_WIDE_INT delta
,
14290 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14293 static int thunk_label
= 0;
14295 int mi_delta
= delta
;
14296 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14298 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14301 mi_delta
= - mi_delta
;
14304 int labelno
= thunk_label
++;
14305 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14306 fputs ("\tldr\tr12, ", file
);
14307 assemble_name (file
, label
);
14308 fputc ('\n', file
);
14310 while (mi_delta
!= 0)
14312 if ((mi_delta
& (3 << shift
)) == 0)
14316 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14317 mi_op
, this_regno
, this_regno
,
14318 mi_delta
& (0xff << shift
));
14319 mi_delta
&= ~(0xff << shift
);
14325 fprintf (file
, "\tbx\tr12\n");
14326 ASM_OUTPUT_ALIGN (file
, 2);
14327 assemble_name (file
, label
);
14328 fputs (":\n", file
);
14329 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14333 fputs ("\tb\t", file
);
14334 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14335 if (NEED_PLT_RELOC
)
14336 fputs ("(PLT)", file
);
14337 fputc ('\n', file
);
14342 arm_emit_vector_const (FILE *file
, rtx x
)
14345 const char * pattern
;
14347 if (GET_CODE (x
) != CONST_VECTOR
)
14350 switch (GET_MODE (x
))
14352 case V2SImode
: pattern
= "%08x"; break;
14353 case V4HImode
: pattern
= "%04x"; break;
14354 case V8QImode
: pattern
= "%02x"; break;
14358 fprintf (file
, "0x");
14359 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14363 element
= CONST_VECTOR_ELT (x
, i
);
14364 fprintf (file
, pattern
, INTVAL (element
));
14371 arm_output_load_gr (rtx
*operands
)
14378 if (GET_CODE (operands
[1]) != MEM
14379 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14380 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14381 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14382 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14383 return "wldrw%?\t%0, %1";
14385 /* Fix up an out-of-range load of a GR register. */
14386 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14387 wcgr
= operands
[0];
14389 output_asm_insn ("ldr%?\t%0, %1", operands
);
14391 operands
[0] = wcgr
;
14393 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14394 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14400 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14401 int incoming ATTRIBUTE_UNUSED
)
14404 /* FIXME: The ARM backend has special code to handle structure
14405 returns, and will reserve its own hidden first argument. So
14406 if this macro is enabled a *second* hidden argument will be
14407 reserved, which will break binary compatibility with old
14408 toolchains and also thunk handling. One day this should be
14412 /* Register in which address to store a structure value
14413 is passed to a function. */
14414 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14418 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14420 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14421 named arg and all anonymous args onto the stack.
14422 XXX I know the prologue shouldn't be pushing registers, but it is faster
14426 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14427 enum machine_mode mode ATTRIBUTE_UNUSED
,
14428 tree type ATTRIBUTE_UNUSED
,
14430 int second_time ATTRIBUTE_UNUSED
)
14432 cfun
->machine
->uses_anonymous_args
= 1;
14433 if (cum
->nregs
< NUM_ARG_REGS
)
14434 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14437 /* Return nonzero if the CONSUMER instruction (a store) does not need
14438 PRODUCER's value to calculate the address. */
14441 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14443 rtx value
= PATTERN (producer
);
14444 rtx addr
= PATTERN (consumer
);
14446 if (GET_CODE (value
) == COND_EXEC
)
14447 value
= COND_EXEC_CODE (value
);
14448 if (GET_CODE (value
) == PARALLEL
)
14449 value
= XVECEXP (value
, 0, 0);
14450 value
= XEXP (value
, 0);
14451 if (GET_CODE (addr
) == COND_EXEC
)
14452 addr
= COND_EXEC_CODE (addr
);
14453 if (GET_CODE (addr
) == PARALLEL
)
14454 addr
= XVECEXP (addr
, 0, 0);
14455 addr
= XEXP (addr
, 0);
14457 return !reg_overlap_mentioned_p (value
, addr
);
14460 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14461 have an early register shift value or amount dependency on the
14462 result of PRODUCER. */
14465 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14467 rtx value
= PATTERN (producer
);
14468 rtx op
= PATTERN (consumer
);
14471 if (GET_CODE (value
) == COND_EXEC
)
14472 value
= COND_EXEC_CODE (value
);
14473 if (GET_CODE (value
) == PARALLEL
)
14474 value
= XVECEXP (value
, 0, 0);
14475 value
= XEXP (value
, 0);
14476 if (GET_CODE (op
) == COND_EXEC
)
14477 op
= COND_EXEC_CODE (op
);
14478 if (GET_CODE (op
) == PARALLEL
)
14479 op
= XVECEXP (op
, 0, 0);
14482 early_op
= XEXP (op
, 0);
14483 /* This is either an actual independent shift, or a shift applied to
14484 the first operand of another operation. We want the whole shift
14486 if (GET_CODE (early_op
) == REG
)
14489 return !reg_overlap_mentioned_p (value
, early_op
);
14492 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14493 have an early register shift value dependency on the result of
14497 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14499 rtx value
= PATTERN (producer
);
14500 rtx op
= PATTERN (consumer
);
14503 if (GET_CODE (value
) == COND_EXEC
)
14504 value
= COND_EXEC_CODE (value
);
14505 if (GET_CODE (value
) == PARALLEL
)
14506 value
= XVECEXP (value
, 0, 0);
14507 value
= XEXP (value
, 0);
14508 if (GET_CODE (op
) == COND_EXEC
)
14509 op
= COND_EXEC_CODE (op
);
14510 if (GET_CODE (op
) == PARALLEL
)
14511 op
= XVECEXP (op
, 0, 0);
14514 early_op
= XEXP (op
, 0);
14516 /* This is either an actual independent shift, or a shift applied to
14517 the first operand of another operation. We want the value being
14518 shifted, in either case. */
14519 if (GET_CODE (early_op
) != REG
)
14520 early_op
= XEXP (early_op
, 0);
14522 return !reg_overlap_mentioned_p (value
, early_op
);
14525 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14526 have an early register mult dependency on the result of
14530 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14532 rtx value
= PATTERN (producer
);
14533 rtx op
= PATTERN (consumer
);
14535 if (GET_CODE (value
) == COND_EXEC
)
14536 value
= COND_EXEC_CODE (value
);
14537 if (GET_CODE (value
) == PARALLEL
)
14538 value
= XVECEXP (value
, 0, 0);
14539 value
= XEXP (value
, 0);
14540 if (GET_CODE (op
) == COND_EXEC
)
14541 op
= COND_EXEC_CODE (op
);
14542 if (GET_CODE (op
) == PARALLEL
)
14543 op
= XVECEXP (op
, 0, 0);
14546 return (GET_CODE (op
) == PLUS
14547 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14551 /* We can't rely on the caller doing the proper promotion when
14552 using APCS or ATPCS. */
14555 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14557 return !TARGET_AAPCS_BASED
;
14561 /* AAPCS based ABIs use short enums by default. */
14564 arm_default_short_enums (void)
14566 return TARGET_AAPCS_BASED
;