1 ;; Scheduling description for IBM POWER6 processor.
2 ;; Copyright (C) 2006-2014 Free Software Foundation, Inc.
3 ;; Contributed by Peter Steinmetz (steinmtz@us.ibm.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
23 ;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine
24 ;; (2 engines per chip). The chip can issue up to 5 internal ops
27 (define_automaton "power6iu,power6lsu,power6fpu,power6bu")
29 (define_cpu_unit "iu1_power6,iu2_power6" "power6iu")
30 (define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu")
31 (define_cpu_unit "bpu_power6" "power6bu")
32 (define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu")
34 (define_reservation "LS2_power6"
35 "lsu1_power6+lsu2_power6")
37 (define_reservation "FPU_power6"
38 "fpu1_power6|fpu2_power6")
40 (define_reservation "BRU_power6"
43 (define_reservation "LSU_power6"
44 "lsu1_power6|lsu2_power6")
46 (define_reservation "LSF_power6"
47 "(lsu1_power6+fpu1_power6)\
48 |(lsu1_power6+fpu2_power6)\
49 |(lsu2_power6+fpu1_power6)\
50 |(lsu2_power6+fpu2_power6)")
52 (define_reservation "LX2_power6"
53 "(iu1_power6+iu2_power6+lsu1_power6)\
54 |(iu1_power6+iu2_power6+lsu2_power6)")
56 (define_reservation "FX2_power6"
57 "iu1_power6+iu2_power6")
59 (define_reservation "X2F_power6"
60 "(iu1_power6+iu2_power6+fpu1_power6)\
61 |(iu1_power6+iu2_power6+fpu2_power6)")
63 (define_reservation "BX2_power6"
64 "iu1_power6+iu2_power6+bpu_power6")
66 (define_reservation "LSX_power6"
67 "(iu1_power6+lsu1_power6)\
68 |(iu1_power6+lsu2_power6)\
69 |(iu2_power6+lsu1_power6)\
70 |(iu2_power6+lsu2_power6)")
72 (define_reservation "FXU_power6"
73 "iu1_power6|iu2_power6")
75 (define_reservation "XLF_power6"
76 "(iu1_power6+lsu1_power6+fpu1_power6)\
77 |(iu1_power6+lsu1_power6+fpu2_power6)\
78 |(iu1_power6+lsu2_power6+fpu1_power6)\
79 |(iu1_power6+lsu2_power6+fpu2_power6)\
80 |(iu2_power6+lsu1_power6+fpu1_power6)\
81 |(iu2_power6+lsu1_power6+fpu2_power6)\
82 |(iu2_power6+lsu2_power6+fpu1_power6)\
83 |(iu2_power6+lsu2_power6+fpu2_power6)")
85 (define_reservation "BRX_power6"
86 "(bpu_power6+iu1_power6)\
87 |(bpu_power6+iu2_power6)")
91 ; The default for a value written by a fixed point load
92 ; that is read/written by a subsequent fixed point op.
93 (define_insn_reservation "power6-load" 2 ; fx
94 (and (eq_attr "type" "load")
95 (eq_attr "sign_extend" "no")
96 (eq_attr "update" "no")
97 (eq_attr "cpu" "power6"))
100 ; define the bypass for the case where the value written
101 ; by a fixed point load is used as the source value on
103 (define_bypass 1 "power6-load,\
105 power6-load-update-indexed"
107 power6-store-update,\
108 power6-store-update-indexed,\
110 power6-fpstore-update"
111 "store_data_bypass_p")
113 (define_insn_reservation "power6-load-ext" 4 ; fx
114 (and (eq_attr "type" "load")
115 (eq_attr "sign_extend" "yes")
116 (eq_attr "update" "no")
117 (eq_attr "cpu" "power6"))
120 ; define the bypass for the case where the value written
121 ; by a fixed point load ext is used as the source value on
123 (define_bypass 1 "power6-load-ext,\
124 power6-load-ext-update,\
125 power6-load-ext-update-indexed"
127 power6-store-update,\
128 power6-store-update-indexed,\
130 power6-fpstore-update"
131 "store_data_bypass_p")
133 (define_insn_reservation "power6-load-update" 2 ; fx
134 (and (eq_attr "type" "load")
135 (eq_attr "sign_extend" "no")
136 (eq_attr "update" "yes")
137 (eq_attr "indexed" "no")
138 (eq_attr "cpu" "power6"))
141 (define_insn_reservation "power6-load-update-indexed" 2 ; fx
142 (and (eq_attr "type" "load")
143 (eq_attr "sign_extend" "no")
144 (eq_attr "update" "yes")
145 (eq_attr "indexed" "yes")
146 (eq_attr "cpu" "power6"))
149 (define_insn_reservation "power6-load-ext-update" 4 ; fx
150 (and (eq_attr "type" "load")
151 (eq_attr "sign_extend" "yes")
152 (eq_attr "update" "yes")
153 (eq_attr "indexed" "no")
154 (eq_attr "cpu" "power6"))
157 (define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
158 (and (eq_attr "type" "load")
159 (eq_attr "sign_extend" "yes")
160 (eq_attr "update" "yes")
161 (eq_attr "indexed" "yes")
162 (eq_attr "cpu" "power6"))
165 (define_insn_reservation "power6-fpload" 1
166 (and (eq_attr "type" "fpload")
167 (eq_attr "update" "no")
168 (eq_attr "cpu" "power6"))
171 (define_insn_reservation "power6-fpload-update" 1
172 (and (eq_attr "type" "fpload")
173 (eq_attr "update" "yes")
174 (eq_attr "cpu" "power6"))
177 (define_insn_reservation "power6-store" 14
178 (and (eq_attr "type" "store")
179 (eq_attr "update" "no")
180 (eq_attr "cpu" "power6"))
183 (define_insn_reservation "power6-store-update" 14
184 (and (eq_attr "type" "store")
185 (eq_attr "update" "yes")
186 (eq_attr "indexed" "no")
187 (eq_attr "cpu" "power6"))
190 (define_insn_reservation "power6-store-update-indexed" 14
191 (and (eq_attr "type" "store")
192 (eq_attr "update" "yes")
193 (eq_attr "indexed" "yes")
194 (eq_attr "cpu" "power6"))
197 (define_insn_reservation "power6-fpstore" 14
198 (and (eq_attr "type" "fpstore")
199 (eq_attr "update" "no")
200 (eq_attr "cpu" "power6"))
203 (define_insn_reservation "power6-fpstore-update" 14
204 (and (eq_attr "type" "fpstore")
205 (eq_attr "update" "yes")
206 (eq_attr "cpu" "power6"))
209 (define_insn_reservation "power6-larx" 3
210 (and (eq_attr "type" "load_l")
211 (eq_attr "cpu" "power6"))
214 (define_insn_reservation "power6-stcx" 10 ; best case
215 (and (eq_attr "type" "store_c")
216 (eq_attr "cpu" "power6"))
219 (define_insn_reservation "power6-sync" 11 ; N/A
220 (and (eq_attr "type" "sync")
221 (eq_attr "cpu" "power6"))
224 (define_insn_reservation "power6-integer" 1
225 (and (ior (eq_attr "type" "integer")
226 (and (eq_attr "type" "add")
227 (eq_attr "dot" "no")))
228 (eq_attr "cpu" "power6"))
231 (define_insn_reservation "power6-isel" 1
232 (and (eq_attr "type" "isel")
233 (eq_attr "cpu" "power6"))
236 (define_insn_reservation "power6-exts" 1
237 (and (eq_attr "type" "exts")
238 (eq_attr "cpu" "power6"))
241 (define_insn_reservation "power6-shift" 1
242 (and (eq_attr "type" "shift")
243 (eq_attr "var_shift" "no")
245 (eq_attr "cpu" "power6"))
248 (define_insn_reservation "power6-popcnt" 1
249 (and (eq_attr "type" "popcnt")
250 (eq_attr "cpu" "power6"))
253 (define_insn_reservation "power6-insert" 1
254 (and (eq_attr "type" "insert")
255 (eq_attr "size" "32")
256 (eq_attr "cpu" "power6"))
259 (define_insn_reservation "power6-insert-dword" 1
260 (and (eq_attr "type" "insert")
261 (eq_attr "size" "64")
262 (eq_attr "cpu" "power6"))
265 ; define the bypass for the case where the value written
266 ; by a fixed point op is used as the source value on a
268 (define_bypass 1 "power6-integer,\
274 power6-store-update,\
275 power6-store-update-indexed,\
277 power6-fpstore-update"
278 "store_data_bypass_p")
280 (define_insn_reservation "power6-cntlz" 2
281 (and (eq_attr "type" "cntlz")
282 (eq_attr "cpu" "power6"))
285 (define_bypass 1 "power6-cntlz"
287 power6-store-update,\
288 power6-store-update-indexed,\
290 power6-fpstore-update"
291 "store_data_bypass_p")
293 (define_insn_reservation "power6-var-rotate" 4
294 (and (eq_attr "type" "shift")
295 (eq_attr "var_shift" "yes")
297 (eq_attr "cpu" "power6"))
300 (define_insn_reservation "power6-trap" 1 ; N/A
301 (and (eq_attr "type" "trap")
302 (eq_attr "cpu" "power6"))
305 (define_insn_reservation "power6-two" 1
306 (and (eq_attr "type" "two")
307 (eq_attr "cpu" "power6"))
308 "(iu1_power6,iu1_power6)\
309 |(iu1_power6+iu2_power6,nothing)\
310 |(iu1_power6,iu2_power6)\
311 |(iu2_power6,iu1_power6)\
312 |(iu2_power6,iu2_power6)")
314 (define_insn_reservation "power6-three" 1
315 (and (eq_attr "type" "three")
316 (eq_attr "cpu" "power6"))
317 "(iu1_power6,iu1_power6,iu1_power6)\
318 |(iu1_power6,iu1_power6,iu2_power6)\
319 |(iu1_power6,iu2_power6,iu1_power6)\
320 |(iu1_power6,iu2_power6,iu2_power6)\
321 |(iu2_power6,iu1_power6,iu1_power6)\
322 |(iu2_power6,iu1_power6,iu2_power6)\
323 |(iu2_power6,iu2_power6,iu1_power6)\
324 |(iu2_power6,iu2_power6,iu2_power6)\
325 |(iu1_power6+iu2_power6,iu1_power6)\
326 |(iu1_power6+iu2_power6,iu2_power6)\
327 |(iu1_power6,iu1_power6+iu2_power6)\
328 |(iu2_power6,iu1_power6+iu2_power6)")
330 (define_insn_reservation "power6-cmp" 1
331 (and (eq_attr "type" "cmp")
332 (eq_attr "cpu" "power6"))
335 (define_insn_reservation "power6-compare" 1
336 (and (eq_attr "type" "compare")
337 (eq_attr "cpu" "power6"))
340 (define_insn_reservation "power6-fast-compare" 1
341 (and (ior (eq_attr "type" "fast_compare")
342 (and (eq_attr "type" "add")
343 (eq_attr "dot" "yes")))
344 (eq_attr "cpu" "power6"))
347 ; define the bypass for the case where the value written
348 ; by a fixed point rec form op is used as the source value
350 (define_bypass 1 "power6-compare,\
353 power6-store-update,\
354 power6-store-update-indexed,\
356 power6-fpstore-update"
357 "store_data_bypass_p")
359 (define_insn_reservation "power6-delayed-compare" 2 ; N/A
360 (and (eq_attr "type" "shift")
361 (eq_attr "var_shift" "no")
362 (eq_attr "dot" "yes")
363 (eq_attr "cpu" "power6"))
366 (define_insn_reservation "power6-var-delayed-compare" 4
367 (and (eq_attr "type" "shift")
368 (eq_attr "var_shift" "yes")
369 (eq_attr "dot" "yes")
370 (eq_attr "cpu" "power6"))
373 (define_insn_reservation "power6-lmul-cmp" 16
374 (and (eq_attr "type" "mul")
375 (eq_attr "dot" "yes")
376 (eq_attr "size" "64")
377 (eq_attr "cpu" "power6"))
378 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
379 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
381 (define_insn_reservation "power6-imul-cmp" 16
382 (and (eq_attr "type" "mul")
383 (eq_attr "dot" "yes")
384 (eq_attr "size" "32")
385 (eq_attr "cpu" "power6"))
386 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
387 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
389 (define_insn_reservation "power6-lmul" 16
390 (and (eq_attr "type" "mul")
392 (eq_attr "size" "64")
393 (eq_attr "cpu" "power6"))
394 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
395 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
397 (define_insn_reservation "power6-imul" 16
398 (and (eq_attr "type" "mul")
400 (eq_attr "size" "32")
401 (eq_attr "cpu" "power6"))
402 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
403 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
405 (define_insn_reservation "power6-imul3" 16
406 (and (eq_attr "type" "mul")
407 (eq_attr "size" "8,16")
408 (eq_attr "cpu" "power6"))
409 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
410 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
412 (define_bypass 9 "power6-imul,\
418 power6-store-update,\
419 power6-store-update-indexed,\
421 power6-fpstore-update"
422 "store_data_bypass_p")
424 (define_insn_reservation "power6-idiv" 44
425 (and (eq_attr "type" "div")
426 (eq_attr "size" "32")
427 (eq_attr "cpu" "power6"))
428 "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\
429 |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)");
431 ; The latency for this bypass is yet to be defined
432 ;(define_bypass ? "power6-idiv"
434 ; power6-store-update,\
435 ; power6-store-update-indexed,\
437 ; power6-fpstore-update"
438 ; "store_data_bypass_p")
440 (define_insn_reservation "power6-ldiv" 56
441 (and (eq_attr "type" "div")
442 (eq_attr "size" "64")
443 (eq_attr "cpu" "power6"))
444 "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\
445 |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)");
447 ; The latency for this bypass is yet to be defined
448 ;(define_bypass ? "power6-ldiv"
450 ; power6-store-update,\
451 ; power6-store-update-indexed,\
453 ; power6-fpstore-update"
454 ; "store_data_bypass_p")
456 (define_insn_reservation "power6-mtjmpr" 2
457 (and (eq_attr "type" "mtjmpr,mfjmpr")
458 (eq_attr "cpu" "power6"))
461 (define_bypass 5 "power6-mtjmpr" "power6-branch")
463 (define_insn_reservation "power6-branch" 2
464 (and (eq_attr "type" "jmpreg,branch")
465 (eq_attr "cpu" "power6"))
468 (define_bypass 5 "power6-branch" "power6-mtjmpr")
470 (define_insn_reservation "power6-crlogical" 3
471 (and (eq_attr "type" "cr_logical")
472 (eq_attr "cpu" "power6"))
475 (define_bypass 3 "power6-crlogical" "power6-branch")
477 (define_insn_reservation "power6-delayedcr" 3
478 (and (eq_attr "type" "delayed_cr")
479 (eq_attr "cpu" "power6"))
482 (define_insn_reservation "power6-mfcr" 6 ; N/A
483 (and (eq_attr "type" "mfcr")
484 (eq_attr "cpu" "power6"))
488 (define_insn_reservation "power6-mfcrf" 3 ; N/A
489 (and (eq_attr "type" "mfcrf")
490 (eq_attr "cpu" "power6"))
494 (define_insn_reservation "power6-mtcr" 4 ; N/A
495 (and (eq_attr "type" "mtcr")
496 (eq_attr "cpu" "power6"))
499 (define_bypass 9 "power6-mtcr" "power6-branch")
501 (define_insn_reservation "power6-fp" 6
502 (and (eq_attr "type" "fp,dmul")
503 (eq_attr "cpu" "power6"))
506 ; Any fp instruction that updates a CR has a latency
507 ; of 6 to a dependent branch
508 (define_bypass 6 "power6-fp" "power6-branch")
510 (define_bypass 1 "power6-fp"
511 "power6-fpstore,power6-fpstore-update"
512 "store_data_bypass_p")
514 (define_insn_reservation "power6-fpcompare" 8
515 (and (eq_attr "type" "fpcompare")
516 (eq_attr "cpu" "power6"))
519 (define_bypass 12 "power6-fpcompare"
520 "power6-branch,power6-crlogical")
522 (define_insn_reservation "power6-sdiv" 26
523 (and (eq_attr "type" "sdiv")
524 (eq_attr "cpu" "power6"))
527 (define_insn_reservation "power6-ddiv" 32
528 (and (eq_attr "type" "ddiv")
529 (eq_attr "cpu" "power6"))
532 (define_insn_reservation "power6-sqrt" 30
533 (and (eq_attr "type" "ssqrt")
534 (eq_attr "cpu" "power6"))
537 (define_insn_reservation "power6-dsqrt" 42
538 (and (eq_attr "type" "dsqrt")
539 (eq_attr "cpu" "power6"))
542 (define_insn_reservation "power6-isync" 2 ; N/A
543 (and (eq_attr "type" "isync")
544 (eq_attr "cpu" "power6"))
547 (define_insn_reservation "power6-vecload" 1
548 (and (eq_attr "type" "vecload")
549 (eq_attr "cpu" "power6"))
552 (define_insn_reservation "power6-vecstore" 1
553 (and (eq_attr "type" "vecstore")
554 (eq_attr "cpu" "power6"))
557 (define_insn_reservation "power6-vecsimple" 3
558 (and (eq_attr "type" "vecsimple")
559 (eq_attr "cpu" "power6"))
562 (define_bypass 6 "power6-vecsimple" "power6-veccomplex,\
565 (define_bypass 5 "power6-vecsimple" "power6-vecfloat")
567 (define_bypass 4 "power6-vecsimple" "power6-vecstore" )
569 (define_insn_reservation "power6-veccmp" 1
570 (and (eq_attr "type" "veccmp")
571 (eq_attr "cpu" "power6"))
574 (define_bypass 10 "power6-veccmp" "power6-branch")
576 (define_insn_reservation "power6-vecfloat" 7
577 (and (eq_attr "type" "vecfloat")
578 (eq_attr "cpu" "power6"))
581 (define_bypass 10 "power6-vecfloat" "power6-vecsimple")
583 (define_bypass 11 "power6-vecfloat" "power6-veccomplex,\
586 (define_bypass 9 "power6-vecfloat" "power6-vecstore" )
588 (define_insn_reservation "power6-veccomplex" 7
589 (and (eq_attr "type" "vecsimple")
590 (eq_attr "cpu" "power6"))
593 (define_bypass 10 "power6-veccomplex" "power6-vecsimple,\
596 (define_bypass 9 "power6-veccomplex" "power6-vecperm" )
598 (define_bypass 8 "power6-veccomplex" "power6-vecstore" )
600 (define_insn_reservation "power6-vecperm" 4
601 (and (eq_attr "type" "vecperm")
602 (eq_attr "cpu" "power6"))
605 (define_bypass 7 "power6-vecperm" "power6-vecsimple,\
608 (define_bypass 6 "power6-vecperm" "power6-veccomplex" )
610 (define_bypass 5 "power6-vecperm" "power6-vecstore" )
612 (define_insn_reservation "power6-mftgpr" 8
613 (and (eq_attr "type" "mftgpr")
614 (eq_attr "cpu" "power6"))
617 (define_insn_reservation "power6-mffgpr" 14
618 (and (eq_attr "type" "mffgpr")
619 (eq_attr "cpu" "power6"))
622 (define_bypass 4 "power6-mftgpr" "power6-imul,\