1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
5 Contributed by Michael Tiemann (tiemann@cygnus.com)
6 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "insn-codes.h"
37 #include "conditions.h"
39 #include "insn-attr.h"
50 #include "target-def.h"
51 #include "cfglayout.h"
52 #include "tree-gimple.h"
53 #include "langhooks.h"
57 struct processor_costs cypress_costs
= {
58 COSTS_N_INSNS (2), /* int load */
59 COSTS_N_INSNS (2), /* int signed load */
60 COSTS_N_INSNS (2), /* int zeroed load */
61 COSTS_N_INSNS (2), /* float load */
62 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
63 COSTS_N_INSNS (5), /* fadd, fsub */
64 COSTS_N_INSNS (1), /* fcmp */
65 COSTS_N_INSNS (1), /* fmov, fmovr */
66 COSTS_N_INSNS (7), /* fmul */
67 COSTS_N_INSNS (37), /* fdivs */
68 COSTS_N_INSNS (37), /* fdivd */
69 COSTS_N_INSNS (63), /* fsqrts */
70 COSTS_N_INSNS (63), /* fsqrtd */
71 COSTS_N_INSNS (1), /* imul */
72 COSTS_N_INSNS (1), /* imulX */
73 0, /* imul bit factor */
74 COSTS_N_INSNS (1), /* idiv */
75 COSTS_N_INSNS (1), /* idivX */
76 COSTS_N_INSNS (1), /* movcc/movr */
77 0, /* shift penalty */
81 struct processor_costs supersparc_costs
= {
82 COSTS_N_INSNS (1), /* int load */
83 COSTS_N_INSNS (1), /* int signed load */
84 COSTS_N_INSNS (1), /* int zeroed load */
85 COSTS_N_INSNS (0), /* float load */
86 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
87 COSTS_N_INSNS (3), /* fadd, fsub */
88 COSTS_N_INSNS (3), /* fcmp */
89 COSTS_N_INSNS (1), /* fmov, fmovr */
90 COSTS_N_INSNS (3), /* fmul */
91 COSTS_N_INSNS (6), /* fdivs */
92 COSTS_N_INSNS (9), /* fdivd */
93 COSTS_N_INSNS (12), /* fsqrts */
94 COSTS_N_INSNS (12), /* fsqrtd */
95 COSTS_N_INSNS (4), /* imul */
96 COSTS_N_INSNS (4), /* imulX */
97 0, /* imul bit factor */
98 COSTS_N_INSNS (4), /* idiv */
99 COSTS_N_INSNS (4), /* idivX */
100 COSTS_N_INSNS (1), /* movcc/movr */
101 1, /* shift penalty */
105 struct processor_costs hypersparc_costs
= {
106 COSTS_N_INSNS (1), /* int load */
107 COSTS_N_INSNS (1), /* int signed load */
108 COSTS_N_INSNS (1), /* int zeroed load */
109 COSTS_N_INSNS (1), /* float load */
110 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
111 COSTS_N_INSNS (1), /* fadd, fsub */
112 COSTS_N_INSNS (1), /* fcmp */
113 COSTS_N_INSNS (1), /* fmov, fmovr */
114 COSTS_N_INSNS (1), /* fmul */
115 COSTS_N_INSNS (8), /* fdivs */
116 COSTS_N_INSNS (12), /* fdivd */
117 COSTS_N_INSNS (17), /* fsqrts */
118 COSTS_N_INSNS (17), /* fsqrtd */
119 COSTS_N_INSNS (17), /* imul */
120 COSTS_N_INSNS (17), /* imulX */
121 0, /* imul bit factor */
122 COSTS_N_INSNS (17), /* idiv */
123 COSTS_N_INSNS (17), /* idivX */
124 COSTS_N_INSNS (1), /* movcc/movr */
125 0, /* shift penalty */
129 struct processor_costs sparclet_costs
= {
130 COSTS_N_INSNS (3), /* int load */
131 COSTS_N_INSNS (3), /* int signed load */
132 COSTS_N_INSNS (1), /* int zeroed load */
133 COSTS_N_INSNS (1), /* float load */
134 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
135 COSTS_N_INSNS (1), /* fadd, fsub */
136 COSTS_N_INSNS (1), /* fcmp */
137 COSTS_N_INSNS (1), /* fmov, fmovr */
138 COSTS_N_INSNS (1), /* fmul */
139 COSTS_N_INSNS (1), /* fdivs */
140 COSTS_N_INSNS (1), /* fdivd */
141 COSTS_N_INSNS (1), /* fsqrts */
142 COSTS_N_INSNS (1), /* fsqrtd */
143 COSTS_N_INSNS (5), /* imul */
144 COSTS_N_INSNS (5), /* imulX */
145 0, /* imul bit factor */
146 COSTS_N_INSNS (5), /* idiv */
147 COSTS_N_INSNS (5), /* idivX */
148 COSTS_N_INSNS (1), /* movcc/movr */
149 0, /* shift penalty */
153 struct processor_costs ultrasparc_costs
= {
154 COSTS_N_INSNS (2), /* int load */
155 COSTS_N_INSNS (3), /* int signed load */
156 COSTS_N_INSNS (2), /* int zeroed load */
157 COSTS_N_INSNS (2), /* float load */
158 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
159 COSTS_N_INSNS (4), /* fadd, fsub */
160 COSTS_N_INSNS (1), /* fcmp */
161 COSTS_N_INSNS (2), /* fmov, fmovr */
162 COSTS_N_INSNS (4), /* fmul */
163 COSTS_N_INSNS (13), /* fdivs */
164 COSTS_N_INSNS (23), /* fdivd */
165 COSTS_N_INSNS (13), /* fsqrts */
166 COSTS_N_INSNS (23), /* fsqrtd */
167 COSTS_N_INSNS (4), /* imul */
168 COSTS_N_INSNS (4), /* imulX */
169 2, /* imul bit factor */
170 COSTS_N_INSNS (37), /* idiv */
171 COSTS_N_INSNS (68), /* idivX */
172 COSTS_N_INSNS (2), /* movcc/movr */
173 2, /* shift penalty */
177 struct processor_costs ultrasparc3_costs
= {
178 COSTS_N_INSNS (2), /* int load */
179 COSTS_N_INSNS (3), /* int signed load */
180 COSTS_N_INSNS (3), /* int zeroed load */
181 COSTS_N_INSNS (2), /* float load */
182 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
183 COSTS_N_INSNS (4), /* fadd, fsub */
184 COSTS_N_INSNS (5), /* fcmp */
185 COSTS_N_INSNS (3), /* fmov, fmovr */
186 COSTS_N_INSNS (4), /* fmul */
187 COSTS_N_INSNS (17), /* fdivs */
188 COSTS_N_INSNS (20), /* fdivd */
189 COSTS_N_INSNS (20), /* fsqrts */
190 COSTS_N_INSNS (29), /* fsqrtd */
191 COSTS_N_INSNS (6), /* imul */
192 COSTS_N_INSNS (6), /* imulX */
193 0, /* imul bit factor */
194 COSTS_N_INSNS (40), /* idiv */
195 COSTS_N_INSNS (71), /* idivX */
196 COSTS_N_INSNS (2), /* movcc/movr */
197 0, /* shift penalty */
200 const struct processor_costs
*sparc_costs
= &cypress_costs
;
202 #ifdef HAVE_AS_RELAX_OPTION
203 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
204 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
205 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
206 somebody does not branch between the sethi and jmp. */
207 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
209 #define LEAF_SIBCALL_SLOT_RESERVED_P \
210 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
213 /* Global variables for machine-dependent things. */
215 /* Size of frame. Need to know this to emit return insns from leaf procedures.
216 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
217 reload pass. This is important as the value is later used for scheduling
218 (to see what can go in a delay slot).
219 APPARENT_FSIZE is the size of the stack less the register save area and less
220 the outgoing argument area. It is used when saving call preserved regs. */
221 static HOST_WIDE_INT apparent_fsize
;
222 static HOST_WIDE_INT actual_fsize
;
224 /* Number of live general or floating point registers needed to be
225 saved (as 4-byte quantities). */
226 static int num_gfregs
;
228 /* The alias set for prologue/epilogue register save/restore. */
229 static GTY(()) int sparc_sr_alias_set
;
231 /* The alias set for the structure return value. */
232 static GTY(()) int struct_value_alias_set
;
234 /* Save the operands last given to a compare for use when we
235 generate a scc or bcc insn. */
236 rtx sparc_compare_op0
, sparc_compare_op1
, sparc_compare_emitted
;
238 /* Vector to say how input registers are mapped to output registers.
239 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
240 eliminate it. You must use -fomit-frame-pointer to get that. */
241 char leaf_reg_remap
[] =
242 { 0, 1, 2, 3, 4, 5, 6, 7,
243 -1, -1, -1, -1, -1, -1, 14, -1,
244 -1, -1, -1, -1, -1, -1, -1, -1,
245 8, 9, 10, 11, 12, 13, -1, 15,
247 32, 33, 34, 35, 36, 37, 38, 39,
248 40, 41, 42, 43, 44, 45, 46, 47,
249 48, 49, 50, 51, 52, 53, 54, 55,
250 56, 57, 58, 59, 60, 61, 62, 63,
251 64, 65, 66, 67, 68, 69, 70, 71,
252 72, 73, 74, 75, 76, 77, 78, 79,
253 80, 81, 82, 83, 84, 85, 86, 87,
254 88, 89, 90, 91, 92, 93, 94, 95,
255 96, 97, 98, 99, 100};
257 /* Vector, indexed by hard register number, which contains 1
258 for a register that is allowable in a candidate for leaf
259 function treatment. */
260 char sparc_leaf_regs
[] =
261 { 1, 1, 1, 1, 1, 1, 1, 1,
262 0, 0, 0, 0, 0, 0, 1, 0,
263 0, 0, 0, 0, 0, 0, 0, 0,
264 1, 1, 1, 1, 1, 1, 0, 1,
265 1, 1, 1, 1, 1, 1, 1, 1,
266 1, 1, 1, 1, 1, 1, 1, 1,
267 1, 1, 1, 1, 1, 1, 1, 1,
268 1, 1, 1, 1, 1, 1, 1, 1,
269 1, 1, 1, 1, 1, 1, 1, 1,
270 1, 1, 1, 1, 1, 1, 1, 1,
271 1, 1, 1, 1, 1, 1, 1, 1,
272 1, 1, 1, 1, 1, 1, 1, 1,
275 struct machine_function
GTY(())
277 /* Some local-dynamic TLS symbol name. */
278 const char *some_ld_name
;
280 /* True if the current function is leaf and uses only leaf regs,
281 so that the SPARC leaf function optimization can be applied.
282 Private version of current_function_uses_only_leaf_regs, see
283 sparc_expand_prologue for the rationale. */
286 /* True if the data calculated by sparc_expand_prologue are valid. */
287 bool prologue_data_valid_p
;
290 #define sparc_leaf_function_p cfun->machine->leaf_function_p
291 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
293 /* Register we pretend to think the frame pointer is allocated to.
294 Normally, this is %fp, but if we are in a leaf procedure, this
295 is %sp+"something". We record "something" separately as it may
296 be too big for reg+constant addressing. */
297 static rtx frame_base_reg
;
298 static HOST_WIDE_INT frame_base_offset
;
300 /* 1 if the next opcode is to be specially indented. */
301 int sparc_indent_opcode
= 0;
303 static bool sparc_handle_option (size_t, const char *, int);
304 static void sparc_init_modes (void);
305 static void scan_record_type (tree
, int *, int *, int *);
306 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
307 tree
, int, int, int *, int *);
309 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
310 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
312 static void sparc_output_addr_vec (rtx
);
313 static void sparc_output_addr_diff_vec (rtx
);
314 static void sparc_output_deferred_case_vectors (void);
315 static rtx
sparc_builtin_saveregs (void);
316 static int epilogue_renumber (rtx
*, int);
317 static bool sparc_assemble_integer (rtx
, unsigned int, int);
318 static int set_extends (rtx
);
319 static void emit_pic_helper (void);
320 static void load_pic_register (bool);
321 static int save_or_restore_regs (int, int, rtx
, int, int);
322 static void emit_save_or_restore_regs (int);
323 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
324 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
325 #ifdef OBJECT_FORMAT_ELF
326 static void sparc_elf_asm_named_section (const char *, unsigned int, tree
);
329 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
330 static int sparc_issue_rate (void);
331 static void sparc_sched_init (FILE *, int, int);
332 static int sparc_use_sched_lookahead (void);
334 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
335 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
336 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
337 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
338 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
340 static bool sparc_function_ok_for_sibcall (tree
, tree
);
341 static void sparc_init_libfuncs (void);
342 static void sparc_init_builtins (void);
343 static void sparc_vis_init_builtins (void);
344 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
345 static tree
sparc_fold_builtin (tree
, tree
, bool);
346 static int sparc_vis_mul8x16 (int, int);
347 static tree
sparc_handle_vis_mul8x16 (int, tree
, tree
, tree
);
348 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
349 HOST_WIDE_INT
, tree
);
350 static bool sparc_can_output_mi_thunk (tree
, HOST_WIDE_INT
,
351 HOST_WIDE_INT
, tree
);
352 static struct machine_function
* sparc_init_machine_status (void);
353 static bool sparc_cannot_force_const_mem (rtx
);
354 static rtx
sparc_tls_get_addr (void);
355 static rtx
sparc_tls_got (void);
356 static const char *get_some_local_dynamic_name (void);
357 static int get_some_local_dynamic_name_1 (rtx
*, void *);
358 static bool sparc_rtx_costs (rtx
, int, int, int *);
359 static bool sparc_promote_prototypes (tree
);
360 static rtx
sparc_struct_value_rtx (tree
, int);
361 static bool sparc_return_in_memory (tree
, tree
);
362 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS
*);
363 static tree
sparc_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
364 static bool sparc_vector_mode_supported_p (enum machine_mode
);
365 static bool sparc_pass_by_reference (CUMULATIVE_ARGS
*,
366 enum machine_mode
, tree
, bool);
367 static int sparc_arg_partial_bytes (CUMULATIVE_ARGS
*,
368 enum machine_mode
, tree
, bool);
369 static void sparc_dwarf_handle_frame_unspec (const char *, rtx
, int);
370 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
371 static void sparc_file_end (void);
372 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
373 static const char *sparc_mangle_fundamental_type (tree
);
375 #ifdef SUBTARGET_ATTRIBUTE_TABLE
376 const struct attribute_spec sparc_attribute_table
[];
379 /* Option handling. */
382 enum cmodel sparc_cmodel
;
384 char sparc_hard_reg_printed
[8];
386 struct sparc_cpu_select sparc_select
[] =
388 /* switch name, tune arch */
389 { (char *)0, "default", 1, 1 },
390 { (char *)0, "-mcpu=", 1, 1 },
391 { (char *)0, "-mtune=", 1, 0 },
395 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
396 enum processor_type sparc_cpu
;
398 /* Whether\fan FPU option was specified. */
399 static bool fpu_option_set
= false;
401 /* Initialize the GCC target structure. */
403 /* The sparc default is to use .half rather than .short for aligned
404 HI objects. Use .word instead of .long on non-ELF systems. */
405 #undef TARGET_ASM_ALIGNED_HI_OP
406 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
407 #ifndef OBJECT_FORMAT_ELF
408 #undef TARGET_ASM_ALIGNED_SI_OP
409 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
412 #undef TARGET_ASM_UNALIGNED_HI_OP
413 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
414 #undef TARGET_ASM_UNALIGNED_SI_OP
415 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
416 #undef TARGET_ASM_UNALIGNED_DI_OP
417 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
419 /* The target hook has to handle DI-mode values. */
420 #undef TARGET_ASM_INTEGER
421 #define TARGET_ASM_INTEGER sparc_assemble_integer
423 #undef TARGET_ASM_FUNCTION_PROLOGUE
424 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
425 #undef TARGET_ASM_FUNCTION_EPILOGUE
426 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
428 #undef TARGET_SCHED_ADJUST_COST
429 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
430 #undef TARGET_SCHED_ISSUE_RATE
431 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
432 #undef TARGET_SCHED_INIT
433 #define TARGET_SCHED_INIT sparc_sched_init
434 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
435 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
437 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
438 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
440 #undef TARGET_INIT_LIBFUNCS
441 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
442 #undef TARGET_INIT_BUILTINS
443 #define TARGET_INIT_BUILTINS sparc_init_builtins
445 #undef TARGET_EXPAND_BUILTIN
446 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
447 #undef TARGET_FOLD_BUILTIN
448 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
451 #undef TARGET_HAVE_TLS
452 #define TARGET_HAVE_TLS true
455 #undef TARGET_CANNOT_FORCE_CONST_MEM
456 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
458 #undef TARGET_ASM_OUTPUT_MI_THUNK
459 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
460 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
461 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
463 #undef TARGET_RTX_COSTS
464 #define TARGET_RTX_COSTS sparc_rtx_costs
465 #undef TARGET_ADDRESS_COST
466 #define TARGET_ADDRESS_COST hook_int_rtx_0
468 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
469 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
470 test for this value. */
471 #undef TARGET_PROMOTE_FUNCTION_ARGS
472 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
474 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
475 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
476 test for this value. */
477 #undef TARGET_PROMOTE_FUNCTION_RETURN
478 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
480 #undef TARGET_PROMOTE_PROTOTYPES
481 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
483 #undef TARGET_STRUCT_VALUE_RTX
484 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
485 #undef TARGET_RETURN_IN_MEMORY
486 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
487 #undef TARGET_MUST_PASS_IN_STACK
488 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
489 #undef TARGET_PASS_BY_REFERENCE
490 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
491 #undef TARGET_ARG_PARTIAL_BYTES
492 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
494 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
495 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
496 #undef TARGET_STRICT_ARGUMENT_NAMING
497 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
499 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
500 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
502 #undef TARGET_VECTOR_MODE_SUPPORTED_P
503 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
505 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
506 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec
508 #ifdef SUBTARGET_INSERT_ATTRIBUTES
509 #undef TARGET_INSERT_ATTRIBUTES
510 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
513 #ifdef SUBTARGET_ATTRIBUTE_TABLE
514 #undef TARGET_ATTRIBUTE_TABLE
515 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
518 #undef TARGET_RELAXED_ORDERING
519 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
521 #undef TARGET_DEFAULT_TARGET_FLAGS
522 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
523 #undef TARGET_HANDLE_OPTION
524 #define TARGET_HANDLE_OPTION sparc_handle_option
527 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
528 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
531 #undef TARGET_ASM_FILE_END
532 #define TARGET_ASM_FILE_END sparc_file_end
534 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
535 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
536 #define TARGET_MANGLE_FUNDAMENTAL_TYPE sparc_mangle_fundamental_type
539 struct gcc_target targetm
= TARGET_INITIALIZER
;
541 /* Implement TARGET_HANDLE_OPTION. */
544 sparc_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
549 case OPT_mhard_float
:
550 case OPT_msoft_float
:
551 fpu_option_set
= true;
555 sparc_select
[1].string
= arg
;
559 sparc_select
[2].string
= arg
;
566 /* Validate and override various options, and do some machine dependent
570 sparc_override_options (void)
572 static struct code_model
{
573 const char *const name
;
575 } const cmodels
[] = {
577 { "medlow", CM_MEDLOW
},
578 { "medmid", CM_MEDMID
},
579 { "medany", CM_MEDANY
},
580 { "embmedany", CM_EMBMEDANY
},
583 const struct code_model
*cmodel
;
584 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
585 static struct cpu_default
{
587 const char *const name
;
588 } const cpu_default
[] = {
589 /* There must be one entry here for each TARGET_CPU value. */
590 { TARGET_CPU_sparc
, "cypress" },
591 { TARGET_CPU_sparclet
, "tsc701" },
592 { TARGET_CPU_sparclite
, "f930" },
593 { TARGET_CPU_v8
, "v8" },
594 { TARGET_CPU_hypersparc
, "hypersparc" },
595 { TARGET_CPU_sparclite86x
, "sparclite86x" },
596 { TARGET_CPU_supersparc
, "supersparc" },
597 { TARGET_CPU_v9
, "v9" },
598 { TARGET_CPU_ultrasparc
, "ultrasparc" },
599 { TARGET_CPU_ultrasparc3
, "ultrasparc3" },
602 const struct cpu_default
*def
;
603 /* Table of values for -m{cpu,tune}=. */
604 static struct cpu_table
{
605 const char *const name
;
606 const enum processor_type processor
;
609 } const cpu_table
[] = {
610 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
611 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
612 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
613 /* TI TMS390Z55 supersparc */
614 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
615 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
616 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
617 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
618 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
619 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
620 { "hypersparc", PROCESSOR_HYPERSPARC
, MASK_ISA
, MASK_V8
|MASK_FPU
},
621 { "sparclite86x", PROCESSOR_SPARCLITE86X
, MASK_ISA
|MASK_FPU
,
623 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
625 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
626 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
627 /* TI ultrasparc I, II, IIi */
628 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
629 /* Although insns using %y are deprecated, it is a clear win on current
631 |MASK_DEPRECATED_V8_INSNS
},
632 /* TI ultrasparc III */
633 /* ??? Check if %y issue still holds true in ultra3. */
634 { "ultrasparc3", PROCESSOR_ULTRASPARC3
, MASK_ISA
, MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
637 const struct cpu_table
*cpu
;
638 const struct sparc_cpu_select
*sel
;
641 #ifndef SPARC_BI_ARCH
642 /* Check for unsupported architecture size. */
643 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
644 error ("%s is not supported by this configuration",
645 DEFAULT_ARCH32_P
? "-m64" : "-m32");
648 /* We force all 64bit archs to use 128 bit long double */
649 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
651 error ("-mlong-double-64 not allowed with -m64");
652 target_flags
|= MASK_LONG_DOUBLE_128
;
655 /* Code model selection. */
656 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
660 sparc_cmodel
= CM_32
;
663 if (sparc_cmodel_string
!= NULL
)
667 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
668 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
670 if (cmodel
->name
== NULL
)
671 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
673 sparc_cmodel
= cmodel
->value
;
676 error ("-mcmodel= is not supported on 32 bit systems");
679 fpu
= TARGET_FPU
; /* save current -mfpu status */
681 /* Set the default CPU. */
682 for (def
= &cpu_default
[0]; def
->name
; ++def
)
683 if (def
->cpu
== TARGET_CPU_DEFAULT
)
685 gcc_assert (def
->name
);
686 sparc_select
[0].string
= def
->name
;
688 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
692 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
693 if (! strcmp (sel
->string
, cpu
->name
))
696 sparc_cpu
= cpu
->processor
;
700 target_flags
&= ~cpu
->disable
;
701 target_flags
|= cpu
->enable
;
707 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
711 /* If -mfpu or -mno-fpu was explicitly used, don't override with
712 the processor default. */
714 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
716 /* Don't allow -mvis if FPU is disabled. */
718 target_flags
&= ~MASK_VIS
;
720 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
722 -m64 also implies v9. */
723 if (TARGET_VIS
|| TARGET_ARCH64
)
725 target_flags
|= MASK_V9
;
726 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
729 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
730 if (TARGET_V9
&& TARGET_ARCH32
)
731 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
733 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
734 if (! TARGET_V9
|| TARGET_ARCH64
)
735 target_flags
&= ~MASK_V8PLUS
;
737 /* Don't use stack biasing in 32 bit mode. */
739 target_flags
&= ~MASK_STACK_BIAS
;
741 /* Supply a default value for align_functions. */
742 if (align_functions
== 0
743 && (sparc_cpu
== PROCESSOR_ULTRASPARC
744 || sparc_cpu
== PROCESSOR_ULTRASPARC3
))
745 align_functions
= 32;
747 /* Validate PCC_STRUCT_RETURN. */
748 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
749 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
751 /* Only use .uaxword when compiling for a 64-bit target. */
753 targetm
.asm_out
.unaligned_op
.di
= NULL
;
755 /* Do various machine dependent initializations. */
758 /* Acquire unique alias sets for our private stuff. */
759 sparc_sr_alias_set
= new_alias_set ();
760 struct_value_alias_set
= new_alias_set ();
762 /* Set up function hooks. */
763 init_machine_status
= sparc_init_machine_status
;
768 case PROCESSOR_CYPRESS
:
769 sparc_costs
= &cypress_costs
;
772 case PROCESSOR_SPARCLITE
:
773 case PROCESSOR_SUPERSPARC
:
774 sparc_costs
= &supersparc_costs
;
778 case PROCESSOR_HYPERSPARC
:
779 case PROCESSOR_SPARCLITE86X
:
780 sparc_costs
= &hypersparc_costs
;
782 case PROCESSOR_SPARCLET
:
783 case PROCESSOR_TSC701
:
784 sparc_costs
= &sparclet_costs
;
787 case PROCESSOR_ULTRASPARC
:
788 sparc_costs
= &ultrasparc_costs
;
790 case PROCESSOR_ULTRASPARC3
:
791 sparc_costs
= &ultrasparc3_costs
;
796 #ifdef SUBTARGET_ATTRIBUTE_TABLE
797 /* Table of valid machine attributes. */
798 const struct attribute_spec sparc_attribute_table
[] =
800 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
801 SUBTARGET_ATTRIBUTE_TABLE
,
802 { NULL
, 0, 0, false, false, false, NULL
}
806 /* Miscellaneous utilities. */
808 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
809 or branch on register contents instructions. */
812 v9_regcmp_p (enum rtx_code code
)
814 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
815 || code
== LE
|| code
== GT
);
818 /* Nonzero if OP is a floating point constant which can
819 be loaded into an integer register using a single
820 sethi instruction. */
825 if (GET_CODE (op
) == CONST_DOUBLE
)
830 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
831 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
832 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
838 /* Nonzero if OP is a floating point constant which can
839 be loaded into an integer register using a single
845 if (GET_CODE (op
) == CONST_DOUBLE
)
850 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
851 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
852 return SPARC_SIMM13_P (i
);
858 /* Nonzero if OP is a floating point constant which can
859 be loaded into an integer register using a high/losum
860 instruction sequence. */
863 fp_high_losum_p (rtx op
)
865 /* The constraints calling this should only be in
866 SFmode move insns, so any constant which cannot
867 be moved using a single insn will do. */
868 if (GET_CODE (op
) == CONST_DOUBLE
)
873 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
874 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
875 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
881 /* Expand a move instruction. Return true if all work is done. */
884 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
886 /* Handle sets of MEM first. */
887 if (GET_CODE (operands
[0]) == MEM
)
889 /* 0 is a register (or a pair of registers) on SPARC. */
890 if (register_or_zero_operand (operands
[1], mode
))
893 if (!reload_in_progress
)
895 operands
[0] = validize_mem (operands
[0]);
896 operands
[1] = force_reg (mode
, operands
[1]);
900 /* Fixup TLS cases. */
902 && CONSTANT_P (operands
[1])
903 && GET_CODE (operands
[1]) != HIGH
904 && sparc_tls_referenced_p (operands
[1]))
906 rtx sym
= operands
[1];
909 if (GET_CODE (sym
) == CONST
&& GET_CODE (XEXP (sym
, 0)) == PLUS
)
911 addend
= XEXP (XEXP (sym
, 0), 1);
912 sym
= XEXP (XEXP (sym
, 0), 0);
915 gcc_assert (SPARC_SYMBOL_REF_TLS_P (sym
));
917 sym
= legitimize_tls_address (sym
);
920 sym
= gen_rtx_PLUS (mode
, sym
, addend
);
921 sym
= force_operand (sym
, operands
[0]);
926 /* Fixup PIC cases. */
927 if (flag_pic
&& CONSTANT_P (operands
[1]))
929 if (pic_address_needs_scratch (operands
[1]))
930 operands
[1] = legitimize_pic_address (operands
[1], mode
, 0);
932 if (GET_CODE (operands
[1]) == LABEL_REF
&& mode
== SImode
)
934 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
938 if (GET_CODE (operands
[1]) == LABEL_REF
&& mode
== DImode
)
940 gcc_assert (TARGET_ARCH64
);
941 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
945 if (symbolic_operand (operands
[1], mode
))
947 operands
[1] = legitimize_pic_address (operands
[1],
949 (reload_in_progress
?
956 /* If we are trying to toss an integer constant into FP registers,
957 or loading a FP or vector constant, force it into memory. */
958 if (CONSTANT_P (operands
[1])
959 && REG_P (operands
[0])
960 && (SPARC_FP_REG_P (REGNO (operands
[0]))
961 || SCALAR_FLOAT_MODE_P (mode
)
962 || VECTOR_MODE_P (mode
)))
964 /* emit_group_store will send such bogosity to us when it is
965 not storing directly into memory. So fix this up to avoid
966 crashes in output_constant_pool. */
967 if (operands
[1] == const0_rtx
)
968 operands
[1] = CONST0_RTX (mode
);
970 /* We can clear FP registers if TARGET_VIS, and always other regs. */
971 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
972 && const_zero_operand (operands
[1], mode
))
975 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
976 /* We are able to build any SF constant in integer registers
977 with at most 2 instructions. */
979 /* And any DF constant in integer registers. */
981 && (reload_completed
|| reload_in_progress
))))
984 operands
[1] = force_const_mem (mode
, operands
[1]);
985 if (!reload_in_progress
)
986 operands
[1] = validize_mem (operands
[1]);
990 /* Accept non-constants and valid constants unmodified. */
991 if (!CONSTANT_P (operands
[1])
992 || GET_CODE (operands
[1]) == HIGH
993 || input_operand (operands
[1], mode
))
999 /* All QImode constants require only one insn, so proceed. */
1004 sparc_emit_set_const32 (operands
[0], operands
[1]);
1008 /* input_operand should have filtered out 32-bit mode. */
1009 sparc_emit_set_const64 (operands
[0], operands
[1]);
1019 /* Load OP1, a 32-bit constant, into OP0, a register.
1020 We know it can't be done in one insn when we get
1021 here, the move expander guarantees this. */
1024 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1026 enum machine_mode mode
= GET_MODE (op0
);
1029 if (reload_in_progress
|| reload_completed
)
1032 temp
= gen_reg_rtx (mode
);
1034 if (GET_CODE (op1
) == CONST_INT
)
1036 gcc_assert (!small_int_operand (op1
, mode
)
1037 && !const_high_operand (op1
, mode
));
1039 /* Emit them as real moves instead of a HIGH/LO_SUM,
1040 this way CSE can see everything and reuse intermediate
1041 values if it wants. */
1042 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1043 GEN_INT (INTVAL (op1
)
1044 & ~(HOST_WIDE_INT
)0x3ff)));
1046 emit_insn (gen_rtx_SET (VOIDmode
,
1048 gen_rtx_IOR (mode
, temp
,
1049 GEN_INT (INTVAL (op1
) & 0x3ff))));
1053 /* A symbol, emit in the traditional way. */
1054 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1055 gen_rtx_HIGH (mode
, op1
)));
1056 emit_insn (gen_rtx_SET (VOIDmode
,
1057 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1061 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1062 If TEMP is nonzero, we are forbidden to use any other scratch
1063 registers. Otherwise, we are allowed to generate them as needed.
1065 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1066 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1069 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1071 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1074 if (temp
&& GET_MODE (temp
) == TImode
)
1077 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1080 /* SPARC-V9 code-model support. */
1081 switch (sparc_cmodel
)
1084 /* The range spanned by all instructions in the object is less
1085 than 2^31 bytes (2GB) and the distance from any instruction
1086 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1087 than 2^31 bytes (2GB).
1089 The executable must be in the low 4TB of the virtual address
1092 sethi %hi(symbol), %temp1
1093 or %temp1, %lo(symbol), %reg */
1095 temp1
= temp
; /* op0 is allowed. */
1097 temp1
= gen_reg_rtx (DImode
);
1099 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1100 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1104 /* The range spanned by all instructions in the object is less
1105 than 2^31 bytes (2GB) and the distance from any instruction
1106 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1107 than 2^31 bytes (2GB).
1109 The executable must be in the low 16TB of the virtual address
1112 sethi %h44(symbol), %temp1
1113 or %temp1, %m44(symbol), %temp2
1114 sllx %temp2, 12, %temp3
1115 or %temp3, %l44(symbol), %reg */
1120 temp3
= temp
; /* op0 is allowed. */
1124 temp1
= gen_reg_rtx (DImode
);
1125 temp2
= gen_reg_rtx (DImode
);
1126 temp3
= gen_reg_rtx (DImode
);
1129 emit_insn (gen_seth44 (temp1
, op1
));
1130 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1131 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1132 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1133 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1137 /* The range spanned by all instructions in the object is less
1138 than 2^31 bytes (2GB) and the distance from any instruction
1139 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1140 than 2^31 bytes (2GB).
1142 The executable can be placed anywhere in the virtual address
1145 sethi %hh(symbol), %temp1
1146 sethi %lm(symbol), %temp2
1147 or %temp1, %hm(symbol), %temp3
1148 sllx %temp3, 32, %temp4
1149 or %temp4, %temp2, %temp5
1150 or %temp5, %lo(symbol), %reg */
1153 /* It is possible that one of the registers we got for operands[2]
1154 might coincide with that of operands[0] (which is why we made
1155 it TImode). Pick the other one to use as our scratch. */
1156 if (rtx_equal_p (temp
, op0
))
1158 gcc_assert (ti_temp
);
1159 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1162 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1169 temp1
= gen_reg_rtx (DImode
);
1170 temp2
= gen_reg_rtx (DImode
);
1171 temp3
= gen_reg_rtx (DImode
);
1172 temp4
= gen_reg_rtx (DImode
);
1173 temp5
= gen_reg_rtx (DImode
);
1176 emit_insn (gen_sethh (temp1
, op1
));
1177 emit_insn (gen_setlm (temp2
, op1
));
1178 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1179 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1180 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1181 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1182 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1183 emit_insn (gen_setlo (op0
, temp5
, op1
));
1187 /* Old old old backwards compatibility kruft here.
1188 Essentially it is MEDLOW with a fixed 64-bit
1189 virtual base added to all data segment addresses.
1190 Text-segment stuff is computed like MEDANY, we can't
1191 reuse the code above because the relocation knobs
1194 Data segment: sethi %hi(symbol), %temp1
1195 add %temp1, EMBMEDANY_BASE_REG, %temp2
1196 or %temp2, %lo(symbol), %reg */
1197 if (data_segment_operand (op1
, GET_MODE (op1
)))
1201 temp1
= temp
; /* op0 is allowed. */
1206 temp1
= gen_reg_rtx (DImode
);
1207 temp2
= gen_reg_rtx (DImode
);
1210 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1211 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1212 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1215 /* Text segment: sethi %uhi(symbol), %temp1
1216 sethi %hi(symbol), %temp2
1217 or %temp1, %ulo(symbol), %temp3
1218 sllx %temp3, 32, %temp4
1219 or %temp4, %temp2, %temp5
1220 or %temp5, %lo(symbol), %reg */
1225 /* It is possible that one of the registers we got for operands[2]
1226 might coincide with that of operands[0] (which is why we made
1227 it TImode). Pick the other one to use as our scratch. */
1228 if (rtx_equal_p (temp
, op0
))
1230 gcc_assert (ti_temp
);
1231 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1234 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1241 temp1
= gen_reg_rtx (DImode
);
1242 temp2
= gen_reg_rtx (DImode
);
1243 temp3
= gen_reg_rtx (DImode
);
1244 temp4
= gen_reg_rtx (DImode
);
1245 temp5
= gen_reg_rtx (DImode
);
1248 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1249 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1250 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1251 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1252 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1253 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1254 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1255 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1264 #if HOST_BITS_PER_WIDE_INT == 32
1266 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
1271 /* These avoid problems when cross compiling. If we do not
1272 go through all this hair then the optimizer will see
1273 invalid REG_EQUAL notes or in some cases none at all. */
1274 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1275 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1276 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1277 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1279 /* The optimizer is not to assume anything about exactly
1280 which bits are set for a HIGH, they are unspecified.
1281 Unfortunately this leads to many missed optimizations
1282 during CSE. We mask out the non-HIGH bits, and matches
1283 a plain movdi, to alleviate this problem. */
1285 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1287 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
1291 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1293 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
1297 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1299 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
1303 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1305 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
1308 /* Worker routines for 64-bit constant formation on arch64.
1309 One of the key things to be doing in these emissions is
1310 to create as many temp REGs as possible. This makes it
1311 possible for half-built constants to be used later when
1312 such values are similar to something required later on.
1313 Without doing this, the optimizer cannot see such
1316 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1317 unsigned HOST_WIDE_INT
, int);
1320 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1321 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1323 unsigned HOST_WIDE_INT high_bits
;
1326 high_bits
= (~low_bits
) & 0xffffffff;
1328 high_bits
= low_bits
;
1330 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1333 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1334 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1338 /* If we are XOR'ing with -1, then we should emit a one's complement
1339 instead. This way the combiner will notice logical operations
1340 such as ANDN later on and substitute. */
1341 if ((low_bits
& 0x3ff) == 0x3ff)
1343 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1344 gen_rtx_NOT (DImode
, temp
)));
1348 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1349 gen_safe_XOR64 (temp
,
1350 (-(HOST_WIDE_INT
)0x400
1351 | (low_bits
& 0x3ff)))));
1356 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1357 unsigned HOST_WIDE_INT
, int);
1360 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1361 unsigned HOST_WIDE_INT high_bits
,
1362 unsigned HOST_WIDE_INT low_immediate
,
1367 if ((high_bits
& 0xfffffc00) != 0)
1369 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1370 if ((high_bits
& ~0xfffffc00) != 0)
1371 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1372 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1378 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1382 /* Now shift it up into place. */
1383 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1384 gen_rtx_ASHIFT (DImode
, temp2
,
1385 GEN_INT (shift_count
))));
1387 /* If there is a low immediate part piece, finish up by
1388 putting that in as well. */
1389 if (low_immediate
!= 0)
1390 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1391 gen_safe_OR64 (op0
, low_immediate
)));
1394 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1395 unsigned HOST_WIDE_INT
);
1397 /* Full 64-bit constant decomposition. Even though this is the
1398 'worst' case, we still optimize a few things away. */
1400 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1401 unsigned HOST_WIDE_INT high_bits
,
1402 unsigned HOST_WIDE_INT low_bits
)
1406 if (reload_in_progress
|| reload_completed
)
1409 sub_temp
= gen_reg_rtx (DImode
);
1411 if ((high_bits
& 0xfffffc00) != 0)
1413 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1414 if ((high_bits
& ~0xfffffc00) != 0)
1415 emit_insn (gen_rtx_SET (VOIDmode
,
1417 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1423 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1427 if (!reload_in_progress
&& !reload_completed
)
1429 rtx temp2
= gen_reg_rtx (DImode
);
1430 rtx temp3
= gen_reg_rtx (DImode
);
1431 rtx temp4
= gen_reg_rtx (DImode
);
1433 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1434 gen_rtx_ASHIFT (DImode
, sub_temp
,
1437 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
1438 if ((low_bits
& ~0xfffffc00) != 0)
1440 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1441 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1442 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1443 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1447 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1448 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1453 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1454 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1455 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1458 /* We are in the middle of reload, so this is really
1459 painful. However we do still make an attempt to
1460 avoid emitting truly stupid code. */
1461 if (low1
!= const0_rtx
)
1463 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1464 gen_rtx_ASHIFT (DImode
, sub_temp
,
1465 GEN_INT (to_shift
))));
1466 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1467 gen_rtx_IOR (DImode
, op0
, low1
)));
1475 if (low2
!= const0_rtx
)
1477 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1478 gen_rtx_ASHIFT (DImode
, sub_temp
,
1479 GEN_INT (to_shift
))));
1480 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1481 gen_rtx_IOR (DImode
, op0
, low2
)));
1489 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1490 gen_rtx_ASHIFT (DImode
, sub_temp
,
1491 GEN_INT (to_shift
))));
1492 if (low3
!= const0_rtx
)
1493 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1494 gen_rtx_IOR (DImode
, op0
, low3
)));
1499 /* Analyze a 64-bit constant for certain properties. */
1500 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1501 unsigned HOST_WIDE_INT
,
1502 int *, int *, int *);
1505 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1506 unsigned HOST_WIDE_INT low_bits
,
1507 int *hbsp
, int *lbsp
, int *abbasp
)
1509 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1512 lowest_bit_set
= highest_bit_set
= -1;
1516 if ((lowest_bit_set
== -1)
1517 && ((low_bits
>> i
) & 1))
1519 if ((highest_bit_set
== -1)
1520 && ((high_bits
>> (32 - i
- 1)) & 1))
1521 highest_bit_set
= (64 - i
- 1);
1524 && ((highest_bit_set
== -1)
1525 || (lowest_bit_set
== -1)));
1531 if ((lowest_bit_set
== -1)
1532 && ((high_bits
>> i
) & 1))
1533 lowest_bit_set
= i
+ 32;
1534 if ((highest_bit_set
== -1)
1535 && ((low_bits
>> (32 - i
- 1)) & 1))
1536 highest_bit_set
= 32 - i
- 1;
1539 && ((highest_bit_set
== -1)
1540 || (lowest_bit_set
== -1)));
1542 /* If there are no bits set this should have gone out
1543 as one instruction! */
1544 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
1545 all_bits_between_are_set
= 1;
1546 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1550 if ((low_bits
& (1 << i
)) != 0)
1555 if ((high_bits
& (1 << (i
- 32))) != 0)
1558 all_bits_between_are_set
= 0;
1561 *hbsp
= highest_bit_set
;
1562 *lbsp
= lowest_bit_set
;
1563 *abbasp
= all_bits_between_are_set
;
1566 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
1569 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
1570 unsigned HOST_WIDE_INT low_bits
)
1572 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1575 || high_bits
== 0xffffffff)
1578 analyze_64bit_constant (high_bits
, low_bits
,
1579 &highest_bit_set
, &lowest_bit_set
,
1580 &all_bits_between_are_set
);
1582 if ((highest_bit_set
== 63
1583 || lowest_bit_set
== 0)
1584 && all_bits_between_are_set
!= 0)
1587 if ((highest_bit_set
- lowest_bit_set
) < 21)
1593 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
1594 unsigned HOST_WIDE_INT
,
1597 static unsigned HOST_WIDE_INT
1598 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
1599 unsigned HOST_WIDE_INT low_bits
,
1600 int lowest_bit_set
, int shift
)
1602 HOST_WIDE_INT hi
, lo
;
1604 if (lowest_bit_set
< 32)
1606 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1607 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1612 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1614 gcc_assert (! (hi
& lo
));
1618 /* Here we are sure to be arch64 and this is an integer constant
1619 being loaded into a register. Emit the most efficient
1620 insn sequence possible. Detection of all the 1-insn cases
1621 has been done already. */
1623 sparc_emit_set_const64 (rtx op0
, rtx op1
)
1625 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1626 int lowest_bit_set
, highest_bit_set
;
1627 int all_bits_between_are_set
;
1630 /* Sanity check that we know what we are working with. */
1631 gcc_assert (TARGET_ARCH64
1632 && (GET_CODE (op0
) == SUBREG
1633 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
1635 if (reload_in_progress
|| reload_completed
)
1638 if (GET_CODE (op1
) != CONST_INT
)
1640 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1645 temp
= gen_reg_rtx (DImode
);
1647 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1648 low_bits
= (INTVAL (op1
) & 0xffffffff);
1650 /* low_bits bits 0 --> 31
1651 high_bits bits 32 --> 63 */
1653 analyze_64bit_constant (high_bits
, low_bits
,
1654 &highest_bit_set
, &lowest_bit_set
,
1655 &all_bits_between_are_set
);
1657 /* First try for a 2-insn sequence. */
1659 /* These situations are preferred because the optimizer can
1660 * do more things with them:
1662 * sllx %reg, shift, %reg
1664 * srlx %reg, shift, %reg
1665 * 3) mov some_small_const, %reg
1666 * sllx %reg, shift, %reg
1668 if (((highest_bit_set
== 63
1669 || lowest_bit_set
== 0)
1670 && all_bits_between_are_set
!= 0)
1671 || ((highest_bit_set
- lowest_bit_set
) < 12))
1673 HOST_WIDE_INT the_const
= -1;
1674 int shift
= lowest_bit_set
;
1676 if ((highest_bit_set
!= 63
1677 && lowest_bit_set
!= 0)
1678 || all_bits_between_are_set
== 0)
1681 create_simple_focus_bits (high_bits
, low_bits
,
1684 else if (lowest_bit_set
== 0)
1685 shift
= -(63 - highest_bit_set
);
1687 gcc_assert (SPARC_SIMM13_P (the_const
));
1688 gcc_assert (shift
!= 0);
1690 emit_insn (gen_safe_SET64 (temp
, the_const
));
1692 emit_insn (gen_rtx_SET (VOIDmode
,
1694 gen_rtx_ASHIFT (DImode
,
1698 emit_insn (gen_rtx_SET (VOIDmode
,
1700 gen_rtx_LSHIFTRT (DImode
,
1702 GEN_INT (-shift
))));
1706 /* Now a range of 22 or less bits set somewhere.
1707 * 1) sethi %hi(focus_bits), %reg
1708 * sllx %reg, shift, %reg
1709 * 2) sethi %hi(focus_bits), %reg
1710 * srlx %reg, shift, %reg
1712 if ((highest_bit_set
- lowest_bit_set
) < 21)
1714 unsigned HOST_WIDE_INT focus_bits
=
1715 create_simple_focus_bits (high_bits
, low_bits
,
1716 lowest_bit_set
, 10);
1718 gcc_assert (SPARC_SETHI_P (focus_bits
));
1719 gcc_assert (lowest_bit_set
!= 10);
1721 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
1723 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1724 if (lowest_bit_set
< 10)
1725 emit_insn (gen_rtx_SET (VOIDmode
,
1727 gen_rtx_LSHIFTRT (DImode
, temp
,
1728 GEN_INT (10 - lowest_bit_set
))));
1729 else if (lowest_bit_set
> 10)
1730 emit_insn (gen_rtx_SET (VOIDmode
,
1732 gen_rtx_ASHIFT (DImode
, temp
,
1733 GEN_INT (lowest_bit_set
- 10))));
1737 /* 1) sethi %hi(low_bits), %reg
1738 * or %reg, %lo(low_bits), %reg
1739 * 2) sethi %hi(~low_bits), %reg
1740 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1743 || high_bits
== 0xffffffff)
1745 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
1746 (high_bits
== 0xffffffff));
1750 /* Now, try 3-insn sequences. */
1752 /* 1) sethi %hi(high_bits), %reg
1753 * or %reg, %lo(high_bits), %reg
1754 * sllx %reg, 32, %reg
1758 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
1762 /* We may be able to do something quick
1763 when the constant is negated, so try that. */
1764 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
1765 (~low_bits
) & 0xfffffc00))
1767 /* NOTE: The trailing bits get XOR'd so we need the
1768 non-negated bits, not the negated ones. */
1769 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
1771 if ((((~high_bits
) & 0xffffffff) == 0
1772 && ((~low_bits
) & 0x80000000) == 0)
1773 || (((~high_bits
) & 0xffffffff) == 0xffffffff
1774 && ((~low_bits
) & 0x80000000) != 0))
1776 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
1778 if ((SPARC_SETHI_P (fast_int
)
1779 && (~high_bits
& 0xffffffff) == 0)
1780 || SPARC_SIMM13_P (fast_int
))
1781 emit_insn (gen_safe_SET64 (temp
, fast_int
));
1783 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
1788 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
1789 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
1790 sparc_emit_set_const64 (temp
, negated_const
);
1793 /* If we are XOR'ing with -1, then we should emit a one's complement
1794 instead. This way the combiner will notice logical operations
1795 such as ANDN later on and substitute. */
1796 if (trailing_bits
== 0x3ff)
1798 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1799 gen_rtx_NOT (DImode
, temp
)));
1803 emit_insn (gen_rtx_SET (VOIDmode
,
1805 gen_safe_XOR64 (temp
,
1806 (-0x400 | trailing_bits
))));
1811 /* 1) sethi %hi(xxx), %reg
1812 * or %reg, %lo(xxx), %reg
1813 * sllx %reg, yyy, %reg
1815 * ??? This is just a generalized version of the low_bits==0
1816 * thing above, FIXME...
1818 if ((highest_bit_set
- lowest_bit_set
) < 32)
1820 unsigned HOST_WIDE_INT focus_bits
=
1821 create_simple_focus_bits (high_bits
, low_bits
,
1824 /* We can't get here in this state. */
1825 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
1827 /* So what we know is that the set bits straddle the
1828 middle of the 64-bit word. */
1829 sparc_emit_set_const64_quick2 (op0
, temp
,
1835 /* 1) sethi %hi(high_bits), %reg
1836 * or %reg, %lo(high_bits), %reg
1837 * sllx %reg, 32, %reg
1838 * or %reg, low_bits, %reg
1840 if (SPARC_SIMM13_P(low_bits
)
1841 && ((int)low_bits
> 0))
1843 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
1847 /* The easiest way when all else fails, is full decomposition. */
1849 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1850 high_bits
, low_bits
, ~high_bits
, ~low_bits
);
1852 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
1854 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
1856 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1857 return the mode to be used for the comparison. For floating-point,
1858 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
1859 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1860 processing is needed. */
1863 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
1865 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1891 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
1892 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
1894 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
1895 return CCX_NOOVmode
;
1901 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
1908 /* X and Y are two things to compare using CODE. Emit the compare insn and
1909 return the rtx for the cc reg in the proper mode. */
1912 gen_compare_reg (enum rtx_code code
)
1914 rtx x
= sparc_compare_op0
;
1915 rtx y
= sparc_compare_op1
;
1916 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
1919 if (sparc_compare_emitted
!= NULL_RTX
)
1921 cc_reg
= sparc_compare_emitted
;
1922 sparc_compare_emitted
= NULL_RTX
;
1926 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
1927 fcc regs (cse can't tell they're really call clobbered regs and will
1928 remove a duplicate comparison even if there is an intervening function
1929 call - it will then try to reload the cc reg via an int reg which is why
1930 we need the movcc patterns). It is possible to provide the movcc
1931 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
1932 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
1933 to tell cse that CCFPE mode registers (even pseudos) are call
1936 /* ??? This is an experiment. Rather than making changes to cse which may
1937 or may not be easy/clean, we do our own cse. This is possible because
1938 we will generate hard registers. Cse knows they're call clobbered (it
1939 doesn't know the same thing about pseudos). If we guess wrong, no big
1940 deal, but if we win, great! */
1942 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1943 #if 1 /* experiment */
1946 /* We cycle through the registers to ensure they're all exercised. */
1947 static int next_fcc_reg
= 0;
1948 /* Previous x,y for each fcc reg. */
1949 static rtx prev_args
[4][2];
1951 /* Scan prev_args for x,y. */
1952 for (reg
= 0; reg
< 4; reg
++)
1953 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
1958 prev_args
[reg
][0] = x
;
1959 prev_args
[reg
][1] = y
;
1960 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
1962 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
1965 cc_reg
= gen_reg_rtx (mode
);
1966 #endif /* ! experiment */
1967 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1968 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
1970 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
1972 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
1973 gen_rtx_COMPARE (mode
, x
, y
)));
1978 /* This function is used for v9 only.
1979 CODE is the code for an Scc's comparison.
1980 OPERANDS[0] is the target of the Scc insn.
1981 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
1982 been generated yet).
1984 This function is needed to turn
1987 (gt (reg:CCX 100 %icc)
1991 (gt:DI (reg:CCX 100 %icc)
1994 IE: The instruction recognizer needs to see the mode of the comparison to
1995 find the right instruction. We could use "gt:DI" right in the
1996 define_expand, but leaving it out allows us to handle DI, SI, etc.
1998 We refer to the global sparc compare operands sparc_compare_op0 and
1999 sparc_compare_op1. */
2002 gen_v9_scc (enum rtx_code compare_code
, register rtx
*operands
)
2005 && (GET_MODE (sparc_compare_op0
) == DImode
2006 || GET_MODE (operands
[0]) == DImode
))
2009 /* Try to use the movrCC insns. */
2011 && GET_MODE_CLASS (GET_MODE (sparc_compare_op0
)) == MODE_INT
2012 && sparc_compare_op1
== const0_rtx
2013 && v9_regcmp_p (compare_code
))
2015 rtx op0
= sparc_compare_op0
;
2018 /* Special case for op0 != 0. This can be done with one instruction if
2019 operands[0] == sparc_compare_op0. */
2021 if (compare_code
== NE
2022 && GET_MODE (operands
[0]) == DImode
2023 && rtx_equal_p (op0
, operands
[0]))
2025 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2026 gen_rtx_IF_THEN_ELSE (DImode
,
2027 gen_rtx_fmt_ee (compare_code
, DImode
,
2034 if (reg_overlap_mentioned_p (operands
[0], op0
))
2036 /* Handle the case where operands[0] == sparc_compare_op0.
2037 We "early clobber" the result. */
2038 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
2039 emit_move_insn (op0
, sparc_compare_op0
);
2042 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2043 if (GET_MODE (op0
) != DImode
)
2045 temp
= gen_reg_rtx (DImode
);
2046 convert_move (temp
, op0
, 0);
2050 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2051 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2052 gen_rtx_fmt_ee (compare_code
, DImode
,
2060 operands
[1] = gen_compare_reg (compare_code
);
2062 switch (GET_MODE (operands
[1]))
2072 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2073 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2074 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2075 gen_rtx_fmt_ee (compare_code
,
2076 GET_MODE (operands
[1]),
2077 operands
[1], const0_rtx
),
2078 const1_rtx
, operands
[0])));
2083 /* Emit a conditional jump insn for the v9 architecture using comparison code
2084 CODE and jump target LABEL.
2085 This function exists to take advantage of the v9 brxx insns. */
2088 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2090 gcc_assert (sparc_compare_emitted
== NULL_RTX
);
2091 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2093 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2094 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2096 gen_rtx_LABEL_REF (VOIDmode
, label
),
2100 /* Generate a DFmode part of a hard TFmode register.
2101 REG is the TFmode hard register, LOW is 1 for the
2102 low 64bit of the register and 0 otherwise.
2105 gen_df_reg (rtx reg
, int low
)
2107 int regno
= REGNO (reg
);
2109 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2110 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2111 return gen_rtx_REG (DFmode
, regno
);
2114 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2115 Unlike normal calls, TFmode operands are passed by reference. It is
2116 assumed that no more than 3 operands are required. */
2119 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2121 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2124 /* We only expect to be called for conversions, unary, and binary ops. */
2125 gcc_assert (nargs
== 2 || nargs
== 3);
2127 for (i
= 0; i
< nargs
; ++i
)
2129 rtx this_arg
= operands
[i
];
2132 /* TFmode arguments and return values are passed by reference. */
2133 if (GET_MODE (this_arg
) == TFmode
)
2135 int force_stack_temp
;
2137 force_stack_temp
= 0;
2138 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2139 force_stack_temp
= 1;
2141 if (GET_CODE (this_arg
) == MEM
2142 && ! force_stack_temp
)
2143 this_arg
= XEXP (this_arg
, 0);
2144 else if (CONSTANT_P (this_arg
)
2145 && ! force_stack_temp
)
2147 this_slot
= force_const_mem (TFmode
, this_arg
);
2148 this_arg
= XEXP (this_slot
, 0);
2152 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2154 /* Operand 0 is the return value. We'll copy it out later. */
2156 emit_move_insn (this_slot
, this_arg
);
2158 ret_slot
= this_slot
;
2160 this_arg
= XEXP (this_slot
, 0);
2167 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2169 if (GET_MODE (operands
[0]) == TFmode
)
2172 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2173 arg
[0], GET_MODE (arg
[0]),
2174 arg
[1], GET_MODE (arg
[1]));
2176 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2177 arg
[0], GET_MODE (arg
[0]),
2178 arg
[1], GET_MODE (arg
[1]),
2179 arg
[2], GET_MODE (arg
[2]));
2182 emit_move_insn (operands
[0], ret_slot
);
2188 gcc_assert (nargs
== 2);
2190 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2191 GET_MODE (operands
[0]), 1,
2192 arg
[1], GET_MODE (arg
[1]));
2194 if (ret
!= operands
[0])
2195 emit_move_insn (operands
[0], ret
);
2199 /* Expand soft-float TFmode calls to sparc abi routines. */
2202 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2224 emit_soft_tfmode_libcall (func
, 3, operands
);
2228 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2232 gcc_assert (code
== SQRT
);
2235 emit_soft_tfmode_libcall (func
, 2, operands
);
2239 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2246 switch (GET_MODE (operands
[1]))
2259 case FLOAT_TRUNCATE
:
2260 switch (GET_MODE (operands
[0]))
2274 switch (GET_MODE (operands
[1]))
2287 case UNSIGNED_FLOAT
:
2288 switch (GET_MODE (operands
[1]))
2302 switch (GET_MODE (operands
[0]))
2316 switch (GET_MODE (operands
[0]))
2333 emit_soft_tfmode_libcall (func
, 2, operands
);
2336 /* Expand a hard-float tfmode operation. All arguments must be in
2340 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2344 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
2346 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2347 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2351 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2352 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2353 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2354 operands
[1], operands
[2]);
2357 if (register_operand (operands
[0], VOIDmode
))
2360 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2362 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2364 if (dest
!= operands
[0])
2365 emit_move_insn (operands
[0], dest
);
2369 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2371 if (TARGET_HARD_QUAD
)
2372 emit_hard_tfmode_operation (code
, operands
);
2374 emit_soft_tfmode_binop (code
, operands
);
2378 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2380 if (TARGET_HARD_QUAD
)
2381 emit_hard_tfmode_operation (code
, operands
);
2383 emit_soft_tfmode_unop (code
, operands
);
2387 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2389 if (TARGET_HARD_QUAD
)
2390 emit_hard_tfmode_operation (code
, operands
);
2392 emit_soft_tfmode_cvt (code
, operands
);
2395 /* Return nonzero if a branch/jump/call instruction will be emitting
2396 nop into its delay slot. */
2399 empty_delay_slot (rtx insn
)
2403 /* If no previous instruction (should not happen), return true. */
2404 if (PREV_INSN (insn
) == NULL
)
2407 seq
= NEXT_INSN (PREV_INSN (insn
));
2408 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2414 /* Return nonzero if TRIAL can go into the call delay slot. */
2417 tls_call_delay (rtx trial
)
2422 call __tls_get_addr, %tgd_call (foo)
2423 add %l7, %o0, %o0, %tgd_add (foo)
2424 while Sun as/ld does not. */
2425 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
2428 pat
= PATTERN (trial
);
2430 /* We must reject tgd_add{32|64}, i.e.
2431 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2432 and tldm_add{32|64}, i.e.
2433 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2435 if (GET_CODE (pat
) == SET
2436 && GET_CODE (SET_SRC (pat
)) == PLUS
)
2438 rtx unspec
= XEXP (SET_SRC (pat
), 1);
2440 if (GET_CODE (unspec
) == UNSPEC
2441 && (XINT (unspec
, 1) == UNSPEC_TLSGD
2442 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
2449 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2450 instruction. RETURN_P is true if the v9 variant 'return' is to be
2451 considered in the test too.
2453 TRIAL must be a SET whose destination is a REG appropriate for the
2454 'restore' instruction or, if RETURN_P is true, for the 'return'
2458 eligible_for_restore_insn (rtx trial
, bool return_p
)
2460 rtx pat
= PATTERN (trial
);
2461 rtx src
= SET_SRC (pat
);
2463 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2464 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2465 && arith_operand (src
, GET_MODE (src
)))
2468 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2470 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2473 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2474 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2475 && arith_double_operand (src
, GET_MODE (src
)))
2476 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2478 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2479 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
2482 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2483 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
2486 /* If we have the 'return' instruction, anything that does not use
2487 local or output registers and can go into a delay slot wins. */
2488 else if (return_p
&& TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2489 && (get_attr_in_uncond_branch_delay (trial
)
2490 == IN_UNCOND_BRANCH_DELAY_TRUE
))
2493 /* The 'restore src1,src2,dest' pattern for SImode. */
2494 else if (GET_CODE (src
) == PLUS
2495 && register_operand (XEXP (src
, 0), SImode
)
2496 && arith_operand (XEXP (src
, 1), SImode
))
2499 /* The 'restore src1,src2,dest' pattern for DImode. */
2500 else if (GET_CODE (src
) == PLUS
2501 && register_operand (XEXP (src
, 0), DImode
)
2502 && arith_double_operand (XEXP (src
, 1), DImode
))
2505 /* The 'restore src1,%lo(src2),dest' pattern. */
2506 else if (GET_CODE (src
) == LO_SUM
2507 && ! TARGET_CM_MEDMID
2508 && ((register_operand (XEXP (src
, 0), SImode
)
2509 && immediate_operand (XEXP (src
, 1), SImode
))
2511 && register_operand (XEXP (src
, 0), DImode
)
2512 && immediate_operand (XEXP (src
, 1), DImode
))))
2515 /* The 'restore src,src,dest' pattern. */
2516 else if (GET_CODE (src
) == ASHIFT
2517 && (register_operand (XEXP (src
, 0), SImode
)
2518 || register_operand (XEXP (src
, 0), DImode
))
2519 && XEXP (src
, 1) == const1_rtx
)
2525 /* Return nonzero if TRIAL can go into the function return's
2529 eligible_for_return_delay (rtx trial
)
2533 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2536 if (get_attr_length (trial
) != 1)
2539 /* If there are any call-saved registers, we should scan TRIAL if it
2540 does not reference them. For now just make it easy. */
2544 /* If the function uses __builtin_eh_return, the eh_return machinery
2545 occupies the delay slot. */
2546 if (current_function_calls_eh_return
)
2549 /* In the case of a true leaf function, anything can go into the slot. */
2550 if (sparc_leaf_function_p
)
2551 return get_attr_in_uncond_branch_delay (trial
)
2552 == IN_UNCOND_BRANCH_DELAY_TRUE
;
2554 pat
= PATTERN (trial
);
2556 /* Otherwise, only operations which can be done in tandem with
2557 a `restore' or `return' insn can go into the delay slot. */
2558 if (GET_CODE (SET_DEST (pat
)) != REG
2559 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24))
2562 /* If this instruction sets up floating point register and we have a return
2563 instruction, it can probably go in. But restore will not work
2565 if (REGNO (SET_DEST (pat
)) >= 32)
2567 && ! epilogue_renumber (&pat
, 1)
2568 && (get_attr_in_uncond_branch_delay (trial
)
2569 == IN_UNCOND_BRANCH_DELAY_TRUE
));
2571 return eligible_for_restore_insn (trial
, true);
2574 /* Return nonzero if TRIAL can go into the sibling call's
2578 eligible_for_sibcall_delay (rtx trial
)
2582 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2585 if (get_attr_length (trial
) != 1)
2588 pat
= PATTERN (trial
);
2590 if (sparc_leaf_function_p
)
2592 /* If the tail call is done using the call instruction,
2593 we have to restore %o7 in the delay slot. */
2594 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
2597 /* %g1 is used to build the function address */
2598 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2604 /* Otherwise, only operations which can be done in tandem with
2605 a `restore' insn can go into the delay slot. */
2606 if (GET_CODE (SET_DEST (pat
)) != REG
2607 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
2608 || REGNO (SET_DEST (pat
)) >= 32)
2611 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2613 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2616 return eligible_for_restore_insn (trial
, false);
2620 short_branch (int uid1
, int uid2
)
2622 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
2624 /* Leave a few words of "slop". */
2625 if (delta
>= -1023 && delta
<= 1022)
2631 /* Return nonzero if REG is not used after INSN.
2632 We assume REG is a reload reg, and therefore does
2633 not live past labels or calls or jumps. */
2635 reg_unused_after (rtx reg
, rtx insn
)
2637 enum rtx_code code
, prev_code
= UNKNOWN
;
2639 while ((insn
= NEXT_INSN (insn
)))
2641 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
2644 code
= GET_CODE (insn
);
2645 if (GET_CODE (insn
) == CODE_LABEL
)
2650 rtx set
= single_set (insn
);
2651 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
2654 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2656 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
2664 /* Determine if it's legal to put X into the constant pool. This
2665 is not possible if X contains the address of a symbol that is
2666 not constant (TLS) or not known at final link time (PIC). */
2669 sparc_cannot_force_const_mem (rtx x
)
2671 switch (GET_CODE (x
))
2676 /* Accept all non-symbolic constants. */
2680 /* Labels are OK iff we are non-PIC. */
2681 return flag_pic
!= 0;
2684 /* 'Naked' TLS symbol references are never OK,
2685 non-TLS symbols are OK iff we are non-PIC. */
2686 if (SYMBOL_REF_TLS_MODEL (x
))
2689 return flag_pic
!= 0;
2692 return sparc_cannot_force_const_mem (XEXP (x
, 0));
2695 return sparc_cannot_force_const_mem (XEXP (x
, 0))
2696 || sparc_cannot_force_const_mem (XEXP (x
, 1));
2705 static GTY(()) char pic_helper_symbol_name
[256];
2706 static GTY(()) rtx pic_helper_symbol
;
2707 static GTY(()) bool pic_helper_emitted_p
= false;
2708 static GTY(()) rtx global_offset_table
;
2710 /* Ensure that we are not using patterns that are not OK with PIC. */
2718 gcc_assert (GET_CODE (recog_data
.operand
[i
]) != SYMBOL_REF
2719 && (GET_CODE (recog_data
.operand
[i
]) != CONST
2720 || (GET_CODE (XEXP (recog_data
.operand
[i
], 0)) == MINUS
2721 && (XEXP (XEXP (recog_data
.operand
[i
], 0), 0)
2722 == global_offset_table
)
2723 && (GET_CODE (XEXP (XEXP (recog_data
.operand
[i
], 0), 1))
2731 /* Return true if X is an address which needs a temporary register when
2732 reloaded while generating PIC code. */
2735 pic_address_needs_scratch (rtx x
)
2737 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2738 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
2739 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2740 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2741 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
2747 /* Determine if a given RTX is a valid constant. We already know this
2748 satisfies CONSTANT_P. */
2751 legitimate_constant_p (rtx x
)
2755 switch (GET_CODE (x
))
2758 /* TLS symbols are not constant. */
2759 if (SYMBOL_REF_TLS_MODEL (x
))
2764 inner
= XEXP (x
, 0);
2766 /* Offsets of TLS symbols are never valid.
2767 Discourage CSE from creating them. */
2768 if (GET_CODE (inner
) == PLUS
2769 && SPARC_SYMBOL_REF_TLS_P (XEXP (inner
, 0)))
2774 if (GET_MODE (x
) == VOIDmode
)
2777 /* Floating point constants are generally not ok.
2778 The only exception is 0.0 in VIS. */
2780 && SCALAR_FLOAT_MODE_P (GET_MODE (x
))
2781 && const_zero_operand (x
, GET_MODE (x
)))
2787 /* Vector constants are generally not ok.
2788 The only exception is 0 in VIS. */
2790 && const_zero_operand (x
, GET_MODE (x
)))
2802 /* Determine if a given RTX is a valid constant address. */
2805 constant_address_p (rtx x
)
2807 switch (GET_CODE (x
))
2815 if (flag_pic
&& pic_address_needs_scratch (x
))
2817 return legitimate_constant_p (x
);
2820 return !flag_pic
&& legitimate_constant_p (x
);
2827 /* Nonzero if the constant value X is a legitimate general operand
2828 when generating PIC code. It is given that flag_pic is on and
2829 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2832 legitimate_pic_operand_p (rtx x
)
2834 if (pic_address_needs_scratch (x
))
2836 if (SPARC_SYMBOL_REF_TLS_P (x
)
2837 || (GET_CODE (x
) == CONST
2838 && GET_CODE (XEXP (x
, 0)) == PLUS
2839 && SPARC_SYMBOL_REF_TLS_P (XEXP (XEXP (x
, 0), 0))))
2844 /* Return nonzero if ADDR is a valid memory address.
2845 STRICT specifies whether strict register checking applies. */
2848 legitimate_address_p (enum machine_mode mode
, rtx addr
, int strict
)
2850 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
2852 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
2854 else if (GET_CODE (addr
) == PLUS
)
2856 rs1
= XEXP (addr
, 0);
2857 rs2
= XEXP (addr
, 1);
2859 /* Canonicalize. REG comes first, if there are no regs,
2860 LO_SUM comes first. */
2862 && GET_CODE (rs1
) != SUBREG
2864 || GET_CODE (rs2
) == SUBREG
2865 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
2867 rs1
= XEXP (addr
, 1);
2868 rs2
= XEXP (addr
, 0);
2872 && rs1
== pic_offset_table_rtx
2874 && GET_CODE (rs2
) != SUBREG
2875 && GET_CODE (rs2
) != LO_SUM
2876 && GET_CODE (rs2
) != MEM
2877 && ! SPARC_SYMBOL_REF_TLS_P (rs2
)
2878 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
2879 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
2881 || GET_CODE (rs1
) == SUBREG
)
2882 && RTX_OK_FOR_OFFSET_P (rs2
)))
2887 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
2888 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
2890 /* We prohibit REG + REG for TFmode when there are no quad move insns
2891 and we consequently need to split. We do this because REG+REG
2892 is not an offsettable address. If we get the situation in reload
2893 where source and destination of a movtf pattern are both MEMs with
2894 REG+REG address, then only one of them gets converted to an
2895 offsettable address. */
2897 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
2900 /* We prohibit REG + REG on ARCH32 if not optimizing for
2901 DFmode/DImode because then mem_min_alignment is likely to be zero
2902 after reload and the forced split would lack a matching splitter
2904 if (TARGET_ARCH32
&& !optimize
2905 && (mode
== DFmode
|| mode
== DImode
))
2908 else if (USE_AS_OFFSETABLE_LO10
2909 && GET_CODE (rs1
) == LO_SUM
2911 && ! TARGET_CM_MEDMID
2912 && RTX_OK_FOR_OLO10_P (rs2
))
2915 imm1
= XEXP (rs1
, 1);
2916 rs1
= XEXP (rs1
, 0);
2917 if (! CONSTANT_P (imm1
) || SPARC_SYMBOL_REF_TLS_P (rs1
))
2921 else if (GET_CODE (addr
) == LO_SUM
)
2923 rs1
= XEXP (addr
, 0);
2924 imm1
= XEXP (addr
, 1);
2926 if (! CONSTANT_P (imm1
) || SPARC_SYMBOL_REF_TLS_P (rs1
))
2929 /* We can't allow TFmode in 32-bit mode, because an offset greater
2930 than the alignment (8) may cause the LO_SUM to overflow. */
2931 if (mode
== TFmode
&& TARGET_ARCH32
)
2934 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
2939 if (GET_CODE (rs1
) == SUBREG
)
2940 rs1
= SUBREG_REG (rs1
);
2946 if (GET_CODE (rs2
) == SUBREG
)
2947 rs2
= SUBREG_REG (rs2
);
2954 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
2955 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
2960 if ((REGNO (rs1
) >= 32
2961 && REGNO (rs1
) != FRAME_POINTER_REGNUM
2962 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
2964 && (REGNO (rs2
) >= 32
2965 && REGNO (rs2
) != FRAME_POINTER_REGNUM
2966 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
2972 /* Construct the SYMBOL_REF for the tls_get_offset function. */
2974 static GTY(()) rtx sparc_tls_symbol
;
2977 sparc_tls_get_addr (void)
2979 if (!sparc_tls_symbol
)
2980 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2982 return sparc_tls_symbol
;
2986 sparc_tls_got (void)
2991 current_function_uses_pic_offset_table
= 1;
2992 return pic_offset_table_rtx
;
2995 if (!global_offset_table
)
2996 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2997 temp
= gen_reg_rtx (Pmode
);
2998 emit_move_insn (temp
, global_offset_table
);
3002 /* Return 1 if *X is a thread-local symbol. */
3005 sparc_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
3007 return SPARC_SYMBOL_REF_TLS_P (*x
);
3010 /* Return 1 if X contains a thread-local symbol. */
3013 sparc_tls_referenced_p (rtx x
)
3015 if (!TARGET_HAVE_TLS
)
3018 return for_each_rtx (&x
, &sparc_tls_symbol_ref_1
, 0);
3021 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3022 this (thread-local) address. */
3025 legitimize_tls_address (rtx addr
)
3027 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3029 gcc_assert (! no_new_pseudos
);
3031 if (GET_CODE (addr
) == SYMBOL_REF
)
3032 switch (SYMBOL_REF_TLS_MODEL (addr
))
3034 case TLS_MODEL_GLOBAL_DYNAMIC
:
3036 temp1
= gen_reg_rtx (SImode
);
3037 temp2
= gen_reg_rtx (SImode
);
3038 ret
= gen_reg_rtx (Pmode
);
3039 o0
= gen_rtx_REG (Pmode
, 8);
3040 got
= sparc_tls_got ();
3041 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3042 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3045 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3046 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3051 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3052 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3055 CALL_INSN_FUNCTION_USAGE (insn
)
3056 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, o0
),
3057 CALL_INSN_FUNCTION_USAGE (insn
));
3058 insn
= get_insns ();
3060 emit_libcall_block (insn
, ret
, o0
, addr
);
3063 case TLS_MODEL_LOCAL_DYNAMIC
:
3065 temp1
= gen_reg_rtx (SImode
);
3066 temp2
= gen_reg_rtx (SImode
);
3067 temp3
= gen_reg_rtx (Pmode
);
3068 ret
= gen_reg_rtx (Pmode
);
3069 o0
= gen_rtx_REG (Pmode
, 8);
3070 got
= sparc_tls_got ();
3071 emit_insn (gen_tldm_hi22 (temp1
));
3072 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3075 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3076 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3081 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3082 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3085 CALL_INSN_FUNCTION_USAGE (insn
)
3086 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, o0
),
3087 CALL_INSN_FUNCTION_USAGE (insn
));
3088 insn
= get_insns ();
3090 emit_libcall_block (insn
, temp3
, o0
,
3091 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3092 UNSPEC_TLSLD_BASE
));
3093 temp1
= gen_reg_rtx (SImode
);
3094 temp2
= gen_reg_rtx (SImode
);
3095 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3096 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3098 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3100 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3103 case TLS_MODEL_INITIAL_EXEC
:
3104 temp1
= gen_reg_rtx (SImode
);
3105 temp2
= gen_reg_rtx (SImode
);
3106 temp3
= gen_reg_rtx (Pmode
);
3107 got
= sparc_tls_got ();
3108 emit_insn (gen_tie_hi22 (temp1
, addr
));
3109 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3111 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3113 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3116 ret
= gen_reg_rtx (Pmode
);
3118 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3121 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3125 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3128 case TLS_MODEL_LOCAL_EXEC
:
3129 temp1
= gen_reg_rtx (Pmode
);
3130 temp2
= gen_reg_rtx (Pmode
);
3133 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3134 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3138 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3139 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3141 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3149 gcc_unreachable (); /* for now ... */
3155 /* Legitimize PIC addresses. If the address is already position-independent,
3156 we return ORIG. Newly generated position-independent addresses go into a
3157 reg. This is REG if nonzero, otherwise we allocate register(s) as
3161 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3164 if (GET_CODE (orig
) == SYMBOL_REF
)
3166 rtx pic_ref
, address
;
3171 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3172 reg
= gen_reg_rtx (Pmode
);
3177 /* If not during reload, allocate another temp reg here for loading
3178 in the address, so that these instructions can be optimized
3180 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3181 ? reg
: gen_reg_rtx (Pmode
));
3183 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3184 won't get confused into thinking that these two instructions
3185 are loading in the true address of the symbol. If in the
3186 future a PIC rtx exists, that should be used instead. */
3189 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3190 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3194 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3195 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3202 pic_ref
= gen_const_mem (Pmode
,
3203 gen_rtx_PLUS (Pmode
,
3204 pic_offset_table_rtx
, address
));
3205 current_function_uses_pic_offset_table
= 1;
3206 insn
= emit_move_insn (reg
, pic_ref
);
3207 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3209 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3213 else if (GET_CODE (orig
) == CONST
)
3217 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3218 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3223 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3224 reg
= gen_reg_rtx (Pmode
);
3227 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3228 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3229 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3230 base
== reg
? 0 : reg
);
3232 if (GET_CODE (offset
) == CONST_INT
)
3234 if (SMALL_INT (offset
))
3235 return plus_constant (base
, INTVAL (offset
));
3236 else if (! reload_in_progress
&& ! reload_completed
)
3237 offset
= force_reg (Pmode
, offset
);
3239 /* If we reach here, then something is seriously wrong. */
3242 return gen_rtx_PLUS (Pmode
, base
, offset
);
3244 else if (GET_CODE (orig
) == LABEL_REF
)
3245 /* ??? Why do we do this? */
3246 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3247 the register is live instead, in case it is eliminated. */
3248 current_function_uses_pic_offset_table
= 1;
3253 /* Try machine-dependent ways of modifying an illegitimate address X
3254 to be legitimate. If we find one, return the new, valid address.
3256 OLDX is the address as it was before break_out_memory_refs was called.
3257 In some cases it is useful to look at this to decide what needs to be done.
3259 MODE is the mode of the operand pointed to by X. */
3262 legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
, enum machine_mode mode
)
3266 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3267 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3268 force_operand (XEXP (x
, 0), NULL_RTX
));
3269 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3270 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3271 force_operand (XEXP (x
, 1), NULL_RTX
));
3272 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3273 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3275 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3276 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3277 force_operand (XEXP (x
, 1), NULL_RTX
));
3279 if (x
!= orig_x
&& legitimate_address_p (mode
, x
, FALSE
))
3282 if (SPARC_SYMBOL_REF_TLS_P (x
))
3283 x
= legitimize_tls_address (x
);
3285 x
= legitimize_pic_address (x
, mode
, 0);
3286 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3287 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3288 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3289 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3290 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3291 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3292 else if (GET_CODE (x
) == SYMBOL_REF
3293 || GET_CODE (x
) == CONST
3294 || GET_CODE (x
) == LABEL_REF
)
3295 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3299 /* Emit the special PIC helper function. */
3302 emit_pic_helper (void)
3304 const char *pic_name
= reg_names
[REGNO (pic_offset_table_rtx
)];
3307 switch_to_section (text_section
);
3309 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
3311 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
3312 ASM_OUTPUT_LABEL (asm_out_file
, pic_helper_symbol_name
);
3313 if (flag_delayed_branch
)
3314 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
3315 pic_name
, pic_name
);
3317 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
3318 pic_name
, pic_name
);
3320 pic_helper_emitted_p
= true;
3323 /* Emit code to load the PIC register. */
3326 load_pic_register (bool delay_pic_helper
)
3328 int orig_flag_pic
= flag_pic
;
3330 /* If we haven't initialized the special PIC symbols, do so now. */
3331 if (!pic_helper_symbol_name
[0])
3333 ASM_GENERATE_INTERNAL_LABEL (pic_helper_symbol_name
, "LADDPC", 0);
3334 pic_helper_symbol
= gen_rtx_SYMBOL_REF (Pmode
, pic_helper_symbol_name
);
3335 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3338 /* If we haven't emitted the special PIC helper function, do so now unless
3339 we are requested to delay it. */
3340 if (!delay_pic_helper
&& !pic_helper_emitted_p
)
3345 emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx
, global_offset_table
,
3346 pic_helper_symbol
));
3348 emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx
, global_offset_table
,
3349 pic_helper_symbol
));
3350 flag_pic
= orig_flag_pic
;
3352 /* Need to emit this whether or not we obey regdecls,
3353 since setjmp/longjmp can cause life info to screw up.
3354 ??? In the case where we don't obey regdecls, this is not sufficient
3355 since we may not fall out the bottom. */
3356 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3359 /* Return 1 if RTX is a MEM which is known to be aligned to at
3360 least a DESIRED byte boundary. */
3363 mem_min_alignment (rtx mem
, int desired
)
3365 rtx addr
, base
, offset
;
3367 /* If it's not a MEM we can't accept it. */
3368 if (GET_CODE (mem
) != MEM
)
3372 if (!TARGET_UNALIGNED_DOUBLES
3373 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
3376 /* ??? The rest of the function predates MEM_ALIGN so
3377 there is probably a bit of redundancy. */
3378 addr
= XEXP (mem
, 0);
3379 base
= offset
= NULL_RTX
;
3380 if (GET_CODE (addr
) == PLUS
)
3382 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3384 base
= XEXP (addr
, 0);
3386 /* What we are saying here is that if the base
3387 REG is aligned properly, the compiler will make
3388 sure any REG based index upon it will be so
3390 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3391 offset
= XEXP (addr
, 1);
3393 offset
= const0_rtx
;
3396 else if (GET_CODE (addr
) == REG
)
3399 offset
= const0_rtx
;
3402 if (base
!= NULL_RTX
)
3404 int regno
= REGNO (base
);
3406 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3408 /* Check if the compiler has recorded some information
3409 about the alignment of the base REG. If reload has
3410 completed, we already matched with proper alignments.
3411 If not running global_alloc, reload might give us
3412 unaligned pointer to local stack though. */
3414 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3415 || (optimize
&& reload_completed
))
3416 && (INTVAL (offset
) & (desired
- 1)) == 0)
3421 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3425 else if (! TARGET_UNALIGNED_DOUBLES
3426 || CONSTANT_P (addr
)
3427 || GET_CODE (addr
) == LO_SUM
)
3429 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3430 is true, in which case we can only assume that an access is aligned if
3431 it is to a constant address, or the address involves a LO_SUM. */
3435 /* An obviously unaligned address. */
3440 /* Vectors to keep interesting information about registers where it can easily
3441 be got. We used to use the actual mode value as the bit number, but there
3442 are more than 32 modes now. Instead we use two tables: one indexed by
3443 hard register number, and one indexed by mode. */
3445 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3446 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3447 mapped into one sparc_mode_class mode. */
3449 enum sparc_mode_class
{
3450 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
3451 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
3455 /* Modes for single-word and smaller quantities. */
3456 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3458 /* Modes for double-word and smaller quantities. */
3459 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3461 /* Modes for quad-word and smaller quantities. */
3462 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3464 /* Modes for 8-word and smaller quantities. */
3465 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3467 /* Modes for single-float quantities. We must allow any single word or
3468 smaller quantity. This is because the fix/float conversion instructions
3469 take integer inputs/outputs from the float registers. */
3470 #define SF_MODES (S_MODES)
3472 /* Modes for double-float and smaller quantities. */
3473 #define DF_MODES (S_MODES | D_MODES)
3475 /* Modes for double-float only quantities. */
3476 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3478 /* Modes for quad-float only quantities. */
3479 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3481 /* Modes for quad-float and smaller quantities. */
3482 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3484 /* Modes for quad-float and double-float quantities. */
3485 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3487 /* Modes for quad-float pair only quantities. */
3488 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3490 /* Modes for quad-float pairs and smaller quantities. */
3491 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3493 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3495 /* Modes for condition codes. */
3496 #define CC_MODES (1 << (int) CC_MODE)
3497 #define CCFP_MODES (1 << (int) CCFP_MODE)
3499 /* Value is 1 if register/mode pair is acceptable on sparc.
3500 The funny mixture of D and T modes is because integer operations
3501 do not specially operate on tetra quantities, so non-quad-aligned
3502 registers can hold quadword quantities (except %o4 and %i4 because
3503 they cross fixed registers). */
3505 /* This points to either the 32 bit or the 64 bit version. */
3506 const int *hard_regno_mode_classes
;
3508 static const int hard_32bit_mode_classes
[] = {
3509 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3510 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3511 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3512 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3514 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3515 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3516 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3517 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3519 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3520 and none can hold SFmode/SImode values. */
3521 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3522 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3523 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3524 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3527 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3533 static const int hard_64bit_mode_classes
[] = {
3534 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3535 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3536 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3537 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3539 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3540 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3541 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3542 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3544 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3545 and none can hold SFmode/SImode values. */
3546 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3547 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3548 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3549 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3552 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3558 int sparc_mode_class
[NUM_MACHINE_MODES
];
3560 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
3563 sparc_init_modes (void)
3567 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
3569 switch (GET_MODE_CLASS (i
))
3572 case MODE_PARTIAL_INT
:
3573 case MODE_COMPLEX_INT
:
3574 if (GET_MODE_SIZE (i
) <= 4)
3575 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
3576 else if (GET_MODE_SIZE (i
) == 8)
3577 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
3578 else if (GET_MODE_SIZE (i
) == 16)
3579 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
3580 else if (GET_MODE_SIZE (i
) == 32)
3581 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
3583 sparc_mode_class
[i
] = 0;
3585 case MODE_VECTOR_INT
:
3586 if (GET_MODE_SIZE (i
) <= 4)
3587 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
3588 else if (GET_MODE_SIZE (i
) == 8)
3589 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
3592 case MODE_COMPLEX_FLOAT
:
3593 if (GET_MODE_SIZE (i
) <= 4)
3594 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
3595 else if (GET_MODE_SIZE (i
) == 8)
3596 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
3597 else if (GET_MODE_SIZE (i
) == 16)
3598 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
3599 else if (GET_MODE_SIZE (i
) == 32)
3600 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
3602 sparc_mode_class
[i
] = 0;
3605 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
3606 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
3608 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
3611 sparc_mode_class
[i
] = 0;
3617 hard_regno_mode_classes
= hard_64bit_mode_classes
;
3619 hard_regno_mode_classes
= hard_32bit_mode_classes
;
3621 /* Initialize the array used by REGNO_REG_CLASS. */
3622 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3624 if (i
< 16 && TARGET_V8PLUS
)
3625 sparc_regno_reg_class
[i
] = I64_REGS
;
3626 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
3627 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
3629 sparc_regno_reg_class
[i
] = FP_REGS
;
3631 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
3633 sparc_regno_reg_class
[i
] = FPCC_REGS
;
3635 sparc_regno_reg_class
[i
] = NO_REGS
;
3639 /* Compute the frame size required by the function. This function is called
3640 during the reload pass and also by sparc_expand_prologue. */
3643 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function_p
)
3645 int outgoing_args_size
= (current_function_outgoing_args_size
3646 + REG_PARM_STACK_SPACE (current_function_decl
));
3647 int n_regs
= 0; /* N_REGS is the number of 4-byte regs saved thus far. */
3652 for (i
= 0; i
< 8; i
++)
3653 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3658 for (i
= 0; i
< 8; i
+= 2)
3659 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3660 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3664 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
3665 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3666 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3669 /* Set up values for use in prologue and epilogue. */
3670 num_gfregs
= n_regs
;
3675 && current_function_outgoing_args_size
== 0)
3676 actual_fsize
= apparent_fsize
= 0;
3679 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3680 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
3681 apparent_fsize
+= n_regs
* 4;
3682 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
3685 /* Make sure nothing can clobber our register windows.
3686 If a SAVE must be done, or there is a stack-local variable,
3687 the register window area must be allocated. */
3688 if (! leaf_function_p
|| size
> 0)
3689 actual_fsize
+= FIRST_PARM_OFFSET (current_function_decl
);
3691 return SPARC_STACK_ALIGN (actual_fsize
);
3694 /* Output any necessary .register pseudo-ops. */
3697 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
3699 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3705 /* Check if %g[2367] were used without
3706 .register being printed for them already. */
3707 for (i
= 2; i
< 8; i
++)
3709 if (regs_ever_live
[i
]
3710 && ! sparc_hard_reg_printed
[i
])
3712 sparc_hard_reg_printed
[i
] = 1;
3713 /* %g7 is used as TLS base register, use #ignore
3714 for it instead of #scratch. */
3715 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
3716 i
== 7 ? "ignore" : "scratch");
3723 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
3724 as needed. LOW should be double-word aligned for 32-bit registers.
3725 Return the new OFFSET. */
3728 #define SORR_RESTORE 1
3731 save_or_restore_regs (int low
, int high
, rtx base
, int offset
, int action
)
3736 if (TARGET_ARCH64
&& high
<= 32)
3738 for (i
= low
; i
< high
; i
++)
3740 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3742 mem
= gen_rtx_MEM (DImode
, plus_constant (base
, offset
));
3743 set_mem_alias_set (mem
, sparc_sr_alias_set
);
3744 if (action
== SORR_SAVE
)
3746 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
3747 RTX_FRAME_RELATED_P (insn
) = 1;
3749 else /* action == SORR_RESTORE */
3750 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
3757 for (i
= low
; i
< high
; i
+= 2)
3759 bool reg0
= regs_ever_live
[i
] && ! call_used_regs
[i
];
3760 bool reg1
= regs_ever_live
[i
+1] && ! call_used_regs
[i
+1];
3761 enum machine_mode mode
;
3766 mode
= i
< 32 ? DImode
: DFmode
;
3771 mode
= i
< 32 ? SImode
: SFmode
;
3776 mode
= i
< 32 ? SImode
: SFmode
;
3783 mem
= gen_rtx_MEM (mode
, plus_constant (base
, offset
));
3784 set_mem_alias_set (mem
, sparc_sr_alias_set
);
3785 if (action
== SORR_SAVE
)
3787 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
3788 RTX_FRAME_RELATED_P (insn
) = 1;
3790 else /* action == SORR_RESTORE */
3791 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
3793 /* Always preserve double-word alignment. */
3794 offset
= (offset
+ 7) & -8;
3801 /* Emit code to save call-saved registers. */
3804 emit_save_or_restore_regs (int action
)
3806 HOST_WIDE_INT offset
;
3809 offset
= frame_base_offset
- apparent_fsize
;
3811 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4095)
3813 /* ??? This might be optimized a little as %g1 might already have a
3814 value close enough that a single add insn will do. */
3815 /* ??? Although, all of this is probably only a temporary fix
3816 because if %g1 can hold a function result, then
3817 sparc_expand_epilogue will lose (the result will be
3819 base
= gen_rtx_REG (Pmode
, 1);
3820 emit_move_insn (base
, GEN_INT (offset
));
3821 emit_insn (gen_rtx_SET (VOIDmode
,
3823 gen_rtx_PLUS (Pmode
, frame_base_reg
, base
)));
3827 base
= frame_base_reg
;
3829 offset
= save_or_restore_regs (0, 8, base
, offset
, action
);
3830 save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, action
);
3833 /* Generate a save_register_window insn. */
3836 gen_save_register_window (rtx increment
)
3839 return gen_save_register_windowdi (increment
);
3841 return gen_save_register_windowsi (increment
);
3844 /* Generate an increment for the stack pointer. */
3847 gen_stack_pointer_inc (rtx increment
)
3849 return gen_rtx_SET (VOIDmode
,
3851 gen_rtx_PLUS (Pmode
,
3856 /* Generate a decrement for the stack pointer. */
3859 gen_stack_pointer_dec (rtx decrement
)
3861 return gen_rtx_SET (VOIDmode
,
3863 gen_rtx_MINUS (Pmode
,
3868 /* Expand the function prologue. The prologue is responsible for reserving
3869 storage for the frame, saving the call-saved registers and loading the
3870 PIC register if needed. */
3873 sparc_expand_prologue (void)
3878 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
3879 on the final value of the flag means deferring the prologue/epilogue
3880 expansion until just before the second scheduling pass, which is too
3881 late to emit multiple epilogues or return insns.
3883 Of course we are making the assumption that the value of the flag
3884 will not change between now and its final value. Of the three parts
3885 of the formula, only the last one can reasonably vary. Let's take a
3886 closer look, after assuming that the first two ones are set to true
3887 (otherwise the last value is effectively silenced).
3889 If only_leaf_regs_used returns false, the global predicate will also
3890 be false so the actual frame size calculated below will be positive.
3891 As a consequence, the save_register_window insn will be emitted in
3892 the instruction stream; now this insn explicitly references %fp
3893 which is not a leaf register so only_leaf_regs_used will always
3894 return false subsequently.
3896 If only_leaf_regs_used returns true, we hope that the subsequent
3897 optimization passes won't cause non-leaf registers to pop up. For
3898 example, the regrename pass has special provisions to not rename to
3899 non-leaf registers in a leaf function. */
3900 sparc_leaf_function_p
3901 = optimize
> 0 && leaf_function_p () && only_leaf_regs_used ();
3903 /* Need to use actual_fsize, since we are also allocating
3904 space for our callee (and our own register save area). */
3906 = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
3908 /* Advertise that the data calculated just above are now valid. */
3909 sparc_prologue_data_valid_p
= true;
3911 if (sparc_leaf_function_p
)
3913 frame_base_reg
= stack_pointer_rtx
;
3914 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
3918 frame_base_reg
= hard_frame_pointer_rtx
;
3919 frame_base_offset
= SPARC_STACK_BIAS
;
3922 if (actual_fsize
== 0)
3924 else if (sparc_leaf_function_p
)
3926 if (actual_fsize
<= 4096)
3927 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-actual_fsize
)));
3928 else if (actual_fsize
<= 8192)
3930 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
3931 /* %sp is still the CFA register. */
3932 RTX_FRAME_RELATED_P (insn
) = 1;
3934 = emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize
)));
3938 rtx reg
= gen_rtx_REG (Pmode
, 1);
3939 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
3940 insn
= emit_insn (gen_stack_pointer_inc (reg
));
3942 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3943 gen_stack_pointer_inc (GEN_INT (-actual_fsize
)),
3947 RTX_FRAME_RELATED_P (insn
) = 1;
3951 if (actual_fsize
<= 4096)
3952 insn
= emit_insn (gen_save_register_window (GEN_INT (-actual_fsize
)));
3953 else if (actual_fsize
<= 8192)
3955 insn
= emit_insn (gen_save_register_window (GEN_INT (-4096)));
3956 /* %sp is not the CFA register anymore. */
3957 emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize
)));
3961 rtx reg
= gen_rtx_REG (Pmode
, 1);
3962 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
3963 insn
= emit_insn (gen_save_register_window (reg
));
3966 RTX_FRAME_RELATED_P (insn
) = 1;
3967 for (i
=0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
3968 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn
), 0, i
)) = 1;
3972 emit_save_or_restore_regs (SORR_SAVE
);
3974 /* Load the PIC register if needed. */
3975 if (flag_pic
&& current_function_uses_pic_offset_table
)
3976 load_pic_register (false);
3979 /* This function generates the assembly code for function entry, which boils
3980 down to emitting the necessary .register directives. */
3983 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3985 /* Check that the assumption we made in sparc_expand_prologue is valid. */
3986 gcc_assert (sparc_leaf_function_p
== current_function_uses_only_leaf_regs
);
3988 sparc_output_scratch_registers (file
);
3991 /* Expand the function epilogue, either normal or part of a sibcall.
3992 We emit all the instructions except the return or the call. */
3995 sparc_expand_epilogue (void)
3998 emit_save_or_restore_regs (SORR_RESTORE
);
4000 if (actual_fsize
== 0)
4002 else if (sparc_leaf_function_p
)
4004 if (actual_fsize
<= 4096)
4005 emit_insn (gen_stack_pointer_dec (GEN_INT (- actual_fsize
)));
4006 else if (actual_fsize
<= 8192)
4008 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4009 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - actual_fsize
)));
4013 rtx reg
= gen_rtx_REG (Pmode
, 1);
4014 emit_move_insn (reg
, GEN_INT (-actual_fsize
));
4015 emit_insn (gen_stack_pointer_dec (reg
));
4020 /* Return true if it is appropriate to emit `return' instructions in the
4021 body of a function. */
4024 sparc_can_use_return_insn_p (void)
4026 return sparc_prologue_data_valid_p
4027 && (actual_fsize
== 0 || !sparc_leaf_function_p
);
4030 /* This function generates the assembly code for function exit. */
4033 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4035 /* If code does not drop into the epilogue, we have to still output
4036 a dummy nop for the sake of sane backtraces. Otherwise, if the
4037 last two instructions of a function were "call foo; dslot;" this
4038 can make the return PC of foo (i.e. address of call instruction
4039 plus 8) point to the first instruction in the next function. */
4041 rtx insn
, last_real_insn
;
4043 insn
= get_last_insn ();
4045 last_real_insn
= prev_real_insn (insn
);
4047 && GET_CODE (last_real_insn
) == INSN
4048 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
4049 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
4051 if (last_real_insn
&& GET_CODE (last_real_insn
) == CALL_INSN
)
4052 fputs("\tnop\n", file
);
4054 sparc_output_deferred_case_vectors ();
4057 /* Output a 'restore' instruction. */
4060 output_restore (rtx pat
)
4066 fputs ("\t restore\n", asm_out_file
);
4070 gcc_assert (GET_CODE (pat
) == SET
);
4072 operands
[0] = SET_DEST (pat
);
4073 pat
= SET_SRC (pat
);
4075 switch (GET_CODE (pat
))
4078 operands
[1] = XEXP (pat
, 0);
4079 operands
[2] = XEXP (pat
, 1);
4080 output_asm_insn (" restore %r1, %2, %Y0", operands
);
4083 operands
[1] = XEXP (pat
, 0);
4084 operands
[2] = XEXP (pat
, 1);
4085 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
4088 operands
[1] = XEXP (pat
, 0);
4089 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
4090 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
4094 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
4099 /* Output a return. */
4102 output_return (rtx insn
)
4104 if (sparc_leaf_function_p
)
4106 /* This is a leaf function so we don't have to bother restoring the
4107 register window, which frees us from dealing with the convoluted
4108 semantics of restore/return. We simply output the jump to the
4109 return address and the insn in the delay slot (if any). */
4111 gcc_assert (! current_function_calls_eh_return
);
4113 return "jmp\t%%o7+%)%#";
4117 /* This is a regular function so we have to restore the register window.
4118 We may have a pending insn for the delay slot, which will be either
4119 combined with the 'restore' instruction or put in the delay slot of
4120 the 'return' instruction. */
4122 if (current_function_calls_eh_return
)
4124 /* If the function uses __builtin_eh_return, the eh_return
4125 machinery occupies the delay slot. */
4126 gcc_assert (! final_sequence
);
4128 if (! flag_delayed_branch
)
4129 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file
);
4132 fputs ("\treturn\t%i7+8\n", asm_out_file
);
4134 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file
);
4136 if (flag_delayed_branch
)
4137 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
4139 fputs ("\t nop\n", asm_out_file
);
4141 else if (final_sequence
)
4145 delay
= NEXT_INSN (insn
);
4148 pat
= PATTERN (delay
);
4150 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
4152 epilogue_renumber (&pat
, 0);
4153 return "return\t%%i7+%)%#";
4157 output_asm_insn ("jmp\t%%i7+%)", NULL
);
4158 output_restore (pat
);
4159 PATTERN (delay
) = gen_blockage ();
4160 INSN_CODE (delay
) = -1;
4165 /* The delay slot is empty. */
4167 return "return\t%%i7+%)\n\t nop";
4168 else if (flag_delayed_branch
)
4169 return "jmp\t%%i7+%)\n\t restore";
4171 return "restore\n\tjmp\t%%o7+%)\n\t nop";
4178 /* Output a sibling call. */
4181 output_sibcall (rtx insn
, rtx call_operand
)
4185 gcc_assert (flag_delayed_branch
);
4187 operands
[0] = call_operand
;
4189 if (sparc_leaf_function_p
)
4191 /* This is a leaf function so we don't have to bother restoring the
4192 register window. We simply output the jump to the function and
4193 the insn in the delay slot (if any). */
4195 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
4198 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
4201 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4202 it into branch if possible. */
4203 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
4208 /* This is a regular function so we have to restore the register window.
4209 We may have a pending insn for the delay slot, which will be combined
4210 with the 'restore' instruction. */
4212 output_asm_insn ("call\t%a0, 0", operands
);
4216 rtx delay
= NEXT_INSN (insn
);
4219 output_restore (PATTERN (delay
));
4221 PATTERN (delay
) = gen_blockage ();
4222 INSN_CODE (delay
) = -1;
4225 output_restore (NULL_RTX
);
4231 /* Functions for handling argument passing.
4233 For 32-bit, the first 6 args are normally in registers and the rest are
4234 pushed. Any arg that starts within the first 6 words is at least
4235 partially passed in a register unless its data type forbids.
4237 For 64-bit, the argument registers are laid out as an array of 16 elements
4238 and arguments are added sequentially. The first 6 int args and up to the
4239 first 16 fp args (depending on size) are passed in regs.
4241 Slot Stack Integral Float Float in structure Double Long Double
4242 ---- ----- -------- ----- ------------------ ------ -----------
4243 15 [SP+248] %f31 %f30,%f31 %d30
4244 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4245 13 [SP+232] %f27 %f26,%f27 %d26
4246 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4247 11 [SP+216] %f23 %f22,%f23 %d22
4248 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4249 9 [SP+200] %f19 %f18,%f19 %d18
4250 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4251 7 [SP+184] %f15 %f14,%f15 %d14
4252 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4253 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4254 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4255 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4256 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4257 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4258 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4260 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4262 Integral arguments are always passed as 64-bit quantities appropriately
4265 Passing of floating point values is handled as follows.
4266 If a prototype is in scope:
4267 If the value is in a named argument (i.e. not a stdarg function or a
4268 value not part of the `...') then the value is passed in the appropriate
4270 If the value is part of the `...' and is passed in one of the first 6
4271 slots then the value is passed in the appropriate int reg.
4272 If the value is part of the `...' and is not passed in one of the first 6
4273 slots then the value is passed in memory.
4274 If a prototype is not in scope:
4275 If the value is one of the first 6 arguments the value is passed in the
4276 appropriate integer reg and the appropriate fp reg.
4277 If the value is not one of the first 6 arguments the value is passed in
4278 the appropriate fp reg and in memory.
4281 Summary of the calling conventions implemented by GCC on SPARC:
4284 size argument return value
4286 small integer <4 int. reg. int. reg.
4287 word 4 int. reg. int. reg.
4288 double word 8 int. reg. int. reg.
4290 _Complex small integer <8 int. reg. int. reg.
4291 _Complex word 8 int. reg. int. reg.
4292 _Complex double word 16 memory int. reg.
4294 vector integer <=8 int. reg. FP reg.
4295 vector integer >8 memory memory
4297 float 4 int. reg. FP reg.
4298 double 8 int. reg. FP reg.
4299 long double 16 memory memory
4301 _Complex float 8 memory FP reg.
4302 _Complex double 16 memory FP reg.
4303 _Complex long double 32 memory FP reg.
4305 vector float any memory memory
4307 aggregate any memory memory
4312 size argument return value
4314 small integer <8 int. reg. int. reg.
4315 word 8 int. reg. int. reg.
4316 double word 16 int. reg. int. reg.
4318 _Complex small integer <16 int. reg. int. reg.
4319 _Complex word 16 int. reg. int. reg.
4320 _Complex double word 32 memory int. reg.
4322 vector integer <=16 FP reg. FP reg.
4323 vector integer 16<s<=32 memory FP reg.
4324 vector integer >32 memory memory
4326 float 4 FP reg. FP reg.
4327 double 8 FP reg. FP reg.
4328 long double 16 FP reg. FP reg.
4330 _Complex float 8 FP reg. FP reg.
4331 _Complex double 16 FP reg. FP reg.
4332 _Complex long double 32 memory FP reg.
4334 vector float <=16 FP reg. FP reg.
4335 vector float 16<s<=32 memory FP reg.
4336 vector float >32 memory memory
4338 aggregate <=16 reg. reg.
4339 aggregate 16<s<=32 memory reg.
4340 aggregate >32 memory memory
4344 Note #1: complex floating-point types follow the extended SPARC ABIs as
4345 implemented by the Sun compiler.
4347 Note #2: integral vector types follow the scalar floating-point types
4348 conventions to match what is implemented by the Sun VIS SDK.
4350 Note #3: floating-point vector types follow the aggregate types
4354 /* Maximum number of int regs for args. */
4355 #define SPARC_INT_ARG_MAX 6
4356 /* Maximum number of fp regs for args. */
4357 #define SPARC_FP_ARG_MAX 16
4359 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4361 /* Handle the INIT_CUMULATIVE_ARGS macro.
4362 Initialize a variable CUM of type CUMULATIVE_ARGS
4363 for a call to a function whose data type is FNTYPE.
4364 For a library call, FNTYPE is 0. */
4367 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
4368 rtx libname ATTRIBUTE_UNUSED
,
4369 tree fndecl ATTRIBUTE_UNUSED
)
4372 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
4373 cum
->libcall_p
= fntype
== 0;
4376 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
4377 When a prototype says `char' or `short', really pass an `int'. */
4380 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED
)
4382 return TARGET_ARCH32
? true : false;
4385 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
4388 sparc_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
4390 return TARGET_ARCH64
? true : false;
4393 /* Scan the record type TYPE and return the following predicates:
4394 - INTREGS_P: the record contains at least one field or sub-field
4395 that is eligible for promotion in integer registers.
4396 - FP_REGS_P: the record contains at least one field or sub-field
4397 that is eligible for promotion in floating-point registers.
4398 - PACKED_P: the record contains at least one field that is packed.
4400 Sub-fields are not taken into account for the PACKED_P predicate. */
4403 scan_record_type (tree type
, int *intregs_p
, int *fpregs_p
, int *packed_p
)
4407 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4409 if (TREE_CODE (field
) == FIELD_DECL
)
4411 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4412 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
4413 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
4414 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
4420 if (packed_p
&& DECL_PACKED (field
))
4426 /* Compute the slot number to pass an argument in.
4427 Return the slot number or -1 if passing on the stack.
4429 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4430 the preceding args and about the function being called.
4431 MODE is the argument's machine mode.
4432 TYPE is the data type of the argument (as a tree).
4433 This is null for libcalls where that information may
4435 NAMED is nonzero if this argument is a named parameter
4436 (otherwise it is an extra parameter matching an ellipsis).
4437 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4438 *PREGNO records the register number to use if scalar type.
4439 *PPADDING records the amount of padding needed in words. */
4442 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
4443 tree type
, int named
, int incoming_p
,
4444 int *pregno
, int *ppadding
)
4446 int regbase
= (incoming_p
4447 ? SPARC_INCOMING_INT_ARG_FIRST
4448 : SPARC_OUTGOING_INT_ARG_FIRST
);
4449 int slotno
= cum
->words
;
4450 enum mode_class mclass
;
4455 if (type
&& TREE_ADDRESSABLE (type
))
4461 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
4464 /* For SPARC64, objects requiring 16-byte alignment get it. */
4466 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
4467 && (slotno
& 1) != 0)
4468 slotno
++, *ppadding
= 1;
4470 mclass
= GET_MODE_CLASS (mode
);
4471 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
4473 /* Vector types deserve special treatment because they are
4474 polymorphic wrt their mode, depending upon whether VIS
4475 instructions are enabled. */
4476 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
4478 /* The SPARC port defines no floating-point vector modes. */
4479 gcc_assert (mode
== BLKmode
);
4483 /* Integral vector types should either have a vector
4484 mode or an integral mode, because we are guaranteed
4485 by pass_by_reference that their size is not greater
4486 than 16 bytes and TImode is 16-byte wide. */
4487 gcc_assert (mode
!= BLKmode
);
4489 /* Vector integers are handled like floats according to
4491 mclass
= MODE_FLOAT
;
4498 case MODE_COMPLEX_FLOAT
:
4499 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
4501 if (slotno
>= SPARC_FP_ARG_MAX
)
4503 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
4504 /* Arguments filling only one single FP register are
4505 right-justified in the outer double FP register. */
4506 if (GET_MODE_SIZE (mode
) <= 4)
4513 case MODE_COMPLEX_INT
:
4514 if (slotno
>= SPARC_INT_ARG_MAX
)
4516 regno
= regbase
+ slotno
;
4520 if (mode
== VOIDmode
)
4521 /* MODE is VOIDmode when generating the actual call. */
4524 gcc_assert (mode
== BLKmode
);
4526 if (TARGET_ARCH32
|| !type
|| (TREE_CODE (type
) == UNION_TYPE
))
4528 if (slotno
>= SPARC_INT_ARG_MAX
)
4530 regno
= regbase
+ slotno
;
4532 else /* TARGET_ARCH64 && type */
4534 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
4536 /* First see what kinds of registers we would need. */
4537 if (TREE_CODE (type
) == VECTOR_TYPE
)
4540 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
4542 /* The ABI obviously doesn't specify how packed structures
4543 are passed. These are defined to be passed in int regs
4544 if possible, otherwise memory. */
4545 if (packed_p
|| !named
)
4546 fpregs_p
= 0, intregs_p
= 1;
4548 /* If all arg slots are filled, then must pass on stack. */
4549 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
4552 /* If there are only int args and all int arg slots are filled,
4553 then must pass on stack. */
4554 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
4557 /* Note that even if all int arg slots are filled, fp members may
4558 still be passed in regs if such regs are available.
4559 *PREGNO isn't set because there may be more than one, it's up
4560 to the caller to compute them. */
4573 /* Handle recursive register counting for structure field layout. */
4575 struct function_arg_record_value_parms
4577 rtx ret
; /* return expression being built. */
4578 int slotno
; /* slot number of the argument. */
4579 int named
; /* whether the argument is named. */
4580 int regbase
; /* regno of the base register. */
4581 int stack
; /* 1 if part of the argument is on the stack. */
4582 int intoffset
; /* offset of the first pending integer field. */
4583 unsigned int nregs
; /* number of words passed in registers. */
4586 static void function_arg_record_value_3
4587 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
4588 static void function_arg_record_value_2
4589 (tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
4590 static void function_arg_record_value_1
4591 (tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
4592 static rtx
function_arg_record_value (tree
, enum machine_mode
, int, int, int);
4593 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
4595 /* A subroutine of function_arg_record_value. Traverse the structure
4596 recursively and determine how many registers will be required. */
4599 function_arg_record_value_1 (tree type
, HOST_WIDE_INT startbitpos
,
4600 struct function_arg_record_value_parms
*parms
,
4605 /* We need to compute how many registers are needed so we can
4606 allocate the PARALLEL but before we can do that we need to know
4607 whether there are any packed fields. The ABI obviously doesn't
4608 specify how structures are passed in this case, so they are
4609 defined to be passed in int regs if possible, otherwise memory,
4610 regardless of whether there are fp values present. */
4613 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4615 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4622 /* Compute how many registers we need. */
4623 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4625 if (TREE_CODE (field
) == FIELD_DECL
)
4627 HOST_WIDE_INT bitpos
= startbitpos
;
4629 if (DECL_SIZE (field
) != 0)
4631 if (integer_zerop (DECL_SIZE (field
)))
4634 if (host_integerp (bit_position (field
), 1))
4635 bitpos
+= int_bit_position (field
);
4638 /* ??? FIXME: else assume zero offset. */
4640 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4641 function_arg_record_value_1 (TREE_TYPE (field
),
4645 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
4646 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
4651 if (parms
->intoffset
!= -1)
4653 unsigned int startbit
, endbit
;
4654 int intslots
, this_slotno
;
4656 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
4657 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4659 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4660 this_slotno
= parms
->slotno
+ parms
->intoffset
4663 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
4665 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
4666 /* We need to pass this field on the stack. */
4670 parms
->nregs
+= intslots
;
4671 parms
->intoffset
= -1;
4674 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4675 If it wasn't true we wouldn't be here. */
4676 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
4677 && DECL_MODE (field
) == BLKmode
)
4678 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
4679 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4686 if (parms
->intoffset
== -1)
4687 parms
->intoffset
= bitpos
;
4693 /* A subroutine of function_arg_record_value. Assign the bits of the
4694 structure between parms->intoffset and bitpos to integer registers. */
4697 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
4698 struct function_arg_record_value_parms
*parms
)
4700 enum machine_mode mode
;
4702 unsigned int startbit
, endbit
;
4703 int this_slotno
, intslots
, intoffset
;
4706 if (parms
->intoffset
== -1)
4709 intoffset
= parms
->intoffset
;
4710 parms
->intoffset
= -1;
4712 startbit
= intoffset
& -BITS_PER_WORD
;
4713 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4714 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4715 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
4717 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4721 /* If this is the trailing part of a word, only load that much into
4722 the register. Otherwise load the whole register. Note that in
4723 the latter case we may pick up unwanted bits. It's not a problem
4724 at the moment but may wish to revisit. */
4726 if (intoffset
% BITS_PER_WORD
!= 0)
4727 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
4732 intoffset
/= BITS_PER_UNIT
;
4735 regno
= parms
->regbase
+ this_slotno
;
4736 reg
= gen_rtx_REG (mode
, regno
);
4737 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
4738 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
4741 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
4746 while (intslots
> 0);
4749 /* A subroutine of function_arg_record_value. Traverse the structure
4750 recursively and assign bits to floating point registers. Track which
4751 bits in between need integer registers; invoke function_arg_record_value_3
4752 to make that happen. */
4755 function_arg_record_value_2 (tree type
, HOST_WIDE_INT startbitpos
,
4756 struct function_arg_record_value_parms
*parms
,
4762 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4764 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4771 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4773 if (TREE_CODE (field
) == FIELD_DECL
)
4775 HOST_WIDE_INT bitpos
= startbitpos
;
4777 if (DECL_SIZE (field
) != 0)
4779 if (integer_zerop (DECL_SIZE (field
)))
4782 if (host_integerp (bit_position (field
), 1))
4783 bitpos
+= int_bit_position (field
);
4786 /* ??? FIXME: else assume zero offset. */
4788 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4789 function_arg_record_value_2 (TREE_TYPE (field
),
4793 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
4794 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
4799 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
4800 int regno
, nregs
, pos
;
4801 enum machine_mode mode
= DECL_MODE (field
);
4804 function_arg_record_value_3 (bitpos
, parms
);
4806 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
4809 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
4810 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
4812 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4814 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
4820 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
4821 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
4823 reg
= gen_rtx_REG (mode
, regno
);
4824 pos
= bitpos
/ BITS_PER_UNIT
;
4825 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
4826 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
4830 regno
+= GET_MODE_SIZE (mode
) / 4;
4831 reg
= gen_rtx_REG (mode
, regno
);
4832 pos
+= GET_MODE_SIZE (mode
);
4833 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
4834 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
4840 if (parms
->intoffset
== -1)
4841 parms
->intoffset
= bitpos
;
4847 /* Used by function_arg and function_value to implement the complex
4848 conventions of the 64-bit ABI for passing and returning structures.
4849 Return an expression valid as a return value for the two macros
4850 FUNCTION_ARG and FUNCTION_VALUE.
4852 TYPE is the data type of the argument (as a tree).
4853 This is null for libcalls where that information may
4855 MODE is the argument's machine mode.
4856 SLOTNO is the index number of the argument's slot in the parameter array.
4857 NAMED is nonzero if this argument is a named parameter
4858 (otherwise it is an extra parameter matching an ellipsis).
4859 REGBASE is the regno of the base register for the parameter array. */
4862 function_arg_record_value (tree type
, enum machine_mode mode
,
4863 int slotno
, int named
, int regbase
)
4865 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
4866 struct function_arg_record_value_parms parms
;
4869 parms
.ret
= NULL_RTX
;
4870 parms
.slotno
= slotno
;
4871 parms
.named
= named
;
4872 parms
.regbase
= regbase
;
4875 /* Compute how many registers we need. */
4877 parms
.intoffset
= 0;
4878 function_arg_record_value_1 (type
, 0, &parms
, false);
4880 /* Take into account pending integer fields. */
4881 if (parms
.intoffset
!= -1)
4883 unsigned int startbit
, endbit
;
4884 int intslots
, this_slotno
;
4886 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
4887 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4888 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4889 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
4891 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
4893 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
4894 /* We need to pass this field on the stack. */
4898 parms
.nregs
+= intslots
;
4900 nregs
= parms
.nregs
;
4902 /* Allocate the vector and handle some annoying special cases. */
4905 /* ??? Empty structure has no value? Duh? */
4908 /* Though there's nothing really to store, return a word register
4909 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4910 leads to breakage due to the fact that there are zero bytes to
4912 return gen_rtx_REG (mode
, regbase
);
4916 /* ??? C++ has structures with no fields, and yet a size. Give up
4917 for now and pass everything back in integer registers. */
4918 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4920 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
4921 nregs
= SPARC_INT_ARG_MAX
- slotno
;
4923 gcc_assert (nregs
!= 0);
4925 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
4927 /* If at least one field must be passed on the stack, generate
4928 (parallel [(expr_list (nil) ...) ...]) so that all fields will
4929 also be passed on the stack. We can't do much better because the
4930 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
4931 of structures for which the fields passed exclusively in registers
4932 are not at the beginning of the structure. */
4934 XVECEXP (parms
.ret
, 0, 0)
4935 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4937 /* Fill in the entries. */
4939 parms
.intoffset
= 0;
4940 function_arg_record_value_2 (type
, 0, &parms
, false);
4941 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
4943 gcc_assert (parms
.nregs
== nregs
);
4948 /* Used by function_arg and function_value to implement the conventions
4949 of the 64-bit ABI for passing and returning unions.
4950 Return an expression valid as a return value for the two macros
4951 FUNCTION_ARG and FUNCTION_VALUE.
4953 SIZE is the size in bytes of the union.
4954 MODE is the argument's machine mode.
4955 REGNO is the hard register the union will be passed in. */
4958 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
4961 int nwords
= ROUND_ADVANCE (size
), i
;
4964 /* See comment in previous function for empty structures. */
4966 return gen_rtx_REG (mode
, regno
);
4968 if (slotno
== SPARC_INT_ARG_MAX
- 1)
4971 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
4973 for (i
= 0; i
< nwords
; i
++)
4975 /* Unions are passed left-justified. */
4976 XVECEXP (regs
, 0, i
)
4977 = gen_rtx_EXPR_LIST (VOIDmode
,
4978 gen_rtx_REG (word_mode
, regno
),
4979 GEN_INT (UNITS_PER_WORD
* i
));
4986 /* Used by function_arg and function_value to implement the conventions
4987 for passing and returning large (BLKmode) vectors.
4988 Return an expression valid as a return value for the two macros
4989 FUNCTION_ARG and FUNCTION_VALUE.
4991 SIZE is the size in bytes of the vector.
4992 BASE_MODE is the argument's base machine mode.
4993 REGNO is the FP hard register the vector will be passed in. */
4996 function_arg_vector_value (int size
, enum machine_mode base_mode
, int regno
)
4998 unsigned short base_mode_size
= GET_MODE_SIZE (base_mode
);
4999 int nregs
= size
/ base_mode_size
, i
;
5002 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
5004 for (i
= 0; i
< nregs
; i
++)
5006 XVECEXP (regs
, 0, i
)
5007 = gen_rtx_EXPR_LIST (VOIDmode
,
5008 gen_rtx_REG (base_mode
, regno
),
5009 GEN_INT (base_mode_size
* i
));
5010 regno
+= base_mode_size
/ 4;
5016 /* Handle the FUNCTION_ARG macro.
5017 Determine where to put an argument to a function.
5018 Value is zero to push the argument on the stack,
5019 or a hard register in which to store the argument.
5021 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5022 the preceding args and about the function being called.
5023 MODE is the argument's machine mode.
5024 TYPE is the data type of the argument (as a tree).
5025 This is null for libcalls where that information may
5027 NAMED is nonzero if this argument is a named parameter
5028 (otherwise it is an extra parameter matching an ellipsis).
5029 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5032 function_arg (const struct sparc_args
*cum
, enum machine_mode mode
,
5033 tree type
, int named
, int incoming_p
)
5035 int regbase
= (incoming_p
5036 ? SPARC_INCOMING_INT_ARG_FIRST
5037 : SPARC_OUTGOING_INT_ARG_FIRST
);
5038 int slotno
, regno
, padding
;
5039 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5042 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
5050 reg
= gen_rtx_REG (mode
, regno
);
5054 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
5056 /* Structures up to 16 bytes in size are passed in arg slots on the
5057 stack and are promoted to registers where possible. */
5059 gcc_assert (int_size_in_bytes (type
) <= 16);
5061 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
5063 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
5065 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5067 gcc_assert (size
<= 16);
5069 return function_arg_union_value (size
, mode
, slotno
, regno
);
5071 else if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5073 /* Vector types deserve special treatment because they are
5074 polymorphic wrt their mode, depending upon whether VIS
5075 instructions are enabled. */
5076 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5078 gcc_assert (size
<= 16);
5080 if (mode
== BLKmode
)
5081 return function_arg_vector_value (size
,
5082 TYPE_MODE (TREE_TYPE (type
)),
5083 SPARC_FP_ARG_FIRST
+ 2*slotno
);
5085 mclass
= MODE_FLOAT
;
5088 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5089 but also have the slot allocated for them.
5090 If no prototype is in scope fp values in register slots get passed
5091 in two places, either fp regs and int regs or fp regs and memory. */
5092 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5093 && SPARC_FP_REG_P (regno
))
5095 reg
= gen_rtx_REG (mode
, regno
);
5096 if (cum
->prototype_p
|| cum
->libcall_p
)
5098 /* "* 2" because fp reg numbers are recorded in 4 byte
5101 /* ??? This will cause the value to be passed in the fp reg and
5102 in the stack. When a prototype exists we want to pass the
5103 value in the reg but reserve space on the stack. That's an
5104 optimization, and is deferred [for a bit]. */
5105 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
5106 return gen_rtx_PARALLEL (mode
,
5108 gen_rtx_EXPR_LIST (VOIDmode
,
5109 NULL_RTX
, const0_rtx
),
5110 gen_rtx_EXPR_LIST (VOIDmode
,
5114 /* ??? It seems that passing back a register even when past
5115 the area declared by REG_PARM_STACK_SPACE will allocate
5116 space appropriately, and will not copy the data onto the
5117 stack, exactly as we desire.
5119 This is due to locate_and_pad_parm being called in
5120 expand_call whenever reg_parm_stack_space > 0, which
5121 while beneficial to our example here, would seem to be
5122 in error from what had been intended. Ho hum... -- r~ */
5130 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
5134 /* On incoming, we don't need to know that the value
5135 is passed in %f0 and %i0, and it confuses other parts
5136 causing needless spillage even on the simplest cases. */
5140 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
5141 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
5143 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
5144 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
5146 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
5150 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5151 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
5152 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
5158 /* Scalar or complex int. */
5159 reg
= gen_rtx_REG (mode
, regno
);
5165 /* For an arg passed partly in registers and partly in memory,
5166 this is the number of bytes of registers used.
5167 For args passed entirely in registers or entirely in memory, zero.
5169 Any arg that starts in the first 6 regs but won't entirely fit in them
5170 needs partial registers on v8. On v9, structures with integer
5171 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5172 values that begin in the last fp reg [where "last fp reg" varies with the
5173 mode] will be split between that reg and memory. */
5176 sparc_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5177 tree type
, bool named
)
5179 int slotno
, regno
, padding
;
5181 /* We pass 0 for incoming_p here, it doesn't matter. */
5182 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5189 if ((slotno
+ (mode
== BLKmode
5190 ? ROUND_ADVANCE (int_size_in_bytes (type
))
5191 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
5192 > SPARC_INT_ARG_MAX
)
5193 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
5197 /* We are guaranteed by pass_by_reference that the size of the
5198 argument is not greater than 16 bytes, so we only need to return
5199 one word if the argument is partially passed in registers. */
5201 if (type
&& AGGREGATE_TYPE_P (type
))
5203 int size
= int_size_in_bytes (type
);
5205 if (size
> UNITS_PER_WORD
5206 && slotno
== SPARC_INT_ARG_MAX
- 1)
5207 return UNITS_PER_WORD
;
5209 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
5210 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5211 && ! (TARGET_FPU
&& named
)))
5213 /* The complex types are passed as packed types. */
5214 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
5215 && slotno
== SPARC_INT_ARG_MAX
- 1)
5216 return UNITS_PER_WORD
;
5218 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5220 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
5222 return UNITS_PER_WORD
;
5229 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
5230 Specify whether to pass the argument by reference. */
5233 sparc_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5234 enum machine_mode mode
, tree type
,
5235 bool named ATTRIBUTE_UNUSED
)
5239 /* Original SPARC 32-bit ABI says that structures and unions,
5240 and quad-precision floats are passed by reference. For Pascal,
5241 also pass arrays by reference. All other base types are passed
5244 Extended ABI (as implemented by the Sun compiler) says that all
5245 complex floats are passed by reference. Pass complex integers
5246 in registers up to 8 bytes. More generally, enforce the 2-word
5247 cap for passing arguments in registers.
5249 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5250 integers are passed like floats of the same size, that is in
5251 registers up to 8 bytes. Pass all vector floats by reference
5252 like structure and unions. */
5253 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
5255 /* Catch CDImode, TFmode, DCmode and TCmode. */
5256 || GET_MODE_SIZE (mode
) > 8
5258 && TREE_CODE (type
) == VECTOR_TYPE
5259 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
5263 /* Original SPARC 64-bit ABI says that structures and unions
5264 smaller than 16 bytes are passed in registers, as well as
5265 all other base types. For Pascal, pass arrays by reference.
5267 Extended ABI (as implemented by the Sun compiler) says that
5268 complex floats are passed in registers up to 16 bytes. Pass
5269 all complex integers in registers up to 16 bytes. More generally,
5270 enforce the 2-word cap for passing arguments in registers.
5272 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5273 integers are passed like floats of the same size, that is in
5274 registers (up to 16 bytes). Pass all vector floats like structure
5276 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
5278 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
5279 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
5280 /* Catch CTImode and TCmode. */
5281 || GET_MODE_SIZE (mode
) > 16);
5285 /* Handle the FUNCTION_ARG_ADVANCE macro.
5286 Update the data in CUM to advance over an argument
5287 of mode MODE and data type TYPE.
5288 TYPE is null for libcalls where that information may not be available. */
5291 function_arg_advance (struct sparc_args
*cum
, enum machine_mode mode
,
5292 tree type
, int named
)
5294 int slotno
, regno
, padding
;
5296 /* We pass 0 for incoming_p here, it doesn't matter. */
5297 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5299 /* If register required leading padding, add it. */
5301 cum
->words
+= padding
;
5305 cum
->words
+= (mode
!= BLKmode
5306 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5307 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5311 if (type
&& AGGREGATE_TYPE_P (type
))
5313 int size
= int_size_in_bytes (type
);
5317 else if (size
<= 16)
5319 else /* passed by reference */
5324 cum
->words
+= (mode
!= BLKmode
5325 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5326 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5331 /* Handle the FUNCTION_ARG_PADDING macro.
5332 For the 64 bit ABI structs are always stored left shifted in their
5336 function_arg_padding (enum machine_mode mode
, tree type
)
5338 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
5341 /* Fall back to the default. */
5342 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
5345 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5346 Specify whether to return the return value in memory. */
5349 sparc_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
5352 /* Original SPARC 32-bit ABI says that structures and unions,
5353 and quad-precision floats are returned in memory. All other
5354 base types are returned in registers.
5356 Extended ABI (as implemented by the Sun compiler) says that
5357 all complex floats are returned in registers (8 FP registers
5358 at most for '_Complex long double'). Return all complex integers
5359 in registers (4 at most for '_Complex long long').
5361 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5362 integers are returned like floats of the same size, that is in
5363 registers up to 8 bytes and in memory otherwise. Return all
5364 vector floats in memory like structure and unions; note that
5365 they always have BLKmode like the latter. */
5366 return (TYPE_MODE (type
) == BLKmode
5367 || TYPE_MODE (type
) == TFmode
5368 || (TREE_CODE (type
) == VECTOR_TYPE
5369 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
5371 /* Original SPARC 64-bit ABI says that structures and unions
5372 smaller than 32 bytes are returned in registers, as well as
5373 all other base types.
5375 Extended ABI (as implemented by the Sun compiler) says that all
5376 complex floats are returned in registers (8 FP registers at most
5377 for '_Complex long double'). Return all complex integers in
5378 registers (4 at most for '_Complex TItype').
5380 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5381 integers are returned like floats of the same size, that is in
5382 registers. Return all vector floats like structure and unions;
5383 note that they always have BLKmode like the latter. */
5384 return ((TYPE_MODE (type
) == BLKmode
5385 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32));
5388 /* Handle the TARGET_STRUCT_VALUE target hook.
5389 Return where to find the structure return value address. */
5392 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED
, int incoming
)
5401 mem
= gen_rtx_MEM (Pmode
, plus_constant (frame_pointer_rtx
,
5402 STRUCT_VALUE_OFFSET
));
5404 mem
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
,
5405 STRUCT_VALUE_OFFSET
));
5407 set_mem_alias_set (mem
, struct_value_alias_set
);
5412 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5413 For v9, function return values are subject to the same rules as arguments,
5414 except that up to 32 bytes may be returned in registers. */
5417 function_value (tree type
, enum machine_mode mode
, int incoming_p
)
5419 /* Beware that the two values are swapped here wrt function_arg. */
5420 int regbase
= (incoming_p
5421 ? SPARC_OUTGOING_INT_ARG_FIRST
5422 : SPARC_INCOMING_INT_ARG_FIRST
);
5423 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5426 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5428 /* Vector types deserve special treatment because they are
5429 polymorphic wrt their mode, depending upon whether VIS
5430 instructions are enabled. */
5431 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5433 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
5434 || (TARGET_ARCH64
&& size
<= 32));
5436 if (mode
== BLKmode
)
5437 return function_arg_vector_value (size
,
5438 TYPE_MODE (TREE_TYPE (type
)),
5439 SPARC_FP_ARG_FIRST
);
5441 mclass
= MODE_FLOAT
;
5443 else if (type
&& TARGET_ARCH64
)
5445 if (TREE_CODE (type
) == RECORD_TYPE
)
5447 /* Structures up to 32 bytes in size are passed in registers,
5448 promoted to fp registers where possible. */
5450 gcc_assert (int_size_in_bytes (type
) <= 32);
5452 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
5454 else if (TREE_CODE (type
) == UNION_TYPE
)
5456 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5458 gcc_assert (size
<= 32);
5460 return function_arg_union_value (size
, mode
, 0, regbase
);
5462 else if (AGGREGATE_TYPE_P (type
))
5464 /* All other aggregate types are passed in an integer register
5465 in a mode corresponding to the size of the type. */
5466 HOST_WIDE_INT bytes
= int_size_in_bytes (type
);
5468 gcc_assert (bytes
<= 32);
5470 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
5472 /* ??? We probably should have made the same ABI change in
5473 3.4.0 as the one we made for unions. The latter was
5474 required by the SCD though, while the former is not
5475 specified, so we favored compatibility and efficiency.
5477 Now we're stuck for aggregates larger than 16 bytes,
5478 because OImode vanished in the meantime. Let's not
5479 try to be unduly clever, and simply follow the ABI
5480 for unions in that case. */
5481 if (mode
== BLKmode
)
5482 return function_arg_union_value (bytes
, mode
, 0, regbase
);
5486 else if (mclass
== MODE_INT
5487 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5491 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5493 regno
= SPARC_FP_ARG_FIRST
;
5497 return gen_rtx_REG (mode
, regno
);
5500 /* Do what is necessary for `va_start'. We look at the current function
5501 to determine if stdarg or varargs is used and return the address of
5502 the first unnamed parameter. */
5505 sparc_builtin_saveregs (void)
5507 int first_reg
= current_function_args_info
.words
;
5511 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
5512 emit_move_insn (gen_rtx_MEM (word_mode
,
5513 gen_rtx_PLUS (Pmode
,
5515 GEN_INT (FIRST_PARM_OFFSET (0)
5518 gen_rtx_REG (word_mode
,
5519 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
5521 address
= gen_rtx_PLUS (Pmode
,
5523 GEN_INT (FIRST_PARM_OFFSET (0)
5524 + UNITS_PER_WORD
* first_reg
));
5529 /* Implement `va_start' for stdarg. */
5532 sparc_va_start (tree valist
, rtx nextarg
)
5534 nextarg
= expand_builtin_saveregs ();
5535 std_expand_builtin_va_start (valist
, nextarg
);
5538 /* Implement `va_arg' for stdarg. */
5541 sparc_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
5543 HOST_WIDE_INT size
, rsize
, align
;
5546 tree ptrtype
= build_pointer_type (type
);
5548 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
5551 size
= rsize
= UNITS_PER_WORD
;
5557 size
= int_size_in_bytes (type
);
5558 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5563 /* For SPARC64, objects requiring 16-byte alignment get it. */
5564 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
5565 align
= 2 * UNITS_PER_WORD
;
5567 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5568 are left-justified in their slots. */
5569 if (AGGREGATE_TYPE_P (type
))
5572 size
= rsize
= UNITS_PER_WORD
;
5582 incr
= fold (build2 (PLUS_EXPR
, ptr_type_node
, incr
,
5583 ssize_int (align
- 1)));
5584 incr
= fold (build2 (BIT_AND_EXPR
, ptr_type_node
, incr
,
5585 ssize_int (-align
)));
5588 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
5591 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
5592 addr
= fold (build2 (PLUS_EXPR
, ptr_type_node
, incr
,
5593 ssize_int (rsize
- size
)));
5597 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
5598 addr
= build_va_arg_indirect_ref (addr
);
5600 /* If the address isn't aligned properly for the type,
5601 we may need to copy to a temporary.
5602 FIXME: This is inefficient. Usually we can do this
5605 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
5607 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
5608 tree dest_addr
= build_fold_addr_expr (tmp
);
5610 tree copy
= build_function_call_expr
5611 (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
5612 tree_cons (NULL_TREE
, dest_addr
,
5613 tree_cons (NULL_TREE
, addr
,
5614 tree_cons (NULL_TREE
, size_int (rsize
),
5617 gimplify_and_add (copy
, pre_p
);
5621 addr
= fold_convert (ptrtype
, addr
);
5623 incr
= fold (build2 (PLUS_EXPR
, ptr_type_node
, incr
, ssize_int (rsize
)));
5624 incr
= build2 (MODIFY_EXPR
, ptr_type_node
, valist
, incr
);
5625 gimplify_and_add (incr
, post_p
);
5627 return build_va_arg_indirect_ref (addr
);
5630 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
5631 Specify whether the vector mode is supported by the hardware. */
5634 sparc_vector_mode_supported_p (enum machine_mode mode
)
5636 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
5639 /* Return the string to output an unconditional branch to LABEL, which is
5640 the operand number of the label.
5642 DEST is the destination insn (i.e. the label), INSN is the source. */
5645 output_ubranch (rtx dest
, int label
, rtx insn
)
5647 static char string
[64];
5648 bool v9_form
= false;
5651 if (TARGET_V9
&& INSN_ADDRESSES_SET_P ())
5653 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5654 - INSN_ADDRESSES (INSN_UID (insn
)));
5655 /* Leave some instructions for "slop". */
5656 if (delta
>= -260000 && delta
< 260000)
5661 strcpy (string
, "ba%*,pt\t%%xcc, ");
5663 strcpy (string
, "b%*\t");
5665 p
= strchr (string
, '\0');
5676 /* Return the string to output a conditional branch to LABEL, which is
5677 the operand number of the label. OP is the conditional expression.
5678 XEXP (OP, 0) is assumed to be a condition code register (integer or
5679 floating point) and its mode specifies what kind of comparison we made.
5681 DEST is the destination insn (i.e. the label), INSN is the source.
5683 REVERSED is nonzero if we should reverse the sense of the comparison.
5685 ANNUL is nonzero if we should generate an annulling branch. */
5688 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
5691 static char string
[64];
5692 enum rtx_code code
= GET_CODE (op
);
5693 rtx cc_reg
= XEXP (op
, 0);
5694 enum machine_mode mode
= GET_MODE (cc_reg
);
5695 const char *labelno
, *branch
;
5696 int spaces
= 8, far
;
5699 /* v9 branches are limited to +-1MB. If it is too far away,
5712 fbne,a,pn %fcc2, .LC29
5720 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
5723 /* Reversal of FP compares takes care -- an ordered compare
5724 becomes an unordered compare and vice versa. */
5725 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5726 code
= reverse_condition_maybe_unordered (code
);
5728 code
= reverse_condition (code
);
5731 /* Start by writing the branch condition. */
5732 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5783 /* ??? !v9: FP branches cannot be preceded by another floating point
5784 insn. Because there is currently no concept of pre-delay slots,
5785 we can fix this only by always emitting a nop before a floating
5790 strcpy (string
, "nop\n\t");
5791 strcat (string
, branch
);
5804 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5816 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5837 strcpy (string
, branch
);
5839 spaces
-= strlen (branch
);
5840 p
= strchr (string
, '\0');
5842 /* Now add the annulling, the label, and a possible noop. */
5855 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
5857 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5858 - INSN_ADDRESSES (INSN_UID (insn
)));
5859 /* Leave some instructions for "slop". */
5860 if (delta
< -260000 || delta
>= 260000)
5864 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5866 static char v9_fcc_labelno
[] = "%%fccX, ";
5867 /* Set the char indicating the number of the fcc reg to use. */
5868 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
5869 labelno
= v9_fcc_labelno
;
5872 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
5876 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
5878 labelno
= "%%xcc, ";
5883 labelno
= "%%icc, ";
5888 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
5891 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
5904 strcpy (p
, labelno
);
5905 p
= strchr (p
, '\0');
5908 strcpy (p
, ".+12\n\t nop\n\tb\t");
5909 /* Skip the next insn if requested or
5910 if we know that it will be a nop. */
5911 if (annul
|| ! final_sequence
)
5925 /* Emit a library call comparison between floating point X and Y.
5926 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5927 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5928 values as arguments instead of the TFmode registers themselves,
5929 that's why we cannot call emit_float_lib_cmp. */
5931 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
5934 rtx slot0
, slot1
, result
, tem
, tem2
;
5935 enum machine_mode mode
;
5940 qpfunc
= (TARGET_ARCH64
) ? "_Qp_feq" : "_Q_feq";
5944 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fne" : "_Q_fne";
5948 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fgt" : "_Q_fgt";
5952 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fge" : "_Q_fge";
5956 qpfunc
= (TARGET_ARCH64
) ? "_Qp_flt" : "_Q_flt";
5960 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fle" : "_Q_fle";
5971 qpfunc
= (TARGET_ARCH64
) ? "_Qp_cmp" : "_Q_cmp";
5980 if (GET_CODE (x
) != MEM
)
5982 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5983 emit_move_insn (slot0
, x
);
5988 if (GET_CODE (y
) != MEM
)
5990 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5991 emit_move_insn (slot1
, y
);
5996 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
5998 XEXP (slot0
, 0), Pmode
,
5999 XEXP (slot1
, 0), Pmode
);
6005 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
6007 x
, TFmode
, y
, TFmode
);
6013 /* Immediately move the result of the libcall into a pseudo
6014 register so reload doesn't clobber the value if it needs
6015 the return register for a spill reg. */
6016 result
= gen_reg_rtx (mode
);
6017 emit_move_insn (result
, hard_libcall_value (mode
));
6022 emit_cmp_insn (result
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
6026 emit_cmp_insn (result
, GEN_INT(3), comparison
== UNORDERED
? EQ
: NE
,
6031 emit_cmp_insn (result
, const1_rtx
,
6032 comparison
== UNGT
? GT
: NE
, NULL_RTX
, mode
, 0);
6035 emit_cmp_insn (result
, const2_rtx
, NE
, NULL_RTX
, mode
, 0);
6038 tem
= gen_reg_rtx (mode
);
6040 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
6042 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
6043 emit_cmp_insn (tem
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
6047 tem
= gen_reg_rtx (mode
);
6049 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
6051 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
6052 tem2
= gen_reg_rtx (mode
);
6054 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
6056 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
6057 emit_cmp_insn (tem2
, const0_rtx
, comparison
== UNEQ
? EQ
: NE
,
6063 /* Generate an unsigned DImode to FP conversion. This is the same code
6064 optabs would emit if we didn't have TFmode patterns. */
6067 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
6069 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
6072 in
= force_reg (DImode
, operands
[1]);
6073 neglab
= gen_label_rtx ();
6074 donelab
= gen_label_rtx ();
6075 i0
= gen_reg_rtx (DImode
);
6076 i1
= gen_reg_rtx (DImode
);
6077 f0
= gen_reg_rtx (mode
);
6079 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
6081 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
6082 emit_jump_insn (gen_jump (donelab
));
6085 emit_label (neglab
);
6087 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
6088 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
6089 emit_insn (gen_iordi3 (i0
, i0
, i1
));
6090 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
6091 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
6093 emit_label (donelab
);
6096 /* Generate an FP to unsigned DImode conversion. This is the same code
6097 optabs would emit if we didn't have TFmode patterns. */
6100 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
6102 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
6105 in
= force_reg (mode
, operands
[1]);
6106 neglab
= gen_label_rtx ();
6107 donelab
= gen_label_rtx ();
6108 i0
= gen_reg_rtx (DImode
);
6109 i1
= gen_reg_rtx (DImode
);
6110 limit
= gen_reg_rtx (mode
);
6111 f0
= gen_reg_rtx (mode
);
6113 emit_move_insn (limit
,
6114 CONST_DOUBLE_FROM_REAL_VALUE (
6115 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
6116 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
6118 emit_insn (gen_rtx_SET (VOIDmode
,
6120 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
6121 emit_jump_insn (gen_jump (donelab
));
6124 emit_label (neglab
);
6126 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
6127 emit_insn (gen_rtx_SET (VOIDmode
,
6129 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
6130 emit_insn (gen_movdi (i1
, const1_rtx
));
6131 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
6132 emit_insn (gen_xordi3 (out
, i0
, i1
));
6134 emit_label (donelab
);
6137 /* Return the string to output a conditional branch to LABEL, testing
6138 register REG. LABEL is the operand number of the label; REG is the
6139 operand number of the reg. OP is the conditional expression. The mode
6140 of REG says what kind of comparison we made.
6142 DEST is the destination insn (i.e. the label), INSN is the source.
6144 REVERSED is nonzero if we should reverse the sense of the comparison.
6146 ANNUL is nonzero if we should generate an annulling branch. */
6149 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
6150 int annul
, rtx insn
)
6152 static char string
[64];
6153 enum rtx_code code
= GET_CODE (op
);
6154 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
6159 /* branch on register are limited to +-128KB. If it is too far away,
6172 brgez,a,pn %o1, .LC29
6178 ba,pt %xcc, .LC29 */
6180 far
= get_attr_length (insn
) >= 3;
6182 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6184 code
= reverse_condition (code
);
6186 /* Only 64 bit versions of these instructions exist. */
6187 gcc_assert (mode
== DImode
);
6189 /* Start by writing the branch condition. */
6194 strcpy (string
, "brnz");
6198 strcpy (string
, "brz");
6202 strcpy (string
, "brgez");
6206 strcpy (string
, "brlz");
6210 strcpy (string
, "brlez");
6214 strcpy (string
, "brgz");
6221 p
= strchr (string
, '\0');
6223 /* Now add the annulling, reg, label, and nop. */
6230 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
6233 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
6238 *p
= p
< string
+ 8 ? '\t' : ' ';
6246 int veryfar
= 1, delta
;
6248 if (INSN_ADDRESSES_SET_P ())
6250 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6251 - INSN_ADDRESSES (INSN_UID (insn
)));
6252 /* Leave some instructions for "slop". */
6253 if (delta
>= -260000 && delta
< 260000)
6257 strcpy (p
, ".+12\n\t nop\n\t");
6258 /* Skip the next insn if requested or
6259 if we know that it will be a nop. */
6260 if (annul
|| ! final_sequence
)
6270 strcpy (p
, "ba,pt\t%%xcc, ");
6284 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6285 Such instructions cannot be used in the delay slot of return insn on v9.
6286 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6290 epilogue_renumber (register rtx
*where
, int test
)
6292 register const char *fmt
;
6294 register enum rtx_code code
;
6299 code
= GET_CODE (*where
);
6304 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
6306 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
6307 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
6315 /* Do not replace the frame pointer with the stack pointer because
6316 it can cause the delayed instruction to load below the stack.
6317 This occurs when instructions like:
6319 (set (reg/i:SI 24 %i0)
6320 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6321 (const_int -20 [0xffffffec])) 0))
6323 are in the return delayed slot. */
6325 if (GET_CODE (XEXP (*where
, 0)) == REG
6326 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
6327 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
6328 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
6333 if (SPARC_STACK_BIAS
6334 && GET_CODE (XEXP (*where
, 0)) == REG
6335 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
6343 fmt
= GET_RTX_FORMAT (code
);
6345 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6350 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
6351 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
6354 else if (fmt
[i
] == 'e'
6355 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
6361 /* Leaf functions and non-leaf functions have different needs. */
6364 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
6367 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
6369 static const int *const reg_alloc_orders
[] = {
6370 reg_leaf_alloc_order
,
6371 reg_nonleaf_alloc_order
};
6374 order_regs_for_local_alloc (void)
6376 static int last_order_nonleaf
= 1;
6378 if (regs_ever_live
[15] != last_order_nonleaf
)
6380 last_order_nonleaf
= !last_order_nonleaf
;
6381 memcpy ((char *) reg_alloc_order
,
6382 (const char *) reg_alloc_orders
[last_order_nonleaf
],
6383 FIRST_PSEUDO_REGISTER
* sizeof (int));
6387 /* Return 1 if REG and MEM are legitimate enough to allow the various
6388 mem<-->reg splits to be run. */
6391 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
6393 /* Punt if we are here by mistake. */
6394 gcc_assert (reload_completed
);
6396 /* We must have an offsettable memory reference. */
6397 if (! offsettable_memref_p (mem
))
6400 /* If we have legitimate args for ldd/std, we do not want
6401 the split to happen. */
6402 if ((REGNO (reg
) % 2) == 0
6403 && mem_min_alignment (mem
, 8))
6410 /* Return 1 if x and y are some kind of REG and they refer to
6411 different hard registers. This test is guaranteed to be
6412 run after reload. */
6415 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
6417 if (GET_CODE (x
) != REG
)
6419 if (GET_CODE (y
) != REG
)
6421 if (REGNO (x
) == REGNO (y
))
6426 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6427 This makes them candidates for using ldd and std insns.
6429 Note reg1 and reg2 *must* be hard registers. */
6432 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
6434 /* We might have been passed a SUBREG. */
6435 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
6438 if (REGNO (reg1
) % 2 != 0)
6441 /* Integer ldd is deprecated in SPARC V9 */
6442 if (TARGET_V9
&& REGNO (reg1
) < 32)
6445 return (REGNO (reg1
) == REGNO (reg2
) - 1);
6448 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6451 This can only happen when addr1 and addr2, the addresses in mem1
6452 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6453 addr1 must also be aligned on a 64-bit boundary.
6455 Also iff dependent_reg_rtx is not null it should not be used to
6456 compute the address for mem1, i.e. we cannot optimize a sequence
6468 But, note that the transformation from:
6473 is perfectly fine. Thus, the peephole2 patterns always pass us
6474 the destination register of the first load, never the second one.
6476 For stores we don't have a similar problem, so dependent_reg_rtx is
6480 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
6484 HOST_WIDE_INT offset1
;
6486 /* The mems cannot be volatile. */
6487 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
6490 /* MEM1 should be aligned on a 64-bit boundary. */
6491 if (MEM_ALIGN (mem1
) < 64)
6494 addr1
= XEXP (mem1
, 0);
6495 addr2
= XEXP (mem2
, 0);
6497 /* Extract a register number and offset (if used) from the first addr. */
6498 if (GET_CODE (addr1
) == PLUS
)
6500 /* If not a REG, return zero. */
6501 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
6505 reg1
= REGNO (XEXP (addr1
, 0));
6506 /* The offset must be constant! */
6507 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
6509 offset1
= INTVAL (XEXP (addr1
, 1));
6512 else if (GET_CODE (addr1
) != REG
)
6516 reg1
= REGNO (addr1
);
6517 /* This was a simple (mem (reg)) expression. Offset is 0. */
6521 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6522 if (GET_CODE (addr2
) != PLUS
)
6525 if (GET_CODE (XEXP (addr2
, 0)) != REG
6526 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
6529 if (reg1
!= REGNO (XEXP (addr2
, 0)))
6532 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
6535 /* The first offset must be evenly divisible by 8 to ensure the
6536 address is 64 bit aligned. */
6537 if (offset1
% 8 != 0)
6540 /* The offset for the second addr must be 4 more than the first addr. */
6541 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
6544 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6549 /* Return 1 if reg is a pseudo, or is the first register in
6550 a hard register pair. This makes it a candidate for use in
6551 ldd and std insns. */
6554 register_ok_for_ldd (rtx reg
)
6556 /* We might have been passed a SUBREG. */
6557 if (GET_CODE (reg
) != REG
)
6560 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
6561 return (REGNO (reg
) % 2 == 0);
6566 /* Print operand X (an rtx) in assembler syntax to file FILE.
6567 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6568 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6571 print_operand (FILE *file
, rtx x
, int code
)
6576 /* Output an insn in a delay slot. */
6578 sparc_indent_opcode
= 1;
6580 fputs ("\n\t nop", file
);
6583 /* Output an annul flag if there's nothing for the delay slot and we
6584 are optimizing. This is always used with '(' below.
6585 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6586 this is a dbx bug. So, we only do this when optimizing.
6587 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6588 Always emit a nop in case the next instruction is a branch. */
6589 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6593 /* Output a 'nop' if there's nothing for the delay slot and we are
6594 not optimizing. This is always used with '*' above. */
6595 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6596 fputs ("\n\t nop", file
);
6597 else if (final_sequence
)
6598 sparc_indent_opcode
= 1;
6601 /* Output the right displacement from the saved PC on function return.
6602 The caller may have placed an "unimp" insn immediately after the call
6603 so we have to account for it. This insn is used in the 32-bit ABI
6604 when calling a function that returns a non zero-sized structure. The
6605 64-bit ABI doesn't have it. Be careful to have this test be the same
6606 as that used on the call. */
6608 && current_function_returns_struct
6609 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
6611 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
6617 /* Output the Embedded Medium/Anywhere code model base register. */
6618 fputs (EMBMEDANY_BASE_REG
, file
);
6621 /* Print some local dynamic TLS name. */
6622 assemble_name (file
, get_some_local_dynamic_name ());
6626 /* Adjust the operand to take into account a RESTORE operation. */
6627 if (GET_CODE (x
) == CONST_INT
)
6629 else if (GET_CODE (x
) != REG
)
6630 output_operand_lossage ("invalid %%Y operand");
6631 else if (REGNO (x
) < 8)
6632 fputs (reg_names
[REGNO (x
)], file
);
6633 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
6634 fputs (reg_names
[REGNO (x
)-16], file
);
6636 output_operand_lossage ("invalid %%Y operand");
6639 /* Print out the low order register name of a register pair. */
6640 if (WORDS_BIG_ENDIAN
)
6641 fputs (reg_names
[REGNO (x
)+1], file
);
6643 fputs (reg_names
[REGNO (x
)], file
);
6646 /* Print out the high order register name of a register pair. */
6647 if (WORDS_BIG_ENDIAN
)
6648 fputs (reg_names
[REGNO (x
)], file
);
6650 fputs (reg_names
[REGNO (x
)+1], file
);
6653 /* Print out the second register name of a register pair or quad.
6654 I.e., R (%o0) => %o1. */
6655 fputs (reg_names
[REGNO (x
)+1], file
);
6658 /* Print out the third register name of a register quad.
6659 I.e., S (%o0) => %o2. */
6660 fputs (reg_names
[REGNO (x
)+2], file
);
6663 /* Print out the fourth register name of a register quad.
6664 I.e., T (%o0) => %o3. */
6665 fputs (reg_names
[REGNO (x
)+3], file
);
6668 /* Print a condition code register. */
6669 if (REGNO (x
) == SPARC_ICC_REG
)
6671 /* We don't handle CC[X]_NOOVmode because they're not supposed
6673 if (GET_MODE (x
) == CCmode
)
6674 fputs ("%icc", file
);
6675 else if (GET_MODE (x
) == CCXmode
)
6676 fputs ("%xcc", file
);
6681 /* %fccN register */
6682 fputs (reg_names
[REGNO (x
)], file
);
6685 /* Print the operand's address only. */
6686 output_address (XEXP (x
, 0));
6689 /* In this case we need a register. Use %g0 if the
6690 operand is const0_rtx. */
6692 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
6694 fputs ("%g0", file
);
6701 switch (GET_CODE (x
))
6703 case IOR
: fputs ("or", file
); break;
6704 case AND
: fputs ("and", file
); break;
6705 case XOR
: fputs ("xor", file
); break;
6706 default: output_operand_lossage ("invalid %%A operand");
6711 switch (GET_CODE (x
))
6713 case IOR
: fputs ("orn", file
); break;
6714 case AND
: fputs ("andn", file
); break;
6715 case XOR
: fputs ("xnor", file
); break;
6716 default: output_operand_lossage ("invalid %%B operand");
6720 /* These are used by the conditional move instructions. */
6724 enum rtx_code rc
= GET_CODE (x
);
6728 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
6729 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6730 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
6732 rc
= reverse_condition (GET_CODE (x
));
6736 case NE
: fputs ("ne", file
); break;
6737 case EQ
: fputs ("e", file
); break;
6738 case GE
: fputs ("ge", file
); break;
6739 case GT
: fputs ("g", file
); break;
6740 case LE
: fputs ("le", file
); break;
6741 case LT
: fputs ("l", file
); break;
6742 case GEU
: fputs ("geu", file
); break;
6743 case GTU
: fputs ("gu", file
); break;
6744 case LEU
: fputs ("leu", file
); break;
6745 case LTU
: fputs ("lu", file
); break;
6746 case LTGT
: fputs ("lg", file
); break;
6747 case UNORDERED
: fputs ("u", file
); break;
6748 case ORDERED
: fputs ("o", file
); break;
6749 case UNLT
: fputs ("ul", file
); break;
6750 case UNLE
: fputs ("ule", file
); break;
6751 case UNGT
: fputs ("ug", file
); break;
6752 case UNGE
: fputs ("uge", file
); break;
6753 case UNEQ
: fputs ("ue", file
); break;
6754 default: output_operand_lossage (code
== 'c'
6755 ? "invalid %%c operand"
6756 : "invalid %%C operand");
6761 /* These are used by the movr instruction pattern. */
6765 enum rtx_code rc
= (code
== 'd'
6766 ? reverse_condition (GET_CODE (x
))
6770 case NE
: fputs ("ne", file
); break;
6771 case EQ
: fputs ("e", file
); break;
6772 case GE
: fputs ("gez", file
); break;
6773 case LT
: fputs ("lz", file
); break;
6774 case LE
: fputs ("lez", file
); break;
6775 case GT
: fputs ("gz", file
); break;
6776 default: output_operand_lossage (code
== 'd'
6777 ? "invalid %%d operand"
6778 : "invalid %%D operand");
6785 /* Print a sign-extended character. */
6786 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
6787 fprintf (file
, "%d", i
);
6792 /* Operand must be a MEM; write its address. */
6793 if (GET_CODE (x
) != MEM
)
6794 output_operand_lossage ("invalid %%f operand");
6795 output_address (XEXP (x
, 0));
6800 /* Print a sign-extended 32-bit value. */
6802 if (GET_CODE(x
) == CONST_INT
)
6804 else if (GET_CODE(x
) == CONST_DOUBLE
)
6805 i
= CONST_DOUBLE_LOW (x
);
6808 output_operand_lossage ("invalid %%s operand");
6811 i
= trunc_int_for_mode (i
, SImode
);
6812 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
6817 /* Do nothing special. */
6821 /* Undocumented flag. */
6822 output_operand_lossage ("invalid operand output code");
6825 if (GET_CODE (x
) == REG
)
6826 fputs (reg_names
[REGNO (x
)], file
);
6827 else if (GET_CODE (x
) == MEM
)
6830 /* Poor Sun assembler doesn't understand absolute addressing. */
6831 if (CONSTANT_P (XEXP (x
, 0)))
6832 fputs ("%g0+", file
);
6833 output_address (XEXP (x
, 0));
6836 else if (GET_CODE (x
) == HIGH
)
6838 fputs ("%hi(", file
);
6839 output_addr_const (file
, XEXP (x
, 0));
6842 else if (GET_CODE (x
) == LO_SUM
)
6844 print_operand (file
, XEXP (x
, 0), 0);
6845 if (TARGET_CM_MEDMID
)
6846 fputs ("+%l44(", file
);
6848 fputs ("+%lo(", file
);
6849 output_addr_const (file
, XEXP (x
, 1));
6852 else if (GET_CODE (x
) == CONST_DOUBLE
6853 && (GET_MODE (x
) == VOIDmode
6854 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
6856 if (CONST_DOUBLE_HIGH (x
) == 0)
6857 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
6858 else if (CONST_DOUBLE_HIGH (x
) == -1
6859 && CONST_DOUBLE_LOW (x
) < 0)
6860 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
6862 output_operand_lossage ("long long constant not a valid immediate operand");
6864 else if (GET_CODE (x
) == CONST_DOUBLE
)
6865 output_operand_lossage ("floating point constant not a valid immediate operand");
6866 else { output_addr_const (file
, x
); }
6869 /* Target hook for assembling integer objects. The sparc version has
6870 special handling for aligned DI-mode objects. */
6873 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
6875 /* ??? We only output .xword's for symbols and only then in environments
6876 where the assembler can handle them. */
6877 if (aligned_p
&& size
== 8
6878 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
6882 assemble_integer_with_op ("\t.xword\t", x
);
6887 assemble_aligned_integer (4, const0_rtx
);
6888 assemble_aligned_integer (4, x
);
6892 return default_assemble_integer (x
, size
, aligned_p
);
6895 /* Return the value of a code used in the .proc pseudo-op that says
6896 what kind of result this function returns. For non-C types, we pick
6897 the closest C type. */
6899 #ifndef SHORT_TYPE_SIZE
6900 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6903 #ifndef INT_TYPE_SIZE
6904 #define INT_TYPE_SIZE BITS_PER_WORD
6907 #ifndef LONG_TYPE_SIZE
6908 #define LONG_TYPE_SIZE BITS_PER_WORD
6911 #ifndef LONG_LONG_TYPE_SIZE
6912 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6915 #ifndef FLOAT_TYPE_SIZE
6916 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6919 #ifndef DOUBLE_TYPE_SIZE
6920 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6923 #ifndef LONG_DOUBLE_TYPE_SIZE
6924 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6928 sparc_type_code (register tree type
)
6930 register unsigned long qualifiers
= 0;
6931 register unsigned shift
;
6933 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6934 setting more, since some assemblers will give an error for this. Also,
6935 we must be careful to avoid shifts of 32 bits or more to avoid getting
6936 unpredictable results. */
6938 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
6940 switch (TREE_CODE (type
))
6946 qualifiers
|= (3 << shift
);
6951 qualifiers
|= (2 << shift
);
6955 case REFERENCE_TYPE
:
6957 qualifiers
|= (1 << shift
);
6961 return (qualifiers
| 8);
6964 case QUAL_UNION_TYPE
:
6965 return (qualifiers
| 9);
6968 return (qualifiers
| 10);
6971 return (qualifiers
| 16);
6974 /* If this is a range type, consider it to be the underlying
6976 if (TREE_TYPE (type
) != 0)
6979 /* Carefully distinguish all the standard types of C,
6980 without messing up if the language is not C. We do this by
6981 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
6982 look at both the names and the above fields, but that's redundant.
6983 Any type whose size is between two C types will be considered
6984 to be the wider of the two types. Also, we do not have a
6985 special code to use for "long long", so anything wider than
6986 long is treated the same. Note that we can't distinguish
6987 between "int" and "long" in this code if they are the same
6988 size, but that's fine, since neither can the assembler. */
6990 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
6991 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
6993 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
6994 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
6996 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
6997 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
7000 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
7003 /* If this is a range type, consider it to be the underlying
7005 if (TREE_TYPE (type
) != 0)
7008 /* Carefully distinguish all the standard types of C,
7009 without messing up if the language is not C. */
7011 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
7012 return (qualifiers
| 6);
7015 return (qualifiers
| 7);
7017 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
7018 /* ??? We need to distinguish between double and float complex types,
7019 but I don't know how yet because I can't reach this code from
7020 existing front-ends. */
7021 return (qualifiers
| 7); /* Who knows? */
7024 case BOOLEAN_TYPE
: /* Boolean truth value type. */
7025 case LANG_TYPE
: /* ? */
7029 gcc_unreachable (); /* Not a type! */
7036 /* Nested function support. */
7038 /* Emit RTL insns to initialize the variable parts of a trampoline.
7039 FNADDR is an RTX for the address of the function's pure code.
7040 CXT is an RTX for the static chain value for the function.
7042 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7043 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7044 (to store insns). This is a bit excessive. Perhaps a different
7045 mechanism would be better here.
7047 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7050 sparc_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
7052 /* SPARC 32-bit trampoline:
7055 sethi %hi(static), %g2
7057 or %g2, %lo(static), %g2
7059 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7060 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7064 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 0)),
7065 expand_binop (SImode
, ior_optab
,
7066 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
7067 size_int (10), 0, 1),
7068 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
7069 NULL_RTX
, 1, OPTAB_DIRECT
));
7072 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
7073 expand_binop (SImode
, ior_optab
,
7074 expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
7075 size_int (10), 0, 1),
7076 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
7077 NULL_RTX
, 1, OPTAB_DIRECT
));
7080 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
7081 expand_binop (SImode
, ior_optab
,
7082 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
7083 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
7084 NULL_RTX
, 1, OPTAB_DIRECT
));
7087 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7088 expand_binop (SImode
, ior_optab
,
7089 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
7090 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
7091 NULL_RTX
, 1, OPTAB_DIRECT
));
7093 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7094 aligned on a 16 byte boundary so one flush clears it all. */
7095 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
, tramp
))));
7096 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
7097 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
7098 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
,
7099 plus_constant (tramp
, 8)))));
7101 /* Call __enable_execute_stack after writing onto the stack to make sure
7102 the stack address is accessible. */
7103 #ifdef ENABLE_EXECUTE_STACK
7104 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
7105 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
7110 /* The 64-bit version is simpler because it makes more sense to load the
7111 values as "immediate" data out of the trampoline. It's also easier since
7112 we can read the PC without clobbering a register. */
7115 sparc64_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
7117 /* SPARC 64-bit trampoline:
7126 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
7127 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
7128 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
7129 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
7130 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
7131 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
7132 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7133 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
7134 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), cxt
);
7135 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)), fnaddr
);
7136 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, tramp
))));
7138 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
7139 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
7140 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)))));
7142 /* Call __enable_execute_stack after writing onto the stack to make sure
7143 the stack address is accessible. */
7144 #ifdef ENABLE_EXECUTE_STACK
7145 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
7146 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
7150 /* Adjust the cost of a scheduling dependency. Return the new cost of
7151 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7154 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
7156 enum attr_type insn_type
;
7158 if (! recog_memoized (insn
))
7161 insn_type
= get_attr_type (insn
);
7163 if (REG_NOTE_KIND (link
) == 0)
7165 /* Data dependency; DEP_INSN writes a register that INSN reads some
7168 /* if a load, then the dependence must be on the memory address;
7169 add an extra "cycle". Note that the cost could be two cycles
7170 if the reg was written late in an instruction group; we ca not tell
7172 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
7175 /* Get the delay only if the address of the store is the dependence. */
7176 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
7178 rtx pat
= PATTERN(insn
);
7179 rtx dep_pat
= PATTERN (dep_insn
);
7181 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7182 return cost
; /* This should not happen! */
7184 /* The dependency between the two instructions was on the data that
7185 is being stored. Assume that this implies that the address of the
7186 store is not dependent. */
7187 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7190 return cost
+ 3; /* An approximation. */
7193 /* A shift instruction cannot receive its data from an instruction
7194 in the same cycle; add a one cycle penalty. */
7195 if (insn_type
== TYPE_SHIFT
)
7196 return cost
+ 3; /* Split before cascade into shift. */
7200 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7201 INSN writes some cycles later. */
7203 /* These are only significant for the fpu unit; writing a fp reg before
7204 the fpu has finished with it stalls the processor. */
7206 /* Reusing an integer register causes no problems. */
7207 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7215 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
7217 enum attr_type insn_type
, dep_type
;
7218 rtx pat
= PATTERN(insn
);
7219 rtx dep_pat
= PATTERN (dep_insn
);
7221 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
7224 insn_type
= get_attr_type (insn
);
7225 dep_type
= get_attr_type (dep_insn
);
7227 switch (REG_NOTE_KIND (link
))
7230 /* Data dependency; DEP_INSN writes a register that INSN reads some
7237 /* Get the delay iff the address of the store is the dependence. */
7238 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7241 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7248 /* If a load, then the dependence must be on the memory address. If
7249 the addresses aren't equal, then it might be a false dependency */
7250 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
7252 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
7253 || GET_CODE (SET_DEST (dep_pat
)) != MEM
7254 || GET_CODE (SET_SRC (pat
)) != MEM
7255 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
7256 XEXP (SET_SRC (pat
), 0)))
7264 /* Compare to branch latency is 0. There is no benefit from
7265 separating compare and branch. */
7266 if (dep_type
== TYPE_COMPARE
)
7268 /* Floating point compare to branch latency is less than
7269 compare to conditional move. */
7270 if (dep_type
== TYPE_FPCMP
)
7279 /* Anti-dependencies only penalize the fpu unit. */
7280 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7292 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
7296 case PROCESSOR_SUPERSPARC
:
7297 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
7299 case PROCESSOR_HYPERSPARC
:
7300 case PROCESSOR_SPARCLITE86X
:
7301 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
7310 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
7311 int sched_verbose ATTRIBUTE_UNUSED
,
7312 int max_ready ATTRIBUTE_UNUSED
)
7317 sparc_use_sched_lookahead (void)
7319 if (sparc_cpu
== PROCESSOR_ULTRASPARC
7320 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
7322 if ((1 << sparc_cpu
) &
7323 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7324 (1 << PROCESSOR_SPARCLITE86X
)))
7330 sparc_issue_rate (void)
7337 /* Assume V9 processors are capable of at least dual-issue. */
7339 case PROCESSOR_SUPERSPARC
:
7341 case PROCESSOR_HYPERSPARC
:
7342 case PROCESSOR_SPARCLITE86X
:
7344 case PROCESSOR_ULTRASPARC
:
7345 case PROCESSOR_ULTRASPARC3
:
7351 set_extends (rtx insn
)
7353 register rtx pat
= PATTERN (insn
);
7355 switch (GET_CODE (SET_SRC (pat
)))
7357 /* Load and some shift instructions zero extend. */
7360 /* sethi clears the high bits */
7362 /* LO_SUM is used with sethi. sethi cleared the high
7363 bits and the values used with lo_sum are positive */
7365 /* Store flag stores 0 or 1 */
7375 rtx op0
= XEXP (SET_SRC (pat
), 0);
7376 rtx op1
= XEXP (SET_SRC (pat
), 1);
7377 if (GET_CODE (op1
) == CONST_INT
)
7378 return INTVAL (op1
) >= 0;
7379 if (GET_CODE (op0
) != REG
)
7381 if (sparc_check_64 (op0
, insn
) == 1)
7383 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7388 rtx op0
= XEXP (SET_SRC (pat
), 0);
7389 rtx op1
= XEXP (SET_SRC (pat
), 1);
7390 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
7392 if (GET_CODE (op1
) == CONST_INT
)
7393 return INTVAL (op1
) >= 0;
7394 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7397 return GET_MODE (SET_SRC (pat
)) == SImode
;
7398 /* Positive integers leave the high bits zero. */
7400 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
7402 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
7405 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
7407 return sparc_check_64 (SET_SRC (pat
), insn
);
7413 /* We _ought_ to have only one kind per function, but... */
7414 static GTY(()) rtx sparc_addr_diff_list
;
7415 static GTY(()) rtx sparc_addr_list
;
7418 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
7420 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
7422 sparc_addr_diff_list
7423 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
7425 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
7429 sparc_output_addr_vec (rtx vec
)
7431 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7432 int idx
, vlen
= XVECLEN (body
, 0);
7434 #ifdef ASM_OUTPUT_ADDR_VEC_START
7435 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7438 #ifdef ASM_OUTPUT_CASE_LABEL
7439 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7442 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7445 for (idx
= 0; idx
< vlen
; idx
++)
7447 ASM_OUTPUT_ADDR_VEC_ELT
7448 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
7451 #ifdef ASM_OUTPUT_ADDR_VEC_END
7452 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7457 sparc_output_addr_diff_vec (rtx vec
)
7459 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7460 rtx base
= XEXP (XEXP (body
, 0), 0);
7461 int idx
, vlen
= XVECLEN (body
, 1);
7463 #ifdef ASM_OUTPUT_ADDR_VEC_START
7464 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7467 #ifdef ASM_OUTPUT_CASE_LABEL
7468 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7471 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7474 for (idx
= 0; idx
< vlen
; idx
++)
7476 ASM_OUTPUT_ADDR_DIFF_ELT
7479 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
7480 CODE_LABEL_NUMBER (base
));
7483 #ifdef ASM_OUTPUT_ADDR_VEC_END
7484 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7489 sparc_output_deferred_case_vectors (void)
7494 if (sparc_addr_list
== NULL_RTX
7495 && sparc_addr_diff_list
== NULL_RTX
)
7498 /* Align to cache line in the function's code section. */
7499 switch_to_section (current_function_section ());
7501 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
7503 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
7505 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
7506 sparc_output_addr_vec (XEXP (t
, 0));
7507 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
7508 sparc_output_addr_diff_vec (XEXP (t
, 0));
7510 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
7513 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7514 unknown. Return 1 if the high bits are zero, -1 if the register is
7517 sparc_check_64 (rtx x
, rtx insn
)
7519 /* If a register is set only once it is safe to ignore insns this
7520 code does not know how to handle. The loop will either recognize
7521 the single set and return the correct value or fail to recognize
7526 gcc_assert (GET_CODE (x
) == REG
);
7528 if (GET_MODE (x
) == DImode
)
7529 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
7531 if (flag_expensive_optimizations
7532 && REG_N_SETS (REGNO (y
)) == 1)
7538 insn
= get_last_insn_anywhere ();
7543 while ((insn
= PREV_INSN (insn
)))
7545 switch (GET_CODE (insn
))
7558 rtx pat
= PATTERN (insn
);
7559 if (GET_CODE (pat
) != SET
)
7561 if (rtx_equal_p (x
, SET_DEST (pat
)))
7562 return set_extends (insn
);
7563 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
7564 return set_extends (insn
);
7565 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
7573 /* Returns assembly code to perform a DImode shift using
7574 a 64-bit global or out register on SPARC-V8+. */
7576 output_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
7578 static char asm_code
[60];
7580 /* The scratch register is only required when the destination
7581 register is not a 64-bit global or out register. */
7582 if (which_alternative
!= 2)
7583 operands
[3] = operands
[0];
7585 /* We can only shift by constants <= 63. */
7586 if (GET_CODE (operands
[2]) == CONST_INT
)
7587 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
7589 if (GET_CODE (operands
[1]) == CONST_INT
)
7591 output_asm_insn ("mov\t%1, %3", operands
);
7595 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
7596 if (sparc_check_64 (operands
[1], insn
) <= 0)
7597 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
7598 output_asm_insn ("or\t%L1, %3, %3", operands
);
7601 strcpy(asm_code
, opcode
);
7603 if (which_alternative
!= 2)
7604 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7606 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7609 /* Output rtl to increment the profiler label LABELNO
7610 for profiling a function entry. */
7613 sparc_profile_hook (int labelno
)
7618 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
7619 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
7620 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
7622 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
7625 #ifdef OBJECT_FORMAT_ELF
7627 sparc_elf_asm_named_section (const char *name
, unsigned int flags
,
7630 if (flags
& SECTION_MERGE
)
7632 /* entsize cannot be expressed in this section attributes
7634 default_elf_asm_named_section (name
, flags
, decl
);
7638 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
7640 if (!(flags
& SECTION_DEBUG
))
7641 fputs (",#alloc", asm_out_file
);
7642 if (flags
& SECTION_WRITE
)
7643 fputs (",#write", asm_out_file
);
7644 if (flags
& SECTION_TLS
)
7645 fputs (",#tls", asm_out_file
);
7646 if (flags
& SECTION_CODE
)
7647 fputs (",#execinstr", asm_out_file
);
7649 /* ??? Handle SECTION_BSS. */
7651 fputc ('\n', asm_out_file
);
7653 #endif /* OBJECT_FORMAT_ELF */
7655 /* We do not allow indirect calls to be optimized into sibling calls.
7657 We cannot use sibling calls when delayed branches are disabled
7658 because they will likely require the call delay slot to be filled.
7660 Also, on SPARC 32-bit we cannot emit a sibling call when the
7661 current function returns a structure. This is because the "unimp
7662 after call" convention would cause the callee to return to the
7663 wrong place. The generic code already disallows cases where the
7664 function being called returns a structure.
7666 It may seem strange how this last case could occur. Usually there
7667 is code after the call which jumps to epilogue code which dumps the
7668 return value into the struct return area. That ought to invalidate
7669 the sibling call right? Well, in the C++ case we can end up passing
7670 the pointer to the struct return area to a constructor (which returns
7671 void) and then nothing else happens. Such a sibling call would look
7672 valid without the added check here. */
7674 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7677 && flag_delayed_branch
7678 && (TARGET_ARCH64
|| ! current_function_returns_struct
));
7681 /* libfunc renaming. */
7682 #include "config/gofast.h"
7685 sparc_init_libfuncs (void)
7689 /* Use the subroutines that Sun's library provides for integer
7690 multiply and divide. The `*' prevents an underscore from
7691 being prepended by the compiler. .umul is a little faster
7693 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
7694 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
7695 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
7696 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
7697 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
7699 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
7700 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
7701 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
7702 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
7703 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
7704 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
7706 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
7707 is because with soft-float, the SFmode and DFmode sqrt
7708 instructions will be absent, and the compiler will notice and
7709 try to use the TFmode sqrt instruction for calls to the
7710 builtin function sqrt, but this fails. */
7712 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
7714 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
7715 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
7716 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
7717 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
7718 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
7719 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
7721 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
7722 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
7723 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
7724 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
7726 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
7727 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
7728 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
7729 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
7731 if (DITF_CONVERSION_LIBFUNCS
)
7733 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
7734 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
7735 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
7736 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
7739 if (SUN_CONVERSION_LIBFUNCS
)
7741 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
7742 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
7743 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
7744 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
7749 /* In the SPARC 64bit ABI, SImode multiply and divide functions
7750 do not exist in the library. Make sure the compiler does not
7751 emit calls to them by accident. (It should always use the
7752 hardware instructions.) */
7753 set_optab_libfunc (smul_optab
, SImode
, 0);
7754 set_optab_libfunc (sdiv_optab
, SImode
, 0);
7755 set_optab_libfunc (udiv_optab
, SImode
, 0);
7756 set_optab_libfunc (smod_optab
, SImode
, 0);
7757 set_optab_libfunc (umod_optab
, SImode
, 0);
7759 if (SUN_INTEGER_MULTIPLY_64
)
7761 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
7762 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
7763 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
7764 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
7765 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
7768 if (SUN_CONVERSION_LIBFUNCS
)
7770 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
7771 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
7772 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
7773 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
7777 gofast_maybe_init_libfuncs ();
7780 #define def_builtin(NAME, CODE, TYPE) \
7781 lang_hooks.builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
7784 /* Implement the TARGET_INIT_BUILTINS target hook.
7785 Create builtin functions for special SPARC instructions. */
7788 sparc_init_builtins (void)
7791 sparc_vis_init_builtins ();
7794 /* Create builtin functions for VIS 1.0 instructions. */
7797 sparc_vis_init_builtins (void)
7799 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
7800 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
7801 tree v4hi
= build_vector_type (intHI_type_node
, 4);
7802 tree v2hi
= build_vector_type (intHI_type_node
, 2);
7803 tree v2si
= build_vector_type (intSI_type_node
, 2);
7805 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
7806 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
7807 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
7808 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
7809 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
7810 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
7811 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
7812 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
7813 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
7814 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
7815 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
7816 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
7817 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
7819 intDI_type_node
, 0);
7820 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
7822 intDI_type_node
, 0);
7823 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
7825 intSI_type_node
, 0);
7826 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
7828 intDI_type_node
, 0);
7830 /* Packing and expanding vectors. */
7831 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
, v4qi_ftype_v4hi
);
7832 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
7833 v8qi_ftype_v2si_v8qi
);
7834 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
7836 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
, v4hi_ftype_v4qi
);
7837 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
7838 v8qi_ftype_v4qi_v4qi
);
7840 /* Multiplications. */
7841 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
7842 v4hi_ftype_v4qi_v4hi
);
7843 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
7844 v4hi_ftype_v4qi_v2hi
);
7845 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
7846 v4hi_ftype_v4qi_v2hi
);
7847 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
7848 v4hi_ftype_v8qi_v4hi
);
7849 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
7850 v4hi_ftype_v8qi_v4hi
);
7851 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
7852 v2si_ftype_v4qi_v2hi
);
7853 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
7854 v2si_ftype_v4qi_v2hi
);
7856 /* Data aligning. */
7857 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
7858 v4hi_ftype_v4hi_v4hi
);
7859 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
7860 v8qi_ftype_v8qi_v8qi
);
7861 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
7862 v2si_ftype_v2si_v2si
);
7863 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis
,
7866 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
7869 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
7872 /* Pixel distance. */
7873 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
7874 di_ftype_v8qi_v8qi_di
);
7877 /* Handle TARGET_EXPAND_BUILTIN target hook.
7878 Expand builtin functions for sparc intrinsics. */
7881 sparc_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
7882 enum machine_mode tmode
, int ignore ATTRIBUTE_UNUSED
)
7885 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7886 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
7888 enum machine_mode mode
[4];
7891 mode
[arg_count
] = tmode
;
7894 || GET_MODE (target
) != tmode
7895 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7896 op
[arg_count
] = gen_reg_rtx (tmode
);
7898 op
[arg_count
] = target
;
7900 for (arglist
= TREE_OPERAND (exp
, 1); arglist
;
7901 arglist
= TREE_CHAIN (arglist
))
7903 tree arg
= TREE_VALUE (arglist
);
7906 mode
[arg_count
] = insn_data
[icode
].operand
[arg_count
].mode
;
7907 op
[arg_count
] = expand_normal (arg
);
7909 if (! (*insn_data
[icode
].operand
[arg_count
].predicate
) (op
[arg_count
],
7911 op
[arg_count
] = copy_to_mode_reg (mode
[arg_count
], op
[arg_count
]);
7917 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
7920 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
7923 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
7938 sparc_vis_mul8x16 (int e8
, int e16
)
7940 return (e8
* e16
+ 128) / 256;
7943 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
7944 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
7945 constants. A tree list with the results of the multiplications is returned,
7946 and each element in the list is of INNER_TYPE. */
7949 sparc_handle_vis_mul8x16 (int fncode
, tree inner_type
, tree elts0
, tree elts1
)
7951 tree n_elts
= NULL_TREE
;
7956 case CODE_FOR_fmul8x16_vis
:
7957 for (; elts0
&& elts1
;
7958 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
7961 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
7962 TREE_INT_CST_LOW (TREE_VALUE (elts1
)));
7963 n_elts
= tree_cons (NULL_TREE
,
7964 build_int_cst (inner_type
, val
),
7969 case CODE_FOR_fmul8x16au_vis
:
7970 scale
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
7972 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
7975 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
7977 n_elts
= tree_cons (NULL_TREE
,
7978 build_int_cst (inner_type
, val
),
7983 case CODE_FOR_fmul8x16al_vis
:
7984 scale
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1
)));
7986 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
7989 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
7991 n_elts
= tree_cons (NULL_TREE
,
7992 build_int_cst (inner_type
, val
),
8001 return nreverse (n_elts
);
8004 /* Handle TARGET_FOLD_BUILTIN target hook.
8005 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
8006 result of the function call is ignored. NULL_TREE is returned if the
8007 function could not be folded. */
8010 sparc_fold_builtin (tree fndecl
, tree arglist
, bool ignore
)
8012 tree arg0
, arg1
, arg2
;
8013 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
8016 if (ignore
&& DECL_FUNCTION_CODE (fndecl
) != CODE_FOR_alignaddrsi_vis
8017 && DECL_FUNCTION_CODE (fndecl
) != CODE_FOR_alignaddrdi_vis
)
8018 return build_int_cst (rtype
, 0);
8020 switch (DECL_FUNCTION_CODE (fndecl
))
8022 case CODE_FOR_fexpand_vis
:
8023 arg0
= TREE_VALUE (arglist
);
8026 if (TREE_CODE (arg0
) == VECTOR_CST
)
8028 tree inner_type
= TREE_TYPE (rtype
);
8029 tree elts
= TREE_VECTOR_CST_ELTS (arg0
);
8030 tree n_elts
= NULL_TREE
;
8032 for (; elts
; elts
= TREE_CHAIN (elts
))
8034 unsigned int val
= TREE_INT_CST_LOW (TREE_VALUE (elts
)) << 4;
8035 n_elts
= tree_cons (NULL_TREE
,
8036 build_int_cst (inner_type
, val
),
8039 return build_vector (rtype
, nreverse (n_elts
));
8043 case CODE_FOR_fmul8x16_vis
:
8044 case CODE_FOR_fmul8x16au_vis
:
8045 case CODE_FOR_fmul8x16al_vis
:
8046 arg0
= TREE_VALUE (arglist
);
8047 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8051 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
8053 tree inner_type
= TREE_TYPE (rtype
);
8054 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
8055 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
8056 tree n_elts
= sparc_handle_vis_mul8x16 (DECL_FUNCTION_CODE (fndecl
),
8057 inner_type
, elts0
, elts1
);
8059 return build_vector (rtype
, n_elts
);
8063 case CODE_FOR_fpmerge_vis
:
8064 arg0
= TREE_VALUE (arglist
);
8065 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8069 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
8071 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
8072 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
8073 tree n_elts
= NULL_TREE
;
8075 for (; elts0
&& elts1
;
8076 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
8078 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts0
), n_elts
);
8079 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts1
), n_elts
);
8082 return build_vector (rtype
, nreverse (n_elts
));
8086 case CODE_FOR_pdist_vis
:
8087 arg0
= TREE_VALUE (arglist
);
8088 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8089 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8094 if (TREE_CODE (arg0
) == VECTOR_CST
8095 && TREE_CODE (arg1
) == VECTOR_CST
8096 && TREE_CODE (arg2
) == INTEGER_CST
)
8099 unsigned HOST_WIDE_INT low
= TREE_INT_CST_LOW (arg2
);
8100 HOST_WIDE_INT high
= TREE_INT_CST_HIGH (arg2
);
8101 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
8102 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
8104 for (; elts0
&& elts1
;
8105 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
8107 unsigned HOST_WIDE_INT
8108 low0
= TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
8109 low1
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
8110 HOST_WIDE_INT high0
= TREE_INT_CST_HIGH (TREE_VALUE (elts0
));
8111 HOST_WIDE_INT high1
= TREE_INT_CST_HIGH (TREE_VALUE (elts1
));
8113 unsigned HOST_WIDE_INT l
;
8116 overflow
|= neg_double (low1
, high1
, &l
, &h
);
8117 overflow
|= add_double (low0
, high0
, l
, h
, &l
, &h
);
8119 overflow
|= neg_double (l
, h
, &l
, &h
);
8121 overflow
|= add_double (low
, high
, l
, h
, &low
, &high
);
8124 gcc_assert (overflow
== 0);
8126 return build_int_cst_wide (rtype
, low
, high
);
8136 sparc_extra_constraint_check (rtx op
, int c
, int strict
)
8141 && (c
== 'T' || c
== 'U'))
8147 return fp_sethi_p (op
);
8150 return fp_mov_p (op
);
8153 return fp_high_losum_p (op
);
8157 || (GET_CODE (op
) == REG
8158 && (REGNO (op
) < FIRST_PSEUDO_REGISTER
8159 || reg_renumber
[REGNO (op
)] >= 0)))
8160 return register_ok_for_ldd (op
);
8169 return const_zero_operand (op
, GET_MODE (op
));
8175 /* Our memory extra constraints have to emulate the
8176 behavior of 'm' and 'o' in order for reload to work
8178 if (GET_CODE (op
) == MEM
)
8181 if ((TARGET_ARCH64
|| mem_min_alignment (op
, 8))
8183 || strict_memory_address_p (Pmode
, XEXP (op
, 0))))
8188 reload_ok_mem
= (reload_in_progress
8189 && GET_CODE (op
) == REG
8190 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
8191 && reg_renumber
[REGNO (op
)] < 0);
8194 return reload_ok_mem
;
8197 /* ??? This duplicates information provided to the compiler by the
8198 ??? scheduler description. Some day, teach genautomata to output
8199 ??? the latencies and then CSE will just use that. */
8202 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
8204 enum machine_mode mode
= GET_MODE (x
);
8205 bool float_mode_p
= FLOAT_MODE_P (mode
);
8210 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
8228 if (GET_MODE (x
) == VOIDmode
8229 && ((CONST_DOUBLE_HIGH (x
) == 0
8230 && CONST_DOUBLE_LOW (x
) < 0x1000)
8231 || (CONST_DOUBLE_HIGH (x
) == -1
8232 && CONST_DOUBLE_LOW (x
) < 0
8233 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
8240 /* If outer-code was a sign or zero extension, a cost
8241 of COSTS_N_INSNS (1) was already added in. This is
8242 why we are subtracting it back out. */
8243 if (outer_code
== ZERO_EXTEND
)
8245 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
8247 else if (outer_code
== SIGN_EXTEND
)
8249 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
8251 else if (float_mode_p
)
8253 *total
= sparc_costs
->float_load
;
8257 *total
= sparc_costs
->int_load
;
8265 *total
= sparc_costs
->float_plusminus
;
8267 *total
= COSTS_N_INSNS (1);
8272 *total
= sparc_costs
->float_mul
;
8273 else if (! TARGET_HARD_MUL
)
8274 *total
= COSTS_N_INSNS (25);
8280 if (sparc_costs
->int_mul_bit_factor
)
8284 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8286 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
8287 for (nbits
= 0; value
!= 0; value
&= value
- 1)
8290 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
8291 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
8293 rtx x1
= XEXP (x
, 1);
8294 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
8295 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
8297 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
8299 for (; value2
!= 0; value2
&= value2
- 1)
8307 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
8308 bit_cost
= COSTS_N_INSNS (bit_cost
);
8312 *total
= sparc_costs
->int_mulX
+ bit_cost
;
8314 *total
= sparc_costs
->int_mul
+ bit_cost
;
8321 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
8331 *total
= sparc_costs
->float_div_df
;
8333 *total
= sparc_costs
->float_div_sf
;
8338 *total
= sparc_costs
->int_divX
;
8340 *total
= sparc_costs
->int_div
;
8347 *total
= COSTS_N_INSNS (1);
8354 case UNSIGNED_FLOAT
:
8358 case FLOAT_TRUNCATE
:
8359 *total
= sparc_costs
->float_move
;
8364 *total
= sparc_costs
->float_sqrt_df
;
8366 *total
= sparc_costs
->float_sqrt_sf
;
8371 *total
= sparc_costs
->float_cmp
;
8373 *total
= COSTS_N_INSNS (1);
8378 *total
= sparc_costs
->float_cmove
;
8380 *total
= sparc_costs
->int_cmove
;
8384 /* Handle the NAND vector patterns. */
8385 if (sparc_vector_mode_supported_p (GET_MODE (x
))
8386 && GET_CODE (XEXP (x
, 0)) == NOT
8387 && GET_CODE (XEXP (x
, 1)) == NOT
)
8389 *total
= COSTS_N_INSNS (1);
8400 /* Emit the sequence of insns SEQ while preserving the registers. */
8403 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
8405 /* STACK_BOUNDARY guarantees that this is a 2-word slot. */
8406 rtx slot
= gen_rtx_MEM (word_mode
,
8407 plus_constant (stack_pointer_rtx
, SPARC_STACK_BIAS
));
8409 emit_insn (gen_stack_pointer_dec (GEN_INT (STACK_BOUNDARY
/BITS_PER_UNIT
)));
8410 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
8412 emit_insn (gen_rtx_SET (VOIDmode
,
8413 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
8417 emit_insn (gen_rtx_SET (VOIDmode
,
8419 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
8420 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
8421 emit_insn (gen_stack_pointer_inc (GEN_INT (STACK_BOUNDARY
/BITS_PER_UNIT
)));
8424 /* Output the assembler code for a thunk function. THUNK_DECL is the
8425 declaration for the thunk function itself, FUNCTION is the decl for
8426 the target function. DELTA is an immediate constant offset to be
8427 added to THIS. If VCALL_OFFSET is nonzero, the word at address
8428 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
8431 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
8432 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8435 rtx
this, insn
, funexp
;
8436 unsigned int int_arg_first
;
8438 reload_completed
= 1;
8439 epilogue_completed
= 1;
8441 reset_block_changes ();
8443 emit_note (NOTE_INSN_PROLOGUE_END
);
8445 if (flag_delayed_branch
)
8447 /* We will emit a regular sibcall below, so we need to instruct
8448 output_sibcall that we are in a leaf function. */
8449 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 1;
8451 /* This will cause final.c to invoke leaf_renumber_regs so we
8452 must behave as if we were in a not-yet-leafified function. */
8453 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
8457 /* We will emit the sibcall manually below, so we will need to
8458 manually spill non-leaf registers. */
8459 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 0;
8461 /* We really are in a leaf function. */
8462 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
8465 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8466 returns a structure, the structure return pointer is there instead. */
8467 if (TARGET_ARCH64
&& aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8468 this = gen_rtx_REG (Pmode
, int_arg_first
+ 1);
8470 this = gen_rtx_REG (Pmode
, int_arg_first
);
8472 /* Add DELTA. When possible use a plain add, otherwise load it into
8473 a register first. */
8476 rtx delta_rtx
= GEN_INT (delta
);
8478 if (! SPARC_SIMM13_P (delta
))
8480 rtx scratch
= gen_rtx_REG (Pmode
, 1);
8481 emit_move_insn (scratch
, delta_rtx
);
8482 delta_rtx
= scratch
;
8485 /* THIS += DELTA. */
8486 emit_insn (gen_add2_insn (this, delta_rtx
));
8489 /* Add the word at address (*THIS + VCALL_OFFSET). */
8492 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
8493 rtx scratch
= gen_rtx_REG (Pmode
, 1);
8495 gcc_assert (vcall_offset
< 0);
8497 /* SCRATCH = *THIS. */
8498 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this));
8500 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
8501 may not have any available scratch register at this point. */
8502 if (SPARC_SIMM13_P (vcall_offset
))
8504 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
8505 else if (! fixed_regs
[5]
8506 /* The below sequence is made up of at least 2 insns,
8507 while the default method may need only one. */
8508 && vcall_offset
< -8192)
8510 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
8511 emit_move_insn (scratch2
, vcall_offset_rtx
);
8512 vcall_offset_rtx
= scratch2
;
8516 rtx increment
= GEN_INT (-4096);
8518 /* VCALL_OFFSET is a negative number whose typical range can be
8519 estimated as -32768..0 in 32-bit mode. In almost all cases
8520 it is therefore cheaper to emit multiple add insns than
8521 spilling and loading the constant into a register (at least
8523 while (! SPARC_SIMM13_P (vcall_offset
))
8525 emit_insn (gen_add2_insn (scratch
, increment
));
8526 vcall_offset
+= 4096;
8528 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
8531 /* SCRATCH = *(*THIS + VCALL_OFFSET). */
8532 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
8533 gen_rtx_PLUS (Pmode
,
8535 vcall_offset_rtx
)));
8537 /* THIS += *(*THIS + VCALL_OFFSET). */
8538 emit_insn (gen_add2_insn (this, scratch
));
8541 /* Generate a tail call to the target function. */
8542 if (! TREE_USED (function
))
8544 assemble_external (function
);
8545 TREE_USED (function
) = 1;
8547 funexp
= XEXP (DECL_RTL (function
), 0);
8549 if (flag_delayed_branch
)
8551 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8552 insn
= emit_call_insn (gen_sibcall (funexp
));
8553 SIBLING_CALL_P (insn
) = 1;
8557 /* The hoops we have to jump through in order to generate a sibcall
8558 without using delay slots... */
8559 rtx spill_reg
, spill_reg2
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
8563 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
8564 spill_reg2
= gen_rtx_REG (word_mode
, PIC_OFFSET_TABLE_REGNUM
);
8566 /* Delay emitting the PIC helper function because it needs to
8567 change the section and we are emitting assembly code. */
8568 load_pic_register (true); /* clobbers %o7 */
8569 scratch
= legitimize_pic_address (funexp
, Pmode
, scratch
);
8572 emit_and_preserve (seq
, spill_reg
, spill_reg2
);
8574 else if (TARGET_ARCH32
)
8576 emit_insn (gen_rtx_SET (VOIDmode
,
8578 gen_rtx_HIGH (SImode
, funexp
)));
8579 emit_insn (gen_rtx_SET (VOIDmode
,
8581 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
8583 else /* TARGET_ARCH64 */
8585 switch (sparc_cmodel
)
8589 /* The destination can serve as a temporary. */
8590 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
8595 /* The destination cannot serve as a temporary. */
8596 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
8598 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
8601 emit_and_preserve (seq
, spill_reg
, 0);
8609 emit_jump_insn (gen_indirect_jump (scratch
));
8614 /* Run just enough of rest_of_compilation to get the insns emitted.
8615 There's not really enough bulk here to make other passes such as
8616 instruction scheduling worth while. Note that use_thunk calls
8617 assemble_start_function and assemble_end_function. */
8618 insn
= get_insns ();
8619 insn_locators_initialize ();
8620 shorten_branches (insn
);
8621 final_start_function (insn
, file
, 1);
8622 final (insn
, file
, 1);
8623 final_end_function ();
8625 reload_completed
= 0;
8626 epilogue_completed
= 0;
8630 /* Return true if sparc_output_mi_thunk would be able to output the
8631 assembler code for the thunk function specified by the arguments
8632 it is passed, and false otherwise. */
8634 sparc_can_output_mi_thunk (tree thunk_fndecl ATTRIBUTE_UNUSED
,
8635 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
8636 HOST_WIDE_INT vcall_offset
,
8637 tree function ATTRIBUTE_UNUSED
)
8639 /* Bound the loop used in the default method above. */
8640 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
8643 /* How to allocate a 'struct machine_function'. */
8645 static struct machine_function
*
8646 sparc_init_machine_status (void)
8648 return ggc_alloc_cleared (sizeof (struct machine_function
));
8651 /* Locate some local-dynamic symbol still in use by this function
8652 so that we can print its name in local-dynamic base patterns. */
8655 get_some_local_dynamic_name (void)
8659 if (cfun
->machine
->some_ld_name
)
8660 return cfun
->machine
->some_ld_name
;
8662 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8664 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
8665 return cfun
->machine
->some_ld_name
;
8671 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
8676 && GET_CODE (x
) == SYMBOL_REF
8677 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
8679 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
8686 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
8687 This is called from dwarf2out.c to emit call frame instructions
8688 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
8690 sparc_dwarf_handle_frame_unspec (const char *label
,
8691 rtx pattern ATTRIBUTE_UNUSED
,
8692 int index ATTRIBUTE_UNUSED
)
8694 gcc_assert (index
== UNSPECV_SAVEW
);
8695 dwarf2out_window_save (label
);
8698 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8699 We need to emit DTP-relative relocations. */
8702 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8707 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
8710 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
8715 output_addr_const (file
, x
);
8719 /* Do whatever processing is required at the end of a file. */
8722 sparc_file_end (void)
8724 /* If we haven't emitted the special PIC helper function, do so now. */
8725 if (pic_helper_symbol_name
[0] && !pic_helper_emitted_p
)
8728 if (NEED_INDICATE_EXEC_STACK
)
8729 file_end_indicate_exec_stack ();
8732 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
8733 /* Implement TARGET_MANGLE_FUNDAMENTAL_TYPE. */
8736 sparc_mangle_fundamental_type (tree type
)
8739 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
8740 && TARGET_LONG_DOUBLE_128
)
8743 /* For all other types, use normal C++ mangling. */
8748 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
8749 compare and swap on the word containing the byte or half-word. */
8752 sparc_expand_compare_and_swap_12 (rtx result
, rtx mem
, rtx oldval
, rtx newval
)
8754 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
8755 rtx addr
= gen_reg_rtx (Pmode
);
8756 rtx off
= gen_reg_rtx (SImode
);
8757 rtx oldv
= gen_reg_rtx (SImode
);
8758 rtx newv
= gen_reg_rtx (SImode
);
8759 rtx oldvalue
= gen_reg_rtx (SImode
);
8760 rtx newvalue
= gen_reg_rtx (SImode
);
8761 rtx res
= gen_reg_rtx (SImode
);
8762 rtx resv
= gen_reg_rtx (SImode
);
8763 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
;
8765 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
8766 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
8768 if (Pmode
!= SImode
)
8769 addr1
= gen_lowpart (SImode
, addr1
);
8770 emit_insn (gen_rtx_SET (VOIDmode
, off
,
8771 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
8773 memsi
= gen_rtx_MEM (SImode
, addr
);
8774 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
8775 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
8777 val
= force_reg (SImode
, memsi
);
8779 emit_insn (gen_rtx_SET (VOIDmode
, off
,
8780 gen_rtx_XOR (SImode
, off
,
8781 GEN_INT (GET_MODE (mem
) == QImode
8784 emit_insn (gen_rtx_SET (VOIDmode
, off
,
8785 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
8787 if (GET_MODE (mem
) == QImode
)
8788 mask
= force_reg (SImode
, GEN_INT (0xff));
8790 mask
= force_reg (SImode
, GEN_INT (0xffff));
8792 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
8793 gen_rtx_ASHIFT (SImode
, mask
, off
)));
8795 emit_insn (gen_rtx_SET (VOIDmode
, val
,
8796 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
8799 oldval
= gen_lowpart (SImode
, oldval
);
8800 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
8801 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
8803 newval
= gen_lowpart_common (SImode
, newval
);
8804 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
8805 gen_rtx_ASHIFT (SImode
, newval
, off
)));
8807 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
8808 gen_rtx_AND (SImode
, oldv
, mask
)));
8810 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
8811 gen_rtx_AND (SImode
, newv
, mask
)));
8813 end_label
= gen_label_rtx ();
8814 loop_label
= gen_label_rtx ();
8815 emit_label (loop_label
);
8817 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
8818 gen_rtx_IOR (SImode
, oldv
, val
)));
8820 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
8821 gen_rtx_IOR (SImode
, newv
, val
)));
8823 emit_insn (gen_sync_compare_and_swapsi (res
, memsi
, oldvalue
, newvalue
));
8825 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
8827 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
8828 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
8831 sparc_compare_op0
= resv
;
8832 sparc_compare_op1
= val
;
8833 cc
= gen_compare_reg (NE
);
8835 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
8837 sparc_compare_emitted
= cc
;
8838 emit_jump_insn (gen_bne (loop_label
));
8840 emit_label (end_label
);
8842 emit_insn (gen_rtx_SET (VOIDmode
, res
,
8843 gen_rtx_AND (SImode
, res
, mask
)));
8845 emit_insn (gen_rtx_SET (VOIDmode
, res
,
8846 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
8848 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
8851 #include "gt-sparc.h"