| blob | 8ebb3c58e2bf71f517be48d027e779ab5797e5a4 |
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
27 /* MIPS external variables defined in mips.c. */
29 /* Which processor to schedule for. Since there is no difference between
30 a R2000 and R3000 in terms of the scheduler, we collapse them into
31 just an R3000. The elements of the enumeration must match exactly
32 the cpu attribute in the mips.md machine description. */
35 PROCESSOR_R3000,
36 PROCESSOR_4KC,
37 PROCESSOR_4KP,
38 PROCESSOR_5KC,
39 PROCESSOR_5KF,
40 PROCESSOR_20KC,
41 PROCESSOR_24K,
42 PROCESSOR_24KX,
43 PROCESSOR_M4K,
44 PROCESSOR_R3900,
45 PROCESSOR_R6000,
46 PROCESSOR_R4000,
47 PROCESSOR_R4100,
48 PROCESSOR_R4111,
49 PROCESSOR_R4120,
50 PROCESSOR_R4130,
51 PROCESSOR_R4300,
52 PROCESSOR_R4600,
53 PROCESSOR_R4650,
54 PROCESSOR_R5000,
55 PROCESSOR_R5400,
56 PROCESSOR_R5500,
57 PROCESSOR_R7000,
58 PROCESSOR_R8000,
59 PROCESSOR_R9000,
60 PROCESSOR_SB1,
61 PROCESSOR_SR71000,
62 PROCESSOR_MAX
63 };
65 /* Costs of various operations on the different architectures. */
67 struct mips_rtx_cost_data
68 {
80 };
82 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
83 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
84 to work on a 64 bit machine. */
86 #define ABI_32 0
87 #define ABI_N32 1
88 #define ABI_64 2
89 #define ABI_EABI 3
90 #define ABI_O64 4
92 /* Information about one recognized processor. Defined here for the
93 benefit of TARGET_CPU_CPP_BUILTINS. */
95 /* The 'canonical' name of the processor as far as GCC is concerned.
96 It's typically a manufacturer's prefix followed by a numerical
97 designation. It should be lower case. */
100 /* The internal processor number that most closely matches this
101 entry. Several processors can have the same value, if there's no
102 difference between them from GCC's point of view. */
105 /* The ISA level that the processor implements. */
107 };
131 /* Macros to silence warnings about numbers being signed in traditional
132 C and unsigned in ISO C when compiled on 32-bit hosts. */
138 \f
139 /* Run-time compilation parameters selecting different hardware subsets. */
141 /* True if the call patterns should be split into a jalr followed by
142 an instruction to restore $gp. This is only ever true for SVR4 PIC,
143 in which $gp is call-clobbered. It is only safe to split the load
144 from the call when every use of $gp is explicit. */
146 #define TARGET_SPLIT_CALLS \
147 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
149 /* True if we can optimize sibling calls. For simplicity, we only
150 handle cases in which call_insn_operand will reject invalid
151 sibcall addresses. There are two cases in which this isn't true:
153 - TARGET_MIPS16. call_insn_operand accepts constant addresses
154 but there is no direct jump instruction. It isn't worth
155 using sibling calls in this case anyway; they would usually
156 be longer than normal calls.
158 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
159 accepts global constants, but "jr $25" is the only allowed
160 sibcall. */
162 #define TARGET_SIBCALLS \
163 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
165 /* True if .gpword or .gpdword should be used for switch tables.
167 Although GAS does understand .gpdword, the SGI linker mishandles
168 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
169 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
170 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
172 /* Generate mips16 code */
173 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
174 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
175 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
177 /* Generic ISA defines. */
178 #define ISA_MIPS1 (mips_isa == 1)
179 #define ISA_MIPS2 (mips_isa == 2)
180 #define ISA_MIPS3 (mips_isa == 3)
181 #define ISA_MIPS4 (mips_isa == 4)
182 #define ISA_MIPS32 (mips_isa == 32)
183 #define ISA_MIPS32R2 (mips_isa == 33)
184 #define ISA_MIPS64 (mips_isa == 64)
186 /* Architecture target defines. */
187 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
188 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
189 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
190 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
191 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
192 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
193 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
194 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
195 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
196 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
198 /* Scheduling target defines. */
199 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
200 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
201 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
202 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
203 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
204 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
205 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
206 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
207 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
208 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
209 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
210 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
212 /* True if the pre-reload scheduler should try to create chains of
213 multiply-add or multiply-subtract instructions. For example,
214 suppose we have:
216 t1 = a * b
217 t2 = t1 + c * d
218 t3 = e * f
219 t4 = t3 - g * h
221 t1 will have a higher priority than t2 and t3 will have a higher
222 priority than t4. However, before reload, there is no dependence
223 between t1 and t3, and they can often have similar priorities.
224 The scheduler will then tend to prefer:
226 t1 = a * b
227 t3 = e * f
228 t2 = t1 + c * d
229 t4 = t3 - g * h
231 which stops us from making full use of macc/madd-style instructions.
232 This sort of situation occurs frequently in Fourier transforms and
233 in unrolled loops.
235 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
236 queue so that chained multiply-add and multiply-subtract instructions
237 appear ahead of any other instruction that is likely to clobber lo.
238 In the example above, if t2 and t3 become ready at the same time,
239 the code ensures that t2 is scheduled first.
241 Multiply-accumulate instructions are a bigger win for some targets
242 than others, so this macro is defined on an opt-in basis. */
243 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
244 || TUNE_MIPS4120 \
245 || TUNE_MIPS4130)
247 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
248 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
250 /* IRIX specific stuff. */
251 #define TARGET_IRIX 0
252 #define TARGET_IRIX6 0
254 /* Define preprocessor macros for the -march and -mtune options.
255 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
256 processor. If INFO's canonical name is "foo", define PREFIX to
257 be "foo", and define an additional macro PREFIX_FOO. */
258 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
259 do \
260 { \
261 char *macro, *p; \
262 \
264 for (p = macro; *p != 0; p++) \
265 *p = TOUPPER (*p); \
266 \
267 builtin_define (macro); \
268 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
269 free (macro); \
270 } \
271 while (0)
273 /* Target CPU builtins. */
274 #define TARGET_CPU_CPP_BUILTINS() \
275 do \
276 { \
278 if (!TARGET_IRIX) \
280 \
284 \
285 /* We do this here because __mips is defined below \
287 if (!flag_iso) \
289 \
290 if (TARGET_64BIT) \
292 \
293 if (!TARGET_IRIX) \
294 { \
295 /* Treat _R3000 and _R4000 like register-size \
296 defines, which is how they've historically \
298 if (TARGET_64BIT) \
299 { \
302 } \
303 else \
304 { \
307 } \
308 } \
309 if (TARGET_FLOAT64) \
311 else \
313 \
314 if (TARGET_MIPS16) \
316 \
317 if (TARGET_MIPS3D) \
319 \
320 if (TARGET_DSP) \
322 \
325 \
326 if (ISA_MIPS1) \
327 { \
330 } \
331 else if (ISA_MIPS2) \
332 { \
335 } \
336 else if (ISA_MIPS3) \
337 { \
340 } \
341 else if (ISA_MIPS4) \
342 { \
345 } \
346 else if (ISA_MIPS32) \
347 { \
351 } \
352 else if (ISA_MIPS32R2) \
353 { \
357 } \
358 else if (ISA_MIPS64) \
359 { \
363 } \
364 \
365 if (TARGET_HARD_FLOAT) \
367 else if (TARGET_SOFT_FLOAT) \
369 \
370 if (TARGET_SINGLE_FLOAT) \
372 \
373 if (TARGET_PAIRED_SINGLE_FLOAT) \
375 \
376 if (TARGET_BIG_ENDIAN) \
377 { \
380 } \
381 else \
382 { \
385 } \
386 \
388 if (preprocessing_asm_p ()) \
389 { \
392 } \
393 else if (c_dialect_cxx ()) \
394 { \
398 } \
399 else \
400 { \
403 } \
404 if (c_dialect_objc ()) \
405 { \
411 } \
412 \
413 if (mips_abi == ABI_EABI) \
415 \
416 } while (0)
418 /* Default target_flags if no switches are specified */
420 #ifndef TARGET_DEFAULT
421 #define TARGET_DEFAULT 0
422 #endif
424 #ifndef TARGET_CPU_DEFAULT
425 #define TARGET_CPU_DEFAULT 0
426 #endif
428 #ifndef TARGET_ENDIAN_DEFAULT
429 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
430 #endif
432 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
433 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
434 #endif
436 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
437 #ifndef MIPS_ISA_DEFAULT
438 #ifndef MIPS_CPU_STRING_DEFAULT
440 #endif
441 #endif
443 #ifdef IN_LIBGCC2
444 #undef TARGET_64BIT
445 /* Make this compile time constant for libgcc2 */
446 #ifdef __mips64
447 #define TARGET_64BIT 1
448 #else
449 #define TARGET_64BIT 0
450 #endif
453 #ifndef MULTILIB_ENDIAN_DEFAULT
454 #if TARGET_ENDIAN_DEFAULT == 0
456 #else
458 #endif
459 #endif
461 #ifndef MULTILIB_ISA_DEFAULT
462 # if MIPS_ISA_DEFAULT == 1
464 # else
465 # if MIPS_ISA_DEFAULT == 2
467 # else
468 # if MIPS_ISA_DEFAULT == 3
470 # else
471 # if MIPS_ISA_DEFAULT == 4
473 # else
474 # if MIPS_ISA_DEFAULT == 32
476 # else
477 # if MIPS_ISA_DEFAULT == 33
479 # else
480 # if MIPS_ISA_DEFAULT == 64
482 # else
484 # endif
485 # endif
486 # endif
487 # endif
488 # endif
489 # endif
490 # endif
491 #endif
493 #ifndef MULTILIB_DEFAULTS
494 #define MULTILIB_DEFAULTS \
495 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
496 #endif
498 /* We must pass -EL to the linker by default for little endian embedded
499 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
500 linker will default to using big-endian output files. The OUTPUT_FORMAT
501 line must be in the linker script, otherwise -EB/-EL will not work. */
503 #ifndef ENDIAN_SPEC
504 #if TARGET_ENDIAN_DEFAULT == 0
506 #else
508 #endif
509 #endif
511 /* Support for a compile-time default CPU, et cetera. The rules are:
512 --with-arch is ignored if -march is specified or a -mips is specified
513 (other than -mips16).
514 --with-tune is ignored if -mtune is specified.
515 --with-abi is ignored if -mabi is specified.
516 --with-float is ignored if -mhard-float or -msoft-float are
517 specified.
518 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
519 specified. */
520 #define OPTION_DEFAULT_SPECS \
528 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
529 && ISA_HAS_COND_TRAP)
531 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
532 && !TARGET_SR71K \
533 && !TARGET_MIPS16)
535 /* Generate three-operand multiply instructions for SImode. */
536 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
537 || TARGET_MIPS5400 \
538 || TARGET_MIPS5500 \
539 || TARGET_MIPS7000 \
540 || TARGET_MIPS9000 \
541 || TARGET_MAD \
542 || ISA_MIPS32 \
543 || ISA_MIPS32R2 \
544 || ISA_MIPS64) \
545 && !TARGET_MIPS16)
547 /* Generate three-operand multiply instructions for DImode. */
548 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
549 && !TARGET_MIPS16)
551 /* True if the ABI can only work with 64-bit integer registers. We
552 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
553 otherwise floating-point registers must also be 64-bit. */
554 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
556 /* Likewise for 32-bit regs. */
557 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
559 /* True if symbols are 64 bits wide. At present, n64 is the only
560 ABI for which this is true. */
561 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
563 /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
564 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
565 || ISA_MIPS4 \
566 || ISA_MIPS64)
568 /* ISA has branch likely instructions (e.g. mips2). */
569 /* Disable branchlikely for tx39 until compare rewrite. They haven't
570 been generated up to this point. */
571 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
573 /* ISA has the conditional move instructions introduced in mips4. */
574 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
575 || ISA_MIPS32 \
576 || ISA_MIPS32R2 \
577 || ISA_MIPS64) \
578 && !TARGET_MIPS5500 \
579 && !TARGET_MIPS16)
581 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
582 branch on CC, and move (both FP and non-FP) on CC. */
583 #define ISA_HAS_8CC (ISA_MIPS4 \
584 || ISA_MIPS32 \
585 || ISA_MIPS32R2 \
586 || ISA_MIPS64)
588 /* This is a catch all for other mips4 instructions: indexed load, the
589 FP madd and msub instructions, and the FP recip and recip sqrt
590 instructions. */
591 #define ISA_HAS_FP4 ((ISA_MIPS4 \
592 || ISA_MIPS64) \
593 && !TARGET_MIPS16)
595 /* ISA has conditional trap instructions. */
596 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
597 && !TARGET_MIPS16)
599 /* ISA has integer multiply-accumulate instructions, madd and msub. */
600 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
601 || ISA_MIPS32R2 \
602 || ISA_MIPS64 \
603 ) && !TARGET_MIPS16)
605 /* ISA has floating-point nmadd and nmsub instructions. */
606 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
607 || ISA_MIPS64) \
608 && (!TARGET_MIPS5400 || TARGET_MAD) \
609 && ! TARGET_MIPS16)
611 /* ISA has count leading zeroes/ones instruction (not implemented). */
612 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
613 || ISA_MIPS32R2 \
614 || ISA_MIPS64 \
615 ) && !TARGET_MIPS16)
617 /* ISA has double-word count leading zeroes/ones instruction (not
618 implemented). */
619 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
620 && !TARGET_MIPS16)
622 /* ISA has three operand multiply instructions that put
623 the high part in an accumulator: mulhi or mulhiu. */
624 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
625 || TARGET_MIPS5500 \
626 || TARGET_SR71K \
627 )
629 /* ISA has three operand multiply instructions that
630 negates the result and puts the result in an accumulator. */
631 #define ISA_HAS_MULS (TARGET_MIPS5400 \
632 || TARGET_MIPS5500 \
633 || TARGET_SR71K \
634 )
636 /* ISA has three operand multiply instructions that subtracts the
637 result from a 4th operand and puts the result in an accumulator. */
638 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
639 || TARGET_MIPS5500 \
640 || TARGET_SR71K \
641 )
642 /* ISA has three operand multiply instructions that the result
643 from a 4th operand and puts the result in an accumulator. */
644 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
645 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
646 || TARGET_MIPS5400 \
647 || TARGET_MIPS5500 \
648 || TARGET_SR71K \
649 )
651 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
652 #define ISA_HAS_MACCHI (!TARGET_MIPS16 \
653 && (TARGET_MIPS4120 \
654 || TARGET_MIPS4130))
656 /* ISA has 32-bit rotate right instruction. */
657 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
658 && (ISA_MIPS32R2 \
659 || TARGET_MIPS5400 \
660 || TARGET_MIPS5500 \
661 || TARGET_SR71K \
662 ))
664 /* ISA has 64-bit rotate right instruction. */
665 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
666 && !TARGET_MIPS16 \
667 && (TARGET_MIPS5400 \
668 || TARGET_MIPS5500 \
669 || TARGET_SR71K \
670 ))
672 /* ISA has data prefetch instructions. This controls use of 'pref'. */
673 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
674 || ISA_MIPS32 \
675 || ISA_MIPS32R2 \
676 || ISA_MIPS64) \
677 && !TARGET_MIPS16)
679 /* ISA has data indexed prefetch instructions. This controls use of
680 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
681 (prefx is a cop1x instruction, so can only be used if FP is
682 enabled.) */
683 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
684 || ISA_MIPS64) \
685 && !TARGET_MIPS16)
687 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
688 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
689 also requires TARGET_DOUBLE_FLOAT. */
690 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
692 /* ISA includes the MIPS32r2 seb and seh instructions. */
693 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
694 && (ISA_MIPS32R2 \
695 ))
697 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
698 #define ISA_HAS_EXT_INS (!TARGET_MIPS16 \
699 && (ISA_MIPS32R2 \
700 ))
702 /* True if the result of a load is not available to the next instruction.
703 A nop will then be needed between instructions like "lw $4,..."
704 and "addiu $4,$4,1". */
705 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
706 && !TARGET_MIPS3900 \
707 && !TARGET_MIPS16)
709 /* Likewise mtc1 and mfc1. */
710 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
712 /* Likewise floating-point comparisons. */
713 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
715 /* True if mflo and mfhi can be immediately followed by instructions
716 which write to the HI and LO registers.
718 According to MIPS specifications, MIPS ISAs I, II, and III need
719 (at least) two instructions between the reads of HI/LO and
720 instructions which write them, and later ISAs do not. Contradicting
721 the MIPS specifications, some MIPS IV processor user manuals (e.g.
722 the UM for the NEC Vr5000) document needing the instructions between
723 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
724 MIPS64 and later ISAs to have the interlocks, plus any specific
725 earlier-ISA CPUs for which CPU documentation declares that the
726 instructions are really interlocked. */
727 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
728 || ISA_MIPS32R2 \
729 || ISA_MIPS64 \
730 || TARGET_MIPS5500)
731 \f
732 /* Add -G xx support. */
734 #undef SWITCH_TAKES_ARG
735 #define SWITCH_TAKES_ARG(CHAR) \
738 #define OVERRIDE_OPTIONS override_options ()
740 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
742 /* Show we can debug even without a frame pointer. */
743 #define CAN_DEBUG_WITHOUT_FP
744 \f
745 /* Tell collect what flags to pass to nm. */
746 #ifndef NM_FLAGS
748 #endif
750 \f
751 #ifndef MIPS_ABI_DEFAULT
752 #define MIPS_ABI_DEFAULT ABI_32
753 #endif
755 /* Use the most portable ABI flag for the ASM specs. */
757 #if MIPS_ABI_DEFAULT == ABI_32
759 #endif
761 #if MIPS_ABI_DEFAULT == ABI_O64
763 #endif
765 #if MIPS_ABI_DEFAULT == ABI_N32
767 #endif
769 #if MIPS_ABI_DEFAULT == ABI_64
771 #endif
773 #if MIPS_ABI_DEFAULT == ABI_EABI
775 #endif
777 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
778 to the assembler. It may be overridden by subtargets. */
779 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
781 %{noasmopt:-O0} \
782 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
783 #endif
785 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
786 the assembler. It may be overridden by subtargets.
788 Beginning with gas 2.13, -mdebug must be passed to correctly handle
789 COFF debugging info. */
791 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
793 %{g} %{g0} %{g1} %{g2} %{g3} \
794 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
795 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
796 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
797 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
798 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
799 #endif
801 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
802 overridden by subtargets. */
804 #ifndef SUBTARGET_ASM_SPEC
806 #endif
808 #undef ASM_SPEC
810 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
811 %{mips32} %{mips32r2} %{mips64} \
812 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
813 %{mips3d:-mips3d} \
814 %{mdsp} \
815 %{mfix-vr4120} %{mfix-vr4130} \
816 %(subtarget_asm_optimizing_spec) \
817 %(subtarget_asm_debugging_spec) \
818 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
819 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
820 %{msym32} %{mno-sym32} \
821 %{mtune=*} %{v} \
822 %(subtarget_asm_spec)"
824 /* Extra switches sometimes passed to the linker. */
825 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
826 will interpret it as a -b option. */
828 #ifndef LINK_SPEC
830 %(endian_spec) \
831 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
832 %{bestGnum} %{shared} %{non_shared}"
836 /* Specs for the compiler proper */
838 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
839 overridden by subtargets. */
840 #ifndef SUBTARGET_CC1_SPEC
842 #endif
844 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
846 #ifndef CC1_SPEC
848 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
849 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
850 %{save-temps: } \
851 %(subtarget_cc1_spec)"
852 #endif
854 /* Preprocessor specs. */
856 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
857 overridden by subtargets. */
858 #ifndef SUBTARGET_CPP_SPEC
860 #endif
864 /* This macro defines names of additional specifications to put in the specs
865 that can be used in various specifications like CC1_SPEC. Its definition
866 is an initializer with a subgrouping for each command option.
868 Each subgrouping contains a string constant, that defines the
869 specification name, and a string constant that used by the GCC driver
870 program.
872 Do not define this macro if it does not need to do anything. */
874 #define EXTRA_SPECS \
882 SUBTARGET_EXTRA_SPECS
884 #ifndef SUBTARGET_EXTRA_SPECS
885 #define SUBTARGET_EXTRA_SPECS
886 #endif
887 \f
892 #ifndef PREFERRED_DEBUGGING_TYPE
893 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
894 #endif
896 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
898 /* By default, turn on GDB extensions. */
899 #define DEFAULT_GDB_EXTENSIONS 1
901 /* Local compiler-generated symbols must have a prefix that the assembler
902 understands. By default, this is $, although some targets (e.g.,
903 NetBSD-ELF) need to override this. */
905 #ifndef LOCAL_LABEL_PREFIX
907 #endif
909 /* By default on the mips, external symbols do not have an underscore
910 prepended, but some targets (e.g., NetBSD) require this. */
912 #ifndef USER_LABEL_PREFIX
914 #endif
916 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
917 since the length can run past this up to a continuation point. */
918 #undef DBX_CONTIN_LENGTH
919 #define DBX_CONTIN_LENGTH 1500
921 /* How to renumber registers for dbx and gdb. */
922 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
924 /* The mapping from gcc register number to DWARF 2 CFA column number. */
925 #define DWARF_FRAME_REGNUM(REG) (REG)
927 /* The DWARF 2 CFA column which tracks the return address. */
928 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
930 /* The DWARF 2 CFA column which tracks the return address from a
931 signal handler context. */
932 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
934 /* Before the prologue, RA lives in r31. */
935 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
937 /* Describe how we implement __builtin_eh_return. */
938 #define EH_RETURN_DATA_REGNO(N) \
939 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
941 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
943 /* Offsets recorded in opcodes are a multiple of this alignment factor.
944 The default for this in 64-bit mode is 8, which causes problems with
945 SFmode register saves. */
946 #define DWARF_CIE_DATA_ALIGNMENT -4
948 /* Correct the offset of automatic variables and arguments. Note that
949 the MIPS debug format wants all automatic variables and arguments
950 to be in terms of the virtual frame pointer (stack pointer before
951 any adjustment in the function), while the MIPS 3.0 linker wants
952 the frame pointer to be the stack pointer after the initial
953 adjustment. */
955 #define DEBUGGER_AUTO_OFFSET(X) \
956 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
957 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
958 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
959 \f
960 /* Target machine storage layout */
962 #define BITS_BIG_ENDIAN 0
963 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
964 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
966 /* Define this to set the endianness to use in libgcc2.c, which can
967 not depend on target_flags. */
968 #if !defined(MIPSEL) && !defined(__MIPSEL__)
969 #define LIBGCC2_WORDS_BIG_ENDIAN 1
970 #else
971 #define LIBGCC2_WORDS_BIG_ENDIAN 0
972 #endif
974 #define MAX_BITS_PER_WORD 64
976 /* Width of a word, in units (bytes). */
977 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
978 #ifndef IN_LIBGCC2
979 #define MIN_UNITS_PER_WORD 4
980 #endif
982 /* For MIPS, width of a floating point register. */
983 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
985 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
986 the next available register. */
987 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
989 /* The largest size of value that can be held in floating-point
990 registers and moved with a single instruction. */
991 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
993 /* The largest size of value that can be held in floating-point
994 registers. */
995 #define UNITS_PER_FPVALUE \
996 (TARGET_SOFT_FLOAT ? 0 \
997 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
998 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1000 /* The number of bytes in a double. */
1001 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1003 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1005 /* Set the sizes of the core types. */
1006 #define SHORT_TYPE_SIZE 16
1007 #define INT_TYPE_SIZE 32
1008 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1009 #define LONG_LONG_TYPE_SIZE 64
1011 #define FLOAT_TYPE_SIZE 32
1012 #define DOUBLE_TYPE_SIZE 64
1013 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1015 /* long double is not a fixed mode, but the idea is that, if we
1016 support long double, we also want a 128-bit integer type. */
1017 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1019 #ifdef IN_LIBGCC2
1020 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1021 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1022 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1023 # else
1024 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1025 # endif
1026 #endif
1028 /* Width in bits of a pointer. */
1029 #ifndef POINTER_SIZE
1030 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1031 #endif
1033 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1034 #define PARM_BOUNDARY BITS_PER_WORD
1036 /* Allocation boundary (in *bits*) for the code of a function. */
1037 #define FUNCTION_BOUNDARY 32
1039 /* Alignment of field after `int : 0' in a structure. */
1040 #define EMPTY_FIELD_BOUNDARY 32
1042 /* Every structure's size must be a multiple of this. */
1043 /* 8 is observed right on a DECstation and on riscos 4.02. */
1044 #define STRUCTURE_SIZE_BOUNDARY 8
1046 /* There is no point aligning anything to a rounder boundary than this. */
1047 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1049 /* All accesses must be aligned. */
1050 #define STRICT_ALIGNMENT 1
1052 /* Define this if you wish to imitate the way many other C compilers
1053 handle alignment of bitfields and the structures that contain
1054 them.
1056 The behavior is that the type written for a bit-field (`int',
1057 `short', or other integer type) imposes an alignment for the
1058 entire structure, as if the structure really did contain an
1059 ordinary field of that type. In addition, the bit-field is placed
1060 within the structure so that it would fit within such a field,
1061 not crossing a boundary for it.
1063 Thus, on most machines, a bit-field whose type is written as `int'
1064 would not cross a four-byte boundary, and would force four-byte
1065 alignment for the whole structure. (The alignment used may not
1066 be four bytes; it is controlled by the other alignment
1067 parameters.)
1069 If the macro is defined, its definition should be a C expression;
1070 a nonzero value for the expression enables this behavior. */
1072 #define PCC_BITFIELD_TYPE_MATTERS 1
1074 /* If defined, a C expression to compute the alignment given to a
1075 constant that is being placed in memory. CONSTANT is the constant
1076 and ALIGN is the alignment that the object would ordinarily have.
1077 The value of this macro is used instead of that alignment to align
1078 the object.
1080 If this macro is not defined, then ALIGN is used.
1082 The typical use of this macro is to increase alignment for string
1083 constants to be word aligned so that `strcpy' calls that copy
1084 constants can be done inline. */
1086 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1087 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1088 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1090 /* If defined, a C expression to compute the alignment for a static
1091 variable. TYPE is the data type, and ALIGN is the alignment that
1092 the object would ordinarily have. The value of this macro is used
1093 instead of that alignment to align the object.
1095 If this macro is not defined, then ALIGN is used.
1097 One use of this macro is to increase alignment of medium-size
1098 data to make it all fit in fewer cache lines. Another is to
1099 cause character arrays to be word-aligned so that `strcpy' calls
1100 that copy constants to character arrays can be done inline. */
1102 #undef DATA_ALIGNMENT
1103 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1104 ((((ALIGN) < BITS_PER_WORD) \
1105 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1106 || TREE_CODE (TYPE) == UNION_TYPE \
1107 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1110 #define PAD_VARARGS_DOWN \
1111 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1113 /* Define if operations between registers always perform the operation
1114 on the full register even if a narrower mode is specified. */
1115 #define WORD_REGISTER_OPERATIONS
1117 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1118 moves. All other references are zero extended. */
1119 #define LOAD_EXTEND_OP(MODE) \
1120 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1121 ? SIGN_EXTEND : ZERO_EXTEND)
1123 /* Define this macro if it is advisable to hold scalars in registers
1124 in a wider mode than that declared by the program. In such cases,
1125 the value is constrained to be within the bounds of the declared
1126 type, but kept valid in the wider mode. The signedness of the
1127 extension may differ from that of the type. */
1129 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1130 if (GET_MODE_CLASS (MODE) == MODE_INT \
1131 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1132 { \
1133 if ((MODE) == SImode) \
1134 (UNSIGNEDP) = 0; \
1135 (MODE) = Pmode; \
1136 }
1138 /* Define if loading short immediate values into registers sign extends. */
1139 #define SHORT_IMMEDIATES_SIGN_EXTEND
1141 /* The [d]clz instructions have the natural values at 0. */
1143 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1144 ((VALUE) = GET_MODE_BITSIZE (MODE), true)
1145 \f
1146 /* Standard register usage. */
1148 /* Number of hardware registers. We have:
1150 - 32 integer registers
1151 - 32 floating point registers
1152 - 8 condition code registers
1153 - 2 accumulator registers (hi and lo)
1154 - 32 registers each for coprocessors 0, 2 and 3
1155 - 3 fake registers:
1156 - ARG_POINTER_REGNUM
1157 - FRAME_POINTER_REGNUM
1158 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1159 - 3 dummy entries that were used at various times in the past.
1160 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1161 - 6 DSP control registers */
1163 #define FIRST_PSEUDO_REGISTER 188
1165 /* By default, fix the kernel registers ($26 and $27), the global
1166 pointer ($28) and the stack pointer ($29). This can change
1167 depending on the command-line options.
1169 Regarding coprocessor registers: without evidence to the contrary,
1170 it's best to assume that each coprocessor register has a unique
1171 use. This can be overridden, in, e.g., override_options() or
1172 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1173 for a particular target. */
1175 #define FIXED_REGISTERS \
1176 { \
1177 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1178 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1179 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1180 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1181 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1183 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1184 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1186 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1187 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1189 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1190 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1192 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1193 }
1196 /* Set up this array for o32 by default.
1198 Note that we don't mark $31 as a call-clobbered register. The idea is
1199 that it's really the call instructions themselves which clobber $31.
1200 We don't care what the called function does with it afterwards.
1202 This approach makes it easier to implement sibcalls. Unlike normal
1203 calls, sibcalls don't clobber $31, so the register reaches the
1204 called function in tact. EPILOGUE_USES says that $31 is useful
1205 to the called function. */
1207 #define CALL_USED_REGISTERS \
1208 { \
1209 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1210 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1211 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1212 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1213 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1215 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1216 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1218 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1219 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1221 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1222 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1224 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1225 }
1228 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1230 #define CALL_REALLY_USED_REGISTERS \
1232 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1233 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1235 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1236 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1238 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1240 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1241 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1246 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1247 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1249 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1250 }
1252 /* Internal macros to classify a register number as to whether it's a
1253 general purpose register, a floating point register, a
1254 multiply/divide register, or a status register. */
1256 #define GP_REG_FIRST 0
1257 #define GP_REG_LAST 31
1258 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1259 #define GP_DBX_FIRST 0
1261 #define FP_REG_FIRST 32
1262 #define FP_REG_LAST 63
1263 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1264 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1266 #define MD_REG_FIRST 64
1267 #define MD_REG_LAST 65
1268 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1269 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1271 #define ST_REG_FIRST 67
1272 #define ST_REG_LAST 74
1273 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1276 /* FIXME: renumber. */
1277 #define COP0_REG_FIRST 80
1278 #define COP0_REG_LAST 111
1279 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1281 #define COP2_REG_FIRST 112
1282 #define COP2_REG_LAST 143
1283 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1285 #define COP3_REG_FIRST 144
1286 #define COP3_REG_LAST 175
1287 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1288 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1289 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1291 #define DSP_ACC_REG_FIRST 176
1292 #define DSP_ACC_REG_LAST 181
1293 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1295 #define AT_REGNUM (GP_REG_FIRST + 1)
1296 #define HI_REGNUM (MD_REG_FIRST + 0)
1297 #define LO_REGNUM (MD_REG_FIRST + 1)
1298 #define AC1HI_REGNUM (DSP_ACC_REG_FIRST + 0)
1299 #define AC1LO_REGNUM (DSP_ACC_REG_FIRST + 1)
1300 #define AC2HI_REGNUM (DSP_ACC_REG_FIRST + 2)
1301 #define AC2LO_REGNUM (DSP_ACC_REG_FIRST + 3)
1302 #define AC3HI_REGNUM (DSP_ACC_REG_FIRST + 4)
1303 #define AC3LO_REGNUM (DSP_ACC_REG_FIRST + 5)
1305 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1306 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1307 should be used instead. */
1308 #define FPSW_REGNUM ST_REG_FIRST
1310 #define GP_REG_P(REGNO) \
1311 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1312 #define M16_REG_P(REGNO) \
1313 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1314 #define FP_REG_P(REGNO) \
1315 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1316 #define MD_REG_P(REGNO) \
1317 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1318 #define ST_REG_P(REGNO) \
1319 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1320 #define COP0_REG_P(REGNO) \
1321 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1322 #define COP2_REG_P(REGNO) \
1323 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1324 #define COP3_REG_P(REGNO) \
1325 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1326 #define ALL_COP_REG_P(REGNO) \
1327 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1328 /* Test if REGNO is one of the 6 new DSP accumulators. */
1329 #define DSP_ACC_REG_P(REGNO) \
1330 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1331 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1332 #define ACC_REG_P(REGNO) \
1333 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1334 /* Test if REGNO is HI or the first register of 3 new DSP accumulator pairs. */
1335 #define ACC_HI_REG_P(REGNO) \
1336 ((REGNO) == HI_REGNUM || (REGNO) == AC1HI_REGNUM || (REGNO) == AC2HI_REGNUM \
1337 || (REGNO) == AC3HI_REGNUM)
1339 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1341 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1342 to initialize the mips16 gp pseudo register. */
1343 #define CONST_GP_P(X) \
1344 (GET_CODE (X) == CONST \
1345 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1346 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1348 /* Return coprocessor number from register number. */
1350 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1355 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1357 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1358 array built in override_options. Because machmodes.h is not yet
1359 included before this file is processed, the MODE bound can't be
1360 expressed here. */
1364 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1365 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1367 /* Value is 1 if it is a good idea to tie two pseudo registers
1368 when one has mode MODE1 and one has mode MODE2.
1369 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1370 for any hard reg, then this must be 0 for correct output. */
1371 #define MODES_TIEABLE_P(MODE1, MODE2) \
1372 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1373 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1374 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1375 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1377 /* Register to use for pushing function arguments. */
1378 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1380 /* These two registers don't really exist: they get eliminated to either
1381 the stack or hard frame pointer. */
1382 #define ARG_POINTER_REGNUM 77
1383 #define FRAME_POINTER_REGNUM 78
1385 /* $30 is not available on the mips16, so we use $17 as the frame
1386 pointer. */
1387 #define HARD_FRAME_POINTER_REGNUM \
1388 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1390 /* Value should be nonzero if functions must have frame pointers.
1391 Zero means the frame pointer need not be set up (and parms
1392 may be accessed via the stack pointer) in functions that seem suitable.
1393 This is computed in `reload', in reload1.c. */
1394 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1396 /* Register in which static-chain is passed to a function. */
1397 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1399 /* Registers used as temporaries in prologue/epilogue code. If we're
1400 generating mips16 code, these registers must come from the core set
1401 of 8. The prologue register mustn't conflict with any incoming
1402 arguments, the static chain pointer, or the frame pointer. The
1403 epilogue temporary mustn't conflict with the return registers, the
1404 frame pointer, the EH stack adjustment, or the EH data registers. */
1406 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1407 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1409 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1410 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1412 /* Define this macro if it is as good or better to call a constant
1413 function address than to call an address kept in a register. */
1414 #define NO_FUNCTION_CSE 1
1416 /* The ABI-defined global pointer. Sometimes we use a different
1417 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1418 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1420 /* We normally use $28 as the global pointer. However, when generating
1421 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1422 register instead. They can then avoid saving and restoring $28
1423 and perhaps avoid using a frame at all.
1425 When a leaf function uses something other than $28, mips_expand_prologue
1426 will modify pic_offset_table_rtx in place. Take the register number
1427 from there after reload. */
1428 #define PIC_OFFSET_TABLE_REGNUM \
1429 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1431 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1432 \f
1433 /* Define the classes of registers for register constraints in the
1434 machine description. Also define ranges of constants.
1436 One of the classes must always be named ALL_REGS and include all hard regs.
1437 If there is more than one class, another class must be named NO_REGS
1438 and contain no registers.
1440 The name GENERAL_REGS must be the name of a class (or an alias for
1441 another name such as ALL_REGS). This is the class of registers
1442 that is allowed by "g" or "r" in a register constraint.
1443 Also, registers outside this class are allocated only when
1444 instructions express preferences for them.
1446 The classes must be numbered in nondecreasing order; that is,
1447 a larger-numbered class must never be contained completely
1448 in a smaller-numbered class.
1450 For any two classes, it is very desirable that there be another
1451 class that represents their union. */
1453 enum reg_class
1454 {
1469 COP2_REGS,
1470 COP3_REGS,
1472 LO_AND_GR_REGS,
1473 HI_AND_FP_REGS,
1474 COP0_AND_GR_REGS,
1475 COP2_AND_GR_REGS,
1476 COP3_AND_GR_REGS,
1477 ALL_COP_REGS,
1478 ALL_COP_AND_GR_REGS,
1483 LIM_REG_CLASSES /* max value + 1 */
1484 };
1486 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1488 #define GENERAL_REGS GR_REGS
1490 /* An initializer containing the names of the register classes as C
1491 string constants. These names are used in writing some of the
1492 debugging dumps. */
1494 #define REG_CLASS_NAMES \
1495 { \
1525 }
1527 /* An initializer containing the contents of the register classes,
1528 as integers which are bit masks. The Nth integer specifies the
1529 contents of class N. The way the integer MASK is interpreted is
1530 that register R is in the class if `MASK & (1 << R)' is 1.
1532 When the machine has more than 32 registers, an integer does not
1533 suffice. Then the integers are replaced by sub-initializers,
1534 braced groupings containing several integers. Each
1535 sub-initializer must be suitable as an initializer for the type
1536 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1538 #define REG_CLASS_CONTENTS \
1539 { \
1540 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1541 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1542 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1543 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1544 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1545 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1547 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1548 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1549 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1550 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1551 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1552 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1553 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1554 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1555 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1556 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1557 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1558 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1559 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1560 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1561 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1562 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1563 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1564 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1565 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1566 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1567 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1568 }
1571 /* A C expression whose value is a register class containing hard
1572 register REGNO. In general there is more that one such class;
1573 choose a class which is "minimal", meaning that no smaller class
1574 also contains the register. */
1578 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1580 /* A macro whose definition is the name of the class to which a
1581 valid base register must belong. A base register is one used in
1582 an address which is the register value plus a displacement. */
1584 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1586 /* A macro whose definition is the name of the class to which a
1587 valid index register must belong. An index register is one used
1588 in an address where its value is either multiplied by a scale
1589 factor or added to another register (as well as added to a
1590 displacement). */
1592 #define INDEX_REG_CLASS NO_REGS
1594 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1595 registers explicitly used in the rtl to be used as spill registers
1596 but prevents the compiler from extending the lifetime of these
1597 registers. */
1599 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1601 /* This macro is used later on in the file. */
1602 #define GR_REG_CLASS_P(CLASS) \
1603 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1604 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1605 || (CLASS) == V1_REG \
1606 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1608 /* This macro is also used later on in the file. */
1609 #define COP_REG_CLASS_P(CLASS) \
1610 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1612 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1613 is the default value (allocate the registers in numeric order). We
1614 define it just so that we can override it for the mips16 target in
1615 ORDER_REGS_FOR_LOCAL_ALLOC. */
1617 #define REG_ALLOC_ORDER \
1618 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1619 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1620 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1621 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1622 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1623 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1624 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1625 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1626 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1627 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1628 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1629 176,177,178,179,180,181,182,183,184,185,186,187 \
1630 }
1632 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1633 to be rearranged based on a particular function. On the mips16, we
1634 want to allocate $24 (T_REG) before other registers for
1635 instructions for which it is possible. */
1637 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1639 /* REGISTER AND CONSTANT CLASSES */
1641 /* Get reg_class from a letter such as appears in the machine
1642 description.
1644 DEFINED REGISTER CLASSES:
1646 'd' General (aka integer) registers
1647 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1648 'y' General registers (in both mips16 and non mips16 mode)
1649 'e' Effective address registers (general registers except $25)
1650 't' mips16 temporary register ($24)
1651 'f' Floating point registers
1652 'h' Hi register
1653 'l' Lo register
1654 'v' $v1 only
1655 'x' Multiply/divide registers
1656 'z' FP Status register
1657 'B' Cop0 register
1658 'C' Cop2 register
1659 'D' Cop3 register
1660 'A' DSP accumulator registers
1661 'a' MD registers and DSP accumulator registers
1662 'b' All registers */
1666 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1668 /* True if VALUE is an unsigned 6-bit number. */
1670 #define UIMM6_OPERAND(VALUE) \
1671 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1673 /* True if VALUE is a signed 10-bit number. */
1675 #define IMM10_OPERAND(VALUE) \
1676 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1678 /* True if VALUE is a signed 16-bit number. */
1680 #define SMALL_OPERAND(VALUE) \
1681 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1683 /* True if VALUE is an unsigned 16-bit number. */
1685 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1686 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1688 /* True if VALUE can be loaded into a register using LUI. */
1690 #define LUI_OPERAND(VALUE) \
1691 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1692 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1694 /* Return a value X with the low 16 bits clear, and such that
1695 VALUE - X is a signed 16-bit value. */
1697 #define CONST_HIGH_PART(VALUE) \
1698 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1700 #define CONST_LOW_PART(VALUE) \
1701 ((VALUE) - CONST_HIGH_PART (VALUE))
1703 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1704 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1705 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1707 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1708 string can be used to stand for particular ranges of immediate
1709 operands. This macro defines what the ranges are. C is the
1710 letter, and VALUE is a constant value. Return 1 if VALUE is
1711 in the range specified by C. */
1713 /* For MIPS:
1715 `I' is used for the range of constants an arithmetic insn can
1716 actually contain (16 bits signed integers).
1718 `J' is used for the range which is just zero (i.e., $r0).
1720 `K' is used for the range of constants a logical insn can actually
1721 contain (16 bit zero-extended integers).
1723 `L' is used for the range of constants that be loaded with lui
1724 (i.e., the bottom 16 bits are zero).
1726 `M' is used for the range of constants that take two words to load
1727 (i.e., not matched by `I', `K', and `L').
1729 `N' is used for negative 16 bit constants other than -65536.
1731 `O' is a 15 bit signed integer.
1733 `P' is used for positive 16 bit constants. */
1735 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1741 && !SMALL_OPERAND_UNSIGNED (VALUE) \
1742 && !LUI_OPERAND (VALUE)) \
1746 : 0)
1748 /* Similar, but for floating constants, and defining letters G and H.
1749 Here VALUE is the CONST_DOUBLE rtx itself. */
1751 /* For MIPS
1753 'G' : Floating point 0 */
1755 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1757 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1759 /* Letters in the range `Q' through `U' may be defined in a
1760 machine-dependent fashion to stand for arbitrary operand types.
1761 The machine description macro `EXTRA_CONSTRAINT' is passed the
1762 operand as its first argument and the constraint letter as its
1763 second operand.
1765 `Q' is for signed 16-bit constants.
1766 `R' is for single-instruction memory references. Note that this
1767 constraint has often been used in linux and glibc code.
1768 `S' is for legitimate constant call addresses.
1769 `T' is for constant move_operands that cannot be safely loaded into $25.
1770 `U' is for constant move_operands that can be safely loaded into $25.
1771 `W' is for memory references that are based on a member of BASE_REG_CLASS.
1772 This is true for all non-mips16 references (although it can sometimes
1773 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
1774 stack and constant-pool references.
1775 `YG' is for 0 valued vector constants.
1776 `YA' is for unsigned 6-bit constants.
1777 `YB' is for signed 10-bit constants. */
1779 #define EXTRA_CONSTRAINT_Y(OP,STR) \
1781 && (OP) == CONST0_RTX (GET_MODE (OP))) \
1783 && UIMM6_OPERAND (INTVAL (OP))) \
1785 && IMM10_OPERAND (INTVAL (OP))) \
1786 : FALSE)
1789 #define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \
1792 && mips_fetch_insns (OP) == 1) \
1794 && call_insn_operand (OP, VOIDmode)) \
1796 && move_operand (OP, VOIDmode) \
1797 && mips_dangerous_for_la25_p (OP)) \
1799 && move_operand (OP, VOIDmode) \
1800 && !mips_dangerous_for_la25_p (OP)) \
1802 && memory_operand (OP, VOIDmode) \
1803 && (!TARGET_MIPS16 \
1804 || (!stack_operand (OP, VOIDmode) \
1805 && !CONSTANT_P (XEXP (OP, 0))))) \
1807 : FALSE)
1809 /* Y is the only multi-letter constraint, and has length 2. */
1811 #define CONSTRAINT_LEN(C,STR) \
1813 : DEFAULT_CONSTRAINT_LEN (C, STR))
1815 /* Say which of the above are memory constraints. */
1818 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1819 mips_preferred_reload_class (X, CLASS)
1821 /* Certain machines have the property that some registers cannot be
1822 copied to some other registers without using memory. Define this
1823 macro on those machines to be a C expression that is nonzero if
1824 objects of mode MODE in registers of CLASS1 can only be copied to
1825 registers of class CLASS2 by storing a register of CLASS1 into
1826 memory and loading that memory location into a register of CLASS2.
1828 Do not define this macro if its value would always be zero. */
1829 #if 0
1830 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1831 ((!TARGET_DEBUG_H_MODE \
1832 && GET_MODE_CLASS (MODE) == MODE_INT \
1833 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1834 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1835 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1836 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1837 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1838 #endif
1839 /* The HI and LO registers can only be reloaded via the general
1840 registers. Condition code registers can only be loaded to the
1841 general registers, and from the floating point registers. */
1843 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1844 mips_secondary_reload_class (CLASS, MODE, X, 1)
1845 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1846 mips_secondary_reload_class (CLASS, MODE, X, 0)
1848 /* Return the maximum number of consecutive registers
1849 needed to represent mode MODE in a register of class CLASS. */
1851 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1853 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1854 mips_cannot_change_mode_class (FROM, TO, CLASS)
1855 \f
1856 /* Stack layout; function entry, exit and calling. */
1858 #define STACK_GROWS_DOWNWARD
1860 /* The offset of the first local variable from the beginning of the frame.
1861 See compute_frame_size for details about the frame layout.
1863 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1864 we assume that we will need 16 bytes of argument space. This is because
1865 the value profiling code may emit calls to cmpdi2 in leaf functions.
1866 Without this hack, the local variables will start at sp+8 and the gp save
1867 area will be at sp+16, and thus they will overlap. compute_frame_size is
1868 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1869 will end up as 24 instead of 8. This won't be needed if profiling code is
1870 inserted before virtual register instantiation. */
1872 #define STARTING_FRAME_OFFSET \
1873 ((flag_profile_values && ! TARGET_64BIT \
1874 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1875 : current_function_outgoing_args_size) \
1876 + (TARGET_ABICALLS && !TARGET_NEWABI \
1877 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1879 #define RETURN_ADDR_RTX mips_return_addr
1881 /* Since the mips16 ISA mode is encoded in the least-significant bit
1882 of the address, mask it off return addresses for purposes of
1883 finding exception handling regions. */
1885 #define MASK_RETURN_ADDR GEN_INT (-2)
1888 /* Similarly, don't use the least-significant bit to tell pointers to
1889 code from vtable index. */
1891 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1893 /* The eliminations to $17 are only used for mips16 code. See the
1894 definition of HARD_FRAME_POINTER_REGNUM. */
1896 #define ELIMINABLE_REGS \
1897 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1898 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1899 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1900 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1901 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1902 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1904 /* We can always eliminate to the hard frame pointer. We can eliminate
1905 to the stack pointer unless a frame pointer is needed.
1907 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1908 reload may be unable to compute the address of a local variable,
1909 since there is no way to add a large constant to the stack pointer
1910 without using a temporary register. */
1911 #define CAN_ELIMINATE(FROM, TO) \
1912 ((TO) == HARD_FRAME_POINTER_REGNUM \
1913 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1914 && (!TARGET_MIPS16 \
1915 || compute_frame_size (get_frame_size ()) < 32768)))
1917 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1918 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1920 /* Allocate stack space for arguments at the beginning of each function. */
1921 #define ACCUMULATE_OUTGOING_ARGS 1
1923 /* The argument pointer always points to the first argument. */
1924 #define FIRST_PARM_OFFSET(FNDECL) 0
1926 /* o32 and o64 reserve stack space for all argument registers. */
1927 #define REG_PARM_STACK_SPACE(FNDECL) \
1928 (TARGET_OLDABI \
1929 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1930 : 0)
1932 /* Define this if it is the responsibility of the caller to
1933 allocate the area reserved for arguments passed in registers.
1934 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1935 of this macro is to determine whether the space is included in
1936 `current_function_outgoing_args_size'. */
1937 #define OUTGOING_REG_PARM_STACK_SPACE
1939 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1940 \f
1941 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1943 /* Symbolic macros for the registers used to return integer and floating
1944 point values. */
1946 #define GP_RETURN (GP_REG_FIRST + 2)
1947 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1949 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1951 /* Symbolic macros for the first/last argument registers. */
1953 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1954 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1955 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1956 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1958 #define LIBCALL_VALUE(MODE) \
1959 mips_function_value (NULL_TREE, NULL, (MODE))
1961 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1962 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1964 /* 1 if N is a possible register number for a function value.
1965 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1966 Currently, R2 and F0 are only implemented here (C has no complex type) */
1968 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1969 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1970 && (N) == FP_RETURN + 2))
1972 /* 1 if N is a possible register number for function argument passing.
1973 We have no FP argument registers when soft-float. When FP registers
1974 are 32 bits, we can't directly reference the odd numbered ones. */
1976 #define FUNCTION_ARG_REGNO_P(N) \
1977 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1978 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1979 && !fixed_regs[N])
1980 \f
1981 /* This structure has to cope with two different argument allocation
1982 schemes. Most MIPS ABIs view the arguments as a structure, of which
1983 the first N words go in registers and the rest go on the stack. If I
1984 < N, the Ith word might go in Ith integer argument register or in a
1985 floating-point register. For these ABIs, we only need to remember
1986 the offset of the current argument into the structure.
1988 The EABI instead allocates the integer and floating-point arguments
1989 separately. The first N words of FP arguments go in FP registers,
1990 the rest go on the stack. Likewise, the first N words of the other
1991 arguments go in integer registers, and the rest go on the stack. We
1992 need to maintain three counts: the number of integer registers used,
1993 the number of floating-point registers used, and the number of words
1994 passed on the stack.
1996 We could keep separate information for the two ABIs (a word count for
1997 the standard ABIs, and three separate counts for the EABI). But it
1998 seems simpler to view the standard ABIs as forms of EABI that do not
1999 allocate floating-point registers.
2001 So for the standard ABIs, the first N words are allocated to integer
2002 registers, and function_arg decides on an argument-by-argument basis
2003 whether that argument should really go in an integer register, or in
2004 a floating-point one. */
2007 /* Always true for varargs functions. Otherwise true if at least
2008 one argument has been passed in an integer register. */
2011 /* The number of arguments seen so far. */
2014 /* The number of integer registers used so far. For all ABIs except
2015 EABI, this is the number of words that have been added to the
2016 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2019 /* For EABI, the number of floating-point registers used so far. */
2022 /* The number of words passed on the stack. */
2025 /* On the mips16, we need to keep track of which floating point
2026 arguments were passed in general registers, but would have been
2027 passed in the FP regs if this were a 32 bit function, so that we
2028 can move them to the FP regs if we wind up calling a 32 bit
2029 function. We record this information in fp_code, encoded in base
2030 four. A zero digit means no floating point argument, a one digit
2031 means an SFmode argument, and a two digit means a DFmode argument,
2032 and a three digit is not used. The low order digit is the first
2033 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2034 an SFmode argument. ??? A more sophisticated approach will be
2035 needed if MIPS_ABI != ABI_32. */
2038 /* True if the function has a prototype. */
2042 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2043 for a call to a function whose data type is FNTYPE.
2044 For a library call, FNTYPE is 0. */
2046 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2047 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2049 /* Update the data in CUM to advance over an argument
2050 of mode MODE and data type TYPE.
2051 (TYPE is null for libcalls where that information may not be available.) */
2053 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2054 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2056 /* Determine where to put an argument to a function.
2057 Value is zero to push the argument on the stack,
2058 or a hard register in which to store the argument.
2060 MODE is the argument's machine mode.
2061 TYPE is the data type of the argument (as a tree).
2062 This is null for libcalls where that information may
2063 not be available.
2064 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2065 the preceding args and about the function being called.
2066 NAMED is nonzero if this argument is a named parameter
2067 (otherwise it is an extra parameter matching an ellipsis). */
2069 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2070 function_arg( &CUM, MODE, TYPE, NAMED)
2072 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2074 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2075 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2077 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2078 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2080 /* True if using EABI and varargs can be passed in floating-point
2081 registers. Under these conditions, we need a more complex form
2082 of va_list, which tracks GPR, FPR and stack arguments separately. */
2083 #define EABI_FLOAT_VARARGS_P \
2084 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2086 \f
2087 /* Say that the epilogue uses the return address register. Note that
2088 in the case of sibcalls, the values "used by the epilogue" are
2089 considered live at the start of the called function. */
2090 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2092 /* Treat LOC as a byte offset from the stack pointer and round it up
2093 to the next fully-aligned offset. */
2094 #define MIPS_STACK_ALIGN(LOC) \
2095 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2097 \f
2098 /* Implement `va_start' for varargs and stdarg. */
2099 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2100 mips_va_start (valist, nextarg)
2101 \f
2102 /* Output assembler code to FILE to increment profiler label # LABELNO
2103 for profiling a function entry. */
2105 #define FUNCTION_PROFILER(FILE, LABELNO) \
2106 { \
2107 if (TARGET_MIPS16) \
2111 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2112 if (!TARGET_NEWABI) \
2113 { \
2114 fprintf (FILE, \
2117 reg_names[STACK_POINTER_REGNUM], \
2118 reg_names[STACK_POINTER_REGNUM], \
2119 Pmode == DImode ? 16 : 8); \
2120 } \
2123 }
2125 /* No mips port has ever used the profiler counter word, so don't emit it
2126 or the label for it. */
2128 #define NO_PROFILE_COUNTERS 1
2130 /* Define this macro if the code for function profiling should come
2131 before the function prologue. Normally, the profiling code comes
2132 after. */
2134 /* #define PROFILE_BEFORE_PROLOGUE */
2136 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2137 the stack pointer does not matter. The value is tested only in
2138 functions that have frame pointers.
2139 No definition is equivalent to always zero. */
2141 #define EXIT_IGNORE_STACK 1
2143 \f
2144 /* A C statement to output, on the stream FILE, assembler code for a
2145 block of data that contains the constant parts of a trampoline.
2146 This code should not include a label--the label is taken care of
2147 automatically. */
2149 #define TRAMPOLINE_TEMPLATE(STREAM) \
2150 { \
2154 if (ptr_mode == DImode) \
2155 { \
2158 } \
2159 else \
2160 { \
2163 } \
2167 if (ptr_mode == DImode) \
2168 { \
2171 } \
2172 else \
2173 { \
2176 } \
2177 }
2179 /* A C expression for the size in bytes of the trampoline, as an
2180 integer. */
2182 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2184 /* Alignment required for trampolines, in bits. */
2186 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2188 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2189 program and data caches. */
2191 #ifndef CACHE_FLUSH_FUNC
2193 #endif
2195 /* A C statement to initialize the variable parts of a trampoline.
2196 ADDR is an RTX for the address of the trampoline; FNADDR is an
2197 RTX for the address of the nested function; STATIC_CHAIN is an
2198 RTX for the static chain value that should be passed to the
2199 function when it is called. */
2201 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2202 { \
2203 rtx func_addr, chain_addr; \
2204 \
2205 func_addr = plus_constant (ADDR, 32); \
2206 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2207 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2208 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2209 \
2210 /* Flush both caches. We need to flush the data cache in case \
2213 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2214 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2215 0, VOIDmode, 3, ADDR, Pmode, \
2216 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2217 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2218 }
2219 \f
2220 /* Addressing modes, and classification of registers for them. */
2222 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2223 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2224 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2226 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2227 and check its validity for a certain class.
2228 We have two alternate definitions for each of them.
2229 The usual definition accepts all pseudo regs; the other rejects them all.
2230 The symbol REG_OK_STRICT causes the latter definition to be used.
2232 Most source files want to accept pseudo regs in the hope that
2233 they will get allocated to the class that the insn wants them to be in.
2234 Some source files that are used after register allocation
2235 need to be strict. */
2237 #ifndef REG_OK_STRICT
2238 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2239 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2240 #else
2241 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2242 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2243 #endif
2245 #define REG_OK_FOR_INDEX_P(X) 0
2247 \f
2248 /* Maximum number of registers that can appear in a valid memory address. */
2250 #define MAX_REGS_PER_ADDRESS 1
2252 #ifdef REG_OK_STRICT
2253 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2254 { \
2255 if (mips_legitimate_address_p (MODE, X, 1)) \
2256 goto ADDR; \
2257 }
2258 #else
2259 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2260 { \
2261 if (mips_legitimate_address_p (MODE, X, 0)) \
2262 goto ADDR; \
2263 }
2264 #endif
2266 /* Check for constness inline but use mips_legitimate_address_p
2267 to check whether a constant really is an address. */
2269 #define CONSTANT_ADDRESS_P(X) \
2270 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2272 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2274 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2275 do { \
2276 if (mips_legitimize_address (&(X), MODE)) \
2277 goto WIN; \
2278 } while (0)
2281 /* A C statement or compound statement with a conditional `goto
2282 LABEL;' executed if memory address X (an RTX) can have different
2283 meanings depending on the machine mode of the memory reference it
2284 is used for.
2286 Autoincrement and autodecrement addresses typically have
2287 mode-dependent effects because the amount of the increment or
2288 decrement is the size of the operand being addressed. Some
2289 machines have other mode-dependent addresses. Many RISC machines
2290 have no mode-dependent addresses.
2292 You may assume that ADDR is a valid address for the machine. */
2294 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2296 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2297 'the start of the function that this code is output in'. */
2299 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2302 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2303 else \
2305 \f
2306 /* Flag to mark a function decl symbol that requires a long call. */
2307 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2308 #define SYMBOL_REF_LONG_CALL_P(X) \
2309 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2311 /* Specify the machine mode that this machine uses
2312 for the index in the tablejump instruction.
2313 ??? Using HImode in mips16 mode can cause overflow. */
2314 #define CASE_VECTOR_MODE \
2315 (TARGET_MIPS16 ? HImode : ptr_mode)
2317 /* Define as C expression which evaluates to nonzero if the tablejump
2318 instruction expects the table to contain offsets from the address of the
2319 table.
2320 Do not define this if the table should contain absolute addresses. */
2321 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2323 /* Define this as 1 if `char' should by default be signed; else as 0. */
2324 #ifndef DEFAULT_SIGNED_CHAR
2325 #define DEFAULT_SIGNED_CHAR 1
2326 #endif
2328 /* Max number of bytes we can move from memory to memory
2329 in one reasonably fast instruction. */
2330 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2331 #define MAX_MOVE_MAX 8
2333 /* Define this macro as a C expression which is nonzero if
2334 accessing less than a word of memory (i.e. a `char' or a
2335 `short') is no faster than accessing a word of memory, i.e., if
2336 such access require more than one instruction or if there is no
2337 difference in cost between byte and (aligned) word loads.
2339 On RISC machines, it tends to generate better code to define
2340 this as 1, since it avoids making a QI or HI mode register. */
2341 #define SLOW_BYTE_ACCESS 1
2343 /* Define this to be nonzero if shift instructions ignore all but the low-order
2344 few bits. */
2345 #define SHIFT_COUNT_TRUNCATED 1
2347 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2348 is done just by pretending it is already truncated. */
2349 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2350 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2353 /* Specify the machine mode that pointers have.
2354 After generation of rtl, the compiler makes no further distinction
2355 between pointers and any other objects of this machine mode. */
2357 #ifndef Pmode
2358 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2359 #endif
2361 /* Give call MEMs SImode since it is the "most permissive" mode
2362 for both 32-bit and 64-bit targets. */
2364 #define FUNCTION_MODE SImode
2366 \f
2367 /* The cost of loading values from the constant pool. It should be
2368 larger than the cost of any constant we want to synthesize in-line. */
2370 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2372 /* A C expression for the cost of moving data from a register in
2373 class FROM to one in class TO. The classes are expressed using
2374 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2375 the default; other values are interpreted relative to that.
2377 It is not required that the cost always equal 2 when FROM is the
2378 same as TO; on some machines it is expensive to move between
2379 registers if they are not general registers.
2381 If reload sees an insn consisting of a single `set' between two
2382 hard registers, and if `REGISTER_MOVE_COST' applied to their
2383 classes returns a value of 2, reload does not check to ensure
2384 that the constraints of the insn are met. Setting a cost of
2385 other than 2 will allow reload to verify that the constraints are
2386 met. You should do this if the `movM' pattern's constraints do
2387 not allow such copying. */
2389 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2390 mips_register_move_cost (MODE, FROM, TO)
2392 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2393 (mips_cost->memory_latency \
2394 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2396 /* Define if copies to/from condition code registers should be avoided.
2398 This is needed for the MIPS because reload_outcc is not complete;
2399 it needs to handle cases where the source is a general or another
2400 condition code register. */
2401 #define AVOID_CCMODE_COPIES
2403 /* A C expression for the cost of a branch instruction. A value of
2404 1 is the default; other values are interpreted relative to that. */
2406 #define BRANCH_COST mips_cost->branch_cost
2407 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2409 /* If defined, modifies the length assigned to instruction INSN as a
2410 function of the context in which it is used. LENGTH is an lvalue
2411 that contains the initially computed length of the insn and should
2412 be updated with the correct length of the insn. */
2413 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2414 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2415 \f
2416 /* Control the assembler format that we output. */
2418 /* Output to assembler file text saying following lines
2419 may contain character constants, extra white space, comments, etc. */
2421 #ifndef ASM_APP_ON
2423 #endif
2425 /* Output to assembler file text saying following lines
2426 no longer contain unusual constructs. */
2428 #ifndef ASM_APP_OFF
2430 #endif
2432 #define REGISTER_NAMES \
2458 /* List the "software" names for each register. Also list the numerical
2459 names for $fp and $sp. */
2461 #define ADDITIONAL_REGISTER_NAMES \
2462 { \
2496 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2497 }
2499 /* This is meant to be redefined in the host dependent files. It is a
2500 set of alternative names and regnums for mips coprocessors. */
2502 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2504 /* A C compound statement to output to stdio stream STREAM the
2505 assembler syntax for an instruction operand X. X is an RTL
2506 expression.
2508 CODE is a value that can be used to specify one of several ways
2509 of printing the operand. It is used when identical operands
2510 must be printed differently depending on the context. CODE
2511 comes from the `%' specification that was used to request
2512 printing of the operand. If the specification was just `%DIGIT'
2513 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2514 is the ASCII code for LTR.
2516 If X is a register, this macro should print the register's name.
2517 The names can be found in an array `reg_names' whose type is
2518 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2520 When the machine description has a specification `%PUNCT' (a `%'
2521 followed by a punctuation character), this macro is called with
2522 a null pointer for X and the punctuation character for CODE.
2524 See mips.c for the MIPS specific codes. */
2526 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2528 /* A C expression which evaluates to true if CODE is a valid
2529 punctuation character for use in the `PRINT_OPERAND' macro. If
2530 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2531 punctuation characters (except for the standard one, `%') are
2532 used in this way. */
2534 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2536 /* A C compound statement to output to stdio stream STREAM the
2537 assembler syntax for an instruction operand that is a memory
2538 reference whose address is ADDR. ADDR is an RTL expression. */
2540 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2543 /* A C statement, to be executed after all slot-filler instructions
2544 have been output. If necessary, call `dbr_sequence_length' to
2545 determine the number of slots filled in a sequence (zero if not
2546 currently outputting a sequence), to decide how many no-ops to
2547 output, or whatever.
2549 Don't define this macro if it has nothing to do, but it is
2550 helpful in reading assembly output if the extent of the delay
2551 sequence is made explicit (e.g. with white space).
2553 Note that output routines for instructions with delay slots must
2554 be prepared to deal with not being output as part of a sequence
2555 (i.e. when the scheduling pass is not run, or when no slot
2556 fillers could be found.) The variable `final_sequence' is null
2557 when not processing a sequence, otherwise it contains the
2558 `sequence' rtx being output. */
2560 #define DBR_OUTPUT_SEQEND(STREAM) \
2561 do \
2562 { \
2563 if (set_nomacro > 0 && --set_nomacro == 0) \
2565 \
2566 if (set_noreorder > 0 && --set_noreorder == 0) \
2568 \
2570 } \
2571 while (0)
2574 /* How to tell the debugger about changes of source files. */
2575 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2576 mips_output_filename (STREAM, NAME)
2578 /* mips-tfile does not understand .stabd directives. */
2579 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2580 dbxout_begin_stabn_sline (LINE); \
2582 } while (0)
2584 /* Use .loc directives for SDB line numbers. */
2585 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2588 /* The MIPS implementation uses some labels for its own purpose. The
2589 following lists what labels are created, and are all formed by the
2590 pattern $L[a-z].*. The machine independent portion of GCC creates
2591 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2593 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2594 $Lb[0-9]+ Begin blocks for MIPS debug support
2595 $Lc[0-9]+ Label for use in s<xx> operation.
2596 $Le[0-9]+ End blocks for MIPS debug support */
2598 #undef ASM_DECLARE_OBJECT_NAME
2599 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2602 /* Globalizing directive for a label. */
2605 /* This says how to define a global common symbol. */
2607 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2609 /* This says how to define a local common symbol (i.e., not visible to
2610 linker). */
2612 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2613 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2615 #endif
2617 /* This says how to output an external. It would be possible not to
2618 output anything and let undefined symbol become external. However
2619 the assembler uses length information on externals to allocate in
2620 data/sdata bss/sbss, thereby saving exec time. */
2622 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2623 mips_output_external(STREAM,DECL,NAME)
2625 /* This is how to declare a function name. The actual work of
2626 emitting the label is moved to function_prologue, so that we can
2627 get the line number correctly emitted before the .ent directive,
2628 and after any .file directives. Define as empty so that the function
2629 is not declared before the .ent directive elsewhere. */
2631 #undef ASM_DECLARE_FUNCTION_NAME
2632 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2634 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2635 #define FUNCTION_NAME_ALREADY_DECLARED 0
2636 #endif
2638 /* This is how to store into the string LABEL
2639 the symbol_ref name of an internal numbered label where
2640 PREFIX is the class of label and NUM is the number within the class.
2641 This is suitable for output with `assemble_name'. */
2643 #undef ASM_GENERATE_INTERNAL_LABEL
2644 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2647 /* This is how to output an element of a case-vector that is absolute. */
2649 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2652 LOCAL_LABEL_PREFIX, \
2653 VALUE)
2655 /* This is how to output an element of a case-vector. We can make the
2656 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2657 is supported. */
2659 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2660 do { \
2661 if (TARGET_MIPS16) \
2663 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2664 else if (TARGET_GPWORD) \
2667 LOCAL_LABEL_PREFIX, VALUE); \
2668 else \
2671 LOCAL_LABEL_PREFIX, VALUE); \
2672 } while (0)
2674 /* When generating MIPS16 code, we want the jump table to be in the text
2675 section so that we can load its address using a PC-relative addition. */
2676 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
2678 /* This is how to output an assembler line
2679 that says to advance the location counter
2680 to a multiple of 2**LOG bytes. */
2682 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2685 /* This is how to output an assembler line to advance the location
2686 counter by SIZE bytes. */
2688 #undef ASM_OUTPUT_SKIP
2689 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2692 /* This is how to output a string. */
2693 #undef ASM_OUTPUT_ASCII
2694 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2697 /* Output #ident as a in the read-only data section. */
2698 #undef ASM_OUTPUT_IDENT
2699 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2700 { \
2701 const char *p = STRING; \
2702 int size = strlen (p) + 1; \
2703 switch_to_section (readonly_data_section); \
2704 assemble_string (p, size); \
2705 }
2706 \f
2707 /* Default to -G 8 */
2708 #ifndef MIPS_DEFAULT_GVALUE
2709 #define MIPS_DEFAULT_GVALUE 8
2710 #endif
2712 /* Define the strings to put out for each section in the object file. */
2716 #undef READONLY_DATA_SECTION_ASM_OP
2718 \f
2719 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2720 do \
2721 { \
2724 reg_names[STACK_POINTER_REGNUM], \
2725 reg_names[STACK_POINTER_REGNUM], \
2727 reg_names[REGNO], \
2728 reg_names[STACK_POINTER_REGNUM]); \
2729 } \
2730 while (0)
2732 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2733 do \
2734 { \
2735 if (! set_noreorder) \
2737 \
2740 reg_names[REGNO], \
2741 reg_names[STACK_POINTER_REGNUM], \
2743 reg_names[STACK_POINTER_REGNUM], \
2744 reg_names[STACK_POINTER_REGNUM]); \
2745 \
2746 if (! set_noreorder) \
2748 } \
2749 while (0)
2751 /* How to start an assembler comment.
2752 The leading space is important (the mips native assembler requires it). */
2753 #ifndef ASM_COMMENT_START
2755 #endif
2756 \f
2757 /* Default definitions for size_t and ptrdiff_t. We must override the
2758 definitions from ../svr4.h on mips-*-linux-gnu. */
2760 #undef SIZE_TYPE
2763 #undef PTRDIFF_TYPE
2765 \f
2766 #ifndef __mips16
2767 /* Since the bits of the _init and _fini function is spread across
2768 many object files, each potentially with its own GP, we must assume
2769 we need to load our GP. We don't preserve $gp or $ra, since each
2770 init/fini chunk is supposed to initialize $gp, and crti/crtn
2771 already take care of preserving $ra and, when appropriate, $gp. */
2772 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2773 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2783 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2784 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2785 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2794 #endif
2795 #endif
2797 #ifndef HAVE_AS_TLS
2798 #define HAVE_AS_TLS 0
2799 #endif