gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_notes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 \f
 127 /* Vector mapping INSN_UIDs to cuids.
 128    The cuids are like uids but increase monotonically always.
 129    Combine always uses cuids so that it can compare them.
 130    But actually renumbering the uids, which we used to do,
 131    proves to be a bad idea because it makes it hard to compare
 132    the dumps produced by earlier passes with those from later passes.  */
 133
 134 static int *uid_cuid;
 135 static int max_uid_cuid;
 136
 137 /* Get the cuid of an insn.  */
 138
 139 #define INSN_CUID(INSN) \
 140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 141
 142 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
 143    BITS_PER_WORD would invoke undefined behavior.  Work around it.  */
 144
 145 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
 146   (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
 147
 148 /* Maximum register number, which is the size of the tables below.  */
 149
 150 static unsigned int combine_max_regno;
 151
 152 struct reg_stat {
 153   /* Record last point of death of (hard or pseudo) register n.  */
 154   rtx                           last_death;
 155
 156   /* Record last point of modification of (hard or pseudo) register n.  */
 157   rtx                           last_set;
 158
 159   /* The next group of fields allows the recording of the last value assigned
 160      to (hard or pseudo) register n.  We use this information to see if an
 161      operation being processed is redundant given a prior operation performed
 162      on the register.  For example, an `and' with a constant is redundant if
 163      all the zero bits are already known to be turned off.
 164
 165      We use an approach similar to that used by cse, but change it in the
 166      following ways:
 167
 168      (1) We do not want to reinitialize at each label.
 169      (2) It is useful, but not critical, to know the actual value assigned
 170          to a register.  Often just its form is helpful.
 171
 172      Therefore, we maintain the following fields:
 173
 174      last_set_value             the last value assigned
 175      last_set_label             records the value of label_tick when the
 176                                 register was assigned
 177      last_set_table_tick        records the value of label_tick when a
 178                                 value using the register is assigned
 179      last_set_invalid           set to nonzero when it is not valid
 180                                 to use the value of this register in some
 181                                 register's value
 182
 183      To understand the usage of these tables, it is important to understand
 184      the distinction between the value in last_set_value being valid and
 185      the register being validly contained in some other expression in the
 186      table.
 187
 188      (The next two parameters are out of date).
 189
 190      reg_stat[i].last_set_value is valid if it is nonzero, and either
 191      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 192
 193      Register I may validly appear in any expression returned for the value
 194      of another register if reg_n_sets[i] is 1.  It may also appear in the
 195      value for register J if reg_stat[j].last_set_invalid is zero, or
 196      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 197
 198      If an expression is found in the table containing a register which may
 199      not validly appear in an expression, the register is replaced by
 200      something that won't match, (clobber (const_int 0)).  */
 201
 202   /* Record last value assigned to (hard or pseudo) register n.  */
 203
 204   rtx                           last_set_value;
 205
 206   /* Record the value of label_tick when an expression involving register n
 207      is placed in last_set_value.  */
 208
 209   int                           last_set_table_tick;
 210
 211   /* Record the value of label_tick when the value for register n is placed in
 212      last_set_value.  */
 213
 214   int                           last_set_label;
 215
 216   /* These fields are maintained in parallel with last_set_value and are
 217      used to store the mode in which the register was last set, the bits
 218      that were known to be zero when it was last set, and the number of
 219      sign bits copies it was known to have when it was last set.  */
 220
 221   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 222   char                          last_set_sign_bit_copies;
 223   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 224
 225   /* Set nonzero if references to register n in expressions should not be
 226      used.  last_set_invalid is set nonzero when this register is being
 227      assigned to and last_set_table_tick == label_tick.  */
 228
 229   char                          last_set_invalid;
 230
 231   /* Some registers that are set more than once and used in more than one
 232      basic block are nevertheless always set in similar ways.  For example,
 233      a QImode register may be loaded from memory in two places on a machine
 234      where byte loads zero extend.
 235
 236      We record in the following fields if a register has some leading bits
 237      that are always equal to the sign bit, and what we know about the
 238      nonzero bits of a register, specifically which bits are known to be
 239      zero.
 240
 241      If an entry is zero, it means that we don't know anything special.  */
 242
 243   unsigned char                 sign_bit_copies;
 244
 245   unsigned HOST_WIDE_INT        nonzero_bits;
 246
 247   /* Record the value of the label_tick when the last truncation
 248      happened.  The field truncated_to_mode is only valid if
 249      truncation_label == label_tick.  */
 250
 251   int                           truncation_label;
 252
 253   /* Record the last truncation seen for this register.  If truncation
 254      is not a nop to this mode we might be able to save an explicit
 255      truncation if we know that value already contains a truncated
 256      value.  */
 257
 258   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 259 };
 260
 261 static struct reg_stat *reg_stat;
 262
 263 /* Record the cuid of the last insn that invalidated memory
 264    (anything that writes memory, and subroutine calls, but not pushes).  */
 265
 266 static int mem_last_set;
 267
 268 /* Record the cuid of the last CALL_INSN
 269    so we can tell whether a potential combination crosses any calls.  */
 270
 271 static int last_call_cuid;
 272
 273 /* When `subst' is called, this is the insn that is being modified
 274    (by combining in a previous insn).  The PATTERN of this insn
 275    is still the old pattern partially modified and it should not be
 276    looked at, but this may be used to examine the successors of the insn
 277    to judge whether a simplification is valid.  */
 278
 279 static rtx subst_insn;
 280
 281 /* This is the lowest CUID that `subst' is currently dealing with.
 282    get_last_value will not return a value if the register was set at or
 283    after this CUID.  If not for this mechanism, we could get confused if
 284    I2 or I1 in try_combine were an insn that used the old value of a register
 285    to obtain a new value.  In that case, we might erroneously get the
 286    new value of the register when we wanted the old one.  */
 287
 288 static int subst_low_cuid;
 289
 290 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 291    must consider all these registers to be always live.  */
 292
 293 static HARD_REG_SET newpat_used_regs;
 294
 295 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 296    insn is the earlier than I2 or I3, combine should rescan starting at
 297    that location.  */
 298
 299 static rtx added_links_insn;
 300
 301 /* Basic block in which we are performing combines.  */
 302 static basic_block this_basic_block;
 303
 304 /* A bitmap indicating which blocks had registers go dead at entry.
 305    After combine, we'll need to re-do global life analysis with
 306    those blocks as starting points.  */
 307 static sbitmap refresh_blocks;
 308 \f
 309 /* The following array records the insn_rtx_cost for every insn
 310    in the instruction stream.  */
 311
 312 static int *uid_insn_cost;
 313
 314 /* Length of the currently allocated uid_insn_cost array.  */
 315
 316 static int last_insn_cost;
 317
 318 /* Incremented for each label.  */
 319
 320 static int label_tick;
 321
 322 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 323    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 324
 325 static enum machine_mode nonzero_bits_mode;
 326
 327 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 328    be safely used.  It is zero while computing them and after combine has
 329    completed.  This former test prevents propagating values based on
 330    previously set values, which can be incorrect if a variable is modified
 331    in a loop.  */
 332
 333 static int nonzero_sign_valid;
 334
 335 \f
 336 /* Record one modification to rtl structure
 337    to be undone by storing old_contents into *where.  */
 338
 339 struct undo
 340 {
 341   struct undo *next;
 342   enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
 343   union { rtx r; int i; enum machine_mode m; } old_contents;
 344   union { rtx *r; int *i; } where;
 345 };
 346
 347 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 348    num_undo says how many are currently recorded.
 349
 350    other_insn is nonzero if we have modified some other insn in the process
 351    of working on subst_insn.  It must be verified too.  */
 352
 353 struct undobuf
 354 {
 355   struct undo *undos;
 356   struct undo *frees;
 357   rtx other_insn;
 358 };
 359
 360 static struct undobuf undobuf;
 361
 362 /* Number of times the pseudo being substituted for
 363    was found and replaced.  */
 364
 365 static int n_occurrences;
 366
 367 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 368                                          enum machine_mode,
 369                                          unsigned HOST_WIDE_INT,
 370                                          unsigned HOST_WIDE_INT *);
 371 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 372                                                 enum machine_mode,
 373                                                 unsigned int, unsigned int *);
 374 static void do_SUBST (rtx *, rtx);
 375 static void do_SUBST_INT (int *, int);
 376 static void init_reg_last (void);
 377 static void setup_incoming_promotions (void);
 378 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 379 static int cant_combine_insn_p (rtx);
 380 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 381 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 382 static int contains_muldiv (rtx);
 383 static rtx try_combine (rtx, rtx, rtx, int *);
 384 static void undo_all (void);
 385 static void undo_commit (void);
 386 static rtx *find_split_point (rtx *, rtx);
 387 static rtx subst (rtx, rtx, rtx, int, int);
 388 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 389 static rtx simplify_if_then_else (rtx);
 390 static rtx simplify_set (rtx);
 391 static rtx simplify_logical (rtx);
 392 static rtx expand_compound_operation (rtx);
 393 static rtx expand_field_assignment (rtx);
 394 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 395                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 396 static rtx extract_left_shift (rtx, int);
 397 static rtx make_compound_operation (rtx, enum rtx_code);
 398 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 399                               unsigned HOST_WIDE_INT *);
 400 static rtx canon_reg_for_combine (rtx, rtx);
 401 static rtx force_to_mode (rtx, enum machine_mode,
 402                           unsigned HOST_WIDE_INT, int);
 403 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 404 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 405 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 406 static rtx make_field_assignment (rtx);
 407 static rtx apply_distributive_law (rtx);
 408 static rtx distribute_and_simplify_rtx (rtx, int);
 409 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 410                                      unsigned HOST_WIDE_INT);
 411 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 412                                    unsigned HOST_WIDE_INT);
 413 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 414                             HOST_WIDE_INT, enum machine_mode, int *);
 415 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 416 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 417                                  int);
 418 static int recog_for_combine (rtx *, rtx, rtx *);
 419 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 420 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 421 static void update_table_tick (rtx);
 422 static void record_value_for_reg (rtx, rtx, rtx);
 423 static void check_conversions (rtx, rtx);
 424 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 425 static void record_dead_and_set_regs (rtx);
 426 static int get_last_value_validate (rtx *, rtx, int, int);
 427 static rtx get_last_value (rtx);
 428 static int use_crosses_set_p (rtx, int);
 429 static void reg_dead_at_p_1 (rtx, rtx, void *);
 430 static int reg_dead_at_p (rtx, rtx);
 431 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 432 static int reg_bitfield_target_p (rtx, rtx);
 433 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 434 static void distribute_links (rtx);
 435 static void mark_used_regs_combine (rtx);
 436 static int insn_cuid (rtx);
 437 static void record_promoted_value (rtx, rtx);
 438 static int unmentioned_reg_p_1 (rtx *, void *);
 439 static bool unmentioned_reg_p (rtx, rtx);
 440 static void record_truncated_value (rtx);
 441 static bool reg_truncated_to_mode (enum machine_mode, rtx);
 442 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 443 \f
 444
 445 /* It is not safe to use ordinary gen_lowpart in combine.
 446    See comments in gen_lowpart_for_combine.  */
 447 #undef RTL_HOOKS_GEN_LOWPART
 448 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 449
 450 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 451 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 452 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 453
 454 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 455 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 456
 457 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 458 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 459
 460 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 461
 462 \f
 463 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 464    insn.  The substitution can be undone by undo_all.  If INTO is already
 465    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 466    also call SUBST, we have to compute it before we put anything into
 467    the undo table.  */
 468
 469 static void
 470 do_SUBST (rtx *into, rtx newval)
 471 {
 472   struct undo *buf;
 473   rtx oldval = *into;
 474
 475   if (oldval == newval)
 476     return;
 477
 478   /* We'd like to catch as many invalid transformations here as
 479      possible.  Unfortunately, there are way too many mode changes
 480      that are perfectly valid, so we'd waste too much effort for
 481      little gain doing the checks here.  Focus on catching invalid
 482      transformations involving integer constants.  */
 483   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 484       && GET_CODE (newval) == CONST_INT)
 485     {
 486       /* Sanity check that we're replacing oldval with a CONST_INT
 487          that is a valid sign-extension for the original mode.  */
 488       gcc_assert (INTVAL (newval)
 489                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 490
 491       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 492          CONST_INT is not valid, because after the replacement, the
 493          original mode would be gone.  Unfortunately, we can't tell
 494          when do_SUBST is called to replace the operand thereof, so we
 495          perform this test on oldval instead, checking whether an
 496          invalid replacement took place before we got here.  */
 497       gcc_assert (!(GET_CODE (oldval) == SUBREG
 498                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 499       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 500                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 501     }
 502
 503   if (undobuf.frees)
 504     buf = undobuf.frees, undobuf.frees = buf->next;
 505   else
 506     buf = XNEW (struct undo);
 507
 508   buf->kind = UNDO_RTX;
 509   buf->where.r = into;
 510   buf->old_contents.r = oldval;
 511   *into = newval;
 512
 513   buf->next = undobuf.undos, undobuf.undos = buf;
 514 }
 515
 516 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 517
 518 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 519    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 520    not safe.  */
 521
 522 static void
 523 do_SUBST_INT (int *into, int newval)
 524 {
 525   struct undo *buf;
 526   int oldval = *into;
 527
 528   if (oldval == newval)
 529     return;
 530
 531   if (undobuf.frees)
 532     buf = undobuf.frees, undobuf.frees = buf->next;
 533   else
 534     buf = XNEW (struct undo);
 535
 536   buf->kind = UNDO_INT;
 537   buf->where.i = into;
 538   buf->old_contents.i = oldval;
 539   *into = newval;
 540
 541   buf->next = undobuf.undos, undobuf.undos = buf;
 542 }
 543
 544 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 545
 546 /* Similar to SUBST, but just substitute the mode.  This is used when
 547    changing the mode of a pseudo-register, so that any other
 548    references to the entry in the regno_reg_rtx array will change as
 549    well.  */
 550
 551 static void
 552 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 553 {
 554   struct undo *buf;
 555   enum machine_mode oldval = GET_MODE (*into);
 556
 557   if (oldval == newval)
 558     return;
 559
 560   if (undobuf.frees)
 561     buf = undobuf.frees, undobuf.frees = buf->next;
 562   else
 563     buf = XNEW (struct undo);
 564
 565   buf->kind = UNDO_MODE;
 566   buf->where.r = into;
 567   buf->old_contents.m = oldval;
 568   PUT_MODE (*into, newval);
 569
 570   buf->next = undobuf.undos, undobuf.undos = buf;
 571 }
 572
 573 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 574 \f
 575 /* Subroutine of try_combine.  Determine whether the combine replacement
 576    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 577    that the original instruction sequence I1, I2 and I3.  Note that I1
 578    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 579    costs of all instructions can be estimated, and the replacements are
 580    more expensive than the original sequence.  */
 581
 582 static bool
 583 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 584 {
 585   int i1_cost, i2_cost, i3_cost;
 586   int new_i2_cost, new_i3_cost;
 587   int old_cost, new_cost;
 588
 589   /* Lookup the original insn_rtx_costs.  */
 590   i2_cost = INSN_UID (i2) <= last_insn_cost
 591             ? uid_insn_cost[INSN_UID (i2)] : 0;
 592   i3_cost = INSN_UID (i3) <= last_insn_cost
 593             ? uid_insn_cost[INSN_UID (i3)] : 0;
 594
 595   if (i1)
 596     {
 597       i1_cost = INSN_UID (i1) <= last_insn_cost
 598                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 599       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 600                  ? i1_cost + i2_cost + i3_cost : 0;
 601     }
 602   else
 603     {
 604       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 605       i1_cost = 0;
 606     }
 607
 608   /* Calculate the replacement insn_rtx_costs.  */
 609   new_i3_cost = insn_rtx_cost (newpat);
 610   if (newi2pat)
 611     {
 612       new_i2_cost = insn_rtx_cost (newi2pat);
 613       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 614                  ? new_i2_cost + new_i3_cost : 0;
 615     }
 616   else
 617     {
 618       new_cost = new_i3_cost;
 619       new_i2_cost = 0;
 620     }
 621
 622   if (undobuf.other_insn)
 623     {
 624       int old_other_cost, new_other_cost;
 625
 626       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 627                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 628       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 629       if (old_other_cost > 0 && new_other_cost > 0)
 630         {
 631           old_cost += old_other_cost;
 632           new_cost += new_other_cost;
 633         }
 634       else
 635         old_cost = 0;
 636     }
 637
 638   /* Disallow this recombination if both new_cost and old_cost are
 639      greater than zero, and new_cost is greater than old cost.  */
 640   if (old_cost > 0
 641       && new_cost > old_cost)
 642     {
 643       if (dump_file)
 644         {
 645           if (i1)
 646             {
 647               fprintf (dump_file,
 648                        "rejecting combination of insns %d, %d and %d\n",
 649                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 650               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 651                        i1_cost, i2_cost, i3_cost, old_cost);
 652             }
 653           else
 654             {
 655               fprintf (dump_file,
 656                        "rejecting combination of insns %d and %d\n",
 657                        INSN_UID (i2), INSN_UID (i3));
 658               fprintf (dump_file, "original costs %d + %d = %d\n",
 659                        i2_cost, i3_cost, old_cost);
 660             }
 661
 662           if (newi2pat)
 663             {
 664               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 665                        new_i2_cost, new_i3_cost, new_cost);
 666             }
 667           else
 668             fprintf (dump_file, "replacement cost %d\n", new_cost);
 669         }
 670
 671       return false;
 672     }
 673
 674   /* Update the uid_insn_cost array with the replacement costs.  */
 675   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 676   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 677   if (i1)
 678     uid_insn_cost[INSN_UID (i1)] = 0;
 679
 680   return true;
 681 }
 682 \f
 683 /* Main entry point for combiner.  F is the first insn of the function.
 684    NREGS is the first unused pseudo-reg number.
 685
 686    Return nonzero if the combiner has turned an indirect jump
 687    instruction into a direct jump.  */
 688 static int
 689 combine_instructions (rtx f, unsigned int nregs)
 690 {
 691   rtx insn, next;
 692 #ifdef HAVE_cc0
 693   rtx prev;
 694 #endif
 695   int i;
 696   unsigned int j = 0;
 697   rtx links, nextlinks;
 698   sbitmap_iterator sbi;
 699
 700   int new_direct_jump_p = 0;
 701
 702   combine_attempts = 0;
 703   combine_merges = 0;
 704   combine_extras = 0;
 705   combine_successes = 0;
 706
 707   combine_max_regno = nregs;
 708
 709   rtl_hooks = combine_rtl_hooks;
 710
 711   reg_stat = XCNEWVEC (struct reg_stat, nregs);
 712
 713   init_recog_no_volatile ();
 714
 715   /* Compute maximum uid value so uid_cuid can be allocated.  */
 716
 717   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 718     if (INSN_UID (insn) > i)
 719       i = INSN_UID (insn);
 720
 721   uid_cuid = XNEWVEC (int, i + 1);
 722   max_uid_cuid = i;
 723
 724   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 725
 726   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 727      problems when, for example, we have j <<= 1 in a loop.  */
 728
 729   nonzero_sign_valid = 0;
 730
 731   /* Compute the mapping from uids to cuids.
 732      Cuids are numbers assigned to insns, like uids,
 733      except that cuids increase monotonically through the code.
 734
 735      Scan all SETs and see if we can deduce anything about what
 736      bits are known to be zero for some registers and how many copies
 737      of the sign bit are known to exist for those registers.
 738
 739      Also set any known values so that we can use it while searching
 740      for what bits are known to be set.  */
 741
 742   label_tick = 1;
 743
 744   setup_incoming_promotions ();
 745
 746   refresh_blocks = sbitmap_alloc (last_basic_block);
 747   sbitmap_zero (refresh_blocks);
 748
 749   /* Allocate array of current insn_rtx_costs.  */
 750   uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1);
 751   last_insn_cost = max_uid_cuid;
 752
 753   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 754     {
 755       uid_cuid[INSN_UID (insn)] = ++i;
 756       subst_low_cuid = i;
 757       subst_insn = insn;
 758
 759       if (INSN_P (insn))
 760         {
 761           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 762                        NULL);
 763           record_dead_and_set_regs (insn);
 764
 765 #ifdef AUTO_INC_DEC
 766           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 767             if (REG_NOTE_KIND (links) == REG_INC)
 768               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 769                                                 NULL);
 770 #endif
 771
 772           /* Record the current insn_rtx_cost of this instruction.  */
 773           if (NONJUMP_INSN_P (insn))
 774             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 775           if (dump_file)
 776             fprintf(dump_file, "insn_cost %d: %d\n",
 777                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 778         }
 779
 780       if (LABEL_P (insn))
 781         label_tick++;
 782     }
 783
 784   nonzero_sign_valid = 1;
 785
 786   /* Now scan all the insns in forward order.  */
 787
 788   label_tick = 1;
 789   last_call_cuid = 0;
 790   mem_last_set = 0;
 791   init_reg_last ();
 792   setup_incoming_promotions ();
 793
 794   FOR_EACH_BB (this_basic_block)
 795     {
 796       for (insn = BB_HEAD (this_basic_block);
 797            insn != NEXT_INSN (BB_END (this_basic_block));
 798            insn = next ? next : NEXT_INSN (insn))
 799         {
 800           next = 0;
 801
 802           if (LABEL_P (insn))
 803             label_tick++;
 804
 805           else if (INSN_P (insn))
 806             {
 807               /* See if we know about function return values before this
 808                  insn based upon SUBREG flags.  */
 809               check_conversions (insn, PATTERN (insn));
 810
 811               /* Try this insn with each insn it links back to.  */
 812
 813               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 814                 if ((next = try_combine (insn, XEXP (links, 0),
 815                                          NULL_RTX, &new_direct_jump_p)) != 0)
 816                   goto retry;
 817
 818               /* Try each sequence of three linked insns ending with this one.  */
 819
 820               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 821                 {
 822                   rtx link = XEXP (links, 0);
 823
 824                   /* If the linked insn has been replaced by a note, then there
 825                      is no point in pursuing this chain any further.  */
 826                   if (NOTE_P (link))
 827                     continue;
 828
 829                   for (nextlinks = LOG_LINKS (link);
 830                        nextlinks;
 831                        nextlinks = XEXP (nextlinks, 1))
 832                     if ((next = try_combine (insn, link,
 833                                              XEXP (nextlinks, 0),
 834                                              &new_direct_jump_p)) != 0)
 835                       goto retry;
 836                 }
 837
 838 #ifdef HAVE_cc0
 839               /* Try to combine a jump insn that uses CC0
 840                  with a preceding insn that sets CC0, and maybe with its
 841                  logical predecessor as well.
 842                  This is how we make decrement-and-branch insns.
 843                  We need this special code because data flow connections
 844                  via CC0 do not get entered in LOG_LINKS.  */
 845
 846               if (JUMP_P (insn)
 847                   && (prev = prev_nonnote_insn (insn)) != 0
 848                   && NONJUMP_INSN_P (prev)
 849                   && sets_cc0_p (PATTERN (prev)))
 850                 {
 851                   if ((next = try_combine (insn, prev,
 852                                            NULL_RTX, &new_direct_jump_p)) != 0)
 853                     goto retry;
 854
 855                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 856                        nextlinks = XEXP (nextlinks, 1))
 857                     if ((next = try_combine (insn, prev,
 858                                              XEXP (nextlinks, 0),
 859                                              &new_direct_jump_p)) != 0)
 860                       goto retry;
 861                 }
 862
 863               /* Do the same for an insn that explicitly references CC0.  */
 864               if (NONJUMP_INSN_P (insn)
 865                   && (prev = prev_nonnote_insn (insn)) != 0
 866                   && NONJUMP_INSN_P (prev)
 867                   && sets_cc0_p (PATTERN (prev))
 868                   && GET_CODE (PATTERN (insn)) == SET
 869                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 870                 {
 871                   if ((next = try_combine (insn, prev,
 872                                            NULL_RTX, &new_direct_jump_p)) != 0)
 873                     goto retry;
 874
 875                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 876                        nextlinks = XEXP (nextlinks, 1))
 877                     if ((next = try_combine (insn, prev,
 878                                              XEXP (nextlinks, 0),
 879                                              &new_direct_jump_p)) != 0)
 880                       goto retry;
 881                 }
 882
 883               /* Finally, see if any of the insns that this insn links to
 884                  explicitly references CC0.  If so, try this insn, that insn,
 885                  and its predecessor if it sets CC0.  */
 886               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 887                 if (NONJUMP_INSN_P (XEXP (links, 0))
 888                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 889                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 890                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 891                     && NONJUMP_INSN_P (prev)
 892                     && sets_cc0_p (PATTERN (prev))
 893                     && (next = try_combine (insn, XEXP (links, 0),
 894                                             prev, &new_direct_jump_p)) != 0)
 895                   goto retry;
 896 #endif
 897
 898               /* Try combining an insn with two different insns whose results it
 899                  uses.  */
 900               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 901                 for (nextlinks = XEXP (links, 1); nextlinks;
 902                      nextlinks = XEXP (nextlinks, 1))
 903                   if ((next = try_combine (insn, XEXP (links, 0),
 904                                            XEXP (nextlinks, 0),
 905                                            &new_direct_jump_p)) != 0)
 906                     goto retry;
 907
 908               /* Try this insn with each REG_EQUAL note it links back to.  */
 909               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 910                 {
 911                   rtx set, note;
 912                   rtx temp = XEXP (links, 0);
 913                   if ((set = single_set (temp)) != 0
 914                       && (note = find_reg_equal_equiv_note (temp)) != 0
 915                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 916                       /* Avoid using a register that may already been marked
 917                          dead by an earlier instruction.  */
 918                       && ! unmentioned_reg_p (note, SET_SRC (set))
 919                       && (GET_MODE (note) == VOIDmode
 920                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 921                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 922                     {
 923                       /* Temporarily replace the set's source with the
 924                          contents of the REG_EQUAL note.  The insn will
 925                          be deleted or recognized by try_combine.  */
 926                       rtx orig = SET_SRC (set);
 927                       SET_SRC (set) = note;
 928                       next = try_combine (insn, temp, NULL_RTX,
 929                                           &new_direct_jump_p);
 930                       if (next)
 931                         goto retry;
 932                       SET_SRC (set) = orig;
 933                     }
 934                 }
 935
 936               if (!NOTE_P (insn))
 937                 record_dead_and_set_regs (insn);
 938
 939             retry:
 940               ;
 941             }
 942         }
 943     }
 944   clear_bb_flags ();
 945
 946   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 947     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 948   new_direct_jump_p |= purge_all_dead_edges ();
 949   delete_noop_moves ();
 950
 951   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 952                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 953                                     | PROP_KILL_DEAD_CODE);
 954
 955   /* Clean up.  */
 956   sbitmap_free (refresh_blocks);
 957   free (uid_insn_cost);
 958   free (reg_stat);
 959   free (uid_cuid);
 960
 961   {
 962     struct undo *undo, *next;
 963     for (undo = undobuf.frees; undo; undo = next)
 964       {
 965         next = undo->next;
 966         free (undo);
 967       }
 968     undobuf.frees = 0;
 969   }
 970
 971   total_attempts += combine_attempts;
 972   total_merges += combine_merges;
 973   total_extras += combine_extras;
 974   total_successes += combine_successes;
 975
 976   nonzero_sign_valid = 0;
 977   rtl_hooks = general_rtl_hooks;
 978
 979   /* Make recognizer allow volatile MEMs again.  */
 980   init_recog ();
 981
 982   return new_direct_jump_p;
 983 }
 984
 985 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
 986
 987 static void
 988 init_reg_last (void)
 989 {
 990   unsigned int i;
 991   for (i = 0; i < combine_max_regno; i++)
 992     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
 993 }
 994 \f
 995 /* Set up any promoted values for incoming argument registers.  */
 996
 997 static void
 998 setup_incoming_promotions (void)
 999 {
1000   unsigned int regno;
1001   rtx reg;
1002   enum machine_mode mode;
1003   int unsignedp;
1004   rtx first = get_insns ();
1005
1006   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1007     {
1008       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1009         /* Check whether this register can hold an incoming pointer
1010            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
1011            numbers, so translate if necessary due to register windows.  */
1012         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1013             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1014           {
1015             record_value_for_reg
1016               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1017                                            : SIGN_EXTEND),
1018                                           GET_MODE (reg),
1019                                           gen_rtx_CLOBBER (mode, const0_rtx)));
1020           }
1021     }
1022 }
1023 \f
1024 /* Called via note_stores.  If X is a pseudo that is narrower than
1025    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1026
1027    If we are setting only a portion of X and we can't figure out what
1028    portion, assume all bits will be used since we don't know what will
1029    be happening.
1030
1031    Similarly, set how many bits of X are known to be copies of the sign bit
1032    at all locations in the function.  This is the smallest number implied
1033    by any set of X.  */
1034
1035 static void
1036 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1037                                   void *data ATTRIBUTE_UNUSED)
1038 {
1039   unsigned int num;
1040
1041   if (REG_P (x)
1042       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1043       /* If this register is undefined at the start of the file, we can't
1044          say what its contents were.  */
1045       && ! REGNO_REG_SET_P
1046          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1047       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1048     {
1049       if (set == 0 || GET_CODE (set) == CLOBBER)
1050         {
1051           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1052           reg_stat[REGNO (x)].sign_bit_copies = 1;
1053           return;
1054         }
1055
1056       /* If this is a complex assignment, see if we can convert it into a
1057          simple assignment.  */
1058       set = expand_field_assignment (set);
1059
1060       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1061          set what we know about X.  */
1062
1063       if (SET_DEST (set) == x
1064           || (GET_CODE (SET_DEST (set)) == SUBREG
1065               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1066                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1067               && SUBREG_REG (SET_DEST (set)) == x))
1068         {
1069           rtx src = SET_SRC (set);
1070
1071 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1072           /* If X is narrower than a word and SRC is a non-negative
1073              constant that would appear negative in the mode of X,
1074              sign-extend it for use in reg_stat[].nonzero_bits because some
1075              machines (maybe most) will actually do the sign-extension
1076              and this is the conservative approach.
1077
1078              ??? For 2.5, try to tighten up the MD files in this regard
1079              instead of this kludge.  */
1080
1081           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1082               && GET_CODE (src) == CONST_INT
1083               && INTVAL (src) > 0
1084               && 0 != (INTVAL (src)
1085                        & ((HOST_WIDE_INT) 1
1086                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1087             src = GEN_INT (INTVAL (src)
1088                            | ((HOST_WIDE_INT) (-1)
1089                               << GET_MODE_BITSIZE (GET_MODE (x))));
1090 #endif
1091
1092           /* Don't call nonzero_bits if it cannot change anything.  */
1093           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1094             reg_stat[REGNO (x)].nonzero_bits
1095               |= nonzero_bits (src, nonzero_bits_mode);
1096           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1097           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1098               || reg_stat[REGNO (x)].sign_bit_copies > num)
1099             reg_stat[REGNO (x)].sign_bit_copies = num;
1100         }
1101       else
1102         {
1103           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1104           reg_stat[REGNO (x)].sign_bit_copies = 1;
1105         }
1106     }
1107 }
1108 \f
1109 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1110    insns that were previously combined into I3 or that will be combined
1111    into the merger of INSN and I3.
1112
1113    Return 0 if the combination is not allowed for any reason.
1114
1115    If the combination is allowed, *PDEST will be set to the single
1116    destination of INSN and *PSRC to the single source, and this function
1117    will return 1.  */
1118
1119 static int
1120 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1121                rtx *pdest, rtx *psrc)
1122 {
1123   int i;
1124   rtx set = 0, src, dest;
1125   rtx p;
1126 #ifdef AUTO_INC_DEC
1127   rtx link;
1128 #endif
1129   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1130                               && next_active_insn (succ) == i3)
1131                       : next_active_insn (insn) == i3);
1132
1133   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1134      or a PARALLEL consisting of such a SET and CLOBBERs.
1135
1136      If INSN has CLOBBER parallel parts, ignore them for our processing.
1137      By definition, these happen during the execution of the insn.  When it
1138      is merged with another insn, all bets are off.  If they are, in fact,
1139      needed and aren't also supplied in I3, they may be added by
1140      recog_for_combine.  Otherwise, it won't match.
1141
1142      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1143      note.
1144
1145      Get the source and destination of INSN.  If more than one, can't
1146      combine.  */
1147
1148   if (GET_CODE (PATTERN (insn)) == SET)
1149     set = PATTERN (insn);
1150   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1151            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1152     {
1153       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1154         {
1155           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1156           rtx note;
1157
1158           switch (GET_CODE (elt))
1159             {
1160             /* This is important to combine floating point insns
1161                for the SH4 port.  */
1162             case USE:
1163               /* Combining an isolated USE doesn't make sense.
1164                  We depend here on combinable_i3pat to reject them.  */
1165               /* The code below this loop only verifies that the inputs of
1166                  the SET in INSN do not change.  We call reg_set_between_p
1167                  to verify that the REG in the USE does not change between
1168                  I3 and INSN.
1169                  If the USE in INSN was for a pseudo register, the matching
1170                  insn pattern will likely match any register; combining this
1171                  with any other USE would only be safe if we knew that the
1172                  used registers have identical values, or if there was
1173                  something to tell them apart, e.g. different modes.  For
1174                  now, we forgo such complicated tests and simply disallow
1175                  combining of USES of pseudo registers with any other USE.  */
1176               if (REG_P (XEXP (elt, 0))
1177                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1178                 {
1179                   rtx i3pat = PATTERN (i3);
1180                   int i = XVECLEN (i3pat, 0) - 1;
1181                   unsigned int regno = REGNO (XEXP (elt, 0));
1182
1183                   do
1184                     {
1185                       rtx i3elt = XVECEXP (i3pat, 0, i);
1186
1187                       if (GET_CODE (i3elt) == USE
1188                           && REG_P (XEXP (i3elt, 0))
1189                           && (REGNO (XEXP (i3elt, 0)) == regno
1190                               ? reg_set_between_p (XEXP (elt, 0),
1191                                                    PREV_INSN (insn), i3)
1192                               : regno >= FIRST_PSEUDO_REGISTER))
1193                         return 0;
1194                     }
1195                   while (--i >= 0);
1196                 }
1197               break;
1198
1199               /* We can ignore CLOBBERs.  */
1200             case CLOBBER:
1201               break;
1202
1203             case SET:
1204               /* Ignore SETs whose result isn't used but not those that
1205                  have side-effects.  */
1206               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1207                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1208                       || INTVAL (XEXP (note, 0)) <= 0)
1209                   && ! side_effects_p (elt))
1210                 break;
1211
1212               /* If we have already found a SET, this is a second one and
1213                  so we cannot combine with this insn.  */
1214               if (set)
1215                 return 0;
1216
1217               set = elt;
1218               break;
1219
1220             default:
1221               /* Anything else means we can't combine.  */
1222               return 0;
1223             }
1224         }
1225
1226       if (set == 0
1227           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1228              so don't do anything with it.  */
1229           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1230         return 0;
1231     }
1232   else
1233     return 0;
1234
1235   if (set == 0)
1236     return 0;
1237
1238   set = expand_field_assignment (set);
1239   src = SET_SRC (set), dest = SET_DEST (set);
1240
1241   /* Don't eliminate a store in the stack pointer.  */
1242   if (dest == stack_pointer_rtx
1243       /* Don't combine with an insn that sets a register to itself if it has
1244          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1245       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1246       /* Can't merge an ASM_OPERANDS.  */
1247       || GET_CODE (src) == ASM_OPERANDS
1248       /* Can't merge a function call.  */
1249       || GET_CODE (src) == CALL
1250       /* Don't eliminate a function call argument.  */
1251       || (CALL_P (i3)
1252           && (find_reg_fusage (i3, USE, dest)
1253               || (REG_P (dest)
1254                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1255                   && global_regs[REGNO (dest)])))
1256       /* Don't substitute into an incremented register.  */
1257       || FIND_REG_INC_NOTE (i3, dest)
1258       || (succ && FIND_REG_INC_NOTE (succ, dest))
1259       /* Don't substitute into a non-local goto, this confuses CFG.  */
1260       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1261 #if 0
1262       /* Don't combine the end of a libcall into anything.  */
1263       /* ??? This gives worse code, and appears to be unnecessary, since no
1264          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1265          use REG_RETVAL notes for noconflict blocks, but other code here
1266          makes sure that those insns don't disappear.  */
1267       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1268 #endif
1269       /* Make sure that DEST is not used after SUCC but before I3.  */
1270       || (succ && ! all_adjacent
1271           && reg_used_between_p (dest, succ, i3))
1272       /* Make sure that the value that is to be substituted for the register
1273          does not use any registers whose values alter in between.  However,
1274          If the insns are adjacent, a use can't cross a set even though we
1275          think it might (this can happen for a sequence of insns each setting
1276          the same destination; last_set of that register might point to
1277          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1278          equivalent to the memory so the substitution is valid even if there
1279          are intervening stores.  Also, don't move a volatile asm or
1280          UNSPEC_VOLATILE across any other insns.  */
1281       || (! all_adjacent
1282           && (((!MEM_P (src)
1283                 || ! find_reg_note (insn, REG_EQUIV, src))
1284                && use_crosses_set_p (src, INSN_CUID (insn)))
1285               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1286               || GET_CODE (src) == UNSPEC_VOLATILE))
1287       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1288          better register allocation by not doing the combine.  */
1289       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1290       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1291       /* Don't combine across a CALL_INSN, because that would possibly
1292          change whether the life span of some REGs crosses calls or not,
1293          and it is a pain to update that information.
1294          Exception: if source is a constant, moving it later can't hurt.
1295          Accept that special case, because it helps -fforce-addr a lot.  */
1296       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1297     return 0;
1298
1299   /* DEST must either be a REG or CC0.  */
1300   if (REG_P (dest))
1301     {
1302       /* If register alignment is being enforced for multi-word items in all
1303          cases except for parameters, it is possible to have a register copy
1304          insn referencing a hard register that is not allowed to contain the
1305          mode being copied and which would not be valid as an operand of most
1306          insns.  Eliminate this problem by not combining with such an insn.
1307
1308          Also, on some machines we don't want to extend the life of a hard
1309          register.  */
1310
1311       if (REG_P (src)
1312           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1313                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1314               /* Don't extend the life of a hard register unless it is
1315                  user variable (if we have few registers) or it can't
1316                  fit into the desired register (meaning something special
1317                  is going on).
1318                  Also avoid substituting a return register into I3, because
1319                  reload can't handle a conflict with constraints of other
1320                  inputs.  */
1321               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1322                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1323         return 0;
1324     }
1325   else if (GET_CODE (dest) != CC0)
1326     return 0;
1327
1328
1329   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1330     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1331       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1332         {
1333           /* Don't substitute for a register intended as a clobberable
1334              operand.  */
1335           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1336           if (rtx_equal_p (reg, dest))
1337             return 0;
1338
1339           /* If the clobber represents an earlyclobber operand, we must not
1340              substitute an expression containing the clobbered register.
1341              As we do not analyze the constraint strings here, we have to
1342              make the conservative assumption.  However, if the register is
1343              a fixed hard reg, the clobber cannot represent any operand;
1344              we leave it up to the machine description to either accept or
1345              reject use-and-clobber patterns.  */
1346           if (!REG_P (reg)
1347               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1348               || !fixed_regs[REGNO (reg)])
1349             if (reg_overlap_mentioned_p (reg, src))
1350               return 0;
1351         }
1352
1353   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1354      or not), reject, unless nothing volatile comes between it and I3 */
1355
1356   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1357     {
1358       /* Make sure succ doesn't contain a volatile reference.  */
1359       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1360         return 0;
1361
1362       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1363         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1364           return 0;
1365     }
1366
1367   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1368      to be an explicit register variable, and was chosen for a reason.  */
1369
1370   if (GET_CODE (src) == ASM_OPERANDS
1371       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1372     return 0;
1373
1374   /* If there are any volatile insns between INSN and I3, reject, because
1375      they might affect machine state.  */
1376
1377   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1378     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1379       return 0;
1380
1381   /* If INSN contains an autoincrement or autodecrement, make sure that
1382      register is not used between there and I3, and not already used in
1383      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1384      Also insist that I3 not be a jump; if it were one
1385      and the incremented register were spilled, we would lose.  */
1386
1387 #ifdef AUTO_INC_DEC
1388   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1389     if (REG_NOTE_KIND (link) == REG_INC
1390         && (JUMP_P (i3)
1391             || reg_used_between_p (XEXP (link, 0), insn, i3)
1392             || (pred != NULL_RTX
1393                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1394             || (succ != NULL_RTX
1395                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1396             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1397       return 0;
1398 #endif
1399
1400 #ifdef HAVE_cc0
1401   /* Don't combine an insn that follows a CC0-setting insn.
1402      An insn that uses CC0 must not be separated from the one that sets it.
1403      We do, however, allow I2 to follow a CC0-setting insn if that insn
1404      is passed as I1; in that case it will be deleted also.
1405      We also allow combining in this case if all the insns are adjacent
1406      because that would leave the two CC0 insns adjacent as well.
1407      It would be more logical to test whether CC0 occurs inside I1 or I2,
1408      but that would be much slower, and this ought to be equivalent.  */
1409
1410   p = prev_nonnote_insn (insn);
1411   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1412       && ! all_adjacent)
1413     return 0;
1414 #endif
1415
1416   /* If we get here, we have passed all the tests and the combination is
1417      to be allowed.  */
1418
1419   *pdest = dest;
1420   *psrc = src;
1421
1422   return 1;
1423 }
1424 \f
1425 /* LOC is the location within I3 that contains its pattern or the component
1426    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1427
1428    One problem is if I3 modifies its output, as opposed to replacing it
1429    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1430    so would produce an insn that is not equivalent to the original insns.
1431
1432    Consider:
1433
1434          (set (reg:DI 101) (reg:DI 100))
1435          (set (subreg:SI (reg:DI 101) 0) <foo>)
1436
1437    This is NOT equivalent to:
1438
1439          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1440                     (set (reg:DI 101) (reg:DI 100))])
1441
1442    Not only does this modify 100 (in which case it might still be valid
1443    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1444
1445    We can also run into a problem if I2 sets a register that I1
1446    uses and I1 gets directly substituted into I3 (not via I2).  In that
1447    case, we would be getting the wrong value of I2DEST into I3, so we
1448    must reject the combination.  This case occurs when I2 and I1 both
1449    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1450    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1451    of a SET must prevent combination from occurring.
1452
1453    Before doing the above check, we first try to expand a field assignment
1454    into a set of logical operations.
1455
1456    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1457    we place a register that is both set and used within I3.  If more than one
1458    such register is detected, we fail.
1459
1460    Return 1 if the combination is valid, zero otherwise.  */
1461
1462 static int
1463 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1464                   int i1_not_in_src, rtx *pi3dest_killed)
1465 {
1466   rtx x = *loc;
1467
1468   if (GET_CODE (x) == SET)
1469     {
1470       rtx set = x ;
1471       rtx dest = SET_DEST (set);
1472       rtx src = SET_SRC (set);
1473       rtx inner_dest = dest;
1474       rtx subdest;
1475
1476       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1477              || GET_CODE (inner_dest) == SUBREG
1478              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1479         inner_dest = XEXP (inner_dest, 0);
1480
1481       /* Check for the case where I3 modifies its output, as discussed
1482          above.  We don't want to prevent pseudos from being combined
1483          into the address of a MEM, so only prevent the combination if
1484          i1 or i2 set the same MEM.  */
1485       if ((inner_dest != dest &&
1486            (!MEM_P (inner_dest)
1487             || rtx_equal_p (i2dest, inner_dest)
1488             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1489            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1490                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1491
1492           /* This is the same test done in can_combine_p except we can't test
1493              all_adjacent; we don't have to, since this instruction will stay
1494              in place, thus we are not considering increasing the lifetime of
1495              INNER_DEST.
1496
1497              Also, if this insn sets a function argument, combining it with
1498              something that might need a spill could clobber a previous
1499              function argument; the all_adjacent test in can_combine_p also
1500              checks this; here, we do a more specific test for this case.  */
1501
1502           || (REG_P (inner_dest)
1503               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1504               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1505                                         GET_MODE (inner_dest))))
1506           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1507         return 0;
1508
1509       /* If DEST is used in I3, it is being killed in this insn, so
1510          record that for later.  We have to consider paradoxical
1511          subregs here, since they kill the whole register, but we
1512          ignore partial subregs, STRICT_LOW_PART, etc.
1513          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1514          STACK_POINTER_REGNUM, since these are always considered to be
1515          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1516       subdest = dest;
1517       if (GET_CODE (subdest) == SUBREG
1518           && (GET_MODE_SIZE (GET_MODE (subdest))
1519               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1520         subdest = SUBREG_REG (subdest);
1521       if (pi3dest_killed
1522           && REG_P (subdest)
1523           && reg_referenced_p (subdest, PATTERN (i3))
1524           && REGNO (subdest) != FRAME_POINTER_REGNUM
1525 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1526           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1527 #endif
1528 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1529           && (REGNO (subdest) != ARG_POINTER_REGNUM
1530               || ! fixed_regs [REGNO (subdest)])
1531 #endif
1532           && REGNO (subdest) != STACK_POINTER_REGNUM)
1533         {
1534           if (*pi3dest_killed)
1535             return 0;
1536
1537           *pi3dest_killed = subdest;
1538         }
1539     }
1540
1541   else if (GET_CODE (x) == PARALLEL)
1542     {
1543       int i;
1544
1545       for (i = 0; i < XVECLEN (x, 0); i++)
1546         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1547                                 i1_not_in_src, pi3dest_killed))
1548           return 0;
1549     }
1550
1551   return 1;
1552 }
1553 \f
1554 /* Return 1 if X is an arithmetic expression that contains a multiplication
1555    and division.  We don't count multiplications by powers of two here.  */
1556
1557 static int
1558 contains_muldiv (rtx x)
1559 {
1560   switch (GET_CODE (x))
1561     {
1562     case MOD:  case DIV:  case UMOD:  case UDIV:
1563       return 1;
1564
1565     case MULT:
1566       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1567                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1568     default:
1569       if (BINARY_P (x))
1570         return contains_muldiv (XEXP (x, 0))
1571             || contains_muldiv (XEXP (x, 1));
1572
1573       if (UNARY_P (x))
1574         return contains_muldiv (XEXP (x, 0));
1575
1576       return 0;
1577     }
1578 }
1579 \f
1580 /* Determine whether INSN can be used in a combination.  Return nonzero if
1581    not.  This is used in try_combine to detect early some cases where we
1582    can't perform combinations.  */
1583
1584 static int
1585 cant_combine_insn_p (rtx insn)
1586 {
1587   rtx set;
1588   rtx src, dest;
1589
1590   /* If this isn't really an insn, we can't do anything.
1591      This can occur when flow deletes an insn that it has merged into an
1592      auto-increment address.  */
1593   if (! INSN_P (insn))
1594     return 1;
1595
1596   /* Never combine loads and stores involving hard regs that are likely
1597      to be spilled.  The register allocator can usually handle such
1598      reg-reg moves by tying.  If we allow the combiner to make
1599      substitutions of likely-spilled regs, reload might die.
1600      As an exception, we allow combinations involving fixed regs; these are
1601      not available to the register allocator so there's no risk involved.  */
1602
1603   set = single_set (insn);
1604   if (! set)
1605     return 0;
1606   src = SET_SRC (set);
1607   dest = SET_DEST (set);
1608   if (GET_CODE (src) == SUBREG)
1609     src = SUBREG_REG (src);
1610   if (GET_CODE (dest) == SUBREG)
1611     dest = SUBREG_REG (dest);
1612   if (REG_P (src) && REG_P (dest)
1613       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1614            && ! fixed_regs[REGNO (src)]
1615            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1616           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1617               && ! fixed_regs[REGNO (dest)]
1618               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1619     return 1;
1620
1621   return 0;
1622 }
1623
1624 struct likely_spilled_retval_info
1625 {
1626   unsigned regno, nregs;
1627   unsigned mask;
1628 };
1629
1630 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1631    hard registers that are known to be written to / clobbered in full.  */
1632 static void
1633 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1634 {
1635   struct likely_spilled_retval_info *info = data;
1636   unsigned regno, nregs;
1637   unsigned new_mask;
1638
1639   if (!REG_P (XEXP (set, 0)))
1640     return;
1641   regno = REGNO (x);
1642   if (regno >= info->regno + info->nregs)
1643     return;
1644   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1645   if (regno + nregs <= info->regno)
1646     return;
1647   new_mask = (2U << (nregs - 1)) - 1;
1648   if (regno < info->regno)
1649     new_mask >>= info->regno - regno;
1650   else
1651     new_mask <<= regno - info->regno;
1652   info->mask &= new_mask;
1653 }
1654
1655 /* Return nonzero iff part of the return value is live during INSN, and
1656    it is likely spilled.  This can happen when more than one insn is needed
1657    to copy the return value, e.g. when we consider to combine into the
1658    second copy insn for a complex value.  */
1659
1660 static int
1661 likely_spilled_retval_p (rtx insn)
1662 {
1663   rtx use = BB_END (this_basic_block);
1664   rtx reg, p;
1665   unsigned regno, nregs;
1666   /* We assume here that no machine mode needs more than
1667      32 hard registers when the value overlaps with a register
1668      for which FUNCTION_VALUE_REGNO_P is true.  */
1669   unsigned mask;
1670   struct likely_spilled_retval_info info;
1671
1672   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1673     return 0;
1674   reg = XEXP (PATTERN (use), 0);
1675   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1676     return 0;
1677   regno = REGNO (reg);
1678   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1679   if (nregs == 1)
1680     return 0;
1681   mask = (2U << (nregs - 1)) - 1;
1682
1683   /* Disregard parts of the return value that are set later.  */
1684   info.regno = regno;
1685   info.nregs = nregs;
1686   info.mask = mask;
1687   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1688     note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1689   mask = info.mask;
1690
1691   /* Check if any of the (probably) live return value registers is
1692      likely spilled.  */
1693   nregs --;
1694   do
1695     {
1696       if ((mask & 1 << nregs)
1697           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1698         return 1;
1699     } while (nregs--);
1700   return 0;
1701 }
1702
1703 /* Adjust INSN after we made a change to its destination.
1704
1705    Changing the destination can invalidate notes that say something about
1706    the results of the insn and a LOG_LINK pointing to the insn.  */
1707
1708 static void
1709 adjust_for_new_dest (rtx insn)
1710 {
1711   rtx *loc;
1712
1713   /* For notes, be conservative and simply remove them.  */
1714   loc = &REG_NOTES (insn);
1715   while (*loc)
1716     {
1717       enum reg_note kind = REG_NOTE_KIND (*loc);
1718       if (kind == REG_EQUAL || kind == REG_EQUIV)
1719         *loc = XEXP (*loc, 1);
1720       else
1721         loc = &XEXP (*loc, 1);
1722     }
1723
1724   /* The new insn will have a destination that was previously the destination
1725      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1726      the next use of that destination.  */
1727   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1728 }
1729
1730 /* Return TRUE if combine can reuse reg X in mode MODE.
1731    ADDED_SETS is nonzero if the original set is still required.  */
1732 static bool
1733 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1734 {
1735   unsigned int regno;
1736
1737   if (!REG_P(x))
1738     return false;
1739
1740   regno = REGNO (x);
1741   /* Allow hard registers if the new mode is legal, and occupies no more
1742      registers than the old mode.  */
1743   if (regno < FIRST_PSEUDO_REGISTER)
1744     return (HARD_REGNO_MODE_OK (regno, mode)
1745             && (hard_regno_nregs[regno][GET_MODE (x)]
1746                 >= hard_regno_nregs[regno][mode]));
1747
1748   /* Or a pseudo that is only used once.  */
1749   return (REG_N_SETS (regno) == 1 && !added_sets
1750           && !REG_USERVAR_P (x));
1751 }
1752
1753
1754 /* Check whether X, the destination of a set, refers to part of
1755    the register specified by REG.  */
1756
1757 static bool
1758 reg_subword_p (rtx x, rtx reg)
1759 {
1760   /* Check that reg is an integer mode register.  */
1761   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1762     return false;
1763
1764   if (GET_CODE (x) == STRICT_LOW_PART
1765       || GET_CODE (x) == ZERO_EXTRACT)
1766     x = XEXP (x, 0);
1767
1768   return GET_CODE (x) == SUBREG
1769          && SUBREG_REG (x) == reg
1770          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1771 }
1772
1773
1774 /* Try to combine the insns I1 and I2 into I3.
1775    Here I1 and I2 appear earlier than I3.
1776    I1 can be zero; then we combine just I2 into I3.
1777
1778    If we are combining three insns and the resulting insn is not recognized,
1779    try splitting it into two insns.  If that happens, I2 and I3 are retained
1780    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1781    are pseudo-deleted.
1782
1783    Return 0 if the combination does not work.  Then nothing is changed.
1784    If we did the combination, return the insn at which combine should
1785    resume scanning.
1786
1787    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1788    new direct jump instruction.  */
1789
1790 static rtx
1791 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1792 {
1793   /* New patterns for I3 and I2, respectively.  */
1794   rtx newpat, newi2pat = 0;
1795   rtvec newpat_vec_with_clobbers = 0;
1796   int substed_i2 = 0, substed_i1 = 0;
1797   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1798   int added_sets_1, added_sets_2;
1799   /* Total number of SETs to put into I3.  */
1800   int total_sets;
1801   /* Nonzero if I2's body now appears in I3.  */
1802   int i2_is_used;
1803   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1804   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1805   /* Contains I3 if the destination of I3 is used in its source, which means
1806      that the old life of I3 is being killed.  If that usage is placed into
1807      I2 and not in I3, a REG_DEAD note must be made.  */
1808   rtx i3dest_killed = 0;
1809   /* SET_DEST and SET_SRC of I2 and I1.  */
1810   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1811   /* PATTERN (I2), or a copy of it in certain cases.  */
1812   rtx i2pat;
1813   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1814   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1815   int i2dest_killed = 0, i1dest_killed = 0;
1816   int i1_feeds_i3 = 0;
1817   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1818   rtx new_i3_notes, new_i2_notes;
1819   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1820   int i3_subst_into_i2 = 0;
1821   /* Notes that I1, I2 or I3 is a MULT operation.  */
1822   int have_mult = 0;
1823   int swap_i2i3 = 0;
1824
1825   int maxreg;
1826   rtx temp;
1827   rtx link;
1828   int i;
1829
1830   /* Exit early if one of the insns involved can't be used for
1831      combinations.  */
1832   if (cant_combine_insn_p (i3)
1833       || cant_combine_insn_p (i2)
1834       || (i1 && cant_combine_insn_p (i1))
1835       || likely_spilled_retval_p (i3)
1836       /* We also can't do anything if I3 has a
1837          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1838          libcall.  */
1839 #if 0
1840       /* ??? This gives worse code, and appears to be unnecessary, since no
1841          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1842       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1843 #endif
1844       )
1845     return 0;
1846
1847   combine_attempts++;
1848   undobuf.other_insn = 0;
1849
1850   /* Reset the hard register usage information.  */
1851   CLEAR_HARD_REG_SET (newpat_used_regs);
1852
1853   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1854      code below, set I1 to be the earlier of the two insns.  */
1855   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1856     temp = i1, i1 = i2, i2 = temp;
1857
1858   added_links_insn = 0;
1859
1860   /* First check for one important special-case that the code below will
1861      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1862      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1863      we may be able to replace that destination with the destination of I3.
1864      This occurs in the common code where we compute both a quotient and
1865      remainder into a structure, in which case we want to do the computation
1866      directly into the structure to avoid register-register copies.
1867
1868      Note that this case handles both multiple sets in I2 and also
1869      cases where I2 has a number of CLOBBER or PARALLELs.
1870
1871      We make very conservative checks below and only try to handle the
1872      most common cases of this.  For example, we only handle the case
1873      where I2 and I3 are adjacent to avoid making difficult register
1874      usage tests.  */
1875
1876   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1877       && REG_P (SET_SRC (PATTERN (i3)))
1878       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1879       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1880       && GET_CODE (PATTERN (i2)) == PARALLEL
1881       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1882       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1883          below would need to check what is inside (and reg_overlap_mentioned_p
1884          doesn't support those codes anyway).  Don't allow those destinations;
1885          the resulting insn isn't likely to be recognized anyway.  */
1886       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1887       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1888       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1889                                     SET_DEST (PATTERN (i3)))
1890       && next_real_insn (i2) == i3)
1891     {
1892       rtx p2 = PATTERN (i2);
1893
1894       /* Make sure that the destination of I3,
1895          which we are going to substitute into one output of I2,
1896          is not used within another output of I2.  We must avoid making this:
1897          (parallel [(set (mem (reg 69)) ...)
1898                     (set (reg 69) ...)])
1899          which is not well-defined as to order of actions.
1900          (Besides, reload can't handle output reloads for this.)
1901
1902          The problem can also happen if the dest of I3 is a memory ref,
1903          if another dest in I2 is an indirect memory ref.  */
1904       for (i = 0; i < XVECLEN (p2, 0); i++)
1905         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1906              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1907             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1908                                         SET_DEST (XVECEXP (p2, 0, i))))
1909           break;
1910
1911       if (i == XVECLEN (p2, 0))
1912         for (i = 0; i < XVECLEN (p2, 0); i++)
1913           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1914                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1915               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1916             {
1917               combine_merges++;
1918
1919               subst_insn = i3;
1920               subst_low_cuid = INSN_CUID (i2);
1921
1922               added_sets_2 = added_sets_1 = 0;
1923               i2dest = SET_SRC (PATTERN (i3));
1924               i2dest_killed = dead_or_set_p (i2, i2dest);
1925
1926               /* Replace the dest in I2 with our dest and make the resulting
1927                  insn the new pattern for I3.  Then skip to where we
1928                  validate the pattern.  Everything was set up above.  */
1929               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1930                      SET_DEST (PATTERN (i3)));
1931
1932               newpat = p2;
1933               i3_subst_into_i2 = 1;
1934               goto validate_replacement;
1935             }
1936     }
1937
1938   /* If I2 is setting a pseudo to a constant and I3 is setting some
1939      sub-part of it to another constant, merge them by making a new
1940      constant.  */
1941   if (i1 == 0
1942       && (temp = single_set (i2)) != 0
1943       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1944           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1945       && GET_CODE (PATTERN (i3)) == SET
1946       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1947           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1948       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1949     {
1950       rtx dest = SET_DEST (PATTERN (i3));
1951       int offset = -1;
1952       int width = 0;
1953
1954       if (GET_CODE (dest) == ZERO_EXTRACT)
1955         {
1956           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1957               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1958             {
1959               width = INTVAL (XEXP (dest, 1));
1960               offset = INTVAL (XEXP (dest, 2));
1961               dest = XEXP (dest, 0);
1962               if (BITS_BIG_ENDIAN)
1963                 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
1964             }
1965         }
1966       else
1967         {
1968           if (GET_CODE (dest) == STRICT_LOW_PART)
1969             dest = XEXP (dest, 0);
1970           width = GET_MODE_BITSIZE (GET_MODE (dest));
1971           offset = 0;
1972         }
1973
1974       if (offset >= 0)
1975         {
1976           /* If this is the low part, we're done.  */
1977           if (subreg_lowpart_p (dest))
1978             ;
1979           /* Handle the case where inner is twice the size of outer.  */
1980           else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1981                    == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1982             offset += GET_MODE_BITSIZE (GET_MODE (dest));
1983           /* Otherwise give up for now.  */
1984           else
1985             offset = -1;
1986         }
1987
1988       if (offset >= 0)
1989         {
1990           HOST_WIDE_INT mhi, ohi, ihi;
1991           HOST_WIDE_INT mlo, olo, ilo;
1992           rtx inner = SET_SRC (PATTERN (i3));
1993           rtx outer = SET_SRC (temp);
1994
1995           if (GET_CODE (outer) == CONST_INT)
1996             {
1997               olo = INTVAL (outer);
1998               ohi = olo < 0 ? -1 : 0;
1999             }
2000           else
2001             {
2002               olo = CONST_DOUBLE_LOW (outer);
2003               ohi = CONST_DOUBLE_HIGH (outer);
2004             }
2005
2006           if (GET_CODE (inner) == CONST_INT)
2007             {
2008               ilo = INTVAL (inner);
2009               ihi = ilo < 0 ? -1 : 0;
2010             }
2011           else
2012             {
2013               ilo = CONST_DOUBLE_LOW (inner);
2014               ihi = CONST_DOUBLE_HIGH (inner);
2015             }
2016
2017           if (width < HOST_BITS_PER_WIDE_INT)
2018             {
2019               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2020               mhi = 0;
2021             }
2022           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2023             {
2024               mhi = ((unsigned HOST_WIDE_INT) 1
2025                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2026               mlo = -1;
2027             }
2028           else
2029             {
2030               mlo = -1;
2031               mhi = -1;
2032             }
2033
2034           ilo &= mlo;
2035           ihi &= mhi;
2036
2037           if (offset >= HOST_BITS_PER_WIDE_INT)
2038             {
2039               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2040               mlo = 0;
2041               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2042               ilo = 0;
2043             }
2044           else if (offset > 0)
2045             {
2046               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2047                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2048               mlo = mlo << offset;
2049               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2050                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2051               ilo = ilo << offset;
2052             }
2053
2054           olo = (olo & ~mlo) | ilo;
2055           ohi = (ohi & ~mhi) | ihi;
2056
2057           combine_merges++;
2058           subst_insn = i3;
2059           subst_low_cuid = INSN_CUID (i2);
2060           added_sets_2 = added_sets_1 = 0;
2061           i2dest = SET_DEST (temp);
2062           i2dest_killed = dead_or_set_p (i2, i2dest);
2063
2064           SUBST (SET_SRC (temp),
2065                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2066
2067           newpat = PATTERN (i2);
2068           goto validate_replacement;
2069         }
2070     }
2071
2072 #ifndef HAVE_cc0
2073   /* If we have no I1 and I2 looks like:
2074         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2075                    (set Y OP)])
2076      make up a dummy I1 that is
2077         (set Y OP)
2078      and change I2 to be
2079         (set (reg:CC X) (compare:CC Y (const_int 0)))
2080
2081      (We can ignore any trailing CLOBBERs.)
2082
2083      This undoes a previous combination and allows us to match a branch-and-
2084      decrement insn.  */
2085
2086   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2087       && XVECLEN (PATTERN (i2), 0) >= 2
2088       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2089       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2090           == MODE_CC)
2091       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2092       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2093       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2094       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2095       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2096                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2097     {
2098       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2099         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2100           break;
2101
2102       if (i == 1)
2103         {
2104           /* We make I1 with the same INSN_UID as I2.  This gives it
2105              the same INSN_CUID for value tracking.  Our fake I1 will
2106              never appear in the insn stream so giving it the same INSN_UID
2107              as I2 will not cause a problem.  */
2108
2109           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2110                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2111                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2112                              NULL_RTX);
2113
2114           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2115           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2116                  SET_DEST (PATTERN (i1)));
2117         }
2118     }
2119 #endif
2120
2121   /* Verify that I2 and I1 are valid for combining.  */
2122   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2123       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2124     {
2125       undo_all ();
2126       return 0;
2127     }
2128
2129   /* Record whether I2DEST is used in I2SRC and similarly for the other
2130      cases.  Knowing this will help in register status updating below.  */
2131   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2132   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2133   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2134   i2dest_killed = dead_or_set_p (i2, i2dest);
2135   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2136
2137   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2138      in I2SRC.  */
2139   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2140
2141   /* Ensure that I3's pattern can be the destination of combines.  */
2142   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2143                           i1 && i2dest_in_i1src && i1_feeds_i3,
2144                           &i3dest_killed))
2145     {
2146       undo_all ();
2147       return 0;
2148     }
2149
2150   /* See if any of the insns is a MULT operation.  Unless one is, we will
2151      reject a combination that is, since it must be slower.  Be conservative
2152      here.  */
2153   if (GET_CODE (i2src) == MULT
2154       || (i1 != 0 && GET_CODE (i1src) == MULT)
2155       || (GET_CODE (PATTERN (i3)) == SET
2156           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2157     have_mult = 1;
2158
2159   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2160      We used to do this EXCEPT in one case: I3 has a post-inc in an
2161      output operand.  However, that exception can give rise to insns like
2162         mov r3,(r3)+
2163      which is a famous insn on the PDP-11 where the value of r3 used as the
2164      source was model-dependent.  Avoid this sort of thing.  */
2165
2166 #if 0
2167   if (!(GET_CODE (PATTERN (i3)) == SET
2168         && REG_P (SET_SRC (PATTERN (i3)))
2169         && MEM_P (SET_DEST (PATTERN (i3)))
2170         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2171             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2172     /* It's not the exception.  */
2173 #endif
2174 #ifdef AUTO_INC_DEC
2175     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2176       if (REG_NOTE_KIND (link) == REG_INC
2177           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2178               || (i1 != 0
2179                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2180         {
2181           undo_all ();
2182           return 0;
2183         }
2184 #endif
2185
2186   /* See if the SETs in I1 or I2 need to be kept around in the merged
2187      instruction: whenever the value set there is still needed past I3.
2188      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2189
2190      For the SET in I1, we have two cases:  If I1 and I2 independently
2191      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2192      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2193      in I1 needs to be kept around unless I1DEST dies or is set in either
2194      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2195      I1DEST.  If so, we know I1 feeds into I2.  */
2196
2197   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2198
2199   added_sets_1
2200     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2201                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2202
2203   /* If the set in I2 needs to be kept around, we must make a copy of
2204      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2205      PATTERN (I2), we are only substituting for the original I1DEST, not into
2206      an already-substituted copy.  This also prevents making self-referential
2207      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2208      I2DEST.  */
2209
2210   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2211            ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2212            : PATTERN (i2));
2213
2214   if (added_sets_2)
2215     i2pat = copy_rtx (i2pat);
2216
2217   combine_merges++;
2218
2219   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2220
2221   maxreg = max_reg_num ();
2222
2223   subst_insn = i3;
2224
2225 #ifndef HAVE_cc0
2226   /* Many machines that don't use CC0 have insns that can both perform an
2227      arithmetic operation and set the condition code.  These operations will
2228      be represented as a PARALLEL with the first element of the vector
2229      being a COMPARE of an arithmetic operation with the constant zero.
2230      The second element of the vector will set some pseudo to the result
2231      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2232      match such a pattern and so will generate an extra insn.   Here we test
2233      for this case, where both the comparison and the operation result are
2234      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2235      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2236
2237   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2238       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2239       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2240       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2241     {
2242 #ifdef SELECT_CC_MODE
2243       rtx *cc_use;
2244       enum machine_mode compare_mode;
2245 #endif
2246
2247       newpat = PATTERN (i3);
2248       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2249
2250       i2_is_used = 1;
2251
2252 #ifdef SELECT_CC_MODE
2253       /* See if a COMPARE with the operand we substituted in should be done
2254          with the mode that is currently being used.  If not, do the same
2255          processing we do in `subst' for a SET; namely, if the destination
2256          is used only once, try to replace it with a register of the proper
2257          mode and also replace the COMPARE.  */
2258       if (undobuf.other_insn == 0
2259           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2260                                         &undobuf.other_insn))
2261           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2262                                               i2src, const0_rtx))
2263               != GET_MODE (SET_DEST (newpat))))
2264         {
2265           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2266                                    compare_mode))
2267             {
2268               unsigned int regno = REGNO (SET_DEST (newpat));
2269               rtx new_dest;
2270
2271               if (regno < FIRST_PSEUDO_REGISTER)
2272                 new_dest = gen_rtx_REG (compare_mode, regno);
2273               else
2274                 {
2275                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2276                   new_dest = regno_reg_rtx[regno];
2277                 }
2278
2279               SUBST (SET_DEST (newpat), new_dest);
2280               SUBST (XEXP (*cc_use, 0), new_dest);
2281               SUBST (SET_SRC (newpat),
2282                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2283             }
2284           else
2285             undobuf.other_insn = 0;
2286         }
2287 #endif
2288     }
2289   else
2290 #endif
2291     {
2292       /* It is possible that the source of I2 or I1 may be performing
2293          an unneeded operation, such as a ZERO_EXTEND of something
2294          that is known to have the high part zero.  Handle that case
2295          by letting subst look at the innermost one of them.
2296
2297          Another way to do this would be to have a function that tries
2298          to simplify a single insn instead of merging two or more
2299          insns.  We don't do this because of the potential of infinite
2300          loops and because of the potential extra memory required.
2301          However, doing it the way we are is a bit of a kludge and
2302          doesn't catch all cases.
2303
2304          But only do this if -fexpensive-optimizations since it slows
2305          things down and doesn't usually win.
2306
2307          This is not done in the COMPARE case above because the
2308          unmodified I2PAT is used in the PARALLEL and so a pattern
2309          with a modified I2SRC would not match.  */
2310
2311       if (flag_expensive_optimizations)
2312         {
2313           /* Pass pc_rtx so no substitutions are done, just
2314              simplifications.  */
2315           if (i1)
2316             {
2317               subst_low_cuid = INSN_CUID (i1);
2318               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2319             }
2320           else
2321             {
2322               subst_low_cuid = INSN_CUID (i2);
2323               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2324             }
2325         }
2326
2327       n_occurrences = 0;                /* `subst' counts here */
2328
2329       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2330          need to make a unique copy of I2SRC each time we substitute it
2331          to avoid self-referential rtl.  */
2332
2333       subst_low_cuid = INSN_CUID (i2);
2334       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2335                       ! i1_feeds_i3 && i1dest_in_i1src);
2336       substed_i2 = 1;
2337
2338       /* Record whether i2's body now appears within i3's body.  */
2339       i2_is_used = n_occurrences;
2340     }
2341
2342   /* If we already got a failure, don't try to do more.  Otherwise,
2343      try to substitute in I1 if we have it.  */
2344
2345   if (i1 && GET_CODE (newpat) != CLOBBER)
2346     {
2347       /* Before we can do this substitution, we must redo the test done
2348          above (see detailed comments there) that ensures  that I1DEST
2349          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2350
2351       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2352                               0, (rtx*) 0))
2353         {
2354           undo_all ();
2355           return 0;
2356         }
2357
2358       n_occurrences = 0;
2359       subst_low_cuid = INSN_CUID (i1);
2360       newpat = subst (newpat, i1dest, i1src, 0, 0);
2361       substed_i1 = 1;
2362     }
2363
2364   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2365      to count all the ways that I2SRC and I1SRC can be used.  */
2366   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2367        && i2_is_used + added_sets_2 > 1)
2368       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2369           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2370               > 1))
2371       /* Fail if we tried to make a new register.  */
2372       || max_reg_num () != maxreg
2373       /* Fail if we couldn't do something and have a CLOBBER.  */
2374       || GET_CODE (newpat) == CLOBBER
2375       /* Fail if this new pattern is a MULT and we didn't have one before
2376          at the outer level.  */
2377       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2378           && ! have_mult))
2379     {
2380       undo_all ();
2381       return 0;
2382     }
2383
2384   /* If the actions of the earlier insns must be kept
2385      in addition to substituting them into the latest one,
2386      we must make a new PARALLEL for the latest insn
2387      to hold additional the SETs.  */
2388
2389   if (added_sets_1 || added_sets_2)
2390     {
2391       combine_extras++;
2392
2393       if (GET_CODE (newpat) == PARALLEL)
2394         {
2395           rtvec old = XVEC (newpat, 0);
2396           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2397           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2398           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2399                   sizeof (old->elem[0]) * old->num_elem);
2400         }
2401       else
2402         {
2403           rtx old = newpat;
2404           total_sets = 1 + added_sets_1 + added_sets_2;
2405           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2406           XVECEXP (newpat, 0, 0) = old;
2407         }
2408
2409       if (added_sets_1)
2410         XVECEXP (newpat, 0, --total_sets)
2411           = (GET_CODE (PATTERN (i1)) == PARALLEL
2412              ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2413
2414       if (added_sets_2)
2415         {
2416           /* If there is no I1, use I2's body as is.  We used to also not do
2417              the subst call below if I2 was substituted into I3,
2418              but that could lose a simplification.  */
2419           if (i1 == 0)
2420             XVECEXP (newpat, 0, --total_sets) = i2pat;
2421           else
2422             /* See comment where i2pat is assigned.  */
2423             XVECEXP (newpat, 0, --total_sets)
2424               = subst (i2pat, i1dest, i1src, 0, 0);
2425         }
2426     }
2427
2428   /* We come here when we are replacing a destination in I2 with the
2429      destination of I3.  */
2430  validate_replacement:
2431
2432   /* Note which hard regs this insn has as inputs.  */
2433   mark_used_regs_combine (newpat);
2434
2435   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2436      consider splitting this pattern, we might need these clobbers.  */
2437   if (i1 && GET_CODE (newpat) == PARALLEL
2438       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2439     {
2440       int len = XVECLEN (newpat, 0);
2441
2442       newpat_vec_with_clobbers = rtvec_alloc (len);
2443       for (i = 0; i < len; i++)
2444         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2445     }
2446
2447   /* Is the result of combination a valid instruction?  */
2448   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2449
2450   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2451      the second SET's destination is a register that is unused and isn't
2452      marked as an instruction that might trap in an EH region.  In that case,
2453      we just need the first SET.   This can occur when simplifying a divmod
2454      insn.  We *must* test for this case here because the code below that
2455      splits two independent SETs doesn't handle this case correctly when it
2456      updates the register status.
2457
2458      It's pointless doing this if we originally had two sets, one from
2459      i3, and one from i2.  Combining then splitting the parallel results
2460      in the original i2 again plus an invalid insn (which we delete).
2461      The net effect is only to move instructions around, which makes
2462      debug info less accurate.
2463
2464      Also check the case where the first SET's destination is unused.
2465      That would not cause incorrect code, but does cause an unneeded
2466      insn to remain.  */
2467
2468   if (insn_code_number < 0
2469       && !(added_sets_2 && i1 == 0)
2470       && GET_CODE (newpat) == PARALLEL
2471       && XVECLEN (newpat, 0) == 2
2472       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2473       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2474       && asm_noperands (newpat) < 0)
2475     {
2476       rtx set0 = XVECEXP (newpat, 0, 0);
2477       rtx set1 = XVECEXP (newpat, 0, 1);
2478       rtx note;
2479
2480       if (((REG_P (SET_DEST (set1))
2481             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2482            || (GET_CODE (SET_DEST (set1)) == SUBREG
2483                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2484           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2485               || INTVAL (XEXP (note, 0)) <= 0)
2486           && ! side_effects_p (SET_SRC (set1)))
2487         {
2488           newpat = set0;
2489           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2490         }
2491
2492       else if (((REG_P (SET_DEST (set0))
2493                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2494                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2495                     && find_reg_note (i3, REG_UNUSED,
2496                                       SUBREG_REG (SET_DEST (set0)))))
2497                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2498                    || INTVAL (XEXP (note, 0)) <= 0)
2499                && ! side_effects_p (SET_SRC (set0)))
2500         {
2501           newpat = set1;
2502           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2503
2504           if (insn_code_number >= 0)
2505             {
2506               /* If we will be able to accept this, we have made a
2507                  change to the destination of I3.  This requires us to
2508                  do a few adjustments.  */
2509
2510               PATTERN (i3) = newpat;
2511               adjust_for_new_dest (i3);
2512             }
2513         }
2514     }
2515
2516   /* If we were combining three insns and the result is a simple SET
2517      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2518      insns.  There are two ways to do this.  It can be split using a
2519      machine-specific method (like when you have an addition of a large
2520      constant) or by combine in the function find_split_point.  */
2521
2522   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2523       && asm_noperands (newpat) < 0)
2524     {
2525       rtx m_split, *split;
2526
2527       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2528          use I2DEST as a scratch register will help.  In the latter case,
2529          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2530
2531       m_split = split_insns (newpat, i3);
2532
2533       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2534          inputs of NEWPAT.  */
2535
2536       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2537          possible to try that as a scratch reg.  This would require adding
2538          more code to make it work though.  */
2539
2540       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2541         {
2542           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2543
2544           /* First try to split using the original register as a
2545              scratch register.  */
2546           m_split = split_insns (gen_rtx_PARALLEL
2547                                  (VOIDmode,
2548                                   gen_rtvec (2, newpat,
2549                                              gen_rtx_CLOBBER (VOIDmode,
2550                                                               i2dest))),
2551                                  i3);
2552
2553           /* If that didn't work, try changing the mode of I2DEST if
2554              we can.  */
2555           if (m_split == 0
2556               && new_mode != GET_MODE (i2dest)
2557               && new_mode != VOIDmode
2558               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2559             {
2560               enum machine_mode old_mode = GET_MODE (i2dest);
2561               rtx ni2dest;
2562
2563               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2564                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2565               else
2566                 {
2567                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2568                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
2569                 }
2570
2571               m_split = split_insns (gen_rtx_PARALLEL
2572                                      (VOIDmode,
2573                                       gen_rtvec (2, newpat,
2574                                                  gen_rtx_CLOBBER (VOIDmode,
2575                                                                   ni2dest))),
2576                                      i3);
2577
2578               if (m_split == 0
2579                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2580                 {
2581                   struct undo *buf;
2582
2583                   PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2584                   buf = undobuf.undos;
2585                   undobuf.undos = buf->next;
2586                   buf->next = undobuf.frees;
2587                   undobuf.frees = buf;
2588                 }
2589             }
2590         }
2591
2592       /* If recog_for_combine has discarded clobbers, try to use them
2593          again for the split.  */
2594       if (m_split == 0 && newpat_vec_with_clobbers)
2595         m_split
2596           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2597                                            newpat_vec_with_clobbers), i3);
2598
2599       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2600         {
2601           m_split = PATTERN (m_split);
2602           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2603           if (insn_code_number >= 0)
2604             newpat = m_split;
2605         }
2606       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2607                && (next_real_insn (i2) == i3
2608                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2609         {
2610           rtx i2set, i3set;
2611           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2612           newi2pat = PATTERN (m_split);
2613
2614           i3set = single_set (NEXT_INSN (m_split));
2615           i2set = single_set (m_split);
2616
2617           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2618
2619           /* If I2 or I3 has multiple SETs, we won't know how to track
2620              register status, so don't use these insns.  If I2's destination
2621              is used between I2 and I3, we also can't use these insns.  */
2622
2623           if (i2_code_number >= 0 && i2set && i3set
2624               && (next_real_insn (i2) == i3
2625                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2626             insn_code_number = recog_for_combine (&newi3pat, i3,
2627                                                   &new_i3_notes);
2628           if (insn_code_number >= 0)
2629             newpat = newi3pat;
2630
2631           /* It is possible that both insns now set the destination of I3.
2632              If so, we must show an extra use of it.  */
2633
2634           if (insn_code_number >= 0)
2635             {
2636               rtx new_i3_dest = SET_DEST (i3set);
2637               rtx new_i2_dest = SET_DEST (i2set);
2638
2639               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2640                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2641                      || GET_CODE (new_i3_dest) == SUBREG)
2642                 new_i3_dest = XEXP (new_i3_dest, 0);
2643
2644               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2645                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2646                      || GET_CODE (new_i2_dest) == SUBREG)
2647                 new_i2_dest = XEXP (new_i2_dest, 0);
2648
2649               if (REG_P (new_i3_dest)
2650                   && REG_P (new_i2_dest)
2651                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2652                 REG_N_SETS (REGNO (new_i2_dest))++;
2653             }
2654         }
2655
2656       /* If we can split it and use I2DEST, go ahead and see if that
2657          helps things be recognized.  Verify that none of the registers
2658          are set between I2 and I3.  */
2659       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2660 #ifdef HAVE_cc0
2661           && REG_P (i2dest)
2662 #endif
2663           /* We need I2DEST in the proper mode.  If it is a hard register
2664              or the only use of a pseudo, we can change its mode.
2665              Make sure we don't change a hard register to have a mode that
2666              isn't valid for it, or change the number of registers.  */
2667           && (GET_MODE (*split) == GET_MODE (i2dest)
2668               || GET_MODE (*split) == VOIDmode
2669               || can_change_dest_mode (i2dest, added_sets_2,
2670                                        GET_MODE (*split)))
2671           && (next_real_insn (i2) == i3
2672               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2673           /* We can't overwrite I2DEST if its value is still used by
2674              NEWPAT.  */
2675           && ! reg_referenced_p (i2dest, newpat))
2676         {
2677           rtx newdest = i2dest;
2678           enum rtx_code split_code = GET_CODE (*split);
2679           enum machine_mode split_mode = GET_MODE (*split);
2680           bool subst_done = false;
2681           newi2pat = NULL_RTX;
2682
2683           /* Get NEWDEST as a register in the proper mode.  We have already
2684              validated that we can do this.  */
2685           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2686             {
2687               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2688                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2689               else
2690                 {
2691                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2692                   newdest = regno_reg_rtx[REGNO (i2dest)];
2693                 }
2694             }
2695
2696           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2697              an ASHIFT.  This can occur if it was inside a PLUS and hence
2698              appeared to be a memory address.  This is a kludge.  */
2699           if (split_code == MULT
2700               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2701               && INTVAL (XEXP (*split, 1)) > 0
2702               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2703             {
2704               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2705                                              XEXP (*split, 0), GEN_INT (i)));
2706               /* Update split_code because we may not have a multiply
2707                  anymore.  */
2708               split_code = GET_CODE (*split);
2709             }
2710
2711 #ifdef INSN_SCHEDULING
2712           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2713              be written as a ZERO_EXTEND.  */
2714           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2715             {
2716 #ifdef LOAD_EXTEND_OP
2717               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2718                  what it really is.  */
2719               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2720                   == SIGN_EXTEND)
2721                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2722                                                     SUBREG_REG (*split)));
2723               else
2724 #endif
2725                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2726                                                     SUBREG_REG (*split)));
2727             }
2728 #endif
2729
2730           /* Attempt to split binary operators using arithmetic identities.  */
2731           if (BINARY_P (SET_SRC (newpat))
2732               && split_mode == GET_MODE (SET_SRC (newpat))
2733               && ! side_effects_p (SET_SRC (newpat)))
2734             {
2735               rtx setsrc = SET_SRC (newpat);
2736               enum machine_mode mode = GET_MODE (setsrc);
2737               enum rtx_code code = GET_CODE (setsrc);
2738               rtx src_op0 = XEXP (setsrc, 0);
2739               rtx src_op1 = XEXP (setsrc, 1);
2740
2741               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
2742               if (rtx_equal_p (src_op0, src_op1))
2743                 {
2744                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2745                   SUBST (XEXP (setsrc, 0), newdest);
2746                   SUBST (XEXP (setsrc, 1), newdest);
2747                   subst_done = true;
2748                 }
2749               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
2750               else if ((code == PLUS || code == MULT)
2751                        && GET_CODE (src_op0) == code
2752                        && GET_CODE (XEXP (src_op0, 0)) == code
2753                        && (INTEGRAL_MODE_P (mode)
2754                            || (FLOAT_MODE_P (mode)
2755                                && flag_unsafe_math_optimizations)))
2756                 {
2757                   rtx p = XEXP (XEXP (src_op0, 0), 0);
2758                   rtx q = XEXP (XEXP (src_op0, 0), 1);
2759                   rtx r = XEXP (src_op0, 1);
2760                   rtx s = src_op1;
2761
2762                   /* Split both "((X op Y) op X) op Y" and
2763                      "((X op Y) op Y) op X" as "T op T" where T is
2764                      "X op Y".  */
2765                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2766                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2767                     {
2768                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
2769                                               XEXP (src_op0, 0));
2770                       SUBST (XEXP (setsrc, 0), newdest);
2771                       SUBST (XEXP (setsrc, 1), newdest);
2772                       subst_done = true;
2773                     }
2774                   /* Split "((X op X) op Y) op Y)" as "T op T" where
2775                      T is "X op Y".  */
2776                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2777                     {
2778                       rtx tmp = simplify_gen_binary (code, mode, p, r);
2779                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2780                       SUBST (XEXP (setsrc, 0), newdest);
2781                       SUBST (XEXP (setsrc, 1), newdest);
2782                       subst_done = true;
2783                     }
2784                 }
2785             }
2786
2787           if (!subst_done)
2788             {
2789               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2790               SUBST (*split, newdest);
2791             }
2792
2793           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2794
2795           /* recog_for_combine might have added CLOBBERs to newi2pat.
2796              Make sure NEWPAT does not depend on the clobbered regs.  */
2797           if (GET_CODE (newi2pat) == PARALLEL)
2798             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2799               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2800                 {
2801                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2802                   if (reg_overlap_mentioned_p (reg, newpat))
2803                     {
2804                       undo_all ();
2805                       return 0;
2806                     }
2807                 }
2808
2809           /* If the split point was a MULT and we didn't have one before,
2810              don't use one now.  */
2811           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2812             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2813         }
2814     }
2815
2816   /* Check for a case where we loaded from memory in a narrow mode and
2817      then sign extended it, but we need both registers.  In that case,
2818      we have a PARALLEL with both loads from the same memory location.
2819      We can split this into a load from memory followed by a register-register
2820      copy.  This saves at least one insn, more if register allocation can
2821      eliminate the copy.
2822
2823      We cannot do this if the destination of the first assignment is a
2824      condition code register or cc0.  We eliminate this case by making sure
2825      the SET_DEST and SET_SRC have the same mode.
2826
2827      We cannot do this if the destination of the second assignment is
2828      a register that we have already assumed is zero-extended.  Similarly
2829      for a SUBREG of such a register.  */
2830
2831   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2832            && GET_CODE (newpat) == PARALLEL
2833            && XVECLEN (newpat, 0) == 2
2834            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2835            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2836            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2837                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2838            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2839            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2840                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2841            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2842                                    INSN_CUID (i2))
2843            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2844            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2845            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2846                  (REG_P (temp)
2847                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2848                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2849                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2850                   && (reg_stat[REGNO (temp)].nonzero_bits
2851                       != GET_MODE_MASK (word_mode))))
2852            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2853                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2854                      (REG_P (temp)
2855                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2856                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2857                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2858                       && (reg_stat[REGNO (temp)].nonzero_bits
2859                           != GET_MODE_MASK (word_mode)))))
2860            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2861                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2862            && ! find_reg_note (i3, REG_UNUSED,
2863                                SET_DEST (XVECEXP (newpat, 0, 0))))
2864     {
2865       rtx ni2dest;
2866
2867       newi2pat = XVECEXP (newpat, 0, 0);
2868       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2869       newpat = XVECEXP (newpat, 0, 1);
2870       SUBST (SET_SRC (newpat),
2871              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2872       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2873
2874       if (i2_code_number >= 0)
2875         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2876
2877       if (insn_code_number >= 0)
2878         swap_i2i3 = 1;
2879     }
2880
2881   /* Similarly, check for a case where we have a PARALLEL of two independent
2882      SETs but we started with three insns.  In this case, we can do the sets
2883      as two separate insns.  This case occurs when some SET allows two
2884      other insns to combine, but the destination of that SET is still live.  */
2885
2886   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2887            && GET_CODE (newpat) == PARALLEL
2888            && XVECLEN (newpat, 0) == 2
2889            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2890            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2891            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2892            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2893            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2894            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2895            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2896                                    INSN_CUID (i2))
2897            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2898                                   XVECEXP (newpat, 0, 0))
2899            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2900                                   XVECEXP (newpat, 0, 1))
2901            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2902                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2903     {
2904       /* Normally, it doesn't matter which of the two is done first,
2905          but it does if one references cc0.  In that case, it has to
2906          be first.  */
2907 #ifdef HAVE_cc0
2908       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2909         {
2910           newi2pat = XVECEXP (newpat, 0, 0);
2911           newpat = XVECEXP (newpat, 0, 1);
2912         }
2913       else
2914 #endif
2915         {
2916           newi2pat = XVECEXP (newpat, 0, 1);
2917           newpat = XVECEXP (newpat, 0, 0);
2918         }
2919
2920       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2921
2922       if (i2_code_number >= 0)
2923         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2924     }
2925
2926   /* If it still isn't recognized, fail and change things back the way they
2927      were.  */
2928   if ((insn_code_number < 0
2929        /* Is the result a reasonable ASM_OPERANDS?  */
2930        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2931     {
2932       undo_all ();
2933       return 0;
2934     }
2935
2936   /* If we had to change another insn, make sure it is valid also.  */
2937   if (undobuf.other_insn)
2938     {
2939       rtx other_pat = PATTERN (undobuf.other_insn);
2940       rtx new_other_notes;
2941       rtx note, next;
2942
2943       CLEAR_HARD_REG_SET (newpat_used_regs);
2944
2945       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2946                                              &new_other_notes);
2947
2948       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2949         {
2950           undo_all ();
2951           return 0;
2952         }
2953
2954       PATTERN (undobuf.other_insn) = other_pat;
2955
2956       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2957          are still valid.  Then add any non-duplicate notes added by
2958          recog_for_combine.  */
2959       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2960         {
2961           next = XEXP (note, 1);
2962
2963           if (REG_NOTE_KIND (note) == REG_UNUSED
2964               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2965             {
2966               if (REG_P (XEXP (note, 0)))
2967                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2968
2969               remove_note (undobuf.other_insn, note);
2970             }
2971         }
2972
2973       for (note = new_other_notes; note; note = XEXP (note, 1))
2974         if (REG_P (XEXP (note, 0)))
2975           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2976
2977       distribute_notes (new_other_notes, undobuf.other_insn,
2978                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2979     }
2980 #ifdef HAVE_cc0
2981   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2982      they are adjacent to each other or not.  */
2983   {
2984     rtx p = prev_nonnote_insn (i3);
2985     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2986         && sets_cc0_p (newi2pat))
2987       {
2988         undo_all ();
2989         return 0;
2990       }
2991   }
2992 #endif
2993
2994   /* Only allow this combination if insn_rtx_costs reports that the
2995      replacement instructions are cheaper than the originals.  */
2996   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2997     {
2998       undo_all ();
2999       return 0;
3000     }
3001
3002   /* We now know that we can do this combination.  Merge the insns and
3003      update the status of registers and LOG_LINKS.  */
3004
3005   if (swap_i2i3)
3006     {
3007       rtx insn;
3008       rtx link;
3009       rtx ni2dest;
3010
3011       /* I3 now uses what used to be its destination and which is now
3012          I2's destination.  This requires us to do a few adjustments.  */
3013       PATTERN (i3) = newpat;
3014       adjust_for_new_dest (i3);
3015
3016       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3017          so we still will.
3018
3019          However, some later insn might be using I2's dest and have
3020          a LOG_LINK pointing at I3.  We must remove this link.
3021          The simplest way to remove the link is to point it at I1,
3022          which we know will be a NOTE.  */
3023
3024       /* newi2pat is usually a SET here; however, recog_for_combine might
3025          have added some clobbers.  */
3026       if (GET_CODE (newi2pat) == PARALLEL)
3027         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3028       else
3029         ni2dest = SET_DEST (newi2pat);
3030
3031       for (insn = NEXT_INSN (i3);
3032            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3033                     || insn != BB_HEAD (this_basic_block->next_bb));
3034            insn = NEXT_INSN (insn))
3035         {
3036           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3037             {
3038               for (link = LOG_LINKS (insn); link;
3039                    link = XEXP (link, 1))
3040                 if (XEXP (link, 0) == i3)
3041                   XEXP (link, 0) = i1;
3042
3043               break;
3044             }
3045         }
3046     }
3047
3048   {
3049     rtx i3notes, i2notes, i1notes = 0;
3050     rtx i3links, i2links, i1links = 0;
3051     rtx midnotes = 0;
3052     unsigned int regno;
3053     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3054        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3055        same as i3dest, in which case newi2pat may be setting i1dest.  */
3056     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3057                    || i2dest_in_i2src || i2dest_in_i1src
3058                    || !i2dest_killed
3059                    ? 0 : i2dest);
3060     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3061                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3062                    || !i1dest_killed
3063                    ? 0 : i1dest);
3064
3065     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3066        clear them.  */
3067     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3068     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3069     if (i1)
3070       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3071
3072     /* Ensure that we do not have something that should not be shared but
3073        occurs multiple times in the new insns.  Check this by first
3074        resetting all the `used' flags and then copying anything is shared.  */
3075
3076     reset_used_flags (i3notes);
3077     reset_used_flags (i2notes);
3078     reset_used_flags (i1notes);
3079     reset_used_flags (newpat);
3080     reset_used_flags (newi2pat);
3081     if (undobuf.other_insn)
3082       reset_used_flags (PATTERN (undobuf.other_insn));
3083
3084     i3notes = copy_rtx_if_shared (i3notes);
3085     i2notes = copy_rtx_if_shared (i2notes);
3086     i1notes = copy_rtx_if_shared (i1notes);
3087     newpat = copy_rtx_if_shared (newpat);
3088     newi2pat = copy_rtx_if_shared (newi2pat);
3089     if (undobuf.other_insn)
3090       reset_used_flags (PATTERN (undobuf.other_insn));
3091
3092     INSN_CODE (i3) = insn_code_number;
3093     PATTERN (i3) = newpat;
3094
3095     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3096       {
3097         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3098
3099         reset_used_flags (call_usage);
3100         call_usage = copy_rtx (call_usage);
3101
3102         if (substed_i2)
3103           replace_rtx (call_usage, i2dest, i2src);
3104
3105         if (substed_i1)
3106           replace_rtx (call_usage, i1dest, i1src);
3107
3108         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3109       }
3110
3111     if (undobuf.other_insn)
3112       INSN_CODE (undobuf.other_insn) = other_code_number;
3113
3114     /* We had one special case above where I2 had more than one set and
3115        we replaced a destination of one of those sets with the destination
3116        of I3.  In that case, we have to update LOG_LINKS of insns later
3117        in this basic block.  Note that this (expensive) case is rare.
3118
3119        Also, in this case, we must pretend that all REG_NOTEs for I2
3120        actually came from I3, so that REG_UNUSED notes from I2 will be
3121        properly handled.  */
3122
3123     if (i3_subst_into_i2)
3124       {
3125         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3126           if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
3127               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3128               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3129               && ! find_reg_note (i2, REG_UNUSED,
3130                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3131             for (temp = NEXT_INSN (i2);
3132                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3133                           || BB_HEAD (this_basic_block) != temp);
3134                  temp = NEXT_INSN (temp))
3135               if (temp != i3 && INSN_P (temp))
3136                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3137                   if (XEXP (link, 0) == i2)
3138                     XEXP (link, 0) = i3;
3139
3140         if (i3notes)
3141           {
3142             rtx link = i3notes;
3143             while (XEXP (link, 1))
3144               link = XEXP (link, 1);
3145             XEXP (link, 1) = i2notes;
3146           }
3147         else
3148           i3notes = i2notes;
3149         i2notes = 0;
3150       }
3151
3152     LOG_LINKS (i3) = 0;
3153     REG_NOTES (i3) = 0;
3154     LOG_LINKS (i2) = 0;
3155     REG_NOTES (i2) = 0;
3156
3157     if (newi2pat)
3158       {
3159         INSN_CODE (i2) = i2_code_number;
3160         PATTERN (i2) = newi2pat;
3161       }
3162     else
3163       SET_INSN_DELETED (i2);
3164
3165     if (i1)
3166       {
3167         LOG_LINKS (i1) = 0;
3168         REG_NOTES (i1) = 0;
3169         SET_INSN_DELETED (i1);
3170       }
3171
3172     /* Get death notes for everything that is now used in either I3 or
3173        I2 and used to die in a previous insn.  If we built two new
3174        patterns, move from I1 to I2 then I2 to I3 so that we get the
3175        proper movement on registers that I2 modifies.  */
3176
3177     if (newi2pat)
3178       {
3179         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3180         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3181       }
3182     else
3183       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3184                    i3, &midnotes);
3185
3186     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3187     if (i3notes)
3188       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3189                         elim_i2, elim_i1);
3190     if (i2notes)
3191       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3192                         elim_i2, elim_i1);
3193     if (i1notes)
3194       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3195                         elim_i2, elim_i1);
3196     if (midnotes)
3197       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3198                         elim_i2, elim_i1);
3199
3200     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3201        know these are REG_UNUSED and want them to go to the desired insn,
3202        so we always pass it as i3.  We have not counted the notes in
3203        reg_n_deaths yet, so we need to do so now.  */
3204
3205     if (newi2pat && new_i2_notes)
3206       {
3207         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3208           if (REG_P (XEXP (temp, 0)))
3209             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3210
3211         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3212       }
3213
3214     if (new_i3_notes)
3215       {
3216         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3217           if (REG_P (XEXP (temp, 0)))
3218             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3219
3220         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3221       }
3222
3223     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3224        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3225        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3226        in that case, it might delete I2.  Similarly for I2 and I1.
3227        Show an additional death due to the REG_DEAD note we make here.  If
3228        we discard it in distribute_notes, we will decrement it again.  */
3229
3230     if (i3dest_killed)
3231       {
3232         if (REG_P (i3dest_killed))
3233           REG_N_DEATHS (REGNO (i3dest_killed))++;
3234
3235         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3236           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3237                                                NULL_RTX),
3238                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3239         else
3240           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3241                                                NULL_RTX),
3242                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3243                             elim_i2, elim_i1);
3244       }
3245
3246     if (i2dest_in_i2src)
3247       {
3248         if (REG_P (i2dest))
3249           REG_N_DEATHS (REGNO (i2dest))++;
3250
3251         if (newi2pat && reg_set_p (i2dest, newi2pat))
3252           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3253                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3254         else
3255           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3256                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3257                             NULL_RTX, NULL_RTX);
3258       }
3259
3260     if (i1dest_in_i1src)
3261       {
3262         if (REG_P (i1dest))
3263           REG_N_DEATHS (REGNO (i1dest))++;
3264
3265         if (newi2pat && reg_set_p (i1dest, newi2pat))
3266           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3267                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3268         else
3269           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3270                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3271                             NULL_RTX, NULL_RTX);
3272       }
3273
3274     distribute_links (i3links);
3275     distribute_links (i2links);
3276     distribute_links (i1links);
3277
3278     if (REG_P (i2dest))
3279       {
3280         rtx link;
3281         rtx i2_insn = 0, i2_val = 0, set;
3282
3283         /* The insn that used to set this register doesn't exist, and
3284            this life of the register may not exist either.  See if one of
3285            I3's links points to an insn that sets I2DEST.  If it does,
3286            that is now the last known value for I2DEST. If we don't update
3287            this and I2 set the register to a value that depended on its old
3288            contents, we will get confused.  If this insn is used, thing
3289            will be set correctly in combine_instructions.  */
3290
3291         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3292           if ((set = single_set (XEXP (link, 0))) != 0
3293               && rtx_equal_p (i2dest, SET_DEST (set)))
3294             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3295
3296         record_value_for_reg (i2dest, i2_insn, i2_val);
3297
3298         /* If the reg formerly set in I2 died only once and that was in I3,
3299            zero its use count so it won't make `reload' do any work.  */
3300         if (! added_sets_2
3301             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3302             && ! i2dest_in_i2src)
3303           {
3304             regno = REGNO (i2dest);
3305             REG_N_SETS (regno)--;
3306           }
3307       }
3308
3309     if (i1 && REG_P (i1dest))
3310       {
3311         rtx link;
3312         rtx i1_insn = 0, i1_val = 0, set;
3313
3314         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3315           if ((set = single_set (XEXP (link, 0))) != 0
3316               && rtx_equal_p (i1dest, SET_DEST (set)))
3317             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3318
3319         record_value_for_reg (i1dest, i1_insn, i1_val);
3320
3321         regno = REGNO (i1dest);
3322         if (! added_sets_1 && ! i1dest_in_i1src)
3323           REG_N_SETS (regno)--;
3324       }
3325
3326     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3327        been made to this insn.  The order of
3328        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3329        can affect nonzero_bits of newpat */
3330     if (newi2pat)
3331       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3332     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3333
3334     /* Set new_direct_jump_p if a new return or simple jump instruction
3335        has been created.
3336
3337        If I3 is now an unconditional jump, ensure that it has a
3338        BARRIER following it since it may have initially been a
3339        conditional jump.  It may also be the last nonnote insn.  */
3340
3341     if (returnjump_p (i3) || any_uncondjump_p (i3))
3342       {
3343         *new_direct_jump_p = 1;
3344         mark_jump_label (PATTERN (i3), i3, 0);
3345
3346         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3347             || !BARRIER_P (temp))
3348           emit_barrier_after (i3);
3349       }
3350
3351     if (undobuf.other_insn != NULL_RTX
3352         && (returnjump_p (undobuf.other_insn)
3353             || any_uncondjump_p (undobuf.other_insn)))
3354       {
3355         *new_direct_jump_p = 1;
3356
3357         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3358             || !BARRIER_P (temp))
3359           emit_barrier_after (undobuf.other_insn);
3360       }
3361
3362     /* An NOOP jump does not need barrier, but it does need cleaning up
3363        of CFG.  */
3364     if (GET_CODE (newpat) == SET
3365         && SET_SRC (newpat) == pc_rtx
3366         && SET_DEST (newpat) == pc_rtx)
3367       *new_direct_jump_p = 1;
3368   }
3369
3370   combine_successes++;
3371   undo_commit ();
3372
3373   if (added_links_insn
3374       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3375       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3376     return added_links_insn;
3377   else
3378     return newi2pat ? i2 : i3;
3379 }
3380 \f
3381 /* Undo all the modifications recorded in undobuf.  */
3382
3383 static void
3384 undo_all (void)
3385 {
3386   struct undo *undo, *next;
3387
3388   for (undo = undobuf.undos; undo; undo = next)
3389     {
3390       next = undo->next;
3391       switch (undo->kind)
3392         {
3393         case UNDO_RTX:
3394           *undo->where.r = undo->old_contents.r;
3395           break;
3396         case UNDO_INT:
3397           *undo->where.i = undo->old_contents.i;
3398           break;
3399         case UNDO_MODE:
3400           PUT_MODE (*undo->where.r, undo->old_contents.m);
3401           break;
3402         default:
3403           gcc_unreachable ();
3404         }
3405
3406       undo->next = undobuf.frees;
3407       undobuf.frees = undo;
3408     }
3409
3410   undobuf.undos = 0;
3411 }
3412
3413 /* We've committed to accepting the changes we made.  Move all
3414    of the undos to the free list.  */
3415
3416 static void
3417 undo_commit (void)
3418 {
3419   struct undo *undo, *next;
3420
3421   for (undo = undobuf.undos; undo; undo = next)
3422     {
3423       next = undo->next;
3424       undo->next = undobuf.frees;
3425       undobuf.frees = undo;
3426     }
3427   undobuf.undos = 0;
3428 }
3429
3430 \f
3431 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3432    where we have an arithmetic expression and return that point.  LOC will
3433    be inside INSN.
3434
3435    try_combine will call this function to see if an insn can be split into
3436    two insns.  */
3437
3438 static rtx *
3439 find_split_point (rtx *loc, rtx insn)
3440 {
3441   rtx x = *loc;
3442   enum rtx_code code = GET_CODE (x);
3443   rtx *split;
3444   unsigned HOST_WIDE_INT len = 0;
3445   HOST_WIDE_INT pos = 0;
3446   int unsignedp = 0;
3447   rtx inner = NULL_RTX;
3448
3449   /* First special-case some codes.  */
3450   switch (code)
3451     {
3452     case SUBREG:
3453 #ifdef INSN_SCHEDULING
3454       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3455          point.  */
3456       if (MEM_P (SUBREG_REG (x)))
3457         return loc;
3458 #endif
3459       return find_split_point (&SUBREG_REG (x), insn);
3460
3461     case MEM:
3462 #ifdef HAVE_lo_sum
3463       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3464          using LO_SUM and HIGH.  */
3465       if (GET_CODE (XEXP (x, 0)) == CONST
3466           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3467         {
3468           SUBST (XEXP (x, 0),
3469                  gen_rtx_LO_SUM (Pmode,
3470                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3471                                  XEXP (x, 0)));
3472           return &XEXP (XEXP (x, 0), 0);
3473         }
3474 #endif
3475
3476       /* If we have a PLUS whose second operand is a constant and the
3477          address is not valid, perhaps will can split it up using
3478          the machine-specific way to split large constants.  We use
3479          the first pseudo-reg (one of the virtual regs) as a placeholder;
3480          it will not remain in the result.  */
3481       if (GET_CODE (XEXP (x, 0)) == PLUS
3482           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3483           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3484         {
3485           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3486           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3487                                  subst_insn);
3488
3489           /* This should have produced two insns, each of which sets our
3490              placeholder.  If the source of the second is a valid address,
3491              we can make put both sources together and make a split point
3492              in the middle.  */
3493
3494           if (seq
3495               && NEXT_INSN (seq) != NULL_RTX
3496               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3497               && NONJUMP_INSN_P (seq)
3498               && GET_CODE (PATTERN (seq)) == SET
3499               && SET_DEST (PATTERN (seq)) == reg
3500               && ! reg_mentioned_p (reg,
3501                                     SET_SRC (PATTERN (seq)))
3502               && NONJUMP_INSN_P (NEXT_INSN (seq))
3503               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3504               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3505               && memory_address_p (GET_MODE (x),
3506                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3507             {
3508               rtx src1 = SET_SRC (PATTERN (seq));
3509               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3510
3511               /* Replace the placeholder in SRC2 with SRC1.  If we can
3512                  find where in SRC2 it was placed, that can become our
3513                  split point and we can replace this address with SRC2.
3514                  Just try two obvious places.  */
3515
3516               src2 = replace_rtx (src2, reg, src1);
3517               split = 0;
3518               if (XEXP (src2, 0) == src1)
3519                 split = &XEXP (src2, 0);
3520               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3521                        && XEXP (XEXP (src2, 0), 0) == src1)
3522                 split = &XEXP (XEXP (src2, 0), 0);
3523
3524               if (split)
3525                 {
3526                   SUBST (XEXP (x, 0), src2);
3527                   return split;
3528                 }
3529             }
3530
3531           /* If that didn't work, perhaps the first operand is complex and
3532              needs to be computed separately, so make a split point there.
3533              This will occur on machines that just support REG + CONST
3534              and have a constant moved through some previous computation.  */
3535
3536           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3537                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3538                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3539             return &XEXP (XEXP (x, 0), 0);
3540         }
3541       break;
3542
3543     case SET:
3544 #ifdef HAVE_cc0
3545       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3546          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3547          we need to put the operand into a register.  So split at that
3548          point.  */
3549
3550       if (SET_DEST (x) == cc0_rtx
3551           && GET_CODE (SET_SRC (x)) != COMPARE
3552           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3553           && !OBJECT_P (SET_SRC (x))
3554           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3555                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3556         return &SET_SRC (x);
3557 #endif
3558
3559       /* See if we can split SET_SRC as it stands.  */
3560       split = find_split_point (&SET_SRC (x), insn);
3561       if (split && split != &SET_SRC (x))
3562         return split;
3563
3564       /* See if we can split SET_DEST as it stands.  */
3565       split = find_split_point (&SET_DEST (x), insn);
3566       if (split && split != &SET_DEST (x))
3567         return split;
3568
3569       /* See if this is a bitfield assignment with everything constant.  If
3570          so, this is an IOR of an AND, so split it into that.  */
3571       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3572           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3573               <= HOST_BITS_PER_WIDE_INT)
3574           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3575           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3576           && GET_CODE (SET_SRC (x)) == CONST_INT
3577           && ((INTVAL (XEXP (SET_DEST (x), 1))
3578                + INTVAL (XEXP (SET_DEST (x), 2)))
3579               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3580           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3581         {
3582           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3583           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3584           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3585           rtx dest = XEXP (SET_DEST (x), 0);
3586           enum machine_mode mode = GET_MODE (dest);
3587           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3588           rtx or_mask;
3589
3590           if (BITS_BIG_ENDIAN)
3591             pos = GET_MODE_BITSIZE (mode) - len - pos;
3592
3593           or_mask = gen_int_mode (src << pos, mode);
3594           if (src == mask)
3595             SUBST (SET_SRC (x),
3596                    simplify_gen_binary (IOR, mode, dest, or_mask));
3597           else
3598             {
3599               rtx negmask = gen_int_mode (~(mask << pos), mode);
3600               SUBST (SET_SRC (x),
3601                      simplify_gen_binary (IOR, mode,
3602                                           simplify_gen_binary (AND, mode,
3603                                                                dest, negmask),
3604                                           or_mask));
3605             }
3606
3607           SUBST (SET_DEST (x), dest);
3608
3609           split = find_split_point (&SET_SRC (x), insn);
3610           if (split && split != &SET_SRC (x))
3611             return split;
3612         }
3613
3614       /* Otherwise, see if this is an operation that we can split into two.
3615          If so, try to split that.  */
3616       code = GET_CODE (SET_SRC (x));
3617
3618       switch (code)
3619         {
3620         case AND:
3621           /* If we are AND'ing with a large constant that is only a single
3622              bit and the result is only being used in a context where we
3623              need to know if it is zero or nonzero, replace it with a bit
3624              extraction.  This will avoid the large constant, which might
3625              have taken more than one insn to make.  If the constant were
3626              not a valid argument to the AND but took only one insn to make,
3627              this is no worse, but if it took more than one insn, it will
3628              be better.  */
3629
3630           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3631               && REG_P (XEXP (SET_SRC (x), 0))
3632               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3633               && REG_P (SET_DEST (x))
3634               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3635               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3636               && XEXP (*split, 0) == SET_DEST (x)
3637               && XEXP (*split, 1) == const0_rtx)
3638             {
3639               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3640                                                 XEXP (SET_SRC (x), 0),
3641                                                 pos, NULL_RTX, 1, 1, 0, 0);
3642               if (extraction != 0)
3643                 {
3644                   SUBST (SET_SRC (x), extraction);
3645                   return find_split_point (loc, insn);
3646                 }
3647             }
3648           break;
3649
3650         case NE:
3651           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3652              is known to be on, this can be converted into a NEG of a shift.  */
3653           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3654               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3655               && 1 <= (pos = exact_log2
3656                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3657                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3658             {
3659               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3660
3661               SUBST (SET_SRC (x),
3662                      gen_rtx_NEG (mode,
3663                                   gen_rtx_LSHIFTRT (mode,
3664                                                     XEXP (SET_SRC (x), 0),
3665                                                     GEN_INT (pos))));
3666
3667               split = find_split_point (&SET_SRC (x), insn);
3668               if (split && split != &SET_SRC (x))
3669                 return split;
3670             }
3671           break;
3672
3673         case SIGN_EXTEND:
3674           inner = XEXP (SET_SRC (x), 0);
3675
3676           /* We can't optimize if either mode is a partial integer
3677              mode as we don't know how many bits are significant
3678              in those modes.  */
3679           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3680               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3681             break;
3682
3683           pos = 0;
3684           len = GET_MODE_BITSIZE (GET_MODE (inner));
3685           unsignedp = 0;
3686           break;
3687
3688         case SIGN_EXTRACT:
3689         case ZERO_EXTRACT:
3690           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3691               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3692             {
3693               inner = XEXP (SET_SRC (x), 0);
3694               len = INTVAL (XEXP (SET_SRC (x), 1));
3695               pos = INTVAL (XEXP (SET_SRC (x), 2));
3696
3697               if (BITS_BIG_ENDIAN)
3698                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3699               unsignedp = (code == ZERO_EXTRACT);
3700             }
3701           break;
3702
3703         default:
3704           break;
3705         }
3706
3707       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3708         {
3709           enum machine_mode mode = GET_MODE (SET_SRC (x));
3710
3711           /* For unsigned, we have a choice of a shift followed by an
3712              AND or two shifts.  Use two shifts for field sizes where the
3713              constant might be too large.  We assume here that we can
3714              always at least get 8-bit constants in an AND insn, which is
3715              true for every current RISC.  */
3716
3717           if (unsignedp && len <= 8)
3718             {
3719               SUBST (SET_SRC (x),
3720                      gen_rtx_AND (mode,
3721                                   gen_rtx_LSHIFTRT
3722                                   (mode, gen_lowpart (mode, inner),
3723                                    GEN_INT (pos)),
3724                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3725
3726               split = find_split_point (&SET_SRC (x), insn);
3727               if (split && split != &SET_SRC (x))
3728                 return split;
3729             }
3730           else
3731             {
3732               SUBST (SET_SRC (x),
3733                      gen_rtx_fmt_ee
3734                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3735                       gen_rtx_ASHIFT (mode,
3736                                       gen_lowpart (mode, inner),
3737                                       GEN_INT (GET_MODE_BITSIZE (mode)
3738                                                - len - pos)),
3739                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3740
3741               split = find_split_point (&SET_SRC (x), insn);
3742               if (split && split != &SET_SRC (x))
3743                 return split;
3744             }
3745         }
3746
3747       /* See if this is a simple operation with a constant as the second
3748          operand.  It might be that this constant is out of range and hence
3749          could be used as a split point.  */
3750       if (BINARY_P (SET_SRC (x))
3751           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3752           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3753               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3754                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3755         return &XEXP (SET_SRC (x), 1);
3756
3757       /* Finally, see if this is a simple operation with its first operand
3758          not in a register.  The operation might require this operand in a
3759          register, so return it as a split point.  We can always do this
3760          because if the first operand were another operation, we would have
3761          already found it as a split point.  */
3762       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3763           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3764         return &XEXP (SET_SRC (x), 0);
3765
3766       return 0;
3767
3768     case AND:
3769     case IOR:
3770       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3771          it is better to write this as (not (ior A B)) so we can split it.
3772          Similarly for IOR.  */
3773       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3774         {
3775           SUBST (*loc,
3776                  gen_rtx_NOT (GET_MODE (x),
3777                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3778                                               GET_MODE (x),
3779                                               XEXP (XEXP (x, 0), 0),
3780                                               XEXP (XEXP (x, 1), 0))));
3781           return find_split_point (loc, insn);
3782         }
3783
3784       /* Many RISC machines have a large set of logical insns.  If the
3785          second operand is a NOT, put it first so we will try to split the
3786          other operand first.  */
3787       if (GET_CODE (XEXP (x, 1)) == NOT)
3788         {
3789           rtx tem = XEXP (x, 0);
3790           SUBST (XEXP (x, 0), XEXP (x, 1));
3791           SUBST (XEXP (x, 1), tem);
3792         }
3793       break;
3794
3795     default:
3796       break;
3797     }
3798
3799   /* Otherwise, select our actions depending on our rtx class.  */
3800   switch (GET_RTX_CLASS (code))
3801     {
3802     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3803     case RTX_TERNARY:
3804       split = find_split_point (&XEXP (x, 2), insn);
3805       if (split)
3806         return split;
3807       /* ... fall through ...  */
3808     case RTX_BIN_ARITH:
3809     case RTX_COMM_ARITH:
3810     case RTX_COMPARE:
3811     case RTX_COMM_COMPARE:
3812       split = find_split_point (&XEXP (x, 1), insn);
3813       if (split)
3814         return split;
3815       /* ... fall through ...  */
3816     case RTX_UNARY:
3817       /* Some machines have (and (shift ...) ...) insns.  If X is not
3818          an AND, but XEXP (X, 0) is, use it as our split point.  */
3819       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3820         return &XEXP (x, 0);
3821
3822       split = find_split_point (&XEXP (x, 0), insn);
3823       if (split)
3824         return split;
3825       return loc;
3826
3827     default:
3828       /* Otherwise, we don't have a split point.  */
3829       return 0;
3830     }
3831 }
3832 \f
3833 /* Throughout X, replace FROM with TO, and return the result.
3834    The result is TO if X is FROM;
3835    otherwise the result is X, but its contents may have been modified.
3836    If they were modified, a record was made in undobuf so that
3837    undo_all will (among other things) return X to its original state.
3838
3839    If the number of changes necessary is too much to record to undo,
3840    the excess changes are not made, so the result is invalid.
3841    The changes already made can still be undone.
3842    undobuf.num_undo is incremented for such changes, so by testing that
3843    the caller can tell whether the result is valid.
3844
3845    `n_occurrences' is incremented each time FROM is replaced.
3846
3847    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3848
3849    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3850    by copying if `n_occurrences' is nonzero.  */
3851
3852 static rtx
3853 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3854 {
3855   enum rtx_code code = GET_CODE (x);
3856   enum machine_mode op0_mode = VOIDmode;
3857   const char *fmt;
3858   int len, i;
3859   rtx new;
3860
3861 /* Two expressions are equal if they are identical copies of a shared
3862    RTX or if they are both registers with the same register number
3863    and mode.  */
3864
3865 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3866   ((X) == (Y)                                           \
3867    || (REG_P (X) && REG_P (Y)   \
3868        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3869
3870   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3871     {
3872       n_occurrences++;
3873       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3874     }
3875
3876   /* If X and FROM are the same register but different modes, they will
3877      not have been seen as equal above.  However, flow.c will make a
3878      LOG_LINKS entry for that case.  If we do nothing, we will try to
3879      rerecognize our original insn and, when it succeeds, we will
3880      delete the feeding insn, which is incorrect.
3881
3882      So force this insn not to match in this (rare) case.  */
3883   if (! in_dest && code == REG && REG_P (from)
3884       && REGNO (x) == REGNO (from))
3885     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3886
3887   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3888      of which may contain things that can be combined.  */
3889   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3890     return x;
3891
3892   /* It is possible to have a subexpression appear twice in the insn.
3893      Suppose that FROM is a register that appears within TO.
3894      Then, after that subexpression has been scanned once by `subst',
3895      the second time it is scanned, TO may be found.  If we were
3896      to scan TO here, we would find FROM within it and create a
3897      self-referent rtl structure which is completely wrong.  */
3898   if (COMBINE_RTX_EQUAL_P (x, to))
3899     return to;
3900
3901   /* Parallel asm_operands need special attention because all of the
3902      inputs are shared across the arms.  Furthermore, unsharing the
3903      rtl results in recognition failures.  Failure to handle this case
3904      specially can result in circular rtl.
3905
3906      Solve this by doing a normal pass across the first entry of the
3907      parallel, and only processing the SET_DESTs of the subsequent
3908      entries.  Ug.  */
3909
3910   if (code == PARALLEL
3911       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3912       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3913     {
3914       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3915
3916       /* If this substitution failed, this whole thing fails.  */
3917       if (GET_CODE (new) == CLOBBER
3918           && XEXP (new, 0) == const0_rtx)
3919         return new;
3920
3921       SUBST (XVECEXP (x, 0, 0), new);
3922
3923       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3924         {
3925           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3926
3927           if (!REG_P (dest)
3928               && GET_CODE (dest) != CC0
3929               && GET_CODE (dest) != PC)
3930             {
3931               new = subst (dest, from, to, 0, unique_copy);
3932
3933               /* If this substitution failed, this whole thing fails.  */
3934               if (GET_CODE (new) == CLOBBER
3935                   && XEXP (new, 0) == const0_rtx)
3936                 return new;
3937
3938               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3939             }
3940         }
3941     }
3942   else
3943     {
3944       len = GET_RTX_LENGTH (code);
3945       fmt = GET_RTX_FORMAT (code);
3946
3947       /* We don't need to process a SET_DEST that is a register, CC0,
3948          or PC, so set up to skip this common case.  All other cases
3949          where we want to suppress replacing something inside a
3950          SET_SRC are handled via the IN_DEST operand.  */
3951       if (code == SET
3952           && (REG_P (SET_DEST (x))
3953               || GET_CODE (SET_DEST (x)) == CC0
3954               || GET_CODE (SET_DEST (x)) == PC))
3955         fmt = "ie";
3956
3957       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3958          constant.  */
3959       if (fmt[0] == 'e')
3960         op0_mode = GET_MODE (XEXP (x, 0));
3961
3962       for (i = 0; i < len; i++)
3963         {
3964           if (fmt[i] == 'E')
3965             {
3966               int j;
3967               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3968                 {
3969                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3970                     {
3971                       new = (unique_copy && n_occurrences
3972                              ? copy_rtx (to) : to);
3973                       n_occurrences++;
3974                     }
3975                   else
3976                     {
3977                       new = subst (XVECEXP (x, i, j), from, to, 0,
3978                                    unique_copy);
3979
3980                       /* If this substitution failed, this whole thing
3981                          fails.  */
3982                       if (GET_CODE (new) == CLOBBER
3983                           && XEXP (new, 0) == const0_rtx)
3984                         return new;
3985                     }
3986
3987                   SUBST (XVECEXP (x, i, j), new);
3988                 }
3989             }
3990           else if (fmt[i] == 'e')
3991             {
3992               /* If this is a register being set, ignore it.  */
3993               new = XEXP (x, i);
3994               if (in_dest
3995                   && i == 0
3996                   && (((code == SUBREG || code == ZERO_EXTRACT)
3997                        && REG_P (new))
3998                       || code == STRICT_LOW_PART))
3999                 ;
4000
4001               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4002                 {
4003                   /* In general, don't install a subreg involving two
4004                      modes not tieable.  It can worsen register
4005                      allocation, and can even make invalid reload
4006                      insns, since the reg inside may need to be copied
4007                      from in the outside mode, and that may be invalid
4008                      if it is an fp reg copied in integer mode.
4009
4010                      We allow two exceptions to this: It is valid if
4011                      it is inside another SUBREG and the mode of that
4012                      SUBREG and the mode of the inside of TO is
4013                      tieable and it is valid if X is a SET that copies
4014                      FROM to CC0.  */
4015
4016                   if (GET_CODE (to) == SUBREG
4017                       && ! MODES_TIEABLE_P (GET_MODE (to),
4018                                             GET_MODE (SUBREG_REG (to)))
4019                       && ! (code == SUBREG
4020                             && MODES_TIEABLE_P (GET_MODE (x),
4021                                                 GET_MODE (SUBREG_REG (to))))
4022 #ifdef HAVE_cc0
4023                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4024 #endif
4025                       )
4026                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4027
4028 #ifdef CANNOT_CHANGE_MODE_CLASS
4029                   if (code == SUBREG
4030                       && REG_P (to)
4031                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4032                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4033                                                    GET_MODE (to),
4034                                                    GET_MODE (x)))
4035                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4036 #endif
4037
4038                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4039                   n_occurrences++;
4040                 }
4041               else
4042                 /* If we are in a SET_DEST, suppress most cases unless we
4043                    have gone inside a MEM, in which case we want to
4044                    simplify the address.  We assume here that things that
4045                    are actually part of the destination have their inner
4046                    parts in the first expression.  This is true for SUBREG,
4047                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4048                    things aside from REG and MEM that should appear in a
4049                    SET_DEST.  */
4050                 new = subst (XEXP (x, i), from, to,
4051                              (((in_dest
4052                                 && (code == SUBREG || code == STRICT_LOW_PART
4053                                     || code == ZERO_EXTRACT))
4054                                || code == SET)
4055                               && i == 0), unique_copy);
4056
4057               /* If we found that we will have to reject this combination,
4058                  indicate that by returning the CLOBBER ourselves, rather than
4059                  an expression containing it.  This will speed things up as
4060                  well as prevent accidents where two CLOBBERs are considered
4061                  to be equal, thus producing an incorrect simplification.  */
4062
4063               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4064                 return new;
4065
4066               if (GET_CODE (x) == SUBREG
4067                   && (GET_CODE (new) == CONST_INT
4068                       || GET_CODE (new) == CONST_DOUBLE))
4069                 {
4070                   enum machine_mode mode = GET_MODE (x);
4071
4072                   x = simplify_subreg (GET_MODE (x), new,
4073                                        GET_MODE (SUBREG_REG (x)),
4074                                        SUBREG_BYTE (x));
4075                   if (! x)
4076                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4077                 }
4078               else if (GET_CODE (new) == CONST_INT
4079                        && GET_CODE (x) == ZERO_EXTEND)
4080                 {
4081                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4082                                                 new, GET_MODE (XEXP (x, 0)));
4083                   gcc_assert (x);
4084                 }
4085               else
4086                 SUBST (XEXP (x, i), new);
4087             }
4088         }
4089     }
4090
4091   /* Try to simplify X.  If the simplification changed the code, it is likely
4092      that further simplification will help, so loop, but limit the number
4093      of repetitions that will be performed.  */
4094
4095   for (i = 0; i < 4; i++)
4096     {
4097       /* If X is sufficiently simple, don't bother trying to do anything
4098          with it.  */
4099       if (code != CONST_INT && code != REG && code != CLOBBER)
4100         x = combine_simplify_rtx (x, op0_mode, in_dest);
4101
4102       if (GET_CODE (x) == code)
4103         break;
4104
4105       code = GET_CODE (x);
4106
4107       /* We no longer know the original mode of operand 0 since we
4108          have changed the form of X)  */
4109       op0_mode = VOIDmode;
4110     }
4111
4112   return x;
4113 }
4114 \f
4115 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4116    outer level; call `subst' to simplify recursively.  Return the new
4117    expression.
4118
4119    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4120    if we are inside a SET_DEST.  */
4121
4122 static rtx
4123 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4124 {
4125   enum rtx_code code = GET_CODE (x);
4126   enum machine_mode mode = GET_MODE (x);
4127   rtx temp;
4128   int i;
4129
4130   /* If this is a commutative operation, put a constant last and a complex
4131      expression first.  We don't need to do this for comparisons here.  */
4132   if (COMMUTATIVE_ARITH_P (x)
4133       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4134     {
4135       temp = XEXP (x, 0);
4136       SUBST (XEXP (x, 0), XEXP (x, 1));
4137       SUBST (XEXP (x, 1), temp);
4138     }
4139
4140   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4141      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4142      things.  Check for cases where both arms are testing the same
4143      condition.
4144
4145      Don't do anything if all operands are very simple.  */
4146
4147   if ((BINARY_P (x)
4148        && ((!OBJECT_P (XEXP (x, 0))
4149             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4150                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4151            || (!OBJECT_P (XEXP (x, 1))
4152                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4153                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4154       || (UNARY_P (x)
4155           && (!OBJECT_P (XEXP (x, 0))
4156                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4157                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4158     {
4159       rtx cond, true_rtx, false_rtx;
4160
4161       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4162       if (cond != 0
4163           /* If everything is a comparison, what we have is highly unlikely
4164              to be simpler, so don't use it.  */
4165           && ! (COMPARISON_P (x)
4166                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4167         {
4168           rtx cop1 = const0_rtx;
4169           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4170
4171           if (cond_code == NE && COMPARISON_P (cond))
4172             return x;
4173
4174           /* Simplify the alternative arms; this may collapse the true and
4175              false arms to store-flag values.  Be careful to use copy_rtx
4176              here since true_rtx or false_rtx might share RTL with x as a
4177              result of the if_then_else_cond call above.  */
4178           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4179           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4180
4181           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4182              is unlikely to be simpler.  */
4183           if (general_operand (true_rtx, VOIDmode)
4184               && general_operand (false_rtx, VOIDmode))
4185             {
4186               enum rtx_code reversed;
4187
4188               /* Restarting if we generate a store-flag expression will cause
4189                  us to loop.  Just drop through in this case.  */
4190
4191               /* If the result values are STORE_FLAG_VALUE and zero, we can
4192                  just make the comparison operation.  */
4193               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4194                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4195                                              cond, cop1);
4196               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4197                        && ((reversed = reversed_comparison_code_parts
4198                                         (cond_code, cond, cop1, NULL))
4199                            != UNKNOWN))
4200                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4201                                              cond, cop1);
4202
4203               /* Likewise, we can make the negate of a comparison operation
4204                  if the result values are - STORE_FLAG_VALUE and zero.  */
4205               else if (GET_CODE (true_rtx) == CONST_INT
4206                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4207                        && false_rtx == const0_rtx)
4208                 x = simplify_gen_unary (NEG, mode,
4209                                         simplify_gen_relational (cond_code,
4210                                                                  mode, VOIDmode,
4211                                                                  cond, cop1),
4212                                         mode);
4213               else if (GET_CODE (false_rtx) == CONST_INT
4214                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4215                        && true_rtx == const0_rtx
4216                        && ((reversed = reversed_comparison_code_parts
4217                                         (cond_code, cond, cop1, NULL))
4218                            != UNKNOWN))
4219                 x = simplify_gen_unary (NEG, mode,
4220                                         simplify_gen_relational (reversed,
4221                                                                  mode, VOIDmode,
4222                                                                  cond, cop1),
4223                                         mode);
4224               else
4225                 return gen_rtx_IF_THEN_ELSE (mode,
4226                                              simplify_gen_relational (cond_code,
4227                                                                       mode,
4228                                                                       VOIDmode,
4229                                                                       cond,
4230                                                                       cop1),
4231                                              true_rtx, false_rtx);
4232
4233               code = GET_CODE (x);
4234               op0_mode = VOIDmode;
4235             }
4236         }
4237     }
4238
4239   /* Try to fold this expression in case we have constants that weren't
4240      present before.  */
4241   temp = 0;
4242   switch (GET_RTX_CLASS (code))
4243     {
4244     case RTX_UNARY:
4245       if (op0_mode == VOIDmode)
4246         op0_mode = GET_MODE (XEXP (x, 0));
4247       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4248       break;
4249     case RTX_COMPARE:
4250     case RTX_COMM_COMPARE:
4251       {
4252         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4253         if (cmp_mode == VOIDmode)
4254           {
4255             cmp_mode = GET_MODE (XEXP (x, 1));
4256             if (cmp_mode == VOIDmode)
4257               cmp_mode = op0_mode;
4258           }
4259         temp = simplify_relational_operation (code, mode, cmp_mode,
4260                                               XEXP (x, 0), XEXP (x, 1));
4261       }
4262       break;
4263     case RTX_COMM_ARITH:
4264     case RTX_BIN_ARITH:
4265       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4266       break;
4267     case RTX_BITFIELD_OPS:
4268     case RTX_TERNARY:
4269       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4270                                          XEXP (x, 1), XEXP (x, 2));
4271       break;
4272     default:
4273       break;
4274     }
4275
4276   if (temp)
4277     {
4278       x = temp;
4279       code = GET_CODE (temp);
4280       op0_mode = VOIDmode;
4281       mode = GET_MODE (temp);
4282     }
4283
4284   /* First see if we can apply the inverse distributive law.  */
4285   if (code == PLUS || code == MINUS
4286       || code == AND || code == IOR || code == XOR)
4287     {
4288       x = apply_distributive_law (x);
4289       code = GET_CODE (x);
4290       op0_mode = VOIDmode;
4291     }
4292
4293   /* If CODE is an associative operation not otherwise handled, see if we
4294      can associate some operands.  This can win if they are constants or
4295      if they are logically related (i.e. (a & b) & a).  */
4296   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4297        || code == AND || code == IOR || code == XOR
4298        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4299       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4300           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4301     {
4302       if (GET_CODE (XEXP (x, 0)) == code)
4303         {
4304           rtx other = XEXP (XEXP (x, 0), 0);
4305           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4306           rtx inner_op1 = XEXP (x, 1);
4307           rtx inner;
4308
4309           /* Make sure we pass the constant operand if any as the second
4310              one if this is a commutative operation.  */
4311           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4312             {
4313               rtx tem = inner_op0;
4314               inner_op0 = inner_op1;
4315               inner_op1 = tem;
4316             }
4317           inner = simplify_binary_operation (code == MINUS ? PLUS
4318                                              : code == DIV ? MULT
4319                                              : code,
4320                                              mode, inner_op0, inner_op1);
4321
4322           /* For commutative operations, try the other pair if that one
4323              didn't simplify.  */
4324           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4325             {
4326               other = XEXP (XEXP (x, 0), 1);
4327               inner = simplify_binary_operation (code, mode,
4328                                                  XEXP (XEXP (x, 0), 0),
4329                                                  XEXP (x, 1));
4330             }
4331
4332           if (inner)
4333             return simplify_gen_binary (code, mode, other, inner);
4334         }
4335     }
4336
4337   /* A little bit of algebraic simplification here.  */
4338   switch (code)
4339     {
4340     case MEM:
4341       /* Ensure that our address has any ASHIFTs converted to MULT in case
4342          address-recognizing predicates are called later.  */
4343       temp = make_compound_operation (XEXP (x, 0), MEM);
4344       SUBST (XEXP (x, 0), temp);
4345       break;
4346
4347     case SUBREG:
4348       if (op0_mode == VOIDmode)
4349         op0_mode = GET_MODE (SUBREG_REG (x));
4350
4351       /* See if this can be moved to simplify_subreg.  */
4352       if (CONSTANT_P (SUBREG_REG (x))
4353           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4354              /* Don't call gen_lowpart if the inner mode
4355                 is VOIDmode and we cannot simplify it, as SUBREG without
4356                 inner mode is invalid.  */
4357           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4358               || gen_lowpart_common (mode, SUBREG_REG (x))))
4359         return gen_lowpart (mode, SUBREG_REG (x));
4360
4361       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4362         break;
4363       {
4364         rtx temp;
4365         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4366                                 SUBREG_BYTE (x));
4367         if (temp)
4368           return temp;
4369       }
4370
4371       /* Don't change the mode of the MEM if that would change the meaning
4372          of the address.  */
4373       if (MEM_P (SUBREG_REG (x))
4374           && (MEM_VOLATILE_P (SUBREG_REG (x))
4375               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4376         return gen_rtx_CLOBBER (mode, const0_rtx);
4377
4378       /* Note that we cannot do any narrowing for non-constants since
4379          we might have been counting on using the fact that some bits were
4380          zero.  We now do this in the SET.  */
4381
4382       break;
4383
4384     case NEG:
4385       temp = expand_compound_operation (XEXP (x, 0));
4386
4387       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4388          replaced by (lshiftrt X C).  This will convert
4389          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4390
4391       if (GET_CODE (temp) == ASHIFTRT
4392           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4393           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4394         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4395                                      INTVAL (XEXP (temp, 1)));
4396
4397       /* If X has only a single bit that might be nonzero, say, bit I, convert
4398          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4399          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4400          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4401          or a SUBREG of one since we'd be making the expression more
4402          complex if it was just a register.  */
4403
4404       if (!REG_P (temp)
4405           && ! (GET_CODE (temp) == SUBREG
4406                 && REG_P (SUBREG_REG (temp)))
4407           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4408         {
4409           rtx temp1 = simplify_shift_const
4410             (NULL_RTX, ASHIFTRT, mode,
4411              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4412                                    GET_MODE_BITSIZE (mode) - 1 - i),
4413              GET_MODE_BITSIZE (mode) - 1 - i);
4414
4415           /* If all we did was surround TEMP with the two shifts, we
4416              haven't improved anything, so don't use it.  Otherwise,
4417              we are better off with TEMP1.  */
4418           if (GET_CODE (temp1) != ASHIFTRT
4419               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4420               || XEXP (XEXP (temp1, 0), 0) != temp)
4421             return temp1;
4422         }
4423       break;
4424
4425     case TRUNCATE:
4426       /* We can't handle truncation to a partial integer mode here
4427          because we don't know the real bitsize of the partial
4428          integer mode.  */
4429       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4430         break;
4431
4432       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4433           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4434                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4435         SUBST (XEXP (x, 0),
4436                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4437                               GET_MODE_MASK (mode), 0));
4438
4439       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4440          whose value is a comparison can be replaced with a subreg if
4441          STORE_FLAG_VALUE permits.  */
4442       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4443           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4444           && (temp = get_last_value (XEXP (x, 0)))
4445           && COMPARISON_P (temp))
4446         return gen_lowpart (mode, XEXP (x, 0));
4447       break;
4448
4449 #ifdef HAVE_cc0
4450     case COMPARE:
4451       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4452          using cc0, in which case we want to leave it as a COMPARE
4453          so we can distinguish it from a register-register-copy.  */
4454       if (XEXP (x, 1) == const0_rtx)
4455         return XEXP (x, 0);
4456
4457       /* x - 0 is the same as x unless x's mode has signed zeros and
4458          allows rounding towards -infinity.  Under those conditions,
4459          0 - 0 is -0.  */
4460       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4461             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4462           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4463         return XEXP (x, 0);
4464       break;
4465 #endif
4466
4467     case CONST:
4468       /* (const (const X)) can become (const X).  Do it this way rather than
4469          returning the inner CONST since CONST can be shared with a
4470          REG_EQUAL note.  */
4471       if (GET_CODE (XEXP (x, 0)) == CONST)
4472         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4473       break;
4474
4475 #ifdef HAVE_lo_sum
4476     case LO_SUM:
4477       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4478          can add in an offset.  find_split_point will split this address up
4479          again if it doesn't match.  */
4480       if (GET_CODE (XEXP (x, 0)) == HIGH
4481           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4482         return XEXP (x, 1);
4483       break;
4484 #endif
4485
4486     case PLUS:
4487       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4488          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4489          bit-field and can be replaced by either a sign_extend or a
4490          sign_extract.  The `and' may be a zero_extend and the two
4491          <c>, -<c> constants may be reversed.  */
4492       if (GET_CODE (XEXP (x, 0)) == XOR
4493           && GET_CODE (XEXP (x, 1)) == CONST_INT
4494           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4495           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4496           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4497               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4498           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4499           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4500                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4501                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4502                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4503               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4504                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4505                       == (unsigned int) i + 1))))
4506         return simplify_shift_const
4507           (NULL_RTX, ASHIFTRT, mode,
4508            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4509                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4510                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4511            GET_MODE_BITSIZE (mode) - (i + 1));
4512
4513       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4514          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4515          the bitsize of the mode - 1.  This allows simplification of
4516          "a = (b & 8) == 0;"  */
4517       if (XEXP (x, 1) == constm1_rtx
4518           && !REG_P (XEXP (x, 0))
4519           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4520                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4521           && nonzero_bits (XEXP (x, 0), mode) == 1)
4522         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4523            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4524                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4525                                  GET_MODE_BITSIZE (mode) - 1),
4526            GET_MODE_BITSIZE (mode) - 1);
4527
4528       /* If we are adding two things that have no bits in common, convert
4529          the addition into an IOR.  This will often be further simplified,
4530          for example in cases like ((a & 1) + (a & 2)), which can
4531          become a & 3.  */
4532
4533       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4534           && (nonzero_bits (XEXP (x, 0), mode)
4535               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4536         {
4537           /* Try to simplify the expression further.  */
4538           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4539           temp = combine_simplify_rtx (tor, mode, in_dest);
4540
4541           /* If we could, great.  If not, do not go ahead with the IOR
4542              replacement, since PLUS appears in many special purpose
4543              address arithmetic instructions.  */
4544           if (GET_CODE (temp) != CLOBBER && temp != tor)
4545             return temp;
4546         }
4547       break;
4548
4549     case MINUS:
4550       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4551          (and <foo> (const_int pow2-1))  */
4552       if (GET_CODE (XEXP (x, 1)) == AND
4553           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4554           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4555           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4556         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4557                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4558       break;
4559
4560     case MULT:
4561       /* If we have (mult (plus A B) C), apply the distributive law and then
4562          the inverse distributive law to see if things simplify.  This
4563          occurs mostly in addresses, often when unrolling loops.  */
4564
4565       if (GET_CODE (XEXP (x, 0)) == PLUS)
4566         {
4567           rtx result = distribute_and_simplify_rtx (x, 0);
4568           if (result)
4569             return result;
4570         }
4571
4572       /* Try simplify a*(b/c) as (a*b)/c.  */
4573       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4574           && GET_CODE (XEXP (x, 0)) == DIV)
4575         {
4576           rtx tem = simplify_binary_operation (MULT, mode,
4577                                                XEXP (XEXP (x, 0), 0),
4578                                                XEXP (x, 1));
4579           if (tem)
4580             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4581         }
4582       break;
4583
4584     case UDIV:
4585       /* If this is a divide by a power of two, treat it as a shift if
4586          its first operand is a shift.  */
4587       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4588           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4589           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4590               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4591               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4592               || GET_CODE (XEXP (x, 0)) == ROTATE
4593               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4594         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4595       break;
4596
4597     case EQ:  case NE:
4598     case GT:  case GTU:  case GE:  case GEU:
4599     case LT:  case LTU:  case LE:  case LEU:
4600     case UNEQ:  case LTGT:
4601     case UNGT:  case UNGE:
4602     case UNLT:  case UNLE:
4603     case UNORDERED: case ORDERED:
4604       /* If the first operand is a condition code, we can't do anything
4605          with it.  */
4606       if (GET_CODE (XEXP (x, 0)) == COMPARE
4607           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4608               && ! CC0_P (XEXP (x, 0))))
4609         {
4610           rtx op0 = XEXP (x, 0);
4611           rtx op1 = XEXP (x, 1);
4612           enum rtx_code new_code;
4613
4614           if (GET_CODE (op0) == COMPARE)
4615             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4616
4617           /* Simplify our comparison, if possible.  */
4618           new_code = simplify_comparison (code, &op0, &op1);
4619
4620           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4621              if only the low-order bit is possibly nonzero in X (such as when
4622              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4623              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4624              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4625              (plus X 1).
4626
4627              Remove any ZERO_EXTRACT we made when thinking this was a
4628              comparison.  It may now be simpler to use, e.g., an AND.  If a
4629              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4630              the call to make_compound_operation in the SET case.  */
4631
4632           if (STORE_FLAG_VALUE == 1
4633               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4634               && op1 == const0_rtx
4635               && mode == GET_MODE (op0)
4636               && nonzero_bits (op0, mode) == 1)
4637             return gen_lowpart (mode,
4638                                 expand_compound_operation (op0));
4639
4640           else if (STORE_FLAG_VALUE == 1
4641                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4642                    && op1 == const0_rtx
4643                    && mode == GET_MODE (op0)
4644                    && (num_sign_bit_copies (op0, mode)
4645                        == GET_MODE_BITSIZE (mode)))
4646             {
4647               op0 = expand_compound_operation (op0);
4648               return simplify_gen_unary (NEG, mode,
4649                                          gen_lowpart (mode, op0),
4650                                          mode);
4651             }
4652
4653           else if (STORE_FLAG_VALUE == 1
4654                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4655                    && op1 == const0_rtx
4656                    && mode == GET_MODE (op0)
4657                    && nonzero_bits (op0, mode) == 1)
4658             {
4659               op0 = expand_compound_operation (op0);
4660               return simplify_gen_binary (XOR, mode,
4661                                           gen_lowpart (mode, op0),
4662                                           const1_rtx);
4663             }
4664
4665           else if (STORE_FLAG_VALUE == 1
4666                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4667                    && op1 == const0_rtx
4668                    && mode == GET_MODE (op0)
4669                    && (num_sign_bit_copies (op0, mode)
4670                        == GET_MODE_BITSIZE (mode)))
4671             {
4672               op0 = expand_compound_operation (op0);
4673               return plus_constant (gen_lowpart (mode, op0), 1);
4674             }
4675
4676           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4677              those above.  */
4678           if (STORE_FLAG_VALUE == -1
4679               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4680               && op1 == const0_rtx
4681               && (num_sign_bit_copies (op0, mode)
4682                   == GET_MODE_BITSIZE (mode)))
4683             return gen_lowpart (mode,
4684                                 expand_compound_operation (op0));
4685
4686           else if (STORE_FLAG_VALUE == -1
4687                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4688                    && op1 == const0_rtx
4689                    && mode == GET_MODE (op0)
4690                    && nonzero_bits (op0, mode) == 1)
4691             {
4692               op0 = expand_compound_operation (op0);
4693               return simplify_gen_unary (NEG, mode,
4694                                          gen_lowpart (mode, op0),
4695                                          mode);
4696             }
4697
4698           else if (STORE_FLAG_VALUE == -1
4699                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4700                    && op1 == const0_rtx
4701                    && mode == GET_MODE (op0)
4702                    && (num_sign_bit_copies (op0, mode)
4703                        == GET_MODE_BITSIZE (mode)))
4704             {
4705               op0 = expand_compound_operation (op0);
4706               return simplify_gen_unary (NOT, mode,
4707                                          gen_lowpart (mode, op0),
4708                                          mode);
4709             }
4710
4711           /* If X is 0/1, (eq X 0) is X-1.  */
4712           else if (STORE_FLAG_VALUE == -1
4713                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4714                    && op1 == const0_rtx
4715                    && mode == GET_MODE (op0)
4716                    && nonzero_bits (op0, mode) == 1)
4717             {
4718               op0 = expand_compound_operation (op0);
4719               return plus_constant (gen_lowpart (mode, op0), -1);
4720             }
4721
4722           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4723              one bit that might be nonzero, we can convert (ne x 0) to
4724              (ashift x c) where C puts the bit in the sign bit.  Remove any
4725              AND with STORE_FLAG_VALUE when we are done, since we are only
4726              going to test the sign bit.  */
4727           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4728               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4729               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4730                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4731               && op1 == const0_rtx
4732               && mode == GET_MODE (op0)
4733               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4734             {
4735               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4736                                         expand_compound_operation (op0),
4737                                         GET_MODE_BITSIZE (mode) - 1 - i);
4738               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4739                 return XEXP (x, 0);
4740               else
4741                 return x;
4742             }
4743
4744           /* If the code changed, return a whole new comparison.  */
4745           if (new_code != code)
4746             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4747
4748           /* Otherwise, keep this operation, but maybe change its operands.
4749              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4750           SUBST (XEXP (x, 0), op0);
4751           SUBST (XEXP (x, 1), op1);
4752         }
4753       break;
4754
4755     case IF_THEN_ELSE:
4756       return simplify_if_then_else (x);
4757
4758     case ZERO_EXTRACT:
4759     case SIGN_EXTRACT:
4760     case ZERO_EXTEND:
4761     case SIGN_EXTEND:
4762       /* If we are processing SET_DEST, we are done.  */
4763       if (in_dest)
4764         return x;
4765
4766       return expand_compound_operation (x);
4767
4768     case SET:
4769       return simplify_set (x);
4770
4771     case AND:
4772     case IOR:
4773       return simplify_logical (x);
4774
4775     case ASHIFT:
4776     case LSHIFTRT:
4777     case ASHIFTRT:
4778     case ROTATE:
4779     case ROTATERT:
4780       /* If this is a shift by a constant amount, simplify it.  */
4781       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4782         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4783                                      INTVAL (XEXP (x, 1)));
4784
4785       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4786         SUBST (XEXP (x, 1),
4787                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4788                               ((HOST_WIDE_INT) 1
4789                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4790                               - 1,
4791                               0));
4792       break;
4793
4794     default:
4795       break;
4796     }
4797
4798   return x;
4799 }
4800 \f
4801 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4802
4803 static rtx
4804 simplify_if_then_else (rtx x)
4805 {
4806   enum machine_mode mode = GET_MODE (x);
4807   rtx cond = XEXP (x, 0);
4808   rtx true_rtx = XEXP (x, 1);
4809   rtx false_rtx = XEXP (x, 2);
4810   enum rtx_code true_code = GET_CODE (cond);
4811   int comparison_p = COMPARISON_P (cond);
4812   rtx temp;
4813   int i;
4814   enum rtx_code false_code;
4815   rtx reversed;
4816
4817   /* Simplify storing of the truth value.  */
4818   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4819     return simplify_gen_relational (true_code, mode, VOIDmode,
4820                                     XEXP (cond, 0), XEXP (cond, 1));
4821
4822   /* Also when the truth value has to be reversed.  */
4823   if (comparison_p
4824       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4825       && (reversed = reversed_comparison (cond, mode)))
4826     return reversed;
4827
4828   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4829      in it is being compared against certain values.  Get the true and false
4830      comparisons and see if that says anything about the value of each arm.  */
4831
4832   if (comparison_p
4833       && ((false_code = reversed_comparison_code (cond, NULL))
4834           != UNKNOWN)
4835       && REG_P (XEXP (cond, 0)))
4836     {
4837       HOST_WIDE_INT nzb;
4838       rtx from = XEXP (cond, 0);
4839       rtx true_val = XEXP (cond, 1);
4840       rtx false_val = true_val;
4841       int swapped = 0;
4842
4843       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4844
4845       if (false_code == EQ)
4846         {
4847           swapped = 1, true_code = EQ, false_code = NE;
4848           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4849         }
4850
4851       /* If we are comparing against zero and the expression being tested has
4852          only a single bit that might be nonzero, that is its value when it is
4853          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4854
4855       if (true_code == EQ && true_val == const0_rtx
4856           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4857         false_code = EQ, false_val = GEN_INT (nzb);
4858       else if (true_code == EQ && true_val == const0_rtx
4859                && (num_sign_bit_copies (from, GET_MODE (from))
4860                    == GET_MODE_BITSIZE (GET_MODE (from))))
4861         false_code = EQ, false_val = constm1_rtx;
4862
4863       /* Now simplify an arm if we know the value of the register in the
4864          branch and it is used in the arm.  Be careful due to the potential
4865          of locally-shared RTL.  */
4866
4867       if (reg_mentioned_p (from, true_rtx))
4868         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4869                                       from, true_val),
4870                       pc_rtx, pc_rtx, 0, 0);
4871       if (reg_mentioned_p (from, false_rtx))
4872         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4873                                    from, false_val),
4874                        pc_rtx, pc_rtx, 0, 0);
4875
4876       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4877       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4878
4879       true_rtx = XEXP (x, 1);
4880       false_rtx = XEXP (x, 2);
4881       true_code = GET_CODE (cond);
4882     }
4883
4884   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4885      reversed, do so to avoid needing two sets of patterns for
4886      subtract-and-branch insns.  Similarly if we have a constant in the true
4887      arm, the false arm is the same as the first operand of the comparison, or
4888      the false arm is more complicated than the true arm.  */
4889
4890   if (comparison_p
4891       && reversed_comparison_code (cond, NULL) != UNKNOWN
4892       && (true_rtx == pc_rtx
4893           || (CONSTANT_P (true_rtx)
4894               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4895           || true_rtx == const0_rtx
4896           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4897           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4898               && !OBJECT_P (false_rtx))
4899           || reg_mentioned_p (true_rtx, false_rtx)
4900           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4901     {
4902       true_code = reversed_comparison_code (cond, NULL);
4903       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4904       SUBST (XEXP (x, 1), false_rtx);
4905       SUBST (XEXP (x, 2), true_rtx);
4906
4907       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4908       cond = XEXP (x, 0);
4909
4910       /* It is possible that the conditional has been simplified out.  */
4911       true_code = GET_CODE (cond);
4912       comparison_p = COMPARISON_P (cond);
4913     }
4914
4915   /* If the two arms are identical, we don't need the comparison.  */
4916
4917   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4918     return true_rtx;
4919
4920   /* Convert a == b ? b : a to "a".  */
4921   if (true_code == EQ && ! side_effects_p (cond)
4922       && !HONOR_NANS (mode)
4923       && rtx_equal_p (XEXP (cond, 0), false_rtx)
4924       && rtx_equal_p (XEXP (cond, 1), true_rtx))
4925     return false_rtx;
4926   else if (true_code == NE && ! side_effects_p (cond)
4927            && !HONOR_NANS (mode)
4928            && rtx_equal_p (XEXP (cond, 0), true_rtx)
4929            && rtx_equal_p (XEXP (cond, 1), false_rtx))
4930     return true_rtx;
4931
4932   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4933
4934   if (GET_MODE_CLASS (mode) == MODE_INT
4935       && GET_CODE (false_rtx) == NEG
4936       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4937       && comparison_p
4938       && rtx_equal_p (true_rtx, XEXP (cond, 0))
4939       && ! side_effects_p (true_rtx))
4940     switch (true_code)
4941       {
4942       case GT:
4943       case GE:
4944         return simplify_gen_unary (ABS, mode, true_rtx, mode);
4945       case LT:
4946       case LE:
4947         return
4948           simplify_gen_unary (NEG, mode,
4949                               simplify_gen_unary (ABS, mode, true_rtx, mode),
4950                               mode);
4951       default:
4952         break;
4953       }
4954
4955   /* Look for MIN or MAX.  */
4956
4957   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4958       && comparison_p
4959       && rtx_equal_p (XEXP (cond, 0), true_rtx)
4960       && rtx_equal_p (XEXP (cond, 1), false_rtx)
4961       && ! side_effects_p (cond))
4962     switch (true_code)
4963       {
4964       case GE:
4965       case GT:
4966         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4967       case LE:
4968       case LT:
4969         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4970       case GEU:
4971       case GTU:
4972         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4973       case LEU:
4974       case LTU:
4975         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4976       default:
4977         break;
4978       }
4979
4980   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4981      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4982      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4983      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4984      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4985      neither 1 or -1, but it isn't worth checking for.  */
4986
4987   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4988       && comparison_p
4989       && GET_MODE_CLASS (mode) == MODE_INT
4990       && ! side_effects_p (x))
4991     {
4992       rtx t = make_compound_operation (true_rtx, SET);
4993       rtx f = make_compound_operation (false_rtx, SET);
4994       rtx cond_op0 = XEXP (cond, 0);
4995       rtx cond_op1 = XEXP (cond, 1);
4996       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4997       enum machine_mode m = mode;
4998       rtx z = 0, c1 = NULL_RTX;
4999
5000       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5001            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5002            || GET_CODE (t) == ASHIFT
5003            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5004           && rtx_equal_p (XEXP (t, 0), f))
5005         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5006
5007       /* If an identity-zero op is commutative, check whether there
5008          would be a match if we swapped the operands.  */
5009       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5010                 || GET_CODE (t) == XOR)
5011                && rtx_equal_p (XEXP (t, 1), f))
5012         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5013       else if (GET_CODE (t) == SIGN_EXTEND
5014                && (GET_CODE (XEXP (t, 0)) == PLUS
5015                    || GET_CODE (XEXP (t, 0)) == MINUS
5016                    || GET_CODE (XEXP (t, 0)) == IOR
5017                    || GET_CODE (XEXP (t, 0)) == XOR
5018                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5019                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5020                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5021                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5022                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5023                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5024                && (num_sign_bit_copies (f, GET_MODE (f))
5025                    > (unsigned int)
5026                      (GET_MODE_BITSIZE (mode)
5027                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5028         {
5029           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5030           extend_op = SIGN_EXTEND;
5031           m = GET_MODE (XEXP (t, 0));
5032         }
5033       else if (GET_CODE (t) == SIGN_EXTEND
5034                && (GET_CODE (XEXP (t, 0)) == PLUS
5035                    || GET_CODE (XEXP (t, 0)) == IOR
5036                    || GET_CODE (XEXP (t, 0)) == XOR)
5037                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5038                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5039                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5040                && (num_sign_bit_copies (f, GET_MODE (f))
5041                    > (unsigned int)
5042                      (GET_MODE_BITSIZE (mode)
5043                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5044         {
5045           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5046           extend_op = SIGN_EXTEND;
5047           m = GET_MODE (XEXP (t, 0));
5048         }
5049       else if (GET_CODE (t) == ZERO_EXTEND
5050                && (GET_CODE (XEXP (t, 0)) == PLUS
5051                    || GET_CODE (XEXP (t, 0)) == MINUS
5052                    || GET_CODE (XEXP (t, 0)) == IOR
5053                    || GET_CODE (XEXP (t, 0)) == XOR
5054                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5055                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5056                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5057                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5058                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5059                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5060                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5061                && ((nonzero_bits (f, GET_MODE (f))
5062                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5063                    == 0))
5064         {
5065           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5066           extend_op = ZERO_EXTEND;
5067           m = GET_MODE (XEXP (t, 0));
5068         }
5069       else if (GET_CODE (t) == ZERO_EXTEND
5070                && (GET_CODE (XEXP (t, 0)) == PLUS
5071                    || GET_CODE (XEXP (t, 0)) == IOR
5072                    || GET_CODE (XEXP (t, 0)) == XOR)
5073                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5074                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5075                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5076                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5077                && ((nonzero_bits (f, GET_MODE (f))
5078                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5079                    == 0))
5080         {
5081           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5082           extend_op = ZERO_EXTEND;
5083           m = GET_MODE (XEXP (t, 0));
5084         }
5085
5086       if (z)
5087         {
5088           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5089                                                  cond_op0, cond_op1),
5090                         pc_rtx, pc_rtx, 0, 0);
5091           temp = simplify_gen_binary (MULT, m, temp,
5092                                       simplify_gen_binary (MULT, m, c1,
5093                                                            const_true_rtx));
5094           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5095           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5096
5097           if (extend_op != UNKNOWN)
5098             temp = simplify_gen_unary (extend_op, mode, temp, m);
5099
5100           return temp;
5101         }
5102     }
5103
5104   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5105      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5106      negation of a single bit, we can convert this operation to a shift.  We
5107      can actually do this more generally, but it doesn't seem worth it.  */
5108
5109   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5110       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5111       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5112            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5113           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5114                == GET_MODE_BITSIZE (mode))
5115               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5116     return
5117       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5118                             gen_lowpart (mode, XEXP (cond, 0)), i);
5119
5120   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5121   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5122       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5123       && GET_MODE (XEXP (cond, 0)) == mode
5124       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5125           == nonzero_bits (XEXP (cond, 0), mode)
5126       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5127     return XEXP (cond, 0);
5128
5129   return x;
5130 }
5131 \f
5132 /* Simplify X, a SET expression.  Return the new expression.  */
5133
5134 static rtx
5135 simplify_set (rtx x)
5136 {
5137   rtx src = SET_SRC (x);
5138   rtx dest = SET_DEST (x);
5139   enum machine_mode mode
5140     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5141   rtx other_insn;
5142   rtx *cc_use;
5143
5144   /* (set (pc) (return)) gets written as (return).  */
5145   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5146     return src;
5147
5148   /* Now that we know for sure which bits of SRC we are using, see if we can
5149      simplify the expression for the object knowing that we only need the
5150      low-order bits.  */
5151
5152   if (GET_MODE_CLASS (mode) == MODE_INT
5153       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5154     {
5155       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5156       SUBST (SET_SRC (x), src);
5157     }
5158
5159   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5160      the comparison result and try to simplify it unless we already have used
5161      undobuf.other_insn.  */
5162   if ((GET_MODE_CLASS (mode) == MODE_CC
5163        || GET_CODE (src) == COMPARE
5164        || CC0_P (dest))
5165       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5166       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5167       && COMPARISON_P (*cc_use)
5168       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5169     {
5170       enum rtx_code old_code = GET_CODE (*cc_use);
5171       enum rtx_code new_code;
5172       rtx op0, op1, tmp;
5173       int other_changed = 0;
5174       enum machine_mode compare_mode = GET_MODE (dest);
5175
5176       if (GET_CODE (src) == COMPARE)
5177         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5178       else
5179         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5180
5181       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5182                                            op0, op1);
5183       if (!tmp)
5184         new_code = old_code;
5185       else if (!CONSTANT_P (tmp))
5186         {
5187           new_code = GET_CODE (tmp);
5188           op0 = XEXP (tmp, 0);
5189           op1 = XEXP (tmp, 1);
5190         }
5191       else
5192         {
5193           rtx pat = PATTERN (other_insn);
5194           undobuf.other_insn = other_insn;
5195           SUBST (*cc_use, tmp);
5196
5197           /* Attempt to simplify CC user.  */
5198           if (GET_CODE (pat) == SET)
5199             {
5200               rtx new = simplify_rtx (SET_SRC (pat));
5201               if (new != NULL_RTX)
5202                 SUBST (SET_SRC (pat), new);
5203             }
5204
5205           /* Convert X into a no-op move.  */
5206           SUBST (SET_DEST (x), pc_rtx);
5207           SUBST (SET_SRC (x), pc_rtx);
5208           return x;
5209         }
5210
5211       /* Simplify our comparison, if possible.  */
5212       new_code = simplify_comparison (new_code, &op0, &op1);
5213
5214 #ifdef SELECT_CC_MODE
5215       /* If this machine has CC modes other than CCmode, check to see if we
5216          need to use a different CC mode here.  */
5217       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5218         compare_mode = GET_MODE (op0);
5219       else
5220         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5221
5222 #ifndef HAVE_cc0
5223       /* If the mode changed, we have to change SET_DEST, the mode in the
5224          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5225          a hard register, just build new versions with the proper mode.  If it
5226          is a pseudo, we lose unless it is only time we set the pseudo, in
5227          which case we can safely change its mode.  */
5228       if (compare_mode != GET_MODE (dest))
5229         {
5230           if (can_change_dest_mode (dest, 0, compare_mode))
5231             {
5232               unsigned int regno = REGNO (dest);
5233               rtx new_dest;
5234
5235               if (regno < FIRST_PSEUDO_REGISTER)
5236                 new_dest = gen_rtx_REG (compare_mode, regno);
5237               else
5238                 {
5239                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5240                   new_dest = regno_reg_rtx[regno];
5241                 }
5242
5243               SUBST (SET_DEST (x), new_dest);
5244               SUBST (XEXP (*cc_use, 0), new_dest);
5245               other_changed = 1;
5246
5247               dest = new_dest;
5248             }
5249         }
5250 #endif  /* cc0 */
5251 #endif  /* SELECT_CC_MODE */
5252
5253       /* If the code changed, we have to build a new comparison in
5254          undobuf.other_insn.  */
5255       if (new_code != old_code)
5256         {
5257           int other_changed_previously = other_changed;
5258           unsigned HOST_WIDE_INT mask;
5259
5260           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5261                                           dest, const0_rtx));
5262           other_changed = 1;
5263
5264           /* If the only change we made was to change an EQ into an NE or
5265              vice versa, OP0 has only one bit that might be nonzero, and OP1
5266              is zero, check if changing the user of the condition code will
5267              produce a valid insn.  If it won't, we can keep the original code
5268              in that insn by surrounding our operation with an XOR.  */
5269
5270           if (((old_code == NE && new_code == EQ)
5271                || (old_code == EQ && new_code == NE))
5272               && ! other_changed_previously && op1 == const0_rtx
5273               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5274               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5275             {
5276               rtx pat = PATTERN (other_insn), note = 0;
5277
5278               if ((recog_for_combine (&pat, other_insn, &note) < 0
5279                    && ! check_asm_operands (pat)))
5280                 {
5281                   PUT_CODE (*cc_use, old_code);
5282                   other_changed = 0;
5283
5284                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5285                                              op0, GEN_INT (mask));
5286                 }
5287             }
5288         }
5289
5290       if (other_changed)
5291         undobuf.other_insn = other_insn;
5292
5293 #ifdef HAVE_cc0
5294       /* If we are now comparing against zero, change our source if
5295          needed.  If we do not use cc0, we always have a COMPARE.  */
5296       if (op1 == const0_rtx && dest == cc0_rtx)
5297         {
5298           SUBST (SET_SRC (x), op0);
5299           src = op0;
5300         }
5301       else
5302 #endif
5303
5304       /* Otherwise, if we didn't previously have a COMPARE in the
5305          correct mode, we need one.  */
5306       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5307         {
5308           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5309           src = SET_SRC (x);
5310         }
5311       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5312         {
5313           SUBST(SET_SRC (x), op0);
5314           src = SET_SRC (x);
5315         }
5316       else
5317         {
5318           /* Otherwise, update the COMPARE if needed.  */
5319           SUBST (XEXP (src, 0), op0);
5320           SUBST (XEXP (src, 1), op1);
5321         }
5322     }
5323   else
5324     {
5325       /* Get SET_SRC in a form where we have placed back any
5326          compound expressions.  Then do the checks below.  */
5327       src = make_compound_operation (src, SET);
5328       SUBST (SET_SRC (x), src);
5329     }
5330
5331   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5332      and X being a REG or (subreg (reg)), we may be able to convert this to
5333      (set (subreg:m2 x) (op)).
5334
5335      We can always do this if M1 is narrower than M2 because that means that
5336      we only care about the low bits of the result.
5337
5338      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5339      perform a narrower operation than requested since the high-order bits will
5340      be undefined.  On machine where it is defined, this transformation is safe
5341      as long as M1 and M2 have the same number of words.  */
5342
5343   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5344       && !OBJECT_P (SUBREG_REG (src))
5345       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5346            / UNITS_PER_WORD)
5347           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5348                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5349 #ifndef WORD_REGISTER_OPERATIONS
5350       && (GET_MODE_SIZE (GET_MODE (src))
5351         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5352 #endif
5353 #ifdef CANNOT_CHANGE_MODE_CLASS
5354       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5355             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5356                                          GET_MODE (SUBREG_REG (src)),
5357                                          GET_MODE (src)))
5358 #endif
5359       && (REG_P (dest)
5360           || (GET_CODE (dest) == SUBREG
5361               && REG_P (SUBREG_REG (dest)))))
5362     {
5363       SUBST (SET_DEST (x),
5364              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5365                                       dest));
5366       SUBST (SET_SRC (x), SUBREG_REG (src));
5367
5368       src = SET_SRC (x), dest = SET_DEST (x);
5369     }
5370
5371 #ifdef HAVE_cc0
5372   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5373      in SRC.  */
5374   if (dest == cc0_rtx
5375       && GET_CODE (src) == SUBREG
5376       && subreg_lowpart_p (src)
5377       && (GET_MODE_BITSIZE (GET_MODE (src))
5378           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5379     {
5380       rtx inner = SUBREG_REG (src);
5381       enum machine_mode inner_mode = GET_MODE (inner);
5382
5383       /* Here we make sure that we don't have a sign bit on.  */
5384       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5385           && (nonzero_bits (inner, inner_mode)
5386               < ((unsigned HOST_WIDE_INT) 1
5387                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5388         {
5389           SUBST (SET_SRC (x), inner);
5390           src = SET_SRC (x);
5391         }
5392     }
5393 #endif
5394
5395 #ifdef LOAD_EXTEND_OP
5396   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5397      would require a paradoxical subreg.  Replace the subreg with a
5398      zero_extend to avoid the reload that would otherwise be required.  */
5399
5400   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5401       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5402       && SUBREG_BYTE (src) == 0
5403       && (GET_MODE_SIZE (GET_MODE (src))
5404           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5405       && MEM_P (SUBREG_REG (src)))
5406     {
5407       SUBST (SET_SRC (x),
5408              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5409                             GET_MODE (src), SUBREG_REG (src)));
5410
5411       src = SET_SRC (x);
5412     }
5413 #endif
5414
5415   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5416      are comparing an item known to be 0 or -1 against 0, use a logical
5417      operation instead. Check for one of the arms being an IOR of the other
5418      arm with some value.  We compute three terms to be IOR'ed together.  In
5419      practice, at most two will be nonzero.  Then we do the IOR's.  */
5420
5421   if (GET_CODE (dest) != PC
5422       && GET_CODE (src) == IF_THEN_ELSE
5423       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5424       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5425       && XEXP (XEXP (src, 0), 1) == const0_rtx
5426       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5427 #ifdef HAVE_conditional_move
5428       && ! can_conditionally_move_p (GET_MODE (src))
5429 #endif
5430       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5431                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5432           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5433       && ! side_effects_p (src))
5434     {
5435       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5436                       ? XEXP (src, 1) : XEXP (src, 2));
5437       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5438                    ? XEXP (src, 2) : XEXP (src, 1));
5439       rtx term1 = const0_rtx, term2, term3;
5440
5441       if (GET_CODE (true_rtx) == IOR
5442           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5443         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5444       else if (GET_CODE (true_rtx) == IOR
5445                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5446         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5447       else if (GET_CODE (false_rtx) == IOR
5448                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5449         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5450       else if (GET_CODE (false_rtx) == IOR
5451                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5452         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5453
5454       term2 = simplify_gen_binary (AND, GET_MODE (src),
5455                                    XEXP (XEXP (src, 0), 0), true_rtx);
5456       term3 = simplify_gen_binary (AND, GET_MODE (src),
5457                                    simplify_gen_unary (NOT, GET_MODE (src),
5458                                                        XEXP (XEXP (src, 0), 0),
5459                                                        GET_MODE (src)),
5460                                    false_rtx);
5461
5462       SUBST (SET_SRC (x),
5463              simplify_gen_binary (IOR, GET_MODE (src),
5464                                   simplify_gen_binary (IOR, GET_MODE (src),
5465                                                        term1, term2),
5466                                   term3));
5467
5468       src = SET_SRC (x);
5469     }
5470
5471   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5472      whole thing fail.  */
5473   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5474     return src;
5475   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5476     return dest;
5477   else
5478     /* Convert this into a field assignment operation, if possible.  */
5479     return make_field_assignment (x);
5480 }
5481 \f
5482 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5483    result.  */
5484
5485 static rtx
5486 simplify_logical (rtx x)
5487 {
5488   enum machine_mode mode = GET_MODE (x);
5489   rtx op0 = XEXP (x, 0);
5490   rtx op1 = XEXP (x, 1);
5491
5492   switch (GET_CODE (x))
5493     {
5494     case AND:
5495       /* We can call simplify_and_const_int only if we don't lose
5496          any (sign) bits when converting INTVAL (op1) to
5497          "unsigned HOST_WIDE_INT".  */
5498       if (GET_CODE (op1) == CONST_INT
5499           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5500               || INTVAL (op1) > 0))
5501         {
5502           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5503           if (GET_CODE (x) != AND)
5504             return x;
5505
5506           op0 = XEXP (x, 0);
5507           op1 = XEXP (x, 1);
5508         }
5509
5510       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5511          apply the distributive law and then the inverse distributive
5512          law to see if things simplify.  */
5513       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5514         {
5515           rtx result = distribute_and_simplify_rtx (x, 0);
5516           if (result)
5517             return result;
5518         }
5519       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5520         {
5521           rtx result = distribute_and_simplify_rtx (x, 1);
5522           if (result)
5523             return result;
5524         }
5525       break;
5526
5527     case IOR:
5528       /* If we have (ior (and A B) C), apply the distributive law and then
5529          the inverse distributive law to see if things simplify.  */
5530
5531       if (GET_CODE (op0) == AND)
5532         {
5533           rtx result = distribute_and_simplify_rtx (x, 0);
5534           if (result)
5535             return result;
5536         }
5537
5538       if (GET_CODE (op1) == AND)
5539         {
5540           rtx result = distribute_and_simplify_rtx (x, 1);
5541           if (result)
5542             return result;
5543         }
5544       break;
5545
5546     default:
5547       gcc_unreachable ();
5548     }
5549
5550   return x;
5551 }
5552 \f
5553 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5554    operations" because they can be replaced with two more basic operations.
5555    ZERO_EXTEND is also considered "compound" because it can be replaced with
5556    an AND operation, which is simpler, though only one operation.
5557
5558    The function expand_compound_operation is called with an rtx expression
5559    and will convert it to the appropriate shifts and AND operations,
5560    simplifying at each stage.
5561
5562    The function make_compound_operation is called to convert an expression
5563    consisting of shifts and ANDs into the equivalent compound expression.
5564    It is the inverse of this function, loosely speaking.  */
5565
5566 static rtx
5567 expand_compound_operation (rtx x)
5568 {
5569   unsigned HOST_WIDE_INT pos = 0, len;
5570   int unsignedp = 0;
5571   unsigned int modewidth;
5572   rtx tem;
5573
5574   switch (GET_CODE (x))
5575     {
5576     case ZERO_EXTEND:
5577       unsignedp = 1;
5578     case SIGN_EXTEND:
5579       /* We can't necessarily use a const_int for a multiword mode;
5580          it depends on implicitly extending the value.
5581          Since we don't know the right way to extend it,
5582          we can't tell whether the implicit way is right.
5583
5584          Even for a mode that is no wider than a const_int,
5585          we can't win, because we need to sign extend one of its bits through
5586          the rest of it, and we don't know which bit.  */
5587       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5588         return x;
5589
5590       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5591          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5592          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5593          reloaded. If not for that, MEM's would very rarely be safe.
5594
5595          Reject MODEs bigger than a word, because we might not be able
5596          to reference a two-register group starting with an arbitrary register
5597          (and currently gen_lowpart might crash for a SUBREG).  */
5598
5599       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5600         return x;
5601
5602       /* Reject MODEs that aren't scalar integers because turning vector
5603          or complex modes into shifts causes problems.  */
5604
5605       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5606         return x;
5607
5608       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5609       /* If the inner object has VOIDmode (the only way this can happen
5610          is if it is an ASM_OPERANDS), we can't do anything since we don't
5611          know how much masking to do.  */
5612       if (len == 0)
5613         return x;
5614
5615       break;
5616
5617     case ZERO_EXTRACT:
5618       unsignedp = 1;
5619
5620       /* ... fall through ...  */
5621
5622     case SIGN_EXTRACT:
5623       /* If the operand is a CLOBBER, just return it.  */
5624       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5625         return XEXP (x, 0);
5626
5627       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5628           || GET_CODE (XEXP (x, 2)) != CONST_INT
5629           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5630         return x;
5631
5632       /* Reject MODEs that aren't scalar integers because turning vector
5633          or complex modes into shifts causes problems.  */
5634
5635       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5636         return x;
5637
5638       len = INTVAL (XEXP (x, 1));
5639       pos = INTVAL (XEXP (x, 2));
5640
5641       /* This should stay within the object being extracted, fail otherwise.  */
5642       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5643         return x;
5644
5645       if (BITS_BIG_ENDIAN)
5646         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5647
5648       break;
5649
5650     default:
5651       return x;
5652     }
5653   /* Convert sign extension to zero extension, if we know that the high
5654      bit is not set, as this is easier to optimize.  It will be converted
5655      back to cheaper alternative in make_extraction.  */
5656   if (GET_CODE (x) == SIGN_EXTEND
5657       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5658           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5659                 & ~(((unsigned HOST_WIDE_INT)
5660                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5661                      >> 1))
5662                == 0)))
5663     {
5664       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5665       rtx temp2 = expand_compound_operation (temp);
5666
5667       /* Make sure this is a profitable operation.  */
5668       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5669        return temp2;
5670       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5671        return temp;
5672       else
5673        return x;
5674     }
5675
5676   /* We can optimize some special cases of ZERO_EXTEND.  */
5677   if (GET_CODE (x) == ZERO_EXTEND)
5678     {
5679       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5680          know that the last value didn't have any inappropriate bits
5681          set.  */
5682       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5683           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5684           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5685           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5686               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5687         return XEXP (XEXP (x, 0), 0);
5688
5689       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5690       if (GET_CODE (XEXP (x, 0)) == SUBREG
5691           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5692           && subreg_lowpart_p (XEXP (x, 0))
5693           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5694           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5695               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5696         return SUBREG_REG (XEXP (x, 0));
5697
5698       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5699          is a comparison and STORE_FLAG_VALUE permits.  This is like
5700          the first case, but it works even when GET_MODE (x) is larger
5701          than HOST_WIDE_INT.  */
5702       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5703           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5704           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5705           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5706               <= HOST_BITS_PER_WIDE_INT)
5707           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5708               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5709         return XEXP (XEXP (x, 0), 0);
5710
5711       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5712       if (GET_CODE (XEXP (x, 0)) == SUBREG
5713           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5714           && subreg_lowpart_p (XEXP (x, 0))
5715           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5716           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5717               <= HOST_BITS_PER_WIDE_INT)
5718           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5719               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5720         return SUBREG_REG (XEXP (x, 0));
5721
5722     }
5723
5724   /* If we reach here, we want to return a pair of shifts.  The inner
5725      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5726      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5727      logical depending on the value of UNSIGNEDP.
5728
5729      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5730      converted into an AND of a shift.
5731
5732      We must check for the case where the left shift would have a negative
5733      count.  This can happen in a case like (x >> 31) & 255 on machines
5734      that can't shift by a constant.  On those machines, we would first
5735      combine the shift with the AND to produce a variable-position
5736      extraction.  Then the constant of 31 would be substituted in to produce
5737      a such a position.  */
5738
5739   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5740   if (modewidth + len >= pos)
5741     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5742                                 GET_MODE (x),
5743                                 simplify_shift_const (NULL_RTX, ASHIFT,
5744                                                       GET_MODE (x),
5745                                                       XEXP (x, 0),
5746                                                       modewidth - pos - len),
5747                                 modewidth - len);
5748
5749   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5750     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5751                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5752                                                         GET_MODE (x),
5753                                                         XEXP (x, 0), pos),
5754                                   ((HOST_WIDE_INT) 1 << len) - 1);
5755   else
5756     /* Any other cases we can't handle.  */
5757     return x;
5758
5759   /* If we couldn't do this for some reason, return the original
5760      expression.  */
5761   if (GET_CODE (tem) == CLOBBER)
5762     return x;
5763
5764   return tem;
5765 }
5766 \f
5767 /* X is a SET which contains an assignment of one object into
5768    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5769    or certain SUBREGS). If possible, convert it into a series of
5770    logical operations.
5771
5772    We half-heartedly support variable positions, but do not at all
5773    support variable lengths.  */
5774
5775 static rtx
5776 expand_field_assignment (rtx x)
5777 {
5778   rtx inner;
5779   rtx pos;                      /* Always counts from low bit.  */
5780   int len;
5781   rtx mask, cleared, masked;
5782   enum machine_mode compute_mode;
5783
5784   /* Loop until we find something we can't simplify.  */
5785   while (1)
5786     {
5787       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5788           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5789         {
5790           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5791           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5792           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5793         }
5794       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5795                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5796         {
5797           inner = XEXP (SET_DEST (x), 0);
5798           len = INTVAL (XEXP (SET_DEST (x), 1));
5799           pos = XEXP (SET_DEST (x), 2);
5800
5801           /* A constant position should stay within the width of INNER.  */
5802           if (GET_CODE (pos) == CONST_INT
5803               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5804             break;
5805
5806           if (BITS_BIG_ENDIAN)
5807             {
5808               if (GET_CODE (pos) == CONST_INT)
5809                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5810                                - INTVAL (pos));
5811               else if (GET_CODE (pos) == MINUS
5812                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5813                        && (INTVAL (XEXP (pos, 1))
5814                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5815                 /* If position is ADJUST - X, new position is X.  */
5816                 pos = XEXP (pos, 0);
5817               else
5818                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5819                                            GEN_INT (GET_MODE_BITSIZE (
5820                                                     GET_MODE (inner))
5821                                                     - len),
5822                                            pos);
5823             }
5824         }
5825
5826       /* A SUBREG between two modes that occupy the same numbers of words
5827          can be done by moving the SUBREG to the source.  */
5828       else if (GET_CODE (SET_DEST (x)) == SUBREG
5829                /* We need SUBREGs to compute nonzero_bits properly.  */
5830                && nonzero_sign_valid
5831                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5832                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5833                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5834                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5835         {
5836           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5837                            gen_lowpart
5838                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5839                             SET_SRC (x)));
5840           continue;
5841         }
5842       else
5843         break;
5844
5845       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5846         inner = SUBREG_REG (inner);
5847
5848       compute_mode = GET_MODE (inner);
5849
5850       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
5851       if (! SCALAR_INT_MODE_P (compute_mode))
5852         {
5853           enum machine_mode imode;
5854
5855           /* Don't do anything for vector or complex integral types.  */
5856           if (! FLOAT_MODE_P (compute_mode))
5857             break;
5858
5859           /* Try to find an integral mode to pun with.  */
5860           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5861           if (imode == BLKmode)
5862             break;
5863
5864           compute_mode = imode;
5865           inner = gen_lowpart (imode, inner);
5866         }
5867
5868       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5869       if (len >= HOST_BITS_PER_WIDE_INT)
5870         break;
5871
5872       /* Now compute the equivalent expression.  Make a copy of INNER
5873          for the SET_DEST in case it is a MEM into which we will substitute;
5874          we don't want shared RTL in that case.  */
5875       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5876       cleared = simplify_gen_binary (AND, compute_mode,
5877                                      simplify_gen_unary (NOT, compute_mode,
5878                                        simplify_gen_binary (ASHIFT,
5879                                                             compute_mode,
5880                                                             mask, pos),
5881                                        compute_mode),
5882                                      inner);
5883       masked = simplify_gen_binary (ASHIFT, compute_mode,
5884                                     simplify_gen_binary (
5885                                       AND, compute_mode,
5886                                       gen_lowpart (compute_mode, SET_SRC (x)),
5887                                       mask),
5888                                     pos);
5889
5890       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5891                        simplify_gen_binary (IOR, compute_mode,
5892                                             cleared, masked));
5893     }
5894
5895   return x;
5896 }
5897 \f
5898 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5899    it is an RTX that represents a variable starting position; otherwise,
5900    POS is the (constant) starting bit position (counted from the LSB).
5901
5902    UNSIGNEDP is nonzero for an unsigned reference and zero for a
5903    signed reference.
5904
5905    IN_DEST is nonzero if this is a reference in the destination of a
5906    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
5907    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5908    be used.
5909
5910    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
5911    ZERO_EXTRACT should be built even for bits starting at bit 0.
5912
5913    MODE is the desired mode of the result (if IN_DEST == 0).
5914
5915    The result is an RTX for the extraction or NULL_RTX if the target
5916    can't handle it.  */
5917
5918 static rtx
5919 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5920                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5921                  int in_dest, int in_compare)
5922 {
5923   /* This mode describes the size of the storage area
5924      to fetch the overall value from.  Within that, we
5925      ignore the POS lowest bits, etc.  */
5926   enum machine_mode is_mode = GET_MODE (inner);
5927   enum machine_mode inner_mode;
5928   enum machine_mode wanted_inner_mode;
5929   enum machine_mode wanted_inner_reg_mode = word_mode;
5930   enum machine_mode pos_mode = word_mode;
5931   enum machine_mode extraction_mode = word_mode;
5932   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5933   rtx new = 0;
5934   rtx orig_pos_rtx = pos_rtx;
5935   HOST_WIDE_INT orig_pos;
5936
5937   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5938     {
5939       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5940          consider just the QI as the memory to extract from.
5941          The subreg adds or removes high bits; its mode is
5942          irrelevant to the meaning of this extraction,
5943          since POS and LEN count from the lsb.  */
5944       if (MEM_P (SUBREG_REG (inner)))
5945         is_mode = GET_MODE (SUBREG_REG (inner));
5946       inner = SUBREG_REG (inner);
5947     }
5948   else if (GET_CODE (inner) == ASHIFT
5949            && GET_CODE (XEXP (inner, 1)) == CONST_INT
5950            && pos_rtx == 0 && pos == 0
5951            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5952     {
5953       /* We're extracting the least significant bits of an rtx
5954          (ashift X (const_int C)), where LEN > C.  Extract the
5955          least significant (LEN - C) bits of X, giving an rtx
5956          whose mode is MODE, then shift it left C times.  */
5957       new = make_extraction (mode, XEXP (inner, 0),
5958                              0, 0, len - INTVAL (XEXP (inner, 1)),
5959                              unsignedp, in_dest, in_compare);
5960       if (new != 0)
5961         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5962     }
5963
5964   inner_mode = GET_MODE (inner);
5965
5966   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5967     pos = INTVAL (pos_rtx), pos_rtx = 0;
5968
5969   /* See if this can be done without an extraction.  We never can if the
5970      width of the field is not the same as that of some integer mode. For
5971      registers, we can only avoid the extraction if the position is at the
5972      low-order bit and this is either not in the destination or we have the
5973      appropriate STRICT_LOW_PART operation available.
5974
5975      For MEM, we can avoid an extract if the field starts on an appropriate
5976      boundary and we can change the mode of the memory reference.  */
5977
5978   if (tmode != BLKmode
5979       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5980            && !MEM_P (inner)
5981            && (inner_mode == tmode
5982                || !REG_P (inner)
5983                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
5984                                          GET_MODE_BITSIZE (inner_mode))
5985                || reg_truncated_to_mode (tmode, inner))
5986            && (! in_dest
5987                || (REG_P (inner)
5988                    && have_insn_for (STRICT_LOW_PART, tmode))))
5989           || (MEM_P (inner) && pos_rtx == 0
5990               && (pos
5991                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5992                      : BITS_PER_UNIT)) == 0
5993               /* We can't do this if we are widening INNER_MODE (it
5994                  may not be aligned, for one thing).  */
5995               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5996               && (inner_mode == tmode
5997                   || (! mode_dependent_address_p (XEXP (inner, 0))
5998                       && ! MEM_VOLATILE_P (inner))))))
5999     {
6000       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6001          field.  If the original and current mode are the same, we need not
6002          adjust the offset.  Otherwise, we do if bytes big endian.
6003
6004          If INNER is not a MEM, get a piece consisting of just the field
6005          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6006
6007       if (MEM_P (inner))
6008         {
6009           HOST_WIDE_INT offset;
6010
6011           /* POS counts from lsb, but make OFFSET count in memory order.  */
6012           if (BYTES_BIG_ENDIAN)
6013             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6014           else
6015             offset = pos / BITS_PER_UNIT;
6016
6017           new = adjust_address_nv (inner, tmode, offset);
6018         }
6019       else if (REG_P (inner))
6020         {
6021           if (tmode != inner_mode)
6022             {
6023               /* We can't call gen_lowpart in a DEST since we
6024                  always want a SUBREG (see below) and it would sometimes
6025                  return a new hard register.  */
6026               if (pos || in_dest)
6027                 {
6028                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6029
6030                   if (WORDS_BIG_ENDIAN
6031                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6032                     final_word = ((GET_MODE_SIZE (inner_mode)
6033                                    - GET_MODE_SIZE (tmode))
6034                                   / UNITS_PER_WORD) - final_word;
6035
6036                   final_word *= UNITS_PER_WORD;
6037                   if (BYTES_BIG_ENDIAN &&
6038                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6039                     final_word += (GET_MODE_SIZE (inner_mode)
6040                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6041
6042                   /* Avoid creating invalid subregs, for example when
6043                      simplifying (x>>32)&255.  */
6044                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6045                     return NULL_RTX;
6046
6047                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6048                 }
6049               else
6050                 new = gen_lowpart (tmode, inner);
6051             }
6052           else
6053             new = inner;
6054         }
6055       else
6056         new = force_to_mode (inner, tmode,
6057                              len >= HOST_BITS_PER_WIDE_INT
6058                              ? ~(unsigned HOST_WIDE_INT) 0
6059                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6060                              0);
6061
6062       /* If this extraction is going into the destination of a SET,
6063          make a STRICT_LOW_PART unless we made a MEM.  */
6064
6065       if (in_dest)
6066         return (MEM_P (new) ? new
6067                 : (GET_CODE (new) != SUBREG
6068                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6069                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6070
6071       if (mode == tmode)
6072         return new;
6073
6074       if (GET_CODE (new) == CONST_INT)
6075         return gen_int_mode (INTVAL (new), mode);
6076
6077       /* If we know that no extraneous bits are set, and that the high
6078          bit is not set, convert the extraction to the cheaper of
6079          sign and zero extension, that are equivalent in these cases.  */
6080       if (flag_expensive_optimizations
6081           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6082               && ((nonzero_bits (new, tmode)
6083                    & ~(((unsigned HOST_WIDE_INT)
6084                         GET_MODE_MASK (tmode))
6085                        >> 1))
6086                   == 0)))
6087         {
6088           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6089           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6090
6091           /* Prefer ZERO_EXTENSION, since it gives more information to
6092              backends.  */
6093           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6094             return temp;
6095           return temp1;
6096         }
6097
6098       /* Otherwise, sign- or zero-extend unless we already are in the
6099          proper mode.  */
6100
6101       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6102                              mode, new));
6103     }
6104
6105   /* Unless this is a COMPARE or we have a funny memory reference,
6106      don't do anything with zero-extending field extracts starting at
6107      the low-order bit since they are simple AND operations.  */
6108   if (pos_rtx == 0 && pos == 0 && ! in_dest
6109       && ! in_compare && unsignedp)
6110     return 0;
6111
6112   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6113      if the position is not a constant and the length is not 1.  In all
6114      other cases, we would only be going outside our object in cases when
6115      an original shift would have been undefined.  */
6116   if (MEM_P (inner)
6117       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6118           || (pos_rtx != 0 && len != 1)))
6119     return 0;
6120
6121   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6122      and the mode for the result.  */
6123   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6124     {
6125       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6126       pos_mode = mode_for_extraction (EP_insv, 2);
6127       extraction_mode = mode_for_extraction (EP_insv, 3);
6128     }
6129
6130   if (! in_dest && unsignedp
6131       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6132     {
6133       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6134       pos_mode = mode_for_extraction (EP_extzv, 3);
6135       extraction_mode = mode_for_extraction (EP_extzv, 0);
6136     }
6137
6138   if (! in_dest && ! unsignedp
6139       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6140     {
6141       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6142       pos_mode = mode_for_extraction (EP_extv, 3);
6143       extraction_mode = mode_for_extraction (EP_extv, 0);
6144     }
6145
6146   /* Never narrow an object, since that might not be safe.  */
6147
6148   if (mode != VOIDmode
6149       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6150     extraction_mode = mode;
6151
6152   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6153       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6154     pos_mode = GET_MODE (pos_rtx);
6155
6156   /* If this is not from memory, the desired mode is the preferred mode
6157      for an extraction pattern's first input operand, or word_mode if there
6158      is none.  */
6159   if (!MEM_P (inner))
6160     wanted_inner_mode = wanted_inner_reg_mode;
6161   else
6162     {
6163       /* Be careful not to go beyond the extracted object and maintain the
6164          natural alignment of the memory.  */
6165       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6166       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6167              > GET_MODE_BITSIZE (wanted_inner_mode))
6168         {
6169           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6170           gcc_assert (wanted_inner_mode != VOIDmode);
6171         }
6172
6173       /* If we have to change the mode of memory and cannot, the desired mode
6174          is EXTRACTION_MODE.  */
6175       if (inner_mode != wanted_inner_mode
6176           && (mode_dependent_address_p (XEXP (inner, 0))
6177               || MEM_VOLATILE_P (inner)
6178               || pos_rtx))
6179         wanted_inner_mode = extraction_mode;
6180     }
6181
6182   orig_pos = pos;
6183
6184   if (BITS_BIG_ENDIAN)
6185     {
6186       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6187          BITS_BIG_ENDIAN style.  If position is constant, compute new
6188          position.  Otherwise, build subtraction.
6189          Note that POS is relative to the mode of the original argument.
6190          If it's a MEM we need to recompute POS relative to that.
6191          However, if we're extracting from (or inserting into) a register,
6192          we want to recompute POS relative to wanted_inner_mode.  */
6193       int width = (MEM_P (inner)
6194                    ? GET_MODE_BITSIZE (is_mode)
6195                    : GET_MODE_BITSIZE (wanted_inner_mode));
6196
6197       if (pos_rtx == 0)
6198         pos = width - len - pos;
6199       else
6200         pos_rtx
6201           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6202       /* POS may be less than 0 now, but we check for that below.
6203          Note that it can only be less than 0 if !MEM_P (inner).  */
6204     }
6205
6206   /* If INNER has a wider mode, and this is a constant extraction, try to
6207      make it smaller and adjust the byte to point to the byte containing
6208      the value.  */
6209   if (wanted_inner_mode != VOIDmode
6210       && inner_mode != wanted_inner_mode
6211       && ! pos_rtx
6212       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6213       && MEM_P (inner)
6214       && ! mode_dependent_address_p (XEXP (inner, 0))
6215       && ! MEM_VOLATILE_P (inner))
6216     {
6217       int offset = 0;
6218
6219       /* The computations below will be correct if the machine is big
6220          endian in both bits and bytes or little endian in bits and bytes.
6221          If it is mixed, we must adjust.  */
6222
6223       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6224          adjust OFFSET to compensate.  */
6225       if (BYTES_BIG_ENDIAN
6226           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6227         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6228
6229       /* We can now move to the desired byte.  */
6230       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6231                 * GET_MODE_SIZE (wanted_inner_mode);
6232       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6233
6234       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6235           && is_mode != wanted_inner_mode)
6236         offset = (GET_MODE_SIZE (is_mode)
6237                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6238
6239       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6240     }
6241
6242   /* If INNER is not memory, we can always get it into the proper mode.  If we
6243      are changing its mode, POS must be a constant and smaller than the size
6244      of the new mode.  */
6245   else if (!MEM_P (inner))
6246     {
6247       if (GET_MODE (inner) != wanted_inner_mode
6248           && (pos_rtx != 0
6249               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6250         return 0;
6251
6252       if (orig_pos < 0)
6253         return 0;
6254
6255       inner = force_to_mode (inner, wanted_inner_mode,
6256                              pos_rtx
6257                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6258                              ? ~(unsigned HOST_WIDE_INT) 0
6259                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6260                                 << orig_pos),
6261                              0);
6262     }
6263
6264   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6265      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6266   if (pos_rtx != 0
6267       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6268     {
6269       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6270
6271       /* If we know that no extraneous bits are set, and that the high
6272          bit is not set, convert extraction to cheaper one - either
6273          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6274          cases.  */
6275       if (flag_expensive_optimizations
6276           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6277               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6278                    & ~(((unsigned HOST_WIDE_INT)
6279                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6280                        >> 1))
6281                   == 0)))
6282         {
6283           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6284
6285           /* Prefer ZERO_EXTENSION, since it gives more information to
6286              backends.  */
6287           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6288             temp = temp1;
6289         }
6290       pos_rtx = temp;
6291     }
6292   else if (pos_rtx != 0
6293            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6294     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6295
6296   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6297      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6298      be a CONST_INT.  */
6299   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6300     pos_rtx = orig_pos_rtx;
6301
6302   else if (pos_rtx == 0)
6303     pos_rtx = GEN_INT (pos);
6304
6305   /* Make the required operation.  See if we can use existing rtx.  */
6306   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6307                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6308   if (! in_dest)
6309     new = gen_lowpart (mode, new);
6310
6311   return new;
6312 }
6313 \f
6314 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6315    with any other operations in X.  Return X without that shift if so.  */
6316
6317 static rtx
6318 extract_left_shift (rtx x, int count)
6319 {
6320   enum rtx_code code = GET_CODE (x);
6321   enum machine_mode mode = GET_MODE (x);
6322   rtx tem;
6323
6324   switch (code)
6325     {
6326     case ASHIFT:
6327       /* This is the shift itself.  If it is wide enough, we will return
6328          either the value being shifted if the shift count is equal to
6329          COUNT or a shift for the difference.  */
6330       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6331           && INTVAL (XEXP (x, 1)) >= count)
6332         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6333                                      INTVAL (XEXP (x, 1)) - count);
6334       break;
6335
6336     case NEG:  case NOT:
6337       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6338         return simplify_gen_unary (code, mode, tem, mode);
6339
6340       break;
6341
6342     case PLUS:  case IOR:  case XOR:  case AND:
6343       /* If we can safely shift this constant and we find the inner shift,
6344          make a new operation.  */
6345       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6346           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6347           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6348         return simplify_gen_binary (code, mode, tem,
6349                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6350
6351       break;
6352
6353     default:
6354       break;
6355     }
6356
6357   return 0;
6358 }
6359 \f
6360 /* Look at the expression rooted at X.  Look for expressions
6361    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6362    Form these expressions.
6363
6364    Return the new rtx, usually just X.
6365
6366    Also, for machines like the VAX that don't have logical shift insns,
6367    try to convert logical to arithmetic shift operations in cases where
6368    they are equivalent.  This undoes the canonicalizations to logical
6369    shifts done elsewhere.
6370
6371    We try, as much as possible, to re-use rtl expressions to save memory.
6372
6373    IN_CODE says what kind of expression we are processing.  Normally, it is
6374    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6375    being kludges), it is MEM.  When processing the arguments of a comparison
6376    or a COMPARE against zero, it is COMPARE.  */
6377
6378 static rtx
6379 make_compound_operation (rtx x, enum rtx_code in_code)
6380 {
6381   enum rtx_code code = GET_CODE (x);
6382   enum machine_mode mode = GET_MODE (x);
6383   int mode_width = GET_MODE_BITSIZE (mode);
6384   rtx rhs, lhs;
6385   enum rtx_code next_code;
6386   int i;
6387   rtx new = 0;
6388   rtx tem;
6389   const char *fmt;
6390
6391   /* Select the code to be used in recursive calls.  Once we are inside an
6392      address, we stay there.  If we have a comparison, set to COMPARE,
6393      but once inside, go back to our default of SET.  */
6394
6395   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6396                : ((code == COMPARE || COMPARISON_P (x))
6397                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6398                : in_code == COMPARE ? SET : in_code);
6399
6400   /* Process depending on the code of this operation.  If NEW is set
6401      nonzero, it will be returned.  */
6402
6403   switch (code)
6404     {
6405     case ASHIFT:
6406       /* Convert shifts by constants into multiplications if inside
6407          an address.  */
6408       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6409           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6410           && INTVAL (XEXP (x, 1)) >= 0)
6411         {
6412           new = make_compound_operation (XEXP (x, 0), next_code);
6413           new = gen_rtx_MULT (mode, new,
6414                               GEN_INT ((HOST_WIDE_INT) 1
6415                                        << INTVAL (XEXP (x, 1))));
6416         }
6417       break;
6418
6419     case AND:
6420       /* If the second operand is not a constant, we can't do anything
6421          with it.  */
6422       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6423         break;
6424
6425       /* If the constant is a power of two minus one and the first operand
6426          is a logical right shift, make an extraction.  */
6427       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6428           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6429         {
6430           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6431           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6432                                  0, in_code == COMPARE);
6433         }
6434
6435       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6436       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6437                && subreg_lowpart_p (XEXP (x, 0))
6438                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6439                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6440         {
6441           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6442                                          next_code);
6443           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6444                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6445                                  0, in_code == COMPARE);
6446         }
6447       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6448       else if ((GET_CODE (XEXP (x, 0)) == XOR
6449                 || GET_CODE (XEXP (x, 0)) == IOR)
6450                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6451                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6452                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6453         {
6454           /* Apply the distributive law, and then try to make extractions.  */
6455           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6456                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6457                                              XEXP (x, 1)),
6458                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6459                                              XEXP (x, 1)));
6460           new = make_compound_operation (new, in_code);
6461         }
6462
6463       /* If we are have (and (rotate X C) M) and C is larger than the number
6464          of bits in M, this is an extraction.  */
6465
6466       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6467                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6468                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6469                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6470         {
6471           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6472           new = make_extraction (mode, new,
6473                                  (GET_MODE_BITSIZE (mode)
6474                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6475                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6476         }
6477
6478       /* On machines without logical shifts, if the operand of the AND is
6479          a logical shift and our mask turns off all the propagated sign
6480          bits, we can replace the logical shift with an arithmetic shift.  */
6481       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6482                && !have_insn_for (LSHIFTRT, mode)
6483                && have_insn_for (ASHIFTRT, mode)
6484                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6485                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6486                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6487                && mode_width <= HOST_BITS_PER_WIDE_INT)
6488         {
6489           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6490
6491           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6492           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6493             SUBST (XEXP (x, 0),
6494                    gen_rtx_ASHIFTRT (mode,
6495                                      make_compound_operation
6496                                      (XEXP (XEXP (x, 0), 0), next_code),
6497                                      XEXP (XEXP (x, 0), 1)));
6498         }
6499
6500       /* If the constant is one less than a power of two, this might be
6501          representable by an extraction even if no shift is present.
6502          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6503          we are in a COMPARE.  */
6504       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6505         new = make_extraction (mode,
6506                                make_compound_operation (XEXP (x, 0),
6507                                                         next_code),
6508                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6509
6510       /* If we are in a comparison and this is an AND with a power of two,
6511          convert this into the appropriate bit extract.  */
6512       else if (in_code == COMPARE
6513                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6514         new = make_extraction (mode,
6515                                make_compound_operation (XEXP (x, 0),
6516                                                         next_code),
6517                                i, NULL_RTX, 1, 1, 0, 1);
6518
6519       break;
6520
6521     case LSHIFTRT:
6522       /* If the sign bit is known to be zero, replace this with an
6523          arithmetic shift.  */
6524       if (have_insn_for (ASHIFTRT, mode)
6525           && ! have_insn_for (LSHIFTRT, mode)
6526           && mode_width <= HOST_BITS_PER_WIDE_INT
6527           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6528         {
6529           new = gen_rtx_ASHIFTRT (mode,
6530                                   make_compound_operation (XEXP (x, 0),
6531                                                            next_code),
6532                                   XEXP (x, 1));
6533           break;
6534         }
6535
6536       /* ... fall through ...  */
6537
6538     case ASHIFTRT:
6539       lhs = XEXP (x, 0);
6540       rhs = XEXP (x, 1);
6541
6542       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6543          this is a SIGN_EXTRACT.  */
6544       if (GET_CODE (rhs) == CONST_INT
6545           && GET_CODE (lhs) == ASHIFT
6546           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6547           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6548         {
6549           new = make_compound_operation (XEXP (lhs, 0), next_code);
6550           new = make_extraction (mode, new,
6551                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6552                                  NULL_RTX, mode_width - INTVAL (rhs),
6553                                  code == LSHIFTRT, 0, in_code == COMPARE);
6554           break;
6555         }
6556
6557       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6558          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6559          also do this for some cases of SIGN_EXTRACT, but it doesn't
6560          seem worth the effort; the case checked for occurs on Alpha.  */
6561
6562       if (!OBJECT_P (lhs)
6563           && ! (GET_CODE (lhs) == SUBREG
6564                 && (OBJECT_P (SUBREG_REG (lhs))))
6565           && GET_CODE (rhs) == CONST_INT
6566           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6567           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6568         new = make_extraction (mode, make_compound_operation (new, next_code),
6569                                0, NULL_RTX, mode_width - INTVAL (rhs),
6570                                code == LSHIFTRT, 0, in_code == COMPARE);
6571
6572       break;
6573
6574     case SUBREG:
6575       /* Call ourselves recursively on the inner expression.  If we are
6576          narrowing the object and it has a different RTL code from
6577          what it originally did, do this SUBREG as a force_to_mode.  */
6578
6579       tem = make_compound_operation (SUBREG_REG (x), in_code);
6580
6581       {
6582         rtx simplified;
6583         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6584                                       SUBREG_BYTE (x));
6585
6586         if (simplified)
6587           tem = simplified;
6588
6589         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6590             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6591             && subreg_lowpart_p (x))
6592           {
6593             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6594                                        0);
6595
6596             /* If we have something other than a SUBREG, we might have
6597                done an expansion, so rerun ourselves.  */
6598             if (GET_CODE (newer) != SUBREG)
6599               newer = make_compound_operation (newer, in_code);
6600
6601             return newer;
6602           }
6603
6604         if (simplified)
6605           return tem;
6606       }
6607       break;
6608
6609     default:
6610       break;
6611     }
6612
6613   if (new)
6614     {
6615       x = gen_lowpart (mode, new);
6616       code = GET_CODE (x);
6617     }
6618
6619   /* Now recursively process each operand of this operation.  */
6620   fmt = GET_RTX_FORMAT (code);
6621   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6622     if (fmt[i] == 'e')
6623       {
6624         new = make_compound_operation (XEXP (x, i), next_code);
6625         SUBST (XEXP (x, i), new);
6626       }
6627
6628   /* If this is a commutative operation, the changes to the operands
6629      may have made it noncanonical.  */
6630   if (COMMUTATIVE_ARITH_P (x)
6631       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6632     {
6633       tem = XEXP (x, 0);
6634       SUBST (XEXP (x, 0), XEXP (x, 1));
6635       SUBST (XEXP (x, 1), tem);
6636     }
6637
6638   return x;
6639 }
6640 \f
6641 /* Given M see if it is a value that would select a field of bits
6642    within an item, but not the entire word.  Return -1 if not.
6643    Otherwise, return the starting position of the field, where 0 is the
6644    low-order bit.
6645
6646    *PLEN is set to the length of the field.  */
6647
6648 static int
6649 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6650 {
6651   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6652   int pos = exact_log2 (m & -m);
6653   int len = 0;
6654
6655   if (pos >= 0)
6656     /* Now shift off the low-order zero bits and see if we have a
6657        power of two minus 1.  */
6658     len = exact_log2 ((m >> pos) + 1);
6659
6660   if (len <= 0)
6661     pos = -1;
6662
6663   *plen = len;
6664   return pos;
6665 }
6666 \f
6667 /* If X refers to a register that equals REG in value, replace these
6668    references with REG.  */
6669 static rtx
6670 canon_reg_for_combine (rtx x, rtx reg)
6671 {
6672   rtx op0, op1, op2;
6673   const char *fmt;
6674   int i;
6675   bool copied;
6676
6677   enum rtx_code code = GET_CODE (x);
6678   switch (GET_RTX_CLASS (code))
6679     {
6680     case RTX_UNARY:
6681       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6682       if (op0 != XEXP (x, 0))
6683         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6684                                    GET_MODE (reg));
6685       break;
6686
6687     case RTX_BIN_ARITH:
6688     case RTX_COMM_ARITH:
6689       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6690       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6691       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6692         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6693       break;
6694
6695     case RTX_COMPARE:
6696     case RTX_COMM_COMPARE:
6697       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6698       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6699       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6700         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6701                                         GET_MODE (op0), op0, op1);
6702       break;
6703
6704     case RTX_TERNARY:
6705     case RTX_BITFIELD_OPS:
6706       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6707       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6708       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6709       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6710         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6711                                      GET_MODE (op0), op0, op1, op2);
6712
6713     case RTX_OBJ:
6714       if (REG_P (x))
6715         {
6716           if (rtx_equal_p (get_last_value (reg), x)
6717               || rtx_equal_p (reg, get_last_value (x)))
6718             return reg;
6719           else
6720             break;
6721         }
6722
6723       /* fall through */
6724
6725     default:
6726       fmt = GET_RTX_FORMAT (code);
6727       copied = false;
6728       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6729         if (fmt[i] == 'e')
6730           {
6731             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6732             if (op != XEXP (x, i))
6733               {
6734                 if (!copied)
6735                   {
6736                     copied = true;
6737                     x = copy_rtx (x);
6738                   }
6739                 XEXP (x, i) = op;
6740               }
6741           }
6742         else if (fmt[i] == 'E')
6743           {
6744             int j;
6745             for (j = 0; j < XVECLEN (x, i); j++)
6746               {
6747                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6748                 if (op != XVECEXP (x, i, j))
6749                   {
6750                     if (!copied)
6751                       {
6752                         copied = true;
6753                         x = copy_rtx (x);
6754                       }
6755                     XVECEXP (x, i, j) = op;
6756                   }
6757               }
6758           }
6759
6760       break;
6761     }
6762
6763   return x;
6764 }
6765
6766 /* Return X converted to MODE.  If the value is already truncated to
6767    MODE we can just return a subreg even though in the general case we
6768    would need an explicit truncation.  */
6769
6770 static rtx
6771 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6772 {
6773   if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6774       || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6775                                 GET_MODE_BITSIZE (GET_MODE (x)))
6776       || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6777     return gen_lowpart (mode, x);
6778   else
6779     return gen_rtx_TRUNCATE (mode, x);
6780 }
6781
6782 /* See if X can be simplified knowing that we will only refer to it in
6783    MODE and will only refer to those bits that are nonzero in MASK.
6784    If other bits are being computed or if masking operations are done
6785    that select a superset of the bits in MASK, they can sometimes be
6786    ignored.
6787
6788    Return a possibly simplified expression, but always convert X to
6789    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6790
6791    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6792    are all off in X.  This is used when X will be complemented, by either
6793    NOT, NEG, or XOR.  */
6794
6795 static rtx
6796 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6797                int just_select)
6798 {
6799   enum rtx_code code = GET_CODE (x);
6800   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6801   enum machine_mode op_mode;
6802   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6803   rtx op0, op1, temp;
6804
6805   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6806      code below will do the wrong thing since the mode of such an
6807      expression is VOIDmode.
6808
6809      Also do nothing if X is a CLOBBER; this can happen if X was
6810      the return value from a call to gen_lowpart.  */
6811   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6812     return x;
6813
6814   /* We want to perform the operation is its present mode unless we know
6815      that the operation is valid in MODE, in which case we do the operation
6816      in MODE.  */
6817   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6818               && have_insn_for (code, mode))
6819              ? mode : GET_MODE (x));
6820
6821   /* It is not valid to do a right-shift in a narrower mode
6822      than the one it came in with.  */
6823   if ((code == LSHIFTRT || code == ASHIFTRT)
6824       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6825     op_mode = GET_MODE (x);
6826
6827   /* Truncate MASK to fit OP_MODE.  */
6828   if (op_mode)
6829     mask &= GET_MODE_MASK (op_mode);
6830
6831   /* When we have an arithmetic operation, or a shift whose count we
6832      do not know, we need to assume that all bits up to the highest-order
6833      bit in MASK will be needed.  This is how we form such a mask.  */
6834   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6835     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6836   else
6837     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6838                    - 1);
6839
6840   /* Determine what bits of X are guaranteed to be (non)zero.  */
6841   nonzero = nonzero_bits (x, mode);
6842
6843   /* If none of the bits in X are needed, return a zero.  */
6844   if (! just_select && (nonzero & mask) == 0)
6845     x = const0_rtx;
6846
6847   /* If X is a CONST_INT, return a new one.  Do this here since the
6848      test below will fail.  */
6849   if (GET_CODE (x) == CONST_INT)
6850     {
6851       if (SCALAR_INT_MODE_P (mode))
6852         return gen_int_mode (INTVAL (x) & mask, mode);
6853       else
6854         {
6855           x = GEN_INT (INTVAL (x) & mask);
6856           return gen_lowpart_common (mode, x);
6857         }
6858     }
6859
6860   /* If X is narrower than MODE and we want all the bits in X's mode, just
6861      get X in the proper mode.  */
6862   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6863       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6864     return gen_lowpart (mode, x);
6865
6866   switch (code)
6867     {
6868     case CLOBBER:
6869       /* If X is a (clobber (const_int)), return it since we know we are
6870          generating something that won't match.  */
6871       return x;
6872
6873     case SIGN_EXTEND:
6874     case ZERO_EXTEND:
6875     case ZERO_EXTRACT:
6876     case SIGN_EXTRACT:
6877       x = expand_compound_operation (x);
6878       if (GET_CODE (x) != code)
6879         return force_to_mode (x, mode, mask, next_select);
6880       break;
6881
6882     case SUBREG:
6883       if (subreg_lowpart_p (x)
6884           /* We can ignore the effect of this SUBREG if it narrows the mode or
6885              if the constant masks to zero all the bits the mode doesn't
6886              have.  */
6887           && ((GET_MODE_SIZE (GET_MODE (x))
6888                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6889               || (0 == (mask
6890                         & GET_MODE_MASK (GET_MODE (x))
6891                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6892         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6893       break;
6894
6895     case AND:
6896       /* If this is an AND with a constant, convert it into an AND
6897          whose constant is the AND of that constant with MASK.  If it
6898          remains an AND of MASK, delete it since it is redundant.  */
6899
6900       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6901         {
6902           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6903                                       mask & INTVAL (XEXP (x, 1)));
6904
6905           /* If X is still an AND, see if it is an AND with a mask that
6906              is just some low-order bits.  If so, and it is MASK, we don't
6907              need it.  */
6908
6909           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6910               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6911                   == mask))
6912             x = XEXP (x, 0);
6913
6914           /* If it remains an AND, try making another AND with the bits
6915              in the mode mask that aren't in MASK turned on.  If the
6916              constant in the AND is wide enough, this might make a
6917              cheaper constant.  */
6918
6919           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6920               && GET_MODE_MASK (GET_MODE (x)) != mask
6921               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6922             {
6923               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6924                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6925               int width = GET_MODE_BITSIZE (GET_MODE (x));
6926               rtx y;
6927
6928               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6929                  number, sign extend it.  */
6930               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6931                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6932                 cval |= (HOST_WIDE_INT) -1 << width;
6933
6934               y = simplify_gen_binary (AND, GET_MODE (x),
6935                                        XEXP (x, 0), GEN_INT (cval));
6936               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6937                 x = y;
6938             }
6939
6940           break;
6941         }
6942
6943       goto binop;
6944
6945     case PLUS:
6946       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6947          low-order bits (as in an alignment operation) and FOO is already
6948          aligned to that boundary, mask C1 to that boundary as well.
6949          This may eliminate that PLUS and, later, the AND.  */
6950
6951       {
6952         unsigned int width = GET_MODE_BITSIZE (mode);
6953         unsigned HOST_WIDE_INT smask = mask;
6954
6955         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6956            number, sign extend it.  */
6957
6958         if (width < HOST_BITS_PER_WIDE_INT
6959             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6960           smask |= (HOST_WIDE_INT) -1 << width;
6961
6962         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6963             && exact_log2 (- smask) >= 0
6964             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6965             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6966           return force_to_mode (plus_constant (XEXP (x, 0),
6967                                                (INTVAL (XEXP (x, 1)) & smask)),
6968                                 mode, smask, next_select);
6969       }
6970
6971       /* ... fall through ...  */
6972
6973     case MULT:
6974       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6975          most significant bit in MASK since carries from those bits will
6976          affect the bits we are interested in.  */
6977       mask = fuller_mask;
6978       goto binop;
6979
6980     case MINUS:
6981       /* If X is (minus C Y) where C's least set bit is larger than any bit
6982          in the mask, then we may replace with (neg Y).  */
6983       if (GET_CODE (XEXP (x, 0)) == CONST_INT
6984           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6985                                         & -INTVAL (XEXP (x, 0))))
6986               > mask))
6987         {
6988           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6989                                   GET_MODE (x));
6990           return force_to_mode (x, mode, mask, next_select);
6991         }
6992
6993       /* Similarly, if C contains every bit in the fuller_mask, then we may
6994          replace with (not Y).  */
6995       if (GET_CODE (XEXP (x, 0)) == CONST_INT
6996           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6997               == INTVAL (XEXP (x, 0))))
6998         {
6999           x = simplify_gen_unary (NOT, GET_MODE (x),
7000                                   XEXP (x, 1), GET_MODE (x));
7001           return force_to_mode (x, mode, mask, next_select);
7002         }
7003
7004       mask = fuller_mask;
7005       goto binop;
7006
7007     case IOR:
7008     case XOR:
7009       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7010          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7011          operation which may be a bitfield extraction.  Ensure that the
7012          constant we form is not wider than the mode of X.  */
7013
7014       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7015           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7016           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7017           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7018           && GET_CODE (XEXP (x, 1)) == CONST_INT
7019           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7020                + floor_log2 (INTVAL (XEXP (x, 1))))
7021               < GET_MODE_BITSIZE (GET_MODE (x)))
7022           && (INTVAL (XEXP (x, 1))
7023               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7024         {
7025           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7026                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7027           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7028                                       XEXP (XEXP (x, 0), 0), temp);
7029           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7030                                    XEXP (XEXP (x, 0), 1));
7031           return force_to_mode (x, mode, mask, next_select);
7032         }
7033
7034     binop:
7035       /* For most binary operations, just propagate into the operation and
7036          change the mode if we have an operation of that mode.  */
7037
7038       op0 = gen_lowpart_or_truncate (op_mode,
7039                                      force_to_mode (XEXP (x, 0), mode, mask,
7040                                                     next_select));
7041       op1 = gen_lowpart_or_truncate (op_mode,
7042                                      force_to_mode (XEXP (x, 1), mode, mask,
7043                                         next_select));
7044
7045       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7046         x = simplify_gen_binary (code, op_mode, op0, op1);
7047       break;
7048
7049     case ASHIFT:
7050       /* For left shifts, do the same, but just for the first operand.
7051          However, we cannot do anything with shifts where we cannot
7052          guarantee that the counts are smaller than the size of the mode
7053          because such a count will have a different meaning in a
7054          wider mode.  */
7055
7056       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7057              && INTVAL (XEXP (x, 1)) >= 0
7058              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7059           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7060                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7061                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7062         break;
7063
7064       /* If the shift count is a constant and we can do arithmetic in
7065          the mode of the shift, refine which bits we need.  Otherwise, use the
7066          conservative form of the mask.  */
7067       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7068           && INTVAL (XEXP (x, 1)) >= 0
7069           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7070           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7071         mask >>= INTVAL (XEXP (x, 1));
7072       else
7073         mask = fuller_mask;
7074
7075       op0 = gen_lowpart_or_truncate (op_mode,
7076                                      force_to_mode (XEXP (x, 0), op_mode,
7077                                                     mask, next_select));
7078
7079       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7080         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7081       break;
7082
7083     case LSHIFTRT:
7084       /* Here we can only do something if the shift count is a constant,
7085          this shift constant is valid for the host, and we can do arithmetic
7086          in OP_MODE.  */
7087
7088       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7089           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7090           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7091         {
7092           rtx inner = XEXP (x, 0);
7093           unsigned HOST_WIDE_INT inner_mask;
7094
7095           /* Select the mask of the bits we need for the shift operand.  */
7096           inner_mask = mask << INTVAL (XEXP (x, 1));
7097
7098           /* We can only change the mode of the shift if we can do arithmetic
7099              in the mode of the shift and INNER_MASK is no wider than the
7100              width of X's mode.  */
7101           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7102             op_mode = GET_MODE (x);
7103
7104           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7105
7106           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7107             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7108         }
7109
7110       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7111          shift and AND produces only copies of the sign bit (C2 is one less
7112          than a power of two), we can do this with just a shift.  */
7113
7114       if (GET_CODE (x) == LSHIFTRT
7115           && GET_CODE (XEXP (x, 1)) == CONST_INT
7116           /* The shift puts one of the sign bit copies in the least significant
7117              bit.  */
7118           && ((INTVAL (XEXP (x, 1))
7119                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7120               >= GET_MODE_BITSIZE (GET_MODE (x)))
7121           && exact_log2 (mask + 1) >= 0
7122           /* Number of bits left after the shift must be more than the mask
7123              needs.  */
7124           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7125               <= GET_MODE_BITSIZE (GET_MODE (x)))
7126           /* Must be more sign bit copies than the mask needs.  */
7127           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7128               >= exact_log2 (mask + 1)))
7129         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7130                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7131                                           - exact_log2 (mask + 1)));
7132
7133       goto shiftrt;
7134
7135     case ASHIFTRT:
7136       /* If we are just looking for the sign bit, we don't need this shift at
7137          all, even if it has a variable count.  */
7138       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7139           && (mask == ((unsigned HOST_WIDE_INT) 1
7140                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7141         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7142
7143       /* If this is a shift by a constant, get a mask that contains those bits
7144          that are not copies of the sign bit.  We then have two cases:  If
7145          MASK only includes those bits, this can be a logical shift, which may
7146          allow simplifications.  If MASK is a single-bit field not within
7147          those bits, we are requesting a copy of the sign bit and hence can
7148          shift the sign bit to the appropriate location.  */
7149
7150       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7151           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7152         {
7153           int i;
7154
7155           /* If the considered data is wider than HOST_WIDE_INT, we can't
7156              represent a mask for all its bits in a single scalar.
7157              But we only care about the lower bits, so calculate these.  */
7158
7159           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7160             {
7161               nonzero = ~(HOST_WIDE_INT) 0;
7162
7163               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7164                  is the number of bits a full-width mask would have set.
7165                  We need only shift if these are fewer than nonzero can
7166                  hold.  If not, we must keep all bits set in nonzero.  */
7167
7168               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7169                   < HOST_BITS_PER_WIDE_INT)
7170                 nonzero >>= INTVAL (XEXP (x, 1))
7171                             + HOST_BITS_PER_WIDE_INT
7172                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7173             }
7174           else
7175             {
7176               nonzero = GET_MODE_MASK (GET_MODE (x));
7177               nonzero >>= INTVAL (XEXP (x, 1));
7178             }
7179
7180           if ((mask & ~nonzero) == 0)
7181             {
7182               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7183                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7184               if (GET_CODE (x) != ASHIFTRT)
7185                 return force_to_mode (x, mode, mask, next_select);
7186             }
7187
7188           else if ((i = exact_log2 (mask)) >= 0)
7189             {
7190               x = simplify_shift_const
7191                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7192                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7193
7194               if (GET_CODE (x) != ASHIFTRT)
7195                 return force_to_mode (x, mode, mask, next_select);
7196             }
7197         }
7198
7199       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7200          even if the shift count isn't a constant.  */
7201       if (mask == 1)
7202         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7203                                  XEXP (x, 0), XEXP (x, 1));
7204
7205     shiftrt:
7206
7207       /* If this is a zero- or sign-extension operation that just affects bits
7208          we don't care about, remove it.  Be sure the call above returned
7209          something that is still a shift.  */
7210
7211       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7212           && GET_CODE (XEXP (x, 1)) == CONST_INT
7213           && INTVAL (XEXP (x, 1)) >= 0
7214           && (INTVAL (XEXP (x, 1))
7215               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7216           && GET_CODE (XEXP (x, 0)) == ASHIFT
7217           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7218         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7219                               next_select);
7220
7221       break;
7222
7223     case ROTATE:
7224     case ROTATERT:
7225       /* If the shift count is constant and we can do computations
7226          in the mode of X, compute where the bits we care about are.
7227          Otherwise, we can't do anything.  Don't change the mode of
7228          the shift or propagate MODE into the shift, though.  */
7229       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7230           && INTVAL (XEXP (x, 1)) >= 0)
7231         {
7232           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7233                                             GET_MODE (x), GEN_INT (mask),
7234                                             XEXP (x, 1));
7235           if (temp && GET_CODE (temp) == CONST_INT)
7236             SUBST (XEXP (x, 0),
7237                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7238                                   INTVAL (temp), next_select));
7239         }
7240       break;
7241
7242     case NEG:
7243       /* If we just want the low-order bit, the NEG isn't needed since it
7244          won't change the low-order bit.  */
7245       if (mask == 1)
7246         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7247
7248       /* We need any bits less significant than the most significant bit in
7249          MASK since carries from those bits will affect the bits we are
7250          interested in.  */
7251       mask = fuller_mask;
7252       goto unop;
7253
7254     case NOT:
7255       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7256          same as the XOR case above.  Ensure that the constant we form is not
7257          wider than the mode of X.  */
7258
7259       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7260           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7261           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7262           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7263               < GET_MODE_BITSIZE (GET_MODE (x)))
7264           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7265         {
7266           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7267                                GET_MODE (x));
7268           temp = simplify_gen_binary (XOR, GET_MODE (x),
7269                                       XEXP (XEXP (x, 0), 0), temp);
7270           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7271                                    temp, XEXP (XEXP (x, 0), 1));
7272
7273           return force_to_mode (x, mode, mask, next_select);
7274         }
7275
7276       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7277          use the full mask inside the NOT.  */
7278       mask = fuller_mask;
7279
7280     unop:
7281       op0 = gen_lowpart_or_truncate (op_mode,
7282                                      force_to_mode (XEXP (x, 0), mode, mask,
7283                                                     next_select));
7284       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7285         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7286       break;
7287
7288     case NE:
7289       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7290          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7291          which is equal to STORE_FLAG_VALUE.  */
7292       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7293           && GET_MODE (XEXP (x, 0)) == mode
7294           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7295           && (nonzero_bits (XEXP (x, 0), mode)
7296               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7297         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7298
7299       break;
7300
7301     case IF_THEN_ELSE:
7302       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7303          written in a narrower mode.  We play it safe and do not do so.  */
7304
7305       SUBST (XEXP (x, 1),
7306              gen_lowpart_or_truncate (GET_MODE (x),
7307                                       force_to_mode (XEXP (x, 1), mode,
7308                                                      mask, next_select)));
7309       SUBST (XEXP (x, 2),
7310              gen_lowpart_or_truncate (GET_MODE (x),
7311                                       force_to_mode (XEXP (x, 2), mode,
7312                                                      mask, next_select)));
7313       break;
7314
7315     default:
7316       break;
7317     }
7318
7319   /* Ensure we return a value of the proper mode.  */
7320   return gen_lowpart_or_truncate (mode, x);
7321 }
7322 \f
7323 /* Return nonzero if X is an expression that has one of two values depending on
7324    whether some other value is zero or nonzero.  In that case, we return the
7325    value that is being tested, *PTRUE is set to the value if the rtx being
7326    returned has a nonzero value, and *PFALSE is set to the other alternative.
7327
7328    If we return zero, we set *PTRUE and *PFALSE to X.  */
7329
7330 static rtx
7331 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7332 {
7333   enum machine_mode mode = GET_MODE (x);
7334   enum rtx_code code = GET_CODE (x);
7335   rtx cond0, cond1, true0, true1, false0, false1;
7336   unsigned HOST_WIDE_INT nz;
7337
7338   /* If we are comparing a value against zero, we are done.  */
7339   if ((code == NE || code == EQ)
7340       && XEXP (x, 1) == const0_rtx)
7341     {
7342       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7343       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7344       return XEXP (x, 0);
7345     }
7346
7347   /* If this is a unary operation whose operand has one of two values, apply
7348      our opcode to compute those values.  */
7349   else if (UNARY_P (x)
7350            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7351     {
7352       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7353       *pfalse = simplify_gen_unary (code, mode, false0,
7354                                     GET_MODE (XEXP (x, 0)));
7355       return cond0;
7356     }
7357
7358   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7359      make can't possibly match and would suppress other optimizations.  */
7360   else if (code == COMPARE)
7361     ;
7362
7363   /* If this is a binary operation, see if either side has only one of two
7364      values.  If either one does or if both do and they are conditional on
7365      the same value, compute the new true and false values.  */
7366   else if (BINARY_P (x))
7367     {
7368       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7369       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7370
7371       if ((cond0 != 0 || cond1 != 0)
7372           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7373         {
7374           /* If if_then_else_cond returned zero, then true/false are the
7375              same rtl.  We must copy one of them to prevent invalid rtl
7376              sharing.  */
7377           if (cond0 == 0)
7378             true0 = copy_rtx (true0);
7379           else if (cond1 == 0)
7380             true1 = copy_rtx (true1);
7381
7382           if (COMPARISON_P (x))
7383             {
7384               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7385                                                 true0, true1);
7386               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7387                                                  false0, false1);
7388              }
7389           else
7390             {
7391               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7392               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7393             }
7394
7395           return cond0 ? cond0 : cond1;
7396         }
7397
7398       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7399          operands is zero when the other is nonzero, and vice-versa,
7400          and STORE_FLAG_VALUE is 1 or -1.  */
7401
7402       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7403           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7404               || code == UMAX)
7405           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7406         {
7407           rtx op0 = XEXP (XEXP (x, 0), 1);
7408           rtx op1 = XEXP (XEXP (x, 1), 1);
7409
7410           cond0 = XEXP (XEXP (x, 0), 0);
7411           cond1 = XEXP (XEXP (x, 1), 0);
7412
7413           if (COMPARISON_P (cond0)
7414               && COMPARISON_P (cond1)
7415               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7416                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7417                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7418                   || ((swap_condition (GET_CODE (cond0))
7419                        == reversed_comparison_code (cond1, NULL))
7420                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7421                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7422               && ! side_effects_p (x))
7423             {
7424               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7425               *pfalse = simplify_gen_binary (MULT, mode,
7426                                              (code == MINUS
7427                                               ? simplify_gen_unary (NEG, mode,
7428                                                                     op1, mode)
7429                                               : op1),
7430                                               const_true_rtx);
7431               return cond0;
7432             }
7433         }
7434
7435       /* Similarly for MULT, AND and UMIN, except that for these the result
7436          is always zero.  */
7437       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7438           && (code == MULT || code == AND || code == UMIN)
7439           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7440         {
7441           cond0 = XEXP (XEXP (x, 0), 0);
7442           cond1 = XEXP (XEXP (x, 1), 0);
7443
7444           if (COMPARISON_P (cond0)
7445               && COMPARISON_P (cond1)
7446               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7447                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7448                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7449                   || ((swap_condition (GET_CODE (cond0))
7450                        == reversed_comparison_code (cond1, NULL))
7451                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7452                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7453               && ! side_effects_p (x))
7454             {
7455               *ptrue = *pfalse = const0_rtx;
7456               return cond0;
7457             }
7458         }
7459     }
7460
7461   else if (code == IF_THEN_ELSE)
7462     {
7463       /* If we have IF_THEN_ELSE already, extract the condition and
7464          canonicalize it if it is NE or EQ.  */
7465       cond0 = XEXP (x, 0);
7466       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7467       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7468         return XEXP (cond0, 0);
7469       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7470         {
7471           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7472           return XEXP (cond0, 0);
7473         }
7474       else
7475         return cond0;
7476     }
7477
7478   /* If X is a SUBREG, we can narrow both the true and false values
7479      if the inner expression, if there is a condition.  */
7480   else if (code == SUBREG
7481            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7482                                                &true0, &false0)))
7483     {
7484       true0 = simplify_gen_subreg (mode, true0,
7485                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7486       false0 = simplify_gen_subreg (mode, false0,
7487                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7488       if (true0 && false0)
7489         {
7490           *ptrue = true0;
7491           *pfalse = false0;
7492           return cond0;
7493         }
7494     }
7495
7496   /* If X is a constant, this isn't special and will cause confusions
7497      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7498   else if (CONSTANT_P (x)
7499            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7500     ;
7501
7502   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7503      will be least confusing to the rest of the compiler.  */
7504   else if (mode == BImode)
7505     {
7506       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7507       return x;
7508     }
7509
7510   /* If X is known to be either 0 or -1, those are the true and
7511      false values when testing X.  */
7512   else if (x == constm1_rtx || x == const0_rtx
7513            || (mode != VOIDmode
7514                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7515     {
7516       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7517       return x;
7518     }
7519
7520   /* Likewise for 0 or a single bit.  */
7521   else if (SCALAR_INT_MODE_P (mode)
7522            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7523            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7524     {
7525       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7526       return x;
7527     }
7528
7529   /* Otherwise fail; show no condition with true and false values the same.  */
7530   *ptrue = *pfalse = x;
7531   return 0;
7532 }
7533 \f
7534 /* Return the value of expression X given the fact that condition COND
7535    is known to be true when applied to REG as its first operand and VAL
7536    as its second.  X is known to not be shared and so can be modified in
7537    place.
7538
7539    We only handle the simplest cases, and specifically those cases that
7540    arise with IF_THEN_ELSE expressions.  */
7541
7542 static rtx
7543 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7544 {
7545   enum rtx_code code = GET_CODE (x);
7546   rtx temp;
7547   const char *fmt;
7548   int i, j;
7549
7550   if (side_effects_p (x))
7551     return x;
7552
7553   /* If either operand of the condition is a floating point value,
7554      then we have to avoid collapsing an EQ comparison.  */
7555   if (cond == EQ
7556       && rtx_equal_p (x, reg)
7557       && ! FLOAT_MODE_P (GET_MODE (x))
7558       && ! FLOAT_MODE_P (GET_MODE (val)))
7559     return val;
7560
7561   if (cond == UNEQ && rtx_equal_p (x, reg))
7562     return val;
7563
7564   /* If X is (abs REG) and we know something about REG's relationship
7565      with zero, we may be able to simplify this.  */
7566
7567   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7568     switch (cond)
7569       {
7570       case GE:  case GT:  case EQ:
7571         return XEXP (x, 0);
7572       case LT:  case LE:
7573         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7574                                    XEXP (x, 0),
7575                                    GET_MODE (XEXP (x, 0)));
7576       default:
7577         break;
7578       }
7579
7580   /* The only other cases we handle are MIN, MAX, and comparisons if the
7581      operands are the same as REG and VAL.  */
7582
7583   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7584     {
7585       if (rtx_equal_p (XEXP (x, 0), val))
7586         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7587
7588       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7589         {
7590           if (COMPARISON_P (x))
7591             {
7592               if (comparison_dominates_p (cond, code))
7593                 return const_true_rtx;
7594
7595               code = reversed_comparison_code (x, NULL);
7596               if (code != UNKNOWN
7597                   && comparison_dominates_p (cond, code))
7598                 return const0_rtx;
7599               else
7600                 return x;
7601             }
7602           else if (code == SMAX || code == SMIN
7603                    || code == UMIN || code == UMAX)
7604             {
7605               int unsignedp = (code == UMIN || code == UMAX);
7606
7607               /* Do not reverse the condition when it is NE or EQ.
7608                  This is because we cannot conclude anything about
7609                  the value of 'SMAX (x, y)' when x is not equal to y,
7610                  but we can when x equals y.  */
7611               if ((code == SMAX || code == UMAX)
7612                   && ! (cond == EQ || cond == NE))
7613                 cond = reverse_condition (cond);
7614
7615               switch (cond)
7616                 {
7617                 case GE:   case GT:
7618                   return unsignedp ? x : XEXP (x, 1);
7619                 case LE:   case LT:
7620                   return unsignedp ? x : XEXP (x, 0);
7621                 case GEU:  case GTU:
7622                   return unsignedp ? XEXP (x, 1) : x;
7623                 case LEU:  case LTU:
7624                   return unsignedp ? XEXP (x, 0) : x;
7625                 default:
7626                   break;
7627                 }
7628             }
7629         }
7630     }
7631   else if (code == SUBREG)
7632     {
7633       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7634       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7635
7636       if (SUBREG_REG (x) != r)
7637         {
7638           /* We must simplify subreg here, before we lose track of the
7639              original inner_mode.  */
7640           new = simplify_subreg (GET_MODE (x), r,
7641                                  inner_mode, SUBREG_BYTE (x));
7642           if (new)
7643             return new;
7644           else
7645             SUBST (SUBREG_REG (x), r);
7646         }
7647
7648       return x;
7649     }
7650   /* We don't have to handle SIGN_EXTEND here, because even in the
7651      case of replacing something with a modeless CONST_INT, a
7652      CONST_INT is already (supposed to be) a valid sign extension for
7653      its narrower mode, which implies it's already properly
7654      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7655      story is different.  */
7656   else if (code == ZERO_EXTEND)
7657     {
7658       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7659       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7660
7661       if (XEXP (x, 0) != r)
7662         {
7663           /* We must simplify the zero_extend here, before we lose
7664              track of the original inner_mode.  */
7665           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7666                                           r, inner_mode);
7667           if (new)
7668             return new;
7669           else
7670             SUBST (XEXP (x, 0), r);
7671         }
7672
7673       return x;
7674     }
7675
7676   fmt = GET_RTX_FORMAT (code);
7677   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7678     {
7679       if (fmt[i] == 'e')
7680         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7681       else if (fmt[i] == 'E')
7682         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7683           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7684                                                 cond, reg, val));
7685     }
7686
7687   return x;
7688 }
7689 \f
7690 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7691    assignment as a field assignment.  */
7692
7693 static int
7694 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7695 {
7696   if (x == y || rtx_equal_p (x, y))
7697     return 1;
7698
7699   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7700     return 0;
7701
7702   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7703      Note that all SUBREGs of MEM are paradoxical; otherwise they
7704      would have been rewritten.  */
7705   if (MEM_P (x) && GET_CODE (y) == SUBREG
7706       && MEM_P (SUBREG_REG (y))
7707       && rtx_equal_p (SUBREG_REG (y),
7708                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7709     return 1;
7710
7711   if (MEM_P (y) && GET_CODE (x) == SUBREG
7712       && MEM_P (SUBREG_REG (x))
7713       && rtx_equal_p (SUBREG_REG (x),
7714                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7715     return 1;
7716
7717   /* We used to see if get_last_value of X and Y were the same but that's
7718      not correct.  In one direction, we'll cause the assignment to have
7719      the wrong destination and in the case, we'll import a register into this
7720      insn that might have already have been dead.   So fail if none of the
7721      above cases are true.  */
7722   return 0;
7723 }
7724 \f
7725 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7726    Return that assignment if so.
7727
7728    We only handle the most common cases.  */
7729
7730 static rtx
7731 make_field_assignment (rtx x)
7732 {
7733   rtx dest = SET_DEST (x);
7734   rtx src = SET_SRC (x);
7735   rtx assign;
7736   rtx rhs, lhs;
7737   HOST_WIDE_INT c1;
7738   HOST_WIDE_INT pos;
7739   unsigned HOST_WIDE_INT len;
7740   rtx other;
7741   enum machine_mode mode;
7742
7743   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7744      a clear of a one-bit field.  We will have changed it to
7745      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7746      for a SUBREG.  */
7747
7748   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7749       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7750       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7751       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7752     {
7753       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7754                                 1, 1, 1, 0);
7755       if (assign != 0)
7756         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7757       return x;
7758     }
7759
7760   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7761       && subreg_lowpart_p (XEXP (src, 0))
7762       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7763           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7764       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7765       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7766       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7767       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7768     {
7769       assign = make_extraction (VOIDmode, dest, 0,
7770                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7771                                 1, 1, 1, 0);
7772       if (assign != 0)
7773         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7774       return x;
7775     }
7776
7777   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7778      one-bit field.  */
7779   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7780       && XEXP (XEXP (src, 0), 0) == const1_rtx
7781       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7782     {
7783       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7784                                 1, 1, 1, 0);
7785       if (assign != 0)
7786         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7787       return x;
7788     }
7789
7790   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7791      SRC is an AND with all bits of that field set, then we can discard
7792      the AND.  */
7793   if (GET_CODE (dest) == ZERO_EXTRACT
7794       && GET_CODE (XEXP (dest, 1)) == CONST_INT
7795       && GET_CODE (src) == AND
7796       && GET_CODE (XEXP (src, 1)) == CONST_INT)
7797     {
7798       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7799       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7800       unsigned HOST_WIDE_INT ze_mask;
7801
7802       if (width >= HOST_BITS_PER_WIDE_INT)
7803         ze_mask = -1;
7804       else
7805         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7806
7807       /* Complete overlap.  We can remove the source AND.  */
7808       if ((and_mask & ze_mask) == ze_mask)
7809         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7810
7811       /* Partial overlap.  We can reduce the source AND.  */
7812       if ((and_mask & ze_mask) != and_mask)
7813         {
7814           mode = GET_MODE (src);
7815           src = gen_rtx_AND (mode, XEXP (src, 0),
7816                              gen_int_mode (and_mask & ze_mask, mode));
7817           return gen_rtx_SET (VOIDmode, dest, src);
7818         }
7819     }
7820
7821   /* The other case we handle is assignments into a constant-position
7822      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7823      a mask that has all one bits except for a group of zero bits and
7824      OTHER is known to have zeros where C1 has ones, this is such an
7825      assignment.  Compute the position and length from C1.  Shift OTHER
7826      to the appropriate position, force it to the required mode, and
7827      make the extraction.  Check for the AND in both operands.  */
7828
7829   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7830     return x;
7831
7832   rhs = expand_compound_operation (XEXP (src, 0));
7833   lhs = expand_compound_operation (XEXP (src, 1));
7834
7835   if (GET_CODE (rhs) == AND
7836       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7837       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7838     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7839   else if (GET_CODE (lhs) == AND
7840            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7841            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7842     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7843   else
7844     return x;
7845
7846   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7847   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7848       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7849       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7850     return x;
7851
7852   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7853   if (assign == 0)
7854     return x;
7855
7856   /* The mode to use for the source is the mode of the assignment, or of
7857      what is inside a possible STRICT_LOW_PART.  */
7858   mode = (GET_CODE (assign) == STRICT_LOW_PART
7859           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7860
7861   /* Shift OTHER right POS places and make it the source, restricting it
7862      to the proper length and mode.  */
7863
7864   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7865                                                      GET_MODE (src),
7866                                                      other, pos),
7867                                dest);
7868   src = force_to_mode (src, mode,
7869                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7870                        ? ~(unsigned HOST_WIDE_INT) 0
7871                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7872                        0);
7873
7874   /* If SRC is masked by an AND that does not make a difference in
7875      the value being stored, strip it.  */
7876   if (GET_CODE (assign) == ZERO_EXTRACT
7877       && GET_CODE (XEXP (assign, 1)) == CONST_INT
7878       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7879       && GET_CODE (src) == AND
7880       && GET_CODE (XEXP (src, 1)) == CONST_INT
7881       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7882           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7883     src = XEXP (src, 0);
7884
7885   return gen_rtx_SET (VOIDmode, assign, src);
7886 }
7887 \f
7888 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7889    if so.  */
7890
7891 static rtx
7892 apply_distributive_law (rtx x)
7893 {
7894   enum rtx_code code = GET_CODE (x);
7895   enum rtx_code inner_code;
7896   rtx lhs, rhs, other;
7897   rtx tem;
7898
7899   /* Distributivity is not true for floating point as it can change the
7900      value.  So we don't do it unless -funsafe-math-optimizations.  */
7901   if (FLOAT_MODE_P (GET_MODE (x))
7902       && ! flag_unsafe_math_optimizations)
7903     return x;
7904
7905   /* The outer operation can only be one of the following:  */
7906   if (code != IOR && code != AND && code != XOR
7907       && code != PLUS && code != MINUS)
7908     return x;
7909
7910   lhs = XEXP (x, 0);
7911   rhs = XEXP (x, 1);
7912
7913   /* If either operand is a primitive we can't do anything, so get out
7914      fast.  */
7915   if (OBJECT_P (lhs) || OBJECT_P (rhs))
7916     return x;
7917
7918   lhs = expand_compound_operation (lhs);
7919   rhs = expand_compound_operation (rhs);
7920   inner_code = GET_CODE (lhs);
7921   if (inner_code != GET_CODE (rhs))
7922     return x;
7923
7924   /* See if the inner and outer operations distribute.  */
7925   switch (inner_code)
7926     {
7927     case LSHIFTRT:
7928     case ASHIFTRT:
7929     case AND:
7930     case IOR:
7931       /* These all distribute except over PLUS.  */
7932       if (code == PLUS || code == MINUS)
7933         return x;
7934       break;
7935
7936     case MULT:
7937       if (code != PLUS && code != MINUS)
7938         return x;
7939       break;
7940
7941     case ASHIFT:
7942       /* This is also a multiply, so it distributes over everything.  */
7943       break;
7944
7945     case SUBREG:
7946       /* Non-paradoxical SUBREGs distributes over all operations,
7947          provided the inner modes and byte offsets are the same, this
7948          is an extraction of a low-order part, we don't convert an fp
7949          operation to int or vice versa, this is not a vector mode,
7950          and we would not be converting a single-word operation into a
7951          multi-word operation.  The latter test is not required, but
7952          it prevents generating unneeded multi-word operations.  Some
7953          of the previous tests are redundant given the latter test,
7954          but are retained because they are required for correctness.
7955
7956          We produce the result slightly differently in this case.  */
7957
7958       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7959           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7960           || ! subreg_lowpart_p (lhs)
7961           || (GET_MODE_CLASS (GET_MODE (lhs))
7962               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7963           || (GET_MODE_SIZE (GET_MODE (lhs))
7964               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7965           || VECTOR_MODE_P (GET_MODE (lhs))
7966           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7967           /* Result might need to be truncated.  Don't change mode if
7968              explicit truncation is needed.  */
7969           || !TRULY_NOOP_TRUNCATION
7970                (GET_MODE_BITSIZE (GET_MODE (x)),
7971                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7972         return x;
7973
7974       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7975                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
7976       return gen_lowpart (GET_MODE (x), tem);
7977
7978     default:
7979       return x;
7980     }
7981
7982   /* Set LHS and RHS to the inner operands (A and B in the example
7983      above) and set OTHER to the common operand (C in the example).
7984      There is only one way to do this unless the inner operation is
7985      commutative.  */
7986   if (COMMUTATIVE_ARITH_P (lhs)
7987       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7988     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7989   else if (COMMUTATIVE_ARITH_P (lhs)
7990            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7991     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7992   else if (COMMUTATIVE_ARITH_P (lhs)
7993            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7994     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7995   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7996     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7997   else
7998     return x;
7999
8000   /* Form the new inner operation, seeing if it simplifies first.  */
8001   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8002
8003   /* There is one exception to the general way of distributing:
8004      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8005   if (code == XOR && inner_code == IOR)
8006     {
8007       inner_code = AND;
8008       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8009     }
8010
8011   /* We may be able to continuing distributing the result, so call
8012      ourselves recursively on the inner operation before forming the
8013      outer operation, which we return.  */
8014   return simplify_gen_binary (inner_code, GET_MODE (x),
8015                               apply_distributive_law (tem), other);
8016 }
8017
8018 /* See if X is of the form (* (+ A B) C), and if so convert to
8019    (+ (* A C) (* B C)) and try to simplify.
8020
8021    Most of the time, this results in no change.  However, if some of
8022    the operands are the same or inverses of each other, simplifications
8023    will result.
8024
8025    For example, (and (ior A B) (not B)) can occur as the result of
8026    expanding a bit field assignment.  When we apply the distributive
8027    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8028    which then simplifies to (and (A (not B))).
8029
8030    Note that no checks happen on the validity of applying the inverse
8031    distributive law.  This is pointless since we can do it in the
8032    few places where this routine is called.
8033
8034    N is the index of the term that is decomposed (the arithmetic operation,
8035    i.e. (+ A B) in the first example above).  !N is the index of the term that
8036    is distributed, i.e. of C in the first example above.  */
8037 static rtx
8038 distribute_and_simplify_rtx (rtx x, int n)
8039 {
8040   enum machine_mode mode;
8041   enum rtx_code outer_code, inner_code;
8042   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8043
8044   decomposed = XEXP (x, n);
8045   if (!ARITHMETIC_P (decomposed))
8046     return NULL_RTX;
8047
8048   mode = GET_MODE (x);
8049   outer_code = GET_CODE (x);
8050   distributed = XEXP (x, !n);
8051
8052   inner_code = GET_CODE (decomposed);
8053   inner_op0 = XEXP (decomposed, 0);
8054   inner_op1 = XEXP (decomposed, 1);
8055
8056   /* Special case (and (xor B C) (not A)), which is equivalent to
8057      (xor (ior A B) (ior A C))  */
8058   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8059     {
8060       distributed = XEXP (distributed, 0);
8061       outer_code = IOR;
8062     }
8063
8064   if (n == 0)
8065     {
8066       /* Distribute the second term.  */
8067       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8068       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8069     }
8070   else
8071     {
8072       /* Distribute the first term.  */
8073       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8074       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8075     }
8076
8077   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8078                                                      new_op0, new_op1));
8079   if (GET_CODE (tmp) != outer_code
8080       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8081     return tmp;
8082
8083   return NULL_RTX;
8084 }
8085 \f
8086 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8087    in MODE.  Return an equivalent form, if different from (and VAROP
8088    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8089
8090 static rtx
8091 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8092                           unsigned HOST_WIDE_INT constop)
8093 {
8094   unsigned HOST_WIDE_INT nonzero;
8095   unsigned HOST_WIDE_INT orig_constop;
8096   rtx orig_varop;
8097   int i;
8098
8099   orig_varop = varop;
8100   orig_constop = constop;
8101   if (GET_CODE (varop) == CLOBBER)
8102     return NULL_RTX;
8103
8104   /* Simplify VAROP knowing that we will be only looking at some of the
8105      bits in it.
8106
8107      Note by passing in CONSTOP, we guarantee that the bits not set in
8108      CONSTOP are not significant and will never be examined.  We must
8109      ensure that is the case by explicitly masking out those bits
8110      before returning.  */
8111   varop = force_to_mode (varop, mode, constop, 0);
8112
8113   /* If VAROP is a CLOBBER, we will fail so return it.  */
8114   if (GET_CODE (varop) == CLOBBER)
8115     return varop;
8116
8117   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8118      to VAROP and return the new constant.  */
8119   if (GET_CODE (varop) == CONST_INT)
8120     return gen_int_mode (INTVAL (varop) & constop, mode);
8121
8122   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8123      a call to nonzero_bits, here we don't care about bits outside
8124      MODE.  */
8125
8126   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8127
8128   /* Turn off all bits in the constant that are known to already be zero.
8129      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8130      which is tested below.  */
8131
8132   constop &= nonzero;
8133
8134   /* If we don't have any bits left, return zero.  */
8135   if (constop == 0)
8136     return const0_rtx;
8137
8138   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8139      a power of two, we can replace this with an ASHIFT.  */
8140   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8141       && (i = exact_log2 (constop)) >= 0)
8142     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8143
8144   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8145      or XOR, then try to apply the distributive law.  This may eliminate
8146      operations if either branch can be simplified because of the AND.
8147      It may also make some cases more complex, but those cases probably
8148      won't match a pattern either with or without this.  */
8149
8150   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8151     return
8152       gen_lowpart
8153         (mode,
8154          apply_distributive_law
8155          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8156                                simplify_and_const_int (NULL_RTX,
8157                                                        GET_MODE (varop),
8158                                                        XEXP (varop, 0),
8159                                                        constop),
8160                                simplify_and_const_int (NULL_RTX,
8161                                                        GET_MODE (varop),
8162                                                        XEXP (varop, 1),
8163                                                        constop))));
8164
8165   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8166      the AND and see if one of the operands simplifies to zero.  If so, we
8167      may eliminate it.  */
8168
8169   if (GET_CODE (varop) == PLUS
8170       && exact_log2 (constop + 1) >= 0)
8171     {
8172       rtx o0, o1;
8173
8174       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8175       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8176       if (o0 == const0_rtx)
8177         return o1;
8178       if (o1 == const0_rtx)
8179         return o0;
8180     }
8181
8182   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8183   varop = gen_lowpart (mode, varop);
8184   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8185     return NULL_RTX;
8186
8187   /* If we are only masking insignificant bits, return VAROP.  */
8188   if (constop == nonzero)
8189     return varop;
8190
8191   if (varop == orig_varop && constop == orig_constop)
8192     return NULL_RTX;
8193
8194   /* Otherwise, return an AND.  */
8195   constop = trunc_int_for_mode (constop, mode);
8196   return simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8197 }
8198
8199
8200 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8201    in MODE.
8202
8203    Return an equivalent form, if different from X.  Otherwise, return X.  If
8204    X is zero, we are to always construct the equivalent form.  */
8205
8206 static rtx
8207 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8208                         unsigned HOST_WIDE_INT constop)
8209 {
8210   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8211   if (tem)
8212     return tem;
8213
8214   if (!x)
8215     x = simplify_gen_binary (AND, GET_MODE (varop), varop, GEN_INT (constop));
8216   if (GET_MODE (x) != mode)
8217     x = gen_lowpart (mode, x);
8218   return x;
8219 }
8220 \f
8221 /* Given a REG, X, compute which bits in X can be nonzero.
8222    We don't care about bits outside of those defined in MODE.
8223
8224    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8225    a shift, AND, or zero_extract, we can do better.  */
8226
8227 static rtx
8228 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8229                               rtx known_x ATTRIBUTE_UNUSED,
8230                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8231                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8232                               unsigned HOST_WIDE_INT *nonzero)
8233 {
8234   rtx tem;
8235
8236   /* If X is a register whose nonzero bits value is current, use it.
8237      Otherwise, if X is a register whose value we can find, use that
8238      value.  Otherwise, use the previously-computed global nonzero bits
8239      for this register.  */
8240
8241   if (reg_stat[REGNO (x)].last_set_value != 0
8242       && (reg_stat[REGNO (x)].last_set_mode == mode
8243           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8244               && GET_MODE_CLASS (mode) == MODE_INT))
8245       && (reg_stat[REGNO (x)].last_set_label == label_tick
8246           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8247               && REG_N_SETS (REGNO (x)) == 1
8248               && ! REGNO_REG_SET_P
8249                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8250                   REGNO (x))))
8251       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8252     {
8253       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8254       return NULL;
8255     }
8256
8257   tem = get_last_value (x);
8258
8259   if (tem)
8260     {
8261 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8262       /* If X is narrower than MODE and TEM is a non-negative
8263          constant that would appear negative in the mode of X,
8264          sign-extend it for use in reg_nonzero_bits because some
8265          machines (maybe most) will actually do the sign-extension
8266          and this is the conservative approach.
8267
8268          ??? For 2.5, try to tighten up the MD files in this regard
8269          instead of this kludge.  */
8270
8271       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8272           && GET_CODE (tem) == CONST_INT
8273           && INTVAL (tem) > 0
8274           && 0 != (INTVAL (tem)
8275                    & ((HOST_WIDE_INT) 1
8276                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8277         tem = GEN_INT (INTVAL (tem)
8278                        | ((HOST_WIDE_INT) (-1)
8279                           << GET_MODE_BITSIZE (GET_MODE (x))));
8280 #endif
8281       return tem;
8282     }
8283   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8284     {
8285       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8286
8287       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8288         /* We don't know anything about the upper bits.  */
8289         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8290       *nonzero &= mask;
8291     }
8292
8293   return NULL;
8294 }
8295
8296 /* Return the number of bits at the high-order end of X that are known to
8297    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8298    VOIDmode, X will be used in its own mode.  The returned value  will always
8299    be between 1 and the number of bits in MODE.  */
8300
8301 static rtx
8302 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8303                                      rtx known_x ATTRIBUTE_UNUSED,
8304                                      enum machine_mode known_mode
8305                                      ATTRIBUTE_UNUSED,
8306                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8307                                      unsigned int *result)
8308 {
8309   rtx tem;
8310
8311   if (reg_stat[REGNO (x)].last_set_value != 0
8312       && reg_stat[REGNO (x)].last_set_mode == mode
8313       && (reg_stat[REGNO (x)].last_set_label == label_tick
8314           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8315               && REG_N_SETS (REGNO (x)) == 1
8316               && ! REGNO_REG_SET_P
8317                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8318                   REGNO (x))))
8319       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8320     {
8321       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8322       return NULL;
8323     }
8324
8325   tem = get_last_value (x);
8326   if (tem != 0)
8327     return tem;
8328
8329   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8330       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8331     *result = reg_stat[REGNO (x)].sign_bit_copies;
8332
8333   return NULL;
8334 }
8335 \f
8336 /* Return the number of "extended" bits there are in X, when interpreted
8337    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8338    unsigned quantities, this is the number of high-order zero bits.
8339    For signed quantities, this is the number of copies of the sign bit
8340    minus 1.  In both case, this function returns the number of "spare"
8341    bits.  For example, if two quantities for which this function returns
8342    at least 1 are added, the addition is known not to overflow.
8343
8344    This function will always return 0 unless called during combine, which
8345    implies that it must be called from a define_split.  */
8346
8347 unsigned int
8348 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8349 {
8350   if (nonzero_sign_valid == 0)
8351     return 0;
8352
8353   return (unsignedp
8354           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8355              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8356                                - floor_log2 (nonzero_bits (x, mode)))
8357              : 0)
8358           : num_sign_bit_copies (x, mode) - 1);
8359 }
8360 \f
8361 /* This function is called from `simplify_shift_const' to merge two
8362    outer operations.  Specifically, we have already found that we need
8363    to perform operation *POP0 with constant *PCONST0 at the outermost
8364    position.  We would now like to also perform OP1 with constant CONST1
8365    (with *POP0 being done last).
8366
8367    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8368    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8369    complement the innermost operand, otherwise it is unchanged.
8370
8371    MODE is the mode in which the operation will be done.  No bits outside
8372    the width of this mode matter.  It is assumed that the width of this mode
8373    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8374
8375    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8376    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8377    result is simply *PCONST0.
8378
8379    If the resulting operation cannot be expressed as one operation, we
8380    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8381
8382 static int
8383 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8384 {
8385   enum rtx_code op0 = *pop0;
8386   HOST_WIDE_INT const0 = *pconst0;
8387
8388   const0 &= GET_MODE_MASK (mode);
8389   const1 &= GET_MODE_MASK (mode);
8390
8391   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8392   if (op0 == AND)
8393     const1 &= const0;
8394
8395   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8396      if OP0 is SET.  */
8397
8398   if (op1 == UNKNOWN || op0 == SET)
8399     return 1;
8400
8401   else if (op0 == UNKNOWN)
8402     op0 = op1, const0 = const1;
8403
8404   else if (op0 == op1)
8405     {
8406       switch (op0)
8407         {
8408         case AND:
8409           const0 &= const1;
8410           break;
8411         case IOR:
8412           const0 |= const1;
8413           break;
8414         case XOR:
8415           const0 ^= const1;
8416           break;
8417         case PLUS:
8418           const0 += const1;
8419           break;
8420         case NEG:
8421           op0 = UNKNOWN;
8422           break;
8423         default:
8424           break;
8425         }
8426     }
8427
8428   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8429   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8430     return 0;
8431
8432   /* If the two constants aren't the same, we can't do anything.  The
8433      remaining six cases can all be done.  */
8434   else if (const0 != const1)
8435     return 0;
8436
8437   else
8438     switch (op0)
8439       {
8440       case IOR:
8441         if (op1 == AND)
8442           /* (a & b) | b == b */
8443           op0 = SET;
8444         else /* op1 == XOR */
8445           /* (a ^ b) | b == a | b */
8446           {;}
8447         break;
8448
8449       case XOR:
8450         if (op1 == AND)
8451           /* (a & b) ^ b == (~a) & b */
8452           op0 = AND, *pcomp_p = 1;
8453         else /* op1 == IOR */
8454           /* (a | b) ^ b == a & ~b */
8455           op0 = AND, const0 = ~const0;
8456         break;
8457
8458       case AND:
8459         if (op1 == IOR)
8460           /* (a | b) & b == b */
8461         op0 = SET;
8462         else /* op1 == XOR */
8463           /* (a ^ b) & b) == (~a) & b */
8464           *pcomp_p = 1;
8465         break;
8466       default:
8467         break;
8468       }
8469
8470   /* Check for NO-OP cases.  */
8471   const0 &= GET_MODE_MASK (mode);
8472   if (const0 == 0
8473       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8474     op0 = UNKNOWN;
8475   else if (const0 == 0 && op0 == AND)
8476     op0 = SET;
8477   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8478            && op0 == AND)
8479     op0 = UNKNOWN;
8480
8481   /* ??? Slightly redundant with the above mask, but not entirely.
8482      Moving this above means we'd have to sign-extend the mode mask
8483      for the final test.  */
8484   const0 = trunc_int_for_mode (const0, mode);
8485
8486   *pop0 = op0;
8487   *pconst0 = const0;
8488
8489   return 1;
8490 }
8491 \f
8492 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8493    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8494    simplify it.  Otherwise, return a simplified value.
8495
8496    The shift is normally computed in the widest mode we find in VAROP, as
8497    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8498    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8499
8500 static rtx
8501 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8502                         rtx varop, int orig_count)
8503 {
8504   enum rtx_code orig_code = code;
8505   rtx orig_varop = varop;
8506   int count;
8507   enum machine_mode mode = result_mode;
8508   enum machine_mode shift_mode, tmode;
8509   unsigned int mode_words
8510     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8511   /* We form (outer_op (code varop count) (outer_const)).  */
8512   enum rtx_code outer_op = UNKNOWN;
8513   HOST_WIDE_INT outer_const = 0;
8514   int complement_p = 0;
8515   rtx new, x;
8516
8517   /* Make sure and truncate the "natural" shift on the way in.  We don't
8518      want to do this inside the loop as it makes it more difficult to
8519      combine shifts.  */
8520   if (SHIFT_COUNT_TRUNCATED)
8521     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8522
8523   /* If we were given an invalid count, don't do anything except exactly
8524      what was requested.  */
8525
8526   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8527     return NULL_RTX;
8528
8529   count = orig_count;
8530
8531   /* Unless one of the branches of the `if' in this loop does a `continue',
8532      we will `break' the loop after the `if'.  */
8533
8534   while (count != 0)
8535     {
8536       /* If we have an operand of (clobber (const_int 0)), fail.  */
8537       if (GET_CODE (varop) == CLOBBER)
8538         return NULL_RTX;
8539
8540       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8541          here would cause an infinite loop.  */
8542       if (complement_p)
8543         break;
8544
8545       /* Convert ROTATERT to ROTATE.  */
8546       if (code == ROTATERT)
8547         {
8548           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8549           code = ROTATE;
8550           if (VECTOR_MODE_P (result_mode))
8551             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8552           else
8553             count = bitsize - count;
8554         }
8555
8556       /* We need to determine what mode we will do the shift in.  If the
8557          shift is a right shift or a ROTATE, we must always do it in the mode
8558          it was originally done in.  Otherwise, we can do it in MODE, the
8559          widest mode encountered.  */
8560       shift_mode
8561         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8562            ? result_mode : mode);
8563
8564       /* Handle cases where the count is greater than the size of the mode
8565          minus 1.  For ASHIFT, use the size minus one as the count (this can
8566          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8567          take the count modulo the size.  For other shifts, the result is
8568          zero.
8569
8570          Since these shifts are being produced by the compiler by combining
8571          multiple operations, each of which are defined, we know what the
8572          result is supposed to be.  */
8573
8574       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8575         {
8576           if (code == ASHIFTRT)
8577             count = GET_MODE_BITSIZE (shift_mode) - 1;
8578           else if (code == ROTATE || code == ROTATERT)
8579             count %= GET_MODE_BITSIZE (shift_mode);
8580           else
8581             {
8582               /* We can't simply return zero because there may be an
8583                  outer op.  */
8584               varop = const0_rtx;
8585               count = 0;
8586               break;
8587             }
8588         }
8589
8590       /* An arithmetic right shift of a quantity known to be -1 or 0
8591          is a no-op.  */
8592       if (code == ASHIFTRT
8593           && (num_sign_bit_copies (varop, shift_mode)
8594               == GET_MODE_BITSIZE (shift_mode)))
8595         {
8596           count = 0;
8597           break;
8598         }
8599
8600       /* If we are doing an arithmetic right shift and discarding all but
8601          the sign bit copies, this is equivalent to doing a shift by the
8602          bitsize minus one.  Convert it into that shift because it will often
8603          allow other simplifications.  */
8604
8605       if (code == ASHIFTRT
8606           && (count + num_sign_bit_copies (varop, shift_mode)
8607               >= GET_MODE_BITSIZE (shift_mode)))
8608         count = GET_MODE_BITSIZE (shift_mode) - 1;
8609
8610       /* We simplify the tests below and elsewhere by converting
8611          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8612          `make_compound_operation' will convert it to an ASHIFTRT for
8613          those machines (such as VAX) that don't have an LSHIFTRT.  */
8614       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8615           && code == ASHIFTRT
8616           && ((nonzero_bits (varop, shift_mode)
8617                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8618               == 0))
8619         code = LSHIFTRT;
8620
8621       if (code == LSHIFTRT
8622           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8623           && !(nonzero_bits (varop, shift_mode) >> count))
8624         varop = const0_rtx;
8625       if (code == ASHIFT
8626           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8627           && !((nonzero_bits (varop, shift_mode) << count)
8628                & GET_MODE_MASK (shift_mode)))
8629         varop = const0_rtx;
8630
8631       switch (GET_CODE (varop))
8632         {
8633         case SIGN_EXTEND:
8634         case ZERO_EXTEND:
8635         case SIGN_EXTRACT:
8636         case ZERO_EXTRACT:
8637           new = expand_compound_operation (varop);
8638           if (new != varop)
8639             {
8640               varop = new;
8641               continue;
8642             }
8643           break;
8644
8645         case MEM:
8646           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8647              minus the width of a smaller mode, we can do this with a
8648              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8649           if ((code == ASHIFTRT || code == LSHIFTRT)
8650               && ! mode_dependent_address_p (XEXP (varop, 0))
8651               && ! MEM_VOLATILE_P (varop)
8652               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8653                                          MODE_INT, 1)) != BLKmode)
8654             {
8655               new = adjust_address_nv (varop, tmode,
8656                                        BYTES_BIG_ENDIAN ? 0
8657                                        : count / BITS_PER_UNIT);
8658
8659               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8660                                      : ZERO_EXTEND, mode, new);
8661               count = 0;
8662               continue;
8663             }
8664           break;
8665
8666         case SUBREG:
8667           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8668              the same number of words as what we've seen so far.  Then store
8669              the widest mode in MODE.  */
8670           if (subreg_lowpart_p (varop)
8671               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8672                   > GET_MODE_SIZE (GET_MODE (varop)))
8673               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8674                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8675                  == mode_words)
8676             {
8677               varop = SUBREG_REG (varop);
8678               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8679                 mode = GET_MODE (varop);
8680               continue;
8681             }
8682           break;
8683
8684         case MULT:
8685           /* Some machines use MULT instead of ASHIFT because MULT
8686              is cheaper.  But it is still better on those machines to
8687              merge two shifts into one.  */
8688           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8689               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8690             {
8691               varop
8692                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8693                                        XEXP (varop, 0),
8694                                        GEN_INT (exact_log2 (
8695                                                 INTVAL (XEXP (varop, 1)))));
8696               continue;
8697             }
8698           break;
8699
8700         case UDIV:
8701           /* Similar, for when divides are cheaper.  */
8702           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8703               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8704             {
8705               varop
8706                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8707                                        XEXP (varop, 0),
8708                                        GEN_INT (exact_log2 (
8709                                                 INTVAL (XEXP (varop, 1)))));
8710               continue;
8711             }
8712           break;
8713
8714         case ASHIFTRT:
8715           /* If we are extracting just the sign bit of an arithmetic
8716              right shift, that shift is not needed.  However, the sign
8717              bit of a wider mode may be different from what would be
8718              interpreted as the sign bit in a narrower mode, so, if
8719              the result is narrower, don't discard the shift.  */
8720           if (code == LSHIFTRT
8721               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8722               && (GET_MODE_BITSIZE (result_mode)
8723                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8724             {
8725               varop = XEXP (varop, 0);
8726               continue;
8727             }
8728
8729           /* ... fall through ...  */
8730
8731         case LSHIFTRT:
8732         case ASHIFT:
8733         case ROTATE:
8734           /* Here we have two nested shifts.  The result is usually the
8735              AND of a new shift with a mask.  We compute the result below.  */
8736           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8737               && INTVAL (XEXP (varop, 1)) >= 0
8738               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8739               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8740               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8741             {
8742               enum rtx_code first_code = GET_CODE (varop);
8743               unsigned int first_count = INTVAL (XEXP (varop, 1));
8744               unsigned HOST_WIDE_INT mask;
8745               rtx mask_rtx;
8746
8747               /* We have one common special case.  We can't do any merging if
8748                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8749                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8750                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8751                  we can convert it to
8752                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8753                  This simplifies certain SIGN_EXTEND operations.  */
8754               if (code == ASHIFT && first_code == ASHIFTRT
8755                   && count == (GET_MODE_BITSIZE (result_mode)
8756                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8757                 {
8758                   /* C3 has the low-order C1 bits zero.  */
8759
8760                   mask = (GET_MODE_MASK (mode)
8761                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8762
8763                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8764                                                   XEXP (varop, 0), mask);
8765                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8766                                                 varop, count);
8767                   count = first_count;
8768                   code = ASHIFTRT;
8769                   continue;
8770                 }
8771
8772               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8773                  than C1 high-order bits equal to the sign bit, we can convert
8774                  this to either an ASHIFT or an ASHIFTRT depending on the
8775                  two counts.
8776
8777                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8778
8779               if (code == ASHIFTRT && first_code == ASHIFT
8780                   && GET_MODE (varop) == shift_mode
8781                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8782                       > first_count))
8783                 {
8784                   varop = XEXP (varop, 0);
8785                   count -= first_count;
8786                   if (count < 0)
8787                     {
8788                       count = -count;
8789                       code = ASHIFT;
8790                     }
8791
8792                   continue;
8793                 }
8794
8795               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8796                  we can only do this if FIRST_CODE is also ASHIFTRT.
8797
8798                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8799                  ASHIFTRT.
8800
8801                  If the mode of this shift is not the mode of the outer shift,
8802                  we can't do this if either shift is a right shift or ROTATE.
8803
8804                  Finally, we can't do any of these if the mode is too wide
8805                  unless the codes are the same.
8806
8807                  Handle the case where the shift codes are the same
8808                  first.  */
8809
8810               if (code == first_code)
8811                 {
8812                   if (GET_MODE (varop) != result_mode
8813                       && (code == ASHIFTRT || code == LSHIFTRT
8814                           || code == ROTATE))
8815                     break;
8816
8817                   count += first_count;
8818                   varop = XEXP (varop, 0);
8819                   continue;
8820                 }
8821
8822               if (code == ASHIFTRT
8823                   || (code == ROTATE && first_code == ASHIFTRT)
8824                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8825                   || (GET_MODE (varop) != result_mode
8826                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8827                           || first_code == ROTATE
8828                           || code == ROTATE)))
8829                 break;
8830
8831               /* To compute the mask to apply after the shift, shift the
8832                  nonzero bits of the inner shift the same way the
8833                  outer shift will.  */
8834
8835               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8836
8837               mask_rtx
8838                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8839                                                    GEN_INT (count));
8840
8841               /* Give up if we can't compute an outer operation to use.  */
8842               if (mask_rtx == 0
8843                   || GET_CODE (mask_rtx) != CONST_INT
8844                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8845                                         INTVAL (mask_rtx),
8846                                         result_mode, &complement_p))
8847                 break;
8848
8849               /* If the shifts are in the same direction, we add the
8850                  counts.  Otherwise, we subtract them.  */
8851               if ((code == ASHIFTRT || code == LSHIFTRT)
8852                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8853                 count += first_count;
8854               else
8855                 count -= first_count;
8856
8857               /* If COUNT is positive, the new shift is usually CODE,
8858                  except for the two exceptions below, in which case it is
8859                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8860                  always be used  */
8861               if (count > 0
8862                   && ((first_code == ROTATE && code == ASHIFT)
8863                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8864                 code = first_code;
8865               else if (count < 0)
8866                 code = first_code, count = -count;
8867
8868               varop = XEXP (varop, 0);
8869               continue;
8870             }
8871
8872           /* If we have (A << B << C) for any shift, we can convert this to
8873              (A << C << B).  This wins if A is a constant.  Only try this if
8874              B is not a constant.  */
8875
8876           else if (GET_CODE (varop) == code
8877                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
8878                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8879             {
8880               rtx new = simplify_const_binary_operation (code, mode,
8881                                                          XEXP (varop, 0),
8882                                                          GEN_INT (count));
8883               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8884               count = 0;
8885               continue;
8886             }
8887           break;
8888
8889         case NOT:
8890           /* Make this fit the case below.  */
8891           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8892                                GEN_INT (GET_MODE_MASK (mode)));
8893           continue;
8894
8895         case IOR:
8896         case AND:
8897         case XOR:
8898           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8899              with C the size of VAROP - 1 and the shift is logical if
8900              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8901              we have an (le X 0) operation.   If we have an arithmetic shift
8902              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8903              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8904
8905           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8906               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8907               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8908               && (code == LSHIFTRT || code == ASHIFTRT)
8909               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8910               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8911             {
8912               count = 0;
8913               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8914                                   const0_rtx);
8915
8916               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8917                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8918
8919               continue;
8920             }
8921
8922           /* If we have (shift (logical)), move the logical to the outside
8923              to allow it to possibly combine with another logical and the
8924              shift to combine with another shift.  This also canonicalizes to
8925              what a ZERO_EXTRACT looks like.  Also, some machines have
8926              (and (shift)) insns.  */
8927
8928           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8929               /* We can't do this if we have (ashiftrt (xor))  and the
8930                  constant has its sign bit set in shift_mode.  */
8931               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8932                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8933                                               shift_mode))
8934               && (new = simplify_const_binary_operation (code, result_mode,
8935                                                          XEXP (varop, 1),
8936                                                          GEN_INT (count))) != 0
8937               && GET_CODE (new) == CONST_INT
8938               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8939                                   INTVAL (new), result_mode, &complement_p))
8940             {
8941               varop = XEXP (varop, 0);
8942               continue;
8943             }
8944
8945           /* If we can't do that, try to simplify the shift in each arm of the
8946              logical expression, make a new logical expression, and apply
8947              the inverse distributive law.  This also can't be done
8948              for some (ashiftrt (xor)).  */
8949           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8950              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8951                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8952                                              shift_mode)))
8953             {
8954               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8955                                               XEXP (varop, 0), count);
8956               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8957                                               XEXP (varop, 1), count);
8958
8959               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8960                                            lhs, rhs);
8961               varop = apply_distributive_law (varop);
8962
8963               count = 0;
8964               continue;
8965             }
8966           break;
8967
8968         case EQ:
8969           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8970              says that the sign bit can be tested, FOO has mode MODE, C is
8971              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8972              that may be nonzero.  */
8973           if (code == LSHIFTRT
8974               && XEXP (varop, 1) == const0_rtx
8975               && GET_MODE (XEXP (varop, 0)) == result_mode
8976               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8977               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8978               && STORE_FLAG_VALUE == -1
8979               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8980               && merge_outer_ops (&outer_op, &outer_const, XOR,
8981                                   (HOST_WIDE_INT) 1, result_mode,
8982                                   &complement_p))
8983             {
8984               varop = XEXP (varop, 0);
8985               count = 0;
8986               continue;
8987             }
8988           break;
8989
8990         case NEG:
8991           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8992              than the number of bits in the mode is equivalent to A.  */
8993           if (code == LSHIFTRT
8994               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8995               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8996             {
8997               varop = XEXP (varop, 0);
8998               count = 0;
8999               continue;
9000             }
9001
9002           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9003              NEG outside to allow shifts to combine.  */
9004           if (code == ASHIFT
9005               && merge_outer_ops (&outer_op, &outer_const, NEG,
9006                                   (HOST_WIDE_INT) 0, result_mode,
9007                                   &complement_p))
9008             {
9009               varop = XEXP (varop, 0);
9010               continue;
9011             }
9012           break;
9013
9014         case PLUS:
9015           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9016              is one less than the number of bits in the mode is
9017              equivalent to (xor A 1).  */
9018           if (code == LSHIFTRT
9019               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9020               && XEXP (varop, 1) == constm1_rtx
9021               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9022               && merge_outer_ops (&outer_op, &outer_const, XOR,
9023                                   (HOST_WIDE_INT) 1, result_mode,
9024                                   &complement_p))
9025             {
9026               count = 0;
9027               varop = XEXP (varop, 0);
9028               continue;
9029             }
9030
9031           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9032              that might be nonzero in BAR are those being shifted out and those
9033              bits are known zero in FOO, we can replace the PLUS with FOO.
9034              Similarly in the other operand order.  This code occurs when
9035              we are computing the size of a variable-size array.  */
9036
9037           if ((code == ASHIFTRT || code == LSHIFTRT)
9038               && count < HOST_BITS_PER_WIDE_INT
9039               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9040               && (nonzero_bits (XEXP (varop, 1), result_mode)
9041                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9042             {
9043               varop = XEXP (varop, 0);
9044               continue;
9045             }
9046           else if ((code == ASHIFTRT || code == LSHIFTRT)
9047                    && count < HOST_BITS_PER_WIDE_INT
9048                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9049                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9050                             >> count)
9051                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9052                             & nonzero_bits (XEXP (varop, 1),
9053                                                  result_mode)))
9054             {
9055               varop = XEXP (varop, 1);
9056               continue;
9057             }
9058
9059           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9060           if (code == ASHIFT
9061               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9062               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9063                                                          XEXP (varop, 1),
9064                                                          GEN_INT (count))) != 0
9065               && GET_CODE (new) == CONST_INT
9066               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9067                                   INTVAL (new), result_mode, &complement_p))
9068             {
9069               varop = XEXP (varop, 0);
9070               continue;
9071             }
9072
9073           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9074              signbit', and attempt to change the PLUS to an XOR and move it to
9075              the outer operation as is done above in the AND/IOR/XOR case
9076              leg for shift(logical). See details in logical handling above
9077              for reasoning in doing so.  */
9078           if (code == LSHIFTRT
9079               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9080               && mode_signbit_p (result_mode, XEXP (varop, 1))
9081               && (new = simplify_const_binary_operation (code, result_mode,
9082                                                          XEXP (varop, 1),
9083                                                          GEN_INT (count))) != 0
9084               && GET_CODE (new) == CONST_INT
9085               && merge_outer_ops (&outer_op, &outer_const, XOR,
9086                                   INTVAL (new), result_mode, &complement_p))
9087             {
9088               varop = XEXP (varop, 0);
9089               continue;
9090             }
9091
9092           break;
9093
9094         case MINUS:
9095           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9096              with C the size of VAROP - 1 and the shift is logical if
9097              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9098              we have a (gt X 0) operation.  If the shift is arithmetic with
9099              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9100              we have a (neg (gt X 0)) operation.  */
9101
9102           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9103               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9104               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9105               && (code == LSHIFTRT || code == ASHIFTRT)
9106               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9107               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9108               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9109             {
9110               count = 0;
9111               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9112                                   const0_rtx);
9113
9114               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9115                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9116
9117               continue;
9118             }
9119           break;
9120
9121         case TRUNCATE:
9122           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9123              if the truncate does not affect the value.  */
9124           if (code == LSHIFTRT
9125               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9126               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9127               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9128                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9129                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9130             {
9131               rtx varop_inner = XEXP (varop, 0);
9132
9133               varop_inner
9134                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9135                                     XEXP (varop_inner, 0),
9136                                     GEN_INT
9137                                     (count + INTVAL (XEXP (varop_inner, 1))));
9138               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9139               count = 0;
9140               continue;
9141             }
9142           break;
9143
9144         default:
9145           break;
9146         }
9147
9148       break;
9149     }
9150
9151   /* We need to determine what mode to do the shift in.  If the shift is
9152      a right shift or ROTATE, we must always do it in the mode it was
9153      originally done in.  Otherwise, we can do it in MODE, the widest mode
9154      encountered.  The code we care about is that of the shift that will
9155      actually be done, not the shift that was originally requested.  */
9156   shift_mode
9157     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9158        ? result_mode : mode);
9159
9160   /* We have now finished analyzing the shift.  The result should be
9161      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9162      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9163      to the result of the shift.  OUTER_CONST is the relevant constant,
9164      but we must turn off all bits turned off in the shift.  */
9165
9166   if (outer_op == UNKNOWN
9167       && orig_code == code && orig_count == count
9168       && varop == orig_varop
9169       && shift_mode == GET_MODE (varop))
9170     return NULL_RTX;
9171
9172   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9173   varop = gen_lowpart (shift_mode, varop);
9174   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9175     return NULL_RTX;
9176
9177   /* If we have an outer operation and we just made a shift, it is
9178      possible that we could have simplified the shift were it not
9179      for the outer operation.  So try to do the simplification
9180      recursively.  */
9181
9182   if (outer_op != UNKNOWN)
9183     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9184   else
9185     x = NULL_RTX;
9186
9187   if (x == NULL_RTX)
9188     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9189
9190   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9191      turn off all the bits that the shift would have turned off.  */
9192   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9193     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9194                                 GET_MODE_MASK (result_mode) >> orig_count);
9195
9196   /* Do the remainder of the processing in RESULT_MODE.  */
9197   x = gen_lowpart (result_mode, x);
9198
9199   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9200      operation.  */
9201   if (complement_p)
9202     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9203
9204   if (outer_op != UNKNOWN)
9205     {
9206       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9207         outer_const = trunc_int_for_mode (outer_const, result_mode);
9208
9209       if (outer_op == AND)
9210         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9211       else if (outer_op == SET)
9212         /* This means that we have determined that the result is
9213            equivalent to a constant.  This should be rare.  */
9214         x = GEN_INT (outer_const);
9215       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9216         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9217       else
9218         x = simplify_gen_binary (outer_op, result_mode, x,
9219                                  GEN_INT (outer_const));
9220     }
9221
9222   return x;
9223 }
9224
9225 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9226    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9227    return X or, if it is NULL, synthesize the expression with
9228    simplify_gen_binary.  Otherwise, return a simplified value.
9229
9230    The shift is normally computed in the widest mode we find in VAROP, as
9231    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9232    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9233
9234 static rtx
9235 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9236                       rtx varop, int count)
9237 {
9238   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9239   if (tem)
9240     return tem;
9241
9242   if (!x)
9243     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9244   if (GET_MODE (x) != result_mode)
9245     x = gen_lowpart (result_mode, x);
9246   return x;
9247 }
9248
9249 \f
9250 /* Like recog, but we receive the address of a pointer to a new pattern.
9251    We try to match the rtx that the pointer points to.
9252    If that fails, we may try to modify or replace the pattern,
9253    storing the replacement into the same pointer object.
9254
9255    Modifications include deletion or addition of CLOBBERs.
9256
9257    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9258    the CLOBBERs are placed.
9259
9260    The value is the final insn code from the pattern ultimately matched,
9261    or -1.  */
9262
9263 static int
9264 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9265 {
9266   rtx pat = *pnewpat;
9267   int insn_code_number;
9268   int num_clobbers_to_add = 0;
9269   int i;
9270   rtx notes = 0;
9271   rtx old_notes, old_pat;
9272
9273   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9274      we use to indicate that something didn't match.  If we find such a
9275      thing, force rejection.  */
9276   if (GET_CODE (pat) == PARALLEL)
9277     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9278       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9279           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9280         return -1;
9281
9282   old_pat = PATTERN (insn);
9283   old_notes = REG_NOTES (insn);
9284   PATTERN (insn) = pat;
9285   REG_NOTES (insn) = 0;
9286
9287   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9288
9289   /* If it isn't, there is the possibility that we previously had an insn
9290      that clobbered some register as a side effect, but the combined
9291      insn doesn't need to do that.  So try once more without the clobbers
9292      unless this represents an ASM insn.  */
9293
9294   if (insn_code_number < 0 && ! check_asm_operands (pat)
9295       && GET_CODE (pat) == PARALLEL)
9296     {
9297       int pos;
9298
9299       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9300         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9301           {
9302             if (i != pos)
9303               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9304             pos++;
9305           }
9306
9307       SUBST_INT (XVECLEN (pat, 0), pos);
9308
9309       if (pos == 1)
9310         pat = XVECEXP (pat, 0, 0);
9311
9312       PATTERN (insn) = pat;
9313       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9314     }
9315   PATTERN (insn) = old_pat;
9316   REG_NOTES (insn) = old_notes;
9317
9318   /* Recognize all noop sets, these will be killed by followup pass.  */
9319   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9320     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9321
9322   /* If we had any clobbers to add, make a new pattern than contains
9323      them.  Then check to make sure that all of them are dead.  */
9324   if (num_clobbers_to_add)
9325     {
9326       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9327                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9328                                                   ? (XVECLEN (pat, 0)
9329                                                      + num_clobbers_to_add)
9330                                                   : num_clobbers_to_add + 1));
9331
9332       if (GET_CODE (pat) == PARALLEL)
9333         for (i = 0; i < XVECLEN (pat, 0); i++)
9334           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9335       else
9336         XVECEXP (newpat, 0, 0) = pat;
9337
9338       add_clobbers (newpat, insn_code_number);
9339
9340       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9341            i < XVECLEN (newpat, 0); i++)
9342         {
9343           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9344               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9345             return -1;
9346           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9347                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9348         }
9349       pat = newpat;
9350     }
9351
9352   *pnewpat = pat;
9353   *pnotes = notes;
9354
9355   return insn_code_number;
9356 }
9357 \f
9358 /* Like gen_lowpart_general but for use by combine.  In combine it
9359    is not possible to create any new pseudoregs.  However, it is
9360    safe to create invalid memory addresses, because combine will
9361    try to recognize them and all they will do is make the combine
9362    attempt fail.
9363
9364    If for some reason this cannot do its job, an rtx
9365    (clobber (const_int 0)) is returned.
9366    An insn containing that will not be recognized.  */
9367
9368 static rtx
9369 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9370 {
9371   enum machine_mode imode = GET_MODE (x);
9372   unsigned int osize = GET_MODE_SIZE (omode);
9373   unsigned int isize = GET_MODE_SIZE (imode);
9374   rtx result;
9375
9376   if (omode == imode)
9377     return x;
9378
9379   /* Return identity if this is a CONST or symbolic reference.  */
9380   if (omode == Pmode
9381       && (GET_CODE (x) == CONST
9382           || GET_CODE (x) == SYMBOL_REF
9383           || GET_CODE (x) == LABEL_REF))
9384     return x;
9385
9386   /* We can only support MODE being wider than a word if X is a
9387      constant integer or has a mode the same size.  */
9388   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9389       && ! ((imode == VOIDmode
9390              && (GET_CODE (x) == CONST_INT
9391                  || GET_CODE (x) == CONST_DOUBLE))
9392             || isize == osize))
9393     goto fail;
9394
9395   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9396      won't know what to do.  So we will strip off the SUBREG here and
9397      process normally.  */
9398   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9399     {
9400       x = SUBREG_REG (x);
9401
9402       /* For use in case we fall down into the address adjustments
9403          further below, we need to adjust the known mode and size of
9404          x; imode and isize, since we just adjusted x.  */
9405       imode = GET_MODE (x);
9406
9407       if (imode == omode)
9408         return x;
9409
9410       isize = GET_MODE_SIZE (imode);
9411     }
9412
9413   result = gen_lowpart_common (omode, x);
9414
9415 #ifdef CANNOT_CHANGE_MODE_CLASS
9416   if (result != 0 && GET_CODE (result) == SUBREG)
9417     record_subregs_of_mode (result);
9418 #endif
9419
9420   if (result)
9421     return result;
9422
9423   if (MEM_P (x))
9424     {
9425       int offset = 0;
9426
9427       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9428          address.  */
9429       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9430         goto fail;
9431
9432       /* If we want to refer to something bigger than the original memref,
9433          generate a paradoxical subreg instead.  That will force a reload
9434          of the original memref X.  */
9435       if (isize < osize)
9436         return gen_rtx_SUBREG (omode, x, 0);
9437
9438       if (WORDS_BIG_ENDIAN)
9439         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9440
9441       /* Adjust the address so that the address-after-the-data is
9442          unchanged.  */
9443       if (BYTES_BIG_ENDIAN)
9444         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9445
9446       return adjust_address_nv (x, omode, offset);
9447     }
9448
9449   /* If X is a comparison operator, rewrite it in a new mode.  This
9450      probably won't match, but may allow further simplifications.  */
9451   else if (COMPARISON_P (x))
9452     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9453
9454   /* If we couldn't simplify X any other way, just enclose it in a
9455      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9456      include an explicit SUBREG or we may simplify it further in combine.  */
9457   else
9458     {
9459       int offset = 0;
9460       rtx res;
9461
9462       offset = subreg_lowpart_offset (omode, imode);
9463       if (imode == VOIDmode)
9464         {
9465           imode = int_mode_for_mode (omode);
9466           x = gen_lowpart_common (imode, x);
9467           if (x == NULL)
9468             goto fail;
9469         }
9470       res = simplify_gen_subreg (omode, x, imode, offset);
9471       if (res)
9472         return res;
9473     }
9474
9475  fail:
9476   return gen_rtx_CLOBBER (imode, const0_rtx);
9477 }
9478 \f
9479 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9480    comparison code that will be tested.
9481
9482    The result is a possibly different comparison code to use.  *POP0 and
9483    *POP1 may be updated.
9484
9485    It is possible that we might detect that a comparison is either always
9486    true or always false.  However, we do not perform general constant
9487    folding in combine, so this knowledge isn't useful.  Such tautologies
9488    should have been detected earlier.  Hence we ignore all such cases.  */
9489
9490 static enum rtx_code
9491 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9492 {
9493   rtx op0 = *pop0;
9494   rtx op1 = *pop1;
9495   rtx tem, tem1;
9496   int i;
9497   enum machine_mode mode, tmode;
9498
9499   /* Try a few ways of applying the same transformation to both operands.  */
9500   while (1)
9501     {
9502 #ifndef WORD_REGISTER_OPERATIONS
9503       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9504          so check specially.  */
9505       if (code != GTU && code != GEU && code != LTU && code != LEU
9506           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9507           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9508           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9509           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9510           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9511           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9512               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9513           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9514           && XEXP (op0, 1) == XEXP (op1, 1)
9515           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9516           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9517           && (INTVAL (XEXP (op0, 1))
9518               == (GET_MODE_BITSIZE (GET_MODE (op0))
9519                   - (GET_MODE_BITSIZE
9520                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9521         {
9522           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9523           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9524         }
9525 #endif
9526
9527       /* If both operands are the same constant shift, see if we can ignore the
9528          shift.  We can if the shift is a rotate or if the bits shifted out of
9529          this shift are known to be zero for both inputs and if the type of
9530          comparison is compatible with the shift.  */
9531       if (GET_CODE (op0) == GET_CODE (op1)
9532           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9533           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9534               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9535                   && (code != GT && code != LT && code != GE && code != LE))
9536               || (GET_CODE (op0) == ASHIFTRT
9537                   && (code != GTU && code != LTU
9538                       && code != GEU && code != LEU)))
9539           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9540           && INTVAL (XEXP (op0, 1)) >= 0
9541           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9542           && XEXP (op0, 1) == XEXP (op1, 1))
9543         {
9544           enum machine_mode mode = GET_MODE (op0);
9545           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9546           int shift_count = INTVAL (XEXP (op0, 1));
9547
9548           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9549             mask &= (mask >> shift_count) << shift_count;
9550           else if (GET_CODE (op0) == ASHIFT)
9551             mask = (mask & (mask << shift_count)) >> shift_count;
9552
9553           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9554               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9555             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9556           else
9557             break;
9558         }
9559
9560       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9561          SUBREGs are of the same mode, and, in both cases, the AND would
9562          be redundant if the comparison was done in the narrower mode,
9563          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9564          and the operand's possibly nonzero bits are 0xffffff01; in that case
9565          if we only care about QImode, we don't need the AND).  This case
9566          occurs if the output mode of an scc insn is not SImode and
9567          STORE_FLAG_VALUE == 1 (e.g., the 386).
9568
9569          Similarly, check for a case where the AND's are ZERO_EXTEND
9570          operations from some narrower mode even though a SUBREG is not
9571          present.  */
9572
9573       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9574                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9575                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9576         {
9577           rtx inner_op0 = XEXP (op0, 0);
9578           rtx inner_op1 = XEXP (op1, 0);
9579           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9580           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9581           int changed = 0;
9582
9583           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9584               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9585                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9586               && (GET_MODE (SUBREG_REG (inner_op0))
9587                   == GET_MODE (SUBREG_REG (inner_op1)))
9588               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9589                   <= HOST_BITS_PER_WIDE_INT)
9590               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9591                                              GET_MODE (SUBREG_REG (inner_op0)))))
9592               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9593                                              GET_MODE (SUBREG_REG (inner_op1))))))
9594             {
9595               op0 = SUBREG_REG (inner_op0);
9596               op1 = SUBREG_REG (inner_op1);
9597
9598               /* The resulting comparison is always unsigned since we masked
9599                  off the original sign bit.  */
9600               code = unsigned_condition (code);
9601
9602               changed = 1;
9603             }
9604
9605           else if (c0 == c1)
9606             for (tmode = GET_CLASS_NARROWEST_MODE
9607                  (GET_MODE_CLASS (GET_MODE (op0)));
9608                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9609               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9610                 {
9611                   op0 = gen_lowpart (tmode, inner_op0);
9612                   op1 = gen_lowpart (tmode, inner_op1);
9613                   code = unsigned_condition (code);
9614                   changed = 1;
9615                   break;
9616                 }
9617
9618           if (! changed)
9619             break;
9620         }
9621
9622       /* If both operands are NOT, we can strip off the outer operation
9623          and adjust the comparison code for swapped operands; similarly for
9624          NEG, except that this must be an equality comparison.  */
9625       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9626                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9627                    && (code == EQ || code == NE)))
9628         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9629
9630       else
9631         break;
9632     }
9633
9634   /* If the first operand is a constant, swap the operands and adjust the
9635      comparison code appropriately, but don't do this if the second operand
9636      is already a constant integer.  */
9637   if (swap_commutative_operands_p (op0, op1))
9638     {
9639       tem = op0, op0 = op1, op1 = tem;
9640       code = swap_condition (code);
9641     }
9642
9643   /* We now enter a loop during which we will try to simplify the comparison.
9644      For the most part, we only are concerned with comparisons with zero,
9645      but some things may really be comparisons with zero but not start
9646      out looking that way.  */
9647
9648   while (GET_CODE (op1) == CONST_INT)
9649     {
9650       enum machine_mode mode = GET_MODE (op0);
9651       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9652       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9653       int equality_comparison_p;
9654       int sign_bit_comparison_p;
9655       int unsigned_comparison_p;
9656       HOST_WIDE_INT const_op;
9657
9658       /* We only want to handle integral modes.  This catches VOIDmode,
9659          CCmode, and the floating-point modes.  An exception is that we
9660          can handle VOIDmode if OP0 is a COMPARE or a comparison
9661          operation.  */
9662
9663       if (GET_MODE_CLASS (mode) != MODE_INT
9664           && ! (mode == VOIDmode
9665                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9666         break;
9667
9668       /* Get the constant we are comparing against and turn off all bits
9669          not on in our mode.  */
9670       const_op = INTVAL (op1);
9671       if (mode != VOIDmode)
9672         const_op = trunc_int_for_mode (const_op, mode);
9673       op1 = GEN_INT (const_op);
9674
9675       /* If we are comparing against a constant power of two and the value
9676          being compared can only have that single bit nonzero (e.g., it was
9677          `and'ed with that bit), we can replace this with a comparison
9678          with zero.  */
9679       if (const_op
9680           && (code == EQ || code == NE || code == GE || code == GEU
9681               || code == LT || code == LTU)
9682           && mode_width <= HOST_BITS_PER_WIDE_INT
9683           && exact_log2 (const_op) >= 0
9684           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9685         {
9686           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9687           op1 = const0_rtx, const_op = 0;
9688         }
9689
9690       /* Similarly, if we are comparing a value known to be either -1 or
9691          0 with -1, change it to the opposite comparison against zero.  */
9692
9693       if (const_op == -1
9694           && (code == EQ || code == NE || code == GT || code == LE
9695               || code == GEU || code == LTU)
9696           && num_sign_bit_copies (op0, mode) == mode_width)
9697         {
9698           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9699           op1 = const0_rtx, const_op = 0;
9700         }
9701
9702       /* Do some canonicalizations based on the comparison code.  We prefer
9703          comparisons against zero and then prefer equality comparisons.
9704          If we can reduce the size of a constant, we will do that too.  */
9705
9706       switch (code)
9707         {
9708         case LT:
9709           /* < C is equivalent to <= (C - 1) */
9710           if (const_op > 0)
9711             {
9712               const_op -= 1;
9713               op1 = GEN_INT (const_op);
9714               code = LE;
9715               /* ... fall through to LE case below.  */
9716             }
9717           else
9718             break;
9719
9720         case LE:
9721           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9722           if (const_op < 0)
9723             {
9724               const_op += 1;
9725               op1 = GEN_INT (const_op);
9726               code = LT;
9727             }
9728
9729           /* If we are doing a <= 0 comparison on a value known to have
9730              a zero sign bit, we can replace this with == 0.  */
9731           else if (const_op == 0
9732                    && mode_width <= HOST_BITS_PER_WIDE_INT
9733                    && (nonzero_bits (op0, mode)
9734                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9735             code = EQ;
9736           break;
9737
9738         case GE:
9739           /* >= C is equivalent to > (C - 1).  */
9740           if (const_op > 0)
9741             {
9742               const_op -= 1;
9743               op1 = GEN_INT (const_op);
9744               code = GT;
9745               /* ... fall through to GT below.  */
9746             }
9747           else
9748             break;
9749
9750         case GT:
9751           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9752           if (const_op < 0)
9753             {
9754               const_op += 1;
9755               op1 = GEN_INT (const_op);
9756               code = GE;
9757             }
9758
9759           /* If we are doing a > 0 comparison on a value known to have
9760              a zero sign bit, we can replace this with != 0.  */
9761           else if (const_op == 0
9762                    && mode_width <= HOST_BITS_PER_WIDE_INT
9763                    && (nonzero_bits (op0, mode)
9764                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9765             code = NE;
9766           break;
9767
9768         case LTU:
9769           /* < C is equivalent to <= (C - 1).  */
9770           if (const_op > 0)
9771             {
9772               const_op -= 1;
9773               op1 = GEN_INT (const_op);
9774               code = LEU;
9775               /* ... fall through ...  */
9776             }
9777
9778           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9779           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9780                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9781             {
9782               const_op = 0, op1 = const0_rtx;
9783               code = GE;
9784               break;
9785             }
9786           else
9787             break;
9788
9789         case LEU:
9790           /* unsigned <= 0 is equivalent to == 0 */
9791           if (const_op == 0)
9792             code = EQ;
9793
9794           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9795           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9796                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9797             {
9798               const_op = 0, op1 = const0_rtx;
9799               code = GE;
9800             }
9801           break;
9802
9803         case GEU:
9804           /* >= C is equivalent to > (C - 1).  */
9805           if (const_op > 1)
9806             {
9807               const_op -= 1;
9808               op1 = GEN_INT (const_op);
9809               code = GTU;
9810               /* ... fall through ...  */
9811             }
9812
9813           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9814           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9815                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9816             {
9817               const_op = 0, op1 = const0_rtx;
9818               code = LT;
9819               break;
9820             }
9821           else
9822             break;
9823
9824         case GTU:
9825           /* unsigned > 0 is equivalent to != 0 */
9826           if (const_op == 0)
9827             code = NE;
9828
9829           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9830           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9831                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9832             {
9833               const_op = 0, op1 = const0_rtx;
9834               code = LT;
9835             }
9836           break;
9837
9838         default:
9839           break;
9840         }
9841
9842       /* Compute some predicates to simplify code below.  */
9843
9844       equality_comparison_p = (code == EQ || code == NE);
9845       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9846       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9847                                || code == GEU);
9848
9849       /* If this is a sign bit comparison and we can do arithmetic in
9850          MODE, say that we will only be needing the sign bit of OP0.  */
9851       if (sign_bit_comparison_p
9852           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9853         op0 = force_to_mode (op0, mode,
9854                              ((HOST_WIDE_INT) 1
9855                               << (GET_MODE_BITSIZE (mode) - 1)),
9856                              0);
9857
9858       /* Now try cases based on the opcode of OP0.  If none of the cases
9859          does a "continue", we exit this loop immediately after the
9860          switch.  */
9861
9862       switch (GET_CODE (op0))
9863         {
9864         case ZERO_EXTRACT:
9865           /* If we are extracting a single bit from a variable position in
9866              a constant that has only a single bit set and are comparing it
9867              with zero, we can convert this into an equality comparison
9868              between the position and the location of the single bit.  */
9869           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9870              have already reduced the shift count modulo the word size.  */
9871           if (!SHIFT_COUNT_TRUNCATED
9872               && GET_CODE (XEXP (op0, 0)) == CONST_INT
9873               && XEXP (op0, 1) == const1_rtx
9874               && equality_comparison_p && const_op == 0
9875               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9876             {
9877               if (BITS_BIG_ENDIAN)
9878                 {
9879                   enum machine_mode new_mode
9880                     = mode_for_extraction (EP_extzv, 1);
9881                   if (new_mode == MAX_MACHINE_MODE)
9882                     i = BITS_PER_WORD - 1 - i;
9883                   else
9884                     {
9885                       mode = new_mode;
9886                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
9887                     }
9888                 }
9889
9890               op0 = XEXP (op0, 2);
9891               op1 = GEN_INT (i);
9892               const_op = i;
9893
9894               /* Result is nonzero iff shift count is equal to I.  */
9895               code = reverse_condition (code);
9896               continue;
9897             }
9898
9899           /* ... fall through ...  */
9900
9901         case SIGN_EXTRACT:
9902           tem = expand_compound_operation (op0);
9903           if (tem != op0)
9904             {
9905               op0 = tem;
9906               continue;
9907             }
9908           break;
9909
9910         case NOT:
9911           /* If testing for equality, we can take the NOT of the constant.  */
9912           if (equality_comparison_p
9913               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9914             {
9915               op0 = XEXP (op0, 0);
9916               op1 = tem;
9917               continue;
9918             }
9919
9920           /* If just looking at the sign bit, reverse the sense of the
9921              comparison.  */
9922           if (sign_bit_comparison_p)
9923             {
9924               op0 = XEXP (op0, 0);
9925               code = (code == GE ? LT : GE);
9926               continue;
9927             }
9928           break;
9929
9930         case NEG:
9931           /* If testing for equality, we can take the NEG of the constant.  */
9932           if (equality_comparison_p
9933               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9934             {
9935               op0 = XEXP (op0, 0);
9936               op1 = tem;
9937               continue;
9938             }
9939
9940           /* The remaining cases only apply to comparisons with zero.  */
9941           if (const_op != 0)
9942             break;
9943
9944           /* When X is ABS or is known positive,
9945              (neg X) is < 0 if and only if X != 0.  */
9946
9947           if (sign_bit_comparison_p
9948               && (GET_CODE (XEXP (op0, 0)) == ABS
9949                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9950                       && (nonzero_bits (XEXP (op0, 0), mode)
9951                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9952             {
9953               op0 = XEXP (op0, 0);
9954               code = (code == LT ? NE : EQ);
9955               continue;
9956             }
9957
9958           /* If we have NEG of something whose two high-order bits are the
9959              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9960           if (num_sign_bit_copies (op0, mode) >= 2)
9961             {
9962               op0 = XEXP (op0, 0);
9963               code = swap_condition (code);
9964               continue;
9965             }
9966           break;
9967
9968         case ROTATE:
9969           /* If we are testing equality and our count is a constant, we
9970              can perform the inverse operation on our RHS.  */
9971           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9972               && (tem = simplify_binary_operation (ROTATERT, mode,
9973                                                    op1, XEXP (op0, 1))) != 0)
9974             {
9975               op0 = XEXP (op0, 0);
9976               op1 = tem;
9977               continue;
9978             }
9979
9980           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9981              a particular bit.  Convert it to an AND of a constant of that
9982              bit.  This will be converted into a ZERO_EXTRACT.  */
9983           if (const_op == 0 && sign_bit_comparison_p
9984               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9985               && mode_width <= HOST_BITS_PER_WIDE_INT)
9986             {
9987               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9988                                             ((HOST_WIDE_INT) 1
9989                                              << (mode_width - 1
9990                                                  - INTVAL (XEXP (op0, 1)))));
9991               code = (code == LT ? NE : EQ);
9992               continue;
9993             }
9994
9995           /* Fall through.  */
9996
9997         case ABS:
9998           /* ABS is ignorable inside an equality comparison with zero.  */
9999           if (const_op == 0 && equality_comparison_p)
10000             {
10001               op0 = XEXP (op0, 0);
10002               continue;
10003             }
10004           break;
10005
10006         case SIGN_EXTEND:
10007           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10008              (compare FOO CONST) if CONST fits in FOO's mode and we
10009              are either testing inequality or have an unsigned
10010              comparison with ZERO_EXTEND or a signed comparison with
10011              SIGN_EXTEND.  But don't do it if we don't have a compare
10012              insn of the given mode, since we'd have to revert it
10013              later on, and then we wouldn't know whether to sign- or
10014              zero-extend.  */
10015           mode = GET_MODE (XEXP (op0, 0));
10016           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10017               && ! unsigned_comparison_p
10018               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10019               && ((unsigned HOST_WIDE_INT) const_op
10020                   < (((unsigned HOST_WIDE_INT) 1
10021                       << (GET_MODE_BITSIZE (mode) - 1))))
10022               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10023             {
10024               op0 = XEXP (op0, 0);
10025               continue;
10026             }
10027           break;
10028
10029         case SUBREG:
10030           /* Check for the case where we are comparing A - C1 with C2, that is
10031
10032                (subreg:MODE (plus (A) (-C1))) op (C2)
10033
10034              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10035              comparison in the wider mode.  One of the following two conditions
10036              must be true in order for this to be valid:
10037
10038                1. The mode extension results in the same bit pattern being added
10039                   on both sides and the comparison is equality or unsigned.  As
10040                   C2 has been truncated to fit in MODE, the pattern can only be
10041                   all 0s or all 1s.
10042
10043                2. The mode extension results in the sign bit being copied on
10044                   each side.
10045
10046              The difficulty here is that we have predicates for A but not for
10047              (A - C1) so we need to check that C1 is within proper bounds so
10048              as to perturbate A as little as possible.  */
10049
10050           if (mode_width <= HOST_BITS_PER_WIDE_INT
10051               && subreg_lowpart_p (op0)
10052               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10053               && GET_CODE (SUBREG_REG (op0)) == PLUS
10054               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10055             {
10056               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10057               rtx a = XEXP (SUBREG_REG (op0), 0);
10058               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10059
10060               if ((c1 > 0
10061                    && (unsigned HOST_WIDE_INT) c1
10062                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10063                    && (equality_comparison_p || unsigned_comparison_p)
10064                    /* (A - C1) zero-extends if it is positive and sign-extends
10065                       if it is negative, C2 both zero- and sign-extends.  */
10066                    && ((0 == (nonzero_bits (a, inner_mode)
10067                               & ~GET_MODE_MASK (mode))
10068                         && const_op >= 0)
10069                        /* (A - C1) sign-extends if it is positive and 1-extends
10070                           if it is negative, C2 both sign- and 1-extends.  */
10071                        || (num_sign_bit_copies (a, inner_mode)
10072                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10073                                              - mode_width)
10074                            && const_op < 0)))
10075                   || ((unsigned HOST_WIDE_INT) c1
10076                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10077                       /* (A - C1) always sign-extends, like C2.  */
10078                       && num_sign_bit_copies (a, inner_mode)
10079                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10080                                            - (mode_width - 1))))
10081                 {
10082                   op0 = SUBREG_REG (op0);
10083                   continue;
10084                 }
10085             }
10086
10087           /* If the inner mode is narrower and we are extracting the low part,
10088              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10089           if (subreg_lowpart_p (op0)
10090               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10091             /* Fall through */ ;
10092           else
10093             break;
10094
10095           /* ... fall through ...  */
10096
10097         case ZERO_EXTEND:
10098           mode = GET_MODE (XEXP (op0, 0));
10099           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10100               && (unsigned_comparison_p || equality_comparison_p)
10101               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10102               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10103               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10104             {
10105               op0 = XEXP (op0, 0);
10106               continue;
10107             }
10108           break;
10109
10110         case PLUS:
10111           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10112              this for equality comparisons due to pathological cases involving
10113              overflows.  */
10114           if (equality_comparison_p
10115               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10116                                                         op1, XEXP (op0, 1))))
10117             {
10118               op0 = XEXP (op0, 0);
10119               op1 = tem;
10120               continue;
10121             }
10122
10123           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10124           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10125               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10126             {
10127               op0 = XEXP (XEXP (op0, 0), 0);
10128               code = (code == LT ? EQ : NE);
10129               continue;
10130             }
10131           break;
10132
10133         case MINUS:
10134           /* We used to optimize signed comparisons against zero, but that
10135              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10136              arrive here as equality comparisons, or (GEU, LTU) are
10137              optimized away.  No need to special-case them.  */
10138
10139           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10140              (eq B (minus A C)), whichever simplifies.  We can only do
10141              this for equality comparisons due to pathological cases involving
10142              overflows.  */
10143           if (equality_comparison_p
10144               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10145                                                         XEXP (op0, 1), op1)))
10146             {
10147               op0 = XEXP (op0, 0);
10148               op1 = tem;
10149               continue;
10150             }
10151
10152           if (equality_comparison_p
10153               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10154                                                         XEXP (op0, 0), op1)))
10155             {
10156               op0 = XEXP (op0, 1);
10157               op1 = tem;
10158               continue;
10159             }
10160
10161           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10162              of bits in X minus 1, is one iff X > 0.  */
10163           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10164               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10165               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10166                  == mode_width - 1
10167               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10168             {
10169               op0 = XEXP (op0, 1);
10170               code = (code == GE ? LE : GT);
10171               continue;
10172             }
10173           break;
10174
10175         case XOR:
10176           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10177              if C is zero or B is a constant.  */
10178           if (equality_comparison_p
10179               && 0 != (tem = simplify_binary_operation (XOR, mode,
10180                                                         XEXP (op0, 1), op1)))
10181             {
10182               op0 = XEXP (op0, 0);
10183               op1 = tem;
10184               continue;
10185             }
10186           break;
10187
10188         case EQ:  case NE:
10189         case UNEQ:  case LTGT:
10190         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10191         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10192         case UNORDERED: case ORDERED:
10193           /* We can't do anything if OP0 is a condition code value, rather
10194              than an actual data value.  */
10195           if (const_op != 0
10196               || CC0_P (XEXP (op0, 0))
10197               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10198             break;
10199
10200           /* Get the two operands being compared.  */
10201           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10202             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10203           else
10204             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10205
10206           /* Check for the cases where we simply want the result of the
10207              earlier test or the opposite of that result.  */
10208           if (code == NE || code == EQ
10209               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10210                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10211                   && (STORE_FLAG_VALUE
10212                       & (((HOST_WIDE_INT) 1
10213                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10214                   && (code == LT || code == GE)))
10215             {
10216               enum rtx_code new_code;
10217               if (code == LT || code == NE)
10218                 new_code = GET_CODE (op0);
10219               else
10220                 new_code = reversed_comparison_code (op0, NULL);
10221
10222               if (new_code != UNKNOWN)
10223                 {
10224                   code = new_code;
10225                   op0 = tem;
10226                   op1 = tem1;
10227                   continue;
10228                 }
10229             }
10230           break;
10231
10232         case IOR:
10233           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10234              iff X <= 0.  */
10235           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10236               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10237               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10238             {
10239               op0 = XEXP (op0, 1);
10240               code = (code == GE ? GT : LE);
10241               continue;
10242             }
10243           break;
10244
10245         case AND:
10246           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10247              will be converted to a ZERO_EXTRACT later.  */
10248           if (const_op == 0 && equality_comparison_p
10249               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10250               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10251             {
10252               op0 = simplify_and_const_int
10253                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10254                                                    XEXP (op0, 1),
10255                                                    XEXP (XEXP (op0, 0), 1)),
10256                  (HOST_WIDE_INT) 1);
10257               continue;
10258             }
10259
10260           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10261              zero and X is a comparison and C1 and C2 describe only bits set
10262              in STORE_FLAG_VALUE, we can compare with X.  */
10263           if (const_op == 0 && equality_comparison_p
10264               && mode_width <= HOST_BITS_PER_WIDE_INT
10265               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10266               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10267               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10268               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10269               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10270             {
10271               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10272                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10273               if ((~STORE_FLAG_VALUE & mask) == 0
10274                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10275                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10276                           && COMPARISON_P (tem))))
10277                 {
10278                   op0 = XEXP (XEXP (op0, 0), 0);
10279                   continue;
10280                 }
10281             }
10282
10283           /* If we are doing an equality comparison of an AND of a bit equal
10284              to the sign bit, replace this with a LT or GE comparison of
10285              the underlying value.  */
10286           if (equality_comparison_p
10287               && const_op == 0
10288               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10289               && mode_width <= HOST_BITS_PER_WIDE_INT
10290               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10291                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10292             {
10293               op0 = XEXP (op0, 0);
10294               code = (code == EQ ? GE : LT);
10295               continue;
10296             }
10297
10298           /* If this AND operation is really a ZERO_EXTEND from a narrower
10299              mode, the constant fits within that mode, and this is either an
10300              equality or unsigned comparison, try to do this comparison in
10301              the narrower mode.
10302
10303              Note that in:
10304
10305              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10306              -> (ne:DI (reg:SI 4) (const_int 0))
10307
10308              unless TRULY_NOOP_TRUNCATION allows it or the register is
10309              known to hold a value of the required mode the
10310              transformation is invalid.  */
10311           if ((equality_comparison_p || unsigned_comparison_p)
10312               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10313               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10314                                    & GET_MODE_MASK (mode))
10315                                   + 1)) >= 0
10316               && const_op >> i == 0
10317               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10318               && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10319                                          GET_MODE_BITSIZE (GET_MODE (op0)))
10320                   || (REG_P (XEXP (op0, 0))
10321                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10322             {
10323               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10324               continue;
10325             }
10326
10327           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10328              fits in both M1 and M2 and the SUBREG is either paradoxical
10329              or represents the low part, permute the SUBREG and the AND
10330              and try again.  */
10331           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10332             {
10333               unsigned HOST_WIDE_INT c1;
10334               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10335               /* Require an integral mode, to avoid creating something like
10336                  (AND:SF ...).  */
10337               if (SCALAR_INT_MODE_P (tmode)
10338                   /* It is unsafe to commute the AND into the SUBREG if the
10339                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10340                      not defined.  As originally written the upper bits
10341                      have a defined value due to the AND operation.
10342                      However, if we commute the AND inside the SUBREG then
10343                      they no longer have defined values and the meaning of
10344                      the code has been changed.  */
10345                   && (0
10346 #ifdef WORD_REGISTER_OPERATIONS
10347                       || (mode_width > GET_MODE_BITSIZE (tmode)
10348                           && mode_width <= BITS_PER_WORD)
10349 #endif
10350                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10351                           && subreg_lowpart_p (XEXP (op0, 0))))
10352                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10353                   && mode_width <= HOST_BITS_PER_WIDE_INT
10354                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10355                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10356                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10357                   && c1 != mask
10358                   && c1 != GET_MODE_MASK (tmode))
10359                 {
10360                   op0 = simplify_gen_binary (AND, tmode,
10361                                              SUBREG_REG (XEXP (op0, 0)),
10362                                              gen_int_mode (c1, tmode));
10363                   op0 = gen_lowpart (mode, op0);
10364                   continue;
10365                 }
10366             }
10367
10368           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10369           if (const_op == 0 && equality_comparison_p
10370               && XEXP (op0, 1) == const1_rtx
10371               && GET_CODE (XEXP (op0, 0)) == NOT)
10372             {
10373               op0 = simplify_and_const_int
10374                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10375               code = (code == NE ? EQ : NE);
10376               continue;
10377             }
10378
10379           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10380              (eq (and (lshiftrt X) 1) 0).
10381              Also handle the case where (not X) is expressed using xor.  */
10382           if (const_op == 0 && equality_comparison_p
10383               && XEXP (op0, 1) == const1_rtx
10384               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10385             {
10386               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10387               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10388
10389               if (GET_CODE (shift_op) == NOT
10390                   || (GET_CODE (shift_op) == XOR
10391                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10392                       && GET_CODE (shift_count) == CONST_INT
10393                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10394                       && (INTVAL (XEXP (shift_op, 1))
10395                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10396                 {
10397                   op0 = simplify_and_const_int
10398                     (NULL_RTX, mode,
10399                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10400                      (HOST_WIDE_INT) 1);
10401                   code = (code == NE ? EQ : NE);
10402                   continue;
10403                 }
10404             }
10405           break;
10406
10407         case ASHIFT:
10408           /* If we have (compare (ashift FOO N) (const_int C)) and
10409              the high order N bits of FOO (N+1 if an inequality comparison)
10410              are known to be zero, we can do this by comparing FOO with C
10411              shifted right N bits so long as the low-order N bits of C are
10412              zero.  */
10413           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10414               && INTVAL (XEXP (op0, 1)) >= 0
10415               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10416                   < HOST_BITS_PER_WIDE_INT)
10417               && ((const_op
10418                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10419               && mode_width <= HOST_BITS_PER_WIDE_INT
10420               && (nonzero_bits (XEXP (op0, 0), mode)
10421                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10422                                + ! equality_comparison_p))) == 0)
10423             {
10424               /* We must perform a logical shift, not an arithmetic one,
10425                  as we want the top N bits of C to be zero.  */
10426               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10427
10428               temp >>= INTVAL (XEXP (op0, 1));
10429               op1 = gen_int_mode (temp, mode);
10430               op0 = XEXP (op0, 0);
10431               continue;
10432             }
10433
10434           /* If we are doing a sign bit comparison, it means we are testing
10435              a particular bit.  Convert it to the appropriate AND.  */
10436           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10437               && mode_width <= HOST_BITS_PER_WIDE_INT)
10438             {
10439               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10440                                             ((HOST_WIDE_INT) 1
10441                                              << (mode_width - 1
10442                                                  - INTVAL (XEXP (op0, 1)))));
10443               code = (code == LT ? NE : EQ);
10444               continue;
10445             }
10446
10447           /* If this an equality comparison with zero and we are shifting
10448              the low bit to the sign bit, we can convert this to an AND of the
10449              low-order bit.  */
10450           if (const_op == 0 && equality_comparison_p
10451               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10452               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10453                  == mode_width - 1)
10454             {
10455               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10456                                             (HOST_WIDE_INT) 1);
10457               continue;
10458             }
10459           break;
10460
10461         case ASHIFTRT:
10462           /* If this is an equality comparison with zero, we can do this
10463              as a logical shift, which might be much simpler.  */
10464           if (equality_comparison_p && const_op == 0
10465               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10466             {
10467               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10468                                           XEXP (op0, 0),
10469                                           INTVAL (XEXP (op0, 1)));
10470               continue;
10471             }
10472
10473           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10474              do the comparison in a narrower mode.  */
10475           if (! unsigned_comparison_p
10476               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10477               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10478               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10479               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10480                                          MODE_INT, 1)) != BLKmode
10481               && (((unsigned HOST_WIDE_INT) const_op
10482                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10483                   <= GET_MODE_MASK (tmode)))
10484             {
10485               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10486               continue;
10487             }
10488
10489           /* Likewise if OP0 is a PLUS of a sign extension with a
10490              constant, which is usually represented with the PLUS
10491              between the shifts.  */
10492           if (! unsigned_comparison_p
10493               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10494               && GET_CODE (XEXP (op0, 0)) == PLUS
10495               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10496               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10497               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10498               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10499                                          MODE_INT, 1)) != BLKmode
10500               && (((unsigned HOST_WIDE_INT) const_op
10501                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10502                   <= GET_MODE_MASK (tmode)))
10503             {
10504               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10505               rtx add_const = XEXP (XEXP (op0, 0), 1);
10506               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10507                                                    add_const, XEXP (op0, 1));
10508
10509               op0 = simplify_gen_binary (PLUS, tmode,
10510                                          gen_lowpart (tmode, inner),
10511                                          new_const);
10512               continue;
10513             }
10514
10515           /* ... fall through ...  */
10516         case LSHIFTRT:
10517           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10518              the low order N bits of FOO are known to be zero, we can do this
10519              by comparing FOO with C shifted left N bits so long as no
10520              overflow occurs.  */
10521           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10522               && INTVAL (XEXP (op0, 1)) >= 0
10523               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10524               && mode_width <= HOST_BITS_PER_WIDE_INT
10525               && (nonzero_bits (XEXP (op0, 0), mode)
10526                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10527               && (((unsigned HOST_WIDE_INT) const_op
10528                    + (GET_CODE (op0) != LSHIFTRT
10529                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10530                          + 1)
10531                       : 0))
10532                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10533             {
10534               /* If the shift was logical, then we must make the condition
10535                  unsigned.  */
10536               if (GET_CODE (op0) == LSHIFTRT)
10537                 code = unsigned_condition (code);
10538
10539               const_op <<= INTVAL (XEXP (op0, 1));
10540               op1 = GEN_INT (const_op);
10541               op0 = XEXP (op0, 0);
10542               continue;
10543             }
10544
10545           /* If we are using this shift to extract just the sign bit, we
10546              can replace this with an LT or GE comparison.  */
10547           if (const_op == 0
10548               && (equality_comparison_p || sign_bit_comparison_p)
10549               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10550               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10551                  == mode_width - 1)
10552             {
10553               op0 = XEXP (op0, 0);
10554               code = (code == NE || code == GT ? LT : GE);
10555               continue;
10556             }
10557           break;
10558
10559         default:
10560           break;
10561         }
10562
10563       break;
10564     }
10565
10566   /* Now make any compound operations involved in this comparison.  Then,
10567      check for an outmost SUBREG on OP0 that is not doing anything or is
10568      paradoxical.  The latter transformation must only be performed when
10569      it is known that the "extra" bits will be the same in op0 and op1 or
10570      that they don't matter.  There are three cases to consider:
10571
10572      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10573      care bits and we can assume they have any convenient value.  So
10574      making the transformation is safe.
10575
10576      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10577      In this case the upper bits of op0 are undefined.  We should not make
10578      the simplification in that case as we do not know the contents of
10579      those bits.
10580
10581      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10582      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10583      also be sure that they are the same as the upper bits of op1.
10584
10585      We can never remove a SUBREG for a non-equality comparison because
10586      the sign bit is in a different place in the underlying object.  */
10587
10588   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10589   op1 = make_compound_operation (op1, SET);
10590
10591   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10592       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10593       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10594       && (code == NE || code == EQ))
10595     {
10596       if (GET_MODE_SIZE (GET_MODE (op0))
10597           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10598         {
10599           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10600              implemented.  */
10601           if (REG_P (SUBREG_REG (op0)))
10602             {
10603               op0 = SUBREG_REG (op0);
10604               op1 = gen_lowpart (GET_MODE (op0), op1);
10605             }
10606         }
10607       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10608                 <= HOST_BITS_PER_WIDE_INT)
10609                && (nonzero_bits (SUBREG_REG (op0),
10610                                  GET_MODE (SUBREG_REG (op0)))
10611                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10612         {
10613           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10614
10615           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10616                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10617             op0 = SUBREG_REG (op0), op1 = tem;
10618         }
10619     }
10620
10621   /* We now do the opposite procedure: Some machines don't have compare
10622      insns in all modes.  If OP0's mode is an integer mode smaller than a
10623      word and we can't do a compare in that mode, see if there is a larger
10624      mode for which we can do the compare.  There are a number of cases in
10625      which we can use the wider mode.  */
10626
10627   mode = GET_MODE (op0);
10628   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10629       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10630       && ! have_insn_for (COMPARE, mode))
10631     for (tmode = GET_MODE_WIDER_MODE (mode);
10632          (tmode != VOIDmode
10633           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10634          tmode = GET_MODE_WIDER_MODE (tmode))
10635       if (have_insn_for (COMPARE, tmode))
10636         {
10637           int zero_extended;
10638
10639           /* If the only nonzero bits in OP0 and OP1 are those in the
10640              narrower mode and this is an equality or unsigned comparison,
10641              we can use the wider mode.  Similarly for sign-extended
10642              values, in which case it is true for all comparisons.  */
10643           zero_extended = ((code == EQ || code == NE
10644                             || code == GEU || code == GTU
10645                             || code == LEU || code == LTU)
10646                            && (nonzero_bits (op0, tmode)
10647                                & ~GET_MODE_MASK (mode)) == 0
10648                            && ((GET_CODE (op1) == CONST_INT
10649                                 || (nonzero_bits (op1, tmode)
10650                                     & ~GET_MODE_MASK (mode)) == 0)));
10651
10652           if (zero_extended
10653               || ((num_sign_bit_copies (op0, tmode)
10654                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10655                                      - GET_MODE_BITSIZE (mode)))
10656                   && (num_sign_bit_copies (op1, tmode)
10657                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10658                                         - GET_MODE_BITSIZE (mode)))))
10659             {
10660               /* If OP0 is an AND and we don't have an AND in MODE either,
10661                  make a new AND in the proper mode.  */
10662               if (GET_CODE (op0) == AND
10663                   && !have_insn_for (AND, mode))
10664                 op0 = simplify_gen_binary (AND, tmode,
10665                                            gen_lowpart (tmode,
10666                                                         XEXP (op0, 0)),
10667                                            gen_lowpart (tmode,
10668                                                         XEXP (op0, 1)));
10669
10670               op0 = gen_lowpart (tmode, op0);
10671               if (zero_extended && GET_CODE (op1) == CONST_INT)
10672                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10673               op1 = gen_lowpart (tmode, op1);
10674               break;
10675             }
10676
10677           /* If this is a test for negative, we can make an explicit
10678              test of the sign bit.  */
10679
10680           if (op1 == const0_rtx && (code == LT || code == GE)
10681               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10682             {
10683               op0 = simplify_gen_binary (AND, tmode,
10684                                          gen_lowpart (tmode, op0),
10685                                          GEN_INT ((HOST_WIDE_INT) 1
10686                                                   << (GET_MODE_BITSIZE (mode)
10687                                                       - 1)));
10688               code = (code == LT) ? NE : EQ;
10689               break;
10690             }
10691         }
10692
10693 #ifdef CANONICALIZE_COMPARISON
10694   /* If this machine only supports a subset of valid comparisons, see if we
10695      can convert an unsupported one into a supported one.  */
10696   CANONICALIZE_COMPARISON (code, op0, op1);
10697 #endif
10698
10699   *pop0 = op0;
10700   *pop1 = op1;
10701
10702   return code;
10703 }
10704 \f
10705 /* Utility function for record_value_for_reg.  Count number of
10706    rtxs in X.  */
10707 static int
10708 count_rtxs (rtx x)
10709 {
10710   enum rtx_code code = GET_CODE (x);
10711   const char *fmt;
10712   int i, ret = 1;
10713
10714   if (GET_RTX_CLASS (code) == '2'
10715       || GET_RTX_CLASS (code) == 'c')
10716     {
10717       rtx x0 = XEXP (x, 0);
10718       rtx x1 = XEXP (x, 1);
10719
10720       if (x0 == x1)
10721         return 1 + 2 * count_rtxs (x0);
10722
10723       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10724            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10725           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10726         return 2 + 2 * count_rtxs (x0)
10727                + count_rtxs (x == XEXP (x1, 0)
10728                              ? XEXP (x1, 1) : XEXP (x1, 0));
10729
10730       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10731            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10732           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10733         return 2 + 2 * count_rtxs (x1)
10734                + count_rtxs (x == XEXP (x0, 0)
10735                              ? XEXP (x0, 1) : XEXP (x0, 0));
10736     }
10737
10738   fmt = GET_RTX_FORMAT (code);
10739   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10740     if (fmt[i] == 'e')
10741       ret += count_rtxs (XEXP (x, i));
10742
10743   return ret;
10744 }
10745 \f
10746 /* Utility function for following routine.  Called when X is part of a value
10747    being stored into last_set_value.  Sets last_set_table_tick
10748    for each register mentioned.  Similar to mention_regs in cse.c  */
10749
10750 static void
10751 update_table_tick (rtx x)
10752 {
10753   enum rtx_code code = GET_CODE (x);
10754   const char *fmt = GET_RTX_FORMAT (code);
10755   int i;
10756
10757   if (code == REG)
10758     {
10759       unsigned int regno = REGNO (x);
10760       unsigned int endregno
10761         = regno + (regno < FIRST_PSEUDO_REGISTER
10762                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10763       unsigned int r;
10764
10765       for (r = regno; r < endregno; r++)
10766         reg_stat[r].last_set_table_tick = label_tick;
10767
10768       return;
10769     }
10770
10771   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10772     /* Note that we can't have an "E" in values stored; see
10773        get_last_value_validate.  */
10774     if (fmt[i] == 'e')
10775       {
10776         /* Check for identical subexpressions.  If x contains
10777            identical subexpression we only have to traverse one of
10778            them.  */
10779         if (i == 0 && ARITHMETIC_P (x))
10780           {
10781             /* Note that at this point x1 has already been
10782                processed.  */
10783             rtx x0 = XEXP (x, 0);
10784             rtx x1 = XEXP (x, 1);
10785
10786             /* If x0 and x1 are identical then there is no need to
10787                process x0.  */
10788             if (x0 == x1)
10789               break;
10790
10791             /* If x0 is identical to a subexpression of x1 then while
10792                processing x1, x0 has already been processed.  Thus we
10793                are done with x.  */
10794             if (ARITHMETIC_P (x1)
10795                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10796               break;
10797
10798             /* If x1 is identical to a subexpression of x0 then we
10799                still have to process the rest of x0.  */
10800             if (ARITHMETIC_P (x0)
10801                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10802               {
10803                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10804                 break;
10805               }
10806           }
10807
10808         update_table_tick (XEXP (x, i));
10809       }
10810 }
10811
10812 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10813    are saying that the register is clobbered and we no longer know its
10814    value.  If INSN is zero, don't update reg_stat[].last_set; this is
10815    only permitted with VALUE also zero and is used to invalidate the
10816    register.  */
10817
10818 static void
10819 record_value_for_reg (rtx reg, rtx insn, rtx value)
10820 {
10821   unsigned int regno = REGNO (reg);
10822   unsigned int endregno
10823     = regno + (regno < FIRST_PSEUDO_REGISTER
10824                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10825   unsigned int i;
10826
10827   /* If VALUE contains REG and we have a previous value for REG, substitute
10828      the previous value.  */
10829   if (value && insn && reg_overlap_mentioned_p (reg, value))
10830     {
10831       rtx tem;
10832
10833       /* Set things up so get_last_value is allowed to see anything set up to
10834          our insn.  */
10835       subst_low_cuid = INSN_CUID (insn);
10836       tem = get_last_value (reg);
10837
10838       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10839          it isn't going to be useful and will take a lot of time to process,
10840          so just use the CLOBBER.  */
10841
10842       if (tem)
10843         {
10844           if (ARITHMETIC_P (tem)
10845               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10846               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10847             tem = XEXP (tem, 0);
10848           else if (count_occurrences (value, reg, 1) >= 2)
10849             {
10850               /* If there are two or more occurrences of REG in VALUE,
10851                  prevent the value from growing too much.  */
10852               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10853                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10854             }
10855
10856           value = replace_rtx (copy_rtx (value), reg, tem);
10857         }
10858     }
10859
10860   /* For each register modified, show we don't know its value, that
10861      we don't know about its bitwise content, that its value has been
10862      updated, and that we don't know the location of the death of the
10863      register.  */
10864   for (i = regno; i < endregno; i++)
10865     {
10866       if (insn)
10867         reg_stat[i].last_set = insn;
10868
10869       reg_stat[i].last_set_value = 0;
10870       reg_stat[i].last_set_mode = 0;
10871       reg_stat[i].last_set_nonzero_bits = 0;
10872       reg_stat[i].last_set_sign_bit_copies = 0;
10873       reg_stat[i].last_death = 0;
10874       reg_stat[i].truncated_to_mode = 0;
10875     }
10876
10877   /* Mark registers that are being referenced in this value.  */
10878   if (value)
10879     update_table_tick (value);
10880
10881   /* Now update the status of each register being set.
10882      If someone is using this register in this block, set this register
10883      to invalid since we will get confused between the two lives in this
10884      basic block.  This makes using this register always invalid.  In cse, we
10885      scan the table to invalidate all entries using this register, but this
10886      is too much work for us.  */
10887
10888   for (i = regno; i < endregno; i++)
10889     {
10890       reg_stat[i].last_set_label = label_tick;
10891       if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10892         reg_stat[i].last_set_invalid = 1;
10893       else
10894         reg_stat[i].last_set_invalid = 0;
10895     }
10896
10897   /* The value being assigned might refer to X (like in "x++;").  In that
10898      case, we must replace it with (clobber (const_int 0)) to prevent
10899      infinite loops.  */
10900   if (value && ! get_last_value_validate (&value, insn,
10901                                           reg_stat[regno].last_set_label, 0))
10902     {
10903       value = copy_rtx (value);
10904       if (! get_last_value_validate (&value, insn,
10905                                      reg_stat[regno].last_set_label, 1))
10906         value = 0;
10907     }
10908
10909   /* For the main register being modified, update the value, the mode, the
10910      nonzero bits, and the number of sign bit copies.  */
10911
10912   reg_stat[regno].last_set_value = value;
10913
10914   if (value)
10915     {
10916       enum machine_mode mode = GET_MODE (reg);
10917       subst_low_cuid = INSN_CUID (insn);
10918       reg_stat[regno].last_set_mode = mode;
10919       if (GET_MODE_CLASS (mode) == MODE_INT
10920           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10921         mode = nonzero_bits_mode;
10922       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10923       reg_stat[regno].last_set_sign_bit_copies
10924         = num_sign_bit_copies (value, GET_MODE (reg));
10925     }
10926 }
10927
10928 /* Called via note_stores from record_dead_and_set_regs to handle one
10929    SET or CLOBBER in an insn.  DATA is the instruction in which the
10930    set is occurring.  */
10931
10932 static void
10933 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10934 {
10935   rtx record_dead_insn = (rtx) data;
10936
10937   if (GET_CODE (dest) == SUBREG)
10938     dest = SUBREG_REG (dest);
10939
10940   if (!record_dead_insn)
10941     {
10942       if (REG_P (dest))
10943         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10944       return;
10945     }
10946
10947   if (REG_P (dest))
10948     {
10949       /* If we are setting the whole register, we know its value.  Otherwise
10950          show that we don't know the value.  We can handle SUBREG in
10951          some cases.  */
10952       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10953         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10954       else if (GET_CODE (setter) == SET
10955                && GET_CODE (SET_DEST (setter)) == SUBREG
10956                && SUBREG_REG (SET_DEST (setter)) == dest
10957                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10958                && subreg_lowpart_p (SET_DEST (setter)))
10959         record_value_for_reg (dest, record_dead_insn,
10960                               gen_lowpart (GET_MODE (dest),
10961                                                        SET_SRC (setter)));
10962       else
10963         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10964     }
10965   else if (MEM_P (dest)
10966            /* Ignore pushes, they clobber nothing.  */
10967            && ! push_operand (dest, GET_MODE (dest)))
10968     mem_last_set = INSN_CUID (record_dead_insn);
10969 }
10970
10971 /* Update the records of when each REG was most recently set or killed
10972    for the things done by INSN.  This is the last thing done in processing
10973    INSN in the combiner loop.
10974
10975    We update reg_stat[], in particular fields last_set, last_set_value,
10976    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10977    last_death, and also the similar information mem_last_set (which insn
10978    most recently modified memory) and last_call_cuid (which insn was the
10979    most recent subroutine call).  */
10980
10981 static void
10982 record_dead_and_set_regs (rtx insn)
10983 {
10984   rtx link;
10985   unsigned int i;
10986
10987   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10988     {
10989       if (REG_NOTE_KIND (link) == REG_DEAD
10990           && REG_P (XEXP (link, 0)))
10991         {
10992           unsigned int regno = REGNO (XEXP (link, 0));
10993           unsigned int endregno
10994             = regno + (regno < FIRST_PSEUDO_REGISTER
10995                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10996                        : 1);
10997
10998           for (i = regno; i < endregno; i++)
10999             reg_stat[i].last_death = insn;
11000         }
11001       else if (REG_NOTE_KIND (link) == REG_INC)
11002         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11003     }
11004
11005   if (CALL_P (insn))
11006     {
11007       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11008         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11009           {
11010             reg_stat[i].last_set_value = 0;
11011             reg_stat[i].last_set_mode = 0;
11012             reg_stat[i].last_set_nonzero_bits = 0;
11013             reg_stat[i].last_set_sign_bit_copies = 0;
11014             reg_stat[i].last_death = 0;
11015             reg_stat[i].truncated_to_mode = 0;
11016           }
11017
11018       last_call_cuid = mem_last_set = INSN_CUID (insn);
11019
11020       /* We can't combine into a call pattern.  Remember, though, that
11021          the return value register is set at this CUID.  We could
11022          still replace a register with the return value from the
11023          wrong subroutine call!  */
11024       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11025     }
11026   else
11027     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11028 }
11029
11030 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11031    register present in the SUBREG, so for each such SUBREG go back and
11032    adjust nonzero and sign bit information of the registers that are
11033    known to have some zero/sign bits set.
11034
11035    This is needed because when combine blows the SUBREGs away, the
11036    information on zero/sign bits is lost and further combines can be
11037    missed because of that.  */
11038
11039 static void
11040 record_promoted_value (rtx insn, rtx subreg)
11041 {
11042   rtx links, set;
11043   unsigned int regno = REGNO (SUBREG_REG (subreg));
11044   enum machine_mode mode = GET_MODE (subreg);
11045
11046   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11047     return;
11048
11049   for (links = LOG_LINKS (insn); links;)
11050     {
11051       insn = XEXP (links, 0);
11052       set = single_set (insn);
11053
11054       if (! set || !REG_P (SET_DEST (set))
11055           || REGNO (SET_DEST (set)) != regno
11056           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11057         {
11058           links = XEXP (links, 1);
11059           continue;
11060         }
11061
11062       if (reg_stat[regno].last_set == insn)
11063         {
11064           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11065             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11066         }
11067
11068       if (REG_P (SET_SRC (set)))
11069         {
11070           regno = REGNO (SET_SRC (set));
11071           links = LOG_LINKS (insn);
11072         }
11073       else
11074         break;
11075     }
11076 }
11077
11078 /* Check if X, a register, is known to contain a value already
11079    truncated to MODE.  In this case we can use a subreg to refer to
11080    the truncated value even though in the generic case we would need
11081    an explicit truncation.  */
11082
11083 static bool
11084 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11085 {
11086   enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11087
11088   if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11089     return false;
11090   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11091     return true;
11092   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11093                              GET_MODE_BITSIZE (truncated)))
11094     return true;
11095   return false;
11096 }
11097
11098 /* X is a REG or a SUBREG.  If X is some sort of a truncation record
11099    it.  For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11100    a truncate into a subreg using this information.  */
11101
11102 static void
11103 record_truncated_value (rtx x)
11104 {
11105   enum machine_mode truncated_mode;
11106
11107   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11108     {
11109       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11110       truncated_mode = GET_MODE (x);
11111
11112       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11113         return;
11114
11115       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11116                                  GET_MODE_BITSIZE (original_mode)))
11117         return;
11118
11119       x = SUBREG_REG (x);
11120     }
11121   /* ??? For hard-regs we now record everthing.  We might be able to
11122      optimize this using last_set_mode.  */
11123   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11124     truncated_mode = GET_MODE (x);
11125   else
11126     return;
11127
11128   if (reg_stat[REGNO (x)].truncated_to_mode == 0
11129       || reg_stat[REGNO (x)].truncation_label < label_tick
11130       || (GET_MODE_SIZE (truncated_mode)
11131           < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11132     {
11133       reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11134       reg_stat[REGNO (x)].truncation_label = label_tick;
11135     }
11136 }
11137
11138 /* Scan X for promoted SUBREGs and truncated REGs.  For each one
11139    found, note what it implies to the registers used in it.  */
11140
11141 static void
11142 check_conversions (rtx insn, rtx x)
11143 {
11144   if (GET_CODE (x) == SUBREG || REG_P (x))
11145     {
11146       if (GET_CODE (x) == SUBREG
11147           && SUBREG_PROMOTED_VAR_P (x)
11148           && REG_P (SUBREG_REG (x)))
11149         record_promoted_value (insn, x);
11150
11151       record_truncated_value (x);
11152     }
11153   else
11154     {
11155       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11156       int i, j;
11157
11158       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11159         switch (format[i])
11160           {
11161           case 'e':
11162             check_conversions (insn, XEXP (x, i));
11163             break;
11164           case 'V':
11165           case 'E':
11166             if (XVEC (x, i) != 0)
11167               for (j = 0; j < XVECLEN (x, i); j++)
11168                 check_conversions (insn, XVECEXP (x, i, j));
11169             break;
11170           }
11171     }
11172 }
11173 \f
11174 /* Utility routine for the following function.  Verify that all the registers
11175    mentioned in *LOC are valid when *LOC was part of a value set when
11176    label_tick == TICK.  Return 0 if some are not.
11177
11178    If REPLACE is nonzero, replace the invalid reference with
11179    (clobber (const_int 0)) and return 1.  This replacement is useful because
11180    we often can get useful information about the form of a value (e.g., if
11181    it was produced by a shift that always produces -1 or 0) even though
11182    we don't know exactly what registers it was produced from.  */
11183
11184 static int
11185 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11186 {
11187   rtx x = *loc;
11188   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11189   int len = GET_RTX_LENGTH (GET_CODE (x));
11190   int i;
11191
11192   if (REG_P (x))
11193     {
11194       unsigned int regno = REGNO (x);
11195       unsigned int endregno
11196         = regno + (regno < FIRST_PSEUDO_REGISTER
11197                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11198       unsigned int j;
11199
11200       for (j = regno; j < endregno; j++)
11201         if (reg_stat[j].last_set_invalid
11202             /* If this is a pseudo-register that was only set once and not
11203                live at the beginning of the function, it is always valid.  */
11204             || (! (regno >= FIRST_PSEUDO_REGISTER
11205                    && REG_N_SETS (regno) == 1
11206                    && (! REGNO_REG_SET_P
11207                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11208                         regno)))
11209                 && reg_stat[j].last_set_label > tick))
11210           {
11211             if (replace)
11212               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11213             return replace;
11214           }
11215
11216       return 1;
11217     }
11218   /* If this is a memory reference, make sure that there were
11219      no stores after it that might have clobbered the value.  We don't
11220      have alias info, so we assume any store invalidates it.  */
11221   else if (MEM_P (x) && !MEM_READONLY_P (x)
11222            && INSN_CUID (insn) <= mem_last_set)
11223     {
11224       if (replace)
11225         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11226       return replace;
11227     }
11228
11229   for (i = 0; i < len; i++)
11230     {
11231       if (fmt[i] == 'e')
11232         {
11233           /* Check for identical subexpressions.  If x contains
11234              identical subexpression we only have to traverse one of
11235              them.  */
11236           if (i == 1 && ARITHMETIC_P (x))
11237             {
11238               /* Note that at this point x0 has already been checked
11239                  and found valid.  */
11240               rtx x0 = XEXP (x, 0);
11241               rtx x1 = XEXP (x, 1);
11242
11243               /* If x0 and x1 are identical then x is also valid.  */
11244               if (x0 == x1)
11245                 return 1;
11246
11247               /* If x1 is identical to a subexpression of x0 then
11248                  while checking x0, x1 has already been checked.  Thus
11249                  it is valid and so as x.  */
11250               if (ARITHMETIC_P (x0)
11251                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11252                 return 1;
11253
11254               /* If x0 is identical to a subexpression of x1 then x is
11255                  valid iff the rest of x1 is valid.  */
11256               if (ARITHMETIC_P (x1)
11257                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11258                 return
11259                   get_last_value_validate (&XEXP (x1,
11260                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11261                                            insn, tick, replace);
11262             }
11263
11264           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11265                                        replace) == 0)
11266             return 0;
11267         }
11268       /* Don't bother with these.  They shouldn't occur anyway.  */
11269       else if (fmt[i] == 'E')
11270         return 0;
11271     }
11272
11273   /* If we haven't found a reason for it to be invalid, it is valid.  */
11274   return 1;
11275 }
11276
11277 /* Get the last value assigned to X, if known.  Some registers
11278    in the value may be replaced with (clobber (const_int 0)) if their value
11279    is known longer known reliably.  */
11280
11281 static rtx
11282 get_last_value (rtx x)
11283 {
11284   unsigned int regno;
11285   rtx value;
11286
11287   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11288      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11289      we cannot predict what values the "extra" bits might have.  */
11290   if (GET_CODE (x) == SUBREG
11291       && subreg_lowpart_p (x)
11292       && (GET_MODE_SIZE (GET_MODE (x))
11293           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11294       && (value = get_last_value (SUBREG_REG (x))) != 0)
11295     return gen_lowpart (GET_MODE (x), value);
11296
11297   if (!REG_P (x))
11298     return 0;
11299
11300   regno = REGNO (x);
11301   value = reg_stat[regno].last_set_value;
11302
11303   /* If we don't have a value, or if it isn't for this basic block and
11304      it's either a hard register, set more than once, or it's a live
11305      at the beginning of the function, return 0.
11306
11307      Because if it's not live at the beginning of the function then the reg
11308      is always set before being used (is never used without being set).
11309      And, if it's set only once, and it's always set before use, then all
11310      uses must have the same last value, even if it's not from this basic
11311      block.  */
11312
11313   if (value == 0
11314       || (reg_stat[regno].last_set_label != label_tick
11315           && (regno < FIRST_PSEUDO_REGISTER
11316               || REG_N_SETS (regno) != 1
11317               || (REGNO_REG_SET_P
11318                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11319                    regno)))))
11320     return 0;
11321
11322   /* If the value was set in a later insn than the ones we are processing,
11323      we can't use it even if the register was only set once.  */
11324   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11325     return 0;
11326
11327   /* If the value has all its registers valid, return it.  */
11328   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11329                                reg_stat[regno].last_set_label, 0))
11330     return value;
11331
11332   /* Otherwise, make a copy and replace any invalid register with
11333      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11334
11335   value = copy_rtx (value);
11336   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11337                                reg_stat[regno].last_set_label, 1))
11338     return value;
11339
11340   return 0;
11341 }
11342 \f
11343 /* Return nonzero if expression X refers to a REG or to memory
11344    that is set in an instruction more recent than FROM_CUID.  */
11345
11346 static int
11347 use_crosses_set_p (rtx x, int from_cuid)
11348 {
11349   const char *fmt;
11350   int i;
11351   enum rtx_code code = GET_CODE (x);
11352
11353   if (code == REG)
11354     {
11355       unsigned int regno = REGNO (x);
11356       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11357                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11358
11359 #ifdef PUSH_ROUNDING
11360       /* Don't allow uses of the stack pointer to be moved,
11361          because we don't know whether the move crosses a push insn.  */
11362       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11363         return 1;
11364 #endif
11365       for (; regno < endreg; regno++)
11366         if (reg_stat[regno].last_set
11367             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11368           return 1;
11369       return 0;
11370     }
11371
11372   if (code == MEM && mem_last_set > from_cuid)
11373     return 1;
11374
11375   fmt = GET_RTX_FORMAT (code);
11376
11377   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11378     {
11379       if (fmt[i] == 'E')
11380         {
11381           int j;
11382           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11383             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11384               return 1;
11385         }
11386       else if (fmt[i] == 'e'
11387                && use_crosses_set_p (XEXP (x, i), from_cuid))
11388         return 1;
11389     }
11390   return 0;
11391 }
11392 \f
11393 /* Define three variables used for communication between the following
11394    routines.  */
11395
11396 static unsigned int reg_dead_regno, reg_dead_endregno;
11397 static int reg_dead_flag;
11398
11399 /* Function called via note_stores from reg_dead_at_p.
11400
11401    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11402    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11403
11404 static void
11405 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11406 {
11407   unsigned int regno, endregno;
11408
11409   if (!REG_P (dest))
11410     return;
11411
11412   regno = REGNO (dest);
11413   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11414                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11415
11416   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11417     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11418 }
11419
11420 /* Return nonzero if REG is known to be dead at INSN.
11421
11422    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11423    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11424    live.  Otherwise, see if it is live or dead at the start of the basic
11425    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11426    must be assumed to be always live.  */
11427
11428 static int
11429 reg_dead_at_p (rtx reg, rtx insn)
11430 {
11431   basic_block block;
11432   unsigned int i;
11433
11434   /* Set variables for reg_dead_at_p_1.  */
11435   reg_dead_regno = REGNO (reg);
11436   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11437                                         ? hard_regno_nregs[reg_dead_regno]
11438                                                           [GET_MODE (reg)]
11439                                         : 1);
11440
11441   reg_dead_flag = 0;
11442
11443   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11444      we allow the machine description to decide whether use-and-clobber
11445      patterns are OK.  */
11446   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11447     {
11448       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11449         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11450           return 0;
11451     }
11452
11453   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11454      beginning of function.  */
11455   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11456        insn = prev_nonnote_insn (insn))
11457     {
11458       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11459       if (reg_dead_flag)
11460         return reg_dead_flag == 1 ? 1 : 0;
11461
11462       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11463         return 1;
11464     }
11465
11466   /* Get the basic block that we were in.  */
11467   if (insn == 0)
11468     block = ENTRY_BLOCK_PTR->next_bb;
11469   else
11470     {
11471       FOR_EACH_BB (block)
11472         if (insn == BB_HEAD (block))
11473           break;
11474
11475       if (block == EXIT_BLOCK_PTR)
11476         return 0;
11477     }
11478
11479   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11480     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11481       return 0;
11482
11483   return 1;
11484 }
11485 \f
11486 /* Note hard registers in X that are used.  This code is similar to
11487    that in flow.c, but much simpler since we don't care about pseudos.  */
11488
11489 static void
11490 mark_used_regs_combine (rtx x)
11491 {
11492   RTX_CODE code = GET_CODE (x);
11493   unsigned int regno;
11494   int i;
11495
11496   switch (code)
11497     {
11498     case LABEL_REF:
11499     case SYMBOL_REF:
11500     case CONST_INT:
11501     case CONST:
11502     case CONST_DOUBLE:
11503     case CONST_VECTOR:
11504     case PC:
11505     case ADDR_VEC:
11506     case ADDR_DIFF_VEC:
11507     case ASM_INPUT:
11508 #ifdef HAVE_cc0
11509     /* CC0 must die in the insn after it is set, so we don't need to take
11510        special note of it here.  */
11511     case CC0:
11512 #endif
11513       return;
11514
11515     case CLOBBER:
11516       /* If we are clobbering a MEM, mark any hard registers inside the
11517          address as used.  */
11518       if (MEM_P (XEXP (x, 0)))
11519         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11520       return;
11521
11522     case REG:
11523       regno = REGNO (x);
11524       /* A hard reg in a wide mode may really be multiple registers.
11525          If so, mark all of them just like the first.  */
11526       if (regno < FIRST_PSEUDO_REGISTER)
11527         {
11528           unsigned int endregno, r;
11529
11530           /* None of this applies to the stack, frame or arg pointers.  */
11531           if (regno == STACK_POINTER_REGNUM
11532 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11533               || regno == HARD_FRAME_POINTER_REGNUM
11534 #endif
11535 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11536               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11537 #endif
11538               || regno == FRAME_POINTER_REGNUM)
11539             return;
11540
11541           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11542           for (r = regno; r < endregno; r++)
11543             SET_HARD_REG_BIT (newpat_used_regs, r);
11544         }
11545       return;
11546
11547     case SET:
11548       {
11549         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11550            the address.  */
11551         rtx testreg = SET_DEST (x);
11552
11553         while (GET_CODE (testreg) == SUBREG
11554                || GET_CODE (testreg) == ZERO_EXTRACT
11555                || GET_CODE (testreg) == STRICT_LOW_PART)
11556           testreg = XEXP (testreg, 0);
11557
11558         if (MEM_P (testreg))
11559           mark_used_regs_combine (XEXP (testreg, 0));
11560
11561         mark_used_regs_combine (SET_SRC (x));
11562       }
11563       return;
11564
11565     default:
11566       break;
11567     }
11568
11569   /* Recursively scan the operands of this expression.  */
11570
11571   {
11572     const char *fmt = GET_RTX_FORMAT (code);
11573
11574     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11575       {
11576         if (fmt[i] == 'e')
11577           mark_used_regs_combine (XEXP (x, i));
11578         else if (fmt[i] == 'E')
11579           {
11580             int j;
11581
11582             for (j = 0; j < XVECLEN (x, i); j++)
11583               mark_used_regs_combine (XVECEXP (x, i, j));
11584           }
11585       }
11586   }
11587 }
11588 \f
11589 /* Remove register number REGNO from the dead registers list of INSN.
11590
11591    Return the note used to record the death, if there was one.  */
11592
11593 rtx
11594 remove_death (unsigned int regno, rtx insn)
11595 {
11596   rtx note = find_regno_note (insn, REG_DEAD, regno);
11597
11598   if (note)
11599     {
11600       REG_N_DEATHS (regno)--;
11601       remove_note (insn, note);
11602     }
11603
11604   return note;
11605 }
11606
11607 /* For each register (hardware or pseudo) used within expression X, if its
11608    death is in an instruction with cuid between FROM_CUID (inclusive) and
11609    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11610    list headed by PNOTES.
11611
11612    That said, don't move registers killed by maybe_kill_insn.
11613
11614    This is done when X is being merged by combination into TO_INSN.  These
11615    notes will then be distributed as needed.  */
11616
11617 static void
11618 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11619              rtx *pnotes)
11620 {
11621   const char *fmt;
11622   int len, i;
11623   enum rtx_code code = GET_CODE (x);
11624
11625   if (code == REG)
11626     {
11627       unsigned int regno = REGNO (x);
11628       rtx where_dead = reg_stat[regno].last_death;
11629       rtx before_dead, after_dead;
11630
11631       /* Don't move the register if it gets killed in between from and to.  */
11632       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11633           && ! reg_referenced_p (x, maybe_kill_insn))
11634         return;
11635
11636       /* WHERE_DEAD could be a USE insn made by combine, so first we
11637          make sure that we have insns with valid INSN_CUID values.  */
11638       before_dead = where_dead;
11639       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11640         before_dead = PREV_INSN (before_dead);
11641
11642       after_dead = where_dead;
11643       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11644         after_dead = NEXT_INSN (after_dead);
11645
11646       if (before_dead && after_dead
11647           && INSN_CUID (before_dead) >= from_cuid
11648           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11649               || (where_dead != after_dead
11650                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11651         {
11652           rtx note = remove_death (regno, where_dead);
11653
11654           /* It is possible for the call above to return 0.  This can occur
11655              when last_death points to I2 or I1 that we combined with.
11656              In that case make a new note.
11657
11658              We must also check for the case where X is a hard register
11659              and NOTE is a death note for a range of hard registers
11660              including X.  In that case, we must put REG_DEAD notes for
11661              the remaining registers in place of NOTE.  */
11662
11663           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11664               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11665                   > GET_MODE_SIZE (GET_MODE (x))))
11666             {
11667               unsigned int deadregno = REGNO (XEXP (note, 0));
11668               unsigned int deadend
11669                 = (deadregno + hard_regno_nregs[deadregno]
11670                                                [GET_MODE (XEXP (note, 0))]);
11671               unsigned int ourend
11672                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11673               unsigned int i;
11674
11675               for (i = deadregno; i < deadend; i++)
11676                 if (i < regno || i >= ourend)
11677                   REG_NOTES (where_dead)
11678                     = gen_rtx_EXPR_LIST (REG_DEAD,
11679                                          regno_reg_rtx[i],
11680                                          REG_NOTES (where_dead));
11681             }
11682
11683           /* If we didn't find any note, or if we found a REG_DEAD note that
11684              covers only part of the given reg, and we have a multi-reg hard
11685              register, then to be safe we must check for REG_DEAD notes
11686              for each register other than the first.  They could have
11687              their own REG_DEAD notes lying around.  */
11688           else if ((note == 0
11689                     || (note != 0
11690                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11691                             < GET_MODE_SIZE (GET_MODE (x)))))
11692                    && regno < FIRST_PSEUDO_REGISTER
11693                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11694             {
11695               unsigned int ourend
11696                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11697               unsigned int i, offset;
11698               rtx oldnotes = 0;
11699
11700               if (note)
11701                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11702               else
11703                 offset = 1;
11704
11705               for (i = regno + offset; i < ourend; i++)
11706                 move_deaths (regno_reg_rtx[i],
11707                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11708             }
11709
11710           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11711             {
11712               XEXP (note, 1) = *pnotes;
11713               *pnotes = note;
11714             }
11715           else
11716             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11717
11718           REG_N_DEATHS (regno)++;
11719         }
11720
11721       return;
11722     }
11723
11724   else if (GET_CODE (x) == SET)
11725     {
11726       rtx dest = SET_DEST (x);
11727
11728       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11729
11730       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11731          that accesses one word of a multi-word item, some
11732          piece of everything register in the expression is used by
11733          this insn, so remove any old death.  */
11734       /* ??? So why do we test for equality of the sizes?  */
11735
11736       if (GET_CODE (dest) == ZERO_EXTRACT
11737           || GET_CODE (dest) == STRICT_LOW_PART
11738           || (GET_CODE (dest) == SUBREG
11739               && (((GET_MODE_SIZE (GET_MODE (dest))
11740                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11741                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11742                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11743         {
11744           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11745           return;
11746         }
11747
11748       /* If this is some other SUBREG, we know it replaces the entire
11749          value, so use that as the destination.  */
11750       if (GET_CODE (dest) == SUBREG)
11751         dest = SUBREG_REG (dest);
11752
11753       /* If this is a MEM, adjust deaths of anything used in the address.
11754          For a REG (the only other possibility), the entire value is
11755          being replaced so the old value is not used in this insn.  */
11756
11757       if (MEM_P (dest))
11758         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11759                      to_insn, pnotes);
11760       return;
11761     }
11762
11763   else if (GET_CODE (x) == CLOBBER)
11764     return;
11765
11766   len = GET_RTX_LENGTH (code);
11767   fmt = GET_RTX_FORMAT (code);
11768
11769   for (i = 0; i < len; i++)
11770     {
11771       if (fmt[i] == 'E')
11772         {
11773           int j;
11774           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11775             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11776                          to_insn, pnotes);
11777         }
11778       else if (fmt[i] == 'e')
11779         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11780     }
11781 }
11782 \f
11783 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11784    pattern of an insn.  X must be a REG.  */
11785
11786 static int
11787 reg_bitfield_target_p (rtx x, rtx body)
11788 {
11789   int i;
11790
11791   if (GET_CODE (body) == SET)
11792     {
11793       rtx dest = SET_DEST (body);
11794       rtx target;
11795       unsigned int regno, tregno, endregno, endtregno;
11796
11797       if (GET_CODE (dest) == ZERO_EXTRACT)
11798         target = XEXP (dest, 0);
11799       else if (GET_CODE (dest) == STRICT_LOW_PART)
11800         target = SUBREG_REG (XEXP (dest, 0));
11801       else
11802         return 0;
11803
11804       if (GET_CODE (target) == SUBREG)
11805         target = SUBREG_REG (target);
11806
11807       if (!REG_P (target))
11808         return 0;
11809
11810       tregno = REGNO (target), regno = REGNO (x);
11811       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11812         return target == x;
11813
11814       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11815       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11816
11817       return endregno > tregno && regno < endtregno;
11818     }
11819
11820   else if (GET_CODE (body) == PARALLEL)
11821     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11822       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11823         return 1;
11824
11825   return 0;
11826 }
11827 \f
11828 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11829    as appropriate.  I3 and I2 are the insns resulting from the combination
11830    insns including FROM (I2 may be zero).
11831
11832    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11833    not need REG_DEAD notes because they are being substituted for.  This
11834    saves searching in the most common cases.
11835
11836    Each note in the list is either ignored or placed on some insns, depending
11837    on the type of note.  */
11838
11839 static void
11840 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11841                   rtx elim_i1)
11842 {
11843   rtx note, next_note;
11844   rtx tem;
11845
11846   for (note = notes; note; note = next_note)
11847     {
11848       rtx place = 0, place2 = 0;
11849
11850       next_note = XEXP (note, 1);
11851       switch (REG_NOTE_KIND (note))
11852         {
11853         case REG_BR_PROB:
11854         case REG_BR_PRED:
11855           /* Doesn't matter much where we put this, as long as it's somewhere.
11856              It is preferable to keep these notes on branches, which is most
11857              likely to be i3.  */
11858           place = i3;
11859           break;
11860
11861         case REG_VALUE_PROFILE:
11862           /* Just get rid of this note, as it is unused later anyway.  */
11863           break;
11864
11865         case REG_NON_LOCAL_GOTO:
11866           if (JUMP_P (i3))
11867             place = i3;
11868           else
11869             {
11870               gcc_assert (i2 && JUMP_P (i2));
11871               place = i2;
11872             }
11873           break;
11874
11875         case REG_EH_REGION:
11876           /* These notes must remain with the call or trapping instruction.  */
11877           if (CALL_P (i3))
11878             place = i3;
11879           else if (i2 && CALL_P (i2))
11880             place = i2;
11881           else
11882             {
11883               gcc_assert (flag_non_call_exceptions);
11884               if (may_trap_p (i3))
11885                 place = i3;
11886               else if (i2 && may_trap_p (i2))
11887                 place = i2;
11888               /* ??? Otherwise assume we've combined things such that we
11889                  can now prove that the instructions can't trap.  Drop the
11890                  note in this case.  */
11891             }
11892           break;
11893
11894         case REG_NORETURN:
11895         case REG_SETJMP:
11896           /* These notes must remain with the call.  It should not be
11897              possible for both I2 and I3 to be a call.  */
11898           if (CALL_P (i3))
11899             place = i3;
11900           else
11901             {
11902               gcc_assert (i2 && CALL_P (i2));
11903               place = i2;
11904             }
11905           break;
11906
11907         case REG_UNUSED:
11908           /* Any clobbers for i3 may still exist, and so we must process
11909              REG_UNUSED notes from that insn.
11910
11911              Any clobbers from i2 or i1 can only exist if they were added by
11912              recog_for_combine.  In that case, recog_for_combine created the
11913              necessary REG_UNUSED notes.  Trying to keep any original
11914              REG_UNUSED notes from these insns can cause incorrect output
11915              if it is for the same register as the original i3 dest.
11916              In that case, we will notice that the register is set in i3,
11917              and then add a REG_UNUSED note for the destination of i3, which
11918              is wrong.  However, it is possible to have REG_UNUSED notes from
11919              i2 or i1 for register which were both used and clobbered, so
11920              we keep notes from i2 or i1 if they will turn into REG_DEAD
11921              notes.  */
11922
11923           /* If this register is set or clobbered in I3, put the note there
11924              unless there is one already.  */
11925           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11926             {
11927               if (from_insn != i3)
11928                 break;
11929
11930               if (! (REG_P (XEXP (note, 0))
11931                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11932                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11933                 place = i3;
11934             }
11935           /* Otherwise, if this register is used by I3, then this register
11936              now dies here, so we must put a REG_DEAD note here unless there
11937              is one already.  */
11938           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11939                    && ! (REG_P (XEXP (note, 0))
11940                          ? find_regno_note (i3, REG_DEAD,
11941                                             REGNO (XEXP (note, 0)))
11942                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11943             {
11944               PUT_REG_NOTE_KIND (note, REG_DEAD);
11945               place = i3;
11946             }
11947           break;
11948
11949         case REG_EQUAL:
11950         case REG_EQUIV:
11951         case REG_NOALIAS:
11952           /* These notes say something about results of an insn.  We can
11953              only support them if they used to be on I3 in which case they
11954              remain on I3.  Otherwise they are ignored.
11955
11956              If the note refers to an expression that is not a constant, we
11957              must also ignore the note since we cannot tell whether the
11958              equivalence is still true.  It might be possible to do
11959              slightly better than this (we only have a problem if I2DEST
11960              or I1DEST is present in the expression), but it doesn't
11961              seem worth the trouble.  */
11962
11963           if (from_insn == i3
11964               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11965             place = i3;
11966           break;
11967
11968         case REG_INC:
11969         case REG_NO_CONFLICT:
11970           /* These notes say something about how a register is used.  They must
11971              be present on any use of the register in I2 or I3.  */
11972           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11973             place = i3;
11974
11975           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11976             {
11977               if (place)
11978                 place2 = i2;
11979               else
11980                 place = i2;
11981             }
11982           break;
11983
11984         case REG_LABEL:
11985           /* This can show up in several ways -- either directly in the
11986              pattern, or hidden off in the constant pool with (or without?)
11987              a REG_EQUAL note.  */
11988           /* ??? Ignore the without-reg_equal-note problem for now.  */
11989           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11990               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11991                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11992                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11993             place = i3;
11994
11995           if (i2
11996               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11997                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11998                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11999                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12000             {
12001               if (place)
12002                 place2 = i2;
12003               else
12004                 place = i2;
12005             }
12006
12007           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
12008              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
12009           if (place && JUMP_P (place))
12010             {
12011               rtx label = JUMP_LABEL (place);
12012
12013               if (!label)
12014                 JUMP_LABEL (place) = XEXP (note, 0);
12015               else
12016                 {
12017                   gcc_assert (label == XEXP (note, 0));
12018                   if (LABEL_P (label))
12019                     LABEL_NUSES (label)--;
12020                 }
12021               place = 0;
12022             }
12023           if (place2 && JUMP_P (place2))
12024             {
12025               rtx label = JUMP_LABEL (place2);
12026
12027               if (!label)
12028                 JUMP_LABEL (place2) = XEXP (note, 0);
12029               else
12030                 {
12031                   gcc_assert (label == XEXP (note, 0));
12032                   if (LABEL_P (label))
12033                     LABEL_NUSES (label)--;
12034                 }
12035               place2 = 0;
12036             }
12037           break;
12038
12039         case REG_NONNEG:
12040           /* This note says something about the value of a register prior
12041              to the execution of an insn.  It is too much trouble to see
12042              if the note is still correct in all situations.  It is better
12043              to simply delete it.  */
12044           break;
12045
12046         case REG_RETVAL:
12047           /* If the insn previously containing this note still exists,
12048              put it back where it was.  Otherwise move it to the previous
12049              insn.  Adjust the corresponding REG_LIBCALL note.  */
12050           if (!NOTE_P (from_insn))
12051             place = from_insn;
12052           else
12053             {
12054               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12055               place = prev_real_insn (from_insn);
12056               if (tem && place)
12057                 XEXP (tem, 0) = place;
12058               /* If we're deleting the last remaining instruction of a
12059                  libcall sequence, don't add the notes.  */
12060               else if (XEXP (note, 0) == from_insn)
12061                 tem = place = 0;
12062               /* Don't add the dangling REG_RETVAL note.  */
12063               else if (! tem)
12064                 place = 0;
12065             }
12066           break;
12067
12068         case REG_LIBCALL:
12069           /* This is handled similarly to REG_RETVAL.  */
12070           if (!NOTE_P (from_insn))
12071             place = from_insn;
12072           else
12073             {
12074               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12075               place = next_real_insn (from_insn);
12076               if (tem && place)
12077                 XEXP (tem, 0) = place;
12078               /* If we're deleting the last remaining instruction of a
12079                  libcall sequence, don't add the notes.  */
12080               else if (XEXP (note, 0) == from_insn)
12081                 tem = place = 0;
12082               /* Don't add the dangling REG_LIBCALL note.  */
12083               else if (! tem)
12084                 place = 0;
12085             }
12086           break;
12087
12088         case REG_DEAD:
12089           /* If the register is used as an input in I3, it dies there.
12090              Similarly for I2, if it is nonzero and adjacent to I3.
12091
12092              If the register is not used as an input in either I3 or I2
12093              and it is not one of the registers we were supposed to eliminate,
12094              there are two possibilities.  We might have a non-adjacent I2
12095              or we might have somehow eliminated an additional register
12096              from a computation.  For example, we might have had A & B where
12097              we discover that B will always be zero.  In this case we will
12098              eliminate the reference to A.
12099
12100              In both cases, we must search to see if we can find a previous
12101              use of A and put the death note there.  */
12102
12103           if (from_insn
12104               && CALL_P (from_insn)
12105               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12106             place = from_insn;
12107           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12108             place = i3;
12109           else if (i2 != 0 && next_nonnote_insn (i2) == i3
12110                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12111             place = i2;
12112
12113           if (place == 0
12114               && (rtx_equal_p (XEXP (note, 0), elim_i2)
12115                   || rtx_equal_p (XEXP (note, 0), elim_i1)))
12116             break;
12117
12118           if (place == 0)
12119             {
12120               basic_block bb = this_basic_block;
12121
12122               /* You might think you could search back from FROM_INSN
12123                  rather than from I3, but combine tries to split invalid
12124                  combined instructions.  This can result in the old I2
12125                  or I1 moving later in the insn sequence.  */
12126               for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12127                 {
12128                   if (! INSN_P (tem))
12129                     {
12130                       if (tem == BB_HEAD (bb))
12131                         break;
12132                       continue;
12133                     }
12134
12135                   /* If the register is being set at TEM, see if that is all
12136                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12137                      into a REG_UNUSED note instead. Don't delete sets to
12138                      global register vars.  */
12139                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12140                        || !global_regs[REGNO (XEXP (note, 0))])
12141                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12142                     {
12143                       rtx set = single_set (tem);
12144                       rtx inner_dest = 0;
12145 #ifdef HAVE_cc0
12146                       rtx cc0_setter = NULL_RTX;
12147 #endif
12148
12149                       if (set != 0)
12150                         for (inner_dest = SET_DEST (set);
12151                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12152                               || GET_CODE (inner_dest) == SUBREG
12153                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12154                              inner_dest = XEXP (inner_dest, 0))
12155                           ;
12156
12157                       /* Verify that it was the set, and not a clobber that
12158                          modified the register.
12159
12160                          CC0 targets must be careful to maintain setter/user
12161                          pairs.  If we cannot delete the setter due to side
12162                          effects, mark the user with an UNUSED note instead
12163                          of deleting it.  */
12164
12165                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12166                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12167 #ifdef HAVE_cc0
12168                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12169                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12170                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12171 #endif
12172                           )
12173                         {
12174                           /* Move the notes and links of TEM elsewhere.
12175                              This might delete other dead insns recursively.
12176                              First set the pattern to something that won't use
12177                              any register.  */
12178                           rtx old_notes = REG_NOTES (tem);
12179
12180                           PATTERN (tem) = pc_rtx;
12181                           REG_NOTES (tem) = NULL;
12182
12183                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12184                                             NULL_RTX, NULL_RTX);
12185                           distribute_links (LOG_LINKS (tem));
12186
12187                           SET_INSN_DELETED (tem);
12188
12189 #ifdef HAVE_cc0
12190                           /* Delete the setter too.  */
12191                           if (cc0_setter)
12192                             {
12193                               PATTERN (cc0_setter) = pc_rtx;
12194                               old_notes = REG_NOTES (cc0_setter);
12195                               REG_NOTES (cc0_setter) = NULL;
12196
12197                               distribute_notes (old_notes, cc0_setter,
12198                                                 cc0_setter, NULL_RTX,
12199                                                 NULL_RTX, NULL_RTX);
12200                               distribute_links (LOG_LINKS (cc0_setter));
12201
12202                               SET_INSN_DELETED (cc0_setter);
12203                             }
12204 #endif
12205                         }
12206                       else
12207                         {
12208                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12209
12210                           /*  If there isn't already a REG_UNUSED note, put one
12211                               here.  Do not place a REG_DEAD note, even if
12212                               the register is also used here; that would not
12213                               match the algorithm used in lifetime analysis
12214                               and can cause the consistency check in the
12215                               scheduler to fail.  */
12216                           if (! find_regno_note (tem, REG_UNUSED,
12217                                                  REGNO (XEXP (note, 0))))
12218                             place = tem;
12219                           break;
12220                         }
12221                     }
12222                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12223                            || (CALL_P (tem)
12224                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12225                     {
12226                       /* This may not be the correct place for the death
12227                          note if FROM_INSN is before TEM, and the reg is
12228                          set between FROM_INSN and TEM.  The reg might
12229                          die two or more times.  An existing death note
12230                          means we are looking at the wrong live range.  */
12231                       if (from_insn
12232                           && INSN_CUID (from_insn) < INSN_CUID (tem)
12233                           && find_regno_note (tem, REG_DEAD,
12234                                               REGNO (XEXP (note, 0))))
12235                         {
12236                           tem = from_insn;
12237                           if (tem == BB_HEAD (bb))
12238                             break;
12239                           continue;
12240                         }
12241
12242                       place = tem;
12243
12244                       /* If we are doing a 3->2 combination, and we have a
12245                          register which formerly died in i3 and was not used
12246                          by i2, which now no longer dies in i3 and is used in
12247                          i2 but does not die in i2, and place is between i2
12248                          and i3, then we may need to move a link from place to
12249                          i2.  */
12250                       if (i2 && INSN_UID (place) <= max_uid_cuid
12251                           && INSN_CUID (place) > INSN_CUID (i2)
12252                           && from_insn
12253                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12254                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12255                         {
12256                           rtx links = LOG_LINKS (place);
12257                           LOG_LINKS (place) = 0;
12258                           distribute_links (links);
12259                         }
12260                       break;
12261                     }
12262
12263                   if (tem == BB_HEAD (bb))
12264                     break;
12265                 }
12266
12267               /* We haven't found an insn for the death note and it
12268                  is still a REG_DEAD note, but we have hit the beginning
12269                  of the block.  If the existing life info says the reg
12270                  was dead, there's nothing left to do.  Otherwise, we'll
12271                  need to do a global life update after combine.  */
12272               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12273                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12274                                       REGNO (XEXP (note, 0))))
12275                 SET_BIT (refresh_blocks, this_basic_block->index);
12276             }
12277
12278           /* If the register is set or already dead at PLACE, we needn't do
12279              anything with this note if it is still a REG_DEAD note.
12280              We check here if it is set at all, not if is it totally replaced,
12281              which is what `dead_or_set_p' checks, so also check for it being
12282              set partially.  */
12283
12284           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12285             {
12286               unsigned int regno = REGNO (XEXP (note, 0));
12287
12288               /* Similarly, if the instruction on which we want to place
12289                  the note is a noop, we'll need do a global live update
12290                  after we remove them in delete_noop_moves.  */
12291               if (noop_move_p (place))
12292                 SET_BIT (refresh_blocks, this_basic_block->index);
12293
12294               if (dead_or_set_p (place, XEXP (note, 0))
12295                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12296                 {
12297                   /* Unless the register previously died in PLACE, clear
12298                      last_death.  [I no longer understand why this is
12299                      being done.] */
12300                   if (reg_stat[regno].last_death != place)
12301                     reg_stat[regno].last_death = 0;
12302                   place = 0;
12303                 }
12304               else
12305                 reg_stat[regno].last_death = place;
12306
12307               /* If this is a death note for a hard reg that is occupying
12308                  multiple registers, ensure that we are still using all
12309                  parts of the object.  If we find a piece of the object
12310                  that is unused, we must arrange for an appropriate REG_DEAD
12311                  note to be added for it.  However, we can't just emit a USE
12312                  and tag the note to it, since the register might actually
12313                  be dead; so we recourse, and the recursive call then finds
12314                  the previous insn that used this register.  */
12315
12316               if (place && regno < FIRST_PSEUDO_REGISTER
12317                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12318                 {
12319                   unsigned int endregno
12320                     = regno + hard_regno_nregs[regno]
12321                                               [GET_MODE (XEXP (note, 0))];
12322                   int all_used = 1;
12323                   unsigned int i;
12324
12325                   for (i = regno; i < endregno; i++)
12326                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12327                          && ! find_regno_fusage (place, USE, i))
12328                         || dead_or_set_regno_p (place, i))
12329                       all_used = 0;
12330
12331                   if (! all_used)
12332                     {
12333                       /* Put only REG_DEAD notes for pieces that are
12334                          not already dead or set.  */
12335
12336                       for (i = regno; i < endregno;
12337                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12338                         {
12339                           rtx piece = regno_reg_rtx[i];
12340                           basic_block bb = this_basic_block;
12341
12342                           if (! dead_or_set_p (place, piece)
12343                               && ! reg_bitfield_target_p (piece,
12344                                                           PATTERN (place)))
12345                             {
12346                               rtx new_note
12347                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12348
12349                               distribute_notes (new_note, place, place,
12350                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12351                             }
12352                           else if (! refers_to_regno_p (i, i + 1,
12353                                                         PATTERN (place), 0)
12354                                    && ! find_regno_fusage (place, USE, i))
12355                             for (tem = PREV_INSN (place); ;
12356                                  tem = PREV_INSN (tem))
12357                               {
12358                                 if (! INSN_P (tem))
12359                                   {
12360                                     if (tem == BB_HEAD (bb))
12361                                       {
12362                                         SET_BIT (refresh_blocks,
12363                                                  this_basic_block->index);
12364                                         break;
12365                                       }
12366                                     continue;
12367                                   }
12368                                 if (dead_or_set_p (tem, piece)
12369                                     || reg_bitfield_target_p (piece,
12370                                                               PATTERN (tem)))
12371                                   {
12372                                     REG_NOTES (tem)
12373                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12374                                                            REG_NOTES (tem));
12375                                     break;
12376                                   }
12377                               }
12378
12379                         }
12380
12381                       place = 0;
12382                     }
12383                 }
12384             }
12385           break;
12386
12387         default:
12388           /* Any other notes should not be present at this point in the
12389              compilation.  */
12390           gcc_unreachable ();
12391         }
12392
12393       if (place)
12394         {
12395           XEXP (note, 1) = REG_NOTES (place);
12396           REG_NOTES (place) = note;
12397         }
12398       else if ((REG_NOTE_KIND (note) == REG_DEAD
12399                 || REG_NOTE_KIND (note) == REG_UNUSED)
12400                && REG_P (XEXP (note, 0)))
12401         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12402
12403       if (place2)
12404         {
12405           if ((REG_NOTE_KIND (note) == REG_DEAD
12406                || REG_NOTE_KIND (note) == REG_UNUSED)
12407               && REG_P (XEXP (note, 0)))
12408             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12409
12410           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12411                                                REG_NOTE_KIND (note),
12412                                                XEXP (note, 0),
12413                                                REG_NOTES (place2));
12414         }
12415     }
12416 }
12417 \f
12418 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12419    I3, I2, and I1 to new locations.  This is also called to add a link
12420    pointing at I3 when I3's destination is changed.  */
12421
12422 static void
12423 distribute_links (rtx links)
12424 {
12425   rtx link, next_link;
12426
12427   for (link = links; link; link = next_link)
12428     {
12429       rtx place = 0;
12430       rtx insn;
12431       rtx set, reg;
12432
12433       next_link = XEXP (link, 1);
12434
12435       /* If the insn that this link points to is a NOTE or isn't a single
12436          set, ignore it.  In the latter case, it isn't clear what we
12437          can do other than ignore the link, since we can't tell which
12438          register it was for.  Such links wouldn't be used by combine
12439          anyway.
12440
12441          It is not possible for the destination of the target of the link to
12442          have been changed by combine.  The only potential of this is if we
12443          replace I3, I2, and I1 by I3 and I2.  But in that case the
12444          destination of I2 also remains unchanged.  */
12445
12446       if (NOTE_P (XEXP (link, 0))
12447           || (set = single_set (XEXP (link, 0))) == 0)
12448         continue;
12449
12450       reg = SET_DEST (set);
12451       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12452              || GET_CODE (reg) == STRICT_LOW_PART)
12453         reg = XEXP (reg, 0);
12454
12455       /* A LOG_LINK is defined as being placed on the first insn that uses
12456          a register and points to the insn that sets the register.  Start
12457          searching at the next insn after the target of the link and stop
12458          when we reach a set of the register or the end of the basic block.
12459
12460          Note that this correctly handles the link that used to point from
12461          I3 to I2.  Also note that not much searching is typically done here
12462          since most links don't point very far away.  */
12463
12464       for (insn = NEXT_INSN (XEXP (link, 0));
12465            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12466                      || BB_HEAD (this_basic_block->next_bb) != insn));
12467            insn = NEXT_INSN (insn))
12468         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12469           {
12470             if (reg_referenced_p (reg, PATTERN (insn)))
12471               place = insn;
12472             break;
12473           }
12474         else if (CALL_P (insn)
12475                  && find_reg_fusage (insn, USE, reg))
12476           {
12477             place = insn;
12478             break;
12479           }
12480         else if (INSN_P (insn) && reg_set_p (reg, insn))
12481           break;
12482
12483       /* If we found a place to put the link, place it there unless there
12484          is already a link to the same insn as LINK at that point.  */
12485
12486       if (place)
12487         {
12488           rtx link2;
12489
12490           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12491             if (XEXP (link2, 0) == XEXP (link, 0))
12492               break;
12493
12494           if (link2 == 0)
12495             {
12496               XEXP (link, 1) = LOG_LINKS (place);
12497               LOG_LINKS (place) = link;
12498
12499               /* Set added_links_insn to the earliest insn we added a
12500                  link to.  */
12501               if (added_links_insn == 0
12502                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12503                 added_links_insn = place;
12504             }
12505         }
12506     }
12507 }
12508 \f
12509 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12510    Check whether the expression pointer to by LOC is a register or
12511    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12512    Otherwise return zero.  */
12513
12514 static int
12515 unmentioned_reg_p_1 (rtx *loc, void *expr)
12516 {
12517   rtx x = *loc;
12518
12519   if (x != NULL_RTX
12520       && (REG_P (x) || MEM_P (x))
12521       && ! reg_mentioned_p (x, (rtx) expr))
12522     return 1;
12523   return 0;
12524 }
12525
12526 /* Check for any register or memory mentioned in EQUIV that is not
12527    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12528    of EXPR where some registers may have been replaced by constants.  */
12529
12530 static bool
12531 unmentioned_reg_p (rtx equiv, rtx expr)
12532 {
12533   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12534 }
12535 \f
12536 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12537
12538 static int
12539 insn_cuid (rtx insn)
12540 {
12541   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12542          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12543     insn = NEXT_INSN (insn);
12544
12545   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12546
12547   return INSN_CUID (insn);
12548 }
12549 \f
12550 void
12551 dump_combine_stats (FILE *file)
12552 {
12553   fprintf
12554     (file,
12555      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12556      combine_attempts, combine_merges, combine_extras, combine_successes);
12557 }
12558
12559 void
12560 dump_combine_total_stats (FILE *file)
12561 {
12562   fprintf
12563     (file,
12564      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12565      total_attempts, total_merges, total_extras, total_successes);
12566 }
12567 \f
12568
12569 static bool
12570 gate_handle_combine (void)
12571 {
12572   return (optimize > 0);
12573 }
12574
12575 /* Try combining insns through substitution.  */
12576 static void
12577 rest_of_handle_combine (void)
12578 {
12579   int rebuild_jump_labels_after_combine
12580     = combine_instructions (get_insns (), max_reg_num ());
12581
12582   /* Combining insns may have turned an indirect jump into a
12583      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12584      instructions.  */
12585   if (rebuild_jump_labels_after_combine)
12586     {
12587       timevar_push (TV_JUMP);
12588       rebuild_jump_labels (get_insns ());
12589       timevar_pop (TV_JUMP);
12590
12591       delete_dead_jumptables ();
12592       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12593     }
12594 }
12595
12596 struct tree_opt_pass pass_combine =
12597 {
12598   "combine",                            /* name */
12599   gate_handle_combine,                  /* gate */
12600   rest_of_handle_combine,               /* execute */
12601   NULL,                                 /* sub */
12602   NULL,                                 /* next */
12603   0,                                    /* static_pass_number */
12604   TV_COMBINE,                           /* tv_id */
12605   0,                                    /* properties_required */
12606   0,                                    /* properties_provided */
12607   0,                                    /* properties_destroyed */
12608   0,                                    /* todo_flags_start */
12609   TODO_dump_func |
12610   TODO_ggc_collect,                     /* todo_flags_finish */
12611   'c'                                   /* letter */
12612 };
12613