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1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992-2020 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Instruction reorganization pass.
24 This pass runs after register allocation and final jump
25 optimization. It should be the last pass to run before peephole.
26 It serves primarily to fill delay slots of insns, typically branch
27 and call insns. Other insns typically involve more complicated
28 interactions of data dependencies and resource constraints, and
29 are better handled by scheduling before register allocation (by the
30 function `schedule_insns').
32 The Branch Penalty is the number of extra cycles that are needed to
33 execute a branch insn. On an ideal machine, branches take a single
34 cycle, and the Branch Penalty is 0. Several RISC machines approach
35 branch delays differently:
37 The MIPS has a single branch delay slot. Most insns
38 (except other branches) can be used to fill this slot. When the
39 slot is filled, two insns execute in two cycles, reducing the
40 branch penalty to zero.
42 The SPARC always has a branch delay slot, but its effects can be
43 annulled when the branch is not taken. This means that failing to
44 find other sources of insns, we can hoist an insn from the branch
45 target that would only be safe to execute knowing that the branch
46 is taken.
48 The HP-PA always has a branch delay slot. For unconditional branches
49 its effects can be annulled when the branch is taken. The effects
50 of the delay slot in a conditional branch can be nullified for forward
51 taken branches, or for untaken backward branches. This means
52 we can hoist insns from the fall-through path for forward branches or
53 steal insns from the target of backward branches.
55 The TMS320C3x and C4x have three branch delay slots. When the three
56 slots are filled, the branch penalty is zero. Most insns can fill the
57 delay slots except jump insns.
59 Three techniques for filling delay slots have been implemented so far:
61 (1) `fill_simple_delay_slots' is the simplest, most efficient way
62 to fill delay slots. This pass first looks for insns which come
63 from before the branch and which are safe to execute after the
64 branch. Then it searches after the insn requiring delay slots or,
65 in the case of a branch, for insns that are after the point at
66 which the branch merges into the fallthrough code, if such a point
67 exists. When such insns are found, the branch penalty decreases
68 and no code expansion takes place.
70 (2) `fill_eager_delay_slots' is more complicated: it is used for
71 scheduling conditional jumps, or for scheduling jumps which cannot
72 be filled using (1). A machine need not have annulled jumps to use
73 this strategy, but it helps (by keeping more options open).
74 `fill_eager_delay_slots' tries to guess the direction the branch
75 will go; if it guesses right 100% of the time, it can reduce the
76 branch penalty as much as `fill_simple_delay_slots' does. If it
77 guesses wrong 100% of the time, it might as well schedule nops. When
78 `fill_eager_delay_slots' takes insns from the fall-through path of
79 the jump, usually there is no code expansion; when it takes insns
80 from the branch target, there is code expansion if it is not the
81 only way to reach that target.
83 (3) `relax_delay_slots' uses a set of rules to simplify code that
84 has been reorganized by (1) and (2). It finds cases where
85 conditional test can be eliminated, jumps can be threaded, extra
86 insns can be eliminated, etc. It is the job of (1) and (2) to do a
87 good job of scheduling locally; `relax_delay_slots' takes care of
88 making the various individual schedules work well together. It is
89 especially tuned to handle the control flow interactions of branch
90 insns. It does nothing for insns with delay slots that do not
91 branch.
93 On machines that use CC0, we are very conservative. We will not make
94 a copy of an insn involving CC0 since we want to maintain a 1-1
95 correspondence between the insn that sets and uses CC0. The insns are
96 allowed to be separated by placing an insn that sets CC0 (but not an insn
97 that uses CC0; we could do this, but it doesn't seem worthwhile) in a
98 delay slot. In that case, we point each insn at the other with REG_CC_USER
99 and REG_CC_SETTER notes. Note that these restrictions affect very few
100 machines because most RISC machines with delay slots will not use CC0
101 (the RT is the only known exception at this point). */
121 \f
122 /* First, some functions that were used before GCC got a control flow graph.
123 These functions are now only used here in reorg.c, and have therefore
124 been moved here to avoid inadvertent misuse elsewhere in the compiler. */
126 /* Return the last label to mark the same position as LABEL. Return LABEL
127 itself if it is null or any return rtx. */
129 static rtx
131 {
139 /* __builtin_unreachable can create a CODE_LABEL followed by a BARRIER.
141 Since reaching the CODE_LABEL is undefined behavior, we can return
142 any code label and we're OK at runtime.
144 However, if we return a CODE_LABEL which leads to a shrinked wrapped
145 epilogue, but the path does not have a prologue, then we will trip
146 a sanity check in the dwarf2 cfi code which wants to verify that
147 the CFIs are all the same on the traces leading to the epilogue.
149 So we explicitly disallow looking through BARRIERS here. */
157 }
159 /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER
160 and REG_CC_USER notes so we can find it. */
162 static void
164 {
172 }
173 \f
174 /* Insns which have delay slots that have not yet been filled. */
179 /* Define macros to refer to the first and last slot containing unfilled
180 insns. These are used because the list may move and its address
181 should be recomputed at each use. */
183 #define unfilled_slots_base \
184 ((rtx_insn **) obstack_base (&unfilled_slots_obstack))
186 #define unfilled_slots_next \
187 ((rtx_insn **) obstack_next_free (&unfilled_slots_obstack))
189 /* Points to the label before the end of the function, or before a
190 return insn. */
192 /* Likewise for a simple_return. */
195 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
196 not always monotonically increase. */
199 /* Highest valid index in `uid_to_ruid'. */
227 rtx *);
249 \f
250 /* A wrapper around next_active_insn which takes care to return ret_rtx
251 unchanged. */
253 static rtx
255 {
259 }
260 \f
261 /* Return true iff INSN is a simplejump, or any kind of return insn. */
263 static bool
265 {
269 }
270 \f
271 /* Return TRUE if this insn should stop the search for insn to fill delay
272 slots. LABELS_P indicates that labels should terminate the search.
273 In all cases, jumps terminate the search. */
275 static int
277 {
281 /* If the insn can throw an exception that is caught within the function,
282 it may effectively perform a jump from the viewpoint of the function.
283 Therefore act like for a jump. */
288 {
302 /* OK unless it contains a delay slot or is an `asm' insn of some type.
303 We don't know anything about these. */
310 }
311 }
312 \f
313 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
314 resource set contains a volatile memory reference. Otherwise, return FALSE. */
316 static int
318 {
324 }
326 /* Return TRUE if any resource marked in RES, a `struct resources', is
327 referenced by INSN. If INCLUDE_DELAYED_EFFECTS is set, return if the called
328 routine is using those resources.
330 We compute this by computing all the resources referenced by INSN and
331 seeing if this conflicts with RES. It might be faster to directly check
332 ourselves, and this is the way it used to work, but it means duplicating
333 a large block of complex code. */
335 static int
338 {
344 }
346 /* Return TRUE if INSN modifies resources that are marked in RES.
347 INCLUDE_DELAYED_EFFECTS is set if the actions of that routine should be
348 included. CC0 is only modified if it is explicitly set; see comments
349 in front of mark_set_resources for details. */
351 static int
354 {
359 (include_delayed_effects
360 ? MARK_SRC_DEST_CALL
363 }
364 \f
365 /* Find a label at the end of the function or before a RETURN. If there
366 is none, try to make one. If that fails, returns 0.
368 The property of such a label is that it is placed just before the
369 epilogue or a bare RETURN insn, so that another bare RETURN can be
370 turned into a jump to the label unconditionally. In particular, the
371 label cannot be placed before a RETURN insn with a filled delay slot.
373 ??? There may be a problem with the current implementation. Suppose
374 we start with a bare RETURN insn and call find_end_label. It may set
375 function_return_label just before the RETURN. Suppose the machinery
376 is able to fill the delay slot of the RETURN insn afterwards. Then
377 function_return_label is no longer valid according to the property
378 described above and find_end_label will still return it unmodified.
379 Note that this is probably mitigated by the following observation:
380 once function_return_label is made, it is very likely the target of
381 a jump, so filling the delay slot of the RETURN will be much more
382 difficult.
383 KIND is either simple_return_rtx or ret_rtx, indicating which type of
384 return we're looking for. */
388 {
394 else
395 {
398 }
400 /* If we found one previously, return it. */
404 /* Otherwise, see if there is a label at the end of the function. If there
405 is, it must be that RETURN insns aren't needed, so that is our return
406 label and we don't have to do anything else. */
415 /* When a target threads its epilogue we might already have a
416 suitable return insn. If so put a label before it for the
417 function_return_label. */
421 {
426 /* Put the label before any USE insns that may precede the RETURN
427 insn. */
433 }
437 else
438 {
441 /* If the basic block reorder pass moves the return insn to
442 some other place try to locate it again and put our
443 function_return_label there. */
447 {
450 /* Put the label before any USE insns that may precede the
451 RETURN insn. */
456 }
457 else
458 {
460 /* The RETURN insn has its delay slot filled so we cannot
461 emit the label just before it. Since we already have
462 an epilogue and cannot emit a new RETURN, we cannot
463 emit the label at all. */
466 /* Otherwise, make a new label and emit a RETURN and BARRIER,
467 if needed. */
470 {
471 /* The return we make may have delay slots too. */
478 }
479 }
481 }
483 /* Show one additional use for this label so it won't go away until
484 we are done. */
488 }
489 \f
490 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
491 the pattern of INSN with the SEQUENCE.
493 Returns the insn containing the SEQUENCE that replaces INSN. */
497 {
498 /* Allocate the rtvec to hold the insns and the SEQUENCE. */
503 /* If DELAY_INSN has a location, use it for SEQ_INSN. If DELAY_INSN does
504 not have a location, but one of the delayed insns does, we pick up a
505 location from there later. */
508 /* Unlink INSN from the insn chain, so that we can put it into
509 the SEQUENCE. Remember where we want to emit SEQUENCE in AFTER. */
514 /* Build our SEQUENCE and rebuild the insn chain. */
521 {
525 /* Show that this copy of the insn isn't deleted. */
528 /* Unlink insn from its original place, and re-emit it into
529 the sequence. */
533 /* SPARC assembler, for instance, emit warning when debug info is output
534 into the delay slot. */
540 {
543 {
545 /* Remove any REG_DEAD notes because we can't rely on them now
546 that the insn has been moved. */
552 /* Keep the label reference count up to date. */
559 }
560 }
561 }
564 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
568 }
570 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
571 be in the order in which the insns are to be executed. */
573 static void
575 {
576 /* If INSN has its block number recorded, clear it since we may
577 be moving the insn to a new block. */
580 }
581 \f
582 /* Delete INSN from the delay slot of the insn that it is in, which may
583 produce an insn with no delay slots. Return the new insn. */
587 {
593 /* We first must find the insn containing the SEQUENCE with INSN in its
594 delay slot. Do this by finding an insn, TRIAL, where
595 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
600 ;
608 /* Create a delay list consisting of all the insns other than the one
609 we are deleting (unless we were the only one). */
616 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
617 list, and rebuild the delay list if non-empty. */
623 /* If there was a barrier after the old SEQUENCE, remit it. */
627 /* If there are any delay insns, remit them. Otherwise clear the
628 annul flag. */
636 /* Show we need to fill this insn again. */
640 }
641 \f
642 /* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down
643 the insn that sets CC0 for it and delete it too. */
645 static void
647 {
648 /* Delete the insn that sets cc0 for us. On machines without cc0, we could
649 delete the insn that sets the condition code, but it is hard to find it.
650 Since this case is rare anyway, don't bother trying; there would likely
651 be other insns that became dead anyway, which we wouldn't know to
652 delete. */
655 {
658 /* If a reg-note was found, it points to an insn to set CC0. This
659 insn is in the delay list of some other insn. So delete it from
660 the delay list it was in. */
662 {
666 }
667 else
668 {
669 /* The insn setting CC0 is our previous insn, but it may be in
670 a delay slot. It will be the last insn in the delay slot, if
671 it is. */
680 else
682 }
683 }
686 }
687 \f
688 /* Counters for delay-slot filling. */
690 #define NUM_REORG_FUNCTIONS 2
691 #define MAX_DELAY_HISTOGRAM 3
692 #define MAX_REORG_PASSES 2
700 static void
702 {
707 }
708 \f
709 /* Optimize the following cases:
711 1. When a conditional branch skips over only one instruction,
712 use an annulling branch and put that insn in the delay slot.
713 Use either a branch that annuls when the condition if true or
714 invert the test with a branch that annuls when the condition is
715 false. This saves insns, since otherwise we must copy an insn
716 from the L1 target.
718 (orig) (skip) (otherwise)
719 Bcc.n L1 Bcc',a L1 Bcc,a L1'
720 insn insn insn2
721 L1: L1: L1:
722 insn2 insn2 insn2
723 insn3 insn3 L1':
724 insn3
726 2. When a conditional branch skips over only one instruction,
727 and after that, it unconditionally branches somewhere else,
728 perform the similar optimization. This saves executing the
729 second branch in the case where the inverted condition is true.
731 Bcc.n L1 Bcc',a L2
732 insn insn
733 L1: L1:
734 Bra L2 Bra L2
736 INSN is a JUMP_INSN.
738 This should be expanded to skip over N insns, where N is the number
739 of delay slots required. */
741 static void
743 {
760 /* There are two cases where we are just executing one insn (we assume
761 here that a branch requires only one insn; this should be generalized
762 at some point): Where the branch goes around a single insn or where
763 we have one insn followed by a branch to the same label we branch to.
764 In both of these cases, inverting the jump and annulling the delay
765 slot give the same effect in fewer insns. */
770 {
772 {
777 }
784 /* Also, if we are targeting an unconditional
785 branch, thread our jump to the target of that branch. Don't
786 change this into a RETURN here, because it may not accept what
787 we have in the delay slot. We'll fix this up later. */
789 {
795 {
796 /* Recompute the flags based on TARGET_LABEL since threading
797 the jump to TARGET_LABEL may change the direction of the
798 jump (which may change the circumstances in which the
799 delay slot is nullified). */
803 }
804 }
807 }
808 }
809 \f
810 /* Encode and return branch direction and prediction information for
811 INSN assuming it will jump to LABEL.
813 Non conditional branches return no direction information and
814 are predicted as very likely taken. */
816 static int
818 {
821 /* get_jump_flags can be passed any insn with delay slots, these may
822 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
823 direction information, and only if they are conditional jumps.
825 If LABEL is a return, then there is no way to determine the branch
826 direction. */
832 flags
835 /* No valid direction information. */
836 else
840 }
842 /* Return truth value of the statement that this branch
843 is mostly taken. If we think that the branch is extremely likely
844 to be taken, we return 2. If the branch is slightly more likely to be
845 taken, return 1. If the branch is slightly less likely to be taken,
846 return 0 and if the branch is highly unlikely to be taken, return -1. */
848 static int
850 {
851 /* If branch probabilities are available, then use that number since it
852 always gives a correct answer. */
855 {
865 else
867 }
869 /* If there is no note, assume branches are not taken.
870 This should be rare. */
872 }
874 /* Return the condition under which INSN will branch to TARGET. If TARGET
875 is zero, return the condition under which INSN will return. If INSN is
876 an unconditional branch, return const_true_rtx. If INSN isn't a simple
877 type of jump, or it doesn't go to TARGET, return 0. */
879 static rtx
881 {
883 rtx src;
910 {
917 }
920 }
922 /* Return nonzero if CONDITION is more strict than the condition of
923 INSN, i.e., if INSN will always branch if CONDITION is true. */
925 static int
927 {
946 }
948 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
949 any insns already in the delay slot of JUMP. */
951 static int
953 {
957 /* Make sure all the delay slots of this jump would still
958 be valid after threading the jump. If they are still
959 valid, then return nonzero. */
964 #if ANNUL_IFFALSE_SLOTS
968 #endif
969 #if ANNUL_IFTRUE_SLOTS
973 #endif
978 }
980 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
981 any insns we wish to place in the delay slot of JUMP. */
983 static int
986 {
987 /* Make sure all the insns in DELAY_LIST would still be
988 valid after threading the jump. If they are still
989 valid, then return nonzero. */
996 #if ANNUL_IFFALSE_SLOTS
1000 #endif
1001 #if ANNUL_IFTRUE_SLOTS
1005 #endif
1010 }
1012 /* DELAY_LIST is a list of insns that have already been placed into delay
1013 slots. See if all of them have the same annulling status as ANNUL_TRUE_P.
1014 If not, return 0; otherwise return 1. */
1016 static int
1019 {
1028 }
1029 \f
1030 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
1031 the condition tested by INSN is CONDITION and the resources shown in
1032 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
1033 from SEQ's delay list, in addition to whatever insns it may execute
1034 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
1035 needed while searching for delay slot insns. Return the concatenated
1036 delay list if possible, otherwise, return 0.
1038 SLOTS_TO_FILL is the total number of slots required by INSN, and
1039 PSLOTS_FILLED points to the number filled so far (also the number of
1040 insns in DELAY_LIST). It is updated with the number that have been
1041 filled from the SEQUENCE, if any.
1043 PANNUL_P points to a nonzero value if we already know that we need
1044 to annul INSN. If this routine determines that annulling is needed,
1045 it may set that value nonzero.
1047 PNEW_THREAD points to a location that is to receive the place at which
1048 execution should continue. */
1050 static void
1058 {
1068 /* We can't do anything if there are more delay slots in SEQ than we
1069 can handle, or if we don't know that it will be a taken branch.
1070 We know that it will be a taken branch if it is either an unconditional
1071 branch or a conditional branch with a stricter branch condition.
1073 Also, exit if the branch has more than one set, since then it is computing
1074 other results that can't be ignored, e.g. the HPPA mov&branch instruction.
1075 ??? It may be possible to move other sets into INSN in addition to
1076 moving the instructions in the delay slots.
1078 We cannot steal the delay list if one of the instructions in the
1079 current delay_list modifies the condition codes and the jump in the
1080 sequence is a conditional jump. We cannot do this because we cannot
1081 change the direction of the jump because the condition codes
1082 will effect the direction of the jump in the sequence. */
1088 {
1092 }
1099 /* On some targets, branches with delay slots can have a limited
1100 displacement. Give the back end a chance to tell us we can't do
1101 this. */
1107 {
1114 /* If TRIAL sets CC0, we can't copy it, so we can't steal this
1115 delay list. */
1117 /* If TRIAL is from the fallthrough code of an annulled branch insn
1118 in SEQ, we cannot use it. */
1123 /* If this insn was already done (usually in a previous delay slot),
1124 pretend we put it in our delay slot. */
1129 /* We will end up re-vectoring this branch, so compute flags
1130 based on jumping to the new label. */
1144 {
1146 {
1147 /* Frame related instructions cannot go into annulled delay
1148 slots, it messes up the dwarf info. */
1152 }
1156 total_slots_filled++;
1160 }
1161 else
1163 }
1165 /* Record the effect of the instructions that were redundant and which
1166 we therefore decided not to copy. */
1169 {
1172 }
1174 /* Show the place to which we will be branching. */
1177 /* Add any new insns to the delay list and update the count of the
1178 number of slots filled. */
1186 }
1187 \f
1188 /* Similar to steal_delay_list_from_target except that SEQ is on the
1189 fallthrough path of INSN. Here we only do something if the delay insn
1190 of SEQ is an unconditional branch. In that case we steal its delay slot
1191 for INSN since unconditional branches are much easier to fill. */
1193 static void
1202 {
1210 /* We can't do anything if SEQ's delay insn isn't an
1211 unconditional branch. */
1217 {
1221 /* If TRIAL sets CC0, stealing it will move it too far from the use
1222 of CC0. */
1230 /* If this insn was already done, we don't need it. */
1232 {
1237 }
1247 {
1255 }
1256 else
1258 }
1262 }
1263 \f
1264 /* Try merging insns starting at THREAD which match exactly the insns in
1265 INSN's delay list.
1267 If all insns were matched and the insn was previously annulling, the
1268 annul bit will be cleared.
1270 For each insn that is merged, if the branch is or will be non-annulling,
1271 we delete the merged insn. */
1273 static void
1275 {
1291 /* If this is not an annulling branch, take into account anything needed in
1292 INSN's delay slot. This prevents two increments from being incorrectly
1293 folded into one. If we are annulling, this would be the correct
1294 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1295 will essentially disable this optimization. This method is somewhat of
1296 a kludge, but I don't see a better way.) */
1304 {
1310 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1316 /* We can't share an insn that sets cc0. */
1322 /* Update next_trial, in case try_split succeeded. */
1324 /* Likewise THREAD. */
1327 /* Have to test this condition if annul condition is different
1328 from (and less restrictive than) non-annulling one. */
1330 {
1333 {
1340 }
1341 else
1348 }
1352 }
1354 /* See if we stopped on a filled insn. If we did, try to see if its
1355 delay slots match. */
1361 {
1365 /* Account for resources set/needed by the filled insn. */
1370 {
1374 /* Account for resources set by the insn following NEXT_TO_MATCH
1375 inside INSN's delay list. */
1379 /* Account for resources set by the insn before DTRIAL and inside
1380 TRIAL's delay list. */
1389 /* Check that DTRIAL and NEXT_TO_MATCH does not reference a
1390 resource modified between them (only dtrial is checked because
1391 next_to_match and dtrial shall to be equal in order to hit
1392 this line) */
1395 {
1397 {
1405 }
1406 else
1414 }
1415 else
1416 {
1417 /* Keep track of the set/referenced resources for the delay
1418 slots of any trial insns we encounter. */
1421 }
1422 }
1423 }
1425 /* If all insns in the delay slot have been matched and we were previously
1426 annulling the branch, we need not any more. In that case delete all the
1427 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn in
1428 the delay list so that we know that it isn't only being used at the
1429 target. */
1431 {
1435 {
1440 }
1441 else
1442 {
1445 }
1451 }
1452 }
1453 \f
1454 /* See if INSN is redundant with an insn in front of TARGET. Often this
1455 is called when INSN is a candidate for a delay slot of TARGET.
1456 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1457 of INSN. Often INSN will be redundant with an insn in a delay slot of
1458 some previous insn. This happens when we have a series of branches to the
1459 same label; in that case the first insn at the target might want to go
1460 into each of the delay slots.
1462 If we are not careful, this routine can take up a significant fraction
1463 of the total compilation time (4%), but only wins rarely. Hence we
1464 speed this routine up by making two passes. The first pass goes back
1465 until it hits a label and sees if it finds an insn with an identical
1466 pattern. Only in this (relatively rare) event does it check for
1467 data conflicts.
1469 We do not split insns we encounter. This could cause us not to find a
1470 redundant insn, but the cost of splitting seems greater than the possible
1471 gain in rare cases. */
1475 {
1479 rtx pat;
1484 /* If INSN has any REG_UNUSED notes, it can't match anything since we
1485 are allowed to not actually assign to such a register. */
1489 /* Scan backwards looking for a match. */
1494 {
1495 /* (use (insn))s can come immediately after a barrier if the
1496 label that used to precede them has been deleted as dead.
1497 See delete_related_insns. */
1513 {
1514 /* Stop for a CALL and its delay slots because it is difficult to
1515 track its resource needs correctly. */
1519 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
1520 slots because it is difficult to track its resource needs
1521 correctly. */
1529 /* See if any of the insns in the delay slot match, updating
1530 resource requirements as we go. */
1537 /* If found a match, exit this loop early. */
1540 }
1545 }
1547 /* If we didn't find an insn that matches, return 0. */
1551 /* See what resources this insn sets and needs. If they overlap, or
1552 if this insn references CC0, it can't be redundant. */
1559 /* If TARGET is a SEQUENCE, get the main insn. */
1565 /* The insn requiring the delay may not set anything needed or set by
1566 INSN. */
1571 /* Insns we pass may not set either NEEDED or SET, so merge them for
1572 simpler tests. */
1576 /* This insn isn't redundant if it conflicts with an insn that either is
1577 or will be in a delay slot of TARGET. */
1591 /* Scan backwards until we reach a label or an insn that uses something
1592 INSN sets or sets something insn uses or sets. */
1598 {
1611 {
1615 /* If this is a CALL_INSN and its delay slots, it is hard to track
1616 the resource needs properly, so give up. */
1620 /* If this is an INSN or JUMP_INSN with delayed effects, it
1621 is hard to track the resource needs properly, so give up. */
1632 /* See if any of the insns in the delay slot match, updating
1633 resource requirements as we go. */
1635 {
1638 /* If an insn will be annulled if the branch is false, it isn't
1639 considered as a possible duplicate insn. */
1642 {
1643 /* Show that this insn will be used in the sequel. */
1646 }
1648 /* Unless this is an annulled insn from the target of a branch,
1649 we must stop if it sets anything needed or set by INSN. */
1653 }
1655 /* If the insn requiring the delay slot conflicts with INSN, we
1656 must stop. */
1659 }
1660 else
1661 {
1662 /* See if TRIAL is the same as INSN. */
1667 /* Can't go any further if TRIAL conflicts with INSN. */
1670 }
1671 }
1674 }
1675 \f
1676 /* Return 1 if THREAD can only be executed in one way. If LABEL is nonzero,
1677 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
1678 is nonzero, we are allowed to fall into this thread; otherwise, we are
1679 not.
1681 If LABEL is used more than one or we pass a label other than LABEL before
1682 finding an active insn, we do not own this thread. */
1684 static int
1686 {
1690 /* We don't own the function end. */
1694 /* We have a non-NULL insn. */
1697 /* Get the first active insn, or THREAD_INSN, if it is an active insn. */
1708 /* Ensure that we reach a BARRIER before any insn or label. */
1720 }
1721 \f
1722 /* Called when INSN is being moved from a location near the target of a jump.
1723 We leave a marker of the form (use (INSN)) immediately in front of WHERE
1724 for mark_target_live_regs. These markers will be deleted at the end.
1726 We used to try to update the live status of registers if WHERE is at
1727 the start of a basic block, but that can't work since we may remove a
1728 BARRIER in relax_delay_slots. */
1730 static void
1732 {
1735 /* INSN might be making a value live in a block where it didn't use to
1736 be. So recompute liveness information for this block. */
1738 }
1740 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
1741 the basic block containing the jump. */
1743 static int
1745 {
1748 }
1750 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
1751 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
1752 that reference values used in INSN. If we find one, then we move the
1753 REG_DEAD note to INSN.
1755 This is needed to handle the case where a later insn (after INSN) has a
1756 REG_DEAD note for a register used by INSN, and this later insn subsequently
1757 gets moved before a CODE_LABEL because it is a redundant insn. In this
1758 case, mark_target_live_regs may be confused into thinking the register
1759 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
1761 static void
1763 {
1770 {
1778 {
1779 /* Move the REG_DEAD note from P to INSN. */
1783 }
1784 }
1785 }
1787 /* Called when an insn redundant with start_insn is deleted. If there
1788 is a REG_DEAD note for the target of start_insn between start_insn
1789 and stop_insn, then the REG_DEAD note needs to be deleted since the
1790 value no longer dies there.
1792 If the REG_DEAD note isn't deleted, then mark_target_live_regs may be
1793 confused into thinking the register is dead. */
1795 static void
1797 {
1804 {
1812 {
1815 }
1816 }
1817 }
1819 /* Delete any REG_UNUSED notes that exist on INSN but not on OTHER_INSN.
1821 This handles the case of udivmodXi4 instructions which optimize their
1822 output depending on whether any REG_UNUSED notes are present. We must
1823 make sure that INSN calculates as many results as OTHER_INSN does. */
1825 static void
1827 {
1831 {
1840 }
1841 }
1842 \f
1845 /* Return the label before INSN, or put a new label there. If SIBLING is
1846 non-zero, it is another label associated with the new label (if any),
1847 typically the former target of the jump that will be redirected to
1848 the new label. */
1852 {
1855 /* Find an existing label at this point
1856 or make a new one if there is none. */
1860 {
1867 {
1870 }
1871 }
1873 }
1875 /* Scan a function looking for insns that need a delay slot and find insns to
1876 put into the delay slot.
1878 NON_JUMPS_P is nonzero if we are to only try to fill non-jump insns (such
1879 as calls). We do these first since we don't want jump insns (that are
1880 easier to fill) to get the only insns that could be used for non-jump insns.
1881 When it is zero, only try to fill JUMP_INSNs.
1883 When slots are filled in this manner, the insns (including the
1884 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
1885 it is possible to tell whether a delay slot has really been filled
1886 or not. `final' knows how to deal with this, by communicating
1887 through FINAL_SEQUENCE. */
1889 static void
1891 {
1893 rtx pat;
1901 {
1903 /* Get the next insn to fill. If it has already had any slots assigned,
1904 we can't do anything with it. Maybe we'll improve this later. */
1915 /* It may have been that this insn used to need delay slots, but
1916 now doesn't; ignore in that case. This can happen, for example,
1917 on the HP PA RISC, where the number of delay slots depends on
1918 what insns are nearby. */
1921 /* Some machine description have defined instructions to have
1922 delay slots only in certain circumstances which may depend on
1923 nearby insns (which change due to reorg's actions).
1925 For example, the PA port normally has delay slots for unconditional
1926 jumps.
1928 However, the PA port claims such jumps do not have a delay slot
1929 if they are immediate successors of certain CALL_INSNs. This
1930 allows the port to favor filling the delay slot of the call with
1931 the unconditional jump. */
1935 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
1936 says how many. After initialization, first try optimizing
1938 call _foo call _foo
1939 nop add %o7,.-L1,%o7
1940 b,a L1
1941 nop
1943 If this case applies, the delay slot of the call is filled with
1944 the unconditional jump. This is done first to avoid having the
1945 delay slot of the call filled in the backward scan. Also, since
1946 the unconditional jump is likely to also have a delay slot, that
1947 insn must exist when it is subsequently scanned.
1949 This is tried on each insn with delay slots as some machines
1950 have insns which perform calls, but are not represented as
1951 CALL_INSNs. */
1958 else
1967 {
1969 slots_filled++;
1972 /* TRIAL may have had its delay slot filled, then unfilled. When
1973 the delay slot is unfilled, TRIAL is placed back on the unfilled
1974 slots obstack. Unfortunately, it is placed on the end of the
1975 obstack, not in its original location. Therefore, we must search
1976 from entry i + 1 to the end of the unfilled slots obstack to
1977 try and find TRIAL. */
1980 tmp++;
1982 /* Remove the unconditional jump from consideration for delay slot
1983 filling and unthread it. */
1986 {
1993 }
1994 }
1996 /* Now, scan backwards from the insn to search for a potential
1997 delay-slot candidate. Stop searching when a label or jump is hit.
1999 For each candidate, if it is to go into the delay slot (moved
2000 forward in execution sequence), it must not need or set any resources
2001 that were set by later insns and must not set any resources that
2002 are needed for those insns.
2004 The delay slot insn itself sets resources unless it is a call
2005 (in which case the called routine, not the insn itself, is doing
2006 the setting). */
2009 {
2010 /* If the flags register is dead after the insn, then we want to be
2011 able to accept a candidate that clobbers it. For this purpose,
2012 we need to filter the flags register during life analysis, so
2013 that it doesn't create RAW and WAW dependencies, while still
2014 creating the necessary WAR dependencies. */
2015 bool filter_flags
2024 {
2027 }
2032 {
2035 /* This must be an INSN or CALL_INSN. */
2038 /* Stand-alone USE and CLOBBER are just for flow. */
2042 /* And DEBUG_INSNs never go into delay slots. */
2046 /* Check for resource conflict first, to avoid unnecessary
2047 splitting. */
2053 /* Can't separate set of cc0 from its use. */
2056 {
2060 {
2061 /* In this case, we are searching backward, so if we
2062 find insns to put on the delay list, we want
2063 to put them at the head, rather than the
2064 tail, of the list. */
2073 }
2074 }
2078 {
2080 /* If the flags register is set, then it doesn't create RAW
2081 dependencies any longer and it also doesn't create WAW
2082 dependencies since it's dead after the original insn. */
2084 {
2087 }
2088 }
2090 }
2091 }
2093 /* If all needed slots haven't been filled, we come here. */
2095 /* Try to optimize case of jumping around a single insn. */
2102 {
2106 }
2108 /* Try to get insns from beyond the insn needing the delay slot.
2109 These insns can neither set or reference resources set in insns being
2110 skipped, cannot set resources in the insn being skipped, and, if this
2111 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
2112 call might not return).
2114 There used to be code which continued past the target label if
2115 we saw all uses of the target label. This code did not work,
2116 because it failed to account for some instructions which were
2117 both annulled and marked as from the target. This can happen as a
2118 result of optimize_skip. Since this code was redundant with
2119 fill_eager_delay_slots anyways, it was just deleted. */
2122 /* If this instruction could throw an exception which is
2123 caught in the same function, then it's not safe to fill
2124 the delay slot with an instruction from beyond this
2125 point. For example, consider:
2127 int i = 2;
2129 try {
2130 f();
2131 i = 3;
2132 } catch (...) {}
2134 return i;
2136 Even though `i' is a local variable, we must be sure not
2137 to put `i = 3' in the delay slot if `f' might throw an
2138 exception.
2140 Presumably, we should also check to see if we could get
2141 back to this function via `setjmp'. */
2144 {
2158 {
2161 /* This must be an INSN or CALL_INSN. */
2164 /* Stand-alone USE and CLOBBER are just for flow. */
2168 /* And DEBUG_INSNs do not go in delay slots. */
2172 /* If this already has filled delay slots, get the insn needing
2173 the delay slots. */
2176 else
2179 /* Stop our search when seeing a jump. */
2183 /* See if we have a resource problem before we try to split. */
2193 {
2203 }
2208 /* Ensure we don't put insns between the setting of cc and the
2209 comparison by moving a setting of cc into an earlier delay
2210 slot since these insns could clobber the condition code. */
2213 /* If this is a call, we might not get here. */
2216 }
2218 /* If there are slots left to fill and our search was stopped by an
2219 unconditional branch, try the insn at the branch target. We can
2220 redirect the branch if it works.
2222 Don't do this if the insn at the branch target is a branch. */
2224 && trial
2239 {
2240 /* See comment in relax_delay_slots about necessity of using
2241 next_real_nondebug_insn here. */
2246 else
2250 {
2253 slots_filled++;
2255 new_label);
2256 }
2257 }
2258 }
2260 /* If this is an unconditional jump, then try to get insns from the
2261 target of the jump. */
2280 }
2281 }
2282 \f
2283 /* Follow any unconditional jump at LABEL, for the purpose of redirecting JUMP;
2284 return the ultimate label reached by any such chain of jumps.
2285 Return a suitable return rtx if the chain ultimately leads to a
2286 return instruction.
2287 If LABEL is not followed by a jump, return LABEL.
2288 If the chain loops or we can't find end, return LABEL,
2289 since that tells caller to avoid changing the insn.
2290 If the returned label is obtained by following a crossing jump,
2291 set *CROSSING to true, otherwise set it to false. */
2293 static rtx
2295 {
2315 depth++)
2316 {
2319 /* If we have found a cycle, make the insn jump to itself. */
2323 /* Cannot follow returns and cannot look through tablejumps. */
2337 }
2341 }
2343 /* Try to find insns to place in delay slots.
2345 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
2346 or is an unconditional branch if CONDITION is const_true_rtx.
2347 *PSLOTS_FILLED is updated with the number of slots that we have filled.
2349 THREAD is a flow-of-control, either the insns to be executed if the
2350 branch is true or if the branch is false, THREAD_IF_TRUE says which.
2352 OPPOSITE_THREAD is the thread in the opposite direction. It is used
2353 to see if any potential delay slot insns set things needed there.
2355 LIKELY is nonzero if it is extremely likely that the branch will be
2356 taken and THREAD_IF_TRUE is set. This is used for the branch at the
2357 end of a loop back up to the top.
2359 OWN_THREAD is true if we are the only user of the thread, i.e. it is
2360 the target of the jump when we are the only jump going there.
2362 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
2363 case, we can only take insns from the head of the thread for our delay
2364 slot. We then adjust the jump to point after the insns we have taken. */
2366 static void
2371 {
2372 rtx new_thread;
2379 /* Validate our arguments. */
2385 /* If our thread is the end of subroutine, we can't get any delay
2386 insns from that. */
2392 /* If this is an unconditional branch, nothing is needed at the
2393 opposite thread. Otherwise, compute what is needed there. */
2396 else
2399 /* If the insn at THREAD can be split, do it here to avoid having to
2400 update THREAD and NEW_THREAD if it is done in the loop below. Also
2401 initialize NEW_THREAD. */
2405 /* Scan insns at THREAD. We are looking for an insn that can be removed
2406 from THREAD (it neither sets nor references resources that were set
2407 ahead of it and it doesn't set anything needs by the insns ahead of
2408 it) and that either can be placed in an annulling insn or aren't
2409 needed at OPPOSITE_THREAD. */
2414 /* If we do not own this thread, we must stop as soon as we find
2415 something that we can't put in a delay slot, since all we can do
2416 is branch into THREAD at a later point. Therefore, labels stop
2417 the search if this is not the `true' thread. */
2422 {
2425 /* If we have passed a label, we no longer own this thread. */
2427 {
2430 }
2439 /* If TRIAL conflicts with the insns ahead of it, we lose. Also,
2440 don't separate or copy insns that set and use CC0. */
2447 {
2450 /* If TRIAL is redundant with some insn before INSN, we don't
2451 actually need to add it to the delay list; we can merely pretend
2452 we did. */
2454 {
2457 {
2460 {
2464 }
2467 }
2468 else
2469 {
2472 }
2475 }
2477 /* There are two ways we can win: If TRIAL doesn't set anything
2478 needed at the opposite thread and can't trap, or if it can
2479 go into an annulled delay slot. But we want neither to copy
2480 nor to speculate frame-related insns. */
2487 {
2497 }
2501 {
2514 {
2518 winner:
2523 /* If we own this thread, delete the insn. If this is the
2524 destination of a branch, show that a basic block status
2525 may have been updated. In any case, mark the new
2526 starting point of this thread. */
2528 {
2529 rtx note;
2533 {
2537 }
2539 /* We are moving this insn, not deleting it. We must
2540 temporarily increment the use count on any referenced
2541 label lest it be deleted by delete_related_insns. */
2547 {
2548 /* REG_LABEL_OPERAND could be
2549 NOTE_INSN_DELETED_LABEL too. */
2552 else
2555 }
2566 {
2567 /* REG_LABEL_OPERAND could be
2568 NOTE_INSN_DELETED_LABEL too. */
2571 else
2574 }
2577 }
2578 else
2588 {
2589 /* Even though we have filled all the slots, we
2590 may be branching to a location that has a
2591 redundant insn. Skip any if so. */
2598 && (prior_insn
2601 {
2602 /* We know we do not own the thread, so no need
2603 to call update_block and delete_insn. */
2606 new_thread
2608 }
2610 }
2613 }
2614 }
2615 }
2617 /* This insn can't go into a delay slot. */
2622 /* Ensure we don't put insns between the setting of cc and the comparison
2623 by moving a setting of cc into an earlier delay slot since these insns
2624 could clobber the condition code. */
2627 /* If this insn is a register-register copy and the next insn has
2628 a use of our destination, change it to use our source. That way,
2629 it will become a candidate for our delay slot the next time
2630 through this loop. This case occurs commonly in loops that
2631 scan a list.
2633 We could check for more complex cases than those tested below,
2634 but it doesn't seem worth it. It might also be a good idea to try
2635 to swap the two insns. That might do better.
2637 We can't do this if the next insn modifies our destination, because
2638 that would make the replacement into the insn invalid. We also can't
2639 do this if it modifies our source, because it might be an earlyclobber
2640 operand. This latter test also prevents updating the contents of
2641 a PRE_INC. We also can't do this if there's overlap of source and
2642 destination. Overlap may happen for larger-than-register-size modes. */
2648 {
2658 }
2659 }
2661 /* If we stopped on a branch insn that has delay slots, see if we can
2662 steal some of the insns in those slots. */
2666 {
2668 /* If this is the `true' thread, we will want to follow the jump,
2669 so we can only do this if we have taken everything up to here. */
2671 {
2677 /* If we owned the thread and are told that it branched
2678 elsewhere, make sure we own the thread at the new location. */
2681 }
2687 }
2689 /* If we haven't found anything for this delay slot and it is very
2690 likely that the branch will be taken, see if the insn at our target
2691 increments or decrements a register with an increment that does not
2692 depend on the destination register. If so, try to place the opposite
2693 arithmetic insn after the jump insn and put the arithmetic insn in the
2694 delay slot. If we can't do this, return. */
2701 {
2702 rtx dest;
2703 rtx src;
2705 /* We know "new_thread" is an insn due to NONJUMP_INSN_P (new_thread)
2706 above. */
2723 {
2725 rtx new_arith;
2728 /* If this is a constant adjustment, use the same code with
2729 the negated constant. Otherwise, reverse the sense of the
2730 arithmetic. */
2734 else
2743 {
2746 }
2749 {
2752 {
2756 }
2758 }
2759 else
2768 }
2769 }
2774 /* If we are to branch into the middle of this thread, find an appropriate
2775 label or make a new one if none, and redirect INSN to it. If we hit the
2776 end of the function, use the end-of-function label. */
2778 {
2779 rtx label;
2795 else
2800 {
2804 }
2805 }
2806 }
2807 \f
2808 /* Make another attempt to find insns to place in delay slots.
2810 We previously looked for insns located in front of the delay insn
2811 and, for non-jump delay insns, located behind the delay insn.
2813 Here only try to schedule jump insns and try to move insns from either
2814 the target or the following insns into the delay slot. If annulling is
2815 supported, we will be likely to do this. Otherwise, we can do this only
2816 if safe. */
2818 static void
2820 {
2826 {
2827 rtx condition;
2844 /* Some machine description have defined instructions to have
2845 delay slots only in certain circumstances which may depend on
2846 nearby insns (which change due to reorg's actions).
2848 For example, the PA port normally has delay slots for unconditional
2849 jumps.
2851 However, the PA port claims such jumps do not have a delay slot
2852 if they are immediate successors of certain CALL_INSNs. This
2853 allows the port to favor filling the delay slot of the call with
2854 the unconditional jump. */
2865 /* Get the next active fallthrough and target insns and see if we own
2866 them. Then see whether the branch is likely true. We don't need
2867 to do a lot of this for unconditional branches. */
2873 {
2877 }
2878 else
2879 {
2883 }
2885 /* If this insn is expected to branch, first try to get insns from our
2886 target, then our fallthrough insns. If it is not expected to branch,
2887 try the other order. */
2890 {
2893 own_target,
2897 {
2898 /* Even though we didn't find anything for delay slots,
2899 we might have found a redundant insn which we deleted
2900 from the thread that was filled. So we have to recompute
2901 the next insn at the target. */
2909 }
2910 }
2911 else
2912 {
2922 }
2932 }
2933 }
2934 \f
2937 /* Recursively delete prior insns that compute the value (used only by INSN
2938 which the caller is deleting) stored in the register mentioned by NOTE
2939 which is a REG_DEAD note associated with INSN. */
2941 static void
2943 {
2951 {
2954 /* If we reach a CALL which is not calling a const function
2955 or the callee pops the arguments, then give up. */
2961 /* If we reach a SEQUENCE, it is too complex to try to
2962 do anything with it, so give up. We can be run during
2963 and after reorg, so SEQUENCE rtl can legitimately show
2964 up here. */
2970 /* reorg creates USEs that look like this. We leave them
2971 alone because reorg needs them for its own purposes. */
2975 {
2980 {
2981 /* If we find a SET of something else, we can't
2982 delete the insn. */
2987 {
2993 }
2997 }
3000 {
3010 /* We may have a multi-word hard register and some, but not
3011 all, of the words of the register are needed in subsequent
3012 insns. Write REG_UNUSED notes for those parts that were not
3013 needed. */
3016 {
3027 }
3028 }
3031 }
3033 /* If PAT references the register that dies here, it is an
3034 additional use. Hence any prior SET isn't dead. However, this
3035 insn becomes the new place for the REG_DEAD note. */
3037 {
3041 }
3042 }
3043 }
3045 /* Delete INSN and recursively delete insns that compute values used only
3046 by INSN. This uses the REG_DEAD notes computed during flow analysis.
3048 Look at all our REG_DEAD notes. If a previous insn does nothing other
3049 than set a register that dies in this insn, we can delete that insn
3050 as well.
3052 On machines with CC0, if CC0 is used in this insn, we may be able to
3053 delete the insn that set it. */
3055 static void
3057 {
3061 {
3063 /* We assume that at this stage
3064 CC's are always set explicitly
3065 and always immediately before the jump that
3066 will use them. So if the previous insn
3067 exists to set the CC's, delete it
3068 (unless it performs auto-increments, etc.). */
3071 {
3075 else
3076 /* Otherwise, show that cc0 won't be used. */
3078 }
3079 }
3082 {
3086 /* Verify that the REG_NOTE is legitimate. */
3091 }
3094 }
3096 /* If all INSN does is set the pc, delete it,
3097 and delete the insn that set the condition codes for it
3098 if that's what the previous thing was. */
3100 static void
3102 {
3107 }
3111 {
3114 {
3120 }
3122 }
3124 /* Return TRUE if there is a NOTE_INSN_SWITCH_TEXT_SECTIONS note in between
3125 BEG and END. */
3127 static bool
3129 {
3135 }
3137 \f
3138 /* Once we have tried two ways to fill a delay slot, make a pass over the
3139 code to try to improve the results and to do such things as more jump
3140 threading. */
3142 static void
3144 {
3148 rtx target_label;
3150 /* Look at every JUMP_INSN and see if we can improve it. */
3152 {
3158 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3159 the next insn, or jumps to a label that is not the last of a
3160 group of consecutive labels. */
3164 {
3166 target_label
3176 {
3179 }
3182 {
3186 }
3188 /* See if this jump conditionally branches around an unconditional
3189 jump. If so, invert this jump and point it to the target of the
3190 second jump. Check if it's possible on the target. */
3193 && target_label
3198 {
3201 /* Be careful how we do this to avoid deleting code or
3202 labels that are momentarily dead. See similar optimization
3203 in jump.c.
3205 We also need to ensure we properly handle the case when
3206 invert_jump fails. */
3213 {
3216 }
3225 }
3226 }
3228 /* If this is an unconditional jump and the previous insn is a
3229 conditional jump, try reversing the condition of the previous
3230 insn and swapping our targets. The next pass might be able to
3231 fill the slots.
3233 Don't do this if we expect the conditional branch to be true, because
3234 we would then be making the more common case longer. */
3241 {
3247 }
3249 /* Now look only at cases where we have a filled delay slot. */
3256 /* See if the first insn in the delay slot is redundant with some
3257 previous insn. Remove it from the delay slot if so; then set up
3258 to reprocess this insn. */
3260 {
3266 }
3268 /* See if we have a RETURN insn with a filled delay slot followed
3269 by a RETURN insn with an unfilled a delay slot. If so, we can delete
3270 the first RETURN (but not its delay insn). This gives the same
3271 effect in fewer instructions.
3273 Only do so if optimizing for size since this results in slower, but
3274 smaller code. */
3277 && next
3280 {
3284 /* Delete the RETURN and just execute the delay list insns.
3286 We do this by deleting the INSN containing the SEQUENCE, then
3287 re-emitting the insns separately, and then deleting the RETURN.
3288 This allows the count of the jump target to be properly
3289 decremented.
3291 Note that we need to change the INSN_UID of the re-emitted insns
3292 since it is used to hash the insns for mark_target_live_regs and
3293 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3295 Clear the from target bit, since these insns are no longer
3296 in delay slots. */
3309 }
3311 /* Now look only at the cases where we have a filled JUMP_INSN. */
3322 /* If this jump goes to another unconditional jump, thread it, but
3323 don't convert a jump into a RETURN here. */
3325 delay_jump_insn,
3332 {
3337 }
3339 /* If the first insn at TARGET_LABEL is redundant with a previous
3340 insn, redirect the jump to the following insn and process again.
3341 We use next_real_nondebug_insn instead of next_active_insn so we
3342 don't skip USE-markers, or we'll end up with incorrect
3343 liveness info. */
3348 {
3349 /* Figure out where to emit the special USE insn so we don't
3350 later incorrectly compute register live/death info. */
3356 {
3357 /* Insert the special USE insn and update dataflow info.
3358 We know "trial" is an insn here as it is the output of
3359 next_real_nondebug_insn () above. */
3362 /* Now emit a label before the special USE insn, and
3363 redirect our jump to the new label. */
3368 }
3369 }
3371 /* Similarly, if it is an unconditional jump with one insn in its
3372 delay list and that insn is redundant, thread the jump. */
3380 {
3388 {
3393 }
3394 }
3396 /* See if we have a simple (conditional) jump that is useless. */
3402 /* If the last insn in the delay slot sets CC0 for some insn,
3403 various code assumes that it is in a delay slot. We could
3404 put it back where it belonged and delete the register notes,
3405 but it doesn't seem worthwhile in this uncommon case. */
3406 && (!HAVE_cc0
3409 {
3413 /* All this insn does is execute its delay list and jump to the
3414 following insn. So delete the jump and just execute the delay
3415 list insns.
3417 We do this by deleting the INSN containing the SEQUENCE, then
3418 re-emitting the insns separately, and then deleting the jump.
3419 This allows the count of the jump target to be properly
3420 decremented.
3422 Note that we need to change the INSN_UID of the re-emitted insns
3423 since it is used to hash the insns for mark_target_live_regs and
3424 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3426 Clear the from target bit, since these insns are no longer
3427 in delay slots. */
3440 }
3442 /* See if this is an unconditional jump around a single insn which is
3443 identical to the one in its delay slot. In this case, we can just
3444 delete the branch and the insn in its delay slot. */
3450 {
3453 }
3455 /* See if this jump (with its delay slots) conditionally branches
3456 around an unconditional jump (without delay slots). If so, invert
3457 this jump and point it to the target of the second jump. We cannot
3458 do this for annulled jumps, though. Again, don't convert a jump to
3459 a RETURN here. */
3466 {
3473 /* find_end_label can generate a new label. Check this first. */
3478 {
3479 /* Be careful how we do this to avoid deleting code or labels
3480 that are momentarily dead. See similar optimization in
3481 jump.c */
3486 {
3489 /* Must update the INSN_FROM_TARGET_P bits now that
3490 the branch is reversed, so that mark_target_live_regs
3491 will handle the delay slot insn correctly. */
3493 {
3496 }
3500 }
3505 }
3506 }
3508 /* If we own the thread opposite the way this insn branches, see if we
3509 can merge its delay slots with following insns. */
3518 /* If we get here, we haven't deleted INSN. But we may have deleted
3519 NEXT, so recompute it. */
3521 }
3522 }
3523 \f
3525 /* Look for filled jumps to the end of function label. We can try to convert
3526 them into RETURN insns if the insns in the delay slot are valid for the
3527 RETURN as well. */
3529 static void
3531 {
3538 /* See if there is a RETURN insn in the function other than the one we
3539 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
3540 into a RETURN to jump to it. */
3543 {
3547 else
3550 }
3552 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
3553 was equal to END_OF_FUNCTION_LABEL. */
3559 /* Clear the list of insns to fill so we can use it. */
3563 {
3567 /* Only look at filled JUMP_INSNs that go to the end of function
3568 label. */
3581 {
3584 }
3586 {
3589 }
3590 else
3595 /* If we can't make the jump into a RETURN, try to redirect it to the best
3596 RETURN and go on to the next insn. */
3598 {
3599 /* Make sure redirecting the jump will not invalidate the delay
3600 slot insns. */
3604 }
3606 /* See if this RETURN can accept the insns current in its delay slot.
3607 It can if it has more or an equal number of slots and the contents
3608 of each is valid. */
3613 {
3616 #if ANNUL_IFFALSE_SLOTS
3621 #endif
3622 #if ANNUL_IFTRUE_SLOTS
3627 #endif
3631 }
3632 else
3638 /* We have to do something with this insn. If it is an unconditional
3639 RETURN, delete the SEQUENCE and output the individual insns,
3640 followed by the RETURN. Then set things up so we try to find
3641 insns for its delay slots, if it needs some. */
3643 {
3655 }
3656 else
3657 /* It is probably more efficient to keep this with its current
3658 delay slot as a branch to a RETURN. */
3660 }
3662 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
3663 new delay slots we have created. */
3672 }
3673 \f
3674 /* Try to find insns to place in delay slots. */
3676 static void
3678 {
3683 /* If the current function has no insns other than the prologue and
3684 epilogue, then do not try to fill any delay slots. */
3688 /* Find the highest INSN_UID and allocate and initialize our map from
3689 INSN_UID's to position in code. */
3691 {
3697 }
3703 /* Initialize the list of insns that need filling. */
3705 {
3708 }
3711 {
3712 rtx target;
3714 /* Skip vector tables. We can't get attributes for them. */
3725 /* Ensure all jumps go to the last of a set of consecutive labels. */
3732 }
3736 /* Show we haven't computed an end-of-function label yet. */
3739 /* Initialize the statistics for this function. */
3743 /* Now do the delay slot filling. Try everything twice in case earlier
3744 changes make more slots fillable. */
3748 reorg_pass_number++)
3749 {
3755 }
3757 /* If we made an end of function label, indicate that it is now
3758 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
3759 If it is now unused, delete it. */
3773 /* Delete any USE insns made by update_block; subsequent passes don't need
3774 them or know how to deal with them. */
3776 {
3782 }
3786 /* It is not clear why the line below is needed, but it does seem to be. */
3790 {
3797 reorg_pass_number++)
3798 {
3801 {
3810 {
3816 }
3818 }
3819 }
3823 {
3828 {
3830 {
3831 rtx control;
3838 else
3840 }
3843 }
3844 }
3848 {
3850 {
3855 }
3856 }
3860 {
3864 {
3866 {
3871 }
3872 }
3874 }
3877 }
3880 {
3883 }
3888 }
3889 \f
3890 /* Run delay slot optimization. */
3891 static unsigned int
3893 {
3898 }
3903 {
3913 };
3916 {
3920 {}
3922 /* opt_pass methods: */
3925 {
3927 }
3931 bool
3933 {
3934 /* At -O0 dataflow info isn't updated after RA. */
3939 }
3943 rtl_opt_pass *
3945 {
3947 }
3949 /* Machine dependent reorg pass. */
3954 {
3964 };
3967 {
3971 {}
3973 /* opt_pass methods: */
3975 {
3977 }
3980 {
3983 }
3989 rtl_opt_pass *
3991 {
3993 }