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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
91 /* This file should be included last. */
98 #ifndef CHECK_STACK_LIMIT
99 #define CHECK_STACK_LIMIT (-1)
100 #endif
102 /* Return index of given mode in mult and division cost tables. */
103 #define MODE_INDEX(mode) \
104 ((mode) == QImode ? 0 \
105 : (mode) == HImode ? 1 \
106 : (mode) == SImode ? 2 \
107 : (mode) == DImode ? 3 \
108 : 4)
110 /* Processor costs (relative to an add) */
111 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
112 #define COSTS_N_BYTES(N) ((N) * 2)
114 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
123 const
146 in QImode, HImode and SImode.
147 Relative to reg-reg move (2). */
151 in SFmode, DFmode and XFmode */
153 in SFmode, DFmode and XFmode */
156 in SImode and DImode */
158 in SImode and DImode */
161 in SImode, DImode and TImode */
163 in SImode, DImode and TImode */
176 ix86_size_memcpy,
177 ix86_size_memset,
189 };
191 /* Processor costs (relative to an add) */
194 DUMMY_STRINGOP_ALGS};
197 DUMMY_STRINGOP_ALGS};
199 static const
222 in QImode, HImode and SImode.
223 Relative to reg-reg move (2). */
227 in SFmode, DFmode and XFmode */
229 in SFmode, DFmode and XFmode */
232 in SImode and DImode */
234 in SImode and DImode */
237 in SImode, DImode and TImode */
239 in SImode, DImode and TImode */
252 i386_memcpy,
253 i386_memset,
265 };
269 DUMMY_STRINGOP_ALGS};
272 DUMMY_STRINGOP_ALGS};
274 static const
297 in QImode, HImode and SImode.
298 Relative to reg-reg move (2). */
302 in SFmode, DFmode and XFmode */
304 in SFmode, DFmode and XFmode */
307 in SImode and DImode */
309 in SImode and DImode */
312 in SImode, DImode and TImode */
314 in SImode, DImode and TImode */
317 shared for code and data, so 4kB is
318 not really precise. */
329 i486_memcpy,
330 i486_memset,
342 };
346 DUMMY_STRINGOP_ALGS};
349 DUMMY_STRINGOP_ALGS};
351 static const
374 in QImode, HImode and SImode.
375 Relative to reg-reg move (2). */
379 in SFmode, DFmode and XFmode */
381 in SFmode, DFmode and XFmode */
384 in SImode and DImode */
386 in SImode and DImode */
389 in SImode, DImode and TImode */
391 in SImode, DImode and TImode */
404 pentium_memcpy,
405 pentium_memset,
417 };
419 static const
442 in QImode, HImode and SImode.
443 Relative to reg-reg move (2). */
447 in SFmode, DFmode and XFmode */
449 in SFmode, DFmode and XFmode */
452 in SImode and DImode */
454 in SImode and DImode */
457 in SImode, DImode and TImode */
459 in SImode, DImode and TImode */
472 pentium_memcpy,
473 pentium_memset,
485 };
487 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
488 (we ensure the alignment). For small blocks inline loop is still a
489 noticeable win, for bigger blocks either rep movsl or rep movsb is
490 way to go. Rep movsb has apparently more expensive startup time in CPU,
491 but after 4K the difference is down in the noise. */
496 DUMMY_STRINGOP_ALGS};
501 DUMMY_STRINGOP_ALGS};
502 static const
525 in QImode, HImode and SImode.
526 Relative to reg-reg move (2). */
530 in SFmode, DFmode and XFmode */
532 in SFmode, DFmode and XFmode */
535 in SImode and DImode */
537 in SImode and DImode */
540 in SImode, DImode and TImode */
542 in SImode, DImode and TImode */
555 pentiumpro_memcpy,
556 pentiumpro_memset,
568 };
572 DUMMY_STRINGOP_ALGS};
575 DUMMY_STRINGOP_ALGS};
576 static const
599 in QImode, HImode and SImode.
600 Relative to reg-reg move (2). */
604 in SFmode, DFmode and XFmode */
606 in SFmode, DFmode and XFmode */
610 in SImode and DImode */
612 in SImode and DImode */
615 in SImode, DImode and TImode */
617 in SImode, DImode and TImode */
630 geode_memcpy,
631 geode_memset,
643 };
647 DUMMY_STRINGOP_ALGS};
650 DUMMY_STRINGOP_ALGS};
651 static const
674 in QImode, HImode and SImode.
675 Relative to reg-reg move (2). */
679 in SFmode, DFmode and XFmode */
681 in SFmode, DFmode and XFmode */
684 in SImode and DImode */
686 in SImode and DImode */
689 in SImode, DImode and TImode */
691 in SImode, DImode and TImode */
695 have integrated l2 cache, but
696 optimizing for k6 is not important
697 enough to worry about that. */
707 k6_memcpy,
708 k6_memset,
720 };
722 /* For some reason, Athlon deals better with REP prefix (relative to loops)
723 compared to K8. Alignment becomes important after 8 bytes for memcpy and
724 128 bytes for memset. */
727 DUMMY_STRINGOP_ALGS};
730 DUMMY_STRINGOP_ALGS};
731 static const
754 in QImode, HImode and SImode.
755 Relative to reg-reg move (2). */
759 in SFmode, DFmode and XFmode */
761 in SFmode, DFmode and XFmode */
764 in SImode and DImode */
766 in SImode and DImode */
769 in SImode, DImode and TImode */
771 in SImode, DImode and TImode */
784 athlon_memcpy,
785 athlon_memset,
797 };
799 /* K8 has optimized REP instruction for medium sized blocks, but for very
800 small blocks it is better to use loop. For large blocks, libcall can
801 do nontemporary accesses and beat inline considerably. */
812 static const
835 in QImode, HImode and SImode.
836 Relative to reg-reg move (2). */
840 in SFmode, DFmode and XFmode */
842 in SFmode, DFmode and XFmode */
845 in SImode and DImode */
847 in SImode and DImode */
850 in SImode, DImode and TImode */
852 in SImode, DImode and TImode */
857 /* New AMD processors never drop prefetches; if they cannot be performed
858 immediately, they are queued. We set number of simultaneous prefetches
859 to a large constant to reflect this (it probably is not a good idea not
860 to limit number of prefetches at all, as their execution also takes some
861 time). */
871 k8_memcpy,
872 k8_memset,
884 };
886 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
887 very small blocks it is better to use loop. For large blocks, libcall can
888 do nontemporary accesses and beat inline considerably. */
921 in QImode, HImode and SImode.
922 Relative to reg-reg move (2). */
926 in SFmode, DFmode and XFmode */
928 in SFmode, DFmode and XFmode */
931 in SImode and DImode */
933 in SImode and DImode */
936 in SImode, DImode and TImode */
938 in SImode, DImode and TImode */
940 /* On K8:
941 MOVD reg64, xmmreg Double FSTORE 4
942 MOVD reg32, xmmreg Double FSTORE 4
943 On AMDFAM10:
944 MOVD reg64, xmmreg Double FADD 3
945 1/1 1/1
946 MOVD reg32, xmmreg Double FADD 3
947 1/1 1/1 */
951 /* New AMD processors never drop prefetches; if they cannot be performed
952 immediately, they are queued. We set number of simultaneous prefetches
953 to a large constant to reflect this (it probably is not a good idea not
954 to limit number of prefetches at all, as their execution also takes some
955 time). */
965 amdfam10_memcpy,
966 amdfam10_memset,
978 };
980 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
981 very small blocks it is better to use loop. For large blocks, libcall
982 can do nontemporary accesses and beat inline considerably. */
1016 in QImode, HImode and SImode.
1017 Relative to reg-reg move (2). */
1021 in SFmode, DFmode and XFmode */
1023 in SFmode, DFmode and XFmode */
1026 in SImode and DImode */
1028 in SImode and DImode */
1031 in SImode, DImode and TImode */
1033 in SImode, DImode and TImode */
1035 /* On K8:
1036 MOVD reg64, xmmreg Double FSTORE 4
1037 MOVD reg32, xmmreg Double FSTORE 4
1038 On AMDFAM10:
1039 MOVD reg64, xmmreg Double FADD 3
1040 1/1 1/1
1041 MOVD reg32, xmmreg Double FADD 3
1042 1/1 1/1 */
1046 /* New AMD processors never drop prefetches; if they cannot be performed
1047 immediately, they are queued. We set number of simultaneous prefetches
1048 to a large constant to reflect this (it probably is not a good idea not
1049 to limit number of prefetches at all, as their execution also takes some
1050 time). */
1060 bdver1_memcpy,
1061 bdver1_memset,
1073 };
1075 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1076 very small blocks it is better to use loop. For large blocks, libcall
1077 can do nontemporary accesses and beat inline considerably. */
1112 in QImode, HImode and SImode.
1113 Relative to reg-reg move (2). */
1117 in SFmode, DFmode and XFmode */
1119 in SFmode, DFmode and XFmode */
1122 in SImode and DImode */
1124 in SImode and DImode */
1127 in SImode, DImode and TImode */
1129 in SImode, DImode and TImode */
1131 /* On K8:
1132 MOVD reg64, xmmreg Double FSTORE 4
1133 MOVD reg32, xmmreg Double FSTORE 4
1134 On AMDFAM10:
1135 MOVD reg64, xmmreg Double FADD 3
1136 1/1 1/1
1137 MOVD reg32, xmmreg Double FADD 3
1138 1/1 1/1 */
1142 /* New AMD processors never drop prefetches; if they cannot be performed
1143 immediately, they are queued. We set number of simultaneous prefetches
1144 to a large constant to reflect this (it probably is not a good idea not
1145 to limit number of prefetches at all, as their execution also takes some
1146 time). */
1156 bdver2_memcpy,
1157 bdver2_memset,
1169 };
1172 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1173 very small blocks it is better to use loop. For large blocks, libcall
1174 can do nontemporary accesses and beat inline considerably. */
1207 in QImode, HImode and SImode.
1208 Relative to reg-reg move (2). */
1212 in SFmode, DFmode and XFmode */
1214 in SFmode, DFmode and XFmode */
1217 in SImode and DImode */
1219 in SImode and DImode */
1222 in SImode, DImode and TImode */
1224 in SImode, DImode and TImode */
1229 /* New AMD processors never drop prefetches; if they cannot be performed
1230 immediately, they are queued. We set number of simultaneous prefetches
1231 to a large constant to reflect this (it probably is not a good idea not
1232 to limit number of prefetches at all, as their execution also takes some
1233 time). */
1243 bdver3_memcpy,
1244 bdver3_memset,
1256 };
1258 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1259 very small blocks it is better to use loop. For large blocks, libcall
1260 can do nontemporary accesses and beat inline considerably. */
1293 in QImode, HImode and SImode.
1294 Relative to reg-reg move (2). */
1298 in SFmode, DFmode and XFmode */
1300 in SFmode, DFmode and XFmode */
1303 in SImode and DImode */
1305 in SImode and DImode */
1308 in SImode, DImode and TImode */
1310 in SImode, DImode and TImode */
1315 /* New AMD processors never drop prefetches; if they cannot be performed
1316 immediately, they are queued. We set number of simultaneous prefetches
1317 to a large constant to reflect this (it probably is not a good idea not
1318 to limit number of prefetches at all, as their execution also takes some
1319 time). */
1329 bdver4_memcpy,
1330 bdver4_memset,
1342 };
1344 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1345 very small blocks it is better to use loop. For large blocks, libcall can
1346 do nontemporary accesses and beat inline considerably. */
1379 in QImode, HImode and SImode.
1380 Relative to reg-reg move (2). */
1384 in SFmode, DFmode and XFmode */
1386 in SFmode, DFmode and XFmode */
1389 in SImode and DImode */
1391 in SImode and DImode */
1394 in SImode, DImode and TImode */
1396 in SImode, DImode and TImode */
1398 /* On K8:
1399 MOVD reg64, xmmreg Double FSTORE 4
1400 MOVD reg32, xmmreg Double FSTORE 4
1401 On AMDFAM10:
1402 MOVD reg64, xmmreg Double FADD 3
1403 1/1 1/1
1404 MOVD reg32, xmmreg Double FADD 3
1405 1/1 1/1 */
1418 btver1_memcpy,
1419 btver1_memset,
1431 };
1465 in QImode, HImode and SImode.
1466 Relative to reg-reg move (2). */
1470 in SFmode, DFmode and XFmode */
1472 in SFmode, DFmode and XFmode */
1475 in SImode and DImode */
1477 in SImode and DImode */
1480 in SImode, DImode and TImode */
1482 in SImode, DImode and TImode */
1484 /* On K8:
1485 MOVD reg64, xmmreg Double FSTORE 4
1486 MOVD reg32, xmmreg Double FSTORE 4
1487 On AMDFAM10:
1488 MOVD reg64, xmmreg Double FADD 3
1489 1/1 1/1
1490 MOVD reg32, xmmreg Double FADD 3
1491 1/1 1/1 */
1503 btver2_memcpy,
1504 btver2_memset,
1516 };
1520 DUMMY_STRINGOP_ALGS};
1524 DUMMY_STRINGOP_ALGS};
1526 static const
1549 in QImode, HImode and SImode.
1550 Relative to reg-reg move (2). */
1554 in SFmode, DFmode and XFmode */
1556 in SFmode, DFmode and XFmode */
1559 in SImode and DImode */
1561 in SImode and DImode */
1564 in SImode, DImode and TImode */
1566 in SImode, DImode and TImode */
1579 pentium4_memcpy,
1580 pentium4_memset,
1592 };
1605 static const
1628 in QImode, HImode and SImode.
1629 Relative to reg-reg move (2). */
1633 in SFmode, DFmode and XFmode */
1635 in SFmode, DFmode and XFmode */
1638 in SImode and DImode */
1640 in SImode and DImode */
1643 in SImode, DImode and TImode */
1645 in SImode, DImode and TImode */
1658 nocona_memcpy,
1659 nocona_memset,
1671 };
1682 static const
1705 in QImode, HImode and SImode.
1706 Relative to reg-reg move (2). */
1710 in SFmode, DFmode and XFmode */
1712 in SFmode, DFmode and XFmode */
1715 in SImode and DImode */
1717 in SImode and DImode */
1720 in SImode, DImode and TImode */
1722 in SImode, DImode and TImode */
1735 atom_memcpy,
1736 atom_memset,
1748 };
1759 static const
1782 in QImode, HImode and SImode.
1783 Relative to reg-reg move (2). */
1787 in SFmode, DFmode and XFmode */
1789 in SFmode, DFmode and XFmode */
1792 in SImode and DImode */
1794 in SImode and DImode */
1797 in SImode, DImode and TImode */
1799 in SImode, DImode and TImode */
1812 slm_memcpy,
1813 slm_memset,
1825 };
1836 static const
1859 in QImode, HImode and SImode.
1860 Relative to reg-reg move (2). */
1864 in SFmode, DFmode and XFmode */
1866 in SFmode, DFmode and XFmode */
1869 in SImode and DImode */
1871 in SImode and DImode */
1874 in SImode, DImode and TImode */
1876 in SImode, DImode and TImode */
1889 intel_memcpy,
1890 intel_memset,
1902 };
1904 /* Generic should produce code tuned for Core-i7 (and newer chips)
1905 and btver1 (and newer chips). */
1917 static const
1920 /* On all chips taken into consideration lea is 2 cycles and more. With
1921 this cost however our current implementation of synth_mult results in
1922 use of unnecessary temporary registers causing regression on several
1923 SPECfp benchmarks. */
1944 in QImode, HImode and SImode.
1945 Relative to reg-reg move (2). */
1949 in SFmode, DFmode and XFmode */
1951 in SFmode, DFmode and XFmode */
1954 in SImode and DImode */
1956 in SImode and DImode */
1959 in SImode, DImode and TImode */
1961 in SImode, DImode and TImode */
1967 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1968 value is increased to perhaps more appropriate value of 5. */
1976 generic_memcpy,
1977 generic_memset,
1989 };
1991 /* core_cost should produce code tuned for Core familly of CPUs. */
2004 static const
2007 /* On all chips taken into consideration lea is 2 cycles and more. With
2008 this cost however our current implementation of synth_mult results in
2009 use of unnecessary temporary registers causing regression on several
2010 SPECfp benchmarks. */
2031 in QImode, HImode and SImode.
2032 Relative to reg-reg move (2). */
2036 in SFmode, DFmode and XFmode */
2038 in SFmode, DFmode and XFmode */
2041 in SImode and DImode */
2043 in SImode and DImode */
2046 in SImode, DImode and TImode */
2048 in SImode, DImode and TImode */
2054 /* FIXME perhaps more appropriate value is 5. */
2062 core_memcpy,
2063 core_memset,
2075 };
2078 /* Set by -mtune. */
2081 /* Set by -mtune or -Os. */
2084 /* Processor feature/optimization bitmasks. */
2085 #define m_386 (1<<PROCESSOR_I386)
2086 #define m_486 (1<<PROCESSOR_I486)
2087 #define m_PENT (1<<PROCESSOR_PENTIUM)
2088 #define m_IAMCU (1<<PROCESSOR_IAMCU)
2089 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2090 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2091 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2092 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2093 #define m_CORE2 (1<<PROCESSOR_CORE2)
2094 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2095 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2096 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2097 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2098 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2099 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2100 #define m_KNL (1<<PROCESSOR_KNL)
2101 #define m_INTEL (1<<PROCESSOR_INTEL)
2103 #define m_GEODE (1<<PROCESSOR_GEODE)
2104 #define m_K6 (1<<PROCESSOR_K6)
2105 #define m_K6_GEODE (m_K6 | m_GEODE)
2106 #define m_K8 (1<<PROCESSOR_K8)
2107 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2108 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2109 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2110 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2111 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2112 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2113 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2114 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2115 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2116 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2117 #define m_BTVER (m_BTVER1 | m_BTVER2)
2118 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2120 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2123 #undef DEF_TUNE
2124 #define DEF_TUNE(tune, name, selector) name,
2126 #undef DEF_TUNE
2127 };
2129 /* Feature tests against the various tunings. */
2132 /* Feature tests against the various tunings used to create ix86_tune_features
2133 based on the processor mask. */
2135 #undef DEF_TUNE
2136 #define DEF_TUNE(tune, name, selector) selector,
2138 #undef DEF_TUNE
2139 };
2141 /* Feature tests against the various architecture variations. */
2144 /* Feature tests against the various architecture variations, used to create
2145 ix86_arch_features based on the processor mask. */
2147 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2150 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2153 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2156 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2159 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2161 };
2163 /* In case the average insn count for single function invocation is
2164 lower than this constant, emit fast (but longer) prologue and
2165 epilogue code. */
2166 #define FAST_PROLOGUE_INSN_COUNT 20
2168 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2173 /* Array of the smallest class containing reg number REGNO, indexed by
2174 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2177 {
2178 /* ax, dx, cx, bx */
2180 /* si, di, bp, sp */
2182 /* FP registers */
2185 /* arg pointer */
2186 NON_Q_REGS,
2187 /* flags, fpsr, fpcr, frame */
2189 /* SSE registers */
2192 /* MMX registers */
2195 /* REX registers */
2198 /* SSE REX registers */
2201 /* AVX-512 SSE registers */
2206 /* Mask registers. */
2209 /* MPX bound registers */
2211 };
2213 /* The "default" register map used in 32bit mode. */
2216 {
2228 };
2230 /* The "default" register map used in 64bit mode. */
2233 {
2245 };
2247 /* Define the register numbers to be used in Dwarf debugging information.
2248 The SVR4 reference port C compiler uses the following register numbers
2249 in its Dwarf output code:
2250 0 for %eax (gcc regno = 0)
2251 1 for %ecx (gcc regno = 2)
2252 2 for %edx (gcc regno = 1)
2253 3 for %ebx (gcc regno = 3)
2254 4 for %esp (gcc regno = 7)
2255 5 for %ebp (gcc regno = 6)
2256 6 for %esi (gcc regno = 4)
2257 7 for %edi (gcc regno = 5)
2258 The following three DWARF register numbers are never generated by
2259 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2260 believes these numbers have these meanings.
2261 8 for %eip (no gcc equivalent)
2262 9 for %eflags (gcc regno = 17)
2263 10 for %trapno (no gcc equivalent)
2264 It is not at all clear how we should number the FP stack registers
2265 for the x86 architecture. If the version of SDB on x86/svr4 were
2266 a bit less brain dead with respect to floating-point then we would
2267 have a precedent to follow with respect to DWARF register numbers
2268 for x86 FP registers, but the SDB on x86/svr4 is so completely
2269 broken with respect to FP registers that it is hardly worth thinking
2270 of it as something to strive for compatibility with.
2271 The version of x86/svr4 SDB I have at the moment does (partially)
2272 seem to believe that DWARF register number 11 is associated with
2273 the x86 register %st(0), but that's about all. Higher DWARF
2274 register numbers don't seem to be associated with anything in
2275 particular, and even for DWARF regno 11, SDB only seems to under-
2276 stand that it should say that a variable lives in %st(0) (when
2277 asked via an `=' command) if we said it was in DWARF regno 11,
2278 but SDB still prints garbage when asked for the value of the
2279 variable in question (via a `/' command).
2280 (Also note that the labels SDB prints for various FP stack regs
2281 when doing an `x' command are all wrong.)
2282 Note that these problems generally don't affect the native SVR4
2283 C compiler because it doesn't allow the use of -O with -g and
2284 because when it is *not* optimizing, it allocates a memory
2285 location for each floating-point variable, and the memory
2286 location is what gets described in the DWARF AT_location
2287 attribute for the variable in question.
2288 Regardless of the severe mental illness of the x86/svr4 SDB, we
2289 do something sensible here and we use the following DWARF
2290 register numbers. Note that these are all stack-top-relative
2291 numbers.
2292 11 for %st(0) (gcc regno = 8)
2293 12 for %st(1) (gcc regno = 9)
2294 13 for %st(2) (gcc regno = 10)
2295 14 for %st(3) (gcc regno = 11)
2296 15 for %st(4) (gcc regno = 12)
2297 16 for %st(5) (gcc regno = 13)
2298 17 for %st(6) (gcc regno = 14)
2299 18 for %st(7) (gcc regno = 15)
2300 */
2302 {
2314 };
2316 /* Define parameter passing and return registers. */
2319 {
2321 };
2324 {
2326 };
2329 {
2331 };
2333 /* Additional registers that are clobbered by SYSV calls. */
2336 {
2341 };
2343 /* Define the structure for the machine field in struct function. */
2348 rtx rtl;
2350 };
2352 /* Structure describing stack frame layout.
2353 Stack grows downward:
2355 [arguments]
2356 <- ARG_POINTER
2357 saved pc
2359 saved static chain if ix86_static_chain_on_stack
2361 saved frame pointer if frame_pointer_needed
2362 <- HARD_FRAME_POINTER
2363 [saved regs]
2364 <- regs_save_offset
2365 [padding0]
2367 [saved SSE regs]
2368 <- sse_regs_save_offset
2369 [padding1] |
2370 | <- FRAME_POINTER
2371 [va_arg registers] |
2372 |
2373 [frame] |
2374 |
2375 [padding2] | = to_allocate
2376 <- STACK_POINTER
2377 */
2378 struct ix86_frame
2379 {
2386 /* The offsets relative to ARG_POINTER. */
2387 HOST_WIDE_INT frame_pointer_offset;
2388 HOST_WIDE_INT hard_frame_pointer_offset;
2389 HOST_WIDE_INT stack_pointer_offset;
2390 HOST_WIDE_INT hfp_save_offset;
2391 HOST_WIDE_INT reg_save_offset;
2392 HOST_WIDE_INT sse_reg_save_offset;
2394 /* When save_regs_using_mov is set, emit prologue using
2395 move instead of push instructions. */
2397 };
2399 /* Which cpu are we scheduling for. */
2402 /* Which cpu are we optimizing for. */
2405 /* Which instruction set architecture to use. */
2408 /* True if processor has SSE prefetch instruction. */
2411 /* -mstackrealign option */
2429 /* Preferred alignment for stack boundary in bits. */
2432 /* Alignment for incoming stack boundary in bits specified at
2433 command line. */
2436 /* Default alignment for incoming stack boundary in bits. */
2439 /* Alignment for incoming stack boundary in bits. */
2442 /* Calling abi specific va_list type nodes. */
2446 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2450 /* Fence to use after loop using movnt. */
2451 tree x86_mfence;
2453 /* Register class used for passing given 64bit part of the argument.
2454 These represent classes as documented by the PS ABI, with the exception
2455 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2456 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2458 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2459 whenever possible (upper half does contain padding). */
2460 enum x86_64_reg_class
2461 {
2462 X86_64_NO_CLASS,
2463 X86_64_INTEGER_CLASS,
2464 X86_64_INTEGERSI_CLASS,
2465 X86_64_SSE_CLASS,
2466 X86_64_SSESF_CLASS,
2467 X86_64_SSEDF_CLASS,
2468 X86_64_SSEUP_CLASS,
2469 X86_64_X87_CLASS,
2470 X86_64_X87UP_CLASS,
2471 X86_64_COMPLEX_X87_CLASS,
2472 X86_64_MEMORY_CLASS
2473 };
2475 #define MAX_CLASSES 8
2477 /* Table of constants used by fldpi, fldln2, etc.... */
2481 \f
2486 const_tree);
2498 enum ix86_function_specific_strings
2499 {
2500 IX86_FUNCTION_SPECIFIC_ARCH,
2501 IX86_FUNCTION_SPECIFIC_TUNE,
2502 IX86_FUNCTION_SPECIFIC_MAX
2503 };
2525 \f
2526 #ifndef SUBTARGET32_DEFAULT_CPU
2528 #endif
2530 /* Whether -mtune= or -march= were specified */
2534 /* Vectorization library interface and handlers. */
2540 /* Processor target table, indexed by processor number */
2541 struct ptt
2542 {
2550 };
2552 /* This table must be in sync with enum processor_type in i386.h. */
2554 {
2582 };
2583 \f
2584 static unsigned int
2586 {
2589 /* vzeroupper instructions are inserted immediately after reload to
2590 account for possible spills from 256bit registers. The pass
2591 reuses mode switching infrastructure by re-running mode insertion
2592 pass, so disable entities that have already been processed. */
2598 /* Call optimize_mode_switching. */
2601 }
2606 {
2616 };
2619 {
2623 {}
2625 /* opt_pass methods: */
2627 {
2631 }
2634 {
2636 }
2642 rtl_opt_pass *
2644 {
2646 }
2648 /* Return true if a red-zone is in use. */
2652 {
2654 }
2655 \f
2656 /* Return a string that documents the current -m options. The caller is
2657 responsible for freeing the string. */
2663 {
2664 struct ix86_target_opts
2665 {
2668 };
2670 /* This table is ordered so that options like -msse4.2 that imply
2671 preceding options while match those first. */
2673 {
2727 };
2729 /* Flag options. */
2731 {
2760 };
2777 /* Add -march= option. */
2779 {
2782 }
2784 /* Add -mtune= option. */
2786 {
2789 }
2791 /* Add -m32/-m64/-mx32. */
2793 {
2796 else
2798 isa &= ~ (OPTION_MASK_ISA_64BIT
2799 | OPTION_MASK_ABI_64
2801 }
2802 else
2806 /* Pick out the options in isa options. */
2808 {
2810 {
2813 }
2814 }
2817 {
2820 isa);
2821 }
2823 /* Add flag options. */
2825 {
2827 {
2830 }
2831 }
2834 {
2837 }
2839 /* Add -fpmath= option. */
2841 {
2844 {
2859 }
2860 }
2862 /* Any options? */
2868 /* Size the string. */
2872 {
2877 }
2879 /* Build the string. */
2884 {
2891 {
2893 line_len++;
2896 {
2900 }
2901 }
2905 {
2909 }
2910 }
2916 }
2918 /* Return true, if profiling code should be emitted before
2919 prologue. Otherwise it returns false.
2920 Note: For x86 with "hotfix" it is sorried. */
2921 static bool
2923 {
2925 }
2927 /* Function that is callable from the debugger to print the current
2928 options. */
2929 void ATTRIBUTE_UNUSED
2931 {
2937 {
2940 }
2941 else
2945 }
2948 #define DEF_ENUM
2949 #define DEF_ALG(alg, name) #name,
2951 #undef DEF_ENUM
2952 #undef DEF_ALG
2953 };
2955 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2956 The string is of the following form (or comma separated list of it):
2958 strategy_alg:max_size:[align|noalign]
2960 where the full size range for the strategy is either [0, max_size] or
2961 [min_size, max_size], in which min_size is the max_size + 1 of the
2962 preceding range. The last size range must have max_size == -1.
2964 Examples:
2966 1.
2967 -mmemcpy-strategy=libcall:-1:noalign
2969 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2972 2.
2973 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2975 This is to tell the compiler to use the following strategy for memset
2976 1) when the expected size is between [1, 16], use rep_8byte strategy;
2977 2) when the size is between [17, 2048], use vector_loop;
2978 3) when the size is > 2048, use libcall. */
2980 struct stringop_size_range
2981 {
2983 stringop_alg alg;
2985 };
2987 static void
2989 {
2997 else
3002 do
3003 {
3013 {
3017 }
3020 {
3024 }
3031 {
3033 alg_name,
3036 }
3040 {
3041 /* rep; movq isn't available in 32-bit code. */
3044 alg_name,
3047 }
3055 else
3056 {
3060 }
3061 n++;
3063 }
3067 {
3072 }
3075 {
3079 }
3081 /* Now override the default algs array. */
3083 {
3089 }
3090 }
3092 \f
3093 /* parse -mtune-ctrl= option. When DUMP is true,
3094 print the features that are explicitly set. */
3096 static void
3098 {
3106 do
3107 {
3114 {
3115 curr_feature_string++;
3117 }
3119 {
3121 {
3127 }
3128 }
3133 }
3136 }
3138 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3139 processor type. */
3141 static void
3143 {
3148 {
3151 else
3153 }
3156 {
3161 }
3164 }
3167 /* Default align_* from the processor table. */
3169 static void
3171 {
3173 {
3176 }
3178 {
3181 }
3183 {
3185 }
3186 }
3188 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook. */
3190 static void
3192 {
3194 }
3196 /* Override various settings based on options. If MAIN_ARGS_P, the
3197 options are from the command line, otherwise they are from
3198 attributes. */
3200 static void
3204 {
3212 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3213 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3214 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3215 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3216 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3217 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3218 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3219 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3220 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3221 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3222 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3223 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3224 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3225 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3226 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3227 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3228 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3229 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3230 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3231 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3232 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3233 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3234 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3235 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3236 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3237 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3238 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3239 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3240 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3241 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3242 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3243 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3244 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3245 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3246 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3247 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3248 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3249 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3250 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3251 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3252 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3253 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3254 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3255 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3256 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3257 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3258 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3259 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3260 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3261 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3262 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3263 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3264 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3265 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3266 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3267 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3268 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3269 #define PTA_MWAITX (HOST_WIDE_INT_1 << 57)
3271 #define PTA_CORE2 \
3272 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3273 | PTA_CX16 | PTA_FXSR)
3274 #define PTA_NEHALEM \
3275 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3276 #define PTA_WESTMERE \
3277 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3278 #define PTA_SANDYBRIDGE \
3279 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3280 #define PTA_IVYBRIDGE \
3281 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3282 #define PTA_HASWELL \
3283 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3284 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3285 #define PTA_BROADWELL \
3286 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3287 #define PTA_SKYLAKE \
3288 (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES)
3289 #define PTA_KNL \
3290 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3291 #define PTA_BONNELL \
3292 (PTA_CORE2 | PTA_MOVBE)
3293 #define PTA_SILVERMONT \
3294 (PTA_WESTMERE | PTA_MOVBE)
3296 /* if this reaches 64, need to widen struct pta flags below */
3298 static struct pta
3299 {
3304 }
3306 {
3341 PTA_SANDYBRIDGE},
3343 PTA_SANDYBRIDGE},
3345 PTA_IVYBRIDGE},
3347 PTA_IVYBRIDGE},
3440 PTA_64BIT
3442 };
3444 /* -mrecip options. */
3445 static struct
3446 {
3449 }
3451 {
3458 };
3462 /* Set up prefix/suffix so the error messages refer to either the command
3463 line argument, or the attribute(target). */
3465 {
3469 }
3470 else
3471 {
3475 }
3477 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3478 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3481 #ifdef TARGET_BI_ARCH
3482 else
3483 {
3484 #if TARGET_BI_ARCH == 1
3485 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3486 is on and OPTION_MASK_ABI_X32 is off. We turn off
3487 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3488 -mx32. */
3491 #else
3492 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3493 on and OPTION_MASK_ABI_64 is off. We turn off
3494 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3495 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3499 #endif
3504 }
3505 #endif
3508 {
3509 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3510 OPTION_MASK_ABI_64 for TARGET_X32. */
3513 }
3516 | OPTION_MASK_ABI_X32
3519 {
3520 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3521 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3524 }
3526 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3527 SUBTARGET_OVERRIDE_OPTIONS;
3528 #endif
3530 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3531 SUBSUBTARGET_OVERRIDE_OPTIONS;
3532 #endif
3534 /* -fPIC is the default for x86_64. */
3538 /* Need to check -mtune=generic first. */
3540 {
3541 /* As special support for cross compilers we read -mtune=native
3542 as -mtune=generic. With native compilers we won't see the
3543 -mtune=native, as it was changed by the driver. */
3545 {
3547 }
3552 }
3553 else
3554 {
3558 {
3559 opts->x_ix86_tune_string
3562 }
3564 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3565 or defaulted. We need to use a sensible tune option. */
3567 {
3569 }
3570 }
3574 {
3575 /* rep; movq isn't available in 32-bit code. */
3578 }
3581 opts->x_ix86_arch_string
3584 else
3588 {
3596 }
3597 else
3604 /* For targets using ms ABI enable ms-extensions, if not
3605 explicit turned off. For non-ms ABI we turn off this
3606 option. */
3611 {
3613 {
3657 {
3660 }
3668 }
3669 }
3670 else
3671 {
3672 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3673 use of rip-relative addressing. This eliminates fixups that
3674 would otherwise be needed if this object is to be placed in a
3675 DLL, and is essentially just as efficient as direct addressing. */
3681 else
3683 }
3685 {
3688 }
3696 {
3699 /* Default cpu tuning to the architecture. */
3880 }
3889 {
3890 /* Verify that x87/MMX/SSE/AVX is off for -miamcu. */
3894 | OPTION_MASK_ISA_SSE
3900 }
3918 {
3922 {
3924 {
3926 {
3934 }
3935 else
3938 }
3939 }
3940 /* Intel CPUs have always interpreted SSE prefetch instructions as
3941 NOPs; so, we can enable SSE prefetch instructions even when
3942 -mtune (rather than -march) points us to a processor that has them.
3943 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3944 higher processors. */
3949 }
3957 #ifndef USE_IX86_FRAME_POINTER
3958 #define USE_IX86_FRAME_POINTER 0
3959 #endif
3961 #ifndef USE_X86_64_FRAME_POINTER
3962 #define USE_X86_64_FRAME_POINTER 0
3963 #endif
3965 /* Set the default values for switches whose default depends on TARGET_64BIT
3966 in case they weren't overwritten by command line options. */
3968 {
3976 opts->x_flag_unwind_tables
3980 }
3981 else
3982 {
3984 opts->x_flag_omit_frame_pointer
3989 {
3990 /* Intel MCU psABI specifies that -freg-struct-return should
3991 be on. Instead of setting DEFAULT_PCC_STRUCT_RETURN to 1,
3992 we check -miamcu so that -freg-struct-return is always
3993 turned on if -miamcu is used. */
3996 else
3998 }
3999 }
4002 /* TODO: ix86_cost should be chosen at instruction or function granuality
4003 so for cold code we use size_cost even in !optimize_size compilation. */
4006 else
4009 /* Arrange to set up i386_stack_locals for all functions. */
4012 /* Validate -mregparm= value. */
4014 {
4020 {
4024 }
4025 }
4030 /* Default align_* from the processor table. */
4033 /* Provide default for -mbranch-cost= value. */
4038 {
4039 opts->x_target_flags
4042 /* Enable by default the SSE and MMX builtins. Do allow the user to
4043 explicitly disable any of these. In particular, disabling SSE and
4044 MMX for kernel code is extremely useful. */
4046 opts->x_ix86_isa_flags
4053 }
4054 else
4055 {
4056 opts->x_target_flags
4060 opts->x_ix86_isa_flags
4063 /* i386 ABI does not specify red zone. It still makes sense to use it
4064 when programmer takes care to stack from being destroyed. */
4067 }
4069 /* Keep nonleaf frame pointers. */
4075 /* If we're doing fast math, we don't care about comparison order
4076 wrt NaNs. This lets us use a shorter comparison sequence. */
4080 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
4081 since the insns won't need emulation. */
4085 /* Likewise, if the target doesn't have a 387, or we've specified
4086 software floating point, don't use 387 inline intrinsics. */
4090 /* Turn on MMX builtins for -msse. */
4092 opts->x_ix86_isa_flags
4095 /* Enable SSE prefetch. */
4100 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
4103 opts->x_ix86_isa_flags
4106 /* Enable popcnt instruction for -msse4.2 or -mabm. */
4109 opts->x_ix86_isa_flags
4112 /* Enable lzcnt instruction for -mabm. */
4114 opts->x_ix86_isa_flags
4117 /* Validate -mpreferred-stack-boundary= value or default it to
4118 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4121 {
4128 {
4132 else
4135 }
4136 else
4137 ix86_preferred_stack_boundary
4139 }
4141 /* Set the default value for -mstackrealign. */
4147 /* Validate -mincoming-stack-boundary= value or default it to
4148 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4151 {
4159 else
4160 {
4161 ix86_user_incoming_stack_boundary
4163 ix86_incoming_stack_boundary
4165 }
4166 }
4168 #ifndef NO_PROFILE_COUNTERS
4171 #endif
4175 /* Accept -msseregparm only if at least SSE support is enabled. */
4181 {
4183 {
4185 {
4188 }
4191 {
4194 }
4195 }
4196 }
4197 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4198 fpmath=387. The second is however default at many targets since the
4199 extra 80bit precision of temporaries is considered to be part of ABI.
4200 Overwrite the default at least for -ffast-math.
4201 TODO: -mfpmath=both seems to produce same performing code with bit
4202 smaller binaries. It is however not clear if register allocation is
4203 ready for this setting.
4204 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4205 codegen. We may switch to 387 with -ffast-math for size optimized
4206 functions. */
4210 else
4213 /* If the i387 is disabled, then do not return values in it. */
4217 /* Use external vectorized library in vectorizing intrinsics. */
4220 {
4231 }
4237 /* If stack probes are required, the space used for large function
4238 arguments on the stack must also be probed, so enable
4239 -maccumulate-outgoing-args so this happens in the prologue. */
4242 {
4247 }
4249 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4250 {
4256 }
4258 /* When scheduling description is not available, disable scheduler pass
4259 so it won't slow down the compilation and make x87 code slower. */
4280 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4282 && HAVE_prefetch
4288 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4289 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4294 {
4297 {
4299 ix86_gen_tls_local_dynamic_base_64
4301 }
4302 else
4303 {
4305 ix86_gen_tls_local_dynamic_base_64
4307 }
4308 }
4309 else
4313 {
4324 }
4325 else
4326 {
4337 }
4339 #ifdef USE_IX86_CLD
4340 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4343 #endif
4346 {
4351 }
4353 {
4357 }
4359 {
4360 #if defined(PROFILE_BEFORE_PROLOGUE)
4362 #else
4364 #endif
4365 }
4375 /* Enable 128-bit AVX instruction generation
4376 for the auto-vectorizer. */
4382 {
4389 {
4392 {
4394 q++;
4395 }
4396 else
4401 else
4402 {
4405 {
4408 }
4411 {
4415 }
4416 }
4421 else
4423 }
4424 }
4431 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4432 for 64-bit Bionic. Also default long double to 64-bit for Intel
4433 MCU psABI. */
4438 ? MASK_LONG_DOUBLE_128
4441 /* Only one of them can be active. */
4445 /* Save the initial options in case the user does function specific
4446 options. */
4448 target_option_default_node = target_option_current_node
4451 /* Handle stack protector */
4453 opts->x_ix86_stack_protector_guard
4456 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4458 {
4462 }
4465 {
4469 }
4470 }
4472 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4474 static void
4476 {
4478 struct register_pass_info insert_vzeroupper_info
4481 };
4486 /* This needs to be done at start up. It's convenient to do it here. */
4488 }
4490 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4493 {
4497 }
4499 /* Update register usage after having seen the compiler flags. */
4501 static void
4503 {
4506 /* For 32-bit targets, squash the REX registers. */
4508 {
4515 }
4517 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4525 {
4526 /* Set/reset conditionally defined registers from
4527 CALL_USED_REGISTERS initializer. */
4531 /* Calculate registers of CLOBBERED_REGS register set
4532 as call used registers from GENERAL_REGS register set. */
4536 }
4538 /* If MMX is disabled, squash the registers. */
4544 /* If SSE is disabled, squash the registers. */
4550 /* If the FPU is disabled, squash the registers. */
4556 /* If AVX512F is disabled, squash the registers. */
4558 {
4564 }
4566 /* If MPX is disabled, squash the registers. */
4570 }
4572 \f
4573 /* Save the current options */
4575 static void
4578 {
4614 /* The fields are char but the variables are not; make sure the
4615 values fit in the fields. */
4620 }
4622 /* Restore the current options */
4624 static void
4627 {
4633 /* We don't change -fPIC. */
4671 /* TODO: ix86_cost should be chosen at instruction or function granuality
4672 so for cold code we use size_cost even in !optimize_size compilation. */
4675 else
4678 /* Recreate the arch feature tests if the arch changed */
4680 {
4685 }
4687 /* Recreate the tune optimization tests */
4690 }
4692 /* Adjust target options after streaming them in. This is mainly about
4693 reconciling them with global options. */
4695 static void
4697 {
4698 /* flag_pic is a global option, but ix86_cmodel is target saved option
4699 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4700 for PIC, or error out. */
4703 {
4722 }
4723 else
4725 {
4740 }
4741 }
4743 /* Print the current options */
4745 static void
4748 {
4766 {
4769 }
4770 }
4772 \f
4773 /* Inner function to process the attribute((target(...))), take an argument and
4774 set the current options from the argument. If we have a list, recursively go
4775 over the list. */
4777 static bool
4782 {
4786 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4787 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4788 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4789 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4790 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4792 enum ix86_opt_type
4793 {
4794 ix86_opt_unknown,
4795 ix86_opt_yes,
4796 ix86_opt_no,
4797 ix86_opt_str,
4798 ix86_opt_enum,
4799 ix86_opt_isa
4800 };
4802 static const struct
4803 {
4810 /* isa options */
4864 /* enum options */
4867 /* string options */
4871 /* flag options */
4873 OPT_mcld,
4874 MASK_CLD),
4877 OPT_mfancy_math_387,
4878 MASK_NO_FANCY_MATH_387),
4881 OPT_mieee_fp,
4882 MASK_IEEE_FP),
4885 OPT_minline_all_stringops,
4886 MASK_INLINE_ALL_STRINGOPS),
4889 OPT_minline_stringops_dynamically,
4890 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4893 OPT_mno_align_stringops,
4894 MASK_NO_ALIGN_STRINGOPS),
4897 OPT_mrecip,
4898 MASK_RECIP),
4900 };
4902 /* If this is a list, recurse to get the options. */
4904 {
4911 enum_opts_set))
4915 }
4918 {
4921 }
4923 /* Handle multiple arguments separated by commas. */
4927 {
4941 {
4945 }
4946 else
4947 {
4950 }
4952 /* Recognize no-xxx. */
4954 {
4958 }
4959 else
4962 /* Find the option. */
4966 {
4974 {
4979 }
4980 }
4982 /* Process the option. */
4984 {
4987 }
4990 {
4996 }
4999 {
5005 else
5007 }
5010 {
5012 {
5015 }
5016 else
5018 }
5021 {
5029 global_dc);
5030 else
5031 {
5034 }
5035 }
5037 else
5039 }
5042 }
5044 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
5046 tree
5050 {
5065 /* Process each of the options on the chain. */
5070 /* If the changed options are different from the default, rerun
5071 ix86_option_override_internal, and then save the options away.
5072 The string options are attribute options, and will be undone
5073 when we copy the save structure. */
5079 {
5080 /* If we are using the default tune= or arch=, undo the string assigned,
5081 and use the default. */
5092 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
5097 {
5100 }
5102 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
5105 /* Add any builtin functions with the new isa if any. */
5108 /* Save the current options unless we are validating options for
5109 #pragma. */
5116 /* Free up memory allocated to hold the strings */
5119 }
5122 }
5124 /* Hook to validate attribute((target("string"))). */
5126 static bool
5129 tree args,
5131 {
5136 /* attribute((target("default"))) does nothing, beyond
5137 affecting multi-versioning. */
5146 /* Get the optimization options of the current function. */
5152 /* Init func_options. */
5160 /* Initialize func_options to the default before its target options can
5161 be set. */
5174 {
5179 }
5182 }
5184 \f
5185 /* Hook to determine if one function can safely inline another. */
5187 static bool
5189 {
5194 /* If callee has no option attributes, then it is ok to inline. */
5198 /* If caller has no option attributes, but callee does then it is not ok to
5199 inline. */
5203 else
5204 {
5208 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5209 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5210 function. */
5215 /* See if we have the same non-isa options. */
5219 /* See if arch, tune, etc. are the same. */
5232 else
5234 }
5237 }
5239 \f
5240 /* Remember the last target of ix86_set_current_function. */
5243 /* Set targets globals to the default (or current #pragma GCC target
5244 if active). Invalidate ix86_previous_fndecl cache. */
5246 void
5248 {
5255 else
5258 }
5260 /* Establish appropriate back-end context for processing the function
5261 FNDECL. The argument might be NULL to indicate processing at top
5262 level, outside of any function scope. */
5263 static void
5265 {
5266 /* Only change the context if the function changes. This hook is called
5267 several times in the course of compiling a function, and we don't want to
5268 slow things down too much or call target_reinit when it isn't safe. */
5272 tree old_tree;
5277 else
5281 {
5285 }
5292 {
5298 else
5300 }
5302 }
5304 \f
5305 /* Return true if this goes in large data/bss. */
5307 static bool
5309 {
5313 /* Functions are never large data. */
5317 /* Automatic variables are never large data. */
5322 {
5328 }
5329 else
5330 {
5333 /* If this is an incomplete type with size 0, then we can't put it
5334 in data because it might be too big when completed. Also,
5335 int_size_in_bytes returns -1 if size can vary or is larger than
5336 an integer in which case also it is safer to assume that it goes in
5337 large data. */
5340 }
5343 }
5345 /* Switch to the appropriate section for output of DECL.
5346 DECL is either a `VAR_DECL' node or a constant of some sort.
5347 RELOC indicates whether forming the initial value of DECL requires
5348 link-time relocations. */
5353 {
5355 {
5359 {
5393 /* We don't split these for medium model. Place them into
5394 default sections and hope for best. */
5396 }
5398 {
5399 /* We might get called with string constants, but get_named_section
5400 doesn't like them as they are not DECLs. Also, we need to set
5401 flags in that case. */
5405 }
5406 }
5408 }
5410 /* Select a set of attributes for section NAME based on the properties
5411 of DECL and whether or not RELOC indicates that DECL's initializer
5412 might contain runtime relocations. */
5414 static unsigned int ATTRIBUTE_UNUSED
5416 {
5430 }
5432 /* Build up a unique section name, expressed as a
5433 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5434 RELOC indicates whether the initial value of EXP requires
5435 link-time relocations. */
5437 static void ATTRIBUTE_UNUSED
5439 {
5441 {
5443 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5447 {
5471 /* We don't split these for medium model. Place them into
5472 default sections and hope for best. */
5474 }
5476 {
5483 /* If we're using one_only, then there needs to be a .gnu.linkonce
5484 prefix to the section name. */
5491 }
5492 }
5494 }
5496 #ifdef COMMON_ASM_OP
5497 /* This says how to output assembler code to declare an
5498 uninitialized external linkage data object.
5500 For medium model x86-64 we need to use .largecomm opcode for
5501 large objects. */
5502 void
5506 {
5510 else
5515 }
5516 #endif
5518 /* Utility function for targets to use in implementing
5519 ASM_OUTPUT_ALIGNED_BSS. */
5521 void
5524 {
5528 else
5531 #ifdef ASM_DECLARE_OBJECT_NAME
5534 #else
5535 /* Standard thing is just output label for the object. */
5539 }
5540 \f
5541 /* Decide whether we must probe the stack before any space allocation
5542 on this target. It's essentially TARGET_STACK_PROBE except when
5543 -fstack-check causes the stack to be already probed differently. */
5545 bool
5547 {
5548 /* Do not probe the stack twice if static stack checking is enabled. */
5553 }
5554 \f
5555 /* Decide whether we can make a sibling call to a function. DECL is the
5556 declaration of the function being targeted by the call and EXP is the
5557 CALL_EXPR representing the call. */
5559 static bool
5561 {
5565 /* If we are generating position-independent code, we cannot sibcall
5566 optimize direct calls to global functions, as the PLT requires
5567 %ebx be live. (Darwin does not have a PLT.) */
5569 && !TARGET_64BIT
5570 && flag_pic
5571 && flag_plt
5575 /* If we need to align the outgoing stack, then sibcalling would
5576 unalign the stack, which may break the called function. */
5582 {
5585 }
5586 else
5587 {
5588 /* We're looking at the CALL_EXPR, we need the type of the function. */
5593 }
5595 /* Check that the return value locations are the same. Like
5596 if we are returning floats on the 80387 register stack, we cannot
5597 make a sibcall from a function that doesn't return a float to a
5598 function that does or, conversely, from a function that does return
5599 a float to a function that doesn't; the necessary stack adjustment
5600 would not be executed. This is also the place we notice
5601 differences in the return value ABI. Note that it is ok for one
5602 of the functions to have void return type as long as the return
5603 value of the other is passed in a register. */
5608 {
5611 }
5613 ;
5618 {
5619 /* The SYSV ABI has more call-clobbered registers;
5620 disallow sibcalls from MS to SYSV. */
5624 }
5625 else
5626 {
5627 /* If this call is indirect, we'll need to be able to use a
5628 call-clobbered register for the address of the target function.
5629 Make sure that all such registers are not used for passing
5630 parameters. Note that DLLIMPORT functions are indirect. */
5633 {
5634 /* Check if regparm >= 3 since arg_reg_available is set to
5635 false if regparm == 0. If regparm is 1 or 2, there is
5636 always a call-clobbered register available.
5638 ??? The symbol indirect call doesn't need a call-clobbered
5639 register. But we don't know if this is a symbol indirect
5640 call or not here. */
5644 }
5645 }
5647 /* Otherwise okay. That also includes certain types of indirect calls. */
5649 }
5651 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5652 and "sseregparm" calling convention attributes;
5653 arguments as in struct attribute_spec.handler. */
5655 static tree
5657 tree args,
5660 {
5665 {
5667 name);
5670 }
5672 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5674 {
5675 tree cst;
5678 {
5680 }
5683 {
5685 }
5689 {
5692 name);
5694 }
5696 {
5700 }
5703 }
5706 {
5707 /* Do not warn when emulating the MS ABI. */
5712 name);
5715 }
5717 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5719 {
5721 {
5723 }
5725 {
5727 }
5729 {
5731 }
5733 {
5735 }
5736 }
5738 /* Can combine stdcall with fastcall (redundant), regparm and
5739 sseregparm. */
5741 {
5743 {
5745 }
5747 {
5749 }
5751 {
5753 }
5754 }
5756 /* Can combine cdecl with regparm and sseregparm. */
5758 {
5760 {
5762 }
5764 {
5766 }
5768 {
5770 }
5771 }
5773 {
5776 name);
5778 {
5780 }
5782 {
5784 }
5786 {
5788 }
5789 }
5791 /* Can combine sseregparm with all attributes. */
5794 }
5796 /* The transactional memory builtins are implicitly regparm or fastcall
5797 depending on the ABI. Override the generic do-nothing attribute that
5798 these builtins were declared with, and replace it with one of the two
5799 attributes that we expect elsewhere. */
5801 static tree
5804 {
5805 tree alt;
5807 /* In no case do we want to add the placeholder attribute. */
5810 /* The 64-bit ABI is unchanged for transactional memory. */
5814 /* ??? Is there a better way to validate 32-bit windows? We have
5815 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5818 else
5819 {
5822 }
5826 }
5828 /* This function determines from TYPE the calling-convention. */
5830 unsigned int
5832 {
5835 tree attrs;
5842 {
5852 /* Regparam isn't allowed for thiscall and fastcall. */
5854 {
5859 }
5863 }
5870 || is_stdarg
5876 }
5878 /* Return 0 if the attributes for two types are incompatible, 1 if they
5879 are compatible, and 2 if they are nearly compatible (which causes a
5880 warning to be generated). */
5882 static int
5884 {
5900 }
5901 \f
5902 /* Return the regparm value for a function with the indicated TYPE and DECL.
5903 DECL may be NULL when calling function indirectly
5904 or considering a libcall. */
5906 static int
5908 {
5909 tree attr;
5920 {
5923 {
5926 }
5927 }
5933 /* Use register calling convention for local functions when possible. */
5936 {
5941 /* Caller and callee must agree on the calling convention, so
5942 checking here just optimize means that with
5943 __attribute__((optimize (...))) caller could use regparm convention
5944 and callee not, or vice versa. Instead look at whether the callee
5945 is optimized or not. */
5948 {
5951 {
5954 /* Make sure no regparm register is taken by a
5955 fixed register variable. */
5957 local_regparm++)
5961 /* We don't want to use regparm(3) for nested functions as
5962 these use a static chain pointer in the third argument. */
5966 /* Save a register for the split stack. */
5970 /* Each fixed register usage increases register pressure,
5971 so less registers should be used for argument passing.
5972 This functionality can be overriden by an explicit
5973 regparm value. */
5976 globals++;
5978 local_regparm
5983 }
5984 }
5985 }
5988 }
5990 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5991 DFmode (2) arguments in SSE registers for a function with the
5992 indicated TYPE and DECL. DECL may be NULL when calling function
5993 indirectly or considering a libcall. Return -1 if any FP parameter
5994 should be rejected by error. This is used in siutation we imply SSE
5995 calling convetion but the function is called from another function with
5996 SSE disabled. Otherwise return 0. */
5998 static int
6000 {
6003 /* Use SSE registers to pass SFmode and DFmode arguments if requested
6004 by the sseregparm attribute. */
6007 {
6009 {
6011 {
6015 else
6018 }
6020 }
6023 }
6032 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
6033 (and DFmode for SSE2) arguments in SSE registers. */
6035 /* TARGET_SSE_MATH */
6039 {
6042 {
6043 /* Refuse to produce wrong code when local function with SSE enabled
6044 is called from SSE disabled function.
6045 FIXME: We need a way to detect these cases cross-ltrans partition
6046 and avoid using SSE calling conventions on local functions called
6047 from function with SSE disabled. For now at least delay the
6048 warning until we know we are going to produce wrong code.
6049 See PR66047 */
6054 }
6055 }
6058 }
6060 /* Return true if EAX is live at the start of the function. Used by
6061 ix86_expand_prologue to determine if we need special help before
6062 calling allocate_stack_worker. */
6064 static bool
6066 {
6067 /* Cheat. Don't bother working forward from ix86_function_regparm
6068 to the function type to whether an actual argument is located in
6069 eax. Instead just look at cfg info, which is still close enough
6070 to correct at this point. This gives false positives for broken
6071 functions that might use uninitialized data that happens to be
6072 allocated in eax, but who cares? */
6074 }
6076 static bool
6078 {
6079 tree attr;
6082 {
6088 /* For 32-bit MS-ABI the default is to keep aggregate
6089 return pointer. */
6092 }
6094 }
6096 /* Value is the number of bytes of arguments automatically
6097 popped when returning from a subroutine call.
6098 FUNDECL is the declaration node of the function (as a tree),
6099 FUNTYPE is the data type of the function (as a tree),
6100 or for a library call it is an identifier node for the subroutine name.
6101 SIZE is the number of bytes of arguments passed on the stack.
6103 On the 80386, the RTD insn may be used to pop them if the number
6104 of args is fixed, but if the number is variable then the caller
6105 must pop them all. RTD can't be used for library calls now
6106 because the library is compiled with the Unix compiler.
6107 Use of RTD is a selectable option, since it is incompatible with
6108 standard Unix calling sequences. If the option is not selected,
6109 the caller must always pop the args.
6111 The attribute stdcall is equivalent to RTD on a per module basis. */
6113 static int
6115 {
6118 /* None of the 64-bit ABIs pop arguments. */
6129 /* Lose any fake structure return argument if it is passed on the stack. */
6132 {
6136 }
6139 }
6141 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6143 static bool
6145 {
6146 /* Check operand constraints in case hard registers were propagated
6147 into insn pattern. This check prevents combine pass from
6148 generating insn patterns with invalid hard register operands.
6149 These invalid insns can eventually confuse reload to error out
6150 with a spill failure. See also PRs 46829 and 46843. */
6152 {
6161 {
6169 /* For pre-AVX disallow unaligned loads/stores where the
6170 instructions don't support it. */
6174 {
6178 }
6180 /* A unary operator may be accepted by the predicate, but it
6181 is irrelevant for matching constraints. */
6186 {
6194 }
6201 /* Operand has no constraints, anything is OK. */
6206 {
6211 && operands_match_p
6215 {
6218 }
6219 }
6223 }
6224 }
6227 }
6228 \f
6229 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6231 static unsigned HOST_WIDE_INT
6233 {
6237 }
6238 \f
6239 /* Argument support functions. */
6241 /* Return true when register may be used to pass function parameters. */
6242 bool
6244 {
6253 {
6257 else
6263 }
6269 /* TODO: The function should depend on current function ABI but
6270 builtins.c would need updating then. Therefore we use the
6271 default ABI. */
6274 /* RAX is used as hidden argument to va_arg functions. */
6280 else
6288 }
6290 /* Return if we do not know how to pass TYPE solely in registers. */
6292 static bool
6294 {
6298 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6299 The layout_type routine is crafty and tries to trick us into passing
6300 currently unsupported vector types on the stack by using TImode. */
6303 }
6305 /* It returns the size, in bytes, of the area reserved for arguments passed
6306 in registers for the function represented by fndecl dependent to the used
6307 abi format. */
6308 int
6310 {
6314 else
6319 }
6321 /* We add this as a workaround in order to use libc_has_function
6322 hook in i386.md. */
6323 bool
6325 {
6327 }
6329 /* Returns value SYSV_ABI, MS_ABI dependent on fntype,
6330 specifying the call abi used. */
6331 enum calling_abi
6333 {
6341 {
6346 }
6352 }
6354 static enum calling_abi
6356 {
6358 }
6360 /* Returns value SYSV_ABI, MS_ABI dependent on cfun,
6361 specifying the call abi used. */
6362 enum calling_abi
6364 {
6366 }
6368 static bool
6370 {
6372 {
6376 else
6378 }
6380 }
6382 /* Write the extra assembler code needed to declare a function properly. */
6384 void
6386 tree decl)
6387 {
6391 {
6397 }
6399 #ifdef SUBTARGET_ASM_UNWIND_INIT
6401 #endif
6405 /* Output magic byte marker, if hot-patch attribute is set. */
6407 {
6409 {
6410 /* leaq [%rsp + 0], %rsp */
6413 }
6414 else
6415 {
6416 /* movl.s %edi, %edi
6417 push %ebp
6418 movl.s %esp, %ebp */
6421 }
6422 }
6423 }
6425 /* regclass.c */
6428 /* Implementation of call abi switching target hook. Specific to FNDECL
6429 the specific call register sets are set. See also
6430 ix86_conditional_register_usage for more details. */
6431 void
6433 {
6435 }
6437 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6438 expensive re-initialization of init_regs each time we switch function context
6439 since this is needed only during RTL expansion. */
6440 static void
6442 {
6446 }
6448 /* Return 1 if pseudo register should be created and used to hold
6449 GOT address for PIC code. */
6450 bool
6452 {
6459 }
6461 /* Initialize large model PIC register. */
6463 static void
6465 {
6467 rtx tmp_reg;
6476 label));
6480 }
6482 /* Create and initialize PIC register if required. */
6483 static void
6485 {
6486 edge entry_edge;
6495 {
6498 else
6500 }
6501 else
6502 {
6503 /* If there is future mcount call in the function it is more profitable
6504 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6513 }
6521 }
6523 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6524 for a call to a function whose data type is FNTYPE.
6525 For a library call, FNTYPE is 0. */
6527 void
6531 tree fndecl,
6533 {
6540 {
6543 {
6547 }
6548 else
6550 }
6551 else
6556 /* Set up the number of registers to use for passing arguments. */
6559 {
6561 ? X86_64_REGPARM_MAX
6563 }
6565 {
6568 {
6570 ? X86_64_SSE_REGPARM_MAX
6572 }
6573 }
6581 /* Because type might mismatch in between caller and callee, we need to
6582 use actual type of function for local calls.
6583 FIXME: cgraph_analyze can be told to actually record if function uses
6584 va_start so for local functions maybe_vaarg can be made aggressive
6585 helping K&R code.
6586 FIXME: once typesytem is fixed, we won't need this code anymore. */
6600 {
6601 /* If there are variable arguments, then we won't pass anything
6602 in registers in 32-bit mode. */
6604 {
6606 /* Since in 32-bit, variable arguments are always passed on
6607 stack, there is scratch register available for indirect
6608 sibcall. */
6617 }
6619 /* Use ecx and edx registers if function has fastcall attribute,
6620 else look for regparm information. */
6622 {
6625 {
6628 }
6630 {
6633 }
6634 else
6636 }
6638 /* Set up the number of SSE registers used for passing SFmode
6639 and DFmode arguments. Warn for mismatching ABI. */
6641 }
6644 }
6646 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6647 But in the case of vector types, it is some vector mode.
6649 When we have only some of our vector isa extensions enabled, then there
6650 are some modes for which vector_mode_supported_p is false. For these
6651 modes, the generic vector support in gcc will choose some non-vector mode
6652 in order to implement the type. By computing the natural mode, we'll
6653 select the proper ABI location for the operand and not depend on whatever
6654 the middle-end decides to do with these vector types.
6656 The midde-end can't deal with the vector types > 16 bytes. In this
6657 case, we return the original mode and warn ABI change if CUM isn't
6658 NULL.
6660 If INT_RETURN is true, warn ABI change if the vector mode isn't
6661 available for function return value. */
6663 static machine_mode
6666 {
6670 {
6673 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6675 {
6680 else
6683 /* Get the mode which has this inner mode and number of units. */
6687 {
6689 {
6694 {
6698 }
6700 {
6704 }
6707 }
6709 {
6714 {
6718 }
6720 {
6724 }
6727 }
6729 && !TARGET_SSE
6731 {
6736 {
6740 }
6742 {
6746 }
6747 }
6749 && !TARGET_MMX
6751 {
6756 {
6760 }
6762 {
6766 }
6767 }
6769 }
6772 }
6773 }
6776 }
6778 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6779 this may not agree with the mode that the type system has chosen for the
6780 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6781 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6783 static rtx
6786 {
6787 rtx tmp;
6791 else
6792 {
6796 }
6799 }
6801 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6802 of this code is to classify each 8bytes of incoming argument by the register
6803 class and assign registers accordingly. */
6805 /* Return the union class of CLASS1 and CLASS2.
6806 See the x86-64 PS ABI for details. */
6808 static enum x86_64_reg_class
6810 {
6811 /* Rule #1: If both classes are equal, this is the resulting class. */
6815 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6816 the other class. */
6822 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6826 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6834 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6835 MEMORY is used. */
6844 /* Rule #6: Otherwise class SSE is used. */
6846 }
6848 /* Classify the argument of type TYPE and mode MODE.
6849 CLASSES will be filled by the register class used to pass each word
6850 of the operand. The number of words is returned. In case the parameter
6851 should be passed in memory, 0 is returned. As a special case for zero
6852 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6854 BIT_OFFSET is used internally for handling records and specifies offset
6855 of the offset in bits modulo 512 to avoid overflow cases.
6857 See the x86-64 PS ABI for details.
6858 */
6860 static int
6863 {
6864 HOST_WIDE_INT bytes =
6866 int words
6869 /* Variable sized entities are always passed/returned in memory. */
6877 /* Special case check for pointer to shared, on 64-bit target. */
6881 {
6884 }
6887 {
6889 tree field;
6892 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6899 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6900 signalize memory class, so handle it as special case. */
6902 {
6905 }
6907 /* Classify each field of record and merge classes. */
6909 {
6911 /* And now merge the fields of structure. */
6913 {
6915 {
6921 /* Bitfields are always classified as integer. Handle them
6922 early, since later code would consider them to be
6923 misaligned integers. */
6925 {
6934 }
6935 else
6936 {
6941 /* Flexible array member is ignored. */
6948 {
6952 {
6955 "the ABI of passing struct with"
6956 " a flexible array member has"
6958 }
6960 }
6962 subclasses,
6972 }
6973 }
6974 }
6978 /* Arrays are handled as small records. */
6979 {
6986 /* The partial classes are now full classes. */
6997 }
7000 /* Unions are similar to RECORD_TYPE but offset is always 0.
7001 */
7003 {
7005 {
7013 bit_offset);
7018 }
7019 }
7024 }
7027 {
7028 /* When size > 16 bytes, if the first one isn't
7029 X86_64_SSE_CLASS or any other ones aren't
7030 X86_64_SSEUP_CLASS, everything should be passed in
7031 memory. */
7038 }
7040 /* Final merger cleanup. */
7042 {
7043 /* If one class is MEMORY, everything should be passed in
7044 memory. */
7048 /* The X86_64_SSEUP_CLASS should be always preceded by
7049 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
7053 {
7054 /* The first one should never be X86_64_SSEUP_CLASS. */
7057 }
7059 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
7060 everything should be passed in memory. */
7063 {
7066 /* The first one should never be X86_64_X87UP_CLASS. */
7069 {
7072 "the ABI of passing union with long double"
7074 }
7076 }
7077 }
7079 }
7081 /* Compute alignment needed. We align all types to natural boundaries with
7082 exception of XFmode that is aligned to 64bits. */
7084 {
7093 /* Misaligned fields are always returned in memory. */
7096 }
7098 /* for V1xx modes, just use the base mode */
7103 /* Classification of atomic types. */
7105 {
7121 {
7124 /* Analyze last 128 bits only. */
7128 {
7131 }
7133 {
7136 }
7138 {
7142 }
7144 {
7147 }
7148 else
7150 }
7157 /* OImode shouldn't be used directly. */
7164 else
7182 else
7183 {
7187 {
7190 "the ABI of passing structure with complex float"
7192 }
7195 }
7204 /* This modes is larger than 16 bytes. */
7262 else
7266 }
7267 }
7269 /* Examine the argument and return set number of register required in each
7270 class. Return true iff parameter should be passed in memory. */
7272 static bool
7275 {
7286 {
7307 }
7310 }
7312 /* Construct container for the argument used by GCC interface. See
7313 FUNCTION_ARG for the detailed description. */
7315 static rtx
7319 {
7320 /* The following variables hold the static issued_error state. */
7325 machine_mode tmpmode;
7334 rtx ret;
7345 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7346 some less clueful developer tries to use floating-point anyway. */
7348 {
7350 {
7352 {
7355 }
7356 }
7358 {
7361 }
7363 }
7365 /* Likewise, error if the ABI requires us to return values in the
7366 x87 registers and the user specified -mno-80387. */
7372 {
7374 {
7377 }
7379 }
7381 /* First construct simple cases. Avoid SCmode, since we want to use
7382 single register to pass this type. */
7385 {
7400 /* Zero sized array, struct or class. */
7404 }
7443 /* Otherwise figure out the entries of the PARALLEL. */
7445 {
7449 {
7454 /* Merge TImodes on aligned occasions here too. */
7456 tmpmode
7460 else
7462 /* We've requested 24 bytes we
7463 don't have mode for. Use DImode. */
7470 intreg++;
7478 sse_regno++;
7486 sse_regno++;
7491 {
7497 {
7499 i++;
7500 }
7501 else
7526 }
7532 sse_regno++;
7536 }
7537 }
7539 /* Empty aligned struct, union or class. */
7547 }
7549 /* Update the data in CUM to advance over an argument of mode MODE
7550 and data type TYPE. (TYPE is null for libcalls where that information
7551 may not be available.)
7553 Return a number of integer regsiters advanced over. */
7555 static int
7558 HOST_WIDE_INT words)
7559 {
7564 {
7565 /* Intel MCU psABI passes scalars and aggregates no larger than 8
7566 bytes in registers. */
7570 }
7573 {
7580 /* FALLTHRU */
7586 pass_in_reg:
7593 {
7597 }
7601 /* OImode shouldn't be used directly. */
7614 /* FALLTHRU */
7636 {
7641 {
7644 }
7645 }
7655 {
7660 {
7663 }
7664 }
7666 }
7668 {
7674 }
7677 }
7679 static int
7682 {
7685 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7692 {
7698 }
7699 else
7700 {
7705 }
7706 }
7708 static int
7710 HOST_WIDE_INT words)
7711 {
7712 /* Otherwise, this should be passed indirect. */
7717 {
7721 }
7723 }
7725 /* Update the data in CUM to advance over an argument of mode MODE and
7726 data type TYPE. (TYPE is null for libcalls where that information
7727 may not be available.) */
7729 static void
7732 {
7739 else
7748 {
7749 /* If we pass bounds in BT then just update remained bounds count. */
7751 {
7754 }
7756 /* Update remained number of bounds to force. */
7763 }
7765 /* The first arg not going to Bounds Tables resets this counter. */
7767 /* For unnamed args we always pass bounds to avoid bounds mess when
7768 passed and received types do not match. If bounds do not follow
7769 unnamed arg, still pretend required number of bounds were passed. */
7771 {
7774 }
7777 {
7782 else
7784 }
7785 else
7788 /* For stdarg we expect bounds to be passed for each value passed
7789 in register. */
7792 /* For pointers passed in memory we expect bounds passed in Bounds
7793 Table. */
7796 }
7798 /* Define where to put the arguments to a function.
7799 Value is zero to push the argument on the stack,
7800 or a hard register in which to store the argument.
7802 MODE is the argument's machine mode.
7803 TYPE is the data type of the argument (as a tree).
7804 This is null for libcalls where that information may
7805 not be available.
7806 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7807 the preceding args and about the function being called.
7808 NAMED is nonzero if this argument is a named parameter
7809 (otherwise it is an extra parameter matching an ellipsis). */
7811 static rtx
7815 {
7817 /* Avoid the AL settings for the Unix64 ABI. */
7822 {
7823 /* Intel MCU psABI passes scalars and aggregates no larger than 8
7824 bytes in registers. */
7828 }
7831 {
7838 /* FALLTHRU */
7843 pass_in_reg:
7845 {
7848 /* Fastcall allocates the first two DWORD (SImode) or
7849 smaller arguments to ECX and EDX if it isn't an
7850 aggregate type . */
7852 {
7858 /* ECX not EAX is the first allocated register. */
7861 }
7863 }
7876 /* FALLTHRU */
7878 /* In 32bit, we pass TImode in xmm registers. */
7886 {
7890 }
7895 /* OImode and XImode shouldn't be used directly. */
7911 {
7915 }
7925 {
7929 }
7931 }
7933 {
7939 }
7942 }
7944 static rtx
7947 {
7948 /* Handle a hidden AL argument containing number of registers
7949 for varargs x86-64 functions. */
7953 ? X86_64_SSE_REGPARM_MAX
7958 {
7974 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7978 }
7984 }
7986 static rtx
7989 HOST_WIDE_INT bytes)
7990 {
7993 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7994 We use value of -2 to specify that current function call is MSABI. */
7998 /* If we've run out of registers, it goes on the stack. */
8004 /* Only floating point modes are passed in anything but integer regs. */
8006 {
8009 else
8010 {
8013 /* Unnamed floating parameters are passed in both the
8014 SSE and integer registers. */
8020 }
8021 }
8022 /* Handle aggregated types passed in register. */
8024 {
8029 }
8032 }
8034 /* Return where to put the arguments to a function.
8035 Return zero to push the argument on the stack, or a hard register in which to store the argument.
8037 MODE is the argument's machine mode. TYPE is the data type of the
8038 argument. It is null for libcalls where that information may not be
8039 available. CUM gives information about the preceding args and about
8040 the function being called. NAMED is nonzero if this argument is a
8041 named parameter (otherwise it is an extra parameter matching an
8042 ellipsis). */
8044 static rtx
8047 {
8051 rtx arg;
8053 /* All pointer bounds argumntas are handled separately here. */
8056 {
8057 /* Return NULL if bounds are forced to go in Bounds Table. */
8060 /* Return the next available bound reg if any. */
8063 /* Return the next special slot number otherwise. */
8064 else
8068 }
8072 else
8076 /* To simplify the code below, represent vector types with a vector mode
8077 even if MMX/SSE are not active. */
8082 {
8087 else
8089 }
8090 else
8094 }
8096 /* A C expression that indicates when an argument must be passed by
8097 reference. If nonzero for an argument, a copy of that argument is
8098 made in memory and a pointer to the argument is passed instead of
8099 the argument itself. The pointer is passed in whatever way is
8100 appropriate for passing a pointer to that type. */
8102 static bool
8105 {
8108 /* Bounds are never passed by reference. */
8114 {
8117 /* See Windows x64 Software Convention. */
8119 {
8123 {
8124 /* Arrays are passed by reference. */
8129 {
8130 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
8131 are passed by reference. */
8133 }
8134 }
8136 /* __m128 is passed by reference. */
8138 }
8141 }
8144 }
8146 /* Return true when TYPE should be 128bit aligned for 32bit argument
8147 passing ABI. XXX: This function is obsolete and is only used for
8148 checking psABI compatibility with previous versions of GCC. */
8150 static bool
8152 {
8164 {
8165 /* Walk the aggregates recursively. */
8167 {
8171 {
8172 tree field;
8174 /* Walk all the structure fields. */
8176 {
8180 }
8182 }
8185 /* Just for use if some languages passes arrays by value. */
8192 }
8193 }
8195 }
8197 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8198 XXX: This function is obsolete and is only used for checking psABI
8199 compatibility with previous versions of GCC. */
8201 static unsigned int
8204 {
8205 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8206 natural boundaries. */
8208 {
8209 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8210 make an exception for SSE modes since these require 128bit
8211 alignment.
8213 The handling here differs from field_alignment. ICC aligns MMX
8214 arguments to 4 byte boundaries, while structure fields are aligned
8215 to 8 byte boundaries. */
8217 {
8220 }
8221 else
8222 {
8225 }
8226 }
8230 }
8232 /* Return true when TYPE should be 128bit aligned for 32bit argument
8233 passing ABI. */
8235 static bool
8237 {
8247 {
8248 /* Walk the aggregates recursively. */
8250 {
8254 {
8255 tree field;
8257 /* Walk all the structure fields. */
8259 field;
8261 {
8265 }
8267 }
8270 /* Just for use if some languages passes arrays by value. */
8277 }
8278 }
8279 else
8283 }
8285 /* Gives the alignment boundary, in bits, of an argument with the
8286 specified mode and type. */
8288 static unsigned int
8290 {
8293 {
8294 /* Since the main variant type is used for call, we convert it to
8295 the main variant type. */
8298 }
8299 else
8303 else
8304 {
8309 {
8310 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8312 {
8315 }
8321 }
8324 && !warned
8326 saved_align))
8327 {
8330 "The ABI for passing parameters with %d-byte"
8333 }
8334 }
8337 }
8339 /* Return true if N is a possible register number of function value. */
8341 static bool
8343 {
8345 {
8358 /* Complex values are returned in %st(0)/%st(1) pair. */
8361 /* TODO: The function should depend on current function ABI but
8362 builtins.c would need updating then. Therefore we use the
8363 default ABI. */
8368 /* Complex values are returned in %xmm0/%xmm1 pair. */
8377 }
8380 }
8382 /* Define how to find the value returned by a function.
8383 VALTYPE is the data type of the value (as a tree).
8384 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8385 otherwise, FUNC is 0. */
8387 static rtx
8390 {
8393 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8394 we normally prevent this case when mmx is not available. However
8395 some ABIs may require the result to be returned like DImode. */
8399 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8400 we prevent this case when sse is not available. However some ABIs
8401 may require the result to be returned like integer TImode. */
8406 /* 32-byte vector modes in %ymm0. */
8410 /* 64-byte vector modes in %zmm0. */
8414 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8417 else
8418 /* Most things go in %eax. */
8421 /* Override FP return register with %xmm0 for local functions when
8422 SSE math is enabled or for functions with sseregparm attribute. */
8424 {
8427 {
8432 }
8436 }
8438 /* OImode shouldn't be used directly. */
8442 }
8444 static rtx
8446 const_tree valtype)
8447 {
8448 rtx ret;
8450 /* Handle libcalls, which don't provide a type node. */
8452 {
8456 {
8475 }
8478 }
8481 {
8482 /* Pointers are always returned in word_mode. */
8484 }
8490 /* For zero sized structures, construct_container returns NULL, but we
8491 need to keep rest of compiler happy by returning meaningful value. */
8496 }
8498 static rtx
8500 const_tree valtype)
8501 {
8505 {
8507 {
8526 }
8527 }
8529 }
8531 static rtx
8534 {
8549 else
8551 }
8553 static rtx
8555 {
8561 }
8563 /* Return an RTX representing a place where a function returns
8564 or recieves pointer bounds or NULL if no bounds are returned.
8566 VALTYPE is a data type of a value returned by the function.
8568 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8569 or FUNCTION_TYPE of the function.
8571 If OUTGOING is false, return a place in which the caller will
8572 see the return value. Otherwise, return a place where a
8573 function returns a value. */
8575 static rtx
8577 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8579 {
8585 {
8586 bitmap slots;
8588 bitmap_iterator bi;
8596 {
8601 }
8607 }
8608 else
8612 }
8614 /* Pointer function arguments and return values are promoted to
8615 word_mode. */
8617 static machine_mode
8621 {
8623 {
8625 {
8628 }
8631 }
8633 for_return);
8634 }
8636 /* Return true if a structure, union or array with MODE containing FIELD
8637 should be accessed using BLKmode. */
8639 static bool
8641 {
8642 /* Union with XFmode must be in BLKmode. */
8646 }
8648 rtx
8650 {
8652 }
8654 /* Return true iff type is returned in memory. */
8656 static bool
8658 {
8659 #ifdef SUBTARGET_RETURN_IN_MEMORY
8661 #else
8663 HOST_WIDE_INT size;
8669 {
8671 {
8674 /* __m128 is returned in xmm0. */
8683 /* Otherwise, the size must be exactly in [1248]. */
8685 }
8686 else
8687 {
8692 }
8693 }
8694 else
8695 {
8698 /* Intel MCU psABI returns scalars and aggregates no larger than 8
8699 bytes in registers. */
8710 {
8711 /* User-created vectors small enough to fit in EAX. */
8715 /* Unless ABI prescibes otherwise,
8716 MMX/3dNow values are returned in MM0 if available. */
8721 /* SSE values are returned in XMM0 if available. */
8725 /* AVX values are returned in YMM0 if available. */
8729 /* AVX512F values are returned in ZMM0 if available. */
8732 }
8740 /* OImode shouldn't be used directly. */
8744 }
8745 #endif
8746 }
8748 \f
8749 /* Create the va_list data type. */
8751 static tree
8753 {
8762 unsigned_type_node);
8765 unsigned_type_node);
8768 ptr_type_node);
8771 ptr_type_node);
8790 /* The correct type is an array type of one element. */
8792 }
8794 /* Setup the builtin va_list data type and for 64-bit the additional
8795 calling convention specific va_list data types. */
8797 static tree
8799 {
8801 {
8802 /* Initialize ABI specific va_list builtin types. */
8808 /* For MS_ABI we use plain pointer to argument area. */
8813 }
8814 else
8815 {
8816 /* For i386 we use plain pointer to argument area. */
8818 }
8819 }
8821 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8823 static void
8825 {
8827 alias_set_type set;
8830 /* GPR size of varargs save area. */
8833 else
8836 /* FPR size of varargs save area. We don't need it if we don't pass
8837 anything in SSE registers. */
8840 else
8854 {
8862 }
8865 {
8866 machine_mode smode;
8868 rtx test;
8870 /* Now emit code to save SSE registers. The AX parameter contains number
8871 of SSE parameter registers used to call this function, though all we
8872 actually check here is the zero/non-zero status. */
8877 label));
8879 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8880 we used movdqa (i.e. TImode) instead? Perhaps even better would
8881 be if we could determine the real mode of the data, via a hook
8882 into pass_stdarg. Ignore all that for now. */
8892 {
8901 }
8904 }
8905 }
8907 static void
8909 {
8913 /* Reset to zero, as there might be a sysv vaarg used
8914 before. */
8919 {
8930 }
8931 }
8933 static void
8936 {
8938 CUMULATIVE_ARGS next_cum;
8939 tree fntype;
8941 /* This argument doesn't appear to be used anymore. Which is good,
8942 because the old code here didn't suppress rtl generation. */
8950 /* For varargs, we do not want to skip the dummy va_dcl argument.
8951 For stdargs, we do want to skip the last named argument. */
8959 else
8961 }
8963 static void
8966 tree type,
8969 {
8971 CUMULATIVE_ARGS next_cum;
8972 tree fntype;
8973 rtx save_area;
8978 /* Do nothing if we use plain pointer to argument area. */
8984 /* For varargs, we do not want to skip the dummy va_dcl argument.
8985 For stdargs, we do want to skip the last named argument. */
8999 {
9003 rtx bounds;
9007 else
9008 {
9009 rtx ldx_addr =
9016 }
9022 bnd_reg++;
9023 }
9024 }
9027 /* Checks if TYPE is of kind va_list char *. */
9029 static bool
9031 {
9032 tree canonic;
9034 /* For 32-bit it is always true. */
9040 }
9042 /* Implement va_start. */
9044 static void
9046 {
9050 tree type;
9051 rtx ovf_rtx;
9055 {
9058 /* When we are splitting the stack, we can't refer to the stack
9059 arguments using internal_arg_pointer, because they may be on
9060 the old stack. The split stack prologue will arrange to
9061 leave a pointer to the old stack arguments in a scratch
9062 register, which we here copy to a pseudo-register. The split
9063 stack prologue can't set the pseudo-register directly because
9064 it (the prologue) runs before any registers have been saved. */
9068 {
9069 rtx reg;
9083 }
9084 }
9086 /* Only 64bit target needs something special. */
9088 {
9091 else
9092 {
9102 /* Store zero bounds for va_list. */
9106 next));
9108 }
9110 }
9119 /* The following should be folded into the MEM_REF offset. */
9129 /* Count number of gp and fp argument registers used. */
9135 {
9141 }
9144 {
9150 }
9152 /* Find the overflow area. */
9156 else
9162 /* Store zero bounds for overflow area pointer. */
9171 {
9172 /* Find the register save area.
9173 Prologue of the function save it right above stack frame. */
9179 /* Store zero bounds for save area pointer. */
9186 }
9187 }
9189 /* Implement va_arg. */
9191 static tree
9194 {
9201 rtx container;
9203 tree ptrtype;
9204 machine_mode nat_mode;
9207 /* Only 64bit target needs something special. */
9231 {
9244 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9246 {
9249 }
9257 }
9259 /* Pull the value out of the saved registers. */
9264 {
9278 /* In case we are passing structure, verify that it is consecutive block
9279 on the register save area. If not we need to do moves. */
9281 {
9282 /* Verify that all registers are strictly consecutive */
9284 {
9288 {
9293 }
9294 }
9295 else
9296 {
9300 {
9305 }
9306 }
9307 }
9309 {
9312 }
9313 else
9314 {
9317 }
9319 /* First ensure that we fit completely in registers. */
9321 {
9328 }
9330 {
9338 }
9340 /* Compute index to start of area used for integer regs. */
9342 {
9343 /* int_addr = gpr + sav; */
9346 }
9348 {
9349 /* sse_addr = fpr + sav; */
9352 }
9354 {
9358 /* addr = &temp; */
9363 {
9367 tree piece_type;
9368 tree addr_type;
9369 tree daddr_type;
9378 {
9383 }
9387 else
9394 {
9397 }
9398 else
9399 {
9402 }
9409 {
9414 }
9415 else
9416 {
9417 tree copy
9422 }
9424 }
9425 }
9428 {
9432 }
9435 {
9439 }
9444 }
9446 /* ... otherwise out of the overflow area. */
9448 /* When we align parameter on stack for caller, if the parameter
9449 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9450 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9451 here with caller. */
9456 /* Care for on-stack alignment if needed. */
9459 else
9460 {
9465 }
9482 }
9483 \f
9484 /* Return true if OPNUM's MEM should be matched
9485 in movabs* patterns. */
9487 bool
9489 {
9501 }
9502 \f
9503 /* Initialize the table of extra 80387 mathematical constants. */
9505 static void
9507 {
9509 {
9515 };
9519 {
9521 /* Ensure each constant is rounded to XFmode precision. */
9524 }
9527 }
9529 /* Return non-zero if the constant is something that
9530 can be loaded with a special instruction. */
9532 int
9534 {
9537 REAL_VALUE_TYPE r;
9549 /* For XFmode constants, try to find a special 80387 instruction when
9550 optimizing for size or on those CPUs that benefit from them. */
9553 {
9562 }
9564 /* Load of the constant -0.0 or -1.0 will be split as
9565 fldz;fchs or fld1;fchs sequence. */
9572 }
9574 /* Return the opcode of the special instruction to be used to load
9575 the constant X. */
9579 {
9581 {
9601 }
9602 }
9604 /* Return the CONST_DOUBLE representing the 80387 constant that is
9605 loaded by the specified special instruction. The argument IDX
9606 matches the return value from standard_80387_constant_p. */
9608 rtx
9610 {
9617 {
9628 }
9631 XFmode);
9632 }
9634 /* Return 1 if X is all 0s and 2 if x is all 1s
9635 in supported SSE/AVX vector mode. */
9637 int
9639 {
9640 machine_mode mode;
9651 {
9672 }
9675 }
9677 /* Return the opcode of the special instruction to be used to load
9678 the constant X. */
9682 {
9684 {
9687 {
9714 }
9724 else
9729 }
9731 }
9733 /* Returns true if OP contains a symbol reference */
9735 bool
9737 {
9746 {
9748 {
9754 }
9758 }
9761 }
9763 /* Return true if it is appropriate to emit `ret' instructions in the
9764 body of a function. Do this only if the epilogue is simple, needing a
9765 couple of insns. Prior to reloading, we can't tell how many registers
9766 must be saved, so return false then. Return false if there is no frame
9767 marker to de-allocate. */
9769 bool
9771 {
9777 /* Don't allow more than 32k pop, since that's all we can do
9778 with one instruction. */
9785 }
9786 \f
9787 /* Value should be nonzero if functions must have frame pointers.
9788 Zero means the frame pointer need not be set up (and parms may
9789 be accessed via the stack pointer) in functions that seem suitable. */
9791 static bool
9793 {
9794 /* If we accessed previous frames, then the generated code expects
9795 to be able to access the saved ebp value in our frame. */
9799 /* Several x86 os'es need a frame pointer for other reasons,
9800 usually pertaining to setjmp. */
9804 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9808 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9809 allocation is 4GB. */
9813 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9814 turns off the frame pointer by default. Turn it back on now if
9815 we've not got a leaf function. */
9825 }
9827 /* Record that the current function accesses previous call frames. */
9829 void
9831 {
9833 }
9834 \f
9835 #ifndef USE_HIDDEN_LINKONCE
9836 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9837 # define USE_HIDDEN_LINKONCE 1
9838 # else
9839 # define USE_HIDDEN_LINKONCE 0
9840 # endif
9841 #endif
9845 /* Fills in the label name that should be used for a pc thunk for
9846 the given register. */
9848 static void
9850 {
9855 else
9857 }
9860 /* This function generates code for -fpic that loads %ebx with
9861 the return address of the caller and then returns. */
9863 static void
9865 {
9870 {
9872 tree decl;
9888 #if TARGET_MACHO
9890 {
9899 }
9900 else
9901 #endif
9903 {
9914 }
9915 else
9916 {
9919 }
9925 /* Make sure unwind info is emitted for the thunk if needed. */
9928 /* Pad stack IP move with 4 instructions (two NOPs count
9929 as one instruction). */
9931 {
9936 }
9947 }
9951 }
9953 /* Emit code for the SET_GOT patterns. */
9957 {
9963 {
9964 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9969 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9970 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9971 an unadorned address. */
9976 }
9981 {
9983 /* We don't need a pic base, we're not producing pic. */
9990 }
9991 else
9992 {
10001 #if TARGET_MACHO
10002 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
10003 This is what will be referenced by the Mach-O PIC subsystem. */
10007 /* When we are restoring the pic base at the site of a nonlocal label,
10008 and we decided to emit the pic base above, we will still output a
10009 local label used for calculating the correction offset (even though
10010 the offset will be 0 in that case). */
10014 #endif
10015 }
10021 }
10023 /* Generate an "push" pattern for input ARG. */
10025 static rtx
10027 {
10039 stack_pointer_rtx)),
10040 arg);
10041 }
10043 /* Generate an "pop" pattern for input ARG. */
10045 static rtx
10047 {
10054 stack_pointer_rtx)));
10055 }
10057 /* Return >= 0 if there is an unused call-clobbered register available
10058 for the entire function. */
10060 static unsigned int
10062 {
10069 {
10071 /* Can't use the same register for both PIC and DRAP. */
10074 else
10079 }
10082 }
10084 /* Return TRUE if we need to save REGNO. */
10086 static bool
10088 {
10091 {
10093 {
10094 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
10095 _mcount in prologue. */
10098 }
10105 }
10108 {
10111 {
10117 }
10118 }
10129 }
10131 /* Return number of saved general prupose registers. */
10133 static int
10135 {
10141 nregs ++;
10143 }
10145 /* Return number of saved SSE registrers. */
10147 static int
10149 {
10157 nregs ++;
10159 }
10161 /* Given FROM and TO register numbers, say whether this elimination is
10162 allowed. If stack alignment is needed, we can only replace argument
10163 pointer with hard frame pointer, or replace frame pointer with stack
10164 pointer. Otherwise, frame pointer elimination is automatically
10165 handled and all other eliminations are valid. */
10167 static bool
10169 {
10175 else
10177 }
10179 /* Return the offset between two registers, one to be eliminated, and the other
10180 its replacement, at the start of a routine. */
10182 HOST_WIDE_INT
10184 {
10193 else
10194 {
10202 }
10203 }
10205 /* In a dynamically-aligned function, we can't know the offset from
10206 stack pointer to frame pointer, so we must ensure that setjmp
10207 eliminates fp against the hard fp (%ebp) rather than trying to
10208 index from %esp up to the top of the frame across a gap that is
10209 of unknown (at compile-time) size. */
10210 static rtx
10212 {
10214 }
10216 /* When using -fsplit-stack, the allocation routines set a field in
10217 the TCB to the bottom of the stack plus this much space, measured
10218 in bytes. */
10220 #define SPLIT_STACK_AVAILABLE 256
10222 /* Fill structure ix86_frame about frame of currently computed function. */
10224 static void
10226 {
10228 HOST_WIDE_INT offset;
10231 HOST_WIDE_INT to_allocate;
10236 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10237 function prologues and leaf. */
10241 {
10244 }
10245 /* preferred_stack_boundary is never updated for call
10246 expanded from tls descriptor. Update it here. We don't update it in
10247 expand stage because according to the comments before
10248 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10249 away. */
10252 {
10256 }
10265 /* For SEH we have to limit the amount of code movement into the prologue.
10266 At present we do this via a BLOCKAGE, at which point there's very little
10267 scheduling that can be done, which means that there's very little point
10268 in doing anything except PUSHs. */
10272 /* During reload iteration the amount of registers saved can change.
10273 Recompute the value as needed. Do not recompute when amount of registers
10274 didn't change as reload does multiple calls to the function and does not
10275 expect the decision to change within single iteration. */
10278 {
10284 /* The fast prologue uses move instead of push to save registers. This
10285 is significantly longer, but also executes faster as modern hardware
10286 can execute the moves in parallel, but can't do that for push/pop.
10288 Be careful about choosing what prologue to emit: When function takes
10289 many instructions to execute we may use slow version as well as in
10290 case function is known to be outside hot spot (this is known with
10291 feedback only). Weight the size of function by number of registers
10292 to save as it is cheap to use one or two push instructions but very
10293 slow to use many of them. */
10297 || (flag_branch_probabilities
10300 else
10303 }
10305 frame->save_regs_using_mov
10307 /* If static stack checking is enabled and done with probes,
10308 the registers need to be saved before allocating the frame. */
10311 /* Skip return address. */
10314 /* Skip pushed static chain. */
10318 /* Skip saved base pointer. */
10323 /* The traditional frame pointer location is at the top of the frame. */
10326 /* Register save area */
10330 /* On SEH target, registers are pushed just before the frame pointer
10331 location. */
10335 /* Align and set SSE register save area. */
10337 {
10338 /* The only ABI that has saved SSE registers (Win64) also has a
10339 16-byte aligned default stack, and thus we don't need to be
10340 within the re-aligned local stack frame to save them. */
10344 }
10347 /* The re-aligned stack starts here. Values before this point are not
10348 directly comparable with values below this point. In order to make
10349 sure that no value happens to be the same before and after, force
10350 the alignment computation below to add a non-zero value. */
10354 /* Va-arg area */
10358 /* Align start of frame for local function. */
10367 /* Frame pointer points here. */
10372 /* Add outgoing arguments area. Can be skipped if we eliminated
10373 all the function calls as dead code.
10374 Skipping is however impossible when function calls alloca. Alloca
10375 expander assumes that last crtl->outgoing_args_size
10376 of stack frame are unused. */
10380 {
10383 }
10384 else
10387 /* Align stack boundary. Only needed if we're calling another function
10388 or using alloca. */
10393 /* We've reached end of stack frame. */
10396 /* Size prologue needs to allocate. */
10407 {
10413 }
10414 else
10418 /* The SEH frame pointer location is near the bottom of the frame.
10419 This is enforced by the fact that the difference between the
10420 stack pointer and the frame pointer is limited to 240 bytes in
10421 the unwind data structure. */
10423 {
10424 HOST_WIDE_INT diff;
10426 /* If we can leave the frame pointer where it is, do so. Also, returns
10427 the establisher frame for __builtin_frame_address (0). */
10432 {
10433 /* Ideally we'd determine what portion of the local stack frame
10434 (within the constraint of the lowest 240) is most heavily used.
10435 But without that complication, simply bias the frame pointer
10436 by 128 bytes so as to maximize the amount of the local stack
10437 frame that is addressable with 8-bit offsets. */
10439 }
10440 }
10441 }
10443 /* This is semi-inlined memory_address_length, but simplified
10444 since we know that we're always dealing with reg+offset, and
10445 to avoid having to create and discard all that rtl. */
10449 {
10453 {
10454 /* EBP and R13 cannot be encoded without an offset. */
10456 }
10460 /* ESP and R12 must be encoded with a SIB byte. */
10462 len++;
10465 }
10467 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10468 The valid base registers are taken from CFUN->MACHINE->FS. */
10470 static rtx
10472 {
10478 {
10479 /* Choose the base register most likely to allow the most scheduling
10480 opportunities. Generally FP is valid throughout the function,
10481 while DRAP must be reloaded within the epilogue. But choose either
10482 over the SP due to increased encoding size. */
10485 {
10488 }
10490 {
10493 }
10495 {
10498 }
10499 }
10500 else
10501 {
10502 HOST_WIDE_INT toffset;
10505 /* Choose the base register with the smallest address encoding.
10506 With a tie, choose FP > DRAP > SP. */
10508 {
10512 }
10514 {
10518 {
10522 }
10523 }
10525 {
10529 {
10533 }
10534 }
10535 }
10539 }
10541 /* Emit code to save registers in the prologue. */
10543 static void
10545 {
10551 {
10554 }
10555 }
10557 /* Emit a single register save at CFA - CFA_OFFSET. */
10559 static void
10561 HOST_WIDE_INT cfa_offset)
10562 {
10570 /* For SSE saves, we need to indicate the 128-bit alignment. */
10581 /* When saving registers into a re-aligned local stack frame, avoid
10582 any tricky guessing by dwarf2out. */
10584 {
10588 {
10589 /* A bit of a hack. We force the DRAP register to be saved in
10590 the re-aligned stack frame, which provides us with a copy
10591 of the CFA that will last past the prologue. Install it. */
10597 }
10598 else
10599 {
10600 /* The frame pointer is a stable reference within the
10601 aligned frame. Use it. */
10607 }
10608 }
10610 /* The memory may not be relative to the current CFA register,
10611 which means that we may need to generate a new pattern for
10612 use by the unwind info. */
10614 {
10619 }
10620 }
10622 /* Emit code to save registers using MOV insns.
10623 First register is stored at CFA - CFA_OFFSET. */
10624 static void
10626 {
10631 {
10634 }
10635 }
10637 /* Emit code to save SSE registers using MOV insns.
10638 First register is stored at CFA - CFA_OFFSET. */
10639 static void
10641 {
10646 {
10649 }
10650 }
10654 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10655 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10656 Don't add the note if the previously saved value will be left untouched
10657 within stack red-zone till return, as unwinders can find the same value
10658 in the register and on the stack. */
10660 static void
10662 {
10668 {
10671 }
10672 else
10673 queued_cfa_restores
10675 }
10677 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10679 static void
10681 {
10682 rtx last;
10686 ;
10691 }
10693 /* Expand prologue or epilogue stack adjustment.
10694 The pattern exist to put a dependency on all ebp-based memory accesses.
10695 STYLE should be negative if instructions should be marked as frame related,
10696 zero if %r11 register is live and cannot be freely used and positive
10697 otherwise. */
10699 static void
10702 {
10704 rtx insn;
10711 else
10712 {
10713 rtx tmp;
10714 /* r11 is used by indirect sibcall return as well, set before the
10715 epilogue and used after the epilogue. */
10718 else
10719 {
10723 }
10729 }
10736 {
10737 rtx r;
10747 }
10749 {
10752 {
10756 }
10757 }
10760 {
10765 {
10768 }
10770 {
10773 }
10774 else
10775 {
10776 /* Else there are two possibilities: SP itself, which we set
10777 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10778 taken care of this by hand along the eh_return path. */
10781 }
10785 }
10786 }
10788 /* Find an available register to be used as dynamic realign argument
10789 pointer regsiter. Such a register will be written in prologue and
10790 used in begin of body, so it must not be
10791 1. parameter passing register.
10792 2. GOT pointer.
10793 We reuse static-chain register if it is available. Otherwise, we
10794 use DI for i386 and R13 for x86-64. We chose R13 since it has
10795 shorter encoding.
10797 Return: the regno of chosen register. */
10799 static unsigned int
10801 {
10805 {
10806 /* Use R13 for nested function or function need static chain.
10807 Since function with tail call may use any caller-saved
10808 registers in epilogue, DRAP must not use caller-saved
10809 register in such case. */
10814 }
10815 else
10816 {
10817 /* Use DI for nested function or function need static chain.
10818 Since function with tail call may use any caller-saved
10819 registers in epilogue, DRAP must not use caller-saved
10820 register in such case. */
10824 /* Reuse static chain register if it isn't used for parameter
10825 passing. */
10827 {
10831 }
10833 }
10834 }
10836 /* Return minimum incoming stack alignment. */
10838 static unsigned int
10840 {
10843 /* Prefer the one specified at command line. */
10846 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10847 if -mstackrealign is used, it isn't used for sibcall check and
10848 estimated stack alignment is 128bit. */
10850 && !TARGET_64BIT
10851 && ix86_force_align_arg_pointer
10854 else
10857 /* Incoming stack alignment can be changed on individual functions
10858 via force_align_arg_pointer attribute. We use the smallest
10859 incoming stack boundary. */
10865 /* The incoming stack frame has to be aligned at least at
10866 parm_stack_boundary. */
10870 /* Stack at entrance of main is aligned by runtime. We use the
10871 smallest incoming stack boundary. */
10879 }
10881 /* Update incoming stack boundary and estimated stack alignment. */
10883 static void
10885 {
10886 ix86_incoming_stack_boundary
10889 /* x86_64 vararg needs 16byte stack alignment for register save
10890 area. */
10895 }
10897 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10898 needed or an rtx for DRAP otherwise. */
10900 static rtx
10902 {
10907 {
10908 /* Assign DRAP to vDRAP and returns vDRAP */
10910 rtx drap_vreg;
10911 rtx arg_ptr;
10924 {
10927 }
10929 }
10930 else
10932 }
10934 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10936 static rtx
10938 {
10940 }
10943 rtx reg;
10945 };
10947 /* Return a short-lived scratch register for use on function entry.
10948 In 32-bit mode, it is valid only after the registers are saved
10949 in the prologue. This register must be released by means of
10950 release_scratch_register_on_entry once it is dead. */
10952 static void
10954 {
10960 {
10961 /* We always use R11 in 64-bit mode. */
10963 }
10964 else
10965 {
10967 bool fastcall_p
10969 bool thiscall_p
10973 int drap_regno
10976 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10977 for the static chain register. */
10981 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10982 for the static chain register. */
10987 /* ecx is the static chain register. */
10989 && !static_chain_p
10994 /* esi is the static chain register. */
11000 else
11001 {
11004 }
11005 }
11009 {
11012 }
11013 }
11015 /* Release a scratch register obtained from the preceding function. */
11017 static void
11019 {
11021 {
11025 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
11031 }
11032 }
11034 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11036 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
11038 static void
11040 {
11041 /* We skip the probe for the first interval + a small dope of 4 words and
11042 probe that many bytes past the specified size to maintain a protection
11043 area at the botton of the stack. */
11047 /* See if we have a constant small number of probes to generate. If so,
11048 that's the easy case. The run-time loop is made up of 11 insns in the
11049 generic case while the compile-time loop is made up of 3+2*(n-1) insns
11050 for n # of intervals. */
11052 {
11056 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
11057 values of N from 1 until it exceeds SIZE. If only one probe is
11058 needed, this will not generate any code. Then adjust and probe
11059 to PROBE_INTERVAL + SIZE. */
11061 {
11063 {
11066 }
11067 else
11074 }
11078 else
11086 /* Adjust back to account for the additional first interval. */
11090 }
11092 /* Otherwise, do the same as above, but in a loop. Note that we must be
11093 extra careful with variables wrapping around because we might be at
11094 the very top (or the very bottom) of the address space and we have
11095 to be able to handle this case properly; in particular, we use an
11096 equality test for the loop condition. */
11097 else
11098 {
11099 HOST_WIDE_INT rounded_size;
11105 /* Step 1: round SIZE to the previous multiple of the interval. */
11110 /* Step 2: compute initial and final value of the loop counter. */
11112 /* SP = SP_0 + PROBE_INTERVAL. */
11117 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
11121 stack_pointer_rtx)));
11124 /* Step 3: the loop
11126 while (SP != LAST_ADDR)
11127 {
11128 SP = SP + PROBE_INTERVAL
11129 probe at SP
11130 }
11132 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
11133 values of N from 1 until it is equal to ROUNDED_SIZE. */
11138 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
11139 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
11142 {
11147 }
11149 /* Adjust back to account for the additional first interval. */
11155 }
11159 /* Even if the stack pointer isn't the CFA register, we need to correctly
11160 describe the adjustments made to it, in particular differentiate the
11161 frame-related ones from the frame-unrelated ones. */
11163 {
11176 }
11178 /* Make sure nothing is scheduled before we are done. */
11180 }
11182 /* Adjust the stack pointer up to REG while probing it. */
11186 {
11196 /* Jump to END_LAB if SP == LAST_ADDR. */
11204 /* SP = SP + PROBE_INTERVAL. */
11208 /* Probe at SP. */
11219 }
11221 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11222 inclusive. These are offsets from the current stack pointer. */
11224 static void
11226 {
11227 /* See if we have a constant small number of probes to generate. If so,
11228 that's the easy case. The run-time loop is made up of 7 insns in the
11229 generic case while the compile-time loop is made up of n insns for n #
11230 of intervals. */
11232 {
11233 HOST_WIDE_INT i;
11235 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11236 it exceeds SIZE. If only one probe is needed, this will not
11237 generate any code. Then probe at FIRST + SIZE. */
11244 }
11246 /* Otherwise, do the same as above, but in a loop. Note that we must be
11247 extra careful with variables wrapping around because we might be at
11248 the very top (or the very bottom) of the address space and we have
11249 to be able to handle this case properly; in particular, we use an
11250 equality test for the loop condition. */
11251 else
11252 {
11259 /* Step 1: round SIZE to the previous multiple of the interval. */
11264 /* Step 2: compute initial and final value of the loop counter. */
11266 /* TEST_OFFSET = FIRST. */
11269 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11273 /* Step 3: the loop
11275 while (TEST_ADDR != LAST_ADDR)
11276 {
11277 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11278 probe at TEST_ADDR
11279 }
11281 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11282 until it is equal to ROUNDED_SIZE. */
11287 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11288 that SIZE is equal to ROUNDED_SIZE. */
11293 stack_pointer_rtx,
11298 }
11300 /* Make sure nothing is scheduled before we are done. */
11302 }
11304 /* Probe a range of stack addresses from REG to END, inclusive. These are
11305 offsets from the current stack pointer. */
11309 {
11319 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11327 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11331 /* Probe at TEST_ADDR. */
11344 }
11346 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11347 to be generated in correct form. */
11348 static void
11350 {
11351 /* Check if stack realign is really needed after reload, and
11352 stores result in cfun */
11353 unsigned int incoming_stack_boundary
11362 {
11363 /* After stack_realign_needed is finalized, we can't no longer
11364 change it. */
11367 }
11369 /* If the only reason for frame_pointer_needed is that we conservatively
11370 assumed stack realignment might be needed, but in the end nothing that
11371 needed the stack alignment had been spilled, clear frame_pointer_needed
11372 and say we don't need stack realignment. */
11374 && frame_pointer_needed
11376 && flag_omit_frame_pointer
11378 && !ix86_current_function_calls_tls_descriptor
11387 {
11389 basic_block bb;
11396 HARD_FRAME_POINTER_REGNUM);
11398 {
11403 set_up_by_prologue))
11404 {
11408 }
11409 }
11411 /* If drap has been set, but it actually isn't live at the start
11412 of the function, there is no reason to set it up. */
11414 {
11417 {
11420 }
11421 }
11422 else
11437 }
11441 }
11443 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11445 static void
11447 {
11453 {
11456 {
11462 }
11463 }
11464 }
11466 /* Expand the prologue into a bunch of separate insns. */
11468 void
11470 {
11474 HOST_WIDE_INT allocate;
11481 /* DRAP should not coexist with stack_realign_fp */
11486 /* Initialize CFA state for before the prologue. */
11490 /* Track SP offset to the CFA. We continue tracking this after we've
11491 swapped the CFA register away from SP. In the case of re-alignment
11492 this is fudged; we're interested to offsets within the local frame. */
11499 {
11500 /* We should have already generated an error for any use of
11501 ms_hook on a nested function. */
11504 /* Check if profiling is active and we shall use profiling before
11505 prologue variant. If so sorry. */
11510 /* In ix86_asm_output_function_label we emitted:
11511 8b ff movl.s %edi,%edi
11512 55 push %ebp
11513 8b ec movl.s %esp,%ebp
11515 This matches the hookable function prologue in Win32 API
11516 functions in Microsoft Windows XP Service Pack 2 and newer.
11517 Wine uses this to enable Windows apps to hook the Win32 API
11518 functions provided by Wine.
11520 What that means is that we've already set up the frame pointer. */
11524 {
11527 /* We've decided to use the frame pointer already set up.
11528 Describe this to the unwinder by pretending that both
11529 push and mov insns happen right here.
11531 Putting the unwind info here at the end of the ms_hook
11532 is done so that we can make absolutely certain we get
11533 the required byte sequence at the start of the function,
11534 rather than relying on an assembler that can produce
11535 the exact encoding required.
11537 However it does mean (in the unpatched case) that we have
11538 a 1 insn window where the asynchronous unwind info is
11539 incorrect. However, if we placed the unwind info at
11540 its correct location we would have incorrect unwind info
11541 in the patched case. Which is probably all moot since
11542 I don't expect Wine generates dwarf2 unwind info for the
11543 system libraries that use this feature. */
11549 stack_pointer_rtx);
11557 /* Note that gen_push incremented m->fs.cfa_offset, even
11558 though we didn't emit the push insn here. */
11562 }
11563 else
11564 {
11565 /* The frame pointer is not needed so pop %ebp again.
11566 This leaves us with a pristine state. */
11568 }
11569 }
11571 /* The first insn of a function that accepts its static chain on the
11572 stack is to push the register that would be filled in by a direct
11573 call. This insn will be skipped by the trampoline. */
11575 {
11580 /* We don't want to interpret this push insn as a register save,
11581 only as a stack adjustment. The real copy of the register as
11582 a save will be done later, if needed. */
11587 }
11589 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11590 of DRAP is needed and stack realignment is really needed after reload */
11592 {
11595 /* Only need to push parameter pointer reg if it is caller saved. */
11597 {
11598 /* Push arg pointer reg */
11601 }
11603 /* Grab the argument pointer. */
11610 /* Align the stack. */
11612 stack_pointer_rtx,
11616 /* Replicate the return address on the stack so that return
11617 address can be reached via (argp - 1) slot. This is needed
11618 to implement macro RETURN_ADDR_RTX and intrinsic function
11619 expand_builtin_return_addr etc. */
11625 /* For the purposes of frame and register save area addressing,
11626 we've started over with a new frame. */
11631 {
11632 /* Replicate static chain on the stack so that static chain
11633 can be reached via (argp - 2) slot. This is needed for
11634 nested function with stack realignment. */
11637 }
11638 }
11644 {
11645 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11646 slower on all targets. Also sdb doesn't like it. */
11650 /* Push registers now, before setting the frame pointer
11651 on SEH target. */
11653 && TARGET_SEH
11655 {
11659 }
11662 {
11670 }
11671 }
11674 {
11675 /* If saving registers via PUSH, do so now. */
11677 {
11681 }
11683 /* When using red zone we may start register saving before allocating
11684 the stack frame saving one cycle of the prologue. However, avoid
11685 doing this if we have to probe the stack; at least on x86_64 the
11686 stack probe can turn into a call that clobbers a red zone location. */
11688 && (! TARGET_STACK_PROBE
11690 {
11693 }
11694 }
11697 {
11701 /* The computation of the size of the re-aligned stack frame means
11702 that we must allocate the size of the register save area before
11703 performing the actual alignment. Otherwise we cannot guarantee
11704 that there's enough storage above the realignment point. */
11711 /* Align the stack. */
11713 stack_pointer_rtx,
11716 /* For the purposes of register save area addressing, the stack
11717 pointer is no longer valid. As for the value of sp_offset,
11718 see ix86_compute_frame_layout, which we need to match in order
11719 to pass verification of stack_pointer_offset at the end. */
11722 }
11727 {
11728 /* We start to count from ARG_POINTER. */
11731 /* If it was realigned, take into account the fake frame. */
11733 {
11740 /* This over-estimates by 1 minimal-stack-alignment-unit but
11741 mitigates that by counting in the new return address slot. */
11742 current_function_dynamic_stack_size
11744 }
11747 }
11749 /* On SEH target with very large frame size, allocate an area to save
11750 SSE registers (as the very large allocation won't be described). */
11754 {
11755 HOST_WIDE_INT sse_size =
11760 /* No need to do stack checking as the area will be immediately
11761 written. */
11768 }
11770 /* The stack has already been decremented by the instruction calling us
11771 so probe if the size is non-negative to preserve the protection area. */
11773 {
11774 /* We expect the registers to be saved when probes are used. */
11778 {
11781 {
11784 }
11785 }
11786 else
11787 {
11794 {
11796 {
11799 }
11800 else
11802 }
11803 else
11804 {
11806 {
11810 }
11811 else
11813 }
11814 }
11815 }
11818 ;
11821 {
11825 }
11826 else
11827 {
11839 {
11842 /* Note that SEH directives need to continue tracking the stack
11843 pointer even after the frame pointer has been set up. */
11845 {
11853 }
11854 }
11857 {
11862 {
11870 }
11871 }
11876 /* Use the fact that AX still contains ALLOCATE. */
11878 ? gen_pro_epilogue_adjust_stack_di_sub
11885 {
11893 }
11896 /* Use stack_pointer_rtx for relative addressing so that code
11897 works for realigned stack, too. */
11899 {
11906 }
11908 {
11913 }
11914 }
11917 /* If we havn't already set up the frame pointer, do so now. */
11919 {
11931 }
11938 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11939 in PROLOGUE. */
11941 {
11947 /* Deleting already emmitted SET_GOT if exist and allocated to
11948 REAL_PIC_OFFSET_TABLE_REGNUM. */
11950 }
11953 {
11954 /* vDRAP is setup but after reload it turns out stack realign
11955 isn't necessary, here we will emit prologue to setup DRAP
11956 without stack realign adjustment */
11959 }
11961 /* Prevent instructions from being scheduled into register save push
11962 sequence when access to the redzone area is done through frame pointer.
11963 The offset between the frame pointer and the stack pointer is calculated
11964 relative to the value of the stack pointer at the end of the function
11965 prologue, and moving instructions that access redzone area via frame
11966 pointer inside push sequence violates this assumption. */
11970 /* Emit cld instruction if stringops are used in the function. */
11974 /* SEH requires that the prologue end within 256 bytes of the start of
11975 the function. Prevent instruction schedules that would extend that.
11976 Further, prevent alloca modifications to the stack pointer from being
11977 combined with prologue modifications. */
11980 }
11982 /* Emit code to restore REG using a POP insn. */
11984 static void
11986 {
11995 {
11996 /* Previously we'd represented the CFA as an expression
11997 like *(%ebp - 8). We've just popped that value from
11998 the stack, which means we need to reset the CFA to
11999 the drap register. This will remain until we restore
12000 the stack pointer. */
12004 /* This means that the DRAP register is valid for addressing too. */
12007 }
12010 {
12017 }
12019 /* When the frame pointer is the CFA, and we pop it, we are
12020 swapping back to the stack pointer as the CFA. This happens
12021 for stack frames that don't allocate other data, so we assume
12022 the stack pointer is now pointing at the return address, i.e.
12023 the function entry state, which makes the offset be 1 word. */
12025 {
12028 {
12036 }
12037 }
12038 }
12040 /* Emit code to restore saved registers using POP insns. */
12042 static void
12044 {
12050 }
12052 /* Emit code and notes for the LEAVE instruction. */
12054 static void
12056 {
12068 {
12076 }
12079 }
12081 /* Emit code to restore saved registers using MOV insns.
12082 First register is restored from CFA - CFA_OFFSET. */
12083 static void
12086 {
12092 {
12094 rtx mem;
12102 {
12103 /* Previously we'd represented the CFA as an expression
12104 like *(%ebp - 8). We've just popped that value from
12105 the stack, which means we need to reset the CFA to
12106 the drap register. This will remain until we restore
12107 the stack pointer. */
12111 /* This means that the DRAP register is valid for addressing. */
12113 }
12114 else
12118 }
12119 }
12121 /* Emit code to restore saved registers using MOV insns.
12122 First register is restored from CFA - CFA_OFFSET. */
12123 static void
12126 {
12131 {
12133 rtx mem;
12143 }
12144 }
12146 /* Restore function stack, frame, and registers. */
12148 void
12150 {
12166 /* The FP must be valid if the frame pointer is present. */
12171 /* We must have *some* valid pointer to the stack frame. */
12174 /* The DRAP is never valid at this point. */
12177 /* See the comment about red zone and frame
12178 pointer usage in ix86_expand_prologue. */
12185 /* Determine the CFA offset of the end of the red-zone. */
12188 {
12189 /* The red-zone begins below the return address. */
12192 /* When the register save area is in the aligned portion of
12193 the stack, determine the maximum runtime displacement that
12194 matches up with the aligned frame. */
12198 }
12200 /* Special care must be taken for the normal return case of a function
12201 using eh_return: the eax and edx registers are marked as saved, but
12202 not restored along this path. Adjust the save location to match. */
12206 /* EH_RETURN requires the use of moves to function properly. */
12209 /* SEH requires the use of pops to identify the epilogue. */
12212 /* If we're only restoring one register and sp is not valid then
12213 using a move instruction to restore the register since it's
12214 less work than reloading sp and popping the register. */
12227 && TARGET_USE_LEAVE
12231 else
12235 {
12236 /* Ensure that the entire register save area is addressable via
12237 the stack pointer, if we will restore via sp. */
12242 {
12246 style,
12248 }
12249 }
12251 /* If there are any SSE registers to restore, then we have to do it
12252 via moves, since there's obviously no pop for SSE regs. */
12258 {
12259 rtx t;
12264 /* eh_return epilogues need %ecx added to the stack pointer. */
12266 {
12270 /* Stack align doesn't work with eh_return. */
12272 /* Neither does regparm nested functions. */
12276 {
12284 /* Note that we use SA as a temporary CFA, as the return
12285 address is at the proper place relative to it. We
12286 pretend this happens at the FP restore insn because
12287 prior to this insn the FP would be stored at the wrong
12288 offset relative to SA, and after this insn we have no
12289 other reasonable register to use for the CFA. We don't
12290 bother resetting the CFA to the SP for the duration of
12291 the return insn. */
12304 }
12305 else
12306 {
12314 {
12318 UNITS_PER_WORD));
12320 }
12321 }
12324 }
12325 }
12326 else
12327 {
12328 /* SEH requires that the function end with (1) a stack adjustment
12329 if necessary, (2) a sequence of pops, and (3) a return or
12330 jump instruction. Prevent insns from the function body from
12331 being scheduled into this sequence. */
12333 {
12334 /* Prevent a catch region from being adjacent to the standard
12335 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12336 several other flags that would be interesting to test are
12337 not yet set up. */
12340 else
12342 }
12344 /* First step is to deallocate the stack frame so that we can
12345 pop the registers. Also do it on SEH target for very large
12346 frame as the emitted instructions aren't allowed by the ABI in
12347 epilogues. */
12349 || (TARGET_SEH
12352 {
12357 }
12359 {
12363 style,
12365 }
12368 }
12370 /* If we used a stack pointer and haven't already got rid of it,
12371 then do so now. */
12373 {
12374 /* If the stack pointer is valid and pointing at the frame
12375 pointer store address, then we only need a pop. */
12378 /* Leave results in shorter dependency chains on CPUs that are
12379 able to grok it fast. */
12384 else
12385 {
12387 hard_frame_pointer_rtx,
12390 }
12391 }
12394 {
12422 }
12424 /* At this point the stack pointer must be valid, and we must have
12425 restored all of the registers. We may not have deallocated the
12426 entire stack frame. We've delayed this until now because it may
12427 be possible to merge the local stack deallocation with the
12428 deallocation forced by ix86_static_chain_on_stack. */
12433 {
12437 }
12438 else
12441 /* Sibcall epilogues don't want a return instruction. */
12443 {
12446 }
12449 {
12452 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12453 address, do explicit add, and jump indirectly to the caller. */
12456 {
12460 /* There is no "pascal" calling convention in any 64bit ABI. */
12476 }
12477 else
12479 }
12480 else
12483 /* Restore the state back to the state from the prologue,
12484 so that it's correct for the next epilogue. */
12486 }
12488 /* Reset from the function's potential modifications. */
12490 static void
12492 {
12496 #if TARGET_MACHO
12497 /* Mach-O doesn't support labels at the end of objects, so if
12498 it looks like we might want one, insert a NOP. */
12499 {
12505 {
12506 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12507 notes only, instead set their CODE_LABEL_NUMBER to -1,
12508 otherwise there would be code generation differences
12509 in between -g and -g0. */
12513 }
12523 }
12524 #endif
12526 }
12528 /* Return a scratch register to use in the split stack prologue. The
12529 split stack prologue is used for -fsplit-stack. It is the first
12530 instructions in the function, even before the regular prologue.
12531 The scratch register can be any caller-saved register which is not
12532 used for parameters or for the static chain. */
12534 static unsigned int
12536 {
12539 else
12540 {
12553 {
12555 {
12559 }
12561 }
12563 {
12567 }
12569 {
12572 else
12573 {
12575 {
12579 }
12581 }
12582 }
12583 else
12584 {
12585 /* FIXME: We could make this work by pushing a register
12586 around the addition and comparison. */
12589 }
12590 }
12591 }
12593 /* A SYMBOL_REF for the function which allocates new stackspace for
12594 -fsplit-stack. */
12598 /* A SYMBOL_REF for the more stack function when using the large
12599 model. */
12603 /* Handle -fsplit-stack. These are the first instructions in the
12604 function, even before the regular prologue. */
12606 void
12608 {
12610 HOST_WIDE_INT allocate;
12616 rtx fn;
12624 /* This is the label we will branch to if we have enough stack
12625 space. We expect the basic block reordering pass to reverse this
12626 branch if optimizing, so that we branch in the unlikely case. */
12629 /* We need to compare the stack pointer minus the frame size with
12630 the stack boundary in the TCB. The stack boundary always gives
12631 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12632 can compare directly. Otherwise we need to do an addition. */
12635 UNSPEC_STACK_CHECK);
12640 else
12641 {
12643 rtx offset;
12645 /* We need a scratch register to hold the stack pointer minus
12646 the required frame size. Since this is the very start of the
12647 function, the scratch register can be any caller-saved
12648 register which is not used for parameters. */
12655 {
12656 /* We don't use ix86_gen_add3 in this case because it will
12657 want to split to lea, but when not optimizing the insn
12658 will not be split after this point. */
12661 offset)));
12662 }
12663 else
12664 {
12667 stack_pointer_rtx));
12668 }
12670 }
12676 /* Mark the jump as very likely to be taken. */
12681 {
12684 }
12687 /* Get more stack space. We pass in the desired stack space and the
12688 size of the arguments to copy to the new stack. In 32-bit mode
12689 we push the parameters; __morestack will return on a new stack
12690 anyhow. In 64-bit mode we pass the parameters in r10 and
12691 r11. */
12696 {
12702 /* If this function uses a static chain, it will be in %r10.
12703 Preserve it across the call to __morestack. */
12705 {
12706 rtx rax;
12711 }
12715 {
12716 HOST_WIDE_INT argval;
12719 /* When using the large model we need to load the address
12720 into a register, and we've run out of registers. So we
12721 switch to a different calling convention, and we call a
12722 different function: __morestack_large. We pass the
12723 argument size in the upper 32 bits of r10 and pass the
12724 frame size in the lower 32 bits. */
12729 {
12730 split_stack_fn_large =
12733 }
12735 {
12737 rtx x;
12746 UNSPEC_GOT);
12752 }
12753 else
12760 }
12761 else
12762 {
12766 }
12769 }
12770 else
12771 {
12774 }
12780 /* In order to make call/return prediction work right, we now need
12781 to execute a return instruction. See
12782 libgcc/config/i386/morestack.S for the details on how this works.
12784 For flow purposes gcc must not see this as a return
12785 instruction--we need control flow to continue at the subsequent
12786 label. Therefore, we use an unspec. */
12790 /* If we are in 64-bit mode and this function uses a static chain,
12791 we saved %r10 in %rax before calling _morestack. */
12796 /* If this function calls va_start, we need to store a pointer to
12797 the arguments on the old stack, because they may not have been
12798 all copied to the new stack. At this point the old stack can be
12799 found at the frame pointer value used by __morestack, because
12800 __morestack has set that up before calling back to us. Here we
12801 store that pointer in a scratch register, and in
12802 ix86_expand_prologue we store the scratch register in a stack
12803 slot. */
12805 {
12807 rtx frame_reg;
12814 /* 64-bit:
12815 fp -> old fp value
12816 return address within this function
12817 return address of caller of this function
12818 stack arguments
12819 So we add three words to get to the stack arguments.
12821 32-bit:
12822 fp -> old fp value
12823 return address within this function
12824 first argument to __morestack
12825 second argument to __morestack
12826 return address of caller of this function
12827 stack arguments
12828 So we add five words to get to the stack arguments.
12829 */
12840 }
12845 /* If this function calls va_start, we now have to set the scratch
12846 register for the case where we do not call __morestack. In this
12847 case we need to set it based on the stack pointer. */
12849 {
12856 }
12857 }
12859 /* We may have to tell the dataflow pass that the split stack prologue
12860 is initializing a scratch register. */
12862 static void
12864 {
12866 {
12869 }
12870 }
12871 \f
12872 /* Extract the parts of an RTL expression that is a valid memory address
12873 for an instruction. Return 0 if the structure of the address is
12874 grossly off. Return -1 if the address contains ASHIFT, so it is not
12875 strictly valid, but still used for computing length of lea instruction. */
12877 int
12879 {
12884 rtx tmp;
12888 /* Allow zero-extended SImode addresses,
12889 they will be emitted with addr32 prefix. */
12891 {
12894 {
12898 }
12901 {
12908 }
12909 }
12911 /* Allow SImode subregs of DImode addresses,
12912 they will be emitted with addr32 prefix. */
12914 {
12917 {
12921 }
12922 }
12927 {
12930 else
12932 }
12934 {
12939 do
12940 {
12945 }
12952 {
12955 {
12980 /* FALLTHRU */
12984 && TARGET_TLS_DIRECT_SEG_REFS
12987 else
12994 /* FALLTHRU */
13001 else
13016 }
13017 }
13018 }
13020 {
13023 }
13025 {
13026 /* We're called for lea too, which implements ashift on occasion. */
13036 }
13037 else
13041 {
13043 ;
13046 ;
13047 else
13049 }
13051 /* Extract the integral value of scale. */
13053 {
13057 }
13062 /* Avoid useless 0 displacement. */
13066 /* Allow arg pointer and stack pointer as index if there is not scaling. */
13071 {
13074 }
13076 /* Special case: %ebp cannot be encoded as a base without a displacement.
13077 Similarly %r13. */
13079 && base_reg
13088 /* Special case: on K6, [%esi] makes the instruction vector decoded.
13089 Avoid this by transforming to [%esi+0].
13090 Reload calls address legitimization without cfun defined, so we need
13091 to test cfun for being non-NULL. */
13097 /* Special case: encode reg+reg instead of reg*2. */
13101 /* Special case: scaling cannot be encoded without base or displacement. */
13112 }
13113 \f
13114 /* Return cost of the memory address x.
13115 For i386, it is better to use a complex address than let gcc copy
13116 the address into a reg and make a new pseudo. But not if the address
13117 requires to two regs - that would mean more pseudos with longer
13118 lifetimes. */
13119 static int
13121 {
13133 /* Attempt to minimize number of registers in the address by increasing
13134 address cost for each used register. We don't increase address cost
13135 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
13136 is not invariant itself it most likely means that base or index is not
13137 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
13138 which is not profitable for x86. */
13142 || !pic_offset_table_rtx
13145 cost++;
13150 || !pic_offset_table_rtx
13153 cost++;
13155 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
13156 since it's predecode logic can't detect the length of instructions
13157 and it degenerates to vector decoded. Increase cost of such
13158 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
13159 to split such addresses or even refuse such addresses at all.
13161 Following addressing modes are affected:
13162 [base+scale*index]
13163 [scale*index+disp]
13164 [base+index]
13166 The first and last case may be avoidable by explicitly coding the zero in
13167 memory address, but I don't have AMD-K6 machine handy to check this
13168 theory. */
13177 }
13178 \f
13179 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
13180 this is used for to form addresses to local data when -fPIC is in
13181 use. */
13183 static bool
13185 {
13188 }
13190 /* Determine if a given RTX is a valid constant. We already know this
13191 satisfies CONSTANT_P. */
13193 static bool
13195 {
13196 /* Pointer bounds constants are not valid. */
13201 {
13206 {
13210 }
13215 /* Only some unspecs are valid as "constants". */
13218 {
13234 }
13236 /* We must have drilled down to a symbol. */
13241 /* FALLTHRU */
13244 /* TLS symbols are never valid. */
13248 /* DLLIMPORT symbols are never valid. */
13253 #if TARGET_MACHO
13254 /* mdynamic-no-pic */
13257 #endif
13271 }
13273 /* Otherwise we handle everything else in the move patterns. */
13275 }
13277 /* Determine if it's legal to put X into the constant pool. This
13278 is not possible for the address of thread-local symbols, which
13279 is checked above. */
13281 static bool
13283 {
13284 /* We can always put integral constants and vectors in memory. */
13286 {
13295 }
13297 }
13299 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13300 otherwise zero. */
13302 static bool
13304 {
13310 }
13313 /* Nonzero if the constant value X is a legitimate general operand
13314 when generating PIC code. It is given that flag_pic is on and
13315 that X satisfies CONSTANT_P. */
13317 bool
13319 {
13320 rtx inner;
13323 {
13330 /* Only some unspecs are valid as "constants". */
13333 {
13346 }
13347 /* FALLTHRU */
13355 }
13356 }
13358 /* Determine if a given CONST RTX is a valid memory displacement
13359 in PIC mode. */
13361 bool
13363 {
13366 /* In 64bit mode we can allow direct addresses of symbols and labels
13367 when they are not dynamic symbols. */
13369 {
13373 {
13397 /* FALLTHRU */
13400 /* TLS references should always be enclosed in UNSPEC.
13401 The dllimported symbol needs always to be resolved. */
13407 {
13415 /* Function-symbols need to be resolved only for
13416 large-model.
13417 For the small-model we don't need to resolve anything
13418 here. */
13423 /* Non-external symbols don't need to be resolved for
13424 large, and medium-model. */
13429 }
13432 || (HAVE_LD_PIE_COPYRELOC
13433 && flag_pie
13442 }
13443 }
13449 {
13450 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13451 of GOT tables. We should not need these anyway. */
13463 }
13467 {
13472 }
13481 {
13485 /* We need to check for both symbols and labels because VxWorks loads
13486 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13487 details. */
13491 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13492 While ABI specify also 32bit relocation but we don't produce it in
13493 small PIC model at all. */
13515 }
13518 }
13520 /* Determine if op is suitable RTX for an address register.
13521 Return naked register if a register or a register subreg is
13522 found, otherwise return NULL_RTX. */
13524 static rtx
13526 {
13529 /* Only SImode or DImode registers can form the address. */
13536 {
13544 /* Don't allow SUBREGs that span more than a word. It can
13545 lead to spill failures when the register is one word out
13546 of a two word structure. */
13550 /* Allow only SUBREGs of non-eliminable hard registers. */
13553 }
13555 /* Op is not a register. */
13557 }
13559 /* Recognizes RTL expressions that are valid memory addresses for an
13560 instruction. The MODE argument is the machine mode for the MEM
13561 expression that wants to use this address.
13563 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13564 convert common non-canonical forms to canonical form so that they will
13565 be recognized. */
13567 static bool
13569 {
13572 HOST_WIDE_INT scale;
13576 /* Decomposition failed. */
13585 /* Validate base register. */
13587 {
13595 /* Base is not valid. */
13597 }
13599 /* Validate index register. */
13601 {
13609 /* Index is not valid. */
13611 }
13613 /* Index and base should have the same mode. */
13618 /* Address override works only on the (%reg) part of %fs:(%reg). */
13624 /* Validate scale factor. */
13626 {
13628 /* Scale without index. */
13632 /* Scale is not a valid multiplier. */
13634 }
13636 /* Validate displacement. */
13638 {
13643 {
13644 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13645 used. While ABI specify also 32bit relocations, we don't produce
13646 them at all and use IP relative instead. */
13653 /* 64bit address unspec. */
13673 /* Invalid address unspec. */
13675 }
13678 && (flag_pic
13679 || (TARGET_MACHO
13680 #if TARGET_MACHO
13681 && MACHOPIC_INDIRECT
13683 #endif
13684 )))
13685 {
13687 is_legitimate_pic:
13689 {
13690 /* foo@dtpoff(%rX) is ok. */
13697 /* Non-constant pic memory reference. */
13699 }
13702 /* Displacement is an invalid pic construct. */
13704 #if TARGET_MACHO
13707 /* displacment must be referenced via non_lazy_pointer */
13709 #endif
13711 /* This code used to verify that a symbolic pic displacement
13712 includes the pic_offset_table_rtx register.
13714 While this is good idea, unfortunately these constructs may
13715 be created by "adds using lea" optimization for incorrect
13716 code like:
13718 int a;
13719 int foo(int i)
13720 {
13721 return *(&a+i);
13722 }
13724 This code is nonsensical, but results in addressing
13725 GOT table with pic_offset_table_rtx base. We can't
13726 just refuse it easily, since it gets matched by
13727 "addsi3" pattern, that later gets split to lea in the
13728 case output register differs from input. While this
13729 can be handled by separate addsi pattern for this case
13730 that never results in lea, this seems to be easier and
13731 correct fix for crash to disable this test. */
13732 }
13739 /* Displacement is not constant. */
13743 /* Displacement is out of range. */
13745 /* In x32 mode, constant addresses are sign extended to 64bit, so
13746 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13751 }
13753 /* Everything looks valid. */
13755 }
13757 /* Determine if a given RTX is a valid constant address. */
13759 bool
13761 {
13763 }
13764 \f
13765 /* Return a unique alias set for the GOT. */
13767 static alias_set_type
13769 {
13774 }
13776 /* Return a legitimate reference for ORIG (an address) using the
13777 register REG. If REG is 0, a new pseudo is generated.
13779 There are two types of references that must be handled:
13781 1. Global data references must load the address from the GOT, via
13782 the PIC reg. An insn is emitted to do this load, and the reg is
13783 returned.
13785 2. Static data references, constant pool addresses, and code labels
13786 compute the address as an offset from the GOT, whose base is in
13787 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13788 differentiate them from global data objects. The returned
13789 address is the PIC reg + an unspec constant.
13791 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13792 reg also appears in the address. */
13794 static rtx
13796 {
13800 #if TARGET_MACHO
13802 {
13805 /* Use the generic Mach-O PIC machinery. */
13807 }
13808 #endif
13811 {
13815 }
13821 {
13822 rtx tmpreg;
13823 /* This symbol may be referenced via a displacement from the PIC
13824 base address (@GOTOFF). */
13829 {
13831 UNSPEC_GOTOFF);
13833 }
13834 else
13839 else
13844 {
13848 }
13849 else
13851 }
13853 {
13854 /* This symbol may be referenced via a displacement from the PIC
13855 base address (@GOTOFF). */
13860 {
13862 UNSPEC_GOTOFF);
13864 }
13865 else
13871 {
13874 }
13875 }
13877 /* We can't use @GOTOFF for text labels on VxWorks;
13878 see gotoff_operand. */
13880 {
13885 /* For x64 PE-COFF there is no GOT table. So we use address
13886 directly. */
13888 {
13896 }
13898 {
13906 /* Use directly gen_movsi, otherwise the address is loaded
13907 into register for CSE. We don't want to CSE this addresses,
13908 instead we CSE addresses from the GOT table, so skip this. */
13911 }
13912 else
13913 {
13914 /* This symbol must be referenced via a load from the
13915 Global Offset Table (@GOT). */
13929 }
13930 }
13931 else
13932 {
13935 {
13937 {
13940 }
13941 else
13943 }
13945 {
13948 /* We must match stuff we generate before. Assume the only
13949 unspecs that can get here are ours. Not that we could do
13950 anything with them anyway.... */
13956 }
13958 {
13961 /* Check first to see if this is a constant offset from a @GOTOFF
13962 symbol reference. */
13965 {
13967 {
13969 UNSPEC_GOTOFF);
13975 {
13978 }
13979 }
13980 else
13981 {
13984 {
13988 }
13989 }
13990 }
13991 else
13992 {
13995 new_rtx
13999 {
14002 {
14005 new_rtx
14007 }
14008 else
14010 }
14011 else
14012 {
14013 /* For %rip addressing, we have to use just disp32, not
14014 base nor index. */
14021 {
14024 }
14026 }
14027 }
14028 }
14029 }
14031 }
14032 \f
14033 /* Load the thread pointer. If TO_REG is true, force it into a register. */
14035 static rtx
14037 {
14041 {
14046 }
14052 }
14054 /* Construct the SYMBOL_REF for the tls_get_addr function. */
14058 static rtx
14060 {
14062 {
14068 }
14071 {
14073 UNSPEC_PLTOFF);
14076 }
14079 }
14081 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
14085 rtx
14087 {
14089 {
14090 ix86_tls_module_base_symbol
14095 }
14098 }
14100 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
14101 false if we expect this to be used for a memory address and true if
14102 we expect to load the address into a register. */
14104 static rtx
14106 {
14112 /* Fall back to global dynamic model if tool chain cannot support local
14113 dynamic. */
14120 {
14125 {
14128 else
14129 {
14132 }
14133 }
14136 {
14139 else
14149 }
14150 else
14151 {
14155 {
14160 emit_call_insn
14170 }
14171 else
14173 }
14180 {
14183 else
14184 {
14187 }
14188 }
14191 {
14196 else
14202 }
14203 else
14204 {
14208 {
14211 rtx eqv;
14214 emit_call_insn
14219 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14220 share the LD_BASE result with other LD model accesses. */
14222 UNSPEC_TLS_LD_BASE);
14226 }
14227 else
14229 }
14237 {
14244 }
14249 {
14251 {
14252 /* The Sun linker took the AMD64 TLS spec literally
14253 and can only handle %rax as destination of the
14254 initial executable code sequence. */
14259 }
14261 /* Generate DImode references to avoid %fs:(%reg32)
14262 problems and linker IE->LE relaxation bug. */
14266 }
14268 {
14271 }
14273 {
14277 }
14278 else
14279 {
14282 }
14292 {
14297 }
14298 else
14299 {
14303 }
14313 {
14317 }
14318 else
14319 {
14323 }
14328 }
14331 }
14333 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14334 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14335 unique refptr-DECL symbol corresponding to symbol DECL. */
14338 {
14342 {
14344 }
14346 static int
14348 {
14350 }
14351 };
14355 static tree
14357 {
14363 tree to;
14364 rtx rtl;
14391 else
14404 {
14406 #ifdef SUB_TARGET_RECORD_STUB
14408 #endif
14409 }
14418 }
14420 /* Expand SYMBOL into its corresponding far-addresse symbol.
14421 WANT_REG is true if we require the result be a register. */
14423 static rtx
14425 {
14426 tree imp_decl;
14427 rtx x;
14436 }
14438 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14439 true if we require the result be a register. */
14441 static rtx
14443 {
14444 tree imp_decl;
14445 rtx x;
14454 }
14456 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14457 is true if we require the result be a register. */
14459 static rtx
14461 {
14466 {
14473 {
14476 }
14477 }
14493 {
14496 }
14498 }
14500 /* Try machine-dependent ways of modifying an illegitimate address
14501 to be legitimate. If we find one, return the new, valid address.
14502 This macro is used in only one place: `memory_address' in explow.c.
14504 OLDX is the address as it was before break_out_memory_refs was called.
14505 In some cases it is useful to look at this to decide what needs to be done.
14507 It is always safe for this macro to do nothing. It exists to recognize
14508 opportunities to optimize the output.
14510 For the 80386, we handle X+REG by loading X into a register R and
14511 using R+REG. R will go in a general reg and indexing will be used.
14512 However, if REG is a broken-out memory address or multiplication,
14513 nothing needs to be done because REG can certainly go in a general reg.
14515 When -fpic is used, special handling is needed for symbolic references.
14516 See comments by legitimize_pic_address in i386.c for details. */
14518 static rtx
14520 {
14531 {
14535 }
14538 {
14542 }
14547 #if TARGET_MACHO
14550 #endif
14552 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14556 {
14561 }
14564 {
14565 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14570 {
14576 }
14581 {
14587 }
14589 /* Put multiply first if it isn't already. */
14591 {
14594 }
14596 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14597 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14598 created by virtual register instantiation, register elimination, and
14599 similar optimizations. */
14601 {
14607 }
14609 /* Canonicalize
14610 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14611 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14616 {
14617 rtx constant;
14621 {
14624 }
14626 {
14629 }
14630 else
14634 {
14641 }
14642 }
14648 {
14651 }
14654 {
14657 }
14665 {
14668 }
14674 {
14678 {
14681 }
14685 }
14688 {
14692 {
14695 }
14699 }
14700 }
14703 }
14704 \f
14705 /* Print an integer constant expression in assembler syntax. Addition
14706 and subtraction are the only arithmetic that may appear in these
14707 expressions. FILE is the stdio stream to write to, X is the rtx, and
14708 CODE is the operand print code from the output string. */
14710 static void
14712 {
14716 {
14725 else
14726 {
14729 /* Mark the decl as referenced so that cgraph will
14730 output the function. */
14734 #if TARGET_MACHO
14738 #endif
14740 }
14748 /* FALLTHRU */
14759 /* This used to output parentheses around the expression,
14760 but that does not work on the 386 (either ATT or BSD assembler). */
14765 /* We can't handle floating point constants;
14766 TARGET_PRINT_OPERAND must handle them. */
14771 /* Some assemblers need integer constants to appear first. */
14773 {
14777 }
14778 else
14779 {
14784 }
14799 {
14803 }
14808 {
14827 /* FIXME: This might be @TPOFF in Sun ld too. */
14836 else
14846 else
14852 #if TARGET_MACHO
14857 #endif
14861 }
14866 }
14867 }
14869 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14870 We need to emit DTP-relative relocations. */
14872 static void ATTRIBUTE_UNUSED
14874 {
14879 {
14887 }
14888 }
14890 /* Return true if X is a representation of the PIC register. This copes
14891 with calls from ix86_find_base_term, where the register might have
14892 been replaced by a cselib value. */
14894 static bool
14896 {
14903 {
14911 }
14912 else
14914 }
14916 /* Helper function for ix86_delegitimize_address.
14917 Attempt to delegitimize TLS local-exec accesses. */
14919 static rtx
14921 {
14946 {
14951 }
14957 }
14959 /* In the name of slightly smaller debug output, and to cater to
14960 general assembler lossage, recognize PIC+GOTOFF and turn it back
14961 into a direct symbol reference.
14963 On Darwin, this is necessary to avoid a crash, because Darwin
14964 has a different PIC label for each routine but the DWARF debugging
14965 information is not associated with any particular routine, so it's
14966 necessary to remove references to the PIC label from RTL stored by
14967 the DWARF output code. */
14969 static rtx
14971 {
14973 /* addend is NULL or some rtx if x is something+GOTOFF where
14974 something doesn't include the PIC register. */
14976 /* reg_addend is NULL or a multiple of some register. */
14978 /* const_addend is NULL or a const_int. */
14980 /* This is the result, or NULL. */
14989 {
14996 {
15002 }
15009 {
15012 {
15017 }
15019 }
15024 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
15025 and -mcmodel=medium -fpic. */
15026 }
15033 /* %ebx + GOT/GOTOFF */
15034 ;
15036 {
15037 /* %ebx + %reg * scale + GOT/GOTOFF */
15043 else
15044 {
15047 }
15048 }
15049 else
15055 {
15058 }
15079 {
15080 /* If the rest of original X doesn't involve the PIC register, add
15081 addend and subtract pic_offset_table_rtx. This can happen e.g.
15082 for code like:
15083 leal (%ebx, %ecx, 4), %ecx
15084 ...
15085 movl foo@GOTOFF(%ecx), %edx
15086 in which case we return (%ecx - %ebx) + foo
15087 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
15088 and reload has completed. */
15092 pic_offset_table_rtx),
15093 result);
15095 {
15099 }
15100 else
15102 }
15104 {
15108 }
15110 }
15112 /* If X is a machine specific address (i.e. a symbol or label being
15113 referenced as a displacement from the GOT implemented using an
15114 UNSPEC), then return the base term. Otherwise return X. */
15116 rtx
15118 {
15119 rtx term;
15122 {
15135 }
15138 }
15139 \f
15140 static void
15143 {
15147 {
15150 }
15155 {
15158 {
15177 }
15181 {
15200 }
15207 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15208 Those same assemblers have the same but opposite lossage on cmov. */
15211 else
15216 {
15229 }
15236 else
15241 {
15254 }
15261 else
15271 else
15282 }
15284 }
15286 /* Print the name of register X to FILE based on its machine mode and number.
15287 If CODE is 'w', pretend the mode is HImode.
15288 If CODE is 'b', pretend the mode is QImode.
15289 If CODE is 'k', pretend the mode is SImode.
15290 If CODE is 'q', pretend the mode is DImode.
15291 If CODE is 'x', pretend the mode is V4SFmode.
15292 If CODE is 't', pretend the mode is V8SFmode.
15293 If CODE is 'g', pretend the mode is V16SFmode.
15294 If CODE is 'h', pretend the reg is the 'high' byte register.
15295 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15296 If CODE is 'd', duplicate the operand for AVX instruction.
15297 */
15299 void
15301 {
15311 {
15315 }
15318 {
15321 }
15339 else
15353 {
15361 normal:
15377 {
15382 }
15386 }
15390 /* Irritatingly, AMD extended registers use
15391 different naming convention: "r%d[bwd]" */
15393 {
15396 {
15410 /* no suffix */
15415 }
15417 }
15420 {
15423 else
15425 }
15426 }
15428 /* Meaning of CODE:
15429 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15430 C -- print opcode suffix for set/cmov insn.
15431 c -- like C, but print reversed condition
15432 F,f -- likewise, but for floating-point.
15433 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15434 otherwise nothing
15435 R -- print embeded rounding and sae.
15436 r -- print only sae.
15437 z -- print the opcode suffix for the size of the current operand.
15438 Z -- likewise, with special suffixes for x87 instructions.
15439 * -- print a star (in certain assembler syntax)
15440 A -- print an absolute memory reference.
15441 E -- print address with DImode register names if TARGET_64BIT.
15442 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15443 s -- print a shift double count, followed by the assemblers argument
15444 delimiter.
15445 b -- print the QImode name of the register for the indicated operand.
15446 %b0 would print %al if operands[0] is reg 0.
15447 w -- likewise, print the HImode name of the register.
15448 k -- likewise, print the SImode name of the register.
15449 q -- likewise, print the DImode name of the register.
15450 x -- likewise, print the V4SFmode name of the register.
15451 t -- likewise, print the V8SFmode name of the register.
15452 g -- likewise, print the V16SFmode name of the register.
15453 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15454 y -- print "st(0)" instead of "st" as a register.
15455 d -- print duplicated register operand for AVX instruction.
15456 D -- print condition for SSE cmp instruction.
15457 P -- if PIC, print an @PLT suffix.
15458 p -- print raw symbol name.
15459 X -- don't print any sort of PIC '@' suffix for a symbol.
15460 & -- print some in-use local-dynamic symbol name.
15461 H -- print a memory address offset by 8; used for sse high-parts
15462 Y -- print condition for XOP pcom* instruction.
15463 + -- print a branch hint as 'cs' or 'ds' prefix
15464 ; -- print a semicolon (after prefixes due to bug in older gas).
15465 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15466 @ -- print a segment register of thread base pointer load
15467 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15468 ! -- print MPX prefix for jxx/call/ret instructions if required.
15469 */
15471 void
15473 {
15475 {
15477 {
15480 {
15486 /* Intel syntax. For absolute addresses, registers should not
15487 be surrounded by braces. */
15489 {
15494 }
15499 }
15505 /* Wrap address in an UNSPEC to declare special handling. */
15543 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15548 {
15562 output_operand_lossage
15565 }
15568 #endif
15573 {
15574 /* Opcodes don't get size suffixes if using Intel opcodes. */
15579 {
15597 output_operand_lossage
15600 }
15601 }
15604 warning
15606 /* FALLTHRU */
15609 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15614 {
15616 {
15618 #ifdef HAVE_AS_IX86_FILDS
15620 #endif
15628 #ifdef HAVE_AS_IX86_FILDQ
15630 #else
15632 #endif
15637 }
15638 }
15640 {
15641 /* 387 opcodes don't get size suffixes
15642 if the operands are registers. */
15647 {
15663 }
15664 }
15665 else
15666 {
15667 output_operand_lossage
15670 }
15672 output_operand_lossage
15693 {
15696 }
15701 {
15752 }
15756 /* Little bit of braindamage here. The SSE compare instructions
15757 does use completely different names for the comparisons that the
15758 fp conditional moves. */
15760 {
15763 {
15766 }
15772 {
15775 }
15781 {
15784 }
15793 {
15796 }
15802 {
15805 }
15811 {
15814 }
15825 }
15830 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15833 #endif
15838 {
15842 }
15846 file);
15851 {
15855 }
15856 /* It doesn't actually matter what mode we use here, as we're
15857 only going to use this for printing. */
15859 /* Output 'qword ptr' for intel assembler dialect. */
15868 #ifdef HAVE_AS_IX86_HLE
15870 #else
15872 #endif
15874 #ifdef HAVE_AS_IX86_HLE
15876 #else
15878 #endif
15879 /* We do not want to print value of the operand. */
15908 {
15923 }
15936 {
15941 else
15944 }
15947 {
15948 rtx x;
15957 {
15962 {
15964 bool cputaken
15967 /* Emit hints only in the case default branch prediction
15968 heuristics would fail. */
15970 {
15971 /* We use 3e (DS) prefix for taken branches and
15972 2e (CS) prefix for not taken branches. */
15975 else
15977 }
15978 }
15979 }
15981 }
15984 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15986 #endif
15993 /* The kernel uses a different segment register for performance
15994 reasons; a system call would not have to trash the userspace
15995 segment register, which would be expensive. */
15998 else
16018 }
16019 }
16025 {
16026 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
16029 {
16032 {
16041 else
16048 }
16050 /* Check for explicit size override (codes 'b', 'w', 'k',
16051 'q' and 'x') */
16065 }
16068 /* Avoid (%rip) for call operands. */
16074 else
16076 }
16079 {
16080 REAL_VALUE_TYPE r;
16088 /* Sign extend 32bit SFmode immediate to 8 bytes. */
16092 else
16094 }
16097 {
16098 REAL_VALUE_TYPE r;
16107 }
16109 /* These float cases don't actually occur as immediate operands. */
16111 {
16116 }
16118 else
16119 {
16120 /* We have patterns that allow zero sets of memory, for instance.
16121 In 64-bit mode, we should probably support all 8-byte vectors,
16122 since we can in fact encode that into an immediate. */
16124 {
16127 }
16130 {
16132 {
16135 }
16138 {
16141 else
16143 }
16144 }
16149 else
16151 }
16152 }
16154 static bool
16156 {
16159 }
16160 \f
16161 /* Print a memory operand whose address is ADDR. */
16163 static void
16165 {
16174 {
16181 }
16183 {
16187 }
16189 {
16193 {
16196 }
16199 }
16201 {
16206 }
16207 else
16218 {
16229 }
16231 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16233 {
16245 }
16247 {
16248 /* Displacement only requires special attention. */
16251 {
16255 }
16258 else
16260 }
16261 else
16262 {
16263 /* Print SImode register names to force addr32 prefix. */
16265 {
16266 #ifdef ENABLE_CHECKING
16269 {
16280 }
16281 #endif
16284 }
16286 && TARGET_X32
16287 && disp
16290 {
16291 /* X32 runs in 64-bit mode, where displacement, DISP, in
16292 address DISP(%r64), is encoded as 32-bit immediate sign-
16293 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16294 address is %r64 + 0xffffffffbffffd00. When %r64 <
16295 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16296 which is invalid for x32. The correct address is %r64
16297 - 0x40000300 == 0xf7ffdd64. To properly encode
16298 -0x40000300(%r64) for x32, we zero-extend negative
16299 displacement by forcing addr32 prefix which truncates
16300 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16301 zero-extend all negative displacements, including -1(%rsp).
16302 However, for small negative displacements, sign-extension
16303 won't cause overflow. We only zero-extend negative
16304 displacements if they < -16*1024*1024, which is also used
16305 to check legitimate address displacements for PIC. */
16307 }
16310 {
16312 {
16317 else
16319 }
16325 {
16330 }
16332 }
16333 else
16334 {
16338 {
16339 /* Pull out the offset of a symbol; print any symbol itself. */
16343 {
16347 }
16355 else
16357 }
16361 {
16364 {
16368 }
16369 }
16372 else
16376 {
16381 }
16383 }
16384 }
16385 }
16387 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16389 static bool
16391 {
16392 rtx op;
16399 {
16402 /* FIXME: This might be @TPOFF in Sun ld. */
16413 else
16425 else
16432 #if TARGET_MACHO
16438 #endif
16441 {
16446 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16448 #else
16450 #endif
16453 }
16458 }
16461 }
16462 \f
16463 /* Split one or more double-mode RTL references into pairs of half-mode
16464 references. The RTL can be REG, offsettable MEM, integer constant, or
16465 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16466 split and "num" is its length. lo_half and hi_half are output arrays
16467 that parallel "operands". */
16469 void
16472 {
16473 machine_mode half_mode;
16477 {
16486 }
16491 {
16494 /* simplify_subreg refuse to split volatile memory addresses,
16495 but we still have to handle it. */
16497 {
16500 }
16501 else
16502 {
16509 }
16510 }
16511 }
16512 \f
16513 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16514 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16515 is the expression of the binary operation. The output may either be
16516 emitted here, or returned to the caller, like all output_* functions.
16518 There is no guarantee that the operands are the same mode, as they
16519 might be within FLOAT or FLOAT_EXTEND expressions. */
16521 #ifndef SYSV386_COMPAT
16522 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16523 wants to fix the assemblers because that causes incompatibility
16524 with gcc. No-one wants to fix gcc because that causes
16525 incompatibility with assemblers... You can use the option of
16526 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16527 #define SYSV386_COMPAT 1
16528 #endif
16532 {
16538 #ifdef ENABLE_CHECKING
16539 /* Even if we do not want to check the inputs, this documents input
16540 constraints. Which helps in understanding the following code. */
16550 else
16552 #endif
16555 {
16560 else
16569 else
16578 else
16587 else
16594 }
16597 {
16599 {
16603 else
16605 }
16606 else
16607 {
16611 else
16613 }
16615 }
16619 {
16625 /* know operands[0] == operands[1]. */
16628 {
16631 }
16634 {
16636 /* How is it that we are storing to a dead operand[2]?
16637 Well, presumably operands[1] is dead too. We can't
16638 store the result to st(0) as st(0) gets popped on this
16639 instruction. Instead store to operands[2] (which I
16640 think has to be st(1)). st(1) will be popped later.
16641 gcc <= 2.8.1 didn't have this check and generated
16642 assembly code that the Unixware assembler rejected. */
16644 else
16647 }
16651 else
16658 {
16661 }
16664 {
16667 }
16670 {
16671 #if SYSV386_COMPAT
16672 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16673 derived assemblers, confusingly reverse the direction of
16674 the operation for fsub{r} and fdiv{r} when the
16675 destination register is not st(0). The Intel assembler
16676 doesn't have this brain damage. Read !SYSV386_COMPAT to
16677 figure out what the hardware really does. */
16680 else
16682 #else
16684 /* As above for fmul/fadd, we can't store to st(0). */
16686 else
16688 #endif
16690 }
16693 {
16694 #if SYSV386_COMPAT
16697 else
16699 #else
16702 else
16704 #endif
16706 }
16709 {
16712 else
16715 }
16717 {
16718 #if SYSV386_COMPAT
16720 #else
16722 #endif
16723 }
16724 else
16725 {
16726 #if SYSV386_COMPAT
16728 #else
16730 #endif
16731 }
16736 }
16740 }
16742 /* Check if a 256bit AVX register is referenced inside of EXP. */
16744 static bool
16746 {
16752 }
16754 /* Return needed mode for entity in optimize_mode_switching pass. */
16756 static int
16758 {
16760 {
16761 rtx link;
16763 /* Needed mode is set to AVX_U128_CLEAN if there are
16764 no 256bit modes used in function arguments. */
16766 link;
16768 {
16770 {
16775 }
16776 }
16779 }
16781 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16782 changes state only when a 256bit register is written to, but we need
16783 to prevent the compiler from moving optimal insertion point above
16784 eventual read from 256bit register. */
16791 }
16793 /* Return mode that i387 must be switched into
16794 prior to the execution of insn. */
16796 static int
16798 {
16801 /* The mode UNINITIALIZED is used to store control word after a
16802 function call or ASM pattern. The mode ANY specify that function
16803 has no requirements on the control word and make no changes in the
16804 bits we are interested in. */
16818 {
16841 }
16844 }
16846 /* Return mode that entity must be switched into
16847 prior to the execution of insn. */
16849 static int
16851 {
16853 {
16863 }
16865 }
16867 /* Check if a 256bit AVX register is referenced in stores. */
16869 static void
16871 {
16873 {
16876 }
16877 }
16879 /* Calculate mode of upper 128bit AVX registers after the insn. */
16881 static int
16883 {
16890 /* We know that state is clean after CALL insn if there are no
16891 256bit registers used in the function return register. */
16893 {
16898 }
16900 /* Otherwise, return current mode. Remember that if insn
16901 references AVX 256bit registers, the mode was already changed
16902 to DIRTY from MODE_NEEDED. */
16904 }
16906 /* Return the mode that an insn results in. */
16908 static int
16910 {
16912 {
16922 }
16923 }
16925 static int
16927 {
16928 tree arg;
16930 /* Entry mode is set to AVX_U128_DIRTY if there are
16931 256bit modes used in function arguments. */
16934 {
16939 }
16942 }
16944 /* Return a mode that ENTITY is assumed to be
16945 switched to at function entry. */
16947 static int
16949 {
16951 {
16961 }
16962 }
16964 static int
16966 {
16969 /* Exit mode is set to AVX_U128_DIRTY if there are
16970 256bit modes used in the function return register. */
16975 }
16977 /* Return a mode that ENTITY is assumed to be
16978 switched to at function exit. */
16980 static int
16982 {
16984 {
16994 }
16995 }
16997 static int
16999 {
17001 }
17003 /* Output code to initialize control word copies used by trunc?f?i and
17004 rounding patterns. CURRENT_MODE is set to current control word,
17005 while NEW_MODE is set to new control word. */
17007 static void
17009 {
17011 rtx new_mode;
17022 {
17024 {
17026 /* round toward zero (truncate) */
17032 /* round down toward -oo */
17039 /* round up toward +oo */
17046 /* mask precision exception for nearbyint() */
17053 }
17054 }
17055 else
17056 {
17058 {
17060 /* round toward zero (truncate) */
17066 /* round down toward -oo */
17072 /* round up toward +oo */
17078 /* mask precision exception for nearbyint() */
17085 }
17086 }
17092 }
17094 /* Emit vzeroupper. */
17096 void
17098 {
17101 /* Cancel automatic vzeroupper insertion if there are
17102 live call-saved SSE registers at the insertion point. */
17114 }
17116 /* Generate one or more insns to set ENTITY to MODE. */
17118 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
17119 is the set of hard registers live at the point where the insn(s)
17120 are to be inserted. */
17122 static void
17124 HARD_REG_SET regs_live)
17125 {
17127 {
17142 }
17143 }
17145 /* Output code for INSN to convert a float to a signed int. OPERANDS
17146 are the insn operands. The output may be [HSD]Imode and the input
17147 operand may be [SDX]Fmode. */
17151 {
17156 /* Jump through a hoop or two for DImode, since the hardware has no
17157 non-popping instruction. We used to do this a different way, but
17158 that was somewhat fragile and broke with post-reload splitters. */
17168 else
17169 {
17174 else
17178 }
17181 }
17183 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17184 have the values zero or one, indicates the ffreep insn's operand
17185 from the OPERANDS array. */
17189 {
17191 #ifdef HAVE_AS_IX86_FFREEP
17193 #else
17194 {
17204 }
17205 #endif
17208 }
17211 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17212 should be used. UNORDERED_P is true when fucom should be used. */
17216 {
17222 {
17225 }
17226 else
17227 {
17230 }
17233 {
17237 else
17239 else
17242 else
17244 }
17251 {
17253 {
17256 }
17257 else
17259 }
17262 && stack_top_dies
17265 {
17266 /* If both the top of the 387 stack dies, and the other operand
17267 is also a stack register that dies, then this must be a
17268 `fcompp' float compare */
17271 {
17272 /* There is no double popping fcomi variant. Fortunately,
17273 eflags is immune from the fstp's cc clobbering. */
17276 else
17279 }
17280 else
17281 {
17284 else
17286 }
17287 }
17288 else
17289 {
17290 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17293 {
17301 NULL,
17302 NULL,
17309 NULL,
17310 NULL,
17311 NULL,
17312 NULL
17313 };
17328 }
17329 }
17331 void
17333 {
17336 #ifdef ASM_QUAD
17339 #else
17341 #endif
17344 }
17346 void
17348 {
17351 #ifdef ASM_QUAD
17354 #else
17356 #endif
17357 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17363 #if TARGET_MACHO
17365 {
17369 }
17370 #endif
17371 else
17374 }
17375 \f
17376 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17377 for the target. */
17379 void
17381 {
17382 rtx tmp;
17384 /* We play register width games, which are only valid after reload. */
17387 /* Avoid HImode and its attendant prefix byte. */
17393 {
17396 }
17399 }
17401 /* X is an unchanging MEM. If it is a constant pool reference, return
17402 the constant pool rtx, else NULL. */
17404 rtx
17406 {
17413 }
17415 void
17417 {
17425 {
17426 rtx tmp;
17430 {
17436 }
17439 }
17443 {
17446 rtx tmp;
17451 else
17455 {
17462 }
17463 }
17467 {
17469 {
17470 #if TARGET_MACHO
17471 /* dynamic-no-pic */
17473 {
17480 }
17482 {
17486 }
17489 else
17490 {
17498 }
17499 /* dynamic-no-pic */
17500 #endif
17501 }
17502 else
17503 {
17507 {
17513 }
17514 }
17515 }
17516 else
17517 {
17528 /* Force large constants in 64bit compilation into register
17529 to get them CSEed. */
17540 {
17541 /* If we are loading a floating point constant to a register,
17542 force the value to memory now, since we'll get better code
17543 out the back end. */
17547 {
17552 }
17553 }
17554 }
17557 }
17559 void
17561 {
17568 /* Force constants other than zero into memory. We do not know how
17569 the instructions used to build constants modify the upper 64 bits
17570 of the register, once we have that information we may be able
17571 to handle some of them more efficiently. */
17580 /* We need to check memory alignment for SSE mode since attribute
17581 can make operands unaligned. */
17586 {
17589 /* ix86_expand_vector_move_misalign() does not like constants ... */
17595 /* ... nor both arguments in memory. */
17603 }
17605 /* Make operand1 a register if it isn't already. */
17609 {
17612 }
17615 }
17617 /* Split 32-byte AVX unaligned load and store if needed. */
17619 static void
17621 {
17622 rtx m;
17626 machine_mode mode;
17629 {
17650 }
17653 {
17656 {
17663 }
17664 /* Normal *mov<mode>_internal pattern will handle
17665 unaligned loads just fine if misaligned_operand
17666 is true, and without the UNSPEC it can be combined
17667 with arithmetic instructions. */
17670 else
17672 }
17674 {
17677 {
17682 }
17683 else
17685 }
17686 else
17688 }
17690 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17691 straight to ix86_expand_vector_move. */
17692 /* Code generation for scalar reg-reg moves of single and double precision data:
17693 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17694 movaps reg, reg
17695 else
17696 movss reg, reg
17697 if (x86_sse_partial_reg_dependency == true)
17698 movapd reg, reg
17699 else
17700 movsd reg, reg
17702 Code generation for scalar loads of double precision data:
17703 if (x86_sse_split_regs == true)
17704 movlpd mem, reg (gas syntax)
17705 else
17706 movsd mem, reg
17708 Code generation for unaligned packed loads of single precision data
17709 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17710 if (x86_sse_unaligned_move_optimal)
17711 movups mem, reg
17713 if (x86_sse_partial_reg_dependency == true)
17714 {
17715 xorps reg, reg
17716 movlps mem, reg
17717 movhps mem+8, reg
17718 }
17719 else
17720 {
17721 movlps mem, reg
17722 movhps mem+8, reg
17723 }
17725 Code generation for unaligned packed loads of double precision data
17726 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17727 if (x86_sse_unaligned_move_optimal)
17728 movupd mem, reg
17730 if (x86_sse_split_regs == true)
17731 {
17732 movlpd mem, reg
17733 movhpd mem+8, reg
17734 }
17735 else
17736 {
17737 movsd mem, reg
17738 movhpd mem+8, reg
17739 }
17740 */
17742 void
17744 {
17753 {
17755 {
17759 {
17761 {
17764 }
17765 else
17767 }
17769 /* FALLTHRU */
17773 {
17788 }
17794 else
17802 }
17805 }
17809 {
17811 {
17815 {
17817 {
17820 }
17821 else
17823 }
17825 /* FALLTHRU */
17835 }
17838 }
17841 {
17842 /* Normal *mov<mode>_internal pattern will handle
17843 unaligned loads just fine if misaligned_operand
17844 is true, and without the UNSPEC it can be combined
17845 with arithmetic instructions. */
17851 /* ??? If we have typed data, then it would appear that using
17852 movdqu is the only way to get unaligned data loaded with
17853 integer type. */
17855 {
17857 {
17860 }
17862 /* We will eventually emit movups based on insn attributes. */
17866 }
17868 {
17869 rtx zero;
17872 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17873 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17875 {
17876 /* We will eventually emit movups based on insn attributes. */
17879 }
17881 /* When SSE registers are split into halves, we can avoid
17882 writing to the top half twice. */
17884 {
17887 }
17888 else
17889 {
17890 /* ??? Not sure about the best option for the Intel chips.
17891 The following would seem to satisfy; the register is
17892 entirely cleared, breaking the dependency chain. We
17893 then store to the upper half, with a dependency depth
17894 of one. A rumor has it that Intel recommends two movsd
17895 followed by an unpacklpd, but this is unconfirmed. And
17896 given that the dependency depth of the unpacklpd would
17897 still be one, I'm not sure why this would be better. */
17899 }
17905 }
17906 else
17907 {
17908 rtx t;
17911 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17912 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17914 {
17916 {
17919 }
17926 }
17930 else
17935 else
17944 }
17945 }
17947 {
17949 {
17952 /* We will eventually emit movups based on insn attributes. */
17954 }
17956 {
17958 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17959 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17961 /* We will eventually emit movups based on insn attributes. */
17963 else
17964 {
17969 }
17970 }
17971 else
17972 {
17977 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17978 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17980 {
17983 }
17984 else
17985 {
17990 }
17991 }
17992 }
17993 else
17995 }
17997 /* Helper function of ix86_fixup_binary_operands to canonicalize
17998 operand order. Returns true if the operands should be swapped. */
18000 static bool
18002 rtx operands[])
18003 {
18008 /* If the operation is not commutative, we can't do anything. */
18012 /* Highest priority is that src1 should match dst. */
18018 /* Next highest priority is that immediate constants come second. */
18024 /* Lowest priority is that memory references should come second. */
18031 }
18034 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
18035 destination to use for the operation. If different from the true
18036 destination in operands[0], a copy operation will be required. */
18038 rtx
18040 rtx operands[])
18041 {
18046 /* Canonicalize operand order. */
18048 {
18049 /* It is invalid to swap operands of different modes. */
18053 }
18055 /* Both source operands cannot be in memory. */
18057 {
18058 /* Optimization: Only read from memory once. */
18060 {
18063 }
18066 else
18068 }
18070 /* If the destination is memory, and we do not have matching source
18071 operands, do things in registers. */
18075 /* Source 1 cannot be a constant. */
18079 /* Source 1 cannot be a non-matching memory. */
18083 /* Improve address combine. */
18092 }
18094 /* Similarly, but assume that the destination has already been
18095 set up properly. */
18097 void
18100 {
18103 }
18105 /* Attempt to expand a binary operator. Make the expansion closer to the
18106 actual machine, then just general_operand, which will allow 3 separate
18107 memory references (one output, two input) in a single insn. */
18109 void
18111 rtx operands[])
18112 {
18119 /* Emit the instruction. */
18126 {
18127 /* This is going to be an LEA; avoid splitting it later. */
18129 }
18130 else
18131 {
18134 }
18136 /* Fix up the destination if needed. */
18139 }
18141 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
18142 the given OPERANDS. */
18144 void
18146 rtx operands[])
18147 {
18150 {
18153 }
18155 {
18158 }
18159 /* Optimize (__m128i) d | (__m128i) e and similar code
18160 when d and e are float vectors into float vector logical
18161 insn. In C/C++ without using intrinsics there is no other way
18162 to express vector logical operation on float vectors than
18163 to cast them temporarily to integer vectors. */
18165 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18174 {
18175 rtx dst;
18177 {
18186 {
18189 }
18190 else
18191 {
18196 }
18207 }
18208 }
18217 }
18219 /* Return TRUE or FALSE depending on whether the binary operator meets the
18220 appropriate constraints. */
18222 bool
18225 {
18230 /* Both source operands cannot be in memory. */
18234 /* Canonicalize operand order for commutative operators. */
18238 /* If the destination is memory, we must have a matching source operand. */
18242 /* Source 1 cannot be a constant. */
18246 /* Source 1 cannot be a non-matching memory. */
18248 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18256 }
18258 /* Attempt to expand a unary operator. Make the expansion closer to the
18259 actual machine, then just general_operand, which will allow 2 separate
18260 memory references (one output, one input) in a single insn. */
18262 void
18264 rtx operands[])
18265 {
18272 /* If the destination is memory, and we do not have matching source
18273 operands, do things in registers. */
18275 {
18278 else
18280 }
18282 /* When source operand is memory, destination must match. */
18286 /* Emit the instruction. */
18292 else
18293 {
18296 }
18298 /* Fix up the destination if needed. */
18301 }
18303 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18304 divisor are within the range [0-255]. */
18306 void
18309 {
18318 {
18331 }
18338 /* Use 8bit unsigned divimod if dividend and divisor are within
18339 the range [0-255]. */
18348 pc_rtx);
18353 /* Generate original signed/unsigned divimod. */
18358 /* Branch to the end. */
18362 /* Generate 8bit unsigned divide. */
18364 /* Don't use operands[0] for result of 8bit divide since not all
18365 registers support QImode ZERO_EXTRACT. */
18372 {
18375 }
18376 else
18377 {
18380 }
18382 /* Extract remainder from AH. */
18386 else
18387 {
18388 /* Need a new scratch register since the old one has result
18389 of 8bit divide. */
18393 }
18396 /* Zero extend quotient from AL. */
18402 }
18404 #define LEA_MAX_STALL (3)
18405 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18407 /* Increase given DISTANCE in half-cycles according to
18408 dependencies between PREV and NEXT instructions.
18409 Add 1 half-cycle if there is no dependency and
18410 go to next cycle if there is some dependecy. */
18412 static unsigned int
18414 {
18430 }
18432 /* Function checks if instruction INSN defines register number
18433 REGNO1 or REGNO2. */
18435 static bool
18438 {
18439 df_ref def;
18449 }
18451 /* Function checks if instruction INSN uses register number
18452 REGNO as a part of address expression. */
18454 static bool
18456 {
18457 df_ref use;
18464 }
18466 /* Search backward for non-agu definition of register number REGNO1
18467 or register number REGNO2 in basic block starting from instruction
18468 START up to head of basic block or instruction INSN.
18470 Function puts true value into *FOUND var if definition was found
18471 and false otherwise.
18473 Distance in half-cycles between START and found instruction or head
18474 of BB is added to DISTANCE and returned. */
18476 static int
18480 {
18490 {
18492 {
18495 {
18498 {
18501 }
18502 }
18505 }
18510 }
18513 }
18515 /* Search backward for non-agu definition of register number REGNO1
18516 or register number REGNO2 in INSN's basic block until
18517 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18518 2. Reach neighbour BBs boundary, or
18519 3. Reach agu definition.
18520 Returns the distance between the non-agu definition point and INSN.
18521 If no definition point, returns -1. */
18523 static int
18526 {
18537 {
18538 edge e;
18539 edge_iterator ei;
18544 {
18547 }
18553 else
18554 {
18559 {
18560 int bb_dist
18566 {
18573 }
18574 }
18577 }
18578 }
18580 /* get_attr_type may modify recog data. We want to make sure
18581 that recog data is valid for instruction INSN, on which
18582 distance_non_agu_define is called. INSN is unchanged here. */
18589 }
18591 /* Return the distance in half-cycles between INSN and the next
18592 insn that uses register number REGNO in memory address added
18593 to DISTANCE. Return -1 if REGNO0 is set.
18595 Put true value into *FOUND if register usage was found and
18596 false otherwise.
18597 Put true value into *REDEFINED if register redefinition was
18598 found and false otherwise. */
18600 static int
18604 {
18613 {
18616 /* If insn and start belong to the same bb, set prev to insn,
18617 so the call to increase_distance will increase the distance
18618 between insns by 1. */
18620 }
18625 {
18627 {
18630 {
18631 /* Return DISTANCE if OP0 is used in memory
18632 address in NEXT. */
18635 }
18638 {
18639 /* Return -1 if OP0 is set in NEXT. */
18642 }
18645 }
18651 }
18654 }
18656 /* Return the distance between INSN and the next insn that uses
18657 register number REGNO0 in memory address. Return -1 if no such
18658 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18660 static int
18662 {
18674 {
18675 edge e;
18676 edge_iterator ei;
18681 {
18684 }
18690 else
18691 {
18697 {
18698 int bb_dist
18703 {
18710 }
18711 }
18714 }
18715 }
18721 }
18723 /* Define this macro to tune LEA priority vs ADD, it take effect when
18724 there is a dilemma of choicing LEA or ADD
18725 Negative value: ADD is more preferred than LEA
18726 Zero: Netrual
18727 Positive value: LEA is more preferred than ADD*/
18728 #define IX86_LEA_PRIORITY 0
18730 /* Return true if usage of lea INSN has performance advantage
18731 over a sequence of instructions. Instructions sequence has
18732 SPLIT_COST cycles higher latency than lea latency. */
18734 static bool
18737 {
18740 /* For Silvermont if using a 2-source or 3-source LEA for
18741 non-destructive destination purposes, or due to wanting
18742 ability to use SCALE, the use of LEA is justified. */
18744 {
18752 }
18758 {
18759 /* If there is no non AGU operand definition, no AGU
18760 operand usage and split cost is 0 then both lea
18761 and non lea variants have same priority. Currently
18762 we prefer lea for 64 bit code and non lea on 32 bit
18763 code. */
18766 else
18768 }
18770 /* With longer definitions distance lea is more preferable.
18771 Here we change it to take into account splitting cost and
18772 lea priority. */
18775 /* If there is no use in memory addess then we just check
18776 that split cost exceeds AGU stall. */
18780 /* If this insn has both backward non-agu dependence and forward
18781 agu dependence, the one with short distance takes effect. */
18783 }
18785 /* Return true if it is legal to clobber flags by INSN and
18786 false otherwise. */
18788 static bool
18790 {
18792 df_ref use;
18793 bitmap live;
18796 {
18798 {
18805 }
18811 }
18815 }
18817 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18818 move and add to avoid AGU stalls. */
18820 bool
18822 {
18825 /* Check if we need to optimize. */
18829 /* Check it is correct to split here. */
18837 /* We need to split only adds with non destructive
18838 destination operand. */
18841 else
18843 }
18845 /* Return true if we should emit lea instruction instead of mov
18846 instruction. */
18848 bool
18850 {
18853 /* Check if we need to optimize. */
18857 /* Use lea for reg to reg moves only. */
18865 }
18867 /* Return true if we need to split lea into a sequence of
18868 instructions to avoid AGU stalls. */
18870 bool
18872 {
18878 /* Check we need to optimize. */
18882 /* The "at least two components" test below might not catch simple
18883 move or zero extension insns if parts.base is non-NULL and parts.disp
18884 is const0_rtx as the only components in the address, e.g. if the
18885 register is %rbp or %r13. As this test is much cheaper and moves or
18886 zero extensions are the common case, do this check first. */
18892 /* Check if it is OK to split here. */
18899 /* There should be at least two components in the address. */
18904 /* We should not split into add if non legitimate pic
18905 operand is used as displacement. */
18920 /* Compute how many cycles we will add to execution time
18921 if split lea into a sequence of instructions. */
18923 {
18924 /* Have to use mov instruction if non desctructive
18925 destination form is used. */
18929 /* Have to add index to base if both exist. */
18933 /* Have to use shift and adds if scale is 2 or greater. */
18935 {
18940 else
18942 }
18944 /* Have to use add instruction with immediate if
18945 disp is non zero. */
18949 /* Subtract the price of lea. */
18951 }
18955 }
18957 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18958 matches destination. RTX includes clobber of FLAGS_REG. */
18960 static void
18963 {
18970 }
18972 /* Return true if regno1 def is nearest to the insn. */
18974 static bool
18976 {
18983 {
18985 {
18988 }
18994 }
18996 /* None of the regs is defined in the bb. */
18998 }
19000 /* Split lea instructions into a sequence of instructions
19001 which are executed on ALU to avoid AGU stalls.
19002 It is assumed that it is allowed to clobber flags register
19003 at lea position. */
19005 void
19007 {
19023 {
19026 }
19029 {
19032 }
19038 {
19039 /* Case r1 = r1 + ... */
19041 {
19042 /* If we have a case r1 = r1 + C * r2 then we
19043 should use multiplication which is very
19044 expensive. Assume cost model is wrong if we
19045 have such case here. */
19050 }
19051 else
19052 {
19053 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
19057 /* Use shift for scaling. */
19066 }
19067 }
19069 {
19072 }
19073 else
19074 {
19076 {
19079 }
19081 {
19084 }
19085 else
19086 {
19091 else
19092 {
19093 rtx tmp1;
19095 /* Find better operand for SET instruction, depending
19096 on which definition is farther from the insn. */
19099 else
19109 }
19112 }
19116 }
19117 }
19119 /* Return true if it is ok to optimize an ADD operation to LEA
19120 operation to avoid flag register consumation. For most processors,
19121 ADD is faster than LEA. For the processors like BONNELL, if the
19122 destination register of LEA holds an actual address which will be
19123 used soon, LEA is better and otherwise ADD is better. */
19125 bool
19127 {
19132 /* If a = b + c, (a!=b && a!=c), must use lea form. */
19140 }
19142 /* Return true if destination reg of SET_BODY is shift count of
19143 USE_BODY. */
19145 static bool
19147 {
19148 rtx set_dest;
19149 rtx shift_rtx;
19152 /* Retrieve destination of SET_BODY. */
19154 {
19163 use_body))
19168 }
19170 /* Retrieve shift count of USE_BODY. */
19172 {
19184 }
19192 {
19195 /* Return true if shift count is dest of SET_BODY. */
19197 {
19198 /* Add check since it can be invoked before register
19199 allocation in pre-reload schedule. */
19205 }
19206 }
19209 }
19211 /* Return true if destination reg of SET_INSN is shift count of
19212 USE_INSN. */
19214 bool
19216 {
19219 }
19221 /* Return TRUE or FALSE depending on whether the unary operator meets the
19222 appropriate constraints. */
19224 bool
19226 machine_mode,
19228 {
19229 /* If one of operands is memory, source and destination must match. */
19235 }
19237 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19238 are ok, keeping in mind the possible movddup alternative. */
19240 bool
19242 {
19248 }
19250 /* Post-reload splitter for converting an SF or DFmode value in an
19251 SSE register into an unsigned SImode. */
19253 void
19255 {
19256 machine_mode vecmode;
19266 /* Load up the value into the low element. We must ensure that the other
19267 elements are valid floats -- zero is the easiest such value. */
19269 {
19272 else
19274 }
19275 else
19276 {
19281 else
19283 }
19303 else
19308 }
19310 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19311 Expects the 64-bit DImode to be supplied in a pair of integral
19312 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19313 -mfpmath=sse, !optimize_size only. */
19315 void
19317 {
19321 rtx x;
19327 {
19330 }
19331 else
19332 {
19336 }
19344 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19347 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19348 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19349 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19350 (0x1.0p84 + double(fp_value_hi_xmm)).
19351 Note these exponents differ by 32. */
19355 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19356 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19365 /* Add the upper and lower DFmode values together. */
19368 else
19369 {
19373 }
19376 }
19378 /* Not used, but eases macroization of patterns. */
19379 void
19381 {
19383 }
19385 /* Convert an unsigned SImode value into a DFmode. Only currently used
19386 for SSE, but applicable anywhere. */
19388 void
19390 {
19391 REAL_VALUE_TYPE TWO31r;
19406 }
19408 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19409 32-bit mode; otherwise we have a direct convert instruction. */
19411 void
19413 {
19414 REAL_VALUE_TYPE TWO32r;
19432 }
19434 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19435 For x86_32, -mfpmath=sse, !optimize_size only. */
19436 void
19438 {
19439 REAL_VALUE_TYPE ONE16r;
19458 }
19460 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19461 a vector of unsigned ints VAL to vector of floats TARGET. */
19463 void
19465 {
19467 REAL_VALUE_TYPE TWO16r;
19474 else
19479 OPTAB_DIRECT);
19490 OPTAB_DIRECT);
19492 OPTAB_DIRECT);
19495 }
19497 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19498 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19499 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19500 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19502 rtx
19504 {
19505 REAL_VALUE_TYPE TWO31r;
19520 {
19526 }
19535 OPTAB_DIRECT);
19536 else
19537 {
19543 OPTAB_DIRECT);
19544 }
19547 }
19549 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19550 then replicate the value for all elements of the vector
19551 register. */
19553 rtx
19555 {
19557 rtvec v;
19558 machine_mode scalar_mode;
19561 {
19594 }
19595 }
19597 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19598 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19599 for an SSE register. If VECT is true, then replicate the mask for
19600 all elements of the vector register. If INVERT is true, then create
19601 a mask excluding the sign bit. */
19603 rtx
19605 {
19607 wide_int w;
19611 {
19640 }
19648 /* Force this value into the low part of a fp vector constant. */
19657 }
19659 /* Generate code for floating point ABS or NEG. */
19661 void
19663 rtx operands[])
19664 {
19675 {
19681 }
19683 /* NEG and ABS performed with SSE use bitwise mask operations.
19684 Create the appropriate mask now. */
19687 else
19697 {
19699 rtvec par;
19704 else
19705 {
19708 }
19710 }
19711 else
19713 }
19715 /* Expand a copysign operation. Special case operand 0 being a constant. */
19717 void
19719 {
19733 else
19737 {
19744 {
19747 else
19748 {
19752 }
19753 }
19763 else
19767 }
19768 else
19769 {
19779 else
19783 }
19784 }
19786 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19787 be a constant, and so has already been expanded into a vector constant. */
19789 void
19791 {
19807 {
19810 }
19811 }
19813 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19814 so we have to do two masks. */
19816 void
19818 {
19833 {
19834 /* Shouldn't happen often (it's useless, obviously), but when it does
19835 we'd generate incorrect code if we continue below. */
19838 }
19841 {
19852 }
19853 else
19854 {
19856 {
19858 }
19860 {
19864 }
19868 {
19871 }
19873 {
19878 }
19880 }
19884 }
19886 /* Return TRUE or FALSE depending on whether the first SET in INSN
19887 has source and destination with matching CC modes, and that the
19888 CC mode is at least as constrained as REQ_MODE. */
19890 bool
19892 {
19893 rtx set;
19894 machine_mode set_mode;
19904 {
19914 /* FALLTHRU */
19918 /* FALLTHRU */
19922 /* FALLTHRU */
19937 }
19940 }
19942 /* Generate insn patterns to do an integer compare of OPERANDS. */
19944 static rtx
19946 {
19947 machine_mode cmpmode;
19953 /* This is very simple, but making the interface the same as in the
19954 FP case makes the rest of the code easier. */
19958 /* Return the test that should be put into the flags user, i.e.
19959 the bcc, scc, or cmov instruction. */
19961 }
19963 /* Figure out whether to use ordered or unordered fp comparisons.
19964 Return the appropriate mode to use. */
19966 machine_mode
19968 {
19969 /* ??? In order to make all comparisons reversible, we do all comparisons
19970 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19971 all forms trapping and nontrapping comparisons, we can make inequality
19972 comparisons trapping again, since it results in better code when using
19973 FCOM based compares. */
19975 }
19977 machine_mode
19979 {
19983 {
19986 }
19989 {
19990 /* Only zero flag is needed. */
19994 /* Codes needing carry flag. */
19997 /* Detect overflow checks. They need just the carry flag. */
20001 else
20006 /* Codes possibly doable only with sign flag when
20007 comparing against zero. */
20012 else
20013 /* For other cases Carry flag is not required. */
20015 /* Codes doable only with sign flag when comparing
20016 against zero, but we miss jump instruction for it
20017 so we need to use relational tests against overflow
20018 that thus needs to be zero. */
20023 else
20025 /* strcmp pattern do (use flags) and combine may ask us for proper
20026 mode. */
20031 }
20032 }
20034 /* Return the fixed registers used for condition codes. */
20036 static bool
20038 {
20042 }
20044 /* If two condition code modes are compatible, return a condition code
20045 mode which is compatible with both. Otherwise, return
20046 VOIDmode. */
20048 static machine_mode
20050 {
20067 {
20082 {
20097 }
20101 /* These are only compatible with themselves, which we already
20102 checked above. */
20104 }
20105 }
20108 /* Return a comparison we can do and that it is equivalent to
20109 swap_condition (code) apart possibly from orderedness.
20110 But, never change orderedness if TARGET_IEEE_FP, returning
20111 UNKNOWN in that case if necessary. */
20113 static enum rtx_code
20115 {
20117 {
20128 }
20129 }
20131 /* Return cost of comparison CODE using the best strategy for performance.
20132 All following functions do use number of instructions as a cost metrics.
20133 In future this should be tweaked to compute bytes for optimize_size and
20134 take into account performance of various instructions on various CPUs. */
20136 static int
20138 {
20141 /* The cost of code using bit-twiddling on %ah. */
20143 {
20166 }
20169 {
20176 }
20177 }
20179 /* Return strategy to use for floating-point. We assume that fcomi is always
20180 preferrable where available, since that is also true when looking at size
20181 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20183 enum ix86_fpcmp_strategy
20185 {
20186 /* Do fcomi/sahf based test when profitable. */
20195 }
20197 /* Swap, force into registers, or otherwise massage the two operands
20198 to a fp comparison. The operands are updated in place; the new
20199 comparison code is returned. */
20201 static enum rtx_code
20203 {
20209 /* All of the unordered compare instructions only work on registers.
20210 The same is true of the fcomi compare instructions. The XFmode
20211 compare instructions require registers except when comparing
20212 against zero or when converting operand 1 from fixed point to
20213 floating point. */
20222 {
20225 }
20226 else
20227 {
20228 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20229 things around if they appear profitable, otherwise force op0
20230 into a register. */
20236 {
20239 {
20242 }
20243 }
20249 {
20254 {
20257 }
20258 else
20260 }
20261 }
20263 /* Try to rearrange the comparison to make it cheaper. */
20267 {
20272 }
20277 }
20279 /* Convert comparison codes we use to represent FP comparison to integer
20280 code that will result in proper branch. Return UNKNOWN if no such code
20281 is available. */
20283 enum rtx_code
20285 {
20287 {
20310 }
20311 }
20313 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20315 static rtx
20317 {
20324 /* Do fcomi/sahf based test when profitable. */
20326 {
20346 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20353 /* In the unordered case, we have to check C2 for NaN's, which
20354 doesn't happen to work out to anything nice combination-wise.
20355 So do some bit twiddling on the value we've got in AH to come
20356 up with an appropriate set of condition codes. */
20360 {
20364 {
20367 }
20368 else
20369 {
20375 }
20380 {
20385 }
20386 else
20387 {
20390 }
20395 {
20398 }
20399 else
20400 {
20404 }
20409 {
20415 }
20416 else
20417 {
20420 }
20425 {
20430 }
20431 else
20432 {
20435 }
20440 {
20445 }
20446 else
20447 {
20450 }
20464 }
20469 }
20471 /* Return the test that should be put into the flags user, i.e.
20472 the bcc, scc, or cmov instruction. */
20475 const0_rtx);
20476 }
20478 static rtx
20480 {
20481 rtx ret;
20487 {
20490 }
20491 else
20495 }
20497 void
20499 {
20501 rtx tmp;
20504 {
20511 simple:
20515 pc_rtx);
20523 /* Expand DImode branch into multiple compare+branch. */
20524 {
20528 machine_mode submode;
20531 {
20534 }
20541 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20542 avoid two branches. This costs one extra insn, so disable when
20543 optimizing for size. */
20548 {
20566 }
20568 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20569 op1 is a constant and the low word is zero, then we can just
20570 examine the high word. Similarly for low word -1 and
20571 less-or-equal-than or greater-than. */
20575 {
20578 {
20581 }
20585 {
20588 }
20592 }
20594 /* Otherwise, we need two or three jumps. */
20603 {
20617 }
20619 /*
20620 * a < b =>
20621 * if (hi(a) < hi(b)) goto true;
20622 * if (hi(a) > hi(b)) goto false;
20623 * if (lo(a) < lo(b)) goto true;
20624 * false:
20625 */
20637 }
20642 }
20643 }
20645 /* Split branch based on floating point condition. */
20646 void
20649 {
20650 rtx condition;
20651 rtx i;
20654 {
20657 }
20660 tmp);
20668 }
20670 void
20672 {
20673 rtx ret;
20680 }
20682 /* Expand comparison setting or clearing carry flag. Return true when
20683 successful and set pop for the operation. */
20684 static bool
20686 {
20687 machine_mode mode =
20690 /* Do not handle double-mode compares that go through special path. */
20695 {
20696 rtx compare_op;
20701 /* Shortcut: following common codes never translate
20702 into carry flag compares. */
20707 /* These comparisons require zero flag; swap operands so they won't. */
20710 {
20713 }
20715 /* Try to expand the comparison and verify that we end up with
20716 carry flag based comparison. This fails to be true only when
20717 we decide to expand comparison using arithmetic that is not
20718 too common scenario. */
20727 else
20736 }
20742 {
20747 /* Convert a==0 into (unsigned)a<1. */
20756 /* Convert a>b into b<a or a>=b-1. */
20760 {
20762 /* Bail out on overflow. We still can swap operands but that
20763 would force loading of the constant into register. */
20768 }
20769 else
20770 {
20773 }
20776 /* Convert a>=0 into (unsigned)a<0x80000000. */
20794 }
20795 /* Swapping operands may cause constant to appear as first operand. */
20797 {
20801 }
20805 }
20807 bool
20809 {
20812 rtx compare_op;
20834 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20835 HImode insns, we'd be swallowed in word prefix ops. */
20841 {
20845 HOST_WIDE_INT diff;
20848 /* Sign bit compares are better done using shifts than we do by using
20849 sbb. */
20852 {
20853 /* Detect overlap between destination and compare sources. */
20857 {
20858 rtx flags;
20867 {
20869 compare_code
20871 }
20873 /* To simplify rest of code, restrict to the GEU case. */
20875 {
20879 }
20880 else
20881 {
20884 reverse_condition_maybe_unordered
20886 else
20889 }
20898 else
20901 }
20902 else
20903 {
20906 else
20907 {
20910 }
20912 }
20915 {
20916 /*
20917 * cmpl op0,op1
20918 * sbbl dest,dest
20919 * [addl dest, ct]
20920 *
20921 * Size 5 - 8.
20922 */
20927 }
20929 {
20930 /*
20931 * cmpl op0,op1
20932 * sbbl dest,dest
20933 * orl $ct, dest
20934 *
20935 * Size 8.
20936 */
20940 }
20942 {
20943 /*
20944 * cmpl op0,op1
20945 * sbbl dest,dest
20946 * notl dest
20947 * [addl dest, cf]
20948 *
20949 * Size 8 - 11.
20950 */
20956 }
20957 else
20958 {
20959 /*
20960 * cmpl op0,op1
20961 * sbbl dest,dest
20962 * [notl dest]
20963 * andl cf - ct, dest
20964 * [addl dest, ct]
20965 *
20966 * Size 8 - 11.
20967 */
20970 {
20974 }
20984 }
20990 }
20993 {
20998 {
21001 /* We may be reversing unordered compare to normal compare, that
21002 is not valid in general (we may convert non-trapping condition
21003 to trapping one), however on i386 we currently emit all
21004 comparisons unordered. */
21006 }
21007 else
21010 {
21014 }
21015 }
21020 {
21025 {
21030 }
21031 }
21033 /* Optimize dest = (op0 < 0) ? -1 : cf. */
21037 {
21038 /* If lea code below could be used, only optimize
21039 if it results in a 2 insn sequence. */
21045 {
21046 /*
21047 * notl op1 (if necessary)
21048 * sarl $31, op1
21049 * orl cf, op1
21050 */
21052 {
21056 }
21067 }
21068 }
21076 {
21077 /*
21078 * xorl dest,dest
21079 * cmpl op1,op2
21080 * setcc dest
21081 * lea cf(dest*(ct-cf)),dest
21082 *
21083 * Size 14.
21084 *
21085 * This also catches the degenerate setcc-only case.
21086 */
21088 rtx tmp;
21094 /* On x86_64 the lea instruction operates on Pmode, so we need
21095 to get arithmetics done in proper mode to match. */
21098 else
21099 {
21100 rtx out1;
21103 nops++;
21105 {
21107 nops++;
21108 }
21109 }
21111 {
21113 nops++;
21114 }
21116 {
21119 else
21121 }
21126 }
21128 /*
21129 * General case: Jumpful:
21130 * xorl dest,dest cmpl op1, op2
21131 * cmpl op1, op2 movl ct, dest
21132 * setcc dest jcc 1f
21133 * decl dest movl cf, dest
21134 * andl (cf-ct),dest 1:
21135 * addl ct,dest
21136 *
21137 * Size 20. Size 14.
21138 *
21139 * This is reasonably steep, but branch mispredict costs are
21140 * high on modern cpus, so consider failing only if optimizing
21141 * for space.
21142 */
21147 {
21149 {
21154 {
21157 /* We may be reversing unordered compare to normal compare,
21158 that is not valid in general (we may convert non-trapping
21159 condition to trapping one), however on i386 we currently
21160 emit all comparisons unordered. */
21162 }
21163 else
21164 {
21168 }
21171 {
21175 }
21176 }
21179 {
21180 /* notl op1 (if needed)
21181 sarl $31, op1
21182 andl (cf-ct), op1
21183 addl ct, op1
21185 For x < 0 (resp. x <= -1) there will be no notl,
21186 so if possible swap the constants to get rid of the
21187 complement.
21188 True/false will be -1/0 while code below (store flag
21189 followed by decrement) is 0/-1, so the constants need
21190 to be exchanged once more. */
21193 {
21196 }
21197 else
21201 }
21202 else
21203 {
21207 constm1_rtx,
21209 }
21221 }
21222 }
21225 {
21226 /* Try a few things more with specific constants and a variable. */
21228 optab op;
21234 /* If one of the two operands is an interesting constant, load a
21235 constant with the above and mask it in with a logical operation. */
21238 {
21244 else
21246 }
21248 {
21254 else
21256 }
21257 else
21264 /* Recurse to get the constant loaded. */
21268 /* Mask in the interesting variable. */
21270 OPTAB_WIDEN);
21275 }
21277 /*
21278 * For comparison with above,
21279 *
21280 * movl cf,dest
21281 * movl ct,tmp
21282 * cmpl op1,op2
21283 * cmovcc tmp,dest
21284 *
21285 * Size 15.
21286 */
21308 }
21310 /* Swap, force into registers, or otherwise massage the two operands
21311 to an sse comparison with a mask result. Thus we differ a bit from
21312 ix86_prepare_fp_compare_args which expects to produce a flags result.
21314 The DEST operand exists to help determine whether to commute commutative
21315 operators. The POP0/POP1 operands are updated in place. The new
21316 comparison code is returned, or UNKNOWN if not implementable. */
21318 static enum rtx_code
21321 {
21323 {
21326 /* AVX supports all the needed comparisons. */
21329 /* We have no LTGT as an operator. We could implement it with
21330 NE & ORDERED, but this requires an extra temporary. It's
21331 not clear that it's worth it. */
21338 /* These are supported directly. */
21345 /* AVX has 3 operand comparisons, no need to swap anything. */
21348 /* For commutative operators, try to canonicalize the destination
21349 operand to be first in the comparison - this helps reload to
21350 avoid extra moves. */
21353 /* FALLTHRU */
21359 /* These are not supported directly before AVX, and furthermore
21360 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21361 comparison operands to transform into something that is
21362 supported. */
21369 }
21372 }
21374 /* Detect conditional moves that exactly match min/max operational
21375 semantics. Note that this is IEEE safe, as long as we don't
21376 interchange the operands.
21378 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21379 and TRUE if the operation is successful and instructions are emitted. */
21381 static bool
21384 {
21385 machine_mode mode;
21387 rtx tmp;
21390 ;
21393 else
21400 else
21405 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21406 but MODE may be a vector mode and thus not appropriate. */
21408 {
21410 rtvec v;
21415 }
21416 else
21417 {
21420 }
21424 }
21426 /* Expand an sse vector comparison. Return the register with the result. */
21428 static rtx
21431 {
21435 /* In general case result of comparison can differ from operands' type. */
21436 machine_mode cmp_mode;
21438 /* In AVX512F the result of comparison is an integer mask. */
21440 rtx x;
21443 {
21448 }
21449 else
21462 /* Compare patterns for int modes are unspec in AVX512F only. */
21464 {
21468 {
21485 }
21488 {
21491 }
21492 }
21496 {
21499 }
21500 else
21504 }
21506 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21507 operations. This is used for both scalar and vector conditional moves. */
21509 static void
21511 {
21515 /* In AVX512F the result of comparison is an integer mask. */
21523 {
21525 }
21528 {
21532 }
21535 {
21540 }
21543 {
21547 }
21550 {
21557 op_true,
21558 op_false)));
21559 }
21560 else
21561 {
21571 {
21585 {
21592 }
21607 {
21614 }
21638 }
21641 {
21645 }
21646 else
21647 {
21653 else
21665 }
21666 }
21667 }
21669 /* Expand a floating-point conditional move. Return true if successful. */
21671 bool
21673 {
21681 {
21682 machine_mode cmode;
21684 /* Since we've no cmove for sse registers, don't force bad register
21685 allocation just to gain access to it. Deny movcc when the
21686 comparison mode doesn't match the move mode. */
21705 }
21712 /* The floating point conditional move instructions don't directly
21713 support conditions resulting from a signed integer comparison. */
21717 {
21722 }
21729 }
21731 /* Expand a floating-point vector conditional move; a vcond operation
21732 rather than a movcc operation. */
21734 bool
21736 {
21738 rtx cmp;
21743 {
21744 rtx temp;
21746 {
21763 }
21765 OPTAB_DIRECT);
21768 }
21778 }
21780 /* Expand a signed/unsigned integral vector conditional move. */
21782 bool
21784 {
21794 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21795 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21804 {
21808 {
21814 }
21817 {
21823 }
21824 }
21833 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21837 ;
21838 else
21839 {
21840 /* Canonicalize the comparison to EQ, GT, GTU. */
21842 {
21859 /* FALLTHRU */
21869 }
21871 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21873 {
21875 {
21877 /* SSE4.1 supports EQ. */
21884 /* SSE4.2 supports GT/GTU. */
21891 }
21892 }
21894 /* Unsigned parallel compare is not supported by the hardware.
21895 Play some tricks to turn this into a signed comparison
21896 against 0. */
21898 {
21902 {
21909 {
21914 {
21923 }
21924 /* Subtract (-(INT MAX) - 1) from both operands to make
21925 them signed. */
21936 }
21945 /* Perform a parallel unsigned saturating subtraction. */
21957 }
21958 }
21959 }
21961 /* Allow the comparison to be done in one mode, but the movcc to
21962 happen in another mode. */
21964 {
21967 }
21968 else
21969 {
21975 }
21980 }
21982 /* AVX512F does support 64-byte integer vector operations,
21983 thus the longest vector we are faced with is V64QImode. */
21984 #define MAX_VECT_LEN 64
21986 struct expand_vec_perm_d
21987 {
21990 machine_mode vmode;
21994 };
21996 static bool
21999 {
22000 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
22001 expander, so args are either in d, or in op0, op1 etc. */
22007 {
22038 {
22041 }
22045 {
22048 }
22052 {
22055 }
22071 {
22074 }
22078 {
22081 }
22085 {
22088 }
22092 }
22097 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
22098 expander, so args are either in d, or in op0, op1 etc. */
22100 {
22108 }
22112 }
22114 /* Expand a variable vector permutation. */
22116 void
22118 {
22129 /* Number of elements in the vector. */
22138 {
22140 {
22141 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
22142 an constant shuffle operand. With a tiny bit of effort we can
22143 use VPERMD instead. A re-interpretation stall for V4DFmode is
22144 unfortunate but there's no avoiding it.
22145 Similarly for V16HImode we don't have instructions for variable
22146 shuffling, while for V32QImode we can use after preparing suitable
22147 masks vpshufb; vpshufb; vpermq; vpor. */
22150 {
22154 }
22155 else
22156 {
22160 }
22163 /* Replicate the low bits of the V4DImode mask into V8SImode:
22164 mask = { A B C D }
22165 t1 = { A A B B C C D D }. */
22173 else
22176 /* Multiply the shuffle indicies by two. */
22178 OPTAB_DIRECT);
22180 /* Add one to the odd shuffle indicies:
22181 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22183 {
22186 }
22190 OPTAB_DIRECT);
22192 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22197 }
22200 {
22202 /* The VPERMD and VPERMPS instructions already properly ignore
22203 the high bits of the shuffle elements. No need for us to
22204 perform an AND ourselves. */
22206 {
22211 }
22212 else
22213 {
22219 }
22226 else
22227 {
22233 }
22237 /* By combining the two 128-bit input vectors into one 256-bit
22238 input vector, we can use VPERMD and VPERMPS for the full
22239 two-operand shuffle. */
22271 /* From mask create two adjusted masks, which contain the same
22272 bits as mask in the low 7 bits of each vector element.
22273 The first mask will have the most significant bit clear
22274 if it requests element from the same 128-bit lane
22275 and MSB set if it requests element from the other 128-bit lane.
22276 The second mask will have the opposite values of the MSB,
22277 and additionally will have its 128-bit lanes swapped.
22278 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22279 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22280 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22281 stands for other 12 bytes. */
22282 /* The bit whether element is from the same lane or the other
22283 lane is bit 4, so shift it up by 3 to the MSB position. */
22287 /* Clear MSB bits from the mask just in case it had them set. */
22289 /* After this t1 will have MSB set for elements from other lane. */
22291 /* Clear bits other than MSB. */
22293 /* Or in the lower bits from mask into t3. */
22295 /* And invert MSB bits in t1, so MSB is set for elements from the same
22296 lane. */
22298 /* Swap 128-bit lanes in t3. */
22303 /* And or in the lower bits from mask into t1. */
22306 {
22307 /* Each of these shuffles will put 0s in places where
22308 element from the other 128-bit lane is needed, otherwise
22309 will shuffle in the requested value. */
22313 /* For t3 the 128-bit lanes are swapped again. */
22318 /* And oring both together leads to the result. */
22325 }
22328 /* Similarly to the above one_operand_shuffle code,
22329 just for repeated twice for each operand. merge_two:
22330 code will merge the two results together. */
22354 }
22355 }
22358 {
22359 /* The XOP VPPERM insn supports three inputs. By ignoring the
22360 one_operand_shuffle special case, we avoid creating another
22361 set of constant vectors in memory. */
22364 /* mask = mask & {2*w-1, ...} */
22366 }
22367 else
22368 {
22369 /* mask = mask & {w-1, ...} */
22371 }
22379 /* For non-QImode operations, convert the word permutation control
22380 into a byte permutation control. */
22382 {
22387 /* Convert mask to vector of chars. */
22390 /* Replicate each of the input bytes into byte positions:
22391 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22392 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22393 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22400 else
22403 /* Convert it into the byte positions by doing
22404 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22410 }
22412 /* The actual shuffle operations all operate on V16QImode. */
22417 {
22424 }
22426 {
22433 }
22434 else
22435 {
22439 /* Shuffle the two input vectors independently. */
22445 merge_two:
22446 /* Then merge them together. The key is whether any given control
22447 element contained a bit set that indicates the second word. */
22451 {
22452 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22453 more shuffle to convert the V2DI input mask into a V4SI
22454 input mask. At which point the masking that expand_int_vcond
22455 will work as desired. */
22463 }
22485 }
22486 }
22488 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22489 true if we should do zero extension, else sign extension. HIGH_P is
22490 true if we want the N/2 high elements, else the low elements. */
22492 void
22494 {
22496 rtx tmp;
22499 {
22505 {
22509 else
22512 extract
22518 else
22521 extract
22527 else
22530 extract
22536 else
22539 extract
22545 else
22548 extract
22554 else
22557 extract
22563 else
22569 else
22575 else
22580 }
22583 {
22586 }
22588 {
22589 /* Shift higher 8 bytes to lower 8 bytes. */
22594 }
22595 else
22599 }
22600 else
22601 {
22605 {
22609 else
22615 else
22621 else
22626 }
22630 else
22637 }
22638 }
22640 /* Expand conditional increment or decrement using adb/sbb instructions.
22641 The default case using setcc followed by the conditional move can be
22642 done by generic code. */
22643 bool
22645 {
22647 rtx flags;
22649 rtx compare_op;
22652 machine_mode mode;
22667 {
22670 }
22673 {
22677 reverse_condition_maybe_unordered
22679 else
22681 }
22685 /* Construct either adc or sbb insn. */
22687 {
22689 {
22704 }
22705 }
22706 else
22707 {
22709 {
22724 }
22725 }
22729 }
22732 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22733 but works for floating pointer parameters and nonoffsetable memories.
22734 For pushes, it returns just stack offsets; the values will be saved
22735 in the right order. Maximally three parts are generated. */
22737 static int
22739 {
22744 else
22750 /* Optimize constant pool reference to immediates. This is used by fp
22751 moves, that force all constants to memory to allow combining. */
22753 {
22757 }
22760 {
22761 /* The only non-offsetable memories we handle are pushes. */
22770 }
22773 {
22775 /* Caution: if we looked through a constant pool memory above,
22776 the operand may actually have a different mode now. That's
22777 ok, since we want to pun this all the way back to an integer. */
22781 }
22784 {
22787 else
22788 {
22792 {
22796 }
22798 {
22803 }
22805 {
22806 REAL_VALUE_TYPE r;
22811 {
22818 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22819 long double may not be 80-bit. */
22828 }
22831 }
22832 else
22834 }
22835 }
22836 else
22837 {
22841 {
22844 {
22848 }
22850 {
22854 }
22856 {
22857 REAL_VALUE_TYPE r;
22863 /* real_to_target puts 32-bit pieces in each long. */
22865 gen_int_mode
22868 DImode);
22872 else
22874 gen_int_mode
22877 DImode);
22878 }
22879 else
22881 }
22882 }
22885 }
22887 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22888 Return false when normal moves are needed; true when all required
22889 insns have been emitted. Operands 2-4 contain the input values
22890 int the correct order; operands 5-7 contain the output values. */
22892 void
22894 {
22902 /* The DFmode expanders may ask us to move double.
22903 For 64bit target this is single move. By hiding the fact
22904 here we simplify i386.md splitters. */
22906 {
22907 /* Optimize constant pool reference to immediates. This is used by
22908 fp moves, that force all constants to memory to allow combining. */
22915 {
22918 }
22919 else
22924 }
22926 /* The only non-offsettable memory we handle is push. */
22929 else
22936 /* When emitting push, take care for source operands on the stack. */
22939 {
22942 /* Compensate for the stack decrement by 4. */
22947 /* src_base refers to the stack pointer and is
22948 automatically decreased by emitted push. */
22952 }
22954 /* We need to do copy in the right order in case an address register
22955 of the source overlaps the destination. */
22957 {
22958 rtx tmp;
22961 {
22965 collisions++;
22966 }
22968 /* Collision in the middle part can be handled by reordering. */
22970 {
22973 }
22977 {
22979 {
22982 }
22983 else
22984 {
22987 }
22988 }
22990 /* If there are more collisions, we can't handle it by reordering.
22991 Do an lea to the last part and use only one colliding move. */
22993 {
23000 /* Handle the case when the last part isn't valid for lea.
23001 Happens in 64-bit mode storing the 12-byte XFmode. */
23007 {
23012 {
23013 /* It is not valid to use %gs: or %fs: in
23014 lea though, so we need to remove it from the
23015 address used for lea and add it to each individual
23016 memory loads instead. */
23020 {
23022 {
23028 {
23032 }
23033 }
23037 }
23039 }
23040 }
23046 {
23051 }
23052 }
23053 }
23056 {
23058 {
23060 {
23065 }
23067 {
23070 }
23071 }
23072 else
23073 {
23074 /* In 64bit mode we don't have 32bit push available. In case this is
23075 register, it is OK - we will just use larger counterpart. We also
23076 retype memory - these comes from attempt to avoid REX prefix on
23077 moving of second half of TFmode value. */
23079 {
23081 {
23092 }
23096 }
23097 }
23101 }
23103 /* Choose correct order to not overwrite the source before it is copied. */
23113 {
23115 {
23118 }
23119 }
23120 else
23121 {
23123 {
23126 }
23127 }
23129 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
23131 {
23140 }
23146 }
23148 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
23149 left shift by a constant, either using a single shift or
23150 a sequence of add instructions. */
23152 static void
23154 {
23160 {
23164 }
23165 else
23166 {
23169 }
23170 }
23172 void
23174 {
23183 {
23188 {
23194 }
23195 else
23196 {
23204 }
23206 }
23213 {
23214 /* Assuming we've chosen a QImode capable registers, then 1 << N
23215 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23217 {
23233 }
23235 /* Otherwise, we can get the same results by manually performing
23236 a bit extract operation on bit 5/6, and then performing the two
23237 shifts. The two methods of getting 0/1 into low/high are exactly
23238 the same size. Avoiding the shift in the bit extract case helps
23239 pentium4 a bit; no one else seems to care much either way. */
23240 else
23241 {
23242 machine_mode half_mode;
23246 HOST_WIDE_INT bits;
23247 rtx x;
23250 {
23256 }
23257 else
23258 {
23264 }
23268 else
23276 }
23281 }
23284 {
23285 /* For -1 << N, we can avoid the shld instruction, because we
23286 know that we're shifting 0...31/63 ones into a -1. */
23290 else
23292 }
23293 else
23294 {
23302 }
23307 {
23313 }
23314 else
23315 {
23320 }
23321 }
23323 void
23325 {
23335 {
23340 {
23346 }
23348 {
23357 }
23358 else
23359 {
23367 }
23368 }
23369 else
23370 {
23382 {
23390 scratch));
23391 }
23392 else
23393 {
23398 }
23399 }
23400 }
23402 void
23404 {
23414 {
23419 {
23426 }
23427 else
23428 {
23436 }
23437 }
23438 else
23439 {
23451 {
23457 scratch));
23458 }
23459 else
23460 {
23465 }
23466 }
23467 }
23469 /* Predict just emitted jump instruction to be taken with probability PROB. */
23470 static void
23472 {
23476 }
23478 /* Helper function for the string operations below. Dest VARIABLE whether
23479 it is aligned to VALUE bytes. If true, jump to the label. */
23482 {
23487 else
23493 else
23496 }
23498 /* Adjust COUNTER by the VALUE. */
23499 static void
23501 {
23506 }
23508 /* Zero extend possibly SImode EXP to Pmode register. */
23509 rtx
23511 {
23513 }
23515 /* Divide COUNTREG by SCALE. */
23516 static rtx
23518 {
23519 rtx sc;
23531 }
23533 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23534 DImode for constant loop counts. */
23536 static machine_mode
23538 {
23546 }
23548 /* Copy the address to a Pmode register. This is used for x32 to
23549 truncate DImode TLS address to a SImode register. */
23551 static rtx
23553 {
23554 rtx reg;
23556 {
23560 }
23561 else
23562 {
23567 }
23568 }
23570 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23571 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23572 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23573 memory by VALUE (supposed to be in MODE).
23575 The size is rounded down to whole number of chunk size moved at once.
23576 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23579 static void
23584 {
23591 rtx size;
23600 /* Those two should combine. */
23602 {
23606 }
23613 /* This assert could be relaxed - in this case we'll need to compute
23614 smallest power of two, containing in PIECE_SIZE_N and pass it to
23615 offset_address. */
23621 {
23625 /* When unrolling for chips that reorder memory reads and writes,
23626 we can save registers by using single temporary.
23627 Also using 4 temporaries is overkill in 32bit mode. */
23629 {
23631 {
23633 {
23634 destmem =
23636 srcmem =
23638 }
23640 }
23641 }
23642 else
23643 {
23647 {
23650 {
23651 srcmem =
23653 }
23655 }
23657 {
23659 {
23660 destmem =
23662 }
23664 }
23665 }
23666 }
23667 else
23669 {
23671 destmem =
23674 }
23684 {
23690 else
23692 }
23693 else
23701 {
23706 }
23708 }
23710 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23711 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23712 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23713 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23714 ORIG_VALUE is the original value passed to memset to fill the memory with.
23715 Other arguments have same meaning as for previous function. */
23717 static void
23720 rtx count,
23722 {
23723 rtx destexp;
23724 rtx srcexp;
23725 rtx countreg;
23726 HOST_WIDE_INT rounded_count;
23728 /* If possible, it is shorter to use rep movs.
23729 TODO: Maybe it is better to move this logic to decide_alg. */
23740 {
23744 }
23745 else
23748 {
23753 }
23758 {
23761 }
23762 else
23763 {
23767 {
23771 }
23772 else
23775 {
23780 }
23781 else
23782 {
23785 }
23788 }
23789 }
23791 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23792 DESTMEM.
23793 SRC is passed by pointer to be updated on return.
23794 Return value is updated DST. */
23795 static rtx
23797 HOST_WIDE_INT size_to_move)
23798 {
23801 machine_mode move_mode;
23804 /* Find the widest mode in which we could perform moves.
23805 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23806 it until move of such size is supported. */
23811 {
23815 }
23817 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23818 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23820 {
23825 {
23829 }
23830 }
23836 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23840 {
23841 /* We move from memory to memory, so we'll need to do it via
23842 a temporary register. */
23853 piece_size);
23855 piece_size);
23856 }
23858 /* Update DST and SRC rtx. */
23861 }
23863 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23864 static void
23867 {
23870 {
23875 /* For now MAX_SIZE should be a power of 2. This assert could be
23876 relaxed, but it'll require a bit more complicated epilogue
23877 expanding. */
23880 {
23883 }
23885 }
23887 {
23893 }
23895 /* When there are stringops, we can cheaply increase dest and src pointers.
23896 Otherwise we save code size by maintaining offset (zero is readily
23897 available from preceding rep operation) and using x86 addressing modes.
23898 */
23900 {
23902 {
23909 }
23911 {
23918 }
23920 {
23927 }
23928 }
23929 else
23930 {
23932 rtx tmp;
23935 {
23946 }
23948 {
23961 }
23963 {
23972 }
23973 }
23974 }
23976 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23977 with value PROMOTED_VAL.
23978 SRC is passed by pointer to be updated on return.
23979 Return value is updated DST. */
23980 static rtx
23982 HOST_WIDE_INT size_to_move)
23983 {
23986 machine_mode move_mode;
23989 /* Find the widest mode in which we could perform moves.
23990 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23991 it until move of such size is supported. */
23996 {
23999 }
24006 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
24010 {
24012 {
24015 piece_size);
24017 }
24025 piece_size);
24026 }
24028 /* Update DST rtx. */
24030 }
24031 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
24032 static void
24035 {
24036 count =
24042 }
24044 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
24045 static void
24048 {
24049 rtx dest;
24052 {
24057 /* For now MAX_SIZE should be a power of 2. This assert could be
24058 relaxed, but it'll require a bit more complicated epilogue
24059 expanding. */
24062 {
24064 {
24067 else
24069 }
24070 }
24072 }
24074 {
24077 }
24079 {
24082 {
24087 }
24088 else
24089 {
24098 }
24101 }
24103 {
24106 {
24109 }
24110 else
24111 {
24116 }
24119 }
24121 {
24127 }
24129 {
24135 }
24137 {
24143 }
24144 }
24146 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
24147 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
24148 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
24149 ignored.
24150 Return value is updated DESTMEM. */
24151 static rtx
24156 {
24159 {
24161 {
24164 {
24167 else
24169 }
24170 else
24176 }
24177 }
24179 }
24181 /* Test if COUNT&SIZE is nonzero and if so, expand movme
24182 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
24183 and jump to DONE_LABEL. */
24184 static void
24190 {
24193 rtx modesize;
24196 /* If we do not have vector value to copy, we must reduce size. */
24198 {
24200 {
24205 }
24206 else
24208 }
24209 else
24210 {
24211 /* Choose appropriate vector mode. */
24217 }
24222 {
24225 else
24226 {
24229 }
24231 }
24237 {
24241 }
24243 {
24246 else
24247 {
24250 }
24252 }
24258 }
24260 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24261 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24262 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24263 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24264 DONE_LABEL is a label after the whole copying sequence. The label is created
24265 on demand if *DONE_LABEL is NULL.
24266 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24267 bounds after the initial copies.
24269 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24270 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24271 we will dispatch to a library call for large blocks.
24273 In pseudocode we do:
24275 if (COUNT < SIZE)
24276 {
24277 Assume that SIZE is 4. Bigger sizes are handled analogously
24278 if (COUNT & 4)
24279 {
24280 copy 4 bytes from SRCPTR to DESTPTR
24281 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24282 goto done_label
24283 }
24284 if (!COUNT)
24285 goto done_label;
24286 copy 1 byte from SRCPTR to DESTPTR
24287 if (COUNT & 2)
24288 {
24289 copy 2 bytes from SRCPTR to DESTPTR
24290 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24291 }
24292 }
24293 else
24294 {
24295 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24296 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24298 OLD_DESPTR = DESTPTR;
24299 Align DESTPTR up to DESIRED_ALIGN
24300 SRCPTR += DESTPTR - OLD_DESTPTR
24301 COUNT -= DEST_PTR - OLD_DESTPTR
24302 if (DYNAMIC_CHECK)
24303 Round COUNT down to multiple of SIZE
24304 << optional caller supplied zero size guard is here >>
24305 << optional caller suppplied dynamic check is here >>
24306 << caller supplied main copy loop is here >>
24307 }
24308 done_label:
24309 */
24310 static void
24313 machine_mode mode,
24323 {
24326 rtx modesize;
24328 rtx mode_value;
24330 /* Chose proper value to copy. */
24333 else
24337 /* See if block is big or small, handle small blocks. */
24339 {
24350 /* Handle sizes > 3. */
24357 /* Nothing to copy? Jump to DONE_LABEL if so */
24361 /* Do a byte copy. */
24365 else
24366 {
24369 }
24371 /* Handle sizes 2 and 3. */
24378 else
24379 {
24384 }
24390 }
24391 else
24395 /* Start memcpy for COUNT >= SIZE. */
24397 {
24400 }
24402 /* Copy first desired_align bytes. */
24408 {
24411 else
24412 {
24415 }
24418 }
24421 /* Copy last SIZE bytes. */
24428 else
24429 {
24435 }
24437 {
24441 else
24442 {
24445 }
24446 }
24448 /* Align destination. */
24450 {
24454 /* Align destptr up, place it to new register. */
24463 /* See how many bytes we skipped. */
24467 /* Adjust srcptr and count. */
24473 /* We copied at most size + prolog_size. */
24476 else
24479 /* Our loops always round down the bock size, but for dispatch to library
24480 we need precise value. */
24484 }
24485 else
24486 {
24488 /* Decrease count, so we won't end up copying last word twice. */
24492 else
24496 }
24497 }
24500 /* This function is like the previous one, except here we know how many bytes
24501 need to be copied. That allows us to update alignment not only of DST, which
24502 is returned, but also of SRC, which is passed as a pointer for that
24503 reason. */
24504 static rtx
24509 {
24517 {
24521 }
24526 {
24528 {
24530 {
24533 else
24535 }
24536 else
24539 }
24540 }
24547 {
24553 {
24556 {
24560 }
24565 }
24569 }
24572 }
24574 /* Return true if ALG can be used in current context.
24575 Assume we expand memset if MEMSET is true. */
24576 static bool
24578 {
24583 /* Algorithms using the rep prefix want at least edi and ecx;
24584 additionally, memset wants eax and memcpy wants esi. Don't
24585 consider such algorithms if the user has appropriated those
24586 registers for their own purposes. */
24593 }
24595 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24596 static enum stringop_alg
24600 {
24611 /* Even if the string operation call is cold, we still might spend a lot
24612 of time processing large blocks. */
24618 else
24624 else
24627 /* See maximal size for user defined algorithm. */
24629 {
24636 }
24638 /* If expected size is not known but max size is small enough
24639 so inline version is a win, set expected size into
24640 the range. */
24645 /* If user specified the algorithm, honnor it if possible. */
24649 /* rep; movq or rep; movl is the smallest variant. */
24651 {
24656 else
24659 }
24660 /* Very tiny blocks are best handled via the loop, REP is expensive to
24661 setup. */
24665 {
24669 {
24670 /* We get here if the algorithms that were not libcall-based
24671 were rep-prefix based and we are unable to use rep prefixes
24672 based on global register usage. Break out of the loop and
24673 use the heuristic below. */
24677 {
24681 {
24684 }
24685 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24686 last non-libcall inline algorithm. */
24688 {
24689 /* When the current size is best to be copied by a libcall,
24690 but we are still forced to inline, run the heuristic below
24691 that will pick code for medium sized blocks. */
24693 {
24696 }
24699 }
24701 {
24704 }
24705 }
24706 }
24707 }
24708 /* When asked to inline the call anyway, try to pick meaningful choice.
24709 We look for maximal size of block that is faster to copy by hand and
24710 take blocks of at most of that size guessing that average size will
24711 be roughly half of the block.
24713 If this turns out to be bad, we might simply specify the preferred
24714 choice in ix86_costs. */
24718 {
24721 /* If there aren't any usable algorithms, then recursing on
24722 smaller sizes isn't going to find anything. Just return the
24723 simple byte-at-a-time copy loop. */
24725 {
24726 /* Pick something reasonable. */
24730 }
24738 else
24741 }
24744 }
24746 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24747 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24748 static int
24752 machine_mode move_mode)
24753 {
24764 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24765 copying whole cacheline at once. */
24778 }
24781 /* Helper function for memcpy. For QImode value 0xXY produce
24782 0xXYXYXYXY of wide specified by MODE. This is essentially
24783 a * 0x10101010, but we can do slightly better than
24784 synth_mult by unwinding the sequence by hand on CPUs with
24785 slow multiply. */
24786 static rtx
24788 {
24790 rtx tmp;
24797 {
24805 }
24814 nops--;
24819 {
24823 OPTAB_DIRECT);
24824 }
24825 else
24826 {
24832 else
24834 else
24835 {
24838 reg =
24840 }
24850 }
24851 }
24853 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24854 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24855 alignment from ALIGN to DESIRED_ALIGN. */
24856 static rtx
24859 {
24860 rtx promoted_val;
24869 else
24873 }
24875 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24876 operations when profitable. The code depends upon architecture, block size
24877 and alignment, but always has one of the following overall structures:
24879 Aligned move sequence:
24881 1) Prologue guard: Conditional that jumps up to epilogues for small
24882 blocks that can be handled by epilogue alone. This is faster
24883 but also needed for correctness, since prologue assume the block
24884 is larger than the desired alignment.
24886 Optional dynamic check for size and libcall for large
24887 blocks is emitted here too, with -minline-stringops-dynamically.
24889 2) Prologue: copy first few bytes in order to get destination
24890 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24891 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24892 copied. We emit either a jump tree on power of two sized
24893 blocks, or a byte loop.
24895 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24896 with specified algorithm.
24898 4) Epilogue: code copying tail of the block that is too small to be
24899 handled by main body (or up to size guarded by prologue guard).
24901 Misaligned move sequence
24903 1) missaligned move prologue/epilogue containing:
24904 a) Prologue handling small memory blocks and jumping to done_label
24905 (skipped if blocks are known to be large enough)
24906 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24907 needed by single possibly misaligned move
24908 (skipped if alignment is not needed)
24909 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24911 2) Zero size guard dispatching to done_label, if needed
24913 3) dispatch to library call, if needed,
24915 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24916 with specified algorithm. */
24917 bool
24923 {
24924 rtx destreg;
24927 rtx tmp;
24943 /* TODO: Once value ranges are available, fill in proper data. */
24951 /* i386 can do misaligned access on reasonably increased cost. */
24955 /* ALIGN is the minimum of destination and source alignment, but we care here
24956 just about destination alignment. */
24962 {
24965 /* When COUNT is 0, there is nothing to do. */
24968 }
24969 else
24970 {
24979 }
24981 /* Make sure we don't need to care about overflow later on. */
24985 /* Step 0: Decide on preferred algorithm, desired alignment and
24986 size of chunks to be copied by main loop. */
24988 issetmem,
24995 /* For now vector-version of memset is generated only for memory zeroing, as
24996 creating of promoted vector value is very cheap in this case. */
25009 {
25028 /* Find the widest supported mode. */
25034 /* Find the corresponding vector mode with the same size as MOVE_MODE.
25035 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
25037 {
25042 }
25054 }
25062 /* Step 1: Prologue guard. */
25064 /* Alignment code needs count to be in register. */
25066 {
25069 {
25070 align_bytes
25074 else
25076 }
25079 }
25082 /* Misaligned move sequences handle both prologue and epilogue at once.
25083 Default code generation results in a smaller code for large alignments
25084 and also avoids redundant job when sizes are known precisely. */
25085 misaligned_prologue_used
25086 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
25092 /* Do the cheap promotion to allow better CSE across the
25093 main loop and epilogue (ie one load of the big constant in the
25094 front of all code.
25095 For now the misaligned move sequences do not have fast path
25096 without broadcasting. */
25098 {
25100 {
25106 }
25107 else
25108 {
25111 }
25112 }
25113 /* Misaligned move sequences handles both prologues and epilogues at once.
25114 Default code generation results in smaller code for large alignments and
25115 also avoids redundant job when sizes are known precisely. */
25117 {
25118 /* Misaligned move prologue handled small blocks by itself. */
25119 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
25124 desired_align < align
25134 {
25135 /* It is possible that we copied enough so the main loop will not
25136 execute. */
25146 else
25148 }
25149 }
25150 /* Ensure that alignment prologue won't copy past end of block. */
25152 {
25154 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
25155 Make sure it is power of 2. */
25158 /* To improve performance of small blocks, we jump around the VAL
25159 promoting mode. This mean that if the promoted VAL is not constant,
25160 we might not use it in the epilogue and have to use byte
25161 loop variant. */
25166 {
25167 /* If main algorithm works on QImode, no epilogue is needed.
25168 For small sizes just don't align anything. */
25171 else
25173 }
25176 {
25183 else
25185 }
25186 }
25188 /* Emit code to decide on runtime whether library call or inline should be
25189 used. */
25191 {
25193 {
25195 {
25199 }
25200 }
25201 else
25202 {
25212 else
25216 }
25217 }
25219 /* Step 2: Alignment prologue. */
25220 /* Do the expensive promotion once we branched off the small blocks. */
25226 {
25228 {
25229 /* Except for the first move in prologue, we no longer know
25230 constant offset in aliasing info. It don't seems to worth
25231 the pain to maintain it for the first move, so throw away
25232 the info early. */
25239 issetmem);
25240 /* At most desired_align - align bytes are copied. */
25243 else
25245 }
25246 else
25247 {
25248 /* If we know how many bytes need to be stored before dst is
25249 sufficiently aligned, maintain aliasing info accurately. */
25251 srcreg,
25252 promoted_val,
25253 vec_promoted_val,
25254 desired_align,
25255 align_bytes,
25256 issetmem);
25263 }
25270 {
25271 /* It is possible that we copied enough so the main loop will not
25272 execute. */
25282 else
25284 }
25285 }
25287 {
25294 }
25298 /* Step 3: Main loop. */
25301 {
25324 }
25325 /* Adjust properly the offset of src and dest memory for aliasing. */
25327 {
25333 }
25334 else
25335 {
25339 }
25341 /* Step 4: Epilogue to copy the remaining bytes. */
25342 epilogue:
25344 {
25345 /* When the main loop is done, COUNT_EXP might hold original count,
25346 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25347 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25348 bytes. Compensate if needed. */
25351 {
25352 tmp =
25355 OPTAB_DIRECT);
25358 }
25361 }
25364 {
25367 epilogue_size_needed);
25368 else
25369 {
25373 epilogue_size_needed);
25374 else
25376 epilogue_size_needed);
25377 }
25378 }
25382 }
25385 /* Expand the appropriate insns for doing strlen if not just doing
25386 repnz; scasb
25388 out = result, initialized with the start address
25389 align_rtx = alignment of the address.
25390 scratch = scratch register, initialized with the startaddress when
25391 not aligned, otherwise undefined
25393 This is just the body. It needs the initializations mentioned above and
25394 some address computing at the end. These things are done in i386.md. */
25396 static void
25398 {
25400 rtx tmp;
25405 rtx mem;
25408 rtx cmp;
25414 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25416 /* Is there a known alignment and is it less than 4? */
25418 {
25421 /* Is there a known alignment and is it not 2? */
25423 {
25427 /* Leave just the 3 lower bits. */
25437 }
25438 else
25439 {
25440 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25441 check if is aligned to 4 - byte. */
25448 }
25452 /* Now compare the bytes. */
25454 /* Compare the first n unaligned byte on a byte per byte basis. */
25458 /* Increment the address. */
25461 /* Not needed with an alignment of 2 */
25463 {
25467 end_0_label);
25472 }
25475 end_0_label);
25478 }
25480 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25481 align this loop. It gives only huge programs, but does not help to
25482 speed up. */
25489 /* This formula yields a nonzero result iff one of the bytes is zero.
25490 This saves three branches inside loop and many cycles. */
25498 align_4_label);
25501 {
25507 /* If zero is not in the first two bytes, move two bytes forward. */
25513 reg,
25514 tmpreg)));
25515 /* Emit lea manually to avoid clobbering of flags. */
25522 reg2,
25523 out)));
25524 }
25525 else
25526 {
25528 /* Is zero in the first two bytes? */
25535 pc_rtx);
25539 /* Not in the first two. Move two bytes forward. */
25545 }
25547 /* Avoid branch in fixing the byte. */
25555 }
25557 /* Expand strlen. */
25559 bool
25561 {
25564 /* The generic case of strlen expander is long. Avoid it's
25565 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25568 && !TARGET_INLINE_ALL_STRINGOPS
25578 {
25579 /* Well it seems that some optimizer does not combine a call like
25580 foo(strlen(bar), strlen(bar));
25581 when the move and the subtraction is done here. It does calculate
25582 the length just once when these instructions are done inside of
25583 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25584 often used and I use one fewer register for the lifetime of
25585 output_strlen_unroll() this is better. */
25591 /* strlensi_unroll_1 returns the address of the zero at the end of
25592 the string, like memchr(), so compute the length by subtracting
25593 the start address. */
25595 }
25596 else
25597 {
25598 rtx unspec;
25600 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25613 /* If .md starts supporting :P, this can be done in .md. */
25619 }
25621 }
25623 /* For given symbol (function) construct code to compute address of it's PLT
25624 entry in large x86-64 PIC model. */
25625 static rtx
25627 {
25640 }
25642 rtx
25644 rtx callarg2,
25646 {
25656 {
25657 #if TARGET_MACHO
25660 #endif
25661 }
25662 else
25663 {
25664 /* Static functions and indirect calls don't need the pic register. Also,
25665 check if PLT was explicitly avoided via no-plt or "noplt" attribute, making
25666 it an indirect call. */
25668 && (!TARGET_64BIT
25673 && flag_plt
25677 {
25681 pic_offset_table_rtx);
25682 }
25683 }
25685 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25686 parameters passed in vector registers. */
25691 {
25695 }
25698 && !TARGET_PECOFF
25706 {
25709 }
25714 {
25715 /* We should add bounds as destination register in case
25716 pointer with bounds may be returned. */
25718 {
25722 {
25727 }
25728 else
25729 {
25733 }
25734 }
25737 }
25741 {
25745 }
25749 {
25750 int const cregs_size
25755 {
25760 }
25761 }
25770 }
25772 /* Return true if the function being called was marked with attribute "noplt"
25773 or using -fno-plt and we are compiling for non-PIC and x86_64. We need to
25774 handle the non-PIC case in the backend because there is no easy interface
25775 for the front-end to force non-PLT calls to use the GOT. This is currently
25776 used only with 64-bit ELF targets to call the function marked "noplt"
25777 indirectly. */
25779 static bool
25781 {
25795 }
25797 /* Output the assembly for a call instruction. */
25801 {
25807 {
25812 /* SEH epilogue detection requires the indirect branch case
25813 to include REX.W. */
25816 else
25821 }
25823 /* SEH unwinding can require an extra nop to be emitted in several
25824 circumstances. Determine if we have one of those. */
25826 {
25830 {
25831 /* If we get to another real insn, we don't need the nop. */
25835 /* If we get to the epilogue note, prevent a catch region from
25836 being adjacent to the standard epilogue sequence. If non-
25837 call-exceptions, we'll have done this during epilogue emission. */
25839 && !flag_non_call_exceptions
25841 {
25844 }
25845 }
25847 /* If we didn't find a real insn following the call, prevent the
25848 unwinder from looking into the next function. */
25851 }
25857 else
25866 }
25867 \f
25868 /* Clear stack slot assignments remembered from previous functions.
25869 This is called from INIT_EXPANDERS once before RTL is emitted for each
25870 function. */
25874 {
25882 }
25884 /* Return a MEM corresponding to a stack slot with mode MODE.
25885 Allocate a new slot if necessary.
25887 The RTL for a function can have several slots available: N is
25888 which slot to use. */
25890 rtx
25892 {
25909 }
25911 static void
25913 {
25919 }
25920 \f
25921 /* Check whether x86 address PARTS is a pc-relative address. */
25923 static bool
25925 {
25933 {
25935 {
25952 }
25953 }
25955 }
25957 /* Calculate the length of the memory address in the instruction encoding.
25958 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25959 or other prefixes. We never generate addr32 prefix for LEA insn. */
25961 int
25963 {
25980 /* If this is not LEA instruction, add the length of addr32 prefix. */
25985 len++;
25999 /* Rule of thumb:
26000 - esp as the base always wants an index,
26001 - ebp as the base always wants a displacement,
26002 - r12 as the base always wants an index,
26003 - r13 as the base always wants a displacement. */
26005 /* Register Indirect. */
26007 {
26008 /* esp (for its index) and ebp (for its displacement) need
26009 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
26010 code. */
26017 len++;
26018 }
26020 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
26021 is not disp32, but disp32(%rip), so for disp32
26022 SIB byte is needed, unless print_operand_address
26023 optimizes it into disp32(%rip) or (%rip) is implied
26024 by UNSPEC. */
26026 {
26029 len++;
26030 }
26031 else
26032 {
26033 /* Find the length of the displacement constant. */
26035 {
26038 else
26040 }
26041 /* ebp always wants a displacement. Similarly r13. */
26043 len++;
26045 /* An index requires the two-byte modrm form.... */
26047 /* ...like esp (or r12), which always wants an index. */
26051 len++;
26052 }
26055 }
26057 /* Compute default value for "length_immediate" attribute. When SHORTFORM
26058 is set, expect that insn have 8bit immediate alternative. */
26059 int
26061 {
26067 {
26072 {
26075 {
26087 }
26089 {
26092 }
26093 }
26095 {
26105 /* Immediates for DImode instructions are encoded
26106 as 32bit sign extended values. */
26112 }
26113 }
26115 }
26117 /* Compute default value for "length_address" attribute. */
26118 int
26120 {
26124 {
26135 }
26140 {
26143 {
26148 constraints++;
26151 ;
26152 /* Skip ignored operands. */
26155 }
26157 }
26159 }
26161 /* Compute default value for "length_vex" attribute. It includes
26162 2 or 3 byte VEX prefix and 1 opcode byte. */
26164 int
26167 {
26170 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
26171 byte VEX prefix. */
26175 /* We can always use 2 byte VEX prefix in 32bit. */
26183 {
26184 /* REX.W bit uses 3 byte VEX prefix. */
26188 }
26189 else
26190 {
26191 /* REX.X or REX.B bits use 3 byte VEX prefix. */
26195 }
26198 }
26199 \f
26200 /* Return the maximum number of instructions a cpu can issue. */
26202 static int
26204 {
26206 {
26239 }
26240 }
26242 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26243 by DEP_INSN and nothing set by DEP_INSN. */
26245 static bool
26247 {
26250 /* Simplify the test for uninteresting insns. */
26258 {
26261 }
26266 {
26269 }
26270 else
26276 /* This test is true if the dependent insn reads the flags but
26277 not any other potentially set register. */
26285 }
26287 /* Return true iff USE_INSN has a memory address with operands set by
26288 SET_INSN. */
26290 bool
26292 {
26297 {
26300 }
26302 }
26304 /* Helper function for exact_store_load_dependency.
26305 Return true if addr is found in insn. */
26306 static bool
26308 {
26315 {
26321 CASE_CONST_ANY:
26330 }
26334 {
26336 {
26346 }
26347 }
26349 }
26351 /* Return true if there exists exact dependency for store & load, i.e.
26352 the same memory address is used in them. */
26353 static bool
26355 {
26369 }
26371 static int
26373 {
26379 /* Anti and output dependencies have zero cost on all CPUs. */
26385 /* If we can't recognize the insns, we can't really do anything. */
26393 {
26396 /* Address Generation Interlock adds a cycle of latency. */
26398 {
26409 }
26413 /* ??? Compares pair with jump/setcc. */
26417 /* Floating point stores require value to be ready one cycle earlier. */
26425 /* INT->FP conversion is expensive. */
26429 /* There is one cycle extra latency between an FP op and a store. */
26439 /* Show ability of reorder buffer to hide latency of load by executing
26440 in parallel with previous instruction in case
26441 previous instruction is not needed to compute the address. */
26444 {
26445 /* Claim moves to take one cycle, as core can issue one load
26446 at time and the next load can start cycle later. */
26451 cost--;
26452 }
26456 /* The esp dependency is resolved before
26457 the instruction is really finished. */
26462 /* INT->FP conversion is expensive. */
26468 /* Show ability of reorder buffer to hide latency of load by executing
26469 in parallel with previous instruction in case
26470 previous instruction is not needed to compute the address. */
26473 {
26474 /* Claim moves to take one cycle, as core can issue one load
26475 at time and the next load can start cycle later. */
26481 else
26483 }
26494 /* Stack engine allows to execute push&pop instructions in parall. */
26498 /* FALLTHRU */
26504 /* Show ability of reorder buffer to hide latency of load by executing
26505 in parallel with previous instruction in case
26506 previous instruction is not needed to compute the address. */
26509 {
26513 /* Because of the difference between the length of integer and
26514 floating unit pipeline preparation stages, the memory operands
26515 for floating point are cheaper.
26517 ??? For Athlon it the difference is most probably 2. */
26520 else
26525 else
26527 }
26534 /* Stack engine allows to execute push&pop instructions in parall. */
26541 /* Show ability of reorder buffer to hide latency of load by executing
26542 in parallel with previous instruction in case
26543 previous instruction is not needed to compute the address. */
26546 {
26549 else
26551 }
26560 /* Increase cost of integer loads. */
26563 {
26566 {
26569 else
26570 {
26571 /* Increase cost of ld/st for short int types only
26572 because of store forwarding issue. */
26576 {
26577 /* Increase cost of store/load insn if exact
26578 dependence exists and it is load insn. */
26583 }
26584 }
26585 }
26586 }
26590 }
26593 }
26595 /* How many alternative schedules to try. This should be as wide as the
26596 scheduling freedom in the DFA, but no wider. Making this value too
26597 large results extra work for the scheduler. */
26599 static int
26601 {
26603 {
26616 /* We use lookahead value 4 for BD both before and after reload
26617 schedules. Plan is to have value 8 included for O3. */
26628 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26629 as many instructions can be executed on a cycle, i.e.,
26630 issue_rate. I wonder why tuning for many CPUs does not do this. */
26633 /* Don't use lookahead for pre-reload schedule to save compile time. */
26638 }
26639 }
26641 /* Return true if target platform supports macro-fusion. */
26643 static bool
26645 {
26647 }
26649 /* Check whether current microarchitecture support macro fusion
26650 for insn pair "CONDGEN + CONDJMP". Refer to
26651 "Intel Architectures Optimization Reference Manual". */
26653 static bool
26655 {
26676 {
26681 {
26685 else
26687 }
26688 }
26695 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26696 supported. */
26703 /* No fusion for RIP-relative address. */
26710 ix86_address parts;
26716 }
26721 /* Check whether conditional jump use Sign or Overflow Flags. */
26729 /* Return true for TYPE_TEST and TYPE_ICMP. */
26734 /* The following is the case that macro-fusion for alu + jmp. */
26738 /* No fusion for alu op with memory destination operand. */
26743 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26744 supported. */
26753 }
26755 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26756 execution. It is applied if
26757 (1) IMUL instruction is on the top of list;
26758 (2) There exists the only producer of independent IMUL instruction in
26759 ready list.
26760 Return index of IMUL producer if it was found and -1 otherwise. */
26761 static int
26763 {
26766 sd_iterator_def sd_it;
26767 dep_t dep;
26774 /* Check that IMUL instruction is on the top of ready list. */
26783 /* Search for producer of independent IMUL instruction. */
26785 {
26789 /* Skip IMUL instruction. */
26799 {
26800 rtx con;
26811 {
26812 sd_iterator_def sd_it1;
26813 dep_t dep1;
26814 /* Check if there is no other dependee for IMUL. */
26817 {
26818 rtx pro;
26824 }
26827 }
26828 }
26831 }
26833 }
26835 /* Try to find the best candidate on the top of ready list if two insns
26836 have the same priority - candidate is best if its dependees were
26837 scheduled earlier. Applied for Silvermont only.
26838 Return true if top 2 insns must be interchanged. */
26839 static bool
26841 {
26844 rtx set;
26845 sd_iterator_def sd_it;
26846 dep_t dep;
26849 #define INSN_TICK(INSN) (HID (INSN)->tick)
26870 {
26873 /* Determine winner more precise. */
26875 {
26876 rtx pro;
26882 }
26884 {
26885 rtx pro;
26891 }
26894 {
26895 /* Determine winner - load must win. */
26901 }
26903 }
26905 #undef INSN_TICK
26906 }
26908 /* Perform possible reodering of ready list for Atom/Silvermont only.
26909 Return issue rate. */
26910 static int
26913 {
26920 /* Set up issue rate. */
26923 /* Do reodering for BONNELL/SILVERMONT only. */
26927 /* Nothing to do if ready list contains only 1 instruction. */
26931 /* Do reodering for post-reload scheduler only. */
26936 {
26941 /* Put IMUL producer (ready[index]) at the top of ready list. */
26947 }
26949 /* Skip selective scheduling since HID is not populated in it. */
26953 {
26957 /* Swap 2 top elements of ready list. */
26961 }
26963 }
26965 static bool
26968 /* Returns true if lhs of insn is HW function argument register and set up
26969 is_spilled to true if it is likely spilled HW register. */
26970 static bool
26972 {
26973 rtx dst;
26977 /* Call instructions are not movable, ignore it. */
26988 {
26989 /* Is it likely spilled HW register? */
26994 }
26996 }
26998 /* Add output dependencies for chain of function adjacent arguments if only
26999 there is a move to likely spilled HW register. Return first argument
27000 if at least one dependence was added or NULL otherwise. */
27003 {
27011 /* Find nearest to call argument passing instruction. */
27013 {
27022 }
27026 {
27033 {
27036 }
27038 {
27039 /* Add output depdendence between two function arguments if chain
27040 of output arguments contains likely spilled HW registers. */
27044 }
27045 else
27047 }
27051 }
27053 /* Add output or anti dependency from insn to first_arg to restrict its code
27054 motion. */
27055 static void
27057 {
27058 rtx set;
27059 rtx tmp;
27061 /* Add anti dependencies for bounds stores. */
27066 {
27069 }
27076 {
27077 /* Add output dependency to the first function argument. */
27080 }
27081 /* Add anti dependency. */
27083 }
27085 /* Avoid cross block motion of function argument through adding dependency
27086 from the first non-jump instruction in bb. */
27087 static void
27089 {
27093 {
27095 {
27098 {
27101 }
27102 }
27106 }
27107 }
27109 /* Hook for pre-reload schedule - avoid motion of function arguments
27110 passed in likely spilled HW registers. */
27111 static void
27113 {
27122 {
27125 {
27126 /* Add dependee for first argument to predecessors if only
27127 region contains more than one block. */
27131 /* Skip trivial regions and region head blocks that can have
27132 predecessors outside of region. */
27134 {
27135 edge e;
27136 edge_iterator ei;
27138 /* Regions are SCCs with the exception of selective
27139 scheduling with pipelining of outer blocks enabled.
27140 So also check that immediate predecessors of a non-head
27141 block are in the same region. */
27143 {
27144 /* Avoid creating of loop-carried dependencies through
27145 using topological ordering in the region. */
27149 }
27150 }
27154 }
27155 }
27158 }
27160 /* Hook for pre-reload schedule - set priority of moves from likely spilled
27161 HW registers to maximum, to schedule them at soon as possible. These are
27162 moves from function argument registers at the top of the function entry
27163 and moves from function return value registers after call. */
27164 static int
27166 {
27167 rtx set;
27177 {
27184 }
27187 }
27189 /* Model decoder of Core 2/i7.
27190 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
27191 track the instruction fetch block boundaries and make sure that long
27192 (9+ bytes) instructions are assigned to D0. */
27194 /* Maximum length of an insn that can be handled by
27195 a secondary decoder unit. '8' for Core 2/i7. */
27198 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
27199 '16' for Core 2/i7. */
27202 /* Maximum number of instructions decoder can handle per cycle.
27203 '6' for Core 2/i7. */
27207 ix86_first_cycle_multipass_data_t;
27209 const_ix86_first_cycle_multipass_data_t;
27211 /* A variable to store target state across calls to max_issue within
27212 one cycle. */
27216 /* Initialize DATA. */
27217 static void
27219 {
27220 ix86_first_cycle_multipass_data_t data
27227 }
27229 /* Advancing the cycle; reset ifetch block counts. */
27230 static void
27232 {
27239 }
27243 /* Filter out insns from ready_try that the core will not be able to issue
27244 on current cycle due to decoder. */
27245 static void
27246 core2i7_first_cycle_multipass_filter_ready_try
27249 {
27251 {
27262 (!first_cycle_insn_p
27264 /* ... or it would not fit into the ifetch block ... */
27266 /* ... or the decoder is full already ... */
27268 /* ... mask the insn out. */
27269 {
27274 }
27275 }
27276 }
27278 /* Prepare for a new round of multipass lookahead scheduling. */
27279 static void
27283 {
27284 ix86_first_cycle_multipass_data_t data
27286 const_ix86_first_cycle_multipass_data_t prev_data
27289 /* Restore the state from the end of the previous round. */
27293 /* Filter instructions that cannot be issued on current cycle due to
27294 decoder restrictions. */
27296 first_cycle_insn_p);
27297 }
27299 /* INSN is being issued in current solution. Account for its impact on
27300 the decoder model. */
27301 static void
27305 {
27306 ix86_first_cycle_multipass_data_t data
27308 const_ix86_first_cycle_multipass_data_t prev_data
27318 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27320 {
27323 }
27325 {
27329 }
27332 /* Filter out insns from ready_try that the core will not be able to issue
27333 on current cycle due to decoder. */
27336 }
27338 /* Revert the effect on ready_try. */
27339 static void
27343 {
27344 const_ix86_first_cycle_multipass_data_t data
27347 sbitmap_iterator sbi;
27351 {
27353 }
27354 }
27356 /* Save the result of multipass lookahead scheduling for the next round. */
27357 static void
27359 {
27360 const_ix86_first_cycle_multipass_data_t data
27362 ix86_first_cycle_multipass_data_t next_data
27366 {
27369 }
27370 }
27372 /* Deallocate target data. */
27373 static void
27375 {
27376 ix86_first_cycle_multipass_data_t data
27380 {
27384 }
27385 }
27387 /* Prepare for scheduling pass. */
27388 static void
27390 {
27391 /* Install scheduling hooks for current CPU. Some of these hooks are used
27392 in time-critical parts of the scheduler, so we only set them up when
27393 they are actually used. */
27395 {
27400 /* Do not perform multipass scheduling for pre-reload schedule
27401 to save compile time. */
27403 {
27419 /* Set decoder parameters. */
27424 }
27425 /* ... Fall through ... */
27435 }
27436 }
27438 \f
27439 /* Compute the alignment given to a constant that is being placed in memory.
27440 EXP is the constant and ALIGN is the alignment that the object would
27441 ordinarily have.
27442 The value of this function is used instead of that alignment to align
27443 the object. */
27445 int
27447 {
27450 {
27455 }
27461 }
27463 /* Compute the alignment for a variable for Intel MCU psABI. TYPE is
27464 the data type, and ALIGN is the alignment that the object would
27465 ordinarily have. */
27467 static int
27469 {
27475 /* Intel MCU psABI specifies scalar types > 4 bytes aligned to 4
27476 bytes. */
27479 {
27488 }
27489 }
27491 /* Compute the alignment for a static variable.
27492 TYPE is the data type, and ALIGN is the alignment that
27493 the object would ordinarily have. The value of this function is used
27494 instead of that alignment to align the object. */
27496 int
27498 {
27499 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27500 for symbols from other compilation units or symbols that don't need
27501 to bind locally. In order to preserve some ABI compatibility with
27502 those compilers, ensure we don't decrease alignment from what we
27503 used to assume. */
27507 /* A data structure, equal or greater than the size of a cache line
27508 (64 bytes in the Pentium 4 and other recent Intel processors, including
27509 processors based on Intel Core microarchitecture) should be aligned
27510 so that its base address is a multiple of a cache line size. */
27512 int max_align
27519 {
27523 }
27532 {
27539 }
27541 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27542 to 16byte boundary. */
27544 {
27551 }
27557 {
27562 }
27564 {
27571 }
27576 {
27581 }
27584 {
27589 }
27592 }
27594 /* Compute the alignment for a local variable or a stack slot. EXP is
27595 the data type or decl itself, MODE is the widest mode available and
27596 ALIGN is the alignment that the object would ordinarily have. The
27597 value of this macro is used instead of that alignment to align the
27598 object. */
27600 unsigned int
27603 {
27607 {
27610 }
27611 else
27612 {
27615 }
27617 /* Don't do dynamic stack realignment for long long objects with
27618 -mpreferred-stack-boundary=2. */
27627 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27628 register in MODE. We will return the largest alignment of XF
27629 and DF. */
27631 {
27635 }
27637 /* Don't increase alignment for Intel MCU psABI. */
27641 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27642 to 16byte boundary. Exact wording is:
27644 An array uses the same alignment as its elements, except that a local or
27645 global array variable of length at least 16 bytes or
27646 a C99 variable-length array variable always has alignment of at least 16 bytes.
27648 This was added to allow use of aligned SSE instructions at arrays. This
27649 rule is meant for static storage (where compiler can not do the analysis
27650 by itself). We follow it for automatic variables only when convenient.
27651 We fully control everything in the function compiled and functions from
27652 other unit can not rely on the alignment.
27654 Exclude va_list type. It is the common case of local array where
27655 we can not benefit from the alignment.
27657 TODO: Probably one should optimize for size only when var is not escaping. */
27660 {
27670 }
27672 {
27677 }
27679 {
27685 }
27690 {
27695 }
27698 {
27704 }
27706 }
27708 /* Compute the minimum required alignment for dynamic stack realignment
27709 purposes for a local variable, parameter or a stack slot. EXP is
27710 the data type or decl itself, MODE is its mode and ALIGN is the
27711 alignment that the object would ordinarily have. */
27713 unsigned int
27716 {
27720 {
27723 }
27724 else
27725 {
27728 }
27733 /* Don't do dynamic stack realignment for long long objects with
27734 -mpreferred-stack-boundary=2. */
27741 }
27742 \f
27743 /* Find a location for the static chain incoming to a nested function.
27744 This is a register, unless all free registers are used by arguments. */
27746 static rtx
27748 {
27751 /* While this function won't be called by the middle-end when a static
27752 chain isn't needed, it's also used throughout the backend so it's
27753 easiest to keep this check centralized. */
27758 {
27759 /* We always use R10 in 64-bit mode. */
27761 }
27762 else
27763 {
27767 /* By default in 32-bit mode we use ECX to pass the static chain. */
27771 {
27774 }
27775 else
27776 {
27779 }
27783 {
27784 /* Fastcall functions use ecx/edx for arguments, which leaves
27785 us with EAX for the static chain.
27786 Thiscall functions use ecx for arguments, which also
27787 leaves us with EAX for the static chain. */
27789 }
27791 {
27792 /* Thiscall functions use ecx for arguments, which leaves
27793 us with EAX and EDX for the static chain.
27794 We are using for abi-compatibility EAX. */
27796 }
27798 {
27799 /* For regparm 3, we have no free call-clobbered registers in
27800 which to store the static chain. In order to implement this,
27801 we have the trampoline push the static chain to the stack.
27802 However, we can't push a value below the return address when
27803 we call the nested function directly, so we have to use an
27804 alternate entry point. For this we use ESI, and have the
27805 alternate entry point push ESI, so that things appear the
27806 same once we're executing the nested function. */
27808 {
27814 }
27816 }
27817 }
27820 }
27822 /* Emit RTL insns to initialize the variable parts of a trampoline.
27823 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27824 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27825 to be passed to the target function. */
27827 static void
27829 {
27837 {
27840 /* Load the function address to r11. Try to load address using
27841 the shorter movl instead of movabs. We may want to support
27842 movq for kernel mode, but kernel does not use trampolines at
27843 the moment. FNADDR is a 32bit address and may not be in
27844 DImode when ptr_mode == SImode. Always use movl in this
27845 case. */
27848 {
27857 }
27858 else
27859 {
27866 }
27868 /* Load static chain using movabs to r10. Use the shorter movl
27869 instead of movabs when ptr_mode == SImode. */
27871 {
27874 }
27875 else
27876 {
27879 }
27888 /* Jump to r11; the last (unused) byte is a nop, only there to
27889 pad the write out to a single 32-bit store. */
27893 }
27894 else
27895 {
27898 /* Depending on the static chain location, either load a register
27899 with a constant, or push the constant to the stack. All of the
27900 instructions are the same size. */
27903 {
27905 {
27912 }
27913 }
27914 else
27929 /* Compute offset from the end of the jmp to the target function.
27930 In the case in which the trampoline stores the static chain on
27931 the stack, we need to skip the first insn which pushes the
27932 (call-saved) register static chain; this push is 1 byte. */
27939 }
27943 #ifdef HAVE_ENABLE_EXECUTE_STACK
27944 #ifdef CHECK_EXECUTE_STACK_ENABLED
27946 #endif
27949 #endif
27950 }
27951 \f
27952 /* The following file contains several enumerations and data structures
27953 built from the definitions in i386-builtin-types.def. */
27957 /* Table for the ix86 builtin non-function types. */
27960 /* Retrieve an element from the above table, building some of
27961 the types lazily. */
27963 static tree
27965 {
27977 {
27978 machine_mode mode;
27985 }
27986 else
27987 {
27993 else
28001 }
28005 }
28007 /* Table for the ix86 builtin function types. */
28010 /* Retrieve an element from the above table, building some of
28011 the types lazily. */
28013 static tree
28015 {
28016 tree type;
28025 {
28033 {
28036 }
28039 }
28040 else
28041 {
28047 }
28051 }
28054 /* Codes for all the SSE/MMX builtins. */
28055 enum ix86_builtins
28056 {
28057 IX86_BUILTIN_ADDPS,
28058 IX86_BUILTIN_ADDSS,
28059 IX86_BUILTIN_DIVPS,
28060 IX86_BUILTIN_DIVSS,
28061 IX86_BUILTIN_MULPS,
28062 IX86_BUILTIN_MULSS,
28063 IX86_BUILTIN_SUBPS,
28064 IX86_BUILTIN_SUBSS,
28066 IX86_BUILTIN_CMPEQPS,
28067 IX86_BUILTIN_CMPLTPS,
28068 IX86_BUILTIN_CMPLEPS,
28069 IX86_BUILTIN_CMPGTPS,
28070 IX86_BUILTIN_CMPGEPS,
28071 IX86_BUILTIN_CMPNEQPS,
28072 IX86_BUILTIN_CMPNLTPS,
28073 IX86_BUILTIN_CMPNLEPS,
28074 IX86_BUILTIN_CMPNGTPS,
28075 IX86_BUILTIN_CMPNGEPS,
28076 IX86_BUILTIN_CMPORDPS,
28077 IX86_BUILTIN_CMPUNORDPS,
28078 IX86_BUILTIN_CMPEQSS,
28079 IX86_BUILTIN_CMPLTSS,
28080 IX86_BUILTIN_CMPLESS,
28081 IX86_BUILTIN_CMPNEQSS,
28082 IX86_BUILTIN_CMPNLTSS,
28083 IX86_BUILTIN_CMPNLESS,
28084 IX86_BUILTIN_CMPORDSS,
28085 IX86_BUILTIN_CMPUNORDSS,
28087 IX86_BUILTIN_COMIEQSS,
28088 IX86_BUILTIN_COMILTSS,
28089 IX86_BUILTIN_COMILESS,
28090 IX86_BUILTIN_COMIGTSS,
28091 IX86_BUILTIN_COMIGESS,
28092 IX86_BUILTIN_COMINEQSS,
28093 IX86_BUILTIN_UCOMIEQSS,
28094 IX86_BUILTIN_UCOMILTSS,
28095 IX86_BUILTIN_UCOMILESS,
28096 IX86_BUILTIN_UCOMIGTSS,
28097 IX86_BUILTIN_UCOMIGESS,
28098 IX86_BUILTIN_UCOMINEQSS,
28100 IX86_BUILTIN_CVTPI2PS,
28101 IX86_BUILTIN_CVTPS2PI,
28102 IX86_BUILTIN_CVTSI2SS,
28103 IX86_BUILTIN_CVTSI642SS,
28104 IX86_BUILTIN_CVTSS2SI,
28105 IX86_BUILTIN_CVTSS2SI64,
28106 IX86_BUILTIN_CVTTPS2PI,
28107 IX86_BUILTIN_CVTTSS2SI,
28108 IX86_BUILTIN_CVTTSS2SI64,
28110 IX86_BUILTIN_MAXPS,
28111 IX86_BUILTIN_MAXSS,
28112 IX86_BUILTIN_MINPS,
28113 IX86_BUILTIN_MINSS,
28115 IX86_BUILTIN_LOADUPS,
28116 IX86_BUILTIN_STOREUPS,
28117 IX86_BUILTIN_MOVSS,
28119 IX86_BUILTIN_MOVHLPS,
28120 IX86_BUILTIN_MOVLHPS,
28121 IX86_BUILTIN_LOADHPS,
28122 IX86_BUILTIN_LOADLPS,
28123 IX86_BUILTIN_STOREHPS,
28124 IX86_BUILTIN_STORELPS,
28126 IX86_BUILTIN_MASKMOVQ,
28127 IX86_BUILTIN_MOVMSKPS,
28128 IX86_BUILTIN_PMOVMSKB,
28130 IX86_BUILTIN_MOVNTPS,
28131 IX86_BUILTIN_MOVNTQ,
28133 IX86_BUILTIN_LOADDQU,
28134 IX86_BUILTIN_STOREDQU,
28136 IX86_BUILTIN_PACKSSWB,
28137 IX86_BUILTIN_PACKSSDW,
28138 IX86_BUILTIN_PACKUSWB,
28140 IX86_BUILTIN_PADDB,
28141 IX86_BUILTIN_PADDW,
28142 IX86_BUILTIN_PADDD,
28143 IX86_BUILTIN_PADDQ,
28144 IX86_BUILTIN_PADDSB,
28145 IX86_BUILTIN_PADDSW,
28146 IX86_BUILTIN_PADDUSB,
28147 IX86_BUILTIN_PADDUSW,
28148 IX86_BUILTIN_PSUBB,
28149 IX86_BUILTIN_PSUBW,
28150 IX86_BUILTIN_PSUBD,
28151 IX86_BUILTIN_PSUBQ,
28152 IX86_BUILTIN_PSUBSB,
28153 IX86_BUILTIN_PSUBSW,
28154 IX86_BUILTIN_PSUBUSB,
28155 IX86_BUILTIN_PSUBUSW,
28157 IX86_BUILTIN_PAND,
28158 IX86_BUILTIN_PANDN,
28159 IX86_BUILTIN_POR,
28160 IX86_BUILTIN_PXOR,
28162 IX86_BUILTIN_PAVGB,
28163 IX86_BUILTIN_PAVGW,
28165 IX86_BUILTIN_PCMPEQB,
28166 IX86_BUILTIN_PCMPEQW,
28167 IX86_BUILTIN_PCMPEQD,
28168 IX86_BUILTIN_PCMPGTB,
28169 IX86_BUILTIN_PCMPGTW,
28170 IX86_BUILTIN_PCMPGTD,
28172 IX86_BUILTIN_PMADDWD,
28174 IX86_BUILTIN_PMAXSW,
28175 IX86_BUILTIN_PMAXUB,
28176 IX86_BUILTIN_PMINSW,
28177 IX86_BUILTIN_PMINUB,
28179 IX86_BUILTIN_PMULHUW,
28180 IX86_BUILTIN_PMULHW,
28181 IX86_BUILTIN_PMULLW,
28183 IX86_BUILTIN_PSADBW,
28184 IX86_BUILTIN_PSHUFW,
28186 IX86_BUILTIN_PSLLW,
28187 IX86_BUILTIN_PSLLD,
28188 IX86_BUILTIN_PSLLQ,
28189 IX86_BUILTIN_PSRAW,
28190 IX86_BUILTIN_PSRAD,
28191 IX86_BUILTIN_PSRLW,
28192 IX86_BUILTIN_PSRLD,
28193 IX86_BUILTIN_PSRLQ,
28194 IX86_BUILTIN_PSLLWI,
28195 IX86_BUILTIN_PSLLDI,
28196 IX86_BUILTIN_PSLLQI,
28197 IX86_BUILTIN_PSRAWI,
28198 IX86_BUILTIN_PSRADI,
28199 IX86_BUILTIN_PSRLWI,
28200 IX86_BUILTIN_PSRLDI,
28201 IX86_BUILTIN_PSRLQI,
28203 IX86_BUILTIN_PUNPCKHBW,
28204 IX86_BUILTIN_PUNPCKHWD,
28205 IX86_BUILTIN_PUNPCKHDQ,
28206 IX86_BUILTIN_PUNPCKLBW,
28207 IX86_BUILTIN_PUNPCKLWD,
28208 IX86_BUILTIN_PUNPCKLDQ,
28210 IX86_BUILTIN_SHUFPS,
28212 IX86_BUILTIN_RCPPS,
28213 IX86_BUILTIN_RCPSS,
28214 IX86_BUILTIN_RSQRTPS,
28215 IX86_BUILTIN_RSQRTPS_NR,
28216 IX86_BUILTIN_RSQRTSS,
28217 IX86_BUILTIN_RSQRTF,
28218 IX86_BUILTIN_SQRTPS,
28219 IX86_BUILTIN_SQRTPS_NR,
28220 IX86_BUILTIN_SQRTSS,
28222 IX86_BUILTIN_UNPCKHPS,
28223 IX86_BUILTIN_UNPCKLPS,
28225 IX86_BUILTIN_ANDPS,
28226 IX86_BUILTIN_ANDNPS,
28227 IX86_BUILTIN_ORPS,
28228 IX86_BUILTIN_XORPS,
28230 IX86_BUILTIN_EMMS,
28231 IX86_BUILTIN_LDMXCSR,
28232 IX86_BUILTIN_STMXCSR,
28233 IX86_BUILTIN_SFENCE,
28235 IX86_BUILTIN_FXSAVE,
28236 IX86_BUILTIN_FXRSTOR,
28237 IX86_BUILTIN_FXSAVE64,
28238 IX86_BUILTIN_FXRSTOR64,
28240 IX86_BUILTIN_XSAVE,
28241 IX86_BUILTIN_XRSTOR,
28242 IX86_BUILTIN_XSAVE64,
28243 IX86_BUILTIN_XRSTOR64,
28245 IX86_BUILTIN_XSAVEOPT,
28246 IX86_BUILTIN_XSAVEOPT64,
28248 IX86_BUILTIN_XSAVEC,
28249 IX86_BUILTIN_XSAVEC64,
28251 IX86_BUILTIN_XSAVES,
28252 IX86_BUILTIN_XRSTORS,
28253 IX86_BUILTIN_XSAVES64,
28254 IX86_BUILTIN_XRSTORS64,
28256 /* 3DNow! Original */
28257 IX86_BUILTIN_FEMMS,
28258 IX86_BUILTIN_PAVGUSB,
28259 IX86_BUILTIN_PF2ID,
28260 IX86_BUILTIN_PFACC,
28261 IX86_BUILTIN_PFADD,
28262 IX86_BUILTIN_PFCMPEQ,
28263 IX86_BUILTIN_PFCMPGE,
28264 IX86_BUILTIN_PFCMPGT,
28265 IX86_BUILTIN_PFMAX,
28266 IX86_BUILTIN_PFMIN,
28267 IX86_BUILTIN_PFMUL,
28268 IX86_BUILTIN_PFRCP,
28269 IX86_BUILTIN_PFRCPIT1,
28270 IX86_BUILTIN_PFRCPIT2,
28271 IX86_BUILTIN_PFRSQIT1,
28272 IX86_BUILTIN_PFRSQRT,
28273 IX86_BUILTIN_PFSUB,
28274 IX86_BUILTIN_PFSUBR,
28275 IX86_BUILTIN_PI2FD,
28276 IX86_BUILTIN_PMULHRW,
28278 /* 3DNow! Athlon Extensions */
28279 IX86_BUILTIN_PF2IW,
28280 IX86_BUILTIN_PFNACC,
28281 IX86_BUILTIN_PFPNACC,
28282 IX86_BUILTIN_PI2FW,
28283 IX86_BUILTIN_PSWAPDSI,
28284 IX86_BUILTIN_PSWAPDSF,
28286 /* SSE2 */
28287 IX86_BUILTIN_ADDPD,
28288 IX86_BUILTIN_ADDSD,
28289 IX86_BUILTIN_DIVPD,
28290 IX86_BUILTIN_DIVSD,
28291 IX86_BUILTIN_MULPD,
28292 IX86_BUILTIN_MULSD,
28293 IX86_BUILTIN_SUBPD,
28294 IX86_BUILTIN_SUBSD,
28296 IX86_BUILTIN_CMPEQPD,
28297 IX86_BUILTIN_CMPLTPD,
28298 IX86_BUILTIN_CMPLEPD,
28299 IX86_BUILTIN_CMPGTPD,
28300 IX86_BUILTIN_CMPGEPD,
28301 IX86_BUILTIN_CMPNEQPD,
28302 IX86_BUILTIN_CMPNLTPD,
28303 IX86_BUILTIN_CMPNLEPD,
28304 IX86_BUILTIN_CMPNGTPD,
28305 IX86_BUILTIN_CMPNGEPD,
28306 IX86_BUILTIN_CMPORDPD,
28307 IX86_BUILTIN_CMPUNORDPD,
28308 IX86_BUILTIN_CMPEQSD,
28309 IX86_BUILTIN_CMPLTSD,
28310 IX86_BUILTIN_CMPLESD,
28311 IX86_BUILTIN_CMPNEQSD,
28312 IX86_BUILTIN_CMPNLTSD,
28313 IX86_BUILTIN_CMPNLESD,
28314 IX86_BUILTIN_CMPORDSD,
28315 IX86_BUILTIN_CMPUNORDSD,
28317 IX86_BUILTIN_COMIEQSD,
28318 IX86_BUILTIN_COMILTSD,
28319 IX86_BUILTIN_COMILESD,
28320 IX86_BUILTIN_COMIGTSD,
28321 IX86_BUILTIN_COMIGESD,
28322 IX86_BUILTIN_COMINEQSD,
28323 IX86_BUILTIN_UCOMIEQSD,
28324 IX86_BUILTIN_UCOMILTSD,
28325 IX86_BUILTIN_UCOMILESD,
28326 IX86_BUILTIN_UCOMIGTSD,
28327 IX86_BUILTIN_UCOMIGESD,
28328 IX86_BUILTIN_UCOMINEQSD,
28330 IX86_BUILTIN_MAXPD,
28331 IX86_BUILTIN_MAXSD,
28332 IX86_BUILTIN_MINPD,
28333 IX86_BUILTIN_MINSD,
28335 IX86_BUILTIN_ANDPD,
28336 IX86_BUILTIN_ANDNPD,
28337 IX86_BUILTIN_ORPD,
28338 IX86_BUILTIN_XORPD,
28340 IX86_BUILTIN_SQRTPD,
28341 IX86_BUILTIN_SQRTSD,
28343 IX86_BUILTIN_UNPCKHPD,
28344 IX86_BUILTIN_UNPCKLPD,
28346 IX86_BUILTIN_SHUFPD,
28348 IX86_BUILTIN_LOADUPD,
28349 IX86_BUILTIN_STOREUPD,
28350 IX86_BUILTIN_MOVSD,
28352 IX86_BUILTIN_LOADHPD,
28353 IX86_BUILTIN_LOADLPD,
28355 IX86_BUILTIN_CVTDQ2PD,
28356 IX86_BUILTIN_CVTDQ2PS,
28358 IX86_BUILTIN_CVTPD2DQ,
28359 IX86_BUILTIN_CVTPD2PI,
28360 IX86_BUILTIN_CVTPD2PS,
28361 IX86_BUILTIN_CVTTPD2DQ,
28362 IX86_BUILTIN_CVTTPD2PI,
28364 IX86_BUILTIN_CVTPI2PD,
28365 IX86_BUILTIN_CVTSI2SD,
28366 IX86_BUILTIN_CVTSI642SD,
28368 IX86_BUILTIN_CVTSD2SI,
28369 IX86_BUILTIN_CVTSD2SI64,
28370 IX86_BUILTIN_CVTSD2SS,
28371 IX86_BUILTIN_CVTSS2SD,
28372 IX86_BUILTIN_CVTTSD2SI,
28373 IX86_BUILTIN_CVTTSD2SI64,
28375 IX86_BUILTIN_CVTPS2DQ,
28376 IX86_BUILTIN_CVTPS2PD,
28377 IX86_BUILTIN_CVTTPS2DQ,
28379 IX86_BUILTIN_MOVNTI,
28380 IX86_BUILTIN_MOVNTI64,
28381 IX86_BUILTIN_MOVNTPD,
28382 IX86_BUILTIN_MOVNTDQ,
28384 IX86_BUILTIN_MOVQ128,
28386 /* SSE2 MMX */
28387 IX86_BUILTIN_MASKMOVDQU,
28388 IX86_BUILTIN_MOVMSKPD,
28389 IX86_BUILTIN_PMOVMSKB128,
28391 IX86_BUILTIN_PACKSSWB128,
28392 IX86_BUILTIN_PACKSSDW128,
28393 IX86_BUILTIN_PACKUSWB128,
28395 IX86_BUILTIN_PADDB128,
28396 IX86_BUILTIN_PADDW128,
28397 IX86_BUILTIN_PADDD128,
28398 IX86_BUILTIN_PADDQ128,
28399 IX86_BUILTIN_PADDSB128,
28400 IX86_BUILTIN_PADDSW128,
28401 IX86_BUILTIN_PADDUSB128,
28402 IX86_BUILTIN_PADDUSW128,
28403 IX86_BUILTIN_PSUBB128,
28404 IX86_BUILTIN_PSUBW128,
28405 IX86_BUILTIN_PSUBD128,
28406 IX86_BUILTIN_PSUBQ128,
28407 IX86_BUILTIN_PSUBSB128,
28408 IX86_BUILTIN_PSUBSW128,
28409 IX86_BUILTIN_PSUBUSB128,
28410 IX86_BUILTIN_PSUBUSW128,
28412 IX86_BUILTIN_PAND128,
28413 IX86_BUILTIN_PANDN128,
28414 IX86_BUILTIN_POR128,
28415 IX86_BUILTIN_PXOR128,
28417 IX86_BUILTIN_PAVGB128,
28418 IX86_BUILTIN_PAVGW128,
28420 IX86_BUILTIN_PCMPEQB128,
28421 IX86_BUILTIN_PCMPEQW128,
28422 IX86_BUILTIN_PCMPEQD128,
28423 IX86_BUILTIN_PCMPGTB128,
28424 IX86_BUILTIN_PCMPGTW128,
28425 IX86_BUILTIN_PCMPGTD128,
28427 IX86_BUILTIN_PMADDWD128,
28429 IX86_BUILTIN_PMAXSW128,
28430 IX86_BUILTIN_PMAXUB128,
28431 IX86_BUILTIN_PMINSW128,
28432 IX86_BUILTIN_PMINUB128,
28434 IX86_BUILTIN_PMULUDQ,
28435 IX86_BUILTIN_PMULUDQ128,
28436 IX86_BUILTIN_PMULHUW128,
28437 IX86_BUILTIN_PMULHW128,
28438 IX86_BUILTIN_PMULLW128,
28440 IX86_BUILTIN_PSADBW128,
28441 IX86_BUILTIN_PSHUFHW,
28442 IX86_BUILTIN_PSHUFLW,
28443 IX86_BUILTIN_PSHUFD,
28445 IX86_BUILTIN_PSLLDQI128,
28446 IX86_BUILTIN_PSLLWI128,
28447 IX86_BUILTIN_PSLLDI128,
28448 IX86_BUILTIN_PSLLQI128,
28449 IX86_BUILTIN_PSRAWI128,
28450 IX86_BUILTIN_PSRADI128,
28451 IX86_BUILTIN_PSRLDQI128,
28452 IX86_BUILTIN_PSRLWI128,
28453 IX86_BUILTIN_PSRLDI128,
28454 IX86_BUILTIN_PSRLQI128,
28456 IX86_BUILTIN_PSLLDQ128,
28457 IX86_BUILTIN_PSLLW128,
28458 IX86_BUILTIN_PSLLD128,
28459 IX86_BUILTIN_PSLLQ128,
28460 IX86_BUILTIN_PSRAW128,
28461 IX86_BUILTIN_PSRAD128,
28462 IX86_BUILTIN_PSRLW128,
28463 IX86_BUILTIN_PSRLD128,
28464 IX86_BUILTIN_PSRLQ128,
28466 IX86_BUILTIN_PUNPCKHBW128,
28467 IX86_BUILTIN_PUNPCKHWD128,
28468 IX86_BUILTIN_PUNPCKHDQ128,
28469 IX86_BUILTIN_PUNPCKHQDQ128,
28470 IX86_BUILTIN_PUNPCKLBW128,
28471 IX86_BUILTIN_PUNPCKLWD128,
28472 IX86_BUILTIN_PUNPCKLDQ128,
28473 IX86_BUILTIN_PUNPCKLQDQ128,
28475 IX86_BUILTIN_CLFLUSH,
28476 IX86_BUILTIN_MFENCE,
28477 IX86_BUILTIN_LFENCE,
28478 IX86_BUILTIN_PAUSE,
28480 IX86_BUILTIN_FNSTENV,
28481 IX86_BUILTIN_FLDENV,
28482 IX86_BUILTIN_FNSTSW,
28483 IX86_BUILTIN_FNCLEX,
28485 IX86_BUILTIN_BSRSI,
28486 IX86_BUILTIN_BSRDI,
28487 IX86_BUILTIN_RDPMC,
28488 IX86_BUILTIN_RDTSC,
28489 IX86_BUILTIN_RDTSCP,
28490 IX86_BUILTIN_ROLQI,
28491 IX86_BUILTIN_ROLHI,
28492 IX86_BUILTIN_RORQI,
28493 IX86_BUILTIN_RORHI,
28495 /* SSE3. */
28496 IX86_BUILTIN_ADDSUBPS,
28497 IX86_BUILTIN_HADDPS,
28498 IX86_BUILTIN_HSUBPS,
28499 IX86_BUILTIN_MOVSHDUP,
28500 IX86_BUILTIN_MOVSLDUP,
28501 IX86_BUILTIN_ADDSUBPD,
28502 IX86_BUILTIN_HADDPD,
28503 IX86_BUILTIN_HSUBPD,
28504 IX86_BUILTIN_LDDQU,
28506 IX86_BUILTIN_MONITOR,
28507 IX86_BUILTIN_MWAIT,
28509 /* SSSE3. */
28510 IX86_BUILTIN_PHADDW,
28511 IX86_BUILTIN_PHADDD,
28512 IX86_BUILTIN_PHADDSW,
28513 IX86_BUILTIN_PHSUBW,
28514 IX86_BUILTIN_PHSUBD,
28515 IX86_BUILTIN_PHSUBSW,
28516 IX86_BUILTIN_PMADDUBSW,
28517 IX86_BUILTIN_PMULHRSW,
28518 IX86_BUILTIN_PSHUFB,
28519 IX86_BUILTIN_PSIGNB,
28520 IX86_BUILTIN_PSIGNW,
28521 IX86_BUILTIN_PSIGND,
28522 IX86_BUILTIN_PALIGNR,
28523 IX86_BUILTIN_PABSB,
28524 IX86_BUILTIN_PABSW,
28525 IX86_BUILTIN_PABSD,
28527 IX86_BUILTIN_PHADDW128,
28528 IX86_BUILTIN_PHADDD128,
28529 IX86_BUILTIN_PHADDSW128,
28530 IX86_BUILTIN_PHSUBW128,
28531 IX86_BUILTIN_PHSUBD128,
28532 IX86_BUILTIN_PHSUBSW128,
28533 IX86_BUILTIN_PMADDUBSW128,
28534 IX86_BUILTIN_PMULHRSW128,
28535 IX86_BUILTIN_PSHUFB128,
28536 IX86_BUILTIN_PSIGNB128,
28537 IX86_BUILTIN_PSIGNW128,
28538 IX86_BUILTIN_PSIGND128,
28539 IX86_BUILTIN_PALIGNR128,
28540 IX86_BUILTIN_PABSB128,
28541 IX86_BUILTIN_PABSW128,
28542 IX86_BUILTIN_PABSD128,
28544 /* AMDFAM10 - SSE4A New Instructions. */
28545 IX86_BUILTIN_MOVNTSD,
28546 IX86_BUILTIN_MOVNTSS,
28547 IX86_BUILTIN_EXTRQI,
28548 IX86_BUILTIN_EXTRQ,
28549 IX86_BUILTIN_INSERTQI,
28550 IX86_BUILTIN_INSERTQ,
28552 /* SSE4.1. */
28553 IX86_BUILTIN_BLENDPD,
28554 IX86_BUILTIN_BLENDPS,
28555 IX86_BUILTIN_BLENDVPD,
28556 IX86_BUILTIN_BLENDVPS,
28557 IX86_BUILTIN_PBLENDVB128,
28558 IX86_BUILTIN_PBLENDW128,
28560 IX86_BUILTIN_DPPD,
28561 IX86_BUILTIN_DPPS,
28563 IX86_BUILTIN_INSERTPS128,
28565 IX86_BUILTIN_MOVNTDQA,
28566 IX86_BUILTIN_MPSADBW128,
28567 IX86_BUILTIN_PACKUSDW128,
28568 IX86_BUILTIN_PCMPEQQ,
28569 IX86_BUILTIN_PHMINPOSUW128,
28571 IX86_BUILTIN_PMAXSB128,
28572 IX86_BUILTIN_PMAXSD128,
28573 IX86_BUILTIN_PMAXUD128,
28574 IX86_BUILTIN_PMAXUW128,
28576 IX86_BUILTIN_PMINSB128,
28577 IX86_BUILTIN_PMINSD128,
28578 IX86_BUILTIN_PMINUD128,
28579 IX86_BUILTIN_PMINUW128,
28581 IX86_BUILTIN_PMOVSXBW128,
28582 IX86_BUILTIN_PMOVSXBD128,
28583 IX86_BUILTIN_PMOVSXBQ128,
28584 IX86_BUILTIN_PMOVSXWD128,
28585 IX86_BUILTIN_PMOVSXWQ128,
28586 IX86_BUILTIN_PMOVSXDQ128,
28588 IX86_BUILTIN_PMOVZXBW128,
28589 IX86_BUILTIN_PMOVZXBD128,
28590 IX86_BUILTIN_PMOVZXBQ128,
28591 IX86_BUILTIN_PMOVZXWD128,
28592 IX86_BUILTIN_PMOVZXWQ128,
28593 IX86_BUILTIN_PMOVZXDQ128,
28595 IX86_BUILTIN_PMULDQ128,
28596 IX86_BUILTIN_PMULLD128,
28598 IX86_BUILTIN_ROUNDSD,
28599 IX86_BUILTIN_ROUNDSS,
28601 IX86_BUILTIN_ROUNDPD,
28602 IX86_BUILTIN_ROUNDPS,
28604 IX86_BUILTIN_FLOORPD,
28605 IX86_BUILTIN_CEILPD,
28606 IX86_BUILTIN_TRUNCPD,
28607 IX86_BUILTIN_RINTPD,
28608 IX86_BUILTIN_ROUNDPD_AZ,
28610 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28611 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28612 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28614 IX86_BUILTIN_FLOORPS,
28615 IX86_BUILTIN_CEILPS,
28616 IX86_BUILTIN_TRUNCPS,
28617 IX86_BUILTIN_RINTPS,
28618 IX86_BUILTIN_ROUNDPS_AZ,
28620 IX86_BUILTIN_FLOORPS_SFIX,
28621 IX86_BUILTIN_CEILPS_SFIX,
28622 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28624 IX86_BUILTIN_PTESTZ,
28625 IX86_BUILTIN_PTESTC,
28626 IX86_BUILTIN_PTESTNZC,
28628 IX86_BUILTIN_VEC_INIT_V2SI,
28629 IX86_BUILTIN_VEC_INIT_V4HI,
28630 IX86_BUILTIN_VEC_INIT_V8QI,
28631 IX86_BUILTIN_VEC_EXT_V2DF,
28632 IX86_BUILTIN_VEC_EXT_V2DI,
28633 IX86_BUILTIN_VEC_EXT_V4SF,
28634 IX86_BUILTIN_VEC_EXT_V4SI,
28635 IX86_BUILTIN_VEC_EXT_V8HI,
28636 IX86_BUILTIN_VEC_EXT_V2SI,
28637 IX86_BUILTIN_VEC_EXT_V4HI,
28638 IX86_BUILTIN_VEC_EXT_V16QI,
28639 IX86_BUILTIN_VEC_SET_V2DI,
28640 IX86_BUILTIN_VEC_SET_V4SF,
28641 IX86_BUILTIN_VEC_SET_V4SI,
28642 IX86_BUILTIN_VEC_SET_V8HI,
28643 IX86_BUILTIN_VEC_SET_V4HI,
28644 IX86_BUILTIN_VEC_SET_V16QI,
28646 IX86_BUILTIN_VEC_PACK_SFIX,
28647 IX86_BUILTIN_VEC_PACK_SFIX256,
28649 /* SSE4.2. */
28650 IX86_BUILTIN_CRC32QI,
28651 IX86_BUILTIN_CRC32HI,
28652 IX86_BUILTIN_CRC32SI,
28653 IX86_BUILTIN_CRC32DI,
28655 IX86_BUILTIN_PCMPESTRI128,
28656 IX86_BUILTIN_PCMPESTRM128,
28657 IX86_BUILTIN_PCMPESTRA128,
28658 IX86_BUILTIN_PCMPESTRC128,
28659 IX86_BUILTIN_PCMPESTRO128,
28660 IX86_BUILTIN_PCMPESTRS128,
28661 IX86_BUILTIN_PCMPESTRZ128,
28662 IX86_BUILTIN_PCMPISTRI128,
28663 IX86_BUILTIN_PCMPISTRM128,
28664 IX86_BUILTIN_PCMPISTRA128,
28665 IX86_BUILTIN_PCMPISTRC128,
28666 IX86_BUILTIN_PCMPISTRO128,
28667 IX86_BUILTIN_PCMPISTRS128,
28668 IX86_BUILTIN_PCMPISTRZ128,
28670 IX86_BUILTIN_PCMPGTQ,
28672 /* AES instructions */
28673 IX86_BUILTIN_AESENC128,
28674 IX86_BUILTIN_AESENCLAST128,
28675 IX86_BUILTIN_AESDEC128,
28676 IX86_BUILTIN_AESDECLAST128,
28677 IX86_BUILTIN_AESIMC128,
28678 IX86_BUILTIN_AESKEYGENASSIST128,
28680 /* PCLMUL instruction */
28681 IX86_BUILTIN_PCLMULQDQ128,
28683 /* AVX */
28684 IX86_BUILTIN_ADDPD256,
28685 IX86_BUILTIN_ADDPS256,
28686 IX86_BUILTIN_ADDSUBPD256,
28687 IX86_BUILTIN_ADDSUBPS256,
28688 IX86_BUILTIN_ANDPD256,
28689 IX86_BUILTIN_ANDPS256,
28690 IX86_BUILTIN_ANDNPD256,
28691 IX86_BUILTIN_ANDNPS256,
28692 IX86_BUILTIN_BLENDPD256,
28693 IX86_BUILTIN_BLENDPS256,
28694 IX86_BUILTIN_BLENDVPD256,
28695 IX86_BUILTIN_BLENDVPS256,
28696 IX86_BUILTIN_DIVPD256,
28697 IX86_BUILTIN_DIVPS256,
28698 IX86_BUILTIN_DPPS256,
28699 IX86_BUILTIN_HADDPD256,
28700 IX86_BUILTIN_HADDPS256,
28701 IX86_BUILTIN_HSUBPD256,
28702 IX86_BUILTIN_HSUBPS256,
28703 IX86_BUILTIN_MAXPD256,
28704 IX86_BUILTIN_MAXPS256,
28705 IX86_BUILTIN_MINPD256,
28706 IX86_BUILTIN_MINPS256,
28707 IX86_BUILTIN_MULPD256,
28708 IX86_BUILTIN_MULPS256,
28709 IX86_BUILTIN_ORPD256,
28710 IX86_BUILTIN_ORPS256,
28711 IX86_BUILTIN_SHUFPD256,
28712 IX86_BUILTIN_SHUFPS256,
28713 IX86_BUILTIN_SUBPD256,
28714 IX86_BUILTIN_SUBPS256,
28715 IX86_BUILTIN_XORPD256,
28716 IX86_BUILTIN_XORPS256,
28717 IX86_BUILTIN_CMPSD,
28718 IX86_BUILTIN_CMPSS,
28719 IX86_BUILTIN_CMPPD,
28720 IX86_BUILTIN_CMPPS,
28721 IX86_BUILTIN_CMPPD256,
28722 IX86_BUILTIN_CMPPS256,
28723 IX86_BUILTIN_CVTDQ2PD256,
28724 IX86_BUILTIN_CVTDQ2PS256,
28725 IX86_BUILTIN_CVTPD2PS256,
28726 IX86_BUILTIN_CVTPS2DQ256,
28727 IX86_BUILTIN_CVTPS2PD256,
28728 IX86_BUILTIN_CVTTPD2DQ256,
28729 IX86_BUILTIN_CVTPD2DQ256,
28730 IX86_BUILTIN_CVTTPS2DQ256,
28731 IX86_BUILTIN_EXTRACTF128PD256,
28732 IX86_BUILTIN_EXTRACTF128PS256,
28733 IX86_BUILTIN_EXTRACTF128SI256,
28734 IX86_BUILTIN_VZEROALL,
28735 IX86_BUILTIN_VZEROUPPER,
28736 IX86_BUILTIN_VPERMILVARPD,
28737 IX86_BUILTIN_VPERMILVARPS,
28738 IX86_BUILTIN_VPERMILVARPD256,
28739 IX86_BUILTIN_VPERMILVARPS256,
28740 IX86_BUILTIN_VPERMILPD,
28741 IX86_BUILTIN_VPERMILPS,
28742 IX86_BUILTIN_VPERMILPD256,
28743 IX86_BUILTIN_VPERMILPS256,
28744 IX86_BUILTIN_VPERMIL2PD,
28745 IX86_BUILTIN_VPERMIL2PS,
28746 IX86_BUILTIN_VPERMIL2PD256,
28747 IX86_BUILTIN_VPERMIL2PS256,
28748 IX86_BUILTIN_VPERM2F128PD256,
28749 IX86_BUILTIN_VPERM2F128PS256,
28750 IX86_BUILTIN_VPERM2F128SI256,
28751 IX86_BUILTIN_VBROADCASTSS,
28752 IX86_BUILTIN_VBROADCASTSD256,
28753 IX86_BUILTIN_VBROADCASTSS256,
28754 IX86_BUILTIN_VBROADCASTPD256,
28755 IX86_BUILTIN_VBROADCASTPS256,
28756 IX86_BUILTIN_VINSERTF128PD256,
28757 IX86_BUILTIN_VINSERTF128PS256,
28758 IX86_BUILTIN_VINSERTF128SI256,
28759 IX86_BUILTIN_LOADUPD256,
28760 IX86_BUILTIN_LOADUPS256,
28761 IX86_BUILTIN_STOREUPD256,
28762 IX86_BUILTIN_STOREUPS256,
28763 IX86_BUILTIN_LDDQU256,
28764 IX86_BUILTIN_MOVNTDQ256,
28765 IX86_BUILTIN_MOVNTPD256,
28766 IX86_BUILTIN_MOVNTPS256,
28767 IX86_BUILTIN_LOADDQU256,
28768 IX86_BUILTIN_STOREDQU256,
28769 IX86_BUILTIN_MASKLOADPD,
28770 IX86_BUILTIN_MASKLOADPS,
28771 IX86_BUILTIN_MASKSTOREPD,
28772 IX86_BUILTIN_MASKSTOREPS,
28773 IX86_BUILTIN_MASKLOADPD256,
28774 IX86_BUILTIN_MASKLOADPS256,
28775 IX86_BUILTIN_MASKSTOREPD256,
28776 IX86_BUILTIN_MASKSTOREPS256,
28777 IX86_BUILTIN_MOVSHDUP256,
28778 IX86_BUILTIN_MOVSLDUP256,
28779 IX86_BUILTIN_MOVDDUP256,
28781 IX86_BUILTIN_SQRTPD256,
28782 IX86_BUILTIN_SQRTPS256,
28783 IX86_BUILTIN_SQRTPS_NR256,
28784 IX86_BUILTIN_RSQRTPS256,
28785 IX86_BUILTIN_RSQRTPS_NR256,
28787 IX86_BUILTIN_RCPPS256,
28789 IX86_BUILTIN_ROUNDPD256,
28790 IX86_BUILTIN_ROUNDPS256,
28792 IX86_BUILTIN_FLOORPD256,
28793 IX86_BUILTIN_CEILPD256,
28794 IX86_BUILTIN_TRUNCPD256,
28795 IX86_BUILTIN_RINTPD256,
28796 IX86_BUILTIN_ROUNDPD_AZ256,
28798 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28799 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28800 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28802 IX86_BUILTIN_FLOORPS256,
28803 IX86_BUILTIN_CEILPS256,
28804 IX86_BUILTIN_TRUNCPS256,
28805 IX86_BUILTIN_RINTPS256,
28806 IX86_BUILTIN_ROUNDPS_AZ256,
28808 IX86_BUILTIN_FLOORPS_SFIX256,
28809 IX86_BUILTIN_CEILPS_SFIX256,
28810 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28812 IX86_BUILTIN_UNPCKHPD256,
28813 IX86_BUILTIN_UNPCKLPD256,
28814 IX86_BUILTIN_UNPCKHPS256,
28815 IX86_BUILTIN_UNPCKLPS256,
28817 IX86_BUILTIN_SI256_SI,
28818 IX86_BUILTIN_PS256_PS,
28819 IX86_BUILTIN_PD256_PD,
28820 IX86_BUILTIN_SI_SI256,
28821 IX86_BUILTIN_PS_PS256,
28822 IX86_BUILTIN_PD_PD256,
28824 IX86_BUILTIN_VTESTZPD,
28825 IX86_BUILTIN_VTESTCPD,
28826 IX86_BUILTIN_VTESTNZCPD,
28827 IX86_BUILTIN_VTESTZPS,
28828 IX86_BUILTIN_VTESTCPS,
28829 IX86_BUILTIN_VTESTNZCPS,
28830 IX86_BUILTIN_VTESTZPD256,
28831 IX86_BUILTIN_VTESTCPD256,
28832 IX86_BUILTIN_VTESTNZCPD256,
28833 IX86_BUILTIN_VTESTZPS256,
28834 IX86_BUILTIN_VTESTCPS256,
28835 IX86_BUILTIN_VTESTNZCPS256,
28836 IX86_BUILTIN_PTESTZ256,
28837 IX86_BUILTIN_PTESTC256,
28838 IX86_BUILTIN_PTESTNZC256,
28840 IX86_BUILTIN_MOVMSKPD256,
28841 IX86_BUILTIN_MOVMSKPS256,
28843 /* AVX2 */
28844 IX86_BUILTIN_MPSADBW256,
28845 IX86_BUILTIN_PABSB256,
28846 IX86_BUILTIN_PABSW256,
28847 IX86_BUILTIN_PABSD256,
28848 IX86_BUILTIN_PACKSSDW256,
28849 IX86_BUILTIN_PACKSSWB256,
28850 IX86_BUILTIN_PACKUSDW256,
28851 IX86_BUILTIN_PACKUSWB256,
28852 IX86_BUILTIN_PADDB256,
28853 IX86_BUILTIN_PADDW256,
28854 IX86_BUILTIN_PADDD256,
28855 IX86_BUILTIN_PADDQ256,
28856 IX86_BUILTIN_PADDSB256,
28857 IX86_BUILTIN_PADDSW256,
28858 IX86_BUILTIN_PADDUSB256,
28859 IX86_BUILTIN_PADDUSW256,
28860 IX86_BUILTIN_PALIGNR256,
28861 IX86_BUILTIN_AND256I,
28862 IX86_BUILTIN_ANDNOT256I,
28863 IX86_BUILTIN_PAVGB256,
28864 IX86_BUILTIN_PAVGW256,
28865 IX86_BUILTIN_PBLENDVB256,
28866 IX86_BUILTIN_PBLENDVW256,
28867 IX86_BUILTIN_PCMPEQB256,
28868 IX86_BUILTIN_PCMPEQW256,
28869 IX86_BUILTIN_PCMPEQD256,
28870 IX86_BUILTIN_PCMPEQQ256,
28871 IX86_BUILTIN_PCMPGTB256,
28872 IX86_BUILTIN_PCMPGTW256,
28873 IX86_BUILTIN_PCMPGTD256,
28874 IX86_BUILTIN_PCMPGTQ256,
28875 IX86_BUILTIN_PHADDW256,
28876 IX86_BUILTIN_PHADDD256,
28877 IX86_BUILTIN_PHADDSW256,
28878 IX86_BUILTIN_PHSUBW256,
28879 IX86_BUILTIN_PHSUBD256,
28880 IX86_BUILTIN_PHSUBSW256,
28881 IX86_BUILTIN_PMADDUBSW256,
28882 IX86_BUILTIN_PMADDWD256,
28883 IX86_BUILTIN_PMAXSB256,
28884 IX86_BUILTIN_PMAXSW256,
28885 IX86_BUILTIN_PMAXSD256,
28886 IX86_BUILTIN_PMAXUB256,
28887 IX86_BUILTIN_PMAXUW256,
28888 IX86_BUILTIN_PMAXUD256,
28889 IX86_BUILTIN_PMINSB256,
28890 IX86_BUILTIN_PMINSW256,
28891 IX86_BUILTIN_PMINSD256,
28892 IX86_BUILTIN_PMINUB256,
28893 IX86_BUILTIN_PMINUW256,
28894 IX86_BUILTIN_PMINUD256,
28895 IX86_BUILTIN_PMOVMSKB256,
28896 IX86_BUILTIN_PMOVSXBW256,
28897 IX86_BUILTIN_PMOVSXBD256,
28898 IX86_BUILTIN_PMOVSXBQ256,
28899 IX86_BUILTIN_PMOVSXWD256,
28900 IX86_BUILTIN_PMOVSXWQ256,
28901 IX86_BUILTIN_PMOVSXDQ256,
28902 IX86_BUILTIN_PMOVZXBW256,
28903 IX86_BUILTIN_PMOVZXBD256,
28904 IX86_BUILTIN_PMOVZXBQ256,
28905 IX86_BUILTIN_PMOVZXWD256,
28906 IX86_BUILTIN_PMOVZXWQ256,
28907 IX86_BUILTIN_PMOVZXDQ256,
28908 IX86_BUILTIN_PMULDQ256,
28909 IX86_BUILTIN_PMULHRSW256,
28910 IX86_BUILTIN_PMULHUW256,
28911 IX86_BUILTIN_PMULHW256,
28912 IX86_BUILTIN_PMULLW256,
28913 IX86_BUILTIN_PMULLD256,
28914 IX86_BUILTIN_PMULUDQ256,
28915 IX86_BUILTIN_POR256,
28916 IX86_BUILTIN_PSADBW256,
28917 IX86_BUILTIN_PSHUFB256,
28918 IX86_BUILTIN_PSHUFD256,
28919 IX86_BUILTIN_PSHUFHW256,
28920 IX86_BUILTIN_PSHUFLW256,
28921 IX86_BUILTIN_PSIGNB256,
28922 IX86_BUILTIN_PSIGNW256,
28923 IX86_BUILTIN_PSIGND256,
28924 IX86_BUILTIN_PSLLDQI256,
28925 IX86_BUILTIN_PSLLWI256,
28926 IX86_BUILTIN_PSLLW256,
28927 IX86_BUILTIN_PSLLDI256,
28928 IX86_BUILTIN_PSLLD256,
28929 IX86_BUILTIN_PSLLQI256,
28930 IX86_BUILTIN_PSLLQ256,
28931 IX86_BUILTIN_PSRAWI256,
28932 IX86_BUILTIN_PSRAW256,
28933 IX86_BUILTIN_PSRADI256,
28934 IX86_BUILTIN_PSRAD256,
28935 IX86_BUILTIN_PSRLDQI256,
28936 IX86_BUILTIN_PSRLWI256,
28937 IX86_BUILTIN_PSRLW256,
28938 IX86_BUILTIN_PSRLDI256,
28939 IX86_BUILTIN_PSRLD256,
28940 IX86_BUILTIN_PSRLQI256,
28941 IX86_BUILTIN_PSRLQ256,
28942 IX86_BUILTIN_PSUBB256,
28943 IX86_BUILTIN_PSUBW256,
28944 IX86_BUILTIN_PSUBD256,
28945 IX86_BUILTIN_PSUBQ256,
28946 IX86_BUILTIN_PSUBSB256,
28947 IX86_BUILTIN_PSUBSW256,
28948 IX86_BUILTIN_PSUBUSB256,
28949 IX86_BUILTIN_PSUBUSW256,
28950 IX86_BUILTIN_PUNPCKHBW256,
28951 IX86_BUILTIN_PUNPCKHWD256,
28952 IX86_BUILTIN_PUNPCKHDQ256,
28953 IX86_BUILTIN_PUNPCKHQDQ256,
28954 IX86_BUILTIN_PUNPCKLBW256,
28955 IX86_BUILTIN_PUNPCKLWD256,
28956 IX86_BUILTIN_PUNPCKLDQ256,
28957 IX86_BUILTIN_PUNPCKLQDQ256,
28958 IX86_BUILTIN_PXOR256,
28959 IX86_BUILTIN_MOVNTDQA256,
28960 IX86_BUILTIN_VBROADCASTSS_PS,
28961 IX86_BUILTIN_VBROADCASTSS_PS256,
28962 IX86_BUILTIN_VBROADCASTSD_PD256,
28963 IX86_BUILTIN_VBROADCASTSI256,
28964 IX86_BUILTIN_PBLENDD256,
28965 IX86_BUILTIN_PBLENDD128,
28966 IX86_BUILTIN_PBROADCASTB256,
28967 IX86_BUILTIN_PBROADCASTW256,
28968 IX86_BUILTIN_PBROADCASTD256,
28969 IX86_BUILTIN_PBROADCASTQ256,
28970 IX86_BUILTIN_PBROADCASTB128,
28971 IX86_BUILTIN_PBROADCASTW128,
28972 IX86_BUILTIN_PBROADCASTD128,
28973 IX86_BUILTIN_PBROADCASTQ128,
28974 IX86_BUILTIN_VPERMVARSI256,
28975 IX86_BUILTIN_VPERMDF256,
28976 IX86_BUILTIN_VPERMVARSF256,
28977 IX86_BUILTIN_VPERMDI256,
28978 IX86_BUILTIN_VPERMTI256,
28979 IX86_BUILTIN_VEXTRACT128I256,
28980 IX86_BUILTIN_VINSERT128I256,
28981 IX86_BUILTIN_MASKLOADD,
28982 IX86_BUILTIN_MASKLOADQ,
28983 IX86_BUILTIN_MASKLOADD256,
28984 IX86_BUILTIN_MASKLOADQ256,
28985 IX86_BUILTIN_MASKSTORED,
28986 IX86_BUILTIN_MASKSTOREQ,
28987 IX86_BUILTIN_MASKSTORED256,
28988 IX86_BUILTIN_MASKSTOREQ256,
28989 IX86_BUILTIN_PSLLVV4DI,
28990 IX86_BUILTIN_PSLLVV2DI,
28991 IX86_BUILTIN_PSLLVV8SI,
28992 IX86_BUILTIN_PSLLVV4SI,
28993 IX86_BUILTIN_PSRAVV8SI,
28994 IX86_BUILTIN_PSRAVV4SI,
28995 IX86_BUILTIN_PSRLVV4DI,
28996 IX86_BUILTIN_PSRLVV2DI,
28997 IX86_BUILTIN_PSRLVV8SI,
28998 IX86_BUILTIN_PSRLVV4SI,
29000 IX86_BUILTIN_GATHERSIV2DF,
29001 IX86_BUILTIN_GATHERSIV4DF,
29002 IX86_BUILTIN_GATHERDIV2DF,
29003 IX86_BUILTIN_GATHERDIV4DF,
29004 IX86_BUILTIN_GATHERSIV4SF,
29005 IX86_BUILTIN_GATHERSIV8SF,
29006 IX86_BUILTIN_GATHERDIV4SF,
29007 IX86_BUILTIN_GATHERDIV8SF,
29008 IX86_BUILTIN_GATHERSIV2DI,
29009 IX86_BUILTIN_GATHERSIV4DI,
29010 IX86_BUILTIN_GATHERDIV2DI,
29011 IX86_BUILTIN_GATHERDIV4DI,
29012 IX86_BUILTIN_GATHERSIV4SI,
29013 IX86_BUILTIN_GATHERSIV8SI,
29014 IX86_BUILTIN_GATHERDIV4SI,
29015 IX86_BUILTIN_GATHERDIV8SI,
29017 /* AVX512F */
29018 IX86_BUILTIN_SI512_SI256,
29019 IX86_BUILTIN_PD512_PD256,
29020 IX86_BUILTIN_PS512_PS256,
29021 IX86_BUILTIN_SI512_SI,
29022 IX86_BUILTIN_PD512_PD,
29023 IX86_BUILTIN_PS512_PS,
29024 IX86_BUILTIN_ADDPD512,
29025 IX86_BUILTIN_ADDPS512,
29026 IX86_BUILTIN_ADDSD_ROUND,
29027 IX86_BUILTIN_ADDSS_ROUND,
29028 IX86_BUILTIN_ALIGND512,
29029 IX86_BUILTIN_ALIGNQ512,
29030 IX86_BUILTIN_BLENDMD512,
29031 IX86_BUILTIN_BLENDMPD512,
29032 IX86_BUILTIN_BLENDMPS512,
29033 IX86_BUILTIN_BLENDMQ512,
29034 IX86_BUILTIN_BROADCASTF32X4_512,
29035 IX86_BUILTIN_BROADCASTF64X4_512,
29036 IX86_BUILTIN_BROADCASTI32X4_512,
29037 IX86_BUILTIN_BROADCASTI64X4_512,
29038 IX86_BUILTIN_BROADCASTSD512,
29039 IX86_BUILTIN_BROADCASTSS512,
29040 IX86_BUILTIN_CMPD512,
29041 IX86_BUILTIN_CMPPD512,
29042 IX86_BUILTIN_CMPPS512,
29043 IX86_BUILTIN_CMPQ512,
29044 IX86_BUILTIN_CMPSD_MASK,
29045 IX86_BUILTIN_CMPSS_MASK,
29046 IX86_BUILTIN_COMIDF,
29047 IX86_BUILTIN_COMISF,
29048 IX86_BUILTIN_COMPRESSPD512,
29049 IX86_BUILTIN_COMPRESSPDSTORE512,
29050 IX86_BUILTIN_COMPRESSPS512,
29051 IX86_BUILTIN_COMPRESSPSSTORE512,
29052 IX86_BUILTIN_CVTDQ2PD512,
29053 IX86_BUILTIN_CVTDQ2PS512,
29054 IX86_BUILTIN_CVTPD2DQ512,
29055 IX86_BUILTIN_CVTPD2PS512,
29056 IX86_BUILTIN_CVTPD2UDQ512,
29057 IX86_BUILTIN_CVTPH2PS512,
29058 IX86_BUILTIN_CVTPS2DQ512,
29059 IX86_BUILTIN_CVTPS2PD512,
29060 IX86_BUILTIN_CVTPS2PH512,
29061 IX86_BUILTIN_CVTPS2UDQ512,
29062 IX86_BUILTIN_CVTSD2SS_ROUND,
29063 IX86_BUILTIN_CVTSI2SD64,
29064 IX86_BUILTIN_CVTSI2SS32,
29065 IX86_BUILTIN_CVTSI2SS64,
29066 IX86_BUILTIN_CVTSS2SD_ROUND,
29067 IX86_BUILTIN_CVTTPD2DQ512,
29068 IX86_BUILTIN_CVTTPD2UDQ512,
29069 IX86_BUILTIN_CVTTPS2DQ512,
29070 IX86_BUILTIN_CVTTPS2UDQ512,
29071 IX86_BUILTIN_CVTUDQ2PD512,
29072 IX86_BUILTIN_CVTUDQ2PS512,
29073 IX86_BUILTIN_CVTUSI2SD32,
29074 IX86_BUILTIN_CVTUSI2SD64,
29075 IX86_BUILTIN_CVTUSI2SS32,
29076 IX86_BUILTIN_CVTUSI2SS64,
29077 IX86_BUILTIN_DIVPD512,
29078 IX86_BUILTIN_DIVPS512,
29079 IX86_BUILTIN_DIVSD_ROUND,
29080 IX86_BUILTIN_DIVSS_ROUND,
29081 IX86_BUILTIN_EXPANDPD512,
29082 IX86_BUILTIN_EXPANDPD512Z,
29083 IX86_BUILTIN_EXPANDPDLOAD512,
29084 IX86_BUILTIN_EXPANDPDLOAD512Z,
29085 IX86_BUILTIN_EXPANDPS512,
29086 IX86_BUILTIN_EXPANDPS512Z,
29087 IX86_BUILTIN_EXPANDPSLOAD512,
29088 IX86_BUILTIN_EXPANDPSLOAD512Z,
29089 IX86_BUILTIN_EXTRACTF32X4,
29090 IX86_BUILTIN_EXTRACTF64X4,
29091 IX86_BUILTIN_EXTRACTI32X4,
29092 IX86_BUILTIN_EXTRACTI64X4,
29093 IX86_BUILTIN_FIXUPIMMPD512_MASK,
29094 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
29095 IX86_BUILTIN_FIXUPIMMPS512_MASK,
29096 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
29097 IX86_BUILTIN_FIXUPIMMSD128_MASK,
29098 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
29099 IX86_BUILTIN_FIXUPIMMSS128_MASK,
29100 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
29101 IX86_BUILTIN_GETEXPPD512,
29102 IX86_BUILTIN_GETEXPPS512,
29103 IX86_BUILTIN_GETEXPSD128,
29104 IX86_BUILTIN_GETEXPSS128,
29105 IX86_BUILTIN_GETMANTPD512,
29106 IX86_BUILTIN_GETMANTPS512,
29107 IX86_BUILTIN_GETMANTSD128,
29108 IX86_BUILTIN_GETMANTSS128,
29109 IX86_BUILTIN_INSERTF32X4,
29110 IX86_BUILTIN_INSERTF64X4,
29111 IX86_BUILTIN_INSERTI32X4,
29112 IX86_BUILTIN_INSERTI64X4,
29113 IX86_BUILTIN_LOADAPD512,
29114 IX86_BUILTIN_LOADAPS512,
29115 IX86_BUILTIN_LOADDQUDI512,
29116 IX86_BUILTIN_LOADDQUSI512,
29117 IX86_BUILTIN_LOADUPD512,
29118 IX86_BUILTIN_LOADUPS512,
29119 IX86_BUILTIN_MAXPD512,
29120 IX86_BUILTIN_MAXPS512,
29121 IX86_BUILTIN_MAXSD_ROUND,
29122 IX86_BUILTIN_MAXSS_ROUND,
29123 IX86_BUILTIN_MINPD512,
29124 IX86_BUILTIN_MINPS512,
29125 IX86_BUILTIN_MINSD_ROUND,
29126 IX86_BUILTIN_MINSS_ROUND,
29127 IX86_BUILTIN_MOVAPD512,
29128 IX86_BUILTIN_MOVAPS512,
29129 IX86_BUILTIN_MOVDDUP512,
29130 IX86_BUILTIN_MOVDQA32LOAD512,
29131 IX86_BUILTIN_MOVDQA32STORE512,
29132 IX86_BUILTIN_MOVDQA32_512,
29133 IX86_BUILTIN_MOVDQA64LOAD512,
29134 IX86_BUILTIN_MOVDQA64STORE512,
29135 IX86_BUILTIN_MOVDQA64_512,
29136 IX86_BUILTIN_MOVNTDQ512,
29137 IX86_BUILTIN_MOVNTDQA512,
29138 IX86_BUILTIN_MOVNTPD512,
29139 IX86_BUILTIN_MOVNTPS512,
29140 IX86_BUILTIN_MOVSHDUP512,
29141 IX86_BUILTIN_MOVSLDUP512,
29142 IX86_BUILTIN_MULPD512,
29143 IX86_BUILTIN_MULPS512,
29144 IX86_BUILTIN_MULSD_ROUND,
29145 IX86_BUILTIN_MULSS_ROUND,
29146 IX86_BUILTIN_PABSD512,
29147 IX86_BUILTIN_PABSQ512,
29148 IX86_BUILTIN_PADDD512,
29149 IX86_BUILTIN_PADDQ512,
29150 IX86_BUILTIN_PANDD512,
29151 IX86_BUILTIN_PANDND512,
29152 IX86_BUILTIN_PANDNQ512,
29153 IX86_BUILTIN_PANDQ512,
29154 IX86_BUILTIN_PBROADCASTD512,
29155 IX86_BUILTIN_PBROADCASTD512_GPR,
29156 IX86_BUILTIN_PBROADCASTMB512,
29157 IX86_BUILTIN_PBROADCASTMW512,
29158 IX86_BUILTIN_PBROADCASTQ512,
29159 IX86_BUILTIN_PBROADCASTQ512_GPR,
29160 IX86_BUILTIN_PCMPEQD512_MASK,
29161 IX86_BUILTIN_PCMPEQQ512_MASK,
29162 IX86_BUILTIN_PCMPGTD512_MASK,
29163 IX86_BUILTIN_PCMPGTQ512_MASK,
29164 IX86_BUILTIN_PCOMPRESSD512,
29165 IX86_BUILTIN_PCOMPRESSDSTORE512,
29166 IX86_BUILTIN_PCOMPRESSQ512,
29167 IX86_BUILTIN_PCOMPRESSQSTORE512,
29168 IX86_BUILTIN_PEXPANDD512,
29169 IX86_BUILTIN_PEXPANDD512Z,
29170 IX86_BUILTIN_PEXPANDDLOAD512,
29171 IX86_BUILTIN_PEXPANDDLOAD512Z,
29172 IX86_BUILTIN_PEXPANDQ512,
29173 IX86_BUILTIN_PEXPANDQ512Z,
29174 IX86_BUILTIN_PEXPANDQLOAD512,
29175 IX86_BUILTIN_PEXPANDQLOAD512Z,
29176 IX86_BUILTIN_PMAXSD512,
29177 IX86_BUILTIN_PMAXSQ512,
29178 IX86_BUILTIN_PMAXUD512,
29179 IX86_BUILTIN_PMAXUQ512,
29180 IX86_BUILTIN_PMINSD512,
29181 IX86_BUILTIN_PMINSQ512,
29182 IX86_BUILTIN_PMINUD512,
29183 IX86_BUILTIN_PMINUQ512,
29184 IX86_BUILTIN_PMOVDB512,
29185 IX86_BUILTIN_PMOVDB512_MEM,
29186 IX86_BUILTIN_PMOVDW512,
29187 IX86_BUILTIN_PMOVDW512_MEM,
29188 IX86_BUILTIN_PMOVQB512,
29189 IX86_BUILTIN_PMOVQB512_MEM,
29190 IX86_BUILTIN_PMOVQD512,
29191 IX86_BUILTIN_PMOVQD512_MEM,
29192 IX86_BUILTIN_PMOVQW512,
29193 IX86_BUILTIN_PMOVQW512_MEM,
29194 IX86_BUILTIN_PMOVSDB512,
29195 IX86_BUILTIN_PMOVSDB512_MEM,
29196 IX86_BUILTIN_PMOVSDW512,
29197 IX86_BUILTIN_PMOVSDW512_MEM,
29198 IX86_BUILTIN_PMOVSQB512,
29199 IX86_BUILTIN_PMOVSQB512_MEM,
29200 IX86_BUILTIN_PMOVSQD512,
29201 IX86_BUILTIN_PMOVSQD512_MEM,
29202 IX86_BUILTIN_PMOVSQW512,
29203 IX86_BUILTIN_PMOVSQW512_MEM,
29204 IX86_BUILTIN_PMOVSXBD512,
29205 IX86_BUILTIN_PMOVSXBQ512,
29206 IX86_BUILTIN_PMOVSXDQ512,
29207 IX86_BUILTIN_PMOVSXWD512,
29208 IX86_BUILTIN_PMOVSXWQ512,
29209 IX86_BUILTIN_PMOVUSDB512,
29210 IX86_BUILTIN_PMOVUSDB512_MEM,
29211 IX86_BUILTIN_PMOVUSDW512,
29212 IX86_BUILTIN_PMOVUSDW512_MEM,
29213 IX86_BUILTIN_PMOVUSQB512,
29214 IX86_BUILTIN_PMOVUSQB512_MEM,
29215 IX86_BUILTIN_PMOVUSQD512,
29216 IX86_BUILTIN_PMOVUSQD512_MEM,
29217 IX86_BUILTIN_PMOVUSQW512,
29218 IX86_BUILTIN_PMOVUSQW512_MEM,
29219 IX86_BUILTIN_PMOVZXBD512,
29220 IX86_BUILTIN_PMOVZXBQ512,
29221 IX86_BUILTIN_PMOVZXDQ512,
29222 IX86_BUILTIN_PMOVZXWD512,
29223 IX86_BUILTIN_PMOVZXWQ512,
29224 IX86_BUILTIN_PMULDQ512,
29225 IX86_BUILTIN_PMULLD512,
29226 IX86_BUILTIN_PMULUDQ512,
29227 IX86_BUILTIN_PORD512,
29228 IX86_BUILTIN_PORQ512,
29229 IX86_BUILTIN_PROLD512,
29230 IX86_BUILTIN_PROLQ512,
29231 IX86_BUILTIN_PROLVD512,
29232 IX86_BUILTIN_PROLVQ512,
29233 IX86_BUILTIN_PRORD512,
29234 IX86_BUILTIN_PRORQ512,
29235 IX86_BUILTIN_PRORVD512,
29236 IX86_BUILTIN_PRORVQ512,
29237 IX86_BUILTIN_PSHUFD512,
29238 IX86_BUILTIN_PSLLD512,
29239 IX86_BUILTIN_PSLLDI512,
29240 IX86_BUILTIN_PSLLQ512,
29241 IX86_BUILTIN_PSLLQI512,
29242 IX86_BUILTIN_PSLLVV16SI,
29243 IX86_BUILTIN_PSLLVV8DI,
29244 IX86_BUILTIN_PSRAD512,
29245 IX86_BUILTIN_PSRADI512,
29246 IX86_BUILTIN_PSRAQ512,
29247 IX86_BUILTIN_PSRAQI512,
29248 IX86_BUILTIN_PSRAVV16SI,
29249 IX86_BUILTIN_PSRAVV8DI,
29250 IX86_BUILTIN_PSRLD512,
29251 IX86_BUILTIN_PSRLDI512,
29252 IX86_BUILTIN_PSRLQ512,
29253 IX86_BUILTIN_PSRLQI512,
29254 IX86_BUILTIN_PSRLVV16SI,
29255 IX86_BUILTIN_PSRLVV8DI,
29256 IX86_BUILTIN_PSUBD512,
29257 IX86_BUILTIN_PSUBQ512,
29258 IX86_BUILTIN_PTESTMD512,
29259 IX86_BUILTIN_PTESTMQ512,
29260 IX86_BUILTIN_PTESTNMD512,
29261 IX86_BUILTIN_PTESTNMQ512,
29262 IX86_BUILTIN_PUNPCKHDQ512,
29263 IX86_BUILTIN_PUNPCKHQDQ512,
29264 IX86_BUILTIN_PUNPCKLDQ512,
29265 IX86_BUILTIN_PUNPCKLQDQ512,
29266 IX86_BUILTIN_PXORD512,
29267 IX86_BUILTIN_PXORQ512,
29268 IX86_BUILTIN_RCP14PD512,
29269 IX86_BUILTIN_RCP14PS512,
29270 IX86_BUILTIN_RCP14SD,
29271 IX86_BUILTIN_RCP14SS,
29272 IX86_BUILTIN_RNDSCALEPD,
29273 IX86_BUILTIN_RNDSCALEPS,
29274 IX86_BUILTIN_RNDSCALESD,
29275 IX86_BUILTIN_RNDSCALESS,
29276 IX86_BUILTIN_RSQRT14PD512,
29277 IX86_BUILTIN_RSQRT14PS512,
29278 IX86_BUILTIN_RSQRT14SD,
29279 IX86_BUILTIN_RSQRT14SS,
29280 IX86_BUILTIN_SCALEFPD512,
29281 IX86_BUILTIN_SCALEFPS512,
29282 IX86_BUILTIN_SCALEFSD,
29283 IX86_BUILTIN_SCALEFSS,
29284 IX86_BUILTIN_SHUFPD512,
29285 IX86_BUILTIN_SHUFPS512,
29286 IX86_BUILTIN_SHUF_F32x4,
29287 IX86_BUILTIN_SHUF_F64x2,
29288 IX86_BUILTIN_SHUF_I32x4,
29289 IX86_BUILTIN_SHUF_I64x2,
29290 IX86_BUILTIN_SQRTPD512,
29291 IX86_BUILTIN_SQRTPD512_MASK,
29292 IX86_BUILTIN_SQRTPS512_MASK,
29293 IX86_BUILTIN_SQRTPS_NR512,
29294 IX86_BUILTIN_SQRTSD_ROUND,
29295 IX86_BUILTIN_SQRTSS_ROUND,
29296 IX86_BUILTIN_STOREAPD512,
29297 IX86_BUILTIN_STOREAPS512,
29298 IX86_BUILTIN_STOREDQUDI512,
29299 IX86_BUILTIN_STOREDQUSI512,
29300 IX86_BUILTIN_STOREUPD512,
29301 IX86_BUILTIN_STOREUPS512,
29302 IX86_BUILTIN_SUBPD512,
29303 IX86_BUILTIN_SUBPS512,
29304 IX86_BUILTIN_SUBSD_ROUND,
29305 IX86_BUILTIN_SUBSS_ROUND,
29306 IX86_BUILTIN_UCMPD512,
29307 IX86_BUILTIN_UCMPQ512,
29308 IX86_BUILTIN_UNPCKHPD512,
29309 IX86_BUILTIN_UNPCKHPS512,
29310 IX86_BUILTIN_UNPCKLPD512,
29311 IX86_BUILTIN_UNPCKLPS512,
29312 IX86_BUILTIN_VCVTSD2SI32,
29313 IX86_BUILTIN_VCVTSD2SI64,
29314 IX86_BUILTIN_VCVTSD2USI32,
29315 IX86_BUILTIN_VCVTSD2USI64,
29316 IX86_BUILTIN_VCVTSS2SI32,
29317 IX86_BUILTIN_VCVTSS2SI64,
29318 IX86_BUILTIN_VCVTSS2USI32,
29319 IX86_BUILTIN_VCVTSS2USI64,
29320 IX86_BUILTIN_VCVTTSD2SI32,
29321 IX86_BUILTIN_VCVTTSD2SI64,
29322 IX86_BUILTIN_VCVTTSD2USI32,
29323 IX86_BUILTIN_VCVTTSD2USI64,
29324 IX86_BUILTIN_VCVTTSS2SI32,
29325 IX86_BUILTIN_VCVTTSS2SI64,
29326 IX86_BUILTIN_VCVTTSS2USI32,
29327 IX86_BUILTIN_VCVTTSS2USI64,
29328 IX86_BUILTIN_VFMADDPD512_MASK,
29329 IX86_BUILTIN_VFMADDPD512_MASK3,
29330 IX86_BUILTIN_VFMADDPD512_MASKZ,
29331 IX86_BUILTIN_VFMADDPS512_MASK,
29332 IX86_BUILTIN_VFMADDPS512_MASK3,
29333 IX86_BUILTIN_VFMADDPS512_MASKZ,
29334 IX86_BUILTIN_VFMADDSD3_ROUND,
29335 IX86_BUILTIN_VFMADDSS3_ROUND,
29336 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29337 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29338 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29339 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29340 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29341 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29342 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29343 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29344 IX86_BUILTIN_VFMSUBPD512_MASK3,
29345 IX86_BUILTIN_VFMSUBPS512_MASK3,
29346 IX86_BUILTIN_VFMSUBSD3_MASK3,
29347 IX86_BUILTIN_VFMSUBSS3_MASK3,
29348 IX86_BUILTIN_VFNMADDPD512_MASK,
29349 IX86_BUILTIN_VFNMADDPS512_MASK,
29350 IX86_BUILTIN_VFNMSUBPD512_MASK,
29351 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29352 IX86_BUILTIN_VFNMSUBPS512_MASK,
29353 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29354 IX86_BUILTIN_VPCLZCNTD512,
29355 IX86_BUILTIN_VPCLZCNTQ512,
29356 IX86_BUILTIN_VPCONFLICTD512,
29357 IX86_BUILTIN_VPCONFLICTQ512,
29358 IX86_BUILTIN_VPERMDF512,
29359 IX86_BUILTIN_VPERMDI512,
29360 IX86_BUILTIN_VPERMI2VARD512,
29361 IX86_BUILTIN_VPERMI2VARPD512,
29362 IX86_BUILTIN_VPERMI2VARPS512,
29363 IX86_BUILTIN_VPERMI2VARQ512,
29364 IX86_BUILTIN_VPERMILPD512,
29365 IX86_BUILTIN_VPERMILPS512,
29366 IX86_BUILTIN_VPERMILVARPD512,
29367 IX86_BUILTIN_VPERMILVARPS512,
29368 IX86_BUILTIN_VPERMT2VARD512,
29369 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29370 IX86_BUILTIN_VPERMT2VARPD512,
29371 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29372 IX86_BUILTIN_VPERMT2VARPS512,
29373 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29374 IX86_BUILTIN_VPERMT2VARQ512,
29375 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29376 IX86_BUILTIN_VPERMVARDF512,
29377 IX86_BUILTIN_VPERMVARDI512,
29378 IX86_BUILTIN_VPERMVARSF512,
29379 IX86_BUILTIN_VPERMVARSI512,
29380 IX86_BUILTIN_VTERNLOGD512_MASK,
29381 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29382 IX86_BUILTIN_VTERNLOGQ512_MASK,
29383 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29385 /* Mask arithmetic operations */
29386 IX86_BUILTIN_KAND16,
29387 IX86_BUILTIN_KANDN16,
29388 IX86_BUILTIN_KNOT16,
29389 IX86_BUILTIN_KOR16,
29390 IX86_BUILTIN_KORTESTC16,
29391 IX86_BUILTIN_KORTESTZ16,
29392 IX86_BUILTIN_KUNPCKBW,
29393 IX86_BUILTIN_KXNOR16,
29394 IX86_BUILTIN_KXOR16,
29395 IX86_BUILTIN_KMOV16,
29397 /* AVX512VL. */
29398 IX86_BUILTIN_PMOVUSQD256_MEM,
29399 IX86_BUILTIN_PMOVUSQD128_MEM,
29400 IX86_BUILTIN_PMOVSQD256_MEM,
29401 IX86_BUILTIN_PMOVSQD128_MEM,
29402 IX86_BUILTIN_PMOVQD256_MEM,
29403 IX86_BUILTIN_PMOVQD128_MEM,
29404 IX86_BUILTIN_PMOVUSQW256_MEM,
29405 IX86_BUILTIN_PMOVUSQW128_MEM,
29406 IX86_BUILTIN_PMOVSQW256_MEM,
29407 IX86_BUILTIN_PMOVSQW128_MEM,
29408 IX86_BUILTIN_PMOVQW256_MEM,
29409 IX86_BUILTIN_PMOVQW128_MEM,
29410 IX86_BUILTIN_PMOVUSQB256_MEM,
29411 IX86_BUILTIN_PMOVUSQB128_MEM,
29412 IX86_BUILTIN_PMOVSQB256_MEM,
29413 IX86_BUILTIN_PMOVSQB128_MEM,
29414 IX86_BUILTIN_PMOVQB256_MEM,
29415 IX86_BUILTIN_PMOVQB128_MEM,
29416 IX86_BUILTIN_PMOVUSDW256_MEM,
29417 IX86_BUILTIN_PMOVUSDW128_MEM,
29418 IX86_BUILTIN_PMOVSDW256_MEM,
29419 IX86_BUILTIN_PMOVSDW128_MEM,
29420 IX86_BUILTIN_PMOVDW256_MEM,
29421 IX86_BUILTIN_PMOVDW128_MEM,
29422 IX86_BUILTIN_PMOVUSDB256_MEM,
29423 IX86_BUILTIN_PMOVUSDB128_MEM,
29424 IX86_BUILTIN_PMOVSDB256_MEM,
29425 IX86_BUILTIN_PMOVSDB128_MEM,
29426 IX86_BUILTIN_PMOVDB256_MEM,
29427 IX86_BUILTIN_PMOVDB128_MEM,
29428 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29429 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29430 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29431 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29432 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29433 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29434 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29435 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29436 IX86_BUILTIN_LOADAPD256_MASK,
29437 IX86_BUILTIN_LOADAPD128_MASK,
29438 IX86_BUILTIN_LOADAPS256_MASK,
29439 IX86_BUILTIN_LOADAPS128_MASK,
29440 IX86_BUILTIN_STOREAPD256_MASK,
29441 IX86_BUILTIN_STOREAPD128_MASK,
29442 IX86_BUILTIN_STOREAPS256_MASK,
29443 IX86_BUILTIN_STOREAPS128_MASK,
29444 IX86_BUILTIN_LOADUPD256_MASK,
29445 IX86_BUILTIN_LOADUPD128_MASK,
29446 IX86_BUILTIN_LOADUPS256_MASK,
29447 IX86_BUILTIN_LOADUPS128_MASK,
29448 IX86_BUILTIN_STOREUPD256_MASK,
29449 IX86_BUILTIN_STOREUPD128_MASK,
29450 IX86_BUILTIN_STOREUPS256_MASK,
29451 IX86_BUILTIN_STOREUPS128_MASK,
29452 IX86_BUILTIN_LOADDQUDI256_MASK,
29453 IX86_BUILTIN_LOADDQUDI128_MASK,
29454 IX86_BUILTIN_LOADDQUSI256_MASK,
29455 IX86_BUILTIN_LOADDQUSI128_MASK,
29456 IX86_BUILTIN_LOADDQUHI256_MASK,
29457 IX86_BUILTIN_LOADDQUHI128_MASK,
29458 IX86_BUILTIN_LOADDQUQI256_MASK,
29459 IX86_BUILTIN_LOADDQUQI128_MASK,
29460 IX86_BUILTIN_STOREDQUDI256_MASK,
29461 IX86_BUILTIN_STOREDQUDI128_MASK,
29462 IX86_BUILTIN_STOREDQUSI256_MASK,
29463 IX86_BUILTIN_STOREDQUSI128_MASK,
29464 IX86_BUILTIN_STOREDQUHI256_MASK,
29465 IX86_BUILTIN_STOREDQUHI128_MASK,
29466 IX86_BUILTIN_STOREDQUQI256_MASK,
29467 IX86_BUILTIN_STOREDQUQI128_MASK,
29468 IX86_BUILTIN_COMPRESSPDSTORE256,
29469 IX86_BUILTIN_COMPRESSPDSTORE128,
29470 IX86_BUILTIN_COMPRESSPSSTORE256,
29471 IX86_BUILTIN_COMPRESSPSSTORE128,
29472 IX86_BUILTIN_PCOMPRESSQSTORE256,
29473 IX86_BUILTIN_PCOMPRESSQSTORE128,
29474 IX86_BUILTIN_PCOMPRESSDSTORE256,
29475 IX86_BUILTIN_PCOMPRESSDSTORE128,
29476 IX86_BUILTIN_EXPANDPDLOAD256,
29477 IX86_BUILTIN_EXPANDPDLOAD128,
29478 IX86_BUILTIN_EXPANDPSLOAD256,
29479 IX86_BUILTIN_EXPANDPSLOAD128,
29480 IX86_BUILTIN_PEXPANDQLOAD256,
29481 IX86_BUILTIN_PEXPANDQLOAD128,
29482 IX86_BUILTIN_PEXPANDDLOAD256,
29483 IX86_BUILTIN_PEXPANDDLOAD128,
29484 IX86_BUILTIN_EXPANDPDLOAD256Z,
29485 IX86_BUILTIN_EXPANDPDLOAD128Z,
29486 IX86_BUILTIN_EXPANDPSLOAD256Z,
29487 IX86_BUILTIN_EXPANDPSLOAD128Z,
29488 IX86_BUILTIN_PEXPANDQLOAD256Z,
29489 IX86_BUILTIN_PEXPANDQLOAD128Z,
29490 IX86_BUILTIN_PEXPANDDLOAD256Z,
29491 IX86_BUILTIN_PEXPANDDLOAD128Z,
29492 IX86_BUILTIN_PALIGNR256_MASK,
29493 IX86_BUILTIN_PALIGNR128_MASK,
29494 IX86_BUILTIN_MOVDQA64_256_MASK,
29495 IX86_BUILTIN_MOVDQA64_128_MASK,
29496 IX86_BUILTIN_MOVDQA32_256_MASK,
29497 IX86_BUILTIN_MOVDQA32_128_MASK,
29498 IX86_BUILTIN_MOVAPD256_MASK,
29499 IX86_BUILTIN_MOVAPD128_MASK,
29500 IX86_BUILTIN_MOVAPS256_MASK,
29501 IX86_BUILTIN_MOVAPS128_MASK,
29502 IX86_BUILTIN_MOVDQUHI256_MASK,
29503 IX86_BUILTIN_MOVDQUHI128_MASK,
29504 IX86_BUILTIN_MOVDQUQI256_MASK,
29505 IX86_BUILTIN_MOVDQUQI128_MASK,
29506 IX86_BUILTIN_MINPS128_MASK,
29507 IX86_BUILTIN_MAXPS128_MASK,
29508 IX86_BUILTIN_MINPD128_MASK,
29509 IX86_BUILTIN_MAXPD128_MASK,
29510 IX86_BUILTIN_MAXPD256_MASK,
29511 IX86_BUILTIN_MAXPS256_MASK,
29512 IX86_BUILTIN_MINPD256_MASK,
29513 IX86_BUILTIN_MINPS256_MASK,
29514 IX86_BUILTIN_MULPS128_MASK,
29515 IX86_BUILTIN_DIVPS128_MASK,
29516 IX86_BUILTIN_MULPD128_MASK,
29517 IX86_BUILTIN_DIVPD128_MASK,
29518 IX86_BUILTIN_DIVPD256_MASK,
29519 IX86_BUILTIN_DIVPS256_MASK,
29520 IX86_BUILTIN_MULPD256_MASK,
29521 IX86_BUILTIN_MULPS256_MASK,
29522 IX86_BUILTIN_ADDPD128_MASK,
29523 IX86_BUILTIN_ADDPD256_MASK,
29524 IX86_BUILTIN_ADDPS128_MASK,
29525 IX86_BUILTIN_ADDPS256_MASK,
29526 IX86_BUILTIN_SUBPD128_MASK,
29527 IX86_BUILTIN_SUBPD256_MASK,
29528 IX86_BUILTIN_SUBPS128_MASK,
29529 IX86_BUILTIN_SUBPS256_MASK,
29530 IX86_BUILTIN_XORPD256_MASK,
29531 IX86_BUILTIN_XORPD128_MASK,
29532 IX86_BUILTIN_XORPS256_MASK,
29533 IX86_BUILTIN_XORPS128_MASK,
29534 IX86_BUILTIN_ORPD256_MASK,
29535 IX86_BUILTIN_ORPD128_MASK,
29536 IX86_BUILTIN_ORPS256_MASK,
29537 IX86_BUILTIN_ORPS128_MASK,
29538 IX86_BUILTIN_BROADCASTF32x2_256,
29539 IX86_BUILTIN_BROADCASTI32x2_256,
29540 IX86_BUILTIN_BROADCASTI32x2_128,
29541 IX86_BUILTIN_BROADCASTF64X2_256,
29542 IX86_BUILTIN_BROADCASTI64X2_256,
29543 IX86_BUILTIN_BROADCASTF32X4_256,
29544 IX86_BUILTIN_BROADCASTI32X4_256,
29545 IX86_BUILTIN_EXTRACTF32X4_256,
29546 IX86_BUILTIN_EXTRACTI32X4_256,
29547 IX86_BUILTIN_DBPSADBW256,
29548 IX86_BUILTIN_DBPSADBW128,
29549 IX86_BUILTIN_CVTTPD2QQ256,
29550 IX86_BUILTIN_CVTTPD2QQ128,
29551 IX86_BUILTIN_CVTTPD2UQQ256,
29552 IX86_BUILTIN_CVTTPD2UQQ128,
29553 IX86_BUILTIN_CVTPD2QQ256,
29554 IX86_BUILTIN_CVTPD2QQ128,
29555 IX86_BUILTIN_CVTPD2UQQ256,
29556 IX86_BUILTIN_CVTPD2UQQ128,
29557 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29558 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29559 IX86_BUILTIN_CVTTPS2QQ256,
29560 IX86_BUILTIN_CVTTPS2QQ128,
29561 IX86_BUILTIN_CVTTPS2UQQ256,
29562 IX86_BUILTIN_CVTTPS2UQQ128,
29563 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29564 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29565 IX86_BUILTIN_CVTTPS2UDQ256,
29566 IX86_BUILTIN_CVTTPS2UDQ128,
29567 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29568 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29569 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29570 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29571 IX86_BUILTIN_CVTPD2DQ256_MASK,
29572 IX86_BUILTIN_CVTPD2DQ128_MASK,
29573 IX86_BUILTIN_CVTDQ2PD256_MASK,
29574 IX86_BUILTIN_CVTDQ2PD128_MASK,
29575 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29576 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29577 IX86_BUILTIN_CVTDQ2PS256_MASK,
29578 IX86_BUILTIN_CVTDQ2PS128_MASK,
29579 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29580 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29581 IX86_BUILTIN_CVTPS2PD256_MASK,
29582 IX86_BUILTIN_CVTPS2PD128_MASK,
29583 IX86_BUILTIN_PBROADCASTB256_MASK,
29584 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29585 IX86_BUILTIN_PBROADCASTB128_MASK,
29586 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29587 IX86_BUILTIN_PBROADCASTW256_MASK,
29588 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29589 IX86_BUILTIN_PBROADCASTW128_MASK,
29590 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29591 IX86_BUILTIN_PBROADCASTD256_MASK,
29592 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29593 IX86_BUILTIN_PBROADCASTD128_MASK,
29594 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29595 IX86_BUILTIN_PBROADCASTQ256_MASK,
29596 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29597 IX86_BUILTIN_PBROADCASTQ128_MASK,
29598 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29599 IX86_BUILTIN_BROADCASTSS256,
29600 IX86_BUILTIN_BROADCASTSS128,
29601 IX86_BUILTIN_BROADCASTSD256,
29602 IX86_BUILTIN_EXTRACTF64X2_256,
29603 IX86_BUILTIN_EXTRACTI64X2_256,
29604 IX86_BUILTIN_INSERTF32X4_256,
29605 IX86_BUILTIN_INSERTI32X4_256,
29606 IX86_BUILTIN_PMOVSXBW256_MASK,
29607 IX86_BUILTIN_PMOVSXBW128_MASK,
29608 IX86_BUILTIN_PMOVSXBD256_MASK,
29609 IX86_BUILTIN_PMOVSXBD128_MASK,
29610 IX86_BUILTIN_PMOVSXBQ256_MASK,
29611 IX86_BUILTIN_PMOVSXBQ128_MASK,
29612 IX86_BUILTIN_PMOVSXWD256_MASK,
29613 IX86_BUILTIN_PMOVSXWD128_MASK,
29614 IX86_BUILTIN_PMOVSXWQ256_MASK,
29615 IX86_BUILTIN_PMOVSXWQ128_MASK,
29616 IX86_BUILTIN_PMOVSXDQ256_MASK,
29617 IX86_BUILTIN_PMOVSXDQ128_MASK,
29618 IX86_BUILTIN_PMOVZXBW256_MASK,
29619 IX86_BUILTIN_PMOVZXBW128_MASK,
29620 IX86_BUILTIN_PMOVZXBD256_MASK,
29621 IX86_BUILTIN_PMOVZXBD128_MASK,
29622 IX86_BUILTIN_PMOVZXBQ256_MASK,
29623 IX86_BUILTIN_PMOVZXBQ128_MASK,
29624 IX86_BUILTIN_PMOVZXWD256_MASK,
29625 IX86_BUILTIN_PMOVZXWD128_MASK,
29626 IX86_BUILTIN_PMOVZXWQ256_MASK,
29627 IX86_BUILTIN_PMOVZXWQ128_MASK,
29628 IX86_BUILTIN_PMOVZXDQ256_MASK,
29629 IX86_BUILTIN_PMOVZXDQ128_MASK,
29630 IX86_BUILTIN_REDUCEPD256_MASK,
29631 IX86_BUILTIN_REDUCEPD128_MASK,
29632 IX86_BUILTIN_REDUCEPS256_MASK,
29633 IX86_BUILTIN_REDUCEPS128_MASK,
29634 IX86_BUILTIN_REDUCESD_MASK,
29635 IX86_BUILTIN_REDUCESS_MASK,
29636 IX86_BUILTIN_VPERMVARHI256_MASK,
29637 IX86_BUILTIN_VPERMVARHI128_MASK,
29638 IX86_BUILTIN_VPERMT2VARHI256,
29639 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29640 IX86_BUILTIN_VPERMT2VARHI128,
29641 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29642 IX86_BUILTIN_VPERMI2VARHI256,
29643 IX86_BUILTIN_VPERMI2VARHI128,
29644 IX86_BUILTIN_RCP14PD256,
29645 IX86_BUILTIN_RCP14PD128,
29646 IX86_BUILTIN_RCP14PS256,
29647 IX86_BUILTIN_RCP14PS128,
29648 IX86_BUILTIN_RSQRT14PD256_MASK,
29649 IX86_BUILTIN_RSQRT14PD128_MASK,
29650 IX86_BUILTIN_RSQRT14PS256_MASK,
29651 IX86_BUILTIN_RSQRT14PS128_MASK,
29652 IX86_BUILTIN_SQRTPD256_MASK,
29653 IX86_BUILTIN_SQRTPD128_MASK,
29654 IX86_BUILTIN_SQRTPS256_MASK,
29655 IX86_BUILTIN_SQRTPS128_MASK,
29656 IX86_BUILTIN_PADDB128_MASK,
29657 IX86_BUILTIN_PADDW128_MASK,
29658 IX86_BUILTIN_PADDD128_MASK,
29659 IX86_BUILTIN_PADDQ128_MASK,
29660 IX86_BUILTIN_PSUBB128_MASK,
29661 IX86_BUILTIN_PSUBW128_MASK,
29662 IX86_BUILTIN_PSUBD128_MASK,
29663 IX86_BUILTIN_PSUBQ128_MASK,
29664 IX86_BUILTIN_PADDSB128_MASK,
29665 IX86_BUILTIN_PADDSW128_MASK,
29666 IX86_BUILTIN_PSUBSB128_MASK,
29667 IX86_BUILTIN_PSUBSW128_MASK,
29668 IX86_BUILTIN_PADDUSB128_MASK,
29669 IX86_BUILTIN_PADDUSW128_MASK,
29670 IX86_BUILTIN_PSUBUSB128_MASK,
29671 IX86_BUILTIN_PSUBUSW128_MASK,
29672 IX86_BUILTIN_PADDB256_MASK,
29673 IX86_BUILTIN_PADDW256_MASK,
29674 IX86_BUILTIN_PADDD256_MASK,
29675 IX86_BUILTIN_PADDQ256_MASK,
29676 IX86_BUILTIN_PADDSB256_MASK,
29677 IX86_BUILTIN_PADDSW256_MASK,
29678 IX86_BUILTIN_PADDUSB256_MASK,
29679 IX86_BUILTIN_PADDUSW256_MASK,
29680 IX86_BUILTIN_PSUBB256_MASK,
29681 IX86_BUILTIN_PSUBW256_MASK,
29682 IX86_BUILTIN_PSUBD256_MASK,
29683 IX86_BUILTIN_PSUBQ256_MASK,
29684 IX86_BUILTIN_PSUBSB256_MASK,
29685 IX86_BUILTIN_PSUBSW256_MASK,
29686 IX86_BUILTIN_PSUBUSB256_MASK,
29687 IX86_BUILTIN_PSUBUSW256_MASK,
29688 IX86_BUILTIN_SHUF_F64x2_256,
29689 IX86_BUILTIN_SHUF_I64x2_256,
29690 IX86_BUILTIN_SHUF_I32x4_256,
29691 IX86_BUILTIN_SHUF_F32x4_256,
29692 IX86_BUILTIN_PMOVWB128,
29693 IX86_BUILTIN_PMOVWB256,
29694 IX86_BUILTIN_PMOVSWB128,
29695 IX86_BUILTIN_PMOVSWB256,
29696 IX86_BUILTIN_PMOVUSWB128,
29697 IX86_BUILTIN_PMOVUSWB256,
29698 IX86_BUILTIN_PMOVDB128,
29699 IX86_BUILTIN_PMOVDB256,
29700 IX86_BUILTIN_PMOVSDB128,
29701 IX86_BUILTIN_PMOVSDB256,
29702 IX86_BUILTIN_PMOVUSDB128,
29703 IX86_BUILTIN_PMOVUSDB256,
29704 IX86_BUILTIN_PMOVDW128,
29705 IX86_BUILTIN_PMOVDW256,
29706 IX86_BUILTIN_PMOVSDW128,
29707 IX86_BUILTIN_PMOVSDW256,
29708 IX86_BUILTIN_PMOVUSDW128,
29709 IX86_BUILTIN_PMOVUSDW256,
29710 IX86_BUILTIN_PMOVQB128,
29711 IX86_BUILTIN_PMOVQB256,
29712 IX86_BUILTIN_PMOVSQB128,
29713 IX86_BUILTIN_PMOVSQB256,
29714 IX86_BUILTIN_PMOVUSQB128,
29715 IX86_BUILTIN_PMOVUSQB256,
29716 IX86_BUILTIN_PMOVQW128,
29717 IX86_BUILTIN_PMOVQW256,
29718 IX86_BUILTIN_PMOVSQW128,
29719 IX86_BUILTIN_PMOVSQW256,
29720 IX86_BUILTIN_PMOVUSQW128,
29721 IX86_BUILTIN_PMOVUSQW256,
29722 IX86_BUILTIN_PMOVQD128,
29723 IX86_BUILTIN_PMOVQD256,
29724 IX86_BUILTIN_PMOVSQD128,
29725 IX86_BUILTIN_PMOVSQD256,
29726 IX86_BUILTIN_PMOVUSQD128,
29727 IX86_BUILTIN_PMOVUSQD256,
29728 IX86_BUILTIN_RANGEPD256,
29729 IX86_BUILTIN_RANGEPD128,
29730 IX86_BUILTIN_RANGEPS256,
29731 IX86_BUILTIN_RANGEPS128,
29732 IX86_BUILTIN_GETEXPPS256,
29733 IX86_BUILTIN_GETEXPPD256,
29734 IX86_BUILTIN_GETEXPPS128,
29735 IX86_BUILTIN_GETEXPPD128,
29736 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29737 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29738 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29739 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29740 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29741 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29742 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29743 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29744 IX86_BUILTIN_PABSQ256,
29745 IX86_BUILTIN_PABSQ128,
29746 IX86_BUILTIN_PABSD256_MASK,
29747 IX86_BUILTIN_PABSD128_MASK,
29748 IX86_BUILTIN_PMULHRSW256_MASK,
29749 IX86_BUILTIN_PMULHRSW128_MASK,
29750 IX86_BUILTIN_PMULHUW128_MASK,
29751 IX86_BUILTIN_PMULHUW256_MASK,
29752 IX86_BUILTIN_PMULHW256_MASK,
29753 IX86_BUILTIN_PMULHW128_MASK,
29754 IX86_BUILTIN_PMULLW256_MASK,
29755 IX86_BUILTIN_PMULLW128_MASK,
29756 IX86_BUILTIN_PMULLQ256,
29757 IX86_BUILTIN_PMULLQ128,
29758 IX86_BUILTIN_ANDPD256_MASK,
29759 IX86_BUILTIN_ANDPD128_MASK,
29760 IX86_BUILTIN_ANDPS256_MASK,
29761 IX86_BUILTIN_ANDPS128_MASK,
29762 IX86_BUILTIN_ANDNPD256_MASK,
29763 IX86_BUILTIN_ANDNPD128_MASK,
29764 IX86_BUILTIN_ANDNPS256_MASK,
29765 IX86_BUILTIN_ANDNPS128_MASK,
29766 IX86_BUILTIN_PSLLWI128_MASK,
29767 IX86_BUILTIN_PSLLDI128_MASK,
29768 IX86_BUILTIN_PSLLQI128_MASK,
29769 IX86_BUILTIN_PSLLW128_MASK,
29770 IX86_BUILTIN_PSLLD128_MASK,
29771 IX86_BUILTIN_PSLLQ128_MASK,
29772 IX86_BUILTIN_PSLLWI256_MASK ,
29773 IX86_BUILTIN_PSLLW256_MASK,
29774 IX86_BUILTIN_PSLLDI256_MASK,
29775 IX86_BUILTIN_PSLLD256_MASK,
29776 IX86_BUILTIN_PSLLQI256_MASK,
29777 IX86_BUILTIN_PSLLQ256_MASK,
29778 IX86_BUILTIN_PSRADI128_MASK,
29779 IX86_BUILTIN_PSRAD128_MASK,
29780 IX86_BUILTIN_PSRADI256_MASK,
29781 IX86_BUILTIN_PSRAD256_MASK,
29782 IX86_BUILTIN_PSRAQI128_MASK,
29783 IX86_BUILTIN_PSRAQ128_MASK,
29784 IX86_BUILTIN_PSRAQI256_MASK,
29785 IX86_BUILTIN_PSRAQ256_MASK,
29786 IX86_BUILTIN_PANDD256,
29787 IX86_BUILTIN_PANDD128,
29788 IX86_BUILTIN_PSRLDI128_MASK,
29789 IX86_BUILTIN_PSRLD128_MASK,
29790 IX86_BUILTIN_PSRLDI256_MASK,
29791 IX86_BUILTIN_PSRLD256_MASK,
29792 IX86_BUILTIN_PSRLQI128_MASK,
29793 IX86_BUILTIN_PSRLQ128_MASK,
29794 IX86_BUILTIN_PSRLQI256_MASK,
29795 IX86_BUILTIN_PSRLQ256_MASK,
29796 IX86_BUILTIN_PANDQ256,
29797 IX86_BUILTIN_PANDQ128,
29798 IX86_BUILTIN_PANDND256,
29799 IX86_BUILTIN_PANDND128,
29800 IX86_BUILTIN_PANDNQ256,
29801 IX86_BUILTIN_PANDNQ128,
29802 IX86_BUILTIN_PORD256,
29803 IX86_BUILTIN_PORD128,
29804 IX86_BUILTIN_PORQ256,
29805 IX86_BUILTIN_PORQ128,
29806 IX86_BUILTIN_PXORD256,
29807 IX86_BUILTIN_PXORD128,
29808 IX86_BUILTIN_PXORQ256,
29809 IX86_BUILTIN_PXORQ128,
29810 IX86_BUILTIN_PACKSSWB256_MASK,
29811 IX86_BUILTIN_PACKSSWB128_MASK,
29812 IX86_BUILTIN_PACKUSWB256_MASK,
29813 IX86_BUILTIN_PACKUSWB128_MASK,
29814 IX86_BUILTIN_RNDSCALEPS256,
29815 IX86_BUILTIN_RNDSCALEPD256,
29816 IX86_BUILTIN_RNDSCALEPS128,
29817 IX86_BUILTIN_RNDSCALEPD128,
29818 IX86_BUILTIN_VTERNLOGQ256_MASK,
29819 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29820 IX86_BUILTIN_VTERNLOGD256_MASK,
29821 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29822 IX86_BUILTIN_VTERNLOGQ128_MASK,
29823 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29824 IX86_BUILTIN_VTERNLOGD128_MASK,
29825 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29826 IX86_BUILTIN_SCALEFPD256,
29827 IX86_BUILTIN_SCALEFPS256,
29828 IX86_BUILTIN_SCALEFPD128,
29829 IX86_BUILTIN_SCALEFPS128,
29830 IX86_BUILTIN_VFMADDPD256_MASK,
29831 IX86_BUILTIN_VFMADDPD256_MASK3,
29832 IX86_BUILTIN_VFMADDPD256_MASKZ,
29833 IX86_BUILTIN_VFMADDPD128_MASK,
29834 IX86_BUILTIN_VFMADDPD128_MASK3,
29835 IX86_BUILTIN_VFMADDPD128_MASKZ,
29836 IX86_BUILTIN_VFMADDPS256_MASK,
29837 IX86_BUILTIN_VFMADDPS256_MASK3,
29838 IX86_BUILTIN_VFMADDPS256_MASKZ,
29839 IX86_BUILTIN_VFMADDPS128_MASK,
29840 IX86_BUILTIN_VFMADDPS128_MASK3,
29841 IX86_BUILTIN_VFMADDPS128_MASKZ,
29842 IX86_BUILTIN_VFMSUBPD256_MASK3,
29843 IX86_BUILTIN_VFMSUBPD128_MASK3,
29844 IX86_BUILTIN_VFMSUBPS256_MASK3,
29845 IX86_BUILTIN_VFMSUBPS128_MASK3,
29846 IX86_BUILTIN_VFNMADDPD256_MASK,
29847 IX86_BUILTIN_VFNMADDPD128_MASK,
29848 IX86_BUILTIN_VFNMADDPS256_MASK,
29849 IX86_BUILTIN_VFNMADDPS128_MASK,
29850 IX86_BUILTIN_VFNMSUBPD256_MASK,
29851 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29852 IX86_BUILTIN_VFNMSUBPD128_MASK,
29853 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29854 IX86_BUILTIN_VFNMSUBPS256_MASK,
29855 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29856 IX86_BUILTIN_VFNMSUBPS128_MASK,
29857 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29858 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29859 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29860 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29861 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29862 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29863 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29864 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29865 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29866 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29867 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29868 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29869 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29870 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29871 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29872 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29873 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29874 IX86_BUILTIN_INSERTF64X2_256,
29875 IX86_BUILTIN_INSERTI64X2_256,
29876 IX86_BUILTIN_PSRAVV16HI,
29877 IX86_BUILTIN_PSRAVV8HI,
29878 IX86_BUILTIN_PMADDUBSW256_MASK,
29879 IX86_BUILTIN_PMADDUBSW128_MASK,
29880 IX86_BUILTIN_PMADDWD256_MASK,
29881 IX86_BUILTIN_PMADDWD128_MASK,
29882 IX86_BUILTIN_PSRLVV16HI,
29883 IX86_BUILTIN_PSRLVV8HI,
29884 IX86_BUILTIN_CVTPS2DQ256_MASK,
29885 IX86_BUILTIN_CVTPS2DQ128_MASK,
29886 IX86_BUILTIN_CVTPS2UDQ256,
29887 IX86_BUILTIN_CVTPS2UDQ128,
29888 IX86_BUILTIN_CVTPS2QQ256,
29889 IX86_BUILTIN_CVTPS2QQ128,
29890 IX86_BUILTIN_CVTPS2UQQ256,
29891 IX86_BUILTIN_CVTPS2UQQ128,
29892 IX86_BUILTIN_GETMANTPS256,
29893 IX86_BUILTIN_GETMANTPS128,
29894 IX86_BUILTIN_GETMANTPD256,
29895 IX86_BUILTIN_GETMANTPD128,
29896 IX86_BUILTIN_MOVDDUP256_MASK,
29897 IX86_BUILTIN_MOVDDUP128_MASK,
29898 IX86_BUILTIN_MOVSHDUP256_MASK,
29899 IX86_BUILTIN_MOVSHDUP128_MASK,
29900 IX86_BUILTIN_MOVSLDUP256_MASK,
29901 IX86_BUILTIN_MOVSLDUP128_MASK,
29902 IX86_BUILTIN_CVTQQ2PS256,
29903 IX86_BUILTIN_CVTQQ2PS128,
29904 IX86_BUILTIN_CVTUQQ2PS256,
29905 IX86_BUILTIN_CVTUQQ2PS128,
29906 IX86_BUILTIN_CVTQQ2PD256,
29907 IX86_BUILTIN_CVTQQ2PD128,
29908 IX86_BUILTIN_CVTUQQ2PD256,
29909 IX86_BUILTIN_CVTUQQ2PD128,
29910 IX86_BUILTIN_VPERMT2VARQ256,
29911 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29912 IX86_BUILTIN_VPERMT2VARD256,
29913 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29914 IX86_BUILTIN_VPERMI2VARQ256,
29915 IX86_BUILTIN_VPERMI2VARD256,
29916 IX86_BUILTIN_VPERMT2VARPD256,
29917 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29918 IX86_BUILTIN_VPERMT2VARPS256,
29919 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29920 IX86_BUILTIN_VPERMI2VARPD256,
29921 IX86_BUILTIN_VPERMI2VARPS256,
29922 IX86_BUILTIN_VPERMT2VARQ128,
29923 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29924 IX86_BUILTIN_VPERMT2VARD128,
29925 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29926 IX86_BUILTIN_VPERMI2VARQ128,
29927 IX86_BUILTIN_VPERMI2VARD128,
29928 IX86_BUILTIN_VPERMT2VARPD128,
29929 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29930 IX86_BUILTIN_VPERMT2VARPS128,
29931 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29932 IX86_BUILTIN_VPERMI2VARPD128,
29933 IX86_BUILTIN_VPERMI2VARPS128,
29934 IX86_BUILTIN_PSHUFB256_MASK,
29935 IX86_BUILTIN_PSHUFB128_MASK,
29936 IX86_BUILTIN_PSHUFHW256_MASK,
29937 IX86_BUILTIN_PSHUFHW128_MASK,
29938 IX86_BUILTIN_PSHUFLW256_MASK,
29939 IX86_BUILTIN_PSHUFLW128_MASK,
29940 IX86_BUILTIN_PSHUFD256_MASK,
29941 IX86_BUILTIN_PSHUFD128_MASK,
29942 IX86_BUILTIN_SHUFPD256_MASK,
29943 IX86_BUILTIN_SHUFPD128_MASK,
29944 IX86_BUILTIN_SHUFPS256_MASK,
29945 IX86_BUILTIN_SHUFPS128_MASK,
29946 IX86_BUILTIN_PROLVQ256,
29947 IX86_BUILTIN_PROLVQ128,
29948 IX86_BUILTIN_PROLQ256,
29949 IX86_BUILTIN_PROLQ128,
29950 IX86_BUILTIN_PRORVQ256,
29951 IX86_BUILTIN_PRORVQ128,
29952 IX86_BUILTIN_PRORQ256,
29953 IX86_BUILTIN_PRORQ128,
29954 IX86_BUILTIN_PSRAVQ128,
29955 IX86_BUILTIN_PSRAVQ256,
29956 IX86_BUILTIN_PSLLVV4DI_MASK,
29957 IX86_BUILTIN_PSLLVV2DI_MASK,
29958 IX86_BUILTIN_PSLLVV8SI_MASK,
29959 IX86_BUILTIN_PSLLVV4SI_MASK,
29960 IX86_BUILTIN_PSRAVV8SI_MASK,
29961 IX86_BUILTIN_PSRAVV4SI_MASK,
29962 IX86_BUILTIN_PSRLVV4DI_MASK,
29963 IX86_BUILTIN_PSRLVV2DI_MASK,
29964 IX86_BUILTIN_PSRLVV8SI_MASK,
29965 IX86_BUILTIN_PSRLVV4SI_MASK,
29966 IX86_BUILTIN_PSRAWI256_MASK,
29967 IX86_BUILTIN_PSRAW256_MASK,
29968 IX86_BUILTIN_PSRAWI128_MASK,
29969 IX86_BUILTIN_PSRAW128_MASK,
29970 IX86_BUILTIN_PSRLWI256_MASK,
29971 IX86_BUILTIN_PSRLW256_MASK,
29972 IX86_BUILTIN_PSRLWI128_MASK,
29973 IX86_BUILTIN_PSRLW128_MASK,
29974 IX86_BUILTIN_PRORVD256,
29975 IX86_BUILTIN_PROLVD256,
29976 IX86_BUILTIN_PRORD256,
29977 IX86_BUILTIN_PROLD256,
29978 IX86_BUILTIN_PRORVD128,
29979 IX86_BUILTIN_PROLVD128,
29980 IX86_BUILTIN_PRORD128,
29981 IX86_BUILTIN_PROLD128,
29982 IX86_BUILTIN_FPCLASSPD256,
29983 IX86_BUILTIN_FPCLASSPD128,
29984 IX86_BUILTIN_FPCLASSSD,
29985 IX86_BUILTIN_FPCLASSPS256,
29986 IX86_BUILTIN_FPCLASSPS128,
29987 IX86_BUILTIN_FPCLASSSS,
29988 IX86_BUILTIN_CVTB2MASK128,
29989 IX86_BUILTIN_CVTB2MASK256,
29990 IX86_BUILTIN_CVTW2MASK128,
29991 IX86_BUILTIN_CVTW2MASK256,
29992 IX86_BUILTIN_CVTD2MASK128,
29993 IX86_BUILTIN_CVTD2MASK256,
29994 IX86_BUILTIN_CVTQ2MASK128,
29995 IX86_BUILTIN_CVTQ2MASK256,
29996 IX86_BUILTIN_CVTMASK2B128,
29997 IX86_BUILTIN_CVTMASK2B256,
29998 IX86_BUILTIN_CVTMASK2W128,
29999 IX86_BUILTIN_CVTMASK2W256,
30000 IX86_BUILTIN_CVTMASK2D128,
30001 IX86_BUILTIN_CVTMASK2D256,
30002 IX86_BUILTIN_CVTMASK2Q128,
30003 IX86_BUILTIN_CVTMASK2Q256,
30004 IX86_BUILTIN_PCMPEQB128_MASK,
30005 IX86_BUILTIN_PCMPEQB256_MASK,
30006 IX86_BUILTIN_PCMPEQW128_MASK,
30007 IX86_BUILTIN_PCMPEQW256_MASK,
30008 IX86_BUILTIN_PCMPEQD128_MASK,
30009 IX86_BUILTIN_PCMPEQD256_MASK,
30010 IX86_BUILTIN_PCMPEQQ128_MASK,
30011 IX86_BUILTIN_PCMPEQQ256_MASK,
30012 IX86_BUILTIN_PCMPGTB128_MASK,
30013 IX86_BUILTIN_PCMPGTB256_MASK,
30014 IX86_BUILTIN_PCMPGTW128_MASK,
30015 IX86_BUILTIN_PCMPGTW256_MASK,
30016 IX86_BUILTIN_PCMPGTD128_MASK,
30017 IX86_BUILTIN_PCMPGTD256_MASK,
30018 IX86_BUILTIN_PCMPGTQ128_MASK,
30019 IX86_BUILTIN_PCMPGTQ256_MASK,
30020 IX86_BUILTIN_PTESTMB128,
30021 IX86_BUILTIN_PTESTMB256,
30022 IX86_BUILTIN_PTESTMW128,
30023 IX86_BUILTIN_PTESTMW256,
30024 IX86_BUILTIN_PTESTMD128,
30025 IX86_BUILTIN_PTESTMD256,
30026 IX86_BUILTIN_PTESTMQ128,
30027 IX86_BUILTIN_PTESTMQ256,
30028 IX86_BUILTIN_PTESTNMB128,
30029 IX86_BUILTIN_PTESTNMB256,
30030 IX86_BUILTIN_PTESTNMW128,
30031 IX86_BUILTIN_PTESTNMW256,
30032 IX86_BUILTIN_PTESTNMD128,
30033 IX86_BUILTIN_PTESTNMD256,
30034 IX86_BUILTIN_PTESTNMQ128,
30035 IX86_BUILTIN_PTESTNMQ256,
30036 IX86_BUILTIN_PBROADCASTMB128,
30037 IX86_BUILTIN_PBROADCASTMB256,
30038 IX86_BUILTIN_PBROADCASTMW128,
30039 IX86_BUILTIN_PBROADCASTMW256,
30040 IX86_BUILTIN_COMPRESSPD256,
30041 IX86_BUILTIN_COMPRESSPD128,
30042 IX86_BUILTIN_COMPRESSPS256,
30043 IX86_BUILTIN_COMPRESSPS128,
30044 IX86_BUILTIN_PCOMPRESSQ256,
30045 IX86_BUILTIN_PCOMPRESSQ128,
30046 IX86_BUILTIN_PCOMPRESSD256,
30047 IX86_BUILTIN_PCOMPRESSD128,
30048 IX86_BUILTIN_EXPANDPD256,
30049 IX86_BUILTIN_EXPANDPD128,
30050 IX86_BUILTIN_EXPANDPS256,
30051 IX86_BUILTIN_EXPANDPS128,
30052 IX86_BUILTIN_PEXPANDQ256,
30053 IX86_BUILTIN_PEXPANDQ128,
30054 IX86_BUILTIN_PEXPANDD256,
30055 IX86_BUILTIN_PEXPANDD128,
30056 IX86_BUILTIN_EXPANDPD256Z,
30057 IX86_BUILTIN_EXPANDPD128Z,
30058 IX86_BUILTIN_EXPANDPS256Z,
30059 IX86_BUILTIN_EXPANDPS128Z,
30060 IX86_BUILTIN_PEXPANDQ256Z,
30061 IX86_BUILTIN_PEXPANDQ128Z,
30062 IX86_BUILTIN_PEXPANDD256Z,
30063 IX86_BUILTIN_PEXPANDD128Z,
30064 IX86_BUILTIN_PMAXSD256_MASK,
30065 IX86_BUILTIN_PMINSD256_MASK,
30066 IX86_BUILTIN_PMAXUD256_MASK,
30067 IX86_BUILTIN_PMINUD256_MASK,
30068 IX86_BUILTIN_PMAXSD128_MASK,
30069 IX86_BUILTIN_PMINSD128_MASK,
30070 IX86_BUILTIN_PMAXUD128_MASK,
30071 IX86_BUILTIN_PMINUD128_MASK,
30072 IX86_BUILTIN_PMAXSQ256_MASK,
30073 IX86_BUILTIN_PMINSQ256_MASK,
30074 IX86_BUILTIN_PMAXUQ256_MASK,
30075 IX86_BUILTIN_PMINUQ256_MASK,
30076 IX86_BUILTIN_PMAXSQ128_MASK,
30077 IX86_BUILTIN_PMINSQ128_MASK,
30078 IX86_BUILTIN_PMAXUQ128_MASK,
30079 IX86_BUILTIN_PMINUQ128_MASK,
30080 IX86_BUILTIN_PMINSB256_MASK,
30081 IX86_BUILTIN_PMINUB256_MASK,
30082 IX86_BUILTIN_PMAXSB256_MASK,
30083 IX86_BUILTIN_PMAXUB256_MASK,
30084 IX86_BUILTIN_PMINSB128_MASK,
30085 IX86_BUILTIN_PMINUB128_MASK,
30086 IX86_BUILTIN_PMAXSB128_MASK,
30087 IX86_BUILTIN_PMAXUB128_MASK,
30088 IX86_BUILTIN_PMINSW256_MASK,
30089 IX86_BUILTIN_PMINUW256_MASK,
30090 IX86_BUILTIN_PMAXSW256_MASK,
30091 IX86_BUILTIN_PMAXUW256_MASK,
30092 IX86_BUILTIN_PMINSW128_MASK,
30093 IX86_BUILTIN_PMINUW128_MASK,
30094 IX86_BUILTIN_PMAXSW128_MASK,
30095 IX86_BUILTIN_PMAXUW128_MASK,
30096 IX86_BUILTIN_VPCONFLICTQ256,
30097 IX86_BUILTIN_VPCONFLICTD256,
30098 IX86_BUILTIN_VPCLZCNTQ256,
30099 IX86_BUILTIN_VPCLZCNTD256,
30100 IX86_BUILTIN_UNPCKHPD256_MASK,
30101 IX86_BUILTIN_UNPCKHPD128_MASK,
30102 IX86_BUILTIN_UNPCKHPS256_MASK,
30103 IX86_BUILTIN_UNPCKHPS128_MASK,
30104 IX86_BUILTIN_UNPCKLPD256_MASK,
30105 IX86_BUILTIN_UNPCKLPD128_MASK,
30106 IX86_BUILTIN_UNPCKLPS256_MASK,
30107 IX86_BUILTIN_VPCONFLICTQ128,
30108 IX86_BUILTIN_VPCONFLICTD128,
30109 IX86_BUILTIN_VPCLZCNTQ128,
30110 IX86_BUILTIN_VPCLZCNTD128,
30111 IX86_BUILTIN_UNPCKLPS128_MASK,
30112 IX86_BUILTIN_ALIGND256,
30113 IX86_BUILTIN_ALIGNQ256,
30114 IX86_BUILTIN_ALIGND128,
30115 IX86_BUILTIN_ALIGNQ128,
30116 IX86_BUILTIN_CVTPS2PH256_MASK,
30117 IX86_BUILTIN_CVTPS2PH_MASK,
30118 IX86_BUILTIN_CVTPH2PS_MASK,
30119 IX86_BUILTIN_CVTPH2PS256_MASK,
30120 IX86_BUILTIN_PUNPCKHDQ128_MASK,
30121 IX86_BUILTIN_PUNPCKHDQ256_MASK,
30122 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
30123 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
30124 IX86_BUILTIN_PUNPCKLDQ128_MASK,
30125 IX86_BUILTIN_PUNPCKLDQ256_MASK,
30126 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
30127 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
30128 IX86_BUILTIN_PUNPCKHBW128_MASK,
30129 IX86_BUILTIN_PUNPCKHBW256_MASK,
30130 IX86_BUILTIN_PUNPCKHWD128_MASK,
30131 IX86_BUILTIN_PUNPCKHWD256_MASK,
30132 IX86_BUILTIN_PUNPCKLBW128_MASK,
30133 IX86_BUILTIN_PUNPCKLBW256_MASK,
30134 IX86_BUILTIN_PUNPCKLWD128_MASK,
30135 IX86_BUILTIN_PUNPCKLWD256_MASK,
30136 IX86_BUILTIN_PSLLVV16HI,
30137 IX86_BUILTIN_PSLLVV8HI,
30138 IX86_BUILTIN_PACKSSDW256_MASK,
30139 IX86_BUILTIN_PACKSSDW128_MASK,
30140 IX86_BUILTIN_PACKUSDW256_MASK,
30141 IX86_BUILTIN_PACKUSDW128_MASK,
30142 IX86_BUILTIN_PAVGB256_MASK,
30143 IX86_BUILTIN_PAVGW256_MASK,
30144 IX86_BUILTIN_PAVGB128_MASK,
30145 IX86_BUILTIN_PAVGW128_MASK,
30146 IX86_BUILTIN_VPERMVARSF256_MASK,
30147 IX86_BUILTIN_VPERMVARDF256_MASK,
30148 IX86_BUILTIN_VPERMDF256_MASK,
30149 IX86_BUILTIN_PABSB256_MASK,
30150 IX86_BUILTIN_PABSB128_MASK,
30151 IX86_BUILTIN_PABSW256_MASK,
30152 IX86_BUILTIN_PABSW128_MASK,
30153 IX86_BUILTIN_VPERMILVARPD_MASK,
30154 IX86_BUILTIN_VPERMILVARPS_MASK,
30155 IX86_BUILTIN_VPERMILVARPD256_MASK,
30156 IX86_BUILTIN_VPERMILVARPS256_MASK,
30157 IX86_BUILTIN_VPERMILPD_MASK,
30158 IX86_BUILTIN_VPERMILPS_MASK,
30159 IX86_BUILTIN_VPERMILPD256_MASK,
30160 IX86_BUILTIN_VPERMILPS256_MASK,
30161 IX86_BUILTIN_BLENDMQ256,
30162 IX86_BUILTIN_BLENDMD256,
30163 IX86_BUILTIN_BLENDMPD256,
30164 IX86_BUILTIN_BLENDMPS256,
30165 IX86_BUILTIN_BLENDMQ128,
30166 IX86_BUILTIN_BLENDMD128,
30167 IX86_BUILTIN_BLENDMPD128,
30168 IX86_BUILTIN_BLENDMPS128,
30169 IX86_BUILTIN_BLENDMW256,
30170 IX86_BUILTIN_BLENDMB256,
30171 IX86_BUILTIN_BLENDMW128,
30172 IX86_BUILTIN_BLENDMB128,
30173 IX86_BUILTIN_PMULLD256_MASK,
30174 IX86_BUILTIN_PMULLD128_MASK,
30175 IX86_BUILTIN_PMULUDQ256_MASK,
30176 IX86_BUILTIN_PMULDQ256_MASK,
30177 IX86_BUILTIN_PMULDQ128_MASK,
30178 IX86_BUILTIN_PMULUDQ128_MASK,
30179 IX86_BUILTIN_CVTPD2PS256_MASK,
30180 IX86_BUILTIN_CVTPD2PS_MASK,
30181 IX86_BUILTIN_VPERMVARSI256_MASK,
30182 IX86_BUILTIN_VPERMVARDI256_MASK,
30183 IX86_BUILTIN_VPERMDI256_MASK,
30184 IX86_BUILTIN_CMPQ256,
30185 IX86_BUILTIN_CMPD256,
30186 IX86_BUILTIN_UCMPQ256,
30187 IX86_BUILTIN_UCMPD256,
30188 IX86_BUILTIN_CMPB256,
30189 IX86_BUILTIN_CMPW256,
30190 IX86_BUILTIN_UCMPB256,
30191 IX86_BUILTIN_UCMPW256,
30192 IX86_BUILTIN_CMPPD256_MASK,
30193 IX86_BUILTIN_CMPPS256_MASK,
30194 IX86_BUILTIN_CMPQ128,
30195 IX86_BUILTIN_CMPD128,
30196 IX86_BUILTIN_UCMPQ128,
30197 IX86_BUILTIN_UCMPD128,
30198 IX86_BUILTIN_CMPB128,
30199 IX86_BUILTIN_CMPW128,
30200 IX86_BUILTIN_UCMPB128,
30201 IX86_BUILTIN_UCMPW128,
30202 IX86_BUILTIN_CMPPD128_MASK,
30203 IX86_BUILTIN_CMPPS128_MASK,
30205 IX86_BUILTIN_GATHER3SIV8SF,
30206 IX86_BUILTIN_GATHER3SIV4SF,
30207 IX86_BUILTIN_GATHER3SIV4DF,
30208 IX86_BUILTIN_GATHER3SIV2DF,
30209 IX86_BUILTIN_GATHER3DIV8SF,
30210 IX86_BUILTIN_GATHER3DIV4SF,
30211 IX86_BUILTIN_GATHER3DIV4DF,
30212 IX86_BUILTIN_GATHER3DIV2DF,
30213 IX86_BUILTIN_GATHER3SIV8SI,
30214 IX86_BUILTIN_GATHER3SIV4SI,
30215 IX86_BUILTIN_GATHER3SIV4DI,
30216 IX86_BUILTIN_GATHER3SIV2DI,
30217 IX86_BUILTIN_GATHER3DIV8SI,
30218 IX86_BUILTIN_GATHER3DIV4SI,
30219 IX86_BUILTIN_GATHER3DIV4DI,
30220 IX86_BUILTIN_GATHER3DIV2DI,
30221 IX86_BUILTIN_SCATTERSIV8SF,
30222 IX86_BUILTIN_SCATTERSIV4SF,
30223 IX86_BUILTIN_SCATTERSIV4DF,
30224 IX86_BUILTIN_SCATTERSIV2DF,
30225 IX86_BUILTIN_SCATTERDIV8SF,
30226 IX86_BUILTIN_SCATTERDIV4SF,
30227 IX86_BUILTIN_SCATTERDIV4DF,
30228 IX86_BUILTIN_SCATTERDIV2DF,
30229 IX86_BUILTIN_SCATTERSIV8SI,
30230 IX86_BUILTIN_SCATTERSIV4SI,
30231 IX86_BUILTIN_SCATTERSIV4DI,
30232 IX86_BUILTIN_SCATTERSIV2DI,
30233 IX86_BUILTIN_SCATTERDIV8SI,
30234 IX86_BUILTIN_SCATTERDIV4SI,
30235 IX86_BUILTIN_SCATTERDIV4DI,
30236 IX86_BUILTIN_SCATTERDIV2DI,
30238 /* AVX512DQ. */
30239 IX86_BUILTIN_RANGESD128,
30240 IX86_BUILTIN_RANGESS128,
30241 IX86_BUILTIN_KUNPCKWD,
30242 IX86_BUILTIN_KUNPCKDQ,
30243 IX86_BUILTIN_BROADCASTF32x2_512,
30244 IX86_BUILTIN_BROADCASTI32x2_512,
30245 IX86_BUILTIN_BROADCASTF64X2_512,
30246 IX86_BUILTIN_BROADCASTI64X2_512,
30247 IX86_BUILTIN_BROADCASTF32X8_512,
30248 IX86_BUILTIN_BROADCASTI32X8_512,
30249 IX86_BUILTIN_EXTRACTF64X2_512,
30250 IX86_BUILTIN_EXTRACTF32X8,
30251 IX86_BUILTIN_EXTRACTI64X2_512,
30252 IX86_BUILTIN_EXTRACTI32X8,
30253 IX86_BUILTIN_REDUCEPD512_MASK,
30254 IX86_BUILTIN_REDUCEPS512_MASK,
30255 IX86_BUILTIN_PMULLQ512,
30256 IX86_BUILTIN_XORPD512,
30257 IX86_BUILTIN_XORPS512,
30258 IX86_BUILTIN_ORPD512,
30259 IX86_BUILTIN_ORPS512,
30260 IX86_BUILTIN_ANDPD512,
30261 IX86_BUILTIN_ANDPS512,
30262 IX86_BUILTIN_ANDNPD512,
30263 IX86_BUILTIN_ANDNPS512,
30264 IX86_BUILTIN_INSERTF32X8,
30265 IX86_BUILTIN_INSERTI32X8,
30266 IX86_BUILTIN_INSERTF64X2_512,
30267 IX86_BUILTIN_INSERTI64X2_512,
30268 IX86_BUILTIN_FPCLASSPD512,
30269 IX86_BUILTIN_FPCLASSPS512,
30270 IX86_BUILTIN_CVTD2MASK512,
30271 IX86_BUILTIN_CVTQ2MASK512,
30272 IX86_BUILTIN_CVTMASK2D512,
30273 IX86_BUILTIN_CVTMASK2Q512,
30274 IX86_BUILTIN_CVTPD2QQ512,
30275 IX86_BUILTIN_CVTPS2QQ512,
30276 IX86_BUILTIN_CVTPD2UQQ512,
30277 IX86_BUILTIN_CVTPS2UQQ512,
30278 IX86_BUILTIN_CVTQQ2PS512,
30279 IX86_BUILTIN_CVTUQQ2PS512,
30280 IX86_BUILTIN_CVTQQ2PD512,
30281 IX86_BUILTIN_CVTUQQ2PD512,
30282 IX86_BUILTIN_CVTTPS2QQ512,
30283 IX86_BUILTIN_CVTTPS2UQQ512,
30284 IX86_BUILTIN_CVTTPD2QQ512,
30285 IX86_BUILTIN_CVTTPD2UQQ512,
30286 IX86_BUILTIN_RANGEPS512,
30287 IX86_BUILTIN_RANGEPD512,
30289 /* AVX512BW. */
30290 IX86_BUILTIN_PACKUSDW512,
30291 IX86_BUILTIN_PACKSSDW512,
30292 IX86_BUILTIN_LOADDQUHI512_MASK,
30293 IX86_BUILTIN_LOADDQUQI512_MASK,
30294 IX86_BUILTIN_PSLLDQ512,
30295 IX86_BUILTIN_PSRLDQ512,
30296 IX86_BUILTIN_STOREDQUHI512_MASK,
30297 IX86_BUILTIN_STOREDQUQI512_MASK,
30298 IX86_BUILTIN_PALIGNR512,
30299 IX86_BUILTIN_PALIGNR512_MASK,
30300 IX86_BUILTIN_MOVDQUHI512_MASK,
30301 IX86_BUILTIN_MOVDQUQI512_MASK,
30302 IX86_BUILTIN_PSADBW512,
30303 IX86_BUILTIN_DBPSADBW512,
30304 IX86_BUILTIN_PBROADCASTB512,
30305 IX86_BUILTIN_PBROADCASTB512_GPR,
30306 IX86_BUILTIN_PBROADCASTW512,
30307 IX86_BUILTIN_PBROADCASTW512_GPR,
30308 IX86_BUILTIN_PMOVSXBW512_MASK,
30309 IX86_BUILTIN_PMOVZXBW512_MASK,
30310 IX86_BUILTIN_VPERMVARHI512_MASK,
30311 IX86_BUILTIN_VPERMT2VARHI512,
30312 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30313 IX86_BUILTIN_VPERMI2VARHI512,
30314 IX86_BUILTIN_PAVGB512,
30315 IX86_BUILTIN_PAVGW512,
30316 IX86_BUILTIN_PADDB512,
30317 IX86_BUILTIN_PSUBB512,
30318 IX86_BUILTIN_PSUBSB512,
30319 IX86_BUILTIN_PADDSB512,
30320 IX86_BUILTIN_PSUBUSB512,
30321 IX86_BUILTIN_PADDUSB512,
30322 IX86_BUILTIN_PSUBW512,
30323 IX86_BUILTIN_PADDW512,
30324 IX86_BUILTIN_PSUBSW512,
30325 IX86_BUILTIN_PADDSW512,
30326 IX86_BUILTIN_PSUBUSW512,
30327 IX86_BUILTIN_PADDUSW512,
30328 IX86_BUILTIN_PMAXUW512,
30329 IX86_BUILTIN_PMAXSW512,
30330 IX86_BUILTIN_PMINUW512,
30331 IX86_BUILTIN_PMINSW512,
30332 IX86_BUILTIN_PMAXUB512,
30333 IX86_BUILTIN_PMAXSB512,
30334 IX86_BUILTIN_PMINUB512,
30335 IX86_BUILTIN_PMINSB512,
30336 IX86_BUILTIN_PMOVWB512,
30337 IX86_BUILTIN_PMOVSWB512,
30338 IX86_BUILTIN_PMOVUSWB512,
30339 IX86_BUILTIN_PMULHRSW512_MASK,
30340 IX86_BUILTIN_PMULHUW512_MASK,
30341 IX86_BUILTIN_PMULHW512_MASK,
30342 IX86_BUILTIN_PMULLW512_MASK,
30343 IX86_BUILTIN_PSLLWI512_MASK,
30344 IX86_BUILTIN_PSLLW512_MASK,
30345 IX86_BUILTIN_PACKSSWB512,
30346 IX86_BUILTIN_PACKUSWB512,
30347 IX86_BUILTIN_PSRAVV32HI,
30348 IX86_BUILTIN_PMADDUBSW512_MASK,
30349 IX86_BUILTIN_PMADDWD512_MASK,
30350 IX86_BUILTIN_PSRLVV32HI,
30351 IX86_BUILTIN_PUNPCKHBW512,
30352 IX86_BUILTIN_PUNPCKHWD512,
30353 IX86_BUILTIN_PUNPCKLBW512,
30354 IX86_BUILTIN_PUNPCKLWD512,
30355 IX86_BUILTIN_PSHUFB512,
30356 IX86_BUILTIN_PSHUFHW512,
30357 IX86_BUILTIN_PSHUFLW512,
30358 IX86_BUILTIN_PSRAWI512,
30359 IX86_BUILTIN_PSRAW512,
30360 IX86_BUILTIN_PSRLWI512,
30361 IX86_BUILTIN_PSRLW512,
30362 IX86_BUILTIN_CVTB2MASK512,
30363 IX86_BUILTIN_CVTW2MASK512,
30364 IX86_BUILTIN_CVTMASK2B512,
30365 IX86_BUILTIN_CVTMASK2W512,
30366 IX86_BUILTIN_PCMPEQB512_MASK,
30367 IX86_BUILTIN_PCMPEQW512_MASK,
30368 IX86_BUILTIN_PCMPGTB512_MASK,
30369 IX86_BUILTIN_PCMPGTW512_MASK,
30370 IX86_BUILTIN_PTESTMB512,
30371 IX86_BUILTIN_PTESTMW512,
30372 IX86_BUILTIN_PTESTNMB512,
30373 IX86_BUILTIN_PTESTNMW512,
30374 IX86_BUILTIN_PSLLVV32HI,
30375 IX86_BUILTIN_PABSB512,
30376 IX86_BUILTIN_PABSW512,
30377 IX86_BUILTIN_BLENDMW512,
30378 IX86_BUILTIN_BLENDMB512,
30379 IX86_BUILTIN_CMPB512,
30380 IX86_BUILTIN_CMPW512,
30381 IX86_BUILTIN_UCMPB512,
30382 IX86_BUILTIN_UCMPW512,
30384 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30385 where all operands are 32-byte or 64-byte wide respectively. */
30386 IX86_BUILTIN_GATHERALTSIV4DF,
30387 IX86_BUILTIN_GATHERALTDIV8SF,
30388 IX86_BUILTIN_GATHERALTSIV4DI,
30389 IX86_BUILTIN_GATHERALTDIV8SI,
30390 IX86_BUILTIN_GATHER3ALTDIV16SF,
30391 IX86_BUILTIN_GATHER3ALTDIV16SI,
30392 IX86_BUILTIN_GATHER3ALTSIV4DF,
30393 IX86_BUILTIN_GATHER3ALTDIV8SF,
30394 IX86_BUILTIN_GATHER3ALTSIV4DI,
30395 IX86_BUILTIN_GATHER3ALTDIV8SI,
30396 IX86_BUILTIN_GATHER3ALTSIV8DF,
30397 IX86_BUILTIN_GATHER3ALTSIV8DI,
30398 IX86_BUILTIN_GATHER3DIV16SF,
30399 IX86_BUILTIN_GATHER3DIV16SI,
30400 IX86_BUILTIN_GATHER3DIV8DF,
30401 IX86_BUILTIN_GATHER3DIV8DI,
30402 IX86_BUILTIN_GATHER3SIV16SF,
30403 IX86_BUILTIN_GATHER3SIV16SI,
30404 IX86_BUILTIN_GATHER3SIV8DF,
30405 IX86_BUILTIN_GATHER3SIV8DI,
30406 IX86_BUILTIN_SCATTERDIV16SF,
30407 IX86_BUILTIN_SCATTERDIV16SI,
30408 IX86_BUILTIN_SCATTERDIV8DF,
30409 IX86_BUILTIN_SCATTERDIV8DI,
30410 IX86_BUILTIN_SCATTERSIV16SF,
30411 IX86_BUILTIN_SCATTERSIV16SI,
30412 IX86_BUILTIN_SCATTERSIV8DF,
30413 IX86_BUILTIN_SCATTERSIV8DI,
30415 /* AVX512PF */
30416 IX86_BUILTIN_GATHERPFQPD,
30417 IX86_BUILTIN_GATHERPFDPS,
30418 IX86_BUILTIN_GATHERPFDPD,
30419 IX86_BUILTIN_GATHERPFQPS,
30420 IX86_BUILTIN_SCATTERPFDPD,
30421 IX86_BUILTIN_SCATTERPFDPS,
30422 IX86_BUILTIN_SCATTERPFQPD,
30423 IX86_BUILTIN_SCATTERPFQPS,
30425 /* AVX-512ER */
30426 IX86_BUILTIN_EXP2PD_MASK,
30427 IX86_BUILTIN_EXP2PS_MASK,
30428 IX86_BUILTIN_EXP2PS,
30429 IX86_BUILTIN_RCP28PD,
30430 IX86_BUILTIN_RCP28PS,
30431 IX86_BUILTIN_RCP28SD,
30432 IX86_BUILTIN_RCP28SS,
30433 IX86_BUILTIN_RSQRT28PD,
30434 IX86_BUILTIN_RSQRT28PS,
30435 IX86_BUILTIN_RSQRT28SD,
30436 IX86_BUILTIN_RSQRT28SS,
30438 /* AVX-512IFMA */
30439 IX86_BUILTIN_VPMADD52LUQ512,
30440 IX86_BUILTIN_VPMADD52HUQ512,
30441 IX86_BUILTIN_VPMADD52LUQ256,
30442 IX86_BUILTIN_VPMADD52HUQ256,
30443 IX86_BUILTIN_VPMADD52LUQ128,
30444 IX86_BUILTIN_VPMADD52HUQ128,
30445 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30446 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30447 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30448 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30449 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30450 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30452 /* AVX-512VBMI */
30453 IX86_BUILTIN_VPMULTISHIFTQB512,
30454 IX86_BUILTIN_VPMULTISHIFTQB256,
30455 IX86_BUILTIN_VPMULTISHIFTQB128,
30456 IX86_BUILTIN_VPERMVARQI512_MASK,
30457 IX86_BUILTIN_VPERMT2VARQI512,
30458 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30459 IX86_BUILTIN_VPERMI2VARQI512,
30460 IX86_BUILTIN_VPERMVARQI256_MASK,
30461 IX86_BUILTIN_VPERMVARQI128_MASK,
30462 IX86_BUILTIN_VPERMT2VARQI256,
30463 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30464 IX86_BUILTIN_VPERMT2VARQI128,
30465 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30466 IX86_BUILTIN_VPERMI2VARQI256,
30467 IX86_BUILTIN_VPERMI2VARQI128,
30469 /* SHA builtins. */
30470 IX86_BUILTIN_SHA1MSG1,
30471 IX86_BUILTIN_SHA1MSG2,
30472 IX86_BUILTIN_SHA1NEXTE,
30473 IX86_BUILTIN_SHA1RNDS4,
30474 IX86_BUILTIN_SHA256MSG1,
30475 IX86_BUILTIN_SHA256MSG2,
30476 IX86_BUILTIN_SHA256RNDS2,
30478 /* CLWB instructions. */
30479 IX86_BUILTIN_CLWB,
30481 /* PCOMMIT instructions. */
30482 IX86_BUILTIN_PCOMMIT,
30484 /* CLFLUSHOPT instructions. */
30485 IX86_BUILTIN_CLFLUSHOPT,
30487 /* TFmode support builtins. */
30488 IX86_BUILTIN_INFQ,
30489 IX86_BUILTIN_HUGE_VALQ,
30490 IX86_BUILTIN_FABSQ,
30491 IX86_BUILTIN_COPYSIGNQ,
30493 /* Vectorizer support builtins. */
30494 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30495 IX86_BUILTIN_CPYSGNPS,
30496 IX86_BUILTIN_CPYSGNPD,
30497 IX86_BUILTIN_CPYSGNPS256,
30498 IX86_BUILTIN_CPYSGNPS512,
30499 IX86_BUILTIN_CPYSGNPD256,
30500 IX86_BUILTIN_CPYSGNPD512,
30501 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30502 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30505 /* FMA4 instructions. */
30506 IX86_BUILTIN_VFMADDSS,
30507 IX86_BUILTIN_VFMADDSD,
30508 IX86_BUILTIN_VFMADDPS,
30509 IX86_BUILTIN_VFMADDPD,
30510 IX86_BUILTIN_VFMADDPS256,
30511 IX86_BUILTIN_VFMADDPD256,
30512 IX86_BUILTIN_VFMADDSUBPS,
30513 IX86_BUILTIN_VFMADDSUBPD,
30514 IX86_BUILTIN_VFMADDSUBPS256,
30515 IX86_BUILTIN_VFMADDSUBPD256,
30517 /* FMA3 instructions. */
30518 IX86_BUILTIN_VFMADDSS3,
30519 IX86_BUILTIN_VFMADDSD3,
30521 /* XOP instructions. */
30522 IX86_BUILTIN_VPCMOV,
30523 IX86_BUILTIN_VPCMOV_V2DI,
30524 IX86_BUILTIN_VPCMOV_V4SI,
30525 IX86_BUILTIN_VPCMOV_V8HI,
30526 IX86_BUILTIN_VPCMOV_V16QI,
30527 IX86_BUILTIN_VPCMOV_V4SF,
30528 IX86_BUILTIN_VPCMOV_V2DF,
30529 IX86_BUILTIN_VPCMOV256,
30530 IX86_BUILTIN_VPCMOV_V4DI256,
30531 IX86_BUILTIN_VPCMOV_V8SI256,
30532 IX86_BUILTIN_VPCMOV_V16HI256,
30533 IX86_BUILTIN_VPCMOV_V32QI256,
30534 IX86_BUILTIN_VPCMOV_V8SF256,
30535 IX86_BUILTIN_VPCMOV_V4DF256,
30537 IX86_BUILTIN_VPPERM,
30539 IX86_BUILTIN_VPMACSSWW,
30540 IX86_BUILTIN_VPMACSWW,
30541 IX86_BUILTIN_VPMACSSWD,
30542 IX86_BUILTIN_VPMACSWD,
30543 IX86_BUILTIN_VPMACSSDD,
30544 IX86_BUILTIN_VPMACSDD,
30545 IX86_BUILTIN_VPMACSSDQL,
30546 IX86_BUILTIN_VPMACSSDQH,
30547 IX86_BUILTIN_VPMACSDQL,
30548 IX86_BUILTIN_VPMACSDQH,
30549 IX86_BUILTIN_VPMADCSSWD,
30550 IX86_BUILTIN_VPMADCSWD,
30552 IX86_BUILTIN_VPHADDBW,
30553 IX86_BUILTIN_VPHADDBD,
30554 IX86_BUILTIN_VPHADDBQ,
30555 IX86_BUILTIN_VPHADDWD,
30556 IX86_BUILTIN_VPHADDWQ,
30557 IX86_BUILTIN_VPHADDDQ,
30558 IX86_BUILTIN_VPHADDUBW,
30559 IX86_BUILTIN_VPHADDUBD,
30560 IX86_BUILTIN_VPHADDUBQ,
30561 IX86_BUILTIN_VPHADDUWD,
30562 IX86_BUILTIN_VPHADDUWQ,
30563 IX86_BUILTIN_VPHADDUDQ,
30564 IX86_BUILTIN_VPHSUBBW,
30565 IX86_BUILTIN_VPHSUBWD,
30566 IX86_BUILTIN_VPHSUBDQ,
30568 IX86_BUILTIN_VPROTB,
30569 IX86_BUILTIN_VPROTW,
30570 IX86_BUILTIN_VPROTD,
30571 IX86_BUILTIN_VPROTQ,
30572 IX86_BUILTIN_VPROTB_IMM,
30573 IX86_BUILTIN_VPROTW_IMM,
30574 IX86_BUILTIN_VPROTD_IMM,
30575 IX86_BUILTIN_VPROTQ_IMM,
30577 IX86_BUILTIN_VPSHLB,
30578 IX86_BUILTIN_VPSHLW,
30579 IX86_BUILTIN_VPSHLD,
30580 IX86_BUILTIN_VPSHLQ,
30581 IX86_BUILTIN_VPSHAB,
30582 IX86_BUILTIN_VPSHAW,
30583 IX86_BUILTIN_VPSHAD,
30584 IX86_BUILTIN_VPSHAQ,
30586 IX86_BUILTIN_VFRCZSS,
30587 IX86_BUILTIN_VFRCZSD,
30588 IX86_BUILTIN_VFRCZPS,
30589 IX86_BUILTIN_VFRCZPD,
30590 IX86_BUILTIN_VFRCZPS256,
30591 IX86_BUILTIN_VFRCZPD256,
30593 IX86_BUILTIN_VPCOMEQUB,
30594 IX86_BUILTIN_VPCOMNEUB,
30595 IX86_BUILTIN_VPCOMLTUB,
30596 IX86_BUILTIN_VPCOMLEUB,
30597 IX86_BUILTIN_VPCOMGTUB,
30598 IX86_BUILTIN_VPCOMGEUB,
30599 IX86_BUILTIN_VPCOMFALSEUB,
30600 IX86_BUILTIN_VPCOMTRUEUB,
30602 IX86_BUILTIN_VPCOMEQUW,
30603 IX86_BUILTIN_VPCOMNEUW,
30604 IX86_BUILTIN_VPCOMLTUW,
30605 IX86_BUILTIN_VPCOMLEUW,
30606 IX86_BUILTIN_VPCOMGTUW,
30607 IX86_BUILTIN_VPCOMGEUW,
30608 IX86_BUILTIN_VPCOMFALSEUW,
30609 IX86_BUILTIN_VPCOMTRUEUW,
30611 IX86_BUILTIN_VPCOMEQUD,
30612 IX86_BUILTIN_VPCOMNEUD,
30613 IX86_BUILTIN_VPCOMLTUD,
30614 IX86_BUILTIN_VPCOMLEUD,
30615 IX86_BUILTIN_VPCOMGTUD,
30616 IX86_BUILTIN_VPCOMGEUD,
30617 IX86_BUILTIN_VPCOMFALSEUD,
30618 IX86_BUILTIN_VPCOMTRUEUD,
30620 IX86_BUILTIN_VPCOMEQUQ,
30621 IX86_BUILTIN_VPCOMNEUQ,
30622 IX86_BUILTIN_VPCOMLTUQ,
30623 IX86_BUILTIN_VPCOMLEUQ,
30624 IX86_BUILTIN_VPCOMGTUQ,
30625 IX86_BUILTIN_VPCOMGEUQ,
30626 IX86_BUILTIN_VPCOMFALSEUQ,
30627 IX86_BUILTIN_VPCOMTRUEUQ,
30629 IX86_BUILTIN_VPCOMEQB,
30630 IX86_BUILTIN_VPCOMNEB,
30631 IX86_BUILTIN_VPCOMLTB,
30632 IX86_BUILTIN_VPCOMLEB,
30633 IX86_BUILTIN_VPCOMGTB,
30634 IX86_BUILTIN_VPCOMGEB,
30635 IX86_BUILTIN_VPCOMFALSEB,
30636 IX86_BUILTIN_VPCOMTRUEB,
30638 IX86_BUILTIN_VPCOMEQW,
30639 IX86_BUILTIN_VPCOMNEW,
30640 IX86_BUILTIN_VPCOMLTW,
30641 IX86_BUILTIN_VPCOMLEW,
30642 IX86_BUILTIN_VPCOMGTW,
30643 IX86_BUILTIN_VPCOMGEW,
30644 IX86_BUILTIN_VPCOMFALSEW,
30645 IX86_BUILTIN_VPCOMTRUEW,
30647 IX86_BUILTIN_VPCOMEQD,
30648 IX86_BUILTIN_VPCOMNED,
30649 IX86_BUILTIN_VPCOMLTD,
30650 IX86_BUILTIN_VPCOMLED,
30651 IX86_BUILTIN_VPCOMGTD,
30652 IX86_BUILTIN_VPCOMGED,
30653 IX86_BUILTIN_VPCOMFALSED,
30654 IX86_BUILTIN_VPCOMTRUED,
30656 IX86_BUILTIN_VPCOMEQQ,
30657 IX86_BUILTIN_VPCOMNEQ,
30658 IX86_BUILTIN_VPCOMLTQ,
30659 IX86_BUILTIN_VPCOMLEQ,
30660 IX86_BUILTIN_VPCOMGTQ,
30661 IX86_BUILTIN_VPCOMGEQ,
30662 IX86_BUILTIN_VPCOMFALSEQ,
30663 IX86_BUILTIN_VPCOMTRUEQ,
30665 /* LWP instructions. */
30666 IX86_BUILTIN_LLWPCB,
30667 IX86_BUILTIN_SLWPCB,
30668 IX86_BUILTIN_LWPVAL32,
30669 IX86_BUILTIN_LWPVAL64,
30670 IX86_BUILTIN_LWPINS32,
30671 IX86_BUILTIN_LWPINS64,
30673 IX86_BUILTIN_CLZS,
30675 /* RTM */
30676 IX86_BUILTIN_XBEGIN,
30677 IX86_BUILTIN_XEND,
30678 IX86_BUILTIN_XABORT,
30679 IX86_BUILTIN_XTEST,
30681 /* MPX */
30682 IX86_BUILTIN_BNDMK,
30683 IX86_BUILTIN_BNDSTX,
30684 IX86_BUILTIN_BNDLDX,
30685 IX86_BUILTIN_BNDCL,
30686 IX86_BUILTIN_BNDCU,
30687 IX86_BUILTIN_BNDRET,
30688 IX86_BUILTIN_BNDNARROW,
30689 IX86_BUILTIN_BNDINT,
30690 IX86_BUILTIN_SIZEOF,
30691 IX86_BUILTIN_BNDLOWER,
30692 IX86_BUILTIN_BNDUPPER,
30694 /* BMI instructions. */
30695 IX86_BUILTIN_BEXTR32,
30696 IX86_BUILTIN_BEXTR64,
30697 IX86_BUILTIN_CTZS,
30699 /* TBM instructions. */
30700 IX86_BUILTIN_BEXTRI32,
30701 IX86_BUILTIN_BEXTRI64,
30703 /* BMI2 instructions. */
30704 IX86_BUILTIN_BZHI32,
30705 IX86_BUILTIN_BZHI64,
30706 IX86_BUILTIN_PDEP32,
30707 IX86_BUILTIN_PDEP64,
30708 IX86_BUILTIN_PEXT32,
30709 IX86_BUILTIN_PEXT64,
30711 /* ADX instructions. */
30712 IX86_BUILTIN_ADDCARRYX32,
30713 IX86_BUILTIN_ADDCARRYX64,
30715 /* SBB instructions. */
30716 IX86_BUILTIN_SBB32,
30717 IX86_BUILTIN_SBB64,
30719 /* FSGSBASE instructions. */
30720 IX86_BUILTIN_RDFSBASE32,
30721 IX86_BUILTIN_RDFSBASE64,
30722 IX86_BUILTIN_RDGSBASE32,
30723 IX86_BUILTIN_RDGSBASE64,
30724 IX86_BUILTIN_WRFSBASE32,
30725 IX86_BUILTIN_WRFSBASE64,
30726 IX86_BUILTIN_WRGSBASE32,
30727 IX86_BUILTIN_WRGSBASE64,
30729 /* RDRND instructions. */
30730 IX86_BUILTIN_RDRAND16_STEP,
30731 IX86_BUILTIN_RDRAND32_STEP,
30732 IX86_BUILTIN_RDRAND64_STEP,
30734 /* RDSEED instructions. */
30735 IX86_BUILTIN_RDSEED16_STEP,
30736 IX86_BUILTIN_RDSEED32_STEP,
30737 IX86_BUILTIN_RDSEED64_STEP,
30739 /* F16C instructions. */
30740 IX86_BUILTIN_CVTPH2PS,
30741 IX86_BUILTIN_CVTPH2PS256,
30742 IX86_BUILTIN_CVTPS2PH,
30743 IX86_BUILTIN_CVTPS2PH256,
30745 /* MONITORX and MWAITX instrucions. */
30746 IX86_BUILTIN_MONITORX,
30747 IX86_BUILTIN_MWAITX,
30749 /* CFString built-in for darwin */
30750 IX86_BUILTIN_CFSTRING,
30752 /* Builtins to get CPU type and supported features. */
30753 IX86_BUILTIN_CPU_INIT,
30754 IX86_BUILTIN_CPU_IS,
30755 IX86_BUILTIN_CPU_SUPPORTS,
30757 /* Read/write FLAGS register built-ins. */
30758 IX86_BUILTIN_READ_FLAGS,
30759 IX86_BUILTIN_WRITE_FLAGS,
30761 IX86_BUILTIN_MAX
30762 };
30764 /* Table for the ix86 builtin decls. */
30767 /* Table of all of the builtin functions that are possible with different ISA's
30768 but are waiting to be built until a function is declared to use that
30769 ISA. */
30778 };
30782 /* Bits that can still enable any inclusion of a builtin. */
30785 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30786 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30787 function decl in the ix86_builtins array. Returns the function decl or
30788 NULL_TREE, if the builtin was not added.
30790 If the front end has a special hook for builtin functions, delay adding
30791 builtin functions that aren't in the current ISA until the ISA is changed
30792 with function specific optimization. Doing so, can save about 300K for the
30793 default compiler. When the builtin is expanded, check at that time whether
30794 it is valid.
30796 If the front end doesn't have a special hook, record all builtins, even if
30797 it isn't an instruction set in the current ISA in case the user uses
30798 function specific options for a different ISA, so that we don't get scope
30799 errors if a builtin is added in the middle of a function scope. */
30805 {
30809 {
30818 {
30824 }
30825 else
30826 {
30827 /* Just a MASK where set_and_not_built_p == true can potentially
30828 include a builtin. */
30837 }
30838 }
30841 }
30843 /* Like def_builtin, but also marks the function decl "const". */
30848 {
30852 else
30856 }
30858 /* Add any new builtin functions for a given ISA that may not have been
30859 declared. This saves a bit of space compared to adding all of the
30860 declarations to the tree, even if we didn't use them. */
30862 static void
30864 {
30868 /* Bits in ISA value can be removed from potential isa values. */
30876 {
30879 {
30882 /* Don't define the builtin again. */
30888 NULL_TREE);
30895 NULL_TREE);
30898 }
30899 }
30902 }
30904 /* Bits for builtin_description.flag. */
30906 /* Set when we don't support the comparison natively, and should
30907 swap_comparison in order to support it. */
30908 #define BUILTIN_DESC_SWAP_OPERANDS 1
30910 struct builtin_description
30911 {
30918 };
30921 {
30922 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30923 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30924 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30925 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30926 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30927 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30928 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30929 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30932 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30933 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30934 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30935 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30936 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30937 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30938 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30939 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30940 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30941 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30942 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30943 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30944 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30945 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30946 };
30949 {
30950 /* SSE4.2 */
30951 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30952 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30953 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30954 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30955 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30956 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30957 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30958 };
30961 {
30962 /* SSE4.2 */
30963 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30964 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30965 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30966 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30967 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30968 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30969 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30970 };
30972 /* Special builtins with variable number of arguments. */
30974 {
30975 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30976 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30977 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30979 /* 80387 (for use internally for atomic compound assignment). */
30980 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30981 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30982 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30983 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30985 /* MMX */
30986 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30988 /* 3DNow! */
30989 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30991 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30992 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30993 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30994 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30995 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30996 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30997 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30998 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30999 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31001 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
31002 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
31003 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31004 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31005 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31006 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31007 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31008 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31010 /* SSE */
31011 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
31012 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
31013 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
31015 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
31016 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
31017 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
31018 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
31020 /* SSE or 3DNow!A */
31021 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31022 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
31024 /* SSE2 */
31025 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31026 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31027 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31028 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
31029 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31030 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
31031 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
31032 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
31033 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
31034 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
31036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
31037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
31039 /* SSE3 */
31040 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
31042 /* SSE4.1 */
31043 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
31045 /* SSE4A */
31046 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31047 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
31049 /* AVX */
31050 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
31051 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
31053 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
31054 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
31055 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
31056 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
31057 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
31059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
31060 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
31061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
31062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
31063 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
31064 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
31065 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
31067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
31068 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
31069 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
31071 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
31072 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
31073 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
31074 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
31075 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
31076 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
31077 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
31078 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
31080 /* AVX2 */
31081 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
31082 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
31083 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
31084 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
31085 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
31086 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
31087 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
31088 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
31089 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
31091 /* AVX512F */
31092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_UHI },
31093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_UHI },
31094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_UQI },
31095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_UQI },
31096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_UHI },
31097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_UHI },
31098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_UHI },
31099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_UHI },
31100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_UQI },
31101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_UQI },
31102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_UQI },
31103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_UQI },
31104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_UHI },
31105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_UQI },
31106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_UQI },
31107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_UHI },
31108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_UHI },
31109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_UHI },
31110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_UQI },
31111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_UQI },
31112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
31113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
31114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
31115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
31116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_UHI },
31117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_UQI },
31118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_UQI },
31119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_UQI },
31120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_UQI },
31121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_UQI },
31122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_UQI },
31123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_UQI },
31124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_UQI },
31125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_UHI },
31126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_UHI },
31127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_UHI },
31128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_UQI },
31129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_UQI },
31130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_UQI },
31131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_UHI },
31132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_UHI },
31133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_UHI },
31134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_UHI },
31135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_UHI },
31136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_UHI },
31137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_UQI },
31138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_UQI },
31140 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
31141 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
31142 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
31143 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
31144 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
31145 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
31147 /* FSGSBASE */
31148 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31149 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
31150 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31151 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
31152 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
31153 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
31154 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
31155 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
31157 /* RTM */
31158 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31159 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
31160 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
31162 /* AVX512BW */
31163 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_USI },
31164 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_UDI },
31165 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_USI },
31166 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_UDI },
31168 /* AVX512VL */
31169 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_UHI },
31170 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_UQI },
31171 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_USI },
31172 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_UHI },
31173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_UQI },
31174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_UQI },
31175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_UQI },
31176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_UQI },
31177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_UQI },
31178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_UQI },
31179 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_UQI },
31180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_UQI },
31181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_UQI },
31182 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_UQI },
31183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_UQI },
31184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_UQI },
31185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_UQI },
31186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_UQI },
31187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_UQI },
31188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_UQI },
31189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_UQI },
31190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_UQI },
31191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_UQI },
31192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_UQI },
31193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_UQI },
31194 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_UQI },
31195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_UQI },
31196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_UQI },
31197 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_UQI },
31198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_UQI },
31199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_UQI },
31200 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_UQI },
31201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_UQI },
31202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_UQI },
31203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_UQI },
31204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_UQI },
31205 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_UHI },
31206 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_UQI },
31207 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_USI },
31208 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_UHI },
31209 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_UQI },
31210 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_UQI },
31211 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_UQI },
31212 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_UQI },
31213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_UQI },
31214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_UQI },
31215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_UQI },
31216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_UQI },
31217 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_UQI },
31218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_UQI },
31219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_UQI },
31220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_UQI },
31221 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_UQI },
31222 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_UQI },
31223 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_UQI },
31224 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_UQI },
31225 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_UQI },
31226 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_UQI },
31227 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_UQI },
31228 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_UQI },
31229 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_UQI },
31230 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_UQI },
31231 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_UQI },
31232 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_UQI },
31233 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_UQI },
31234 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_UQI },
31235 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_UQI },
31236 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_UQI },
31237 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_UQI },
31238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_UQI },
31239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_UQI },
31240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_UQI },
31241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_UQI },
31242 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_UQI },
31243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_UQI },
31244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_UQI },
31245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_UQI },
31246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_UQI },
31247 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_UQI },
31248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_UQI },
31249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_UQI },
31250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_UQI },
31251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_UQI },
31252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_UQI },
31253 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_UQI },
31254 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_UQI },
31255 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_UQI },
31256 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_UQI },
31257 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_UQI },
31258 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_UQI },
31259 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_UQI },
31260 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_UQI },
31261 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_UQI },
31262 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_UQI },
31264 /* PCOMMIT. */
31265 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
31266 };
31268 /* Builtins with variable number of arguments. */
31270 {
31271 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
31272 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
31273 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
31274 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31275 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31276 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31277 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31279 /* MMX */
31280 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31281 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31282 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31283 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31284 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31285 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31287 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31288 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31289 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31290 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31291 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31292 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31293 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31294 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31296 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31297 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31299 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31300 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31301 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31302 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31304 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31305 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31306 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31307 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31308 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31309 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31311 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31312 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31313 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31314 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31315 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31316 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31318 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31319 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31320 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31322 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31324 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31325 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31326 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31327 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31328 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31329 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31331 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31332 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31333 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31334 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31335 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31336 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31338 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31339 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31340 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31341 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31343 /* 3DNow! */
31344 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31345 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31346 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31347 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31349 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31350 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31351 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31352 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31353 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31354 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31355 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31356 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31357 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31358 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31359 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31360 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31361 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31362 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31363 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31365 /* 3DNow!A */
31366 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31367 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31368 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31369 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31370 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31371 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31373 /* SSE */
31374 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31375 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31376 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31377 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31378 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31379 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31380 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31381 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31382 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31383 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31384 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31385 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31387 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31389 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31390 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31391 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31392 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31393 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31394 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31395 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31396 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31398 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31399 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31400 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31401 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31402 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31403 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31404 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31405 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31406 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31407 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31408 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31409 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31410 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31411 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31412 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31413 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31414 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31415 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31416 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31417 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31419 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31420 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31421 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31422 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31424 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31425 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31426 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31427 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31429 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31431 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31432 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31433 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31434 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31435 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31437 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31438 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31439 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31441 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31443 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31444 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31445 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31447 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31448 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31450 /* SSE MMX or 3Dnow!A */
31451 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31452 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31453 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31455 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31456 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31457 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31458 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31460 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31461 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31463 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31465 /* SSE2 */
31466 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31468 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31470 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31472 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31474 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31477 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31483 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31484 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31485 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31487 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31489 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31491 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31492 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31493 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31494 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31495 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31496 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31497 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31501 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31502 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31504 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31505 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31509 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31512 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31514 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31515 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31517 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31518 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31519 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31522 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31524 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31526 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31527 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31528 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31529 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31531 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31533 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31534 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31535 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31537 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31539 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31540 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31541 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31542 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31543 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31544 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31545 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31546 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31548 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31549 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31550 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31551 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31552 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31553 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31555 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31557 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31558 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31560 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31561 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31562 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31563 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31565 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31566 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31568 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31569 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31570 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31571 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31572 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31573 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31575 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31576 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31577 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31578 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31580 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31581 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31582 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31583 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31584 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31585 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31586 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31587 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31589 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31590 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31591 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31593 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31594 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31596 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31597 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31599 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31601 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31602 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31603 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31604 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31606 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31607 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31608 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31609 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31610 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31611 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31612 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31614 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31615 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31616 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31617 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31618 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31619 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31620 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31622 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31623 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31624 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31625 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31627 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31628 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31629 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31631 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31633 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31635 /* SSE2 MMX */
31636 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31637 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31639 /* SSE3 */
31640 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31641 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31643 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31644 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31645 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31646 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31647 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31648 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31650 /* SSSE3 */
31651 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31652 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31653 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31654 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31655 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31656 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31658 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31659 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31660 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31661 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31662 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31663 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31664 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31665 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31666 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31667 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31668 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31669 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31670 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31671 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31672 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31673 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31674 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31675 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31676 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31677 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31678 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31679 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31680 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31681 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31683 /* SSSE3. */
31684 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31685 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31687 /* SSE4.1 */
31688 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31689 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31690 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31691 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31692 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31693 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31694 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31695 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31696 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31697 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31699 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31700 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31701 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31702 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31703 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31704 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31705 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31706 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31707 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31708 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31709 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31710 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31711 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31713 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31714 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31715 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31716 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31717 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31718 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31719 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31720 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31721 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31722 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31723 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31724 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31726 /* SSE4.1 */
31727 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31728 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31729 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31730 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31732 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31733 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31734 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31735 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31737 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31738 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31740 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31741 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31743 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31744 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31745 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31746 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31748 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31749 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31751 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31752 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31754 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31755 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31756 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31758 /* SSE4.2 */
31759 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31760 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31761 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31762 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31763 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31765 /* SSE4A */
31766 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31767 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31768 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31769 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31771 /* AES */
31772 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31773 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31775 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31776 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31777 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31778 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31780 /* PCLMUL */
31781 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31783 /* AVX */
31784 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31785 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31787 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31788 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31789 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31790 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31791 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31792 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31793 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31794 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31795 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31797 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31798 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31799 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31800 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31801 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31802 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31803 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31804 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31805 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31806 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31807 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31808 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31809 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31814 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31816 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31817 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31818 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31821 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31822 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31825 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31826 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31827 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31828 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31829 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31830 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31831 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31832 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31833 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31834 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31835 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31836 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31837 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31838 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31839 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31840 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31841 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31842 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31843 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31844 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31845 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31846 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31848 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31849 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31851 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31853 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31855 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31856 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31857 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31859 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31861 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31866 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31867 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31868 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31869 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31871 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31872 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31874 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31875 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31877 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31878 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31879 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31880 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31882 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31883 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31885 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31886 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31888 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31889 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31890 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31891 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31893 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31894 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31895 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31896 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31897 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31898 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31900 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31901 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31902 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31903 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31904 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31905 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31906 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31907 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31908 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31909 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31910 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31911 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31912 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31913 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31914 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31916 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31917 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31919 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31920 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31922 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31924 /* AVX2 */
31925 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31926 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31927 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31928 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31929 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31930 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31931 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31932 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31933 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31934 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31935 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31936 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31937 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31938 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31939 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31940 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31941 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31942 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31943 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31944 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31946 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31947 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31948 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31949 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31950 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31951 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31952 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31953 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31954 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31955 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31956 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31957 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31958 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31959 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31960 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31961 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31962 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31963 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31964 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31965 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31966 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31967 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31968 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31969 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31970 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31971 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31972 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31973 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31974 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31975 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31976 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31977 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31978 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31979 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31980 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31981 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31982 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31983 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31984 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31985 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31986 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31987 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31988 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31989 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31990 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31991 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31992 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31993 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31994 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31995 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31996 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31997 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31998 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31999 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
32000 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
32001 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
32002 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32003 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32004 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32005 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
32006 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
32007 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
32008 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
32009 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
32010 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
32011 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
32012 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
32013 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
32014 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
32015 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
32016 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
32017 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
32018 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
32019 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
32020 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
32021 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
32022 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
32023 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32024 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32025 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32026 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32027 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32028 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32029 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32030 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32031 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32032 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32033 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32034 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32035 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32036 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32037 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32038 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32039 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32040 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
32041 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
32042 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
32043 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
32044 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32045 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
32046 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
32047 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
32048 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
32049 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
32050 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
32051 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
32052 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
32053 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
32054 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32055 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
32056 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
32057 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
32058 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
32059 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
32060 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
32061 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32062 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
32063 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32064 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32065 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32066 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32067 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32068 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
32069 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32070 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32072 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
32074 /* BMI */
32075 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32076 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32077 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
32079 /* TBM */
32080 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32081 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32083 /* F16C */
32084 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
32085 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
32086 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
32087 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
32089 /* BMI2 */
32090 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32091 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32092 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32093 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32094 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32095 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32097 /* AVX512F */
32098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
32099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
32100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
32101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
32102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
32103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
32104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_UHI },
32105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_UQI },
32106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_UHI },
32111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_UQI },
32112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_UHI },
32113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_UQI },
32114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_UQI },
32115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_UHI },
32116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_INT_UHI },
32117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_INT_UQI },
32118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI },
32121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI },
32122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI },
32123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
32124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_UQI },
32129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_UQI },
32130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_UQI },
32131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_UQI },
32132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_UHI },
32133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_UQI },
32134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_UHI },
32135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_UQI },
32136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_UHI },
32152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_UHI },
32153 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_UQI },
32154 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_UHI },
32155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_UQI },
32156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_UQI },
32157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_UHI },
32158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_UQI },
32159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_UHI },
32160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_UQI },
32161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_UHI },
32176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_UHI },
32177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_UQI },
32178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_UQI },
32179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_UQI },
32180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_UHI },
32181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_UHI },
32182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_UQI },
32183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_UQI },
32184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_UQI },
32185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_UHI },
32186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_UQI },
32187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_UQI },
32188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_UHI },
32189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_UQI },
32190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_UHI },
32191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_UHI },
32192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_UQI },
32193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_UQI },
32194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_UQI },
32195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_UHI },
32196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_UQI },
32197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_UQI },
32198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_UHI },
32199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_UQI },
32200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_UQI },
32201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_UQI },
32203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_UHI },
32215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_UQI },
32217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_UHI },
32221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_UQI },
32223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_UHI },
32227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_UQI },
32229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_UHI },
32235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_UQI },
32236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_UHI },
32237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_UQI },
32238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_UQI },
32253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_UHI },
32254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_UHI },
32255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_UQI },
32256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_UHI },
32257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_UQI },
32258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_INT_UHI },
32259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_INT_UQI },
32260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI },
32261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
32262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI },
32263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
32264 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32265 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32266 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32267 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_UQI },
32269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_UQI },
32272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_UHI },
32273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_UQI },
32275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_UHI },
32276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_UQI },
32277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_UHI },
32278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_UQI },
32281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_UQI },
32282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_UHI },
32283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_UHI },
32284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_UQI },
32287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_UHI },
32289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_UHI },
32291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_UHI },
32292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_UQI },
32293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_UQI },
32295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32299 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32304 /* Mask arithmetic operations */
32305 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32306 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32307 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) UHI_FTYPE_UHI },
32308 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32309 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32310 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32311 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32312 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32313 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32314 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) UHI_FTYPE_UHI },
32316 /* SHA */
32317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32325 /* AVX512VL. */
32326 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_USI_CONVERT },
32327 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_UHI_CONVERT },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32336 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_UHI },
32337 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI },
32338 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI },
32339 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32351 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32352 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32353 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32354 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32355 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32364 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32365 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32366 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32367 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32368 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32369 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32370 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32371 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32372 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_UQI },
32373 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_UQI },
32374 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32375 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_UQI },
32376 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_UQI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_UQI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_UQI },
32379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_UQI },
32380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_UQI },
32381 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_UHI },
32382 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_UQI },
32383 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI },
32384 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI },
32385 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI },
32386 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI },
32387 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI },
32388 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI },
32389 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI },
32390 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI },
32393 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI },
32394 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI },
32395 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI },
32396 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI },
32401 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI },
32402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI },
32403 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI },
32404 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI },
32405 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI },
32406 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI },
32407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_UQI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_UQI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_UQI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_UQI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_UQI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_UQI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_UQI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_UQI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_UQI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_UQI },
32417 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_USI },
32418 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_USI },
32419 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI },
32420 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_UHI },
32421 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_UHI },
32422 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_UHI },
32423 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI },
32424 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_UQI },
32425 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_UQI },
32426 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_UQI },
32427 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32428 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_UQI },
32429 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_UQI },
32430 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_UQI },
32431 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32432 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_UQI },
32433 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_UQI },
32434 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32435 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_UQI },
32436 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_UQI },
32437 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_UQI },
32438 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_UQI },
32439 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_UQI },
32440 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_UHI },
32441 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_UQI },
32442 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_UQI },
32443 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_UQI },
32444 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_UQI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_UQI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_UQI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_UQI },
32448 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_UQI },
32449 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_UQI },
32450 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_UQI },
32451 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_UQI },
32452 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_UHI },
32453 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_UQI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_UQI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_UQI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_UQI },
32457 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_UQI },
32458 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_UQI },
32459 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_UQI },
32460 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_UQI },
32461 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_UQI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_UQI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_UQI },
32464 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI },
32465 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_UQI },
32466 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_UQI },
32467 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_UQI },
32468 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32469 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32470 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32471 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32472 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32473 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32474 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32475 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32476 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32477 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32479 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32480 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32484 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32485 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32486 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32487 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32488 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32489 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32490 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32491 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32494 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32495 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32496 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32498 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32499 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32500 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32501 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32502 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32503 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32504 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32505 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32506 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32507 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32510 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32511 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32512 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32513 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32514 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32515 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32516 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32517 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32518 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32519 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32520 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32521 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32522 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI },
32523 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_UQI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_UQI },
32525 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI },
32526 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_UQI },
32527 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_UHI },
32528 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_UQI },
32529 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_UHI },
32530 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_UQI },
32531 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_UHI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_UQI },
32533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_UQI },
32534 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_UQI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_UQI },
32536 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_UQI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_UQI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_UQI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_UQI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_UQI },
32541 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_UQI },
32542 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_UQI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_UQI },
32544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_UQI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_UQI },
32546 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_UQI },
32547 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_UQI },
32548 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_UQI },
32549 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_UQI },
32550 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_UQI },
32551 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_UQI },
32552 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_UQI },
32553 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_UQI },
32554 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_UQI },
32555 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_UQI },
32556 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_UQI },
32557 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_UQI },
32558 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_UQI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_UQI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_UQI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_UQI },
32562 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI },
32563 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_UQI },
32564 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI },
32565 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI },
32566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_UQI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_UQI },
32572 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_UQI },
32573 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_UQI },
32574 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_UQI },
32575 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_UQI },
32576 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_UQI },
32577 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_UQI },
32578 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32579 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32580 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32581 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32582 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32583 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32584 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32585 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32586 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32587 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32588 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32589 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32590 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32591 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32592 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32593 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32594 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32595 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32596 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32597 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32598 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32599 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32600 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_UQI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_UQI },
32603 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32606 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_UHI },
32607 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_UHI },
32608 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_UQI },
32610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
32611 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_UQI },
32612 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32613 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_UQI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_UQI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_UQI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_UQI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_UQI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_UQI },
32630 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32631 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32632 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32633 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32634 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32635 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32636 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32637 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32638 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32639 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32640 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32641 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32642 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32643 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32644 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_USI },
32645 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_UHI },
32646 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_USI },
32647 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_UHI },
32648 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_UQI },
32649 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI },
32650 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_UQI },
32651 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_UQI },
32652 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_UQI },
32653 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_UQI },
32654 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_UQI },
32655 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_UQI },
32656 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_UQI },
32657 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_UQI },
32658 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_UQI },
32659 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_UQI },
32660 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32661 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32662 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32665 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32666 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32667 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32668 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32669 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32670 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32671 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32672 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32673 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32674 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32675 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32676 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32677 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32678 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32681 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32682 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32683 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32684 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32685 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32686 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32687 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32688 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32689 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32690 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32691 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32692 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32693 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32694 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32695 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32696 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32697 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32698 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32699 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32700 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32701 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32702 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32703 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32704 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32706 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32708 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_UQI },
32709 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_UQI },
32710 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32711 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32712 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_UHI },
32713 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_UQI },
32714 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_UQI },
32715 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_UQI },
32716 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32717 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI },
32719 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI },
32720 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI },
32721 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI },
32722 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI },
32723 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI },
32724 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI },
32725 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI },
32726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_UQI },
32727 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_UQI },
32728 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI },
32729 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_UQI },
32730 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32731 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32732 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32733 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32736 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_UQI },
32737 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_UQI },
32738 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_UQI },
32739 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_UQI },
32740 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_UQI },
32741 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_UQI },
32742 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_UQI },
32743 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_UQI },
32744 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32745 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32746 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32747 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32748 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32749 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32750 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_UQI },
32751 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_UQI },
32752 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_UQI },
32753 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_UQI },
32754 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_UQI },
32755 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_UQI },
32756 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32757 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32758 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32759 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32760 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32761 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32762 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_UQI },
32763 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_UQI },
32764 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_UQI },
32765 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_UQI },
32766 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_UQI },
32767 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_UQI },
32768 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32769 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32770 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_UHI },
32771 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_UQI },
32772 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_UHI },
32773 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_UQI },
32774 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32775 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32776 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI },
32777 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_UQI },
32778 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI },
32779 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI },
32780 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32781 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32782 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
32783 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_UQI },
32784 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32785 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32786 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
32787 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_UQI },
32788 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32789 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32790 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32791 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32792 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32793 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32794 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32795 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32796 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32797 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32798 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32799 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32800 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_UHI },
32801 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_UHI },
32802 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_UQI },
32803 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32804 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_UHI },
32805 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_UHI },
32806 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_UQI },
32807 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32808 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32809 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32810 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32811 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32812 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32813 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32814 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32815 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32816 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_UQI },
32817 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI },
32818 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32819 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_UQI },
32820 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI },
32821 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32822 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) UHI_FTYPE_V16QI },
32823 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) USI_FTYPE_V32QI },
32824 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) UQI_FTYPE_V8HI },
32825 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) UHI_FTYPE_V16HI },
32826 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) UQI_FTYPE_V4SI },
32827 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) UQI_FTYPE_V8SI },
32828 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) UQI_FTYPE_V2DI },
32829 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) UQI_FTYPE_V4DI },
32830 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_UHI },
32831 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_USI },
32832 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_UQI },
32833 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_UHI },
32834 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_UQI },
32835 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_UQI },
32836 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_UQI },
32837 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_UQI },
32838 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI },
32839 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI },
32840 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_UQI },
32841 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_UHI },
32842 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_UQI },
32843 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_UQI },
32844 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_UQI },
32845 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_UQI },
32846 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI },
32847 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI },
32848 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_UQI },
32849 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_UHI },
32850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_UQI },
32851 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_UQI },
32852 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_UQI },
32853 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_UQI },
32854 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI },
32855 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI },
32856 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_UQI },
32857 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_UHI },
32858 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_UQI },
32859 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_UQI },
32860 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_UQI },
32861 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_UQI },
32862 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI },
32863 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI },
32864 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_UQI },
32865 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_UHI },
32866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_UQI },
32867 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_UQI },
32868 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_UQI },
32869 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_UQI },
32870 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_UQI },
32871 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_UQI },
32872 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_UHI },
32873 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_UHI },
32874 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32875 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32876 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32877 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32878 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32879 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32880 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32881 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32882 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32883 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32884 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32885 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32886 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32887 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32888 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32889 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32890 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32891 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32892 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32893 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32894 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32895 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32896 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32897 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32898 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32899 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32900 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32901 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32902 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32903 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32904 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32905 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32906 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32907 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32908 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32909 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32910 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32911 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32912 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32913 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32914 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32915 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32916 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32917 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32918 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32919 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32920 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32921 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32922 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32923 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32924 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32925 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32926 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32927 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32928 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32929 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32930 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32931 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32932 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32933 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32934 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32935 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32936 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32937 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32938 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32939 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32941 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32942 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32943 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32944 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32945 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32946 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_UQI },
32947 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_UQI },
32948 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_UQI },
32949 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_UQI },
32950 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_UQI },
32951 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_UQI },
32952 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_UQI },
32953 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_UQI },
32954 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32955 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32956 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32957 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32958 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32959 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32960 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32961 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32962 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32963 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32964 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32965 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32966 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32967 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32968 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32969 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32970 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32971 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32972 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_UHI },
32973 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_UQI },
32974 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_UHI },
32975 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_UQI },
32976 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32977 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32978 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32979 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32980 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_UQI },
32981 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_UQI },
32982 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI },
32983 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI },
32984 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI },
32985 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_UHI },
32986 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI },
32987 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_UQI },
32988 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_UQI },
32989 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_UQI },
32990 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_UQI },
32991 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_UQI },
32992 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_UQI },
32993 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI },
32994 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_UQI },
32995 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32996 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32997 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32998 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32999 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
33000 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
33001 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
33002 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
33003 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_UHI },
33004 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI },
33005 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI },
33006 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI },
33007 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
33008 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
33009 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_UQI },
33010 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_UQI },
33011 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_UQI },
33012 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_UQI },
33013 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_UQI },
33014 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_UQI },
33015 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
33016 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
33017 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
33018 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_INT_UQI },
33019 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_INT_UQI },
33020 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_INT_UQI },
33021 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_INT_UQI },
33022 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_INT_USI },
33023 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_INT_UHI },
33024 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_INT_USI },
33025 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_INT_UHI },
33026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_UQI },
33027 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_UQI },
33028 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_INT_UQI },
33029 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_INT_UQI },
33030 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_INT_UQI },
33031 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_INT_UQI },
33032 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_INT_UHI },
33033 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_INT_UQI },
33034 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_INT_UHI },
33035 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_INT_UQI },
33036 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) UQI_FTYPE_V2DF_V2DF_INT_UQI },
33037 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) UQI_FTYPE_V4SF_V4SF_INT_UQI },
33039 /* AVX512DQ. */
33040 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_UHI },
33041 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_UHI },
33042 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_UQI },
33043 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_UQI },
33044 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_UHI },
33045 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_UHI },
33046 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_UQI },
33047 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_UQI },
33048 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_UQI },
33049 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_UQI },
33050 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_UQI },
33051 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_UHI },
33052 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
33053 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI },
33054 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
33055 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI },
33056 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
33057 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI },
33058 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
33059 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI},
33060 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
33061 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_UHI },
33062 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_UHI },
33063 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_UQI },
33064 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_UQI },
33065 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_UQI },
33066 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_UHI },
33067 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) UHI_FTYPE_V16SI },
33068 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) UQI_FTYPE_V8DI },
33069 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_UHI },
33070 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_UQI },
33072 /* AVX512BW. */
33073 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) USI_FTYPE_USI_USI },
33074 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) UDI_FTYPE_UDI_UDI },
33075 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_USI },
33076 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
33077 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
33078 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_USI },
33079 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
33080 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_UDI_CONVERT },
33081 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI },
33082 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI },
33083 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
33084 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_USI },
33085 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_UDI },
33086 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_UDI },
33087 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_USI },
33088 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_USI },
33089 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_USI },
33090 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_USI },
33091 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33092 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33093 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33094 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33095 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33096 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33097 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33098 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33099 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33100 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33101 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33102 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33103 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33104 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33105 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33106 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33107 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33108 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33109 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33110 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33111 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33112 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33113 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33114 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33115 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33116 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33117 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_USI },
33118 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_USI },
33119 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_USI },
33120 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33121 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33122 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33123 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33124 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_USI },
33125 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_USI },
33126 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_UDI },
33127 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_UDI },
33128 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33129 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_USI },
33130 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_UHI },
33131 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33132 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33133 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33134 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33135 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33136 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33137 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_USI },
33138 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_USI },
33139 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_USI },
33140 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_USI },
33141 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_USI },
33142 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_USI },
33143 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) UDI_FTYPE_V64QI },
33144 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) USI_FTYPE_V32HI },
33145 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_UDI },
33146 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_USI },
33147 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI },
33148 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_USI },
33149 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI },
33150 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_USI },
33151 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI },
33152 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_USI },
33153 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI },
33154 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_USI },
33155 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33156 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI },
33157 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI },
33158 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI },
33159 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI },
33160 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_INT_UDI },
33161 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_INT_USI },
33162 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_INT_UDI },
33163 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_INT_USI },
33165 /* AVX512IFMA */
33166 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
33167 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
33168 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
33169 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
33170 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
33171 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
33172 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
33173 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
33174 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
33175 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
33176 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
33177 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
33179 /* AVX512VBMI */
33180 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33181 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
33182 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
33183 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33184 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33185 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33186 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33187 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
33188 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
33189 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
33190 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
33191 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
33192 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
33193 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
33194 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
33195 };
33197 /* Builtins with rounding support. */
33199 {
33200 /* AVX512F */
33201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) UQI_FTYPE_V8DF_V8DF_INT_UQI_INT },
33206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) UHI_FTYPE_V16SF_V16SF_INT_UHI_INT },
33207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) UQI_FTYPE_V2DF_V2DF_INT_UQI_INT },
33208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) UQI_FTYPE_V4SF_V4SF_INT_UQI_INT },
33209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
33210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
33211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
33214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
33216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
33218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
33220 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
33221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
33222 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
33223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
33224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33229 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
33230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
33231 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
33232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33281 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33283 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33285 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33287 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33289 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33291 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33293 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33295 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33304 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33305 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33306 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33307 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33308 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33309 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33310 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33311 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33312 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33313 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33314 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33315 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33316 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33317 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33318 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33319 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33321 /* AVX512ER */
33322 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33323 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33324 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33325 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33326 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33327 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33328 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33329 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33330 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33331 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33333 /* AVX512DQ. */
33334 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33335 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33336 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33337 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33338 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33339 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33340 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33341 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33342 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33343 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33344 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33345 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33346 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33347 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33348 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33349 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33350 };
33352 /* Bultins for MPX. */
33354 {
33355 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33356 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33357 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33358 };
33360 /* Const builtins for MPX. */
33362 {
33363 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33364 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33365 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33366 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33367 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33368 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33369 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33370 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33371 };
33373 /* FMA4 and XOP. */
33374 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33375 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33376 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33377 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33378 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33379 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33380 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33381 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33382 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33383 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33384 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33385 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33386 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33387 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33388 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33389 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33390 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33391 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33392 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33393 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33394 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33395 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33396 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33397 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33398 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33399 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33400 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33401 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33402 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33403 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33404 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33405 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33406 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33407 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33408 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33409 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33410 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33411 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33412 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33413 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33414 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33415 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33416 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33417 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33418 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33419 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33420 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33421 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33422 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33423 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33424 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33425 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33428 {
33469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33470 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33551 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33574 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33575 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33576 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33581 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33583 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33584 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33585 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33591 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33592 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33593 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33598 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33600 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33601 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33604 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33605 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33609 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33610 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33613 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33614 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33615 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33616 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33617 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33618 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33619 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33620 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33622 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33623 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33624 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33625 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33627 };
33628 \f
33629 /* TM vector builtins. */
33631 /* Reuse the existing x86-specific `struct builtin_description' cause
33632 we're lazy. Add casts to make them fit. */
33634 {
33635 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33636 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33637 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33638 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33639 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33640 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33641 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33643 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33644 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33645 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33646 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33647 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33648 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33649 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33651 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33652 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33653 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33654 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33655 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33656 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33657 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33659 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33660 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33661 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33662 };
33664 /* TM callbacks. */
33666 /* Return the builtin decl needed to load a vector of TYPE. */
33668 static tree
33670 {
33672 {
33674 {
33681 }
33682 }
33684 }
33686 /* Return the builtin decl needed to store a vector of TYPE. */
33688 static tree
33690 {
33692 {
33694 {
33701 }
33702 }
33704 }
33705 \f
33706 /* Initialize the transactional memory vector load/store builtins. */
33708 static void
33710 {
33714 tree decl;
33721 /* If there are no builtins defined, we must be compiling in a
33722 language without trans-mem support. */
33726 /* Use whatever attributes a normal TM load has. */
33730 /* Use whatever attributes a normal TM store has. */
33734 /* Use whatever attributes a normal TM log has. */
33742 {
33746 {
33754 {
33757 }
33759 {
33762 }
33763 else
33764 {
33767 }
33769 /* The builtin without the prefix for
33770 calling it directly. */
33772 attrs);
33773 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33774 set the TYPE_ATTRIBUTES. */
33778 }
33779 }
33780 }
33782 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33783 in the current target ISA to allow the user to compile particular modules
33784 with different target specific options that differ from the command line
33785 options. */
33786 static void
33788 {
33793 /* Add all special builtins with variable number of operands. */
33797 {
33803 }
33805 /* Add all builtins with variable number of operands. */
33809 {
33815 }
33817 /* Add all builtins with rounding. */
33821 {
33827 }
33829 /* pcmpestr[im] insns. */
33833 {
33836 else
33839 }
33841 /* pcmpistr[im] insns. */
33845 {
33848 else
33851 }
33853 /* comi/ucomi insns. */
33855 {
33858 else
33861 }
33863 /* SSE */
33869 /* SSE or 3DNow!A */
33872 IX86_BUILTIN_MASKMOVQ);
33874 /* SSE2 */
33883 /* SSE3. */
33889 /* AES */
33903 /* PCLMUL */
33907 /* RDRND */
33914 IX86_BUILTIN_RDRAND64_STEP);
33916 /* AVX2 */
33918 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33919 IX86_BUILTIN_GATHERSIV2DF);
33922 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33923 IX86_BUILTIN_GATHERSIV4DF);
33926 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33927 IX86_BUILTIN_GATHERDIV2DF);
33930 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33931 IX86_BUILTIN_GATHERDIV4DF);
33934 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33935 IX86_BUILTIN_GATHERSIV4SF);
33938 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33939 IX86_BUILTIN_GATHERSIV8SF);
33942 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33943 IX86_BUILTIN_GATHERDIV4SF);
33946 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33947 IX86_BUILTIN_GATHERDIV8SF);
33950 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33951 IX86_BUILTIN_GATHERSIV2DI);
33954 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33955 IX86_BUILTIN_GATHERSIV4DI);
33958 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33959 IX86_BUILTIN_GATHERDIV2DI);
33962 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33963 IX86_BUILTIN_GATHERDIV4DI);
33966 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33967 IX86_BUILTIN_GATHERSIV4SI);
33970 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33971 IX86_BUILTIN_GATHERSIV8SI);
33974 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33975 IX86_BUILTIN_GATHERDIV4SI);
33978 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33979 IX86_BUILTIN_GATHERDIV8SI);
33982 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33983 IX86_BUILTIN_GATHERALTSIV4DF);
33986 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33987 IX86_BUILTIN_GATHERALTDIV8SF);
33990 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33991 IX86_BUILTIN_GATHERALTSIV4DI);
33994 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33995 IX86_BUILTIN_GATHERALTDIV8SI);
33997 /* AVX512F */
33999 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
34000 IX86_BUILTIN_GATHER3SIV16SF);
34003 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
34004 IX86_BUILTIN_GATHER3SIV8DF);
34007 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
34008 IX86_BUILTIN_GATHER3DIV16SF);
34011 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
34012 IX86_BUILTIN_GATHER3DIV8DF);
34015 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
34016 IX86_BUILTIN_GATHER3SIV16SI);
34019 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
34020 IX86_BUILTIN_GATHER3SIV8DI);
34023 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
34024 IX86_BUILTIN_GATHER3DIV16SI);
34027 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
34028 IX86_BUILTIN_GATHER3DIV8DI);
34031 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
34032 IX86_BUILTIN_GATHER3ALTSIV8DF);
34035 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
34036 IX86_BUILTIN_GATHER3ALTDIV16SF);
34039 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
34040 IX86_BUILTIN_GATHER3ALTSIV8DI);
34043 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
34044 IX86_BUILTIN_GATHER3ALTDIV16SI);
34047 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
34048 IX86_BUILTIN_SCATTERSIV16SF);
34051 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
34052 IX86_BUILTIN_SCATTERSIV8DF);
34055 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
34056 IX86_BUILTIN_SCATTERDIV16SF);
34059 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
34060 IX86_BUILTIN_SCATTERDIV8DF);
34063 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
34064 IX86_BUILTIN_SCATTERSIV16SI);
34067 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
34068 IX86_BUILTIN_SCATTERSIV8DI);
34071 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
34072 IX86_BUILTIN_SCATTERDIV16SI);
34075 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
34076 IX86_BUILTIN_SCATTERDIV8DI);
34078 /* AVX512VL */
34080 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
34081 IX86_BUILTIN_GATHER3SIV2DF);
34084 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
34085 IX86_BUILTIN_GATHER3SIV4DF);
34088 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
34089 IX86_BUILTIN_GATHER3DIV2DF);
34092 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
34093 IX86_BUILTIN_GATHER3DIV4DF);
34096 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
34097 IX86_BUILTIN_GATHER3SIV4SF);
34100 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
34101 IX86_BUILTIN_GATHER3SIV8SF);
34104 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
34105 IX86_BUILTIN_GATHER3DIV4SF);
34108 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
34109 IX86_BUILTIN_GATHER3DIV8SF);
34112 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
34113 IX86_BUILTIN_GATHER3SIV2DI);
34116 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
34117 IX86_BUILTIN_GATHER3SIV4DI);
34120 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
34121 IX86_BUILTIN_GATHER3DIV2DI);
34124 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
34125 IX86_BUILTIN_GATHER3DIV4DI);
34128 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
34129 IX86_BUILTIN_GATHER3SIV4SI);
34132 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
34133 IX86_BUILTIN_GATHER3SIV8SI);
34136 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
34137 IX86_BUILTIN_GATHER3DIV4SI);
34140 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
34141 IX86_BUILTIN_GATHER3DIV8SI);
34144 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
34145 IX86_BUILTIN_GATHER3ALTSIV4DF);
34148 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
34149 IX86_BUILTIN_GATHER3ALTDIV8SF);
34152 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
34153 IX86_BUILTIN_GATHER3ALTSIV4DI);
34156 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
34157 IX86_BUILTIN_GATHER3ALTDIV8SI);
34160 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
34161 IX86_BUILTIN_SCATTERSIV8SF);
34164 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
34165 IX86_BUILTIN_SCATTERSIV4SF);
34168 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
34169 IX86_BUILTIN_SCATTERSIV4DF);
34172 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
34173 IX86_BUILTIN_SCATTERSIV2DF);
34176 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
34177 IX86_BUILTIN_SCATTERDIV8SF);
34180 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
34181 IX86_BUILTIN_SCATTERDIV4SF);
34184 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
34185 IX86_BUILTIN_SCATTERDIV4DF);
34188 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
34189 IX86_BUILTIN_SCATTERDIV2DF);
34192 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
34193 IX86_BUILTIN_SCATTERSIV8SI);
34196 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
34197 IX86_BUILTIN_SCATTERSIV4SI);
34200 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
34201 IX86_BUILTIN_SCATTERSIV4DI);
34204 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
34205 IX86_BUILTIN_SCATTERSIV2DI);
34208 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
34209 IX86_BUILTIN_SCATTERDIV8SI);
34212 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
34213 IX86_BUILTIN_SCATTERDIV4SI);
34216 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
34217 IX86_BUILTIN_SCATTERDIV4DI);
34220 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
34221 IX86_BUILTIN_SCATTERDIV2DI);
34223 /* AVX512PF */
34225 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34226 IX86_BUILTIN_GATHERPFDPD);
34228 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34229 IX86_BUILTIN_GATHERPFDPS);
34231 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34232 IX86_BUILTIN_GATHERPFQPD);
34234 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34235 IX86_BUILTIN_GATHERPFQPS);
34237 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34238 IX86_BUILTIN_SCATTERPFDPD);
34240 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34241 IX86_BUILTIN_SCATTERPFDPS);
34243 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34244 IX86_BUILTIN_SCATTERPFQPD);
34246 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34247 IX86_BUILTIN_SCATTERPFQPS);
34249 /* SHA */
34265 /* RTM. */
34269 /* MMX access to the vec_init patterns. */
34274 V4HI_FTYPE_HI_HI_HI_HI,
34275 IX86_BUILTIN_VEC_INIT_V4HI);
34278 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
34279 IX86_BUILTIN_VEC_INIT_V8QI);
34281 /* Access to the vec_extract patterns. */
34303 /* Access to the vec_set patterns. */
34324 /* RDSEED */
34333 /* ADCX */
34338 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34339 IX86_BUILTIN_ADDCARRYX64);
34341 /* SBB */
34346 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34347 IX86_BUILTIN_SBB64);
34349 /* Read/write FLAGS. */
34359 /* CLFLUSHOPT. */
34363 /* CLWB. */
34367 /* MONITORX and MWAITX. */
34373 /* Add FMA4 multi-arg argument instructions */
34375 {
34381 }
34382 }
34384 static void
34386 {
34389 tree decl;
34395 {
34402 /* With no leaf and nothrow flags for MPX builtins
34403 abnormal edges may follow its call when setjmp
34404 presents in the function. Since we may have a lot
34405 of MPX builtins calls it causes lots of useless
34406 edges and enormous PHI nodes. To avoid this we mark
34407 MPX builtins as leaf and nothrow. */
34409 {
34411 NULL_TREE);
34413 }
34414 else
34415 {
34418 }
34419 }
34424 {
34432 {
34434 NULL_TREE);
34436 }
34437 else
34438 {
34441 }
34442 }
34443 }
34445 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34446 to return a pointer to VERSION_DECL if the outcome of the expression
34447 formed by PREDICATE_CHAIN is true. This function will be called during
34448 version dispatch to decide which function version to execute. It returns
34449 the basic block at the end, to which more conditions can be added. */
34451 static basic_block
34454 {
34455 gimple return_stmt;
34457 gimple convert_stmt;
34458 gimple call_cond_stmt;
34459 gimple if_else_stmt;
34465 gimple_seq gseq;
34482 {
34490 }
34493 {
34508 else
34509 {
34510 gimple assign_stmt;
34511 /* Use MIN_EXPR to check if any integer is zero?.
34512 and_expr_var = min_expr <cond_var, and_expr_var> */
34520 }
34521 }
34524 integer_zero_node,
34554 }
34556 /* This parses the attribute arguments to target in DECL and determines
34557 the right builtin to use to match the platform specification.
34558 It returns the priority value for this version decl. If PREDICATE_LIST
34559 is not NULL, it stores the list of cpu features that need to be checked
34560 before dispatching this function. */
34562 static unsigned int
34564 {
34565 tree attrs;
34567 tree target_node;
34574 /* Priority of i386 features, greater value is higher priority. This is
34575 used to decide the order in which function dispatch must happen. For
34576 instance, a version specialized for SSE4.2 should be checked for dispatch
34577 before a version for SSE3, as SSE4.2 implies SSE3. */
34578 enum feature_priority
34579 {
34581 P_MMX,
34582 P_SSE,
34583 P_SSE2,
34584 P_SSE3,
34585 P_SSSE3,
34586 P_PROC_SSSE3,
34587 P_SSE4_A,
34588 P_PROC_SSE4_A,
34589 P_SSE4_1,
34590 P_SSE4_2,
34591 P_PROC_SSE4_2,
34592 P_POPCNT,
34593 P_AES,
34594 P_PCLMUL,
34595 P_AVX,
34596 P_PROC_AVX,
34597 P_BMI,
34598 P_PROC_BMI,
34599 P_FMA4,
34600 P_XOP,
34601 P_PROC_XOP,
34602 P_FMA,
34603 P_PROC_FMA,
34604 P_BMI2,
34605 P_AVX2,
34606 P_PROC_AVX2,
34607 P_AVX512F,
34608 P_PROC_AVX512F
34609 };
34613 /* These are the target attribute strings for which a dispatcher is
34614 available, from fold_builtin_cpu. */
34616 static struct _feature_list
34617 {
34620 }
34622 {
34642 };
34645 static unsigned int NUM_FEATURES
34661 /* Return priority zero for default function. */
34665 /* Handle arch= if specified. For priority, set it to be 1 more than
34666 the best instruction set the processor can handle. For instance, if
34667 there is a version for atom and a version for ssse3 (the highest ISA
34668 priority for atom), the atom version must be checked for dispatch
34669 before the ssse3 version. */
34671 {
34681 {
34683 {
34691 else
34692 /* We translate "arch=corei7" and "arch=nehalem" to
34693 "corei7" so that it will be mapped to M_INTEL_COREI7
34694 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34701 else
34708 else
34752 }
34753 }
34758 {
34762 }
34765 {
34767 /* For a C string literal the length includes the trailing NULL. */
34770 predicate_chain);
34771 }
34772 }
34774 /* Process feature name. */
34781 {
34782 /* Do not process "arch=" */
34784 {
34787 }
34789 {
34791 {
34793 {
34798 predicate_chain);
34799 }
34800 /* Find the maximum priority feature. */
34805 }
34806 }
34808 {
34812 }
34814 }
34818 {
34821 attrs_str);
34823 }
34825 {
34828 }
34831 }
34833 /* This compares the priority of target features in function DECL1
34834 and DECL2. It returns positive value if DECL1 is higher priority,
34835 negative value if DECL2 is higher priority and 0 if they are the
34836 same. */
34838 static int
34840 {
34845 }
34847 /* V1 and V2 point to function versions with different priorities
34848 based on the target ISA. This function compares their priorities. */
34850 static int
34852 {
34854 {
34855 tree version_decl;
34856 tree predicate_chain;
34863 }
34865 /* This function generates the dispatch function for
34866 multi-versioned functions. DISPATCH_DECL is the function which will
34867 contain the dispatch logic. FNDECLS are the function choices for
34868 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34869 in DISPATCH_DECL in which the dispatch code is generated. */
34871 static int
34875 {
34876 tree default_decl;
34877 gimple ifunc_cpu_init_stmt;
34878 gimple_seq gseq;
34880 tree ele;
34886 struct _function_version_info
34887 {
34888 tree version_decl;
34889 tree predicate_chain;
34897 /*fndecls_p is actually a vector. */
34900 /* At least one more version other than the default. */
34907 /* The first version in the vector is the default decl. */
34913 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34914 constructors, so explicity call __builtin_cpu_init here. */
34925 {
34929 /* Get attribute string, parse it and find the right predicate decl.
34930 The predicate function could be a lengthy combination of many
34931 features, like arch-type and various isa-variants. */
34942 actual_versions++;
34943 }
34945 /* Sort the versions according to descending order of dispatch priority. The
34946 priority is based on the ISA. This is not a perfect solution. There
34947 could still be ambiguity. If more than one function version is suitable
34948 to execute, which one should be dispatched? In future, allow the user
34949 to specify a dispatch priority next to the version. */
34959 /* dispatch default version at the end. */
34965 }
34967 /* Comparator function to be used in qsort routine to sort attribute
34968 specification strings to "target". */
34970 static int
34972 {
34976 }
34978 /* ARGLIST is the argument to target attribute. This function tokenizes
34979 the comma separated arguments, sorts them and returns a string which
34980 is a unique identifier for the comma separated arguments. It also
34981 replaces non-identifier characters "=,-" with "_". */
34985 {
34986 tree arg;
34995 {
35000 argnum++;
35003 argnum++;
35004 }
35009 {
35015 }
35017 /* Replace "=,-" with "_". */
35030 {
35032 i++;
35034 }
35041 {
35046 }
35051 }
35053 /* This function changes the assembler name for functions that are
35054 versions. If DECL is a function version and has a "target"
35055 attribute, it appends the attribute string to its assembler name. */
35057 static tree
35059 {
35060 tree version_attr;
35068 "Function versions cannot be marked as gnu_inline,"
35077 /* target attribute string cannot be NULL. */
35081 version_string
35092 /* Allow assembler name to be modified if already set. */
35100 }
35102 /* This function returns true if FN1 and FN2 are versions of the same function,
35103 that is, the target strings of the function decls are different. This assumes
35104 that FN1 and FN2 have the same signature. */
35106 static bool
35108 {
35120 /* At least one function decl should have the target attribute specified. */
35124 /* Diagnose missing target attribute if one of the decls is already
35125 multi-versioned. */
35127 {
35129 {
35131 {
35134 }
35137 fn2);
35140 /* Prevent diagnosing of the same error multiple times. */
35145 }
35147 }
35152 /* The sorted target strings must be different for fn1 and fn2
35153 to be versions. */
35156 else
35163 }
35165 static tree
35167 {
35168 /* For function version, add the target suffix to the assembler name. */
35172 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
35174 #endif
35177 }
35179 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
35180 is true, append the full path name of the source file. */
35184 {
35192 /* Get a unique name that can be used globally without any chances
35193 of collision at link time. */
35203 /* Use '.' to concatenate names as it is demangler friendly. */
35206 suffix);
35207 else
35211 }
35213 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35215 /* Make a dispatcher declaration for the multi-versioned function DECL.
35216 Calls to DECL function will be replaced with calls to the dispatcher
35217 by the front-end. Return the decl created. */
35219 static tree
35221 {
35222 tree func_decl;
35242 /* Mark this func as external, the resolver will flip it again if
35243 it gets generated. */
35245 /* This will be of type IFUNCs have to be externally visible. */
35249 }
35251 #endif
35253 /* Returns true if decl is multi-versioned and DECL is the default function,
35254 that is it is not tagged with target specific optimization. */
35256 static bool
35258 {
35267 }
35269 /* Make a dispatcher declaration for the multi-versioned function DECL.
35270 Calls to DECL function will be replaced with calls to the dispatcher
35271 by the front-end. Returns the decl of the dispatcher function. */
35273 static tree
35275 {
35297 /* Find the default version and make it the first node. */
35299 /* Go to the beginning of the chain. */
35304 {
35309 }
35311 /* If there is no default node, just return NULL. */
35315 /* Make default info the first node. */
35317 {
35324 }
35328 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35330 {
35335 /* Right now, the dispatching is done via ifunc. */
35341 dispatcher_version_info
35346 /* Set the dispatcher for all the versions. */
35349 {
35352 }
35353 }
35354 else
35355 #endif
35356 {
35358 "multiversioning needs ifunc which is not supported "
35360 }
35363 }
35365 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35366 it to CHAIN. */
35368 static tree
35370 {
35371 tree attr_name;
35372 tree attr_arg_name;
35373 tree attr_args;
35374 tree attr;
35381 }
35383 /* Make the resolver function decl to dispatch the versions of
35384 a multi-versioned function, DEFAULT_DECL. Create an
35385 empty basic block in the resolver and store the pointer in
35386 EMPTY_BB. Return the decl of the resolver function. */
35388 static tree
35392 {
35397 /* IFUNC's have to be globally visible. So, if the default_decl is
35398 not, then the name of the IFUNC should be made unique. */
35402 /* Append the filename to the resolver function if the versions are
35403 not externally visible. This is because the resolver function has
35404 to be externally visible for the loader to find it. So, appending
35405 the filename will prevent conflicts with a resolver function from
35406 another module which is based on the same version name. */
35409 /* The resolver function should return a (void *). */
35420 /* IFUNC resolvers have to be externally visible. */
35424 /* Resolver is not external, body is generated. */
35434 {
35435 /* In this case, each translation unit with a call to this
35436 versioned function will put out a resolver. Ensure it
35437 is comdat to keep just one copy. */
35440 }
35441 /* Build result decl and add to function_decl. */
35457 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35461 /* Create the alias for dispatch to resolver here. */
35462 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35466 }
35468 /* Generate the dispatching code body to dispatch multi-versioned function
35469 DECL. The target hook is called to process the "target" attributes and
35470 provide the code to dispatch the right function at run-time. NODE points
35471 to the dispatcher decl whose body will be created. */
35473 static tree
35475 {
35476 tree resolver_decl;
35477 basic_block empty_bb;
35478 tree default_ver_decl;
35494 /* The first version in the chain corresponds to the default version. */
35497 /* node is going to be an alias, so remove the finalized bit. */
35511 {
35513 /* Check for virtual functions here again, as by this time it should
35514 have been determined if this function needs a vtable index or
35515 not. This happens for methods in derived classes that override
35516 virtual methods in base classes but are not explicitly marked as
35517 virtual. */
35522 }
35528 }
35529 /* This builds the processor_model struct type defined in
35530 libgcc/config/i386/cpuinfo.c */
35532 static tree
35534 {
35541 /* The first 3 fields are unsigned int. */
35543 {
35549 }
35551 /* The last field is an array of unsigned integers of size one. */
35562 }
35564 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35566 static tree
35568 {
35569 tree new_decl;
35572 VAR_DECL,
35574 type);
35587 }
35589 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35590 into an integer defined in libgcc/config/i386/cpuinfo.c */
35592 static tree
35594 {
35600 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35601 enum processor_features
35602 {
35604 F_MMX,
35605 F_POPCNT,
35606 F_SSE,
35607 F_SSE2,
35608 F_SSE3,
35609 F_SSSE3,
35610 F_SSE4_1,
35611 F_SSE4_2,
35612 F_AVX,
35613 F_AVX2,
35614 F_SSE4_A,
35615 F_FMA4,
35616 F_XOP,
35617 F_FMA,
35618 F_AVX512F,
35619 F_BMI,
35620 F_BMI2,
35621 F_AES,
35622 F_PCLMUL,
35623 F_MAX
35624 };
35626 /* These are the values for vendor types and cpu types and subtypes
35627 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35628 the corresponding start value. */
35629 enum processor_model
35630 {
35632 M_AMD,
35633 M_CPU_TYPE_START,
35634 M_INTEL_BONNELL,
35635 M_INTEL_CORE2,
35636 M_INTEL_COREI7,
35637 M_AMDFAM10H,
35638 M_AMDFAM15H,
35639 M_INTEL_SILVERMONT,
35640 M_INTEL_KNL,
35641 M_AMD_BTVER1,
35642 M_AMD_BTVER2,
35643 M_CPU_SUBTYPE_START,
35644 M_INTEL_COREI7_NEHALEM,
35645 M_INTEL_COREI7_WESTMERE,
35646 M_INTEL_COREI7_SANDYBRIDGE,
35647 M_AMDFAM10H_BARCELONA,
35648 M_AMDFAM10H_SHANGHAI,
35649 M_AMDFAM10H_ISTANBUL,
35650 M_AMDFAM15H_BDVER1,
35651 M_AMDFAM15H_BDVER2,
35652 M_AMDFAM15H_BDVER3,
35653 M_AMDFAM15H_BDVER4,
35654 M_INTEL_COREI7_IVYBRIDGE,
35655 M_INTEL_COREI7_HASWELL,
35656 M_INTEL_COREI7_BROADWELL,
35657 M_INTEL_COREI7_SKYLAKE
35658 };
35660 static struct _arch_names_table
35661 {
35664 }
35666 {
35694 };
35696 static struct _isa_names_table
35697 {
35700 }
35702 {
35723 };
35737 {
35738 /* *args must be a expr that can contain other EXPRS leading to a
35739 STRING_CST. */
35741 {
35744 }
35746 }
35751 {
35752 tree ref;
35753 tree field;
35754 tree final;
35757 unsigned int NUM_ARCH_NAMES
35766 {
35770 }
35775 /* CPU types are stored in the next field. */
35778 {
35781 }
35783 /* CPU subtypes are stored in the next field. */
35785 {
35788 }
35790 /* Get the appropriate field in __cpu_model. */
35794 /* Check the value. */
35798 }
35800 {
35801 tree ref;
35802 tree array_elt;
35803 tree field;
35804 tree final;
35807 unsigned int NUM_ISA_NAMES
35816 {
35820 }
35823 /* Get the last field, which is __cpu_features. */
35827 /* Get the appropriate field: __cpu_model.__cpu_features */
35831 /* Access the 0th element of __cpu_features array. */
35836 /* Return __cpu_model.__cpu_features[0] & field_val */
35840 }
35842 }
35844 static tree
35847 {
35849 {
35854 {
35857 }
35858 }
35860 #ifdef SUBTARGET_FOLD_BUILTIN
35862 #endif
35865 }
35867 /* Make builtins to detect cpu type and features supported. NAME is
35868 the builtin name, CODE is the builtin code, and FTYPE is the function
35869 type of the builtin. */
35871 static void
35874 {
35875 tree decl;
35876 tree type;
35884 }
35886 /* Make builtins to get CPU type and features supported. The created
35887 builtins are :
35889 __builtin_cpu_init (), to detect cpu type and features,
35890 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35891 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35892 */
35894 static void
35896 {
35903 }
35905 /* Internal method for ix86_init_builtins. */
35907 static void
35909 {
35921 sysv_va_ref =
35924 fnvoid_va_end_ms =
35926 fnvoid_va_start_ms =
35928 fnvoid_va_end_sysv =
35930 fnvoid_va_start_sysv =
35932 NULL_TREE);
35933 fnvoid_va_copy_ms =
35935 NULL_TREE);
35936 fnvoid_va_copy_sysv =
35952 }
35954 static void
35956 {
35959 /* The __float80 type. */
35962 {
35963 /* The __float80 type. */
35968 }
35971 /* The __float128 type. */
35977 /* This macro is built by i386-builtin-types.awk. */
35978 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35979 }
35981 static void
35983 {
35984 tree t;
35988 /* Builtins to get CPU type and features. */
35991 /* TFmode support builtins. */
35997 /* We will expand them to normal call if SSE isn't available since
35998 they are used by libgcc. */
36018 #ifdef SUBTARGET_INIT_BUILTINS
36019 SUBTARGET_INIT_BUILTINS;
36020 #endif
36021 }
36023 /* Return the ix86 builtin for CODE. */
36025 static tree
36027 {
36032 }
36034 /* Errors in the source file can cause expand_expr to return const0_rtx
36035 where we expect a vector. To avoid crashing, use one of the vector
36036 clear instructions. */
36037 static rtx
36039 {
36043 }
36045 /* Fixup modeless constants to fit required mode. */
36046 static rtx
36048 {
36052 }
36054 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
36056 static rtx
36058 {
36059 rtx pat;
36079 {
36083 }
36097 }
36099 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
36101 static rtx
36105 {
36106 rtx pat;
36114 rtx op;
36115 machine_mode mode;
36121 {
36201 }
36211 {
36218 {
36220 {
36223 {
36241 xop_rotl:
36243 {
36246 gcc_checking_assert
36248 }
36249 else
36250 {
36251 gcc_checking_assert
36262 }
36266 }
36267 }
36268 }
36269 else
36270 {
36271 non_constant:
36275 /* If we aren't optimizing, only allow one memory operand to be
36276 generated. */
36278 num_memory++;
36286 }
36290 }
36293 {
36304 else
36305 {
36311 }
36324 }
36331 }
36333 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36334 insns with vec_merge. */
36336 static rtx
36338 rtx target)
36339 {
36340 rtx pat;
36367 }
36369 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36371 static rtx
36374 {
36375 rtx pat;
36380 rtx op2;
36391 /* Swap operands if we have a comparison that isn't available in
36392 hardware. */
36414 }
36416 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36418 static rtx
36420 rtx target)
36421 {
36422 rtx pat;
36436 /* Swap operands if we have a comparison that isn't available in
36437 hardware. */
36459 const0_rtx)));
36462 }
36464 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36466 static rtx
36468 rtx target)
36469 {
36470 rtx pat;
36495 }
36497 static rtx
36500 {
36501 rtx pat;
36506 rtx op2;
36533 }
36535 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36537 static rtx
36539 rtx target)
36540 {
36541 rtx pat;
36573 const0_rtx)));
36576 }
36578 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36580 static rtx
36583 {
36584 rtx pat;
36622 {
36625 }
36628 {
36637 }
36639 {
36648 }
36649 else
36650 {
36657 }
36665 {
36670 emit_insn
36674 FLAGS_REG),
36675 const0_rtx)));
36677 }
36678 else
36680 }
36683 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36685 static rtx
36688 {
36689 rtx pat;
36717 {
36720 }
36723 {
36732 }
36734 {
36743 }
36744 else
36745 {
36752 }
36760 {
36765 emit_insn
36769 FLAGS_REG),
36770 const0_rtx)));
36772 }
36773 else
36775 }
36777 /* Subroutine of ix86_expand_builtin to take care of insns with
36778 variable number of operands. */
36780 static rtx
36783 {
36789 struct
36790 {
36791 rtx op;
36792 machine_mode mode;
36803 {
37458 }
37463 {
37466 }
37469 {
37476 }
37477 else
37478 {
37481 }
37484 {
37491 {
37492 /* SIMD shift insns take either an 8-bit immediate or
37493 register as count. But builtin functions take int as
37494 count. If count doesn't match, we put it in register. */
37496 {
37500 }
37501 }
37504 {
37507 {
37616 {
37620 {
37623 }
37629 }
37631 }
37632 }
37633 else
37634 {
37638 /* If we aren't optimizing, only allow one memory operand to
37639 be generated. */
37641 num_memory++;
37646 {
37649 }
37650 else
37651 {
37654 }
37655 }
37659 }
37662 {
37687 }
37694 }
37696 /* Transform pattern of following layout:
37697 (parallel [
37698 set (A B)
37699 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37700 ])
37701 into:
37702 (set (A B))
37704 Or:
37705 (parallel [ A B
37706 ...
37707 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37708 ...
37709 ])
37710 into:
37711 (parallel [ A B ... ]) */
37713 static rtx
37715 {
37722 {
37731 }
37732 else
37733 {
37739 {
37744 }
37746 /* No more than 1 occurence was removed. */
37750 }
37751 }
37753 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37754 with rounding. */
37755 static rtx
37758 {
37775 /* See avxintrin.h for values. */
37777 {
37781 };
37783 {
37788 };
37791 {
37794 }
37796 {
37799 }
37802 {
37805 }
37828 ? CODE_FOR_sse_ucomi_round
37835 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37837 {
37843 }
37844 else
37845 {
37848 }
37853 set_dst,
37854 const0_rtx)));
37857 }
37859 static rtx
37862 {
37863 rtx pat;
37865 struct
37866 {
37867 rtx op;
37868 machine_mode mode;
37877 {
37960 }
37970 {
37977 {
37979 {
37981 {
37997 }
37998 }
37999 }
38001 {
38003 {
38006 }
38008 /* If there is no rounding use normal version of the pattern. */
38011 }
38012 else
38013 {
38020 {
38023 }
38024 else
38025 {
38028 }
38029 }
38033 }
38036 {
38061 }
38071 }
38073 /* Subroutine of ix86_expand_builtin to take care of special insns
38074 with variable number of operands. */
38076 static rtx
38079 {
38080 tree arg;
38084 struct
38085 {
38086 rtx op;
38087 machine_mode mode;
38096 {
38132 {
38140 }
38159 /* Reserve memory operand for target. */
38162 {
38163 /* These builtins and instructions require the memory
38164 to be properly aligned. */
38183 }
38212 {
38213 /* These builtins and instructions require the memory
38214 to be properly aligned. */
38231 }
38232 /* FALLTHRU */
38268 /* Reserve memory operand for target. */
38293 {
38294 /* These builtins and instructions require the memory
38295 to be properly aligned. */
38318 }
38331 }
38336 {
38341 {
38344 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38345 on it. Try to improve it using get_pointer_alignment,
38346 and if the special builtin is one that requires strict
38347 mode alignment, also from it's GET_MODE_ALIGNMENT.
38348 Failure to do so could lead to ix86_legitimate_combined_insn
38349 rejecting all changes to such insns. */
38355 }
38356 else
38359 }
38360 else
38361 {
38368 }
38371 {
38380 {
38382 {
38388 else
38391 }
38392 }
38393 else
38394 {
38396 {
38397 /* This must be the memory operand. */
38400 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38401 on it. Try to improve it using get_pointer_alignment,
38402 and if the special builtin is one that requires strict
38403 mode alignment, also from it's GET_MODE_ALIGNMENT.
38404 Failure to do so could lead to ix86_legitimate_combined_insn
38405 rejecting all changes to such insns. */
38411 }
38412 else
38413 {
38414 /* This must be register. */
38422 else
38423 {
38426 }
38427 }
38428 }
38432 }
38435 {
38450 }
38456 }
38458 /* Return the integer constant in ARG. Constrain it to be in the range
38459 of the subparts of VEC_TYPE; issue an error if not. */
38461 static int
38463 {
38468 {
38471 }
38474 }
38476 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38477 ix86_expand_vector_init. We DO have language-level syntax for this, in
38478 the form of (type){ init-list }. Except that since we can't place emms
38479 instructions from inside the compiler, we can't allow the use of MMX
38480 registers unless the user explicitly asks for it. So we do *not* define
38481 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38482 we have builtins invoked by mmintrin.h that gives us license to emit
38483 these sorts of instructions. */
38485 static rtx
38487 {
38497 {
38500 }
38507 }
38509 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38510 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38511 had a language-level syntax for referencing vector elements. */
38513 static rtx
38515 {
38519 rtx op0;
38539 }
38541 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38542 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38543 a language-level syntax for referencing vector elements. */
38545 static rtx
38547 {
38571 /* OP0 is the source of these builtin functions and shouldn't be
38572 modified. Create a copy, use it and return it as target. */
38578 }
38580 /* Emit conditional move of SRC to DST with condition
38581 OP1 CODE OP2. */
38582 static void
38584 {
38585 rtx t;
38588 {
38592 }
38593 else
38594 {
38600 }
38601 }
38603 /* Choose max of DST and SRC and put it to DST. */
38604 static void
38606 {
38608 }
38610 /* Expand an expression EXP that calls a built-in function,
38611 with result going to TARGET if that's convenient
38612 (and in mode MODE if that's convenient).
38613 SUBTARGET may be used as the target for computing one of EXP's operands.
38614 IGNORE is nonzero if the value is to be ignored. */
38616 static rtx
38619 {
38629 /* For CPU builtins that can be folded, fold first and expand the fold. */
38631 {
38633 {
38634 /* Make it call __cpu_indicator_init in libgcc. */
38640 }
38643 {
38648 }
38649 }
38651 /* Determine whether the builtin function is available under the current ISA.
38652 Originally the builtin was not created if it wasn't applicable to the
38653 current ISA based on the command line switches. With function specific
38654 options, we need to check in the context of the function making the call
38655 whether it is supported. */
38658 {
38664 else
38665 {
38669 }
38671 }
38674 {
38692 /* Builtin arg1 is size of block but instruction op1 should
38693 be (size - 1). */
38784 /* If no bounds were specified for returned value,
38785 then use INIT bounds. It usually happens when
38786 some built-in function is expanded. */
38788 {
38797 }
38803 {
38806 /* Return value and lb. */
38808 /* Bounds. */
38810 /* Size. */
38817 /* Size was passed but we need to use (size - 1) as for bndmk. */
38821 /* Add LB to size and inverse to get UB. */
38831 /* We need to move bounds to memory before any computations. */
38834 else
38835 {
38838 }
38840 /* Generate mem expression to be used for access to LB and UB. */
38846 /* Compute LB. */
38851 /* Compute UB. UB is stored in 1's complement form. Therefore
38852 we also use max here. */
38861 }
38864 {
38882 /* Put first bounds to temporaries. */
38886 {
38890 }
38891 else
38892 {
38896 }
38898 /* Put second bounds to temporaries. */
38902 {
38906 }
38907 else
38908 {
38912 }
38914 /* Compute LB. */
38918 /* Compute UB. UB is stored in 1's complement form. Therefore
38919 we also use max here. */
38926 }
38929 {
38930 tree name;
38931 rtx symbol;
38949 }
38952 {
38963 /* We need to move bounds to memory first. */
38966 else
38967 {
38970 }
38972 /* Generate mem expression to access LB and load it. */
38977 }
38980 {
38991 /* We need to move bounds to memory first. */
38994 else
38995 {
38998 }
39000 /* Generate mem expression to access UB. */
39003 /* We need to inverse all bits of UB. */
39010 }
39015 ? CODE_FOR_mmx_maskmovq
39017 /* Note the arg order is different from the operand order. */
39158 {
39159 REAL_VALUE_TYPE inf;
39160 rtx tmp;
39172 }
39182 {
39188 insn = (TARGET_64BIT
39192 }
39194 {
39195 insn = (TARGET_64BIT
39199 }
39200 else
39201 {
39204 insn = (TARGET_64BIT
39212 {
39215 }
39217 }
39220 {
39221 /* mode is VOIDmode if __builtin_rd* has been called
39222 without lhs. */
39226 }
39229 {
39234 }
39247 {
39268 }
39274 {
39277 }
39303 {
39306 }
39312 {
39316 {
39355 }
39360 }
39361 else
39362 {
39364 {
39385 }
39387 }
39417 ? CODE_FOR_tbm_bextri_si
39420 {
39423 }
39424 else
39425 {
39434 }
39450 rdrand_step:
39457 {
39460 }
39466 /* Emit SImode conditional move. */
39468 {
39471 }
39474 else
39482 const0_rtx);
39501 rdseed_step:
39508 {
39511 }
39517 const0_rtx);
39546 handlecarry:
39565 {
39568 }
39570 /* Generate CF from input operand. */
39573 /* Generate instruction that consumes CF. */
39580 /* Return current CF value. */
39587 /* Store the result. */
39626 kortest:
39640 /* Emit kortest. */
39642 /* And use setcc to return result from flags. */
39900 gather_gen:
39901 rtx half;
39914 /* Note the arg order is different from the operand order. */
39925 else
39929 {
39953 else
39960 {
39965 }
39974 else
39981 {
39986 }
39990 }
39992 /* Force memory operand only with base register here. But we
39993 don't want to do it on memory operand for other builtin
39994 functions. */
40007 {
40010 }
40011 else
40012 {
40015 }
40017 {
40020 }
40022 /* Optimize. If mask is known to have all high bits set,
40023 replace op0 with pc_rtx to signal that the instruction
40024 overwrites the whole destination and doesn't use its
40025 previous contents. */
40027 {
40029 {
40032 }
40034 {
40037 {
40041 negative++;
40044 negative++;
40045 }
40048 }
40051 {
40052 /* Recognize also when mask is like:
40053 __v2df src = _mm_setzero_pd ();
40054 __v2df mask = _mm_cmpeq_pd (src, src);
40055 or
40056 __v8sf src = _mm256_setzero_ps ();
40057 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
40058 as that is a cheaper way to load all ones into
40059 a register than having to load a constant from
40060 memory. */
40063 {
40068 {
40075 /* FALLTHRU */
40085 }
40086 }
40087 }
40088 }
40096 {
40122 }
40125 scatter_gen:
40141 /* Force memory operand only with base register here. But we
40142 don't want to do it on memory operand for other builtin
40143 functions. */
40152 {
40155 }
40156 else
40157 {
40160 }
40169 {
40172 }
40181 vec_prefetch_gen:
40201 {
40204 }
40206 {
40209 }
40214 /* Force memory operand only with base register here. But we
40215 don't want to do it on memory operand for other builtin
40216 functions. */
40223 {
40226 }
40229 {
40232 }
40248 {
40251 }
40257 }
40270 {
40274 /* Emit a normal call if SSE isn't available. */
40278 }
40307 }
40309 /* This returns the target-specific builtin with code CODE if
40310 current_function_decl has visibility on this builtin, which is checked
40311 using isa flags. Returns NULL_TREE otherwise. */
40314 {
40318 /* Determine the isa flags of current_function_decl. */
40330 else
40332 }
40334 /* Return function decl for target specific builtin
40335 for given MPX builtin passed i FCODE. */
40336 static tree
40338 {
40340 {
40376 }
40379 }
40381 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40383 Return an address to be used to load/store bounds for pointer
40384 passed in SLOT.
40386 SLOT_NO is an integer constant holding number of a target
40387 dependent special slot to be used in case SLOT is not a memory.
40389 SPECIAL_BASE is a pointer to be used as a base of fake address
40390 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40391 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40393 static rtx
40395 {
40398 /* NULL slot means we pass bounds for pointer not passed to the
40399 function at all. Register slot means we pass pointer in a
40400 register. In both these cases bounds are passed via Bounds
40401 Table. Since we do not have actual pointer stored in memory,
40402 we have to use fake addresses to access Bounds Table. We
40403 start with (special_base - sizeof (void*)) and decrease this
40404 address by pointer size to get addresses for other slots. */
40406 {
40410 }
40411 /* If pointer is passed in a memory then its address is used to
40412 access Bounds Table. */
40414 {
40418 }
40419 else
40423 }
40425 /* Expand pass uses this hook to load bounds for function parameter
40426 PTR passed in SLOT in case its bounds are not passed in a register.
40428 If SLOT is a memory, then bounds are loaded as for regular pointer
40429 loaded from memory. PTR may be NULL in case SLOT is a memory.
40430 In such case value of PTR (if required) may be loaded from SLOT.
40432 If SLOT is NULL or a register then SLOT_NO is an integer constant
40433 holding number of the target dependent special slot which should be
40434 used to obtain bounds.
40436 Return loaded bounds. */
40438 static rtx
40440 {
40442 rtx addr;
40444 /* Get address to be used to access Bounds Table. Special slots start
40445 at the location of return address of the current function. */
40448 /* Load pointer value from a memory if we don't have it. */
40450 {
40453 }
40463 }
40465 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40466 passed in SLOT in case BOUNDS are not passed in a register.
40468 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40469 stored in memory. PTR may be NULL in case SLOT is a memory.
40470 In such case value of PTR (if required) may be loaded from SLOT.
40472 If SLOT is NULL or a register then SLOT_NO is an integer constant
40473 holding number of the target dependent special slot which should be
40474 used to store BOUNDS. */
40476 static void
40478 {
40479 rtx addr;
40481 /* Get address to be used to access Bounds Table. Special slots start
40482 at the location of return address of a called function. */
40485 /* Load pointer value from a memory if we don't have it. */
40487 {
40490 }
40502 }
40504 /* Load and return bounds returned by function in SLOT. */
40506 static rtx
40508 {
40509 rtx res;
40516 }
40518 /* Store BOUNDS returned by function into SLOT. */
40520 static void
40522 {
40525 }
40527 /* Returns a function decl for a vectorized version of the builtin function
40528 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40529 if it is not available. */
40531 static tree
40533 tree type_in)
40534 {
40550 {
40553 {
40560 }
40565 {
40568 }
40573 {
40580 }
40586 /* The round insn does not trap on denormals. */
40591 {
40598 }
40604 /* The round insn does not trap on denormals. */
40609 {
40614 }
40620 /* The round insn does not trap on denormals. */
40625 {
40632 }
40638 /* The round insn does not trap on denormals. */
40643 {
40648 }
40655 {
40660 }
40667 {
40672 }
40678 /* The round insn does not trap on denormals. */
40683 {
40690 }
40696 /* The round insn does not trap on denormals. */
40701 {
40706 }
40711 {
40718 }
40723 {
40730 }
40734 /* The round insn does not trap on denormals. */
40739 {
40744 }
40748 /* The round insn does not trap on denormals. */
40753 {
40758 }
40762 /* The round insn does not trap on denormals. */
40767 {
40772 }
40776 /* The round insn does not trap on denormals. */
40781 {
40786 }
40790 /* The round insn does not trap on denormals. */
40795 {
40800 }
40804 /* The round insn does not trap on denormals. */
40809 {
40814 }
40818 /* The round insn does not trap on denormals. */
40823 {
40828 }
40832 /* The round insn does not trap on denormals. */
40837 {
40842 }
40846 /* The round insn does not trap on denormals. */
40851 {
40856 }
40860 /* The round insn does not trap on denormals. */
40865 {
40870 }
40875 {
40880 }
40885 {
40890 }
40895 }
40897 /* Dispatch to a handler for a vectorization library. */
40900 type_in);
40903 }
40905 /* Handler for an SVML-style interface to
40906 a library with vectorized intrinsics. */
40908 static tree
40910 {
40918 /* The SVML is suitable for unsafe math only. */
40931 {
40978 }
40987 {
40990 }
40991 else
40994 /* Convert to uppercase. */
40999 args;
41001 arity++;
41005 else
41008 /* Build a function declaration for the vectorized function. */
41017 }
41019 /* Handler for an ACML-style interface to
41020 a library with vectorized intrinsics. */
41022 static tree
41024 {
41032 /* The ACML is 64bits only and suitable for unsafe math only as
41033 it does not correctly support parts of IEEE with the required
41034 precision such as denormals. */
41048 {
41078 }
41085 args;
41087 arity++;
41091 else
41094 /* Build a function declaration for the vectorized function. */
41103 }
41105 /* Returns a decl of a function that implements gather load with
41106 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
41107 Return NULL_TREE if it is not available. */
41109 static tree
41112 {
41128 /* v*gather* insn sign extends index to pointer mode. */
41140 {
41144 else
41150 else
41156 else
41162 else
41168 else
41174 else
41180 else
41186 else
41192 else
41198 else
41204 else
41210 else
41215 }
41218 }
41220 /* Returns a code for a target-specific builtin that implements
41221 reciprocal of the function, or NULL_TREE if not available. */
41223 static tree
41225 {
41232 /* Machine dependent builtins. */
41234 {
41235 /* Vectorized version of sqrt to rsqrt conversion. */
41244 }
41245 else
41246 /* Normal builtins. */
41248 {
41249 /* Sqrt to rsqrt conversion. */
41255 }
41256 }
41257 \f
41258 /* Helper for avx_vpermilps256_operand et al. This is also used by
41259 the expansion functions to turn the parallel back into a mask.
41260 The return value is 0 for no match and the imm8+1 for a match. */
41262 int
41264 {
41272 /* Validate that all of the elements are constants, and not totally
41273 out of range. Copy the data into an integral array to make the
41274 subsequent checks easier. */
41276 {
41286 }
41289 {
41291 /* In the 512-bit DFmode case, we can only move elements within
41292 a 128-bit lane. First fill the second part of the mask,
41293 then fallthru. */
41295 {
41299 }
41301 {
41305 }
41306 /* FALLTHRU */
41309 /* In the 256-bit DFmode case, we can only move elements within
41310 a 128-bit lane. */
41312 {
41316 }
41318 {
41322 }
41326 /* In 512 bit SFmode case, permutation in the upper 256 bits
41327 must mirror the permutation in the lower 256-bits. */
41331 /* FALLTHRU */
41334 /* In 256 bit SFmode case, we have full freedom of
41335 movement within the low 128-bit lane, but the high 128-bit
41336 lane must mirror the exact same pattern. */
41341 /* FALLTHRU */
41345 /* In the 128-bit case, we've full freedom in the placement of
41346 the elements from the source operand. */
41353 }
41355 /* Make sure success has a non-zero value by adding one. */
41357 }
41359 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41360 the expansion functions to turn the parallel back into a mask.
41361 The return value is 0 for no match and the imm8+1 for a match. */
41363 int
41365 {
41373 /* Validate that all of the elements are constants, and not totally
41374 out of range. Copy the data into an integral array to make the
41375 subsequent checks easier. */
41377 {
41387 }
41389 /* Validate that the halves of the permute are halves. */
41397 /* Reconstruct the mask. */
41399 {
41405 }
41407 /* Make sure success has a non-zero value by adding one. */
41409 }
41410 \f
41411 /* Return a register priority for hard reg REGNO. */
41412 static int
41414 {
41415 /* ebp and r13 as the base always wants a displacement, r12 as the
41416 base always wants an index. So discourage their usage in an
41417 address. */
41422 /* New x86-64 int registers result in bigger code size. Discourage
41423 them. */
41426 /* New x86-64 SSE registers result in bigger code size. Discourage
41427 them. */
41430 /* Usage of AX register results in smaller code. Prefer it. */
41434 }
41436 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41438 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41439 QImode must go into class Q_REGS.
41440 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41441 movdf to do mem-to-mem moves through integer regs. */
41443 static reg_class_t
41445 {
41448 /* We're only allowed to return a subclass of CLASS. Many of the
41449 following checks fail for NO_REGS, so eliminate that early. */
41453 /* All classes can load zeros. */
41457 /* Force constants into memory if we are loading a (nonzero) constant into
41458 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41459 instructions to load from a constant. */
41466 /* Prefer SSE regs only, if we can use them for math. */
41470 /* Floating-point constants need more complex checks. */
41472 {
41473 /* General regs can load everything. */
41477 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41478 zero above. We only want to wind up preferring 80387 registers if
41479 we plan on doing computation with them. */
41482 {
41483 /* Limit class to non-sse. */
41492 }
41495 }
41497 /* Generally when we see PLUS here, it's the function invariant
41498 (plus soft-fp const_int). Which can only be computed into general
41499 regs. */
41503 /* QImode constants are easy to load, but non-constant QImode data
41504 must go into Q_REGS. */
41506 {
41512 }
41515 }
41517 /* Discourage putting floating-point values in SSE registers unless
41518 SSE math is being used, and likewise for the 387 registers. */
41519 static reg_class_t
41521 {
41524 /* Restrict the output reload class to the register bank that we are doing
41525 math on. If we would like not to return a subset of CLASS, reject this
41526 alternative: if reload cannot do this, it will still use its choice. */
41532 {
41537 else
41539 }
41542 }
41544 static reg_class_t
41547 {
41548 /* Double-word spills from general registers to non-offsettable memory
41549 references (zero-extended addresses) require special handling. */
41555 {
41557 ? CODE_FOR_reload_noff_load
41559 /* Add the cost of moving address to a temporary. */
41563 }
41565 /* QImode spills from non-QI registers require
41566 intermediate register on 32bit targets. */
41572 {
41577 else
41583 /* Return Q_REGS if the operand is in memory. */
41586 }
41588 /* This condition handles corner case where an expression involving
41589 pointers gets vectorized. We're trying to use the address of a
41590 stack slot as a vector initializer.
41592 (set (reg:V2DI 74 [ vect_cst_.2 ])
41593 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41595 Eventually frame gets turned into sp+offset like this:
41597 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41598 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41599 (const_int 392 [0x188]))))
41601 That later gets turned into:
41603 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41604 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41605 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41607 We'll have the following reload recorded:
41609 Reload 0: reload_in (DI) =
41610 (plus:DI (reg/f:DI 7 sp)
41611 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41612 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41613 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41614 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41615 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41616 reload_reg_rtx: (reg:V2DI 22 xmm1)
41618 Which isn't going to work since SSE instructions can't handle scalar
41619 additions. Returning GENERAL_REGS forces the addition into integer
41620 register and reload can handle subsequent reloads without problems. */
41628 }
41630 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41632 static bool
41634 {
41636 {
41652 }
41655 }
41657 /* If we are copying between general and FP registers, we need a memory
41658 location. The same is true for SSE and MMX registers.
41660 To optimize register_move_cost performance, allow inline variant.
41662 The macro can't work reliably when one of the CLASSES is class containing
41663 registers from multiple units (SSE, MMX, integer). We avoid this by never
41664 combining those units in single alternative in the machine description.
41665 Ensure that this constraint holds to avoid unexpected surprises.
41667 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41668 enforce these sanity checks. */
41673 {
41682 {
41685 }
41690 /* Between mask and general, we have moves no larger than word size. */
41695 /* ??? This is a lie. We do have moves between mmx/general, and for
41696 mmx/sse2. But by saying we need secondary memory we discourage the
41697 register allocator from using the mmx registers unless needed. */
41702 {
41703 /* SSE1 doesn't have any direct moves from other classes. */
41707 /* If the target says that inter-unit moves are more expensive
41708 than moving through memory, then don't generate them. */
41713 /* Between SSE and general, we have moves no larger than word size. */
41716 }
41719 }
41721 bool
41724 {
41726 }
41728 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41730 On the 80386, this is the size of MODE in words,
41731 except in the FP regs, where a single reg is always enough. */
41733 static unsigned char
41735 {
41737 {
41742 else
41744 }
41745 else
41746 {
41749 else
41751 }
41752 }
41754 /* Return true if the registers in CLASS cannot represent the change from
41755 modes FROM to TO. */
41757 bool
41760 {
41764 /* x87 registers can't do subreg at all, as all values are reformatted
41765 to extended precision. */
41770 {
41771 /* Vector registers do not support QI or HImode loads. If we don't
41772 disallow a change to these modes, reload will assume it's ok to
41773 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41774 the vec_dupv4hi pattern. */
41777 }
41780 }
41782 /* Return the cost of moving data of mode M between a
41783 register and memory. A value of 2 is the default; this cost is
41784 relative to those in `REGISTER_MOVE_COST'.
41786 This function is used extensively by register_move_cost that is used to
41787 build tables at startup. Make it inline in this case.
41788 When IN is 2, return maximum of in and out move cost.
41790 If moving between registers and memory is more expensive than
41791 between two registers, you should define this macro to express the
41792 relative cost.
41794 Model also increased moving costs of QImode registers in non
41795 Q_REGS classes.
41796 */
41800 {
41803 {
41806 {
41818 }
41822 }
41824 {
41827 {
41839 }
41843 }
41845 {
41848 {
41857 }
41861 }
41863 {
41866 {
41872 else
41877 }
41878 else
41879 {
41884 else
41886 }
41893 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41900 else
41904 }
41905 }
41907 static int
41910 {
41912 }
41915 /* Return the cost of moving data from a register in class CLASS1 to
41916 one in class CLASS2.
41918 It is not required that the cost always equal 2 when FROM is the same as TO;
41919 on some machines it is expensive to move between registers if they are not
41920 general registers. */
41922 static int
41924 reg_class_t class2_i)
41925 {
41929 /* In case we require secondary memory, compute cost of the store followed
41930 by load. In order to avoid bad register allocation choices, we need
41931 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41934 {
41940 /* In case of copying from general_purpose_register we may emit multiple
41941 stores followed by single load causing memory size mismatch stall.
41942 Count this as arbitrarily high cost of 20. */
41947 /* In the case of FP/MMX moves, the registers actually overlap, and we
41948 have to switch modes in order to treat them differently. */
41954 }
41956 /* Moves between SSE/MMX and integer unit are expensive. */
41960 /* ??? By keeping returned value relatively high, we limit the number
41961 of moves between integer and MMX/SSE registers for all targets.
41962 Additionally, high value prevents problem with x86_modes_tieable_p(),
41963 where integer modes in MMX/SSE registers are not tieable
41964 because of missing QImode and HImode moves to, from or between
41965 MMX/SSE registers. */
41975 }
41977 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41978 MODE. */
41980 bool
41982 {
41983 /* Flags and only flags can only hold CCmode values. */
41994 || (TARGET_AVX512BW
41999 {
42000 /* We implement the move patterns for all vector modes into and
42001 out of SSE registers, even when no operation instructions
42002 are available. */
42004 /* For AVX-512 we allow, regardless of regno:
42005 - XI mode
42006 - any of 512-bit wide vector mode
42007 - any scalar mode. */
42014 /* TODO check for QI/HI scalars. */
42015 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
42023 /* xmm16-xmm31 are only available for AVX-512. */
42027 /* OImode and AVX modes are available only when AVX is enabled. */
42034 }
42036 {
42037 /* We implement the move patterns for 3DNOW modes even in MMX mode,
42038 so if the register is available at all, then we can move data of
42039 the given mode into or out of it. */
42042 }
42045 {
42046 /* Take care for QImode values - they can be in non-QI regs,
42047 but then they do cause partial register stalls. */
42052 /* LRA checks if the hard register is OK for the given mode.
42053 QImode values can live in non-QI regs, so we allow all
42054 registers here. */
42058 }
42059 /* We handle both integer and floats in the general purpose registers. */
42066 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
42067 on to use that value in smaller contexts, this can easily force a
42068 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
42069 supporting DImode, allow it. */
42074 }
42076 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
42077 tieable integer mode. */
42079 static bool
42081 {
42083 {
42096 }
42097 }
42099 /* Return true if MODE1 is accessible in a register that can hold MODE2
42100 without copying. That is, all register classes that can hold MODE2
42101 can also hold MODE1. */
42103 bool
42105 {
42113 /* MODE2 being XFmode implies fp stack or general regs, which means we
42114 can tie any smaller floating point modes to it. Note that we do not
42115 tie this with TFmode. */
42119 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
42120 that we can tie it with SFmode. */
42124 /* If MODE2 is only appropriate for an SSE register, then tie with
42125 any other mode acceptable to SSE registers. */
42135 /* If MODE2 is appropriate for an MMX register, then tie
42136 with any other mode acceptable to MMX registers. */
42143 }
42145 /* Return the cost of moving between two registers of mode MODE. */
42147 static int
42149 {
42153 {
42185 }
42187 /* Return the cost of moving between two registers of mode MODE,
42188 assuming that the move will be in pieces of at most UNITS bytes. */
42190 }
42192 /* Compute a (partial) cost for rtx X. Return true if the complete
42193 cost has been computed, and false if subexpressions should be
42194 scanned. In either case, *TOTAL contains the cost result. */
42196 static bool
42199 {
42200 rtx mask;
42206 {
42210 {
42213 }
42225 && !(TARGET_64BIT
42229 /* Use 0 cost for CONST to improve its propagation. */
42232 else
42242 {
42252 }
42254 {
42257 {
42266 }
42267 }
42268 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42269 it'll probably end up. Add a penalty for size. */
42276 /* The zero extensions is often completely free on x86_64, so make
42277 it as cheap as possible. */
42283 else
42295 {
42298 {
42301 }
42304 {
42307 }
42308 }
42309 /* FALLTHRU */
42316 {
42317 /* ??? Should be SSE vector operation cost. */
42318 /* At least for published AMD latencies, this really is the same
42319 as the latency for a simple fpu operation like fabs. */
42320 /* V*QImode is emulated with 1-11 insns. */
42322 {
42325 {
42326 /* For XOP we use vpshab, which requires a broadcast of the
42327 value to the variable shift insn. For constants this
42328 means a V16Q const in mem; even when we can perform the
42329 shift with one insn set the cost to prefer paddb. */
42331 {
42336 }
42338 }
42342 }
42343 else
42345 }
42347 {
42349 {
42352 else
42354 }
42355 else
42356 {
42359 else
42361 }
42362 }
42363 else
42364 {
42369 {
42370 /* Return the cost after shift-and truncation. */
42373 }
42374 else
42376 }
42380 {
42381 rtx sub;
42386 /* ??? SSE scalar/vector cost should be used here. */
42387 /* ??? Bald assumption that fma has the same cost as fmul. */
42391 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42402 }
42406 {
42407 /* ??? SSE scalar cost should be used here. */
42410 }
42412 {
42415 }
42417 {
42418 /* ??? SSE vector cost should be used here. */
42421 }
42423 {
42424 /* V*QImode is emulated with 7-13 insns. */
42426 {
42433 }
42434 /* V*DImode is emulated with 5-8 insns. */
42436 {
42439 else
42441 }
42442 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42443 insns, including two PMULUDQ. */
42446 else
42449 }
42450 else
42451 {
42456 {
42459 nbits++;
42460 }
42461 else
42462 /* This is arbitrary. */
42465 /* Compute costs correctly for widening multiplication. */
42469 {
42476 {
42480 else
42482 }
42486 }
42494 }
42501 /* ??? SSE cost should be used here. */
42506 /* ??? SSE vector cost should be used here. */
42508 else
42515 {
42520 {
42523 {
42532 }
42533 }
42536 {
42539 {
42546 }
42547 }
42549 {
42558 }
42559 }
42560 /* FALLTHRU */
42564 {
42565 /* ??? SSE cost should be used here. */
42568 }
42570 {
42573 }
42575 {
42576 /* ??? SSE vector cost should be used here. */
42579 }
42580 /* FALLTHRU */
42587 {
42594 }
42595 /* FALLTHRU */
42599 {
42600 /* ??? SSE cost should be used here. */
42603 }
42605 {
42608 }
42610 {
42611 /* ??? SSE vector cost should be used here. */
42614 }
42615 /* FALLTHRU */
42619 {
42620 /* ??? Should be SSE vector operation cost. */
42621 /* At least for published AMD latencies, this really is the same
42622 as the latency for a simple fpu operation like fabs. */
42624 }
42627 else
42636 {
42637 /* This kind of construct is implemented using test[bwl].
42638 Treat it as if we had an AND. */
42645 }
42647 /* The embedded comparison operand is completely free. */
42661 /* ??? SSE cost should be used here. */
42666 /* ??? SSE vector cost should be used here. */
42672 /* ??? SSE cost should be used here. */
42677 /* ??? SSE vector cost should be used here. */
42689 /* ??? Assume all of these vector manipulation patterns are
42690 recognizable. In which case they all pretty much have the
42691 same cost. */
42696 /* This is masked instruction, assume the same cost,
42697 as nonmasked variant. */
42700 else
42706 }
42707 }
42709 #if TARGET_MACHO
42713 /* Given a symbol name and its associated stub, write out the
42714 definition of the stub. */
42716 void
42718 {
42723 /* For 64-bit we shouldn't get here. */
42726 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42743 else
42750 {
42752 }
42754 {
42755 /* PIC stub. */
42756 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42762 }
42763 else
42766 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42767 it needs no stub-binding-helper. */
42774 {
42777 }
42778 else
42783 /* N.B. Keep the correspondence of these
42784 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42785 old-pic/new-pic/non-pic stubs; altering this will break
42786 compatibility with existing dylibs. */
42788 {
42789 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42791 }
42792 else
42793 /* 16-byte -mdynamic-no-pic stub. */
42799 }
42802 /* Order the registers for register allocator. */
42804 void
42806 {
42810 /* First allocate the local general purpose registers. */
42815 /* Global general purpose registers. */
42820 /* x87 registers come first in case we are doing FP math
42821 using them. */
42826 /* SSE registers. */
42832 /* Extended REX SSE registers. */
42836 /* Mask register. */
42840 /* MPX bound registers. */
42844 /* x87 registers. */
42852 /* Initialize the rest of array as we do not allocate some registers
42853 at all. */
42856 }
42858 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42859 in struct attribute_spec handler. */
42860 static tree
42862 tree args,
42865 {
42870 {
42872 name);
42875 }
42877 {
42879 name);
42882 }
42884 {
42885 tree cst;
42889 {
42892 name);
42894 }
42897 {
42900 name);
42902 }
42905 }
42908 }
42910 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42911 struct attribute_spec.handler. */
42912 static tree
42915 {
42920 {
42922 name);
42925 }
42927 /* Can combine regparm with all attributes but fastcall. */
42929 {
42931 {
42933 }
42936 }
42938 {
42940 {
42942 }
42945 }
42948 }
42950 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42951 struct attribute_spec.handler. */
42952 static tree
42955 {
42958 {
42961 }
42962 else
42966 {
42968 name);
42970 }
42976 {
42978 name);
42980 }
42983 }
42985 static tree
42988 {
42990 {
42992 name);
42994 }
42996 }
42998 static bool
43000 {
43004 }
43006 /* Returns an expression indicating where the this parameter is
43007 located on entry to the FUNCTION. */
43009 static rtx
43011 {
43017 {
43022 else
43025 }
43030 {
43037 {
43042 }
43043 else
43044 {
43047 {
43053 }
43054 }
43056 }
43060 }
43062 /* Determine whether x86_output_mi_thunk can succeed. */
43064 static bool
43066 const_tree function)
43067 {
43068 /* 64-bit can handle anything. */
43072 /* For 32-bit, everything's fine if we have one free register. */
43076 /* Need a free register for vcall_offset. */
43080 /* Need a free register for GOT references. */
43084 /* Otherwise ok. */
43086 }
43088 /* Output the assembler code for a thunk function. THUNK_DECL is the
43089 declaration for the thunk function itself, FUNCTION is the decl for
43090 the target function. DELTA is an immediate constant offset to be
43091 added to THIS. If VCALL_OFFSET is nonzero, the word at
43092 *(*this + vcall_offset) should be added to THIS. */
43094 static void
43097 {
43105 else
43106 {
43112 else
43114 }
43118 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
43119 pull it in now and let DELTA benefit. */
43123 {
43124 /* Put the this parameter into %eax. */
43127 }
43128 else
43131 /* Adjust the this parameter by a fixed constant. */
43133 {
43138 {
43140 {
43144 }
43145 }
43148 }
43150 /* Adjust the this parameter by a value stored in the vtable. */
43152 {
43162 /* Adjust the this parameter. */
43166 {
43170 }
43177 vcall_mem));
43178 else
43180 }
43182 /* If necessary, drop THIS back to its stack slot. */
43188 {
43191 ;
43192 else
43193 {
43197 }
43198 }
43199 else
43200 {
43202 ;
43203 #if TARGET_MACHO
43205 {
43208 }
43210 else
43211 {
43219 }
43220 }
43222 /* Our sibling call patterns do not allow memories, because we have no
43223 predicate that can distinguish between frame and non-frame memory.
43224 For our purposes here, we can get away with (ab)using a jump pattern,
43225 because we're going to do no optimization. */
43227 {
43229 {
43235 }
43236 else
43238 }
43239 else
43240 {
43242 {
43243 // CM_LARGE_PIC always uses pseudo PIC register which is
43244 // uninitialized. Since FUNCTION is local and calling it
43245 // doesn't go through PLT, we use scratch register %r11 as
43246 // PIC register and initialize it here.
43251 }
43254 {
43260 }
43266 }
43269 /* Emit just enough of rest_of_compilation to get the insns emitted.
43270 Note that use_thunk calls assemble_start_function et al. */
43276 }
43278 static void
43280 {
43284 #if TARGET_MACHO
43286 #endif
43293 }
43295 int
43297 {
43298 machine_mode mode;
43311 }
43313 /* Print call to TARGET to FILE. */
43315 static void
43317 {
43320 else
43322 }
43324 /* Output assembler code to FILE to increment profiler label # LABELNO
43325 for profiling a function entry. */
43326 void
43328 {
43332 {
43333 #ifndef NO_PROFILE_COUNTERS
43335 #endif
43339 else
43341 }
43343 {
43344 #ifndef NO_PROFILE_COUNTERS
43347 #endif
43349 }
43350 else
43351 {
43352 #ifndef NO_PROFILE_COUNTERS
43355 #endif
43357 }
43360 {
43364 }
43365 }
43367 /* We don't have exact information about the insn sizes, but we may assume
43368 quite safely that we are informed about all 1 byte insns and memory
43369 address sizes. This is enough to eliminate unnecessary padding in
43370 99% of cases. */
43372 static int
43374 {
43380 /* Discard alignments we've emit and jump instructions. */
43385 /* Important case - calls are always 5 bytes.
43386 It is common to have many calls in the row. */
43395 /* For normal instructions we rely on get_attr_length being exact,
43396 with a few exceptions. */
43398 {
43402 {
43412 /* Otherwise trust get_attr_length. */
43414 }
43419 }
43422 else
43424 }
43426 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43428 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43429 window. */
43431 static void
43433 {
43438 /* Look for all minimal intervals of instructions containing 4 jumps.
43439 The intervals are bounded by START and INSN. NBYTES is the total
43440 size of instructions in the interval including INSN and not including
43441 START. When the NBYTES is smaller than 16 bytes, it is possible
43442 that the end of START and INSN ends up in the same 16byte page.
43444 The smallest offset in the page INSN can start is the case where START
43445 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43446 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43448 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43449 have to, control transfer to label(s) can be performed through other
43450 means, and also we estimate minimum length of all asm stmts as 0. */
43452 {
43456 {
43462 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43463 already in the current 16 byte page, because otherwise
43464 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43465 bytes to reach 16 byte boundary. */
43473 {
43475 {
43480 else
43483 }
43484 }
43486 }
43495 njumps++;
43496 else
43500 {
43505 else
43508 }
43515 {
43522 }
43523 }
43524 }
43525 #endif
43527 /* AMD Athlon works faster
43528 when RET is not destination of conditional jump or directly preceded
43529 by other jump instruction. We avoid the penalty by inserting NOP just
43530 before the RET instructions in such cases. */
43531 static void
43533 {
43534 edge e;
43535 edge_iterator ei;
43538 {
43551 {
43552 edge e;
43553 edge_iterator ei;
43558 {
43561 }
43562 }
43564 {
43570 /* Empty functions get branch mispredict even when
43571 the jump destination is not visible to us. */
43574 }
43576 {
43579 }
43580 }
43581 }
43583 /* Count the minimum number of instructions in BB. Return 4 if the
43584 number of instructions >= 4. */
43586 static int
43588 {
43592 /* Count number of instructions in this block. Return 4 if the number
43593 of instructions >= 4. */
43595 {
43596 /* Only happen in exit blocks. */
43604 {
43605 insn_count++;
43608 }
43609 }
43612 }
43615 /* Count the minimum number of instructions in code path in BB.
43616 Return 4 if the number of instructions >= 4. */
43618 static int
43620 {
43621 edge e;
43622 edge_iterator ei;
43625 /* Only bother counting instructions along paths with no
43626 more than 2 basic blocks between entry and exit. Given
43627 that BB has an edge to exit, determine if a predecessor
43628 of BB has an edge from entry. If so, compute the number
43629 of instructions in the predecessor block. If there
43630 happen to be multiple such blocks, compute the minimum. */
43633 {
43634 edge prev_e;
43635 edge_iterator prev_ei;
43638 {
43641 }
43643 {
43645 {
43650 }
43651 }
43652 }
43658 }
43660 /* Pad short function to 4 instructions. */
43662 static void
43664 {
43665 edge e;
43666 edge_iterator ei;
43669 {
43672 {
43675 /* Pad short function. */
43677 {
43680 /* Find epilogue. */
43689 /* Two NOPs count as one instruction. */
43692 }
43693 }
43694 }
43695 }
43697 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43698 the epilogue, the Windows system unwinder will apply epilogue logic and
43699 produce incorrect offsets. This can be avoided by adding a nop between
43700 the last insn that can throw and the first insn of the epilogue. */
43702 static void
43704 {
43705 edge e;
43706 edge_iterator ei;
43709 {
43712 /* Find the beginning of the epilogue. */
43719 /* We only care about preceding insns that can throw. */
43724 /* Do not separate calls from their debug information. */
43730 else
43734 }
43735 }
43737 /* Implement machine specific optimizations. We implement padding of returns
43738 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43739 static void
43741 {
43742 /* We are freeing block_for_insn in the toplev to keep compatibility
43743 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43750 {
43755 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43758 #endif
43759 }
43760 }
43762 /* Return nonzero when QImode register that must be represented via REX prefix
43763 is used. */
43764 bool
43766 {
43774 }
43776 /* Return true when INSN mentions register that must be encoded using REX
43777 prefix. */
43778 bool
43780 {
43783 {
43788 }
43790 }
43792 /* If profitable, negate (without causing overflow) integer constant
43793 of mode MODE at location LOC. Return true in this case. */
43794 bool
43796 {
43797 HOST_WIDE_INT val;
43803 {
43805 /* DImode x86_64 constants must fit in 32 bits. */
43818 }
43820 /* Avoid overflows. */
43826 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43827 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43830 {
43833 }
43836 }
43838 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43839 optabs would emit if we didn't have TFmode patterns. */
43841 void
43843 {
43878 }
43879 \f
43885 /* Get a vector mode of the same size as the original but with elements
43886 twice as wide. This is only guaranteed to apply to integral vectors. */
43890 {
43891 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43896 }
43898 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43899 fill target with val via vec_duplicate. */
43901 static bool
43903 {
43906 rtx dup;
43908 /* First attempt to recognize VAL as-is. */
43912 {
43914 /* If that fails, force VAL into a register. */
43925 }
43927 }
43929 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43930 with all elements equal to VAR. Return true if successful. */
43932 static bool
43935 {
43939 {
43944 /* FALLTHRU */
43964 {
43965 rtx x;
43972 }
43985 {
43989 permute:
43997 /* Extend to SImode using a paradoxical SUBREG. */
44001 /* Insert the SImode value as low element of a V4SImode vector. */
44010 }
44021 widen:
44022 /* Replicate the value once into the next wider mode and recurse. */
44023 {
44025 rtx x;
44042 }
44048 else
44049 {
44058 }
44065 else
44066 {
44075 }
44080 }
44081 }
44083 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44084 whose ONE_VAR element is VAR, and other elements are zero. Return true
44085 if successful. */
44087 static bool
44090 {
44091 machine_mode vsimode;
44092 rtx new_target;
44097 {
44099 /* For SSE4.1, we normally use vector set. But if the second
44100 element is zero and inter-unit moves are OK, we use movq
44101 instead. */
44103 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
44125 /* Use ix86_expand_vector_set in 64bit mode only. */
44130 }
44133 {
44138 }
44141 {
44146 /* FALLTHRU */
44161 else
44168 {
44169 /* We need to shuffle the value to the correct position, so
44170 create a new pseudo to store the intermediate result. */
44172 /* With SSE2, we can use the integer shuffle insns. */
44174 {
44176 const1_rtx,
44183 }
44185 /* Otherwise convert the intermediate result to V4SFmode and
44186 use the SSE1 shuffle instructions. */
44188 {
44191 }
44192 else
44196 const1_rtx,
44205 }
44220 widen:
44224 /* Zero extend the variable element to SImode and recurse. */
44237 }
44238 }
44240 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44241 consisting of the values in VALS. It is known that all elements
44242 except ONE_VAR are constants. Return true if successful. */
44244 static bool
44247 {
44249 machine_mode wmode;
44257 {
44262 /* For the two element vectors, it's just as easy to use
44263 the general case. */
44267 /* Use ix86_expand_vector_set in 64bit mode only. */
44289 widen:
44290 /* There's no way to set one QImode entry easily. Combine
44291 the variable value with its adjacent constant value, and
44292 promote to an HImode set. */
44295 {
44300 }
44301 else
44302 {
44305 }
44319 }
44324 }
44326 /* A subroutine of ix86_expand_vector_init_general. Use vector
44327 concatenate to handle the most general case: all values variable,
44328 and none identical. */
44330 static void
44333 {
44336 rtvec v;
44340 {
44343 {
44388 }
44400 {
44415 }
44420 {
44439 }
44444 {
44457 }
44460 half:
44461 /* FIXME: We process inputs backward to help RA. PR 36222. */
44465 {
44470 }
44474 {
44478 {
44482 }
44485 {
44489 }
44492 }
44494 {
44497 {
44501 }
44504 }
44505 else
44511 }
44512 }
44514 /* A subroutine of ix86_expand_vector_init_general. Use vector
44515 interleave to handle the most general case: all values variable,
44516 and none identical. */
44518 static void
44521 {
44530 {
44551 }
44554 {
44555 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44559 /* Insert the SImode value as low element of V4SImode vector. */
44563 op0),
44565 const1_rtx);
44568 /* Cast the V4SImode vector back to a vector in orignal mode. */
44572 /* Load even elements into the second position. */
44576 const1_rtx));
44578 /* Cast vector to FIRST_IMODE vector. */
44581 }
44583 /* Interleave low FIRST_IMODE vectors. */
44585 {
44589 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44592 }
44594 /* Interleave low SECOND_IMODE vectors. */
44596 {
44599 {
44604 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44605 vector. */
44608 }
44611 /* FALLTHRU */
44618 /* Cast the SECOND_IMODE vector back to a vector on original
44619 mode. */
44625 }
44626 }
44628 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44629 all values variable, and none identical. */
44631 static void
44634 {
44641 {
44646 /* FALLTHRU */
44674 half:
44697 quarter:
44723 /* FALLTHRU */
44729 /* Don't use ix86_expand_vector_init_interleave if we can't
44730 move from GPR to SSE register directly. */
44746 }
44748 {
44750 machine_mode inner_mode;
44760 {
44764 {
44770 else
44771 {
44776 }
44777 }
44780 }
44785 {
44791 }
44793 {
44799 }
44800 else
44802 }
44803 }
44805 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44806 instructions unless MMX_OK is true. */
44808 void
44810 {
44817 rtx x;
44820 {
44830 }
44832 /* Constants are best loaded from the constant pool. */
44834 {
44837 }
44839 /* If all values are identical, broadcast the value. */
44845 /* Values where only one field is non-constant are best loaded from
44846 the pool and overwritten via move later. */
44848 {
44852 one_var))
44857 }
44860 }
44862 void
44864 {
44867 machine_mode half_mode;
44869 rtx tmp;
44871 = {
44878 };
44880 = {
44887 };
44893 {
44897 {
44902 else
44906 }
44918 else
44924 {
44927 /* For the two element vectors, we implement a VEC_CONCAT with
44928 the extraction of the other element. */
44935 else
44940 }
44949 {
44955 /* tmp = target = A B C D */
44957 /* target = A A B B */
44959 /* target = X A B B */
44961 /* target = A X C D */
44968 /* tmp = target = A B C D */
44970 /* tmp = X B C D */
44972 /* target = A B X D */
44979 /* tmp = target = A B C D */
44981 /* tmp = X B C D */
44983 /* target = A B X D */
44991 }
44999 /* Element 0 handled by vec_merge below. */
45001 {
45004 }
45007 {
45008 /* With SSE2, use integer shuffles to swap element 0 and ELT,
45009 store into element 0, then shuffle them back. */
45026 }
45027 else
45028 {
45029 /* For SSE1, we have to reuse the V4SF code. */
45033 }
45086 half:
45087 /* Compute offset. */
45093 /* Extract the half. */
45097 /* Put val in tmp at elt. */
45100 /* Put it back. */
45106 {
45109 }
45114 {
45117 }
45122 {
45125 }
45130 {
45133 }
45138 {
45141 }
45146 {
45149 }
45154 }
45157 {
45163 }
45165 {
45169 }
45170 else
45171 {
45180 }
45181 }
45183 void
45185 {
45189 rtx tmp;
45192 {
45197 /* FALLTHRU */
45210 {
45230 }
45242 {
45244 {
45264 }
45268 }
45269 else
45270 {
45271 /* For SSE1, we have to reuse the V4SF code. */
45275 }
45291 {
45295 else
45299 }
45304 {
45308 else
45312 }
45317 {
45321 else
45325 }
45330 {
45334 else
45338 }
45343 {
45347 else
45351 }
45356 {
45360 else
45364 }
45369 {
45373 else
45377 }
45382 {
45386 else
45390 }
45397 else
45406 else
45415 else
45424 else
45430 /* ??? Could extract the appropriate HImode element and shift. */
45433 }
45436 {
45440 /* Let the rtl optimizers know about the zero extension performed. */
45442 {
45445 }
45448 }
45449 else
45450 {
45457 }
45458 }
45460 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45461 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45462 The upper bits of DEST are undefined, though they shouldn't cause
45463 exceptions (some bits from src or all zeros are ok). */
45465 static void
45467 {
45470 {
45474 else
45492 else
45499 else
45507 {
45512 const1_rtx);
45513 }
45514 else
45515 {
45519 }
45541 else
45563 }
45567 }
45569 /* Expand a vector reduction. FN is the binary pattern to reduce;
45570 DEST is the destination; IN is the input vector. */
45572 void
45574 {
45579 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45583 {
45586 }
45591 {
45596 else
45600 }
45601 }
45602 \f
45603 /* Target hook for scalar_mode_supported_p. */
45604 static bool
45606 {
45611 else
45613 }
45615 /* Implements target hook vector_mode_supported_p. */
45616 static bool
45618 {
45632 }
45634 /* Implement target hook libgcc_floating_mode_supported_p. */
45635 static bool
45637 {
45639 {
45646 #ifdef IX86_NO_LIBGCC_TFMODE
45648 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45650 #else
45652 #endif
45656 }
45657 }
45659 /* Target hook for c_mode_for_suffix. */
45660 static machine_mode
45662 {
45669 }
45671 /* Worker function for TARGET_MD_ASM_ADJUST.
45673 We implement asm flag outputs, and maintain source compatibility
45674 with the old cc0-based compiler. */
45680 {
45688 {
45694 {
45697 }
45707 {
45756 }
45758 {
45761 }
45767 {
45768 /* This is the first asm flag output. Here we put the flags
45769 register in as the real output and adjust the condition to
45770 allow it. */
45774 }
45775 else
45776 {
45777 /* We don't need the flags register as output twice. */
45780 }
45787 {
45790 }
45796 {
45802 {
45807 }
45808 else
45810 }
45813 {
45818 }
45819 else
45821 }
45827 else
45828 {
45829 /* If we had no asm flag outputs, clobber the flags. */
45833 }
45834 }
45836 /* Implements target vector targetm.asm.encode_section_info. */
45838 static void ATTRIBUTE_UNUSED
45840 {
45845 }
45847 /* Worker function for REVERSE_CONDITION. */
45849 enum rtx_code
45851 {
45855 }
45857 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45858 to OPERANDS[0]. */
45862 {
45864 {
45867 {
45871 }
45875 }
45877 {
45881 else
45882 {
45883 /* There is no non-popping store to memory for XFmode.
45884 So if we need one, follow the store with a load. */
45887 else
45889 }
45890 }
45891 else
45893 }
45895 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45896 FP status register is set. */
45898 void
45900 {
45902 rtx temp;
45907 {
45912 }
45913 else
45914 {
45919 }
45923 pc_rtx);
45928 }
45930 /* Output code to perform a log1p XFmode calculation. */
45933 {
45939 rtx test;
45945 XFmode));
45959 }
45961 /* Emit code for round calculation. */
45963 {
45970 rtx insn;
45975 {
45987 }
45990 {
46011 }
46019 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
46021 /* scratch = fxam(op1) */
46024 UNSPEC_FXAM)));
46025 /* e1 = fabs(op1) */
46028 /* e2 = e1 + 0.5 */
46032 /* res = floor(e2) */
46034 {
46038 }
46039 else
46043 {
46046 {
46053 UNSPEC_TRUNC_NOOP)));
46054 }
46070 }
46072 /* flags = signbit(a) */
46075 /* if (flags) then res = -res */
46079 pc_rtx);
46090 }
46092 /* Output code to perform a Newton-Rhapson approximation of a single precision
46093 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
46096 {
46104 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
46108 /* x0 = rcp(b) estimate */
46111 UNSPEC_RCP14)));
46112 else
46114 UNSPEC_RCP)));
46116 /* e0 = x0 * b */
46119 /* e0 = x0 * e0 */
46122 /* e1 = x0 + x0 */
46125 /* x1 = e1 - e0 */
46128 /* res = a * x1 */
46130 }
46132 /* Output code to perform a Newton-Rhapson approximation of a
46133 single precision floating point [reciprocal] square root. */
46137 {
46139 REAL_VALUE_TYPE r;
46156 {
46159 /* There is no 512-bit rsqrt. There is however rsqrt14. */
46162 }
46164 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
46165 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
46169 /* x0 = rsqrt(a) estimate */
46171 unspec)));
46173 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
46175 {
46183 /* Handle masked compare. */
46185 {
46187 /* Imm value 0x4 corresponds to not-equal comparison. */
46190 }
46191 else
46192 {
46196 }
46197 }
46199 /* e0 = x0 * a */
46201 /* e1 = e0 * x0 */
46204 /* e2 = e1 - 3. */
46210 /* e3 = -.5 * x0 */
46212 else
46213 /* e3 = -.5 * e0 */
46215 /* ret = e2 * e3 */
46217 }
46219 #ifdef TARGET_SOLARIS
46220 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
46222 static void
46224 tree decl)
46225 {
46226 /* With Binutils 2.15, the "@unwind" marker must be specified on
46227 every occurrence of the ".eh_frame" section, not just the first
46228 one. */
46231 {
46235 }
46237 #ifndef USE_GAS
46239 {
46242 }
46243 #endif
46246 }
46249 /* Return the mangling of TYPE if it is an extended fundamental type. */
46253 {
46261 {
46263 /* __float128 is "g". */
46266 /* "long double" or __float80 is "e". */
46270 }
46271 }
46273 /* For 32-bit code we can save PIC register setup by using
46274 __stack_chk_fail_local hidden function instead of calling
46275 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
46276 register, so it is better to call __stack_chk_fail directly. */
46278 static tree ATTRIBUTE_UNUSED
46280 {
46281 return TARGET_64BIT
46284 }
46286 /* Select a format to encode pointers in exception handling data. CODE
46287 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
46288 true if the symbol may be affected by dynamic relocations.
46290 ??? All x86 object file formats are capable of representing this.
46291 After all, the relocation needed is the same as for the call insn.
46292 Whether or not a particular assembler allows us to enter such, I
46293 guess we'll have to see. */
46294 int
46296 {
46298 {
46305 }
46310 }
46311 \f
46312 /* Expand copysign from SIGN to the positive value ABS_VALUE
46313 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
46314 the sign-bit. */
46315 static void
46317 {
46321 {
46322 machine_mode vmode;
46328 else
46333 {
46334 /* We need to generate a scalar mode mask in this case. */
46339 }
46340 }
46341 else
46345 }
46347 /* Expand fabs (OP0) and return a new rtx that holds the result. The
46348 mask for masking out the sign-bit is stored in *SMASK, if that is
46349 non-null. */
46350 static rtx
46352 {
46361 else
46365 {
46366 /* We need to generate a scalar mode mask in this case. */
46371 }
46378 }
46380 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
46381 swapping the operands if SWAP_OPERANDS is true. The expanded
46382 code is a forward jump to a newly created label in case the
46383 comparison is true. The generated label rtx is returned. */
46387 {
46390 rtx tmp;
46405 }
46407 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
46408 using comparison code CODE. Operands are swapped for the comparison if
46409 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
46410 static rtx
46413 {
46426 }
46428 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46429 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46430 static rtx
46432 {
46433 REAL_VALUE_TYPE TWO52r;
46434 rtx TWO52;
46441 }
46443 /* Expand SSE sequence for computing lround from OP1 storing
46444 into OP0. */
46445 void
46447 {
46448 /* C code for the stuff we're doing below:
46449 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46450 return (long)tmp;
46451 */
46455 rtx adj;
46457 /* load nextafter (0.5, 0.0) */
46462 /* adj = copysign (0.5, op1) */
46466 /* adj = op1 + adj */
46469 /* op0 = (imode)adj */
46471 }
46473 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46474 into OPERAND0. */
46475 void
46477 {
46478 /* C code for the stuff we're doing below (for do_floor):
46479 xi = (long)op1;
46480 xi -= (double)xi > op1 ? 1 : 0;
46481 return xi;
46482 */
46488 /* reg = (long)op1 */
46492 /* freg = (double)reg */
46496 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46507 }
46509 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46510 result in OPERAND0. */
46511 void
46513 {
46514 /* C code for the stuff we're doing below:
46515 xa = fabs (operand1);
46516 if (!isless (xa, 2**52))
46517 return operand1;
46518 xa = xa + 2**52 - 2**52;
46519 return copysign (xa, operand1);
46520 */
46528 /* xa = abs (operand1) */
46531 /* if (!isless (xa, TWO52)) goto label; */
46544 }
46546 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46547 into OPERAND0. */
46548 void
46550 {
46551 /* C code for the stuff we expand below.
46552 double xa = fabs (x), x2;
46553 if (!isless (xa, TWO52))
46554 return x;
46555 xa = xa + TWO52 - TWO52;
46556 x2 = copysign (xa, x);
46557 Compensate. Floor:
46558 if (x2 > x)
46559 x2 -= 1;
46560 Compensate. Ceil:
46561 if (x2 < x)
46562 x2 -= -1;
46563 return x2;
46564 */
46571 /* Temporary for holding the result, initialized to the input
46572 operand to ease control flow. */
46576 /* xa = abs (operand1) */
46579 /* if (!isless (xa, TWO52)) goto label; */
46582 /* xa = xa + TWO52 - TWO52; */
46586 /* xa = copysign (xa, operand1) */
46589 /* generate 1.0 or -1.0 */
46594 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46597 /* We always need to subtract here to preserve signed zero. */
46606 }
46608 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46609 into OPERAND0. */
46610 void
46612 {
46613 /* C code for the stuff we expand below.
46614 double xa = fabs (x), x2;
46615 if (!isless (xa, TWO52))
46616 return x;
46617 x2 = (double)(long)x;
46618 Compensate. Floor:
46619 if (x2 > x)
46620 x2 -= 1;
46621 Compensate. Ceil:
46622 if (x2 < x)
46623 x2 += 1;
46624 if (HONOR_SIGNED_ZEROS (mode))
46625 return copysign (x2, x);
46626 return x2;
46627 */
46634 /* Temporary for holding the result, initialized to the input
46635 operand to ease control flow. */
46639 /* xa = abs (operand1) */
46642 /* if (!isless (xa, TWO52)) goto label; */
46645 /* xa = (double)(long)x */
46650 /* generate 1.0 */
46653 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46667 }
46669 /* Expand SSE sequence for computing round from OPERAND1 storing
46670 into OPERAND0. Sequence that works without relying on DImode truncation
46671 via cvttsd2siq that is only available on 64bit targets. */
46672 void
46674 {
46675 /* C code for the stuff we expand below.
46676 double xa = fabs (x), xa2, x2;
46677 if (!isless (xa, TWO52))
46678 return x;
46679 Using the absolute value and copying back sign makes
46680 -0.0 -> -0.0 correct.
46681 xa2 = xa + TWO52 - TWO52;
46682 Compensate.
46683 dxa = xa2 - xa;
46684 if (dxa <= -0.5)
46685 xa2 += 1;
46686 else if (dxa > 0.5)
46687 xa2 -= 1;
46688 x2 = copysign (xa2, x);
46689 return x2;
46690 */
46697 /* Temporary for holding the result, initialized to the input
46698 operand to ease control flow. */
46702 /* xa = abs (operand1) */
46705 /* if (!isless (xa, TWO52)) goto label; */
46708 /* xa2 = xa + TWO52 - TWO52; */
46712 /* dxa = xa2 - xa; */
46715 /* generate 0.5, 1.0 and -0.5 */
46721 /* Compensate. */
46723 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46727 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46732 /* res = copysign (xa2, operand1) */
46739 }
46741 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46742 into OPERAND0. */
46743 void
46745 {
46746 /* C code for SSE variant we expand below.
46747 double xa = fabs (x), x2;
46748 if (!isless (xa, TWO52))
46749 return x;
46750 x2 = (double)(long)x;
46751 if (HONOR_SIGNED_ZEROS (mode))
46752 return copysign (x2, x);
46753 return x2;
46754 */
46761 /* Temporary for holding the result, initialized to the input
46762 operand to ease control flow. */
46766 /* xa = abs (operand1) */
46769 /* if (!isless (xa, TWO52)) goto label; */
46772 /* x = (double)(long)x */
46784 }
46786 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46787 into OPERAND0. */
46788 void
46790 {
46795 /* C code for SSE variant we expand below.
46796 double xa = fabs (x), x2;
46797 if (!isless (xa, TWO52))
46798 return x;
46799 xa2 = xa + TWO52 - TWO52;
46800 Compensate:
46801 if (xa2 > xa)
46802 xa2 -= 1.0;
46803 x2 = copysign (xa2, x);
46804 return x2;
46805 */
46809 /* Temporary for holding the result, initialized to the input
46810 operand to ease control flow. */
46814 /* xa = abs (operand1) */
46817 /* if (!isless (xa, TWO52)) goto label; */
46820 /* res = xa + TWO52 - TWO52; */
46825 /* generate 1.0 */
46828 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46835 /* res = copysign (res, operand1) */
46842 }
46844 /* Expand SSE sequence for computing round from OPERAND1 storing
46845 into OPERAND0. */
46846 void
46848 {
46849 /* C code for the stuff we're doing below:
46850 double xa = fabs (x);
46851 if (!isless (xa, TWO52))
46852 return x;
46853 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46854 return copysign (xa, x);
46855 */
46862 /* Temporary for holding the result, initialized to the input
46863 operand to ease control flow. */
46871 /* load nextafter (0.5, 0.0) */
46876 /* xa = xa + 0.5 */
46880 /* xa = (double)(int64_t)xa */
46885 /* res = copysign (xa, operand1) */
46892 }
46894 /* Expand SSE sequence for computing round
46895 from OP1 storing into OP0 using sse4 round insn. */
46896 void
46898 {
46907 {
46918 }
46920 /* round (a) = trunc (a + copysign (0.5, a)) */
46922 /* load nextafter (0.5, 0.0) */
46928 /* e1 = copysign (0.5, op1) */
46932 /* e2 = op1 + e1 */
46935 /* res = trunc (e2) */
46940 }
46941 \f
46943 /* Table of valid machine attributes. */
46945 {
46946 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46947 affects_type_identity } */
46948 /* Stdcall attribute says callee is responsible for popping arguments
46949 if they are not variable. */
46952 /* Fastcall attribute says callee is responsible for popping arguments
46953 if they are not variable. */
46956 /* Thiscall attribute says callee is responsible for popping arguments
46957 if they are not variable. */
46960 /* Cdecl attribute says the callee is a normal C declaration */
46963 /* Regparm attribute specifies how many integer arguments are to be
46964 passed in registers. */
46967 /* Sseregparm attribute says we are using x86_64 calling conventions
46968 for FP arguments. */
46971 /* The transactional memory builtins are implicitly regparm or fastcall
46972 depending on the ABI. Override the generic do-nothing attribute that
46973 these builtins were declared with. */
46976 /* force_align_arg_pointer says this function realigns the stack at entry. */
46979 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46984 #endif
46989 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46990 SUBTARGET_ATTRIBUTE_TABLE,
46991 #endif
46992 /* ms_abi and sysv_abi calling convention function attributes. */
46999 /* End element. */
47001 };
47003 /* Implement targetm.vectorize.builtin_vectorization_cost. */
47004 static int
47007 {
47011 {
47056 }
47057 }
47059 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
47060 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
47061 insn every time. */
47065 /* Initialize vselect_insn. */
47067 static void
47069 {
47071 rtx x;
47082 }
47084 /* Construct (set target (vec_select op0 (parallel perm))) and
47085 return true if that's a valid instruction in the active ISA. */
47087 static bool
47090 {
47116 }
47118 /* Similar, but generate a vec_concat from op0 and op1 as well. */
47120 static bool
47124 {
47125 machine_mode v2mode;
47126 rtx x;
47141 }
47143 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47144 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
47146 static bool
47148 {
47157 && (TARGET_AVX512BW
47159 ;
47161 ;
47163 ;
47165 ;
47166 else
47169 /* This is a blend, not a permute. Elements must stay in their
47170 respective lanes. */
47172 {
47176 }
47181 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
47182 decision should be extracted elsewhere, so that we only try that
47183 sequence once all budget==3 options have been tried. */
47190 {
47220 /* See if bytes move in pairs so we can use pblendw with
47221 an immediate argument, rather than pblendvb with a vector
47222 argument. */
47225 {
47226 use_pblendvb:
47230 finish_pblendvb:
47236 else
47241 }
47246 /* FALLTHRU */
47248 do_subreg:
47255 /* See if bytes move in pairs. If not, vpblendvb must be used. */
47259 /* See if bytes move in quadruplets. If yes, vpblendd
47260 with immediate can be used. */
47265 {
47266 /* See if bytes move the same in both lanes. If yes,
47267 vpblendw with immediate can be used. */
47272 /* Use vpblendw. */
47277 }
47279 /* Use vpblendd. */
47286 /* See if words move in pairs. If yes, vpblendd can be used. */
47291 {
47292 /* See if words move the same in both lanes. If not,
47293 vpblendvb must be used. */
47296 {
47297 /* Use vpblendvb. */
47307 }
47309 /* Use vpblendw. */
47313 }
47315 /* Use vpblendd. */
47322 /* Use vpblendd. */
47330 }
47333 {
47350 }
47354 else
47357 /* This matches five different patterns with the different modes. */
47365 }
47367 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47368 in terms of the variable form of vpermilps.
47370 Note that we will have already failed the immediate input vpermilps,
47371 which requires that the high and low part shuffle be identical; the
47372 variable form doesn't require that. */
47374 static bool
47376 {
47383 /* We can only permute within the 128-bit lane. */
47385 {
47389 }
47395 {
47398 /* Within each 128-bit lane, the elements of op0 are numbered
47399 from 0 and the elements of op1 are numbered from 4. */
47406 }
47413 }
47415 /* Return true if permutation D can be performed as VMODE permutation
47416 instead. */
47418 static bool
47420 {
47435 else
47441 }
47443 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47444 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47446 static bool
47448 {
47457 {
47459 {
47462 {
47466 /* Use vperm2i128 insn. The pattern uses
47467 V4DImode instead of V2TImode. */
47480 }
47482 }
47483 }
47484 else
47485 {
47487 {
47490 }
47492 {
47496 /* V4DImode should be already handled through
47497 expand_vselect by vpermq instruction. */
47504 {
47505 /* First see if vpermq can be used for
47506 V8SImode/V16HImode/V32QImode. */
47508 {
47516 {
47520 }
47522 }
47524 /* Next see if vpermd can be used. */
47527 }
47528 /* Or if vpermps can be used. */
47533 {
47534 /* vpshufb only works intra lanes, it is not
47535 possible to shuffle bytes in between the lanes. */
47539 }
47540 }
47542 {
47546 /* If vpermq didn't work, vpshufb won't work either. */
47554 {
47555 /* First see if vpermq can be used for
47556 V16SImode/V32HImode/V64QImode. */
47558 {
47566 {
47570 }
47572 }
47574 /* Next see if vpermd can be used. */
47577 }
47578 /* Or if vpermps can be used. */
47582 {
47583 /* vpshufb only works intra lanes, it is not
47584 possible to shuffle bytes in between the lanes. */
47588 }
47589 }
47590 else
47592 }
47603 else
47604 {
47612 else
47616 {
47620 }
47621 }
47632 {
47647 else
47649 }
47650 else
47651 {
47654 }
47659 }
47661 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47662 in a single instruction. */
47664 static bool
47666 {
47670 /* Check plain VEC_SELECT first, because AVX has instructions that could
47671 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47672 input where SEL+CONCAT may not. */
47674 {
47680 {
47686 }
47689 {
47693 }
47695 {
47696 /* Use vpbroadcast{b,w,d}. */
47699 {
47742 /* For other modes prefer other shuffles this function creates. */
47744 }
47746 {
47750 }
47751 }
47756 /* There are plenty of patterns in sse.md that are written for
47757 SEL+CONCAT and are not replicated for a single op. Perhaps
47758 that should be changed, to avoid the nastiness here. */
47760 /* Recognize interleave style patterns, which means incrementing
47761 every other permutation operand. */
47763 {
47766 }
47771 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47773 {
47775 {
47780 }
47785 }
47786 }
47788 /* Finally, try the fully general two operand permute. */
47793 /* Recognize interleave style patterns with reversed operands. */
47795 {
47797 {
47801 else
47804 }
47809 }
47811 /* Try the SSE4.1 blend variable merge instructions. */
47815 /* Try one of the AVX vpermil variable permutations. */
47819 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47820 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47824 /* Try the AVX2 vpalignr instruction. */
47828 /* Try the AVX512F vpermi2 instructions. */
47833 }
47835 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47836 in terms of a pair of pshuflw + pshufhw instructions. */
47838 static bool
47840 {
47848 /* The two permutations only operate in 64-bit lanes. */
47859 /* Emit the pshuflw. */
47866 /* Emit the pshufhw. */
47874 }
47876 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47877 the permutation using the SSSE3 palignr instruction. This succeeds
47878 when all of the elements in PERM fit within one vector and we merely
47879 need to shift them down so that a single vector permutation has a
47880 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47881 the vpalignr instruction itself can perform the requested permutation. */
47883 static bool
47885 {
47892 /* Even with AVX, palignr only operates on 128-bit vectors,
47893 in AVX2 palignr operates on both 128-bit lanes. */
47903 {
47907 {
47910 }
47919 }
47922 {
47931 }
47933 /* Given that we have SSSE3, we know we'll be able to implement the
47934 single operand permutation after the palignr with pshufb for
47935 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47936 first. */
47942 {
47947 }
47951 {
47957 else
47962 }
47968 /* For AVX2, test whether we can permute the result in one instruction. */
47970 {
47975 }
47979 {
47983 }
47984 else
47985 {
47990 shift));
47991 }
47995 /* Test for the degenerate case where the alignment by itself
47996 produces the desired permutation. */
47998 {
48001 }
48007 }
48009 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
48010 the permutation using the SSE4_1 pblendv instruction. Potentially
48011 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
48013 static bool
48015 {
48021 /* Use the same checks as in expand_vec_perm_blend. */
48025 ;
48027 ;
48029 ;
48030 else
48033 /* Figure out where permutation elements stay not in their
48034 respective lanes. */
48036 {
48040 }
48041 /* We can pblend the part where elements stay not in their
48042 respective lanes only when these elements are all in one
48043 half of a permutation.
48044 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
48045 lanes, but both 8 and 9 >= 8
48046 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
48047 respective lanes and 8 >= 8, but 2 not. */
48053 /* First we apply one operand permutation to the part where
48054 elements stay not in their respective lanes. */
48058 else
48070 else
48075 /* Next we put permuted elements into their positions. */
48079 else
48089 }
48093 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48094 a two vector permutation into a single vector permutation by using
48095 an interleave operation to merge the vectors. */
48097 static bool
48099 {
48108 {
48111 }
48113 {
48116 /* For 32-byte modes allow even d->one_operand_p.
48117 The lack of cross-lane shuffling in some instructions
48118 might prevent a single insn shuffle. */
48121 /* If expand_vec_perm_interleave3 can expand this into
48122 a 3 insn sequence, give up and let it be expanded as
48123 3 insn sequence. While that is one insn longer,
48124 it doesn't need a memory operand and in the common
48125 case that both interleave low and high permutations
48126 with the same operands are adjacent needs 4 insns
48127 for both after CSE. */
48130 }
48131 else
48134 /* Examine from whence the elements come. */
48143 {
48146 /* Split the two input vectors into 4 halves. */
48152 /* If the elements from the low halves use interleave low, and similarly
48153 for interleave high. If the elements are from mis-matched halves, we
48154 can use shufps for V4SF/V4SI or do a DImode shuffle. */
48156 {
48157 /* punpckl* */
48159 {
48164 }
48167 }
48169 {
48170 /* punpckh* */
48172 {
48177 }
48180 }
48182 {
48183 /* shufps */
48185 {
48190 }
48192 {
48193 /* shufpd */
48198 }
48199 }
48201 {
48202 /* shufps */
48204 {
48209 }
48211 {
48212 /* shufpd */
48217 }
48218 }
48219 else
48221 }
48222 else
48223 {
48228 /* Split the two input vectors into 8 quarters. */
48234 {
48237 }
48240 {
48244 }
48246 {
48249 }
48252 {
48254 {
48255 /* Attempt to increase the likelihood that dfinal
48256 shuffle will be intra-lane. */
48258 }
48260 /* vperm2f128 or vperm2i128. */
48262 {
48267 }
48272 {
48276 {
48279 }
48280 }
48281 }
48286 {
48287 /* vpunpckl* */
48289 {
48298 }
48299 }
48302 {
48303 /* vpunpckh* */
48305 {
48314 }
48315 }
48316 else
48318 }
48320 /* Use the remapping array set up above to move the elements from their
48321 swizzled locations into their final destinations. */
48324 {
48327 /* If same_halves is true, both halves of the remapped vector are the
48328 same. Avoid cross-lane accesses if possible. */
48330 {
48333 }
48334 else
48336 }
48338 {
48341 }
48345 /* Test if the final remap can be done with a single insn. For V4SFmode or
48346 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
48359 {
48362 }
48369 }
48371 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48372 a single vector cross-lane permutation into vpermq followed
48373 by any of the single insn permutations. */
48375 static bool
48377 {
48391 {
48394 }
48397 {
48402 }
48415 {
48422 }
48429 {
48434 ;
48437 else
48439 }
48448 }
48450 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48451 a vector permutation using two instructions, vperm2f128 resp.
48452 vperm2i128 followed by any single in-lane permutation. */
48454 static bool
48456 {
48470 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48471 immediate. For perm < 16 the second permutation uses
48472 d->op0 as first operand, for perm >= 16 it uses d->op1
48473 as first operand. The second operand is the result of
48474 vperm2[fi]128. */
48476 {
48477 /* Ignore permutations which do not move anything cross-lane. */
48479 {
48480 /* The second shuffle for e.g. V4DFmode has
48481 0123 and ABCD operands.
48482 Ignore AB23, as 23 is already in the second lane
48483 of the first operand. */
48485 /* And 01CD, as 01 is in the first lane of the first
48486 operand. */
48488 /* And 4567, as then the vperm2[fi]128 doesn't change
48489 anything on the original 4567 second operand. */
48491 }
48492 else
48493 {
48494 /* The second shuffle for e.g. V4DFmode has
48495 4567 and ABCD operands.
48496 Ignore AB67, as 67 is already in the second lane
48497 of the first operand. */
48499 /* And 45CD, as 45 is in the first lane of the first
48500 operand. */
48502 /* And 0123, as then the vperm2[fi]128 doesn't change
48503 anything on the original 0123 first operand. */
48505 }
48508 {
48514 else
48516 }
48519 {
48523 }
48524 else
48528 {
48532 /* Found a usable second shuffle. dfirst will be
48533 vperm2f128 on d->op0 and d->op1. */
48545 /* And dsecond is some single insn shuffle, taking
48546 d->op0 and result of vperm2f128 (if perm < 16) or
48547 d->op1 and result of vperm2f128 (otherwise). */
48556 }
48558 /* For one operand, the only useful vperm2f128 permutation is 0x01
48559 aka lanes swap. */
48562 }
48565 }
48567 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48568 a two vector permutation using 2 intra-lane interleave insns
48569 and cross-lane shuffle for 32-byte vectors. */
48571 static bool
48573 {
48580 ;
48582 ;
48583 else
48598 {
48602 else
48608 else
48614 else
48620 else
48626 else
48632 else
48637 }
48641 }
48643 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48644 a single vector permutation using a single intra-lane vector
48645 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48646 the non-swapped and swapped vectors together. */
48648 static bool
48650 {
48658 || TARGET_AVX2
48667 {
48674 }
48709 }
48711 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48712 permutation using two vperm2f128, followed by a vshufpd insn blending
48713 the two vectors together. */
48715 static bool
48717 {
48760 }
48762 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48763 permutation with two pshufb insns and an ior. We should have already
48764 failed all two instruction sequences. */
48766 static bool
48768 {
48782 /* Generate two permutation masks. If the required element is within
48783 the given vector it is shuffled into the proper lane. If the required
48784 element is in the other vector, force a zero into the lane by setting
48785 bit 7 in the permutation mask. */
48788 {
48795 {
48798 }
48799 }
48823 }
48825 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48826 with two vpshufb insns, vpermq and vpor. We should have already failed
48827 all two or three instruction sequences. */
48829 static bool
48831 {
48846 /* Generate two permutation masks. If the required element is within
48847 the same lane, it is shuffled in. If the required element from the
48848 other lane, force a zero by setting bit 7 in the permutation mask.
48849 In the other mask the mask has non-negative elements if element
48850 is requested from the other lane, but also moved to the other lane,
48851 so that the result of vpshufb can have the two V2TImode halves
48852 swapped. */
48855 {
48860 {
48863 }
48864 }
48873 /* Swap the 128-byte lanes of h into hp. */
48877 const1_rtx));
48894 }
48896 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48897 and extract-odd permutations of two V32QImode and V16QImode operand
48898 with two vpshufb insns, vpor and vpermq. We should have already
48899 failed all two or three instruction sequences. */
48901 static bool
48903 {
48922 /* Generate two permutation masks. In the first permutation mask
48923 the first quarter will contain indexes for the first half
48924 of the op0, the second quarter will contain bit 7 set, third quarter
48925 will contain indexes for the second half of the op0 and the
48926 last quarter bit 7 set. In the second permutation mask
48927 the first quarter will contain bit 7 set, the second quarter
48928 indexes for the first half of the op1, the third quarter bit 7 set
48929 and last quarter indexes for the second half of the op1.
48930 I.e. the first mask e.g. for V32QImode extract even will be:
48931 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48932 (all values masked with 0xf except for -128) and second mask
48933 for extract even will be
48934 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48937 {
48943 {
48946 }
48947 }
48966 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48974 }
48976 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48977 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48978 with two "and" and "pack" or two "shift" and "pack" insns. We should
48979 have already failed all two instruction sequences. */
48981 static bool
48983 {
48987 machine_mode half_mode;
48996 {
48998 /* Required for "pack". */
49009 /* No check as all instructions are SSE2. */
49040 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
49041 general shuffles. */
49043 }
49045 /* Check that permutation is even or odd. */
49060 {
49067 }
49068 else
49069 {
49076 }
49077 /* In AVX2 for 256 bit case we need to permute pack result. */
49079 {
49085 const0_rtx,
49086 const2_rtx,
49087 const1_rtx,
49090 }
49091 else
49095 }
49097 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
49098 and extract-odd permutations. */
49100 static bool
49102 {
49106 {
49113 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
49117 /* Now an unpck[lh]pd will produce the result required. */
49120 else
49126 {
49135 /* Shuffle within the 128-bit lanes to produce:
49136 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
49140 /* Shuffle the lanes around to produce:
49141 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
49145 /* Shuffle within the 128-bit lanes to produce:
49146 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
49149 /* Shuffle within the 128-bit lanes to produce:
49150 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
49153 /* Shuffle the lanes around to produce:
49154 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
49157 }
49164 /* These are always directly implementable by expand_vec_perm_1. */
49172 else
49173 {
49176 /* We need 2*log2(N)-1 operations to achieve odd/even
49177 with interleave. */
49186 else
49189 }
49201 {
49206 else
49211 {
49216 }
49218 }
49226 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
49230 /* Now an vpunpck[lh]qdq will produce the result required. */
49233 else
49240 {
49245 else
49250 {
49255 }
49257 }
49268 /* Shuffle the lanes around into
49269 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
49277 /* Swap the 2nd and 3rd position in each lane into
49278 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
49284 /* Now an vpunpck[lh]qdq will produce
49285 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
49289 else
49298 }
49301 }
49303 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49304 extract-even and extract-odd permutations. */
49306 static bool
49308 {
49320 }
49322 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
49323 permutations. We assume that expand_vec_perm_1 has already failed. */
49325 static bool
49327 {
49335 {
49338 /* These are special-cased in sse.md so that we can optionally
49339 use the vbroadcast instruction. They expand to two insns
49340 if the input happens to be in a register. */
49347 /* These are always implementable using standard shuffle patterns. */
49352 /* These can be implemented via interleave. We save one insn by
49353 stopping once we have promoted to V4SImode and then use pshufd. */
49356 do
49357 {
49358 rtx dest;
49364 {
49368 }
49375 }
49391 /* For AVX2 broadcasts of the first element vpbroadcast* or
49392 vpermq should be used by expand_vec_perm_1. */
49398 }
49399 }
49401 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49402 broadcast permutations. */
49404 static bool
49406 {
49418 }
49420 /* Implement arbitrary permutations of two V64QImode operands
49421 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
49422 static bool
49424 {
49434 machine_mode vmode;
49440 {
49447 }
49449 /* Prepare permutations such that the first one takes care of
49450 putting the even bytes into the right positions or one higher
49451 positions (ds[0]) and the second one takes care of
49452 putting the odd bytes into the right positions or one below
49453 (ds[1]). */
49456 {
49459 {
49462 }
49463 else
49464 {
49467 }
49468 }
49490 }
49492 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49493 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49494 all the shorter instruction sequences. */
49496 static bool
49498 {
49514 /* Generate 4 permutation masks. If the required element is within
49515 the same lane, it is shuffled in. If the required element from the
49516 other lane, force a zero by setting bit 7 in the permutation mask.
49517 In the other mask the mask has non-negative elements if element
49518 is requested from the other lane, but also moved to the other lane,
49519 so that the result of vpshufb can have the two V2TImode halves
49520 swapped. */
49523 {
49528 }
49534 {
49542 }
49545 {
49547 {
49550 }
49557 }
49559 /* Swap the 128-byte lanes of h[X]. */
49561 {
49567 const1_rtx));
49569 }
49572 {
49574 {
49577 }
49583 }
49586 {
49588 {
49592 }
49595 }
49605 }
49607 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49608 With all of the interface bits taken care of, perform the expansion
49609 in D and return true on success. */
49611 static bool
49613 {
49614 /* Try a single instruction expansion. */
49618 /* Try sequences of two instructions. */
49641 /* Try sequences of three instructions. */
49658 /* Try sequences of four instructions. */
49669 /* ??? Look for narrow permutations whose element orderings would
49670 allow the promotion to a wider mode. */
49672 /* ??? Look for sequences of interleave or a wider permute that place
49673 the data into the correct lanes for a half-vector shuffle like
49674 pshuf[lh]w or vpermilps. */
49676 /* ??? Look for sequences of interleave that produce the desired results.
49677 The combinatorics of punpck[lh] get pretty ugly... */
49682 /* Even longer sequences. */
49687 }
49689 /* If a permutation only uses one operand, make it clear. Returns true
49690 if the permutation references both operands. */
49692 static bool
49694 {
49702 {
49708 {
49711 }
49712 /* The elements of PERM do not suggest that only the first operand
49713 is used, but both operands are identical. Allow easier matching
49714 of the permutation by folding the permutation into the single
49715 input vector. */
49716 /* FALLTHRU */
49727 }
49730 }
49732 bool
49734 {
49739 rtx sel;
49756 {
49761 }
49768 /* If the selector says both arguments are needed, but the operands are the
49769 same, the above tried to expand with one_operand_p and flattened selector.
49770 If that didn't work, retry without one_operand_p; we succeeded with that
49771 during testing. */
49773 {
49777 }
49780 }
49782 /* Implement targetm.vectorize.vec_perm_const_ok. */
49784 static bool
49787 {
49796 /* Given sufficient ISA support we can just return true here
49797 for selected vector modes. */
49799 {
49805 /* All implementable with a single vpermi2 insn. */
49810 /* All implementable with a single vpermi2 insn. */
49815 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49823 /* All implementable with a single vpermi2 insn. */
49828 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49833 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49840 /* All implementable with a single vpperm insn. */
49843 /* All implementable with 2 pshufb + 1 ior. */
49849 /* All implementable with shufpd or unpck[lh]pd. */
49853 }
49855 /* Extract the values from the vector CST into the permutation
49856 array in D. */
49859 {
49863 }
49865 /* For all elements from second vector, fold the elements to first. */
49870 /* Check whether the mask can be applied to the vector type. */
49873 /* Implementable with shufps or pshufd. */
49877 /* Otherwise we have to go through the motions and see if we can
49878 figure out how to generate the requested permutation. */
49889 }
49891 void
49893 {
49908 /* We'll either be able to implement the permutation directly... */
49912 /* ... or we use the special-case patterns. */
49914 }
49916 static void
49918 {
49933 {
49936 }
49938 /* Note that for AVX this isn't one instruction. */
49941 }
49944 /* Expand a vector operation CODE for a V*QImode in terms of the
49945 same operation on V*HImode. */
49947 void
49949 {
49951 machine_mode himode;
49961 {
49979 }
49983 {
49985 /* Unpack data such that we've got a source byte in each low byte of
49986 each word. We don't care what goes into the high byte of each word.
49987 Rather than trying to get zero in there, most convenient is to let
49988 it be a copy of the low byte. */
49993 /* FALLTHRU */
50005 /* FALLTHRU */
50015 }
50017 /* Perform the operation. */
50024 /* Merge the data back into the right place. */
50034 {
50035 /* For SSE2, we used an full interleave, so the desired
50036 results are in the even elements. */
50039 }
50040 else
50041 {
50042 /* For AVX, the interleave used above was not cross-lane. So the
50043 extraction is evens but with the second and third quarter swapped.
50044 Happily, that is even one insn shorter than even extraction. */
50047 }
50054 }
50056 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
50057 if op is CONST_VECTOR with all odd elements equal to their
50058 preceding element. */
50060 static bool
50062 {
50072 }
50074 void
50077 {
50080 rtx x;
50088 /* We only play even/odd games with vectors of SImode. */
50091 /* If we're looking for the odd results, shift those members down to
50092 the even slots. For some cpus this is faster than a PSHUFD. */
50094 {
50095 /* For XOP use vpmacsdqh, but only for smult, as it is only
50096 signed. */
50098 {
50102 }
50113 }
50116 {
50119 else
50121 }
50123 {
50126 else
50128 }
50133 else
50134 {
50137 /* The easiest way to implement this without PMULDQ is to go through
50138 the motions as if we are performing a full 64-bit multiply. With
50139 the exception that we need to do less shuffling of the elements. */
50141 /* Compute the sign-extension, aka highparts, of the two operands. */
50147 /* Multiply LO(A) * HI(B), and vice-versa. */
50153 /* Multiply LO(A) * LO(B). */
50157 /* Combine and shift the highparts into place. */
50162 /* Combine high and low parts. */
50165 }
50167 }
50169 void
50172 {
50178 {
50183 {
50184 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
50185 shuffle the elements once so that all elements are in the right
50186 place for immediate use: { A C B D }. */
50191 }
50192 else
50193 {
50194 /* Put the elements into place for the multiply. */
50198 }
50203 /* Shuffle the elements between the lanes. After this we
50204 have { A B E F | C D G H } for each operand. */
50214 /* Shuffle the elements within the lanes. After this we
50215 have { A A B B | C C D D } or { E E F F | G G H H }. */
50256 }
50257 }
50259 void
50261 {
50271 /* Move the results in element 2 down to element 1; we don't care
50272 what goes in elements 2 and 3. Then we can merge the parts
50273 back together with an interleave.
50275 Note that two other sequences were tried:
50276 (1) Use interleaves at the start instead of psrldq, which allows
50277 us to use a single shufps to merge things back at the end.
50278 (2) Use shufps here to combine the two vectors, then pshufd to
50279 put the elements in the correct order.
50280 In both cases the cost of the reformatting stall was too high
50281 and the overall sequence slower. */
50292 }
50294 void
50296 {
50307 {
50308 /* op1: A,B,C,D, op2: E,F,G,H */
50317 /* t1: B,A,D,C */
50324 /* t2: (B*E),(A*F),(D*G),(C*H) */
50327 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
50330 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
50333 /* Multiply lower parts and add all */
50340 }
50341 else
50342 {
50343 machine_mode nmode;
50347 {
50350 }
50352 {
50355 }
50357 {
50360 }
50361 else
50365 /* Multiply low parts. */
50369 /* Shift input vectors right 32 bits so we can multiply high parts. */
50374 /* Multiply high parts by low parts. */
50380 /* Combine and shift the highparts back. */
50384 /* Combine high and low parts. */
50386 }
50390 }
50392 /* Return 1 if control tansfer instruction INSN
50393 should be encoded with bnd prefix.
50394 If insn is NULL then return 1 when control
50395 transfer instructions should be prefixed with
50396 bnd by default for current function. */
50398 bool
50400 {
50401 /* For call insns check special flag. */
50403 {
50407 }
50409 /* All other insns are prefixed only if function is instrumented. */
50411 }
50413 /* Calculate integer abs() using only SSE2 instructions. */
50415 void
50417 {
50422 {
50423 /* For 32-bit signed integer X, the best way to calculate the absolute
50424 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
50435 /* For 16-bit signed integer X, the best way to calculate the absolute
50436 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50444 /* For 8-bit signed integer X, the best way to calculate the absolute
50445 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50446 as SSE2 provides the PMINUB insn. */
50456 }
50460 }
50462 /* Expand an extract from a vector register through pextr insn.
50463 Return true if successful. */
50465 bool
50467 {
50475 {
50476 /* Reject non-lowpart subregs. */
50480 }
50483 {
50486 }
50489 {
50496 {
50503 {
50531 }
50533 /* Reject extractions from misaligned positions. */
50539 else
50542 /* Construct insn pattern. */
50546 /* Let the rtl optimizers know about the zero extension performed. */
50548 {
50551 }
50558 }
50562 }
50563 }
50565 /* Expand an insert into a vector register through pinsr insn.
50566 Return true if successful. */
50568 bool
50570 {
50578 {
50581 }
50584 {
50591 {
50594 rtx d;
50599 {
50631 }
50633 /* Reject insertions to misaligned positions. */
50638 {
50642 {
50654 }
50655 else
50657 }
50661 else
50670 }
50674 }
50675 }
50676 \f
50677 /* This function returns the calling abi specific va_list type node.
50678 It returns the FNDECL specific va_list type. */
50680 static tree
50682 {
50689 else
50691 }
50693 /* Returns the canonical va_list type specified by TYPE. If there
50694 is no valid TYPE provided, it return NULL_TREE. */
50696 static tree
50698 {
50701 /* Resolve references and pointers to va_list type. */
50710 {
50715 {
50716 /* If va_list is an array type, the argument may have decayed
50717 to a pointer type, e.g. by being passed to another function.
50718 In that case, unwrap both types so that we can compare the
50719 underlying records. */
50722 {
50725 }
50726 }
50733 {
50734 /* If va_list is an array type, the argument may have decayed
50735 to a pointer type, e.g. by being passed to another function.
50736 In that case, unwrap both types so that we can compare the
50737 underlying records. */
50740 {
50743 }
50744 }
50751 {
50752 /* If va_list is an array type, the argument may have decayed
50753 to a pointer type, e.g. by being passed to another function.
50754 In that case, unwrap both types so that we can compare the
50755 underlying records. */
50758 {
50761 }
50762 }
50766 }
50768 }
50770 /* Iterate through the target-specific builtin types for va_list.
50771 IDX denotes the iterator, *PTREE is set to the result type of
50772 the va_list builtin, and *PNAME to its internal type.
50773 Returns zero if there is no element for this index, otherwise
50774 IDX should be increased upon the next call.
50775 Note, do not iterate a base builtin's name like __builtin_va_list.
50776 Used from c_common_nodes_and_builtins. */
50778 static int
50780 {
50782 {
50784 {
50797 }
50798 }
50801 }
50803 #undef TARGET_SCHED_DISPATCH
50804 #define TARGET_SCHED_DISPATCH has_dispatch
50805 #undef TARGET_SCHED_DISPATCH_DO
50806 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50807 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50808 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50809 #undef TARGET_SCHED_REORDER
50810 #define TARGET_SCHED_REORDER ix86_sched_reorder
50811 #undef TARGET_SCHED_ADJUST_PRIORITY
50812 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50813 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50814 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50815 ix86_dependencies_evaluation_hook
50817 /* The size of the dispatch window is the total number of bytes of
50818 object code allowed in a window. */
50819 #define DISPATCH_WINDOW_SIZE 16
50821 /* Number of dispatch windows considered for scheduling. */
50822 #define MAX_DISPATCH_WINDOWS 3
50824 /* Maximum number of instructions in a window. */
50825 #define MAX_INSN 4
50827 /* Maximum number of immediate operands in a window. */
50828 #define MAX_IMM 4
50830 /* Maximum number of immediate bits allowed in a window. */
50831 #define MAX_IMM_SIZE 128
50833 /* Maximum number of 32 bit immediates allowed in a window. */
50834 #define MAX_IMM_32 4
50836 /* Maximum number of 64 bit immediates allowed in a window. */
50837 #define MAX_IMM_64 2
50839 /* Maximum total of loads or prefetches allowed in a window. */
50840 #define MAX_LOAD 2
50842 /* Maximum total of stores allowed in a window. */
50843 #define MAX_STORE 1
50845 #undef BIG
50846 #define BIG 100
50849 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50852 disp_load,
50853 disp_store,
50854 disp_load_store,
50855 disp_prefetch,
50856 disp_imm,
50857 disp_imm_32,
50858 disp_imm_64,
50859 disp_branch,
50860 disp_cmp,
50861 disp_jcc,
50862 disp_last
50863 };
50865 /* Number of allowable groups in a dispatch window. It is an array
50866 indexed by dispatch_group enum. 100 is used as a big number,
50867 because the number of these kind of operations does not have any
50868 effect in dispatch window, but we need them for other reasons in
50869 the table. */
50872 };
50878 };
50880 /* Instruction path. */
50886 last_path
50887 };
50889 /* sched_insn_info defines a window to the instructions scheduled in
50890 the basic block. It contains a pointer to the insn_info table and
50891 the instruction scheduled.
50893 Windows are allocated for each basic block and are linked
50894 together. */
50896 rtx insn;
50903 /* Linked list of dispatch windows. This is a two way list of
50904 dispatch windows of a basic block. It contains information about
50905 the number of uops in the window and the total number of
50906 instructions and of bytes in the object code for this dispatch
50907 window. */
50925 /* Immediate valuse used in an insn. */
50927 {
50936 /* Get dispatch group of insn. */
50938 static enum dispatch_group
50940 {
50956 }
50958 /* Return true if insn is a compare instruction. */
50960 static bool
50962 {
50970 }
50972 /* Return true if a dispatch violation encountered. */
50974 static bool
50976 {
50980 }
50982 /* Return true if insn is a branch instruction. */
50984 static bool
50986 {
50988 }
50990 /* Return true if insn is a prefetch instruction. */
50992 static bool
50994 {
50996 }
50998 /* This function initializes a dispatch window and the list container holding a
50999 pointer to the window. */
51001 static void
51003 {
51009 else
51027 {
51033 }
51035 }
51037 /* This function allocates and initializes a dispatch window and the
51038 list container holding a pointer to the window. */
51042 {
51047 }
51049 /* This routine initializes the dispatch scheduling information. It
51050 initiates building dispatch scheduler tables and constructs the
51051 first dispatch window. */
51053 static void
51055 {
51056 /* Allocate a dispatch list and a window. */
51061 }
51063 /* This function returns true if a branch is detected. End of a basic block
51064 does not have to be a branch, but here we assume only branches end a
51065 window. */
51067 static bool
51069 {
51071 }
51073 /* This function is called when the end of a window processing is reached. */
51075 static void
51077 {
51080 {
51085 }
51087 }
51089 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
51090 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
51091 for 48 bytes of instructions. Note that these windows are not dispatch
51092 windows that their sizes are DISPATCH_WINDOW_SIZE. */
51096 {
51098 {
51103 }
51109 }
51111 /* Compute number of immediate operands of an instruction. */
51113 static void
51115 {
51122 {
51129 else
51141 {
51144 }
51149 }
51150 }
51152 /* Return total size of immediate operands of an instruction along with number
51153 of corresponding immediate-operands. It initializes its parameters to zero
51154 befor calling FIND_CONSTANT.
51155 INSN is the input instruction. IMM is the total of immediates.
51156 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
51157 bit immediates. */
51159 static int
51161 {
51169 }
51171 /* This function indicates if an operand of an instruction is an
51172 immediate. */
51174 static bool
51176 {
51185 }
51187 /* Return single or double path for instructions. */
51189 static enum insn_path
51191 {
51201 }
51203 /* Return insn dispatch group. */
51205 static enum dispatch_group
51207 {
51225 }
51227 /* Count number of GROUP restricted instructions in a dispatch
51228 window WINDOW_LIST. */
51230 static int
51232 {
51243 {
51262 }
51275 }
51277 /* This function returns true if insn satisfies dispatch rules on the
51278 last window scheduled. */
51280 static bool
51282 {
51290 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
51291 instructions should be given the lowest priority in the
51292 scheduling process in Haifa scheduler to make sure they will be
51293 scheduled in the same dispatch window as the reference to them. */
51297 /* Check nonrestricted. */
51301 /* Get last dispatch window. */
51306 {
51311 /* Window 1 is full. Go for next window. */
51313 }
51320 /* See if it fits in the first window. */
51322 {
51323 /* The first widow should have only single and double path
51324 uops. */
51330 }
51332 }
51334 /* Add an instruction INSN with NUM_UOPS micro-operations to the
51335 dispatch window WINDOW_LIST. */
51337 static void
51339 {
51357 /* Initialize window with new instruction. */
51378 {
51381 }
51382 }
51384 /* Adds a scheduled instruction, INSN, to the current dispatch window.
51385 If the total bytes of instructions or the number of instructions in
51386 the window exceed allowable, it allocates a new window. */
51388 static void
51390 {
51413 /* Get the last dispatch window. */
51421 else
51424 /* If current window is full, get a new window.
51425 Window number zero is full, if MAX_INSN uops are scheduled in it.
51426 Window number one is full, if window zero's bytes plus window
51427 one's bytes is 32, or if the bytes of the new instruction added
51428 to the total makes it greater than 48, or it has already MAX_INSN
51429 instructions in it. */
51438 {
51441 }
51444 {
51448 {
51451 }
51452 }
51454 {
51459 {
51462 }
51465 }
51466 else
51470 {
51471 /* End of basic block is reached do end-basic-block process. */
51474 }
51475 }
51477 /* Print the dispatch window, WINDOW_NUM, to FILE. */
51479 DEBUG_FUNCTION static void
51481 {
51487 else
51501 {
51504 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
51510 }
51511 }
51513 /* Print to stdout a dispatch window. */
51515 DEBUG_FUNCTION void
51517 {
51519 }
51521 /* Print INSN dispatch information to FILE. */
51523 DEBUG_FUNCTION static void
51525 {
51548 }
51550 /* Print to STDERR the status of the ready list with respect to
51551 dispatch windows. */
51553 DEBUG_FUNCTION void
51555 {
51563 }
51565 /* This routine is the driver of the dispatch scheduler. */
51567 static void
51569 {
51574 }
51576 /* Return TRUE if Dispatch Scheduling is supported. */
51578 static bool
51580 {
51584 {
51600 }
51603 }
51605 /* Implementation of reassociation_width target hook used by
51606 reassoc phase to identify parallelism level in reassociated
51607 tree. Statements tree_code is passed in OPC. Arguments type
51608 is passed in MODE.
51610 Currently parallel reassociation is enabled for Atom
51611 processors only and we set reassociation width to be 2
51612 because Atom may issue up to 2 instructions per cycle.
51614 Return value should be fixed if parallel reassociation is
51615 enabled for other processors. */
51617 static int
51619 {
51620 /* Vector part. */
51622 {
51625 else
51627 }
51629 /* Scalar part. */
51634 else
51636 }
51638 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51639 place emms and femms instructions. */
51641 static machine_mode
51643 {
51648 {
51667 else
51679 /* FALLTHRU */
51683 }
51684 }
51686 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51687 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51688 256bit and 128bit vectors. */
51690 static unsigned int
51692 {
51695 }
51697 \f
51699 /* Return class of registers which could be used for pseudo of MODE
51700 and of class RCLASS for spilling instead of memory. Return NO_REGS
51701 if it is not possible or non-profitable. */
51702 static reg_class_t
51704 {
51710 }
51712 /* Implement targetm.vectorize.init_cost. */
51716 {
51720 }
51722 /* Implement targetm.vectorize.add_stmt_cost. */
51724 static unsigned
51728 {
51735 /* Statements in an inner loop relative to the loop being
51736 vectorized are weighted more heavily. The value here is
51737 arbitrary and could potentially be improved with analysis. */
51743 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51744 for Silvermont as it has out of order integer pipeline and can execute
51745 2 scalar instruction per tick, but has in order SIMD pipeline. */
51748 {
51752 }
51757 }
51759 /* Implement targetm.vectorize.finish_cost. */
51761 static void
51764 {
51769 }
51771 /* Implement targetm.vectorize.destroy_cost_data. */
51773 static void
51775 {
51777 }
51779 /* Validate target specific memory model bits in VAL. */
51781 static unsigned HOST_WIDE_INT
51783 {
51790 {
51794 }
51797 {
51801 }
51803 {
51807 }
51809 }
51811 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51812 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51813 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51814 or number of vecsize_mangle variants that should be emitted. */
51816 static int
51820 {
51827 {
51831 }
51836 {
51843 /* case SCmode: */
51844 /* case DCmode: */
51850 }
51852 tree t;
51856 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51858 {
51865 /* case SCmode: */
51866 /* case DCmode: */
51872 }
51875 {
51876 /* Parse here processor clause. If not present, default to 'b'. */
51878 }
51880 {
51881 /* If the function isn't exported, we can pick up just one ISA
51882 for the clones. */
51887 else
51890 }
51891 else
51892 {
51895 }
51897 {
51910 }
51912 {
51915 else
51920 }
51922 }
51924 /* Add target attribute to SIMD clone NODE if needed. */
51926 static void
51928 {
51932 {
51947 }
51957 }
51959 /* If SIMD clone NODE can't be used in a vectorized loop
51960 in current function, return -1, otherwise return a badness of using it
51961 (0 if it is most desirable from vecsize_mangle point of view, 1
51962 slightly less desirable, etc.). */
51964 static int
51966 {
51968 {
51986 }
51987 }
51989 /* This function adjusts the unroll factor based on
51990 the hardware capabilities. For ex, bdver3 has
51991 a loop buffer which makes unrolling of smaller
51992 loops less important. This function decides the
51993 unroll factor using number of memory references
51994 (value 32 is used) as a heuristic. */
51996 static unsigned
51998 {
52007 /* Count the number of memory references within the loop body.
52008 This value determines the unrolling factor for bdver3 and bdver4
52009 architectures. */
52018 {
52023 else
52025 }
52032 }
52035 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
52037 static bool
52039 {
52040 /* For x87 floating point with standard excess precision handling,
52041 there is no adddf3 pattern (since x87 floating point only has
52042 XFmode operations) so the default hook implementation gets this
52043 wrong. */
52045 }
52047 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
52049 static void
52051 {
52056 {
52071 hold_fnclex);
52084 }
52086 {
52095 mxcsr_orig_var,
52105 ldmxcsr_hold_call);
52108 else
52113 ldmxcsr_clear_call);
52114 else
52118 stxmcsr_update_call);
52120 {
52126 exceptions_assign);
52127 }
52128 else
52133 ldmxcsr_update_call);
52134 }
52135 tree atomic_feraiseexcept
52140 atomic_feraiseexcept_call);
52141 }
52143 /* Return mode to be used for bounds or VOIDmode
52144 if bounds are not supported. */
52146 static enum machine_mode
52148 {
52149 /* Do not support pointer checker if MPX
52150 is not enabled. */
52152 {
52157 }
52160 }
52162 /* Return constant used to statically initialize constant bounds.
52164 This function is used to create special bound values. For now
52165 only INIT bounds and NONE bounds are expected. More special
52166 values may be added later. */
52168 static tree
52170 {
52176 /* This function is supposed to be used to create INIT and
52177 NONE bounds only. */
52182 }
52184 /* Generate a list of statements STMTS to initialize pointer bounds
52185 variable VAR with bounds LB and UB. Return the number of generated
52186 statements. */
52188 static int
52190 {
52208 }
52210 #if !TARGET_MACHO && !TARGET_DLLIMPORT_DECL_ATTRIBUTES
52211 /* For i386, common symbol is local only for non-PIE binaries. For
52212 x86-64, common symbol is local only for non-PIE binaries or linker
52213 supports copy reloc in PIE binaries. */
52215 static bool
52217 {
52219 (!flag_pic
52220 || (TARGET_64BIT
52222 }
52223 #endif
52225 /* If MEM is in the form of [base+offset], extract the two parts
52226 of address and set to BASE and OFFSET, otherwise return false. */
52228 static bool
52230 {
52231 rtx addr;
52241 {
52245 }
52251 {
52255 }
52258 }
52260 /* Given OPERANDS of consecutive load/store, check if we can merge
52261 them into move multiple. LOAD is true if they are load instructions.
52262 MODE is the mode of memory operands. */
52264 bool
52267 {
52272 {
52277 }
52278 else
52279 {
52284 }
52291 /* Check if the addresses are in the form of [base+offset]. */
52297 /* Check if the bases are the same. */
52304 /* Check if mem_1 is adjacent to mem_2 and mem_1 has lower address. */
52309 }
52311 /* Initialize the GCC target structure. */
52312 #undef TARGET_RETURN_IN_MEMORY
52313 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
52315 #undef TARGET_LEGITIMIZE_ADDRESS
52316 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
52318 #undef TARGET_ATTRIBUTE_TABLE
52319 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
52320 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
52321 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
52322 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52323 # undef TARGET_MERGE_DECL_ATTRIBUTES
52324 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
52325 #endif
52327 #undef TARGET_COMP_TYPE_ATTRIBUTES
52328 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
52330 #undef TARGET_INIT_BUILTINS
52331 #define TARGET_INIT_BUILTINS ix86_init_builtins
52332 #undef TARGET_BUILTIN_DECL
52333 #define TARGET_BUILTIN_DECL ix86_builtin_decl
52334 #undef TARGET_EXPAND_BUILTIN
52335 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
52337 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
52338 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
52339 ix86_builtin_vectorized_function
52341 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
52342 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
52344 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
52345 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
52347 #undef TARGET_VECTORIZE_BUILTIN_GATHER
52348 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
52350 #undef TARGET_BUILTIN_RECIPROCAL
52351 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
52353 #undef TARGET_ASM_FUNCTION_EPILOGUE
52354 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
52356 #undef TARGET_ENCODE_SECTION_INFO
52357 #ifndef SUBTARGET_ENCODE_SECTION_INFO
52358 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
52359 #else
52360 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
52361 #endif
52363 #undef TARGET_ASM_OPEN_PAREN
52365 #undef TARGET_ASM_CLOSE_PAREN
52368 #undef TARGET_ASM_BYTE_OP
52369 #define TARGET_ASM_BYTE_OP ASM_BYTE
52371 #undef TARGET_ASM_ALIGNED_HI_OP
52372 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
52373 #undef TARGET_ASM_ALIGNED_SI_OP
52374 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
52375 #ifdef ASM_QUAD
52376 #undef TARGET_ASM_ALIGNED_DI_OP
52377 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
52378 #endif
52380 #undef TARGET_PROFILE_BEFORE_PROLOGUE
52381 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
52383 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
52384 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
52386 #undef TARGET_ASM_UNALIGNED_HI_OP
52387 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
52388 #undef TARGET_ASM_UNALIGNED_SI_OP
52389 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
52390 #undef TARGET_ASM_UNALIGNED_DI_OP
52391 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
52393 #undef TARGET_PRINT_OPERAND
52394 #define TARGET_PRINT_OPERAND ix86_print_operand
52395 #undef TARGET_PRINT_OPERAND_ADDRESS
52396 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
52397 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
52398 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
52399 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
52400 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
52402 #undef TARGET_SCHED_INIT_GLOBAL
52403 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
52404 #undef TARGET_SCHED_ADJUST_COST
52405 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
52406 #undef TARGET_SCHED_ISSUE_RATE
52407 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
52408 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
52409 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
52410 ia32_multipass_dfa_lookahead
52411 #undef TARGET_SCHED_MACRO_FUSION_P
52412 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
52413 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
52414 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
52416 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
52417 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
52419 #undef TARGET_MEMMODEL_CHECK
52420 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
52422 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
52423 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
52425 #ifdef HAVE_AS_TLS
52426 #undef TARGET_HAVE_TLS
52427 #define TARGET_HAVE_TLS true
52428 #endif
52429 #undef TARGET_CANNOT_FORCE_CONST_MEM
52430 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
52431 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
52432 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
52434 #undef TARGET_DELEGITIMIZE_ADDRESS
52435 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
52437 #undef TARGET_MS_BITFIELD_LAYOUT_P
52438 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
52440 #if TARGET_MACHO
52441 #undef TARGET_BINDS_LOCAL_P
52442 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
52443 #else
52444 #undef TARGET_BINDS_LOCAL_P
52445 #define TARGET_BINDS_LOCAL_P ix86_binds_local_p
52446 #endif
52447 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52448 #undef TARGET_BINDS_LOCAL_P
52449 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
52450 #endif
52452 #undef TARGET_ASM_OUTPUT_MI_THUNK
52453 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
52454 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
52455 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
52457 #undef TARGET_ASM_FILE_START
52458 #define TARGET_ASM_FILE_START x86_file_start
52460 #undef TARGET_OPTION_OVERRIDE
52461 #define TARGET_OPTION_OVERRIDE ix86_option_override
52463 #undef TARGET_REGISTER_MOVE_COST
52464 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
52465 #undef TARGET_MEMORY_MOVE_COST
52466 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
52467 #undef TARGET_RTX_COSTS
52468 #define TARGET_RTX_COSTS ix86_rtx_costs
52469 #undef TARGET_ADDRESS_COST
52470 #define TARGET_ADDRESS_COST ix86_address_cost
52472 #undef TARGET_FIXED_CONDITION_CODE_REGS
52473 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
52474 #undef TARGET_CC_MODES_COMPATIBLE
52475 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
52477 #undef TARGET_MACHINE_DEPENDENT_REORG
52478 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
52480 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
52481 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
52483 #undef TARGET_BUILD_BUILTIN_VA_LIST
52484 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
52486 #undef TARGET_FOLD_BUILTIN
52487 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
52489 #undef TARGET_COMPARE_VERSION_PRIORITY
52490 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
52492 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
52493 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
52494 ix86_generate_version_dispatcher_body
52496 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
52497 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
52498 ix86_get_function_versions_dispatcher
52500 #undef TARGET_ENUM_VA_LIST_P
52501 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
52503 #undef TARGET_FN_ABI_VA_LIST
52504 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
52506 #undef TARGET_CANONICAL_VA_LIST_TYPE
52507 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
52509 #undef TARGET_EXPAND_BUILTIN_VA_START
52510 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
52512 #undef TARGET_MD_ASM_ADJUST
52513 #define TARGET_MD_ASM_ADJUST ix86_md_asm_adjust
52515 #undef TARGET_PROMOTE_PROTOTYPES
52516 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
52517 #undef TARGET_SETUP_INCOMING_VARARGS
52518 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
52519 #undef TARGET_MUST_PASS_IN_STACK
52520 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
52521 #undef TARGET_FUNCTION_ARG_ADVANCE
52522 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
52523 #undef TARGET_FUNCTION_ARG
52524 #define TARGET_FUNCTION_ARG ix86_function_arg
52525 #undef TARGET_INIT_PIC_REG
52526 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
52527 #undef TARGET_USE_PSEUDO_PIC_REG
52528 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
52529 #undef TARGET_FUNCTION_ARG_BOUNDARY
52530 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
52531 #undef TARGET_PASS_BY_REFERENCE
52532 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
52533 #undef TARGET_INTERNAL_ARG_POINTER
52534 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
52535 #undef TARGET_UPDATE_STACK_BOUNDARY
52536 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
52537 #undef TARGET_GET_DRAP_RTX
52538 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
52539 #undef TARGET_STRICT_ARGUMENT_NAMING
52540 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
52541 #undef TARGET_STATIC_CHAIN
52542 #define TARGET_STATIC_CHAIN ix86_static_chain
52543 #undef TARGET_TRAMPOLINE_INIT
52544 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
52545 #undef TARGET_RETURN_POPS_ARGS
52546 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
52548 #undef TARGET_LEGITIMATE_COMBINED_INSN
52549 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
52551 #undef TARGET_ASAN_SHADOW_OFFSET
52552 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
52554 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
52555 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
52557 #undef TARGET_SCALAR_MODE_SUPPORTED_P
52558 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
52560 #undef TARGET_VECTOR_MODE_SUPPORTED_P
52561 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
52563 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
52564 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
52565 ix86_libgcc_floating_mode_supported_p
52567 #undef TARGET_C_MODE_FOR_SUFFIX
52568 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52570 #ifdef HAVE_AS_TLS
52571 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52572 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52573 #endif
52575 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52576 #undef TARGET_INSERT_ATTRIBUTES
52577 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52578 #endif
52580 #undef TARGET_MANGLE_TYPE
52581 #define TARGET_MANGLE_TYPE ix86_mangle_type
52583 #if !TARGET_MACHO
52584 #undef TARGET_STACK_PROTECT_FAIL
52585 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52586 #endif
52588 #undef TARGET_FUNCTION_VALUE
52589 #define TARGET_FUNCTION_VALUE ix86_function_value
52591 #undef TARGET_FUNCTION_VALUE_REGNO_P
52592 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52594 #undef TARGET_PROMOTE_FUNCTION_MODE
52595 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52597 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
52598 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ix86_override_options_after_change
52600 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52601 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52603 #undef TARGET_INSTANTIATE_DECLS
52604 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52606 #undef TARGET_SECONDARY_RELOAD
52607 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52609 #undef TARGET_CLASS_MAX_NREGS
52610 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52612 #undef TARGET_PREFERRED_RELOAD_CLASS
52613 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52614 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52615 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52616 #undef TARGET_CLASS_LIKELY_SPILLED_P
52617 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52619 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52620 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52621 ix86_builtin_vectorization_cost
52622 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52623 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52624 ix86_vectorize_vec_perm_const_ok
52625 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52626 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52627 ix86_preferred_simd_mode
52628 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52629 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52630 ix86_autovectorize_vector_sizes
52631 #undef TARGET_VECTORIZE_INIT_COST
52632 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52633 #undef TARGET_VECTORIZE_ADD_STMT_COST
52634 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52635 #undef TARGET_VECTORIZE_FINISH_COST
52636 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52637 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52638 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52640 #undef TARGET_SET_CURRENT_FUNCTION
52641 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52643 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52644 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52646 #undef TARGET_OPTION_SAVE
52647 #define TARGET_OPTION_SAVE ix86_function_specific_save
52649 #undef TARGET_OPTION_RESTORE
52650 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52652 #undef TARGET_OPTION_POST_STREAM_IN
52653 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52655 #undef TARGET_OPTION_PRINT
52656 #define TARGET_OPTION_PRINT ix86_function_specific_print
52658 #undef TARGET_OPTION_FUNCTION_VERSIONS
52659 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52661 #undef TARGET_CAN_INLINE_P
52662 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52664 #undef TARGET_EXPAND_TO_RTL_HOOK
52665 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52667 #undef TARGET_LEGITIMATE_ADDRESS_P
52668 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52670 #undef TARGET_LRA_P
52671 #define TARGET_LRA_P hook_bool_void_true
52673 #undef TARGET_REGISTER_PRIORITY
52674 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52676 #undef TARGET_REGISTER_USAGE_LEVELING_P
52677 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52679 #undef TARGET_LEGITIMATE_CONSTANT_P
52680 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52682 #undef TARGET_FRAME_POINTER_REQUIRED
52683 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52685 #undef TARGET_CAN_ELIMINATE
52686 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52688 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52689 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52691 #undef TARGET_ASM_CODE_END
52692 #define TARGET_ASM_CODE_END ix86_code_end
52694 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52695 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52697 #if TARGET_MACHO
52698 #undef TARGET_INIT_LIBFUNCS
52699 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52700 #endif
52702 #undef TARGET_LOOP_UNROLL_ADJUST
52703 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52705 #undef TARGET_SPILL_CLASS
52706 #define TARGET_SPILL_CLASS ix86_spill_class
52708 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52709 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52710 ix86_simd_clone_compute_vecsize_and_simdlen
52712 #undef TARGET_SIMD_CLONE_ADJUST
52713 #define TARGET_SIMD_CLONE_ADJUST \
52714 ix86_simd_clone_adjust
52716 #undef TARGET_SIMD_CLONE_USABLE
52717 #define TARGET_SIMD_CLONE_USABLE \
52718 ix86_simd_clone_usable
52720 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52721 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52722 ix86_float_exceptions_rounding_supported_p
52724 #undef TARGET_MODE_EMIT
52725 #define TARGET_MODE_EMIT ix86_emit_mode_set
52727 #undef TARGET_MODE_NEEDED
52728 #define TARGET_MODE_NEEDED ix86_mode_needed
52730 #undef TARGET_MODE_AFTER
52731 #define TARGET_MODE_AFTER ix86_mode_after
52733 #undef TARGET_MODE_ENTRY
52734 #define TARGET_MODE_ENTRY ix86_mode_entry
52736 #undef TARGET_MODE_EXIT
52737 #define TARGET_MODE_EXIT ix86_mode_exit
52739 #undef TARGET_MODE_PRIORITY
52740 #define TARGET_MODE_PRIORITY ix86_mode_priority
52742 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52743 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52745 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52746 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52748 #undef TARGET_STORE_BOUNDS_FOR_ARG
52749 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52751 #undef TARGET_LOAD_RETURNED_BOUNDS
52752 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52754 #undef TARGET_STORE_RETURNED_BOUNDS
52755 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52757 #undef TARGET_CHKP_BOUND_MODE
52758 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52760 #undef TARGET_BUILTIN_CHKP_FUNCTION
52761 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52763 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52764 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52766 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52767 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52769 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52770 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52772 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52773 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52775 #undef TARGET_OFFLOAD_OPTIONS
52776 #define TARGET_OFFLOAD_OPTIONS \
52777 ix86_offload_options
52779 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52780 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52783 \f