| blob | 863abd7a282b02183a18f4ab14eefa7b64a61b61 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* And similarly, for notes. */
309 /* Basic block in which we are performing combines. */
313 \f
314 /* Length of the currently allocated uid_insn_cost array. */
318 /* The following array records the insn_cost for every insn
319 in the instruction stream. */
323 /* The following array records the LOG_LINKS for every insn in the
324 instruction stream as struct insn_link pointers. */
330 };
336 {
340 }
342 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
343 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
345 #define FOR_EACH_LOG_LINK(L, INSN) \
346 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
348 /* Links for LOG_LINKS are allocated from this obstack. */
352 /* Allocate a link. */
356 {
364 }
366 /* Incremented for each basic block. */
370 /* Reset to label_tick for each extended basic block in scanning order. */
374 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
375 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
379 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
380 be safely used. It is zero while computing them and after combine has
381 completed. This former test prevents propagating values based on
382 previously set values, which can be incorrect if a variable is modified
383 in a loop. */
387 \f
388 /* Record one modification to rtl structure
389 to be undone by storing old_contents into *where. */
393 struct undo
394 {
399 };
401 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
402 num_undo says how many are currently recorded.
404 other_insn is nonzero if we have modified some other insn in the process
405 of working on subst_insn. It must be verified too. */
407 struct undobuf
408 {
412 };
416 /* Number of times the pseudo being substituted for
417 was found and replaced. */
422 scalar_int_mode,
425 scalar_int_mode,
498 \f
500 /* It is not safe to use ordinary gen_lowpart in combine.
501 See comments in gen_lowpart_for_combine. */
502 #undef RTL_HOOKS_GEN_LOWPART
503 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
505 /* Our implementation of gen_lowpart never emits a new pseudo. */
506 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
507 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
509 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
510 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
512 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
513 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
515 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
516 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
520 \f
521 /* Convenience wrapper for the canonicalize_comparison target hook.
522 Target hooks cannot use enum rtx_code. */
526 {
530 }
532 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
533 PATTERN can not be split. Otherwise, it returns an insn sequence.
534 This is a wrapper around split_insns which ensures that the
535 reg_stat vector is made larger if the splitter creates a new
536 register. */
540 {
549 }
551 /* This is used by find_single_use to locate an rtx in LOC that
552 contains exactly one use of DEST, which is typically either a REG
553 or CC0. It returns a pointer to the innermost rtx expression
554 containing DEST. Appearances of DEST that are being used to
555 totally replace it are not counted. */
559 {
568 {
572 CASE_CONST_ANY:
577 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
578 of a REG that occupies all of the REG, the insn uses DEST if
579 it is mentioned in the destination or the source. Otherwise, we
580 need just check the source. */
597 }
599 /* If it wasn't one of the common cases above, check each expression and
600 vector of this code. Look for a unique usage of DEST. */
604 {
606 {
611 else
617 /* Duplicate usage. */
619 }
621 {
625 {
631 else
638 }
639 }
640 }
643 }
646 /* See if DEST, produced in INSN, is used only a single time in the
647 sequel. If so, return a pointer to the innermost rtx expression in which
648 it is used.
650 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
652 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
653 care about REG_DEAD notes or LOG_LINKS.
655 Otherwise, we find the single use by finding an insn that has a
656 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
657 only referenced once in that insn, we know that it must be the first
658 and last insn referencing DEST. */
662 {
663 basic_block bb;
669 {
679 }
689 {
695 {
700 }
701 }
704 }
705 \f
706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
707 insn. The substitution can be undone by undo_all. If INTO is already
708 set to NEWVAL, do not record this change. Because computing NEWVAL might
709 also call SUBST, we have to compute it before we put anything into
710 the undo table. */
712 static void
714 {
721 /* We'd like to catch as many invalid transformations here as
722 possible. Unfortunately, there are way too many mode changes
723 that are perfectly valid, so we'd waste too much effort for
724 little gain doing the checks here. Focus on catching invalid
725 transformations involving integer constants. */
728 {
729 /* Sanity check that we're replacing oldval with a CONST_INT
730 that is a valid sign-extension for the original mode. */
734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
735 CONST_INT is not valid, because after the replacement, the
736 original mode would be gone. Unfortunately, we can't tell
737 when do_SUBST is called to replace the operand thereof, so we
738 perform this test on oldval instead, checking whether an
739 invalid replacement took place before we got here. */
744 }
748 else
757 }
759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
762 for the value of a HOST_WIDE_INT value (including CONST_INT) is
763 not safe. */
765 static void
767 {
776 else
785 }
787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
789 /* Similar to SUBST, but just substitute the mode. This is used when
790 changing the mode of a pseudo-register, so that any other
791 references to the entry in the regno_reg_rtx array will change as
792 well. */
794 static void
796 {
805 else
814 }
816 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
818 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 static void
822 {
831 else
840 }
842 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 \f
844 /* Subroutine of try_combine. Determine whether the replacement patterns
845 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
846 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
847 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
848 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
849 of all the instructions can be estimated and the replacements are more
850 expensive than the original sequence. */
852 static bool
855 {
860 /* Lookup the original insn_costs. */
865 {
868 {
872 }
873 else
874 {
878 }
879 }
880 else
881 {
884 }
886 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 correct that. */
892 /* Calculate the replacement insn_costs. */
901 {
911 }
912 else
913 {
916 }
919 {
928 optimize_this_for_speed_p);
932 {
935 }
936 else
938 }
940 /* Disallow this combination if both new_cost and old_cost are greater than
941 zero, and new_cost is greater than old cost. */
945 {
964 else
966 }
971 /* Update the uid_insn_cost array with the replacement costs. */
975 {
979 }
982 }
985 /* Delete any insns that copy a register to itself. */
987 static void
989 {
991 basic_block bb;
994 {
996 {
999 {
1004 }
1005 }
1006 }
1007 }
1009 \f
1010 /* Return false if we do not want to (or cannot) combine DEF. */
1011 static bool
1013 {
1014 /* Do not consider if it is pre/post modification in MEM. */
1020 /* Do not combine frame pointer adjustments. */
1023 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1031 }
1033 /* Return false if we do not want to (or cannot) combine USE. */
1034 static bool
1036 {
1037 /* Do not consider the usage of the stack pointer by function call. */
1042 }
1044 /* Fill in log links field for all insns. */
1046 static void
1048 {
1049 basic_block bb;
1056 /* Pass through each block from the end, recording the uses of each
1057 register and establishing log links when def is encountered.
1058 Note that we do not clear next_use array in order to save time,
1059 so we have to test whether the use is in the same basic block as def.
1061 There are a few cases below when we do not consider the definition or
1062 usage -- these are taken from original flow.c did. Don't ask me why it is
1063 done this way; I don't know and if it works, I don't want to know. */
1066 {
1068 {
1072 /* Log links are created only once. */
1076 {
1092 /* flow.c claimed:
1094 We don't build a LOG_LINK for hard registers contained
1095 in ASM_OPERANDs. If these registers get replaced,
1096 we might wind up changing the semantics of the insn,
1097 even if reload can make what appear to be valid
1098 assignments later. */
1103 /* Don't add duplicate links between instructions. */
1112 }
1117 }
1118 }
1121 }
1123 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1124 true if we found a LOG_LINK that proves that A feeds B. This only works
1125 if there are no instructions between A and B which could have a link
1126 depending on A, since in that case we would not record a link for B.
1127 We also check the implicit dependency created by a cc0 setter/user
1128 pair. */
1130 static bool
1132 {
1140 }
1141 \f
1142 /* Main entry point for combiner. F is the first insn of the function.
1143 NREGS is the first unused pseudo-reg number.
1145 Return nonzero if the combiner has turned an indirect jump
1146 instruction into a direct jump. */
1147 static int
1149 {
1154 basic_block last_bb;
1174 /* Allocate array for insn info. */
1182 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1183 problems when, for example, we have j <<= 1 in a loop. */
1188 /* Scan all SETs and see if we can deduce anything about what
1189 bits are known to be zero for some registers and how many copies
1190 of the sign bit are known to exist for those registers.
1192 Also set any known values so that we can use it while searching
1193 for what bits are known to be set. */
1196 /* Allow the entry block and the first block to fall into the same EBB.
1197 Conceptually the incoming promotions are assigned to the entry block. */
1202 {
1207 label_tick++;
1215 {
1216 rtx links;
1222 insn);
1229 insn);
1231 /* Record the current insn_cost of this instruction. */
1235 {
1238 }
1239 }
1240 }
1244 /* Now scan all the insns in forward order. */
1252 {
1255 /* Ignore instruction combination in basic blocks that are going to
1256 be removed as unreachable anyway. See PR82386. */
1264 label_tick++;
1274 {
1288 /* See if we know about function return values before this
1289 insn based upon SUBREG flags. */
1292 /* See if we can find hardregs and subreg of pseudos in
1293 narrower modes. This could help turning TRUNCATEs
1294 into SUBREGs. */
1297 /* Try this insn with each insn it links back to. */
1303 {
1306 }
1308 /* Try each sequence of three linked insns ending with this one. */
1312 {
1315 /* If the linked insn has been replaced by a note, then there
1316 is no point in pursuing this chain any further. */
1324 {
1327 }
1328 }
1330 /* Try to combine a jump insn that uses CC0
1331 with a preceding insn that sets CC0, and maybe with its
1332 logical predecessor as well.
1333 This is how we make decrement-and-branch insns.
1334 We need this special code because data flow connections
1335 via CC0 do not get entered in LOG_LINKS. */
1342 {
1353 }
1355 /* Do the same for an insn that explicitly references CC0. */
1362 {
1373 }
1375 /* Finally, see if any of the insns that this insn links to
1376 explicitly references CC0. If so, try this insn, that insn,
1377 and its predecessor if it sets CC0. */
1379 {
1391 }
1393 /* Try combining an insn with two different insns whose results it
1394 uses. */
1404 {
1407 }
1409 /* Try four-instruction combinations. */
1412 {
1416 /* If the linked insn has been replaced by a note, then there
1417 is no point in pursuing this chain any further. */
1422 {
1426 /* I0 -> I1 -> I2 -> I3. */
1432 {
1435 }
1436 /* I0, I1 -> I2, I2 -> I3. */
1443 {
1446 }
1447 }
1450 {
1454 /* I0 -> I2; I1, I2 -> I3. */
1460 {
1463 }
1464 /* I0 -> I1; I1, I2 -> I3. */
1470 {
1473 }
1474 }
1475 }
1477 /* Try this insn with each REG_EQUAL note it links back to. */
1479 {
1485 /* Avoid using a register that may already been marked
1486 dead by an earlier instruction. */
1494 {
1495 /* Temporarily replace the set's source with the
1496 contents of the REG_EQUAL note. The insn will
1497 be deleted or recognized by try_combine. */
1508 last_combined_insn);
1511 {
1514 }
1517 }
1518 }
1523 retry:
1524 ;
1525 }
1526 }
1533 /* Clean up. */
1539 {
1542 {
1545 }
1547 }
1557 /* Make recognizer allow volatile MEMs again. */
1561 }
1563 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1565 static void
1567 {
1573 }
1574 \f
1575 /* Set up any promoted values for incoming argument registers. */
1577 static void
1579 {
1580 tree arg;
1585 {
1590 /* Only continue if the incoming argument is in a register. */
1594 /* Determine, if possible, whether all call sites of the current
1595 function lie within the current compilation unit. (This does
1596 take into account the exporting of a function via taking its
1597 address, and so forth.) */
1600 /* The mode and signedness of the argument before any promotions happen
1601 (equal to the mode of the pseudo holding it at that stage). */
1605 /* The mode and signedness of the argument after any source language and
1606 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1610 /* The mode and signedness of the argument as it is actually passed,
1611 see assign_parm_setup_reg in function.c. */
1615 /* The mode of the register in which the argument is being passed. */
1618 /* Eliminate sign extensions in the callee when:
1619 (a) A mode promotion has occurred; */
1622 /* (b) The mode of the register is the same as the mode of
1623 the argument as it is passed; */
1626 /* (c) There's no language level extension; */
1628 ;
1629 /* (c.1) All callers are from the current compilation unit. If that's
1630 the case we don't have to rely on an ABI, we only have to know
1631 what we're generating right now, and we know that we will do the
1632 mode1 to mode2 promotion with the given sign. */
1635 /* (c.2) The combination of the two promotions is useful. This is
1636 true when the signs match, or if the first promotion is unsigned.
1637 In the later case, (sign_extend (zero_extend x)) is the same as
1638 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1644 /* Record that the value was promoted from mode1 to mode3,
1645 so that any sign extension at the head of the current
1646 function may be eliminated. */
1650 }
1651 }
1653 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1654 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1655 because some machines (maybe most) will actually do the sign-extension and
1656 this is the conservative approach.
1658 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1659 kludge. */
1661 static rtx
1663 {
1664 scalar_int_mode int_mode;
1673 }
1675 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1676 and SET. */
1678 static void
1680 rtx x)
1681 {
1691 {
1695 }
1697 /* Don't call nonzero_bits if it cannot change anything. */
1699 {
1704 }
1706 /* Don't call num_sign_bit_copies if it cannot change anything. */
1708 {
1711 {
1715 }
1718 }
1719 }
1721 /* Called via note_stores. If X is a pseudo that is narrower than
1722 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1724 If we are setting only a portion of X and we can't figure out what
1725 portion, assume all bits will be used since we don't know what will
1726 be happening.
1728 Similarly, set how many bits of X are known to be copies of the sign bit
1729 at all locations in the function. This is the smallest number implied
1730 by any set of X. */
1732 static void
1734 {
1736 scalar_int_mode mode;
1740 /* If this register is undefined at the start of the file, we can't
1741 say what its contents were. */
1742 && ! REGNO_REG_SET_P
1746 {
1750 {
1754 }
1756 /* If this register is being initialized using itself, and the
1757 register is uninitialized in this basic block, and there are
1758 no LOG_LINKS which set the register, then part of the
1759 register is uninitialized. In that case we can't assume
1760 anything about the number of nonzero bits.
1762 ??? We could do better if we checked this in
1763 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1764 could avoid making assumptions about the insn which initially
1765 sets the register, while still using the information in other
1766 insns. We would have to be careful to check every insn
1767 involved in the combination. */
1773 {
1780 {
1784 }
1785 }
1787 /* If this is a complex assignment, see if we can convert it into a
1788 simple assignment. */
1791 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1792 set what we know about X. */
1798 else
1799 {
1802 }
1803 }
1804 }
1805 \f
1806 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1807 optionally insns that were previously combined into I3 or that will be
1808 combined into the merger of INSN and I3. The order is PRED, PRED2,
1809 INSN, SUCC, SUCC2, I3.
1811 Return 0 if the combination is not allowed for any reason.
1813 If the combination is allowed, *PDEST will be set to the single
1814 destination of INSN and *PSRC to the single source, and this function
1815 will return 1. */
1817 static int
1821 {
1826 rtx link;
1831 {
1833 {
1838 }
1843 }
1847 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1848 or a PARALLEL consisting of such a SET and CLOBBERs.
1850 If INSN has CLOBBER parallel parts, ignore them for our processing.
1851 By definition, these happen during the execution of the insn. When it
1852 is merged with another insn, all bets are off. If they are, in fact,
1853 needed and aren't also supplied in I3, they may be added by
1854 recog_for_combine. Otherwise, it won't match.
1856 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1857 note.
1859 Get the source and destination of INSN. If more than one, can't
1860 combine. */
1866 {
1868 {
1872 {
1873 /* This is important to combine floating point insns
1874 for the SH4 port. */
1876 /* Combining an isolated USE doesn't make sense.
1877 We depend here on combinable_i3pat to reject them. */
1878 /* The code below this loop only verifies that the inputs of
1879 the SET in INSN do not change. We call reg_set_between_p
1880 to verify that the REG in the USE does not change between
1881 I3 and INSN.
1882 If the USE in INSN was for a pseudo register, the matching
1883 insn pattern will likely match any register; combining this
1884 with any other USE would only be safe if we knew that the
1885 used registers have identical values, or if there was
1886 something to tell them apart, e.g. different modes. For
1887 now, we forgo such complicated tests and simply disallow
1888 combining of USES of pseudo registers with any other USE. */
1891 {
1896 do
1897 {
1907 }
1909 }
1912 /* We can ignore CLOBBERs. */
1917 /* Ignore SETs whose result isn't used but not those that
1918 have side-effects. */
1924 /* If we have already found a SET, this is a second one and
1925 so we cannot combine with this insn. */
1933 /* Anything else means we can't combine. */
1935 }
1936 }
1939 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1940 so don't do anything with it. */
1943 }
1944 else
1950 /* The simplification in expand_field_assignment may call back to
1951 get_last_value, so set safe guard here. */
1957 /* Do not eliminate user-specified register if it is in an
1958 asm input because we may break the register asm usage defined
1959 in GCC manual if allow to do so.
1960 Be aware that this may cover more cases than we expect but this
1961 should be harmless. */
1966 /* Don't eliminate a store in the stack pointer. */
1968 /* Don't combine with an insn that sets a register to itself if it has
1969 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1971 /* Can't merge an ASM_OPERANDS. */
1973 /* Can't merge a function call. */
1975 /* Don't eliminate a function call argument. */
1981 /* Don't substitute into an incremented register. */
1985 /* Don't substitute into a non-local goto, this confuses CFG. */
1987 /* Make sure that DEST is not used after INSN but before SUCC, or
1988 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1989 || (!all_adjacent
1990 && ((succ2
1994 || (succ
1995 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1996 that case SUCC is not in the insn stream, so use SUCC2
1997 instead for this test. */
1999 succ2
2002 /* Make sure that the value that is to be substituted for the register
2003 does not use any registers whose values alter in between. However,
2004 If the insns are adjacent, a use can't cross a set even though we
2005 think it might (this can happen for a sequence of insns each setting
2006 the same destination; last_set of that register might point to
2007 a NOTE). If INSN has a REG_EQUIV note, the register is always
2008 equivalent to the memory so the substitution is valid even if there
2009 are intervening stores. Also, don't move a volatile asm or
2010 UNSPEC_VOLATILE across any other insns. */
2011 || (! all_adjacent
2017 /* Don't combine across a CALL_INSN, because that would possibly
2018 change whether the life span of some REGs crosses calls or not,
2019 and it is a pain to update that information.
2020 Exception: if source is a constant, moving it later can't hurt.
2021 Accept that as a special case. */
2025 /* DEST must either be a REG or CC0. */
2027 {
2028 /* If register alignment is being enforced for multi-word items in all
2029 cases except for parameters, it is possible to have a register copy
2030 insn referencing a hard register that is not allowed to contain the
2031 mode being copied and which would not be valid as an operand of most
2032 insns. Eliminate this problem by not combining with such an insn.
2034 Also, on some machines we don't want to extend the life of a hard
2035 register. */
2040 /* Don't extend the life of a hard register unless it is
2041 user variable (if we have few registers) or it can't
2042 fit into the desired register (meaning something special
2043 is going on).
2044 Also avoid substituting a return register into I3, because
2045 reload can't handle a conflict with constraints of other
2046 inputs. */
2051 }
2059 {
2062 /* If the clobber represents an earlyclobber operand, we must not
2063 substitute an expression containing the clobbered register.
2064 As we do not analyze the constraint strings here, we have to
2065 make the conservative assumption. However, if the register is
2066 a fixed hard reg, the clobber cannot represent any operand;
2067 we leave it up to the machine description to either accept or
2068 reject use-and-clobber patterns. */
2074 }
2076 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2077 or not), reject, unless nothing volatile comes between it and I3 */
2080 {
2081 /* Make sure neither succ nor succ2 contains a volatile reference. */
2086 /* We'll check insns between INSN and I3 below. */
2087 }
2089 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2090 to be an explicit register variable, and was chosen for a reason. */
2096 /* If INSN contains volatile references (specifically volatile MEMs),
2097 we cannot combine across any other volatile references.
2098 Even if INSN doesn't contain volatile references, any intervening
2099 volatile insn might affect machine state. */
2102 ? volatile_refs_p
2109 /* If INSN contains an autoincrement or autodecrement, make sure that
2110 register is not used between there and I3, and not already used in
2111 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2112 Also insist that I3 not be a jump; if it were one
2113 and the incremented register were spilled, we would lose. */
2131 /* Don't combine an insn that follows a CC0-setting insn.
2132 An insn that uses CC0 must not be separated from the one that sets it.
2133 We do, however, allow I2 to follow a CC0-setting insn if that insn
2134 is passed as I1; in that case it will be deleted also.
2135 We also allow combining in this case if all the insns are adjacent
2136 because that would leave the two CC0 insns adjacent as well.
2137 It would be more logical to test whether CC0 occurs inside I1 or I2,
2138 but that would be much slower, and this ought to be equivalent. */
2141 {
2146 }
2148 /* If we get here, we have passed all the tests and the combination is
2149 to be allowed. */
2155 }
2156 \f
2157 /* LOC is the location within I3 that contains its pattern or the component
2158 of a PARALLEL of the pattern. We validate that it is valid for combining.
2160 One problem is if I3 modifies its output, as opposed to replacing it
2161 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2162 doing so would produce an insn that is not equivalent to the original insns.
2164 Consider:
2166 (set (reg:DI 101) (reg:DI 100))
2167 (set (subreg:SI (reg:DI 101) 0) <foo>)
2169 This is NOT equivalent to:
2171 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2172 (set (reg:DI 101) (reg:DI 100))])
2174 Not only does this modify 100 (in which case it might still be valid
2175 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2177 We can also run into a problem if I2 sets a register that I1
2178 uses and I1 gets directly substituted into I3 (not via I2). In that
2179 case, we would be getting the wrong value of I2DEST into I3, so we
2180 must reject the combination. This case occurs when I2 and I1 both
2181 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2182 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2183 of a SET must prevent combination from occurring. The same situation
2184 can occur for I0, in which case I0_NOT_IN_SRC is set.
2186 Before doing the above check, we first try to expand a field assignment
2187 into a set of logical operations.
2189 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2190 we place a register that is both set and used within I3. If more than one
2191 such register is detected, we fail.
2193 Return 1 if the combination is valid, zero otherwise. */
2195 static int
2198 {
2202 {
2207 rtx subdest;
2214 /* Check for the case where I3 modifies its output, as discussed
2215 above. We don't want to prevent pseudos from being combined
2216 into the address of a MEM, so only prevent the combination if
2217 i1 or i2 set the same MEM. */
2227 /* This is the same test done in can_combine_p except we can't test
2228 all_adjacent; we don't have to, since this instruction will stay
2229 in place, thus we are not considering increasing the lifetime of
2230 INNER_DEST.
2232 Also, if this insn sets a function argument, combining it with
2233 something that might need a spill could clobber a previous
2234 function argument; the all_adjacent test in can_combine_p also
2235 checks this; here, we do a more specific test for this case. */
2245 /* If DEST is used in I3, it is being killed in this insn, so
2246 record that for later. We have to consider paradoxical
2247 subregs here, since they kill the whole register, but we
2248 ignore partial subregs, STRICT_LOW_PART, etc.
2249 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2250 STACK_POINTER_REGNUM, since these are always considered to be
2251 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2259 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2265 {
2270 }
2271 }
2274 {
2281 }
2284 }
2285 \f
2286 /* Return 1 if X is an arithmetic expression that contains a multiplication
2287 and division. We don't count multiplications by powers of two here. */
2289 static int
2291 {
2293 {
2309 }
2310 }
2311 \f
2312 /* Determine whether INSN can be used in a combination. Return nonzero if
2313 not. This is used in try_combine to detect early some cases where we
2314 can't perform combinations. */
2316 static int
2318 {
2319 rtx set;
2322 /* If this isn't really an insn, we can't do anything.
2323 This can occur when flow deletes an insn that it has merged into an
2324 auto-increment address. */
2328 /* Never combine loads and stores involving hard regs that are likely
2329 to be spilled. The register allocator can usually handle such
2330 reg-reg moves by tying. If we allow the combiner to make
2331 substitutions of likely-spilled regs, reload might die.
2332 As an exception, we allow combinations involving fixed regs; these are
2333 not available to the register allocator so there's no risk involved. */
2354 }
2356 struct likely_spilled_retval_info
2357 {
2360 };
2362 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2363 hard registers that are known to be written to / clobbered in full. */
2364 static void
2366 {
2383 else
2386 }
2388 /* Return nonzero iff part of the return value is live during INSN, and
2389 it is likely spilled. This can happen when more than one insn is needed
2390 to copy the return value, e.g. when we consider to combine into the
2391 second copy insn for a complex value. */
2393 static int
2395 {
2397 rtx reg;
2400 /* We assume here that no machine mode needs more than
2401 32 hard registers when the value overlaps with a register
2402 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2417 /* Disregard parts of the return value that are set later. */
2426 /* Check if any of the (probably) live return value registers is
2427 likely spilled. */
2428 nregs --;
2429 do
2430 {
2436 }
2438 /* Adjust INSN after we made a change to its destination.
2440 Changing the destination can invalidate notes that say something about
2441 the results of the insn and a LOG_LINK pointing to the insn. */
2443 static void
2445 {
2446 /* For notes, be conservative and simply remove them. */
2449 /* The new insn will have a destination that was previously the destination
2450 of an insn just above it. Call distribute_links to make a LOG_LINK from
2451 the next use of that destination. */
2467 }
2469 /* Return TRUE if combine can reuse reg X in mode MODE.
2470 ADDED_SETS is nonzero if the original set is still required. */
2471 static bool
2473 {
2479 /* Don't change between modes with different underlying register sizes,
2480 since this could lead to invalid subregs. */
2486 /* Allow hard registers if the new mode is legal, and occupies no more
2487 registers than the old mode. */
2492 /* Or a pseudo that is only used once. */
2495 && !added_sets
2497 }
2500 /* Check whether X, the destination of a set, refers to part of
2501 the register specified by REG. */
2503 static bool
2505 {
2506 /* Check that reg is an integer mode register. */
2517 }
2519 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2520 Note that the INSN should be deleted *after* removing dead edges, so
2521 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2522 but not for a (set (pc) (label_ref FOO)). */
2524 static void
2526 {
2534 {
2539 /* Remove barriers from the footer if there are any. */
2542 {
2545 else
2549 }
2552 }
2553 }
2555 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2556 by an arbitrary number of CLOBBERs. */
2557 static bool
2559 {
2578 }
2580 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2581 CLOBBERs), can be split into individual SETs in that order, without
2582 changing semantics. */
2583 static bool
2585 {
2593 {
2602 }
2605 }
2607 /* Try to combine the insns I0, I1 and I2 into I3.
2608 Here I0, I1 and I2 appear earlier than I3.
2609 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2610 I3.
2612 If we are combining more than two insns and the resulting insn is not
2613 recognized, try splitting it into two insns. If that happens, I2 and I3
2614 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2615 Otherwise, I0, I1 and I2 are pseudo-deleted.
2617 Return 0 if the combination does not work. Then nothing is changed.
2618 If we did the combination, return the insn at which combine should
2619 resume scanning.
2621 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2622 new direct jump instruction.
2624 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2625 been I3 passed to an earlier try_combine within the same basic
2626 block. */
2631 {
2632 /* New patterns for I3 and I2, respectively. */
2636 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2637 dead. */
2639 /* Total number of SETs to put into I3. */
2641 /* Nonzero if I2's or I1's body now appears in I3. */
2643 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2645 /* Contains I3 if the destination of I3 is used in its source, which means
2646 that the old life of I3 is being killed. If that usage is placed into
2647 I2 and not in I3, a REG_DEAD note must be made. */
2649 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2651 /* Copy of SET_SRC of I1 and I0, if needed. */
2653 /* Set if I2DEST was reused as a scratch register. */
2655 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2657 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2662 /* Notes that must be added to REG_NOTES in I3 and I2. */
2664 /* Notes that we substituted I3 into I2 instead of the normal case. */
2666 /* Notes that I1, I2 or I3 is a MULT operation. */
2673 rtx temp_expr;
2676 rtx new_other_notes;
2680 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2681 never be). */
2685 /* Only try four-insn combinations when there's high likelihood of
2686 success. Look for simple insns, such as loads of constants or
2687 binary operations involving a constant. */
2689 {
2699 {
2702 rtx src;
2707 {
2710 }
2712 ngood++;
2715 nshift++;
2716 }
2718 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2719 are likely manipulating its value. Ideally we'll be able to combine
2720 all four insns into a bitfield insertion of some kind.
2722 Note the source in I0 might be inside a sign/zero extension and the
2723 memory modes in I0 and I3 might be different. So extract the address
2724 from the destination of I3 and search for it in the source of I0.
2726 In the event that there's a match but the source/dest do not actually
2727 refer to the same memory, the worst that happens is we try some
2728 combinations that we wouldn't have otherwise. */
2730 /* Ensure the source of SET0 is a MEM, possibly buried inside
2731 an extension. */
2737 /* Ensure the destination of SET3 is a MEM. */
2739 /* Would it be better to extract the base address for the MEM
2740 in SET3 and look for that? I don't have cases where it matters
2741 but I could envision such cases. */
2747 }
2749 /* Exit early if one of the insns involved can't be used for
2750 combinations. */
2761 combine_attempts++;
2764 /* Reset the hard register usage information. */
2768 {
2775 else
2785 }
2787 /* If multiple insns feed into one of I2 or I3, they can be in any
2788 order. To simplify the code below, reorder them in sequence. */
2799 /* First check for one important special case that the code below will
2800 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2801 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2802 we may be able to replace that destination with the destination of I3.
2803 This occurs in the common code where we compute both a quotient and
2804 remainder into a structure, in which case we want to do the computation
2805 directly into the structure to avoid register-register copies.
2807 Note that this case handles both multiple sets in I2 and also cases
2808 where I2 has a number of CLOBBERs inside the PARALLEL.
2810 We make very conservative checks below and only try to handle the
2811 most common cases of this. For example, we only handle the case
2812 where I2 and I3 are adjacent to avoid making difficult register
2813 usage tests. */
2821 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2822 below would need to check what is inside (and reg_overlap_mentioned_p
2823 doesn't support those codes anyway). Don't allow those destinations;
2824 the resulting insn isn't likely to be recognized anyway. */
2830 {
2833 /* Make sure that the destination of I3,
2834 which we are going to substitute into one output of I2,
2835 is not used within another output of I2. We must avoid making this:
2836 (parallel [(set (mem (reg 69)) ...)
2837 (set (reg 69) ...)])
2838 which is not well-defined as to order of actions.
2839 (Besides, reload can't handle output reloads for this.)
2841 The problem can also happen if the dest of I3 is a memory ref,
2842 if another dest in I2 is an indirect memory ref.
2844 Neither can this PARALLEL be an asm. We do not allow combining
2845 that usually (see can_combine_p), so do not here either. */
2848 {
2857 }
2863 {
2864 combine_merges++;
2874 /* Replace the dest in I2 with our dest and make the resulting
2875 insn the new pattern for I3. Then skip to where we validate
2876 the pattern. Everything was set up above. */
2881 }
2882 }
2884 /* If I2 is setting a pseudo to a constant and I3 is setting some
2885 sub-part of it to another constant, merge them by making a new
2886 constant. */
2894 {
2901 {
2906 {
2912 }
2913 }
2914 else
2915 {
2919 {
2922 }
2923 }
2926 {
2927 /* If this is the low part, we're done. */
2929 ;
2930 /* Handle the case where inner is twice the size of outer. */
2934 /* Otherwise give up for now. */
2935 else
2937 }
2940 {
2948 combine_merges++;
2955 /* Replace the source in I2 with the new constant and make the
2956 resulting insn the new pattern for I3. Then skip to where we
2957 validate the pattern. Everything was set up above. */
2963 /* The dest of I3 has been replaced with the dest of I2. */
2966 }
2967 }
2969 /* If we have no I1 and I2 looks like:
2970 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2971 (set Y OP)])
2972 make up a dummy I1 that is
2973 (set Y OP)
2974 and change I2 to be
2975 (set (reg:CC X) (compare:CC Y (const_int 0)))
2977 (We can ignore any trailing CLOBBERs.)
2979 This undoes a previous combination and allows us to match a branch-and-
2980 decrement insn. */
2992 {
2993 /* We make I1 with the same INSN_UID as I2. This gives it
2994 the same DF_INSN_LUID for value tracking. Our fake I1 will
2995 never appear in the insn stream so giving it the same INSN_UID
2996 as I2 will not cause a problem. */
3009 }
3011 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3012 make those two SETs separate I1 and I2 insns, and make an I0 that is
3013 the original I1. */
3021 {
3022 /* If there is no I1, there is no I0 either. */
3025 /* We make I1 with the same INSN_UID as I2. This gives it
3026 the same DF_INSN_LUID for value tracking. Our fake I1 will
3027 never appear in the insn stream so giving it the same INSN_UID
3028 as I2 will not cause a problem. */
3036 }
3038 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3040 {
3045 }
3047 {
3052 }
3054 {
3059 }
3061 /* Record whether I2DEST is used in I2SRC and similarly for the other
3062 cases. Knowing this will help in register status updating below. */
3073 /* For the earlier insns, determine which of the subsequent ones they
3074 feed. */
3081 /* Ensure that I3's pattern can be the destination of combines. */
3087 {
3090 }
3092 /* See if any of the insns is a MULT operation. Unless one is, we will
3093 reject a combination that is, since it must be slower. Be conservative
3094 here. */
3102 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3103 We used to do this EXCEPT in one case: I3 has a post-inc in an
3104 output operand. However, that exception can give rise to insns like
3105 mov r3,(r3)+
3106 which is a famous insn on the PDP-11 where the value of r3 used as the
3107 source was model-dependent. Avoid this sort of thing. */
3109 #if 0
3115 /* It's not the exception. */
3116 #endif
3118 {
3119 rtx link;
3125 {
3128 }
3129 }
3131 /* See if the SETs in I1 or I2 need to be kept around in the merged
3132 instruction: whenever the value set there is still needed past I3.
3133 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3135 For the SET in I1, we have two cases: if I1 and I2 independently feed
3136 into I3, the set in I1 needs to be kept around unless I1DEST dies
3137 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3138 in I1 needs to be kept around unless I1DEST dies or is set in either
3139 I2 or I3. The same considerations apply to I0. */
3146 else
3154 else
3157 /* We are about to copy insns for the case where they need to be kept
3158 around. Check that they can be copied in the merged instruction. */
3164 {
3167 }
3169 /* If the set in I2 needs to be kept around, we must make a copy of
3170 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3171 PATTERN (I2), we are only substituting for the original I1DEST, not into
3172 an already-substituted copy. This also prevents making self-referential
3173 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3174 I2DEST. */
3177 {
3180 else
3182 }
3185 {
3188 else
3190 }
3193 {
3196 else
3198 }
3200 combine_merges++;
3202 /* Substitute in the latest insn for the regs set by the earlier ones. */
3208 /* Many machines that don't use CC0 have insns that can both perform an
3209 arithmetic operation and set the condition code. These operations will
3210 be represented as a PARALLEL with the first element of the vector
3211 being a COMPARE of an arithmetic operation with the constant zero.
3212 The second element of the vector will set some pseudo to the result
3213 of the same arithmetic operation. If we simplify the COMPARE, we won't
3214 match such a pattern and so will generate an extra insn. Here we test
3215 for this case, where both the comparison and the operation result are
3216 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3217 I2SRC. Later we will make the PARALLEL that contains I2. */
3223 {
3224 rtx newpat_dest;
3230 scalar_int_mode mode;
3239 {
3245 }
3247 /* Do the rest only if op1 is const0_rtx, which may be the
3248 result of simplification. */
3250 {
3251 /* If a single use of the CC is found, prepare to modify it
3252 when SELECT_CC_MODE returns a new CC-class mode, or when
3253 the above simplify_compare_const() returned a new comparison
3254 operator. undobuf.other_insn is assigned the CC use insn
3255 when modifying it. */
3257 {
3258 #ifdef SELECT_CC_MODE
3259 machine_mode new_mode
3264 {
3269 else
3270 {
3273 }
3274 }
3275 #endif
3276 /* Cases for modifying the CC-using comparison. */
3278 /* ??? Do we need to verify the zero rtx? */
3280 {
3281 /* Replace cc_use_loc with entire new RTX. */
3286 }
3288 {
3289 /* Just replace the CC reg with a new mode. */
3292 }
3293 }
3295 /* Now we modify the current newpat:
3296 First, SET_DEST(newpat) is updated if the CC mode has been
3297 altered. For targets without SELECT_CC_MODE, this should be
3298 optimized away. */
3301 /* This is always done to propagate i2src into newpat. */
3304 /* Create new version of i2pat if needed; the below PARALLEL
3305 creation needs this to work correctly. */
3309 }
3310 }
3313 {
3314 /* It is possible that the source of I2 or I1 may be performing
3315 an unneeded operation, such as a ZERO_EXTEND of something
3316 that is known to have the high part zero. Handle that case
3317 by letting subst look at the inner insns.
3319 Another way to do this would be to have a function that tries
3320 to simplify a single insn instead of merging two or more
3321 insns. We don't do this because of the potential of infinite
3322 loops and because of the potential extra memory required.
3323 However, doing it the way we are is a bit of a kludge and
3324 doesn't catch all cases.
3326 But only do this if -fexpensive-optimizations since it slows
3327 things down and doesn't usually win.
3329 This is not done in the COMPARE case above because the
3330 unmodified I2PAT is used in the PARALLEL and so a pattern
3331 with a modified I2SRC would not match. */
3334 {
3335 /* Pass pc_rtx so no substitutions are done, just
3336 simplifications. */
3338 {
3341 }
3345 }
3350 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3351 copy of I2SRC each time we substitute it, in order to avoid creating
3352 self-referential RTL when we will be substituting I1SRC for I1DEST
3353 later. Likewise if I0 feeds into I2, either directly or indirectly
3354 through I1, and I0DEST is in I0SRC. */
3361 /* Record whether I2's body now appears within I3's body. */
3363 }
3365 /* If we already got a failure, don't try to do more. Otherwise, try to
3366 substitute I1 if we have it. */
3369 {
3370 /* Check that an autoincrement side-effect on I1 has not been lost.
3371 This happens if I1DEST is mentioned in I2 and dies there, and
3372 has disappeared from the new pattern. */
3374 && i1_feeds_i2_n
3377 /* Before we can do this substitution, we must redo the test done
3378 above (see detailed comments there) that ensures I1DEST isn't
3379 mentioned in any SETs in NEWPAT that are field assignments. */
3382 {
3385 }
3390 /* If the following substitution will modify I1SRC, make a copy of it
3391 for the case where it is substituted for I1DEST in I2PAT later. */
3395 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3396 copy of I1SRC each time we substitute it, in order to avoid creating
3397 self-referential RTL when we will be substituting I0SRC for I0DEST
3398 later. */
3403 /* Record whether I1's body now appears within I3's body. */
3405 }
3407 /* Likewise for I0 if we have it. */
3410 {
3417 {
3420 }
3422 /* If the following substitution will modify I0SRC, make a copy of it
3423 for the case where it is substituted for I0DEST in I1PAT later. */
3426 /* And a copy for I0DEST in I2PAT substitution. */
3435 }
3437 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3438 to count all the ways that I2SRC and I1SRC can be used. */
3449 /* Fail if we tried to make a new register. */
3451 /* Fail if we couldn't do something and have a CLOBBER. */
3453 /* Fail if this new pattern is a MULT and we didn't have one before
3454 at the outer level. */
3457 {
3460 }
3462 /* If the actions of the earlier insns must be kept
3463 in addition to substituting them into the latest one,
3464 we must make a new PARALLEL for the latest insn
3465 to hold additional the SETs. */
3468 {
3470 combine_extras++;
3473 {
3479 }
3480 else
3481 {
3486 }
3492 {
3498 }
3500 {
3509 }
3510 }
3512 validate_replacement:
3514 /* Note which hard regs this insn has as inputs. */
3517 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3518 consider splitting this pattern, we might need these clobbers. */
3521 {
3527 }
3529 /* We have recognized nothing yet. */
3532 /* See if this is a PARALLEL of two SETs where one SET's destination is
3533 a register that is unused and this isn't marked as an instruction that
3534 might trap in an EH region. In that case, we just need the other SET.
3535 We prefer this over the PARALLEL.
3537 This can occur when simplifying a divmod insn. We *must* test for this
3538 case here because the code below that splits two independent SETs doesn't
3539 handle this case correctly when it updates the register status.
3541 It's pointless doing this if we originally had two sets, one from
3542 i3, and one from i2. Combining then splitting the parallel results
3543 in the original i2 again plus an invalid insn (which we delete).
3544 The net effect is only to move instructions around, which makes
3545 debug info less accurate.
3547 If the remaining SET came from I2 its destination should not be used
3548 between I2 and I3. See PR82024. */
3553 {
3564 {
3567 }
3576 {
3581 {
3587 }
3588 }
3592 }
3594 /* Is the result of combination a valid instruction? */
3598 /* If we were combining three insns and the result is a simple SET
3599 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3600 insns. There are two ways to do this. It can be split using a
3601 machine-specific method (like when you have an addition of a large
3602 constant) or by combine in the function find_split_point. */
3606 {
3610 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3611 use I2DEST as a scratch register will help. In the latter case,
3612 convert I2DEST to the mode of the source of NEWPAT if we can. */
3616 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3617 inputs of NEWPAT. */
3619 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3620 possible to try that as a scratch reg. This would require adding
3621 more code to make it work though. */
3624 {
3627 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3628 (temporarily, until we are committed to this instruction
3629 combination) does not work: for example, any call to nonzero_bits
3630 on the register (from a splitter in the MD file, for example)
3631 will get the old information, which is invalid.
3633 Since nowadays we can create registers during combine just fine,
3634 we should just create a new one here, not reuse i2dest. */
3636 /* First try to split using the original register as a
3637 scratch register. */
3641 i2dest)));
3644 /* If that didn't work, try changing the mode of I2DEST if
3645 we can. */
3650 {
3652 rtx ni2dest;
3656 else
3657 {
3660 }
3662 parallel = (gen_rtx_PARALLEL
3666 ni2dest))));
3671 {
3679 }
3680 }
3683 }
3685 /* If recog_for_combine has discarded clobbers, try to use them
3686 again for the split. */
3688 {
3691 }
3694 {
3699 }
3703 {
3713 /* If I2 or I3 has multiple SETs, we won't know how to track
3714 register status, so don't use these insns. If I2's destination
3715 is used between I2 and I3, we also can't use these insns. */
3725 /* It is possible that both insns now set the destination of I3.
3726 If so, we must show an extra use of it. */
3729 {
3748 }
3749 }
3751 /* If we can split it and use I2DEST, go ahead and see if that
3752 helps things be recognized. Verify that none of the registers
3753 are set between I2 and I3. */
3757 /* We need I2DEST in the proper mode. If it is a hard register
3758 or the only use of a pseudo, we can change its mode.
3759 Make sure we don't change a hard register to have a mode that
3760 isn't valid for it, or change the number of registers. */
3767 /* We can't overwrite I2DEST if its value is still used by
3768 NEWPAT. */
3770 {
3779 /* *SPLIT may be part of I2SRC, so make sure we have the
3780 original expression around for later debug processing.
3781 We should not need I2SRC any more in other cases. */
3784 else
3787 /* Get NEWDEST as a register in the proper mode. We have already
3788 validated that we can do this. */
3790 {
3793 else
3794 {
3797 }
3798 }
3800 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3801 an ASHIFT. This can occur if it was inside a PLUS and hence
3802 appeared to be a memory address. This is a kludge. */
3807 {
3810 /* Update split_code because we may not have a multiply
3811 anymore. */
3813 }
3815 /* Similarly for (plus (mult FOO (const_int pow2))). */
3821 {
3825 /* Update split_code because we may not have a multiply
3826 anymore. */
3828 }
3830 #ifdef INSN_SCHEDULING
3831 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3832 be written as a ZERO_EXTEND. */
3834 {
3835 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3836 what it really is. */
3841 else
3844 }
3845 #endif
3847 /* Attempt to split binary operators using arithmetic identities. */
3851 {
3858 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3860 {
3865 }
3866 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3873 {
3879 /* Split both "((X op Y) op X) op Y" and
3880 "((X op Y) op Y) op X" as "T op T" where T is
3881 "X op Y". */
3884 {
3889 }
3890 /* Split "((X op X) op Y) op Y)" as "T op T" where
3891 T is "X op Y". */
3893 {
3899 }
3900 }
3901 }
3904 {
3907 }
3911 /* recog_for_combine might have added CLOBBERs to newi2pat.
3912 Make sure NEWPAT does not depend on the clobbered regs. */
3916 {
3919 {
3922 }
3923 }
3925 /* If the split point was a MULT and we didn't have one before,
3926 don't use one now. */
3929 }
3930 }
3932 /* Check for a case where we loaded from memory in a narrow mode and
3933 then sign extended it, but we need both registers. In that case,
3934 we have a PARALLEL with both loads from the same memory location.
3935 We can split this into a load from memory followed by a register-register
3936 copy. This saves at least one insn, more if register allocation can
3937 eliminate the copy.
3939 We cannot do this if the destination of the first assignment is a
3940 condition code register or cc0. We eliminate this case by making sure
3941 the SET_DEST and SET_SRC have the same mode.
3943 We cannot do this if the destination of the second assignment is
3944 a register that we have already assumed is zero-extended. Similarly
3945 for a SUBREG of such a register. */
3980 {
3981 rtx ni2dest;
3995 }
3997 /* Similarly, check for a case where we have a PARALLEL of two independent
3998 SETs but we started with three insns. In this case, we can do the sets
3999 as two separate insns. This case occurs when some SET allows two
4000 other insns to combine, but the destination of that SET is still live.
4002 Also do this if we started with two insns and (at least) one of the
4003 resulting sets is a noop; this noop will be deleted later. */
4022 {
4026 /* Normally, it doesn't matter which of the two is done first,
4027 but the one that references cc0 can't be the second, and
4028 one which uses any regs/memory set in between i2 and i3 can't
4029 be first. The PARALLEL might also have been pre-existing in i3,
4030 so we need to make sure that we won't wrongly hoist a SET to i2
4031 that would conflict with a death note present in there. */
4039 /* If I3 is a jump, ensure that set0 is a jump so that
4040 we do not create invalid RTL. */
4042 )
4043 {
4046 }
4054 /* If I3 is a jump, ensure that set1 is a jump so that
4055 we do not create invalid RTL. */
4057 )
4058 {
4061 }
4062 else
4063 {
4066 }
4071 {
4072 /* recog_for_combine might have added CLOBBERs to newi2pat.
4073 Make sure NEWPAT does not depend on the clobbered regs. */
4075 {
4078 {
4081 {
4084 }
4085 }
4086 }
4089 }
4090 }
4092 /* If it still isn't recognized, fail and change things back the way they
4093 were. */
4095 /* Is the result a reasonable ASM_OPERANDS? */
4097 {
4100 }
4102 /* If we had to change another insn, make sure it is valid also. */
4104 {
4112 {
4115 }
4116 }
4118 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4119 they are adjacent to each other or not. */
4121 {
4125 {
4128 }
4129 }
4131 /* Only allow this combination if insn_cost reports that the
4132 replacement instructions are cheaper than the originals. */
4134 {
4137 }
4140 {
4145 {
4150 /* Temporarily revert mode back. */
4154 {
4155 /* If we used i2dest as a scratch register with a
4156 different mode, substitute it for the original
4157 i2src while its original mode is temporarily
4158 restored, and then clear i2scratch so that we don't
4159 do it again later. */
4161 this_basic_block);
4163 /* Put back the new mode. */
4165 }
4166 else
4167 {
4172 {
4175 }
4176 else
4177 {
4184 }
4186 /* We're dealing with a reg that changed mode but not
4187 meaning, so we want to turn it into a subreg for
4188 the new mode. However, because of REG sharing and
4189 because its mode had already changed, we have to do
4190 it in two steps. First, replace any debug uses of
4191 reg, with its original mode temporarily restored,
4192 with this copy we have created; then, replace the
4193 copy with the SUBREG of the original shared reg,
4194 once again changed to the new mode. */
4196 this_basic_block);
4200 this_basic_block);
4201 }
4202 }
4203 }
4205 /* If we will be able to accept this, we have made a
4206 change to the destination of I3. This requires us to
4207 do a few adjustments. */
4210 {
4213 }
4215 /* We now know that we can do this combination. Merge the insns and
4216 update the status of registers and LOG_LINKS. */
4219 {
4224 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4225 ensure that they are still valid. Then add any non-duplicate
4226 notes added by recog_for_combine. */
4228 {
4237 /* Simply drop equal note since it may be no longer valid
4238 for other_insn. It may be possible to record that CC
4239 register is changed and only discard those notes, but
4240 in practice it's unnecessary complication and doesn't
4241 give any meaningful improvement.
4243 See PR78559. */
4247 }
4251 NULL_RTX);
4252 }
4255 {
4258 rtx ni2dest;
4260 /* I3 now uses what used to be its destination and which is now
4261 I2's destination. This requires us to do a few adjustments. */
4265 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4266 so we still will.
4268 However, some later insn might be using I2's dest and have
4269 a LOG_LINK pointing at I3. We must remove this link.
4270 The simplest way to remove the link is to point it at I1,
4271 which we know will be a NOTE. */
4273 /* newi2pat is usually a SET here; however, recog_for_combine might
4274 have added some clobbers. */
4277 else
4284 {
4287 {
4293 }
4294 }
4295 }
4297 {
4302 /* Compute which registers we expect to eliminate. newi2pat may be setting
4303 either i3dest or i2dest, so we must check it. */
4306 || !i2dest_killed
4308 /* For i1, we need to compute both local elimination and global
4309 elimination information with respect to newi2pat because i1dest
4310 may be the same as i3dest, in which case newi2pat may be setting
4311 i1dest. Global information is used when distributing REG_DEAD
4312 note for i2 and i3, in which case it does matter if newi2pat sets
4313 i1dest or not.
4315 Local information is used when distributing REG_DEAD note for i1,
4316 in which case it doesn't matter if newi2pat sets i1dest or not.
4317 See PR62151, if we have four insns combination:
4318 i0: r0 <- i0src
4319 i1: r1 <- i1src (using r0)
4320 REG_DEAD (r0)
4321 i2: r0 <- i2src (using r1)
4322 i3: r3 <- i3src (using r0)
4323 ix: using r0
4324 From i1's point of view, r0 is eliminated, no matter if it is set
4325 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4326 should be discarded.
4328 Note local information only affects cases in forms like "I1->I2->I3",
4329 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4330 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4331 i0dest anyway. */
4333 || !i1dest_killed
4338 /* Same case as i1. */
4345 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4346 clear them. */
4354 /* Ensure that we do not have something that should not be shared but
4355 occurs multiple times in the new insns. Check this by first
4356 resetting all the `used' flags and then copying anything is shared. */
4380 {
4383 {
4385 {
4386 /* I2SRC must still be meaningful at this point. Some
4387 splitting operations can invalidate I2SRC, but those
4388 operations do not apply to calls. */
4392 }
4399 }
4400 }
4405 /* We had one special case above where I2 had more than one set and
4406 we replaced a destination of one of those sets with the destination
4407 of I3. In that case, we have to update LOG_LINKS of insns later
4408 in this basic block. Note that this (expensive) case is rare.
4410 Also, in this case, we must pretend that all REG_NOTEs for I2
4411 actually came from I3, so that REG_UNUSED notes from I2 will be
4412 properly handled. */
4415 {
4424 temp_insn
4434 {
4439 }
4440 else
4443 }
4451 {
4454 this_basic_block);
4457 }
4458 else
4459 {
4462 this_basic_block);
4464 }
4467 {
4472 this_basic_block);
4474 }
4477 {
4482 this_basic_block);
4484 }
4486 /* Get death notes for everything that is now used in either I3 or
4487 I2 and used to die in a previous insn. If we built two new
4488 patterns, move from I1 to I2 then I2 to I3 so that we get the
4489 proper movement on registers that I2 modifies. */
4495 else
4501 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4518 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4519 know these are REG_UNUSED and want them to go to the desired insn,
4520 so we always pass it as i3. */
4524 NULL_RTX);
4528 NULL_RTX);
4530 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4531 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4532 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4533 in that case, it might delete I2. Similarly for I2 and I1.
4534 Show an additional death due to the REG_DEAD note we make here. If
4535 we discard it in distribute_notes, we will decrement it again. */
4538 {
4543 else
4546 }
4549 {
4554 else
4557 }
4560 {
4565 else
4568 }
4571 {
4576 else
4579 }
4587 {
4592 /* The insn that used to set this register doesn't exist, and
4593 this life of the register may not exist either. See if one of
4594 I3's links points to an insn that sets I2DEST. If it does,
4595 that is now the last known value for I2DEST. If we don't update
4596 this and I2 set the register to a value that depended on its old
4597 contents, we will get confused. If this insn is used, thing
4598 will be set correctly in combine_instructions. */
4606 /* If the reg formerly set in I2 died only once and that was in I3,
4607 zero its use count so it won't make `reload' do any work. */
4610 && ! i2dest_in_i2src
4613 }
4616 {
4629 && ! i1dest_in_i1src
4632 }
4635 {
4648 && ! i0dest_in_i0src
4651 }
4653 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4654 been made to this insn. The order is important, because newi2pat
4655 can affect nonzero_bits of newpat. */
4659 }
4662 {
4664 {
4667 }
4669 }
4672 {
4674 {
4677 }
4679 }
4682 {
4684 {
4687 }
4689 }
4692 {
4694 {
4697 }
4699 }
4702 {
4704 {
4707 }
4709 }
4711 /* Set new_direct_jump_p if a new return or simple jump instruction
4712 has been created. Adjust the CFG accordingly. */
4714 {
4718 }
4723 {
4726 }
4730 {
4736 }
4741 {
4747 }
4749 /* A noop might also need cleaning up of CFG, if it comes from the
4750 simplification of a jump. */
4755 {
4758 }
4765 {
4768 }
4770 combine_successes++;
4780 }
4781 \f
4782 /* Get a marker for undoing to the current state. */
4786 {
4788 }
4790 /* Undo the modifications up to the marker. */
4792 static void
4794 {
4798 {
4803 {
4818 }
4822 }
4825 }
4827 /* Undo all the modifications recorded in undobuf. */
4829 static void
4831 {
4833 }
4835 /* We've committed to accepting the changes we made. Move all
4836 of the undos to the free list. */
4838 static void
4840 {
4844 {
4848 }
4850 }
4851 \f
4852 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4853 where we have an arithmetic expression and return that point. LOC will
4854 be inside INSN.
4856 try_combine will call this function to see if an insn can be split into
4857 two insns. */
4861 {
4871 /* First special-case some codes. */
4873 {
4875 #ifdef INSN_SCHEDULING
4876 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4877 point. */
4880 #endif
4884 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4885 using LO_SUM and HIGH. */
4888 {
4896 }
4898 /* If we have a PLUS whose second operand is a constant and the
4899 address is not valid, perhaps will can split it up using
4900 the machine-specific way to split large constants. We use
4901 the first pseudo-reg (one of the virtual regs) as a placeholder;
4902 it will not remain in the result. */
4907 {
4910 subst_insn);
4912 /* This should have produced two insns, each of which sets our
4913 placeholder. If the source of the second is a valid address,
4914 we can make put both sources together and make a split point
4915 in the middle. */
4928 && memory_address_addr_space_p
4931 {
4935 /* Replace the placeholder in SRC2 with SRC1. If we can
4936 find where in SRC2 it was placed, that can become our
4937 split point and we can replace this address with SRC2.
4938 Just try two obvious places. */
4949 {
4952 }
4953 }
4955 /* If that didn't work, perhaps the first operand is complex and
4956 needs to be computed separately, so make a split point there.
4957 This will occur on machines that just support REG + CONST
4958 and have a constant moved through some previous computation. */
4964 }
4966 /* If we have a PLUS whose first operand is complex, try computing it
4967 separately by making a split there. */
4978 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4979 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4980 we need to put the operand into a register. So split at that
4981 point. */
4991 /* See if we can split SET_SRC as it stands. */
4996 /* See if we can split SET_DEST as it stands. */
5001 /* See if this is a bitfield assignment with everything constant. If
5002 so, this is an IOR of an AND, so split it into that. */
5014 {
5019 unsigned HOST_WIDE_INT mask
5021 rtx or_mask;
5030 else
5031 {
5037 or_mask));
5038 }
5045 }
5047 /* Otherwise, see if this is an operation that we can split into two.
5048 If so, try to split that. */
5052 {
5054 /* If we are AND'ing with a large constant that is only a single
5055 bit and the result is only being used in a context where we
5056 need to know if it is zero or nonzero, replace it with a bit
5057 extraction. This will avoid the large constant, which might
5058 have taken more than one insn to make. If the constant were
5059 not a valid argument to the AND but took only one insn to make,
5060 this is no worse, but if it took more than one insn, it will
5061 be better. */
5071 {
5076 {
5079 }
5080 }
5084 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5085 is known to be on, this can be converted into a NEG of a shift. */
5091 {
5103 }
5109 /* We can't optimize if either mode is a partial integer
5110 mode as we don't know how many bits are significant
5111 in those modes. */
5127 {
5135 }
5140 }
5145 {
5146 /* For unsigned, we have a choice of a shift followed by an
5147 AND or two shifts. Use two shifts for field sizes where the
5148 constant might be too large. We assume here that we can
5149 always at least get 8-bit constants in an AND insn, which is
5150 true for every current RISC. */
5153 {
5154 unsigned HOST_WIDE_INT mask
5158 gen_rtx_LSHIFTRT
5166 }
5167 else
5168 {
5170 gen_rtx_fmt_ee
5181 }
5182 }
5184 /* See if this is a simple operation with a constant as the second
5185 operand. It might be that this constant is out of range and hence
5186 could be used as a split point. */
5194 /* Finally, see if this is a simple operation with its first operand
5195 not in a register. The operation might require this operand in a
5196 register, so return it as a split point. We can always do this
5197 because if the first operand were another operation, we would have
5198 already found it as a split point. */
5207 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5208 it is better to write this as (not (ior A B)) so we can split it.
5209 Similarly for IOR. */
5211 {
5219 }
5221 /* Many RISC machines have a large set of logical insns. If the
5222 second operand is a NOT, put it first so we will try to split the
5223 other operand first. */
5225 {
5229 }
5234 /* Canonicalization can produce (minus A (mult B C)), where C is a
5235 constant. It may be better to try splitting (plus (mult B -C) A)
5236 instead if this isn't a multiply by a power of two. */
5240 {
5248 mode)),
5251 }
5253 /* Split at a multiply-accumulate instruction. However if this is
5254 the SET_SRC, we likely do not have such an instruction and it's
5255 worthless to try this split. */
5264 }
5266 /* Otherwise, select our actions depending on our rtx class. */
5268 {
5274 /* fall through */
5282 /* fall through */
5284 /* Some machines have (and (shift ...) ...) insns. If X is not
5285 an AND, but XEXP (X, 0) is, use it as our split point. */
5295 /* Otherwise, we don't have a split point. */
5297 }
5298 }
5299 \f
5300 /* Throughout X, replace FROM with TO, and return the result.
5301 The result is TO if X is FROM;
5302 otherwise the result is X, but its contents may have been modified.
5303 If they were modified, a record was made in undobuf so that
5304 undo_all will (among other things) return X to its original state.
5306 If the number of changes necessary is too much to record to undo,
5307 the excess changes are not made, so the result is invalid.
5308 The changes already made can still be undone.
5309 undobuf.num_undo is incremented for such changes, so by testing that
5310 the caller can tell whether the result is valid.
5312 `n_occurrences' is incremented each time FROM is replaced.
5314 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5316 IN_COND is nonzero if we are at the top level of a condition.
5318 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5319 by copying if `n_occurrences' is nonzero. */
5321 static rtx
5323 {
5328 rtx new_rtx;
5330 /* Two expressions are equal if they are identical copies of a shared
5331 RTX or if they are both registers with the same register number
5332 and mode. */
5334 #define COMBINE_RTX_EQUAL_P(X,Y) \
5335 ((X) == (Y) \
5336 || (REG_P (X) && REG_P (Y) \
5337 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5339 /* Do not substitute into clobbers of regs -- this will never result in
5340 valid RTL. */
5345 {
5346 n_occurrences++;
5348 }
5350 /* If X and FROM are the same register but different modes, they
5351 will not have been seen as equal above. However, the log links code
5352 will make a LOG_LINKS entry for that case. If we do nothing, we
5353 will try to rerecognize our original insn and, when it succeeds,
5354 we will delete the feeding insn, which is incorrect.
5356 So force this insn not to match in this (rare) case. */
5361 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5362 of which may contain things that can be combined. */
5366 /* It is possible to have a subexpression appear twice in the insn.
5367 Suppose that FROM is a register that appears within TO.
5368 Then, after that subexpression has been scanned once by `subst',
5369 the second time it is scanned, TO may be found. If we were
5370 to scan TO here, we would find FROM within it and create a
5371 self-referent rtl structure which is completely wrong. */
5375 /* Parallel asm_operands need special attention because all of the
5376 inputs are shared across the arms. Furthermore, unsharing the
5377 rtl results in recognition failures. Failure to handle this case
5378 specially can result in circular rtl.
5380 Solve this by doing a normal pass across the first entry of the
5381 parallel, and only processing the SET_DESTs of the subsequent
5382 entries. Ug. */
5387 {
5390 /* If this substitution failed, this whole thing fails. */
5398 {
5404 {
5407 /* If this substitution failed, this whole thing fails. */
5413 }
5414 }
5415 }
5416 else
5417 {
5421 /* We don't need to process a SET_DEST that is a register, CC0,
5422 or PC, so set up to skip this common case. All other cases
5423 where we want to suppress replacing something inside a
5424 SET_SRC are handled via the IN_DEST operand. */
5431 /* Trying to simplify the operands of a widening MULT is not likely
5432 to create RTL matching a machine insn. */
5444 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5445 constant. */
5450 {
5452 {
5455 {
5457 {
5460 n_occurrences++;
5461 }
5462 else
5463 {
5465 unique_copy);
5467 /* If this substitution failed, this whole thing
5468 fails. */
5472 }
5475 }
5476 }
5478 {
5479 /* If this is a register being set, ignore it. */
5486 ;
5489 {
5490 /* In general, don't install a subreg involving two
5491 modes not tieable. It can worsen register
5492 allocation, and can even make invalid reload
5493 insns, since the reg inside may need to be copied
5494 from in the outside mode, and that may be invalid
5495 if it is an fp reg copied in integer mode.
5497 We allow two exceptions to this: It is valid if
5498 it is inside another SUBREG and the mode of that
5499 SUBREG and the mode of the inside of TO is
5500 tieable and it is valid if X is a SET that copies
5501 FROM to CC0. */
5509 && (!HAVE_cc0
5524 n_occurrences++;
5525 }
5526 else
5527 /* If we are in a SET_DEST, suppress most cases unless we
5528 have gone inside a MEM, in which case we want to
5529 simplify the address. We assume here that things that
5530 are actually part of the destination have their inner
5531 parts in the first expression. This is true for SUBREG,
5532 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5533 things aside from REG and MEM that should appear in a
5534 SET_DEST. */
5536 (((in_dest
5542 unique_copy);
5544 /* If we found that we will have to reject this combination,
5545 indicate that by returning the CLOBBER ourselves, rather than
5546 an expression containing it. This will speed things up as
5547 well as prevent accidents where two CLOBBERs are considered
5548 to be equal, thus producing an incorrect simplification. */
5554 {
5562 }
5565 {
5569 }
5570 else
5572 }
5573 }
5574 }
5576 /* Check if we are loading something from the constant pool via float
5577 extension; in this case we would undo compress_float_constant
5578 optimization and degenerate constant load to an immediate value. */
5582 {
5586 }
5588 /* Try to simplify X. If the simplification changed the code, it is likely
5589 that further simplification will help, so loop, but limit the number
5590 of repetitions that will be performed. */
5593 {
5594 /* If X is sufficiently simple, don't bother trying to do anything
5595 with it. */
5604 /* We no longer know the original mode of operand 0 since we
5605 have changed the form of X) */
5607 }
5610 }
5611 \f
5612 /* If X is a commutative operation whose operands are not in the canonical
5613 order, use substitutions to swap them. */
5615 static void
5617 {
5620 {
5624 }
5625 }
5627 /* Simplify X, a piece of RTL. We just operate on the expression at the
5628 outer level; call `subst' to simplify recursively. Return the new
5629 expression.
5631 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5632 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5633 of a condition. */
5635 static rtx
5638 {
5641 scalar_int_mode int_mode;
5642 rtx temp;
5645 /* If this is a commutative operation, put a constant last and a complex
5646 expression first. We don't need to do this for comparisons here. */
5649 /* Try to fold this expression in case we have constants that weren't
5650 present before. */
5653 {
5661 {
5664 {
5668 }
5671 }
5684 }
5687 {
5692 }
5694 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5695 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5696 things. Check for cases where both arms are testing the same
5697 condition.
5699 Don't do anything if all operands are very simple. */
5712 {
5717 /* If everything is a comparison, what we have is highly unlikely
5718 to be simpler, so don't use it. */
5721 {
5728 /* Simplify the alternative arms; this may collapse the true and
5729 false arms to store-flag values. Be careful to use copy_rtx
5730 here since true_rtx or false_rtx might share RTL with x as a
5731 result of the if_then_else_cond call above. */
5735 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5736 is unlikely to be simpler. */
5739 {
5742 /* Restarting if we generate a store-flag expression will cause
5743 us to loop. Just drop through in this case. */
5745 /* If the result values are STORE_FLAG_VALUE and zero, we can
5746 just make the comparison operation. */
5757 /* Likewise, we can make the negate of a comparison operation
5758 if the result values are - STORE_FLAG_VALUE and zero. */
5766 mode);
5777 mode);
5778 else
5781 mode,
5782 VOIDmode,
5783 cond,
5784 cop1),
5789 }
5790 }
5791 }
5793 /* First see if we can apply the inverse distributive law. */
5796 {
5800 }
5802 /* If CODE is an associative operation not otherwise handled, see if we
5803 can associate some operands. This can win if they are constants or
5804 if they are logically related (i.e. (a & b) & a). */
5810 {
5812 {
5816 rtx inner;
5818 /* Make sure we pass the constant operand if any as the second
5819 one if this is a commutative operation. */
5827 /* For commutative operations, try the other pair if that one
5828 didn't simplify. */
5830 {
5835 }
5839 }
5840 }
5842 /* A little bit of algebraic simplification here. */
5844 {
5846 /* Ensure that our address has any ASHIFTs converted to MULT in case
5847 address-recognizing predicates are called later. */
5856 /* See if this can be moved to simplify_subreg. */
5859 /* Don't call gen_lowpart if the inner mode
5860 is VOIDmode and we cannot simplify it, as SUBREG without
5861 inner mode is invalid. */
5868 {
5869 rtx temp;
5875 /* If op is known to have all lower bits zero, the result is zero. */
5888 }
5890 /* Don't change the mode of the MEM if that would change the meaning
5891 of the address. */
5898 /* Note that we cannot do any narrowing for non-constants since
5899 we might have been counting on using the fact that some bits were
5900 zero. We now do this in the SET. */
5907 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5908 replaced by (lshiftrt X C). This will convert
5909 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5917 /* If X has only a single bit that might be nonzero, say, bit I, convert
5918 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5919 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5920 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5921 or a SUBREG of one since we'd be making the expression more
5922 complex if it was just a register. */
5929 {
5930 rtx temp1 = simplify_shift_const
5936 /* If all we did was surround TEMP with the two shifts, we
5937 haven't improved anything, so don't use it. Otherwise,
5938 we are better off with TEMP1. */
5943 }
5947 /* We can't handle truncation to a partial integer mode here
5948 because we don't know the real bitsize of the partial
5949 integer mode. */
5958 /* We can truncate a constant value and return it. */
5962 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5963 whose value is a comparison can be replaced with a subreg if
5964 STORE_FLAG_VALUE permits. */
5973 /* (const (const X)) can become (const X). Do it this way rather than
5974 returning the inner CONST since CONST can be shared with a
5975 REG_EQUAL note. */
5981 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5982 can add in an offset. find_split_point will split this address up
5983 again if it doesn't match. */
5990 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5991 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5992 bit-field and can be replaced by either a sign_extend or a
5993 sign_extract. The `and' may be a zero_extend and the two
5994 <c>, -<c> constants may be reversed. */
6010 return simplify_shift_const
6017 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6018 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6019 the bitsize of the mode - 1. This allows simplification of
6020 "a = (b & 8) == 0;" */
6027 return simplify_shift_const
6031 const1_rtx),
6035 /* If we are adding two things that have no bits in common, convert
6036 the addition into an IOR. This will often be further simplified,
6037 for example in cases like ((a & 1) + (a & 2)), which can
6038 become a & 3. */
6043 {
6044 /* Try to simplify the expression further. */
6048 /* If we could, great. If not, do not go ahead with the IOR
6049 replacement, since PLUS appears in many special purpose
6050 address arithmetic instructions. */
6058 }
6060 /* Canonicalize x + x into x << 1. */
6069 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6070 (and <foo> (const_int pow2-1)) */
6081 /* If we have (mult (plus A B) C), apply the distributive law and then
6082 the inverse distributive law to see if things simplify. This
6083 occurs mostly in addresses, often when unrolling loops. */
6086 {
6090 }
6092 /* Try simplify a*(b/c) as (a*b)/c. */
6095 {
6101 }
6105 /* If this is a divide by a power of two, treat it as a shift if
6106 its first operand is a shift. */
6126 /* If the first operand is a condition code, we can't do anything
6127 with it. */
6131 {
6139 /* Simplify our comparison, if possible. */
6142 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6143 if only the low-order bit is possibly nonzero in X (such as when
6144 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6145 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6146 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6147 (plus X 1).
6149 Remove any ZERO_EXTRACT we made when thinking this was a
6150 comparison. It may now be simpler to use, e.g., an AND. If a
6151 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6152 the call to make_compound_operation in the SET case.
6154 Don't apply these optimizations if the caller would
6155 prefer a comparison rather than a value.
6156 E.g., for the condition in an IF_THEN_ELSE most targets need
6157 an explicit comparison. */
6160 ;
6178 {
6182 int_mode);
6183 }
6191 {
6195 const1_rtx);
6196 }
6205 {
6208 }
6210 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6211 those above. */
6213 ;
6230 {
6234 int_mode);
6235 }
6244 {
6248 int_mode);
6249 }
6251 /* If X is 0/1, (eq X 0) is X-1. */
6258 {
6261 }
6263 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6264 one bit that might be nonzero, we can convert (ne x 0) to
6265 (ashift x c) where C puts the bit in the sign bit. Remove any
6266 AND with STORE_FLAG_VALUE when we are done, since we are only
6267 going to test the sign bit. */
6275 {
6281 else
6283 }
6285 /* If the code changed, return a whole new comparison.
6286 We also need to avoid using SUBST in cases where
6287 simplify_comparison has widened a comparison with a CONST_INT,
6288 since in that case the wider CONST_INT may fail the sanity
6289 checks in do_SUBST. */
6296 /* Otherwise, keep this operation, but maybe change its operands.
6297 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6300 }
6310 /* If we are processing SET_DEST, we are done. */
6328 /* If this is a shift by a constant amount, simplify it. */
6336 (HOST_WIDE_INT_1U
6345 }
6348 }
6349 \f
6350 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6352 static rtx
6354 {
6361 rtx temp;
6364 rtx reversed;
6367 /* Simplify storing of the truth value. */
6372 /* Also when the truth value has to be reversed. */
6378 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6379 in it is being compared against certain values. Get the true and false
6380 comparisons and see if that says anything about the value of each arm. */
6386 {
6387 HOST_WIDE_INT nzb;
6393 /* If FALSE_CODE is EQ, swap the codes and arms. */
6396 {
6399 }
6401 scalar_int_mode from_mode;
6403 {
6404 /* If we are comparing against zero and the expression being
6405 tested has only a single bit that might be nonzero, that is
6406 its value when it is not equal to zero. Similarly if it is
6407 known to be -1 or 0. */
6411 {
6414 }
6419 {
6422 }
6423 }
6425 /* Now simplify an arm if we know the value of the register in the
6426 branch and it is used in the arm. Be careful due to the potential
6427 of locally-shared RTL. */
6444 }
6446 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6447 reversed, do so to avoid needing two sets of patterns for
6448 subtract-and-branch insns. Similarly if we have a constant in the true
6449 arm, the false arm is the same as the first operand of the comparison, or
6450 the false arm is more complicated than the true arm. */
6463 {
6472 /* It is possible that the conditional has been simplified out. */
6475 }
6477 /* If the two arms are identical, we don't need the comparison. */
6482 /* Convert a == b ? b : a to "a". */
6494 /* Look for cases where we have (abs x) or (neg (abs X)). */
6497 && comparison_p
6504 {
6510 return
6513 mode);
6516 }
6518 /* Look for MIN or MAX. */
6521 && comparison_p
6526 {
6541 }
6543 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6544 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6545 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6546 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6547 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6548 neither 1 or -1, but it isn't worth checking for. */
6551 && comparison_p
6554 {
6570 /* If an identity-zero op is commutative, check whether there
6571 would be a match if we swapped the operands. */
6592 {
6596 }
6609 {
6613 }
6630 {
6634 }
6647 {
6651 }
6654 {
6664 const_true_rtx));
6672 }
6673 }
6675 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6676 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6677 negation of a single bit, we can convert this operation to a shift. We
6678 can actually do this more generally, but it doesn't seem worth it. */
6690 return
6694 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6695 non-zero bit in A is C1. */
6703 {
6709 }
6712 }
6713 \f
6714 /* Simplify X, a SET expression. Return the new expression. */
6716 static rtx
6718 {
6721 machine_mode mode
6725 scalar_int_mode int_mode;
6727 /* (set (pc) (return)) gets written as (return). */
6731 /* Now that we know for sure which bits of SRC we are using, see if we can
6732 simplify the expression for the object knowing that we only need the
6733 low-order bits. */
6736 {
6739 }
6741 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6742 the comparison result and try to simplify it unless we already have used
6743 undobuf.other_insn. */
6751 {
6760 {
6763 {
6766 }
6767 }
6768 else
6776 {
6780 }
6781 else
6782 {
6787 /* Attempt to simplify CC user. */
6789 {
6793 }
6795 /* Convert X into a no-op move. */
6799 }
6801 /* Simplify our comparison, if possible. */
6804 #ifdef SELECT_CC_MODE
6805 /* If this machine has CC modes other than CCmode, check to see if we
6806 need to use a different CC mode here. */
6815 else
6818 /* If the mode changed, we have to change SET_DEST, the mode in the
6819 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6820 a hard register, just build new versions with the proper mode. If it
6821 is a pseudo, we lose unless it is only time we set the pseudo, in
6822 which case we can safely change its mode. */
6824 {
6826 {
6828 rtx new_dest;
6832 else
6833 {
6836 }
6843 }
6844 }
6847 /* If the code changed, we have to build a new comparison in
6848 undobuf.other_insn. */
6850 {
6859 /* If the only change we made was to change an EQ into an NE or
6860 vice versa, OP0 has only one bit that might be nonzero, and OP1
6861 is zero, check if changing the user of the condition code will
6862 produce a valid insn. If it won't, we can keep the original code
6863 in that insn by surrounding our operation with an XOR. */
6870 {
6875 {
6882 }
6883 }
6884 }
6889 /* Don't generate a compare of a CC with 0, just use that CC. */
6891 {
6894 }
6895 /* Otherwise, if we didn't previously have the same COMPARE we
6896 want, create it from scratch. */
6899 {
6902 }
6903 }
6904 else
6905 {
6906 /* Get SET_SRC in a form where we have placed back any
6907 compound expressions. Then do the checks below. */
6910 }
6912 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6913 and X being a REG or (subreg (reg)), we may be able to convert this to
6914 (set (subreg:m2 x) (op)).
6916 We can always do this if M1 is narrower than M2 because that means that
6917 we only care about the low bits of the result.
6919 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6920 perform a narrower operation than requested since the high-order bits will
6921 be undefined. On machine where it is defined, this transformation is safe
6922 as long as M1 and M2 have the same number of words. */
6938 {
6941 dest));
6945 }
6947 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6948 in SRC. */
6952 {
6956 /* Here we make sure that we don't have a sign bit on. */
6959 {
6962 }
6963 }
6965 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6966 would require a paradoxical subreg. Replace the subreg with a
6967 zero_extend to avoid the reload that would otherwise be required. */
6973 {
6978 }
6980 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6981 are comparing an item known to be 0 or -1 against 0, use a logical
6982 operation instead. Check for one of the arms being an IOR of the other
6983 arm with some value. We compute three terms to be IOR'ed together. In
6984 practice, at most two will be nonzero. Then we do the IOR's. */
6992 && (!HAVE_conditional_move
6997 {
7022 int_mode),
7023 false_rtx);
7029 term3));
7032 }
7034 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7035 whole thing fail. */
7040 else
7041 /* Convert this into a field assignment operation, if possible. */
7043 }
7044 \f
7045 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7046 result. */
7048 static rtx
7050 {
7053 scalar_int_mode mode;
7056 {
7058 /* We can call simplify_and_const_int only if we don't lose
7059 any (sign) bits when converting INTVAL (op1) to
7060 "unsigned HOST_WIDE_INT". */
7065 {
7072 }
7074 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7075 apply the distributive law and then the inverse distributive
7076 law to see if things simplify. */
7078 {
7082 }
7084 {
7088 }
7092 /* If we have (ior (and A B) C), apply the distributive law and then
7093 the inverse distributive law to see if things simplify. */
7096 {
7100 }
7103 {
7107 }
7112 }
7115 }
7116 \f
7117 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7118 operations" because they can be replaced with two more basic operations.
7119 ZERO_EXTEND is also considered "compound" because it can be replaced with
7120 an AND operation, which is simpler, though only one operation.
7122 The function expand_compound_operation is called with an rtx expression
7123 and will convert it to the appropriate shifts and AND operations,
7124 simplifying at each stage.
7126 The function make_compound_operation is called to convert an expression
7127 consisting of shifts and ANDs into the equivalent compound expression.
7128 It is the inverse of this function, loosely speaking. */
7130 static rtx
7132 {
7136 rtx tem;
7137 scalar_int_mode inner_mode;
7140 {
7143 /* FALLTHRU */
7145 /* We can't necessarily use a const_int for a multiword mode;
7146 it depends on implicitly extending the value.
7147 Since we don't know the right way to extend it,
7148 we can't tell whether the implicit way is right.
7150 Even for a mode that is no wider than a const_int,
7151 we can't win, because we need to sign extend one of its bits through
7152 the rest of it, and we don't know which bit. */
7156 /* Reject modes that aren't scalar integers because turning vector
7157 or complex modes into shifts causes problems. */
7161 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7162 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7163 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7164 reloaded. If not for that, MEM's would very rarely be safe.
7166 Reject modes bigger than a word, because we might not be able
7167 to reference a two-register group starting with an arbitrary register
7168 (and currently gen_lowpart might crash for a SUBREG). */
7174 /* If the inner object has VOIDmode (the only way this can happen
7175 is if it is an ASM_OPERANDS), we can't do anything since we don't
7176 know how much masking to do. */
7185 /* fall through */
7188 /* If the operand is a CLOBBER, just return it. */
7196 /* Reject modes that aren't scalar integers because turning vector
7197 or complex modes into shifts causes problems. */
7204 /* This should stay within the object being extracted, fail otherwise. */
7215 }
7217 /* We've rejected non-scalar operations by now. */
7220 /* Convert sign extension to zero extension, if we know that the high
7221 bit is not set, as this is easier to optimize. It will be converted
7222 back to cheaper alternative in make_extraction. */
7228 {
7232 /* Make sure this is a profitable operation. */
7239 else
7241 }
7243 /* We can optimize some special cases of ZERO_EXTEND. */
7245 {
7246 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7247 know that the last value didn't have any inappropriate bits
7248 set. */
7256 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7265 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7266 is a comparison and STORE_FLAG_VALUE permits. This is like
7267 the first case, but it works even when MODE is larger
7268 than HOST_WIDE_INT. */
7276 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7285 }
7287 /* If we reach here, we want to return a pair of shifts. The inner
7288 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7289 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7290 logical depending on the value of UNSIGNEDP.
7292 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7293 converted into an AND of a shift.
7295 We must check for the case where the left shift would have a negative
7296 count. This can happen in a case like (x >> 31) & 255 on machines
7297 that can't shift by a constant. On those machines, we would first
7298 combine the shift with the AND to produce a variable-position
7299 extraction. Then the constant of 31 would be substituted in
7300 to produce such a position. */
7304 {
7312 }
7317 pos),
7319 else
7320 /* Any other cases we can't handle. */
7323 /* If we couldn't do this for some reason, return the original
7324 expression. */
7329 }
7330 \f
7331 /* X is a SET which contains an assignment of one object into
7332 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7333 or certain SUBREGS). If possible, convert it into a series of
7334 logical operations.
7336 We half-heartedly support variable positions, but do not at all
7337 support variable lengths. */
7339 static const_rtx
7341 {
7342 rtx inner;
7346 scalar_int_mode compute_mode;
7348 /* Loop until we find something we can't simplify. */
7350 {
7353 {
7357 }
7360 {
7365 /* A constant position should stay within the width of INNER. */
7371 {
7379 /* If position is ADJUST - X, new position is X. */
7381 else
7382 {
7387 pos);
7388 }
7389 }
7390 }
7392 /* If the destination is a subreg that overwrites the whole of the inner
7393 register, we can move the subreg to the source. */
7395 /* We need SUBREGs to compute nonzero_bits properly. */
7396 && nonzero_sign_valid
7398 {
7400 gen_lowpart
7404 }
7405 else
7411 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7413 {
7414 /* Don't do anything for vector or complex integral types. */
7418 /* Try to find an integral mode to pun with. */
7424 }
7426 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7430 /* Don't try to compute in too wide unsupported modes. */
7434 /* Now compute the equivalent expression. Make a copy of INNER
7435 for the SET_DEST in case it is a MEM into which we will substitute;
7436 we don't want shared RTL in that case. */
7438 compute_mode);
7442 compute_mode,
7444 compute_mode),
7445 inner);
7450 mask),
7451 pos);
7456 }
7459 }
7460 \f
7461 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7462 it is an RTX that represents the (variable) starting position; otherwise,
7463 POS is the (constant) starting bit position. Both are counted from the LSB.
7465 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7467 IN_DEST is nonzero if this is a reference in the destination of a SET.
7468 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7469 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7470 be used.
7472 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7473 ZERO_EXTRACT should be built even for bits starting at bit 0.
7475 MODE is the desired mode of the result (if IN_DEST == 0).
7477 The result is an RTX for the extraction or NULL_RTX if the target
7478 can't handle it. */
7480 static rtx
7484 {
7485 /* This mode describes the size of the storage area
7486 to fetch the overall value from. Within that, we
7487 ignore the POS lowest bits, etc. */
7489 machine_mode inner_mode;
7490 scalar_int_mode wanted_inner_mode;
7496 HOST_WIDE_INT orig_pos;
7504 /* If trying or potentionally trying to extract
7505 bits outside of is_mode, don't look through
7506 non-paradoxical SUBREGs. See PR82192. */
7509 {
7510 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7511 consider just the QI as the memory to extract from.
7512 The subreg adds or removes high bits; its mode is
7513 irrelevant to the meaning of this extraction,
7514 since POS and LEN count from the lsb. */
7518 }
7523 {
7524 /* We're extracting the least significant bits of an rtx
7525 (ashift X (const_int C)), where LEN > C. Extract the
7526 least significant (LEN - C) bits of X, giving an rtx
7527 whose mode is MODE, then shift it left C times. */
7533 }
7535 /* If trying or potentionally trying to extract
7536 bits outside of is_mode, don't look through
7537 TRUNCATE. See PR82192. */
7544 /* See if this can be done without an extraction. We never can if the
7545 width of the field is not the same as that of some integer mode. For
7546 registers, we can only avoid the extraction if the position is at the
7547 low-order bit and this is either not in the destination or we have the
7548 appropriate STRICT_LOW_PART operation available.
7550 For MEM, we can avoid an extract if the field starts on an appropriate
7551 boundary and we can change the mode of the memory reference. */
7553 scalar_int_mode tmode;
7562 && (! in_dest
7566 && (pos
7569 /* We can't do this if we are widening INNER_MODE (it
7570 may not be aligned, for one thing). */
7576 {
7577 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7578 field. If the original and current mode are the same, we need not
7579 adjust the offset. Otherwise, we do if bytes big endian.
7581 If INNER is not a MEM, get a piece consisting of just the field
7582 of interest (in this case POS % BITS_PER_WORD must be 0). */
7585 {
7586 HOST_WIDE_INT offset;
7588 /* POS counts from lsb, but make OFFSET count in memory order. */
7591 else
7595 }
7597 {
7599 {
7600 /* We can't call gen_lowpart in a DEST since we
7601 always want a SUBREG (see below) and it would sometimes
7602 return a new hard register. */
7604 {
7605 unsigned int offset
7608 /* Avoid creating invalid subregs, for example when
7609 simplifying (x>>32)&255. */
7614 }
7615 else
7617 }
7618 else
7620 }
7621 else
7623 len >= HOST_BITS_PER_WIDE_INT
7624 ? HOST_WIDE_INT_M1U
7627 /* If this extraction is going into the destination of a SET,
7628 make a STRICT_LOW_PART unless we made a MEM. */
7643 /* If we know that no extraneous bits are set, and that the high
7644 bit is not set, convert the extraction to the cheaper of
7645 sign and zero extension, that are equivalent in these cases. */
7651 {
7655 /* Prefer ZERO_EXTENSION, since it gives more information to
7656 backends. */
7661 }
7663 /* Otherwise, sign- or zero-extend unless we already are in the
7664 proper mode. */
7668 }
7670 /* Unless this is a COMPARE or we have a funny memory reference,
7671 don't do anything with zero-extending field extracts starting at
7672 the low-order bit since they are simple AND operations. */
7677 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7678 if the position is not a constant and the length is not 1. In all
7679 other cases, we would only be going outside our object in cases when
7680 an original shift would have been undefined. */
7689 /* If INNER is not from memory, we want it to have the mode of a register
7690 extraction pattern's structure operand, or word_mode if there is no
7691 such pattern. The same applies to extraction_mode and pos_mode
7692 and their respective operands.
7694 For memory, assume that the desired extraction_mode and pos_mode
7695 are the same as for a register operation, since at present we don't
7696 have named patterns for aligned memory structures. */
7700 {
7704 }
7706 /* Never narrow an object, since that might not be safe. */
7714 else
7715 {
7716 /* Be careful not to go beyond the extracted object and maintain the
7717 natural alignment of the memory. */
7722 }
7727 {
7728 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7729 BITS_BIG_ENDIAN style. If position is constant, compute new
7730 position. Otherwise, build subtraction.
7731 Note that POS is relative to the mode of the original argument.
7732 If it's a MEM we need to recompute POS relative to that.
7733 However, if we're extracting from (or inserting into) a register,
7734 we want to recompute POS relative to wanted_inner_mode. */
7741 else
7742 pos_rtx
7745 pos_rtx);
7746 /* POS may be less than 0 now, but we check for that below.
7747 Note that it can only be less than 0 if !MEM_P (inner). */
7748 }
7750 /* If INNER has a wider mode, and this is a constant extraction, try to
7751 make it smaller and adjust the byte to point to the byte containing
7752 the value. */
7755 && ! pos_rtx
7760 {
7763 /* The computations below will be correct if the machine is big
7764 endian in both bits and bytes or little endian in bits and bytes.
7765 If it is mixed, we must adjust. */
7767 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7768 adjust OFFSET to compensate. */
7773 /* We can now move to the desired byte. */
7784 }
7786 /* If INNER is not memory, get it into the proper mode. If we are changing
7787 its mode, POS must be a constant and smaller than the size of the new
7788 mode. */
7790 {
7791 /* On the LHS, don't create paradoxical subregs implicitely truncating
7792 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7795 wanted_inner_mode))
7807 pos_rtx
7809 ? HOST_WIDE_INT_M1U
7813 }
7815 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7816 have to zero extend. Otherwise, we can just use a SUBREG.
7818 We dealt with constant rtxes earlier, so pos_rtx cannot
7819 have VOIDmode at this point. */
7823 {
7827 /* If we know that no extraneous bits are set, and that the high
7828 bit is not set, convert extraction to cheaper one - either
7829 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7830 cases. */
7838 {
7842 /* Prefer ZERO_EXTENSION, since it gives more information to
7843 backends. */
7847 }
7849 }
7851 /* Make POS_RTX unless we already have it and it is correct. If we don't
7852 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7853 be a CONST_INT. */
7860 /* Make the required operation. See if we can use existing rtx. */
7867 }
7868 \f
7869 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7870 can be commuted with any other operations in X. Return X without
7871 that shift if so. */
7873 static rtx
7875 {
7877 rtx tem;
7880 {
7882 /* This is the shift itself. If it is wide enough, we will return
7883 either the value being shifted if the shift count is equal to
7884 COUNT or a shift for the difference. */
7898 /* If we can safely shift this constant and we find the inner shift,
7899 make a new operation. */
7904 {
7908 }
7913 }
7916 }
7917 \f
7918 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7919 level of the expression and MODE is its mode. IN_CODE is as for
7920 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7921 that should be used when recursing on operands of *X_PTR.
7923 There are two possible actions:
7925 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7926 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7928 - Return a new rtx, which the caller returns directly. */
7930 static rtx
7934 {
7942 rtx tem;
7943 scalar_int_mode inner_mode;
7947 {
7950 }
7952 /* Process depending on the code of this operation. If NEW is set
7953 nonzero, it will be returned. */
7956 {
7958 /* Convert shifts by constants into multiplications if inside
7959 an address. */
7963 {
7969 {
7972 }
7975 }
7984 {
7988 }
7991 {
7995 mode));
7997 }
7998 else
7999 {
8002 }
8012 {
8016 }
8019 {
8023 mode));
8025 }
8026 else
8027 {
8031 }
8034 /* If the second operand is not a constant, we can't do anything
8035 with it. */
8039 /* If the constant is a power of two minus one and the first operand
8040 is a logical right shift, make an extraction. */
8043 {
8047 }
8049 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8056 {
8063 /* If we narrowed the mode when dropping the subreg, then we lose. */
8067 /* If that didn't give anything, see if the AND simplifies on
8068 its own. */
8070 {
8074 }
8075 }
8076 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8082 {
8083 /* Apply the distributive law, and then try to make extractions. */
8090 }
8092 /* If we are have (and (rotate X C) M) and C is larger than the number
8093 of bits in M, this is an extraction. */
8099 {
8105 }
8107 /* On machines without logical shifts, if the operand of the AND is
8108 a logical shift and our mask turns off all the propagated sign
8109 bits, we can replace the logical shift with an arithmetic shift. */
8117 {
8127 next_code),
8129 }
8131 /* If the constant is one less than a power of two, this might be
8132 representable by an extraction even if no shift is present.
8133 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8134 we are in a COMPARE. */
8138 next_code),
8141 /* If we are in a comparison and this is an AND with a power of two,
8142 convert this into the appropriate bit extract. */
8148 next_code),
8151 /* If the one operand is a paradoxical subreg of a register or memory and
8152 the constant (limited to the smaller mode) has only zero bits where
8153 the sub expression has known zero bits, this can be expressed as
8154 a zero_extend. */
8156 {
8157 rtx sub;
8163 {
8167 /* original AND constant with all the known zero bits set */
8170 {
8175 }
8176 }
8177 }
8182 /* If the sign bit is known to be zero, replace this with an
8183 arithmetic shift. */
8188 {
8191 next_code),
8194 }
8196 /* fall through */
8202 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8203 this is a SIGN_EXTRACT. */
8210 {
8217 }
8219 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8220 If so, try to merge the shifts into a SIGN_EXTEND. We could
8221 also do this for some cases of SIGN_EXTRACT, but it doesn't
8222 seem worth the effort; the case checked for occurs on Alpha. */
8233 next_code),
8240 /* Call ourselves recursively on the inner expression. If we are
8241 narrowing the object and it has a different RTL code from
8242 what it originally did, do this SUBREG as a force_to_mode. */
8243 {
8247 /* If the SUBREG is masking of a logical right shift,
8248 make an extraction. */
8255 {
8264 }
8266 /* If in_code is COMPARE, it isn't always safe to pass it through
8267 to the recursive make_compound_operation call. */
8271 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8272 is (const_int 0), rather than
8273 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8274 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8275 for non-equality comparisons against 0 is not equivalent
8276 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8286 simplified
8294 {
8295 rtx newer
8298 /* If we have something other than a SUBREG, we might have
8299 done an expansion, so rerun ourselves. */
8303 /* force_to_mode can expand compounds. If it just re-expanded
8304 the compound, use gen_lowpart to convert to the desired
8305 mode. */
8307 /* Likewise if it re-expanded the compound only partially.
8308 This happens for SUBREG of ZERO_EXTRACT if they extract
8309 the same number of bits. */
8318 }
8322 }
8327 }
8333 }
8335 /* Look at the expression rooted at X. Look for expressions
8336 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8337 Form these expressions.
8339 Return the new rtx, usually just X.
8341 Also, for machines like the VAX that don't have logical shift insns,
8342 try to convert logical to arithmetic shift operations in cases where
8343 they are equivalent. This undoes the canonicalizations to logical
8344 shifts done elsewhere.
8346 We try, as much as possible, to re-use rtl expressions to save memory.
8348 IN_CODE says what kind of expression we are processing. Normally, it is
8349 SET. In a memory address it is MEM. When processing the arguments of
8350 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8351 precisely it is an equality comparison against zero. */
8353 rtx
8355 {
8362 /* Select the code to be used in recursive calls. Once we are inside an
8363 address, we stay there. If we have a comparison, set to COMPARE,
8364 but once inside, go back to our default of SET. */
8371 scalar_int_mode mode;
8373 {
8379 }
8381 /* Now recursively process each operand of this operation. We need to
8382 handle ZERO_EXTEND specially so that we don't lose track of the
8383 inner mode. */
8385 {
8393 }
8398 {
8401 }
8404 {
8407 }
8411 }
8412 \f
8413 /* Given M see if it is a value that would select a field of bits
8414 within an item, but not the entire word. Return -1 if not.
8415 Otherwise, return the starting position of the field, where 0 is the
8416 low-order bit.
8418 *PLEN is set to the length of the field. */
8420 static int
8422 {
8423 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8428 /* Now shift off the low-order zero bits and see if we have a
8429 power of two minus 1. */
8437 }
8438 \f
8439 /* If X refers to a register that equals REG in value, replace these
8440 references with REG. */
8441 static rtx
8443 {
8451 {
8484 /* FALLTHRU */
8488 {
8492 else
8494 }
8496 /* fall through */
8503 {
8506 {
8508 {
8511 }
8513 }
8514 }
8516 {
8519 {
8522 {
8524 {
8527 }
8529 }
8530 }
8531 }
8534 }
8537 }
8539 /* Return X converted to MODE. If the value is already truncated to
8540 MODE we can just return a subreg even though in the general case we
8541 would need an explicit truncation. */
8543 static rtx
8545 {
8550 {
8551 /* Bit-cast X into an integer mode. */
8556 }
8559 }
8561 /* See if X can be simplified knowing that we will only refer to it in
8562 MODE and will only refer to those bits that are nonzero in MASK.
8563 If other bits are being computed or if masking operations are done
8564 that select a superset of the bits in MASK, they can sometimes be
8565 ignored.
8567 Return a possibly simplified expression, but always convert X to
8568 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8570 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8571 are all off in X. This is used when X will be complemented, by either
8572 NOT, NEG, or XOR. */
8574 static rtx
8577 {
8580 machine_mode op_mode;
8583 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8584 code below will do the wrong thing since the mode of such an
8585 expression is VOIDmode.
8587 Also do nothing if X is a CLOBBER; this can happen if X was
8588 the return value from a call to gen_lowpart. */
8592 /* We want to perform the operation in its present mode unless we know
8593 that the operation is valid in MODE, in which case we do the operation
8594 in MODE. */
8599 /* It is not valid to do a right-shift in a narrower mode
8600 than the one it came in with. */
8605 /* Truncate MASK to fit OP_MODE. */
8609 /* Determine what bits of X are guaranteed to be (non)zero. */
8612 /* If none of the bits in X are needed, return a zero. */
8616 /* If X is a CONST_INT, return a new one. Do this here since the
8617 test below will fail. */
8619 {
8622 else
8623 {
8626 }
8627 }
8629 /* If X is narrower than MODE and we want all the bits in X's mode, just
8630 get X in the proper mode. */
8635 /* We can ignore the effect of a SUBREG if it narrows the mode or
8636 if the constant masks to zero all the bits the mode doesn't have. */
8648 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8649 integer too. */
8655 }
8657 /* Subroutine of force_to_mode that handles cases in which both X and
8658 the result are scalar integers. MODE is the mode of the result,
8659 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8660 is preferred for simplified versions of X. The other arguments
8661 are as for force_to_mode. */
8663 static rtx
8667 {
8673 /* When we have an arithmetic operation, or a shift whose count we
8674 do not know, we need to assume that all bits up to the highest-order
8675 bit in MASK will be needed. This is how we form such a mask. */
8678 else
8683 {
8685 /* If X is a (clobber (const_int)), return it since we know we are
8686 generating something that won't match. */
8699 /* Similarly for a truncate. */
8703 /* If this is an AND with a constant, convert it into an AND
8704 whose constant is the AND of that constant with MASK. If it
8705 remains an AND of MASK, delete it since it is redundant. */
8708 {
8713 /* If X is still an AND, see if it is an AND with a mask that
8714 is just some low-order bits. If so, and it is MASK, we don't
8715 need it. */
8721 /* If it remains an AND, try making another AND with the bits
8722 in the mode mask that aren't in MASK turned on. If the
8723 constant in the AND is wide enough, this might make a
8724 cheaper constant. */
8729 {
8730 unsigned HOST_WIDE_INT cval
8732 rtx y;
8739 }
8742 }
8747 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8748 low-order bits (as in an alignment operation) and FOO is already
8749 aligned to that boundary, mask C1 to that boundary as well.
8750 This may eliminate that PLUS and, later, the AND. */
8752 {
8756 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8757 number, sign extend it. */
8770 }
8772 /* fall through */
8775 /* Substituting into the operands of a widening MULT is not likely to
8776 create RTL matching a machine insn. */
8786 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8787 most significant bit in MASK since carries from those bits will
8788 affect the bits we are interested in. */
8793 /* If X is (minus C Y) where C's least set bit is larger than any bit
8794 in the mask, then we may replace with (neg Y). */
8797 {
8800 }
8802 /* Similarly, if C contains every bit in the fuller_mask, then we may
8803 replace with (not Y). */
8806 {
8809 }
8816 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8817 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8818 operation which may be a bitfield extraction. Ensure that the
8819 constant we form is not wider than the mode of X. */
8831 {
8834 xmode);
8840 }
8842 binop:
8843 /* For most binary operations, just propagate into the operation and
8844 change the mode if we have an operation of that mode. */
8849 /* If we ended up truncating both operands, truncate the result of the
8850 operation instead. */
8853 {
8856 }
8862 {
8865 }
8869 /* For left shifts, do the same, but just for the first operand.
8870 However, we cannot do anything with shifts where we cannot
8871 guarantee that the counts are smaller than the size of the mode
8872 because such a count will have a different meaning in a
8873 wider mode. */
8883 /* If the shift count is a constant and we can do arithmetic in
8884 the mode of the shift, refine which bits we need. Otherwise, use the
8885 conservative form of the mask. */
8891 else
8899 {
8902 }
8906 /* Here we can only do something if the shift count is a constant,
8907 this shift constant is valid for the host, and we can do arithmetic
8908 in OP_MODE. */
8914 {
8918 /* Select the mask of the bits we need for the shift operand. */
8921 /* We can only change the mode of the shift if we can do arithmetic
8922 in the mode of the shift and INNER_MASK is no wider than the
8923 width of X's mode. */
8930 {
8933 }
8934 }
8936 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8937 shift and AND produces only copies of the sign bit (C2 is one less
8938 than a power of two), we can do this with just a shift. */
8942 /* The shift puts one of the sign bit copies in the least significant
8943 bit. */
8948 /* Number of bits left after the shift must be more than the mask
8949 needs. */
8952 /* Must be more sign bit copies than the mask needs. */
8962 /* If we are just looking for the sign bit, we don't need this shift at
8963 all, even if it has a variable count. */
8967 /* If this is a shift by a constant, get a mask that contains those bits
8968 that are not copies of the sign bit. We then have two cases: If
8969 MASK only includes those bits, this can be a logical shift, which may
8970 allow simplifications. If MASK is a single-bit field not within
8971 those bits, we are requesting a copy of the sign bit and hence can
8972 shift the sign bit to the appropriate location. */
8976 {
8980 /* If the considered data is wider than HOST_WIDE_INT, we can't
8981 represent a mask for all its bits in a single scalar.
8982 But we only care about the lower bits, so calculate these. */
8985 {
8988 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8989 is the number of bits a full-width mask would have set.
8990 We need only shift if these are fewer than nonzero can
8991 hold. If not, we must keep all bits set in nonzero. */
8996 + HOST_BITS_PER_WIDE_INT
8998 }
8999 else
9000 {
9003 }
9006 {
9011 }
9014 {
9015 x = simplify_shift_const
9021 }
9022 }
9024 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9025 even if the shift count isn't a constant. */
9029 shiftrt:
9031 /* If this is a zero- or sign-extension operation that just affects bits
9032 we don't care about, remove it. Be sure the call above returned
9033 something that is still a shift. */
9043 next_select);
9049 /* If the shift count is constant and we can do computations
9050 in the mode of X, compute where the bits we care about are.
9051 Otherwise, we can't do anything. Don't change the mode of
9052 the shift or propagate MODE into the shift, though. */
9055 {
9064 }
9068 /* If we just want the low-order bit, the NEG isn't needed since it
9069 won't change the low-order bit. */
9073 /* We need any bits less significant than the most significant bit in
9074 MASK since carries from those bits will affect the bits we are
9075 interested in. */
9080 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9081 same as the XOR case above. Ensure that the constant we form is not
9082 wider than the mode of X. */
9090 {
9097 }
9099 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9100 use the full mask inside the NOT. */
9103 unop:
9106 next_select));
9108 {
9111 }
9115 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9116 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9117 which is equal to STORE_FLAG_VALUE. */
9129 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9130 written in a narrower mode. We play it safe and do not do so. */
9146 }
9148 /* Ensure we return a value of the proper mode. */
9150 }
9151 \f
9152 /* Return nonzero if X is an expression that has one of two values depending on
9153 whether some other value is zero or nonzero. In that case, we return the
9154 value that is being tested, *PTRUE is set to the value if the rtx being
9155 returned has a nonzero value, and *PFALSE is set to the other alternative.
9157 If we return zero, we set *PTRUE and *PFALSE to X. */
9159 static rtx
9161 {
9166 scalar_int_mode int_mode;
9168 /* If we are comparing a value against zero, we are done. */
9171 {
9175 }
9177 /* If this is a unary operation whose operand has one of two values, apply
9178 our opcode to compute those values. */
9181 {
9186 }
9188 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9189 make can't possibly match and would suppress other optimizations. */
9191 ;
9193 /* If this is a binary operation, see if either side has only one of two
9194 values. If either one does or if both do and they are conditional on
9195 the same value, compute the new true and false values. */
9197 {
9205 {
9206 /* Try to enable a simplification by undoing work done by
9207 if_then_else_cond if it converted a REG into something more
9208 complex. */
9210 {
9213 }
9214 else
9215 {
9218 }
9219 }
9223 {
9224 /* If if_then_else_cond returned zero, then true/false are the
9225 same rtl. We must copy one of them to prevent invalid rtl
9226 sharing. */
9233 {
9238 }
9239 else
9240 {
9243 }
9246 }
9248 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9249 operands is zero when the other is nonzero, and vice-versa,
9250 and STORE_FLAG_VALUE is 1 or -1. */
9256 {
9273 {
9280 const_true_rtx);
9282 }
9283 }
9285 /* Similarly for MULT, AND and UMIN, except that for these the result
9286 is always zero. */
9290 {
9304 {
9307 }
9308 }
9309 }
9312 {
9313 /* If we have IF_THEN_ELSE already, extract the condition and
9314 canonicalize it if it is NE or EQ. */
9320 {
9323 }
9324 else
9326 }
9328 /* If X is a SUBREG, we can narrow both the true and false values
9329 if the inner expression, if there is a condition. */
9333 {
9339 {
9343 }
9344 }
9346 /* If X is a constant, this isn't special and will cause confusions
9347 if we treat it as such. Likewise if it is equivalent to a constant. */
9350 ;
9352 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9353 will be least confusing to the rest of the compiler. */
9355 {
9358 }
9360 /* If X is known to be either 0 or -1, those are the true and
9361 false values when testing X. */
9366 {
9369 }
9371 /* Likewise for 0 or a single bit. */
9374 {
9377 }
9379 /* Otherwise fail; show no condition with true and false values the same. */
9382 }
9383 \f
9384 /* Return the value of expression X given the fact that condition COND
9385 is known to be true when applied to REG as its first operand and VAL
9386 as its second. X is known to not be shared and so can be modified in
9387 place.
9389 We only handle the simplest cases, and specifically those cases that
9390 arise with IF_THEN_ELSE expressions. */
9392 static rtx
9394 {
9402 /* If either operand of the condition is a floating point value,
9403 then we have to avoid collapsing an EQ comparison. */
9413 /* If X is (abs REG) and we know something about REG's relationship
9414 with zero, we may be able to simplify this. */
9418 {
9427 }
9429 /* The only other cases we handle are MIN, MAX, and comparisons if the
9430 operands are the same as REG and VAL. */
9433 {
9435 {
9438 }
9441 {
9443 {
9451 else
9453 }
9456 {
9459 /* Do not reverse the condition when it is NE or EQ.
9460 This is because we cannot conclude anything about
9461 the value of 'SMAX (x, y)' when x is not equal to y,
9462 but we can when x equals y. */
9468 {
9479 }
9480 }
9481 }
9482 }
9484 {
9489 {
9490 /* We must simplify subreg here, before we lose track of the
9491 original inner_mode. */
9496 else
9498 }
9501 }
9502 /* We don't have to handle SIGN_EXTEND here, because even in the
9503 case of replacing something with a modeless CONST_INT, a
9504 CONST_INT is already (supposed to be) a valid sign extension for
9505 its narrower mode, which implies it's already properly
9506 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9507 story is different. */
9509 {
9514 {
9515 /* We must simplify the zero_extend here, before we lose
9516 track of the original inner_mode. */
9521 else
9523 }
9526 }
9530 {
9537 }
9540 }
9541 \f
9542 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9543 assignment as a field assignment. */
9545 static int
9547 {
9549 {
9557 }
9565 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9566 Note that all SUBREGs of MEM are paradoxical; otherwise they
9567 would have been rewritten. */
9580 /* We used to see if get_last_value of X and Y were the same but that's
9581 not correct. In one direction, we'll cause the assignment to have
9582 the wrong destination and in the case, we'll import a register into this
9583 insn that might have already have been dead. So fail if none of the
9584 above cases are true. */
9586 }
9587 \f
9588 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9589 Return that assignment if so.
9591 We only handle the most common cases. */
9593 static rtx
9595 {
9598 rtx assign;
9600 HOST_WIDE_INT c1;
9601 HOST_WIDE_INT pos;
9603 rtx other;
9605 /* All the rules in this function are specific to scalar integers. */
9606 scalar_int_mode mode;
9610 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9611 a clear of a one-bit field. We will have changed it to
9612 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9613 for a SUBREG. */
9619 {
9625 }
9634 {
9641 }
9643 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9644 one-bit field. */
9648 {
9654 }
9656 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9657 SRC is an AND with all bits of that field set, then we can discard
9658 the AND. */
9663 {
9670 else
9673 /* Complete overlap. We can remove the source AND. */
9677 /* Partial overlap. We can reduce the source AND. */
9679 {
9683 }
9684 }
9686 /* The other case we handle is assignments into a constant-position
9687 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9688 a mask that has all one bits except for a group of zero bits and
9689 OTHER is known to have zeros where C1 has ones, this is such an
9690 assignment. Compute the position and length from C1. Shift OTHER
9691 to the appropriate position, force it to the required mode, and
9692 make the extraction. Check for the AND in both operands. */
9694 /* One or more SUBREGs might obscure the constant-position field
9695 assignment. The first one we are likely to encounter is an outer
9696 narrowing SUBREG, which we can just strip for the purposes of
9697 identifying the constant-field assignment. */
9714 /* The second SUBREG that might get in the way is a paradoxical
9715 SUBREG around the first operand of the AND. We want to
9716 pretend the operand is as wide as the destination here. We
9717 do this by adjusting the MEM to wider mode for the sole
9718 purpose of the call to rtx_equal_for_field_assignment_p. Also
9719 note this trick only works for MEMs. */
9731 /* The second SUBREG that might get in the way is a paradoxical
9732 SUBREG around the first operand of the AND. We want to
9733 pretend the operand is as wide as the destination here. We
9734 do this by adjusting the MEM to wider mode for the sole
9735 purpose of the call to rtx_equal_for_field_assignment_p. Also
9736 note this trick only works for MEMs. */
9744 else
9758 /* The mode to use for the source is the mode of the assignment, or of
9759 what is inside a possible STRICT_LOW_PART. */
9763 /* Shift OTHER right POS places and make it the source, restricting it
9764 to the proper length and mode. */
9768 dest);
9770 len >= HOST_BITS_PER_WIDE_INT
9771 ? HOST_WIDE_INT_M1U
9775 /* If SRC is masked by an AND that does not make a difference in
9776 the value being stored, strip it. */
9787 }
9788 \f
9789 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9790 if so. */
9792 static rtx
9794 {
9798 rtx tem;
9800 /* Distributivity is not true for floating point as it can change the
9801 value. So we don't do it unless -funsafe-math-optimizations. */
9806 /* The outer operation can only be one of the following: */
9814 /* If either operand is a primitive we can't do anything, so get out
9815 fast. */
9825 /* See if the inner and outer operations distribute. */
9827 {
9832 /* These all distribute except over PLUS. */
9843 /* This is also a multiply, so it distributes over everything. */
9846 /* This used to handle SUBREG, but this turned out to be counter-
9847 productive, since (subreg (op ...)) usually is not handled by
9848 insn patterns, and this "optimization" therefore transformed
9849 recognizable patterns into unrecognizable ones. Therefore the
9850 SUBREG case was removed from here.
9852 It is possible that distributing SUBREG over arithmetic operations
9853 leads to an intermediate result than can then be optimized further,
9854 e.g. by moving the outer SUBREG to the other side of a SET as done
9855 in simplify_set. This seems to have been the original intent of
9856 handling SUBREGs here.
9858 However, with current GCC this does not appear to actually happen,
9859 at least on major platforms. If some case is found where removing
9860 the SUBREG case here prevents follow-on optimizations, distributing
9861 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9865 }
9867 /* Set LHS and RHS to the inner operands (A and B in the example
9868 above) and set OTHER to the common operand (C in the example).
9869 There is only one way to do this unless the inner operation is
9870 commutative. */
9882 else
9885 /* Form the new inner operation, seeing if it simplifies first. */
9888 /* There is one exception to the general way of distributing:
9889 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9891 {
9894 }
9896 /* We may be able to continuing distributing the result, so call
9897 ourselves recursively on the inner operation before forming the
9898 outer operation, which we return. */
9901 }
9903 /* See if X is of the form (* (+ A B) C), and if so convert to
9904 (+ (* A C) (* B C)) and try to simplify.
9906 Most of the time, this results in no change. However, if some of
9907 the operands are the same or inverses of each other, simplifications
9908 will result.
9910 For example, (and (ior A B) (not B)) can occur as the result of
9911 expanding a bit field assignment. When we apply the distributive
9912 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9913 which then simplifies to (and (A (not B))).
9915 Note that no checks happen on the validity of applying the inverse
9916 distributive law. This is pointless since we can do it in the
9917 few places where this routine is called.
9919 N is the index of the term that is decomposed (the arithmetic operation,
9920 i.e. (+ A B) in the first example above). !N is the index of the term that
9921 is distributed, i.e. of C in the first example above. */
9922 static rtx
9924 {
9925 machine_mode mode;
9929 /* Distributivity is not true for floating point as it can change the
9930 value. So we don't do it unless -funsafe-math-optimizations. */
9947 /* Special case (and (xor B C) (not A)), which is equivalent to
9948 (xor (ior A B) (ior A C)) */
9950 {
9953 }
9956 {
9957 /* Distribute the second term. */
9960 }
9961 else
9962 {
9963 /* Distribute the first term. */
9966 }
9976 }
9977 \f
9978 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9979 in MODE. Return an equivalent form, if different from (and VAROP
9980 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9982 static rtx
9985 {
9988 rtx orig_varop;
9996 /* Simplify VAROP knowing that we will be only looking at some of the
9997 bits in it.
9999 Note by passing in CONSTOP, we guarantee that the bits not set in
10000 CONSTOP are not significant and will never be examined. We must
10001 ensure that is the case by explicitly masking out those bits
10002 before returning. */
10005 /* If VAROP is a CLOBBER, we will fail so return it. */
10009 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10010 to VAROP and return the new constant. */
10014 /* See what bits may be nonzero in VAROP. Unlike the general case of
10015 a call to nonzero_bits, here we don't care about bits outside
10016 MODE. */
10020 /* Turn off all bits in the constant that are known to already be zero.
10021 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10022 which is tested below. */
10026 /* If we don't have any bits left, return zero. */
10030 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10031 a power of two, we can replace this with an ASHIFT. */
10036 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10037 or XOR, then try to apply the distributive law. This may eliminate
10038 operations if either branch can be simplified because of the AND.
10039 It may also make some cases more complex, but those cases probably
10040 won't match a pattern either with or without this. */
10043 {
10045 return
10046 gen_lowpart
10048 apply_distributive_law
10052 constop),
10055 constop))));
10056 }
10058 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10059 the AND and see if one of the operands simplifies to zero. If so, we
10060 may eliminate it. */
10064 {
10073 }
10075 /* Make a SUBREG if necessary. If we can't make it, fail. */
10080 /* If we are only masking insignificant bits, return VAROP. */
10087 /* Otherwise, return an AND. */
10089 }
10092 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10093 in MODE.
10095 Return an equivalent form, if different from X. Otherwise, return X. If
10096 X is zero, we are to always construct the equivalent form. */
10098 static rtx
10101 {
10112 }
10113 \f
10114 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10115 We don't care about bits outside of those defined in MODE.
10117 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10118 a shift, AND, or zero_extract, we can do better. */
10120 static rtx
10122 scalar_int_mode mode,
10124 {
10125 rtx tem;
10128 /* If X is a register whose nonzero bits value is current, use it.
10129 Otherwise, if X is a register whose value we can find, use that
10130 value. Otherwise, use the previously-computed global nonzero bits
10131 for this register. */
10145 && !REGNO_REG_SET_P
10148 {
10149 /* Note that, even if the precision of last_set_mode is lower than that
10150 of mode, record_value_for_reg invoked nonzero_bits on the register
10151 with nonzero_bits_mode (because last_set_mode is necessarily integral
10152 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10153 are all valid, hence in mode too since nonzero_bits_mode is defined
10154 to the largest HWI_COMPUTABLE_MODE_P mode. */
10157 }
10161 {
10166 }
10169 {
10173 /* We don't know anything about the upper bits. */
10177 }
10180 }
10182 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10183 end of X that are known to be equal to the sign bit. X will be used
10184 in mode MODE; the returned value will always be between 1 and the
10185 number of bits in MODE. */
10187 static rtx
10189 scalar_int_mode mode,
10191 {
10192 rtx tem;
10205 && !REGNO_REG_SET_P
10208 {
10211 }
10222 }
10223 \f
10224 /* Return the number of "extended" bits there are in X, when interpreted
10225 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10226 unsigned quantities, this is the number of high-order zero bits.
10227 For signed quantities, this is the number of copies of the sign bit
10228 minus 1. In both case, this function returns the number of "spare"
10229 bits. For example, if two quantities for which this function returns
10230 at least 1 are added, the addition is known not to overflow.
10232 This function will always return 0 unless called during combine, which
10233 implies that it must be called from a define_split. */
10235 unsigned int
10237 {
10241 scalar_int_mode int_mode;
10249 }
10251 /* This function is called from `simplify_shift_const' to merge two
10252 outer operations. Specifically, we have already found that we need
10253 to perform operation *POP0 with constant *PCONST0 at the outermost
10254 position. We would now like to also perform OP1 with constant CONST1
10255 (with *POP0 being done last).
10257 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10258 the resulting operation. *PCOMP_P is set to 1 if we would need to
10259 complement the innermost operand, otherwise it is unchanged.
10261 MODE is the mode in which the operation will be done. No bits outside
10262 the width of this mode matter. It is assumed that the width of this mode
10263 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10265 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10266 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10267 result is simply *PCONST0.
10269 If the resulting operation cannot be expressed as one operation, we
10270 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10272 static int
10273 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10274 {
10281 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10285 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10286 if OP0 is SET. */
10295 {
10297 {
10315 }
10316 }
10318 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10322 /* If the two constants aren't the same, we can't do anything. The
10323 remaining six cases can all be done. */
10327 else
10329 {
10332 /* (a & b) | b == b */
10335 /* (a ^ b) | b == a | b */
10336 {;}
10341 /* (a & b) ^ b == (~a) & b */
10344 /* (a | b) ^ b == a & ~b */
10350 /* (a | b) & b == b */
10353 /* (a ^ b) & b) == (~a) & b */
10358 }
10360 /* Check for NO-OP cases. */
10373 /* ??? Slightly redundant with the above mask, but not entirely.
10374 Moving this above means we'd have to sign-extend the mode mask
10375 for the final test. */
10380 }
10381 \f
10382 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10383 the shift in. The original shift operation CODE is performed on OP in
10384 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10385 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10386 result of the shift is subject to operation OUTER_CODE with operand
10387 OUTER_CONST. */
10389 static scalar_int_mode
10393 {
10396 /* In general we can't perform in wider mode for right shift and rotate. */
10398 {
10400 /* We can still widen if the bits brought in from the left are identical
10401 to the sign bit of ORIG_MODE. */
10409 /* Similarly here but with zero bits. */
10414 /* We can also widen if the bits brought in will be masked off. This
10415 operation is performed in ORIG_MODE. */
10417 {
10423 }
10424 /* fall through */
10434 }
10435 }
10437 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10438 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10439 if we cannot simplify it. Otherwise, return a simplified value.
10441 The shift is normally computed in the widest mode we find in VAROP, as
10442 long as it isn't a different number of words than RESULT_MODE. Exceptions
10443 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10445 static rtx
10448 {
10453 machine_mode shift_mode;
10455 unsigned int mode_words
10457 /* We form (outer_op (code varop count) (outer_const)). */
10463 /* Make sure and truncate the "natural" shift on the way in. We don't
10464 want to do this inside the loop as it makes it more difficult to
10465 combine shifts. */
10469 /* If we were given an invalid count, don't do anything except exactly
10470 what was requested. */
10477 /* Unless one of the branches of the `if' in this loop does a `continue',
10478 we will `break' the loop after the `if'. */
10481 {
10482 /* If we have an operand of (clobber (const_int 0)), fail. */
10486 /* Convert ROTATERT to ROTATE. */
10488 {
10492 }
10496 {
10497 /* We only change the modes of scalar shifts. */
10503 }
10505 scalar_int_mode shift_unit_mode
10508 /* Handle cases where the count is greater than the size of the mode
10509 minus 1. For ASHIFT, use the size minus one as the count (this can
10510 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10511 take the count modulo the size. For other shifts, the result is
10512 zero.
10514 Since these shifts are being produced by the compiler by combining
10515 multiple operations, each of which are defined, we know what the
10516 result is supposed to be. */
10519 {
10524 else
10525 {
10526 /* We can't simply return zero because there may be an
10527 outer op. */
10531 }
10532 }
10534 /* If we discovered we had to complement VAROP, leave. Making a NOT
10535 here would cause an infinite loop. */
10540 {
10541 /* An arithmetic right shift of a quantity known to be -1 or 0
10542 is a no-op. */
10546 {
10549 }
10551 /* If we are doing an arithmetic right shift and discarding all but
10552 the sign bit copies, this is equivalent to doing a shift by the
10553 bitsize minus one. Convert it into that shift because it will
10554 often allow other simplifications. */
10561 /* We simplify the tests below and elsewhere by converting
10562 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10563 `make_compound_operation' will convert it to an ASHIFTRT for
10564 those machines (such as VAX) that don't have an LSHIFTRT. */
10569 shift_unit_mode)))
10581 }
10584 {
10591 {
10594 }
10598 /* The following rules apply only to scalars. */
10603 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10604 minus the width of a smaller mode, we can do this with a
10605 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10612 {
10621 }
10625 /* The following rules apply only to scalars. */
10631 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10632 the same number of words as what we've seen so far. Then store
10633 the widest mode in MODE. */
10639 == mode_words
10641 {
10646 }
10650 /* Some machines use MULT instead of ASHIFT because MULT
10651 is cheaper. But it is still better on those machines to
10652 merge two shifts into one. */
10655 {
10656 varop
10662 }
10666 /* Similar, for when divides are cheaper. */
10669 {
10670 varop
10676 }
10680 /* If we are extracting just the sign bit of an arithmetic
10681 right shift, that shift is not needed. However, the sign
10682 bit of a wider mode may be different from what would be
10683 interpreted as the sign bit in a narrower mode, so, if
10684 the result is narrower, don't discard the shift. */
10689 {
10692 }
10694 /* fall through */
10699 /* The following rules apply only to scalars. */
10706 /* Here we have two nested shifts. The result is usually the
10707 AND of a new shift with a mask. We compute the result below. */
10713 {
10717 rtx mask_rtx;
10719 /* We have one common special case. We can't do any merging if
10720 the inner code is an ASHIFTRT of a smaller mode. However, if
10721 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10722 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10723 we can convert it to
10724 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10725 This simplifies certain SIGN_EXTEND operations. */
10729 {
10730 /* C3 has the low-order C1 bits zero. */
10742 }
10744 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10745 than C1 high-order bits equal to the sign bit, we can convert
10746 this to either an ASHIFT or an ASHIFTRT depending on the
10747 two counts.
10749 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10755 {
10759 {
10762 }
10765 }
10767 /* There are some cases we can't do. If CODE is ASHIFTRT,
10768 we can only do this if FIRST_CODE is also ASHIFTRT.
10770 We can't do the case when CODE is ROTATE and FIRST_CODE is
10771 ASHIFTRT.
10773 If the mode of this shift is not the mode of the outer shift,
10774 we can't do this if either shift is a right shift or ROTATE.
10776 Finally, we can't do any of these if the mode is too wide
10777 unless the codes are the same.
10779 Handle the case where the shift codes are the same
10780 first. */
10783 {
10792 }
10803 /* To compute the mask to apply after the shift, shift the
10804 nonzero bits of the inner shift the same way the
10805 outer shift will. */
10808 int_result_mode);
10810 mask_rtx
10814 /* Give up if we can't compute an outer operation to use. */
10822 /* If the shifts are in the same direction, we add the
10823 counts. Otherwise, we subtract them. */
10827 else
10830 /* If COUNT is positive, the new shift is usually CODE,
10831 except for the two exceptions below, in which case it is
10832 FIRST_CODE. If the count is negative, FIRST_CODE should
10833 always be used */
10843 }
10845 /* If we have (A << B << C) for any shift, we can convert this to
10846 (A << C << B). This wins if A is a constant. Only try this if
10847 B is not a constant. */
10852 {
10853 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10854 sure the result will be masked. See PR70222. */
10862 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10863 up outer sign extension (often left and right shift) is
10864 hardly more efficient than the original. See PR70429. */
10874 }
10878 /* The following rules apply only to scalars. */
10882 /* Make this fit the case below. */
10889 /* The following rules apply only to scalars. */
10895 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10896 with C the size of VAROP - 1 and the shift is logical if
10897 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10898 we have an (le X 0) operation. If we have an arithmetic shift
10899 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10900 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10908 {
10911 const0_rtx);
10917 }
10919 /* If we have (shift (logical)), move the logical to the outside
10920 to allow it to possibly combine with another logical and the
10921 shift to combine with another shift. This also canonicalizes to
10922 what a ZERO_EXTRACT looks like. Also, some machines have
10923 (and (shift)) insns. */
10926 /* We can't do this if we have (ashiftrt (xor)) and the
10927 constant has its sign bit set in shift_unit_mode with
10928 shift_unit_mode wider than result_mode. */
10932 shift_unit_mode))
10941 {
10944 }
10946 /* If we can't do that, try to simplify the shift in each arm of the
10947 logical expression, make a new logical expression, and apply
10948 the inverse distributive law. This also can't be done for
10949 (ashiftrt (xor)) where we've widened the shift and the constant
10950 changes the sign bit. */
10955 shift_unit_mode)))
10956 {
10968 }
10972 /* The following rules apply only to scalars. */
10977 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10978 says that the sign bit can be tested, FOO has mode MODE, C is
10979 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10980 that may be nonzero. */
10990 {
10994 }
10998 /* The following rules apply only to scalars. */
11003 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11004 than the number of bits in the mode is equivalent to A. */
11008 {
11012 }
11014 /* NEG commutes with ASHIFT since it is multiplication. Move the
11015 NEG outside to allow shifts to combine. */
11019 {
11022 }
11026 /* The following rules apply only to scalars. */
11031 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11032 is one less than the number of bits in the mode is
11033 equivalent to (xor A 1). */
11040 {
11044 }
11046 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11047 that might be nonzero in BAR are those being shifted out and those
11048 bits are known zero in FOO, we can replace the PLUS with FOO.
11049 Similarly in the other operand order. This code occurs when
11050 we are computing the size of a variable-size array. */
11057 {
11060 }
11068 {
11071 }
11073 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11084 {
11087 }
11089 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11090 signbit', and attempt to change the PLUS to an XOR and move it to
11091 the outer operation as is done above in the AND/IOR/XOR case
11092 leg for shift(logical). See details in logical handling above
11093 for reasoning in doing so. */
11105 {
11108 }
11113 /* The following rules apply only to scalars. */
11118 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11119 with C the size of VAROP - 1 and the shift is logical if
11120 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11121 we have a (gt X 0) operation. If the shift is arithmetic with
11122 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11123 we have a (neg (gt X 0)) operation. */
11132 {
11135 const0_rtx);
11141 }
11145 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11146 if the truncate does not affect the value. */
11153 {
11156 varop_inner
11159 GEN_INT
11164 }
11169 }
11172 }
11176 {
11177 /* We only change the modes of scalar shifts. */
11182 }
11184 /* We have now finished analyzing the shift. The result should be
11185 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11186 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11187 to the result of the shift. OUTER_CONST is the relevant constant,
11188 but we must turn off all bits turned off in the shift. */
11196 /* Make a SUBREG if necessary. If we can't make it, fail. */
11201 /* If we have an outer operation and we just made a shift, it is
11202 possible that we could have simplified the shift were it not
11203 for the outer operation. So try to do the simplification
11204 recursively. */
11208 else
11214 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11215 turn off all the bits that the shift would have turned off. */
11217 /* We only change the modes of scalar shifts. */
11221 /* Do the remainder of the processing in RESULT_MODE. */
11224 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11225 operation. */
11230 {
11240 {
11241 /* This means that we have determined that the result is
11242 equivalent to a constant. This should be rare. */
11245 }
11248 else
11251 }
11254 }
11256 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11257 The result of the shift is RESULT_MODE. If we cannot simplify it,
11258 return X or, if it is NULL, synthesize the expression with
11259 simplify_gen_binary. Otherwise, return a simplified value.
11261 The shift is normally computed in the widest mode we find in VAROP, as
11262 long as it isn't a different number of words than RESULT_MODE. Exceptions
11263 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11265 static rtx
11268 {
11278 }
11280 \f
11281 /* A subroutine of recog_for_combine. See there for arguments and
11282 return value. */
11284 static int
11286 {
11288 rtx pat_without_clobbers;
11296 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11297 we use to indicate that something didn't match. If we find such a
11298 thing, force rejection. */
11312 {
11315 else
11318 }
11320 /* If it isn't, there is the possibility that we previously had an insn
11321 that clobbered some register as a side effect, but the combined
11322 insn doesn't need to do that. So try once more without the clobbers
11323 unless this represents an ASM insn. */
11327 {
11332 {
11335 pos++;
11336 }
11346 {
11349 else
11352 }
11353 }
11360 /* Recognize all noop sets, these will be killed by followup pass. */
11364 /* If we had any clobbers to add, make a new pattern than contains
11365 them. Then check to make sure that all of them are dead. */
11367 {
11377 else
11384 {
11389 {
11393 }
11394 }
11396 }
11400 {
11408 /* Allow targets to reject combined insn. */
11410 {
11413 dump_file);
11415 /* Callers expect recog_for_combine to strip
11416 clobbers from the pattern on failure. */
11421 }
11426 }
11432 }
11434 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11435 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11436 Return whether anything was so changed. */
11438 static bool
11440 {
11446 {
11458 {
11467 else
11471 }
11477 {
11483 }
11488 {
11492 }
11493 else
11499 {
11502 }
11506 }
11513 scalar_int_mode mode;
11519 {
11533 else
11541 }
11544 }
11546 /* Like recog, but we receive the address of a pointer to a new pattern.
11547 We try to match the rtx that the pointer points to.
11548 If that fails, we may try to modify or replace the pattern,
11549 storing the replacement into the same pointer object.
11551 Modifications include deletion or addition of CLOBBERs. If the
11552 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11553 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11554 (and undo if that fails).
11556 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11557 the CLOBBERs are placed.
11559 The value is the final insn code from the pattern ultimately matched,
11560 or -1. */
11562 static int
11564 {
11576 {
11579 {
11583 }
11584 }
11587 {
11592 }
11595 }
11596 \f
11597 /* Like gen_lowpart_general but for use by combine. In combine it
11598 is not possible to create any new pseudoregs. However, it is
11599 safe to create invalid memory addresses, because combine will
11600 try to recognize them and all they will do is make the combine
11601 attempt fail.
11603 If for some reason this cannot do its job, an rtx
11604 (clobber (const_int 0)) is returned.
11605 An insn containing that will not be recognized. */
11607 static rtx
11609 {
11613 rtx result;
11618 /* We can only support MODE being wider than a word if X is a
11619 constant integer or has a mode the same size. */
11624 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11625 won't know what to do. So we will strip off the SUBREG here and
11626 process normally. */
11628 {
11631 /* For use in case we fall down into the address adjustments
11632 further below, we need to adjust the known mode and size of
11633 x; imode and isize, since we just adjusted x. */
11640 }
11648 {
11649 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11650 address. */
11655 /* If we want to refer to something bigger than the original memref,
11656 generate a paradoxical subreg instead. That will force a reload
11657 of the original memref X. */
11663 }
11665 /* If X is a comparison operator, rewrite it in a new mode. This
11666 probably won't match, but may allow further simplifications. */
11670 /* If we couldn't simplify X any other way, just enclose it in a
11671 SUBREG. Normally, this SUBREG won't match, but some patterns may
11672 include an explicit SUBREG or we may simplify it further in combine. */
11673 else
11674 {
11675 rtx res;
11678 {
11683 }
11687 }
11689 fail:
11691 }
11692 \f
11693 /* Try to simplify a comparison between OP0 and a constant OP1,
11694 where CODE is the comparison code that will be tested, into a
11695 (CODE OP0 const0_rtx) form.
11697 The result is a possibly different comparison code to use.
11698 *POP1 may be updated. */
11700 static enum rtx_code
11703 {
11704 scalar_int_mode int_mode;
11707 /* Get the constant we are comparing against and turn off all bits
11708 not on in our mode. */
11712 /* If we are comparing against a constant power of two and the value
11713 being compared can only have that single bit nonzero (e.g., it was
11714 `and'ed with that bit), we can replace this with a comparison
11715 with zero. */
11724 {
11727 }
11729 /* Similarly, if we are comparing a value known to be either -1 or
11730 0 with -1, change it to the opposite comparison against zero. */
11736 {
11739 }
11741 /* Do some canonicalizations based on the comparison code. We prefer
11742 comparisons against zero and then prefer equality comparisons.
11743 If we can reduce the size of a constant, we will do that too. */
11745 {
11747 /* < C is equivalent to <= (C - 1) */
11749 {
11752 /* ... fall through to LE case below. */
11754 }
11755 else
11759 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11761 {
11764 }
11766 /* If we are doing a <= 0 comparison on a value known to have
11767 a zero sign bit, we can replace this with == 0. */
11778 /* >= C is equivalent to > (C - 1). */
11780 {
11783 /* ... fall through to GT below. */
11785 }
11786 else
11790 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11792 {
11795 }
11797 /* If we are doing a > 0 comparison on a value known to have
11798 a zero sign bit, we can replace this with != 0. */
11809 /* < C is equivalent to <= (C - 1). */
11811 {
11814 /* ... fall through ... */
11816 }
11817 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11822 {
11826 }
11827 else
11831 /* unsigned <= 0 is equivalent to == 0 */
11834 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11838 == ((HOST_WIDE_INT_1U
11840 {
11843 }
11847 /* >= C is equivalent to > (C - 1). */
11849 {
11852 /* ... fall through ... */
11854 }
11856 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11861 {
11865 }
11866 else
11870 /* unsigned > 0 is equivalent to != 0 */
11873 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11877 == (HOST_WIDE_INT_1U
11879 {
11882 }
11887 }
11891 }
11892 \f
11893 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11894 comparison code that will be tested.
11896 The result is a possibly different comparison code to use. *POP0 and
11897 *POP1 may be updated.
11899 It is possible that we might detect that a comparison is either always
11900 true or always false. However, we do not perform general constant
11901 folding in combine, so this knowledge isn't useful. Such tautologies
11902 should have been detected earlier. Hence we ignore all such cases. */
11904 static enum rtx_code
11906 {
11912 opt_scalar_int_mode tmode_iter;
11914 /* Try a few ways of applying the same transformation to both operands. */
11916 {
11917 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11918 so check specially. */
11937 {
11940 }
11942 /* If both operands are the same constant shift, see if we can ignore the
11943 shift. We can if the shift is a rotate or if the bits shifted out of
11944 this shift are known to be zero for both inputs and if the type of
11945 comparison is compatible with the shift. */
11958 {
11971 else
11973 }
11975 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11976 SUBREGs are of the same mode, and, in both cases, the AND would
11977 be redundant if the comparison was done in the narrower mode,
11978 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11979 and the operand's possibly nonzero bits are 0xffffff01; in that case
11980 if we only care about QImode, we don't need the AND). This case
11981 occurs if the output mode of an scc insn is not SImode and
11982 STORE_FLAG_VALUE == 1 (e.g., the 386).
11984 Similarly, check for a case where the AND's are ZERO_EXTEND
11985 operations from some narrower mode even though a SUBREG is not
11986 present. */
11991 {
12007 {
12011 /* The resulting comparison is always unsigned since we masked
12012 off the original sign bit. */
12016 }
12022 {
12028 }
12032 }
12034 /* If both operands are NOT, we can strip off the outer operation
12035 and adjust the comparison code for swapped operands; similarly for
12036 NEG, except that this must be an equality comparison. */
12042 else
12044 }
12046 /* If the first operand is a constant, swap the operands and adjust the
12047 comparison code appropriately, but don't do this if the second operand
12048 is already a constant integer. */
12050 {
12053 }
12055 /* We now enter a loop during which we will try to simplify the comparison.
12056 For the most part, we only are concerned with comparisons with zero,
12057 but some things may really be comparisons with zero but not start
12058 out looking that way. */
12061 {
12063 scalar_int_mode int_mode;
12067 HOST_WIDE_INT const_op;
12069 /* We only want to handle integral modes. This catches VOIDmode,
12070 CCmode, and the floating-point modes. An exception is that we
12071 can handle VOIDmode if OP0 is a COMPARE or a comparison
12072 operation. */
12079 /* Try to simplify the compare to constant, possibly changing the
12080 comparison op, and/or changing op1 to zero. */
12084 /* Compute some predicates to simplify code below. */
12091 /* If this is a sign bit comparison and we can do arithmetic in
12092 MODE, say that we will only be needing the sign bit of OP0. */
12097 HOST_WIDE_INT_1U
12102 {
12103 /* We can't do anything if OP0 is a condition code value, rather
12104 than an actual data value. */
12110 /* Get the two operands being compared. */
12113 else
12116 /* Check for the cases where we simply want the result of the
12117 earlier test or the opposite of that result. */
12121 {
12125 else
12129 {
12134 }
12135 }
12137 }
12143 /* Now try cases based on the opcode of OP0. If none of the cases
12144 does a "continue", we exit this loop immediately after the
12145 switch. */
12150 {
12152 /* If we are extracting a single bit from a variable position in
12153 a constant that has only a single bit set and are comparing it
12154 with zero, we can convert this into an equality comparison
12155 between the position and the location of the single bit. */
12156 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12157 have already reduced the shift count modulo the word size. */
12163 {
12171 /* Result is nonzero iff shift count is equal to I. */
12174 }
12176 /* fall through */
12181 {
12184 }
12188 /* If testing for equality, we can take the NOT of the constant. */
12191 {
12195 }
12197 /* If just looking at the sign bit, reverse the sense of the
12198 comparison. */
12200 {
12204 }
12208 /* If testing for equality, we can take the NEG of the constant. */
12211 {
12215 }
12217 /* The remaining cases only apply to comparisons with zero. */
12221 /* When X is ABS or is known positive,
12222 (neg X) is < 0 if and only if X != 0. */
12230 {
12234 }
12236 /* If we have NEG of something whose two high-order bits are the
12237 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12239 {
12243 }
12247 /* If we are testing equality and our count is a constant, we
12248 can perform the inverse operation on our RHS. */
12252 {
12256 }
12258 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12259 a particular bit. Convert it to an AND of a constant of that
12260 bit. This will be converted into a ZERO_EXTRACT. */
12264 {
12266 (HOST_WIDE_INT_1U
12271 }
12273 /* Fall through. */
12276 /* ABS is ignorable inside an equality comparison with zero. */
12278 {
12281 }
12285 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12286 (compare FOO CONST) if CONST fits in FOO's mode and we
12287 are either testing inequality or have an unsigned
12288 comparison with ZERO_EXTEND or a signed comparison with
12289 SIGN_EXTEND. But don't do it if we don't have a compare
12290 insn of the given mode, since we'd have to revert it
12291 later on, and then we wouldn't know whether to sign- or
12292 zero-extend. */
12294 && ! unsigned_comparison_p
12298 {
12301 }
12305 /* Check for the case where we are comparing A - C1 with C2, that is
12307 (subreg:MODE (plus (A) (-C1))) op (C2)
12309 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12310 comparison in the wider mode. One of the following two conditions
12311 must be true in order for this to be valid:
12313 1. The mode extension results in the same bit pattern being added
12314 on both sides and the comparison is equality or unsigned. As
12315 C2 has been truncated to fit in MODE, the pattern can only be
12316 all 0s or all 1s.
12318 2. The mode extension results in the sign bit being copied on
12319 each side.
12321 The difficulty here is that we have predicates for A but not for
12322 (A - C1) so we need to check that C1 is within proper bounds so
12323 as to perturbate A as little as possible. */
12332 {
12340 /* (A - C1) zero-extends if it is positive and sign-extends
12341 if it is negative, C2 both zero- and sign-extends. */
12345 /* (A - C1) sign-extends if it is positive and 1-extends
12346 if it is negative, C2 both sign- and 1-extends. */
12353 /* (A - C1) always sign-extends, like C2. */
12357 {
12360 }
12361 }
12363 /* If the inner mode is narrower and we are extracting the low part,
12364 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12366 ;
12375 {
12376 /* Remove outer subregs that don't do anything. */
12381 {
12385 }
12387 }
12388 else
12391 /* FALLTHROUGH */
12400 {
12403 }
12407 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12408 this for equality comparisons due to pathological cases involving
12409 overflows. */
12413 {
12417 }
12419 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12422 {
12426 }
12430 /* We used to optimize signed comparisons against zero, but that
12431 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12432 arrive here as equality comparisons, or (GEU, LTU) are
12433 optimized away. No need to special-case them. */
12435 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12436 (eq B (minus A C)), whichever simplifies. We can only do
12437 this for equality comparisons due to pathological cases involving
12438 overflows. */
12442 {
12446 }
12451 {
12455 }
12457 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12458 of bits in X minus 1, is one iff X > 0. */
12463 {
12467 }
12471 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12472 if C is zero or B is a constant. */
12476 {
12480 }
12485 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12486 iff X <= 0. */
12490 {
12494 }
12498 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12499 will be converted to a ZERO_EXTRACT later. */
12503 {
12508 }
12510 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12511 zero and X is a comparison and C1 and C2 describe only bits set
12512 in STORE_FLAG_VALUE, we can compare with X. */
12520 {
12527 {
12530 }
12531 }
12533 /* If we are doing an equality comparison of an AND of a bit equal
12534 to the sign bit, replace this with a LT or GE comparison of
12535 the underlying value. */
12542 {
12546 }
12548 /* If this AND operation is really a ZERO_EXTEND from a narrower
12549 mode, the constant fits within that mode, and this is either an
12550 equality or unsigned comparison, try to do this comparison in
12551 the narrower mode.
12553 Note that in:
12555 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12556 -> (ne:DI (reg:SI 4) (const_int 0))
12558 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12559 known to hold a value of the required mode the
12560 transformation is invalid. */
12568 {
12571 }
12573 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12574 fits in both M1 and M2 and the SUBREG is either paradoxical
12575 or represents the low part, permute the SUBREG and the AND
12576 and try again. */
12579 {
12581 /* Require an integral mode, to avoid creating something like
12582 (AND:SF ...). */
12585 /* It is unsafe to commute the AND into the SUBREG if the
12586 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12587 not defined. As originally written the upper bits
12588 have a defined value due to the AND operation.
12589 However, if we commute the AND inside the SUBREG then
12590 they no longer have defined values and the meaning of
12591 the code has been changed.
12592 Also C1 should not change value in the smaller mode,
12593 see PR67028 (a positive C1 can become negative in the
12594 smaller mode, so that the AND does no longer mask the
12595 upper bits). */
12596 && ((WORD_REGISTER_OPERATIONS
12608 {
12614 }
12615 }
12617 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12621 {
12626 }
12628 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12629 (eq (and (lshiftrt X) 1) 0).
12630 Also handle the case where (not X) is expressed using xor. */
12634 {
12644 == HOST_WIDE_INT_1U
12646 {
12647 op0
12652 }
12653 }
12657 /* If we have (compare (ashift FOO N) (const_int C)) and
12658 the high order N bits of FOO (N+1 if an inequality comparison)
12659 are known to be zero, we can do this by comparing FOO with C
12660 shifted right N bits so long as the low-order N bits of C are
12661 zero. */
12673 {
12674 /* We must perform a logical shift, not an arithmetic one,
12675 as we want the top N bits of C to be zero. */
12682 }
12684 /* If we are doing a sign bit comparison, it means we are testing
12685 a particular bit. Convert it to the appropriate AND. */
12688 {
12690 (HOST_WIDE_INT_1U
12695 }
12697 /* If this an equality comparison with zero and we are shifting
12698 the low bit to the sign bit, we can convert this to an AND of the
12699 low-order bit. */
12703 {
12706 }
12710 /* If this is an equality comparison with zero, we can do this
12711 as a logical shift, which might be much simpler. */
12714 {
12719 }
12721 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12722 do the comparison in a narrower mode. */
12732 {
12735 }
12737 /* Likewise if OP0 is a PLUS of a sign extension with a
12738 constant, which is usually represented with the PLUS
12739 between the shifts. */
12751 {
12759 new_const);
12761 }
12763 /* FALLTHROUGH */
12765 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12766 the low order N bits of FOO are known to be zero, we can do this
12767 by comparing FOO with C shifted left N bits so long as no
12768 overflow occurs. Even if the low order N bits of FOO aren't known
12769 to be zero, if the comparison is >= or < we can use the same
12770 optimization and for > or <= by setting all the low
12771 order N bits in the comparison constant. */
12782 {
12783 unsigned HOST_WIDE_INT low_bits
12785 & ((HOST_WIDE_INT_1U
12788 {
12789 /* If the shift was logical, then we must make the condition
12790 unsigned. */
12799 const_op
12804 }
12805 }
12807 /* If we are using this shift to extract just the sign bit, we
12808 can replace this with an LT or GE comparison. */
12813 {
12817 }
12822 }
12825 }
12827 /* Now make any compound operations involved in this comparison. Then,
12828 check for an outmost SUBREG on OP0 that is not doing anything or is
12829 paradoxical. The latter transformation must only be performed when
12830 it is known that the "extra" bits will be the same in op0 and op1 or
12831 that they don't matter. There are three cases to consider:
12833 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12834 care bits and we can assume they have any convenient value. So
12835 making the transformation is safe.
12837 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12838 In this case the upper bits of op0 are undefined. We should not make
12839 the simplification in that case as we do not know the contents of
12840 those bits.
12842 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12843 In that case we know those bits are zeros or ones. We must also be
12844 sure that they are the same as the upper bits of op1.
12846 We can never remove a SUBREG for a non-equality comparison because
12847 the sign bit is in a different place in the underlying object. */
12860 {
12862 {
12863 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12864 implemented. */
12866 {
12869 }
12870 }
12874 {
12879 }
12880 }
12882 /* We now do the opposite procedure: Some machines don't have compare
12883 insns in all modes. If OP0's mode is an integer mode smaller than a
12884 word and we can't do a compare in that mode, see if there is a larger
12885 mode for which we can do the compare. There are a number of cases in
12886 which we can use the wider mode. */
12892 {
12897 {
12900 /* If this is a test for negative, we can make an explicit
12901 test of the sign bit. Test this first so we can use
12902 a paradoxical subreg to extend OP0. */
12906 {
12907 unsigned HOST_WIDE_INT sign
12914 }
12916 /* If the only nonzero bits in OP0 and OP1 are those in the
12917 narrower mode and this is an equality or unsigned comparison,
12918 we can use the wider mode. Similarly for sign-extended
12919 values, in which case it is true for all comparisons. */
12936 {
12937 /* If OP0 is an AND and we don't have an AND in MODE either,
12938 make a new AND in the proper mode. */
12946 else
12947 {
12949 {
12954 }
12955 else
12956 {
12961 }
12963 }
12964 }
12965 }
12966 }
12968 /* We may have changed the comparison operands. Re-canonicalize. */
12970 {
12973 }
12975 /* If this machine only supports a subset of valid comparisons, see if we
12976 can convert an unsupported one into a supported one. */
12983 }
12984 \f
12985 /* Utility function for record_value_for_reg. Count number of
12986 rtxs in X. */
12987 static int
12989 {
12996 {
13016 }
13027 }
13028 \f
13029 /* Utility function for following routine. Called when X is part of a value
13030 being stored into last_set_value. Sets last_set_table_tick
13031 for each register mentioned. Similar to mention_regs in cse.c */
13033 static void
13035 {
13041 {
13047 {
13050 }
13053 }
13057 {
13058 /* Check for identical subexpressions. If x contains
13059 identical subexpression we only have to traverse one of
13060 them. */
13062 {
13063 /* Note that at this point x1 has already been
13064 processed. */
13068 /* If x0 and x1 are identical then there is no need to
13069 process x0. */
13073 /* If x0 is identical to a subexpression of x1 then while
13074 processing x1, x0 has already been processed. Thus we
13075 are done with x. */
13080 /* If x1 is identical to a subexpression of x0 then we
13081 still have to process the rest of x0. */
13084 {
13087 }
13088 }
13091 }
13095 }
13097 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13098 are saying that the register is clobbered and we no longer know its
13099 value. If INSN is zero, don't update reg_stat[].last_set; this is
13100 only permitted with VALUE also zero and is used to invalidate the
13101 register. */
13103 static void
13105 {
13111 /* If VALUE contains REG and we have a previous value for REG, substitute
13112 the previous value. */
13114 {
13115 rtx tem;
13117 /* Set things up so get_last_value is allowed to see anything set up to
13118 our insn. */
13122 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13123 it isn't going to be useful and will take a lot of time to process,
13124 so just use the CLOBBER. */
13127 {
13133 {
13134 /* If there are two or more occurrences of REG in VALUE,
13135 prevent the value from growing too much. */
13138 }
13141 }
13142 }
13144 /* For each register modified, show we don't know its value, that
13145 we don't know about its bitwise content, that its value has been
13146 updated, and that we don't know the location of the death of the
13147 register. */
13149 {
13161 }
13163 /* Mark registers that are being referenced in this value. */
13167 /* Now update the status of each register being set.
13168 If someone is using this register in this block, set this register
13169 to invalid since we will get confused between the two lives in this
13170 basic block. This makes using this register always invalid. In cse, we
13171 scan the table to invalidate all entries using this register, but this
13172 is too much work for us. */
13175 {
13181 else
13183 }
13185 /* The value being assigned might refer to X (like in "x++;"). In that
13186 case, we must replace it with (clobber (const_int 0)) to prevent
13187 infinite loops. */
13190 {
13194 }
13196 /* For the main register being modified, update the value, the mode, the
13197 nonzero bits, and the number of sign bit copies. */
13202 {
13210 rsp->last_set_sign_bit_copies
13212 }
13213 }
13215 /* Called via note_stores from record_dead_and_set_regs to handle one
13216 SET or CLOBBER in an insn. DATA is the instruction in which the
13217 set is occurring. */
13219 static void
13221 {
13228 {
13232 }
13235 {
13236 /* If we are setting the whole register, we know its value. Otherwise
13237 show that we don't know the value. We can handle SUBREG in
13238 some cases. */
13249 else
13251 }
13253 /* Ignore pushes, they clobber nothing. */
13256 }
13258 /* Update the records of when each REG was most recently set or killed
13259 for the things done by INSN. This is the last thing done in processing
13260 INSN in the combiner loop.
13262 We update reg_stat[], in particular fields last_set, last_set_value,
13263 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13264 last_death, and also the similar information mem_last_set (which insn
13265 most recently modified memory) and last_call_luid (which insn was the
13266 most recent subroutine call). */
13268 static void
13270 {
13271 rtx link;
13275 {
13278 {
13283 {
13288 }
13289 }
13292 }
13295 {
13296 hard_reg_set_iterator hrsi;
13298 {
13310 }
13314 /* We can't combine into a call pattern. Remember, though, that
13315 the return value register is set at this LUID. We could
13316 still replace a register with the return value from the
13317 wrong subroutine call! */
13319 }
13320 else
13322 }
13324 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13325 register present in the SUBREG, so for each such SUBREG go back and
13326 adjust nonzero and sign bit information of the registers that are
13327 known to have some zero/sign bits set.
13329 This is needed because when combine blows the SUBREGs away, the
13330 information on zero/sign bits is lost and further combines can be
13331 missed because of that. */
13333 static void
13335 {
13337 rtx set;
13345 {
13354 {
13357 }
13361 {
13364 }
13367 {
13370 }
13371 else
13373 }
13374 }
13376 /* Check if X, a register, is known to contain a value already
13377 truncated to MODE. In this case we can use a subreg to refer to
13378 the truncated value even though in the generic case we would need
13379 an explicit truncation. */
13381 static bool
13383 {
13395 }
13397 /* If X is a hard reg or a subreg record the mode that the register is
13398 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13399 able to turn a truncate into a subreg using this information. Return true
13400 if traversing X is complete. */
13402 static bool
13404 {
13405 machine_mode truncated_mode;
13409 {
13421 }
13422 /* ??? For hard-regs we now record everything. We might be able to
13423 optimize this using last_set_mode. */
13426 else
13433 {
13436 }
13439 }
13441 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13442 the modes they are used in. This can help truning TRUNCATEs into
13443 SUBREGs. */
13445 static void
13447 {
13452 }
13454 /* Scan X for promoted SUBREGs. For each one found,
13455 note what it implies to the registers used in it. */
13457 static void
13459 {
13464 else
13465 {
13471 {
13481 }
13482 }
13483 }
13484 \f
13485 /* Verify that all the registers and memory references mentioned in *LOC are
13486 still valid. *LOC was part of a value set in INSN when label_tick was
13487 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13488 the invalid references with (clobber (const_int 0)) and return 1. This
13489 replacement is useful because we often can get useful information about
13490 the form of a value (e.g., if it was produced by a shift that always
13491 produces -1 or 0) even though we don't know exactly what registers it
13492 was produced from. */
13494 static int
13496 {
13503 {
13509 {
13512 /* If this is a pseudo-register that was only set once and not
13513 live at the beginning of the function, it is always valid. */
13517 && (!REGNO_REG_SET_P
13519 regno)))
13521 {
13525 }
13526 }
13529 }
13530 /* If this is a memory reference, make sure that there were no stores after
13531 it that might have clobbered the value. We don't have alias info, so we
13532 assume any store invalidates it. Moreover, we only have local UIDs, so
13533 we also assume that there were stores in the intervening basic blocks. */
13536 {
13540 }
13543 {
13545 {
13546 /* Check for identical subexpressions. If x contains
13547 identical subexpression we only have to traverse one of
13548 them. */
13550 {
13551 /* Note that at this point x0 has already been checked
13552 and found valid. */
13556 /* If x0 and x1 are identical then x is also valid. */
13560 /* If x1 is identical to a subexpression of x0 then
13561 while checking x0, x1 has already been checked. Thus
13562 it is valid and so as x. */
13567 /* If x0 is identical to a subexpression of x1 then x is
13568 valid iff the rest of x1 is valid. */
13571 return
13575 }
13580 }
13586 }
13588 /* If we haven't found a reason for it to be invalid, it is valid. */
13590 }
13592 /* Get the last value assigned to X, if known. Some registers
13593 in the value may be replaced with (clobber (const_int 0)) if their value
13594 is known longer known reliably. */
13596 static rtx
13598 {
13600 rtx value;
13603 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13604 then convert it to the desired mode. If this is a paradoxical SUBREG,
13605 we cannot predict what values the "extra" bits might have. */
13619 /* If we don't have a value, or if it isn't for this basic block and
13620 it's either a hard register, set more than once, or it's a live
13621 at the beginning of the function, return 0.
13623 Because if it's not live at the beginning of the function then the reg
13624 is always set before being used (is never used without being set).
13625 And, if it's set only once, and it's always set before use, then all
13626 uses must have the same last value, even if it's not from this basic
13627 block. */
13634 || REGNO_REG_SET_P
13638 /* If the value was set in a later insn than the ones we are processing,
13639 we can't use it even if the register was only set once. */
13644 /* If fewer bits were set than what we are asked for now, we cannot use
13645 the value. */
13650 /* If the value has all its registers valid, return it. */
13654 /* Otherwise, make a copy and replace any invalid register with
13655 (clobber (const_int 0)). If that fails for some reason, return 0. */
13662 }
13663 \f
13664 /* Return nonzero if expression X refers to a REG or to memory
13665 that is set in an instruction more recent than FROM_LUID. */
13667 static int
13669 {
13675 {
13679 #ifdef PUSH_ROUNDING
13680 /* Don't allow uses of the stack pointer to be moved,
13681 because we don't know whether the move crosses a push insn. */
13684 #endif
13686 {
13692 }
13694 }
13702 {
13704 {
13709 }
13713 }
13715 }
13716 \f
13717 /* Define three variables used for communication between the following
13718 routines. */
13723 /* Function called via note_stores from reg_dead_at_p.
13725 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13726 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13728 static void
13730 {
13740 }
13742 /* Return nonzero if REG is known to be dead at INSN.
13744 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13745 referencing REG, it is dead. If we hit a SET referencing REG, it is
13746 live. Otherwise, see if it is live or dead at the start of the basic
13747 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13748 must be assumed to be always live. */
13750 static int
13752 {
13753 basic_block block;
13756 /* Set variables for reg_dead_at_p_1. */
13762 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13763 we allow the machine description to decide whether use-and-clobber
13764 patterns are OK. */
13766 {
13770 }
13772 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13773 beginning of basic block. */
13776 {
13778 {
13788 }
13794 }
13796 /* Look at live-in sets for the basic block that we were in. */
13802 }
13803 \f
13804 /* Note hard registers in X that are used. */
13806 static void
13808 {
13814 {
13818 CASE_CONST_ANY:
13823 /* CC0 must die in the insn after it is set, so we don't need to take
13824 special note of it here. */
13829 /* If we are clobbering a MEM, mark any hard registers inside the
13830 address as used. */
13837 /* A hard reg in a wide mode may really be multiple registers.
13838 If so, mark all of them just like the first. */
13840 {
13841 /* None of this applies to the stack, frame or arg pointers. */
13843 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13851 }
13855 {
13856 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13857 the address. */
13869 }
13874 }
13876 /* Recursively scan the operands of this expression. */
13878 {
13882 {
13886 {
13891 }
13892 }
13893 }
13894 }
13895 \f
13896 /* Remove register number REGNO from the dead registers list of INSN.
13898 Return the note used to record the death, if there was one. */
13900 rtx
13902 {
13909 }
13911 /* For each register (hardware or pseudo) used within expression X, if its
13912 death is in an instruction with luid between FROM_LUID (inclusive) and
13913 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13914 list headed by PNOTES.
13916 That said, don't move registers killed by maybe_kill_insn.
13918 This is done when X is being merged by combination into TO_INSN. These
13919 notes will then be distributed as needed. */
13921 static void
13924 {
13930 {
13934 /* Don't move the register if it gets killed in between from and to. */
13943 {
13946 /* It is possible for the call above to return 0. This can occur
13947 when last_death points to I2 or I1 that we combined with.
13948 In that case make a new note.
13950 We must also check for the case where X is a hard register
13951 and NOTE is a death note for a range of hard registers
13952 including X. In that case, we must put REG_DEAD notes for
13953 the remaining registers in place of NOTE. */
13957 {
13966 }
13968 /* If we didn't find any note, or if we found a REG_DEAD note that
13969 covers only part of the given reg, and we have a multi-reg hard
13970 register, then to be safe we must check for REG_DEAD notes
13971 for each register other than the first. They could have
13972 their own REG_DEAD notes lying around. */
13979 {
13986 else
13992 }
13995 {
13998 }
13999 else
14001 }
14004 }
14007 {
14012 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14013 that accesses one word of a multi-word item, some
14014 piece of everything register in the expression is used by
14015 this insn, so remove any old death. */
14016 /* ??? So why do we test for equality of the sizes? */
14022 {
14025 }
14027 /* If this is some other SUBREG, we know it replaces the entire
14028 value, so use that as the destination. */
14032 /* If this is a MEM, adjust deaths of anything used in the address.
14033 For a REG (the only other possibility), the entire value is
14034 being replaced so the old value is not used in this insn. */
14040 }
14049 {
14051 {
14056 }
14059 }
14060 }
14061 \f
14062 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14063 pattern of an insn. X must be a REG. */
14065 static int
14067 {
14071 {
14073 rtx target;
14080 else
14097 }
14105 }
14106 \f
14107 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14108 as appropriate. I3 and I2 are the insns resulting from the combination
14109 insns including FROM (I2 may be zero).
14111 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14112 not need REG_DEAD notes because they are being substituted for. This
14113 saves searching in the most common cases.
14115 Each note in the list is either ignored or placed on some insns, depending
14116 on the type of note. */
14118 static void
14121 {
14123 rtx tem_note;
14127 {
14132 {
14135 /* Doesn't matter much where we put this, as long as it's somewhere.
14136 It is preferable to keep these notes on branches, which is most
14137 likely to be i3. */
14144 else
14145 {
14148 }
14152 /* These notes must remain with the call or trapping instruction. */
14157 else
14158 {
14164 /* ??? Otherwise assume we've combined things such that we
14165 can now prove that the instructions can't trap. Drop the
14166 note in this case. */
14167 }
14171 /* ??? How to distribute between i3-i1. Assume i3 contains the
14172 entire adjustment. Assert i3 contains at least some adjust. */
14174 {
14176 /* fixup_args_size_notes looks at REG_NORETURN note,
14177 so ensure the note is placed there first. */
14179 {
14183 {
14189 }
14190 }
14192 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14193 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14196 && !ACCUMULATE_OUTGOING_ARGS
14198 }
14206 /* These notes must remain with the call. It should not be
14207 possible for both I2 and I3 to be a call. */
14210 else
14211 {
14214 }
14218 /* Any clobbers for i3 may still exist, and so we must process
14219 REG_UNUSED notes from that insn.
14221 Any clobbers from i2 or i1 can only exist if they were added by
14222 recog_for_combine. In that case, recog_for_combine created the
14223 necessary REG_UNUSED notes. Trying to keep any original
14224 REG_UNUSED notes from these insns can cause incorrect output
14225 if it is for the same register as the original i3 dest.
14226 In that case, we will notice that the register is set in i3,
14227 and then add a REG_UNUSED note for the destination of i3, which
14228 is wrong. However, it is possible to have REG_UNUSED notes from
14229 i2 or i1 for register which were both used and clobbered, so
14230 we keep notes from i2 or i1 if they will turn into REG_DEAD
14231 notes. */
14233 /* If this register is set or clobbered in I3, put the note there
14234 unless there is one already. */
14236 {
14244 }
14245 /* Otherwise, if this register is used by I3, then this register
14246 now dies here, so we must put a REG_DEAD note here unless there
14247 is one already. */
14253 {
14256 }
14262 /* These notes say something about results of an insn. We can
14263 only support them if they used to be on I3 in which case they
14264 remain on I3. Otherwise they are ignored.
14266 If the note refers to an expression that is not a constant, we
14267 must also ignore the note since we cannot tell whether the
14268 equivalence is still true. It might be possible to do
14269 slightly better than this (we only have a problem if I2DEST
14270 or I1DEST is present in the expression), but it doesn't
14271 seem worth the trouble. */
14279 /* These notes say something about how a register is used. They must
14280 be present on any use of the register in I2 or I3. */
14285 {
14288 else
14290 }
14295 /* This can show up in several ways -- either directly in the
14296 pattern, or hidden off in the constant pool with (or without?)
14297 a REG_EQUAL note. */
14298 /* ??? Ignore the without-reg_equal-note problem for now. */
14310 {
14313 else
14315 }
14317 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14318 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14319 there. */
14324 {
14331 }
14337 {
14345 }
14349 /* This note says something about the value of a register prior
14350 to the execution of an insn. It is too much trouble to see
14351 if the note is still correct in all situations. It is better
14352 to simply delete it. */
14356 /* If we replaced the right hand side of FROM_INSN with a
14357 REG_EQUAL note, the original use of the dying register
14358 will not have been combined into I3 and I2. In such cases,
14359 FROM_INSN is guaranteed to be the first of the combined
14360 instructions, so we simply need to search back before
14361 FROM_INSN for the previous use or set of this register,
14362 then alter the notes there appropriately.
14364 If the register is used as an input in I3, it dies there.
14365 Similarly for I2, if it is nonzero and adjacent to I3.
14367 If the register is not used as an input in either I3 or I2
14368 and it is not one of the registers we were supposed to eliminate,
14369 there are two possibilities. We might have a non-adjacent I2
14370 or we might have somehow eliminated an additional register
14371 from a computation. For example, we might have had A & B where
14372 we discover that B will always be zero. In this case we will
14373 eliminate the reference to A.
14375 In both cases, we must search to see if we can find a previous
14376 use of A and put the death note there. */
14382 else
14383 {
14389 {
14390 /* If the new I2 sets the same register that is marked
14391 dead in the note, we do not in general know where to
14392 put the note. One important case we _can_ handle is
14393 when the note comes from I3. */
14396 else
14398 }
14405 && !(i2mod
14407 i2mod_old_rhs)))
14412 }
14415 {
14419 {
14421 {
14425 }
14427 /* If the register is being set at TEM_INSN, see if that is all
14428 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14429 into a REG_UNUSED note instead. Don't delete sets to
14430 global register vars. */
14434 {
14445 ;
14447 /* Verify that it was the set, and not a clobber that
14448 modified the register.
14450 CC0 targets must be careful to maintain setter/user
14451 pairs. If we cannot delete the setter due to side
14452 effects, mark the user with an UNUSED note instead
14453 of deleting it. */
14457 && (!HAVE_cc0
14461 {
14462 /* Move the notes and links of TEM_INSN elsewhere.
14463 This might delete other dead insns recursively.
14464 First set the pattern to something that won't use
14465 any register. */
14484 /* Delete the setter too. */
14486 {
14499 }
14500 }
14501 else
14502 {
14505 /* If there isn't already a REG_UNUSED note, put one
14506 here. Do not place a REG_DEAD note, even if
14507 the register is also used here; that would not
14508 match the algorithm used in lifetime analysis
14509 and can cause the consistency check in the
14510 scheduler to fail. */
14515 }
14516 }
14520 {
14523 /* If we are doing a 3->2 combination, and we have a
14524 register which formerly died in i3 and was not used
14525 by i2, which now no longer dies in i3 and is used in
14526 i2 but does not die in i2, and place is between i2
14527 and i3, then we may need to move a link from place to
14528 i2. */
14530 && from_insn
14533 {
14537 }
14539 }
14543 }
14545 }
14547 /* If the register is set or already dead at PLACE, we needn't do
14548 anything with this note if it is still a REG_DEAD note.
14549 We check here if it is set at all, not if is it totally replaced,
14550 which is what `dead_or_set_p' checks, so also check for it being
14551 set partially. */
14554 {
14560 {
14561 /* Unless the register previously died in PLACE, clear
14562 last_death. [I no longer understand why this is
14563 being done.] */
14567 }
14568 else
14571 /* If this is a death note for a hard reg that is occupying
14572 multiple registers, ensure that we are still using all
14573 parts of the object. If we find a piece of the object
14574 that is unused, we must arrange for an appropriate REG_DEAD
14575 note to be added for it. However, we can't just emit a USE
14576 and tag the note to it, since the register might actually
14577 be dead; so we recourse, and the recursive call then finds
14578 the previous insn that used this register. */
14581 {
14590 {
14593 }
14596 {
14597 /* Put only REG_DEAD notes for pieces that are
14598 not already dead or set. */
14602 {
14609 {
14611 NULL_RTX);
14615 NULL_RTX);
14616 }
14621 {
14623 {
14627 }
14631 {
14634 }
14635 }
14636 }
14639 }
14640 }
14641 }
14645 /* Any other notes should not be present at this point in the
14646 compilation. */
14648 }
14651 {
14655 /* Set added_notes_insn to the earliest insn we added a note to. */
14659 }
14662 {
14665 /* Set added_notes_insn to the earliest insn we added a note to. */
14669 }
14670 }
14671 }
14672 \f
14673 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14674 I3, I2, and I1 to new locations. This is also called to add a link
14675 pointing at I3 when I3's destination is changed. */
14677 static void
14679 {
14683 {
14690 /* If the insn that this link points to is a NOTE, ignore it. */
14699 {
14702 {
14718 }
14721 }
14722 else
14732 /* A LOG_LINK is defined as being placed on the first insn that uses
14733 a register and points to the insn that sets the register. Start
14734 searching at the next insn after the target of the link and stop
14735 when we reach a set of the register or the end of the basic block.
14737 Note that this correctly handles the link that used to point from
14738 I3 to I2. Also note that not much searching is typically done here
14739 since most links don't point very far away. */
14748 {
14752 }
14755 {
14758 }
14762 /* If we found a place to put the link, place it there unless there
14763 is already a link to the same insn as LINK at that point. */
14766 {
14774 {
14778 /* Set added_links_insn to the earliest insn we added a
14779 link to. */
14783 }
14784 }
14785 }
14786 }
14787 \f
14788 /* Check for any register or memory mentioned in EQUIV that is not
14789 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14790 of EXPR where some registers may have been replaced by constants. */
14792 static bool
14794 {
14797 {
14802 }
14804 }
14805 \f
14806 DEBUG_FUNCTION void
14808 {
14809 fprintf
14811 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14813 }
14815 void
14817 {
14818 fprintf
14820 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14822 }
14823 \f
14824 /* Try combining insns through substitution. */
14825 static unsigned int
14827 {
14837 rebuild_jump_labels_after_combine
14840 /* Combining insns may have turned an indirect jump into a
14841 direct jump. Rebuild the JUMP_LABEL fields of jumping
14842 instructions. */
14844 {
14851 }
14855 }
14860 {
14870 };
14873 {
14877 {}
14879 /* opt_pass methods: */
14882 {
14884 }
14890 rtl_opt_pass *
14892 {
14894 }