1 ;; Scheduling description for IBM POWER5 processor.
2 ;; Copyright (C) 2003-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 3, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Sources: IBM Red Book and White Paper on POWER5
22 ;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
23 ;; Instructions that update more than one register get broken into two
24 ;; (split) or more internal ops. The chip can issue up to 5
25 ;; internal ops per cycle.
27 (define_automaton "power5iu,power5fpu,power5misc")
29 (define_cpu_unit "iu1_power5,iu2_power5" "power5iu")
30 (define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc")
31 (define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu")
32 (define_cpu_unit "bpu_power5,cru_power5" "power5misc")
33 (define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5"
36 (define_reservation "lsq_power5"
37 "(du1_power5,lsu1_power5)\
38 |(du2_power5,lsu2_power5)\
39 |(du3_power5,lsu2_power5)\
40 |(du4_power5,lsu1_power5)")
42 (define_reservation "iq_power5"
43 "(du1_power5|du2_power5|du3_power5|du4_power5),\
44 (iu1_power5|iu2_power5)")
46 (define_reservation "fpq_power5"
47 "(du1_power5|du2_power5|du3_power5|du4_power5),\
48 (fpu1_power5|fpu2_power5)")
50 ; Dispatch slots are allocated in order conforming to program order.
51 (absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
52 (absence_set "du2_power5" "du3_power5,du4_power5,du5_power5")
53 (absence_set "du3_power5" "du4_power5,du5_power5")
54 (absence_set "du4_power5" "du5_power5")
58 (define_insn_reservation "power5-load" 4 ; 3
59 (and (eq_attr "type" "load")
60 (eq_attr "sign_extend" "no")
61 (eq_attr "update" "no")
62 (eq_attr "cpu" "power5"))
65 (define_insn_reservation "power5-load-ext" 5
66 (and (eq_attr "type" "load")
67 (eq_attr "sign_extend" "yes")
68 (eq_attr "update" "no")
69 (eq_attr "cpu" "power5"))
70 "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5")
72 (define_insn_reservation "power5-load-ext-update" 5
73 (and (eq_attr "type" "load")
74 (eq_attr "sign_extend" "yes")
75 (eq_attr "update" "yes")
76 (eq_attr "indexed" "no")
77 (eq_attr "cpu" "power5"))
78 "du1_power5+du2_power5+du3_power5+du4_power5,\
79 lsu1_power5+iu2_power5,nothing,nothing,iu2_power5")
81 (define_insn_reservation "power5-load-ext-update-indexed" 5
82 (and (eq_attr "type" "load")
83 (eq_attr "sign_extend" "yes")
84 (eq_attr "update" "yes")
85 (eq_attr "indexed" "yes")
86 (eq_attr "cpu" "power5"))
87 "du1_power5+du2_power5+du3_power5+du4_power5,\
88 iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5")
90 (define_insn_reservation "power5-load-update-indexed" 3
91 (and (eq_attr "type" "load")
92 (eq_attr "sign_extend" "no")
93 (eq_attr "update" "yes")
94 (eq_attr "indexed" "yes")
95 (eq_attr "cpu" "power5"))
96 "du1_power5+du2_power5+du3_power5+du4_power5,\
97 iu1_power5,lsu2_power5+iu2_power5")
99 (define_insn_reservation "power5-load-update" 4 ; 3
100 (and (eq_attr "type" "load")
101 (eq_attr "sign_extend" "no")
102 (eq_attr "update" "yes")
103 (eq_attr "indexed" "no")
104 (eq_attr "cpu" "power5"))
105 "du1_power5+du2_power5,lsu1_power5+iu2_power5")
107 (define_insn_reservation "power5-fpload" 6 ; 5
108 (and (eq_attr "type" "fpload")
109 (eq_attr "update" "no")
110 (eq_attr "cpu" "power5"))
113 (define_insn_reservation "power5-fpload-update" 6 ; 5
114 (and (eq_attr "type" "fpload")
115 (eq_attr "update" "yes")
116 (eq_attr "cpu" "power5"))
117 "du1_power5+du2_power5,lsu1_power5+iu2_power5")
119 (define_insn_reservation "power5-store" 12
120 (and (eq_attr "type" "store")
121 (eq_attr "update" "no")
122 (eq_attr "cpu" "power5"))
123 "((du1_power5,lsu1_power5)\
124 |(du2_power5,lsu2_power5)\
125 |(du3_power5,lsu2_power5)\
126 |(du4_power5,lsu1_power5)),\
127 (iu1_power5|iu2_power5)")
129 (define_insn_reservation "power5-store-update" 12
130 (and (eq_attr "type" "store")
131 (eq_attr "update" "yes")
132 (eq_attr "indexed" "no")
133 (eq_attr "cpu" "power5"))
134 "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
136 (define_insn_reservation "power5-store-update-indexed" 12
137 (and (eq_attr "type" "store")
138 (eq_attr "update" "yes")
139 (eq_attr "indexed" "yes")
140 (eq_attr "cpu" "power5"))
141 "du1_power5+du2_power5+du3_power5+du4_power5,\
142 iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
144 (define_insn_reservation "power5-fpstore" 12
145 (and (eq_attr "type" "fpstore")
146 (eq_attr "update" "no")
147 (eq_attr "cpu" "power5"))
148 "((du1_power5,lsu1_power5)\
149 |(du2_power5,lsu2_power5)\
150 |(du3_power5,lsu2_power5)\
151 |(du4_power5,lsu1_power5)),\
152 (fpu1_power5|fpu2_power5)")
154 (define_insn_reservation "power5-fpstore-update" 12
155 (and (eq_attr "type" "fpstore")
156 (eq_attr "update" "yes")
157 (eq_attr "cpu" "power5"))
158 "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
160 (define_insn_reservation "power5-llsc" 11
161 (and (eq_attr "type" "load_l,store_c,sync")
162 (eq_attr "cpu" "power5"))
163 "du1_power5+du2_power5+du3_power5+du4_power5,\
167 ; Integer latency is 2 cycles
168 (define_insn_reservation "power5-integer" 2
169 (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel,popcnt")
170 (and (eq_attr "type" "shift")
171 (eq_attr "dot" "no"))
172 (and (eq_attr "type" "insert")
173 (eq_attr "size" "64")))
174 (eq_attr "cpu" "power5"))
177 (define_insn_reservation "power5-two" 2
178 (and (eq_attr "type" "two")
179 (eq_attr "cpu" "power5"))
180 "((du1_power5+du2_power5)\
181 |(du2_power5+du3_power5)\
182 |(du3_power5+du4_power5)\
183 |(du4_power5+du1_power5)),\
184 ((iu1_power5,nothing,iu2_power5)\
185 |(iu2_power5,nothing,iu2_power5)\
186 |(iu2_power5,nothing,iu1_power5)\
187 |(iu1_power5,nothing,iu1_power5))")
189 (define_insn_reservation "power5-three" 2
190 (and (eq_attr "type" "three")
191 (eq_attr "cpu" "power5"))
192 "(du1_power5+du2_power5+du3_power5|du2_power5+du3_power5+du4_power5\
193 |du3_power5+du4_power5+du1_power5|du4_power5+du1_power5+du2_power5),\
194 ((iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
195 |(iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
196 |(iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
197 |(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))")
199 (define_insn_reservation "power5-insert" 4
200 (and (eq_attr "type" "insert")
201 (eq_attr "size" "32")
202 (eq_attr "cpu" "power5"))
203 "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
205 (define_insn_reservation "power5-cmp" 3
206 (and (eq_attr "type" "cmp,fast_compare")
207 (eq_attr "cpu" "power5"))
210 (define_insn_reservation "power5-compare" 2
211 (and (ior (eq_attr "type" "compare")
212 (and (eq_attr "type" "shift")
213 (eq_attr "dot" "yes")))
214 (eq_attr "cpu" "power5"))
215 "du1_power5+du2_power5,iu1_power5,iu2_power5")
217 (define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
219 (define_insn_reservation "power5-lmul-cmp" 7
220 (and (eq_attr "type" "mul")
221 (eq_attr "dot" "yes")
222 (eq_attr "size" "64")
223 (eq_attr "cpu" "power5"))
224 "du1_power5+du2_power5,iu1_power5*6,iu2_power5")
226 (define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
228 (define_insn_reservation "power5-imul-cmp" 5
229 (and (eq_attr "type" "mul")
230 (eq_attr "dot" "yes")
231 (eq_attr "size" "32")
232 (eq_attr "cpu" "power5"))
233 "du1_power5+du2_power5,iu1_power5*4,iu2_power5")
235 (define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
237 (define_insn_reservation "power5-lmul" 7
238 (and (eq_attr "type" "mul")
240 (eq_attr "size" "64")
241 (eq_attr "cpu" "power5"))
242 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*6|iu2_power5*6)")
244 (define_insn_reservation "power5-imul" 5
245 (and (eq_attr "type" "mul")
247 (eq_attr "size" "32")
248 (eq_attr "cpu" "power5"))
249 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*4|iu2_power5*4)")
251 (define_insn_reservation "power5-imul3" 4
252 (and (eq_attr "type" "mul")
253 (eq_attr "size" "8,16")
254 (eq_attr "cpu" "power5"))
255 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*3|iu2_power5*3)")
258 ; SPR move only executes in first IU.
259 ; Integer division only executes in second IU.
260 (define_insn_reservation "power5-idiv" 36
261 (and (eq_attr "type" "div")
262 (eq_attr "size" "32")
263 (eq_attr "cpu" "power5"))
264 "du1_power5+du2_power5,iu2_power5*35")
266 (define_insn_reservation "power5-ldiv" 68
267 (and (eq_attr "type" "div")
268 (eq_attr "size" "64")
269 (eq_attr "cpu" "power5"))
270 "du1_power5+du2_power5,iu2_power5*67")
273 (define_insn_reservation "power5-mtjmpr" 3
274 (and (eq_attr "type" "mtjmpr,mfjmpr")
275 (eq_attr "cpu" "power5"))
276 "du1_power5,bpu_power5")
279 ; Branches take dispatch Slot 4. The presence_sets prevent other insn from
280 ; grabbing previous dispatch slots once this is assigned.
281 (define_insn_reservation "power5-branch" 2
282 (and (eq_attr "type" "jmpreg,branch")
283 (eq_attr "cpu" "power5"))
285 |du4_power5+du5_power5\
286 |du3_power5+du4_power5+du5_power5\
287 |du2_power5+du3_power5+du4_power5+du5_power5\
288 |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5")
291 ; Condition Register logical ops are split if non-destructive (RT != RB)
292 (define_insn_reservation "power5-crlogical" 2
293 (and (eq_attr "type" "cr_logical")
294 (eq_attr "cpu" "power5"))
295 "du1_power5,cru_power5")
297 (define_insn_reservation "power5-delayedcr" 4
298 (and (eq_attr "type" "delayed_cr")
299 (eq_attr "cpu" "power5"))
300 "du1_power5+du2_power5,cru_power5,cru_power5")
302 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
303 (define_insn_reservation "power5-mfcr" 6
304 (and (eq_attr "type" "mfcr")
305 (eq_attr "cpu" "power5"))
306 "du1_power5+du2_power5+du3_power5+du4_power5,\
307 du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\
308 cru_power5,cru_power5,cru_power5")
311 (define_insn_reservation "power5-mfcrf" 3
312 (and (eq_attr "type" "mfcrf")
313 (eq_attr "cpu" "power5"))
314 "du1_power5,cru_power5")
317 (define_insn_reservation "power5-mtcr" 4
318 (and (eq_attr "type" "mtcr")
319 (eq_attr "cpu" "power5"))
320 "du1_power5,iu1_power5")
322 ; Basic FP latency is 6 cycles
323 (define_insn_reservation "power5-fp" 6
324 (and (eq_attr "type" "fp,dmul")
325 (eq_attr "cpu" "power5"))
328 (define_insn_reservation "power5-fpcompare" 5
329 (and (eq_attr "type" "fpcompare")
330 (eq_attr "cpu" "power5"))
333 (define_insn_reservation "power5-sdiv" 33
334 (and (eq_attr "type" "sdiv,ddiv")
335 (eq_attr "cpu" "power5"))
336 "(du1_power5|du2_power5|du3_power5|du4_power5),\
337 (fpu1_power5*28|fpu2_power5*28)")
339 (define_insn_reservation "power5-sqrt" 40
340 (and (eq_attr "type" "ssqrt,dsqrt")
341 (eq_attr "cpu" "power5"))
342 "(du1_power5|du2_power5|du3_power5|du4_power5),\
343 (fpu1_power5*35|fpu2_power5*35)")
345 (define_insn_reservation "power5-isync" 2
346 (and (eq_attr "type" "isync")
347 (eq_attr "cpu" "power5"))
348 "du1_power5+du2_power5+du3_power5+du4_power5,\