1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
26 #include "rtl-error.h"
28 #include "insn-config.h"
29 #include "insn-attr.h"
30 #include "hard-reg-set.h"
33 #include "addresses.h"
37 #include "basic-block.h"
40 #include "tree-pass.h"
42 #include "insn-codes.h"
44 #ifndef STACK_PUSH_CODE
45 #ifdef STACK_GROWS_DOWNWARD
46 #define STACK_PUSH_CODE PRE_DEC
48 #define STACK_PUSH_CODE PRE_INC
52 #ifndef STACK_POP_CODE
53 #ifdef STACK_GROWS_DOWNWARD
54 #define STACK_POP_CODE POST_INC
56 #define STACK_POP_CODE POST_DEC
60 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx
, bool);
61 static void validate_replace_src_1 (rtx
*, void *);
62 static rtx
split_insn (rtx
);
64 struct target_recog default_target_recog
;
66 struct target_recog
*this_target_recog
= &default_target_recog
;
69 /* Nonzero means allow operands to be volatile.
70 This should be 0 if you are generating rtl, such as if you are calling
71 the functions in optabs.c and expmed.c (most of the time).
72 This should be 1 if all valid insns need to be recognized,
73 such as in reginfo.c and final.c and reload.c.
75 init_recog and init_recog_no_volatile are responsible for setting this. */
79 struct recog_data_d recog_data
;
81 /* Contains a vector of operand_alternative structures for every operand.
82 Set up by preprocess_constraints. */
83 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
85 /* On return from `constrain_operands', indicate which alternative
88 int which_alternative
;
90 /* Nonzero after end of reload pass.
91 Set to 1 or 0 by toplev.c.
92 Controls the significance of (SUBREG (MEM)). */
96 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
97 int epilogue_completed
;
99 /* Initialize data used by the function `recog'.
100 This must be called once in the compilation of a function
101 before any insn recognition may be done in the function. */
104 init_recog_no_volatile (void)
116 /* Return true if labels in asm operands BODY are LABEL_REFs. */
119 asm_labels_ok (rtx body
)
124 asmop
= extract_asm_operands (body
);
125 if (asmop
== NULL_RTX
)
128 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
129 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
135 /* Check that X is an insn-body for an `asm' with operands
136 and that the operands mentioned in it are legitimate. */
139 check_asm_operands (rtx x
)
143 const char **constraints
;
146 if (!asm_labels_ok (x
))
149 /* Post-reload, be more strict with things. */
150 if (reload_completed
)
152 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
153 extract_insn (make_insn_raw (x
));
154 constrain_operands (1);
155 return which_alternative
>= 0;
158 noperands
= asm_noperands (x
);
164 operands
= XALLOCAVEC (rtx
, noperands
);
165 constraints
= XALLOCAVEC (const char *, noperands
);
167 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
169 for (i
= 0; i
< noperands
; i
++)
171 const char *c
= constraints
[i
];
174 if (! asm_operand_ok (operands
[i
], c
, constraints
))
181 /* Static data for the next two routines. */
183 typedef struct change_t
192 static change_t
*changes
;
193 static int changes_allocated
;
195 static int num_changes
= 0;
197 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
198 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
199 the change is simply made.
201 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
202 will be called with the address and mode as parameters. If OBJECT is
203 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
206 IN_GROUP is nonzero if this is part of a group of changes that must be
207 performed as a group. In that case, the changes will be stored. The
208 function `apply_change_group' will validate and apply the changes.
210 If IN_GROUP is zero, this is a single change. Try to recognize the insn
211 or validate the memory reference with the change applied. If the result
212 is not valid for the machine, suppress the change and return zero.
213 Otherwise, perform the change and return 1. */
216 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
220 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
223 gcc_assert (in_group
!= 0 || num_changes
== 0);
227 /* Save the information describing this change. */
228 if (num_changes
>= changes_allocated
)
230 if (changes_allocated
== 0)
231 /* This value allows for repeated substitutions inside complex
232 indexed addresses, or changes in up to 5 insns. */
233 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
235 changes_allocated
*= 2;
237 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
240 changes
[num_changes
].object
= object
;
241 changes
[num_changes
].loc
= loc
;
242 changes
[num_changes
].old
= old
;
243 changes
[num_changes
].unshare
= unshare
;
245 if (object
&& !MEM_P (object
))
247 /* Set INSN_CODE to force rerecognition of insn. Save old code in
249 changes
[num_changes
].old_code
= INSN_CODE (object
);
250 INSN_CODE (object
) = -1;
255 /* If we are making a group of changes, return 1. Otherwise, validate the
256 change group we made. */
261 return apply_change_group ();
264 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
268 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
270 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
273 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
277 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
279 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
283 /* Keep X canonicalized if some changes have made it non-canonical; only
284 modifies the operands of X, not (for example) its code. Simplifications
285 are not the job of this routine.
287 Return true if anything was changed. */
289 canonicalize_change_group (rtx insn
, rtx x
)
291 if (COMMUTATIVE_P (x
)
292 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
294 /* Oops, the caller has made X no longer canonical.
295 Let's redo the changes in the correct order. */
296 rtx tem
= XEXP (x
, 0);
297 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
298 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
306 /* This subroutine of apply_change_group verifies whether the changes to INSN
307 were valid; i.e. whether INSN can still be recognized.
309 If IN_GROUP is true clobbers which have to be added in order to
310 match the instructions will be added to the current change group.
311 Otherwise the changes will take effect immediately. */
314 insn_invalid_p (rtx insn
, bool in_group
)
316 rtx pat
= PATTERN (insn
);
317 int num_clobbers
= 0;
318 /* If we are before reload and the pattern is a SET, see if we can add
320 int icode
= recog (pat
, insn
,
321 (GET_CODE (pat
) == SET
322 && ! reload_completed
323 && ! reload_in_progress
)
324 ? &num_clobbers
: 0);
325 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
328 /* If this is an asm and the operand aren't legal, then fail. Likewise if
329 this is not an asm and the insn wasn't recognized. */
330 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
331 || (!is_asm
&& icode
< 0))
334 /* If we have to add CLOBBERs, fail if we have to add ones that reference
335 hard registers since our callers can't know if they are live or not.
336 Otherwise, add them. */
337 if (num_clobbers
> 0)
341 if (added_clobbers_hard_reg_p (icode
))
344 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
345 XVECEXP (newpat
, 0, 0) = pat
;
346 add_clobbers (newpat
, icode
);
348 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
350 PATTERN (insn
) = pat
= newpat
;
353 /* After reload, verify that all constraints are satisfied. */
354 if (reload_completed
)
358 if (! constrain_operands (1))
362 INSN_CODE (insn
) = icode
;
366 /* Return number of changes made and not validated yet. */
368 num_changes_pending (void)
373 /* Tentatively apply the changes numbered NUM and up.
374 Return 1 if all changes are valid, zero otherwise. */
377 verify_changes (int num
)
380 rtx last_validated
= NULL_RTX
;
382 /* The changes have been applied and all INSN_CODEs have been reset to force
385 The changes are valid if we aren't given an object, or if we are
386 given a MEM and it still is a valid address, or if this is in insn
387 and it is recognized. In the latter case, if reload has completed,
388 we also require that the operands meet the constraints for
391 for (i
= num
; i
< num_changes
; i
++)
393 rtx object
= changes
[i
].object
;
395 /* If there is no object to test or if it is the same as the one we
396 already tested, ignore it. */
397 if (object
== 0 || object
== last_validated
)
402 if (! memory_address_addr_space_p (GET_MODE (object
),
404 MEM_ADDR_SPACE (object
)))
407 else if (/* changes[i].old might be zero, e.g. when putting a
408 REG_FRAME_RELATED_EXPR into a previously empty list. */
410 && REG_P (changes
[i
].old
)
411 && asm_noperands (PATTERN (object
)) > 0
412 && REG_EXPR (changes
[i
].old
) != NULL_TREE
413 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
414 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
416 /* Don't allow changes of hard register operands to inline
417 assemblies if they have been defined as register asm ("x"). */
420 else if (DEBUG_INSN_P (object
))
422 else if (insn_invalid_p (object
, true))
424 rtx pat
= PATTERN (object
);
426 /* Perhaps we couldn't recognize the insn because there were
427 extra CLOBBERs at the end. If so, try to re-recognize
428 without the last CLOBBER (later iterations will cause each of
429 them to be eliminated, in turn). But don't do this if we
430 have an ASM_OPERAND. */
431 if (GET_CODE (pat
) == PARALLEL
432 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
433 && asm_noperands (PATTERN (object
)) < 0)
437 if (XVECLEN (pat
, 0) == 2)
438 newpat
= XVECEXP (pat
, 0, 0);
444 = gen_rtx_PARALLEL (VOIDmode
,
445 rtvec_alloc (XVECLEN (pat
, 0) - 1));
446 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
447 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
450 /* Add a new change to this group to replace the pattern
451 with this new pattern. Then consider this change
452 as having succeeded. The change we added will
453 cause the entire call to fail if things remain invalid.
455 Note that this can lose if a later change than the one
456 we are processing specified &XVECEXP (PATTERN (object), 0, X)
457 but this shouldn't occur. */
459 validate_change (object
, &PATTERN (object
), newpat
, 1);
462 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
463 || GET_CODE (pat
) == VAR_LOCATION
)
464 /* If this insn is a CLOBBER or USE, it is always valid, but is
470 last_validated
= object
;
473 return (i
== num_changes
);
476 /* A group of changes has previously been issued with validate_change
477 and verified with verify_changes. Call df_insn_rescan for each of
478 the insn changed and clear num_changes. */
481 confirm_change_group (void)
484 rtx last_object
= NULL
;
486 for (i
= 0; i
< num_changes
; i
++)
488 rtx object
= changes
[i
].object
;
490 if (changes
[i
].unshare
)
491 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
493 /* Avoid unnecessary rescanning when multiple changes to same instruction
497 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
498 df_insn_rescan (last_object
);
499 last_object
= object
;
503 if (last_object
&& INSN_P (last_object
))
504 df_insn_rescan (last_object
);
508 /* Apply a group of changes previously issued with `validate_change'.
509 If all changes are valid, call confirm_change_group and return 1,
510 otherwise, call cancel_changes and return 0. */
513 apply_change_group (void)
515 if (verify_changes (0))
517 confirm_change_group ();
528 /* Return the number of changes so far in the current group. */
531 num_validated_changes (void)
536 /* Retract the changes numbered NUM and up. */
539 cancel_changes (int num
)
543 /* Back out all the changes. Do this in the opposite order in which
545 for (i
= num_changes
- 1; i
>= num
; i
--)
547 *changes
[i
].loc
= changes
[i
].old
;
548 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
549 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
554 /* Reduce conditional compilation elsewhere. */
557 #define CODE_FOR_extv CODE_FOR_nothing
561 #define CODE_FOR_extzv CODE_FOR_nothing
564 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
568 simplify_while_replacing (rtx
*loc
, rtx to
, rtx object
,
569 enum machine_mode op0_mode
)
572 enum rtx_code code
= GET_CODE (x
);
573 rtx new_rtx
= NULL_RTX
;
575 if (SWAPPABLE_OPERANDS_P (x
)
576 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
578 validate_unshare_change (object
, loc
,
579 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
580 : swap_condition (code
),
581 GET_MODE (x
), XEXP (x
, 1),
587 /* Canonicalize arithmetics with all constant operands. */
588 switch (GET_RTX_CLASS (code
))
591 if (CONSTANT_P (XEXP (x
, 0)))
592 new_rtx
= simplify_unary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
597 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
598 new_rtx
= simplify_binary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
602 case RTX_COMM_COMPARE
:
603 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
604 new_rtx
= simplify_relational_operation (code
, GET_MODE (x
), op0_mode
,
605 XEXP (x
, 0), XEXP (x
, 1));
612 validate_change (object
, loc
, new_rtx
, 1);
619 /* If we have a PLUS whose second operand is now a CONST_INT, use
620 simplify_gen_binary to try to simplify it.
621 ??? We may want later to remove this, once simplification is
622 separated from this function. */
623 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
624 validate_change (object
, loc
,
626 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
629 if (CONST_SCALAR_INT_P (XEXP (x
, 1)))
630 validate_change (object
, loc
,
632 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
633 simplify_gen_unary (NEG
,
634 GET_MODE (x
), XEXP (x
, 1),
639 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
641 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
643 /* If any of the above failed, substitute in something that
644 we know won't be recognized. */
646 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
647 validate_change (object
, loc
, new_rtx
, 1);
651 /* All subregs possible to simplify should be simplified. */
652 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
655 /* Subregs of VOIDmode operands are incorrect. */
656 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
657 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
659 validate_change (object
, loc
, new_rtx
, 1);
663 /* If we are replacing a register with memory, try to change the memory
664 to be the mode required for memory in extract operations (this isn't
665 likely to be an insertion operation; if it was, nothing bad will
666 happen, we might just fail in some cases). */
668 if (MEM_P (XEXP (x
, 0))
669 && CONST_INT_P (XEXP (x
, 1))
670 && CONST_INT_P (XEXP (x
, 2))
671 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0),
672 MEM_ADDR_SPACE (XEXP (x
, 0)))
673 && !MEM_VOLATILE_P (XEXP (x
, 0)))
675 enum machine_mode wanted_mode
= VOIDmode
;
676 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
677 int pos
= INTVAL (XEXP (x
, 2));
679 if (GET_CODE (x
) == ZERO_EXTRACT
&& HAVE_extzv
)
681 wanted_mode
= insn_data
[CODE_FOR_extzv
].operand
[1].mode
;
682 if (wanted_mode
== VOIDmode
)
683 wanted_mode
= word_mode
;
685 else if (GET_CODE (x
) == SIGN_EXTRACT
&& HAVE_extv
)
687 wanted_mode
= insn_data
[CODE_FOR_extv
].operand
[1].mode
;
688 if (wanted_mode
== VOIDmode
)
689 wanted_mode
= word_mode
;
692 /* If we have a narrower mode, we can do something. */
693 if (wanted_mode
!= VOIDmode
694 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
696 int offset
= pos
/ BITS_PER_UNIT
;
699 /* If the bytes and bits are counted differently, we
700 must adjust the offset. */
701 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
703 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
706 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
707 == GET_MODE_BITSIZE (wanted_mode
));
708 pos
%= GET_MODE_BITSIZE (wanted_mode
);
710 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
712 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
713 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
724 /* Replace every occurrence of FROM in X with TO. Mark each change with
725 validate_change passing OBJECT. */
728 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx object
,
735 enum machine_mode op0_mode
= VOIDmode
;
736 int prev_changes
= num_changes
;
742 fmt
= GET_RTX_FORMAT (code
);
744 op0_mode
= GET_MODE (XEXP (x
, 0));
746 /* X matches FROM if it is the same rtx or they are both referring to the
747 same register in the same mode. Avoid calling rtx_equal_p unless the
748 operands look similar. */
751 || (REG_P (x
) && REG_P (from
)
752 && GET_MODE (x
) == GET_MODE (from
)
753 && REGNO (x
) == REGNO (from
))
754 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
755 && rtx_equal_p (x
, from
)))
757 validate_unshare_change (object
, loc
, to
, 1);
761 /* Call ourself recursively to perform the replacements.
762 We must not replace inside already replaced expression, otherwise we
763 get infinite recursion for replacements like (reg X)->(subreg (reg X))
764 so we must special case shared ASM_OPERANDS. */
766 if (GET_CODE (x
) == PARALLEL
)
768 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
770 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
771 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
773 /* Verify that operands are really shared. */
774 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
775 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
777 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
778 from
, to
, object
, simplify
);
781 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
786 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
789 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
790 else if (fmt
[i
] == 'E')
791 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
792 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
796 /* If we didn't substitute, there is nothing more to do. */
797 if (num_changes
== prev_changes
)
800 /* ??? The regmove is no more, so is this aberration still necessary? */
801 /* Allow substituted expression to have different mode. This is used by
802 regmove to change mode of pseudo register. */
803 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
804 op0_mode
= GET_MODE (XEXP (x
, 0));
806 /* Do changes needed to keep rtx consistent. Don't do any other
807 simplifications, as it is not our job. */
809 simplify_while_replacing (loc
, to
, object
, op0_mode
);
812 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
813 with TO. After all changes have been made, validate by seeing
814 if INSN is still valid. */
817 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx insn
, rtx
*loc
)
819 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
820 return apply_change_group ();
823 /* Try replacing every occurrence of FROM in INSN with TO. After all
824 changes have been made, validate by seeing if INSN is still valid. */
827 validate_replace_rtx (rtx from
, rtx to
, rtx insn
)
829 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
830 return apply_change_group ();
833 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
834 is a part of INSN. After all changes have been made, validate by seeing if
836 validate_replace_rtx (from, to, insn) is equivalent to
837 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
840 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx insn
)
842 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
843 return apply_change_group ();
846 /* Same as above, but do not simplify rtx afterwards. */
848 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
851 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
852 return apply_change_group ();
856 /* Try replacing every occurrence of FROM in INSN with TO. This also
857 will replace in REG_EQUAL and REG_EQUIV notes. */
860 validate_replace_rtx_group (rtx from
, rtx to
, rtx insn
)
863 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
864 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
865 if (REG_NOTE_KIND (note
) == REG_EQUAL
866 || REG_NOTE_KIND (note
) == REG_EQUIV
)
867 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
870 /* Function called by note_uses to replace used subexpressions. */
871 struct validate_replace_src_data
873 rtx from
; /* Old RTX */
874 rtx to
; /* New RTX */
875 rtx insn
; /* Insn in which substitution is occurring. */
879 validate_replace_src_1 (rtx
*x
, void *data
)
881 struct validate_replace_src_data
*d
882 = (struct validate_replace_src_data
*) data
;
884 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
887 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
891 validate_replace_src_group (rtx from
, rtx to
, rtx insn
)
893 struct validate_replace_src_data d
;
898 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
901 /* Try simplify INSN.
902 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
903 pattern and return true if something was simplified. */
906 validate_simplify_insn (rtx insn
)
912 pat
= PATTERN (insn
);
914 if (GET_CODE (pat
) == SET
)
916 newpat
= simplify_rtx (SET_SRC (pat
));
917 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
918 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
919 newpat
= simplify_rtx (SET_DEST (pat
));
920 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
921 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
923 else if (GET_CODE (pat
) == PARALLEL
)
924 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
926 rtx s
= XVECEXP (pat
, 0, i
);
928 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
930 newpat
= simplify_rtx (SET_SRC (s
));
931 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
932 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
933 newpat
= simplify_rtx (SET_DEST (s
));
934 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
935 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
938 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
942 /* Return 1 if the insn using CC0 set by INSN does not contain
943 any ordered tests applied to the condition codes.
944 EQ and NE tests do not count. */
947 next_insn_tests_no_inequality (rtx insn
)
949 rtx next
= next_cc0_user (insn
);
951 /* If there is no next insn, we have to take the conservative choice. */
955 return (INSN_P (next
)
956 && ! inequality_comparisons_p (PATTERN (next
)));
960 /* Return 1 if OP is a valid general operand for machine mode MODE.
961 This is either a register reference, a memory reference,
962 or a constant. In the case of a memory reference, the address
963 is checked for general validity for the target machine.
965 Register and memory references must have mode MODE in order to be valid,
966 but some constants have no machine mode and are valid for any mode.
968 If MODE is VOIDmode, OP is checked for validity for whatever mode
971 The main use of this function is as a predicate in match_operand
972 expressions in the machine description. */
975 general_operand (rtx op
, enum machine_mode mode
)
977 enum rtx_code code
= GET_CODE (op
);
979 if (mode
== VOIDmode
)
980 mode
= GET_MODE (op
);
982 /* Don't accept CONST_INT or anything similar
983 if the caller wants something floating. */
984 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
985 && GET_MODE_CLASS (mode
) != MODE_INT
986 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
991 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
995 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
997 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
998 && targetm
.legitimate_constant_p (mode
== VOIDmode
1002 /* Except for certain constants with VOIDmode, already checked for,
1003 OP's mode must match MODE if MODE specifies a mode. */
1005 if (GET_MODE (op
) != mode
)
1010 rtx sub
= SUBREG_REG (op
);
1012 #ifdef INSN_SCHEDULING
1013 /* On machines that have insn scheduling, we want all memory
1014 reference to be explicit, so outlaw paradoxical SUBREGs.
1015 However, we must allow them after reload so that they can
1016 get cleaned up by cleanup_subreg_operands. */
1017 if (!reload_completed
&& MEM_P (sub
)
1018 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
1021 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1022 may result in incorrect reference. We should simplify all valid
1023 subregs of MEM anyway. But allow this after reload because we
1024 might be called from cleanup_subreg_operands.
1026 ??? This is a kludge. */
1027 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
1031 #ifdef CANNOT_CHANGE_MODE_CLASS
1033 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1034 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1035 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1036 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
1037 /* LRA can generate some invalid SUBREGS just for matched
1038 operand reload presentation. LRA needs to treat them as
1040 && ! LRA_SUBREG_P (op
))
1044 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1045 create such rtl, and we must reject it. */
1046 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1047 /* LRA can use subreg to store a floating point value in an
1048 integer mode. Although the floating point and the
1049 integer modes need the same number of hard registers, the
1050 size of floating point mode can be less than the integer
1052 && ! lra_in_progress
1053 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1057 code
= GET_CODE (op
);
1061 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1062 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1066 rtx y
= XEXP (op
, 0);
1068 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1071 /* Use the mem's mode, since it will be reloaded thus. LRA can
1072 generate move insn with invalid addresses which is made valid
1073 and efficiently calculated by LRA through further numerous
1076 || memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1083 /* Return 1 if OP is a valid memory address for a memory reference
1086 The main use of this function is as a predicate in match_operand
1087 expressions in the machine description. */
1090 address_operand (rtx op
, enum machine_mode mode
)
1092 return memory_address_p (mode
, op
);
1095 /* Return 1 if OP is a register reference of mode MODE.
1096 If MODE is VOIDmode, accept a register in any mode.
1098 The main use of this function is as a predicate in match_operand
1099 expressions in the machine description. */
1102 register_operand (rtx op
, enum machine_mode mode
)
1104 if (GET_CODE (op
) == SUBREG
)
1106 rtx sub
= SUBREG_REG (op
);
1108 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1109 because it is guaranteed to be reloaded into one.
1110 Just make sure the MEM is valid in itself.
1111 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1112 but currently it does result from (SUBREG (REG)...) where the
1113 reg went on the stack.) */
1114 if (!REG_P (sub
) && (reload_completed
|| !MEM_P (sub
)))
1117 else if (!REG_P (op
))
1119 return general_operand (op
, mode
);
1122 /* Return 1 for a register in Pmode; ignore the tested mode. */
1125 pmode_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1127 return register_operand (op
, Pmode
);
1130 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1131 or a hard register. */
1134 scratch_operand (rtx op
, enum machine_mode mode
)
1136 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1139 return (GET_CODE (op
) == SCRATCH
1141 && (lra_in_progress
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)));
1144 /* Return 1 if OP is a valid immediate operand for mode MODE.
1146 The main use of this function is as a predicate in match_operand
1147 expressions in the machine description. */
1150 immediate_operand (rtx op
, enum machine_mode mode
)
1152 /* Don't accept CONST_INT or anything similar
1153 if the caller wants something floating. */
1154 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1155 && GET_MODE_CLASS (mode
) != MODE_INT
1156 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1159 if (CONST_INT_P (op
)
1161 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1164 return (CONSTANT_P (op
)
1165 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1166 || GET_MODE (op
) == VOIDmode
)
1167 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1168 && targetm
.legitimate_constant_p (mode
== VOIDmode
1173 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1176 const_int_operand (rtx op
, enum machine_mode mode
)
1178 if (!CONST_INT_P (op
))
1181 if (mode
!= VOIDmode
1182 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1188 #if TARGET_SUPPORTS_WIDE_INT
1189 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1192 const_scalar_int_operand (rtx op
, enum machine_mode mode
)
1194 if (!CONST_SCALAR_INT_P (op
))
1197 if (CONST_INT_P (op
))
1198 return const_int_operand (op
, mode
);
1200 if (mode
!= VOIDmode
)
1202 int prec
= GET_MODE_PRECISION (mode
);
1203 int bitsize
= GET_MODE_BITSIZE (mode
);
1205 if (CONST_WIDE_INT_NUNITS (op
) * HOST_BITS_PER_WIDE_INT
> bitsize
)
1208 if (prec
== bitsize
)
1212 /* Multiword partial int. */
1214 = CONST_WIDE_INT_ELT (op
, CONST_WIDE_INT_NUNITS (op
) - 1);
1215 return (sext_hwi (x
, prec
& (HOST_BITS_PER_WIDE_INT
- 1)) == x
);
1221 /* Returns 1 if OP is an operand that is a constant integer or constant
1222 floating-point number of MODE. */
1225 const_double_operand (rtx op
, enum machine_mode mode
)
1227 return (GET_CODE (op
) == CONST_DOUBLE
)
1228 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
);
1231 /* Returns 1 if OP is an operand that is a constant integer or constant
1232 floating-point number of MODE. */
1235 const_double_operand (rtx op
, enum machine_mode mode
)
1237 /* Don't accept CONST_INT or anything similar
1238 if the caller wants something floating. */
1239 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1240 && GET_MODE_CLASS (mode
) != MODE_INT
1241 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1244 return ((CONST_DOUBLE_P (op
) || CONST_INT_P (op
))
1245 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1246 || GET_MODE (op
) == VOIDmode
));
1249 /* Return 1 if OP is a general operand that is not an immediate
1250 operand of mode MODE. */
1253 nonimmediate_operand (rtx op
, enum machine_mode mode
)
1255 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1258 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1261 nonmemory_operand (rtx op
, enum machine_mode mode
)
1263 if (CONSTANT_P (op
))
1264 return immediate_operand (op
, mode
);
1265 return register_operand (op
, mode
);
1268 /* Return 1 if OP is a valid operand that stands for pushing a
1269 value of mode MODE onto the stack.
1271 The main use of this function is as a predicate in match_operand
1272 expressions in the machine description. */
1275 push_operand (rtx op
, enum machine_mode mode
)
1277 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1279 #ifdef PUSH_ROUNDING
1280 rounded_size
= PUSH_ROUNDING (rounded_size
);
1286 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1291 if (rounded_size
== GET_MODE_SIZE (mode
))
1293 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1298 if (GET_CODE (op
) != PRE_MODIFY
1299 || GET_CODE (XEXP (op
, 1)) != PLUS
1300 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1301 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1302 #ifdef STACK_GROWS_DOWNWARD
1303 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1305 || INTVAL (XEXP (XEXP (op
, 1), 1)) != (int) rounded_size
1311 return XEXP (op
, 0) == stack_pointer_rtx
;
1314 /* Return 1 if OP is a valid operand that stands for popping a
1315 value of mode MODE off the stack.
1317 The main use of this function is as a predicate in match_operand
1318 expressions in the machine description. */
1321 pop_operand (rtx op
, enum machine_mode mode
)
1326 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1331 if (GET_CODE (op
) != STACK_POP_CODE
)
1334 return XEXP (op
, 0) == stack_pointer_rtx
;
1337 /* Return 1 if ADDR is a valid memory address
1338 for mode MODE in address space AS. */
1341 memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1342 rtx addr
, addr_space_t as
)
1344 #ifdef GO_IF_LEGITIMATE_ADDRESS
1345 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1346 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1352 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1356 /* Return 1 if OP is a valid memory reference with mode MODE,
1357 including a valid address.
1359 The main use of this function is as a predicate in match_operand
1360 expressions in the machine description. */
1363 memory_operand (rtx op
, enum machine_mode mode
)
1367 if (! reload_completed
)
1368 /* Note that no SUBREG is a memory operand before end of reload pass,
1369 because (SUBREG (MEM...)) forces reloading into a register. */
1370 return MEM_P (op
) && general_operand (op
, mode
);
1372 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1376 if (GET_CODE (inner
) == SUBREG
)
1377 inner
= SUBREG_REG (inner
);
1379 return (MEM_P (inner
) && general_operand (op
, mode
));
1382 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1383 that is, a memory reference whose address is a general_operand. */
1386 indirect_operand (rtx op
, enum machine_mode mode
)
1388 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1389 if (! reload_completed
1390 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1392 int offset
= SUBREG_BYTE (op
);
1393 rtx inner
= SUBREG_REG (op
);
1395 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1398 /* The only way that we can have a general_operand as the resulting
1399 address is if OFFSET is zero and the address already is an operand
1400 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1403 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1404 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1405 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1406 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1407 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1411 && memory_operand (op
, mode
)
1412 && general_operand (XEXP (op
, 0), Pmode
));
1415 /* Return 1 if this is an ordered comparison operator (not including
1416 ORDERED and UNORDERED). */
1419 ordered_comparison_operator (rtx op
, enum machine_mode mode
)
1421 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1423 switch (GET_CODE (op
))
1441 /* Return 1 if this is a comparison operator. This allows the use of
1442 MATCH_OPERATOR to recognize all the branch insns. */
1445 comparison_operator (rtx op
, enum machine_mode mode
)
1447 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1448 && COMPARISON_P (op
));
1451 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1454 extract_asm_operands (rtx body
)
1457 switch (GET_CODE (body
))
1463 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1464 tmp
= SET_SRC (body
);
1465 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1470 tmp
= XVECEXP (body
, 0, 0);
1471 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1473 if (GET_CODE (tmp
) == SET
)
1475 tmp
= SET_SRC (tmp
);
1476 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1487 /* If BODY is an insn body that uses ASM_OPERANDS,
1488 return the number of operands (both input and output) in the insn.
1489 Otherwise return -1. */
1492 asm_noperands (const_rtx body
)
1494 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1500 if (GET_CODE (body
) == SET
)
1502 else if (GET_CODE (body
) == PARALLEL
)
1505 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1507 /* Multiple output operands, or 1 output plus some clobbers:
1509 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1510 /* Count backwards through CLOBBERs to determine number of SETs. */
1511 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1513 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1515 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1519 /* N_SETS is now number of output operands. */
1522 /* Verify that all the SETs we have
1523 came from a single original asm_operands insn
1524 (so that invalid combinations are blocked). */
1525 for (i
= 0; i
< n_sets
; i
++)
1527 rtx elt
= XVECEXP (body
, 0, i
);
1528 if (GET_CODE (elt
) != SET
)
1530 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1532 /* If these ASM_OPERANDS rtx's came from different original insns
1533 then they aren't allowed together. */
1534 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1535 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1541 /* 0 outputs, but some clobbers:
1542 body is [(asm_operands ...) (clobber (reg ...))...]. */
1543 /* Make sure all the other parallel things really are clobbers. */
1544 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1545 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1550 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1551 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1554 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1555 copy its operands (both input and output) into the vector OPERANDS,
1556 the locations of the operands within the insn into the vector OPERAND_LOCS,
1557 and the constraints for the operands into CONSTRAINTS.
1558 Write the modes of the operands into MODES.
1559 Return the assembler-template.
1561 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1562 we don't store that info. */
1565 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1566 const char **constraints
, enum machine_mode
*modes
,
1569 int nbase
= 0, n
, i
;
1572 switch (GET_CODE (body
))
1575 /* Zero output asm: BODY is (asm_operands ...). */
1580 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1581 asmop
= SET_SRC (body
);
1583 /* The output is in the SET.
1584 Its constraint is in the ASM_OPERANDS itself. */
1586 operands
[0] = SET_DEST (body
);
1588 operand_locs
[0] = &SET_DEST (body
);
1590 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1592 modes
[0] = GET_MODE (SET_DEST (body
));
1598 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1600 asmop
= XVECEXP (body
, 0, 0);
1601 if (GET_CODE (asmop
) == SET
)
1603 asmop
= SET_SRC (asmop
);
1605 /* At least one output, plus some CLOBBERs. The outputs are in
1606 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1607 for (i
= 0; i
< nparallel
; i
++)
1609 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1610 break; /* Past last SET */
1612 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1614 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1616 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1618 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1629 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1630 for (i
= 0; i
< n
; i
++)
1633 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1635 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1637 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1639 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1643 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1644 for (i
= 0; i
< n
; i
++)
1647 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1649 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1651 constraints
[nbase
+ i
] = "";
1653 modes
[nbase
+ i
] = Pmode
;
1657 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1659 return ASM_OPERANDS_TEMPLATE (asmop
);
1662 /* Parse inline assembly string STRING and determine which operands are
1663 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1664 to true if operand I is referenced.
1666 This is intended to distinguish barrier-like asms such as:
1668 asm ("" : "=m" (...));
1670 from real references such as:
1672 asm ("sw\t$0, %0" : "=m" (...)); */
1675 get_referenced_operands (const char *string
, bool *used
,
1676 unsigned int noperands
)
1678 memset (used
, 0, sizeof (bool) * noperands
);
1679 const char *p
= string
;
1685 /* A letter followed by a digit indicates an operand number. */
1686 if (ISALPHA (p
[0]) && ISDIGIT (p
[1]))
1691 unsigned long opnum
= strtoul (p
, &endptr
, 10);
1692 if (endptr
!= p
&& opnum
< noperands
)
1706 /* Check if an asm_operand matches its constraints.
1707 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1710 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1714 bool incdec_ok
= false;
1717 /* Use constrain_operands after reload. */
1718 gcc_assert (!reload_completed
);
1720 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1721 many alternatives as required to match the other operands. */
1722 if (*constraint
== '\0')
1727 char c
= *constraint
;
1744 case '0': case '1': case '2': case '3': case '4':
1745 case '5': case '6': case '7': case '8': case '9':
1746 /* If caller provided constraints pointer, look up
1747 the matching constraint. Otherwise, our caller should have
1748 given us the proper matching constraint, but we can't
1749 actually fail the check if they didn't. Indicate that
1750 results are inconclusive. */
1754 unsigned long match
;
1756 match
= strtoul (constraint
, &end
, 10);
1758 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1759 constraint
= (const char *) end
;
1765 while (ISDIGIT (*constraint
));
1772 if (address_operand (op
, VOIDmode
))
1776 case TARGET_MEM_CONSTRAINT
:
1777 case 'V': /* non-offsettable */
1778 if (memory_operand (op
, VOIDmode
))
1782 case 'o': /* offsettable */
1783 if (offsettable_nonstrict_memref_p (op
))
1788 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed to exist,
1789 excepting those that expand_call created. Further, on some
1790 machines which do not have generalized auto inc/dec, an inc/dec
1791 is not a memory_operand.
1793 Match any memory and hope things are resolved after reload. */
1797 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1798 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1808 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1809 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1818 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1819 || (GET_CODE (op
) == CONST_VECTOR
1820 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
1825 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1826 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', constraint
))
1830 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1831 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'H', constraint
))
1836 if (CONST_SCALAR_INT_P (op
))
1841 if (CONSTANT_P (op
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1846 if (CONST_SCALAR_INT_P (op
))
1851 if (CONST_INT_P (op
)
1852 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'I', constraint
))
1856 if (CONST_INT_P (op
)
1857 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'J', constraint
))
1861 if (CONST_INT_P (op
)
1862 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'K', constraint
))
1866 if (CONST_INT_P (op
)
1867 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'L', constraint
))
1871 if (CONST_INT_P (op
)
1872 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'M', constraint
))
1876 if (CONST_INT_P (op
)
1877 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'N', constraint
))
1881 if (CONST_INT_P (op
)
1882 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'O', constraint
))
1886 if (CONST_INT_P (op
)
1887 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'P', constraint
))
1896 if (general_operand (op
, VOIDmode
))
1901 /* For all other letters, we first check for a register class,
1902 otherwise it is an EXTRA_CONSTRAINT. */
1903 if (REG_CLASS_FROM_CONSTRAINT (c
, constraint
) != NO_REGS
)
1906 if (GET_MODE (op
) == BLKmode
)
1908 if (register_operand (op
, VOIDmode
))
1911 #ifdef EXTRA_CONSTRAINT_STR
1912 else if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
))
1913 /* Every memory operand can be reloaded to fit. */
1914 result
= result
|| memory_operand (op
, VOIDmode
);
1915 else if (EXTRA_ADDRESS_CONSTRAINT (c
, constraint
))
1916 /* Every address operand can be reloaded to fit. */
1917 result
= result
|| address_operand (op
, VOIDmode
);
1918 else if (EXTRA_CONSTRAINT_STR (op
, c
, constraint
))
1923 len
= CONSTRAINT_LEN (c
, constraint
);
1926 while (--len
&& *constraint
);
1932 /* For operands without < or > constraints reject side-effects. */
1933 if (!incdec_ok
&& result
&& MEM_P (op
))
1934 switch (GET_CODE (XEXP (op
, 0)))
1951 /* Given an rtx *P, if it is a sum containing an integer constant term,
1952 return the location (type rtx *) of the pointer to that constant term.
1953 Otherwise, return a null pointer. */
1956 find_constant_term_loc (rtx
*p
)
1959 enum rtx_code code
= GET_CODE (*p
);
1961 /* If *P IS such a constant term, P is its location. */
1963 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1967 /* Otherwise, if not a sum, it has no constant term. */
1969 if (GET_CODE (*p
) != PLUS
)
1972 /* If one of the summands is constant, return its location. */
1974 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1975 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1978 /* Otherwise, check each summand for containing a constant term. */
1980 if (XEXP (*p
, 0) != 0)
1982 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1987 if (XEXP (*p
, 1) != 0)
1989 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1997 /* Return 1 if OP is a memory reference
1998 whose address contains no side effects
1999 and remains valid after the addition
2000 of a positive integer less than the
2001 size of the object being referenced.
2003 We assume that the original address is valid and do not check it.
2005 This uses strict_memory_address_p as a subroutine, so
2006 don't use it before reload. */
2009 offsettable_memref_p (rtx op
)
2011 return ((MEM_P (op
))
2012 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
2013 MEM_ADDR_SPACE (op
)));
2016 /* Similar, but don't require a strictly valid mem ref:
2017 consider pseudo-regs valid as index or base regs. */
2020 offsettable_nonstrict_memref_p (rtx op
)
2022 return ((MEM_P (op
))
2023 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
2024 MEM_ADDR_SPACE (op
)));
2027 /* Return 1 if Y is a memory address which contains no side effects
2028 and would remain valid for address space AS after the addition of
2029 a positive integer less than the size of that mode.
2031 We assume that the original address is valid and do not check it.
2032 We do check that it is valid for narrower modes.
2034 If STRICTP is nonzero, we require a strictly valid address,
2035 for the sake of use in reload.c. */
2038 offsettable_address_addr_space_p (int strictp
, enum machine_mode mode
, rtx y
,
2041 enum rtx_code ycode
= GET_CODE (y
);
2045 int (*addressp
) (enum machine_mode
, rtx
, addr_space_t
) =
2046 (strictp
? strict_memory_address_addr_space_p
2047 : memory_address_addr_space_p
);
2048 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
2050 if (CONSTANT_ADDRESS_P (y
))
2053 /* Adjusting an offsettable address involves changing to a narrower mode.
2054 Make sure that's OK. */
2056 if (mode_dependent_address_p (y
, as
))
2059 enum machine_mode address_mode
= GET_MODE (y
);
2060 if (address_mode
== VOIDmode
)
2061 address_mode
= targetm
.addr_space
.address_mode (as
);
2062 #ifdef POINTERS_EXTEND_UNSIGNED
2063 enum machine_mode pointer_mode
= targetm
.addr_space
.pointer_mode (as
);
2066 /* ??? How much offset does an offsettable BLKmode reference need?
2067 Clearly that depends on the situation in which it's being used.
2068 However, the current situation in which we test 0xffffffff is
2069 less than ideal. Caveat user. */
2071 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
2073 /* If the expression contains a constant term,
2074 see if it remains valid when max possible offset is added. */
2076 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
2081 *y2
= plus_constant (address_mode
, *y2
, mode_sz
- 1);
2082 /* Use QImode because an odd displacement may be automatically invalid
2083 for any wider mode. But it should be valid for a single byte. */
2084 good
= (*addressp
) (QImode
, y
, as
);
2086 /* In any case, restore old contents of memory. */
2091 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
2094 /* The offset added here is chosen as the maximum offset that
2095 any instruction could need to add when operating on something
2096 of the specified mode. We assume that if Y and Y+c are
2097 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2098 go inside a LO_SUM here, so we do so as well. */
2099 if (GET_CODE (y
) == LO_SUM
2101 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
2102 z
= gen_rtx_LO_SUM (address_mode
, XEXP (y
, 0),
2103 plus_constant (address_mode
, XEXP (y
, 1),
2105 #ifdef POINTERS_EXTEND_UNSIGNED
2106 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2107 else if (POINTERS_EXTEND_UNSIGNED
> 0
2108 && GET_CODE (y
) == ZERO_EXTEND
2109 && GET_MODE (XEXP (y
, 0)) == pointer_mode
)
2110 z
= gen_rtx_ZERO_EXTEND (address_mode
,
2111 plus_constant (pointer_mode
, XEXP (y
, 0),
2115 z
= plus_constant (address_mode
, y
, mode_sz
- 1);
2117 /* Use QImode because an odd displacement may be automatically invalid
2118 for any wider mode. But it should be valid for a single byte. */
2119 return (*addressp
) (QImode
, z
, as
);
2122 /* Return 1 if ADDR is an address-expression whose effect depends
2123 on the mode of the memory reference it is used in.
2125 ADDRSPACE is the address space associated with the address.
2127 Autoincrement addressing is a typical example of mode-dependence
2128 because the amount of the increment depends on the mode. */
2131 mode_dependent_address_p (rtx addr
, addr_space_t addrspace
)
2133 /* Auto-increment addressing with anything other than post_modify
2134 or pre_modify always introduces a mode dependency. Catch such
2135 cases now instead of deferring to the target. */
2136 if (GET_CODE (addr
) == PRE_INC
2137 || GET_CODE (addr
) == POST_INC
2138 || GET_CODE (addr
) == PRE_DEC
2139 || GET_CODE (addr
) == POST_DEC
)
2142 return targetm
.mode_dependent_address_p (addr
, addrspace
);
2145 /* Return the mask of operand alternatives that are allowed for INSN.
2146 This mask depends only on INSN and on the current target; it does not
2147 depend on things like the values of operands. */
2150 get_enabled_alternatives (rtx insn
)
2152 /* Quick exit for asms and for targets that don't use the "enabled"
2154 int code
= INSN_CODE (insn
);
2155 if (code
< 0 || !HAVE_ATTR_enabled
)
2156 return ALL_ALTERNATIVES
;
2158 /* Calling get_attr_enabled can be expensive, so cache the mask
2160 if (this_target_recog
->x_enabled_alternatives
[code
])
2161 return this_target_recog
->x_enabled_alternatives
[code
];
2163 /* Temporarily install enough information for get_attr_enabled to assume
2164 that the insn operands are already cached. As above, the attribute
2165 mustn't depend on the values of operands, so we don't provide their
2166 real values here. */
2167 rtx old_insn
= recog_data
.insn
;
2168 int old_alternative
= which_alternative
;
2170 recog_data
.insn
= insn
;
2171 alternative_mask enabled
= ALL_ALTERNATIVES
;
2172 int n_alternatives
= insn_data
[code
].n_alternatives
;
2173 for (int i
= 0; i
< n_alternatives
; i
++)
2175 which_alternative
= i
;
2176 if (!get_attr_enabled (insn
))
2177 enabled
&= ~ALTERNATIVE_BIT (i
);
2180 recog_data
.insn
= old_insn
;
2181 which_alternative
= old_alternative
;
2183 this_target_recog
->x_enabled_alternatives
[code
] = enabled
;
2187 /* Like extract_insn, but save insn extracted and don't extract again, when
2188 called again for the same insn expecting that recog_data still contain the
2189 valid information. This is used primary by gen_attr infrastructure that
2190 often does extract insn again and again. */
2192 extract_insn_cached (rtx insn
)
2194 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2196 extract_insn (insn
);
2197 recog_data
.insn
= insn
;
2200 /* Do cached extract_insn, constrain_operands and complain about failures.
2201 Used by insn_attrtab. */
2203 extract_constrain_insn_cached (rtx insn
)
2205 extract_insn_cached (insn
);
2206 if (which_alternative
== -1
2207 && !constrain_operands (reload_completed
))
2208 fatal_insn_not_found (insn
);
2211 /* Do cached constrain_operands and complain about failures. */
2213 constrain_operands_cached (int strict
)
2215 if (which_alternative
== -1)
2216 return constrain_operands (strict
);
2221 /* Analyze INSN and fill in recog_data. */
2224 extract_insn (rtx insn
)
2229 rtx body
= PATTERN (insn
);
2231 recog_data
.n_operands
= 0;
2232 recog_data
.n_alternatives
= 0;
2233 recog_data
.n_dups
= 0;
2234 recog_data
.is_asm
= false;
2236 switch (GET_CODE (body
))
2247 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2252 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2253 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2254 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2260 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2263 /* This insn is an `asm' with operands. */
2265 /* expand_asm_operands makes sure there aren't too many operands. */
2266 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2268 /* Now get the operand values and constraints out of the insn. */
2269 decode_asm_operands (body
, recog_data
.operand
,
2270 recog_data
.operand_loc
,
2271 recog_data
.constraints
,
2272 recog_data
.operand_mode
, NULL
);
2273 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2276 const char *p
= recog_data
.constraints
[0];
2277 recog_data
.n_alternatives
= 1;
2279 recog_data
.n_alternatives
+= (*p
++ == ',');
2281 recog_data
.is_asm
= true;
2284 fatal_insn_not_found (insn
);
2288 /* Ordinary insn: recognize it, get the operands via insn_extract
2289 and get the constraints. */
2291 icode
= recog_memoized (insn
);
2293 fatal_insn_not_found (insn
);
2295 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2296 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2297 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2299 insn_extract (insn
);
2301 for (i
= 0; i
< noperands
; i
++)
2303 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2304 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2305 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2306 /* VOIDmode match_operands gets mode from their real operand. */
2307 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2308 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2311 for (i
= 0; i
< noperands
; i
++)
2312 recog_data
.operand_type
[i
]
2313 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2314 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2317 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2319 recog_data
.enabled_alternatives
= get_enabled_alternatives (insn
);
2321 recog_data
.insn
= NULL
;
2322 which_alternative
= -1;
2325 /* After calling extract_insn, you can use this function to extract some
2326 information from the constraint strings into a more usable form.
2327 The collected data is stored in recog_op_alt. */
2329 preprocess_constraints (void)
2333 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2334 memset (recog_op_alt
[i
], 0, (recog_data
.n_alternatives
2335 * sizeof (struct operand_alternative
)));
2337 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2340 struct operand_alternative
*op_alt
;
2341 const char *p
= recog_data
.constraints
[i
];
2343 op_alt
= recog_op_alt
[i
];
2345 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2347 op_alt
[j
].cl
= NO_REGS
;
2348 op_alt
[j
].constraint
= p
;
2349 op_alt
[j
].matches
= -1;
2350 op_alt
[j
].matched
= -1;
2352 if (!TEST_BIT (recog_data
.enabled_alternatives
, j
))
2354 p
= skip_alternative (p
);
2358 if (*p
== '\0' || *p
== ',')
2360 op_alt
[j
].anything_ok
= 1;
2370 while (c
!= ',' && c
!= '\0');
2371 if (c
== ',' || c
== '\0')
2379 case '=': case '+': case '*': case '%':
2380 case 'E': case 'F': case 'G': case 'H':
2381 case 's': case 'i': case 'n':
2382 case 'I': case 'J': case 'K': case 'L':
2383 case 'M': case 'N': case 'O': case 'P':
2384 /* These don't say anything we care about. */
2388 op_alt
[j
].reject
+= 6;
2391 op_alt
[j
].reject
+= 600;
2394 op_alt
[j
].earlyclobber
= 1;
2397 case '0': case '1': case '2': case '3': case '4':
2398 case '5': case '6': case '7': case '8': case '9':
2401 op_alt
[j
].matches
= strtoul (p
, &end
, 10);
2402 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2407 case TARGET_MEM_CONSTRAINT
:
2408 op_alt
[j
].memory_ok
= 1;
2411 op_alt
[j
].decmem_ok
= 1;
2414 op_alt
[j
].incmem_ok
= 1;
2417 op_alt
[j
].nonoffmem_ok
= 1;
2420 op_alt
[j
].offmem_ok
= 1;
2423 op_alt
[j
].anything_ok
= 1;
2427 op_alt
[j
].is_address
= 1;
2428 op_alt
[j
].cl
= reg_class_subunion
[(int) op_alt
[j
].cl
]
2429 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2436 reg_class_subunion
[(int) op_alt
[j
].cl
][(int) GENERAL_REGS
];
2440 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
2442 op_alt
[j
].memory_ok
= 1;
2445 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2447 op_alt
[j
].is_address
= 1;
2449 = (reg_class_subunion
2450 [(int) op_alt
[j
].cl
]
2451 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2452 ADDRESS
, SCRATCH
)]);
2457 = (reg_class_subunion
2458 [(int) op_alt
[j
].cl
]
2459 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
2462 p
+= CONSTRAINT_LEN (c
, p
);
2468 /* Check the operands of an insn against the insn's operand constraints
2469 and return 1 if they are valid.
2470 The information about the insn's operands, constraints, operand modes
2471 etc. is obtained from the global variables set up by extract_insn.
2473 WHICH_ALTERNATIVE is set to a number which indicates which
2474 alternative of constraints was matched: 0 for the first alternative,
2475 1 for the next, etc.
2477 In addition, when two operands are required to match
2478 and it happens that the output operand is (reg) while the
2479 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2480 make the output operand look like the input.
2481 This is because the output operand is the one the template will print.
2483 This is used in final, just before printing the assembler code and by
2484 the routines that determine an insn's attribute.
2486 If STRICT is a positive nonzero value, it means that we have been
2487 called after reload has been completed. In that case, we must
2488 do all checks strictly. If it is zero, it means that we have been called
2489 before reload has completed. In that case, we first try to see if we can
2490 find an alternative that matches strictly. If not, we try again, this
2491 time assuming that reload will fix up the insn. This provides a "best
2492 guess" for the alternative and is used to compute attributes of insns prior
2493 to reload. A negative value of STRICT is used for this internal call. */
2501 constrain_operands (int strict
)
2503 const char *constraints
[MAX_RECOG_OPERANDS
];
2504 int matching_operands
[MAX_RECOG_OPERANDS
];
2505 int earlyclobber
[MAX_RECOG_OPERANDS
];
2508 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2509 int funny_match_index
;
2511 which_alternative
= 0;
2512 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2515 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2517 constraints
[c
] = recog_data
.constraints
[c
];
2518 matching_operands
[c
] = -1;
2523 int seen_earlyclobber_at
= -1;
2526 funny_match_index
= 0;
2528 if (!TEST_BIT (recog_data
.enabled_alternatives
, which_alternative
))
2532 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2533 constraints
[i
] = skip_alternative (constraints
[i
]);
2535 which_alternative
++;
2539 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2541 rtx op
= recog_data
.operand
[opno
];
2542 enum machine_mode mode
= GET_MODE (op
);
2543 const char *p
= constraints
[opno
];
2549 earlyclobber
[opno
] = 0;
2551 /* A unary operator may be accepted by the predicate, but it
2552 is irrelevant for matching constraints. */
2556 if (GET_CODE (op
) == SUBREG
)
2558 if (REG_P (SUBREG_REG (op
))
2559 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2560 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2561 GET_MODE (SUBREG_REG (op
)),
2564 op
= SUBREG_REG (op
);
2567 /* An empty constraint or empty alternative
2568 allows anything which matched the pattern. */
2569 if (*p
== 0 || *p
== ',')
2573 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2582 case '?': case '!': case '*': case '%':
2587 /* Ignore rest of this alternative as far as
2588 constraint checking is concerned. */
2591 while (*p
&& *p
!= ',');
2596 earlyclobber
[opno
] = 1;
2597 if (seen_earlyclobber_at
< 0)
2598 seen_earlyclobber_at
= opno
;
2601 case '0': case '1': case '2': case '3': case '4':
2602 case '5': case '6': case '7': case '8': case '9':
2604 /* This operand must be the same as a previous one.
2605 This kind of constraint is used for instructions such
2606 as add when they take only two operands.
2608 Note that the lower-numbered operand is passed first.
2610 If we are not testing strictly, assume that this
2611 constraint will be satisfied. */
2616 match
= strtoul (p
, &end
, 10);
2623 rtx op1
= recog_data
.operand
[match
];
2624 rtx op2
= recog_data
.operand
[opno
];
2626 /* A unary operator may be accepted by the predicate,
2627 but it is irrelevant for matching constraints. */
2629 op1
= XEXP (op1
, 0);
2631 op2
= XEXP (op2
, 0);
2633 val
= operands_match_p (op1
, op2
);
2636 matching_operands
[opno
] = match
;
2637 matching_operands
[match
] = opno
;
2642 /* If output is *x and input is *--x, arrange later
2643 to change the output to *--x as well, since the
2644 output op is the one that will be printed. */
2645 if (val
== 2 && strict
> 0)
2647 funny_match
[funny_match_index
].this_op
= opno
;
2648 funny_match
[funny_match_index
++].other
= match
;
2655 /* p is used for address_operands. When we are called by
2656 gen_reload, no one will have checked that the address is
2657 strictly valid, i.e., that all pseudos requiring hard regs
2658 have gotten them. */
2660 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2665 /* No need to check general_operand again;
2666 it was done in insn-recog.c. Well, except that reload
2667 doesn't check the validity of its replacements, but
2668 that should only matter when there's a bug. */
2670 /* Anything goes unless it is a REG and really has a hard reg
2671 but the hard reg is not in the class GENERAL_REGS. */
2675 || GENERAL_REGS
== ALL_REGS
2676 || (reload_in_progress
2677 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2678 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2681 else if (strict
< 0 || general_operand (op
, mode
))
2686 /* This is used for a MATCH_SCRATCH in the cases when
2687 we don't actually need anything. So anything goes
2692 case TARGET_MEM_CONSTRAINT
:
2693 /* Memory operands must be valid, to the extent
2694 required by STRICT. */
2698 && !strict_memory_address_addr_space_p
2699 (GET_MODE (op
), XEXP (op
, 0),
2700 MEM_ADDR_SPACE (op
)))
2703 && !memory_address_addr_space_p
2704 (GET_MODE (op
), XEXP (op
, 0),
2705 MEM_ADDR_SPACE (op
)))
2709 /* Before reload, accept what reload can turn into mem. */
2710 else if (strict
< 0 && CONSTANT_P (op
))
2712 /* During reload, accept a pseudo */
2713 else if (reload_in_progress
&& REG_P (op
)
2714 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2720 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2721 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2727 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2728 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2734 if (CONST_DOUBLE_AS_FLOAT_P (op
)
2735 || (GET_CODE (op
) == CONST_VECTOR
2736 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
2742 if (CONST_DOUBLE_AS_FLOAT_P (op
)
2743 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
2748 if (CONST_SCALAR_INT_P (op
))
2751 if (CONSTANT_P (op
))
2756 if (CONST_SCALAR_INT_P (op
))
2768 if (CONST_INT_P (op
)
2769 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
2775 && ((strict
> 0 && ! offsettable_memref_p (op
))
2777 && !(CONSTANT_P (op
) || MEM_P (op
)))
2778 || (reload_in_progress
2780 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2785 if ((strict
> 0 && offsettable_memref_p (op
))
2786 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2787 /* Before reload, accept what reload can handle. */
2789 && (CONSTANT_P (op
) || MEM_P (op
)))
2790 /* During reload, accept a pseudo */
2791 || (reload_in_progress
&& REG_P (op
)
2792 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2801 ? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c
, p
));
2807 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2808 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2810 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2813 #ifdef EXTRA_CONSTRAINT_STR
2814 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2817 else if (EXTRA_MEMORY_CONSTRAINT (c
, p
)
2818 /* Every memory operand can be reloaded to fit. */
2819 && ((strict
< 0 && MEM_P (op
))
2820 /* Before reload, accept what reload can turn
2822 || (strict
< 0 && CONSTANT_P (op
))
2823 /* During reload, accept a pseudo */
2824 || (reload_in_progress
&& REG_P (op
)
2825 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2827 else if (EXTRA_ADDRESS_CONSTRAINT (c
, p
)
2828 /* Every address operand can be reloaded to fit. */
2831 /* Cater to architectures like IA-64 that define extra memory
2832 constraints without using define_memory_constraint. */
2833 else if (reload_in_progress
2835 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2836 && reg_renumber
[REGNO (op
)] < 0
2837 && reg_equiv_mem (REGNO (op
)) != 0
2838 && EXTRA_CONSTRAINT_STR
2839 (reg_equiv_mem (REGNO (op
)), c
, p
))
2845 while (p
+= len
, c
);
2847 constraints
[opno
] = p
;
2848 /* If this operand did not win somehow,
2849 this alternative loses. */
2853 /* This alternative won; the operands are ok.
2854 Change whichever operands this alternative says to change. */
2859 /* See if any earlyclobber operand conflicts with some other
2862 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2863 for (eopno
= seen_earlyclobber_at
;
2864 eopno
< recog_data
.n_operands
;
2866 /* Ignore earlyclobber operands now in memory,
2867 because we would often report failure when we have
2868 two memory operands, one of which was formerly a REG. */
2869 if (earlyclobber
[eopno
]
2870 && REG_P (recog_data
.operand
[eopno
]))
2871 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2872 if ((MEM_P (recog_data
.operand
[opno
])
2873 || recog_data
.operand_type
[opno
] != OP_OUT
)
2875 /* Ignore things like match_operator operands. */
2876 && *recog_data
.constraints
[opno
] != 0
2877 && ! (matching_operands
[opno
] == eopno
2878 && operands_match_p (recog_data
.operand
[opno
],
2879 recog_data
.operand
[eopno
]))
2880 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2881 recog_data
.operand
[eopno
]))
2886 while (--funny_match_index
>= 0)
2888 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2889 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2893 /* For operands without < or > constraints reject side-effects. */
2894 if (recog_data
.is_asm
)
2896 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2897 if (MEM_P (recog_data
.operand
[opno
]))
2898 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2906 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2907 && strchr (recog_data
.constraints
[opno
], '>')
2920 which_alternative
++;
2922 while (which_alternative
< recog_data
.n_alternatives
);
2924 which_alternative
= -1;
2925 /* If we are about to reject this, but we are not to test strictly,
2926 try a very loose test. Only return failure if it fails also. */
2928 return constrain_operands (-1);
2933 /* Return true iff OPERAND (assumed to be a REG rtx)
2934 is a hard reg in class CLASS when its regno is offset by OFFSET
2935 and changed to mode MODE.
2936 If REG occupies multiple hard regs, all of them must be in CLASS. */
2939 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2940 enum machine_mode mode
)
2942 unsigned int regno
= REGNO (operand
);
2947 /* Regno must not be a pseudo register. Offset may be negative. */
2948 return (HARD_REGISTER_NUM_P (regno
)
2949 && HARD_REGISTER_NUM_P (regno
+ offset
)
2950 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2954 /* Split single instruction. Helper function for split_all_insns and
2955 split_all_insns_noflow. Return last insn in the sequence if successful,
2956 or NULL if unsuccessful. */
2959 split_insn (rtx insn
)
2961 /* Split insns here to get max fine-grain parallelism. */
2962 rtx first
= PREV_INSN (insn
);
2963 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2964 rtx insn_set
, last_set
, note
;
2969 /* If the original instruction was a single set that was known to be
2970 equivalent to a constant, see if we can say the same about the last
2971 instruction in the split sequence. The two instructions must set
2972 the same destination. */
2973 insn_set
= single_set (insn
);
2976 last_set
= single_set (last
);
2977 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2979 note
= find_reg_equal_equiv_note (insn
);
2980 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2981 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2982 else if (CONSTANT_P (SET_SRC (insn_set
)))
2983 set_unique_reg_note (last
, REG_EQUAL
,
2984 copy_rtx (SET_SRC (insn_set
)));
2988 /* try_split returns the NOTE that INSN became. */
2989 SET_INSN_DELETED (insn
);
2991 /* ??? Coddle to md files that generate subregs in post-reload
2992 splitters instead of computing the proper hard register. */
2993 if (reload_completed
&& first
!= last
)
2995 first
= NEXT_INSN (first
);
2999 cleanup_subreg_operands (first
);
3002 first
= NEXT_INSN (first
);
3009 /* Split all insns in the function. If UPD_LIFE, update life info after. */
3012 split_all_insns (void)
3018 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
3019 bitmap_clear (blocks
);
3022 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3025 bool finish
= false;
3027 rtl_profile_for_bb (bb
);
3028 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
3030 /* Can't use `next_real_insn' because that might go across
3031 CODE_LABELS and short-out basic blocks. */
3032 next
= NEXT_INSN (insn
);
3033 finish
= (insn
== BB_END (bb
));
3036 rtx set
= single_set (insn
);
3038 /* Don't split no-op move insns. These should silently
3039 disappear later in final. Splitting such insns would
3040 break the code that handles LIBCALL blocks. */
3041 if (set
&& set_noop_p (set
))
3043 /* Nops get in the way while scheduling, so delete them
3044 now if register allocation has already been done. It
3045 is too risky to try to do this before register
3046 allocation, and there are unlikely to be very many
3047 nops then anyways. */
3048 if (reload_completed
)
3049 delete_insn_and_edges (insn
);
3053 if (split_insn (insn
))
3055 bitmap_set_bit (blocks
, bb
->index
);
3063 default_rtl_profile ();
3065 find_many_sub_basic_blocks (blocks
);
3067 #ifdef ENABLE_CHECKING
3068 verify_flow_info ();
3071 sbitmap_free (blocks
);
3074 /* Same as split_all_insns, but do not expect CFG to be available.
3075 Used by machine dependent reorg passes. */
3078 split_all_insns_noflow (void)
3082 for (insn
= get_insns (); insn
; insn
= next
)
3084 next
= NEXT_INSN (insn
);
3087 /* Don't split no-op move insns. These should silently
3088 disappear later in final. Splitting such insns would
3089 break the code that handles LIBCALL blocks. */
3090 rtx set
= single_set (insn
);
3091 if (set
&& set_noop_p (set
))
3093 /* Nops get in the way while scheduling, so delete them
3094 now if register allocation has already been done. It
3095 is too risky to try to do this before register
3096 allocation, and there are unlikely to be very many
3099 ??? Should we use delete_insn when the CFG isn't valid? */
3100 if (reload_completed
)
3101 delete_insn_and_edges (insn
);
3110 #ifdef HAVE_peephole2
3111 struct peep2_insn_data
3117 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
3118 static int peep2_current
;
3120 static bool peep2_do_rebuild_jump_labels
;
3121 static bool peep2_do_cleanup_cfg
;
3123 /* The number of instructions available to match a peep2. */
3124 int peep2_current_count
;
3126 /* A non-insn marker indicating the last insn of the block.
3127 The live_before regset for this element is correct, indicating
3128 DF_LIVE_OUT for the block. */
3129 #define PEEP2_EOB pc_rtx
3131 /* Wrap N to fit into the peep2_insn_data buffer. */
3134 peep2_buf_position (int n
)
3136 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
3137 n
-= MAX_INSNS_PER_PEEP2
+ 1;
3141 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3142 does not exist. Used by the recognizer to find the next insn to match
3143 in a multi-insn pattern. */
3146 peep2_next_insn (int n
)
3148 gcc_assert (n
<= peep2_current_count
);
3150 n
= peep2_buf_position (peep2_current
+ n
);
3152 return peep2_insn_data
[n
].insn
;
3155 /* Return true if REGNO is dead before the Nth non-note insn
3159 peep2_regno_dead_p (int ofs
, int regno
)
3161 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3163 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3165 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3167 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3170 /* Similarly for a REG. */
3173 peep2_reg_dead_p (int ofs
, rtx reg
)
3177 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3179 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3181 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3183 regno
= REGNO (reg
);
3184 n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
3186 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
3191 /* Regno offset to be used in the register search. */
3192 static int search_ofs
;
3194 /* Try to find a hard register of mode MODE, matching the register class in
3195 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3196 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3197 in which case the only condition is that the register must be available
3198 before CURRENT_INSN.
3199 Registers that already have bits set in REG_SET will not be considered.
3201 If an appropriate register is available, it will be returned and the
3202 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3206 peep2_find_free_register (int from
, int to
, const char *class_str
,
3207 enum machine_mode mode
, HARD_REG_SET
*reg_set
)
3214 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3215 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3217 from
= peep2_buf_position (peep2_current
+ from
);
3218 to
= peep2_buf_position (peep2_current
+ to
);
3220 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3221 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3225 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3227 /* Don't use registers set or clobbered by the insn. */
3228 for (def_rec
= DF_INSN_DEFS (peep2_insn_data
[from
].insn
);
3229 *def_rec
; def_rec
++)
3230 SET_HARD_REG_BIT (live
, DF_REF_REGNO (*def_rec
));
3232 from
= peep2_buf_position (from
+ 1);
3235 cl
= (class_str
[0] == 'r' ? GENERAL_REGS
3236 : REG_CLASS_FROM_CONSTRAINT (class_str
[0], class_str
));
3238 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3240 int raw_regno
, regno
, success
, j
;
3242 /* Distribute the free registers as much as possible. */
3243 raw_regno
= search_ofs
+ i
;
3244 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3245 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3246 #ifdef REG_ALLOC_ORDER
3247 regno
= reg_alloc_order
[raw_regno
];
3252 /* Can it support the mode we need? */
3253 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3257 for (j
= 0; success
&& j
< hard_regno_nregs
[regno
][mode
]; j
++)
3259 /* Don't allocate fixed registers. */
3260 if (fixed_regs
[regno
+ j
])
3265 /* Don't allocate global registers. */
3266 if (global_regs
[regno
+ j
])
3271 /* Make sure the register is of the right class. */
3272 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
+ j
))
3277 /* And that we don't create an extra save/restore. */
3278 if (! call_used_regs
[regno
+ j
] && ! df_regs_ever_live_p (regno
+ j
))
3284 if (! targetm
.hard_regno_scratch_ok (regno
+ j
))
3290 /* And we don't clobber traceback for noreturn functions. */
3291 if ((regno
+ j
== FRAME_POINTER_REGNUM
3292 || regno
+ j
== HARD_FRAME_POINTER_REGNUM
)
3293 && (! reload_completed
|| frame_pointer_needed
))
3299 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3300 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3309 add_to_hard_reg_set (reg_set
, mode
, regno
);
3311 /* Start the next search with the next register. */
3312 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3314 search_ofs
= raw_regno
;
3316 return gen_rtx_REG (mode
, regno
);
3324 /* Forget all currently tracked instructions, only remember current
3328 peep2_reinit_state (regset live
)
3332 /* Indicate that all slots except the last holds invalid data. */
3333 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3334 peep2_insn_data
[i
].insn
= NULL_RTX
;
3335 peep2_current_count
= 0;
3337 /* Indicate that the last slot contains live_after data. */
3338 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3339 peep2_current
= MAX_INSNS_PER_PEEP2
;
3341 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3344 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3345 starting at INSN. Perform the replacement, removing the old insns and
3346 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3347 if the replacement is rejected. */
3350 peep2_attempt (basic_block bb
, rtx insn
, int match_len
, rtx attempt
)
3353 rtx last
, eh_note
, as_note
, before_try
, x
;
3354 rtx old_insn
, new_insn
;
3355 bool was_call
= false;
3357 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3358 match more than one insn, or to be split into more than one insn. */
3359 old_insn
= peep2_insn_data
[peep2_current
].insn
;
3360 if (RTX_FRAME_RELATED_P (old_insn
))
3362 bool any_note
= false;
3368 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3369 may be in the stream for the purpose of register allocation. */
3370 if (active_insn_p (attempt
))
3373 new_insn
= next_active_insn (attempt
);
3374 if (next_active_insn (new_insn
))
3377 /* We have a 1-1 replacement. Copy over any frame-related info. */
3378 RTX_FRAME_RELATED_P (new_insn
) = 1;
3380 /* Allow the backend to fill in a note during the split. */
3381 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3382 switch (REG_NOTE_KIND (note
))
3384 case REG_FRAME_RELATED_EXPR
:
3385 case REG_CFA_DEF_CFA
:
3386 case REG_CFA_ADJUST_CFA
:
3387 case REG_CFA_OFFSET
:
3388 case REG_CFA_REGISTER
:
3389 case REG_CFA_EXPRESSION
:
3390 case REG_CFA_RESTORE
:
3391 case REG_CFA_SET_VDRAP
:
3398 /* If the backend didn't supply a note, copy one over. */
3400 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3401 switch (REG_NOTE_KIND (note
))
3403 case REG_FRAME_RELATED_EXPR
:
3404 case REG_CFA_DEF_CFA
:
3405 case REG_CFA_ADJUST_CFA
:
3406 case REG_CFA_OFFSET
:
3407 case REG_CFA_REGISTER
:
3408 case REG_CFA_EXPRESSION
:
3409 case REG_CFA_RESTORE
:
3410 case REG_CFA_SET_VDRAP
:
3411 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3418 /* If there still isn't a note, make sure the unwind info sees the
3419 same expression as before the split. */
3422 rtx old_set
, new_set
;
3424 /* The old insn had better have been simple, or annotated. */
3425 old_set
= single_set (old_insn
);
3426 gcc_assert (old_set
!= NULL
);
3428 new_set
= single_set (new_insn
);
3429 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3430 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3433 /* Copy prologue/epilogue status. This is required in order to keep
3434 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3435 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3438 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3439 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3440 cfg-related call notes. */
3441 for (i
= 0; i
<= match_len
; ++i
)
3446 j
= peep2_buf_position (peep2_current
+ i
);
3447 old_insn
= peep2_insn_data
[j
].insn
;
3448 if (!CALL_P (old_insn
))
3453 while (new_insn
!= NULL_RTX
)
3455 if (CALL_P (new_insn
))
3457 new_insn
= NEXT_INSN (new_insn
);
3460 gcc_assert (new_insn
!= NULL_RTX
);
3462 CALL_INSN_FUNCTION_USAGE (new_insn
)
3463 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3465 for (note
= REG_NOTES (old_insn
);
3467 note
= XEXP (note
, 1))
3468 switch (REG_NOTE_KIND (note
))
3473 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3477 /* Discard all other reg notes. */
3481 /* Croak if there is another call in the sequence. */
3482 while (++i
<= match_len
)
3484 j
= peep2_buf_position (peep2_current
+ i
);
3485 old_insn
= peep2_insn_data
[j
].insn
;
3486 gcc_assert (!CALL_P (old_insn
));
3491 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3492 move those notes over to the new sequence. */
3494 for (i
= match_len
; i
>= 0; --i
)
3496 int j
= peep2_buf_position (peep2_current
+ i
);
3497 old_insn
= peep2_insn_data
[j
].insn
;
3499 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3504 i
= peep2_buf_position (peep2_current
+ match_len
);
3505 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3507 /* Replace the old sequence with the new. */
3508 last
= emit_insn_after_setloc (attempt
,
3509 peep2_insn_data
[i
].insn
,
3510 INSN_LOCATION (peep2_insn_data
[i
].insn
));
3511 before_try
= PREV_INSN (insn
);
3512 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3514 /* Re-insert the EH_REGION notes. */
3515 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3520 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3521 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3525 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3528 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3529 if (x
!= BB_END (bb
)
3530 && (can_throw_internal (x
)
3531 || can_nonlocal_goto (x
)))
3536 nfte
= split_block (bb
, x
);
3537 flags
= (eh_edge
->flags
3538 & (EDGE_EH
| EDGE_ABNORMAL
));
3540 flags
|= EDGE_ABNORMAL_CALL
;
3541 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3544 nehe
->probability
= eh_edge
->probability
;
3546 = REG_BR_PROB_BASE
- nehe
->probability
;
3548 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3553 /* Converting possibly trapping insn to non-trapping is
3554 possible. Zap dummy outgoing edges. */
3555 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3558 /* Re-insert the ARGS_SIZE notes. */
3560 fixup_args_size_notes (before_try
, last
, INTVAL (XEXP (as_note
, 0)));
3562 /* If we generated a jump instruction, it won't have
3563 JUMP_LABEL set. Recompute after we're done. */
3564 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3567 peep2_do_rebuild_jump_labels
= true;
3574 /* After performing a replacement in basic block BB, fix up the life
3575 information in our buffer. LAST is the last of the insns that we
3576 emitted as a replacement. PREV is the insn before the start of
3577 the replacement. MATCH_LEN is the number of instructions that were
3578 matched, and which now need to be replaced in the buffer. */
3581 peep2_update_life (basic_block bb
, int match_len
, rtx last
, rtx prev
)
3583 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3587 INIT_REG_SET (&live
);
3588 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3590 gcc_assert (peep2_current_count
>= match_len
+ 1);
3591 peep2_current_count
-= match_len
+ 1;
3599 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3601 peep2_current_count
++;
3603 i
= MAX_INSNS_PER_PEEP2
;
3604 peep2_insn_data
[i
].insn
= x
;
3605 df_simulate_one_insn_backwards (bb
, x
, &live
);
3606 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3612 CLEAR_REG_SET (&live
);
3617 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3618 Return true if we added it, false otherwise. The caller will try to match
3619 peepholes against the buffer if we return false; otherwise it will try to
3620 add more instructions to the buffer. */
3623 peep2_fill_buffer (basic_block bb
, rtx insn
, regset live
)
3627 /* Once we have filled the maximum number of insns the buffer can hold,
3628 allow the caller to match the insns against peepholes. We wait until
3629 the buffer is full in case the target has similar peepholes of different
3630 length; we always want to match the longest if possible. */
3631 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3634 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3635 any other pattern, lest it change the semantics of the frame info. */
3636 if (RTX_FRAME_RELATED_P (insn
))
3638 /* Let the buffer drain first. */
3639 if (peep2_current_count
> 0)
3641 /* Now the insn will be the only thing in the buffer. */
3644 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3645 peep2_insn_data
[pos
].insn
= insn
;
3646 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3647 peep2_current_count
++;
3649 df_simulate_one_insn_forwards (bb
, insn
, live
);
3653 /* Perform the peephole2 optimization pass. */
3656 peephole2_optimize (void)
3663 peep2_do_cleanup_cfg
= false;
3664 peep2_do_rebuild_jump_labels
= false;
3666 df_set_flags (DF_LR_RUN_DCE
);
3667 df_note_add_problem ();
3670 /* Initialize the regsets we're going to use. */
3671 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3672 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3674 live
= BITMAP_ALLOC (®_obstack
);
3676 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3678 bool past_end
= false;
3681 rtl_profile_for_bb (bb
);
3683 /* Start up propagation. */
3684 bitmap_copy (live
, DF_LR_IN (bb
));
3685 df_simulate_initialize_forwards (bb
, live
);
3686 peep2_reinit_state (live
);
3688 insn
= BB_HEAD (bb
);
3694 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3697 insn
= NEXT_INSN (insn
);
3698 if (insn
== NEXT_INSN (BB_END (bb
)))
3702 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3705 /* If we did not fill an empty buffer, it signals the end of the
3707 if (peep2_current_count
== 0)
3710 /* The buffer filled to the current maximum, so try to match. */
3712 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3713 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3714 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3716 /* Match the peephole. */
3717 head
= peep2_insn_data
[peep2_current
].insn
;
3718 attempt
= peephole2_insns (PATTERN (head
), head
, &match_len
);
3719 if (attempt
!= NULL
)
3721 rtx last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3724 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3729 /* No match: advance the buffer by one insn. */
3730 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3731 peep2_current_count
--;
3735 default_rtl_profile ();
3736 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3737 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3739 if (peep2_do_rebuild_jump_labels
)
3740 rebuild_jump_labels (get_insns ());
3742 #endif /* HAVE_peephole2 */
3744 /* Common predicates for use with define_bypass. */
3746 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3747 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3748 must be either a single_set or a PARALLEL with SETs inside. */
3751 store_data_bypass_p (rtx out_insn
, rtx in_insn
)
3753 rtx out_set
, in_set
;
3754 rtx out_pat
, in_pat
;
3755 rtx out_exp
, in_exp
;
3758 in_set
= single_set (in_insn
);
3761 if (!MEM_P (SET_DEST (in_set
)))
3764 out_set
= single_set (out_insn
);
3767 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3772 out_pat
= PATTERN (out_insn
);
3774 if (GET_CODE (out_pat
) != PARALLEL
)
3777 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3779 out_exp
= XVECEXP (out_pat
, 0, i
);
3781 if (GET_CODE (out_exp
) == CLOBBER
)
3784 gcc_assert (GET_CODE (out_exp
) == SET
);
3786 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3793 in_pat
= PATTERN (in_insn
);
3794 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3796 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3798 in_exp
= XVECEXP (in_pat
, 0, i
);
3800 if (GET_CODE (in_exp
) == CLOBBER
)
3803 gcc_assert (GET_CODE (in_exp
) == SET
);
3805 if (!MEM_P (SET_DEST (in_exp
)))
3808 out_set
= single_set (out_insn
);
3811 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3816 out_pat
= PATTERN (out_insn
);
3817 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3819 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3821 out_exp
= XVECEXP (out_pat
, 0, j
);
3823 if (GET_CODE (out_exp
) == CLOBBER
)
3826 gcc_assert (GET_CODE (out_exp
) == SET
);
3828 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3838 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3839 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3840 or multiple set; IN_INSN should be single_set for truth, but for convenience
3841 of insn categorization may be any JUMP or CALL insn. */
3844 if_test_bypass_p (rtx out_insn
, rtx in_insn
)
3846 rtx out_set
, in_set
;
3848 in_set
= single_set (in_insn
);
3851 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3855 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3857 in_set
= SET_SRC (in_set
);
3859 out_set
= single_set (out_insn
);
3862 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3863 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3871 out_pat
= PATTERN (out_insn
);
3872 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3874 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3876 rtx exp
= XVECEXP (out_pat
, 0, i
);
3878 if (GET_CODE (exp
) == CLOBBER
)
3881 gcc_assert (GET_CODE (exp
) == SET
);
3883 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3884 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3893 rest_of_handle_peephole2 (void)
3895 #ifdef HAVE_peephole2
3896 peephole2_optimize ();
3903 const pass_data pass_data_peephole2
=
3905 RTL_PASS
, /* type */
3906 "peephole2", /* name */
3907 OPTGROUP_NONE
, /* optinfo_flags */
3908 true, /* has_execute */
3909 TV_PEEPHOLE2
, /* tv_id */
3910 0, /* properties_required */
3911 0, /* properties_provided */
3912 0, /* properties_destroyed */
3913 0, /* todo_flags_start */
3914 TODO_df_finish
, /* todo_flags_finish */
3917 class pass_peephole2
: public rtl_opt_pass
3920 pass_peephole2 (gcc::context
*ctxt
)
3921 : rtl_opt_pass (pass_data_peephole2
, ctxt
)
3924 /* opt_pass methods: */
3925 /* The epiphany backend creates a second instance of this pass, so we need
3927 opt_pass
* clone () { return new pass_peephole2 (m_ctxt
); }
3928 virtual bool gate (function
*) { return (optimize
> 0 && flag_peephole2
); }
3929 virtual unsigned int execute (function
*)
3931 return rest_of_handle_peephole2 ();
3934 }; // class pass_peephole2
3939 make_pass_peephole2 (gcc::context
*ctxt
)
3941 return new pass_peephole2 (ctxt
);
3946 const pass_data pass_data_split_all_insns
=
3948 RTL_PASS
, /* type */
3949 "split1", /* name */
3950 OPTGROUP_NONE
, /* optinfo_flags */
3951 true, /* has_execute */
3952 TV_NONE
, /* tv_id */
3953 0, /* properties_required */
3954 0, /* properties_provided */
3955 0, /* properties_destroyed */
3956 0, /* todo_flags_start */
3957 0, /* todo_flags_finish */
3960 class pass_split_all_insns
: public rtl_opt_pass
3963 pass_split_all_insns (gcc::context
*ctxt
)
3964 : rtl_opt_pass (pass_data_split_all_insns
, ctxt
)
3967 /* opt_pass methods: */
3968 /* The epiphany backend creates a second instance of this pass, so
3969 we need a clone method. */
3970 opt_pass
* clone () { return new pass_split_all_insns (m_ctxt
); }
3971 virtual unsigned int execute (function
*)
3977 }; // class pass_split_all_insns
3982 make_pass_split_all_insns (gcc::context
*ctxt
)
3984 return new pass_split_all_insns (ctxt
);
3988 rest_of_handle_split_after_reload (void)
3990 /* If optimizing, then go ahead and split insns now. */
4000 const pass_data pass_data_split_after_reload
=
4002 RTL_PASS
, /* type */
4003 "split2", /* name */
4004 OPTGROUP_NONE
, /* optinfo_flags */
4005 true, /* has_execute */
4006 TV_NONE
, /* tv_id */
4007 0, /* properties_required */
4008 0, /* properties_provided */
4009 0, /* properties_destroyed */
4010 0, /* todo_flags_start */
4011 0, /* todo_flags_finish */
4014 class pass_split_after_reload
: public rtl_opt_pass
4017 pass_split_after_reload (gcc::context
*ctxt
)
4018 : rtl_opt_pass (pass_data_split_after_reload
, ctxt
)
4021 /* opt_pass methods: */
4022 virtual unsigned int execute (function
*)
4024 return rest_of_handle_split_after_reload ();
4027 }; // class pass_split_after_reload
4032 make_pass_split_after_reload (gcc::context
*ctxt
)
4034 return new pass_split_after_reload (ctxt
);
4039 const pass_data pass_data_split_before_regstack
=
4041 RTL_PASS
, /* type */
4042 "split3", /* name */
4043 OPTGROUP_NONE
, /* optinfo_flags */
4044 true, /* has_execute */
4045 TV_NONE
, /* tv_id */
4046 0, /* properties_required */
4047 0, /* properties_provided */
4048 0, /* properties_destroyed */
4049 0, /* todo_flags_start */
4050 0, /* todo_flags_finish */
4053 class pass_split_before_regstack
: public rtl_opt_pass
4056 pass_split_before_regstack (gcc::context
*ctxt
)
4057 : rtl_opt_pass (pass_data_split_before_regstack
, ctxt
)
4060 /* opt_pass methods: */
4061 virtual bool gate (function
*);
4062 virtual unsigned int execute (function
*)
4068 }; // class pass_split_before_regstack
4071 pass_split_before_regstack::gate (function
*)
4073 #if HAVE_ATTR_length && defined (STACK_REGS)
4074 /* If flow2 creates new instructions which need splitting
4075 and scheduling after reload is not done, they might not be
4076 split until final which doesn't allow splitting
4077 if HAVE_ATTR_length. */
4078 # ifdef INSN_SCHEDULING
4079 return (optimize
&& !flag_schedule_insns_after_reload
);
4091 make_pass_split_before_regstack (gcc::context
*ctxt
)
4093 return new pass_split_before_regstack (ctxt
);
4097 rest_of_handle_split_before_sched2 (void)
4099 #ifdef INSN_SCHEDULING
4107 const pass_data pass_data_split_before_sched2
=
4109 RTL_PASS
, /* type */
4110 "split4", /* name */
4111 OPTGROUP_NONE
, /* optinfo_flags */
4112 true, /* has_execute */
4113 TV_NONE
, /* tv_id */
4114 0, /* properties_required */
4115 0, /* properties_provided */
4116 0, /* properties_destroyed */
4117 0, /* todo_flags_start */
4118 0, /* todo_flags_finish */
4121 class pass_split_before_sched2
: public rtl_opt_pass
4124 pass_split_before_sched2 (gcc::context
*ctxt
)
4125 : rtl_opt_pass (pass_data_split_before_sched2
, ctxt
)
4128 /* opt_pass methods: */
4129 virtual bool gate (function
*)
4131 #ifdef INSN_SCHEDULING
4132 return optimize
> 0 && flag_schedule_insns_after_reload
;
4138 virtual unsigned int execute (function
*)
4140 return rest_of_handle_split_before_sched2 ();
4143 }; // class pass_split_before_sched2
4148 make_pass_split_before_sched2 (gcc::context
*ctxt
)
4150 return new pass_split_before_sched2 (ctxt
);
4155 const pass_data pass_data_split_for_shorten_branches
=
4157 RTL_PASS
, /* type */
4158 "split5", /* name */
4159 OPTGROUP_NONE
, /* optinfo_flags */
4160 true, /* has_execute */
4161 TV_NONE
, /* tv_id */
4162 0, /* properties_required */
4163 0, /* properties_provided */
4164 0, /* properties_destroyed */
4165 0, /* todo_flags_start */
4166 0, /* todo_flags_finish */
4169 class pass_split_for_shorten_branches
: public rtl_opt_pass
4172 pass_split_for_shorten_branches (gcc::context
*ctxt
)
4173 : rtl_opt_pass (pass_data_split_for_shorten_branches
, ctxt
)
4176 /* opt_pass methods: */
4177 virtual bool gate (function
*)
4179 /* The placement of the splitting that we do for shorten_branches
4180 depends on whether regstack is used by the target or not. */
4181 #if HAVE_ATTR_length && !defined (STACK_REGS)
4188 virtual unsigned int execute (function
*)
4190 return split_all_insns_noflow ();
4193 }; // class pass_split_for_shorten_branches
4198 make_pass_split_for_shorten_branches (gcc::context
*ctxt
)
4200 return new pass_split_for_shorten_branches (ctxt
);
4203 /* (Re)initialize the target information after a change in target. */
4208 /* The information is zero-initialized, so we don't need to do anything
4209 first time round. */
4210 if (!this_target_recog
->x_initialized
)
4212 this_target_recog
->x_initialized
= true;
4215 memset (this_target_recog
->x_enabled_alternatives
, 0,
4216 sizeof (this_target_recog
->x_enabled_alternatives
));