gcc/config/aarch64/aarch64-simd-builtins.def

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2012-2014 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* In the list below, the BUILTIN_<ITERATOR> macros expand to create
  22    builtins for each of the modes described by <ITERATOR>.  When adding
  23    new builtins to this list, a helpful idiom to follow is to add
  24    a line for each pattern in the md file.  Thus, ADDP, which has one
  25    pattern defined for the VD_BHSI iterator, and one for DImode, has two
  26    entries below.
  27
  28    Parameter 1 is the 'type' of the intrinsic.  This is used to
  29    describe the type modifiers (for example; unsigned) applied to
  30    each of the parameters to the intrinsic function.
  31
  32    Parameter 2 is the name of the intrinsic.  This is appended
  33    to `__builtin_aarch64_<name><mode>` to give the intrinsic name
  34    as exported to the front-ends.
  35
  36    Parameter 3 describes how to map from the name to the CODE_FOR_
  37    macro holding the RTL pattern for the intrinsic.  This mapping is:
  38    0 - CODE_FOR_aarch64_<name><mode>
  39    1-9 - CODE_FOR_<name><mode><1-9>
  40    10 - CODE_FOR_<name><mode>.  */
  41
  42   BUILTIN_VD1 (CREATE, create, 0)
  43   BUILTIN_VDC (COMBINE, combine, 0)
  44   BUILTIN_VB (BINOP, pmul, 0)
  45   BUILTIN_VDQF (UNOP, sqrt, 2)
  46   BUILTIN_VD_BHSI (BINOP, addp, 0)
  47   VAR1 (UNOP, addp, 0, di)
  48   BUILTIN_VDQ_BHSI (UNOP, clz, 2)
  49
  50   BUILTIN_VALL (GETLANE, be_checked_get_lane, 0)
  51
  52   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
  53   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
  54   BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0)
  55   BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
  56   BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0)
  57   /* Implemented by aarch64_<su_optab><optab><mode>.  */
  58   BUILTIN_VSDQ_I (BINOP, sqadd, 0)
  59   BUILTIN_VSDQ_I (BINOPU, uqadd, 0)
  60   BUILTIN_VSDQ_I (BINOP, sqsub, 0)
  61   BUILTIN_VSDQ_I (BINOPU, uqsub, 0)
  62   /* Implemented by aarch64_<sur>qadd<mode>.  */
  63   BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0)
  64   BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0)
  65
  66   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
  67   BUILTIN_VDC (GETLANE, get_dregoi, 0)
  68   BUILTIN_VDC (GETLANE, get_dregci, 0)
  69   BUILTIN_VDC (GETLANE, get_dregxi, 0)
  70   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
  71   BUILTIN_VQ (GETLANE, get_qregoi, 0)
  72   BUILTIN_VQ (GETLANE, get_qregci, 0)
  73   BUILTIN_VQ (GETLANE, get_qregxi, 0)
  74   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
  75   BUILTIN_VQ (SETLANE, set_qregoi, 0)
  76   BUILTIN_VQ (SETLANE, set_qregci, 0)
  77   BUILTIN_VQ (SETLANE, set_qregxi, 0)
  78   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
  79   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
  80   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
  81   BUILTIN_VDC (LOADSTRUCT, ld4, 0)
  82   /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>.  */
  83   BUILTIN_VQ (LOADSTRUCT, ld2, 0)
  84   BUILTIN_VQ (LOADSTRUCT, ld3, 0)
  85   BUILTIN_VQ (LOADSTRUCT, ld4, 0)
  86   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
  87   BUILTIN_VDC (STORESTRUCT, st2, 0)
  88   BUILTIN_VDC (STORESTRUCT, st3, 0)
  89   BUILTIN_VDC (STORESTRUCT, st4, 0)
  90   /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>.  */
  91   BUILTIN_VQ (STORESTRUCT, st2, 0)
  92   BUILTIN_VQ (STORESTRUCT, st3, 0)
  93   BUILTIN_VQ (STORESTRUCT, st4, 0)
  94
  95   BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0)
  96   BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0)
  97   BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0)
  98
  99   BUILTIN_VQW (BINOP, saddl2, 0)
 100   BUILTIN_VQW (BINOP, uaddl2, 0)
 101   BUILTIN_VQW (BINOP, ssubl2, 0)
 102   BUILTIN_VQW (BINOP, usubl2, 0)
 103   BUILTIN_VQW (BINOP, saddw2, 0)
 104   BUILTIN_VQW (BINOP, uaddw2, 0)
 105   BUILTIN_VQW (BINOP, ssubw2, 0)
 106   BUILTIN_VQW (BINOP, usubw2, 0)
 107   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>.  */
 108   BUILTIN_VDW (BINOP, saddl, 0)
 109   BUILTIN_VDW (BINOP, uaddl, 0)
 110   BUILTIN_VDW (BINOP, ssubl, 0)
 111   BUILTIN_VDW (BINOP, usubl, 0)
 112   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>.  */
 113   BUILTIN_VDW (BINOP, saddw, 0)
 114   BUILTIN_VDW (BINOP, uaddw, 0)
 115   BUILTIN_VDW (BINOP, ssubw, 0)
 116   BUILTIN_VDW (BINOP, usubw, 0)
 117   /* Implemented by aarch64_<sur>h<addsub><mode>.  */
 118   BUILTIN_VQ_S (BINOP, shadd, 0)
 119   BUILTIN_VQ_S (BINOP, uhadd, 0)
 120   BUILTIN_VQ_S (BINOP, srhadd, 0)
 121   BUILTIN_VQ_S (BINOP, urhadd, 0)
 122   /* Implemented by aarch64_<sur><addsub>hn<mode>.  */
 123   BUILTIN_VQN (BINOP, addhn, 0)
 124   BUILTIN_VQN (BINOP, raddhn, 0)
 125   /* Implemented by aarch64_<sur><addsub>hn2<mode>.  */
 126   BUILTIN_VQN (TERNOP, addhn2, 0)
 127   BUILTIN_VQN (TERNOP, raddhn2, 0)
 128
 129   BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
 130   /* Implemented by aarch64_<sur>qmovn<mode>.  */
 131   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
 132   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
 133   /* Implemented by aarch64_s<optab><mode>.  */
 134   BUILTIN_VSDQ_I (UNOP, sqabs, 0)
 135   BUILTIN_VSDQ_I (UNOP, sqneg, 0)
 136
 137   BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_lane, 0)
 138   BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_lane, 0)
 139   BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_laneq, 0)
 140   BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_laneq, 0)
 141   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
 142   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
 143   BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_lane, 0)
 144   BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_lane, 0)
 145   BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_laneq, 0)
 146   BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_laneq, 0)
 147   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
 148   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
 149   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
 150   BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
 151   BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
 152   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>.  */
 153   BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
 154   BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
 155
 156   BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
 157   BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0)
 158   BUILTIN_VD_HSI (TERNOP, sqdmull_laneq, 0)
 159   BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
 160   BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
 161   BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0)
 162   BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq, 0)
 163   BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
 164   /* Implemented by aarch64_sq<r>dmulh<mode>.  */
 165   BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
 166   BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
 167   /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>.  */
 168   BUILTIN_VDQHS (TERNOP, sqdmulh_lane, 0)
 169   BUILTIN_VSDQ_HSI (TERNOP, sqdmulh_laneq, 0)
 170   BUILTIN_VDQHS (TERNOP, sqrdmulh_lane, 0)
 171   BUILTIN_VSDQ_HSI (TERNOP, sqrdmulh_laneq, 0)
 172   BUILTIN_SD_HSI (TERNOP, sqdmulh_lane, 0)
 173   BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane, 0)
 174
 175   BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
 176   /* Implemented by aarch64_<sur>shl<mode>.  */
 177   BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
 178   BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0)
 179   BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
 180   BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0)
 181
 182   BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
 183   VAR1 (SHIFTIMM, ashr_simd, 0, di)
 184   BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
 185   VAR1 (USHIFTIMM, lshr_simd, 0, di)
 186   /* Implemented by aarch64_<sur>shr_n<mode>.  */
 187   BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
 188   BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0)
 189   /* Implemented by aarch64_<sur>sra_n<mode>.  */
 190   BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
 191   BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0)
 192   BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
 193   BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0)
 194   /* Implemented by aarch64_<sur>shll_n<mode>.  */
 195   BUILTIN_VDW (SHIFTIMM, sshll_n, 0)
 196   BUILTIN_VDW (USHIFTIMM, ushll_n, 0)
 197   /* Implemented by aarch64_<sur>shll2_n<mode>.  */
 198   BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
 199   BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
 200   /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>.  */
 201   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
 202   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
 203   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
 204   BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0)
 205   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
 206   BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0)
 207   /* Implemented by aarch64_<sur>s<lr>i_n<mode>.  */
 208   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
 209   BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
 210   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
 211   BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
 212   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
 213   BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
 214   BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
 215   BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0)
 216
 217   /* Implemented by reduc_<sur>plus_<mode>.  */
 218   BUILTIN_VALL (UNOP, reduc_splus_, 10)
 219   BUILTIN_VDQ (UNOP, reduc_uplus_, 10)
 220
 221   /* Implemented by reduc_<maxmin_uns>_<mode>.  */
 222   BUILTIN_VDQIF (UNOP, reduc_smax_, 10)
 223   BUILTIN_VDQIF (UNOP, reduc_smin_, 10)
 224   BUILTIN_VDQ_BHSI (UNOP, reduc_umax_, 10)
 225   BUILTIN_VDQ_BHSI (UNOP, reduc_umin_, 10)
 226   BUILTIN_VDQF (UNOP, reduc_smax_nan_, 10)
 227   BUILTIN_VDQF (UNOP, reduc_smin_nan_, 10)
 228
 229   /* Implemented by <maxmin><mode>3.
 230      smax variants map to fmaxnm,
 231      smax_nan variants map to fmax.  */
 232   BUILTIN_VDQIF (BINOP, smax, 3)
 233   BUILTIN_VDQIF (BINOP, smin, 3)
 234   BUILTIN_VDQ_BHSI (BINOP, umax, 3)
 235   BUILTIN_VDQ_BHSI (BINOP, umin, 3)
 236   BUILTIN_VDQF (BINOP, smax_nan, 3)
 237   BUILTIN_VDQF (BINOP, smin_nan, 3)
 238
 239   /* Implemented by <frint_pattern><mode>2.  */
 240   BUILTIN_VDQF (UNOP, btrunc, 2)
 241   BUILTIN_VDQF (UNOP, ceil, 2)
 242   BUILTIN_VDQF (UNOP, floor, 2)
 243   BUILTIN_VDQF (UNOP, nearbyint, 2)
 244   BUILTIN_VDQF (UNOP, rint, 2)
 245   BUILTIN_VDQF (UNOP, round, 2)
 246   BUILTIN_VDQF_DF (UNOP, frintn, 2)
 247
 248   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
 249   VAR1 (UNOP, lbtruncv2sf, 2, v2si)
 250   VAR1 (UNOP, lbtruncv4sf, 2, v4si)
 251   VAR1 (UNOP, lbtruncv2df, 2, v2di)
 252
 253   VAR1 (UNOP, lbtruncuv2sf, 2, v2si)
 254   VAR1 (UNOP, lbtruncuv4sf, 2, v4si)
 255   VAR1 (UNOP, lbtruncuv2df, 2, v2di)
 256
 257   VAR1 (UNOP, lroundv2sf, 2, v2si)
 258   VAR1 (UNOP, lroundv4sf, 2, v4si)
 259   VAR1 (UNOP, lroundv2df, 2, v2di)
 260   /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2.  */
 261   VAR1 (UNOP, lroundsf, 2, si)
 262   VAR1 (UNOP, lrounddf, 2, di)
 263
 264   VAR1 (UNOP, lrounduv2sf, 2, v2si)
 265   VAR1 (UNOP, lrounduv4sf, 2, v4si)
 266   VAR1 (UNOP, lrounduv2df, 2, v2di)
 267   VAR1 (UNOP, lroundusf, 2, si)
 268   VAR1 (UNOP, lroundudf, 2, di)
 269
 270   VAR1 (UNOP, lceilv2sf, 2, v2si)
 271   VAR1 (UNOP, lceilv4sf, 2, v4si)
 272   VAR1 (UNOP, lceilv2df, 2, v2di)
 273
 274   VAR1 (UNOP, lceiluv2sf, 2, v2si)
 275   VAR1 (UNOP, lceiluv4sf, 2, v4si)
 276   VAR1 (UNOP, lceiluv2df, 2, v2di)
 277   VAR1 (UNOP, lceilusf, 2, si)
 278   VAR1 (UNOP, lceiludf, 2, di)
 279
 280   VAR1 (UNOP, lfloorv2sf, 2, v2si)
 281   VAR1 (UNOP, lfloorv4sf, 2, v4si)
 282   VAR1 (UNOP, lfloorv2df, 2, v2di)
 283
 284   VAR1 (UNOP, lflooruv2sf, 2, v2si)
 285   VAR1 (UNOP, lflooruv4sf, 2, v4si)
 286   VAR1 (UNOP, lflooruv2df, 2, v2di)
 287   VAR1 (UNOP, lfloorusf, 2, si)
 288   VAR1 (UNOP, lfloorudf, 2, di)
 289
 290   VAR1 (UNOP, lfrintnv2sf, 2, v2si)
 291   VAR1 (UNOP, lfrintnv4sf, 2, v4si)
 292   VAR1 (UNOP, lfrintnv2df, 2, v2di)
 293   VAR1 (UNOP, lfrintnsf, 2, si)
 294   VAR1 (UNOP, lfrintndf, 2, di)
 295
 296   VAR1 (UNOP, lfrintnuv2sf, 2, v2si)
 297   VAR1 (UNOP, lfrintnuv4sf, 2, v4si)
 298   VAR1 (UNOP, lfrintnuv2df, 2, v2di)
 299   VAR1 (UNOP, lfrintnusf, 2, si)
 300   VAR1 (UNOP, lfrintnudf, 2, di)
 301
 302   /* Implemented by <optab><fcvt_target><VDQF:mode>2.  */
 303   VAR1 (UNOP, floatv2si, 2, v2sf)
 304   VAR1 (UNOP, floatv4si, 2, v4sf)
 305   VAR1 (UNOP, floatv2di, 2, v2df)
 306
 307   VAR1 (UNOP, floatunsv2si, 2, v2sf)
 308   VAR1 (UNOP, floatunsv4si, 2, v4sf)
 309   VAR1 (UNOP, floatunsv2di, 2, v2df)
 310
 311   VAR5 (UNOPU, bswap, 10, v4hi, v8hi, v2si, v4si, v2di)
 312
 313   BUILTIN_VB (UNOP, rbit, 0)
 314
 315   /* Implemented by
 316      aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>.  */
 317   BUILTIN_VALL (BINOP, zip1, 0)
 318   BUILTIN_VALL (BINOP, zip2, 0)
 319   BUILTIN_VALL (BINOP, uzp1, 0)
 320   BUILTIN_VALL (BINOP, uzp2, 0)
 321   BUILTIN_VALL (BINOP, trn1, 0)
 322   BUILTIN_VALL (BINOP, trn2, 0)
 323
 324   /* Implemented by
 325      aarch64_frecp<FRECP:frecp_suffix><mode>.  */
 326   BUILTIN_GPF (UNOP, frecpe, 0)
 327   BUILTIN_GPF (BINOP, frecps, 0)
 328   BUILTIN_GPF (UNOP, frecpx, 0)
 329
 330   BUILTIN_VDQF (UNOP, frecpe, 0)
 331   BUILTIN_VDQF (BINOP, frecps, 0)
 332
 333   /* Implemented by a mixture of abs2 patterns.  Note the DImode builtin is
 334      only ever used for the int64x1_t intrinsic, there is no scalar version.  */
 335   BUILTIN_VALLDI (UNOP, abs, 2)
 336
 337   VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
 338   VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
 339
 340   VAR1 (UNOP, float_extend_lo_, 0, v2df)
 341   VAR1 (UNOP, float_truncate_lo_, 0, v2sf)
 342
 343   /* Implemented by aarch64_ld1<VALL:mode>.  */
 344   BUILTIN_VALL (LOAD1, ld1, 0)
 345
 346   /* Implemented by aarch64_st1<VALL:mode>.  */
 347   BUILTIN_VALL (STORE1, st1, 0)
 348
 349   /* Implemented by fma<mode>4.  */
 350   BUILTIN_VDQF (TERNOP, fma, 4)
 351
 352   /* Implemented by aarch64_simd_bsl<mode>.  */
 353   BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
 354   BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
 355   BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
 356
 357   /* Implemented by aarch64_crypto_aes<op><mode>.  */
 358   VAR1 (BINOPU, crypto_aese, 0, v16qi)
 359   VAR1 (BINOPU, crypto_aesd, 0, v16qi)
 360   VAR1 (UNOPU, crypto_aesmc, 0, v16qi)
 361   VAR1 (UNOPU, crypto_aesimc, 0, v16qi)
 362
 363   /* Implemented by aarch64_crypto_sha1<op><mode>.  */
 364   VAR1 (UNOPU, crypto_sha1h, 0, si)
 365   VAR1 (BINOPU, crypto_sha1su1, 0, v4si)
 366   VAR1 (TERNOPU, crypto_sha1c, 0, v4si)
 367   VAR1 (TERNOPU, crypto_sha1m, 0, v4si)
 368   VAR1 (TERNOPU, crypto_sha1p, 0, v4si)
 369   VAR1 (TERNOPU, crypto_sha1su0, 0, v4si)
 370
 371   /* Implemented by aarch64_crypto_sha256<op><mode>.  */
 372   VAR1 (TERNOPU, crypto_sha256h, 0, v4si)
 373   VAR1 (TERNOPU, crypto_sha256h2, 0, v4si)
 374   VAR1 (BINOPU, crypto_sha256su0, 0, v4si)
 375   VAR1 (TERNOPU, crypto_sha256su1, 0, v4si)
 376
 377   /* Implemented by aarch64_crypto_pmull<mode>.  */
 378   VAR1 (BINOPP, crypto_pmull, 0, di)
 379   VAR1 (BINOPP, crypto_pmull, 0, v2di)
 380
 381   /* Meta-op to check lane bounds of immediate in aarch64_expand_builtin.  */
 382   VAR1 (BINOPV, im_lane_bound, 0, si)