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Tidy up previous delta
[official-gcc.git] / gcc / config / arm / arm.h
blob685a2672329fdcce636fdb02370bddbda07b785a
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
7 This file is part of GNU CC.
8
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
23
24 /* Configuration triples for ARM ports work as follows:
25 (This is a bit of a mess and needs some thought)
26 arm-*-*: little endian
27 armel-*-*: little endian
28 armeb-*-*: big endian
29 If a non-embedded environment (ie: "real" OS) is specified, `arm'
30 should default to that used by the OS.
31 */
32
33 #ifndef __ARM_H__
34 #define __ARM_H__
35
36 #define TARGET_CPU_arm2 0x0000
37 #define TARGET_CPU_arm250 0x0000
38 #define TARGET_CPU_arm3 0x0000
39 #define TARGET_CPU_arm6 0x0001
40 #define TARGET_CPU_arm600 0x0001
41 #define TARGET_CPU_arm610 0x0002
42 #define TARGET_CPU_arm7 0x0001
43 #define TARGET_CPU_arm7m 0x0004
44 #define TARGET_CPU_arm7dm 0x0004
45 #define TARGET_CPU_arm7dmi 0x0004
46 #define TARGET_CPU_arm700 0x0001
47 #define TARGET_CPU_arm710 0x0002
48 #define TARGET_CPU_arm7100 0x0002
49 #define TARGET_CPU_arm7500 0x0002
50 #define TARGET_CPU_arm7500fe 0x1001
51 #define TARGET_CPU_arm7tdmi 0x0008
52 #define TARGET_CPU_arm8 0x0010
53 #define TARGET_CPU_arm810 0x0020
54 #define TARGET_CPU_strongarm 0x0040
55 #define TARGET_CPU_strongarm110 0x0040
56 #define TARGET_CPU_strongarm1100 0x0040
57 #define TARGET_CPU_arm9 0x0080
58 #define TARGET_CPU_arm9tdmi 0x0080
59 /* Configure didn't specify */
60 #define TARGET_CPU_generic 0x8000
61
62 enum arm_cond_code
63 {
64 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
65 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
66 };
67 extern enum arm_cond_code arm_current_cc;
68 extern char *arm_condition_codes[];
69
70 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
71
72 /* This is needed by the tail-calling peepholes */
73 extern int frame_pointer_needed;
74
75 \f
76 /* Just in case configure has failed to define anything. */
77 #ifndef TARGET_CPU_DEFAULT
78 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
79 #endif
80
81 /* If the configuration file doesn't specify the cpu, the subtarget may
82 override it. If it doesn't, then default to an ARM6. */
83 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
84 #undef TARGET_CPU_DEFAULT
85 #ifdef SUBTARGET_CPU_DEFAULT
86 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
87 #else
88 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
89 #endif
90 #endif
91
92 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
93 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
94 #else
95 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
96 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
97 #else
98 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
99 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
100 #else
101 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_ARM9
102 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
103 #else
104 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
105 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
106 #else
107 Unrecognized value in TARGET_CPU_DEFAULT.
108 #endif
109 #endif
110 #endif
111 #endif
112 #endif
113
114 #ifndef CPP_PREDEFINES
115 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
116 #endif
117
118 #define CPP_SPEC "\
119 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
120 %(cpp_endian) %(subtarget_cpp_spec)"
121
122 /* Set the architecture define -- if -march= is set, then it overrides
123 the -mcpu= setting. */
124 #define CPP_CPU_ARCH_SPEC "\
125 %{m2:-D__arm2__ -D__ARM_ARCH_2__} \
126 %{m3:-D__arm2__ -D__ARM_ARCH_2__} \
127 %{m6:-D__arm6__ -D__ARM_ARCH_3__} \
128 %{march=arm2:-D__ARM_ARCH_2__} \
129 %{march=arm250:-D__ARM_ARCH_2__} \
130 %{march=arm3:-D__ARM_ARCH_2__} \
131 %{march=arm6:-D__ARM_ARCH_3__} \
132 %{march=arm600:-D__ARM_ARCH_3__} \
133 %{march=arm610:-D__ARM_ARCH_3__} \
134 %{march=arm7:-D__ARM_ARCH_3__} \
135 %{march=arm700:-D__ARM_ARCH_3__} \
136 %{march=arm710:-D__ARM_ARCH_3__} \
137 %{march=arm7100:-D__ARM_ARCH_3__} \
138 %{march=arm7500:-D__ARM_ARCH_3__} \
139 %{march=arm7500fe:-D__ARM_ARCH_3__} \
140 %{march=arm7m:-D__ARM_ARCH_3M__} \
141 %{march=arm7dm:-D__ARM_ARCH_3M__} \
142 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
143 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
144 %{march=arm8:-D__ARM_ARCH_4__} \
145 %{march=arm810:-D__ARM_ARCH_4__} \
146 %{march=arm9:-D__ARM_ARCH_4T__} \
147 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
148 %{march=strongarm:-D__ARM_ARCH_4__} \
149 %{march=strongarm110:-D__ARM_ARCH_4__} \
150 %{march=strongarm1100:-D__ARM_ARCH_4__} \
151 %{march=armv2:-D__ARM_ARCH_2__} \
152 %{march=armv2a:-D__ARM_ARCH_2__} \
153 %{march=armv3:-D__ARM_ARCH_3__} \
154 %{march=armv3m:-D__ARM_ARCH_3M__} \
155 %{march=armv4:-D__ARM_ARCH_4__} \
156 %{march=armv4t:-D__ARM_ARCH_4T__} \
157 %{!march=*: \
158 %{mcpu=arm2:-D__ARM_ARCH_2__} \
159 %{mcpu=arm250:-D__ARM_ARCH_2__} \
160 %{mcpu=arm3:-D__ARM_ARCH_2__} \
161 %{mcpu=arm6:-D__ARM_ARCH_3__} \
162 %{mcpu=arm600:-D__ARM_ARCH_3__} \
163 %{mcpu=arm610:-D__ARM_ARCH_3__} \
164 %{mcpu=arm7:-D__ARM_ARCH_3__} \
165 %{mcpu=arm700:-D__ARM_ARCH_3__} \
166 %{mcpu=arm710:-D__ARM_ARCH_3__} \
167 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
168 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
169 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
170 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
171 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
172 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
173 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
174 %{mcpu=arm8:-D__ARM_ARCH_4__} \
175 %{mcpu=arm810:-D__ARM_ARCH_4__} \
176 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
177 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
178 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
179 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
180 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
181 %{!mcpu*:%{!m6:%{!m2:%{!m3:%(cpp_cpu_arch_default)}}}}} \
182 "
183
184 /* Define __APCS_26__ if the PC also contains the PSR */
185 /* This also examines deprecated -m[236] if neither of -mapcs-{26,32} is set,
186 ??? Delete this for 2.9. */
187 #define CPP_APCS_PC_SPEC "\
188 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
189 -D__APCS_32__} \
190 %{mapcs-26:-D__APCS_26__} \
191 %{!mapcs-32: %{!mapcs-26:%{m6:-D__APCS_32__} %{m2:-D__APCS_26__} \
192 %{m3:-D__APCS_26__} %{!m6:%{!m3:%{!m2:%(cpp_apcs_pc_default)}}}}} \
193 "
194
195 #ifndef CPP_APCS_PC_DEFAULT_SPEC
196 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
197 #endif
198
199 #define CPP_FLOAT_SPEC "\
200 %{msoft-float:\
201 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
202 -D__SOFTFP__} \
203 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
204 "
205
206 /* Default is hard float, which doesn't define anything */
207 #define CPP_FLOAT_DEFAULT_SPEC ""
208
209 #define CPP_ENDIAN_SPEC "\
210 %{mbig-endian: \
211 %{mlittle-endian: \
212 %e-mbig-endian and -mlittle-endian may not be used together} \
213 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
214 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
215 "
216
217 /* Default is little endian, which doesn't define anything. */
218 #define CPP_ENDIAN_DEFAULT_SPEC ""
219
220 /* Translate (for now) the old -m[236] option into the appropriate -mcpu=...
221 and -mapcs-xx equivalents.
222 ??? Remove support for this style in 2.9.*/
223 #define CC1_SPEC "\
224 %{m2:-mcpu=arm2 -mapcs-26} \
225 %{m3:-mcpu=arm3 -mapcs-26} \
226 %{m6:-mcpu=arm6 -mapcs-32} \
227 "
228
229 /* This macro defines names of additional specifications to put in the specs
230 that can be used in various specifications like CC1_SPEC. Its definition
231 is an initializer with a subgrouping for each command option.
232
233 Each subgrouping contains a string constant, that defines the
234 specification name, and a string constant that used by the GNU CC driver
235 program.
236
237 Do not define this macro if it does not need to do anything. */
238 #define EXTRA_SPECS \
239 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
240 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
241 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
242 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
243 { "cpp_float", CPP_FLOAT_SPEC }, \
244 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
245 { "cpp_endian", CPP_ENDIAN_SPEC }, \
246 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
247 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
248 SUBTARGET_EXTRA_SPECS
249
250 #define SUBTARGET_EXTRA_SPECS
251 #define SUBTARGET_CPP_SPEC ""
252
253 \f
254 /* Run-time Target Specification. */
255 #ifndef TARGET_VERSION
256 #define TARGET_VERSION \
257 fputs (" (ARM/generic)", stderr);
258 #endif
259
260 /* Run-time compilation parameters selecting different hardware subsets. */
261 extern int target_flags;
262
263 /* The floating point instruction architecture, can be 2 or 3 */
264 extern char * target_fp_name;
265
266 /* Nonzero if the function prologue (and epilogue) should obey
267 the ARM Procedure Call Standard. */
268 #define ARM_FLAG_APCS_FRAME (0x0001)
269
270 /* Nonzero if the function prologue should output the function name to enable
271 the post mortem debugger to print a backtrace (very useful on RISCOS,
272 unused on RISCiX). Specifying this flag also enables
273 -fno-omit-frame-pointer.
274 XXX Must still be implemented in the prologue. */
275 #define ARM_FLAG_POKE (0x0002)
276
277 /* Nonzero if floating point instructions are emulated by the FPE, in which
278 case instruction scheduling becomes very uninteresting. */
279 #define ARM_FLAG_FPE (0x0004)
280
281 /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
282 of condition flags when returning from a branch & link (ie. a function) */
283 /* ********* DEPRECATED ******** */
284 #define ARM_FLAG_ARM6 (0x0008)
285
286 /* ********* DEPRECATED ******** */
287 #define ARM_FLAG_ARM3 (0x0010)
288
289 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
290 that assume restoration of the condition flags when returning from a
291 branch and link (ie a function). */
292 #define ARM_FLAG_APCS_32 (0x0020)
293
294 /* Nonzero if stack checking should be performed on entry to each function
295 which allocates temporary variables on the stack. */
296 #define ARM_FLAG_APCS_STACK (0x0040)
297
298 /* Nonzero if floating point parameters should be passed to functions in
299 floating point registers. */
300 #define ARM_FLAG_APCS_FLOAT (0x0080)
301
302 /* Nonzero if re-entrant, position independent code should be generated.
303 This is equivalent to -fpic. */
304 #define ARM_FLAG_APCS_REENT (0x0100)
305
306 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
307 loaded byte-at-a-time. */
308 #define ARM_FLAG_SHORT_BYTE (0x0200)
309
310 /* Nonzero if all floating point instructions are missing (and there is no
311 emulator either). Generate function calls for all ops in this case. */
312 #define ARM_FLAG_SOFT_FLOAT (0x0400)
313
314 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
315 #define ARM_FLAG_BIG_END (0x0800)
316
317 /* Nonzero if we should compile for Thumb interworking. */
318 #define ARM_FLAG_THUMB (0x1000)
319
320 /* Nonzero if we should have little-endian words even when compiling for
321 big-endian (for backwards compatibility with older versions of GCC). */
322 #define ARM_FLAG_LITTLE_WORDS (0x2000)
323
324 /* Nonzero if we need to protect the prolog from scheduling */
325 #define ARM_FLAG_NO_SCHED_PRO (0x4000)
326
327 /* Nonzero if a call to abort should be generated if a noreturn
328 function tries to return. */
329 #define ARM_FLAG_ABORT_NORETURN (0x8000)
330
331 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
332 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
333 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
334 #define TARGET_6 (target_flags & ARM_FLAG_ARM6)
335 #define TARGET_3 (target_flags & ARM_FLAG_ARM3)
336 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
337 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
338 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
339 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
340 /* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is
341 that short values sould not be accessed using word load instructions
342 as there is a possibility that they may not be word aligned and this
343 would generate an MMU fault. On processors which do not have a 16 bit
344 load instruction therefore, short values must be loaded by individual
345 byte accesses rather than loading a word and then shifting the desired
346 value into place. */
347 #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
348 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
349 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
350 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
351 #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB)
352 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
353 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
354 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
355
356 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
357 Bit 31 is reserved. See riscix.h. */
358 #ifndef SUBTARGET_SWITCHES
359 #define SUBTARGET_SWITCHES
360 #endif
361
362 #define TARGET_SWITCHES \
363 { \
364 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
365 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
366 "Generate APCS conformant stack frames" }, \
367 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
368 {"poke-function-name", ARM_FLAG_POKE, \
369 "Store function names in object code" }, \
370 {"fpe", ARM_FLAG_FPE, "" }, \
371 {"6", ARM_FLAG_ARM6, "" }, \
372 {"2", ARM_FLAG_ARM3, "" }, \
373 {"3", ARM_FLAG_ARM3, "" }, \
374 {"apcs-32", ARM_FLAG_APCS_32, \
375 "Use the 32bit version of the APCS" }, \
376 {"apcs-26", -ARM_FLAG_APCS_32, \
377 "Use the 26bit version of the APCS" }, \
378 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
379 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
380 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
381 "Pass FP arguments in FP registers" }, \
382 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
383 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
384 "Generate re-entrant, PIC code" }, \
385 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
386 {"short-load-bytes", ARM_FLAG_SHORT_BYTE, \
387 "Load shorts a byte at a time" }, \
388 {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE, "" }, \
389 {"short-load-words", -ARM_FLAG_SHORT_BYTE, \
390 "Load words a byte at a time" }, \
391 {"no-short-load-words", ARM_FLAG_SHORT_BYTE, "" }, \
392 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
393 "Use library calls to perform FP operations" }, \
394 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
395 "Use hardware floating point instructions" }, \
396 {"big-endian", ARM_FLAG_BIG_END, \
397 "Assume target CPU is configured as big endian" }, \
398 {"little-endian", -ARM_FLAG_BIG_END, \
399 "Assume target CPU is configured as little endian" }, \
400 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
401 "Assume big endian bytes, little endian words" }, \
402 {"thumb-interwork", ARM_FLAG_THUMB, \
403 "Support calls between THUMB and ARM instructions sets" }, \
404 {"no-thumb-interwork", -ARM_FLAG_THUMB, "" }, \
405 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
406 "Generate a call to abort if a noreturn function returns"}, \
407 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
408 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
409 "Do not move instructions into a function's prologue" }, \
410 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
411 SUBTARGET_SWITCHES \
412 {"", TARGET_DEFAULT } \
413 }
414
415 #define TARGET_OPTIONS \
416 { \
417 {"cpu=", & arm_select[0].string, \
418 "Specify the name of the target CPU" }, \
419 {"arch=", & arm_select[1].string, \
420 "Specify the name of the target architecture" }, \
421 {"tune=", & arm_select[2].string, "" }, \
422 {"fpe=", & target_fp_name, "" }, \
423 {"fp=", & target_fp_name, \
424 "Specify the version of the floating point emulator" }, \
425 { "structure-size-boundary=", & structure_size_string, \
426 "Specify the minumum bit alignment of structures" } \
427 }
428
429 struct arm_cpu_select
430 {
431 char * string;
432 char * name;
433 struct processors * processors;
434 };
435
436 /* This is a magic array. If the user specifies a command line switch
437 which matches one of the entries in TARGET_OPTIONS then the corresponding
438 string pointer will be set to the value specified by the user. */
439 extern struct arm_cpu_select arm_select[];
440
441 enum prog_mode_type
442 {
443 prog_mode26,
444 prog_mode32
445 };
446
447 /* Recast the program mode class to be the prog_mode attribute */
448 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
449
450 extern enum prog_mode_type arm_prgmode;
451
452 /* What sort of floating point unit do we have? Hardware or software.
453 If software, is it issue 2 or issue 3? */
454 enum floating_point_type
455 {
456 FP_HARD,
457 FP_SOFT2,
458 FP_SOFT3
459 };
460
461 /* Recast the floating point class to be the floating point attribute. */
462 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
463
464 /* What type of floating point to tune for */
465 extern enum floating_point_type arm_fpu;
466
467 /* What type of floating point instructions are available */
468 extern enum floating_point_type arm_fpu_arch;
469
470 /* Default floating point architecture. Override in sub-target if
471 necessary. */
472 #define FP_DEFAULT FP_SOFT2
473
474 /* Nonzero if the processor has a fast multiply insn, and one that does
475 a 64-bit multiply of two 32-bit values. */
476 extern int arm_fast_multiply;
477
478 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
479 extern int arm_arch4;
480
481 /* Nonzero if this chip can benefit from load scheduling. */
482 extern int arm_ld_sched;
483
484 /* Nonzero if this chip is a StrongARM. */
485 extern int arm_is_strong;
486
487 /* Nonzero if this chip is a an ARM6 or an ARM7. */
488 extern int arm_is_6_or_7;
489
490 #ifndef TARGET_DEFAULT
491 #define TARGET_DEFAULT 0
492 #endif
493
494 /* The frame pointer register used in gcc has nothing to do with debugging;
495 that is controlled by the APCS-FRAME option. */
496 /* Not fully implemented yet */
497 /* #define CAN_DEBUG_WITHOUT_FP 1 */
498
499 #define TARGET_MEM_FUNCTIONS 1
500
501 #define OVERRIDE_OPTIONS arm_override_options ()
502 \f
503 /* Target machine storage Layout. */
504
505
506 /* Define this macro if it is advisable to hold scalars in registers
507 in a wider mode than that declared by the program. In such cases,
508 the value is constrained to be within the bounds of the declared
509 type, but kept valid in the wider mode. The signedness of the
510 extension may differ from that of the type. */
511
512 /* It is far faster to zero extend chars than to sign extend them */
513
514 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
515 if (GET_MODE_CLASS (MODE) == MODE_INT \
516 && GET_MODE_SIZE (MODE) < 4) \
517 { \
518 if (MODE == QImode) \
519 UNSIGNEDP = 1; \
520 else if (MODE == HImode) \
521 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
522 (MODE) = SImode; \
523 }
524
525 /* Define this macro if the promotion described by `PROMOTE_MODE'
526 should also be done for outgoing function arguments. */
527 /* This is required to ensure that push insns always push a word. */
528 #define PROMOTE_FUNCTION_ARGS
529
530 /* Define for XFmode extended real floating point support.
531 This will automatically cause REAL_ARITHMETIC to be defined. */
532 /* For the ARM:
533 I think I have added all the code to make this work. Unfortunately,
534 early releases of the floating point emulation code on RISCiX used a
535 different format for extended precision numbers. On my RISCiX box there
536 is a bug somewhere which causes the machine to lock up when running enquire
537 with long doubles. There is the additional aspect that Norcroft C
538 treats long doubles as doubles and we ought to remain compatible.
539 Perhaps someone with an FPA coprocessor and not running RISCiX would like
540 to try this someday. */
541 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
542
543 /* Disable XFmode patterns in md file */
544 #define ENABLE_XF_PATTERNS 0
545
546 /* Define if you don't want extended real, but do want to use the
547 software floating point emulator for REAL_ARITHMETIC and
548 decimal <-> binary conversion. */
549 /* See comment above */
550 #define REAL_ARITHMETIC
551
552 /* Define this if most significant bit is lowest numbered
553 in instructions that operate on numbered bit-fields. */
554 #define BITS_BIG_ENDIAN 0
555
556 /* Define this if most significant byte of a word is the lowest numbered.
557 Most ARM processors are run in little endian mode, so that is the default.
558 If you want to have it run-time selectable, change the definition in a
559 cover file to be TARGET_BIG_ENDIAN. */
560 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
561
562 /* Define this if most significant word of a multiword number is the lowest
563 numbered.
564 This is always false, even when in big-endian mode. */
565 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
566
567 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
568 on processor pre-defineds when compiling libgcc2.c. */
569 #if defined(__ARMEB__) && !defined(__ARMWEL__)
570 #define LIBGCC2_WORDS_BIG_ENDIAN 1
571 #else
572 #define LIBGCC2_WORDS_BIG_ENDIAN 0
573 #endif
574
575 /* Define this if most significant word of doubles is the lowest numbered.
576 This is always true, even when in little-endian mode. */
577 #define FLOAT_WORDS_BIG_ENDIAN 1
578
579 /* Number of bits in an addressable storage unit */
580 #define BITS_PER_UNIT 8
581
582 #define BITS_PER_WORD 32
583
584 #define UNITS_PER_WORD 4
585
586 #define POINTER_SIZE 32
587
588 #define PARM_BOUNDARY 32
589
590 #define STACK_BOUNDARY 32
591
592 #define FUNCTION_BOUNDARY 32
593
594 #define EMPTY_FIELD_BOUNDARY 32
595
596 #define BIGGEST_ALIGNMENT 32
597
598 /* Make strings word-aligned so strcpy from constants will be faster. */
599 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
600 (TREE_CODE (EXP) == STRING_CST \
601 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
602
603 /* Every structures size must be a multiple of 32 bits. */
604 /* This is for compatibility with ARMCC. ARM SDT Reference Manual
605 (ARM DUI 0020D) page 2-20 says "Structures are aligned on word
606 boundaries". */
607 #ifndef STRUCTURE_SIZE_BOUNDARY
608 #define STRUCTURE_SIZE_BOUNDARY 32
609 #endif
610
611 /* Used when parsing command line option -mstructure_size_boundary. */
612 extern char * structure_size_string;
613
614 /* Non-zero if move instructions will actually fail to work
615 when given unaligned data. */
616 #define STRICT_ALIGNMENT 1
617
618 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
619
620 \f
621 /* Standard register usage. */
622
623 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
624 (S - saved over call).
625
626 r0 * argument word/integer result
627 r1-r3 argument word
628
629 r4-r8 S register variable
630 r9 S (rfp) register variable (real frame pointer)
631
632 r10 F S (sl) stack limit (used by -mapcs-stack-check)
633 r11 F S (fp) argument pointer
634 r12 (ip) temp workspace
635 r13 F S (sp) lower end of current stack frame
636 r14 (lr) link address/workspace
637 r15 F (pc) program counter
638
639 f0 floating point result
640 f1-f3 floating point scratch
641
642 f4-f7 S floating point variable
643
644 cc This is NOT a real register, but is used internally
645 to represent things that use or set the condition
646 codes.
647 sfp This isn't either. It is used during rtl generation
648 since the offset between the frame pointer and the
649 auto's isn't known until after register allocation.
650 afp Nor this, we only need this because of non-local
651 goto. Without it fp appears to be used and the
652 elimination code won't get rid of sfp. It tracks
653 fp exactly at all times.
654
655 *: See CONDITIONAL_REGISTER_USAGE */
656
657 /* The stack backtrace structure is as follows:
658 fp points to here: | save code pointer | [fp]
659 | return link value | [fp, #-4]
660 | return sp value | [fp, #-8]
661 | return fp value | [fp, #-12]
662 [| saved r10 value |]
663 [| saved r9 value |]
664 [| saved r8 value |]
665 [| saved r7 value |]
666 [| saved r6 value |]
667 [| saved r5 value |]
668 [| saved r4 value |]
669 [| saved r3 value |]
670 [| saved r2 value |]
671 [| saved r1 value |]
672 [| saved r0 value |]
673 [| saved f7 value |] three words
674 [| saved f6 value |] three words
675 [| saved f5 value |] three words
676 [| saved f4 value |] three words
677 r0-r3 are not normally saved in a C function. */
678
679 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
680 #define FIRST_PSEUDO_REGISTER 27
681
682 /* 1 for registers that have pervasive standard uses
683 and are not available for the register allocator. */
684 #define FIXED_REGISTERS \
685 { \
686 0,0,0,0,0,0,0,0, \
687 0,0,0,1,0,1,0,1, \
688 0,0,0,0,0,0,0,0, \
689 1,1,1 \
690 }
691
692 /* 1 for registers not available across function calls.
693 These must include the FIXED_REGISTERS and also any
694 registers that can be used without being saved.
695 The latter must include the registers where values are returned
696 and the register where structure-value addresses are passed.
697 Aside from that, you can include as many other registers as you like.
698 The CC is not preserved over function calls on the ARM 6, so it is
699 easier to assume this for all. SFP is preserved, since FP is. */
700 #define CALL_USED_REGISTERS \
701 { \
702 1,1,1,1,0,0,0,0, \
703 0,0,0,1,1,1,1,1, \
704 1,1,1,1,0,0,0,0, \
705 1,1,1 \
706 }
707
708 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
709 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
710 #endif
711
712 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
713 trampled. This effectively reduces the number of available registers by 1.
714 XXX It is a hack, I know.
715 XXX Is this still needed? */
716 #define CONDITIONAL_REGISTER_USAGE \
717 { \
718 if (obey_regdecls) \
719 fixed_regs[0] = 1; \
720 if (TARGET_SOFT_FLOAT) \
721 { \
722 int regno; \
723 for (regno = 16; regno < 24; ++regno) \
724 fixed_regs[regno] = call_used_regs[regno] = 1; \
725 } \
726 if (flag_pic) \
727 { \
728 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
729 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \
730 } \
731 else if (TARGET_APCS_STACK) \
732 { \
733 fixed_regs[10] = 1; \
734 call_used_regs[10] = 1; \
735 } \
736 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
737 }
738
739 /* Return number of consecutive hard regs needed starting at reg REGNO
740 to hold something of mode MODE.
741 This is ordinarily the length in words of a value of mode MODE
742 but can be less for certain modes in special long registers.
743
744 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
745 mode. */
746 #define HARD_REGNO_NREGS(REGNO, MODE) \
747 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
748 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
749 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
750
751 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
752 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
753 regs holding FP. */
754 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
755 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
756 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
757 || REGNO == ARG_POINTER_REGNUM \
758 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
759
760 /* Value is 1 if it is a good idea to tie two pseudo registers
761 when one has mode MODE1 and one has mode MODE2.
762 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
763 for any hard reg, then this must be 0 for correct output. */
764 #define MODES_TIEABLE_P(MODE1, MODE2) \
765 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
766
767 /* Specify the registers used for certain standard purposes.
768 The values of these macros are register numbers. */
769
770 /* Define this if the program counter is overloaded on a register. */
771 #define PC_REGNUM 15
772
773 /* Register to use for pushing function arguments. */
774 #define STACK_POINTER_REGNUM 13
775
776 /* Base register for access to local variables of the function. */
777 #define FRAME_POINTER_REGNUM 25
778
779 /* Define this to be where the real frame pointer is if it is not possible to
780 work out the offset between the frame pointer and the automatic variables
781 until after register allocation has taken place. FRAME_POINTER_REGNUM
782 should point to a special register that we will make sure is eliminated. */
783 #define HARD_FRAME_POINTER_REGNUM 11
784
785 /* Value should be nonzero if functions must have frame pointers.
786 Zero means the frame pointer need not be set up (and parms may be accessed
787 via the stack pointer) in functions that seem suitable.
788 If we have to have a frame pointer we might as well make use of it.
789 APCS says that the frame pointer does not need to be pushed in leaf
790 functions, or simple tail call functions. */
791 #define FRAME_POINTER_REQUIRED \
792 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
793
794 /* Base register for access to arguments of the function. */
795 #define ARG_POINTER_REGNUM 26
796
797 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
798 as an invisible last argument (possible since varargs don't exist in
799 Pascal), so the following is not true. */
800 #define STATIC_CHAIN_REGNUM 8
801
802 /* Register in which address to store a structure value
803 is passed to a function. */
804 #define STRUCT_VALUE_REGNUM 0
805
806 /* Internal, so that we don't need to refer to a raw number */
807 #define CC_REGNUM 24
808
809 /* The order in which register should be allocated. It is good to use ip
810 since no saving is required (though calls clobber it) and it never contains
811 function parameters. It is quite good to use lr since other calls may
812 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
813 least likely to contain a function parameter; in addition results are
814 returned in r0.
815 */
816 #define REG_ALLOC_ORDER \
817 { \
818 3, 2, 1, 0, 12, 14, 4, 5, \
819 6, 7, 8, 10, 9, 11, 13, 15, \
820 16, 17, 18, 19, 20, 21, 22, 23, \
821 24, 25, 26 \
822 }
823 \f
824 /* Register and constant classes. */
825
826 /* Register classes: all ARM regs or all FPU regs---simple! */
827 enum reg_class
828 {
829 NO_REGS,
830 FPU_REGS,
831 GENERAL_REGS,
832 ALL_REGS,
833 LIM_REG_CLASSES
834 };
835
836 #define N_REG_CLASSES (int) LIM_REG_CLASSES
837
838 /* Give names of register classes as strings for dump file. */
839 #define REG_CLASS_NAMES \
840 { \
841 "NO_REGS", \
842 "FPU_REGS", \
843 "GENERAL_REGS", \
844 "ALL_REGS", \
845 }
846
847 /* Define which registers fit in which classes.
848 This is an initializer for a vector of HARD_REG_SET
849 of length N_REG_CLASSES. */
850 #define REG_CLASS_CONTENTS \
851 { \
852 0x0000000, /* NO_REGS */ \
853 0x0FF0000, /* FPU_REGS */ \
854 0x200FFFF, /* GENERAL_REGS */ \
855 0x2FFFFFF /* ALL_REGS */ \
856 }
857
858 /* The same information, inverted:
859 Return the class number of the smallest class containing
860 reg number REGNO. This could be a conditional expression
861 or could index an array. */
862 #define REGNO_REG_CLASS(REGNO) \
863 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
864 || REGNO == ARG_POINTER_REGNUM) \
865 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
866 ? NO_REGS : FPU_REGS)
867
868 /* The class value for index registers, and the one for base regs. */
869 #define INDEX_REG_CLASS GENERAL_REGS
870 #define BASE_REG_CLASS GENERAL_REGS
871
872 /* Get reg_class from a letter such as appears in the machine description.
873 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
874 #define REG_CLASS_FROM_LETTER(C) \
875 ((C)=='f' ? FPU_REGS : NO_REGS)
876
877 /* The letters I, J, K, L and M in a register constraint string
878 can be used to stand for particular ranges of immediate operands.
879 This macro defines what the ranges are.
880 C is the letter, and VALUE is a constant value.
881 Return 1 if VALUE is in the range specified by C.
882 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
883 J: valid indexing constants.
884 K: ~value ok in rhs argument of data operand.
885 L: -value ok in rhs argument of data operand.
886 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
887 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
888 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
889 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
890 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
891 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
892 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
893 || (((VALUE) & ((VALUE) - 1)) == 0)) \
894 : 0)
895
896 /* For the ARM, `Q' means that this is a memory operand that is just
897 an offset from a register.
898 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
899 address. This means that the symbol is in the text segment and can be
900 accessed without using a load. */
901
902 #define EXTRA_CONSTRAINT(OP, C) \
903 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
904 : (C) == 'R' ? (GET_CODE (OP) == MEM \
905 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
906 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
907 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
908 : 0)
909
910 /* Constant letter 'G' for the FPU immediate constants.
911 'H' means the same constant negated. */
912 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
913 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
914 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
915
916 /* Given an rtx X being reloaded into a reg required to be
917 in class CLASS, return the class of reg to actually use.
918 In general this is just CLASS; but on some machines
919 in some cases it is preferable to use a more restrictive class. */
920 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
921
922 /* Return the register class of a scratch register needed to copy IN into
923 or out of a register in CLASS in MODE. If it can be done directly,
924 NO_REGS is returned. */
925 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
926 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
927 ? GENERAL_REGS : NO_REGS)
928
929 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
930 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
931 (((MODE) == HImode && ! arm_arch4 && TARGET_SHORT_BY_BYTES \
932 && (GET_CODE (X) == MEM \
933 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
934 && true_regnum (X) == -1))) \
935 ? GENERAL_REGS : NO_REGS)
936
937 /* Try a machine-dependent way of reloading an illegitimate address
938 operand. If we find one, push the reload and jump to WIN. This
939 macro is used in only one place: `find_reloads_address' in reload.c.
940
941 For the ARM, we wish to handle large displacements off a base
942 register by splitting the addend across a MOV and the mem insn.
943 This can cut the number of reloads needed. */
944 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
945 do { \
946 if (GET_CODE (X) == PLUS \
947 && GET_CODE (XEXP (X, 0)) == REG \
948 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
949 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
950 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
951 { \
952 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
953 HOST_WIDE_INT low, high; \
954 \
955 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
956 low = ((val & 0xf) ^ 0x8) - 0x8; \
957 else if (MODE == SImode || MODE == QImode \
958 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
959 || (MODE == HImode && ! arm_arch4)) \
960 /* Need to be careful, -4096 is not a valid offset */ \
961 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
962 else if (MODE == HImode && arm_arch4) \
963 /* Need to be careful, -256 is not a valid offset */ \
964 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
965 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
966 && TARGET_HARD_FLOAT) \
967 /* Need to be careful, -1024 is not a valid offset */ \
968 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
969 else \
970 break; \
971 \
972 high = ((((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000); \
973 /* Check for overflow or zero */ \
974 if (low == 0 || high == 0 || (high + low != val)) \
975 break; \
976 \
977 /* Reload the high part into a base reg; leave the low part \
978 in the mem. */ \
979 X = gen_rtx_PLUS (GET_MODE (X), \
980 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
981 GEN_INT (high)), \
982 GEN_INT (low)); \
983 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
984 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
985 OPNUM, TYPE); \
986 goto WIN; \
987 } \
988 } while (0)
989
990 /* Return the maximum number of consecutive registers
991 needed to represent mode MODE in a register of class CLASS.
992 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
993 #define CLASS_MAX_NREGS(CLASS, MODE) \
994 ((CLASS) == FPU_REGS ? 1 \
995 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
996
997 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
998 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
999 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
1000 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
1001 ? 20 : 2)
1002 \f
1003 /* Stack layout; function entry, exit and calling. */
1004
1005 /* Define this if pushing a word on the stack
1006 makes the stack pointer a smaller address. */
1007 #define STACK_GROWS_DOWNWARD 1
1008
1009 /* Define this if the nominal address of the stack frame
1010 is at the high-address end of the local variables;
1011 that is, each additional local variable allocated
1012 goes at a more negative offset in the frame. */
1013 #define FRAME_GROWS_DOWNWARD 1
1014
1015 /* Offset within stack frame to start allocating local variables at.
1016 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1017 first local allocated. Otherwise, it is the offset to the BEGINNING
1018 of the first local allocated. */
1019 #define STARTING_FRAME_OFFSET 0
1020
1021 /* If we generate an insn to push BYTES bytes,
1022 this says how many the stack pointer really advances by. */
1023 /* The push insns do not do this rounding implicitly. So don't define this. */
1024 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
1025
1026 /* Define this if the maximum size of all the outgoing args is to be
1027 accumulated and pushed during the prologue. The amount can be
1028 found in the variable current_function_outgoing_args_size. */
1029 #define ACCUMULATE_OUTGOING_ARGS
1030
1031 /* Offset of first parameter from the argument pointer register value. */
1032 #define FIRST_PARM_OFFSET(FNDECL) 4
1033
1034 /* Value is the number of byte of arguments automatically
1035 popped when returning from a subroutine call.
1036 FUNDECL is the declaration node of the function (as a tree),
1037 FUNTYPE is the data type of the function (as a tree),
1038 or for a library call it is an identifier node for the subroutine name.
1039 SIZE is the number of bytes of arguments passed on the stack.
1040
1041 On the ARM, the caller does not pop any of its arguments that were passed
1042 on the stack. */
1043 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1044
1045 /* Define how to find the value returned by a function.
1046 VALTYPE is the data type of the value (as a tree).
1047 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1048 otherwise, FUNC is 0. */
1049 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1050 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \
1051 ? gen_rtx_REG (TYPE_MODE (VALTYPE), 16) \
1052 : gen_rtx_REG (TYPE_MODE (VALTYPE), 0))
1053
1054 /* Define how to find the value returned by a library function
1055 assuming the value has mode MODE. */
1056 #define LIBCALL_VALUE(MODE) \
1057 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
1058 ? gen_rtx_REG (MODE, 16) \
1059 : gen_rtx_REG (MODE, 0))
1060
1061 /* 1 if N is a possible register number for a function value.
1062 On the ARM, only r0 and f0 can return results. */
1063 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1064 ((REGNO) == 0 || ((REGNO) == 16) && TARGET_HARD_FLOAT)
1065
1066 /* How large values are returned */
1067 /* A C expression which can inhibit the returning of certain function values
1068 in registers, based on the type of value. */
1069 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1070
1071 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1072 values must be in memory. On the ARM, they need only do so if larger
1073 than a word, or if they contain elements offset from zero in the struct. */
1074 #define DEFAULT_PCC_STRUCT_RETURN 0
1075
1076 /* Define where to put the arguments to a function.
1077 Value is zero to push the argument on the stack,
1078 or a hard register in which to store the argument.
1079
1080 MODE is the argument's machine mode.
1081 TYPE is the data type of the argument (as a tree).
1082 This is null for libcalls where that information may
1083 not be available.
1084 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1085 the preceding args and about the function being called.
1086 NAMED is nonzero if this argument is a named parameter
1087 (otherwise it is an extra parameter matching an ellipsis).
1088
1089 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1090 other arguments are passed on the stack. If (NAMED == 0) (which happens
1091 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1092 passed in the stack (function_prologue will indeed make it pass in the
1093 stack if necessary). */
1094 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1095 ((NAMED) \
1096 ? ((CUM) >= 16 ? 0 : gen_rtx_REG (MODE, (CUM) / 4)) \
1097 : 0)
1098
1099 /* For an arg passed partly in registers and partly in memory,
1100 this is the number of registers used.
1101 For args passed entirely in registers or entirely in memory, zero. */
1102 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1103 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
1104 ? GET_MODE_SIZE (MODE) \
1105 : int_size_in_bytes (TYPE)) \
1106 ? 4 - (CUM) / 4 : 0)
1107
1108 /* A C type for declaring a variable that is used as the first argument of
1109 `FUNCTION_ARG' and other related values. For some target machines, the
1110 type `int' suffices and can hold the number of bytes of argument so far.
1111
1112 On the ARM, this is the number of bytes of arguments scanned so far. */
1113 #define CUMULATIVE_ARGS int
1114
1115 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1116 for a call to a function whose data type is FNTYPE.
1117 For a library call, FNTYPE is 0.
1118 On the ARM, the offset starts at 0. */
1119 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1120 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
1121
1122 /* Update the data in CUM to advance over an argument
1123 of mode MODE and data type TYPE.
1124 (TYPE is null for libcalls where that information may not be available.) */
1125 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1126 (CUM) += ((MODE) != BLKmode \
1127 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1128 : (int_size_in_bytes (TYPE) + 3) & ~3) \
1129
1130 /* 1 if N is a possible register number for function argument passing.
1131 On the ARM, r0-r3 are used to pass args. */
1132 #define FUNCTION_ARG_REGNO_P(REGNO) \
1133 ((REGNO) >= 0 && (REGNO) <= 3)
1134
1135 /* Perform any actions needed for a function that is receiving a variable
1136 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1137 of the current parameter. PRETEND_SIZE is a variable that should be set to
1138 the amount of stack that must be pushed by the prolog to pretend that our
1139 caller pushed it.
1140
1141 Normally, this macro will push all remaining incoming registers on the
1142 stack and set PRETEND_SIZE to the length of the registers pushed.
1143
1144 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1145 named arg and all anonymous args onto the stack.
1146 XXX I know the prologue shouldn't be pushing registers, but it is faster
1147 that way. */
1148 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1149 { \
1150 extern int current_function_anonymous_args; \
1151 current_function_anonymous_args = 1; \
1152 if ((CUM) < 16) \
1153 (PRETEND_SIZE) = 16 - (CUM); \
1154 }
1155
1156 /* Generate assembly output for the start of a function. */
1157 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1158 output_func_prologue ((STREAM), (SIZE))
1159
1160 /* Call the function profiler with a given profile label. The Acorn compiler
1161 puts this BEFORE the prolog but gcc puts it afterwards. The ``mov ip,lr''
1162 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
1163 to mind about this! */
1164 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1165 { \
1166 fprintf(STREAM, "\tmov\t%sip, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX); \
1167 fprintf(STREAM, "\tbl\tmcount\n"); \
1168 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
1169 }
1170
1171 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1172 the stack pointer does not matter. The value is tested only in
1173 functions that have frame pointers.
1174 No definition is equivalent to always zero.
1175
1176 On the ARM, the function epilogue recovers the stack pointer from the
1177 frame. */
1178 #define EXIT_IGNORE_STACK 1
1179
1180 /* Generate the assembly code for function exit. */
1181 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1182 output_func_epilogue ((STREAM), (SIZE))
1183
1184 /* Determine if the epilogue should be output as RTL.
1185 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1186 #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND)
1187
1188 /* Definitions for register eliminations.
1189
1190 This is an array of structures. Each structure initializes one pair
1191 of eliminable registers. The "from" register number is given first,
1192 followed by "to". Eliminations of the same "from" register are listed
1193 in order of preference.
1194
1195 We have two registers that can be eliminated on the ARM. First, the
1196 arg pointer register can often be eliminated in favor of the stack
1197 pointer register. Secondly, the pseudo frame pointer register can always
1198 be eliminated; it is replaced with either the stack or the real frame
1199 pointer. */
1200
1201 #define ELIMINABLE_REGS \
1202 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1203 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1204 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1205 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
1206
1207 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1208 Frame pointer elimination is automatically handled.
1209
1210 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1211 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1212 pointer, we must eliminate FRAME_POINTER_REGNUM into
1213 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1214 #define CAN_ELIMINATE(FROM, TO) \
1215 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1216
1217 /* Define the offset between two registers, one to be eliminated, and the other
1218 its replacement, at the start of a routine. */
1219 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1220 { \
1221 int volatile_func = arm_volatile_func (); \
1222 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1223 (OFFSET) = 0; \
1224 else if ((FROM) == FRAME_POINTER_REGNUM \
1225 && (TO) == STACK_POINTER_REGNUM) \
1226 (OFFSET) = (current_function_outgoing_args_size \
1227 + (get_frame_size () + 3 & ~3)); \
1228 else \
1229 { \
1230 int regno; \
1231 int offset = 12; \
1232 int saved_hard_reg = 0; \
1233 \
1234 if (! volatile_func) \
1235 { \
1236 for (regno = 0; regno <= 10; regno++) \
1237 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1238 saved_hard_reg = 1, offset += 4; \
1239 for (regno = 16; regno <=23; regno++) \
1240 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1241 offset += 12; \
1242 } \
1243 if ((FROM) == FRAME_POINTER_REGNUM) \
1244 (OFFSET) = -offset; \
1245 else \
1246 { \
1247 if (! frame_pointer_needed) \
1248 offset -= 16; \
1249 if (! volatile_func \
1250 && (regs_ever_live[14] || saved_hard_reg)) \
1251 offset += 4; \
1252 offset += current_function_outgoing_args_size; \
1253 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
1254 } \
1255 } \
1256 }
1257
1258 /* Output assembler code for a block containing the constant parts
1259 of a trampoline, leaving space for the variable parts.
1260
1261 On the ARM, (if r8 is the static chain regnum, and remembering that
1262 referencing pc adds an offset of 8) the trampoline looks like:
1263 ldr r8, [pc, #0]
1264 ldr pc, [pc]
1265 .word static chain value
1266 .word function's address
1267 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1268 #define TRAMPOLINE_TEMPLATE(FILE) \
1269 { \
1270 fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", \
1271 REGISTER_PREFIX, REGISTER_PREFIX); \
1272 fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", \
1273 REGISTER_PREFIX, REGISTER_PREFIX); \
1274 fprintf ((FILE), "\t.word\t0\n"); \
1275 fprintf ((FILE), "\t.word\t0\n"); \
1276 }
1277
1278 /* Length in units of the trampoline for entering a nested function. */
1279 #define TRAMPOLINE_SIZE 16
1280
1281 /* Alignment required for a trampoline in units. */
1282 #define TRAMPOLINE_ALIGN 4
1283
1284 /* Emit RTL insns to initialize the variable parts of a trampoline.
1285 FNADDR is an RTX for the address of the function's pure code.
1286 CXT is an RTX for the static chain value for the function. */
1287 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1288 { \
1289 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1290 (CXT)); \
1291 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1292 (FNADDR)); \
1293 }
1294
1295 \f
1296 /* Addressing modes, and classification of registers for them. */
1297
1298 #define HAVE_POST_INCREMENT 1
1299 #define HAVE_PRE_INCREMENT 1
1300 #define HAVE_POST_DECREMENT 1
1301 #define HAVE_PRE_DECREMENT 1
1302
1303 /* Macros to check register numbers against specific register classes. */
1304
1305 /* These assume that REGNO is a hard or pseudo reg number.
1306 They give nonzero only if REGNO is a hard reg of the suitable class
1307 or a pseudo reg currently allocated to a suitable hard reg.
1308 Since they use reg_renumber, they are safe only once reg_renumber
1309 has been allocated, which happens in local-alloc.c.
1310
1311 On the ARM, don't allow the pc to be used. */
1312 #define REGNO_OK_FOR_BASE_P(REGNO) \
1313 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1314 || (REGNO) == ARG_POINTER_REGNUM \
1315 || (unsigned) reg_renumber[(REGNO)] < 15 \
1316 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1317 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1318 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1319 REGNO_OK_FOR_BASE_P(REGNO)
1320
1321 /* Maximum number of registers that can appear in a valid memory address.
1322 Shifts in addresses can't be by a register. */
1323
1324 #define MAX_REGS_PER_ADDRESS 2
1325
1326 /* Recognize any constant value that is a valid address. */
1327 /* XXX We can address any constant, eventually... */
1328
1329 #ifdef AOF_ASSEMBLER
1330
1331 #define CONSTANT_ADDRESS_P(X) \
1332 (GET_CODE (X) == SYMBOL_REF \
1333 && CONSTANT_POOL_ADDRESS_P (X))
1334
1335 #else
1336
1337 #define CONSTANT_ADDRESS_P(X) \
1338 (GET_CODE (X) == SYMBOL_REF \
1339 && (CONSTANT_POOL_ADDRESS_P (X) \
1340 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1341
1342 #endif /* AOF_ASSEMBLER */
1343
1344 /* Nonzero if the constant value X is a legitimate general operand.
1345 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1346
1347 On the ARM, allow any integer (invalid ones are removed later by insn
1348 patterns), nice doubles and symbol_refs which refer to the function's
1349 constant pool XXX. */
1350 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1351
1352 /* Symbols in the text segment can be accessed without indirecting via the
1353 constant pool; it may take an extra binary operation, but this is still
1354 faster than indirecting via memory. Don't do this when not optimizing,
1355 since we won't be calculating al of the offsets necessary to do this
1356 simplification. */
1357 /* This doesn't work with AOF syntax, since the string table may be in
1358 a different AREA. */
1359 #ifndef AOF_ASSEMBLER
1360 #define ENCODE_SECTION_INFO(decl) \
1361 { \
1362 if (optimize > 0 && TREE_CONSTANT (decl) \
1363 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1364 { \
1365 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1366 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1367 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1368 } \
1369 }
1370 #endif
1371
1372 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1373 and check its validity for a certain class.
1374 We have two alternate definitions for each of them.
1375 The usual definition accepts all pseudo regs; the other rejects
1376 them unless they have been allocated suitable hard regs.
1377 The symbol REG_OK_STRICT causes the latter definition to be used. */
1378 #ifndef REG_OK_STRICT
1379
1380 /* Nonzero if X is a hard reg that can be used as a base reg
1381 or if it is a pseudo reg. */
1382 #define REG_OK_FOR_BASE_P(X) \
1383 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1384 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1385
1386 /* Nonzero if X is a hard reg that can be used as an index
1387 or if it is a pseudo reg. */
1388 #define REG_OK_FOR_INDEX_P(X) \
1389 REG_OK_FOR_BASE_P(X)
1390
1391 #define REG_OK_FOR_PRE_POST_P(X) \
1392 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1393 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1394
1395 #else
1396
1397 /* Nonzero if X is a hard reg that can be used as a base reg. */
1398 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1399
1400 /* Nonzero if X is a hard reg that can be used as an index. */
1401 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1402
1403 #define REG_OK_FOR_PRE_POST_P(X) \
1404 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1405 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1406 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1407 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1408
1409 #endif
1410 \f
1411 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1412 that is a valid memory address for an instruction.
1413 The MODE argument is the machine mode for the MEM expression
1414 that wants to use this address.
1415
1416 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1417 #define BASE_REGISTER_RTX_P(X) \
1418 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1419
1420 #define INDEX_REGISTER_RTX_P(X) \
1421 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1422
1423 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1424 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1425 only be small constants. */
1426 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1427 do \
1428 { \
1429 HOST_WIDE_INT range; \
1430 enum rtx_code code = GET_CODE (INDEX); \
1431 \
1432 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1433 { \
1434 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1435 && INTVAL (INDEX) > -1024 \
1436 && (INTVAL (INDEX) & 3) == 0) \
1437 goto LABEL; \
1438 } \
1439 else \
1440 { \
1441 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1442 goto LABEL; \
1443 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1444 && (! arm_arch4 || (MODE) != HImode)) \
1445 { \
1446 rtx xiop0 = XEXP (INDEX, 0); \
1447 rtx xiop1 = XEXP (INDEX, 1); \
1448 if (INDEX_REGISTER_RTX_P (xiop0) \
1449 && power_of_two_operand (xiop1, SImode)) \
1450 goto LABEL; \
1451 if (INDEX_REGISTER_RTX_P (xiop1) \
1452 && power_of_two_operand (xiop0, SImode)) \
1453 goto LABEL; \
1454 } \
1455 if (GET_MODE_SIZE (MODE) <= 4 \
1456 && (code == LSHIFTRT || code == ASHIFTRT \
1457 || code == ASHIFT || code == ROTATERT) \
1458 && (! arm_arch4 || (MODE) != HImode)) \
1459 { \
1460 rtx op = XEXP (INDEX, 1); \
1461 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1462 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1463 && INTVAL (op) <= 31) \
1464 goto LABEL; \
1465 } \
1466 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
1467 range = ((MODE) == HImode || (MODE) == QImode) \
1468 ? (arm_arch4 ? 256 : 4095) : 4096; \
1469 if (code == CONST_INT && INTVAL (INDEX) < range \
1470 && INTVAL (INDEX) > -range) \
1471 goto LABEL; \
1472 } \
1473 } while (0)
1474
1475 /* Jump to LABEL if X is a valid address RTX. This must also take
1476 REG_OK_STRICT into account when deciding about valid registers, but it uses
1477 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1478 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1479 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1480 refs must be forced though a static cell to ensure addressability. */
1481 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1482 { \
1483 if (BASE_REGISTER_RTX_P (X)) \
1484 goto LABEL; \
1485 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1486 && GET_CODE (XEXP (X, 0)) == REG \
1487 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1488 goto LABEL; \
1489 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1490 && (GET_CODE (X) == LABEL_REF \
1491 || (GET_CODE (X) == CONST \
1492 && GET_CODE (XEXP ((X), 0)) == PLUS \
1493 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1494 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1495 goto LABEL; \
1496 else if ((MODE) == TImode) \
1497 ; \
1498 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1499 { \
1500 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1501 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1502 { \
1503 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1504 if (val == 4 || val == -4 || val == -8) \
1505 goto LABEL; \
1506 } \
1507 } \
1508 else if (GET_CODE (X) == PLUS) \
1509 { \
1510 rtx xop0 = XEXP(X,0); \
1511 rtx xop1 = XEXP(X,1); \
1512 \
1513 if (BASE_REGISTER_RTX_P (xop0)) \
1514 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1515 else if (BASE_REGISTER_RTX_P (xop1)) \
1516 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1517 } \
1518 /* Reload currently can't handle MINUS, so disable this for now */ \
1519 /* else if (GET_CODE (X) == MINUS) \
1520 { \
1521 rtx xop0 = XEXP (X,0); \
1522 rtx xop1 = XEXP (X,1); \
1523 \
1524 if (BASE_REGISTER_RTX_P (xop0)) \
1525 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1526 } */ \
1527 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1528 && GET_CODE (X) == SYMBOL_REF \
1529 && CONSTANT_POOL_ADDRESS_P (X) \
1530 && ! (flag_pic \
1531 && symbol_mentioned_p (get_pool_constant (X)))) \
1532 goto LABEL; \
1533 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1534 && (GET_MODE_SIZE (MODE) <= 4) \
1535 && GET_CODE (XEXP (X, 0)) == REG \
1536 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1537 goto LABEL; \
1538 }
1539 \f
1540 /* Try machine-dependent ways of modifying an illegitimate address
1541 to be legitimate. If we find one, return the new, valid address.
1542 This macro is used in only one place: `memory_address' in explow.c.
1543
1544 OLDX is the address as it was before break_out_memory_refs was called.
1545 In some cases it is useful to look at this to decide what needs to be done.
1546
1547 MODE and WIN are passed so that this macro can use
1548 GO_IF_LEGITIMATE_ADDRESS.
1549
1550 It is always safe for this macro to do nothing. It exists to recognize
1551 opportunities to optimize the output.
1552
1553 On the ARM, try to convert [REG, #BIGCONST]
1554 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1555 where VALIDCONST == 0 in case of TImode. */
1556 extern struct rtx_def *legitimize_pic_address ();
1557 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1558 { \
1559 if (GET_CODE (X) == PLUS) \
1560 { \
1561 rtx xop0 = XEXP (X, 0); \
1562 rtx xop1 = XEXP (X, 1); \
1563 \
1564 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1565 xop0 = force_reg (SImode, xop0); \
1566 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1567 xop1 = force_reg (SImode, xop1); \
1568 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1569 { \
1570 HOST_WIDE_INT n, low_n; \
1571 rtx base_reg, val; \
1572 n = INTVAL (xop1); \
1573 \
1574 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1575 { \
1576 low_n = n & 0x0f; \
1577 n &= ~0x0f; \
1578 if (low_n > 4) \
1579 { \
1580 n += 16; \
1581 low_n -= 16; \
1582 } \
1583 } \
1584 else \
1585 { \
1586 low_n = ((MODE) == TImode ? 0 \
1587 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1588 n -= low_n; \
1589 } \
1590 base_reg = gen_reg_rtx (SImode); \
1591 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
1592 GEN_INT (n)), NULL_RTX); \
1593 emit_move_insn (base_reg, val); \
1594 (X) = (low_n == 0 ? base_reg \
1595 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
1596 } \
1597 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1598 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
1599 } \
1600 else if (GET_CODE (X) == MINUS) \
1601 { \
1602 rtx xop0 = XEXP (X, 0); \
1603 rtx xop1 = XEXP (X, 1); \
1604 \
1605 if (CONSTANT_P (xop0)) \
1606 xop0 = force_reg (SImode, xop0); \
1607 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1608 xop1 = force_reg (SImode, xop1); \
1609 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1610 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
1611 } \
1612 if (flag_pic) \
1613 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1614 if (memory_address_p (MODE, X)) \
1615 goto WIN; \
1616 }
1617
1618 /* Go to LABEL if ADDR (a legitimate address expression)
1619 has an effect that depends on the machine mode it is used for. */
1620 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1621 { \
1622 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1623 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1624 goto LABEL; \
1625 }
1626 \f
1627 /* Specify the machine mode that this machine uses
1628 for the index in the tablejump instruction. */
1629 #define CASE_VECTOR_MODE SImode
1630
1631 /* Define as C expression which evaluates to nonzero if the tablejump
1632 instruction expects the table to contain offsets from the address of the
1633 table.
1634 Do not define this if the table should contain absolute addresses. */
1635 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1636
1637 /* Specify the tree operation to be used to convert reals to integers. */
1638 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1639
1640 /* This is the kind of divide that is easiest to do in the general case. */
1641 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1642
1643 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1644 unsigned is probably best, but may break some code. */
1645 #ifndef DEFAULT_SIGNED_CHAR
1646 #define DEFAULT_SIGNED_CHAR 0
1647 #endif
1648
1649 /* Don't cse the address of the function being compiled. */
1650 #define NO_RECURSIVE_FUNCTION_CSE 1
1651
1652 /* Max number of bytes we can move from memory to memory
1653 in one reasonably fast instruction. */
1654 #define MOVE_MAX 4
1655
1656 /* Define if operations between registers always perform the operation
1657 on the full register even if a narrower mode is specified. */
1658 #define WORD_REGISTER_OPERATIONS
1659
1660 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1661 will either zero-extend or sign-extend. The value of this macro should
1662 be the code that says which one of the two operations is implicitly
1663 done, NIL if none. */
1664 #define LOAD_EXTEND_OP(MODE) \
1665 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1666 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1667
1668 /* Define this if zero-extension is slow (more than one real instruction).
1669 On the ARM, it is more than one instruction only if not fetching from
1670 memory. */
1671 /* #define SLOW_ZERO_EXTEND */
1672
1673 /* Nonzero if access to memory by bytes is slow and undesirable. */
1674 #define SLOW_BYTE_ACCESS 0
1675
1676 /* Immediate shift counts are truncated by the output routines (or was it
1677 the assembler?). Shift counts in a register are truncated by ARM. Note
1678 that the native compiler puts too large (> 32) immediate shift counts
1679 into a register and shifts by the register, letting the ARM decide what
1680 to do instead of doing that itself. */
1681 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1682 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1683 On the arm, Y in a register is used modulo 256 for the shift. Only for
1684 rotates is modulo 32 used. */
1685 /* #define SHIFT_COUNT_TRUNCATED 1 */
1686
1687 /* All integers have the same format so truncation is easy. */
1688 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1689
1690 /* Calling from registers is a massive pain. */
1691 #define NO_FUNCTION_CSE 1
1692
1693 /* Chars and shorts should be passed as ints. */
1694 #define PROMOTE_PROTOTYPES 1
1695
1696 /* The machine modes of pointers and functions */
1697 #define Pmode SImode
1698 #define FUNCTION_MODE Pmode
1699
1700 /* The structure type of the machine dependent info field of insns
1701 No uses for this yet. */
1702 /* #define INSN_MACHINE_INFO struct machine_info */
1703
1704 /* The relative costs of various types of constants. Note that cse.c defines
1705 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1706 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1707 case CONST_INT: \
1708 if (const_ok_for_arm (INTVAL (RTX))) \
1709 return (OUTER_CODE) == SET ? 2 : -1; \
1710 else if (OUTER_CODE == AND \
1711 && const_ok_for_arm (~INTVAL (RTX))) \
1712 return -1; \
1713 else if ((OUTER_CODE == COMPARE \
1714 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1715 && const_ok_for_arm (-INTVAL (RTX))) \
1716 return -1; \
1717 else \
1718 return 5; \
1719 case CONST: \
1720 case LABEL_REF: \
1721 case SYMBOL_REF: \
1722 return 6; \
1723 case CONST_DOUBLE: \
1724 if (const_double_rtx_ok_for_fpu (RTX)) \
1725 return (OUTER_CODE) == SET ? 2 : -1; \
1726 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1727 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1728 return -1; \
1729 return(7);
1730
1731 #define ARM_FRAME_RTX(X) \
1732 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1733 || (X) == arg_pointer_rtx)
1734
1735 #define DEFAULT_RTX_COSTS(X,CODE,OUTER_CODE) \
1736 return arm_rtx_costs (X, CODE, OUTER_CODE);
1737
1738 /* Moves to and from memory are quite expensive */
1739 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
1740
1741 /* All address computations that can be done are free, but rtx cost returns
1742 the same for practically all of them. So we weight the different types
1743 of address here in the order (most pref first):
1744 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1745 #define ADDRESS_COST(X) \
1746 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1747 || GET_CODE (X) == SYMBOL_REF) \
1748 ? 0 \
1749 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1750 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1751 ? 10 \
1752 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1753 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1754 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1755 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1756 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1757 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1758 ? 1 : 0)) \
1759 : 4)))))
1760
1761
1762
1763 /* Try to generate sequences that don't involve branches, we can then use
1764 conditional instructions */
1765 #define BRANCH_COST 4
1766
1767 /* A C statement to update the variable COST based on the relationship
1768 between INSN that is dependent on DEP through dependence LINK. */
1769 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1770 (COST) = arm_adjust_cost ((INSN), (LINK), (DEP), (COST))
1771 \f
1772 /* Position Independent Code. */
1773 /* We decide which register to use based on the compilation options and
1774 the assembler in use; this is more general than the APCS restriction of
1775 using sb (r9) all the time. */
1776 extern int arm_pic_register;
1777
1778 /* The register number of the register used to address a table of static
1779 data addresses in memory. */
1780 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1781
1782 #define FINALIZE_PIC arm_finalize_pic ()
1783
1784 /* We can't directly access anything that contains a symbol,
1785 nor can we indirect via the constant pool. */
1786 #define LEGITIMATE_PIC_OPERAND_P(X) \
1787 (! symbol_mentioned_p (X) \
1788 && (! CONSTANT_POOL_ADDRESS_P (X) \
1789 || ! symbol_mentioned_p (get_pool_constant (X))))
1790
1791
1792 \f
1793 /* Condition code information. */
1794 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1795 return the mode to be used for the comparison.
1796 CCFPEmode should be used with floating inequalities,
1797 CCFPmode should be used with floating equalities.
1798 CC_NOOVmode should be used with SImode integer equalities.
1799 CC_Zmode should be used if only the Z flag is set correctly
1800 CCmode should be used otherwise. */
1801
1802 #define EXTRA_CC_MODES CC_NOOVmode, CC_Zmode, CC_SWPmode, \
1803 CCFPmode, CCFPEmode, CC_DNEmode, CC_DEQmode, CC_DLEmode, \
1804 CC_DLTmode, CC_DGEmode, CC_DGTmode, CC_DLEUmode, CC_DLTUmode, \
1805 CC_DGEUmode, CC_DGTUmode, CC_Cmode
1806
1807 #define EXTRA_CC_NAMES "CC_NOOV", "CC_Z", "CC_SWP", "CCFP", "CCFPE", \
1808 "CC_DNE", "CC_DEQ", "CC_DLE", "CC_DLT", "CC_DGE", "CC_DGT", "CC_DLEU", \
1809 "CC_DLTU", "CC_DGEU", "CC_DGTU", "CC_C"
1810
1811 enum machine_mode arm_select_cc_mode ();
1812 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
1813
1814 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1815
1816 enum rtx_code arm_canonicalize_comparison ();
1817 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1818 do \
1819 { \
1820 if (GET_CODE (OP1) == CONST_INT \
1821 && ! (const_ok_for_arm (INTVAL (OP1)) \
1822 || (const_ok_for_arm (- INTVAL (OP1))))) \
1823 { \
1824 rtx const_op = OP1; \
1825 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
1826 OP1 = const_op; \
1827 } \
1828 } while (0)
1829
1830 #define STORE_FLAG_VALUE 1
1831
1832 /* Define the information needed to generate branch insns. This is
1833 stored from the compare operation. Note that we can't use "rtx" here
1834 since it hasn't been defined! */
1835
1836 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1837 extern int arm_compare_fp;
1838
1839 /* Define the codes that are matched by predicates in arm.c */
1840 #define PREDICATE_CODES \
1841 {"s_register_operand", {SUBREG, REG}}, \
1842 {"f_register_operand", {SUBREG, REG}}, \
1843 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1844 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1845 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1846 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1847 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1848 {"offsettable_memory_operand", {MEM}}, \
1849 {"bad_signed_byte_operand", {MEM}}, \
1850 {"alignable_memory_operand", {MEM}}, \
1851 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1852 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1853 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1854 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1855 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
1856 {"load_multiple_operation", {PARALLEL}}, \
1857 {"store_multiple_operation", {PARALLEL}}, \
1858 {"equality_operator", {EQ, NE}}, \
1859 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1860 {"const_shift_operand", {CONST_INT}}, \
1861 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1862 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1863 {"multi_register_push", {PARALLEL}}, \
1864 {"cc_register", {REG}}, \
1865 {"dominant_cc_register", {REG}},
1866
1867 \f
1868
1869 /* Gcc puts the pool in the wrong place for ARM, since we can only
1870 load addresses a limited distance around the pc. We do some
1871 special munging to move the constant pool values to the correct
1872 point in the code. */
1873 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1874
1875 /* The pool is empty, since we have moved everything into the code. */
1876 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE,X,MODE,ALIGN,LABELNO,JUMPTO) \
1877 goto JUMPTO
1878
1879 /* Output an internal label definition. */
1880 #ifndef ASM_OUTPUT_INTERNAL_LABEL
1881 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1882 do \
1883 { \
1884 char * s = (char *) alloca (40 + strlen (PREFIX)); \
1885 extern int arm_target_label, arm_ccfsm_state; \
1886 extern rtx arm_target_insn; \
1887 \
1888 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1889 && !strcmp (PREFIX, "L")) \
1890 { \
1891 arm_ccfsm_state = 0; \
1892 arm_target_insn = NULL; \
1893 } \
1894 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
1895 ASM_OUTPUT_LABEL (STREAM, s); \
1896 } while (0)
1897 #endif
1898
1899 /* Output a push or a pop instruction (only used when profiling). */
1900 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1901 fprintf (STREAM,"\tstmfd\t%ssp!,{%s%s}\n", \
1902 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO])
1903
1904 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1905 fprintf (STREAM,"\tldmfd\t%ssp!,{%s%s}\n", \
1906 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO])
1907
1908 /* Target characters. */
1909 #define TARGET_BELL 007
1910 #define TARGET_BS 010
1911 #define TARGET_TAB 011
1912 #define TARGET_NEWLINE 012
1913 #define TARGET_VT 013
1914 #define TARGET_FF 014
1915 #define TARGET_CR 015
1916 \f
1917 /* Only perform branch elimination (by making instructions conditional) if
1918 we're optimising. Otherwise it's of no use anyway. */
1919 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1920 if (optimize) \
1921 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1922
1923 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1924 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1925 /* Output an operand of an instruction. */
1926 #define PRINT_OPERAND(STREAM, X, CODE) \
1927 arm_print_operand (STREAM, X, CODE)
1928
1929 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1930 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1931 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1932 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1933 ? ((~ (HOST_WIDE_INT) 0) \
1934 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1935 : 0))))
1936
1937 /* Output the address of an operand. */
1938 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1939 { \
1940 int is_minus = GET_CODE (X) == MINUS; \
1941 \
1942 if (GET_CODE (X) == REG) \
1943 fprintf (STREAM, "[%s%s, #0]", REGISTER_PREFIX, \
1944 reg_names[REGNO (X)]); \
1945 else if (GET_CODE (X) == PLUS || is_minus) \
1946 { \
1947 rtx base = XEXP (X, 0); \
1948 rtx index = XEXP (X, 1); \
1949 char * base_reg_name; \
1950 HOST_WIDE_INT offset = 0; \
1951 if (GET_CODE (base) != REG) \
1952 { \
1953 /* Ensure that BASE is a register (one of them must be). */ \
1954 rtx temp = base; \
1955 base = index; \
1956 index = temp; \
1957 } \
1958 base_reg_name = reg_names[REGNO (base)]; \
1959 switch (GET_CODE (index)) \
1960 { \
1961 case CONST_INT: \
1962 offset = INTVAL (index); \
1963 if (is_minus) \
1964 offset = -offset; \
1965 fprintf (STREAM, "[%s%s, #%d]", REGISTER_PREFIX, \
1966 base_reg_name, offset); \
1967 break; \
1968 \
1969 case REG: \
1970 fprintf (STREAM, "[%s%s, %s%s%s]", REGISTER_PREFIX, \
1971 base_reg_name, is_minus ? "-" : "", \
1972 REGISTER_PREFIX, reg_names[REGNO (index)] ); \
1973 break; \
1974 \
1975 case MULT: \
1976 case ASHIFTRT: \
1977 case LSHIFTRT: \
1978 case ASHIFT: \
1979 case ROTATERT: \
1980 { \
1981 fprintf (STREAM, "[%s%s, %s%s%s", REGISTER_PREFIX, \
1982 base_reg_name, is_minus ? "-" : "", REGISTER_PREFIX,\
1983 reg_names[REGNO (XEXP (index, 0))]); \
1984 arm_print_operand (STREAM, index, 'S'); \
1985 fputs ("]", STREAM); \
1986 break; \
1987 } \
1988 \
1989 default: \
1990 abort(); \
1991 } \
1992 } \
1993 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1994 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1995 { \
1996 extern int output_memory_reference_mode; \
1997 \
1998 if (GET_CODE (XEXP (X, 0)) != REG) \
1999 abort (); \
2000 \
2001 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2002 fprintf (STREAM, "[%s%s, #%s%d]!", REGISTER_PREFIX, \
2003 reg_names[REGNO (XEXP (X, 0))], \
2004 GET_CODE (X) == PRE_DEC ? "-" : "", \
2005 GET_MODE_SIZE (output_memory_reference_mode)); \
2006 else \
2007 fprintf (STREAM, "[%s%s], #%s%d", REGISTER_PREFIX, \
2008 reg_names[REGNO (XEXP (X, 0))], \
2009 GET_CODE (X) == POST_DEC ? "-" : "", \
2010 GET_MODE_SIZE (output_memory_reference_mode)); \
2011 } \
2012 else output_addr_const(STREAM, X); \
2013 }
2014
2015 /* Handles PIC addr specially */
2016 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
2017 { \
2018 if (flag_pic && GET_CODE(X) == CONST && is_pic(X)) \
2019 { \
2020 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2021 fputs(" - (", STREAM); \
2022 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2023 fputs(")", STREAM); \
2024 } \
2025 else output_addr_const(STREAM, X); \
2026 }
2027
2028 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2029 Used for C++ multiple inheritance. */
2030 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2031 do { \
2032 int mi_delta = (DELTA); \
2033 char *mi_op = mi_delta < 0 ? "sub" : "add"; \
2034 int shift = 0; \
2035 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2036 ? 1 : 0); \
2037 if (mi_delta < 0) mi_delta = -mi_delta; \
2038 while (mi_delta != 0) \
2039 { \
2040 if (mi_delta & (3 << shift) == 0) \
2041 shift += 2; \
2042 else \
2043 { \
2044 fprintf (FILE, "\t%s\t%s%s, %s%s, #%d\n", \
2045 mi_op, REGISTER_PREFIX, reg_names[this_regno], \
2046 REGISTER_PREFIX, reg_names[this_regno], \
2047 mi_delta & (0xff << shift)); \
2048 mi_delta &= ~(0xff << shift); \
2049 shift += 8; \
2050 } \
2051 } \
2052 fputs ("\tb\t", FILE); \
2053 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2054 fputc ('\n', FILE); \
2055 } while (0)
2056
2057 /* A C expression whose value is RTL representing the value of the return
2058 address for the frame COUNT steps up from the current frame. */
2059
2060 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2061 ((COUNT == 0) \
2062 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \
2063 : NULL_RTX)
2064
2065 /* Used to mask out junk bits from the return address, such as
2066 processor state, interrupt status, condition codes and the like. */
2067 #define MASK_RETURN_ADDR \
2068 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2069 in 26 bit mode, the condition codes must be masked out of the \
2070 return address. This does not apply to ARM6 and later processors \
2071 when running in 32 bit mode. */ \
2072 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
2073
2074 /* Prototypes for arm.c -- actually, they aren't since the types aren't
2075 fully defined yet. */
2076
2077 void arm_override_options (/* void */);
2078 int use_return_insn (/* int */);
2079 int const_ok_for_arm (/* HOST_WIDE_INT */);
2080 int const_ok_for_op (/* HOST_WIDE_INT, enum rtx_code,
2081 enum machine_mode */);
2082 int arm_split_constant (/* enum rtx_code, enum machine_mode,
2083 HOST_WIDE_INT, struct rtx_def *,
2084 struct rtx_def *, int */);
2085 enum rtx_code arm_canonicalize_comparison (/* enum rtx_code,
2086 struct rtx_def ** */);
2087 int arm_return_in_memory (/* union tree_node * */);
2088 int legitimate_pic_operand_p (/* struct rtx_def * */);
2089 struct rtx_def *legitimize_pic_address (/* struct rtx_def *,
2090 enum machine_mode,
2091 struct rtx_def * */);
2092 int is_pic (/* struct rtx_def * */);
2093 void arm_finalize_pic (/* void */);
2094 int arm_rtx_costs (/* struct rtx_def *, enum rtx_code, enum rtx_code */);
2095 int arm_adjust_cost (/* struct rtx_def *, struct rtx_def *,
2096 struct rtx_def *, int */);
2097 int const_double_rtx_ok_for_fpu (/* struct rtx_def * */);
2098 int neg_const_double_rtx_ok_for_fpu (/* struct rtx_def * */);
2099 int s_register_operand (/* struct rtx_def *, enum machine_mode */);
2100 int f_register_operand (/* struct rtx_def *, enum machine_mode */);
2101 int reg_or_int_operand (/* struct rtx_def *, enum machine_mode */);
2102 int reload_memory_operand (/* struct rtx_def *, enum machine_mode */);
2103 int arm_rhs_operand (/* struct rtx_def *, enum machine_mode */);
2104 int arm_rhsm_operand (/* struct rtx_def *, enum machine_mode */);
2105 int arm_add_operand (/* struct rtx_def *, enum machine_mode */);
2106 int arm_not_operand (/* struct rtx_def *, enum machine_mode */);
2107 int offsettable_memory_operand (/* struct rtx_def *, enum machine_mode */);
2108 int alignable_memory_operand (/* struct rtx_def *, enum machine_mode */);
2109 int bad_signed_byte_operand (/* struct rtx_def *, enum machine_mode */);
2110 int fpu_rhs_operand (/* struct rtx_def *, enum machine_mode */);
2111 int fpu_add_operand (/* struct rtx_def *, enum machine_mode */);
2112 int power_of_two_operand (/* struct rtx_def *, enum machine_mode */);
2113 int di_operand (/* struct rtx_def *, enum machine_mode */);
2114 int soft_df_operand (/* struct rtx_def *, enum machine_mode */);
2115 int index_operand (/* struct rtx_def *, enum machine_mode */);
2116 int const_shift_operand (/* struct rtx_def *, enum machine_mode */);
2117 int shiftable_operator (/* struct rtx_def *, enum machine_mode */);
2118 int shift_operator (/* struct rtx_def *, enum machine_mode */);
2119 int equality_operator (/* struct rtx_def *, enum machine_mode */);
2120 int minmax_operator (/* struct rtx_def *, enum machine_mode */);
2121 int cc_register (/* struct rtx_def *, enum machine_mode */);
2122 int dominant_cc_register (/* struct rtx_def *, enum machine_mode */);
2123 int symbol_mentioned_p (/* struct rtx_def * */);
2124 int label_mentioned_p (/* struct rtx_def * */);
2125 enum rtx_code minmax_code (/* struct rtx_def * */);
2126 int adjacent_mem_locations (/* struct rtx_def *, struct rtx_def * */);
2127 int load_multiple_operation (/* struct rtx_def *, enum machine_mode */);
2128 int store_multiple_operation (/* struct rtx_def *, enum machine_mode */);
2129 int load_multiple_sequence (/* struct rtx_def **, int, int *, int *,
2130 HOST_WIDE_INT * */);
2131 char *emit_ldm_seq (/* struct rtx_def **, int */);
2132 int store_multiple_sequence (/* struct rtx_def **, int, int *, int *,
2133 HOST_WIDE_INT * */);
2134 char *emit_stm_seq (/* struct rtx_def **, int */);
2135 int multi_register_push (/* struct rtx_def *, enum machine_mode */);
2136 int arm_valid_machine_decl_attribute (/* union tree_node *, union tree_node *,
2137 union tree_node *,
2138 union tree_node * */);
2139 struct rtx_def *arm_gen_load_multiple (/* int, int, struct rtx_def *,
2140 int, int, int, int, int */);
2141 struct rtx_def *arm_gen_store_multiple (/* int, int, struct rtx_def *,
2142 int, int, int, int, int */);
2143 int arm_gen_movstrqi (/* struct rtx_def ** */);
2144 struct rtx_def *gen_rotated_half_load (/* struct rtx_def * */);
2145 enum machine_mode arm_select_cc_mode (/* enum rtx_code, struct rtx_def *,
2146 struct rtx_def * */);
2147 struct rtx_def *gen_compare_reg (/* enum rtx_code, struct rtx_def *,
2148 struct rtx_def * */);
2149 void arm_reload_in_hi (/* struct rtx_def ** */);
2150 void arm_reload_out_hi (/* struct rtx_def ** */);
2151 void arm_reorg (/* struct rtx_def * */);
2152 char *fp_immediate_constant (/* struct rtx_def * */);
2153 void print_multi_reg (/* FILE *, char *, int, int */);
2154 char *output_call (/* struct rtx_def ** */);
2155 char *output_call_mem (/* struct rtx_def ** */);
2156 char *output_mov_long_double_fpu_from_arm (/* struct rtx_def ** */);
2157 char *output_mov_long_double_arm_from_fpu (/* struct rtx_def ** */);
2158 char *output_mov_long_double_arm_from_arm (/* struct rtx_def ** */);
2159 char *output_mov_double_fpu_from_arm (/* struct rtx_def ** */);
2160 char *output_mov_double_arm_from_fpu (/* struct rtx_def ** */);
2161 char *output_move_double (/* struct rtx_def ** */);
2162 char *output_mov_immediate (/* struct rtx_def ** */);
2163 char *output_add_immediate (/* struct rtx_def ** */);
2164 char *arithmetic_instr (/* struct rtx_def *, int */);
2165 void output_ascii_pseudo_op (/* FILE *, unsigned char *, int */);
2166 char *output_return_instruction (/* struct rtx_def *, int, int */);
2167 int arm_volatile_func (/* void */);
2168 void output_func_prologue (/* FILE *, int */);
2169 void output_func_epilogue (/* FILE *, int */);
2170 void arm_expand_prologue (/* void */);
2171 void arm_print_operand (/* FILE *, struct rtx_def *, int */);
2172 void final_prescan_insn (/* struct rtx_def *, struct rtx_def **, int */);
2173 #ifdef AOF_ASSEMBLER
2174 struct rtx_def *aof_pic_entry (/* struct rtx_def * */);
2175 void aof_dump_pic_table (/* FILE * */);
2176 char *aof_text_section (/* void */);
2177 char *aof_data_section (/* void */);
2178 void aof_add_import (/* char * */);
2179 void aof_delete_import (/* char * */);
2180 void aof_dump_imports (/* FILE * */);
2181 #endif
2182
2183 #endif /* __ARM_H__ */
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