gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_notes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 /* Sometimes combine tries to replace the right hand side of an insn
 127    with the value of a REG_EQUAL note.  This is the insn that has been
 128    so modified, or null if none.  */
 129
 130 static rtx replaced_rhs_insn;
 131
 132 /* When REPLACED_RHS_INSN is nonnull, this is a copy of the new right
 133    hand side.  */
 134
 135 static rtx replaced_rhs_value;
 136 \f
 137 /* Vector mapping INSN_UIDs to cuids.
 138    The cuids are like uids but increase monotonically always.
 139    Combine always uses cuids so that it can compare them.
 140    But actually renumbering the uids, which we used to do,
 141    proves to be a bad idea because it makes it hard to compare
 142    the dumps produced by earlier passes with those from later passes.  */
 143
 144 static int *uid_cuid;
 145 static int max_uid_cuid;
 146
 147 /* Get the cuid of an insn.  */
 148
 149 #define INSN_CUID(INSN) \
 150 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 151
 152 /* Maximum register number, which is the size of the tables below.  */
 153
 154 static unsigned int combine_max_regno;
 155
 156 struct reg_stat {
 157   /* Record last point of death of (hard or pseudo) register n.  */
 158   rtx                           last_death;
 159
 160   /* Record last point of modification of (hard or pseudo) register n.  */
 161   rtx                           last_set;
 162
 163   /* The next group of fields allows the recording of the last value assigned
 164      to (hard or pseudo) register n.  We use this information to see if an
 165      operation being processed is redundant given a prior operation performed
 166      on the register.  For example, an `and' with a constant is redundant if
 167      all the zero bits are already known to be turned off.
 168
 169      We use an approach similar to that used by cse, but change it in the
 170      following ways:
 171
 172      (1) We do not want to reinitialize at each label.
 173      (2) It is useful, but not critical, to know the actual value assigned
 174          to a register.  Often just its form is helpful.
 175
 176      Therefore, we maintain the following fields:
 177
 178      last_set_value             the last value assigned
 179      last_set_label             records the value of label_tick when the
 180                                 register was assigned
 181      last_set_table_tick        records the value of label_tick when a
 182                                 value using the register is assigned
 183      last_set_invalid           set to nonzero when it is not valid
 184                                 to use the value of this register in some
 185                                 register's value
 186
 187      To understand the usage of these tables, it is important to understand
 188      the distinction between the value in last_set_value being valid and
 189      the register being validly contained in some other expression in the
 190      table.
 191
 192      (The next two parameters are out of date).
 193
 194      reg_stat[i].last_set_value is valid if it is nonzero, and either
 195      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 196
 197      Register I may validly appear in any expression returned for the value
 198      of another register if reg_n_sets[i] is 1.  It may also appear in the
 199      value for register J if reg_stat[j].last_set_invalid is zero, or
 200      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 201
 202      If an expression is found in the table containing a register which may
 203      not validly appear in an expression, the register is replaced by
 204      something that won't match, (clobber (const_int 0)).  */
 205
 206   /* Record last value assigned to (hard or pseudo) register n.  */
 207
 208   rtx                           last_set_value;
 209
 210   /* Record the value of label_tick when an expression involving register n
 211      is placed in last_set_value.  */
 212
 213   int                           last_set_table_tick;
 214
 215   /* Record the value of label_tick when the value for register n is placed in
 216      last_set_value.  */
 217
 218   int                           last_set_label;
 219
 220   /* These fields are maintained in parallel with last_set_value and are
 221      used to store the mode in which the register was last set, the bits
 222      that were known to be zero when it was last set, and the number of
 223      sign bits copies it was known to have when it was last set.  */
 224
 225   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 226   char                          last_set_sign_bit_copies;
 227   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 228
 229   /* Set nonzero if references to register n in expressions should not be
 230      used.  last_set_invalid is set nonzero when this register is being
 231      assigned to and last_set_table_tick == label_tick.  */
 232
 233   char                          last_set_invalid;
 234
 235   /* Some registers that are set more than once and used in more than one
 236      basic block are nevertheless always set in similar ways.  For example,
 237      a QImode register may be loaded from memory in two places on a machine
 238      where byte loads zero extend.
 239
 240      We record in the following fields if a register has some leading bits
 241      that are always equal to the sign bit, and what we know about the
 242      nonzero bits of a register, specifically which bits are known to be
 243      zero.
 244
 245      If an entry is zero, it means that we don't know anything special.  */
 246
 247   unsigned char                 sign_bit_copies;
 248
 249   unsigned HOST_WIDE_INT        nonzero_bits;
 250
 251   /* Record the value of the label_tick when the last truncation
 252      happened.  The field truncated_to_mode is only valid if
 253      truncation_label == label_tick.  */
 254
 255   int                           truncation_label;
 256
 257   /* Record the last truncation seen for this register.  If truncation
 258      is not a nop to this mode we might be able to save an explicit
 259      truncation if we know that value already contains a truncated
 260      value.  */
 261
 262   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 263 };
 264
 265 static struct reg_stat *reg_stat;
 266
 267 /* Record the cuid of the last insn that invalidated memory
 268    (anything that writes memory, and subroutine calls, but not pushes).  */
 269
 270 static int mem_last_set;
 271
 272 /* Record the cuid of the last CALL_INSN
 273    so we can tell whether a potential combination crosses any calls.  */
 274
 275 static int last_call_cuid;
 276
 277 /* When `subst' is called, this is the insn that is being modified
 278    (by combining in a previous insn).  The PATTERN of this insn
 279    is still the old pattern partially modified and it should not be
 280    looked at, but this may be used to examine the successors of the insn
 281    to judge whether a simplification is valid.  */
 282
 283 static rtx subst_insn;
 284
 285 /* This is the lowest CUID that `subst' is currently dealing with.
 286    get_last_value will not return a value if the register was set at or
 287    after this CUID.  If not for this mechanism, we could get confused if
 288    I2 or I1 in try_combine were an insn that used the old value of a register
 289    to obtain a new value.  In that case, we might erroneously get the
 290    new value of the register when we wanted the old one.  */
 291
 292 static int subst_low_cuid;
 293
 294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 295    must consider all these registers to be always live.  */
 296
 297 static HARD_REG_SET newpat_used_regs;
 298
 299 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 300    insn is the earlier than I2 or I3, combine should rescan starting at
 301    that location.  */
 302
 303 static rtx added_links_insn;
 304
 305 /* Basic block in which we are performing combines.  */
 306 static basic_block this_basic_block;
 307
 308 /* A bitmap indicating which blocks had registers go dead at entry.
 309    After combine, we'll need to re-do global life analysis with
 310    those blocks as starting points.  */
 311 static sbitmap refresh_blocks;
 312 \f
 313 /* The following array records the insn_rtx_cost for every insn
 314    in the instruction stream.  */
 315
 316 static int *uid_insn_cost;
 317
 318 /* Length of the currently allocated uid_insn_cost array.  */
 319
 320 static int last_insn_cost;
 321
 322 /* Incremented for each label.  */
 323
 324 static int label_tick;
 325
 326 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 327    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 328
 329 static enum machine_mode nonzero_bits_mode;
 330
 331 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 332    be safely used.  It is zero while computing them and after combine has
 333    completed.  This former test prevents propagating values based on
 334    previously set values, which can be incorrect if a variable is modified
 335    in a loop.  */
 336
 337 static int nonzero_sign_valid;
 338
 339 \f
 340 /* Record one modification to rtl structure
 341    to be undone by storing old_contents into *where.  */
 342
 343 struct undo
 344 {
 345   struct undo *next;
 346   enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
 347   union { rtx r; int i; enum machine_mode m; } old_contents;
 348   union { rtx *r; int *i; } where;
 349 };
 350
 351 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 352    num_undo says how many are currently recorded.
 353
 354    other_insn is nonzero if we have modified some other insn in the process
 355    of working on subst_insn.  It must be verified too.  */
 356
 357 struct undobuf
 358 {
 359   struct undo *undos;
 360   struct undo *frees;
 361   rtx other_insn;
 362 };
 363
 364 static struct undobuf undobuf;
 365
 366 /* Number of times the pseudo being substituted for
 367    was found and replaced.  */
 368
 369 static int n_occurrences;
 370
 371 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 372                                          enum machine_mode,
 373                                          unsigned HOST_WIDE_INT,
 374                                          unsigned HOST_WIDE_INT *);
 375 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 376                                                 enum machine_mode,
 377                                                 unsigned int, unsigned int *);
 378 static void do_SUBST (rtx *, rtx);
 379 static void do_SUBST_INT (int *, int);
 380 static void init_reg_last (void);
 381 static void setup_incoming_promotions (void);
 382 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 383 static int cant_combine_insn_p (rtx);
 384 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 385 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 386 static int contains_muldiv (rtx);
 387 static rtx try_combine (rtx, rtx, rtx, int *);
 388 static void undo_all (void);
 389 static void undo_commit (void);
 390 static rtx *find_split_point (rtx *, rtx);
 391 static rtx subst (rtx, rtx, rtx, int, int);
 392 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 393 static rtx simplify_if_then_else (rtx);
 394 static rtx simplify_set (rtx);
 395 static rtx simplify_logical (rtx);
 396 static rtx expand_compound_operation (rtx);
 397 static rtx expand_field_assignment (rtx);
 398 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 399                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 400 static rtx extract_left_shift (rtx, int);
 401 static rtx make_compound_operation (rtx, enum rtx_code);
 402 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 403                               unsigned HOST_WIDE_INT *);
 404 static rtx canon_reg_for_combine (rtx, rtx);
 405 static rtx force_to_mode (rtx, enum machine_mode,
 406                           unsigned HOST_WIDE_INT, int);
 407 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 408 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 409 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 410 static rtx make_field_assignment (rtx);
 411 static rtx apply_distributive_law (rtx);
 412 static rtx distribute_and_simplify_rtx (rtx, int);
 413 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 414                                      unsigned HOST_WIDE_INT);
 415 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 416                                    unsigned HOST_WIDE_INT);
 417 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 418                             HOST_WIDE_INT, enum machine_mode, int *);
 419 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 420 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 421                                  int);
 422 static int recog_for_combine (rtx *, rtx, rtx *);
 423 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 424 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 425 static void update_table_tick (rtx);
 426 static void record_value_for_reg (rtx, rtx, rtx);
 427 static void check_conversions (rtx, rtx);
 428 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 429 static void record_dead_and_set_regs (rtx);
 430 static int get_last_value_validate (rtx *, rtx, int, int);
 431 static rtx get_last_value (rtx);
 432 static int use_crosses_set_p (rtx, int);
 433 static void reg_dead_at_p_1 (rtx, rtx, void *);
 434 static int reg_dead_at_p (rtx, rtx);
 435 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 436 static int reg_bitfield_target_p (rtx, rtx);
 437 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 438 static void distribute_links (rtx);
 439 static void mark_used_regs_combine (rtx);
 440 static int insn_cuid (rtx);
 441 static void record_promoted_value (rtx, rtx);
 442 static int unmentioned_reg_p_1 (rtx *, void *);
 443 static bool unmentioned_reg_p (rtx, rtx);
 444 static void record_truncated_value (rtx);
 445 static bool reg_truncated_to_mode (enum machine_mode, rtx);
 446 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 447 \f
 448
 449 /* It is not safe to use ordinary gen_lowpart in combine.
 450    See comments in gen_lowpart_for_combine.  */
 451 #undef RTL_HOOKS_GEN_LOWPART
 452 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 453
 454 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 455 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 456 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 457
 458 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 459 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 460
 461 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 462 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 463
 464 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 465 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 466
 467 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 468
 469 \f
 470 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 471    insn.  The substitution can be undone by undo_all.  If INTO is already
 472    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 473    also call SUBST, we have to compute it before we put anything into
 474    the undo table.  */
 475
 476 static void
 477 do_SUBST (rtx *into, rtx newval)
 478 {
 479   struct undo *buf;
 480   rtx oldval = *into;
 481
 482   if (oldval == newval)
 483     return;
 484
 485   /* We'd like to catch as many invalid transformations here as
 486      possible.  Unfortunately, there are way too many mode changes
 487      that are perfectly valid, so we'd waste too much effort for
 488      little gain doing the checks here.  Focus on catching invalid
 489      transformations involving integer constants.  */
 490   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 491       && GET_CODE (newval) == CONST_INT)
 492     {
 493       /* Sanity check that we're replacing oldval with a CONST_INT
 494          that is a valid sign-extension for the original mode.  */
 495       gcc_assert (INTVAL (newval)
 496                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 497
 498       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 499          CONST_INT is not valid, because after the replacement, the
 500          original mode would be gone.  Unfortunately, we can't tell
 501          when do_SUBST is called to replace the operand thereof, so we
 502          perform this test on oldval instead, checking whether an
 503          invalid replacement took place before we got here.  */
 504       gcc_assert (!(GET_CODE (oldval) == SUBREG
 505                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 506       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 507                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 508     }
 509
 510   if (undobuf.frees)
 511     buf = undobuf.frees, undobuf.frees = buf->next;
 512   else
 513     buf = XNEW (struct undo);
 514
 515   buf->kind = UNDO_RTX;
 516   buf->where.r = into;
 517   buf->old_contents.r = oldval;
 518   *into = newval;
 519
 520   buf->next = undobuf.undos, undobuf.undos = buf;
 521 }
 522
 523 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 524
 525 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 526    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 527    not safe.  */
 528
 529 static void
 530 do_SUBST_INT (int *into, int newval)
 531 {
 532   struct undo *buf;
 533   int oldval = *into;
 534
 535   if (oldval == newval)
 536     return;
 537
 538   if (undobuf.frees)
 539     buf = undobuf.frees, undobuf.frees = buf->next;
 540   else
 541     buf = XNEW (struct undo);
 542
 543   buf->kind = UNDO_INT;
 544   buf->where.i = into;
 545   buf->old_contents.i = oldval;
 546   *into = newval;
 547
 548   buf->next = undobuf.undos, undobuf.undos = buf;
 549 }
 550
 551 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 552
 553 /* Similar to SUBST, but just substitute the mode.  This is used when
 554    changing the mode of a pseudo-register, so that any other
 555    references to the entry in the regno_reg_rtx array will change as
 556    well.  */
 557
 558 static void
 559 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 560 {
 561   struct undo *buf;
 562   enum machine_mode oldval = GET_MODE (*into);
 563
 564   if (oldval == newval)
 565     return;
 566
 567   if (undobuf.frees)
 568     buf = undobuf.frees, undobuf.frees = buf->next;
 569   else
 570     buf = XNEW (struct undo);
 571
 572   buf->kind = UNDO_MODE;
 573   buf->where.r = into;
 574   buf->old_contents.m = oldval;
 575   PUT_MODE (*into, newval);
 576
 577   buf->next = undobuf.undos, undobuf.undos = buf;
 578 }
 579
 580 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 581 \f
 582 /* Subroutine of try_combine.  Determine whether the combine replacement
 583    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 584    that the original instruction sequence I1, I2 and I3.  Note that I1
 585    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 586    costs of all instructions can be estimated, and the replacements are
 587    more expensive than the original sequence.  */
 588
 589 static bool
 590 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 591 {
 592   int i1_cost, i2_cost, i3_cost;
 593   int new_i2_cost, new_i3_cost;
 594   int old_cost, new_cost;
 595
 596   /* Lookup the original insn_rtx_costs.  */
 597   i2_cost = INSN_UID (i2) <= last_insn_cost
 598             ? uid_insn_cost[INSN_UID (i2)] : 0;
 599   i3_cost = INSN_UID (i3) <= last_insn_cost
 600             ? uid_insn_cost[INSN_UID (i3)] : 0;
 601
 602   if (i1)
 603     {
 604       i1_cost = INSN_UID (i1) <= last_insn_cost
 605                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 606       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 607                  ? i1_cost + i2_cost + i3_cost : 0;
 608     }
 609   else
 610     {
 611       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 612       i1_cost = 0;
 613     }
 614
 615   /* Calculate the replacement insn_rtx_costs.  */
 616   new_i3_cost = insn_rtx_cost (newpat);
 617   if (newi2pat)
 618     {
 619       new_i2_cost = insn_rtx_cost (newi2pat);
 620       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 621                  ? new_i2_cost + new_i3_cost : 0;
 622     }
 623   else
 624     {
 625       new_cost = new_i3_cost;
 626       new_i2_cost = 0;
 627     }
 628
 629   if (undobuf.other_insn)
 630     {
 631       int old_other_cost, new_other_cost;
 632
 633       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 634                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 635       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 636       if (old_other_cost > 0 && new_other_cost > 0)
 637         {
 638           old_cost += old_other_cost;
 639           new_cost += new_other_cost;
 640         }
 641       else
 642         old_cost = 0;
 643     }
 644
 645   /* Disallow this recombination if both new_cost and old_cost are
 646      greater than zero, and new_cost is greater than old cost.  */
 647   if (old_cost > 0
 648       && new_cost > old_cost)
 649     {
 650       if (dump_file)
 651         {
 652           if (i1)
 653             {
 654               fprintf (dump_file,
 655                        "rejecting combination of insns %d, %d and %d\n",
 656                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 657               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 658                        i1_cost, i2_cost, i3_cost, old_cost);
 659             }
 660           else
 661             {
 662               fprintf (dump_file,
 663                        "rejecting combination of insns %d and %d\n",
 664                        INSN_UID (i2), INSN_UID (i3));
 665               fprintf (dump_file, "original costs %d + %d = %d\n",
 666                        i2_cost, i3_cost, old_cost);
 667             }
 668
 669           if (newi2pat)
 670             {
 671               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 672                        new_i2_cost, new_i3_cost, new_cost);
 673             }
 674           else
 675             fprintf (dump_file, "replacement cost %d\n", new_cost);
 676         }
 677
 678       return false;
 679     }
 680
 681   /* Update the uid_insn_cost array with the replacement costs.  */
 682   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 683   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 684   if (i1)
 685     uid_insn_cost[INSN_UID (i1)] = 0;
 686
 687   return true;
 688 }
 689 \f
 690 /* Main entry point for combiner.  F is the first insn of the function.
 691    NREGS is the first unused pseudo-reg number.
 692
 693    Return nonzero if the combiner has turned an indirect jump
 694    instruction into a direct jump.  */
 695 static int
 696 combine_instructions (rtx f, unsigned int nregs)
 697 {
 698   rtx insn, next;
 699 #ifdef HAVE_cc0
 700   rtx prev;
 701 #endif
 702   int i;
 703   unsigned int j = 0;
 704   rtx links, nextlinks;
 705   sbitmap_iterator sbi;
 706
 707   int new_direct_jump_p = 0;
 708
 709   combine_attempts = 0;
 710   combine_merges = 0;
 711   combine_extras = 0;
 712   combine_successes = 0;
 713
 714   combine_max_regno = nregs;
 715
 716   rtl_hooks = combine_rtl_hooks;
 717
 718   reg_stat = XCNEWVEC (struct reg_stat, nregs);
 719
 720   init_recog_no_volatile ();
 721
 722   /* Compute maximum uid value so uid_cuid can be allocated.  */
 723
 724   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 725     if (INSN_UID (insn) > i)
 726       i = INSN_UID (insn);
 727
 728   uid_cuid = XNEWVEC (int, i + 1);
 729   max_uid_cuid = i;
 730
 731   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 732
 733   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 734      problems when, for example, we have j <<= 1 in a loop.  */
 735
 736   nonzero_sign_valid = 0;
 737
 738   /* Compute the mapping from uids to cuids.
 739      Cuids are numbers assigned to insns, like uids,
 740      except that cuids increase monotonically through the code.
 741
 742      Scan all SETs and see if we can deduce anything about what
 743      bits are known to be zero for some registers and how many copies
 744      of the sign bit are known to exist for those registers.
 745
 746      Also set any known values so that we can use it while searching
 747      for what bits are known to be set.  */
 748
 749   label_tick = 1;
 750
 751   setup_incoming_promotions ();
 752
 753   refresh_blocks = sbitmap_alloc (last_basic_block);
 754   sbitmap_zero (refresh_blocks);
 755
 756   /* Allocate array of current insn_rtx_costs.  */
 757   uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1);
 758   last_insn_cost = max_uid_cuid;
 759
 760   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 761     {
 762       uid_cuid[INSN_UID (insn)] = ++i;
 763       subst_low_cuid = i;
 764       subst_insn = insn;
 765
 766       if (INSN_P (insn))
 767         {
 768           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 769                        NULL);
 770           record_dead_and_set_regs (insn);
 771
 772 #ifdef AUTO_INC_DEC
 773           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 774             if (REG_NOTE_KIND (links) == REG_INC)
 775               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 776                                                 NULL);
 777 #endif
 778
 779           /* Record the current insn_rtx_cost of this instruction.  */
 780           if (NONJUMP_INSN_P (insn))
 781             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 782           if (dump_file)
 783             fprintf(dump_file, "insn_cost %d: %d\n",
 784                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 785         }
 786
 787       if (LABEL_P (insn))
 788         label_tick++;
 789     }
 790
 791   nonzero_sign_valid = 1;
 792
 793   /* Now scan all the insns in forward order.  */
 794
 795   label_tick = 1;
 796   last_call_cuid = 0;
 797   mem_last_set = 0;
 798   init_reg_last ();
 799   setup_incoming_promotions ();
 800
 801   FOR_EACH_BB (this_basic_block)
 802     {
 803       for (insn = BB_HEAD (this_basic_block);
 804            insn != NEXT_INSN (BB_END (this_basic_block));
 805            insn = next ? next : NEXT_INSN (insn))
 806         {
 807           next = 0;
 808
 809           if (LABEL_P (insn))
 810             label_tick++;
 811
 812           else if (INSN_P (insn))
 813             {
 814               /* See if we know about function return values before this
 815                  insn based upon SUBREG flags.  */
 816               check_conversions (insn, PATTERN (insn));
 817
 818               /* Try this insn with each insn it links back to.  */
 819
 820               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 821                 if ((next = try_combine (insn, XEXP (links, 0),
 822                                          NULL_RTX, &new_direct_jump_p)) != 0)
 823                   goto retry;
 824
 825               /* Try each sequence of three linked insns ending with this one.  */
 826
 827               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 828                 {
 829                   rtx link = XEXP (links, 0);
 830
 831                   /* If the linked insn has been replaced by a note, then there
 832                      is no point in pursuing this chain any further.  */
 833                   if (NOTE_P (link))
 834                     continue;
 835
 836                   for (nextlinks = LOG_LINKS (link);
 837                        nextlinks;
 838                        nextlinks = XEXP (nextlinks, 1))
 839                     if ((next = try_combine (insn, link,
 840                                              XEXP (nextlinks, 0),
 841                                              &new_direct_jump_p)) != 0)
 842                       goto retry;
 843                 }
 844
 845 #ifdef HAVE_cc0
 846               /* Try to combine a jump insn that uses CC0
 847                  with a preceding insn that sets CC0, and maybe with its
 848                  logical predecessor as well.
 849                  This is how we make decrement-and-branch insns.
 850                  We need this special code because data flow connections
 851                  via CC0 do not get entered in LOG_LINKS.  */
 852
 853               if (JUMP_P (insn)
 854                   && (prev = prev_nonnote_insn (insn)) != 0
 855                   && NONJUMP_INSN_P (prev)
 856                   && sets_cc0_p (PATTERN (prev)))
 857                 {
 858                   if ((next = try_combine (insn, prev,
 859                                            NULL_RTX, &new_direct_jump_p)) != 0)
 860                     goto retry;
 861
 862                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 863                        nextlinks = XEXP (nextlinks, 1))
 864                     if ((next = try_combine (insn, prev,
 865                                              XEXP (nextlinks, 0),
 866                                              &new_direct_jump_p)) != 0)
 867                       goto retry;
 868                 }
 869
 870               /* Do the same for an insn that explicitly references CC0.  */
 871               if (NONJUMP_INSN_P (insn)
 872                   && (prev = prev_nonnote_insn (insn)) != 0
 873                   && NONJUMP_INSN_P (prev)
 874                   && sets_cc0_p (PATTERN (prev))
 875                   && GET_CODE (PATTERN (insn)) == SET
 876                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 877                 {
 878                   if ((next = try_combine (insn, prev,
 879                                            NULL_RTX, &new_direct_jump_p)) != 0)
 880                     goto retry;
 881
 882                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 883                        nextlinks = XEXP (nextlinks, 1))
 884                     if ((next = try_combine (insn, prev,
 885                                              XEXP (nextlinks, 0),
 886                                              &new_direct_jump_p)) != 0)
 887                       goto retry;
 888                 }
 889
 890               /* Finally, see if any of the insns that this insn links to
 891                  explicitly references CC0.  If so, try this insn, that insn,
 892                  and its predecessor if it sets CC0.  */
 893               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 894                 if (NONJUMP_INSN_P (XEXP (links, 0))
 895                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 896                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 897                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 898                     && NONJUMP_INSN_P (prev)
 899                     && sets_cc0_p (PATTERN (prev))
 900                     && (next = try_combine (insn, XEXP (links, 0),
 901                                             prev, &new_direct_jump_p)) != 0)
 902                   goto retry;
 903 #endif
 904
 905               /* Try combining an insn with two different insns whose results it
 906                  uses.  */
 907               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 908                 for (nextlinks = XEXP (links, 1); nextlinks;
 909                      nextlinks = XEXP (nextlinks, 1))
 910                   if ((next = try_combine (insn, XEXP (links, 0),
 911                                            XEXP (nextlinks, 0),
 912                                            &new_direct_jump_p)) != 0)
 913                     goto retry;
 914
 915               /* Try this insn with each REG_EQUAL note it links back to.  */
 916               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 917                 {
 918                   rtx set, note;
 919                   rtx temp = XEXP (links, 0);
 920                   if ((set = single_set (temp)) != 0
 921                       && (note = find_reg_equal_equiv_note (temp)) != 0
 922                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 923                       /* Avoid using a register that may already been marked
 924                          dead by an earlier instruction.  */
 925                       && ! unmentioned_reg_p (note, SET_SRC (set))
 926                       && (GET_MODE (note) == VOIDmode
 927                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 928                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 929                     {
 930                       /* Temporarily replace the set's source with the
 931                          contents of the REG_EQUAL note.  The insn will
 932                          be deleted or recognized by try_combine.  */
 933                       rtx orig = SET_SRC (set);
 934                       SET_SRC (set) = note;
 935                       replaced_rhs_insn = temp;
 936                       replaced_rhs_value = copy_rtx (note);
 937                       next = try_combine (insn, temp, NULL_RTX,
 938                                           &new_direct_jump_p);
 939                       replaced_rhs_insn = NULL;
 940                       if (next)
 941                         goto retry;
 942                       SET_SRC (set) = orig;
 943                     }
 944                 }
 945
 946               if (!NOTE_P (insn))
 947                 record_dead_and_set_regs (insn);
 948
 949             retry:
 950               ;
 951             }
 952         }
 953     }
 954   clear_bb_flags ();
 955
 956   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 957     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 958   new_direct_jump_p |= purge_all_dead_edges ();
 959   delete_noop_moves ();
 960
 961   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 962                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 963                                     | PROP_KILL_DEAD_CODE);
 964
 965   /* Clean up.  */
 966   sbitmap_free (refresh_blocks);
 967   free (uid_insn_cost);
 968   free (reg_stat);
 969   free (uid_cuid);
 970
 971   {
 972     struct undo *undo, *next;
 973     for (undo = undobuf.frees; undo; undo = next)
 974       {
 975         next = undo->next;
 976         free (undo);
 977       }
 978     undobuf.frees = 0;
 979   }
 980
 981   total_attempts += combine_attempts;
 982   total_merges += combine_merges;
 983   total_extras += combine_extras;
 984   total_successes += combine_successes;
 985
 986   nonzero_sign_valid = 0;
 987   rtl_hooks = general_rtl_hooks;
 988
 989   /* Make recognizer allow volatile MEMs again.  */
 990   init_recog ();
 991
 992   return new_direct_jump_p;
 993 }
 994
 995 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
 996
 997 static void
 998 init_reg_last (void)
 999 {
1000   unsigned int i;
1001   for (i = 0; i < combine_max_regno; i++)
1002     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
1003 }
1004 \f
1005 /* Set up any promoted values for incoming argument registers.  */
1006
1007 static void
1008 setup_incoming_promotions (void)
1009 {
1010   unsigned int regno;
1011   rtx reg;
1012   enum machine_mode mode;
1013   int unsignedp;
1014   rtx first = get_insns ();
1015
1016   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1017     {
1018       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1019         /* Check whether this register can hold an incoming pointer
1020            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
1021            numbers, so translate if necessary due to register windows.  */
1022         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1023             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1024           {
1025             record_value_for_reg
1026               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1027                                            : SIGN_EXTEND),
1028                                           GET_MODE (reg),
1029                                           gen_rtx_CLOBBER (mode, const0_rtx)));
1030           }
1031     }
1032 }
1033 \f
1034 /* Called via note_stores.  If X is a pseudo that is narrower than
1035    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1036
1037    If we are setting only a portion of X and we can't figure out what
1038    portion, assume all bits will be used since we don't know what will
1039    be happening.
1040
1041    Similarly, set how many bits of X are known to be copies of the sign bit
1042    at all locations in the function.  This is the smallest number implied
1043    by any set of X.  */
1044
1045 static void
1046 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1047                                   void *data ATTRIBUTE_UNUSED)
1048 {
1049   unsigned int num;
1050
1051   if (REG_P (x)
1052       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1053       /* If this register is undefined at the start of the file, we can't
1054          say what its contents were.  */
1055       && ! REGNO_REG_SET_P
1056          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1057       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1058     {
1059       if (set == 0 || GET_CODE (set) == CLOBBER)
1060         {
1061           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1062           reg_stat[REGNO (x)].sign_bit_copies = 1;
1063           return;
1064         }
1065
1066       /* If this is a complex assignment, see if we can convert it into a
1067          simple assignment.  */
1068       set = expand_field_assignment (set);
1069
1070       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1071          set what we know about X.  */
1072
1073       if (SET_DEST (set) == x
1074           || (GET_CODE (SET_DEST (set)) == SUBREG
1075               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1076                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1077               && SUBREG_REG (SET_DEST (set)) == x))
1078         {
1079           rtx src = SET_SRC (set);
1080
1081 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1082           /* If X is narrower than a word and SRC is a non-negative
1083              constant that would appear negative in the mode of X,
1084              sign-extend it for use in reg_stat[].nonzero_bits because some
1085              machines (maybe most) will actually do the sign-extension
1086              and this is the conservative approach.
1087
1088              ??? For 2.5, try to tighten up the MD files in this regard
1089              instead of this kludge.  */
1090
1091           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1092               && GET_CODE (src) == CONST_INT
1093               && INTVAL (src) > 0
1094               && 0 != (INTVAL (src)
1095                        & ((HOST_WIDE_INT) 1
1096                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1097             src = GEN_INT (INTVAL (src)
1098                            | ((HOST_WIDE_INT) (-1)
1099                               << GET_MODE_BITSIZE (GET_MODE (x))));
1100 #endif
1101
1102           /* Don't call nonzero_bits if it cannot change anything.  */
1103           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1104             reg_stat[REGNO (x)].nonzero_bits
1105               |= nonzero_bits (src, nonzero_bits_mode);
1106           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1107           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1108               || reg_stat[REGNO (x)].sign_bit_copies > num)
1109             reg_stat[REGNO (x)].sign_bit_copies = num;
1110         }
1111       else
1112         {
1113           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1114           reg_stat[REGNO (x)].sign_bit_copies = 1;
1115         }
1116     }
1117 }
1118 \f
1119 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1120    insns that were previously combined into I3 or that will be combined
1121    into the merger of INSN and I3.
1122
1123    Return 0 if the combination is not allowed for any reason.
1124
1125    If the combination is allowed, *PDEST will be set to the single
1126    destination of INSN and *PSRC to the single source, and this function
1127    will return 1.  */
1128
1129 static int
1130 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1131                rtx *pdest, rtx *psrc)
1132 {
1133   int i;
1134   rtx set = 0, src, dest;
1135   rtx p;
1136 #ifdef AUTO_INC_DEC
1137   rtx link;
1138 #endif
1139   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1140                               && next_active_insn (succ) == i3)
1141                       : next_active_insn (insn) == i3);
1142
1143   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1144      or a PARALLEL consisting of such a SET and CLOBBERs.
1145
1146      If INSN has CLOBBER parallel parts, ignore them for our processing.
1147      By definition, these happen during the execution of the insn.  When it
1148      is merged with another insn, all bets are off.  If they are, in fact,
1149      needed and aren't also supplied in I3, they may be added by
1150      recog_for_combine.  Otherwise, it won't match.
1151
1152      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1153      note.
1154
1155      Get the source and destination of INSN.  If more than one, can't
1156      combine.  */
1157
1158   if (GET_CODE (PATTERN (insn)) == SET)
1159     set = PATTERN (insn);
1160   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1161            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1162     {
1163       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1164         {
1165           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1166           rtx note;
1167
1168           switch (GET_CODE (elt))
1169             {
1170             /* This is important to combine floating point insns
1171                for the SH4 port.  */
1172             case USE:
1173               /* Combining an isolated USE doesn't make sense.
1174                  We depend here on combinable_i3pat to reject them.  */
1175               /* The code below this loop only verifies that the inputs of
1176                  the SET in INSN do not change.  We call reg_set_between_p
1177                  to verify that the REG in the USE does not change between
1178                  I3 and INSN.
1179                  If the USE in INSN was for a pseudo register, the matching
1180                  insn pattern will likely match any register; combining this
1181                  with any other USE would only be safe if we knew that the
1182                  used registers have identical values, or if there was
1183                  something to tell them apart, e.g. different modes.  For
1184                  now, we forgo such complicated tests and simply disallow
1185                  combining of USES of pseudo registers with any other USE.  */
1186               if (REG_P (XEXP (elt, 0))
1187                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1188                 {
1189                   rtx i3pat = PATTERN (i3);
1190                   int i = XVECLEN (i3pat, 0) - 1;
1191                   unsigned int regno = REGNO (XEXP (elt, 0));
1192
1193                   do
1194                     {
1195                       rtx i3elt = XVECEXP (i3pat, 0, i);
1196
1197                       if (GET_CODE (i3elt) == USE
1198                           && REG_P (XEXP (i3elt, 0))
1199                           && (REGNO (XEXP (i3elt, 0)) == regno
1200                               ? reg_set_between_p (XEXP (elt, 0),
1201                                                    PREV_INSN (insn), i3)
1202                               : regno >= FIRST_PSEUDO_REGISTER))
1203                         return 0;
1204                     }
1205                   while (--i >= 0);
1206                 }
1207               break;
1208
1209               /* We can ignore CLOBBERs.  */
1210             case CLOBBER:
1211               break;
1212
1213             case SET:
1214               /* Ignore SETs whose result isn't used but not those that
1215                  have side-effects.  */
1216               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1217                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1218                       || INTVAL (XEXP (note, 0)) <= 0)
1219                   && ! side_effects_p (elt))
1220                 break;
1221
1222               /* If we have already found a SET, this is a second one and
1223                  so we cannot combine with this insn.  */
1224               if (set)
1225                 return 0;
1226
1227               set = elt;
1228               break;
1229
1230             default:
1231               /* Anything else means we can't combine.  */
1232               return 0;
1233             }
1234         }
1235
1236       if (set == 0
1237           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1238              so don't do anything with it.  */
1239           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1240         return 0;
1241     }
1242   else
1243     return 0;
1244
1245   if (set == 0)
1246     return 0;
1247
1248   set = expand_field_assignment (set);
1249   src = SET_SRC (set), dest = SET_DEST (set);
1250
1251   /* Don't eliminate a store in the stack pointer.  */
1252   if (dest == stack_pointer_rtx
1253       /* Don't combine with an insn that sets a register to itself if it has
1254          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1255       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1256       /* Can't merge an ASM_OPERANDS.  */
1257       || GET_CODE (src) == ASM_OPERANDS
1258       /* Can't merge a function call.  */
1259       || GET_CODE (src) == CALL
1260       /* Don't eliminate a function call argument.  */
1261       || (CALL_P (i3)
1262           && (find_reg_fusage (i3, USE, dest)
1263               || (REG_P (dest)
1264                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1265                   && global_regs[REGNO (dest)])))
1266       /* Don't substitute into an incremented register.  */
1267       || FIND_REG_INC_NOTE (i3, dest)
1268       || (succ && FIND_REG_INC_NOTE (succ, dest))
1269       /* Don't substitute into a non-local goto, this confuses CFG.  */
1270       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1271 #if 0
1272       /* Don't combine the end of a libcall into anything.  */
1273       /* ??? This gives worse code, and appears to be unnecessary, since no
1274          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1275          use REG_RETVAL notes for noconflict blocks, but other code here
1276          makes sure that those insns don't disappear.  */
1277       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1278 #endif
1279       /* Make sure that DEST is not used after SUCC but before I3.  */
1280       || (succ && ! all_adjacent
1281           && reg_used_between_p (dest, succ, i3))
1282       /* Make sure that the value that is to be substituted for the register
1283          does not use any registers whose values alter in between.  However,
1284          If the insns are adjacent, a use can't cross a set even though we
1285          think it might (this can happen for a sequence of insns each setting
1286          the same destination; last_set of that register might point to
1287          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1288          equivalent to the memory so the substitution is valid even if there
1289          are intervening stores.  Also, don't move a volatile asm or
1290          UNSPEC_VOLATILE across any other insns.  */
1291       || (! all_adjacent
1292           && (((!MEM_P (src)
1293                 || ! find_reg_note (insn, REG_EQUIV, src))
1294                && use_crosses_set_p (src, INSN_CUID (insn)))
1295               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1296               || GET_CODE (src) == UNSPEC_VOLATILE))
1297       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1298          better register allocation by not doing the combine.  */
1299       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1300       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1301       /* Don't combine across a CALL_INSN, because that would possibly
1302          change whether the life span of some REGs crosses calls or not,
1303          and it is a pain to update that information.
1304          Exception: if source is a constant, moving it later can't hurt.
1305          Accept that special case, because it helps -fforce-addr a lot.  */
1306       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1307     return 0;
1308
1309   /* DEST must either be a REG or CC0.  */
1310   if (REG_P (dest))
1311     {
1312       /* If register alignment is being enforced for multi-word items in all
1313          cases except for parameters, it is possible to have a register copy
1314          insn referencing a hard register that is not allowed to contain the
1315          mode being copied and which would not be valid as an operand of most
1316          insns.  Eliminate this problem by not combining with such an insn.
1317
1318          Also, on some machines we don't want to extend the life of a hard
1319          register.  */
1320
1321       if (REG_P (src)
1322           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1323                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1324               /* Don't extend the life of a hard register unless it is
1325                  user variable (if we have few registers) or it can't
1326                  fit into the desired register (meaning something special
1327                  is going on).
1328                  Also avoid substituting a return register into I3, because
1329                  reload can't handle a conflict with constraints of other
1330                  inputs.  */
1331               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1332                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1333         return 0;
1334     }
1335   else if (GET_CODE (dest) != CC0)
1336     return 0;
1337
1338
1339   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1340     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1341       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1342         {
1343           /* Don't substitute for a register intended as a clobberable
1344              operand.  */
1345           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1346           if (rtx_equal_p (reg, dest))
1347             return 0;
1348
1349           /* If the clobber represents an earlyclobber operand, we must not
1350              substitute an expression containing the clobbered register.
1351              As we do not analyze the constraint strings here, we have to
1352              make the conservative assumption.  However, if the register is
1353              a fixed hard reg, the clobber cannot represent any operand;
1354              we leave it up to the machine description to either accept or
1355              reject use-and-clobber patterns.  */
1356           if (!REG_P (reg)
1357               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1358               || !fixed_regs[REGNO (reg)])
1359             if (reg_overlap_mentioned_p (reg, src))
1360               return 0;
1361         }
1362
1363   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1364      or not), reject, unless nothing volatile comes between it and I3 */
1365
1366   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1367     {
1368       /* Make sure succ doesn't contain a volatile reference.  */
1369       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1370         return 0;
1371
1372       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1373         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1374           return 0;
1375     }
1376
1377   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1378      to be an explicit register variable, and was chosen for a reason.  */
1379
1380   if (GET_CODE (src) == ASM_OPERANDS
1381       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1382     return 0;
1383
1384   /* If there are any volatile insns between INSN and I3, reject, because
1385      they might affect machine state.  */
1386
1387   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1388     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1389       return 0;
1390
1391   /* If INSN contains an autoincrement or autodecrement, make sure that
1392      register is not used between there and I3, and not already used in
1393      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1394      Also insist that I3 not be a jump; if it were one
1395      and the incremented register were spilled, we would lose.  */
1396
1397 #ifdef AUTO_INC_DEC
1398   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1399     if (REG_NOTE_KIND (link) == REG_INC
1400         && (JUMP_P (i3)
1401             || reg_used_between_p (XEXP (link, 0), insn, i3)
1402             || (pred != NULL_RTX
1403                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1404             || (succ != NULL_RTX
1405                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1406             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1407       return 0;
1408 #endif
1409
1410 #ifdef HAVE_cc0
1411   /* Don't combine an insn that follows a CC0-setting insn.
1412      An insn that uses CC0 must not be separated from the one that sets it.
1413      We do, however, allow I2 to follow a CC0-setting insn if that insn
1414      is passed as I1; in that case it will be deleted also.
1415      We also allow combining in this case if all the insns are adjacent
1416      because that would leave the two CC0 insns adjacent as well.
1417      It would be more logical to test whether CC0 occurs inside I1 or I2,
1418      but that would be much slower, and this ought to be equivalent.  */
1419
1420   p = prev_nonnote_insn (insn);
1421   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1422       && ! all_adjacent)
1423     return 0;
1424 #endif
1425
1426   /* If we get here, we have passed all the tests and the combination is
1427      to be allowed.  */
1428
1429   *pdest = dest;
1430   *psrc = src;
1431
1432   return 1;
1433 }
1434 \f
1435 /* LOC is the location within I3 that contains its pattern or the component
1436    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1437
1438    One problem is if I3 modifies its output, as opposed to replacing it
1439    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1440    so would produce an insn that is not equivalent to the original insns.
1441
1442    Consider:
1443
1444          (set (reg:DI 101) (reg:DI 100))
1445          (set (subreg:SI (reg:DI 101) 0) <foo>)
1446
1447    This is NOT equivalent to:
1448
1449          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1450                     (set (reg:DI 101) (reg:DI 100))])
1451
1452    Not only does this modify 100 (in which case it might still be valid
1453    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1454
1455    We can also run into a problem if I2 sets a register that I1
1456    uses and I1 gets directly substituted into I3 (not via I2).  In that
1457    case, we would be getting the wrong value of I2DEST into I3, so we
1458    must reject the combination.  This case occurs when I2 and I1 both
1459    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1460    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1461    of a SET must prevent combination from occurring.
1462
1463    Before doing the above check, we first try to expand a field assignment
1464    into a set of logical operations.
1465
1466    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1467    we place a register that is both set and used within I3.  If more than one
1468    such register is detected, we fail.
1469
1470    Return 1 if the combination is valid, zero otherwise.  */
1471
1472 static int
1473 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1474                   int i1_not_in_src, rtx *pi3dest_killed)
1475 {
1476   rtx x = *loc;
1477
1478   if (GET_CODE (x) == SET)
1479     {
1480       rtx set = x ;
1481       rtx dest = SET_DEST (set);
1482       rtx src = SET_SRC (set);
1483       rtx inner_dest = dest;
1484       rtx subdest;
1485
1486       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1487              || GET_CODE (inner_dest) == SUBREG
1488              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1489         inner_dest = XEXP (inner_dest, 0);
1490
1491       /* Check for the case where I3 modifies its output, as discussed
1492          above.  We don't want to prevent pseudos from being combined
1493          into the address of a MEM, so only prevent the combination if
1494          i1 or i2 set the same MEM.  */
1495       if ((inner_dest != dest &&
1496            (!MEM_P (inner_dest)
1497             || rtx_equal_p (i2dest, inner_dest)
1498             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1499            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1500                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1501
1502           /* This is the same test done in can_combine_p except we can't test
1503              all_adjacent; we don't have to, since this instruction will stay
1504              in place, thus we are not considering increasing the lifetime of
1505              INNER_DEST.
1506
1507              Also, if this insn sets a function argument, combining it with
1508              something that might need a spill could clobber a previous
1509              function argument; the all_adjacent test in can_combine_p also
1510              checks this; here, we do a more specific test for this case.  */
1511
1512           || (REG_P (inner_dest)
1513               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1514               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1515                                         GET_MODE (inner_dest))))
1516           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1517         return 0;
1518
1519       /* If DEST is used in I3, it is being killed in this insn, so
1520          record that for later.  We have to consider paradoxical
1521          subregs here, since they kill the whole register, but we
1522          ignore partial subregs, STRICT_LOW_PART, etc.
1523          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1524          STACK_POINTER_REGNUM, since these are always considered to be
1525          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1526       subdest = dest;
1527       if (GET_CODE (subdest) == SUBREG
1528           && (GET_MODE_SIZE (GET_MODE (subdest))
1529               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1530         subdest = SUBREG_REG (subdest);
1531       if (pi3dest_killed
1532           && REG_P (subdest)
1533           && reg_referenced_p (subdest, PATTERN (i3))
1534           && REGNO (subdest) != FRAME_POINTER_REGNUM
1535 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1536           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1537 #endif
1538 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1539           && (REGNO (subdest) != ARG_POINTER_REGNUM
1540               || ! fixed_regs [REGNO (subdest)])
1541 #endif
1542           && REGNO (subdest) != STACK_POINTER_REGNUM)
1543         {
1544           if (*pi3dest_killed)
1545             return 0;
1546
1547           *pi3dest_killed = subdest;
1548         }
1549     }
1550
1551   else if (GET_CODE (x) == PARALLEL)
1552     {
1553       int i;
1554
1555       for (i = 0; i < XVECLEN (x, 0); i++)
1556         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1557                                 i1_not_in_src, pi3dest_killed))
1558           return 0;
1559     }
1560
1561   return 1;
1562 }
1563 \f
1564 /* Return 1 if X is an arithmetic expression that contains a multiplication
1565    and division.  We don't count multiplications by powers of two here.  */
1566
1567 static int
1568 contains_muldiv (rtx x)
1569 {
1570   switch (GET_CODE (x))
1571     {
1572     case MOD:  case DIV:  case UMOD:  case UDIV:
1573       return 1;
1574
1575     case MULT:
1576       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1577                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1578     default:
1579       if (BINARY_P (x))
1580         return contains_muldiv (XEXP (x, 0))
1581             || contains_muldiv (XEXP (x, 1));
1582
1583       if (UNARY_P (x))
1584         return contains_muldiv (XEXP (x, 0));
1585
1586       return 0;
1587     }
1588 }
1589 \f
1590 /* Determine whether INSN can be used in a combination.  Return nonzero if
1591    not.  This is used in try_combine to detect early some cases where we
1592    can't perform combinations.  */
1593
1594 static int
1595 cant_combine_insn_p (rtx insn)
1596 {
1597   rtx set;
1598   rtx src, dest;
1599
1600   /* If this isn't really an insn, we can't do anything.
1601      This can occur when flow deletes an insn that it has merged into an
1602      auto-increment address.  */
1603   if (! INSN_P (insn))
1604     return 1;
1605
1606   /* Never combine loads and stores involving hard regs that are likely
1607      to be spilled.  The register allocator can usually handle such
1608      reg-reg moves by tying.  If we allow the combiner to make
1609      substitutions of likely-spilled regs, reload might die.
1610      As an exception, we allow combinations involving fixed regs; these are
1611      not available to the register allocator so there's no risk involved.  */
1612
1613   set = single_set (insn);
1614   if (! set)
1615     return 0;
1616   src = SET_SRC (set);
1617   dest = SET_DEST (set);
1618   if (GET_CODE (src) == SUBREG)
1619     src = SUBREG_REG (src);
1620   if (GET_CODE (dest) == SUBREG)
1621     dest = SUBREG_REG (dest);
1622   if (REG_P (src) && REG_P (dest)
1623       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1624            && ! fixed_regs[REGNO (src)]
1625            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1626           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1627               && ! fixed_regs[REGNO (dest)]
1628               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1629     return 1;
1630
1631   return 0;
1632 }
1633
1634 struct likely_spilled_retval_info
1635 {
1636   unsigned regno, nregs;
1637   unsigned mask;
1638 };
1639
1640 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1641    hard registers that are known to be written to / clobbered in full.  */
1642 static void
1643 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1644 {
1645   struct likely_spilled_retval_info *info = data;
1646   unsigned regno, nregs;
1647   unsigned new_mask;
1648
1649   if (!REG_P (XEXP (set, 0)))
1650     return;
1651   regno = REGNO (x);
1652   if (regno >= info->regno + info->nregs)
1653     return;
1654   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1655   if (regno + nregs <= info->regno)
1656     return;
1657   new_mask = (2U << (nregs - 1)) - 1;
1658   if (regno < info->regno)
1659     new_mask >>= info->regno - regno;
1660   else
1661     new_mask <<= regno - info->regno;
1662   info->mask &= ~new_mask;
1663 }
1664
1665 /* Return nonzero iff part of the return value is live during INSN, and
1666    it is likely spilled.  This can happen when more than one insn is needed
1667    to copy the return value, e.g. when we consider to combine into the
1668    second copy insn for a complex value.  */
1669
1670 static int
1671 likely_spilled_retval_p (rtx insn)
1672 {
1673   rtx use = BB_END (this_basic_block);
1674   rtx reg, p;
1675   unsigned regno, nregs;
1676   /* We assume here that no machine mode needs more than
1677      32 hard registers when the value overlaps with a register
1678      for which FUNCTION_VALUE_REGNO_P is true.  */
1679   unsigned mask;
1680   struct likely_spilled_retval_info info;
1681
1682   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1683     return 0;
1684   reg = XEXP (PATTERN (use), 0);
1685   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1686     return 0;
1687   regno = REGNO (reg);
1688   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1689   if (nregs == 1)
1690     return 0;
1691   mask = (2U << (nregs - 1)) - 1;
1692
1693   /* Disregard parts of the return value that are set later.  */
1694   info.regno = regno;
1695   info.nregs = nregs;
1696   info.mask = mask;
1697   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1698     if (INSN_P (p))
1699       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
1700   mask = info.mask;
1701
1702   /* Check if any of the (probably) live return value registers is
1703      likely spilled.  */
1704   nregs --;
1705   do
1706     {
1707       if ((mask & 1 << nregs)
1708           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1709         return 1;
1710     } while (nregs--);
1711   return 0;
1712 }
1713
1714 /* Adjust INSN after we made a change to its destination.
1715
1716    Changing the destination can invalidate notes that say something about
1717    the results of the insn and a LOG_LINK pointing to the insn.  */
1718
1719 static void
1720 adjust_for_new_dest (rtx insn)
1721 {
1722   rtx *loc;
1723
1724   /* For notes, be conservative and simply remove them.  */
1725   loc = &REG_NOTES (insn);
1726   while (*loc)
1727     {
1728       enum reg_note kind = REG_NOTE_KIND (*loc);
1729       if (kind == REG_EQUAL || kind == REG_EQUIV)
1730         *loc = XEXP (*loc, 1);
1731       else
1732         loc = &XEXP (*loc, 1);
1733     }
1734
1735   /* The new insn will have a destination that was previously the destination
1736      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1737      the next use of that destination.  */
1738   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1739 }
1740
1741 /* Return TRUE if combine can reuse reg X in mode MODE.
1742    ADDED_SETS is nonzero if the original set is still required.  */
1743 static bool
1744 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1745 {
1746   unsigned int regno;
1747
1748   if (!REG_P(x))
1749     return false;
1750
1751   regno = REGNO (x);
1752   /* Allow hard registers if the new mode is legal, and occupies no more
1753      registers than the old mode.  */
1754   if (regno < FIRST_PSEUDO_REGISTER)
1755     return (HARD_REGNO_MODE_OK (regno, mode)
1756             && (hard_regno_nregs[regno][GET_MODE (x)]
1757                 >= hard_regno_nregs[regno][mode]));
1758
1759   /* Or a pseudo that is only used once.  */
1760   return (REG_N_SETS (regno) == 1 && !added_sets
1761           && !REG_USERVAR_P (x));
1762 }
1763
1764
1765 /* Check whether X, the destination of a set, refers to part of
1766    the register specified by REG.  */
1767
1768 static bool
1769 reg_subword_p (rtx x, rtx reg)
1770 {
1771   /* Check that reg is an integer mode register.  */
1772   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1773     return false;
1774
1775   if (GET_CODE (x) == STRICT_LOW_PART
1776       || GET_CODE (x) == ZERO_EXTRACT)
1777     x = XEXP (x, 0);
1778
1779   return GET_CODE (x) == SUBREG
1780          && SUBREG_REG (x) == reg
1781          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1782 }
1783
1784
1785 /* Try to combine the insns I1 and I2 into I3.
1786    Here I1 and I2 appear earlier than I3.
1787    I1 can be zero; then we combine just I2 into I3.
1788
1789    If we are combining three insns and the resulting insn is not recognized,
1790    try splitting it into two insns.  If that happens, I2 and I3 are retained
1791    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1792    are pseudo-deleted.
1793
1794    Return 0 if the combination does not work.  Then nothing is changed.
1795    If we did the combination, return the insn at which combine should
1796    resume scanning.
1797
1798    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1799    new direct jump instruction.  */
1800
1801 static rtx
1802 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1803 {
1804   /* New patterns for I3 and I2, respectively.  */
1805   rtx newpat, newi2pat = 0;
1806   rtvec newpat_vec_with_clobbers = 0;
1807   int substed_i2 = 0, substed_i1 = 0;
1808   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1809   int added_sets_1, added_sets_2;
1810   /* Total number of SETs to put into I3.  */
1811   int total_sets;
1812   /* Nonzero if I2's body now appears in I3.  */
1813   int i2_is_used;
1814   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1815   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1816   /* Contains I3 if the destination of I3 is used in its source, which means
1817      that the old life of I3 is being killed.  If that usage is placed into
1818      I2 and not in I3, a REG_DEAD note must be made.  */
1819   rtx i3dest_killed = 0;
1820   /* SET_DEST and SET_SRC of I2 and I1.  */
1821   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1822   /* PATTERN (I2), or a copy of it in certain cases.  */
1823   rtx i2pat;
1824   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1825   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1826   int i2dest_killed = 0, i1dest_killed = 0;
1827   int i1_feeds_i3 = 0;
1828   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1829   rtx new_i3_notes, new_i2_notes;
1830   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1831   int i3_subst_into_i2 = 0;
1832   /* Notes that I1, I2 or I3 is a MULT operation.  */
1833   int have_mult = 0;
1834   int swap_i2i3 = 0;
1835
1836   int maxreg;
1837   rtx temp;
1838   rtx link;
1839   int i;
1840
1841   /* Exit early if one of the insns involved can't be used for
1842      combinations.  */
1843   if (cant_combine_insn_p (i3)
1844       || cant_combine_insn_p (i2)
1845       || (i1 && cant_combine_insn_p (i1))
1846       || likely_spilled_retval_p (i3)
1847       /* We also can't do anything if I3 has a
1848          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1849          libcall.  */
1850 #if 0
1851       /* ??? This gives worse code, and appears to be unnecessary, since no
1852          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1853       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1854 #endif
1855       )
1856     return 0;
1857
1858   combine_attempts++;
1859   undobuf.other_insn = 0;
1860
1861   /* Reset the hard register usage information.  */
1862   CLEAR_HARD_REG_SET (newpat_used_regs);
1863
1864   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1865      code below, set I1 to be the earlier of the two insns.  */
1866   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1867     temp = i1, i1 = i2, i2 = temp;
1868
1869   added_links_insn = 0;
1870
1871   /* First check for one important special-case that the code below will
1872      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1873      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1874      we may be able to replace that destination with the destination of I3.
1875      This occurs in the common code where we compute both a quotient and
1876      remainder into a structure, in which case we want to do the computation
1877      directly into the structure to avoid register-register copies.
1878
1879      Note that this case handles both multiple sets in I2 and also
1880      cases where I2 has a number of CLOBBER or PARALLELs.
1881
1882      We make very conservative checks below and only try to handle the
1883      most common cases of this.  For example, we only handle the case
1884      where I2 and I3 are adjacent to avoid making difficult register
1885      usage tests.  */
1886
1887   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1888       && REG_P (SET_SRC (PATTERN (i3)))
1889       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1890       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1891       && GET_CODE (PATTERN (i2)) == PARALLEL
1892       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1893       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1894          below would need to check what is inside (and reg_overlap_mentioned_p
1895          doesn't support those codes anyway).  Don't allow those destinations;
1896          the resulting insn isn't likely to be recognized anyway.  */
1897       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1898       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1899       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1900                                     SET_DEST (PATTERN (i3)))
1901       && next_real_insn (i2) == i3)
1902     {
1903       rtx p2 = PATTERN (i2);
1904
1905       /* Make sure that the destination of I3,
1906          which we are going to substitute into one output of I2,
1907          is not used within another output of I2.  We must avoid making this:
1908          (parallel [(set (mem (reg 69)) ...)
1909                     (set (reg 69) ...)])
1910          which is not well-defined as to order of actions.
1911          (Besides, reload can't handle output reloads for this.)
1912
1913          The problem can also happen if the dest of I3 is a memory ref,
1914          if another dest in I2 is an indirect memory ref.  */
1915       for (i = 0; i < XVECLEN (p2, 0); i++)
1916         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1917              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1918             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1919                                         SET_DEST (XVECEXP (p2, 0, i))))
1920           break;
1921
1922       if (i == XVECLEN (p2, 0))
1923         for (i = 0; i < XVECLEN (p2, 0); i++)
1924           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1925                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1926               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1927             {
1928               combine_merges++;
1929
1930               subst_insn = i3;
1931               subst_low_cuid = INSN_CUID (i2);
1932
1933               added_sets_2 = added_sets_1 = 0;
1934               i2dest = SET_SRC (PATTERN (i3));
1935               i2dest_killed = dead_or_set_p (i2, i2dest);
1936
1937               /* Replace the dest in I2 with our dest and make the resulting
1938                  insn the new pattern for I3.  Then skip to where we
1939                  validate the pattern.  Everything was set up above.  */
1940               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1941                      SET_DEST (PATTERN (i3)));
1942
1943               newpat = p2;
1944               i3_subst_into_i2 = 1;
1945               goto validate_replacement;
1946             }
1947     }
1948
1949   /* If I2 is setting a pseudo to a constant and I3 is setting some
1950      sub-part of it to another constant, merge them by making a new
1951      constant.  */
1952   if (i1 == 0
1953       && (temp = single_set (i2)) != 0
1954       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1955           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1956       && GET_CODE (PATTERN (i3)) == SET
1957       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1958           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1959       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1960     {
1961       rtx dest = SET_DEST (PATTERN (i3));
1962       int offset = -1;
1963       int width = 0;
1964
1965       if (GET_CODE (dest) == ZERO_EXTRACT)
1966         {
1967           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1968               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1969             {
1970               width = INTVAL (XEXP (dest, 1));
1971               offset = INTVAL (XEXP (dest, 2));
1972               dest = XEXP (dest, 0);
1973               if (BITS_BIG_ENDIAN)
1974                 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
1975             }
1976         }
1977       else
1978         {
1979           if (GET_CODE (dest) == STRICT_LOW_PART)
1980             dest = XEXP (dest, 0);
1981           width = GET_MODE_BITSIZE (GET_MODE (dest));
1982           offset = 0;
1983         }
1984
1985       if (offset >= 0)
1986         {
1987           /* If this is the low part, we're done.  */
1988           if (subreg_lowpart_p (dest))
1989             ;
1990           /* Handle the case where inner is twice the size of outer.  */
1991           else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1992                    == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1993             offset += GET_MODE_BITSIZE (GET_MODE (dest));
1994           /* Otherwise give up for now.  */
1995           else
1996             offset = -1;
1997         }
1998
1999       if (offset >= 0)
2000         {
2001           HOST_WIDE_INT mhi, ohi, ihi;
2002           HOST_WIDE_INT mlo, olo, ilo;
2003           rtx inner = SET_SRC (PATTERN (i3));
2004           rtx outer = SET_SRC (temp);
2005
2006           if (GET_CODE (outer) == CONST_INT)
2007             {
2008               olo = INTVAL (outer);
2009               ohi = olo < 0 ? -1 : 0;
2010             }
2011           else
2012             {
2013               olo = CONST_DOUBLE_LOW (outer);
2014               ohi = CONST_DOUBLE_HIGH (outer);
2015             }
2016
2017           if (GET_CODE (inner) == CONST_INT)
2018             {
2019               ilo = INTVAL (inner);
2020               ihi = ilo < 0 ? -1 : 0;
2021             }
2022           else
2023             {
2024               ilo = CONST_DOUBLE_LOW (inner);
2025               ihi = CONST_DOUBLE_HIGH (inner);
2026             }
2027
2028           if (width < HOST_BITS_PER_WIDE_INT)
2029             {
2030               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2031               mhi = 0;
2032             }
2033           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2034             {
2035               mhi = ((unsigned HOST_WIDE_INT) 1
2036                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2037               mlo = -1;
2038             }
2039           else
2040             {
2041               mlo = -1;
2042               mhi = -1;
2043             }
2044
2045           ilo &= mlo;
2046           ihi &= mhi;
2047
2048           if (offset >= HOST_BITS_PER_WIDE_INT)
2049             {
2050               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2051               mlo = 0;
2052               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2053               ilo = 0;
2054             }
2055           else if (offset > 0)
2056             {
2057               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2058                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2059               mlo = mlo << offset;
2060               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2061                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2062               ilo = ilo << offset;
2063             }
2064
2065           olo = (olo & ~mlo) | ilo;
2066           ohi = (ohi & ~mhi) | ihi;
2067
2068           combine_merges++;
2069           subst_insn = i3;
2070           subst_low_cuid = INSN_CUID (i2);
2071           added_sets_2 = added_sets_1 = 0;
2072           i2dest = SET_DEST (temp);
2073           i2dest_killed = dead_or_set_p (i2, i2dest);
2074
2075           SUBST (SET_SRC (temp),
2076                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2077
2078           newpat = PATTERN (i2);
2079           goto validate_replacement;
2080         }
2081     }
2082
2083 #ifndef HAVE_cc0
2084   /* If we have no I1 and I2 looks like:
2085         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2086                    (set Y OP)])
2087      make up a dummy I1 that is
2088         (set Y OP)
2089      and change I2 to be
2090         (set (reg:CC X) (compare:CC Y (const_int 0)))
2091
2092      (We can ignore any trailing CLOBBERs.)
2093
2094      This undoes a previous combination and allows us to match a branch-and-
2095      decrement insn.  */
2096
2097   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2098       && XVECLEN (PATTERN (i2), 0) >= 2
2099       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2100       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2101           == MODE_CC)
2102       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2103       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2104       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2105       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2106       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2107                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2108     {
2109       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2110         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2111           break;
2112
2113       if (i == 1)
2114         {
2115           /* We make I1 with the same INSN_UID as I2.  This gives it
2116              the same INSN_CUID for value tracking.  Our fake I1 will
2117              never appear in the insn stream so giving it the same INSN_UID
2118              as I2 will not cause a problem.  */
2119
2120           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2121                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2122                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2123                              NULL_RTX);
2124
2125           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2126           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2127                  SET_DEST (PATTERN (i1)));
2128         }
2129     }
2130 #endif
2131
2132   /* Verify that I2 and I1 are valid for combining.  */
2133   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2134       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2135     {
2136       undo_all ();
2137       return 0;
2138     }
2139
2140   /* Record whether I2DEST is used in I2SRC and similarly for the other
2141      cases.  Knowing this will help in register status updating below.  */
2142   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2143   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2144   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2145   i2dest_killed = dead_or_set_p (i2, i2dest);
2146   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2147
2148   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2149      in I2SRC.  */
2150   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2151
2152   /* Ensure that I3's pattern can be the destination of combines.  */
2153   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2154                           i1 && i2dest_in_i1src && i1_feeds_i3,
2155                           &i3dest_killed))
2156     {
2157       undo_all ();
2158       return 0;
2159     }
2160
2161   /* See if any of the insns is a MULT operation.  Unless one is, we will
2162      reject a combination that is, since it must be slower.  Be conservative
2163      here.  */
2164   if (GET_CODE (i2src) == MULT
2165       || (i1 != 0 && GET_CODE (i1src) == MULT)
2166       || (GET_CODE (PATTERN (i3)) == SET
2167           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2168     have_mult = 1;
2169
2170   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2171      We used to do this EXCEPT in one case: I3 has a post-inc in an
2172      output operand.  However, that exception can give rise to insns like
2173         mov r3,(r3)+
2174      which is a famous insn on the PDP-11 where the value of r3 used as the
2175      source was model-dependent.  Avoid this sort of thing.  */
2176
2177 #if 0
2178   if (!(GET_CODE (PATTERN (i3)) == SET
2179         && REG_P (SET_SRC (PATTERN (i3)))
2180         && MEM_P (SET_DEST (PATTERN (i3)))
2181         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2182             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2183     /* It's not the exception.  */
2184 #endif
2185 #ifdef AUTO_INC_DEC
2186     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2187       if (REG_NOTE_KIND (link) == REG_INC
2188           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2189               || (i1 != 0
2190                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2191         {
2192           undo_all ();
2193           return 0;
2194         }
2195 #endif
2196
2197   /* See if the SETs in I1 or I2 need to be kept around in the merged
2198      instruction: whenever the value set there is still needed past I3.
2199      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2200
2201      For the SET in I1, we have two cases:  If I1 and I2 independently
2202      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2203      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2204      in I1 needs to be kept around unless I1DEST dies or is set in either
2205      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2206      I1DEST.  If so, we know I1 feeds into I2.  */
2207
2208   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2209
2210   added_sets_1
2211     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2212                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2213
2214   /* If the set in I2 needs to be kept around, we must make a copy of
2215      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2216      PATTERN (I2), we are only substituting for the original I1DEST, not into
2217      an already-substituted copy.  This also prevents making self-referential
2218      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2219      I2DEST.  */
2220
2221   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2222            ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2223            : PATTERN (i2));
2224
2225   if (added_sets_2)
2226     i2pat = copy_rtx (i2pat);
2227
2228   combine_merges++;
2229
2230   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2231
2232   maxreg = max_reg_num ();
2233
2234   subst_insn = i3;
2235
2236 #ifndef HAVE_cc0
2237   /* Many machines that don't use CC0 have insns that can both perform an
2238      arithmetic operation and set the condition code.  These operations will
2239      be represented as a PARALLEL with the first element of the vector
2240      being a COMPARE of an arithmetic operation with the constant zero.
2241      The second element of the vector will set some pseudo to the result
2242      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2243      match such a pattern and so will generate an extra insn.   Here we test
2244      for this case, where both the comparison and the operation result are
2245      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2246      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2247
2248   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2249       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2250       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2251       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2252     {
2253 #ifdef SELECT_CC_MODE
2254       rtx *cc_use;
2255       enum machine_mode compare_mode;
2256 #endif
2257
2258       newpat = PATTERN (i3);
2259       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2260
2261       i2_is_used = 1;
2262
2263 #ifdef SELECT_CC_MODE
2264       /* See if a COMPARE with the operand we substituted in should be done
2265          with the mode that is currently being used.  If not, do the same
2266          processing we do in `subst' for a SET; namely, if the destination
2267          is used only once, try to replace it with a register of the proper
2268          mode and also replace the COMPARE.  */
2269       if (undobuf.other_insn == 0
2270           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2271                                         &undobuf.other_insn))
2272           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2273                                               i2src, const0_rtx))
2274               != GET_MODE (SET_DEST (newpat))))
2275         {
2276           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2277                                    compare_mode))
2278             {
2279               unsigned int regno = REGNO (SET_DEST (newpat));
2280               rtx new_dest;
2281
2282               if (regno < FIRST_PSEUDO_REGISTER)
2283                 new_dest = gen_rtx_REG (compare_mode, regno);
2284               else
2285                 {
2286                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2287                   new_dest = regno_reg_rtx[regno];
2288                 }
2289
2290               SUBST (SET_DEST (newpat), new_dest);
2291               SUBST (XEXP (*cc_use, 0), new_dest);
2292               SUBST (SET_SRC (newpat),
2293                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2294             }
2295           else
2296             undobuf.other_insn = 0;
2297         }
2298 #endif
2299     }
2300   else
2301 #endif
2302     {
2303       /* It is possible that the source of I2 or I1 may be performing
2304          an unneeded operation, such as a ZERO_EXTEND of something
2305          that is known to have the high part zero.  Handle that case
2306          by letting subst look at the innermost one of them.
2307
2308          Another way to do this would be to have a function that tries
2309          to simplify a single insn instead of merging two or more
2310          insns.  We don't do this because of the potential of infinite
2311          loops and because of the potential extra memory required.
2312          However, doing it the way we are is a bit of a kludge and
2313          doesn't catch all cases.
2314
2315          But only do this if -fexpensive-optimizations since it slows
2316          things down and doesn't usually win.
2317
2318          This is not done in the COMPARE case above because the
2319          unmodified I2PAT is used in the PARALLEL and so a pattern
2320          with a modified I2SRC would not match.  */
2321
2322       if (flag_expensive_optimizations)
2323         {
2324           /* Pass pc_rtx so no substitutions are done, just
2325              simplifications.  */
2326           if (i1)
2327             {
2328               subst_low_cuid = INSN_CUID (i1);
2329               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2330             }
2331           else
2332             {
2333               subst_low_cuid = INSN_CUID (i2);
2334               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2335             }
2336         }
2337
2338       n_occurrences = 0;                /* `subst' counts here */
2339
2340       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2341          need to make a unique copy of I2SRC each time we substitute it
2342          to avoid self-referential rtl.  */
2343
2344       subst_low_cuid = INSN_CUID (i2);
2345       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2346                       ! i1_feeds_i3 && i1dest_in_i1src);
2347       substed_i2 = 1;
2348
2349       /* Record whether i2's body now appears within i3's body.  */
2350       i2_is_used = n_occurrences;
2351     }
2352
2353   /* If we already got a failure, don't try to do more.  Otherwise,
2354      try to substitute in I1 if we have it.  */
2355
2356   if (i1 && GET_CODE (newpat) != CLOBBER)
2357     {
2358       /* Before we can do this substitution, we must redo the test done
2359          above (see detailed comments there) that ensures  that I1DEST
2360          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2361
2362       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2363                               0, (rtx*) 0))
2364         {
2365           undo_all ();
2366           return 0;
2367         }
2368
2369       n_occurrences = 0;
2370       subst_low_cuid = INSN_CUID (i1);
2371       newpat = subst (newpat, i1dest, i1src, 0, 0);
2372       substed_i1 = 1;
2373     }
2374
2375   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2376      to count all the ways that I2SRC and I1SRC can be used.  */
2377   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2378        && i2_is_used + added_sets_2 > 1)
2379       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2380           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2381               > 1))
2382       /* Fail if we tried to make a new register.  */
2383       || max_reg_num () != maxreg
2384       /* Fail if we couldn't do something and have a CLOBBER.  */
2385       || GET_CODE (newpat) == CLOBBER
2386       /* Fail if this new pattern is a MULT and we didn't have one before
2387          at the outer level.  */
2388       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2389           && ! have_mult))
2390     {
2391       undo_all ();
2392       return 0;
2393     }
2394
2395   /* If the actions of the earlier insns must be kept
2396      in addition to substituting them into the latest one,
2397      we must make a new PARALLEL for the latest insn
2398      to hold additional the SETs.  */
2399
2400   if (added_sets_1 || added_sets_2)
2401     {
2402       combine_extras++;
2403
2404       if (GET_CODE (newpat) == PARALLEL)
2405         {
2406           rtvec old = XVEC (newpat, 0);
2407           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2408           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2409           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2410                   sizeof (old->elem[0]) * old->num_elem);
2411         }
2412       else
2413         {
2414           rtx old = newpat;
2415           total_sets = 1 + added_sets_1 + added_sets_2;
2416           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2417           XVECEXP (newpat, 0, 0) = old;
2418         }
2419
2420       if (added_sets_1)
2421         XVECEXP (newpat, 0, --total_sets)
2422           = (GET_CODE (PATTERN (i1)) == PARALLEL
2423              ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2424
2425       if (added_sets_2)
2426         {
2427           /* If there is no I1, use I2's body as is.  We used to also not do
2428              the subst call below if I2 was substituted into I3,
2429              but that could lose a simplification.  */
2430           if (i1 == 0)
2431             XVECEXP (newpat, 0, --total_sets) = i2pat;
2432           else
2433             /* See comment where i2pat is assigned.  */
2434             XVECEXP (newpat, 0, --total_sets)
2435               = subst (i2pat, i1dest, i1src, 0, 0);
2436         }
2437     }
2438
2439   /* We come here when we are replacing a destination in I2 with the
2440      destination of I3.  */
2441  validate_replacement:
2442
2443   /* Note which hard regs this insn has as inputs.  */
2444   mark_used_regs_combine (newpat);
2445
2446   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2447      consider splitting this pattern, we might need these clobbers.  */
2448   if (i1 && GET_CODE (newpat) == PARALLEL
2449       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2450     {
2451       int len = XVECLEN (newpat, 0);
2452
2453       newpat_vec_with_clobbers = rtvec_alloc (len);
2454       for (i = 0; i < len; i++)
2455         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2456     }
2457
2458   /* Is the result of combination a valid instruction?  */
2459   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2460
2461   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2462      the second SET's destination is a register that is unused and isn't
2463      marked as an instruction that might trap in an EH region.  In that case,
2464      we just need the first SET.   This can occur when simplifying a divmod
2465      insn.  We *must* test for this case here because the code below that
2466      splits two independent SETs doesn't handle this case correctly when it
2467      updates the register status.
2468
2469      It's pointless doing this if we originally had two sets, one from
2470      i3, and one from i2.  Combining then splitting the parallel results
2471      in the original i2 again plus an invalid insn (which we delete).
2472      The net effect is only to move instructions around, which makes
2473      debug info less accurate.
2474
2475      Also check the case where the first SET's destination is unused.
2476      That would not cause incorrect code, but does cause an unneeded
2477      insn to remain.  */
2478
2479   if (insn_code_number < 0
2480       && !(added_sets_2 && i1 == 0)
2481       && GET_CODE (newpat) == PARALLEL
2482       && XVECLEN (newpat, 0) == 2
2483       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2484       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2485       && asm_noperands (newpat) < 0)
2486     {
2487       rtx set0 = XVECEXP (newpat, 0, 0);
2488       rtx set1 = XVECEXP (newpat, 0, 1);
2489       rtx note;
2490
2491       if (((REG_P (SET_DEST (set1))
2492             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2493            || (GET_CODE (SET_DEST (set1)) == SUBREG
2494                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2495           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2496               || INTVAL (XEXP (note, 0)) <= 0)
2497           && ! side_effects_p (SET_SRC (set1)))
2498         {
2499           newpat = set0;
2500           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2501         }
2502
2503       else if (((REG_P (SET_DEST (set0))
2504                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2505                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2506                     && find_reg_note (i3, REG_UNUSED,
2507                                       SUBREG_REG (SET_DEST (set0)))))
2508                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2509                    || INTVAL (XEXP (note, 0)) <= 0)
2510                && ! side_effects_p (SET_SRC (set0)))
2511         {
2512           newpat = set1;
2513           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2514
2515           if (insn_code_number >= 0)
2516             {
2517               /* If we will be able to accept this, we have made a
2518                  change to the destination of I3.  This requires us to
2519                  do a few adjustments.  */
2520
2521               PATTERN (i3) = newpat;
2522               adjust_for_new_dest (i3);
2523             }
2524         }
2525     }
2526
2527   /* If we were combining three insns and the result is a simple SET
2528      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2529      insns.  There are two ways to do this.  It can be split using a
2530      machine-specific method (like when you have an addition of a large
2531      constant) or by combine in the function find_split_point.  */
2532
2533   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2534       && asm_noperands (newpat) < 0)
2535     {
2536       rtx m_split, *split;
2537
2538       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2539          use I2DEST as a scratch register will help.  In the latter case,
2540          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2541
2542       m_split = split_insns (newpat, i3);
2543
2544       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2545          inputs of NEWPAT.  */
2546
2547       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2548          possible to try that as a scratch reg.  This would require adding
2549          more code to make it work though.  */
2550
2551       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2552         {
2553           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2554
2555           /* First try to split using the original register as a
2556              scratch register.  */
2557           m_split = split_insns (gen_rtx_PARALLEL
2558                                  (VOIDmode,
2559                                   gen_rtvec (2, newpat,
2560                                              gen_rtx_CLOBBER (VOIDmode,
2561                                                               i2dest))),
2562                                  i3);
2563
2564           /* If that didn't work, try changing the mode of I2DEST if
2565              we can.  */
2566           if (m_split == 0
2567               && new_mode != GET_MODE (i2dest)
2568               && new_mode != VOIDmode
2569               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2570             {
2571               enum machine_mode old_mode = GET_MODE (i2dest);
2572               rtx ni2dest;
2573
2574               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2575                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2576               else
2577                 {
2578                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2579                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
2580                 }
2581
2582               m_split = split_insns (gen_rtx_PARALLEL
2583                                      (VOIDmode,
2584                                       gen_rtvec (2, newpat,
2585                                                  gen_rtx_CLOBBER (VOIDmode,
2586                                                                   ni2dest))),
2587                                      i3);
2588
2589               if (m_split == 0
2590                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2591                 {
2592                   struct undo *buf;
2593
2594                   PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2595                   buf = undobuf.undos;
2596                   undobuf.undos = buf->next;
2597                   buf->next = undobuf.frees;
2598                   undobuf.frees = buf;
2599                 }
2600             }
2601         }
2602
2603       /* If recog_for_combine has discarded clobbers, try to use them
2604          again for the split.  */
2605       if (m_split == 0 && newpat_vec_with_clobbers)
2606         m_split
2607           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2608                                            newpat_vec_with_clobbers), i3);
2609
2610       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2611         {
2612           m_split = PATTERN (m_split);
2613           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2614           if (insn_code_number >= 0)
2615             newpat = m_split;
2616         }
2617       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2618                && (next_real_insn (i2) == i3
2619                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2620         {
2621           rtx i2set, i3set;
2622           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2623           newi2pat = PATTERN (m_split);
2624
2625           i3set = single_set (NEXT_INSN (m_split));
2626           i2set = single_set (m_split);
2627
2628           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2629
2630           /* If I2 or I3 has multiple SETs, we won't know how to track
2631              register status, so don't use these insns.  If I2's destination
2632              is used between I2 and I3, we also can't use these insns.  */
2633
2634           if (i2_code_number >= 0 && i2set && i3set
2635               && (next_real_insn (i2) == i3
2636                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2637             insn_code_number = recog_for_combine (&newi3pat, i3,
2638                                                   &new_i3_notes);
2639           if (insn_code_number >= 0)
2640             newpat = newi3pat;
2641
2642           /* It is possible that both insns now set the destination of I3.
2643              If so, we must show an extra use of it.  */
2644
2645           if (insn_code_number >= 0)
2646             {
2647               rtx new_i3_dest = SET_DEST (i3set);
2648               rtx new_i2_dest = SET_DEST (i2set);
2649
2650               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2651                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2652                      || GET_CODE (new_i3_dest) == SUBREG)
2653                 new_i3_dest = XEXP (new_i3_dest, 0);
2654
2655               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2656                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2657                      || GET_CODE (new_i2_dest) == SUBREG)
2658                 new_i2_dest = XEXP (new_i2_dest, 0);
2659
2660               if (REG_P (new_i3_dest)
2661                   && REG_P (new_i2_dest)
2662                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2663                 REG_N_SETS (REGNO (new_i2_dest))++;
2664             }
2665         }
2666
2667       /* If we can split it and use I2DEST, go ahead and see if that
2668          helps things be recognized.  Verify that none of the registers
2669          are set between I2 and I3.  */
2670       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2671 #ifdef HAVE_cc0
2672           && REG_P (i2dest)
2673 #endif
2674           /* We need I2DEST in the proper mode.  If it is a hard register
2675              or the only use of a pseudo, we can change its mode.
2676              Make sure we don't change a hard register to have a mode that
2677              isn't valid for it, or change the number of registers.  */
2678           && (GET_MODE (*split) == GET_MODE (i2dest)
2679               || GET_MODE (*split) == VOIDmode
2680               || can_change_dest_mode (i2dest, added_sets_2,
2681                                        GET_MODE (*split)))
2682           && (next_real_insn (i2) == i3
2683               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2684           /* We can't overwrite I2DEST if its value is still used by
2685              NEWPAT.  */
2686           && ! reg_referenced_p (i2dest, newpat))
2687         {
2688           rtx newdest = i2dest;
2689           enum rtx_code split_code = GET_CODE (*split);
2690           enum machine_mode split_mode = GET_MODE (*split);
2691           bool subst_done = false;
2692           newi2pat = NULL_RTX;
2693
2694           /* Get NEWDEST as a register in the proper mode.  We have already
2695              validated that we can do this.  */
2696           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2697             {
2698               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2699                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2700               else
2701                 {
2702                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2703                   newdest = regno_reg_rtx[REGNO (i2dest)];
2704                 }
2705             }
2706
2707           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2708              an ASHIFT.  This can occur if it was inside a PLUS and hence
2709              appeared to be a memory address.  This is a kludge.  */
2710           if (split_code == MULT
2711               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2712               && INTVAL (XEXP (*split, 1)) > 0
2713               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2714             {
2715               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2716                                              XEXP (*split, 0), GEN_INT (i)));
2717               /* Update split_code because we may not have a multiply
2718                  anymore.  */
2719               split_code = GET_CODE (*split);
2720             }
2721
2722 #ifdef INSN_SCHEDULING
2723           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2724              be written as a ZERO_EXTEND.  */
2725           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2726             {
2727 #ifdef LOAD_EXTEND_OP
2728               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2729                  what it really is.  */
2730               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2731                   == SIGN_EXTEND)
2732                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2733                                                     SUBREG_REG (*split)));
2734               else
2735 #endif
2736                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2737                                                     SUBREG_REG (*split)));
2738             }
2739 #endif
2740
2741           /* Attempt to split binary operators using arithmetic identities.  */
2742           if (BINARY_P (SET_SRC (newpat))
2743               && split_mode == GET_MODE (SET_SRC (newpat))
2744               && ! side_effects_p (SET_SRC (newpat)))
2745             {
2746               rtx setsrc = SET_SRC (newpat);
2747               enum machine_mode mode = GET_MODE (setsrc);
2748               enum rtx_code code = GET_CODE (setsrc);
2749               rtx src_op0 = XEXP (setsrc, 0);
2750               rtx src_op1 = XEXP (setsrc, 1);
2751
2752               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
2753               if (rtx_equal_p (src_op0, src_op1))
2754                 {
2755                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2756                   SUBST (XEXP (setsrc, 0), newdest);
2757                   SUBST (XEXP (setsrc, 1), newdest);
2758                   subst_done = true;
2759                 }
2760               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
2761               else if ((code == PLUS || code == MULT)
2762                        && GET_CODE (src_op0) == code
2763                        && GET_CODE (XEXP (src_op0, 0)) == code
2764                        && (INTEGRAL_MODE_P (mode)
2765                            || (FLOAT_MODE_P (mode)
2766                                && flag_unsafe_math_optimizations)))
2767                 {
2768                   rtx p = XEXP (XEXP (src_op0, 0), 0);
2769                   rtx q = XEXP (XEXP (src_op0, 0), 1);
2770                   rtx r = XEXP (src_op0, 1);
2771                   rtx s = src_op1;
2772
2773                   /* Split both "((X op Y) op X) op Y" and
2774                      "((X op Y) op Y) op X" as "T op T" where T is
2775                      "X op Y".  */
2776                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2777                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2778                     {
2779                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
2780                                               XEXP (src_op0, 0));
2781                       SUBST (XEXP (setsrc, 0), newdest);
2782                       SUBST (XEXP (setsrc, 1), newdest);
2783                       subst_done = true;
2784                     }
2785                   /* Split "((X op X) op Y) op Y)" as "T op T" where
2786                      T is "X op Y".  */
2787                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2788                     {
2789                       rtx tmp = simplify_gen_binary (code, mode, p, r);
2790                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2791                       SUBST (XEXP (setsrc, 0), newdest);
2792                       SUBST (XEXP (setsrc, 1), newdest);
2793                       subst_done = true;
2794                     }
2795                 }
2796             }
2797
2798           if (!subst_done)
2799             {
2800               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2801               SUBST (*split, newdest);
2802             }
2803
2804           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2805
2806           /* recog_for_combine might have added CLOBBERs to newi2pat.
2807              Make sure NEWPAT does not depend on the clobbered regs.  */
2808           if (GET_CODE (newi2pat) == PARALLEL)
2809             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2810               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2811                 {
2812                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2813                   if (reg_overlap_mentioned_p (reg, newpat))
2814                     {
2815                       undo_all ();
2816                       return 0;
2817                     }
2818                 }
2819
2820           /* If the split point was a MULT and we didn't have one before,
2821              don't use one now.  */
2822           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2823             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2824         }
2825     }
2826
2827   /* Check for a case where we loaded from memory in a narrow mode and
2828      then sign extended it, but we need both registers.  In that case,
2829      we have a PARALLEL with both loads from the same memory location.
2830      We can split this into a load from memory followed by a register-register
2831      copy.  This saves at least one insn, more if register allocation can
2832      eliminate the copy.
2833
2834      We cannot do this if the destination of the first assignment is a
2835      condition code register or cc0.  We eliminate this case by making sure
2836      the SET_DEST and SET_SRC have the same mode.
2837
2838      We cannot do this if the destination of the second assignment is
2839      a register that we have already assumed is zero-extended.  Similarly
2840      for a SUBREG of such a register.  */
2841
2842   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2843            && GET_CODE (newpat) == PARALLEL
2844            && XVECLEN (newpat, 0) == 2
2845            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2846            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2847            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2848                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2849            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2850            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2851                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2852            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2853                                    INSN_CUID (i2))
2854            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2855            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2856            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2857                  (REG_P (temp)
2858                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2859                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2860                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2861                   && (reg_stat[REGNO (temp)].nonzero_bits
2862                       != GET_MODE_MASK (word_mode))))
2863            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2864                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2865                      (REG_P (temp)
2866                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2867                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2868                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2869                       && (reg_stat[REGNO (temp)].nonzero_bits
2870                           != GET_MODE_MASK (word_mode)))))
2871            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2872                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2873            && ! find_reg_note (i3, REG_UNUSED,
2874                                SET_DEST (XVECEXP (newpat, 0, 0))))
2875     {
2876       rtx ni2dest;
2877
2878       newi2pat = XVECEXP (newpat, 0, 0);
2879       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2880       newpat = XVECEXP (newpat, 0, 1);
2881       SUBST (SET_SRC (newpat),
2882              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2883       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2884
2885       if (i2_code_number >= 0)
2886         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2887
2888       if (insn_code_number >= 0)
2889         swap_i2i3 = 1;
2890     }
2891
2892   /* Similarly, check for a case where we have a PARALLEL of two independent
2893      SETs but we started with three insns.  In this case, we can do the sets
2894      as two separate insns.  This case occurs when some SET allows two
2895      other insns to combine, but the destination of that SET is still live.  */
2896
2897   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2898            && GET_CODE (newpat) == PARALLEL
2899            && XVECLEN (newpat, 0) == 2
2900            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2901            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2902            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2903            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2904            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2905            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2906            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2907                                    INSN_CUID (i2))
2908            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2909                                   XVECEXP (newpat, 0, 0))
2910            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2911                                   XVECEXP (newpat, 0, 1))
2912            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2913                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
2914 #ifdef HAVE_cc0
2915            /* We cannot split the parallel into two sets if both sets
2916               reference cc0.  */
2917            && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
2918                  && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
2919 #endif
2920            )
2921     {
2922       /* Normally, it doesn't matter which of the two is done first,
2923          but it does if one references cc0.  In that case, it has to
2924          be first.  */
2925 #ifdef HAVE_cc0
2926       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2927         {
2928           newi2pat = XVECEXP (newpat, 0, 0);
2929           newpat = XVECEXP (newpat, 0, 1);
2930         }
2931       else
2932 #endif
2933         {
2934           newi2pat = XVECEXP (newpat, 0, 1);
2935           newpat = XVECEXP (newpat, 0, 0);
2936         }
2937
2938       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2939
2940       if (i2_code_number >= 0)
2941         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2942     }
2943
2944   /* If it still isn't recognized, fail and change things back the way they
2945      were.  */
2946   if ((insn_code_number < 0
2947        /* Is the result a reasonable ASM_OPERANDS?  */
2948        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2949     {
2950       undo_all ();
2951       return 0;
2952     }
2953
2954   /* If we had to change another insn, make sure it is valid also.  */
2955   if (undobuf.other_insn)
2956     {
2957       rtx other_pat = PATTERN (undobuf.other_insn);
2958       rtx new_other_notes;
2959       rtx note, next;
2960
2961       CLEAR_HARD_REG_SET (newpat_used_regs);
2962
2963       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2964                                              &new_other_notes);
2965
2966       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2967         {
2968           undo_all ();
2969           return 0;
2970         }
2971
2972       PATTERN (undobuf.other_insn) = other_pat;
2973
2974       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2975          are still valid.  Then add any non-duplicate notes added by
2976          recog_for_combine.  */
2977       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2978         {
2979           next = XEXP (note, 1);
2980
2981           if (REG_NOTE_KIND (note) == REG_UNUSED
2982               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2983             {
2984               if (REG_P (XEXP (note, 0)))
2985                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2986
2987               remove_note (undobuf.other_insn, note);
2988             }
2989         }
2990
2991       for (note = new_other_notes; note; note = XEXP (note, 1))
2992         if (REG_P (XEXP (note, 0)))
2993           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2994
2995       distribute_notes (new_other_notes, undobuf.other_insn,
2996                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2997     }
2998 #ifdef HAVE_cc0
2999   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3000      they are adjacent to each other or not.  */
3001   {
3002     rtx p = prev_nonnote_insn (i3);
3003     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3004         && sets_cc0_p (newi2pat))
3005       {
3006         undo_all ();
3007         return 0;
3008       }
3009   }
3010 #endif
3011
3012   /* Only allow this combination if insn_rtx_costs reports that the
3013      replacement instructions are cheaper than the originals.  */
3014   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
3015     {
3016       undo_all ();
3017       return 0;
3018     }
3019
3020   /* We now know that we can do this combination.  Merge the insns and
3021      update the status of registers and LOG_LINKS.  */
3022
3023   if (swap_i2i3)
3024     {
3025       rtx insn;
3026       rtx link;
3027       rtx ni2dest;
3028
3029       /* I3 now uses what used to be its destination and which is now
3030          I2's destination.  This requires us to do a few adjustments.  */
3031       PATTERN (i3) = newpat;
3032       adjust_for_new_dest (i3);
3033
3034       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3035          so we still will.
3036
3037          However, some later insn might be using I2's dest and have
3038          a LOG_LINK pointing at I3.  We must remove this link.
3039          The simplest way to remove the link is to point it at I1,
3040          which we know will be a NOTE.  */
3041
3042       /* newi2pat is usually a SET here; however, recog_for_combine might
3043          have added some clobbers.  */
3044       if (GET_CODE (newi2pat) == PARALLEL)
3045         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3046       else
3047         ni2dest = SET_DEST (newi2pat);
3048
3049       for (insn = NEXT_INSN (i3);
3050            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3051                     || insn != BB_HEAD (this_basic_block->next_bb));
3052            insn = NEXT_INSN (insn))
3053         {
3054           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3055             {
3056               for (link = LOG_LINKS (insn); link;
3057                    link = XEXP (link, 1))
3058                 if (XEXP (link, 0) == i3)
3059                   XEXP (link, 0) = i1;
3060
3061               break;
3062             }
3063         }
3064     }
3065
3066   {
3067     rtx i3notes, i2notes, i1notes = 0;
3068     rtx i3links, i2links, i1links = 0;
3069     rtx midnotes = 0;
3070     unsigned int regno;
3071     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3072        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3073        same as i3dest, in which case newi2pat may be setting i1dest.  */
3074     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3075                    || i2dest_in_i2src || i2dest_in_i1src
3076                    || !i2dest_killed
3077                    ? 0 : i2dest);
3078     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3079                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3080                    || !i1dest_killed
3081                    ? 0 : i1dest);
3082
3083     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3084        clear them.  */
3085     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3086     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3087     if (i1)
3088       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3089
3090     /* Ensure that we do not have something that should not be shared but
3091        occurs multiple times in the new insns.  Check this by first
3092        resetting all the `used' flags and then copying anything is shared.  */
3093
3094     reset_used_flags (i3notes);
3095     reset_used_flags (i2notes);
3096     reset_used_flags (i1notes);
3097     reset_used_flags (newpat);
3098     reset_used_flags (newi2pat);
3099     if (undobuf.other_insn)
3100       reset_used_flags (PATTERN (undobuf.other_insn));
3101
3102     i3notes = copy_rtx_if_shared (i3notes);
3103     i2notes = copy_rtx_if_shared (i2notes);
3104     i1notes = copy_rtx_if_shared (i1notes);
3105     newpat = copy_rtx_if_shared (newpat);
3106     newi2pat = copy_rtx_if_shared (newi2pat);
3107     if (undobuf.other_insn)
3108       reset_used_flags (PATTERN (undobuf.other_insn));
3109
3110     INSN_CODE (i3) = insn_code_number;
3111     PATTERN (i3) = newpat;
3112
3113     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3114       {
3115         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3116
3117         reset_used_flags (call_usage);
3118         call_usage = copy_rtx (call_usage);
3119
3120         if (substed_i2)
3121           replace_rtx (call_usage, i2dest, i2src);
3122
3123         if (substed_i1)
3124           replace_rtx (call_usage, i1dest, i1src);
3125
3126         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3127       }
3128
3129     if (undobuf.other_insn)
3130       INSN_CODE (undobuf.other_insn) = other_code_number;
3131
3132     /* We had one special case above where I2 had more than one set and
3133        we replaced a destination of one of those sets with the destination
3134        of I3.  In that case, we have to update LOG_LINKS of insns later
3135        in this basic block.  Note that this (expensive) case is rare.
3136
3137        Also, in this case, we must pretend that all REG_NOTEs for I2
3138        actually came from I3, so that REG_UNUSED notes from I2 will be
3139        properly handled.  */
3140
3141     if (i3_subst_into_i2)
3142       {
3143         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3144           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3145                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3146               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3147               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3148               && ! find_reg_note (i2, REG_UNUSED,
3149                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3150             for (temp = NEXT_INSN (i2);
3151                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3152                           || BB_HEAD (this_basic_block) != temp);
3153                  temp = NEXT_INSN (temp))
3154               if (temp != i3 && INSN_P (temp))
3155                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3156                   if (XEXP (link, 0) == i2)
3157                     XEXP (link, 0) = i3;
3158
3159         if (i3notes)
3160           {
3161             rtx link = i3notes;
3162             while (XEXP (link, 1))
3163               link = XEXP (link, 1);
3164             XEXP (link, 1) = i2notes;
3165           }
3166         else
3167           i3notes = i2notes;
3168         i2notes = 0;
3169       }
3170
3171     LOG_LINKS (i3) = 0;
3172     REG_NOTES (i3) = 0;
3173     LOG_LINKS (i2) = 0;
3174     REG_NOTES (i2) = 0;
3175
3176     if (newi2pat)
3177       {
3178         INSN_CODE (i2) = i2_code_number;
3179         PATTERN (i2) = newi2pat;
3180       }
3181     else
3182       SET_INSN_DELETED (i2);
3183
3184     if (i1)
3185       {
3186         LOG_LINKS (i1) = 0;
3187         REG_NOTES (i1) = 0;
3188         SET_INSN_DELETED (i1);
3189       }
3190
3191     /* Get death notes for everything that is now used in either I3 or
3192        I2 and used to die in a previous insn.  If we built two new
3193        patterns, move from I1 to I2 then I2 to I3 so that we get the
3194        proper movement on registers that I2 modifies.  */
3195
3196     if (newi2pat)
3197       {
3198         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3199         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3200       }
3201     else
3202       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3203                    i3, &midnotes);
3204
3205     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3206     if (i3notes)
3207       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3208                         elim_i2, elim_i1);
3209     if (i2notes)
3210       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3211                         elim_i2, elim_i1);
3212     if (i1notes)
3213       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3214                         elim_i2, elim_i1);
3215     if (midnotes)
3216       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3217                         elim_i2, elim_i1);
3218
3219     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3220        know these are REG_UNUSED and want them to go to the desired insn,
3221        so we always pass it as i3.  We have not counted the notes in
3222        reg_n_deaths yet, so we need to do so now.  */
3223
3224     if (newi2pat && new_i2_notes)
3225       {
3226         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3227           if (REG_P (XEXP (temp, 0)))
3228             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3229
3230         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3231       }
3232
3233     if (new_i3_notes)
3234       {
3235         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3236           if (REG_P (XEXP (temp, 0)))
3237             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3238
3239         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3240       }
3241
3242     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3243        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3244        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3245        in that case, it might delete I2.  Similarly for I2 and I1.
3246        Show an additional death due to the REG_DEAD note we make here.  If
3247        we discard it in distribute_notes, we will decrement it again.  */
3248
3249     if (i3dest_killed)
3250       {
3251         if (REG_P (i3dest_killed))
3252           REG_N_DEATHS (REGNO (i3dest_killed))++;
3253
3254         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3255           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3256                                                NULL_RTX),
3257                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3258         else
3259           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3260                                                NULL_RTX),
3261                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3262                             elim_i2, elim_i1);
3263       }
3264
3265     if (i2dest_in_i2src)
3266       {
3267         if (REG_P (i2dest))
3268           REG_N_DEATHS (REGNO (i2dest))++;
3269
3270         if (newi2pat && reg_set_p (i2dest, newi2pat))
3271           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3272                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3273         else
3274           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3275                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3276                             NULL_RTX, NULL_RTX);
3277       }
3278
3279     if (i1dest_in_i1src)
3280       {
3281         if (REG_P (i1dest))
3282           REG_N_DEATHS (REGNO (i1dest))++;
3283
3284         if (newi2pat && reg_set_p (i1dest, newi2pat))
3285           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3286                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3287         else
3288           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3289                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3290                             NULL_RTX, NULL_RTX);
3291       }
3292
3293     distribute_links (i3links);
3294     distribute_links (i2links);
3295     distribute_links (i1links);
3296
3297     if (REG_P (i2dest))
3298       {
3299         rtx link;
3300         rtx i2_insn = 0, i2_val = 0, set;
3301
3302         /* The insn that used to set this register doesn't exist, and
3303            this life of the register may not exist either.  See if one of
3304            I3's links points to an insn that sets I2DEST.  If it does,
3305            that is now the last known value for I2DEST. If we don't update
3306            this and I2 set the register to a value that depended on its old
3307            contents, we will get confused.  If this insn is used, thing
3308            will be set correctly in combine_instructions.  */
3309
3310         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3311           if ((set = single_set (XEXP (link, 0))) != 0
3312               && rtx_equal_p (i2dest, SET_DEST (set)))
3313             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3314
3315         record_value_for_reg (i2dest, i2_insn, i2_val);
3316
3317         /* If the reg formerly set in I2 died only once and that was in I3,
3318            zero its use count so it won't make `reload' do any work.  */
3319         if (! added_sets_2
3320             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3321             && ! i2dest_in_i2src)
3322           {
3323             regno = REGNO (i2dest);
3324             REG_N_SETS (regno)--;
3325           }
3326       }
3327
3328     if (i1 && REG_P (i1dest))
3329       {
3330         rtx link;
3331         rtx i1_insn = 0, i1_val = 0, set;
3332
3333         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3334           if ((set = single_set (XEXP (link, 0))) != 0
3335               && rtx_equal_p (i1dest, SET_DEST (set)))
3336             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3337
3338         record_value_for_reg (i1dest, i1_insn, i1_val);
3339
3340         regno = REGNO (i1dest);
3341         if (! added_sets_1 && ! i1dest_in_i1src)
3342           REG_N_SETS (regno)--;
3343       }
3344
3345     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3346        been made to this insn.  The order of
3347        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3348        can affect nonzero_bits of newpat */
3349     if (newi2pat)
3350       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3351     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3352
3353     /* Set new_direct_jump_p if a new return or simple jump instruction
3354        has been created.
3355
3356        If I3 is now an unconditional jump, ensure that it has a
3357        BARRIER following it since it may have initially been a
3358        conditional jump.  It may also be the last nonnote insn.  */
3359
3360     if (returnjump_p (i3) || any_uncondjump_p (i3))
3361       {
3362         *new_direct_jump_p = 1;
3363         mark_jump_label (PATTERN (i3), i3, 0);
3364
3365         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3366             || !BARRIER_P (temp))
3367           emit_barrier_after (i3);
3368       }
3369
3370     if (undobuf.other_insn != NULL_RTX
3371         && (returnjump_p (undobuf.other_insn)
3372             || any_uncondjump_p (undobuf.other_insn)))
3373       {
3374         *new_direct_jump_p = 1;
3375
3376         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3377             || !BARRIER_P (temp))
3378           emit_barrier_after (undobuf.other_insn);
3379       }
3380
3381     /* An NOOP jump does not need barrier, but it does need cleaning up
3382        of CFG.  */
3383     if (GET_CODE (newpat) == SET
3384         && SET_SRC (newpat) == pc_rtx
3385         && SET_DEST (newpat) == pc_rtx)
3386       *new_direct_jump_p = 1;
3387   }
3388
3389   combine_successes++;
3390   undo_commit ();
3391
3392   if (added_links_insn
3393       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3394       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3395     return added_links_insn;
3396   else
3397     return newi2pat ? i2 : i3;
3398 }
3399 \f
3400 /* Undo all the modifications recorded in undobuf.  */
3401
3402 static void
3403 undo_all (void)
3404 {
3405   struct undo *undo, *next;
3406
3407   for (undo = undobuf.undos; undo; undo = next)
3408     {
3409       next = undo->next;
3410       switch (undo->kind)
3411         {
3412         case UNDO_RTX:
3413           *undo->where.r = undo->old_contents.r;
3414           break;
3415         case UNDO_INT:
3416           *undo->where.i = undo->old_contents.i;
3417           break;
3418         case UNDO_MODE:
3419           PUT_MODE (*undo->where.r, undo->old_contents.m);
3420           break;
3421         default:
3422           gcc_unreachable ();
3423         }
3424
3425       undo->next = undobuf.frees;
3426       undobuf.frees = undo;
3427     }
3428
3429   undobuf.undos = 0;
3430 }
3431
3432 /* We've committed to accepting the changes we made.  Move all
3433    of the undos to the free list.  */
3434
3435 static void
3436 undo_commit (void)
3437 {
3438   struct undo *undo, *next;
3439
3440   for (undo = undobuf.undos; undo; undo = next)
3441     {
3442       next = undo->next;
3443       undo->next = undobuf.frees;
3444       undobuf.frees = undo;
3445     }
3446   undobuf.undos = 0;
3447 }
3448 \f
3449 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3450    where we have an arithmetic expression and return that point.  LOC will
3451    be inside INSN.
3452
3453    try_combine will call this function to see if an insn can be split into
3454    two insns.  */
3455
3456 static rtx *
3457 find_split_point (rtx *loc, rtx insn)
3458 {
3459   rtx x = *loc;
3460   enum rtx_code code = GET_CODE (x);
3461   rtx *split;
3462   unsigned HOST_WIDE_INT len = 0;
3463   HOST_WIDE_INT pos = 0;
3464   int unsignedp = 0;
3465   rtx inner = NULL_RTX;
3466
3467   /* First special-case some codes.  */
3468   switch (code)
3469     {
3470     case SUBREG:
3471 #ifdef INSN_SCHEDULING
3472       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3473          point.  */
3474       if (MEM_P (SUBREG_REG (x)))
3475         return loc;
3476 #endif
3477       return find_split_point (&SUBREG_REG (x), insn);
3478
3479     case MEM:
3480 #ifdef HAVE_lo_sum
3481       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3482          using LO_SUM and HIGH.  */
3483       if (GET_CODE (XEXP (x, 0)) == CONST
3484           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3485         {
3486           SUBST (XEXP (x, 0),
3487                  gen_rtx_LO_SUM (Pmode,
3488                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3489                                  XEXP (x, 0)));
3490           return &XEXP (XEXP (x, 0), 0);
3491         }
3492 #endif
3493
3494       /* If we have a PLUS whose second operand is a constant and the
3495          address is not valid, perhaps will can split it up using
3496          the machine-specific way to split large constants.  We use
3497          the first pseudo-reg (one of the virtual regs) as a placeholder;
3498          it will not remain in the result.  */
3499       if (GET_CODE (XEXP (x, 0)) == PLUS
3500           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3501           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3502         {
3503           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3504           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3505                                  subst_insn);
3506
3507           /* This should have produced two insns, each of which sets our
3508              placeholder.  If the source of the second is a valid address,
3509              we can make put both sources together and make a split point
3510              in the middle.  */
3511
3512           if (seq
3513               && NEXT_INSN (seq) != NULL_RTX
3514               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3515               && NONJUMP_INSN_P (seq)
3516               && GET_CODE (PATTERN (seq)) == SET
3517               && SET_DEST (PATTERN (seq)) == reg
3518               && ! reg_mentioned_p (reg,
3519                                     SET_SRC (PATTERN (seq)))
3520               && NONJUMP_INSN_P (NEXT_INSN (seq))
3521               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3522               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3523               && memory_address_p (GET_MODE (x),
3524                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3525             {
3526               rtx src1 = SET_SRC (PATTERN (seq));
3527               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3528
3529               /* Replace the placeholder in SRC2 with SRC1.  If we can
3530                  find where in SRC2 it was placed, that can become our
3531                  split point and we can replace this address with SRC2.
3532                  Just try two obvious places.  */
3533
3534               src2 = replace_rtx (src2, reg, src1);
3535               split = 0;
3536               if (XEXP (src2, 0) == src1)
3537                 split = &XEXP (src2, 0);
3538               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3539                        && XEXP (XEXP (src2, 0), 0) == src1)
3540                 split = &XEXP (XEXP (src2, 0), 0);
3541
3542               if (split)
3543                 {
3544                   SUBST (XEXP (x, 0), src2);
3545                   return split;
3546                 }
3547             }
3548
3549           /* If that didn't work, perhaps the first operand is complex and
3550              needs to be computed separately, so make a split point there.
3551              This will occur on machines that just support REG + CONST
3552              and have a constant moved through some previous computation.  */
3553
3554           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3555                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3556                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3557             return &XEXP (XEXP (x, 0), 0);
3558         }
3559       break;
3560
3561     case SET:
3562 #ifdef HAVE_cc0
3563       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3564          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3565          we need to put the operand into a register.  So split at that
3566          point.  */
3567
3568       if (SET_DEST (x) == cc0_rtx
3569           && GET_CODE (SET_SRC (x)) != COMPARE
3570           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3571           && !OBJECT_P (SET_SRC (x))
3572           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3573                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3574         return &SET_SRC (x);
3575 #endif
3576
3577       /* See if we can split SET_SRC as it stands.  */
3578       split = find_split_point (&SET_SRC (x), insn);
3579       if (split && split != &SET_SRC (x))
3580         return split;
3581
3582       /* See if we can split SET_DEST as it stands.  */
3583       split = find_split_point (&SET_DEST (x), insn);
3584       if (split && split != &SET_DEST (x))
3585         return split;
3586
3587       /* See if this is a bitfield assignment with everything constant.  If
3588          so, this is an IOR of an AND, so split it into that.  */
3589       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3590           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3591               <= HOST_BITS_PER_WIDE_INT)
3592           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3593           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3594           && GET_CODE (SET_SRC (x)) == CONST_INT
3595           && ((INTVAL (XEXP (SET_DEST (x), 1))
3596                + INTVAL (XEXP (SET_DEST (x), 2)))
3597               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3598           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3599         {
3600           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3601           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3602           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3603           rtx dest = XEXP (SET_DEST (x), 0);
3604           enum machine_mode mode = GET_MODE (dest);
3605           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3606           rtx or_mask;
3607
3608           if (BITS_BIG_ENDIAN)
3609             pos = GET_MODE_BITSIZE (mode) - len - pos;
3610
3611           or_mask = gen_int_mode (src << pos, mode);
3612           if (src == mask)
3613             SUBST (SET_SRC (x),
3614                    simplify_gen_binary (IOR, mode, dest, or_mask));
3615           else
3616             {
3617               rtx negmask = gen_int_mode (~(mask << pos), mode);
3618               SUBST (SET_SRC (x),
3619                      simplify_gen_binary (IOR, mode,
3620                                           simplify_gen_binary (AND, mode,
3621                                                                dest, negmask),
3622                                           or_mask));
3623             }
3624
3625           SUBST (SET_DEST (x), dest);
3626
3627           split = find_split_point (&SET_SRC (x), insn);
3628           if (split && split != &SET_SRC (x))
3629             return split;
3630         }
3631
3632       /* Otherwise, see if this is an operation that we can split into two.
3633          If so, try to split that.  */
3634       code = GET_CODE (SET_SRC (x));
3635
3636       switch (code)
3637         {
3638         case AND:
3639           /* If we are AND'ing with a large constant that is only a single
3640              bit and the result is only being used in a context where we
3641              need to know if it is zero or nonzero, replace it with a bit
3642              extraction.  This will avoid the large constant, which might
3643              have taken more than one insn to make.  If the constant were
3644              not a valid argument to the AND but took only one insn to make,
3645              this is no worse, but if it took more than one insn, it will
3646              be better.  */
3647
3648           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3649               && REG_P (XEXP (SET_SRC (x), 0))
3650               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3651               && REG_P (SET_DEST (x))
3652               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3653               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3654               && XEXP (*split, 0) == SET_DEST (x)
3655               && XEXP (*split, 1) == const0_rtx)
3656             {
3657               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3658                                                 XEXP (SET_SRC (x), 0),
3659                                                 pos, NULL_RTX, 1, 1, 0, 0);
3660               if (extraction != 0)
3661                 {
3662                   SUBST (SET_SRC (x), extraction);
3663                   return find_split_point (loc, insn);
3664                 }
3665             }
3666           break;
3667
3668         case NE:
3669           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3670              is known to be on, this can be converted into a NEG of a shift.  */
3671           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3672               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3673               && 1 <= (pos = exact_log2
3674                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3675                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3676             {
3677               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3678
3679               SUBST (SET_SRC (x),
3680                      gen_rtx_NEG (mode,
3681                                   gen_rtx_LSHIFTRT (mode,
3682                                                     XEXP (SET_SRC (x), 0),
3683                                                     GEN_INT (pos))));
3684
3685               split = find_split_point (&SET_SRC (x), insn);
3686               if (split && split != &SET_SRC (x))
3687                 return split;
3688             }
3689           break;
3690
3691         case SIGN_EXTEND:
3692           inner = XEXP (SET_SRC (x), 0);
3693
3694           /* We can't optimize if either mode is a partial integer
3695              mode as we don't know how many bits are significant
3696              in those modes.  */
3697           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3698               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3699             break;
3700
3701           pos = 0;
3702           len = GET_MODE_BITSIZE (GET_MODE (inner));
3703           unsignedp = 0;
3704           break;
3705
3706         case SIGN_EXTRACT:
3707         case ZERO_EXTRACT:
3708           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3709               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3710             {
3711               inner = XEXP (SET_SRC (x), 0);
3712               len = INTVAL (XEXP (SET_SRC (x), 1));
3713               pos = INTVAL (XEXP (SET_SRC (x), 2));
3714
3715               if (BITS_BIG_ENDIAN)
3716                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3717               unsignedp = (code == ZERO_EXTRACT);
3718             }
3719           break;
3720
3721         default:
3722           break;
3723         }
3724
3725       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3726         {
3727           enum machine_mode mode = GET_MODE (SET_SRC (x));
3728
3729           /* For unsigned, we have a choice of a shift followed by an
3730              AND or two shifts.  Use two shifts for field sizes where the
3731              constant might be too large.  We assume here that we can
3732              always at least get 8-bit constants in an AND insn, which is
3733              true for every current RISC.  */
3734
3735           if (unsignedp && len <= 8)
3736             {
3737               SUBST (SET_SRC (x),
3738                      gen_rtx_AND (mode,
3739                                   gen_rtx_LSHIFTRT
3740                                   (mode, gen_lowpart (mode, inner),
3741                                    GEN_INT (pos)),
3742                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3743
3744               split = find_split_point (&SET_SRC (x), insn);
3745               if (split && split != &SET_SRC (x))
3746                 return split;
3747             }
3748           else
3749             {
3750               SUBST (SET_SRC (x),
3751                      gen_rtx_fmt_ee
3752                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3753                       gen_rtx_ASHIFT (mode,
3754                                       gen_lowpart (mode, inner),
3755                                       GEN_INT (GET_MODE_BITSIZE (mode)
3756                                                - len - pos)),
3757                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3758
3759               split = find_split_point (&SET_SRC (x), insn);
3760               if (split && split != &SET_SRC (x))
3761                 return split;
3762             }
3763         }
3764
3765       /* See if this is a simple operation with a constant as the second
3766          operand.  It might be that this constant is out of range and hence
3767          could be used as a split point.  */
3768       if (BINARY_P (SET_SRC (x))
3769           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3770           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3771               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3772                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3773         return &XEXP (SET_SRC (x), 1);
3774
3775       /* Finally, see if this is a simple operation with its first operand
3776          not in a register.  The operation might require this operand in a
3777          register, so return it as a split point.  We can always do this
3778          because if the first operand were another operation, we would have
3779          already found it as a split point.  */
3780       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3781           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3782         return &XEXP (SET_SRC (x), 0);
3783
3784       return 0;
3785
3786     case AND:
3787     case IOR:
3788       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3789          it is better to write this as (not (ior A B)) so we can split it.
3790          Similarly for IOR.  */
3791       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3792         {
3793           SUBST (*loc,
3794                  gen_rtx_NOT (GET_MODE (x),
3795                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3796                                               GET_MODE (x),
3797                                               XEXP (XEXP (x, 0), 0),
3798                                               XEXP (XEXP (x, 1), 0))));
3799           return find_split_point (loc, insn);
3800         }
3801
3802       /* Many RISC machines have a large set of logical insns.  If the
3803          second operand is a NOT, put it first so we will try to split the
3804          other operand first.  */
3805       if (GET_CODE (XEXP (x, 1)) == NOT)
3806         {
3807           rtx tem = XEXP (x, 0);
3808           SUBST (XEXP (x, 0), XEXP (x, 1));
3809           SUBST (XEXP (x, 1), tem);
3810         }
3811       break;
3812
3813     default:
3814       break;
3815     }
3816
3817   /* Otherwise, select our actions depending on our rtx class.  */
3818   switch (GET_RTX_CLASS (code))
3819     {
3820     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3821     case RTX_TERNARY:
3822       split = find_split_point (&XEXP (x, 2), insn);
3823       if (split)
3824         return split;
3825       /* ... fall through ...  */
3826     case RTX_BIN_ARITH:
3827     case RTX_COMM_ARITH:
3828     case RTX_COMPARE:
3829     case RTX_COMM_COMPARE:
3830       split = find_split_point (&XEXP (x, 1), insn);
3831       if (split)
3832         return split;
3833       /* ... fall through ...  */
3834     case RTX_UNARY:
3835       /* Some machines have (and (shift ...) ...) insns.  If X is not
3836          an AND, but XEXP (X, 0) is, use it as our split point.  */
3837       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3838         return &XEXP (x, 0);
3839
3840       split = find_split_point (&XEXP (x, 0), insn);
3841       if (split)
3842         return split;
3843       return loc;
3844
3845     default:
3846       /* Otherwise, we don't have a split point.  */
3847       return 0;
3848     }
3849 }
3850 \f
3851 /* Throughout X, replace FROM with TO, and return the result.
3852    The result is TO if X is FROM;
3853    otherwise the result is X, but its contents may have been modified.
3854    If they were modified, a record was made in undobuf so that
3855    undo_all will (among other things) return X to its original state.
3856
3857    If the number of changes necessary is too much to record to undo,
3858    the excess changes are not made, so the result is invalid.
3859    The changes already made can still be undone.
3860    undobuf.num_undo is incremented for such changes, so by testing that
3861    the caller can tell whether the result is valid.
3862
3863    `n_occurrences' is incremented each time FROM is replaced.
3864
3865    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3866
3867    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3868    by copying if `n_occurrences' is nonzero.  */
3869
3870 static rtx
3871 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3872 {
3873   enum rtx_code code = GET_CODE (x);
3874   enum machine_mode op0_mode = VOIDmode;
3875   const char *fmt;
3876   int len, i;
3877   rtx new;
3878
3879 /* Two expressions are equal if they are identical copies of a shared
3880    RTX or if they are both registers with the same register number
3881    and mode.  */
3882
3883 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3884   ((X) == (Y)                                           \
3885    || (REG_P (X) && REG_P (Y)   \
3886        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3887
3888   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3889     {
3890       n_occurrences++;
3891       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3892     }
3893
3894   /* If X and FROM are the same register but different modes, they will
3895      not have been seen as equal above.  However, flow.c will make a
3896      LOG_LINKS entry for that case.  If we do nothing, we will try to
3897      rerecognize our original insn and, when it succeeds, we will
3898      delete the feeding insn, which is incorrect.
3899
3900      So force this insn not to match in this (rare) case.  */
3901   if (! in_dest && code == REG && REG_P (from)
3902       && REGNO (x) == REGNO (from))
3903     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3904
3905   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3906      of which may contain things that can be combined.  */
3907   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3908     return x;
3909
3910   /* It is possible to have a subexpression appear twice in the insn.
3911      Suppose that FROM is a register that appears within TO.
3912      Then, after that subexpression has been scanned once by `subst',
3913      the second time it is scanned, TO may be found.  If we were
3914      to scan TO here, we would find FROM within it and create a
3915      self-referent rtl structure which is completely wrong.  */
3916   if (COMBINE_RTX_EQUAL_P (x, to))
3917     return to;
3918
3919   /* Parallel asm_operands need special attention because all of the
3920      inputs are shared across the arms.  Furthermore, unsharing the
3921      rtl results in recognition failures.  Failure to handle this case
3922      specially can result in circular rtl.
3923
3924      Solve this by doing a normal pass across the first entry of the
3925      parallel, and only processing the SET_DESTs of the subsequent
3926      entries.  Ug.  */
3927
3928   if (code == PARALLEL
3929       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3930       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3931     {
3932       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3933
3934       /* If this substitution failed, this whole thing fails.  */
3935       if (GET_CODE (new) == CLOBBER
3936           && XEXP (new, 0) == const0_rtx)
3937         return new;
3938
3939       SUBST (XVECEXP (x, 0, 0), new);
3940
3941       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3942         {
3943           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3944
3945           if (!REG_P (dest)
3946               && GET_CODE (dest) != CC0
3947               && GET_CODE (dest) != PC)
3948             {
3949               new = subst (dest, from, to, 0, unique_copy);
3950
3951               /* If this substitution failed, this whole thing fails.  */
3952               if (GET_CODE (new) == CLOBBER
3953                   && XEXP (new, 0) == const0_rtx)
3954                 return new;
3955
3956               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3957             }
3958         }
3959     }
3960   else
3961     {
3962       len = GET_RTX_LENGTH (code);
3963       fmt = GET_RTX_FORMAT (code);
3964
3965       /* We don't need to process a SET_DEST that is a register, CC0,
3966          or PC, so set up to skip this common case.  All other cases
3967          where we want to suppress replacing something inside a
3968          SET_SRC are handled via the IN_DEST operand.  */
3969       if (code == SET
3970           && (REG_P (SET_DEST (x))
3971               || GET_CODE (SET_DEST (x)) == CC0
3972               || GET_CODE (SET_DEST (x)) == PC))
3973         fmt = "ie";
3974
3975       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3976          constant.  */
3977       if (fmt[0] == 'e')
3978         op0_mode = GET_MODE (XEXP (x, 0));
3979
3980       for (i = 0; i < len; i++)
3981         {
3982           if (fmt[i] == 'E')
3983             {
3984               int j;
3985               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3986                 {
3987                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3988                     {
3989                       new = (unique_copy && n_occurrences
3990                              ? copy_rtx (to) : to);
3991                       n_occurrences++;
3992                     }
3993                   else
3994                     {
3995                       new = subst (XVECEXP (x, i, j), from, to, 0,
3996                                    unique_copy);
3997
3998                       /* If this substitution failed, this whole thing
3999                          fails.  */
4000                       if (GET_CODE (new) == CLOBBER
4001                           && XEXP (new, 0) == const0_rtx)
4002                         return new;
4003                     }
4004
4005                   SUBST (XVECEXP (x, i, j), new);
4006                 }
4007             }
4008           else if (fmt[i] == 'e')
4009             {
4010               /* If this is a register being set, ignore it.  */
4011               new = XEXP (x, i);
4012               if (in_dest
4013                   && i == 0
4014                   && (((code == SUBREG || code == ZERO_EXTRACT)
4015                        && REG_P (new))
4016                       || code == STRICT_LOW_PART))
4017                 ;
4018
4019               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4020                 {
4021                   /* In general, don't install a subreg involving two
4022                      modes not tieable.  It can worsen register
4023                      allocation, and can even make invalid reload
4024                      insns, since the reg inside may need to be copied
4025                      from in the outside mode, and that may be invalid
4026                      if it is an fp reg copied in integer mode.
4027
4028                      We allow two exceptions to this: It is valid if
4029                      it is inside another SUBREG and the mode of that
4030                      SUBREG and the mode of the inside of TO is
4031                      tieable and it is valid if X is a SET that copies
4032                      FROM to CC0.  */
4033
4034                   if (GET_CODE (to) == SUBREG
4035                       && ! MODES_TIEABLE_P (GET_MODE (to),
4036                                             GET_MODE (SUBREG_REG (to)))
4037                       && ! (code == SUBREG
4038                             && MODES_TIEABLE_P (GET_MODE (x),
4039                                                 GET_MODE (SUBREG_REG (to))))
4040 #ifdef HAVE_cc0
4041                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4042 #endif
4043                       )
4044                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4045
4046 #ifdef CANNOT_CHANGE_MODE_CLASS
4047                   if (code == SUBREG
4048                       && REG_P (to)
4049                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4050                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4051                                                    GET_MODE (to),
4052                                                    GET_MODE (x)))
4053                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4054 #endif
4055
4056                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4057                   n_occurrences++;
4058                 }
4059               else
4060                 /* If we are in a SET_DEST, suppress most cases unless we
4061                    have gone inside a MEM, in which case we want to
4062                    simplify the address.  We assume here that things that
4063                    are actually part of the destination have their inner
4064                    parts in the first expression.  This is true for SUBREG,
4065                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4066                    things aside from REG and MEM that should appear in a
4067                    SET_DEST.  */
4068                 new = subst (XEXP (x, i), from, to,
4069                              (((in_dest
4070                                 && (code == SUBREG || code == STRICT_LOW_PART
4071                                     || code == ZERO_EXTRACT))
4072                                || code == SET)
4073                               && i == 0), unique_copy);
4074
4075               /* If we found that we will have to reject this combination,
4076                  indicate that by returning the CLOBBER ourselves, rather than
4077                  an expression containing it.  This will speed things up as
4078                  well as prevent accidents where two CLOBBERs are considered
4079                  to be equal, thus producing an incorrect simplification.  */
4080
4081               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4082                 return new;
4083
4084               if (GET_CODE (x) == SUBREG
4085                   && (GET_CODE (new) == CONST_INT
4086                       || GET_CODE (new) == CONST_DOUBLE))
4087                 {
4088                   enum machine_mode mode = GET_MODE (x);
4089
4090                   x = simplify_subreg (GET_MODE (x), new,
4091                                        GET_MODE (SUBREG_REG (x)),
4092                                        SUBREG_BYTE (x));
4093                   if (! x)
4094                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4095                 }
4096               else if (GET_CODE (new) == CONST_INT
4097                        && GET_CODE (x) == ZERO_EXTEND)
4098                 {
4099                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4100                                                 new, GET_MODE (XEXP (x, 0)));
4101                   gcc_assert (x);
4102                 }
4103               else
4104                 SUBST (XEXP (x, i), new);
4105             }
4106         }
4107     }
4108
4109   /* Try to simplify X.  If the simplification changed the code, it is likely
4110      that further simplification will help, so loop, but limit the number
4111      of repetitions that will be performed.  */
4112
4113   for (i = 0; i < 4; i++)
4114     {
4115       /* If X is sufficiently simple, don't bother trying to do anything
4116          with it.  */
4117       if (code != CONST_INT && code != REG && code != CLOBBER)
4118         x = combine_simplify_rtx (x, op0_mode, in_dest);
4119
4120       if (GET_CODE (x) == code)
4121         break;
4122
4123       code = GET_CODE (x);
4124
4125       /* We no longer know the original mode of operand 0 since we
4126          have changed the form of X)  */
4127       op0_mode = VOIDmode;
4128     }
4129
4130   return x;
4131 }
4132 \f
4133 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4134    outer level; call `subst' to simplify recursively.  Return the new
4135    expression.
4136
4137    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4138    if we are inside a SET_DEST.  */
4139
4140 static rtx
4141 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4142 {
4143   enum rtx_code code = GET_CODE (x);
4144   enum machine_mode mode = GET_MODE (x);
4145   rtx temp;
4146   int i;
4147
4148   /* If this is a commutative operation, put a constant last and a complex
4149      expression first.  We don't need to do this for comparisons here.  */
4150   if (COMMUTATIVE_ARITH_P (x)
4151       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4152     {
4153       temp = XEXP (x, 0);
4154       SUBST (XEXP (x, 0), XEXP (x, 1));
4155       SUBST (XEXP (x, 1), temp);
4156     }
4157
4158   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4159      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4160      things.  Check for cases where both arms are testing the same
4161      condition.
4162
4163      Don't do anything if all operands are very simple.  */
4164
4165   if ((BINARY_P (x)
4166        && ((!OBJECT_P (XEXP (x, 0))
4167             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4168                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4169            || (!OBJECT_P (XEXP (x, 1))
4170                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4171                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4172       || (UNARY_P (x)
4173           && (!OBJECT_P (XEXP (x, 0))
4174                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4175                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4176     {
4177       rtx cond, true_rtx, false_rtx;
4178
4179       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4180       if (cond != 0
4181           /* If everything is a comparison, what we have is highly unlikely
4182              to be simpler, so don't use it.  */
4183           && ! (COMPARISON_P (x)
4184                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4185         {
4186           rtx cop1 = const0_rtx;
4187           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4188
4189           if (cond_code == NE && COMPARISON_P (cond))
4190             return x;
4191
4192           /* Simplify the alternative arms; this may collapse the true and
4193              false arms to store-flag values.  Be careful to use copy_rtx
4194              here since true_rtx or false_rtx might share RTL with x as a
4195              result of the if_then_else_cond call above.  */
4196           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4197           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4198
4199           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4200              is unlikely to be simpler.  */
4201           if (general_operand (true_rtx, VOIDmode)
4202               && general_operand (false_rtx, VOIDmode))
4203             {
4204               enum rtx_code reversed;
4205
4206               /* Restarting if we generate a store-flag expression will cause
4207                  us to loop.  Just drop through in this case.  */
4208
4209               /* If the result values are STORE_FLAG_VALUE and zero, we can
4210                  just make the comparison operation.  */
4211               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4212                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4213                                              cond, cop1);
4214               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4215                        && ((reversed = reversed_comparison_code_parts
4216                                         (cond_code, cond, cop1, NULL))
4217                            != UNKNOWN))
4218                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4219                                              cond, cop1);
4220
4221               /* Likewise, we can make the negate of a comparison operation
4222                  if the result values are - STORE_FLAG_VALUE and zero.  */
4223               else if (GET_CODE (true_rtx) == CONST_INT
4224                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4225                        && false_rtx == const0_rtx)
4226                 x = simplify_gen_unary (NEG, mode,
4227                                         simplify_gen_relational (cond_code,
4228                                                                  mode, VOIDmode,
4229                                                                  cond, cop1),
4230                                         mode);
4231               else if (GET_CODE (false_rtx) == CONST_INT
4232                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4233                        && true_rtx == const0_rtx
4234                        && ((reversed = reversed_comparison_code_parts
4235                                         (cond_code, cond, cop1, NULL))
4236                            != UNKNOWN))
4237                 x = simplify_gen_unary (NEG, mode,
4238                                         simplify_gen_relational (reversed,
4239                                                                  mode, VOIDmode,
4240                                                                  cond, cop1),
4241                                         mode);
4242               else
4243                 return gen_rtx_IF_THEN_ELSE (mode,
4244                                              simplify_gen_relational (cond_code,
4245                                                                       mode,
4246                                                                       VOIDmode,
4247                                                                       cond,
4248                                                                       cop1),
4249                                              true_rtx, false_rtx);
4250
4251               code = GET_CODE (x);
4252               op0_mode = VOIDmode;
4253             }
4254         }
4255     }
4256
4257   /* Try to fold this expression in case we have constants that weren't
4258      present before.  */
4259   temp = 0;
4260   switch (GET_RTX_CLASS (code))
4261     {
4262     case RTX_UNARY:
4263       if (op0_mode == VOIDmode)
4264         op0_mode = GET_MODE (XEXP (x, 0));
4265       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4266       break;
4267     case RTX_COMPARE:
4268     case RTX_COMM_COMPARE:
4269       {
4270         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4271         if (cmp_mode == VOIDmode)
4272           {
4273             cmp_mode = GET_MODE (XEXP (x, 1));
4274             if (cmp_mode == VOIDmode)
4275               cmp_mode = op0_mode;
4276           }
4277         temp = simplify_relational_operation (code, mode, cmp_mode,
4278                                               XEXP (x, 0), XEXP (x, 1));
4279       }
4280       break;
4281     case RTX_COMM_ARITH:
4282     case RTX_BIN_ARITH:
4283       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4284       break;
4285     case RTX_BITFIELD_OPS:
4286     case RTX_TERNARY:
4287       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4288                                          XEXP (x, 1), XEXP (x, 2));
4289       break;
4290     default:
4291       break;
4292     }
4293
4294   if (temp)
4295     {
4296       x = temp;
4297       code = GET_CODE (temp);
4298       op0_mode = VOIDmode;
4299       mode = GET_MODE (temp);
4300     }
4301
4302   /* First see if we can apply the inverse distributive law.  */
4303   if (code == PLUS || code == MINUS
4304       || code == AND || code == IOR || code == XOR)
4305     {
4306       x = apply_distributive_law (x);
4307       code = GET_CODE (x);
4308       op0_mode = VOIDmode;
4309     }
4310
4311   /* If CODE is an associative operation not otherwise handled, see if we
4312      can associate some operands.  This can win if they are constants or
4313      if they are logically related (i.e. (a & b) & a).  */
4314   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4315        || code == AND || code == IOR || code == XOR
4316        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4317       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4318           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4319     {
4320       if (GET_CODE (XEXP (x, 0)) == code)
4321         {
4322           rtx other = XEXP (XEXP (x, 0), 0);
4323           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4324           rtx inner_op1 = XEXP (x, 1);
4325           rtx inner;
4326
4327           /* Make sure we pass the constant operand if any as the second
4328              one if this is a commutative operation.  */
4329           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4330             {
4331               rtx tem = inner_op0;
4332               inner_op0 = inner_op1;
4333               inner_op1 = tem;
4334             }
4335           inner = simplify_binary_operation (code == MINUS ? PLUS
4336                                              : code == DIV ? MULT
4337                                              : code,
4338                                              mode, inner_op0, inner_op1);
4339
4340           /* For commutative operations, try the other pair if that one
4341              didn't simplify.  */
4342           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4343             {
4344               other = XEXP (XEXP (x, 0), 1);
4345               inner = simplify_binary_operation (code, mode,
4346                                                  XEXP (XEXP (x, 0), 0),
4347                                                  XEXP (x, 1));
4348             }
4349
4350           if (inner)
4351             return simplify_gen_binary (code, mode, other, inner);
4352         }
4353     }
4354
4355   /* A little bit of algebraic simplification here.  */
4356   switch (code)
4357     {
4358     case MEM:
4359       /* Ensure that our address has any ASHIFTs converted to MULT in case
4360          address-recognizing predicates are called later.  */
4361       temp = make_compound_operation (XEXP (x, 0), MEM);
4362       SUBST (XEXP (x, 0), temp);
4363       break;
4364
4365     case SUBREG:
4366       if (op0_mode == VOIDmode)
4367         op0_mode = GET_MODE (SUBREG_REG (x));
4368
4369       /* See if this can be moved to simplify_subreg.  */
4370       if (CONSTANT_P (SUBREG_REG (x))
4371           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4372              /* Don't call gen_lowpart if the inner mode
4373                 is VOIDmode and we cannot simplify it, as SUBREG without
4374                 inner mode is invalid.  */
4375           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4376               || gen_lowpart_common (mode, SUBREG_REG (x))))
4377         return gen_lowpart (mode, SUBREG_REG (x));
4378
4379       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4380         break;
4381       {
4382         rtx temp;
4383         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4384                                 SUBREG_BYTE (x));
4385         if (temp)
4386           return temp;
4387       }
4388
4389       /* Don't change the mode of the MEM if that would change the meaning
4390          of the address.  */
4391       if (MEM_P (SUBREG_REG (x))
4392           && (MEM_VOLATILE_P (SUBREG_REG (x))
4393               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4394         return gen_rtx_CLOBBER (mode, const0_rtx);
4395
4396       /* Note that we cannot do any narrowing for non-constants since
4397          we might have been counting on using the fact that some bits were
4398          zero.  We now do this in the SET.  */
4399
4400       break;
4401
4402     case NEG:
4403       temp = expand_compound_operation (XEXP (x, 0));
4404
4405       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4406          replaced by (lshiftrt X C).  This will convert
4407          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4408
4409       if (GET_CODE (temp) == ASHIFTRT
4410           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4411           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4412         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4413                                      INTVAL (XEXP (temp, 1)));
4414
4415       /* If X has only a single bit that might be nonzero, say, bit I, convert
4416          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4417          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4418          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4419          or a SUBREG of one since we'd be making the expression more
4420          complex if it was just a register.  */
4421
4422       if (!REG_P (temp)
4423           && ! (GET_CODE (temp) == SUBREG
4424                 && REG_P (SUBREG_REG (temp)))
4425           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4426         {
4427           rtx temp1 = simplify_shift_const
4428             (NULL_RTX, ASHIFTRT, mode,
4429              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4430                                    GET_MODE_BITSIZE (mode) - 1 - i),
4431              GET_MODE_BITSIZE (mode) - 1 - i);
4432
4433           /* If all we did was surround TEMP with the two shifts, we
4434              haven't improved anything, so don't use it.  Otherwise,
4435              we are better off with TEMP1.  */
4436           if (GET_CODE (temp1) != ASHIFTRT
4437               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4438               || XEXP (XEXP (temp1, 0), 0) != temp)
4439             return temp1;
4440         }
4441       break;
4442
4443     case TRUNCATE:
4444       /* We can't handle truncation to a partial integer mode here
4445          because we don't know the real bitsize of the partial
4446          integer mode.  */
4447       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4448         break;
4449
4450       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4451           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4452                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4453         SUBST (XEXP (x, 0),
4454                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4455                               GET_MODE_MASK (mode), 0));
4456
4457       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4458          whose value is a comparison can be replaced with a subreg if
4459          STORE_FLAG_VALUE permits.  */
4460       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4461           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4462           && (temp = get_last_value (XEXP (x, 0)))
4463           && COMPARISON_P (temp))
4464         return gen_lowpart (mode, XEXP (x, 0));
4465       break;
4466
4467 #ifdef HAVE_cc0
4468     case COMPARE:
4469       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4470          using cc0, in which case we want to leave it as a COMPARE
4471          so we can distinguish it from a register-register-copy.  */
4472       if (XEXP (x, 1) == const0_rtx)
4473         return XEXP (x, 0);
4474
4475       /* x - 0 is the same as x unless x's mode has signed zeros and
4476          allows rounding towards -infinity.  Under those conditions,
4477          0 - 0 is -0.  */
4478       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4479             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4480           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4481         return XEXP (x, 0);
4482       break;
4483 #endif
4484
4485     case CONST:
4486       /* (const (const X)) can become (const X).  Do it this way rather than
4487          returning the inner CONST since CONST can be shared with a
4488          REG_EQUAL note.  */
4489       if (GET_CODE (XEXP (x, 0)) == CONST)
4490         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4491       break;
4492
4493 #ifdef HAVE_lo_sum
4494     case LO_SUM:
4495       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4496          can add in an offset.  find_split_point will split this address up
4497          again if it doesn't match.  */
4498       if (GET_CODE (XEXP (x, 0)) == HIGH
4499           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4500         return XEXP (x, 1);
4501       break;
4502 #endif
4503
4504     case PLUS:
4505       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4506          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4507          bit-field and can be replaced by either a sign_extend or a
4508          sign_extract.  The `and' may be a zero_extend and the two
4509          <c>, -<c> constants may be reversed.  */
4510       if (GET_CODE (XEXP (x, 0)) == XOR
4511           && GET_CODE (XEXP (x, 1)) == CONST_INT
4512           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4513           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4514           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4515               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4516           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4517           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4518                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4519                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4520                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4521               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4522                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4523                       == (unsigned int) i + 1))))
4524         return simplify_shift_const
4525           (NULL_RTX, ASHIFTRT, mode,
4526            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4527                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4528                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4529            GET_MODE_BITSIZE (mode) - (i + 1));
4530
4531       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4532          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4533          the bitsize of the mode - 1.  This allows simplification of
4534          "a = (b & 8) == 0;"  */
4535       if (XEXP (x, 1) == constm1_rtx
4536           && !REG_P (XEXP (x, 0))
4537           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4538                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4539           && nonzero_bits (XEXP (x, 0), mode) == 1)
4540         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4541            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4542                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4543                                  GET_MODE_BITSIZE (mode) - 1),
4544            GET_MODE_BITSIZE (mode) - 1);
4545
4546       /* If we are adding two things that have no bits in common, convert
4547          the addition into an IOR.  This will often be further simplified,
4548          for example in cases like ((a & 1) + (a & 2)), which can
4549          become a & 3.  */
4550
4551       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4552           && (nonzero_bits (XEXP (x, 0), mode)
4553               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4554         {
4555           /* Try to simplify the expression further.  */
4556           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4557           temp = combine_simplify_rtx (tor, mode, in_dest);
4558
4559           /* If we could, great.  If not, do not go ahead with the IOR
4560              replacement, since PLUS appears in many special purpose
4561              address arithmetic instructions.  */
4562           if (GET_CODE (temp) != CLOBBER && temp != tor)
4563             return temp;
4564         }
4565       break;
4566
4567     case MINUS:
4568       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4569          (and <foo> (const_int pow2-1))  */
4570       if (GET_CODE (XEXP (x, 1)) == AND
4571           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4572           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4573           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4574         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4575                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4576       break;
4577
4578     case MULT:
4579       /* If we have (mult (plus A B) C), apply the distributive law and then
4580          the inverse distributive law to see if things simplify.  This
4581          occurs mostly in addresses, often when unrolling loops.  */
4582
4583       if (GET_CODE (XEXP (x, 0)) == PLUS)
4584         {
4585           rtx result = distribute_and_simplify_rtx (x, 0);
4586           if (result)
4587             return result;
4588         }
4589
4590       /* Try simplify a*(b/c) as (a*b)/c.  */
4591       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4592           && GET_CODE (XEXP (x, 0)) == DIV)
4593         {
4594           rtx tem = simplify_binary_operation (MULT, mode,
4595                                                XEXP (XEXP (x, 0), 0),
4596                                                XEXP (x, 1));
4597           if (tem)
4598             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4599         }
4600       break;
4601
4602     case UDIV:
4603       /* If this is a divide by a power of two, treat it as a shift if
4604          its first operand is a shift.  */
4605       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4606           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4607           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4608               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4609               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4610               || GET_CODE (XEXP (x, 0)) == ROTATE
4611               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4612         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4613       break;
4614
4615     case EQ:  case NE:
4616     case GT:  case GTU:  case GE:  case GEU:
4617     case LT:  case LTU:  case LE:  case LEU:
4618     case UNEQ:  case LTGT:
4619     case UNGT:  case UNGE:
4620     case UNLT:  case UNLE:
4621     case UNORDERED: case ORDERED:
4622       /* If the first operand is a condition code, we can't do anything
4623          with it.  */
4624       if (GET_CODE (XEXP (x, 0)) == COMPARE
4625           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4626               && ! CC0_P (XEXP (x, 0))))
4627         {
4628           rtx op0 = XEXP (x, 0);
4629           rtx op1 = XEXP (x, 1);
4630           enum rtx_code new_code;
4631
4632           if (GET_CODE (op0) == COMPARE)
4633             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4634
4635           /* Simplify our comparison, if possible.  */
4636           new_code = simplify_comparison (code, &op0, &op1);
4637
4638           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4639              if only the low-order bit is possibly nonzero in X (such as when
4640              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4641              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4642              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4643              (plus X 1).
4644
4645              Remove any ZERO_EXTRACT we made when thinking this was a
4646              comparison.  It may now be simpler to use, e.g., an AND.  If a
4647              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4648              the call to make_compound_operation in the SET case.  */
4649
4650           if (STORE_FLAG_VALUE == 1
4651               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4652               && op1 == const0_rtx
4653               && mode == GET_MODE (op0)
4654               && nonzero_bits (op0, mode) == 1)
4655             return gen_lowpart (mode,
4656                                 expand_compound_operation (op0));
4657
4658           else if (STORE_FLAG_VALUE == 1
4659                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4660                    && op1 == const0_rtx
4661                    && mode == GET_MODE (op0)
4662                    && (num_sign_bit_copies (op0, mode)
4663                        == GET_MODE_BITSIZE (mode)))
4664             {
4665               op0 = expand_compound_operation (op0);
4666               return simplify_gen_unary (NEG, mode,
4667                                          gen_lowpart (mode, op0),
4668                                          mode);
4669             }
4670
4671           else if (STORE_FLAG_VALUE == 1
4672                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4673                    && op1 == const0_rtx
4674                    && mode == GET_MODE (op0)
4675                    && nonzero_bits (op0, mode) == 1)
4676             {
4677               op0 = expand_compound_operation (op0);
4678               return simplify_gen_binary (XOR, mode,
4679                                           gen_lowpart (mode, op0),
4680                                           const1_rtx);
4681             }
4682
4683           else if (STORE_FLAG_VALUE == 1
4684                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4685                    && op1 == const0_rtx
4686                    && mode == GET_MODE (op0)
4687                    && (num_sign_bit_copies (op0, mode)
4688                        == GET_MODE_BITSIZE (mode)))
4689             {
4690               op0 = expand_compound_operation (op0);
4691               return plus_constant (gen_lowpart (mode, op0), 1);
4692             }
4693
4694           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4695              those above.  */
4696           if (STORE_FLAG_VALUE == -1
4697               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4698               && op1 == const0_rtx
4699               && (num_sign_bit_copies (op0, mode)
4700                   == GET_MODE_BITSIZE (mode)))
4701             return gen_lowpart (mode,
4702                                 expand_compound_operation (op0));
4703
4704           else if (STORE_FLAG_VALUE == -1
4705                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4706                    && op1 == const0_rtx
4707                    && mode == GET_MODE (op0)
4708                    && nonzero_bits (op0, mode) == 1)
4709             {
4710               op0 = expand_compound_operation (op0);
4711               return simplify_gen_unary (NEG, mode,
4712                                          gen_lowpart (mode, op0),
4713                                          mode);
4714             }
4715
4716           else if (STORE_FLAG_VALUE == -1
4717                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4718                    && op1 == const0_rtx
4719                    && mode == GET_MODE (op0)
4720                    && (num_sign_bit_copies (op0, mode)
4721                        == GET_MODE_BITSIZE (mode)))
4722             {
4723               op0 = expand_compound_operation (op0);
4724               return simplify_gen_unary (NOT, mode,
4725                                          gen_lowpart (mode, op0),
4726                                          mode);
4727             }
4728
4729           /* If X is 0/1, (eq X 0) is X-1.  */
4730           else if (STORE_FLAG_VALUE == -1
4731                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4732                    && op1 == const0_rtx
4733                    && mode == GET_MODE (op0)
4734                    && nonzero_bits (op0, mode) == 1)
4735             {
4736               op0 = expand_compound_operation (op0);
4737               return plus_constant (gen_lowpart (mode, op0), -1);
4738             }
4739
4740           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4741              one bit that might be nonzero, we can convert (ne x 0) to
4742              (ashift x c) where C puts the bit in the sign bit.  Remove any
4743              AND with STORE_FLAG_VALUE when we are done, since we are only
4744              going to test the sign bit.  */
4745           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4746               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4747               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4748                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4749               && op1 == const0_rtx
4750               && mode == GET_MODE (op0)
4751               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4752             {
4753               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4754                                         expand_compound_operation (op0),
4755                                         GET_MODE_BITSIZE (mode) - 1 - i);
4756               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4757                 return XEXP (x, 0);
4758               else
4759                 return x;
4760             }
4761
4762           /* If the code changed, return a whole new comparison.  */
4763           if (new_code != code)
4764             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4765
4766           /* Otherwise, keep this operation, but maybe change its operands.
4767              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4768           SUBST (XEXP (x, 0), op0);
4769           SUBST (XEXP (x, 1), op1);
4770         }
4771       break;
4772
4773     case IF_THEN_ELSE:
4774       return simplify_if_then_else (x);
4775
4776     case ZERO_EXTRACT:
4777     case SIGN_EXTRACT:
4778     case ZERO_EXTEND:
4779     case SIGN_EXTEND:
4780       /* If we are processing SET_DEST, we are done.  */
4781       if (in_dest)
4782         return x;
4783
4784       return expand_compound_operation (x);
4785
4786     case SET:
4787       return simplify_set (x);
4788
4789     case AND:
4790     case IOR:
4791       return simplify_logical (x);
4792
4793     case ASHIFT:
4794     case LSHIFTRT:
4795     case ASHIFTRT:
4796     case ROTATE:
4797     case ROTATERT:
4798       /* If this is a shift by a constant amount, simplify it.  */
4799       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4800         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4801                                      INTVAL (XEXP (x, 1)));
4802
4803       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4804         SUBST (XEXP (x, 1),
4805                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4806                               ((HOST_WIDE_INT) 1
4807                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4808                               - 1,
4809                               0));
4810       break;
4811
4812     default:
4813       break;
4814     }
4815
4816   return x;
4817 }
4818 \f
4819 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4820
4821 static rtx
4822 simplify_if_then_else (rtx x)
4823 {
4824   enum machine_mode mode = GET_MODE (x);
4825   rtx cond = XEXP (x, 0);
4826   rtx true_rtx = XEXP (x, 1);
4827   rtx false_rtx = XEXP (x, 2);
4828   enum rtx_code true_code = GET_CODE (cond);
4829   int comparison_p = COMPARISON_P (cond);
4830   rtx temp;
4831   int i;
4832   enum rtx_code false_code;
4833   rtx reversed;
4834
4835   /* Simplify storing of the truth value.  */
4836   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4837     return simplify_gen_relational (true_code, mode, VOIDmode,
4838                                     XEXP (cond, 0), XEXP (cond, 1));
4839
4840   /* Also when the truth value has to be reversed.  */
4841   if (comparison_p
4842       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4843       && (reversed = reversed_comparison (cond, mode)))
4844     return reversed;
4845
4846   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4847      in it is being compared against certain values.  Get the true and false
4848      comparisons and see if that says anything about the value of each arm.  */
4849
4850   if (comparison_p
4851       && ((false_code = reversed_comparison_code (cond, NULL))
4852           != UNKNOWN)
4853       && REG_P (XEXP (cond, 0)))
4854     {
4855       HOST_WIDE_INT nzb;
4856       rtx from = XEXP (cond, 0);
4857       rtx true_val = XEXP (cond, 1);
4858       rtx false_val = true_val;
4859       int swapped = 0;
4860
4861       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4862
4863       if (false_code == EQ)
4864         {
4865           swapped = 1, true_code = EQ, false_code = NE;
4866           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4867         }
4868
4869       /* If we are comparing against zero and the expression being tested has
4870          only a single bit that might be nonzero, that is its value when it is
4871          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4872
4873       if (true_code == EQ && true_val == const0_rtx
4874           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4875         false_code = EQ, false_val = GEN_INT (nzb);
4876       else if (true_code == EQ && true_val == const0_rtx
4877                && (num_sign_bit_copies (from, GET_MODE (from))
4878                    == GET_MODE_BITSIZE (GET_MODE (from))))
4879         false_code = EQ, false_val = constm1_rtx;
4880
4881       /* Now simplify an arm if we know the value of the register in the
4882          branch and it is used in the arm.  Be careful due to the potential
4883          of locally-shared RTL.  */
4884
4885       if (reg_mentioned_p (from, true_rtx))
4886         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4887                                       from, true_val),
4888                       pc_rtx, pc_rtx, 0, 0);
4889       if (reg_mentioned_p (from, false_rtx))
4890         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4891                                    from, false_val),
4892                        pc_rtx, pc_rtx, 0, 0);
4893
4894       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4895       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4896
4897       true_rtx = XEXP (x, 1);
4898       false_rtx = XEXP (x, 2);
4899       true_code = GET_CODE (cond);
4900     }
4901
4902   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4903      reversed, do so to avoid needing two sets of patterns for
4904      subtract-and-branch insns.  Similarly if we have a constant in the true
4905      arm, the false arm is the same as the first operand of the comparison, or
4906      the false arm is more complicated than the true arm.  */
4907
4908   if (comparison_p
4909       && reversed_comparison_code (cond, NULL) != UNKNOWN
4910       && (true_rtx == pc_rtx
4911           || (CONSTANT_P (true_rtx)
4912               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4913           || true_rtx == const0_rtx
4914           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4915           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4916               && !OBJECT_P (false_rtx))
4917           || reg_mentioned_p (true_rtx, false_rtx)
4918           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4919     {
4920       true_code = reversed_comparison_code (cond, NULL);
4921       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4922       SUBST (XEXP (x, 1), false_rtx);
4923       SUBST (XEXP (x, 2), true_rtx);
4924
4925       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4926       cond = XEXP (x, 0);
4927
4928       /* It is possible that the conditional has been simplified out.  */
4929       true_code = GET_CODE (cond);
4930       comparison_p = COMPARISON_P (cond);
4931     }
4932
4933   /* If the two arms are identical, we don't need the comparison.  */
4934
4935   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4936     return true_rtx;
4937
4938   /* Convert a == b ? b : a to "a".  */
4939   if (true_code == EQ && ! side_effects_p (cond)
4940       && !HONOR_NANS (mode)
4941       && rtx_equal_p (XEXP (cond, 0), false_rtx)
4942       && rtx_equal_p (XEXP (cond, 1), true_rtx))
4943     return false_rtx;
4944   else if (true_code == NE && ! side_effects_p (cond)
4945            && !HONOR_NANS (mode)
4946            && rtx_equal_p (XEXP (cond, 0), true_rtx)
4947            && rtx_equal_p (XEXP (cond, 1), false_rtx))
4948     return true_rtx;
4949
4950   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4951
4952   if (GET_MODE_CLASS (mode) == MODE_INT
4953       && GET_CODE (false_rtx) == NEG
4954       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4955       && comparison_p
4956       && rtx_equal_p (true_rtx, XEXP (cond, 0))
4957       && ! side_effects_p (true_rtx))
4958     switch (true_code)
4959       {
4960       case GT:
4961       case GE:
4962         return simplify_gen_unary (ABS, mode, true_rtx, mode);
4963       case LT:
4964       case LE:
4965         return
4966           simplify_gen_unary (NEG, mode,
4967                               simplify_gen_unary (ABS, mode, true_rtx, mode),
4968                               mode);
4969       default:
4970         break;
4971       }
4972
4973   /* Look for MIN or MAX.  */
4974
4975   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4976       && comparison_p
4977       && rtx_equal_p (XEXP (cond, 0), true_rtx)
4978       && rtx_equal_p (XEXP (cond, 1), false_rtx)
4979       && ! side_effects_p (cond))
4980     switch (true_code)
4981       {
4982       case GE:
4983       case GT:
4984         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4985       case LE:
4986       case LT:
4987         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4988       case GEU:
4989       case GTU:
4990         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4991       case LEU:
4992       case LTU:
4993         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4994       default:
4995         break;
4996       }
4997
4998   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4999      second operand is zero, this can be done as (OP Z (mult COND C2)) where
5000      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5001      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5002      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5003      neither 1 or -1, but it isn't worth checking for.  */
5004
5005   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5006       && comparison_p
5007       && GET_MODE_CLASS (mode) == MODE_INT
5008       && ! side_effects_p (x))
5009     {
5010       rtx t = make_compound_operation (true_rtx, SET);
5011       rtx f = make_compound_operation (false_rtx, SET);
5012       rtx cond_op0 = XEXP (cond, 0);
5013       rtx cond_op1 = XEXP (cond, 1);
5014       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5015       enum machine_mode m = mode;
5016       rtx z = 0, c1 = NULL_RTX;
5017
5018       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5019            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5020            || GET_CODE (t) == ASHIFT
5021            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5022           && rtx_equal_p (XEXP (t, 0), f))
5023         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5024
5025       /* If an identity-zero op is commutative, check whether there
5026          would be a match if we swapped the operands.  */
5027       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5028                 || GET_CODE (t) == XOR)
5029                && rtx_equal_p (XEXP (t, 1), f))
5030         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5031       else if (GET_CODE (t) == SIGN_EXTEND
5032                && (GET_CODE (XEXP (t, 0)) == PLUS
5033                    || GET_CODE (XEXP (t, 0)) == MINUS
5034                    || GET_CODE (XEXP (t, 0)) == IOR
5035                    || GET_CODE (XEXP (t, 0)) == XOR
5036                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5037                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5038                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5039                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5040                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5041                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5042                && (num_sign_bit_copies (f, GET_MODE (f))
5043                    > (unsigned int)
5044                      (GET_MODE_BITSIZE (mode)
5045                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5046         {
5047           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5048           extend_op = SIGN_EXTEND;
5049           m = GET_MODE (XEXP (t, 0));
5050         }
5051       else if (GET_CODE (t) == SIGN_EXTEND
5052                && (GET_CODE (XEXP (t, 0)) == PLUS
5053                    || GET_CODE (XEXP (t, 0)) == IOR
5054                    || GET_CODE (XEXP (t, 0)) == XOR)
5055                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5056                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5057                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5058                && (num_sign_bit_copies (f, GET_MODE (f))
5059                    > (unsigned int)
5060                      (GET_MODE_BITSIZE (mode)
5061                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5062         {
5063           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5064           extend_op = SIGN_EXTEND;
5065           m = GET_MODE (XEXP (t, 0));
5066         }
5067       else if (GET_CODE (t) == ZERO_EXTEND
5068                && (GET_CODE (XEXP (t, 0)) == PLUS
5069                    || GET_CODE (XEXP (t, 0)) == MINUS
5070                    || GET_CODE (XEXP (t, 0)) == IOR
5071                    || GET_CODE (XEXP (t, 0)) == XOR
5072                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5073                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5074                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5075                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5076                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5077                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5078                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5079                && ((nonzero_bits (f, GET_MODE (f))
5080                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5081                    == 0))
5082         {
5083           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5084           extend_op = ZERO_EXTEND;
5085           m = GET_MODE (XEXP (t, 0));
5086         }
5087       else if (GET_CODE (t) == ZERO_EXTEND
5088                && (GET_CODE (XEXP (t, 0)) == PLUS
5089                    || GET_CODE (XEXP (t, 0)) == IOR
5090                    || GET_CODE (XEXP (t, 0)) == XOR)
5091                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5092                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5093                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5094                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5095                && ((nonzero_bits (f, GET_MODE (f))
5096                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5097                    == 0))
5098         {
5099           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5100           extend_op = ZERO_EXTEND;
5101           m = GET_MODE (XEXP (t, 0));
5102         }
5103
5104       if (z)
5105         {
5106           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5107                                                  cond_op0, cond_op1),
5108                         pc_rtx, pc_rtx, 0, 0);
5109           temp = simplify_gen_binary (MULT, m, temp,
5110                                       simplify_gen_binary (MULT, m, c1,
5111                                                            const_true_rtx));
5112           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5113           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5114
5115           if (extend_op != UNKNOWN)
5116             temp = simplify_gen_unary (extend_op, mode, temp, m);
5117
5118           return temp;
5119         }
5120     }
5121
5122   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5123      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5124      negation of a single bit, we can convert this operation to a shift.  We
5125      can actually do this more generally, but it doesn't seem worth it.  */
5126
5127   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5128       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5129       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5130            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5131           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5132                == GET_MODE_BITSIZE (mode))
5133               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5134     return
5135       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5136                             gen_lowpart (mode, XEXP (cond, 0)), i);
5137
5138   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5139   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5140       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5141       && GET_MODE (XEXP (cond, 0)) == mode
5142       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5143           == nonzero_bits (XEXP (cond, 0), mode)
5144       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5145     return XEXP (cond, 0);
5146
5147   return x;
5148 }
5149 \f
5150 /* Simplify X, a SET expression.  Return the new expression.  */
5151
5152 static rtx
5153 simplify_set (rtx x)
5154 {
5155   rtx src = SET_SRC (x);
5156   rtx dest = SET_DEST (x);
5157   enum machine_mode mode
5158     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5159   rtx other_insn;
5160   rtx *cc_use;
5161
5162   /* (set (pc) (return)) gets written as (return).  */
5163   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5164     return src;
5165
5166   /* Now that we know for sure which bits of SRC we are using, see if we can
5167      simplify the expression for the object knowing that we only need the
5168      low-order bits.  */
5169
5170   if (GET_MODE_CLASS (mode) == MODE_INT
5171       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5172     {
5173       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5174       SUBST (SET_SRC (x), src);
5175     }
5176
5177   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5178      the comparison result and try to simplify it unless we already have used
5179      undobuf.other_insn.  */
5180   if ((GET_MODE_CLASS (mode) == MODE_CC
5181        || GET_CODE (src) == COMPARE
5182        || CC0_P (dest))
5183       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5184       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5185       && COMPARISON_P (*cc_use)
5186       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5187     {
5188       enum rtx_code old_code = GET_CODE (*cc_use);
5189       enum rtx_code new_code;
5190       rtx op0, op1, tmp;
5191       int other_changed = 0;
5192       enum machine_mode compare_mode = GET_MODE (dest);
5193
5194       if (GET_CODE (src) == COMPARE)
5195         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5196       else
5197         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5198
5199       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5200                                            op0, op1);
5201       if (!tmp)
5202         new_code = old_code;
5203       else if (!CONSTANT_P (tmp))
5204         {
5205           new_code = GET_CODE (tmp);
5206           op0 = XEXP (tmp, 0);
5207           op1 = XEXP (tmp, 1);
5208         }
5209       else
5210         {
5211           rtx pat = PATTERN (other_insn);
5212           undobuf.other_insn = other_insn;
5213           SUBST (*cc_use, tmp);
5214
5215           /* Attempt to simplify CC user.  */
5216           if (GET_CODE (pat) == SET)
5217             {
5218               rtx new = simplify_rtx (SET_SRC (pat));
5219               if (new != NULL_RTX)
5220                 SUBST (SET_SRC (pat), new);
5221             }
5222
5223           /* Convert X into a no-op move.  */
5224           SUBST (SET_DEST (x), pc_rtx);
5225           SUBST (SET_SRC (x), pc_rtx);
5226           return x;
5227         }
5228
5229       /* Simplify our comparison, if possible.  */
5230       new_code = simplify_comparison (new_code, &op0, &op1);
5231
5232 #ifdef SELECT_CC_MODE
5233       /* If this machine has CC modes other than CCmode, check to see if we
5234          need to use a different CC mode here.  */
5235       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5236         compare_mode = GET_MODE (op0);
5237       else
5238         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5239
5240 #ifndef HAVE_cc0
5241       /* If the mode changed, we have to change SET_DEST, the mode in the
5242          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5243          a hard register, just build new versions with the proper mode.  If it
5244          is a pseudo, we lose unless it is only time we set the pseudo, in
5245          which case we can safely change its mode.  */
5246       if (compare_mode != GET_MODE (dest))
5247         {
5248           if (can_change_dest_mode (dest, 0, compare_mode))
5249             {
5250               unsigned int regno = REGNO (dest);
5251               rtx new_dest;
5252
5253               if (regno < FIRST_PSEUDO_REGISTER)
5254                 new_dest = gen_rtx_REG (compare_mode, regno);
5255               else
5256                 {
5257                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5258                   new_dest = regno_reg_rtx[regno];
5259                 }
5260
5261               SUBST (SET_DEST (x), new_dest);
5262               SUBST (XEXP (*cc_use, 0), new_dest);
5263               other_changed = 1;
5264
5265               dest = new_dest;
5266             }
5267         }
5268 #endif  /* cc0 */
5269 #endif  /* SELECT_CC_MODE */
5270
5271       /* If the code changed, we have to build a new comparison in
5272          undobuf.other_insn.  */
5273       if (new_code != old_code)
5274         {
5275           int other_changed_previously = other_changed;
5276           unsigned HOST_WIDE_INT mask;
5277
5278           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5279                                           dest, const0_rtx));
5280           other_changed = 1;
5281
5282           /* If the only change we made was to change an EQ into an NE or
5283              vice versa, OP0 has only one bit that might be nonzero, and OP1
5284              is zero, check if changing the user of the condition code will
5285              produce a valid insn.  If it won't, we can keep the original code
5286              in that insn by surrounding our operation with an XOR.  */
5287
5288           if (((old_code == NE && new_code == EQ)
5289                || (old_code == EQ && new_code == NE))
5290               && ! other_changed_previously && op1 == const0_rtx
5291               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5292               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5293             {
5294               rtx pat = PATTERN (other_insn), note = 0;
5295
5296               if ((recog_for_combine (&pat, other_insn, &note) < 0
5297                    && ! check_asm_operands (pat)))
5298                 {
5299                   PUT_CODE (*cc_use, old_code);
5300                   other_changed = 0;
5301
5302                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5303                                              op0, GEN_INT (mask));
5304                 }
5305             }
5306         }
5307
5308       if (other_changed)
5309         undobuf.other_insn = other_insn;
5310
5311 #ifdef HAVE_cc0
5312       /* If we are now comparing against zero, change our source if
5313          needed.  If we do not use cc0, we always have a COMPARE.  */
5314       if (op1 == const0_rtx && dest == cc0_rtx)
5315         {
5316           SUBST (SET_SRC (x), op0);
5317           src = op0;
5318         }
5319       else
5320 #endif
5321
5322       /* Otherwise, if we didn't previously have a COMPARE in the
5323          correct mode, we need one.  */
5324       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5325         {
5326           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5327           src = SET_SRC (x);
5328         }
5329       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5330         {
5331           SUBST(SET_SRC (x), op0);
5332           src = SET_SRC (x);
5333         }
5334       else
5335         {
5336           /* Otherwise, update the COMPARE if needed.  */
5337           SUBST (XEXP (src, 0), op0);
5338           SUBST (XEXP (src, 1), op1);
5339         }
5340     }
5341   else
5342     {
5343       /* Get SET_SRC in a form where we have placed back any
5344          compound expressions.  Then do the checks below.  */
5345       src = make_compound_operation (src, SET);
5346       SUBST (SET_SRC (x), src);
5347     }
5348
5349   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5350      and X being a REG or (subreg (reg)), we may be able to convert this to
5351      (set (subreg:m2 x) (op)).
5352
5353      We can always do this if M1 is narrower than M2 because that means that
5354      we only care about the low bits of the result.
5355
5356      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5357      perform a narrower operation than requested since the high-order bits will
5358      be undefined.  On machine where it is defined, this transformation is safe
5359      as long as M1 and M2 have the same number of words.  */
5360
5361   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5362       && !OBJECT_P (SUBREG_REG (src))
5363       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5364            / UNITS_PER_WORD)
5365           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5366                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5367 #ifndef WORD_REGISTER_OPERATIONS
5368       && (GET_MODE_SIZE (GET_MODE (src))
5369         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5370 #endif
5371 #ifdef CANNOT_CHANGE_MODE_CLASS
5372       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5373             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5374                                          GET_MODE (SUBREG_REG (src)),
5375                                          GET_MODE (src)))
5376 #endif
5377       && (REG_P (dest)
5378           || (GET_CODE (dest) == SUBREG
5379               && REG_P (SUBREG_REG (dest)))))
5380     {
5381       SUBST (SET_DEST (x),
5382              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5383                                       dest));
5384       SUBST (SET_SRC (x), SUBREG_REG (src));
5385
5386       src = SET_SRC (x), dest = SET_DEST (x);
5387     }
5388
5389 #ifdef HAVE_cc0
5390   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5391      in SRC.  */
5392   if (dest == cc0_rtx
5393       && GET_CODE (src) == SUBREG
5394       && subreg_lowpart_p (src)
5395       && (GET_MODE_BITSIZE (GET_MODE (src))
5396           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5397     {
5398       rtx inner = SUBREG_REG (src);
5399       enum machine_mode inner_mode = GET_MODE (inner);
5400
5401       /* Here we make sure that we don't have a sign bit on.  */
5402       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5403           && (nonzero_bits (inner, inner_mode)
5404               < ((unsigned HOST_WIDE_INT) 1
5405                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5406         {
5407           SUBST (SET_SRC (x), inner);
5408           src = SET_SRC (x);
5409         }
5410     }
5411 #endif
5412
5413 #ifdef LOAD_EXTEND_OP
5414   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5415      would require a paradoxical subreg.  Replace the subreg with a
5416      zero_extend to avoid the reload that would otherwise be required.  */
5417
5418   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5419       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5420       && SUBREG_BYTE (src) == 0
5421       && (GET_MODE_SIZE (GET_MODE (src))
5422           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5423       && MEM_P (SUBREG_REG (src)))
5424     {
5425       SUBST (SET_SRC (x),
5426              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5427                             GET_MODE (src), SUBREG_REG (src)));
5428
5429       src = SET_SRC (x);
5430     }
5431 #endif
5432
5433   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5434      are comparing an item known to be 0 or -1 against 0, use a logical
5435      operation instead. Check for one of the arms being an IOR of the other
5436      arm with some value.  We compute three terms to be IOR'ed together.  In
5437      practice, at most two will be nonzero.  Then we do the IOR's.  */
5438
5439   if (GET_CODE (dest) != PC
5440       && GET_CODE (src) == IF_THEN_ELSE
5441       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5442       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5443       && XEXP (XEXP (src, 0), 1) == const0_rtx
5444       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5445 #ifdef HAVE_conditional_move
5446       && ! can_conditionally_move_p (GET_MODE (src))
5447 #endif
5448       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5449                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5450           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5451       && ! side_effects_p (src))
5452     {
5453       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5454                       ? XEXP (src, 1) : XEXP (src, 2));
5455       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5456                    ? XEXP (src, 2) : XEXP (src, 1));
5457       rtx term1 = const0_rtx, term2, term3;
5458
5459       if (GET_CODE (true_rtx) == IOR
5460           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5461         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5462       else if (GET_CODE (true_rtx) == IOR
5463                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5464         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5465       else if (GET_CODE (false_rtx) == IOR
5466                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5467         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5468       else if (GET_CODE (false_rtx) == IOR
5469                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5470         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5471
5472       term2 = simplify_gen_binary (AND, GET_MODE (src),
5473                                    XEXP (XEXP (src, 0), 0), true_rtx);
5474       term3 = simplify_gen_binary (AND, GET_MODE (src),
5475                                    simplify_gen_unary (NOT, GET_MODE (src),
5476                                                        XEXP (XEXP (src, 0), 0),
5477                                                        GET_MODE (src)),
5478                                    false_rtx);
5479
5480       SUBST (SET_SRC (x),
5481              simplify_gen_binary (IOR, GET_MODE (src),
5482                                   simplify_gen_binary (IOR, GET_MODE (src),
5483                                                        term1, term2),
5484                                   term3));
5485
5486       src = SET_SRC (x);
5487     }
5488
5489   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5490      whole thing fail.  */
5491   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5492     return src;
5493   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5494     return dest;
5495   else
5496     /* Convert this into a field assignment operation, if possible.  */
5497     return make_field_assignment (x);
5498 }
5499 \f
5500 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5501    result.  */
5502
5503 static rtx
5504 simplify_logical (rtx x)
5505 {
5506   enum machine_mode mode = GET_MODE (x);
5507   rtx op0 = XEXP (x, 0);
5508   rtx op1 = XEXP (x, 1);
5509
5510   switch (GET_CODE (x))
5511     {
5512     case AND:
5513       /* We can call simplify_and_const_int only if we don't lose
5514          any (sign) bits when converting INTVAL (op1) to
5515          "unsigned HOST_WIDE_INT".  */
5516       if (GET_CODE (op1) == CONST_INT
5517           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5518               || INTVAL (op1) > 0))
5519         {
5520           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5521           if (GET_CODE (x) != AND)
5522             return x;
5523
5524           op0 = XEXP (x, 0);
5525           op1 = XEXP (x, 1);
5526         }
5527
5528       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5529          apply the distributive law and then the inverse distributive
5530          law to see if things simplify.  */
5531       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5532         {
5533           rtx result = distribute_and_simplify_rtx (x, 0);
5534           if (result)
5535             return result;
5536         }
5537       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5538         {
5539           rtx result = distribute_and_simplify_rtx (x, 1);
5540           if (result)
5541             return result;
5542         }
5543       break;
5544
5545     case IOR:
5546       /* If we have (ior (and A B) C), apply the distributive law and then
5547          the inverse distributive law to see if things simplify.  */
5548
5549       if (GET_CODE (op0) == AND)
5550         {
5551           rtx result = distribute_and_simplify_rtx (x, 0);
5552           if (result)
5553             return result;
5554         }
5555
5556       if (GET_CODE (op1) == AND)
5557         {
5558           rtx result = distribute_and_simplify_rtx (x, 1);
5559           if (result)
5560             return result;
5561         }
5562       break;
5563
5564     default:
5565       gcc_unreachable ();
5566     }
5567
5568   return x;
5569 }
5570 \f
5571 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5572    operations" because they can be replaced with two more basic operations.
5573    ZERO_EXTEND is also considered "compound" because it can be replaced with
5574    an AND operation, which is simpler, though only one operation.
5575
5576    The function expand_compound_operation is called with an rtx expression
5577    and will convert it to the appropriate shifts and AND operations,
5578    simplifying at each stage.
5579
5580    The function make_compound_operation is called to convert an expression
5581    consisting of shifts and ANDs into the equivalent compound expression.
5582    It is the inverse of this function, loosely speaking.  */
5583
5584 static rtx
5585 expand_compound_operation (rtx x)
5586 {
5587   unsigned HOST_WIDE_INT pos = 0, len;
5588   int unsignedp = 0;
5589   unsigned int modewidth;
5590   rtx tem;
5591
5592   switch (GET_CODE (x))
5593     {
5594     case ZERO_EXTEND:
5595       unsignedp = 1;
5596     case SIGN_EXTEND:
5597       /* We can't necessarily use a const_int for a multiword mode;
5598          it depends on implicitly extending the value.
5599          Since we don't know the right way to extend it,
5600          we can't tell whether the implicit way is right.
5601
5602          Even for a mode that is no wider than a const_int,
5603          we can't win, because we need to sign extend one of its bits through
5604          the rest of it, and we don't know which bit.  */
5605       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5606         return x;
5607
5608       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5609          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5610          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5611          reloaded. If not for that, MEM's would very rarely be safe.
5612
5613          Reject MODEs bigger than a word, because we might not be able
5614          to reference a two-register group starting with an arbitrary register
5615          (and currently gen_lowpart might crash for a SUBREG).  */
5616
5617       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5618         return x;
5619
5620       /* Reject MODEs that aren't scalar integers because turning vector
5621          or complex modes into shifts causes problems.  */
5622
5623       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5624         return x;
5625
5626       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5627       /* If the inner object has VOIDmode (the only way this can happen
5628          is if it is an ASM_OPERANDS), we can't do anything since we don't
5629          know how much masking to do.  */
5630       if (len == 0)
5631         return x;
5632
5633       break;
5634
5635     case ZERO_EXTRACT:
5636       unsignedp = 1;
5637
5638       /* ... fall through ...  */
5639
5640     case SIGN_EXTRACT:
5641       /* If the operand is a CLOBBER, just return it.  */
5642       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5643         return XEXP (x, 0);
5644
5645       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5646           || GET_CODE (XEXP (x, 2)) != CONST_INT
5647           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5648         return x;
5649
5650       /* Reject MODEs that aren't scalar integers because turning vector
5651          or complex modes into shifts causes problems.  */
5652
5653       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5654         return x;
5655
5656       len = INTVAL (XEXP (x, 1));
5657       pos = INTVAL (XEXP (x, 2));
5658
5659       /* This should stay within the object being extracted, fail otherwise.  */
5660       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5661         return x;
5662
5663       if (BITS_BIG_ENDIAN)
5664         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5665
5666       break;
5667
5668     default:
5669       return x;
5670     }
5671   /* Convert sign extension to zero extension, if we know that the high
5672      bit is not set, as this is easier to optimize.  It will be converted
5673      back to cheaper alternative in make_extraction.  */
5674   if (GET_CODE (x) == SIGN_EXTEND
5675       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5676           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5677                 & ~(((unsigned HOST_WIDE_INT)
5678                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5679                      >> 1))
5680                == 0)))
5681     {
5682       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5683       rtx temp2 = expand_compound_operation (temp);
5684
5685       /* Make sure this is a profitable operation.  */
5686       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5687        return temp2;
5688       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5689        return temp;
5690       else
5691        return x;
5692     }
5693
5694   /* We can optimize some special cases of ZERO_EXTEND.  */
5695   if (GET_CODE (x) == ZERO_EXTEND)
5696     {
5697       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5698          know that the last value didn't have any inappropriate bits
5699          set.  */
5700       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5701           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5702           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5703           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5704               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5705         return XEXP (XEXP (x, 0), 0);
5706
5707       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5708       if (GET_CODE (XEXP (x, 0)) == SUBREG
5709           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5710           && subreg_lowpart_p (XEXP (x, 0))
5711           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5712           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5713               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5714         return SUBREG_REG (XEXP (x, 0));
5715
5716       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5717          is a comparison and STORE_FLAG_VALUE permits.  This is like
5718          the first case, but it works even when GET_MODE (x) is larger
5719          than HOST_WIDE_INT.  */
5720       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5721           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5722           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5723           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5724               <= HOST_BITS_PER_WIDE_INT)
5725           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5726               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5727         return XEXP (XEXP (x, 0), 0);
5728
5729       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5730       if (GET_CODE (XEXP (x, 0)) == SUBREG
5731           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5732           && subreg_lowpart_p (XEXP (x, 0))
5733           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5734           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5735               <= HOST_BITS_PER_WIDE_INT)
5736           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5737               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5738         return SUBREG_REG (XEXP (x, 0));
5739
5740     }
5741
5742   /* If we reach here, we want to return a pair of shifts.  The inner
5743      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5744      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5745      logical depending on the value of UNSIGNEDP.
5746
5747      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5748      converted into an AND of a shift.
5749
5750      We must check for the case where the left shift would have a negative
5751      count.  This can happen in a case like (x >> 31) & 255 on machines
5752      that can't shift by a constant.  On those machines, we would first
5753      combine the shift with the AND to produce a variable-position
5754      extraction.  Then the constant of 31 would be substituted in to produce
5755      a such a position.  */
5756
5757   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5758   if (modewidth + len >= pos)
5759     {
5760       enum machine_mode mode = GET_MODE (x);
5761       tem = gen_lowpart (mode, XEXP (x, 0));
5762       if (!tem || GET_CODE (tem) == CLOBBER)
5763         return x;
5764       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5765                                   tem, modewidth - pos - len);
5766       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5767                                   mode, tem, modewidth - len);
5768     }
5769   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5770     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5771                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5772                                                         GET_MODE (x),
5773                                                         XEXP (x, 0), pos),
5774                                   ((HOST_WIDE_INT) 1 << len) - 1);
5775   else
5776     /* Any other cases we can't handle.  */
5777     return x;
5778
5779   /* If we couldn't do this for some reason, return the original
5780      expression.  */
5781   if (GET_CODE (tem) == CLOBBER)
5782     return x;
5783
5784   return tem;
5785 }
5786 \f
5787 /* X is a SET which contains an assignment of one object into
5788    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5789    or certain SUBREGS). If possible, convert it into a series of
5790    logical operations.
5791
5792    We half-heartedly support variable positions, but do not at all
5793    support variable lengths.  */
5794
5795 static rtx
5796 expand_field_assignment (rtx x)
5797 {
5798   rtx inner;
5799   rtx pos;                      /* Always counts from low bit.  */
5800   int len;
5801   rtx mask, cleared, masked;
5802   enum machine_mode compute_mode;
5803
5804   /* Loop until we find something we can't simplify.  */
5805   while (1)
5806     {
5807       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5808           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5809         {
5810           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5811           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5812           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5813         }
5814       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5815                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5816         {
5817           inner = XEXP (SET_DEST (x), 0);
5818           len = INTVAL (XEXP (SET_DEST (x), 1));
5819           pos = XEXP (SET_DEST (x), 2);
5820
5821           /* A constant position should stay within the width of INNER.  */
5822           if (GET_CODE (pos) == CONST_INT
5823               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5824             break;
5825
5826           if (BITS_BIG_ENDIAN)
5827             {
5828               if (GET_CODE (pos) == CONST_INT)
5829                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5830                                - INTVAL (pos));
5831               else if (GET_CODE (pos) == MINUS
5832                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5833                        && (INTVAL (XEXP (pos, 1))
5834                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5835                 /* If position is ADJUST - X, new position is X.  */
5836                 pos = XEXP (pos, 0);
5837               else
5838                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5839                                            GEN_INT (GET_MODE_BITSIZE (
5840                                                     GET_MODE (inner))
5841                                                     - len),
5842                                            pos);
5843             }
5844         }
5845
5846       /* A SUBREG between two modes that occupy the same numbers of words
5847          can be done by moving the SUBREG to the source.  */
5848       else if (GET_CODE (SET_DEST (x)) == SUBREG
5849                /* We need SUBREGs to compute nonzero_bits properly.  */
5850                && nonzero_sign_valid
5851                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5852                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5853                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5854                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5855         {
5856           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5857                            gen_lowpart
5858                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5859                             SET_SRC (x)));
5860           continue;
5861         }
5862       else
5863         break;
5864
5865       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5866         inner = SUBREG_REG (inner);
5867
5868       compute_mode = GET_MODE (inner);
5869
5870       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
5871       if (! SCALAR_INT_MODE_P (compute_mode))
5872         {
5873           enum machine_mode imode;
5874
5875           /* Don't do anything for vector or complex integral types.  */
5876           if (! FLOAT_MODE_P (compute_mode))
5877             break;
5878
5879           /* Try to find an integral mode to pun with.  */
5880           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5881           if (imode == BLKmode)
5882             break;
5883
5884           compute_mode = imode;
5885           inner = gen_lowpart (imode, inner);
5886         }
5887
5888       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5889       if (len >= HOST_BITS_PER_WIDE_INT)
5890         break;
5891
5892       /* Now compute the equivalent expression.  Make a copy of INNER
5893          for the SET_DEST in case it is a MEM into which we will substitute;
5894          we don't want shared RTL in that case.  */
5895       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5896       cleared = simplify_gen_binary (AND, compute_mode,
5897                                      simplify_gen_unary (NOT, compute_mode,
5898                                        simplify_gen_binary (ASHIFT,
5899                                                             compute_mode,
5900                                                             mask, pos),
5901                                        compute_mode),
5902                                      inner);
5903       masked = simplify_gen_binary (ASHIFT, compute_mode,
5904                                     simplify_gen_binary (
5905                                       AND, compute_mode,
5906                                       gen_lowpart (compute_mode, SET_SRC (x)),
5907                                       mask),
5908                                     pos);
5909
5910       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5911                        simplify_gen_binary (IOR, compute_mode,
5912                                             cleared, masked));
5913     }
5914
5915   return x;
5916 }
5917 \f
5918 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5919    it is an RTX that represents a variable starting position; otherwise,
5920    POS is the (constant) starting bit position (counted from the LSB).
5921
5922    UNSIGNEDP is nonzero for an unsigned reference and zero for a
5923    signed reference.
5924
5925    IN_DEST is nonzero if this is a reference in the destination of a
5926    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
5927    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5928    be used.
5929
5930    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
5931    ZERO_EXTRACT should be built even for bits starting at bit 0.
5932
5933    MODE is the desired mode of the result (if IN_DEST == 0).
5934
5935    The result is an RTX for the extraction or NULL_RTX if the target
5936    can't handle it.  */
5937
5938 static rtx
5939 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5940                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5941                  int in_dest, int in_compare)
5942 {
5943   /* This mode describes the size of the storage area
5944      to fetch the overall value from.  Within that, we
5945      ignore the POS lowest bits, etc.  */
5946   enum machine_mode is_mode = GET_MODE (inner);
5947   enum machine_mode inner_mode;
5948   enum machine_mode wanted_inner_mode;
5949   enum machine_mode wanted_inner_reg_mode = word_mode;
5950   enum machine_mode pos_mode = word_mode;
5951   enum machine_mode extraction_mode = word_mode;
5952   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5953   rtx new = 0;
5954   rtx orig_pos_rtx = pos_rtx;
5955   HOST_WIDE_INT orig_pos;
5956
5957   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5958     {
5959       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5960          consider just the QI as the memory to extract from.
5961          The subreg adds or removes high bits; its mode is
5962          irrelevant to the meaning of this extraction,
5963          since POS and LEN count from the lsb.  */
5964       if (MEM_P (SUBREG_REG (inner)))
5965         is_mode = GET_MODE (SUBREG_REG (inner));
5966       inner = SUBREG_REG (inner);
5967     }
5968   else if (GET_CODE (inner) == ASHIFT
5969            && GET_CODE (XEXP (inner, 1)) == CONST_INT
5970            && pos_rtx == 0 && pos == 0
5971            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5972     {
5973       /* We're extracting the least significant bits of an rtx
5974          (ashift X (const_int C)), where LEN > C.  Extract the
5975          least significant (LEN - C) bits of X, giving an rtx
5976          whose mode is MODE, then shift it left C times.  */
5977       new = make_extraction (mode, XEXP (inner, 0),
5978                              0, 0, len - INTVAL (XEXP (inner, 1)),
5979                              unsignedp, in_dest, in_compare);
5980       if (new != 0)
5981         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5982     }
5983
5984   inner_mode = GET_MODE (inner);
5985
5986   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5987     pos = INTVAL (pos_rtx), pos_rtx = 0;
5988
5989   /* See if this can be done without an extraction.  We never can if the
5990      width of the field is not the same as that of some integer mode. For
5991      registers, we can only avoid the extraction if the position is at the
5992      low-order bit and this is either not in the destination or we have the
5993      appropriate STRICT_LOW_PART operation available.
5994
5995      For MEM, we can avoid an extract if the field starts on an appropriate
5996      boundary and we can change the mode of the memory reference.  */
5997
5998   if (tmode != BLKmode
5999       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6000            && !MEM_P (inner)
6001            && (inner_mode == tmode
6002                || !REG_P (inner)
6003                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6004                                          GET_MODE_BITSIZE (inner_mode))
6005                || reg_truncated_to_mode (tmode, inner))
6006            && (! in_dest
6007                || (REG_P (inner)
6008                    && have_insn_for (STRICT_LOW_PART, tmode))))
6009           || (MEM_P (inner) && pos_rtx == 0
6010               && (pos
6011                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6012                      : BITS_PER_UNIT)) == 0
6013               /* We can't do this if we are widening INNER_MODE (it
6014                  may not be aligned, for one thing).  */
6015               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6016               && (inner_mode == tmode
6017                   || (! mode_dependent_address_p (XEXP (inner, 0))
6018                       && ! MEM_VOLATILE_P (inner))))))
6019     {
6020       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6021          field.  If the original and current mode are the same, we need not
6022          adjust the offset.  Otherwise, we do if bytes big endian.
6023
6024          If INNER is not a MEM, get a piece consisting of just the field
6025          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6026
6027       if (MEM_P (inner))
6028         {
6029           HOST_WIDE_INT offset;
6030
6031           /* POS counts from lsb, but make OFFSET count in memory order.  */
6032           if (BYTES_BIG_ENDIAN)
6033             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6034           else
6035             offset = pos / BITS_PER_UNIT;
6036
6037           new = adjust_address_nv (inner, tmode, offset);
6038         }
6039       else if (REG_P (inner))
6040         {
6041           if (tmode != inner_mode)
6042             {
6043               /* We can't call gen_lowpart in a DEST since we
6044                  always want a SUBREG (see below) and it would sometimes
6045                  return a new hard register.  */
6046               if (pos || in_dest)
6047                 {
6048                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6049
6050                   if (WORDS_BIG_ENDIAN
6051                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6052                     final_word = ((GET_MODE_SIZE (inner_mode)
6053                                    - GET_MODE_SIZE (tmode))
6054                                   / UNITS_PER_WORD) - final_word;
6055
6056                   final_word *= UNITS_PER_WORD;
6057                   if (BYTES_BIG_ENDIAN &&
6058                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6059                     final_word += (GET_MODE_SIZE (inner_mode)
6060                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6061
6062                   /* Avoid creating invalid subregs, for example when
6063                      simplifying (x>>32)&255.  */
6064                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6065                     return NULL_RTX;
6066
6067                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6068                 }
6069               else
6070                 new = gen_lowpart (tmode, inner);
6071             }
6072           else
6073             new = inner;
6074         }
6075       else
6076         new = force_to_mode (inner, tmode,
6077                              len >= HOST_BITS_PER_WIDE_INT
6078                              ? ~(unsigned HOST_WIDE_INT) 0
6079                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6080                              0);
6081
6082       /* If this extraction is going into the destination of a SET,
6083          make a STRICT_LOW_PART unless we made a MEM.  */
6084
6085       if (in_dest)
6086         return (MEM_P (new) ? new
6087                 : (GET_CODE (new) != SUBREG
6088                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6089                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6090
6091       if (mode == tmode)
6092         return new;
6093
6094       if (GET_CODE (new) == CONST_INT)
6095         return gen_int_mode (INTVAL (new), mode);
6096
6097       /* If we know that no extraneous bits are set, and that the high
6098          bit is not set, convert the extraction to the cheaper of
6099          sign and zero extension, that are equivalent in these cases.  */
6100       if (flag_expensive_optimizations
6101           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6102               && ((nonzero_bits (new, tmode)
6103                    & ~(((unsigned HOST_WIDE_INT)
6104                         GET_MODE_MASK (tmode))
6105                        >> 1))
6106                   == 0)))
6107         {
6108           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6109           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6110
6111           /* Prefer ZERO_EXTENSION, since it gives more information to
6112              backends.  */
6113           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6114             return temp;
6115           return temp1;
6116         }
6117
6118       /* Otherwise, sign- or zero-extend unless we already are in the
6119          proper mode.  */
6120
6121       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6122                              mode, new));
6123     }
6124
6125   /* Unless this is a COMPARE or we have a funny memory reference,
6126      don't do anything with zero-extending field extracts starting at
6127      the low-order bit since they are simple AND operations.  */
6128   if (pos_rtx == 0 && pos == 0 && ! in_dest
6129       && ! in_compare && unsignedp)
6130     return 0;
6131
6132   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6133      if the position is not a constant and the length is not 1.  In all
6134      other cases, we would only be going outside our object in cases when
6135      an original shift would have been undefined.  */
6136   if (MEM_P (inner)
6137       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6138           || (pos_rtx != 0 && len != 1)))
6139     return 0;
6140
6141   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6142      and the mode for the result.  */
6143   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6144     {
6145       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6146       pos_mode = mode_for_extraction (EP_insv, 2);
6147       extraction_mode = mode_for_extraction (EP_insv, 3);
6148     }
6149
6150   if (! in_dest && unsignedp
6151       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6152     {
6153       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6154       pos_mode = mode_for_extraction (EP_extzv, 3);
6155       extraction_mode = mode_for_extraction (EP_extzv, 0);
6156     }
6157
6158   if (! in_dest && ! unsignedp
6159       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6160     {
6161       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6162       pos_mode = mode_for_extraction (EP_extv, 3);
6163       extraction_mode = mode_for_extraction (EP_extv, 0);
6164     }
6165
6166   /* Never narrow an object, since that might not be safe.  */
6167
6168   if (mode != VOIDmode
6169       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6170     extraction_mode = mode;
6171
6172   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6173       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6174     pos_mode = GET_MODE (pos_rtx);
6175
6176   /* If this is not from memory, the desired mode is the preferred mode
6177      for an extraction pattern's first input operand, or word_mode if there
6178      is none.  */
6179   if (!MEM_P (inner))
6180     wanted_inner_mode = wanted_inner_reg_mode;
6181   else
6182     {
6183       /* Be careful not to go beyond the extracted object and maintain the
6184          natural alignment of the memory.  */
6185       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6186       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6187              > GET_MODE_BITSIZE (wanted_inner_mode))
6188         {
6189           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6190           gcc_assert (wanted_inner_mode != VOIDmode);
6191         }
6192
6193       /* If we have to change the mode of memory and cannot, the desired mode
6194          is EXTRACTION_MODE.  */
6195       if (inner_mode != wanted_inner_mode
6196           && (mode_dependent_address_p (XEXP (inner, 0))
6197               || MEM_VOLATILE_P (inner)
6198               || pos_rtx))
6199         wanted_inner_mode = extraction_mode;
6200     }
6201
6202   orig_pos = pos;
6203
6204   if (BITS_BIG_ENDIAN)
6205     {
6206       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6207          BITS_BIG_ENDIAN style.  If position is constant, compute new
6208          position.  Otherwise, build subtraction.
6209          Note that POS is relative to the mode of the original argument.
6210          If it's a MEM we need to recompute POS relative to that.
6211          However, if we're extracting from (or inserting into) a register,
6212          we want to recompute POS relative to wanted_inner_mode.  */
6213       int width = (MEM_P (inner)
6214                    ? GET_MODE_BITSIZE (is_mode)
6215                    : GET_MODE_BITSIZE (wanted_inner_mode));
6216
6217       if (pos_rtx == 0)
6218         pos = width - len - pos;
6219       else
6220         pos_rtx
6221           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6222       /* POS may be less than 0 now, but we check for that below.
6223          Note that it can only be less than 0 if !MEM_P (inner).  */
6224     }
6225
6226   /* If INNER has a wider mode, and this is a constant extraction, try to
6227      make it smaller and adjust the byte to point to the byte containing
6228      the value.  */
6229   if (wanted_inner_mode != VOIDmode
6230       && inner_mode != wanted_inner_mode
6231       && ! pos_rtx
6232       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6233       && MEM_P (inner)
6234       && ! mode_dependent_address_p (XEXP (inner, 0))
6235       && ! MEM_VOLATILE_P (inner))
6236     {
6237       int offset = 0;
6238
6239       /* The computations below will be correct if the machine is big
6240          endian in both bits and bytes or little endian in bits and bytes.
6241          If it is mixed, we must adjust.  */
6242
6243       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6244          adjust OFFSET to compensate.  */
6245       if (BYTES_BIG_ENDIAN
6246           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6247         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6248
6249       /* We can now move to the desired byte.  */
6250       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6251                 * GET_MODE_SIZE (wanted_inner_mode);
6252       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6253
6254       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6255           && is_mode != wanted_inner_mode)
6256         offset = (GET_MODE_SIZE (is_mode)
6257                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6258
6259       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6260     }
6261
6262   /* If INNER is not memory, we can always get it into the proper mode.  If we
6263      are changing its mode, POS must be a constant and smaller than the size
6264      of the new mode.  */
6265   else if (!MEM_P (inner))
6266     {
6267       if (GET_MODE (inner) != wanted_inner_mode
6268           && (pos_rtx != 0
6269               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6270         return 0;
6271
6272       if (orig_pos < 0)
6273         return 0;
6274
6275       inner = force_to_mode (inner, wanted_inner_mode,
6276                              pos_rtx
6277                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6278                              ? ~(unsigned HOST_WIDE_INT) 0
6279                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6280                                 << orig_pos),
6281                              0);
6282     }
6283
6284   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6285      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6286   if (pos_rtx != 0
6287       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6288     {
6289       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6290
6291       /* If we know that no extraneous bits are set, and that the high
6292          bit is not set, convert extraction to cheaper one - either
6293          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6294          cases.  */
6295       if (flag_expensive_optimizations
6296           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6297               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6298                    & ~(((unsigned HOST_WIDE_INT)
6299                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6300                        >> 1))
6301                   == 0)))
6302         {
6303           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6304
6305           /* Prefer ZERO_EXTENSION, since it gives more information to
6306              backends.  */
6307           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6308             temp = temp1;
6309         }
6310       pos_rtx = temp;
6311     }
6312   else if (pos_rtx != 0
6313            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6314     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6315
6316   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6317      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6318      be a CONST_INT.  */
6319   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6320     pos_rtx = orig_pos_rtx;
6321
6322   else if (pos_rtx == 0)
6323     pos_rtx = GEN_INT (pos);
6324
6325   /* Make the required operation.  See if we can use existing rtx.  */
6326   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6327                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6328   if (! in_dest)
6329     new = gen_lowpart (mode, new);
6330
6331   return new;
6332 }
6333 \f
6334 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6335    with any other operations in X.  Return X without that shift if so.  */
6336
6337 static rtx
6338 extract_left_shift (rtx x, int count)
6339 {
6340   enum rtx_code code = GET_CODE (x);
6341   enum machine_mode mode = GET_MODE (x);
6342   rtx tem;
6343
6344   switch (code)
6345     {
6346     case ASHIFT:
6347       /* This is the shift itself.  If it is wide enough, we will return
6348          either the value being shifted if the shift count is equal to
6349          COUNT or a shift for the difference.  */
6350       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6351           && INTVAL (XEXP (x, 1)) >= count)
6352         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6353                                      INTVAL (XEXP (x, 1)) - count);
6354       break;
6355
6356     case NEG:  case NOT:
6357       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6358         return simplify_gen_unary (code, mode, tem, mode);
6359
6360       break;
6361
6362     case PLUS:  case IOR:  case XOR:  case AND:
6363       /* If we can safely shift this constant and we find the inner shift,
6364          make a new operation.  */
6365       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6366           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6367           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6368         return simplify_gen_binary (code, mode, tem,
6369                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6370
6371       break;
6372
6373     default:
6374       break;
6375     }
6376
6377   return 0;
6378 }
6379 \f
6380 /* Look at the expression rooted at X.  Look for expressions
6381    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6382    Form these expressions.
6383
6384    Return the new rtx, usually just X.
6385
6386    Also, for machines like the VAX that don't have logical shift insns,
6387    try to convert logical to arithmetic shift operations in cases where
6388    they are equivalent.  This undoes the canonicalizations to logical
6389    shifts done elsewhere.
6390
6391    We try, as much as possible, to re-use rtl expressions to save memory.
6392
6393    IN_CODE says what kind of expression we are processing.  Normally, it is
6394    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6395    being kludges), it is MEM.  When processing the arguments of a comparison
6396    or a COMPARE against zero, it is COMPARE.  */
6397
6398 static rtx
6399 make_compound_operation (rtx x, enum rtx_code in_code)
6400 {
6401   enum rtx_code code = GET_CODE (x);
6402   enum machine_mode mode = GET_MODE (x);
6403   int mode_width = GET_MODE_BITSIZE (mode);
6404   rtx rhs, lhs;
6405   enum rtx_code next_code;
6406   int i;
6407   rtx new = 0;
6408   rtx tem;
6409   const char *fmt;
6410
6411   /* Select the code to be used in recursive calls.  Once we are inside an
6412      address, we stay there.  If we have a comparison, set to COMPARE,
6413      but once inside, go back to our default of SET.  */
6414
6415   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6416                : ((code == COMPARE || COMPARISON_P (x))
6417                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6418                : in_code == COMPARE ? SET : in_code);
6419
6420   /* Process depending on the code of this operation.  If NEW is set
6421      nonzero, it will be returned.  */
6422
6423   switch (code)
6424     {
6425     case ASHIFT:
6426       /* Convert shifts by constants into multiplications if inside
6427          an address.  */
6428       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6429           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6430           && INTVAL (XEXP (x, 1)) >= 0)
6431         {
6432           new = make_compound_operation (XEXP (x, 0), next_code);
6433           new = gen_rtx_MULT (mode, new,
6434                               GEN_INT ((HOST_WIDE_INT) 1
6435                                        << INTVAL (XEXP (x, 1))));
6436         }
6437       break;
6438
6439     case AND:
6440       /* If the second operand is not a constant, we can't do anything
6441          with it.  */
6442       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6443         break;
6444
6445       /* If the constant is a power of two minus one and the first operand
6446          is a logical right shift, make an extraction.  */
6447       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6448           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6449         {
6450           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6451           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6452                                  0, in_code == COMPARE);
6453         }
6454
6455       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6456       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6457                && subreg_lowpart_p (XEXP (x, 0))
6458                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6459                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6460         {
6461           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6462                                          next_code);
6463           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6464                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6465                                  0, in_code == COMPARE);
6466         }
6467       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6468       else if ((GET_CODE (XEXP (x, 0)) == XOR
6469                 || GET_CODE (XEXP (x, 0)) == IOR)
6470                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6471                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6472                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6473         {
6474           /* Apply the distributive law, and then try to make extractions.  */
6475           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6476                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6477                                              XEXP (x, 1)),
6478                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6479                                              XEXP (x, 1)));
6480           new = make_compound_operation (new, in_code);
6481         }
6482
6483       /* If we are have (and (rotate X C) M) and C is larger than the number
6484          of bits in M, this is an extraction.  */
6485
6486       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6487                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6488                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6489                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6490         {
6491           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6492           new = make_extraction (mode, new,
6493                                  (GET_MODE_BITSIZE (mode)
6494                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6495                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6496         }
6497
6498       /* On machines without logical shifts, if the operand of the AND is
6499          a logical shift and our mask turns off all the propagated sign
6500          bits, we can replace the logical shift with an arithmetic shift.  */
6501       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6502                && !have_insn_for (LSHIFTRT, mode)
6503                && have_insn_for (ASHIFTRT, mode)
6504                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6505                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6506                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6507                && mode_width <= HOST_BITS_PER_WIDE_INT)
6508         {
6509           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6510
6511           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6512           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6513             SUBST (XEXP (x, 0),
6514                    gen_rtx_ASHIFTRT (mode,
6515                                      make_compound_operation
6516                                      (XEXP (XEXP (x, 0), 0), next_code),
6517                                      XEXP (XEXP (x, 0), 1)));
6518         }
6519
6520       /* If the constant is one less than a power of two, this might be
6521          representable by an extraction even if no shift is present.
6522          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6523          we are in a COMPARE.  */
6524       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6525         new = make_extraction (mode,
6526                                make_compound_operation (XEXP (x, 0),
6527                                                         next_code),
6528                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6529
6530       /* If we are in a comparison and this is an AND with a power of two,
6531          convert this into the appropriate bit extract.  */
6532       else if (in_code == COMPARE
6533                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6534         new = make_extraction (mode,
6535                                make_compound_operation (XEXP (x, 0),
6536                                                         next_code),
6537                                i, NULL_RTX, 1, 1, 0, 1);
6538
6539       break;
6540
6541     case LSHIFTRT:
6542       /* If the sign bit is known to be zero, replace this with an
6543          arithmetic shift.  */
6544       if (have_insn_for (ASHIFTRT, mode)
6545           && ! have_insn_for (LSHIFTRT, mode)
6546           && mode_width <= HOST_BITS_PER_WIDE_INT
6547           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6548         {
6549           new = gen_rtx_ASHIFTRT (mode,
6550                                   make_compound_operation (XEXP (x, 0),
6551                                                            next_code),
6552                                   XEXP (x, 1));
6553           break;
6554         }
6555
6556       /* ... fall through ...  */
6557
6558     case ASHIFTRT:
6559       lhs = XEXP (x, 0);
6560       rhs = XEXP (x, 1);
6561
6562       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6563          this is a SIGN_EXTRACT.  */
6564       if (GET_CODE (rhs) == CONST_INT
6565           && GET_CODE (lhs) == ASHIFT
6566           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6567           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6568         {
6569           new = make_compound_operation (XEXP (lhs, 0), next_code);
6570           new = make_extraction (mode, new,
6571                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6572                                  NULL_RTX, mode_width - INTVAL (rhs),
6573                                  code == LSHIFTRT, 0, in_code == COMPARE);
6574           break;
6575         }
6576
6577       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6578          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6579          also do this for some cases of SIGN_EXTRACT, but it doesn't
6580          seem worth the effort; the case checked for occurs on Alpha.  */
6581
6582       if (!OBJECT_P (lhs)
6583           && ! (GET_CODE (lhs) == SUBREG
6584                 && (OBJECT_P (SUBREG_REG (lhs))))
6585           && GET_CODE (rhs) == CONST_INT
6586           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6587           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6588         new = make_extraction (mode, make_compound_operation (new, next_code),
6589                                0, NULL_RTX, mode_width - INTVAL (rhs),
6590                                code == LSHIFTRT, 0, in_code == COMPARE);
6591
6592       break;
6593
6594     case SUBREG:
6595       /* Call ourselves recursively on the inner expression.  If we are
6596          narrowing the object and it has a different RTL code from
6597          what it originally did, do this SUBREG as a force_to_mode.  */
6598
6599       tem = make_compound_operation (SUBREG_REG (x), in_code);
6600
6601       {
6602         rtx simplified;
6603         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6604                                       SUBREG_BYTE (x));
6605
6606         if (simplified)
6607           tem = simplified;
6608
6609         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6610             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6611             && subreg_lowpart_p (x))
6612           {
6613             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6614                                        0);
6615
6616             /* If we have something other than a SUBREG, we might have
6617                done an expansion, so rerun ourselves.  */
6618             if (GET_CODE (newer) != SUBREG)
6619               newer = make_compound_operation (newer, in_code);
6620
6621             return newer;
6622           }
6623
6624         if (simplified)
6625           return tem;
6626       }
6627       break;
6628
6629     default:
6630       break;
6631     }
6632
6633   if (new)
6634     {
6635       x = gen_lowpart (mode, new);
6636       code = GET_CODE (x);
6637     }
6638
6639   /* Now recursively process each operand of this operation.  */
6640   fmt = GET_RTX_FORMAT (code);
6641   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6642     if (fmt[i] == 'e')
6643       {
6644         new = make_compound_operation (XEXP (x, i), next_code);
6645         SUBST (XEXP (x, i), new);
6646       }
6647
6648   /* If this is a commutative operation, the changes to the operands
6649      may have made it noncanonical.  */
6650   if (COMMUTATIVE_ARITH_P (x)
6651       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6652     {
6653       tem = XEXP (x, 0);
6654       SUBST (XEXP (x, 0), XEXP (x, 1));
6655       SUBST (XEXP (x, 1), tem);
6656     }
6657
6658   return x;
6659 }
6660 \f
6661 /* Given M see if it is a value that would select a field of bits
6662    within an item, but not the entire word.  Return -1 if not.
6663    Otherwise, return the starting position of the field, where 0 is the
6664    low-order bit.
6665
6666    *PLEN is set to the length of the field.  */
6667
6668 static int
6669 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6670 {
6671   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6672   int pos = exact_log2 (m & -m);
6673   int len = 0;
6674
6675   if (pos >= 0)
6676     /* Now shift off the low-order zero bits and see if we have a
6677        power of two minus 1.  */
6678     len = exact_log2 ((m >> pos) + 1);
6679
6680   if (len <= 0)
6681     pos = -1;
6682
6683   *plen = len;
6684   return pos;
6685 }
6686 \f
6687 /* If X refers to a register that equals REG in value, replace these
6688    references with REG.  */
6689 static rtx
6690 canon_reg_for_combine (rtx x, rtx reg)
6691 {
6692   rtx op0, op1, op2;
6693   const char *fmt;
6694   int i;
6695   bool copied;
6696
6697   enum rtx_code code = GET_CODE (x);
6698   switch (GET_RTX_CLASS (code))
6699     {
6700     case RTX_UNARY:
6701       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6702       if (op0 != XEXP (x, 0))
6703         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6704                                    GET_MODE (reg));
6705       break;
6706
6707     case RTX_BIN_ARITH:
6708     case RTX_COMM_ARITH:
6709       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6710       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6711       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6712         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6713       break;
6714
6715     case RTX_COMPARE:
6716     case RTX_COMM_COMPARE:
6717       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6718       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6719       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6720         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6721                                         GET_MODE (op0), op0, op1);
6722       break;
6723
6724     case RTX_TERNARY:
6725     case RTX_BITFIELD_OPS:
6726       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6727       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6728       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6729       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6730         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6731                                      GET_MODE (op0), op0, op1, op2);
6732
6733     case RTX_OBJ:
6734       if (REG_P (x))
6735         {
6736           if (rtx_equal_p (get_last_value (reg), x)
6737               || rtx_equal_p (reg, get_last_value (x)))
6738             return reg;
6739           else
6740             break;
6741         }
6742
6743       /* fall through */
6744
6745     default:
6746       fmt = GET_RTX_FORMAT (code);
6747       copied = false;
6748       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6749         if (fmt[i] == 'e')
6750           {
6751             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6752             if (op != XEXP (x, i))
6753               {
6754                 if (!copied)
6755                   {
6756                     copied = true;
6757                     x = copy_rtx (x);
6758                   }
6759                 XEXP (x, i) = op;
6760               }
6761           }
6762         else if (fmt[i] == 'E')
6763           {
6764             int j;
6765             for (j = 0; j < XVECLEN (x, i); j++)
6766               {
6767                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6768                 if (op != XVECEXP (x, i, j))
6769                   {
6770                     if (!copied)
6771                       {
6772                         copied = true;
6773                         x = copy_rtx (x);
6774                       }
6775                     XVECEXP (x, i, j) = op;
6776                   }
6777               }
6778           }
6779
6780       break;
6781     }
6782
6783   return x;
6784 }
6785
6786 /* Return X converted to MODE.  If the value is already truncated to
6787    MODE we can just return a subreg even though in the general case we
6788    would need an explicit truncation.  */
6789
6790 static rtx
6791 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6792 {
6793   if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6794       || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6795                                 GET_MODE_BITSIZE (GET_MODE (x)))
6796       || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6797     return gen_lowpart (mode, x);
6798   else
6799     return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
6800 }
6801
6802 /* See if X can be simplified knowing that we will only refer to it in
6803    MODE and will only refer to those bits that are nonzero in MASK.
6804    If other bits are being computed or if masking operations are done
6805    that select a superset of the bits in MASK, they can sometimes be
6806    ignored.
6807
6808    Return a possibly simplified expression, but always convert X to
6809    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6810
6811    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6812    are all off in X.  This is used when X will be complemented, by either
6813    NOT, NEG, or XOR.  */
6814
6815 static rtx
6816 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6817                int just_select)
6818 {
6819   enum rtx_code code = GET_CODE (x);
6820   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6821   enum machine_mode op_mode;
6822   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6823   rtx op0, op1, temp;
6824
6825   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6826      code below will do the wrong thing since the mode of such an
6827      expression is VOIDmode.
6828
6829      Also do nothing if X is a CLOBBER; this can happen if X was
6830      the return value from a call to gen_lowpart.  */
6831   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6832     return x;
6833
6834   /* We want to perform the operation is its present mode unless we know
6835      that the operation is valid in MODE, in which case we do the operation
6836      in MODE.  */
6837   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6838               && have_insn_for (code, mode))
6839              ? mode : GET_MODE (x));
6840
6841   /* It is not valid to do a right-shift in a narrower mode
6842      than the one it came in with.  */
6843   if ((code == LSHIFTRT || code == ASHIFTRT)
6844       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6845     op_mode = GET_MODE (x);
6846
6847   /* Truncate MASK to fit OP_MODE.  */
6848   if (op_mode)
6849     mask &= GET_MODE_MASK (op_mode);
6850
6851   /* When we have an arithmetic operation, or a shift whose count we
6852      do not know, we need to assume that all bits up to the highest-order
6853      bit in MASK will be needed.  This is how we form such a mask.  */
6854   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6855     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6856   else
6857     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6858                    - 1);
6859
6860   /* Determine what bits of X are guaranteed to be (non)zero.  */
6861   nonzero = nonzero_bits (x, mode);
6862
6863   /* If none of the bits in X are needed, return a zero.  */
6864   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
6865     x = const0_rtx;
6866
6867   /* If X is a CONST_INT, return a new one.  Do this here since the
6868      test below will fail.  */
6869   if (GET_CODE (x) == CONST_INT)
6870     {
6871       if (SCALAR_INT_MODE_P (mode))
6872         return gen_int_mode (INTVAL (x) & mask, mode);
6873       else
6874         {
6875           x = GEN_INT (INTVAL (x) & mask);
6876           return gen_lowpart_common (mode, x);
6877         }
6878     }
6879
6880   /* If X is narrower than MODE and we want all the bits in X's mode, just
6881      get X in the proper mode.  */
6882   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6883       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6884     return gen_lowpart (mode, x);
6885
6886   switch (code)
6887     {
6888     case CLOBBER:
6889       /* If X is a (clobber (const_int)), return it since we know we are
6890          generating something that won't match.  */
6891       return x;
6892
6893     case SIGN_EXTEND:
6894     case ZERO_EXTEND:
6895     case ZERO_EXTRACT:
6896     case SIGN_EXTRACT:
6897       x = expand_compound_operation (x);
6898       if (GET_CODE (x) != code)
6899         return force_to_mode (x, mode, mask, next_select);
6900       break;
6901
6902     case SUBREG:
6903       if (subreg_lowpart_p (x)
6904           /* We can ignore the effect of this SUBREG if it narrows the mode or
6905              if the constant masks to zero all the bits the mode doesn't
6906              have.  */
6907           && ((GET_MODE_SIZE (GET_MODE (x))
6908                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6909               || (0 == (mask
6910                         & GET_MODE_MASK (GET_MODE (x))
6911                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6912         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6913       break;
6914
6915     case AND:
6916       /* If this is an AND with a constant, convert it into an AND
6917          whose constant is the AND of that constant with MASK.  If it
6918          remains an AND of MASK, delete it since it is redundant.  */
6919
6920       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6921         {
6922           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6923                                       mask & INTVAL (XEXP (x, 1)));
6924
6925           /* If X is still an AND, see if it is an AND with a mask that
6926              is just some low-order bits.  If so, and it is MASK, we don't
6927              need it.  */
6928
6929           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6930               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6931                   == mask))
6932             x = XEXP (x, 0);
6933
6934           /* If it remains an AND, try making another AND with the bits
6935              in the mode mask that aren't in MASK turned on.  If the
6936              constant in the AND is wide enough, this might make a
6937              cheaper constant.  */
6938
6939           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6940               && GET_MODE_MASK (GET_MODE (x)) != mask
6941               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6942             {
6943               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6944                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6945               int width = GET_MODE_BITSIZE (GET_MODE (x));
6946               rtx y;
6947
6948               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6949                  number, sign extend it.  */
6950               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6951                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6952                 cval |= (HOST_WIDE_INT) -1 << width;
6953
6954               y = simplify_gen_binary (AND, GET_MODE (x),
6955                                        XEXP (x, 0), GEN_INT (cval));
6956               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6957                 x = y;
6958             }
6959
6960           break;
6961         }
6962
6963       goto binop;
6964
6965     case PLUS:
6966       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6967          low-order bits (as in an alignment operation) and FOO is already
6968          aligned to that boundary, mask C1 to that boundary as well.
6969          This may eliminate that PLUS and, later, the AND.  */
6970
6971       {
6972         unsigned int width = GET_MODE_BITSIZE (mode);
6973         unsigned HOST_WIDE_INT smask = mask;
6974
6975         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6976            number, sign extend it.  */
6977
6978         if (width < HOST_BITS_PER_WIDE_INT
6979             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6980           smask |= (HOST_WIDE_INT) -1 << width;
6981
6982         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6983             && exact_log2 (- smask) >= 0
6984             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6985             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6986           return force_to_mode (plus_constant (XEXP (x, 0),
6987                                                (INTVAL (XEXP (x, 1)) & smask)),
6988                                 mode, smask, next_select);
6989       }
6990
6991       /* ... fall through ...  */
6992
6993     case MULT:
6994       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6995          most significant bit in MASK since carries from those bits will
6996          affect the bits we are interested in.  */
6997       mask = fuller_mask;
6998       goto binop;
6999
7000     case MINUS:
7001       /* If X is (minus C Y) where C's least set bit is larger than any bit
7002          in the mask, then we may replace with (neg Y).  */
7003       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7004           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7005                                         & -INTVAL (XEXP (x, 0))))
7006               > mask))
7007         {
7008           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7009                                   GET_MODE (x));
7010           return force_to_mode (x, mode, mask, next_select);
7011         }
7012
7013       /* Similarly, if C contains every bit in the fuller_mask, then we may
7014          replace with (not Y).  */
7015       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7016           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7017               == INTVAL (XEXP (x, 0))))
7018         {
7019           x = simplify_gen_unary (NOT, GET_MODE (x),
7020                                   XEXP (x, 1), GET_MODE (x));
7021           return force_to_mode (x, mode, mask, next_select);
7022         }
7023
7024       mask = fuller_mask;
7025       goto binop;
7026
7027     case IOR:
7028     case XOR:
7029       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7030          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7031          operation which may be a bitfield extraction.  Ensure that the
7032          constant we form is not wider than the mode of X.  */
7033
7034       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7035           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7036           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7037           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7038           && GET_CODE (XEXP (x, 1)) == CONST_INT
7039           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7040                + floor_log2 (INTVAL (XEXP (x, 1))))
7041               < GET_MODE_BITSIZE (GET_MODE (x)))
7042           && (INTVAL (XEXP (x, 1))
7043               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7044         {
7045           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7046                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7047           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7048                                       XEXP (XEXP (x, 0), 0), temp);
7049           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7050                                    XEXP (XEXP (x, 0), 1));
7051           return force_to_mode (x, mode, mask, next_select);
7052         }
7053
7054     binop:
7055       /* For most binary operations, just propagate into the operation and
7056          change the mode if we have an operation of that mode.  */
7057
7058       op0 = gen_lowpart_or_truncate (op_mode,
7059                                      force_to_mode (XEXP (x, 0), mode, mask,
7060                                                     next_select));
7061       op1 = gen_lowpart_or_truncate (op_mode,
7062                                      force_to_mode (XEXP (x, 1), mode, mask,
7063                                         next_select));
7064
7065       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7066         x = simplify_gen_binary (code, op_mode, op0, op1);
7067       break;
7068
7069     case ASHIFT:
7070       /* For left shifts, do the same, but just for the first operand.
7071          However, we cannot do anything with shifts where we cannot
7072          guarantee that the counts are smaller than the size of the mode
7073          because such a count will have a different meaning in a
7074          wider mode.  */
7075
7076       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7077              && INTVAL (XEXP (x, 1)) >= 0
7078              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7079           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7080                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7081                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7082         break;
7083
7084       /* If the shift count is a constant and we can do arithmetic in
7085          the mode of the shift, refine which bits we need.  Otherwise, use the
7086          conservative form of the mask.  */
7087       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7088           && INTVAL (XEXP (x, 1)) >= 0
7089           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7090           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7091         mask >>= INTVAL (XEXP (x, 1));
7092       else
7093         mask = fuller_mask;
7094
7095       op0 = gen_lowpart_or_truncate (op_mode,
7096                                      force_to_mode (XEXP (x, 0), op_mode,
7097                                                     mask, next_select));
7098
7099       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7100         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7101       break;
7102
7103     case LSHIFTRT:
7104       /* Here we can only do something if the shift count is a constant,
7105          this shift constant is valid for the host, and we can do arithmetic
7106          in OP_MODE.  */
7107
7108       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7109           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7110           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7111         {
7112           rtx inner = XEXP (x, 0);
7113           unsigned HOST_WIDE_INT inner_mask;
7114
7115           /* Select the mask of the bits we need for the shift operand.  */
7116           inner_mask = mask << INTVAL (XEXP (x, 1));
7117
7118           /* We can only change the mode of the shift if we can do arithmetic
7119              in the mode of the shift and INNER_MASK is no wider than the
7120              width of X's mode.  */
7121           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7122             op_mode = GET_MODE (x);
7123
7124           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7125
7126           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7127             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7128         }
7129
7130       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7131          shift and AND produces only copies of the sign bit (C2 is one less
7132          than a power of two), we can do this with just a shift.  */
7133
7134       if (GET_CODE (x) == LSHIFTRT
7135           && GET_CODE (XEXP (x, 1)) == CONST_INT
7136           /* The shift puts one of the sign bit copies in the least significant
7137              bit.  */
7138           && ((INTVAL (XEXP (x, 1))
7139                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7140               >= GET_MODE_BITSIZE (GET_MODE (x)))
7141           && exact_log2 (mask + 1) >= 0
7142           /* Number of bits left after the shift must be more than the mask
7143              needs.  */
7144           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7145               <= GET_MODE_BITSIZE (GET_MODE (x)))
7146           /* Must be more sign bit copies than the mask needs.  */
7147           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7148               >= exact_log2 (mask + 1)))
7149         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7150                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7151                                           - exact_log2 (mask + 1)));
7152
7153       goto shiftrt;
7154
7155     case ASHIFTRT:
7156       /* If we are just looking for the sign bit, we don't need this shift at
7157          all, even if it has a variable count.  */
7158       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7159           && (mask == ((unsigned HOST_WIDE_INT) 1
7160                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7161         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7162
7163       /* If this is a shift by a constant, get a mask that contains those bits
7164          that are not copies of the sign bit.  We then have two cases:  If
7165          MASK only includes those bits, this can be a logical shift, which may
7166          allow simplifications.  If MASK is a single-bit field not within
7167          those bits, we are requesting a copy of the sign bit and hence can
7168          shift the sign bit to the appropriate location.  */
7169
7170       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7171           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7172         {
7173           int i;
7174
7175           /* If the considered data is wider than HOST_WIDE_INT, we can't
7176              represent a mask for all its bits in a single scalar.
7177              But we only care about the lower bits, so calculate these.  */
7178
7179           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7180             {
7181               nonzero = ~(HOST_WIDE_INT) 0;
7182
7183               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7184                  is the number of bits a full-width mask would have set.
7185                  We need only shift if these are fewer than nonzero can
7186                  hold.  If not, we must keep all bits set in nonzero.  */
7187
7188               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7189                   < HOST_BITS_PER_WIDE_INT)
7190                 nonzero >>= INTVAL (XEXP (x, 1))
7191                             + HOST_BITS_PER_WIDE_INT
7192                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7193             }
7194           else
7195             {
7196               nonzero = GET_MODE_MASK (GET_MODE (x));
7197               nonzero >>= INTVAL (XEXP (x, 1));
7198             }
7199
7200           if ((mask & ~nonzero) == 0)
7201             {
7202               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7203                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7204               if (GET_CODE (x) != ASHIFTRT)
7205                 return force_to_mode (x, mode, mask, next_select);
7206             }
7207
7208           else if ((i = exact_log2 (mask)) >= 0)
7209             {
7210               x = simplify_shift_const
7211                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7212                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7213
7214               if (GET_CODE (x) != ASHIFTRT)
7215                 return force_to_mode (x, mode, mask, next_select);
7216             }
7217         }
7218
7219       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7220          even if the shift count isn't a constant.  */
7221       if (mask == 1)
7222         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7223                                  XEXP (x, 0), XEXP (x, 1));
7224
7225     shiftrt:
7226
7227       /* If this is a zero- or sign-extension operation that just affects bits
7228          we don't care about, remove it.  Be sure the call above returned
7229          something that is still a shift.  */
7230
7231       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7232           && GET_CODE (XEXP (x, 1)) == CONST_INT
7233           && INTVAL (XEXP (x, 1)) >= 0
7234           && (INTVAL (XEXP (x, 1))
7235               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7236           && GET_CODE (XEXP (x, 0)) == ASHIFT
7237           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7238         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7239                               next_select);
7240
7241       break;
7242
7243     case ROTATE:
7244     case ROTATERT:
7245       /* If the shift count is constant and we can do computations
7246          in the mode of X, compute where the bits we care about are.
7247          Otherwise, we can't do anything.  Don't change the mode of
7248          the shift or propagate MODE into the shift, though.  */
7249       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7250           && INTVAL (XEXP (x, 1)) >= 0)
7251         {
7252           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7253                                             GET_MODE (x), GEN_INT (mask),
7254                                             XEXP (x, 1));
7255           if (temp && GET_CODE (temp) == CONST_INT)
7256             SUBST (XEXP (x, 0),
7257                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7258                                   INTVAL (temp), next_select));
7259         }
7260       break;
7261
7262     case NEG:
7263       /* If we just want the low-order bit, the NEG isn't needed since it
7264          won't change the low-order bit.  */
7265       if (mask == 1)
7266         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7267
7268       /* We need any bits less significant than the most significant bit in
7269          MASK since carries from those bits will affect the bits we are
7270          interested in.  */
7271       mask = fuller_mask;
7272       goto unop;
7273
7274     case NOT:
7275       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7276          same as the XOR case above.  Ensure that the constant we form is not
7277          wider than the mode of X.  */
7278
7279       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7280           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7281           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7282           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7283               < GET_MODE_BITSIZE (GET_MODE (x)))
7284           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7285         {
7286           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7287                                GET_MODE (x));
7288           temp = simplify_gen_binary (XOR, GET_MODE (x),
7289                                       XEXP (XEXP (x, 0), 0), temp);
7290           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7291                                    temp, XEXP (XEXP (x, 0), 1));
7292
7293           return force_to_mode (x, mode, mask, next_select);
7294         }
7295
7296       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7297          use the full mask inside the NOT.  */
7298       mask = fuller_mask;
7299
7300     unop:
7301       op0 = gen_lowpart_or_truncate (op_mode,
7302                                      force_to_mode (XEXP (x, 0), mode, mask,
7303                                                     next_select));
7304       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7305         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7306       break;
7307
7308     case NE:
7309       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7310          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7311          which is equal to STORE_FLAG_VALUE.  */
7312       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7313           && GET_MODE (XEXP (x, 0)) == mode
7314           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7315           && (nonzero_bits (XEXP (x, 0), mode)
7316               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7317         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7318
7319       break;
7320
7321     case IF_THEN_ELSE:
7322       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7323          written in a narrower mode.  We play it safe and do not do so.  */
7324
7325       SUBST (XEXP (x, 1),
7326              gen_lowpart_or_truncate (GET_MODE (x),
7327                                       force_to_mode (XEXP (x, 1), mode,
7328                                                      mask, next_select)));
7329       SUBST (XEXP (x, 2),
7330              gen_lowpart_or_truncate (GET_MODE (x),
7331                                       force_to_mode (XEXP (x, 2), mode,
7332                                                      mask, next_select)));
7333       break;
7334
7335     default:
7336       break;
7337     }
7338
7339   /* Ensure we return a value of the proper mode.  */
7340   return gen_lowpart_or_truncate (mode, x);
7341 }
7342 \f
7343 /* Return nonzero if X is an expression that has one of two values depending on
7344    whether some other value is zero or nonzero.  In that case, we return the
7345    value that is being tested, *PTRUE is set to the value if the rtx being
7346    returned has a nonzero value, and *PFALSE is set to the other alternative.
7347
7348    If we return zero, we set *PTRUE and *PFALSE to X.  */
7349
7350 static rtx
7351 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7352 {
7353   enum machine_mode mode = GET_MODE (x);
7354   enum rtx_code code = GET_CODE (x);
7355   rtx cond0, cond1, true0, true1, false0, false1;
7356   unsigned HOST_WIDE_INT nz;
7357
7358   /* If we are comparing a value against zero, we are done.  */
7359   if ((code == NE || code == EQ)
7360       && XEXP (x, 1) == const0_rtx)
7361     {
7362       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7363       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7364       return XEXP (x, 0);
7365     }
7366
7367   /* If this is a unary operation whose operand has one of two values, apply
7368      our opcode to compute those values.  */
7369   else if (UNARY_P (x)
7370            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7371     {
7372       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7373       *pfalse = simplify_gen_unary (code, mode, false0,
7374                                     GET_MODE (XEXP (x, 0)));
7375       return cond0;
7376     }
7377
7378   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7379      make can't possibly match and would suppress other optimizations.  */
7380   else if (code == COMPARE)
7381     ;
7382
7383   /* If this is a binary operation, see if either side has only one of two
7384      values.  If either one does or if both do and they are conditional on
7385      the same value, compute the new true and false values.  */
7386   else if (BINARY_P (x))
7387     {
7388       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7389       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7390
7391       if ((cond0 != 0 || cond1 != 0)
7392           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7393         {
7394           /* If if_then_else_cond returned zero, then true/false are the
7395              same rtl.  We must copy one of them to prevent invalid rtl
7396              sharing.  */
7397           if (cond0 == 0)
7398             true0 = copy_rtx (true0);
7399           else if (cond1 == 0)
7400             true1 = copy_rtx (true1);
7401
7402           if (COMPARISON_P (x))
7403             {
7404               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7405                                                 true0, true1);
7406               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7407                                                  false0, false1);
7408              }
7409           else
7410             {
7411               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7412               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7413             }
7414
7415           return cond0 ? cond0 : cond1;
7416         }
7417
7418       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7419          operands is zero when the other is nonzero, and vice-versa,
7420          and STORE_FLAG_VALUE is 1 or -1.  */
7421
7422       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7423           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7424               || code == UMAX)
7425           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7426         {
7427           rtx op0 = XEXP (XEXP (x, 0), 1);
7428           rtx op1 = XEXP (XEXP (x, 1), 1);
7429
7430           cond0 = XEXP (XEXP (x, 0), 0);
7431           cond1 = XEXP (XEXP (x, 1), 0);
7432
7433           if (COMPARISON_P (cond0)
7434               && COMPARISON_P (cond1)
7435               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7436                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7437                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7438                   || ((swap_condition (GET_CODE (cond0))
7439                        == reversed_comparison_code (cond1, NULL))
7440                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7441                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7442               && ! side_effects_p (x))
7443             {
7444               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7445               *pfalse = simplify_gen_binary (MULT, mode,
7446                                              (code == MINUS
7447                                               ? simplify_gen_unary (NEG, mode,
7448                                                                     op1, mode)
7449                                               : op1),
7450                                               const_true_rtx);
7451               return cond0;
7452             }
7453         }
7454
7455       /* Similarly for MULT, AND and UMIN, except that for these the result
7456          is always zero.  */
7457       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7458           && (code == MULT || code == AND || code == UMIN)
7459           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7460         {
7461           cond0 = XEXP (XEXP (x, 0), 0);
7462           cond1 = XEXP (XEXP (x, 1), 0);
7463
7464           if (COMPARISON_P (cond0)
7465               && COMPARISON_P (cond1)
7466               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7467                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7468                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7469                   || ((swap_condition (GET_CODE (cond0))
7470                        == reversed_comparison_code (cond1, NULL))
7471                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7472                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7473               && ! side_effects_p (x))
7474             {
7475               *ptrue = *pfalse = const0_rtx;
7476               return cond0;
7477             }
7478         }
7479     }
7480
7481   else if (code == IF_THEN_ELSE)
7482     {
7483       /* If we have IF_THEN_ELSE already, extract the condition and
7484          canonicalize it if it is NE or EQ.  */
7485       cond0 = XEXP (x, 0);
7486       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7487       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7488         return XEXP (cond0, 0);
7489       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7490         {
7491           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7492           return XEXP (cond0, 0);
7493         }
7494       else
7495         return cond0;
7496     }
7497
7498   /* If X is a SUBREG, we can narrow both the true and false values
7499      if the inner expression, if there is a condition.  */
7500   else if (code == SUBREG
7501            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7502                                                &true0, &false0)))
7503     {
7504       true0 = simplify_gen_subreg (mode, true0,
7505                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7506       false0 = simplify_gen_subreg (mode, false0,
7507                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7508       if (true0 && false0)
7509         {
7510           *ptrue = true0;
7511           *pfalse = false0;
7512           return cond0;
7513         }
7514     }
7515
7516   /* If X is a constant, this isn't special and will cause confusions
7517      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7518   else if (CONSTANT_P (x)
7519            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7520     ;
7521
7522   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7523      will be least confusing to the rest of the compiler.  */
7524   else if (mode == BImode)
7525     {
7526       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7527       return x;
7528     }
7529
7530   /* If X is known to be either 0 or -1, those are the true and
7531      false values when testing X.  */
7532   else if (x == constm1_rtx || x == const0_rtx
7533            || (mode != VOIDmode
7534                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7535     {
7536       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7537       return x;
7538     }
7539
7540   /* Likewise for 0 or a single bit.  */
7541   else if (SCALAR_INT_MODE_P (mode)
7542            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7543            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7544     {
7545       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7546       return x;
7547     }
7548
7549   /* Otherwise fail; show no condition with true and false values the same.  */
7550   *ptrue = *pfalse = x;
7551   return 0;
7552 }
7553 \f
7554 /* Return the value of expression X given the fact that condition COND
7555    is known to be true when applied to REG as its first operand and VAL
7556    as its second.  X is known to not be shared and so can be modified in
7557    place.
7558
7559    We only handle the simplest cases, and specifically those cases that
7560    arise with IF_THEN_ELSE expressions.  */
7561
7562 static rtx
7563 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7564 {
7565   enum rtx_code code = GET_CODE (x);
7566   rtx temp;
7567   const char *fmt;
7568   int i, j;
7569
7570   if (side_effects_p (x))
7571     return x;
7572
7573   /* If either operand of the condition is a floating point value,
7574      then we have to avoid collapsing an EQ comparison.  */
7575   if (cond == EQ
7576       && rtx_equal_p (x, reg)
7577       && ! FLOAT_MODE_P (GET_MODE (x))
7578       && ! FLOAT_MODE_P (GET_MODE (val)))
7579     return val;
7580
7581   if (cond == UNEQ && rtx_equal_p (x, reg))
7582     return val;
7583
7584   /* If X is (abs REG) and we know something about REG's relationship
7585      with zero, we may be able to simplify this.  */
7586
7587   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7588     switch (cond)
7589       {
7590       case GE:  case GT:  case EQ:
7591         return XEXP (x, 0);
7592       case LT:  case LE:
7593         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7594                                    XEXP (x, 0),
7595                                    GET_MODE (XEXP (x, 0)));
7596       default:
7597         break;
7598       }
7599
7600   /* The only other cases we handle are MIN, MAX, and comparisons if the
7601      operands are the same as REG and VAL.  */
7602
7603   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7604     {
7605       if (rtx_equal_p (XEXP (x, 0), val))
7606         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7607
7608       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7609         {
7610           if (COMPARISON_P (x))
7611             {
7612               if (comparison_dominates_p (cond, code))
7613                 return const_true_rtx;
7614
7615               code = reversed_comparison_code (x, NULL);
7616               if (code != UNKNOWN
7617                   && comparison_dominates_p (cond, code))
7618                 return const0_rtx;
7619               else
7620                 return x;
7621             }
7622           else if (code == SMAX || code == SMIN
7623                    || code == UMIN || code == UMAX)
7624             {
7625               int unsignedp = (code == UMIN || code == UMAX);
7626
7627               /* Do not reverse the condition when it is NE or EQ.
7628                  This is because we cannot conclude anything about
7629                  the value of 'SMAX (x, y)' when x is not equal to y,
7630                  but we can when x equals y.  */
7631               if ((code == SMAX || code == UMAX)
7632                   && ! (cond == EQ || cond == NE))
7633                 cond = reverse_condition (cond);
7634
7635               switch (cond)
7636                 {
7637                 case GE:   case GT:
7638                   return unsignedp ? x : XEXP (x, 1);
7639                 case LE:   case LT:
7640                   return unsignedp ? x : XEXP (x, 0);
7641                 case GEU:  case GTU:
7642                   return unsignedp ? XEXP (x, 1) : x;
7643                 case LEU:  case LTU:
7644                   return unsignedp ? XEXP (x, 0) : x;
7645                 default:
7646                   break;
7647                 }
7648             }
7649         }
7650     }
7651   else if (code == SUBREG)
7652     {
7653       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7654       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7655
7656       if (SUBREG_REG (x) != r)
7657         {
7658           /* We must simplify subreg here, before we lose track of the
7659              original inner_mode.  */
7660           new = simplify_subreg (GET_MODE (x), r,
7661                                  inner_mode, SUBREG_BYTE (x));
7662           if (new)
7663             return new;
7664           else
7665             SUBST (SUBREG_REG (x), r);
7666         }
7667
7668       return x;
7669     }
7670   /* We don't have to handle SIGN_EXTEND here, because even in the
7671      case of replacing something with a modeless CONST_INT, a
7672      CONST_INT is already (supposed to be) a valid sign extension for
7673      its narrower mode, which implies it's already properly
7674      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7675      story is different.  */
7676   else if (code == ZERO_EXTEND)
7677     {
7678       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7679       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7680
7681       if (XEXP (x, 0) != r)
7682         {
7683           /* We must simplify the zero_extend here, before we lose
7684              track of the original inner_mode.  */
7685           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7686                                           r, inner_mode);
7687           if (new)
7688             return new;
7689           else
7690             SUBST (XEXP (x, 0), r);
7691         }
7692
7693       return x;
7694     }
7695
7696   fmt = GET_RTX_FORMAT (code);
7697   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7698     {
7699       if (fmt[i] == 'e')
7700         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7701       else if (fmt[i] == 'E')
7702         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7703           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7704                                                 cond, reg, val));
7705     }
7706
7707   return x;
7708 }
7709 \f
7710 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7711    assignment as a field assignment.  */
7712
7713 static int
7714 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7715 {
7716   if (x == y || rtx_equal_p (x, y))
7717     return 1;
7718
7719   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7720     return 0;
7721
7722   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7723      Note that all SUBREGs of MEM are paradoxical; otherwise they
7724      would have been rewritten.  */
7725   if (MEM_P (x) && GET_CODE (y) == SUBREG
7726       && MEM_P (SUBREG_REG (y))
7727       && rtx_equal_p (SUBREG_REG (y),
7728                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7729     return 1;
7730
7731   if (MEM_P (y) && GET_CODE (x) == SUBREG
7732       && MEM_P (SUBREG_REG (x))
7733       && rtx_equal_p (SUBREG_REG (x),
7734                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7735     return 1;
7736
7737   /* We used to see if get_last_value of X and Y were the same but that's
7738      not correct.  In one direction, we'll cause the assignment to have
7739      the wrong destination and in the case, we'll import a register into this
7740      insn that might have already have been dead.   So fail if none of the
7741      above cases are true.  */
7742   return 0;
7743 }
7744 \f
7745 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7746    Return that assignment if so.
7747
7748    We only handle the most common cases.  */
7749
7750 static rtx
7751 make_field_assignment (rtx x)
7752 {
7753   rtx dest = SET_DEST (x);
7754   rtx src = SET_SRC (x);
7755   rtx assign;
7756   rtx rhs, lhs;
7757   HOST_WIDE_INT c1;
7758   HOST_WIDE_INT pos;
7759   unsigned HOST_WIDE_INT len;
7760   rtx other;
7761   enum machine_mode mode;
7762
7763   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7764      a clear of a one-bit field.  We will have changed it to
7765      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7766      for a SUBREG.  */
7767
7768   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7769       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7770       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7771       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7772     {
7773       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7774                                 1, 1, 1, 0);
7775       if (assign != 0)
7776         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7777       return x;
7778     }
7779
7780   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7781       && subreg_lowpart_p (XEXP (src, 0))
7782       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7783           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7784       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7785       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7786       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7787       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7788     {
7789       assign = make_extraction (VOIDmode, dest, 0,
7790                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7791                                 1, 1, 1, 0);
7792       if (assign != 0)
7793         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7794       return x;
7795     }
7796
7797   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7798      one-bit field.  */
7799   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7800       && XEXP (XEXP (src, 0), 0) == const1_rtx
7801       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7802     {
7803       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7804                                 1, 1, 1, 0);
7805       if (assign != 0)
7806         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7807       return x;
7808     }
7809
7810   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7811      SRC is an AND with all bits of that field set, then we can discard
7812      the AND.  */
7813   if (GET_CODE (dest) == ZERO_EXTRACT
7814       && GET_CODE (XEXP (dest, 1)) == CONST_INT
7815       && GET_CODE (src) == AND
7816       && GET_CODE (XEXP (src, 1)) == CONST_INT)
7817     {
7818       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7819       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7820       unsigned HOST_WIDE_INT ze_mask;
7821
7822       if (width >= HOST_BITS_PER_WIDE_INT)
7823         ze_mask = -1;
7824       else
7825         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7826
7827       /* Complete overlap.  We can remove the source AND.  */
7828       if ((and_mask & ze_mask) == ze_mask)
7829         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7830
7831       /* Partial overlap.  We can reduce the source AND.  */
7832       if ((and_mask & ze_mask) != and_mask)
7833         {
7834           mode = GET_MODE (src);
7835           src = gen_rtx_AND (mode, XEXP (src, 0),
7836                              gen_int_mode (and_mask & ze_mask, mode));
7837           return gen_rtx_SET (VOIDmode, dest, src);
7838         }
7839     }
7840
7841   /* The other case we handle is assignments into a constant-position
7842      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7843      a mask that has all one bits except for a group of zero bits and
7844      OTHER is known to have zeros where C1 has ones, this is such an
7845      assignment.  Compute the position and length from C1.  Shift OTHER
7846      to the appropriate position, force it to the required mode, and
7847      make the extraction.  Check for the AND in both operands.  */
7848
7849   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7850     return x;
7851
7852   rhs = expand_compound_operation (XEXP (src, 0));
7853   lhs = expand_compound_operation (XEXP (src, 1));
7854
7855   if (GET_CODE (rhs) == AND
7856       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7857       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7858     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7859   else if (GET_CODE (lhs) == AND
7860            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7861            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7862     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7863   else
7864     return x;
7865
7866   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7867   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7868       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7869       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7870     return x;
7871
7872   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7873   if (assign == 0)
7874     return x;
7875
7876   /* The mode to use for the source is the mode of the assignment, or of
7877      what is inside a possible STRICT_LOW_PART.  */
7878   mode = (GET_CODE (assign) == STRICT_LOW_PART
7879           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7880
7881   /* Shift OTHER right POS places and make it the source, restricting it
7882      to the proper length and mode.  */
7883
7884   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7885                                                      GET_MODE (src),
7886                                                      other, pos),
7887                                dest);
7888   src = force_to_mode (src, mode,
7889                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7890                        ? ~(unsigned HOST_WIDE_INT) 0
7891                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7892                        0);
7893
7894   /* If SRC is masked by an AND that does not make a difference in
7895      the value being stored, strip it.  */
7896   if (GET_CODE (assign) == ZERO_EXTRACT
7897       && GET_CODE (XEXP (assign, 1)) == CONST_INT
7898       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7899       && GET_CODE (src) == AND
7900       && GET_CODE (XEXP (src, 1)) == CONST_INT
7901       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7902           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7903     src = XEXP (src, 0);
7904
7905   return gen_rtx_SET (VOIDmode, assign, src);
7906 }
7907 \f
7908 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7909    if so.  */
7910
7911 static rtx
7912 apply_distributive_law (rtx x)
7913 {
7914   enum rtx_code code = GET_CODE (x);
7915   enum rtx_code inner_code;
7916   rtx lhs, rhs, other;
7917   rtx tem;
7918
7919   /* Distributivity is not true for floating point as it can change the
7920      value.  So we don't do it unless -funsafe-math-optimizations.  */
7921   if (FLOAT_MODE_P (GET_MODE (x))
7922       && ! flag_unsafe_math_optimizations)
7923     return x;
7924
7925   /* The outer operation can only be one of the following:  */
7926   if (code != IOR && code != AND && code != XOR
7927       && code != PLUS && code != MINUS)
7928     return x;
7929
7930   lhs = XEXP (x, 0);
7931   rhs = XEXP (x, 1);
7932
7933   /* If either operand is a primitive we can't do anything, so get out
7934      fast.  */
7935   if (OBJECT_P (lhs) || OBJECT_P (rhs))
7936     return x;
7937
7938   lhs = expand_compound_operation (lhs);
7939   rhs = expand_compound_operation (rhs);
7940   inner_code = GET_CODE (lhs);
7941   if (inner_code != GET_CODE (rhs))
7942     return x;
7943
7944   /* See if the inner and outer operations distribute.  */
7945   switch (inner_code)
7946     {
7947     case LSHIFTRT:
7948     case ASHIFTRT:
7949     case AND:
7950     case IOR:
7951       /* These all distribute except over PLUS.  */
7952       if (code == PLUS || code == MINUS)
7953         return x;
7954       break;
7955
7956     case MULT:
7957       if (code != PLUS && code != MINUS)
7958         return x;
7959       break;
7960
7961     case ASHIFT:
7962       /* This is also a multiply, so it distributes over everything.  */
7963       break;
7964
7965     case SUBREG:
7966       /* Non-paradoxical SUBREGs distributes over all operations,
7967          provided the inner modes and byte offsets are the same, this
7968          is an extraction of a low-order part, we don't convert an fp
7969          operation to int or vice versa, this is not a vector mode,
7970          and we would not be converting a single-word operation into a
7971          multi-word operation.  The latter test is not required, but
7972          it prevents generating unneeded multi-word operations.  Some
7973          of the previous tests are redundant given the latter test,
7974          but are retained because they are required for correctness.
7975
7976          We produce the result slightly differently in this case.  */
7977
7978       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7979           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7980           || ! subreg_lowpart_p (lhs)
7981           || (GET_MODE_CLASS (GET_MODE (lhs))
7982               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7983           || (GET_MODE_SIZE (GET_MODE (lhs))
7984               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7985           || VECTOR_MODE_P (GET_MODE (lhs))
7986           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7987           /* Result might need to be truncated.  Don't change mode if
7988              explicit truncation is needed.  */
7989           || !TRULY_NOOP_TRUNCATION
7990                (GET_MODE_BITSIZE (GET_MODE (x)),
7991                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7992         return x;
7993
7994       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7995                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
7996       return gen_lowpart (GET_MODE (x), tem);
7997
7998     default:
7999       return x;
8000     }
8001
8002   /* Set LHS and RHS to the inner operands (A and B in the example
8003      above) and set OTHER to the common operand (C in the example).
8004      There is only one way to do this unless the inner operation is
8005      commutative.  */
8006   if (COMMUTATIVE_ARITH_P (lhs)
8007       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8008     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8009   else if (COMMUTATIVE_ARITH_P (lhs)
8010            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8011     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8012   else if (COMMUTATIVE_ARITH_P (lhs)
8013            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8014     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8015   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8016     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8017   else
8018     return x;
8019
8020   /* Form the new inner operation, seeing if it simplifies first.  */
8021   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8022
8023   /* There is one exception to the general way of distributing:
8024      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8025   if (code == XOR && inner_code == IOR)
8026     {
8027       inner_code = AND;
8028       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8029     }
8030
8031   /* We may be able to continuing distributing the result, so call
8032      ourselves recursively on the inner operation before forming the
8033      outer operation, which we return.  */
8034   return simplify_gen_binary (inner_code, GET_MODE (x),
8035                               apply_distributive_law (tem), other);
8036 }
8037
8038 /* See if X is of the form (* (+ A B) C), and if so convert to
8039    (+ (* A C) (* B C)) and try to simplify.
8040
8041    Most of the time, this results in no change.  However, if some of
8042    the operands are the same or inverses of each other, simplifications
8043    will result.
8044
8045    For example, (and (ior A B) (not B)) can occur as the result of
8046    expanding a bit field assignment.  When we apply the distributive
8047    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8048    which then simplifies to (and (A (not B))).
8049
8050    Note that no checks happen on the validity of applying the inverse
8051    distributive law.  This is pointless since we can do it in the
8052    few places where this routine is called.
8053
8054    N is the index of the term that is decomposed (the arithmetic operation,
8055    i.e. (+ A B) in the first example above).  !N is the index of the term that
8056    is distributed, i.e. of C in the first example above.  */
8057 static rtx
8058 distribute_and_simplify_rtx (rtx x, int n)
8059 {
8060   enum machine_mode mode;
8061   enum rtx_code outer_code, inner_code;
8062   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8063
8064   decomposed = XEXP (x, n);
8065   if (!ARITHMETIC_P (decomposed))
8066     return NULL_RTX;
8067
8068   mode = GET_MODE (x);
8069   outer_code = GET_CODE (x);
8070   distributed = XEXP (x, !n);
8071
8072   inner_code = GET_CODE (decomposed);
8073   inner_op0 = XEXP (decomposed, 0);
8074   inner_op1 = XEXP (decomposed, 1);
8075
8076   /* Special case (and (xor B C) (not A)), which is equivalent to
8077      (xor (ior A B) (ior A C))  */
8078   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8079     {
8080       distributed = XEXP (distributed, 0);
8081       outer_code = IOR;
8082     }
8083
8084   if (n == 0)
8085     {
8086       /* Distribute the second term.  */
8087       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8088       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8089     }
8090   else
8091     {
8092       /* Distribute the first term.  */
8093       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8094       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8095     }
8096
8097   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8098                                                      new_op0, new_op1));
8099   if (GET_CODE (tmp) != outer_code
8100       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8101     return tmp;
8102
8103   return NULL_RTX;
8104 }
8105 \f
8106 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8107    in MODE.  Return an equivalent form, if different from (and VAROP
8108    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8109
8110 static rtx
8111 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8112                           unsigned HOST_WIDE_INT constop)
8113 {
8114   unsigned HOST_WIDE_INT nonzero;
8115   unsigned HOST_WIDE_INT orig_constop;
8116   rtx orig_varop;
8117   int i;
8118
8119   orig_varop = varop;
8120   orig_constop = constop;
8121   if (GET_CODE (varop) == CLOBBER)
8122     return NULL_RTX;
8123
8124   /* Simplify VAROP knowing that we will be only looking at some of the
8125      bits in it.
8126
8127      Note by passing in CONSTOP, we guarantee that the bits not set in
8128      CONSTOP are not significant and will never be examined.  We must
8129      ensure that is the case by explicitly masking out those bits
8130      before returning.  */
8131   varop = force_to_mode (varop, mode, constop, 0);
8132
8133   /* If VAROP is a CLOBBER, we will fail so return it.  */
8134   if (GET_CODE (varop) == CLOBBER)
8135     return varop;
8136
8137   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8138      to VAROP and return the new constant.  */
8139   if (GET_CODE (varop) == CONST_INT)
8140     return gen_int_mode (INTVAL (varop) & constop, mode);
8141
8142   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8143      a call to nonzero_bits, here we don't care about bits outside
8144      MODE.  */
8145
8146   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8147
8148   /* Turn off all bits in the constant that are known to already be zero.
8149      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8150      which is tested below.  */
8151
8152   constop &= nonzero;
8153
8154   /* If we don't have any bits left, return zero.  */
8155   if (constop == 0)
8156     return const0_rtx;
8157
8158   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8159      a power of two, we can replace this with an ASHIFT.  */
8160   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8161       && (i = exact_log2 (constop)) >= 0)
8162     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8163
8164   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8165      or XOR, then try to apply the distributive law.  This may eliminate
8166      operations if either branch can be simplified because of the AND.
8167      It may also make some cases more complex, but those cases probably
8168      won't match a pattern either with or without this.  */
8169
8170   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8171     return
8172       gen_lowpart
8173         (mode,
8174          apply_distributive_law
8175          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8176                                simplify_and_const_int (NULL_RTX,
8177                                                        GET_MODE (varop),
8178                                                        XEXP (varop, 0),
8179                                                        constop),
8180                                simplify_and_const_int (NULL_RTX,
8181                                                        GET_MODE (varop),
8182                                                        XEXP (varop, 1),
8183                                                        constop))));
8184
8185   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8186      the AND and see if one of the operands simplifies to zero.  If so, we
8187      may eliminate it.  */
8188
8189   if (GET_CODE (varop) == PLUS
8190       && exact_log2 (constop + 1) >= 0)
8191     {
8192       rtx o0, o1;
8193
8194       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8195       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8196       if (o0 == const0_rtx)
8197         return o1;
8198       if (o1 == const0_rtx)
8199         return o0;
8200     }
8201
8202   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8203   varop = gen_lowpart (mode, varop);
8204   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8205     return NULL_RTX;
8206
8207   /* If we are only masking insignificant bits, return VAROP.  */
8208   if (constop == nonzero)
8209     return varop;
8210
8211   if (varop == orig_varop && constop == orig_constop)
8212     return NULL_RTX;
8213
8214   /* Otherwise, return an AND.  */
8215   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8216 }
8217
8218
8219 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8220    in MODE.
8221
8222    Return an equivalent form, if different from X.  Otherwise, return X.  If
8223    X is zero, we are to always construct the equivalent form.  */
8224
8225 static rtx
8226 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8227                         unsigned HOST_WIDE_INT constop)
8228 {
8229   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8230   if (tem)
8231     return tem;
8232
8233   if (!x)
8234     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8235                              gen_int_mode (constop, mode));
8236   if (GET_MODE (x) != mode)
8237     x = gen_lowpart (mode, x);
8238   return x;
8239 }
8240 \f
8241 /* Given a REG, X, compute which bits in X can be nonzero.
8242    We don't care about bits outside of those defined in MODE.
8243
8244    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8245    a shift, AND, or zero_extract, we can do better.  */
8246
8247 static rtx
8248 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8249                               rtx known_x ATTRIBUTE_UNUSED,
8250                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8251                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8252                               unsigned HOST_WIDE_INT *nonzero)
8253 {
8254   rtx tem;
8255
8256   /* If X is a register whose nonzero bits value is current, use it.
8257      Otherwise, if X is a register whose value we can find, use that
8258      value.  Otherwise, use the previously-computed global nonzero bits
8259      for this register.  */
8260
8261   if (reg_stat[REGNO (x)].last_set_value != 0
8262       && (reg_stat[REGNO (x)].last_set_mode == mode
8263           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8264               && GET_MODE_CLASS (mode) == MODE_INT))
8265       && (reg_stat[REGNO (x)].last_set_label == label_tick
8266           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8267               && REG_N_SETS (REGNO (x)) == 1
8268               && ! REGNO_REG_SET_P
8269                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8270                   REGNO (x))))
8271       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8272     {
8273       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8274       return NULL;
8275     }
8276
8277   tem = get_last_value (x);
8278
8279   if (tem)
8280     {
8281 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8282       /* If X is narrower than MODE and TEM is a non-negative
8283          constant that would appear negative in the mode of X,
8284          sign-extend it for use in reg_nonzero_bits because some
8285          machines (maybe most) will actually do the sign-extension
8286          and this is the conservative approach.
8287
8288          ??? For 2.5, try to tighten up the MD files in this regard
8289          instead of this kludge.  */
8290
8291       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8292           && GET_CODE (tem) == CONST_INT
8293           && INTVAL (tem) > 0
8294           && 0 != (INTVAL (tem)
8295                    & ((HOST_WIDE_INT) 1
8296                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8297         tem = GEN_INT (INTVAL (tem)
8298                        | ((HOST_WIDE_INT) (-1)
8299                           << GET_MODE_BITSIZE (GET_MODE (x))));
8300 #endif
8301       return tem;
8302     }
8303   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8304     {
8305       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8306
8307       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8308         /* We don't know anything about the upper bits.  */
8309         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8310       *nonzero &= mask;
8311     }
8312
8313   return NULL;
8314 }
8315
8316 /* Return the number of bits at the high-order end of X that are known to
8317    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8318    VOIDmode, X will be used in its own mode.  The returned value  will always
8319    be between 1 and the number of bits in MODE.  */
8320
8321 static rtx
8322 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8323                                      rtx known_x ATTRIBUTE_UNUSED,
8324                                      enum machine_mode known_mode
8325                                      ATTRIBUTE_UNUSED,
8326                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8327                                      unsigned int *result)
8328 {
8329   rtx tem;
8330
8331   if (reg_stat[REGNO (x)].last_set_value != 0
8332       && reg_stat[REGNO (x)].last_set_mode == mode
8333       && (reg_stat[REGNO (x)].last_set_label == label_tick
8334           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8335               && REG_N_SETS (REGNO (x)) == 1
8336               && ! REGNO_REG_SET_P
8337                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8338                   REGNO (x))))
8339       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8340     {
8341       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8342       return NULL;
8343     }
8344
8345   tem = get_last_value (x);
8346   if (tem != 0)
8347     return tem;
8348
8349   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8350       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8351     *result = reg_stat[REGNO (x)].sign_bit_copies;
8352
8353   return NULL;
8354 }
8355 \f
8356 /* Return the number of "extended" bits there are in X, when interpreted
8357    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8358    unsigned quantities, this is the number of high-order zero bits.
8359    For signed quantities, this is the number of copies of the sign bit
8360    minus 1.  In both case, this function returns the number of "spare"
8361    bits.  For example, if two quantities for which this function returns
8362    at least 1 are added, the addition is known not to overflow.
8363
8364    This function will always return 0 unless called during combine, which
8365    implies that it must be called from a define_split.  */
8366
8367 unsigned int
8368 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8369 {
8370   if (nonzero_sign_valid == 0)
8371     return 0;
8372
8373   return (unsignedp
8374           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8375              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8376                                - floor_log2 (nonzero_bits (x, mode)))
8377              : 0)
8378           : num_sign_bit_copies (x, mode) - 1);
8379 }
8380 \f
8381 /* This function is called from `simplify_shift_const' to merge two
8382    outer operations.  Specifically, we have already found that we need
8383    to perform operation *POP0 with constant *PCONST0 at the outermost
8384    position.  We would now like to also perform OP1 with constant CONST1
8385    (with *POP0 being done last).
8386
8387    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8388    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8389    complement the innermost operand, otherwise it is unchanged.
8390
8391    MODE is the mode in which the operation will be done.  No bits outside
8392    the width of this mode matter.  It is assumed that the width of this mode
8393    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8394
8395    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8396    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8397    result is simply *PCONST0.
8398
8399    If the resulting operation cannot be expressed as one operation, we
8400    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8401
8402 static int
8403 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8404 {
8405   enum rtx_code op0 = *pop0;
8406   HOST_WIDE_INT const0 = *pconst0;
8407
8408   const0 &= GET_MODE_MASK (mode);
8409   const1 &= GET_MODE_MASK (mode);
8410
8411   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8412   if (op0 == AND)
8413     const1 &= const0;
8414
8415   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8416      if OP0 is SET.  */
8417
8418   if (op1 == UNKNOWN || op0 == SET)
8419     return 1;
8420
8421   else if (op0 == UNKNOWN)
8422     op0 = op1, const0 = const1;
8423
8424   else if (op0 == op1)
8425     {
8426       switch (op0)
8427         {
8428         case AND:
8429           const0 &= const1;
8430           break;
8431         case IOR:
8432           const0 |= const1;
8433           break;
8434         case XOR:
8435           const0 ^= const1;
8436           break;
8437         case PLUS:
8438           const0 += const1;
8439           break;
8440         case NEG:
8441           op0 = UNKNOWN;
8442           break;
8443         default:
8444           break;
8445         }
8446     }
8447
8448   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8449   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8450     return 0;
8451
8452   /* If the two constants aren't the same, we can't do anything.  The
8453      remaining six cases can all be done.  */
8454   else if (const0 != const1)
8455     return 0;
8456
8457   else
8458     switch (op0)
8459       {
8460       case IOR:
8461         if (op1 == AND)
8462           /* (a & b) | b == b */
8463           op0 = SET;
8464         else /* op1 == XOR */
8465           /* (a ^ b) | b == a | b */
8466           {;}
8467         break;
8468
8469       case XOR:
8470         if (op1 == AND)
8471           /* (a & b) ^ b == (~a) & b */
8472           op0 = AND, *pcomp_p = 1;
8473         else /* op1 == IOR */
8474           /* (a | b) ^ b == a & ~b */
8475           op0 = AND, const0 = ~const0;
8476         break;
8477
8478       case AND:
8479         if (op1 == IOR)
8480           /* (a | b) & b == b */
8481         op0 = SET;
8482         else /* op1 == XOR */
8483           /* (a ^ b) & b) == (~a) & b */
8484           *pcomp_p = 1;
8485         break;
8486       default:
8487         break;
8488       }
8489
8490   /* Check for NO-OP cases.  */
8491   const0 &= GET_MODE_MASK (mode);
8492   if (const0 == 0
8493       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8494     op0 = UNKNOWN;
8495   else if (const0 == 0 && op0 == AND)
8496     op0 = SET;
8497   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8498            && op0 == AND)
8499     op0 = UNKNOWN;
8500
8501   /* ??? Slightly redundant with the above mask, but not entirely.
8502      Moving this above means we'd have to sign-extend the mode mask
8503      for the final test.  */
8504   const0 = trunc_int_for_mode (const0, mode);
8505
8506   *pop0 = op0;
8507   *pconst0 = const0;
8508
8509   return 1;
8510 }
8511 \f
8512 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8513    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8514    simplify it.  Otherwise, return a simplified value.
8515
8516    The shift is normally computed in the widest mode we find in VAROP, as
8517    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8518    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8519
8520 static rtx
8521 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8522                         rtx varop, int orig_count)
8523 {
8524   enum rtx_code orig_code = code;
8525   rtx orig_varop = varop;
8526   int count;
8527   enum machine_mode mode = result_mode;
8528   enum machine_mode shift_mode, tmode;
8529   unsigned int mode_words
8530     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8531   /* We form (outer_op (code varop count) (outer_const)).  */
8532   enum rtx_code outer_op = UNKNOWN;
8533   HOST_WIDE_INT outer_const = 0;
8534   int complement_p = 0;
8535   rtx new, x;
8536
8537   /* Make sure and truncate the "natural" shift on the way in.  We don't
8538      want to do this inside the loop as it makes it more difficult to
8539      combine shifts.  */
8540   if (SHIFT_COUNT_TRUNCATED)
8541     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8542
8543   /* If we were given an invalid count, don't do anything except exactly
8544      what was requested.  */
8545
8546   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8547     return NULL_RTX;
8548
8549   count = orig_count;
8550
8551   /* Unless one of the branches of the `if' in this loop does a `continue',
8552      we will `break' the loop after the `if'.  */
8553
8554   while (count != 0)
8555     {
8556       /* If we have an operand of (clobber (const_int 0)), fail.  */
8557       if (GET_CODE (varop) == CLOBBER)
8558         return NULL_RTX;
8559
8560       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8561          here would cause an infinite loop.  */
8562       if (complement_p)
8563         break;
8564
8565       /* Convert ROTATERT to ROTATE.  */
8566       if (code == ROTATERT)
8567         {
8568           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8569           code = ROTATE;
8570           if (VECTOR_MODE_P (result_mode))
8571             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8572           else
8573             count = bitsize - count;
8574         }
8575
8576       /* We need to determine what mode we will do the shift in.  If the
8577          shift is a right shift or a ROTATE, we must always do it in the mode
8578          it was originally done in.  Otherwise, we can do it in MODE, the
8579          widest mode encountered.  */
8580       shift_mode
8581         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8582            ? result_mode : mode);
8583
8584       /* Handle cases where the count is greater than the size of the mode
8585          minus 1.  For ASHIFT, use the size minus one as the count (this can
8586          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8587          take the count modulo the size.  For other shifts, the result is
8588          zero.
8589
8590          Since these shifts are being produced by the compiler by combining
8591          multiple operations, each of which are defined, we know what the
8592          result is supposed to be.  */
8593
8594       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8595         {
8596           if (code == ASHIFTRT)
8597             count = GET_MODE_BITSIZE (shift_mode) - 1;
8598           else if (code == ROTATE || code == ROTATERT)
8599             count %= GET_MODE_BITSIZE (shift_mode);
8600           else
8601             {
8602               /* We can't simply return zero because there may be an
8603                  outer op.  */
8604               varop = const0_rtx;
8605               count = 0;
8606               break;
8607             }
8608         }
8609
8610       /* An arithmetic right shift of a quantity known to be -1 or 0
8611          is a no-op.  */
8612       if (code == ASHIFTRT
8613           && (num_sign_bit_copies (varop, shift_mode)
8614               == GET_MODE_BITSIZE (shift_mode)))
8615         {
8616           count = 0;
8617           break;
8618         }
8619
8620       /* If we are doing an arithmetic right shift and discarding all but
8621          the sign bit copies, this is equivalent to doing a shift by the
8622          bitsize minus one.  Convert it into that shift because it will often
8623          allow other simplifications.  */
8624
8625       if (code == ASHIFTRT
8626           && (count + num_sign_bit_copies (varop, shift_mode)
8627               >= GET_MODE_BITSIZE (shift_mode)))
8628         count = GET_MODE_BITSIZE (shift_mode) - 1;
8629
8630       /* We simplify the tests below and elsewhere by converting
8631          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8632          `make_compound_operation' will convert it to an ASHIFTRT for
8633          those machines (such as VAX) that don't have an LSHIFTRT.  */
8634       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8635           && code == ASHIFTRT
8636           && ((nonzero_bits (varop, shift_mode)
8637                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8638               == 0))
8639         code = LSHIFTRT;
8640
8641       if (((code == LSHIFTRT
8642             && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8643             && !(nonzero_bits (varop, shift_mode) >> count))
8644            || (code == ASHIFT
8645                && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8646                && !((nonzero_bits (varop, shift_mode) << count)
8647                     & GET_MODE_MASK (shift_mode))))
8648           && !side_effects_p (varop))
8649         varop = const0_rtx;
8650
8651       switch (GET_CODE (varop))
8652         {
8653         case SIGN_EXTEND:
8654         case ZERO_EXTEND:
8655         case SIGN_EXTRACT:
8656         case ZERO_EXTRACT:
8657           new = expand_compound_operation (varop);
8658           if (new != varop)
8659             {
8660               varop = new;
8661               continue;
8662             }
8663           break;
8664
8665         case MEM:
8666           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8667              minus the width of a smaller mode, we can do this with a
8668              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8669           if ((code == ASHIFTRT || code == LSHIFTRT)
8670               && ! mode_dependent_address_p (XEXP (varop, 0))
8671               && ! MEM_VOLATILE_P (varop)
8672               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8673                                          MODE_INT, 1)) != BLKmode)
8674             {
8675               new = adjust_address_nv (varop, tmode,
8676                                        BYTES_BIG_ENDIAN ? 0
8677                                        : count / BITS_PER_UNIT);
8678
8679               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8680                                      : ZERO_EXTEND, mode, new);
8681               count = 0;
8682               continue;
8683             }
8684           break;
8685
8686         case SUBREG:
8687           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8688              the same number of words as what we've seen so far.  Then store
8689              the widest mode in MODE.  */
8690           if (subreg_lowpart_p (varop)
8691               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8692                   > GET_MODE_SIZE (GET_MODE (varop)))
8693               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8694                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8695                  == mode_words)
8696             {
8697               varop = SUBREG_REG (varop);
8698               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8699                 mode = GET_MODE (varop);
8700               continue;
8701             }
8702           break;
8703
8704         case MULT:
8705           /* Some machines use MULT instead of ASHIFT because MULT
8706              is cheaper.  But it is still better on those machines to
8707              merge two shifts into one.  */
8708           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8709               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8710             {
8711               varop
8712                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8713                                        XEXP (varop, 0),
8714                                        GEN_INT (exact_log2 (
8715                                                 INTVAL (XEXP (varop, 1)))));
8716               continue;
8717             }
8718           break;
8719
8720         case UDIV:
8721           /* Similar, for when divides are cheaper.  */
8722           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8723               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8724             {
8725               varop
8726                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8727                                        XEXP (varop, 0),
8728                                        GEN_INT (exact_log2 (
8729                                                 INTVAL (XEXP (varop, 1)))));
8730               continue;
8731             }
8732           break;
8733
8734         case ASHIFTRT:
8735           /* If we are extracting just the sign bit of an arithmetic
8736              right shift, that shift is not needed.  However, the sign
8737              bit of a wider mode may be different from what would be
8738              interpreted as the sign bit in a narrower mode, so, if
8739              the result is narrower, don't discard the shift.  */
8740           if (code == LSHIFTRT
8741               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8742               && (GET_MODE_BITSIZE (result_mode)
8743                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8744             {
8745               varop = XEXP (varop, 0);
8746               continue;
8747             }
8748
8749           /* ... fall through ...  */
8750
8751         case LSHIFTRT:
8752         case ASHIFT:
8753         case ROTATE:
8754           /* Here we have two nested shifts.  The result is usually the
8755              AND of a new shift with a mask.  We compute the result below.  */
8756           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8757               && INTVAL (XEXP (varop, 1)) >= 0
8758               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8759               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8760               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8761               && !VECTOR_MODE_P (result_mode))
8762             {
8763               enum rtx_code first_code = GET_CODE (varop);
8764               unsigned int first_count = INTVAL (XEXP (varop, 1));
8765               unsigned HOST_WIDE_INT mask;
8766               rtx mask_rtx;
8767
8768               /* We have one common special case.  We can't do any merging if
8769                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8770                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8771                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8772                  we can convert it to
8773                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8774                  This simplifies certain SIGN_EXTEND operations.  */
8775               if (code == ASHIFT && first_code == ASHIFTRT
8776                   && count == (GET_MODE_BITSIZE (result_mode)
8777                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8778                 {
8779                   /* C3 has the low-order C1 bits zero.  */
8780
8781                   mask = (GET_MODE_MASK (mode)
8782                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8783
8784                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8785                                                   XEXP (varop, 0), mask);
8786                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8787                                                 varop, count);
8788                   count = first_count;
8789                   code = ASHIFTRT;
8790                   continue;
8791                 }
8792
8793               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8794                  than C1 high-order bits equal to the sign bit, we can convert
8795                  this to either an ASHIFT or an ASHIFTRT depending on the
8796                  two counts.
8797
8798                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8799
8800               if (code == ASHIFTRT && first_code == ASHIFT
8801                   && GET_MODE (varop) == shift_mode
8802                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8803                       > first_count))
8804                 {
8805                   varop = XEXP (varop, 0);
8806                   count -= first_count;
8807                   if (count < 0)
8808                     {
8809                       count = -count;
8810                       code = ASHIFT;
8811                     }
8812
8813                   continue;
8814                 }
8815
8816               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8817                  we can only do this if FIRST_CODE is also ASHIFTRT.
8818
8819                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8820                  ASHIFTRT.
8821
8822                  If the mode of this shift is not the mode of the outer shift,
8823                  we can't do this if either shift is a right shift or ROTATE.
8824
8825                  Finally, we can't do any of these if the mode is too wide
8826                  unless the codes are the same.
8827
8828                  Handle the case where the shift codes are the same
8829                  first.  */
8830
8831               if (code == first_code)
8832                 {
8833                   if (GET_MODE (varop) != result_mode
8834                       && (code == ASHIFTRT || code == LSHIFTRT
8835                           || code == ROTATE))
8836                     break;
8837
8838                   count += first_count;
8839                   varop = XEXP (varop, 0);
8840                   continue;
8841                 }
8842
8843               if (code == ASHIFTRT
8844                   || (code == ROTATE && first_code == ASHIFTRT)
8845                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8846                   || (GET_MODE (varop) != result_mode
8847                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8848                           || first_code == ROTATE
8849                           || code == ROTATE)))
8850                 break;
8851
8852               /* To compute the mask to apply after the shift, shift the
8853                  nonzero bits of the inner shift the same way the
8854                  outer shift will.  */
8855
8856               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8857
8858               mask_rtx
8859                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8860                                                    GEN_INT (count));
8861
8862               /* Give up if we can't compute an outer operation to use.  */
8863               if (mask_rtx == 0
8864                   || GET_CODE (mask_rtx) != CONST_INT
8865                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8866                                         INTVAL (mask_rtx),
8867                                         result_mode, &complement_p))
8868                 break;
8869
8870               /* If the shifts are in the same direction, we add the
8871                  counts.  Otherwise, we subtract them.  */
8872               if ((code == ASHIFTRT || code == LSHIFTRT)
8873                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8874                 count += first_count;
8875               else
8876                 count -= first_count;
8877
8878               /* If COUNT is positive, the new shift is usually CODE,
8879                  except for the two exceptions below, in which case it is
8880                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8881                  always be used  */
8882               if (count > 0
8883                   && ((first_code == ROTATE && code == ASHIFT)
8884                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8885                 code = first_code;
8886               else if (count < 0)
8887                 code = first_code, count = -count;
8888
8889               varop = XEXP (varop, 0);
8890               continue;
8891             }
8892
8893           /* If we have (A << B << C) for any shift, we can convert this to
8894              (A << C << B).  This wins if A is a constant.  Only try this if
8895              B is not a constant.  */
8896
8897           else if (GET_CODE (varop) == code
8898                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
8899                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8900             {
8901               rtx new = simplify_const_binary_operation (code, mode,
8902                                                          XEXP (varop, 0),
8903                                                          GEN_INT (count));
8904               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8905               count = 0;
8906               continue;
8907             }
8908           break;
8909
8910         case NOT:
8911           /* Make this fit the case below.  */
8912           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8913                                GEN_INT (GET_MODE_MASK (mode)));
8914           continue;
8915
8916         case IOR:
8917         case AND:
8918         case XOR:
8919           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8920              with C the size of VAROP - 1 and the shift is logical if
8921              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8922              we have an (le X 0) operation.   If we have an arithmetic shift
8923              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8924              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8925
8926           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8927               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8928               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8929               && (code == LSHIFTRT || code == ASHIFTRT)
8930               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8931               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8932             {
8933               count = 0;
8934               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8935                                   const0_rtx);
8936
8937               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8938                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8939
8940               continue;
8941             }
8942
8943           /* If we have (shift (logical)), move the logical to the outside
8944              to allow it to possibly combine with another logical and the
8945              shift to combine with another shift.  This also canonicalizes to
8946              what a ZERO_EXTRACT looks like.  Also, some machines have
8947              (and (shift)) insns.  */
8948
8949           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8950               /* We can't do this if we have (ashiftrt (xor))  and the
8951                  constant has its sign bit set in shift_mode.  */
8952               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8953                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8954                                               shift_mode))
8955               && (new = simplify_const_binary_operation (code, result_mode,
8956                                                          XEXP (varop, 1),
8957                                                          GEN_INT (count))) != 0
8958               && GET_CODE (new) == CONST_INT
8959               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8960                                   INTVAL (new), result_mode, &complement_p))
8961             {
8962               varop = XEXP (varop, 0);
8963               continue;
8964             }
8965
8966           /* If we can't do that, try to simplify the shift in each arm of the
8967              logical expression, make a new logical expression, and apply
8968              the inverse distributive law.  This also can't be done
8969              for some (ashiftrt (xor)).  */
8970           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8971              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8972                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8973                                              shift_mode)))
8974             {
8975               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8976                                               XEXP (varop, 0), count);
8977               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8978                                               XEXP (varop, 1), count);
8979
8980               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8981                                            lhs, rhs);
8982               varop = apply_distributive_law (varop);
8983
8984               count = 0;
8985               continue;
8986             }
8987           break;
8988
8989         case EQ:
8990           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8991              says that the sign bit can be tested, FOO has mode MODE, C is
8992              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8993              that may be nonzero.  */
8994           if (code == LSHIFTRT
8995               && XEXP (varop, 1) == const0_rtx
8996               && GET_MODE (XEXP (varop, 0)) == result_mode
8997               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8998               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8999               && STORE_FLAG_VALUE == -1
9000               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9001               && merge_outer_ops (&outer_op, &outer_const, XOR,
9002                                   (HOST_WIDE_INT) 1, result_mode,
9003                                   &complement_p))
9004             {
9005               varop = XEXP (varop, 0);
9006               count = 0;
9007               continue;
9008             }
9009           break;
9010
9011         case NEG:
9012           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9013              than the number of bits in the mode is equivalent to A.  */
9014           if (code == LSHIFTRT
9015               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9016               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9017             {
9018               varop = XEXP (varop, 0);
9019               count = 0;
9020               continue;
9021             }
9022
9023           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9024              NEG outside to allow shifts to combine.  */
9025           if (code == ASHIFT
9026               && merge_outer_ops (&outer_op, &outer_const, NEG,
9027                                   (HOST_WIDE_INT) 0, result_mode,
9028                                   &complement_p))
9029             {
9030               varop = XEXP (varop, 0);
9031               continue;
9032             }
9033           break;
9034
9035         case PLUS:
9036           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9037              is one less than the number of bits in the mode is
9038              equivalent to (xor A 1).  */
9039           if (code == LSHIFTRT
9040               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9041               && XEXP (varop, 1) == constm1_rtx
9042               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9043               && merge_outer_ops (&outer_op, &outer_const, XOR,
9044                                   (HOST_WIDE_INT) 1, result_mode,
9045                                   &complement_p))
9046             {
9047               count = 0;
9048               varop = XEXP (varop, 0);
9049               continue;
9050             }
9051
9052           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9053              that might be nonzero in BAR are those being shifted out and those
9054              bits are known zero in FOO, we can replace the PLUS with FOO.
9055              Similarly in the other operand order.  This code occurs when
9056              we are computing the size of a variable-size array.  */
9057
9058           if ((code == ASHIFTRT || code == LSHIFTRT)
9059               && count < HOST_BITS_PER_WIDE_INT
9060               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9061               && (nonzero_bits (XEXP (varop, 1), result_mode)
9062                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9063             {
9064               varop = XEXP (varop, 0);
9065               continue;
9066             }
9067           else if ((code == ASHIFTRT || code == LSHIFTRT)
9068                    && count < HOST_BITS_PER_WIDE_INT
9069                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9070                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9071                             >> count)
9072                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9073                             & nonzero_bits (XEXP (varop, 1),
9074                                                  result_mode)))
9075             {
9076               varop = XEXP (varop, 1);
9077               continue;
9078             }
9079
9080           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9081           if (code == ASHIFT
9082               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9083               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9084                                                          XEXP (varop, 1),
9085                                                          GEN_INT (count))) != 0
9086               && GET_CODE (new) == CONST_INT
9087               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9088                                   INTVAL (new), result_mode, &complement_p))
9089             {
9090               varop = XEXP (varop, 0);
9091               continue;
9092             }
9093
9094           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9095              signbit', and attempt to change the PLUS to an XOR and move it to
9096              the outer operation as is done above in the AND/IOR/XOR case
9097              leg for shift(logical). See details in logical handling above
9098              for reasoning in doing so.  */
9099           if (code == LSHIFTRT
9100               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9101               && mode_signbit_p (result_mode, XEXP (varop, 1))
9102               && (new = simplify_const_binary_operation (code, result_mode,
9103                                                          XEXP (varop, 1),
9104                                                          GEN_INT (count))) != 0
9105               && GET_CODE (new) == CONST_INT
9106               && merge_outer_ops (&outer_op, &outer_const, XOR,
9107                                   INTVAL (new), result_mode, &complement_p))
9108             {
9109               varop = XEXP (varop, 0);
9110               continue;
9111             }
9112
9113           break;
9114
9115         case MINUS:
9116           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9117              with C the size of VAROP - 1 and the shift is logical if
9118              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9119              we have a (gt X 0) operation.  If the shift is arithmetic with
9120              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9121              we have a (neg (gt X 0)) operation.  */
9122
9123           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9124               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9125               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9126               && (code == LSHIFTRT || code == ASHIFTRT)
9127               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9128               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9129               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9130             {
9131               count = 0;
9132               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9133                                   const0_rtx);
9134
9135               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9136                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9137
9138               continue;
9139             }
9140           break;
9141
9142         case TRUNCATE:
9143           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9144              if the truncate does not affect the value.  */
9145           if (code == LSHIFTRT
9146               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9147               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9148               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9149                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9150                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9151             {
9152               rtx varop_inner = XEXP (varop, 0);
9153
9154               varop_inner
9155                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9156                                     XEXP (varop_inner, 0),
9157                                     GEN_INT
9158                                     (count + INTVAL (XEXP (varop_inner, 1))));
9159               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9160               count = 0;
9161               continue;
9162             }
9163           break;
9164
9165         default:
9166           break;
9167         }
9168
9169       break;
9170     }
9171
9172   /* We need to determine what mode to do the shift in.  If the shift is
9173      a right shift or ROTATE, we must always do it in the mode it was
9174      originally done in.  Otherwise, we can do it in MODE, the widest mode
9175      encountered.  The code we care about is that of the shift that will
9176      actually be done, not the shift that was originally requested.  */
9177   shift_mode
9178     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9179        ? result_mode : mode);
9180
9181   /* We have now finished analyzing the shift.  The result should be
9182      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9183      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9184      to the result of the shift.  OUTER_CONST is the relevant constant,
9185      but we must turn off all bits turned off in the shift.  */
9186
9187   if (outer_op == UNKNOWN
9188       && orig_code == code && orig_count == count
9189       && varop == orig_varop
9190       && shift_mode == GET_MODE (varop))
9191     return NULL_RTX;
9192
9193   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9194   varop = gen_lowpart (shift_mode, varop);
9195   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9196     return NULL_RTX;
9197
9198   /* If we have an outer operation and we just made a shift, it is
9199      possible that we could have simplified the shift were it not
9200      for the outer operation.  So try to do the simplification
9201      recursively.  */
9202
9203   if (outer_op != UNKNOWN)
9204     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9205   else
9206     x = NULL_RTX;
9207
9208   if (x == NULL_RTX)
9209     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9210
9211   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9212      turn off all the bits that the shift would have turned off.  */
9213   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9214     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9215                                 GET_MODE_MASK (result_mode) >> orig_count);
9216
9217   /* Do the remainder of the processing in RESULT_MODE.  */
9218   x = gen_lowpart_or_truncate (result_mode, x);
9219
9220   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9221      operation.  */
9222   if (complement_p)
9223     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9224
9225   if (outer_op != UNKNOWN)
9226     {
9227       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9228         outer_const = trunc_int_for_mode (outer_const, result_mode);
9229
9230       if (outer_op == AND)
9231         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9232       else if (outer_op == SET)
9233         {
9234           /* This means that we have determined that the result is
9235              equivalent to a constant.  This should be rare.  */
9236           if (!side_effects_p (x))
9237             x = GEN_INT (outer_const);
9238         }
9239       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9240         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9241       else
9242         x = simplify_gen_binary (outer_op, result_mode, x,
9243                                  GEN_INT (outer_const));
9244     }
9245
9246   return x;
9247 }
9248
9249 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9250    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9251    return X or, if it is NULL, synthesize the expression with
9252    simplify_gen_binary.  Otherwise, return a simplified value.
9253
9254    The shift is normally computed in the widest mode we find in VAROP, as
9255    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9256    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9257
9258 static rtx
9259 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9260                       rtx varop, int count)
9261 {
9262   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9263   if (tem)
9264     return tem;
9265
9266   if (!x)
9267     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9268   if (GET_MODE (x) != result_mode)
9269     x = gen_lowpart (result_mode, x);
9270   return x;
9271 }
9272
9273 \f
9274 /* Like recog, but we receive the address of a pointer to a new pattern.
9275    We try to match the rtx that the pointer points to.
9276    If that fails, we may try to modify or replace the pattern,
9277    storing the replacement into the same pointer object.
9278
9279    Modifications include deletion or addition of CLOBBERs.
9280
9281    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9282    the CLOBBERs are placed.
9283
9284    The value is the final insn code from the pattern ultimately matched,
9285    or -1.  */
9286
9287 static int
9288 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9289 {
9290   rtx pat = *pnewpat;
9291   int insn_code_number;
9292   int num_clobbers_to_add = 0;
9293   int i;
9294   rtx notes = 0;
9295   rtx old_notes, old_pat;
9296
9297   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9298      we use to indicate that something didn't match.  If we find such a
9299      thing, force rejection.  */
9300   if (GET_CODE (pat) == PARALLEL)
9301     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9302       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9303           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9304         return -1;
9305
9306   old_pat = PATTERN (insn);
9307   old_notes = REG_NOTES (insn);
9308   PATTERN (insn) = pat;
9309   REG_NOTES (insn) = 0;
9310
9311   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9312
9313   /* If it isn't, there is the possibility that we previously had an insn
9314      that clobbered some register as a side effect, but the combined
9315      insn doesn't need to do that.  So try once more without the clobbers
9316      unless this represents an ASM insn.  */
9317
9318   if (insn_code_number < 0 && ! check_asm_operands (pat)
9319       && GET_CODE (pat) == PARALLEL)
9320     {
9321       int pos;
9322
9323       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9324         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9325           {
9326             if (i != pos)
9327               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9328             pos++;
9329           }
9330
9331       SUBST_INT (XVECLEN (pat, 0), pos);
9332
9333       if (pos == 1)
9334         pat = XVECEXP (pat, 0, 0);
9335
9336       PATTERN (insn) = pat;
9337       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9338     }
9339   PATTERN (insn) = old_pat;
9340   REG_NOTES (insn) = old_notes;
9341
9342   /* Recognize all noop sets, these will be killed by followup pass.  */
9343   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9344     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9345
9346   /* If we had any clobbers to add, make a new pattern than contains
9347      them.  Then check to make sure that all of them are dead.  */
9348   if (num_clobbers_to_add)
9349     {
9350       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9351                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9352                                                   ? (XVECLEN (pat, 0)
9353                                                      + num_clobbers_to_add)
9354                                                   : num_clobbers_to_add + 1));
9355
9356       if (GET_CODE (pat) == PARALLEL)
9357         for (i = 0; i < XVECLEN (pat, 0); i++)
9358           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9359       else
9360         XVECEXP (newpat, 0, 0) = pat;
9361
9362       add_clobbers (newpat, insn_code_number);
9363
9364       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9365            i < XVECLEN (newpat, 0); i++)
9366         {
9367           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9368               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9369             return -1;
9370           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9371                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9372         }
9373       pat = newpat;
9374     }
9375
9376   *pnewpat = pat;
9377   *pnotes = notes;
9378
9379   return insn_code_number;
9380 }
9381 \f
9382 /* Like gen_lowpart_general but for use by combine.  In combine it
9383    is not possible to create any new pseudoregs.  However, it is
9384    safe to create invalid memory addresses, because combine will
9385    try to recognize them and all they will do is make the combine
9386    attempt fail.
9387
9388    If for some reason this cannot do its job, an rtx
9389    (clobber (const_int 0)) is returned.
9390    An insn containing that will not be recognized.  */
9391
9392 static rtx
9393 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9394 {
9395   enum machine_mode imode = GET_MODE (x);
9396   unsigned int osize = GET_MODE_SIZE (omode);
9397   unsigned int isize = GET_MODE_SIZE (imode);
9398   rtx result;
9399
9400   if (omode == imode)
9401     return x;
9402
9403   /* Return identity if this is a CONST or symbolic reference.  */
9404   if (omode == Pmode
9405       && (GET_CODE (x) == CONST
9406           || GET_CODE (x) == SYMBOL_REF
9407           || GET_CODE (x) == LABEL_REF))
9408     return x;
9409
9410   /* We can only support MODE being wider than a word if X is a
9411      constant integer or has a mode the same size.  */
9412   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9413       && ! ((imode == VOIDmode
9414              && (GET_CODE (x) == CONST_INT
9415                  || GET_CODE (x) == CONST_DOUBLE))
9416             || isize == osize))
9417     goto fail;
9418
9419   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9420      won't know what to do.  So we will strip off the SUBREG here and
9421      process normally.  */
9422   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9423     {
9424       x = SUBREG_REG (x);
9425
9426       /* For use in case we fall down into the address adjustments
9427          further below, we need to adjust the known mode and size of
9428          x; imode and isize, since we just adjusted x.  */
9429       imode = GET_MODE (x);
9430
9431       if (imode == omode)
9432         return x;
9433
9434       isize = GET_MODE_SIZE (imode);
9435     }
9436
9437   result = gen_lowpart_common (omode, x);
9438
9439 #ifdef CANNOT_CHANGE_MODE_CLASS
9440   if (result != 0 && GET_CODE (result) == SUBREG)
9441     record_subregs_of_mode (result);
9442 #endif
9443
9444   if (result)
9445     return result;
9446
9447   if (MEM_P (x))
9448     {
9449       int offset = 0;
9450
9451       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9452          address.  */
9453       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9454         goto fail;
9455
9456       /* If we want to refer to something bigger than the original memref,
9457          generate a paradoxical subreg instead.  That will force a reload
9458          of the original memref X.  */
9459       if (isize < osize)
9460         return gen_rtx_SUBREG (omode, x, 0);
9461
9462       if (WORDS_BIG_ENDIAN)
9463         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9464
9465       /* Adjust the address so that the address-after-the-data is
9466          unchanged.  */
9467       if (BYTES_BIG_ENDIAN)
9468         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9469
9470       return adjust_address_nv (x, omode, offset);
9471     }
9472
9473   /* If X is a comparison operator, rewrite it in a new mode.  This
9474      probably won't match, but may allow further simplifications.  */
9475   else if (COMPARISON_P (x))
9476     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9477
9478   /* If we couldn't simplify X any other way, just enclose it in a
9479      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9480      include an explicit SUBREG or we may simplify it further in combine.  */
9481   else
9482     {
9483       int offset = 0;
9484       rtx res;
9485
9486       offset = subreg_lowpart_offset (omode, imode);
9487       if (imode == VOIDmode)
9488         {
9489           imode = int_mode_for_mode (omode);
9490           x = gen_lowpart_common (imode, x);
9491           if (x == NULL)
9492             goto fail;
9493         }
9494       res = simplify_gen_subreg (omode, x, imode, offset);
9495       if (res)
9496         return res;
9497     }
9498
9499  fail:
9500   return gen_rtx_CLOBBER (imode, const0_rtx);
9501 }
9502 \f
9503 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9504    comparison code that will be tested.
9505
9506    The result is a possibly different comparison code to use.  *POP0 and
9507    *POP1 may be updated.
9508
9509    It is possible that we might detect that a comparison is either always
9510    true or always false.  However, we do not perform general constant
9511    folding in combine, so this knowledge isn't useful.  Such tautologies
9512    should have been detected earlier.  Hence we ignore all such cases.  */
9513
9514 static enum rtx_code
9515 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9516 {
9517   rtx op0 = *pop0;
9518   rtx op1 = *pop1;
9519   rtx tem, tem1;
9520   int i;
9521   enum machine_mode mode, tmode;
9522
9523   /* Try a few ways of applying the same transformation to both operands.  */
9524   while (1)
9525     {
9526 #ifndef WORD_REGISTER_OPERATIONS
9527       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9528          so check specially.  */
9529       if (code != GTU && code != GEU && code != LTU && code != LEU
9530           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9531           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9532           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9533           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9534           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9535           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9536               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9537           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9538           && XEXP (op0, 1) == XEXP (op1, 1)
9539           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9540           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9541           && (INTVAL (XEXP (op0, 1))
9542               == (GET_MODE_BITSIZE (GET_MODE (op0))
9543                   - (GET_MODE_BITSIZE
9544                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9545         {
9546           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9547           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9548         }
9549 #endif
9550
9551       /* If both operands are the same constant shift, see if we can ignore the
9552          shift.  We can if the shift is a rotate or if the bits shifted out of
9553          this shift are known to be zero for both inputs and if the type of
9554          comparison is compatible with the shift.  */
9555       if (GET_CODE (op0) == GET_CODE (op1)
9556           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9557           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9558               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9559                   && (code != GT && code != LT && code != GE && code != LE))
9560               || (GET_CODE (op0) == ASHIFTRT
9561                   && (code != GTU && code != LTU
9562                       && code != GEU && code != LEU)))
9563           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9564           && INTVAL (XEXP (op0, 1)) >= 0
9565           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9566           && XEXP (op0, 1) == XEXP (op1, 1))
9567         {
9568           enum machine_mode mode = GET_MODE (op0);
9569           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9570           int shift_count = INTVAL (XEXP (op0, 1));
9571
9572           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9573             mask &= (mask >> shift_count) << shift_count;
9574           else if (GET_CODE (op0) == ASHIFT)
9575             mask = (mask & (mask << shift_count)) >> shift_count;
9576
9577           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9578               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9579             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9580           else
9581             break;
9582         }
9583
9584       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9585          SUBREGs are of the same mode, and, in both cases, the AND would
9586          be redundant if the comparison was done in the narrower mode,
9587          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9588          and the operand's possibly nonzero bits are 0xffffff01; in that case
9589          if we only care about QImode, we don't need the AND).  This case
9590          occurs if the output mode of an scc insn is not SImode and
9591          STORE_FLAG_VALUE == 1 (e.g., the 386).
9592
9593          Similarly, check for a case where the AND's are ZERO_EXTEND
9594          operations from some narrower mode even though a SUBREG is not
9595          present.  */
9596
9597       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9598                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9599                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9600         {
9601           rtx inner_op0 = XEXP (op0, 0);
9602           rtx inner_op1 = XEXP (op1, 0);
9603           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9604           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9605           int changed = 0;
9606
9607           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9608               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9609                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9610               && (GET_MODE (SUBREG_REG (inner_op0))
9611                   == GET_MODE (SUBREG_REG (inner_op1)))
9612               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9613                   <= HOST_BITS_PER_WIDE_INT)
9614               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9615                                              GET_MODE (SUBREG_REG (inner_op0)))))
9616               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9617                                              GET_MODE (SUBREG_REG (inner_op1))))))
9618             {
9619               op0 = SUBREG_REG (inner_op0);
9620               op1 = SUBREG_REG (inner_op1);
9621
9622               /* The resulting comparison is always unsigned since we masked
9623                  off the original sign bit.  */
9624               code = unsigned_condition (code);
9625
9626               changed = 1;
9627             }
9628
9629           else if (c0 == c1)
9630             for (tmode = GET_CLASS_NARROWEST_MODE
9631                  (GET_MODE_CLASS (GET_MODE (op0)));
9632                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9633               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9634                 {
9635                   op0 = gen_lowpart (tmode, inner_op0);
9636                   op1 = gen_lowpart (tmode, inner_op1);
9637                   code = unsigned_condition (code);
9638                   changed = 1;
9639                   break;
9640                 }
9641
9642           if (! changed)
9643             break;
9644         }
9645
9646       /* If both operands are NOT, we can strip off the outer operation
9647          and adjust the comparison code for swapped operands; similarly for
9648          NEG, except that this must be an equality comparison.  */
9649       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9650                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9651                    && (code == EQ || code == NE)))
9652         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9653
9654       else
9655         break;
9656     }
9657
9658   /* If the first operand is a constant, swap the operands and adjust the
9659      comparison code appropriately, but don't do this if the second operand
9660      is already a constant integer.  */
9661   if (swap_commutative_operands_p (op0, op1))
9662     {
9663       tem = op0, op0 = op1, op1 = tem;
9664       code = swap_condition (code);
9665     }
9666
9667   /* We now enter a loop during which we will try to simplify the comparison.
9668      For the most part, we only are concerned with comparisons with zero,
9669      but some things may really be comparisons with zero but not start
9670      out looking that way.  */
9671
9672   while (GET_CODE (op1) == CONST_INT)
9673     {
9674       enum machine_mode mode = GET_MODE (op0);
9675       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9676       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9677       int equality_comparison_p;
9678       int sign_bit_comparison_p;
9679       int unsigned_comparison_p;
9680       HOST_WIDE_INT const_op;
9681
9682       /* We only want to handle integral modes.  This catches VOIDmode,
9683          CCmode, and the floating-point modes.  An exception is that we
9684          can handle VOIDmode if OP0 is a COMPARE or a comparison
9685          operation.  */
9686
9687       if (GET_MODE_CLASS (mode) != MODE_INT
9688           && ! (mode == VOIDmode
9689                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9690         break;
9691
9692       /* Get the constant we are comparing against and turn off all bits
9693          not on in our mode.  */
9694       const_op = INTVAL (op1);
9695       if (mode != VOIDmode)
9696         const_op = trunc_int_for_mode (const_op, mode);
9697       op1 = GEN_INT (const_op);
9698
9699       /* If we are comparing against a constant power of two and the value
9700          being compared can only have that single bit nonzero (e.g., it was
9701          `and'ed with that bit), we can replace this with a comparison
9702          with zero.  */
9703       if (const_op
9704           && (code == EQ || code == NE || code == GE || code == GEU
9705               || code == LT || code == LTU)
9706           && mode_width <= HOST_BITS_PER_WIDE_INT
9707           && exact_log2 (const_op) >= 0
9708           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9709         {
9710           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9711           op1 = const0_rtx, const_op = 0;
9712         }
9713
9714       /* Similarly, if we are comparing a value known to be either -1 or
9715          0 with -1, change it to the opposite comparison against zero.  */
9716
9717       if (const_op == -1
9718           && (code == EQ || code == NE || code == GT || code == LE
9719               || code == GEU || code == LTU)
9720           && num_sign_bit_copies (op0, mode) == mode_width)
9721         {
9722           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9723           op1 = const0_rtx, const_op = 0;
9724         }
9725
9726       /* Do some canonicalizations based on the comparison code.  We prefer
9727          comparisons against zero and then prefer equality comparisons.
9728          If we can reduce the size of a constant, we will do that too.  */
9729
9730       switch (code)
9731         {
9732         case LT:
9733           /* < C is equivalent to <= (C - 1) */
9734           if (const_op > 0)
9735             {
9736               const_op -= 1;
9737               op1 = GEN_INT (const_op);
9738               code = LE;
9739               /* ... fall through to LE case below.  */
9740             }
9741           else
9742             break;
9743
9744         case LE:
9745           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9746           if (const_op < 0)
9747             {
9748               const_op += 1;
9749               op1 = GEN_INT (const_op);
9750               code = LT;
9751             }
9752
9753           /* If we are doing a <= 0 comparison on a value known to have
9754              a zero sign bit, we can replace this with == 0.  */
9755           else if (const_op == 0
9756                    && mode_width <= HOST_BITS_PER_WIDE_INT
9757                    && (nonzero_bits (op0, mode)
9758                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9759             code = EQ;
9760           break;
9761
9762         case GE:
9763           /* >= C is equivalent to > (C - 1).  */
9764           if (const_op > 0)
9765             {
9766               const_op -= 1;
9767               op1 = GEN_INT (const_op);
9768               code = GT;
9769               /* ... fall through to GT below.  */
9770             }
9771           else
9772             break;
9773
9774         case GT:
9775           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9776           if (const_op < 0)
9777             {
9778               const_op += 1;
9779               op1 = GEN_INT (const_op);
9780               code = GE;
9781             }
9782
9783           /* If we are doing a > 0 comparison on a value known to have
9784              a zero sign bit, we can replace this with != 0.  */
9785           else if (const_op == 0
9786                    && mode_width <= HOST_BITS_PER_WIDE_INT
9787                    && (nonzero_bits (op0, mode)
9788                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9789             code = NE;
9790           break;
9791
9792         case LTU:
9793           /* < C is equivalent to <= (C - 1).  */
9794           if (const_op > 0)
9795             {
9796               const_op -= 1;
9797               op1 = GEN_INT (const_op);
9798               code = LEU;
9799               /* ... fall through ...  */
9800             }
9801
9802           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9803           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9804                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9805             {
9806               const_op = 0, op1 = const0_rtx;
9807               code = GE;
9808               break;
9809             }
9810           else
9811             break;
9812
9813         case LEU:
9814           /* unsigned <= 0 is equivalent to == 0 */
9815           if (const_op == 0)
9816             code = EQ;
9817
9818           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9819           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9820                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9821             {
9822               const_op = 0, op1 = const0_rtx;
9823               code = GE;
9824             }
9825           break;
9826
9827         case GEU:
9828           /* >= C is equivalent to > (C - 1).  */
9829           if (const_op > 1)
9830             {
9831               const_op -= 1;
9832               op1 = GEN_INT (const_op);
9833               code = GTU;
9834               /* ... fall through ...  */
9835             }
9836
9837           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9838           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9839                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9840             {
9841               const_op = 0, op1 = const0_rtx;
9842               code = LT;
9843               break;
9844             }
9845           else
9846             break;
9847
9848         case GTU:
9849           /* unsigned > 0 is equivalent to != 0 */
9850           if (const_op == 0)
9851             code = NE;
9852
9853           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9854           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9855                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9856             {
9857               const_op = 0, op1 = const0_rtx;
9858               code = LT;
9859             }
9860           break;
9861
9862         default:
9863           break;
9864         }
9865
9866       /* Compute some predicates to simplify code below.  */
9867
9868       equality_comparison_p = (code == EQ || code == NE);
9869       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9870       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9871                                || code == GEU);
9872
9873       /* If this is a sign bit comparison and we can do arithmetic in
9874          MODE, say that we will only be needing the sign bit of OP0.  */
9875       if (sign_bit_comparison_p
9876           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9877         op0 = force_to_mode (op0, mode,
9878                              ((HOST_WIDE_INT) 1
9879                               << (GET_MODE_BITSIZE (mode) - 1)),
9880                              0);
9881
9882       /* Now try cases based on the opcode of OP0.  If none of the cases
9883          does a "continue", we exit this loop immediately after the
9884          switch.  */
9885
9886       switch (GET_CODE (op0))
9887         {
9888         case ZERO_EXTRACT:
9889           /* If we are extracting a single bit from a variable position in
9890              a constant that has only a single bit set and are comparing it
9891              with zero, we can convert this into an equality comparison
9892              between the position and the location of the single bit.  */
9893           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9894              have already reduced the shift count modulo the word size.  */
9895           if (!SHIFT_COUNT_TRUNCATED
9896               && GET_CODE (XEXP (op0, 0)) == CONST_INT
9897               && XEXP (op0, 1) == const1_rtx
9898               && equality_comparison_p && const_op == 0
9899               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9900             {
9901               if (BITS_BIG_ENDIAN)
9902                 {
9903                   enum machine_mode new_mode
9904                     = mode_for_extraction (EP_extzv, 1);
9905                   if (new_mode == MAX_MACHINE_MODE)
9906                     i = BITS_PER_WORD - 1 - i;
9907                   else
9908                     {
9909                       mode = new_mode;
9910                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
9911                     }
9912                 }
9913
9914               op0 = XEXP (op0, 2);
9915               op1 = GEN_INT (i);
9916               const_op = i;
9917
9918               /* Result is nonzero iff shift count is equal to I.  */
9919               code = reverse_condition (code);
9920               continue;
9921             }
9922
9923           /* ... fall through ...  */
9924
9925         case SIGN_EXTRACT:
9926           tem = expand_compound_operation (op0);
9927           if (tem != op0)
9928             {
9929               op0 = tem;
9930               continue;
9931             }
9932           break;
9933
9934         case NOT:
9935           /* If testing for equality, we can take the NOT of the constant.  */
9936           if (equality_comparison_p
9937               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9938             {
9939               op0 = XEXP (op0, 0);
9940               op1 = tem;
9941               continue;
9942             }
9943
9944           /* If just looking at the sign bit, reverse the sense of the
9945              comparison.  */
9946           if (sign_bit_comparison_p)
9947             {
9948               op0 = XEXP (op0, 0);
9949               code = (code == GE ? LT : GE);
9950               continue;
9951             }
9952           break;
9953
9954         case NEG:
9955           /* If testing for equality, we can take the NEG of the constant.  */
9956           if (equality_comparison_p
9957               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9958             {
9959               op0 = XEXP (op0, 0);
9960               op1 = tem;
9961               continue;
9962             }
9963
9964           /* The remaining cases only apply to comparisons with zero.  */
9965           if (const_op != 0)
9966             break;
9967
9968           /* When X is ABS or is known positive,
9969              (neg X) is < 0 if and only if X != 0.  */
9970
9971           if (sign_bit_comparison_p
9972               && (GET_CODE (XEXP (op0, 0)) == ABS
9973                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9974                       && (nonzero_bits (XEXP (op0, 0), mode)
9975                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9976             {
9977               op0 = XEXP (op0, 0);
9978               code = (code == LT ? NE : EQ);
9979               continue;
9980             }
9981
9982           /* If we have NEG of something whose two high-order bits are the
9983              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9984           if (num_sign_bit_copies (op0, mode) >= 2)
9985             {
9986               op0 = XEXP (op0, 0);
9987               code = swap_condition (code);
9988               continue;
9989             }
9990           break;
9991
9992         case ROTATE:
9993           /* If we are testing equality and our count is a constant, we
9994              can perform the inverse operation on our RHS.  */
9995           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9996               && (tem = simplify_binary_operation (ROTATERT, mode,
9997                                                    op1, XEXP (op0, 1))) != 0)
9998             {
9999               op0 = XEXP (op0, 0);
10000               op1 = tem;
10001               continue;
10002             }
10003
10004           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10005              a particular bit.  Convert it to an AND of a constant of that
10006              bit.  This will be converted into a ZERO_EXTRACT.  */
10007           if (const_op == 0 && sign_bit_comparison_p
10008               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10009               && mode_width <= HOST_BITS_PER_WIDE_INT)
10010             {
10011               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10012                                             ((HOST_WIDE_INT) 1
10013                                              << (mode_width - 1
10014                                                  - INTVAL (XEXP (op0, 1)))));
10015               code = (code == LT ? NE : EQ);
10016               continue;
10017             }
10018
10019           /* Fall through.  */
10020
10021         case ABS:
10022           /* ABS is ignorable inside an equality comparison with zero.  */
10023           if (const_op == 0 && equality_comparison_p)
10024             {
10025               op0 = XEXP (op0, 0);
10026               continue;
10027             }
10028           break;
10029
10030         case SIGN_EXTEND:
10031           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10032              (compare FOO CONST) if CONST fits in FOO's mode and we
10033              are either testing inequality or have an unsigned
10034              comparison with ZERO_EXTEND or a signed comparison with
10035              SIGN_EXTEND.  But don't do it if we don't have a compare
10036              insn of the given mode, since we'd have to revert it
10037              later on, and then we wouldn't know whether to sign- or
10038              zero-extend.  */
10039           mode = GET_MODE (XEXP (op0, 0));
10040           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10041               && ! unsigned_comparison_p
10042               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10043               && ((unsigned HOST_WIDE_INT) const_op
10044                   < (((unsigned HOST_WIDE_INT) 1
10045                       << (GET_MODE_BITSIZE (mode) - 1))))
10046               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10047             {
10048               op0 = XEXP (op0, 0);
10049               continue;
10050             }
10051           break;
10052
10053         case SUBREG:
10054           /* Check for the case where we are comparing A - C1 with C2, that is
10055
10056                (subreg:MODE (plus (A) (-C1))) op (C2)
10057
10058              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10059              comparison in the wider mode.  One of the following two conditions
10060              must be true in order for this to be valid:
10061
10062                1. The mode extension results in the same bit pattern being added
10063                   on both sides and the comparison is equality or unsigned.  As
10064                   C2 has been truncated to fit in MODE, the pattern can only be
10065                   all 0s or all 1s.
10066
10067                2. The mode extension results in the sign bit being copied on
10068                   each side.
10069
10070              The difficulty here is that we have predicates for A but not for
10071              (A - C1) so we need to check that C1 is within proper bounds so
10072              as to perturbate A as little as possible.  */
10073
10074           if (mode_width <= HOST_BITS_PER_WIDE_INT
10075               && subreg_lowpart_p (op0)
10076               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10077               && GET_CODE (SUBREG_REG (op0)) == PLUS
10078               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10079             {
10080               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10081               rtx a = XEXP (SUBREG_REG (op0), 0);
10082               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10083
10084               if ((c1 > 0
10085                    && (unsigned HOST_WIDE_INT) c1
10086                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10087                    && (equality_comparison_p || unsigned_comparison_p)
10088                    /* (A - C1) zero-extends if it is positive and sign-extends
10089                       if it is negative, C2 both zero- and sign-extends.  */
10090                    && ((0 == (nonzero_bits (a, inner_mode)
10091                               & ~GET_MODE_MASK (mode))
10092                         && const_op >= 0)
10093                        /* (A - C1) sign-extends if it is positive and 1-extends
10094                           if it is negative, C2 both sign- and 1-extends.  */
10095                        || (num_sign_bit_copies (a, inner_mode)
10096                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10097                                              - mode_width)
10098                            && const_op < 0)))
10099                   || ((unsigned HOST_WIDE_INT) c1
10100                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10101                       /* (A - C1) always sign-extends, like C2.  */
10102                       && num_sign_bit_copies (a, inner_mode)
10103                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10104                                            - (mode_width - 1))))
10105                 {
10106                   op0 = SUBREG_REG (op0);
10107                   continue;
10108                 }
10109             }
10110
10111           /* If the inner mode is narrower and we are extracting the low part,
10112              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10113           if (subreg_lowpart_p (op0)
10114               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10115             /* Fall through */ ;
10116           else
10117             break;
10118
10119           /* ... fall through ...  */
10120
10121         case ZERO_EXTEND:
10122           mode = GET_MODE (XEXP (op0, 0));
10123           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10124               && (unsigned_comparison_p || equality_comparison_p)
10125               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10126               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10127               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10128             {
10129               op0 = XEXP (op0, 0);
10130               continue;
10131             }
10132           break;
10133
10134         case PLUS:
10135           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10136              this for equality comparisons due to pathological cases involving
10137              overflows.  */
10138           if (equality_comparison_p
10139               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10140                                                         op1, XEXP (op0, 1))))
10141             {
10142               op0 = XEXP (op0, 0);
10143               op1 = tem;
10144               continue;
10145             }
10146
10147           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10148           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10149               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10150             {
10151               op0 = XEXP (XEXP (op0, 0), 0);
10152               code = (code == LT ? EQ : NE);
10153               continue;
10154             }
10155           break;
10156
10157         case MINUS:
10158           /* We used to optimize signed comparisons against zero, but that
10159              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10160              arrive here as equality comparisons, or (GEU, LTU) are
10161              optimized away.  No need to special-case them.  */
10162
10163           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10164              (eq B (minus A C)), whichever simplifies.  We can only do
10165              this for equality comparisons due to pathological cases involving
10166              overflows.  */
10167           if (equality_comparison_p
10168               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10169                                                         XEXP (op0, 1), op1)))
10170             {
10171               op0 = XEXP (op0, 0);
10172               op1 = tem;
10173               continue;
10174             }
10175
10176           if (equality_comparison_p
10177               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10178                                                         XEXP (op0, 0), op1)))
10179             {
10180               op0 = XEXP (op0, 1);
10181               op1 = tem;
10182               continue;
10183             }
10184
10185           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10186              of bits in X minus 1, is one iff X > 0.  */
10187           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10188               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10189               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10190                  == mode_width - 1
10191               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10192             {
10193               op0 = XEXP (op0, 1);
10194               code = (code == GE ? LE : GT);
10195               continue;
10196             }
10197           break;
10198
10199         case XOR:
10200           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10201              if C is zero or B is a constant.  */
10202           if (equality_comparison_p
10203               && 0 != (tem = simplify_binary_operation (XOR, mode,
10204                                                         XEXP (op0, 1), op1)))
10205             {
10206               op0 = XEXP (op0, 0);
10207               op1 = tem;
10208               continue;
10209             }
10210           break;
10211
10212         case EQ:  case NE:
10213         case UNEQ:  case LTGT:
10214         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10215         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10216         case UNORDERED: case ORDERED:
10217           /* We can't do anything if OP0 is a condition code value, rather
10218              than an actual data value.  */
10219           if (const_op != 0
10220               || CC0_P (XEXP (op0, 0))
10221               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10222             break;
10223
10224           /* Get the two operands being compared.  */
10225           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10226             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10227           else
10228             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10229
10230           /* Check for the cases where we simply want the result of the
10231              earlier test or the opposite of that result.  */
10232           if (code == NE || code == EQ
10233               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10234                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10235                   && (STORE_FLAG_VALUE
10236                       & (((HOST_WIDE_INT) 1
10237                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10238                   && (code == LT || code == GE)))
10239             {
10240               enum rtx_code new_code;
10241               if (code == LT || code == NE)
10242                 new_code = GET_CODE (op0);
10243               else
10244                 new_code = reversed_comparison_code (op0, NULL);
10245
10246               if (new_code != UNKNOWN)
10247                 {
10248                   code = new_code;
10249                   op0 = tem;
10250                   op1 = tem1;
10251                   continue;
10252                 }
10253             }
10254           break;
10255
10256         case IOR:
10257           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10258              iff X <= 0.  */
10259           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10260               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10261               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10262             {
10263               op0 = XEXP (op0, 1);
10264               code = (code == GE ? GT : LE);
10265               continue;
10266             }
10267           break;
10268
10269         case AND:
10270           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10271              will be converted to a ZERO_EXTRACT later.  */
10272           if (const_op == 0 && equality_comparison_p
10273               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10274               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10275             {
10276               op0 = simplify_and_const_int
10277                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10278                                                    XEXP (op0, 1),
10279                                                    XEXP (XEXP (op0, 0), 1)),
10280                  (HOST_WIDE_INT) 1);
10281               continue;
10282             }
10283
10284           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10285              zero and X is a comparison and C1 and C2 describe only bits set
10286              in STORE_FLAG_VALUE, we can compare with X.  */
10287           if (const_op == 0 && equality_comparison_p
10288               && mode_width <= HOST_BITS_PER_WIDE_INT
10289               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10290               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10291               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10292               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10293               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10294             {
10295               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10296                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10297               if ((~STORE_FLAG_VALUE & mask) == 0
10298                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10299                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10300                           && COMPARISON_P (tem))))
10301                 {
10302                   op0 = XEXP (XEXP (op0, 0), 0);
10303                   continue;
10304                 }
10305             }
10306
10307           /* If we are doing an equality comparison of an AND of a bit equal
10308              to the sign bit, replace this with a LT or GE comparison of
10309              the underlying value.  */
10310           if (equality_comparison_p
10311               && const_op == 0
10312               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10313               && mode_width <= HOST_BITS_PER_WIDE_INT
10314               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10315                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10316             {
10317               op0 = XEXP (op0, 0);
10318               code = (code == EQ ? GE : LT);
10319               continue;
10320             }
10321
10322           /* If this AND operation is really a ZERO_EXTEND from a narrower
10323              mode, the constant fits within that mode, and this is either an
10324              equality or unsigned comparison, try to do this comparison in
10325              the narrower mode.
10326
10327              Note that in:
10328
10329              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10330              -> (ne:DI (reg:SI 4) (const_int 0))
10331
10332              unless TRULY_NOOP_TRUNCATION allows it or the register is
10333              known to hold a value of the required mode the
10334              transformation is invalid.  */
10335           if ((equality_comparison_p || unsigned_comparison_p)
10336               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10337               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10338                                    & GET_MODE_MASK (mode))
10339                                   + 1)) >= 0
10340               && const_op >> i == 0
10341               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10342               && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10343                                          GET_MODE_BITSIZE (GET_MODE (op0)))
10344                   || (REG_P (XEXP (op0, 0))
10345                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10346             {
10347               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10348               continue;
10349             }
10350
10351           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10352              fits in both M1 and M2 and the SUBREG is either paradoxical
10353              or represents the low part, permute the SUBREG and the AND
10354              and try again.  */
10355           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10356             {
10357               unsigned HOST_WIDE_INT c1;
10358               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10359               /* Require an integral mode, to avoid creating something like
10360                  (AND:SF ...).  */
10361               if (SCALAR_INT_MODE_P (tmode)
10362                   /* It is unsafe to commute the AND into the SUBREG if the
10363                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10364                      not defined.  As originally written the upper bits
10365                      have a defined value due to the AND operation.
10366                      However, if we commute the AND inside the SUBREG then
10367                      they no longer have defined values and the meaning of
10368                      the code has been changed.  */
10369                   && (0
10370 #ifdef WORD_REGISTER_OPERATIONS
10371                       || (mode_width > GET_MODE_BITSIZE (tmode)
10372                           && mode_width <= BITS_PER_WORD)
10373 #endif
10374                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10375                           && subreg_lowpart_p (XEXP (op0, 0))))
10376                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10377                   && mode_width <= HOST_BITS_PER_WIDE_INT
10378                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10379                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10380                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10381                   && c1 != mask
10382                   && c1 != GET_MODE_MASK (tmode))
10383                 {
10384                   op0 = simplify_gen_binary (AND, tmode,
10385                                              SUBREG_REG (XEXP (op0, 0)),
10386                                              gen_int_mode (c1, tmode));
10387                   op0 = gen_lowpart (mode, op0);
10388                   continue;
10389                 }
10390             }
10391
10392           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10393           if (const_op == 0 && equality_comparison_p
10394               && XEXP (op0, 1) == const1_rtx
10395               && GET_CODE (XEXP (op0, 0)) == NOT)
10396             {
10397               op0 = simplify_and_const_int
10398                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10399               code = (code == NE ? EQ : NE);
10400               continue;
10401             }
10402
10403           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10404              (eq (and (lshiftrt X) 1) 0).
10405              Also handle the case where (not X) is expressed using xor.  */
10406           if (const_op == 0 && equality_comparison_p
10407               && XEXP (op0, 1) == const1_rtx
10408               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10409             {
10410               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10411               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10412
10413               if (GET_CODE (shift_op) == NOT
10414                   || (GET_CODE (shift_op) == XOR
10415                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10416                       && GET_CODE (shift_count) == CONST_INT
10417                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10418                       && (INTVAL (XEXP (shift_op, 1))
10419                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10420                 {
10421                   op0 = simplify_and_const_int
10422                     (NULL_RTX, mode,
10423                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10424                      (HOST_WIDE_INT) 1);
10425                   code = (code == NE ? EQ : NE);
10426                   continue;
10427                 }
10428             }
10429           break;
10430
10431         case ASHIFT:
10432           /* If we have (compare (ashift FOO N) (const_int C)) and
10433              the high order N bits of FOO (N+1 if an inequality comparison)
10434              are known to be zero, we can do this by comparing FOO with C
10435              shifted right N bits so long as the low-order N bits of C are
10436              zero.  */
10437           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10438               && INTVAL (XEXP (op0, 1)) >= 0
10439               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10440                   < HOST_BITS_PER_WIDE_INT)
10441               && ((const_op
10442                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10443               && mode_width <= HOST_BITS_PER_WIDE_INT
10444               && (nonzero_bits (XEXP (op0, 0), mode)
10445                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10446                                + ! equality_comparison_p))) == 0)
10447             {
10448               /* We must perform a logical shift, not an arithmetic one,
10449                  as we want the top N bits of C to be zero.  */
10450               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10451
10452               temp >>= INTVAL (XEXP (op0, 1));
10453               op1 = gen_int_mode (temp, mode);
10454               op0 = XEXP (op0, 0);
10455               continue;
10456             }
10457
10458           /* If we are doing a sign bit comparison, it means we are testing
10459              a particular bit.  Convert it to the appropriate AND.  */
10460           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10461               && mode_width <= HOST_BITS_PER_WIDE_INT)
10462             {
10463               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10464                                             ((HOST_WIDE_INT) 1
10465                                              << (mode_width - 1
10466                                                  - INTVAL (XEXP (op0, 1)))));
10467               code = (code == LT ? NE : EQ);
10468               continue;
10469             }
10470
10471           /* If this an equality comparison with zero and we are shifting
10472              the low bit to the sign bit, we can convert this to an AND of the
10473              low-order bit.  */
10474           if (const_op == 0 && equality_comparison_p
10475               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10476               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10477                  == mode_width - 1)
10478             {
10479               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10480                                             (HOST_WIDE_INT) 1);
10481               continue;
10482             }
10483           break;
10484
10485         case ASHIFTRT:
10486           /* If this is an equality comparison with zero, we can do this
10487              as a logical shift, which might be much simpler.  */
10488           if (equality_comparison_p && const_op == 0
10489               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10490             {
10491               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10492                                           XEXP (op0, 0),
10493                                           INTVAL (XEXP (op0, 1)));
10494               continue;
10495             }
10496
10497           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10498              do the comparison in a narrower mode.  */
10499           if (! unsigned_comparison_p
10500               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10501               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10502               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10503               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10504                                          MODE_INT, 1)) != BLKmode
10505               && (((unsigned HOST_WIDE_INT) const_op
10506                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10507                   <= GET_MODE_MASK (tmode)))
10508             {
10509               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10510               continue;
10511             }
10512
10513           /* Likewise if OP0 is a PLUS of a sign extension with a
10514              constant, which is usually represented with the PLUS
10515              between the shifts.  */
10516           if (! unsigned_comparison_p
10517               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10518               && GET_CODE (XEXP (op0, 0)) == PLUS
10519               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10520               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10521               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10522               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10523                                          MODE_INT, 1)) != BLKmode
10524               && (((unsigned HOST_WIDE_INT) const_op
10525                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10526                   <= GET_MODE_MASK (tmode)))
10527             {
10528               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10529               rtx add_const = XEXP (XEXP (op0, 0), 1);
10530               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10531                                                    add_const, XEXP (op0, 1));
10532
10533               op0 = simplify_gen_binary (PLUS, tmode,
10534                                          gen_lowpart (tmode, inner),
10535                                          new_const);
10536               continue;
10537             }
10538
10539           /* ... fall through ...  */
10540         case LSHIFTRT:
10541           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10542              the low order N bits of FOO are known to be zero, we can do this
10543              by comparing FOO with C shifted left N bits so long as no
10544              overflow occurs.  */
10545           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10546               && INTVAL (XEXP (op0, 1)) >= 0
10547               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10548               && mode_width <= HOST_BITS_PER_WIDE_INT
10549               && (nonzero_bits (XEXP (op0, 0), mode)
10550                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10551               && (((unsigned HOST_WIDE_INT) const_op
10552                    + (GET_CODE (op0) != LSHIFTRT
10553                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10554                          + 1)
10555                       : 0))
10556                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10557             {
10558               /* If the shift was logical, then we must make the condition
10559                  unsigned.  */
10560               if (GET_CODE (op0) == LSHIFTRT)
10561                 code = unsigned_condition (code);
10562
10563               const_op <<= INTVAL (XEXP (op0, 1));
10564               op1 = GEN_INT (const_op);
10565               op0 = XEXP (op0, 0);
10566               continue;
10567             }
10568
10569           /* If we are using this shift to extract just the sign bit, we
10570              can replace this with an LT or GE comparison.  */
10571           if (const_op == 0
10572               && (equality_comparison_p || sign_bit_comparison_p)
10573               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10574               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10575                  == mode_width - 1)
10576             {
10577               op0 = XEXP (op0, 0);
10578               code = (code == NE || code == GT ? LT : GE);
10579               continue;
10580             }
10581           break;
10582
10583         default:
10584           break;
10585         }
10586
10587       break;
10588     }
10589
10590   /* Now make any compound operations involved in this comparison.  Then,
10591      check for an outmost SUBREG on OP0 that is not doing anything or is
10592      paradoxical.  The latter transformation must only be performed when
10593      it is known that the "extra" bits will be the same in op0 and op1 or
10594      that they don't matter.  There are three cases to consider:
10595
10596      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10597      care bits and we can assume they have any convenient value.  So
10598      making the transformation is safe.
10599
10600      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10601      In this case the upper bits of op0 are undefined.  We should not make
10602      the simplification in that case as we do not know the contents of
10603      those bits.
10604
10605      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10606      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10607      also be sure that they are the same as the upper bits of op1.
10608
10609      We can never remove a SUBREG for a non-equality comparison because
10610      the sign bit is in a different place in the underlying object.  */
10611
10612   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10613   op1 = make_compound_operation (op1, SET);
10614
10615   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10616       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10617       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10618       && (code == NE || code == EQ))
10619     {
10620       if (GET_MODE_SIZE (GET_MODE (op0))
10621           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10622         {
10623           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10624              implemented.  */
10625           if (REG_P (SUBREG_REG (op0)))
10626             {
10627               op0 = SUBREG_REG (op0);
10628               op1 = gen_lowpart (GET_MODE (op0), op1);
10629             }
10630         }
10631       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10632                 <= HOST_BITS_PER_WIDE_INT)
10633                && (nonzero_bits (SUBREG_REG (op0),
10634                                  GET_MODE (SUBREG_REG (op0)))
10635                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10636         {
10637           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10638
10639           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10640                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10641             op0 = SUBREG_REG (op0), op1 = tem;
10642         }
10643     }
10644
10645   /* We now do the opposite procedure: Some machines don't have compare
10646      insns in all modes.  If OP0's mode is an integer mode smaller than a
10647      word and we can't do a compare in that mode, see if there is a larger
10648      mode for which we can do the compare.  There are a number of cases in
10649      which we can use the wider mode.  */
10650
10651   mode = GET_MODE (op0);
10652   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10653       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10654       && ! have_insn_for (COMPARE, mode))
10655     for (tmode = GET_MODE_WIDER_MODE (mode);
10656          (tmode != VOIDmode
10657           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10658          tmode = GET_MODE_WIDER_MODE (tmode))
10659       if (have_insn_for (COMPARE, tmode))
10660         {
10661           int zero_extended;
10662
10663           /* If the only nonzero bits in OP0 and OP1 are those in the
10664              narrower mode and this is an equality or unsigned comparison,
10665              we can use the wider mode.  Similarly for sign-extended
10666              values, in which case it is true for all comparisons.  */
10667           zero_extended = ((code == EQ || code == NE
10668                             || code == GEU || code == GTU
10669                             || code == LEU || code == LTU)
10670                            && (nonzero_bits (op0, tmode)
10671                                & ~GET_MODE_MASK (mode)) == 0
10672                            && ((GET_CODE (op1) == CONST_INT
10673                                 || (nonzero_bits (op1, tmode)
10674                                     & ~GET_MODE_MASK (mode)) == 0)));
10675
10676           if (zero_extended
10677               || ((num_sign_bit_copies (op0, tmode)
10678                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10679                                      - GET_MODE_BITSIZE (mode)))
10680                   && (num_sign_bit_copies (op1, tmode)
10681                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10682                                         - GET_MODE_BITSIZE (mode)))))
10683             {
10684               /* If OP0 is an AND and we don't have an AND in MODE either,
10685                  make a new AND in the proper mode.  */
10686               if (GET_CODE (op0) == AND
10687                   && !have_insn_for (AND, mode))
10688                 op0 = simplify_gen_binary (AND, tmode,
10689                                            gen_lowpart (tmode,
10690                                                         XEXP (op0, 0)),
10691                                            gen_lowpart (tmode,
10692                                                         XEXP (op0, 1)));
10693
10694               op0 = gen_lowpart (tmode, op0);
10695               if (zero_extended && GET_CODE (op1) == CONST_INT)
10696                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10697               op1 = gen_lowpart (tmode, op1);
10698               break;
10699             }
10700
10701           /* If this is a test for negative, we can make an explicit
10702              test of the sign bit.  */
10703
10704           if (op1 == const0_rtx && (code == LT || code == GE)
10705               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10706             {
10707               op0 = simplify_gen_binary (AND, tmode,
10708                                          gen_lowpart (tmode, op0),
10709                                          GEN_INT ((HOST_WIDE_INT) 1
10710                                                   << (GET_MODE_BITSIZE (mode)
10711                                                       - 1)));
10712               code = (code == LT) ? NE : EQ;
10713               break;
10714             }
10715         }
10716
10717 #ifdef CANONICALIZE_COMPARISON
10718   /* If this machine only supports a subset of valid comparisons, see if we
10719      can convert an unsupported one into a supported one.  */
10720   CANONICALIZE_COMPARISON (code, op0, op1);
10721 #endif
10722
10723   *pop0 = op0;
10724   *pop1 = op1;
10725
10726   return code;
10727 }
10728 \f
10729 /* Utility function for record_value_for_reg.  Count number of
10730    rtxs in X.  */
10731 static int
10732 count_rtxs (rtx x)
10733 {
10734   enum rtx_code code = GET_CODE (x);
10735   const char *fmt;
10736   int i, ret = 1;
10737
10738   if (GET_RTX_CLASS (code) == '2'
10739       || GET_RTX_CLASS (code) == 'c')
10740     {
10741       rtx x0 = XEXP (x, 0);
10742       rtx x1 = XEXP (x, 1);
10743
10744       if (x0 == x1)
10745         return 1 + 2 * count_rtxs (x0);
10746
10747       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10748            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10749           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10750         return 2 + 2 * count_rtxs (x0)
10751                + count_rtxs (x == XEXP (x1, 0)
10752                              ? XEXP (x1, 1) : XEXP (x1, 0));
10753
10754       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10755            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10756           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10757         return 2 + 2 * count_rtxs (x1)
10758                + count_rtxs (x == XEXP (x0, 0)
10759                              ? XEXP (x0, 1) : XEXP (x0, 0));
10760     }
10761
10762   fmt = GET_RTX_FORMAT (code);
10763   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10764     if (fmt[i] == 'e')
10765       ret += count_rtxs (XEXP (x, i));
10766
10767   return ret;
10768 }
10769 \f
10770 /* Utility function for following routine.  Called when X is part of a value
10771    being stored into last_set_value.  Sets last_set_table_tick
10772    for each register mentioned.  Similar to mention_regs in cse.c  */
10773
10774 static void
10775 update_table_tick (rtx x)
10776 {
10777   enum rtx_code code = GET_CODE (x);
10778   const char *fmt = GET_RTX_FORMAT (code);
10779   int i;
10780
10781   if (code == REG)
10782     {
10783       unsigned int regno = REGNO (x);
10784       unsigned int endregno
10785         = regno + (regno < FIRST_PSEUDO_REGISTER
10786                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10787       unsigned int r;
10788
10789       for (r = regno; r < endregno; r++)
10790         reg_stat[r].last_set_table_tick = label_tick;
10791
10792       return;
10793     }
10794
10795   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10796     /* Note that we can't have an "E" in values stored; see
10797        get_last_value_validate.  */
10798     if (fmt[i] == 'e')
10799       {
10800         /* Check for identical subexpressions.  If x contains
10801            identical subexpression we only have to traverse one of
10802            them.  */
10803         if (i == 0 && ARITHMETIC_P (x))
10804           {
10805             /* Note that at this point x1 has already been
10806                processed.  */
10807             rtx x0 = XEXP (x, 0);
10808             rtx x1 = XEXP (x, 1);
10809
10810             /* If x0 and x1 are identical then there is no need to
10811                process x0.  */
10812             if (x0 == x1)
10813               break;
10814
10815             /* If x0 is identical to a subexpression of x1 then while
10816                processing x1, x0 has already been processed.  Thus we
10817                are done with x.  */
10818             if (ARITHMETIC_P (x1)
10819                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10820               break;
10821
10822             /* If x1 is identical to a subexpression of x0 then we
10823                still have to process the rest of x0.  */
10824             if (ARITHMETIC_P (x0)
10825                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10826               {
10827                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10828                 break;
10829               }
10830           }
10831
10832         update_table_tick (XEXP (x, i));
10833       }
10834 }
10835
10836 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10837    are saying that the register is clobbered and we no longer know its
10838    value.  If INSN is zero, don't update reg_stat[].last_set; this is
10839    only permitted with VALUE also zero and is used to invalidate the
10840    register.  */
10841
10842 static void
10843 record_value_for_reg (rtx reg, rtx insn, rtx value)
10844 {
10845   unsigned int regno = REGNO (reg);
10846   unsigned int endregno
10847     = regno + (regno < FIRST_PSEUDO_REGISTER
10848                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10849   unsigned int i;
10850
10851   /* If VALUE contains REG and we have a previous value for REG, substitute
10852      the previous value.  */
10853   if (value && insn && reg_overlap_mentioned_p (reg, value))
10854     {
10855       rtx tem;
10856
10857       /* Set things up so get_last_value is allowed to see anything set up to
10858          our insn.  */
10859       subst_low_cuid = INSN_CUID (insn);
10860       tem = get_last_value (reg);
10861
10862       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10863          it isn't going to be useful and will take a lot of time to process,
10864          so just use the CLOBBER.  */
10865
10866       if (tem)
10867         {
10868           if (ARITHMETIC_P (tem)
10869               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10870               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10871             tem = XEXP (tem, 0);
10872           else if (count_occurrences (value, reg, 1) >= 2)
10873             {
10874               /* If there are two or more occurrences of REG in VALUE,
10875                  prevent the value from growing too much.  */
10876               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10877                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10878             }
10879
10880           value = replace_rtx (copy_rtx (value), reg, tem);
10881         }
10882     }
10883
10884   /* For each register modified, show we don't know its value, that
10885      we don't know about its bitwise content, that its value has been
10886      updated, and that we don't know the location of the death of the
10887      register.  */
10888   for (i = regno; i < endregno; i++)
10889     {
10890       if (insn)
10891         reg_stat[i].last_set = insn;
10892
10893       reg_stat[i].last_set_value = 0;
10894       reg_stat[i].last_set_mode = 0;
10895       reg_stat[i].last_set_nonzero_bits = 0;
10896       reg_stat[i].last_set_sign_bit_copies = 0;
10897       reg_stat[i].last_death = 0;
10898       reg_stat[i].truncated_to_mode = 0;
10899     }
10900
10901   /* Mark registers that are being referenced in this value.  */
10902   if (value)
10903     update_table_tick (value);
10904
10905   /* Now update the status of each register being set.
10906      If someone is using this register in this block, set this register
10907      to invalid since we will get confused between the two lives in this
10908      basic block.  This makes using this register always invalid.  In cse, we
10909      scan the table to invalidate all entries using this register, but this
10910      is too much work for us.  */
10911
10912   for (i = regno; i < endregno; i++)
10913     {
10914       reg_stat[i].last_set_label = label_tick;
10915       if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10916         reg_stat[i].last_set_invalid = 1;
10917       else
10918         reg_stat[i].last_set_invalid = 0;
10919     }
10920
10921   /* The value being assigned might refer to X (like in "x++;").  In that
10922      case, we must replace it with (clobber (const_int 0)) to prevent
10923      infinite loops.  */
10924   if (value && ! get_last_value_validate (&value, insn,
10925                                           reg_stat[regno].last_set_label, 0))
10926     {
10927       value = copy_rtx (value);
10928       if (! get_last_value_validate (&value, insn,
10929                                      reg_stat[regno].last_set_label, 1))
10930         value = 0;
10931     }
10932
10933   /* For the main register being modified, update the value, the mode, the
10934      nonzero bits, and the number of sign bit copies.  */
10935
10936   reg_stat[regno].last_set_value = value;
10937
10938   if (value)
10939     {
10940       enum machine_mode mode = GET_MODE (reg);
10941       subst_low_cuid = INSN_CUID (insn);
10942       reg_stat[regno].last_set_mode = mode;
10943       if (GET_MODE_CLASS (mode) == MODE_INT
10944           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10945         mode = nonzero_bits_mode;
10946       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10947       reg_stat[regno].last_set_sign_bit_copies
10948         = num_sign_bit_copies (value, GET_MODE (reg));
10949     }
10950 }
10951
10952 /* Called via note_stores from record_dead_and_set_regs to handle one
10953    SET or CLOBBER in an insn.  DATA is the instruction in which the
10954    set is occurring.  */
10955
10956 static void
10957 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10958 {
10959   rtx record_dead_insn = (rtx) data;
10960
10961   if (GET_CODE (dest) == SUBREG)
10962     dest = SUBREG_REG (dest);
10963
10964   if (!record_dead_insn)
10965     {
10966       if (REG_P (dest))
10967         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10968       return;
10969     }
10970
10971   if (REG_P (dest))
10972     {
10973       /* If we are setting the whole register, we know its value.  Otherwise
10974          show that we don't know the value.  We can handle SUBREG in
10975          some cases.  */
10976       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10977         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10978       else if (GET_CODE (setter) == SET
10979                && GET_CODE (SET_DEST (setter)) == SUBREG
10980                && SUBREG_REG (SET_DEST (setter)) == dest
10981                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10982                && subreg_lowpart_p (SET_DEST (setter)))
10983         record_value_for_reg (dest, record_dead_insn,
10984                               gen_lowpart (GET_MODE (dest),
10985                                                        SET_SRC (setter)));
10986       else
10987         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10988     }
10989   else if (MEM_P (dest)
10990            /* Ignore pushes, they clobber nothing.  */
10991            && ! push_operand (dest, GET_MODE (dest)))
10992     mem_last_set = INSN_CUID (record_dead_insn);
10993 }
10994
10995 /* Update the records of when each REG was most recently set or killed
10996    for the things done by INSN.  This is the last thing done in processing
10997    INSN in the combiner loop.
10998
10999    We update reg_stat[], in particular fields last_set, last_set_value,
11000    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11001    last_death, and also the similar information mem_last_set (which insn
11002    most recently modified memory) and last_call_cuid (which insn was the
11003    most recent subroutine call).  */
11004
11005 static void
11006 record_dead_and_set_regs (rtx insn)
11007 {
11008   rtx link;
11009   unsigned int i;
11010
11011   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11012     {
11013       if (REG_NOTE_KIND (link) == REG_DEAD
11014           && REG_P (XEXP (link, 0)))
11015         {
11016           unsigned int regno = REGNO (XEXP (link, 0));
11017           unsigned int endregno
11018             = regno + (regno < FIRST_PSEUDO_REGISTER
11019                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11020                        : 1);
11021
11022           for (i = regno; i < endregno; i++)
11023             reg_stat[i].last_death = insn;
11024         }
11025       else if (REG_NOTE_KIND (link) == REG_INC)
11026         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11027     }
11028
11029   if (CALL_P (insn))
11030     {
11031       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11032         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11033           {
11034             reg_stat[i].last_set_value = 0;
11035             reg_stat[i].last_set_mode = 0;
11036             reg_stat[i].last_set_nonzero_bits = 0;
11037             reg_stat[i].last_set_sign_bit_copies = 0;
11038             reg_stat[i].last_death = 0;
11039             reg_stat[i].truncated_to_mode = 0;
11040           }
11041
11042       last_call_cuid = mem_last_set = INSN_CUID (insn);
11043
11044       /* We can't combine into a call pattern.  Remember, though, that
11045          the return value register is set at this CUID.  We could
11046          still replace a register with the return value from the
11047          wrong subroutine call!  */
11048       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11049     }
11050   else
11051     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11052 }
11053
11054 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11055    register present in the SUBREG, so for each such SUBREG go back and
11056    adjust nonzero and sign bit information of the registers that are
11057    known to have some zero/sign bits set.
11058
11059    This is needed because when combine blows the SUBREGs away, the
11060    information on zero/sign bits is lost and further combines can be
11061    missed because of that.  */
11062
11063 static void
11064 record_promoted_value (rtx insn, rtx subreg)
11065 {
11066   rtx links, set;
11067   unsigned int regno = REGNO (SUBREG_REG (subreg));
11068   enum machine_mode mode = GET_MODE (subreg);
11069
11070   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11071     return;
11072
11073   for (links = LOG_LINKS (insn); links;)
11074     {
11075       insn = XEXP (links, 0);
11076       set = single_set (insn);
11077
11078       if (! set || !REG_P (SET_DEST (set))
11079           || REGNO (SET_DEST (set)) != regno
11080           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11081         {
11082           links = XEXP (links, 1);
11083           continue;
11084         }
11085
11086       if (reg_stat[regno].last_set == insn)
11087         {
11088           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11089             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11090         }
11091
11092       if (REG_P (SET_SRC (set)))
11093         {
11094           regno = REGNO (SET_SRC (set));
11095           links = LOG_LINKS (insn);
11096         }
11097       else
11098         break;
11099     }
11100 }
11101
11102 /* Check if X, a register, is known to contain a value already
11103    truncated to MODE.  In this case we can use a subreg to refer to
11104    the truncated value even though in the generic case we would need
11105    an explicit truncation.  */
11106
11107 static bool
11108 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11109 {
11110   enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11111
11112   if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11113     return false;
11114   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11115     return true;
11116   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11117                              GET_MODE_BITSIZE (truncated)))
11118     return true;
11119   return false;
11120 }
11121
11122 /* X is a REG or a SUBREG.  If X is some sort of a truncation record
11123    it.  For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11124    a truncate into a subreg using this information.  */
11125
11126 static void
11127 record_truncated_value (rtx x)
11128 {
11129   enum machine_mode truncated_mode;
11130
11131   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11132     {
11133       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11134       truncated_mode = GET_MODE (x);
11135
11136       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11137         return;
11138
11139       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11140                                  GET_MODE_BITSIZE (original_mode)))
11141         return;
11142
11143       x = SUBREG_REG (x);
11144     }
11145   /* ??? For hard-regs we now record everything.  We might be able to
11146      optimize this using last_set_mode.  */
11147   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11148     truncated_mode = GET_MODE (x);
11149   else
11150     return;
11151
11152   if (reg_stat[REGNO (x)].truncated_to_mode == 0
11153       || reg_stat[REGNO (x)].truncation_label < label_tick
11154       || (GET_MODE_SIZE (truncated_mode)
11155           < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11156     {
11157       reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11158       reg_stat[REGNO (x)].truncation_label = label_tick;
11159     }
11160 }
11161
11162 /* Scan X for promoted SUBREGs and truncated REGs.  For each one
11163    found, note what it implies to the registers used in it.  */
11164
11165 static void
11166 check_conversions (rtx insn, rtx x)
11167 {
11168   if (GET_CODE (x) == SUBREG || REG_P (x))
11169     {
11170       if (GET_CODE (x) == SUBREG
11171           && SUBREG_PROMOTED_VAR_P (x)
11172           && REG_P (SUBREG_REG (x)))
11173         record_promoted_value (insn, x);
11174
11175       record_truncated_value (x);
11176     }
11177   else
11178     {
11179       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11180       int i, j;
11181
11182       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11183         switch (format[i])
11184           {
11185           case 'e':
11186             check_conversions (insn, XEXP (x, i));
11187             break;
11188           case 'V':
11189           case 'E':
11190             if (XVEC (x, i) != 0)
11191               for (j = 0; j < XVECLEN (x, i); j++)
11192                 check_conversions (insn, XVECEXP (x, i, j));
11193             break;
11194           }
11195     }
11196 }
11197 \f
11198 /* Utility routine for the following function.  Verify that all the registers
11199    mentioned in *LOC are valid when *LOC was part of a value set when
11200    label_tick == TICK.  Return 0 if some are not.
11201
11202    If REPLACE is nonzero, replace the invalid reference with
11203    (clobber (const_int 0)) and return 1.  This replacement is useful because
11204    we often can get useful information about the form of a value (e.g., if
11205    it was produced by a shift that always produces -1 or 0) even though
11206    we don't know exactly what registers it was produced from.  */
11207
11208 static int
11209 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11210 {
11211   rtx x = *loc;
11212   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11213   int len = GET_RTX_LENGTH (GET_CODE (x));
11214   int i;
11215
11216   if (REG_P (x))
11217     {
11218       unsigned int regno = REGNO (x);
11219       unsigned int endregno
11220         = regno + (regno < FIRST_PSEUDO_REGISTER
11221                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11222       unsigned int j;
11223
11224       for (j = regno; j < endregno; j++)
11225         if (reg_stat[j].last_set_invalid
11226             /* If this is a pseudo-register that was only set once and not
11227                live at the beginning of the function, it is always valid.  */
11228             || (! (regno >= FIRST_PSEUDO_REGISTER
11229                    && REG_N_SETS (regno) == 1
11230                    && (! REGNO_REG_SET_P
11231                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11232                         regno)))
11233                 && reg_stat[j].last_set_label > tick))
11234           {
11235             if (replace)
11236               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11237             return replace;
11238           }
11239
11240       return 1;
11241     }
11242   /* If this is a memory reference, make sure that there were
11243      no stores after it that might have clobbered the value.  We don't
11244      have alias info, so we assume any store invalidates it.  */
11245   else if (MEM_P (x) && !MEM_READONLY_P (x)
11246            && INSN_CUID (insn) <= mem_last_set)
11247     {
11248       if (replace)
11249         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11250       return replace;
11251     }
11252
11253   for (i = 0; i < len; i++)
11254     {
11255       if (fmt[i] == 'e')
11256         {
11257           /* Check for identical subexpressions.  If x contains
11258              identical subexpression we only have to traverse one of
11259              them.  */
11260           if (i == 1 && ARITHMETIC_P (x))
11261             {
11262               /* Note that at this point x0 has already been checked
11263                  and found valid.  */
11264               rtx x0 = XEXP (x, 0);
11265               rtx x1 = XEXP (x, 1);
11266
11267               /* If x0 and x1 are identical then x is also valid.  */
11268               if (x0 == x1)
11269                 return 1;
11270
11271               /* If x1 is identical to a subexpression of x0 then
11272                  while checking x0, x1 has already been checked.  Thus
11273                  it is valid and so as x.  */
11274               if (ARITHMETIC_P (x0)
11275                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11276                 return 1;
11277
11278               /* If x0 is identical to a subexpression of x1 then x is
11279                  valid iff the rest of x1 is valid.  */
11280               if (ARITHMETIC_P (x1)
11281                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11282                 return
11283                   get_last_value_validate (&XEXP (x1,
11284                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11285                                            insn, tick, replace);
11286             }
11287
11288           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11289                                        replace) == 0)
11290             return 0;
11291         }
11292       /* Don't bother with these.  They shouldn't occur anyway.  */
11293       else if (fmt[i] == 'E')
11294         return 0;
11295     }
11296
11297   /* If we haven't found a reason for it to be invalid, it is valid.  */
11298   return 1;
11299 }
11300
11301 /* Get the last value assigned to X, if known.  Some registers
11302    in the value may be replaced with (clobber (const_int 0)) if their value
11303    is known longer known reliably.  */
11304
11305 static rtx
11306 get_last_value (rtx x)
11307 {
11308   unsigned int regno;
11309   rtx value;
11310
11311   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11312      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11313      we cannot predict what values the "extra" bits might have.  */
11314   if (GET_CODE (x) == SUBREG
11315       && subreg_lowpart_p (x)
11316       && (GET_MODE_SIZE (GET_MODE (x))
11317           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11318       && (value = get_last_value (SUBREG_REG (x))) != 0)
11319     return gen_lowpart (GET_MODE (x), value);
11320
11321   if (!REG_P (x))
11322     return 0;
11323
11324   regno = REGNO (x);
11325   value = reg_stat[regno].last_set_value;
11326
11327   /* If we don't have a value, or if it isn't for this basic block and
11328      it's either a hard register, set more than once, or it's a live
11329      at the beginning of the function, return 0.
11330
11331      Because if it's not live at the beginning of the function then the reg
11332      is always set before being used (is never used without being set).
11333      And, if it's set only once, and it's always set before use, then all
11334      uses must have the same last value, even if it's not from this basic
11335      block.  */
11336
11337   if (value == 0
11338       || (reg_stat[regno].last_set_label != label_tick
11339           && (regno < FIRST_PSEUDO_REGISTER
11340               || REG_N_SETS (regno) != 1
11341               || (REGNO_REG_SET_P
11342                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11343                    regno)))))
11344     return 0;
11345
11346   /* If the value was set in a later insn than the ones we are processing,
11347      we can't use it even if the register was only set once.  */
11348   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11349     return 0;
11350
11351   /* If the value has all its registers valid, return it.  */
11352   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11353                                reg_stat[regno].last_set_label, 0))
11354     return value;
11355
11356   /* Otherwise, make a copy and replace any invalid register with
11357      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11358
11359   value = copy_rtx (value);
11360   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11361                                reg_stat[regno].last_set_label, 1))
11362     return value;
11363
11364   return 0;
11365 }
11366 \f
11367 /* Return nonzero if expression X refers to a REG or to memory
11368    that is set in an instruction more recent than FROM_CUID.  */
11369
11370 static int
11371 use_crosses_set_p (rtx x, int from_cuid)
11372 {
11373   const char *fmt;
11374   int i;
11375   enum rtx_code code = GET_CODE (x);
11376
11377   if (code == REG)
11378     {
11379       unsigned int regno = REGNO (x);
11380       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11381                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11382
11383 #ifdef PUSH_ROUNDING
11384       /* Don't allow uses of the stack pointer to be moved,
11385          because we don't know whether the move crosses a push insn.  */
11386       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11387         return 1;
11388 #endif
11389       for (; regno < endreg; regno++)
11390         if (reg_stat[regno].last_set
11391             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11392           return 1;
11393       return 0;
11394     }
11395
11396   if (code == MEM && mem_last_set > from_cuid)
11397     return 1;
11398
11399   fmt = GET_RTX_FORMAT (code);
11400
11401   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11402     {
11403       if (fmt[i] == 'E')
11404         {
11405           int j;
11406           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11407             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11408               return 1;
11409         }
11410       else if (fmt[i] == 'e'
11411                && use_crosses_set_p (XEXP (x, i), from_cuid))
11412         return 1;
11413     }
11414   return 0;
11415 }
11416 \f
11417 /* Define three variables used for communication between the following
11418    routines.  */
11419
11420 static unsigned int reg_dead_regno, reg_dead_endregno;
11421 static int reg_dead_flag;
11422
11423 /* Function called via note_stores from reg_dead_at_p.
11424
11425    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11426    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11427
11428 static void
11429 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11430 {
11431   unsigned int regno, endregno;
11432
11433   if (!REG_P (dest))
11434     return;
11435
11436   regno = REGNO (dest);
11437   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11438                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11439
11440   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11441     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11442 }
11443
11444 /* Return nonzero if REG is known to be dead at INSN.
11445
11446    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11447    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11448    live.  Otherwise, see if it is live or dead at the start of the basic
11449    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11450    must be assumed to be always live.  */
11451
11452 static int
11453 reg_dead_at_p (rtx reg, rtx insn)
11454 {
11455   basic_block block;
11456   unsigned int i;
11457
11458   /* Set variables for reg_dead_at_p_1.  */
11459   reg_dead_regno = REGNO (reg);
11460   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11461                                         ? hard_regno_nregs[reg_dead_regno]
11462                                                           [GET_MODE (reg)]
11463                                         : 1);
11464
11465   reg_dead_flag = 0;
11466
11467   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11468      we allow the machine description to decide whether use-and-clobber
11469      patterns are OK.  */
11470   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11471     {
11472       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11473         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11474           return 0;
11475     }
11476
11477   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11478      beginning of function.  */
11479   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11480        insn = prev_nonnote_insn (insn))
11481     {
11482       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11483       if (reg_dead_flag)
11484         return reg_dead_flag == 1 ? 1 : 0;
11485
11486       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11487         return 1;
11488     }
11489
11490   /* Get the basic block that we were in.  */
11491   if (insn == 0)
11492     block = ENTRY_BLOCK_PTR->next_bb;
11493   else
11494     {
11495       FOR_EACH_BB (block)
11496         if (insn == BB_HEAD (block))
11497           break;
11498
11499       if (block == EXIT_BLOCK_PTR)
11500         return 0;
11501     }
11502
11503   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11504     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11505       return 0;
11506
11507   return 1;
11508 }
11509 \f
11510 /* Note hard registers in X that are used.  This code is similar to
11511    that in flow.c, but much simpler since we don't care about pseudos.  */
11512
11513 static void
11514 mark_used_regs_combine (rtx x)
11515 {
11516   RTX_CODE code = GET_CODE (x);
11517   unsigned int regno;
11518   int i;
11519
11520   switch (code)
11521     {
11522     case LABEL_REF:
11523     case SYMBOL_REF:
11524     case CONST_INT:
11525     case CONST:
11526     case CONST_DOUBLE:
11527     case CONST_VECTOR:
11528     case PC:
11529     case ADDR_VEC:
11530     case ADDR_DIFF_VEC:
11531     case ASM_INPUT:
11532 #ifdef HAVE_cc0
11533     /* CC0 must die in the insn after it is set, so we don't need to take
11534        special note of it here.  */
11535     case CC0:
11536 #endif
11537       return;
11538
11539     case CLOBBER:
11540       /* If we are clobbering a MEM, mark any hard registers inside the
11541          address as used.  */
11542       if (MEM_P (XEXP (x, 0)))
11543         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11544       return;
11545
11546     case REG:
11547       regno = REGNO (x);
11548       /* A hard reg in a wide mode may really be multiple registers.
11549          If so, mark all of them just like the first.  */
11550       if (regno < FIRST_PSEUDO_REGISTER)
11551         {
11552           unsigned int endregno, r;
11553
11554           /* None of this applies to the stack, frame or arg pointers.  */
11555           if (regno == STACK_POINTER_REGNUM
11556 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11557               || regno == HARD_FRAME_POINTER_REGNUM
11558 #endif
11559 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11560               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11561 #endif
11562               || regno == FRAME_POINTER_REGNUM)
11563             return;
11564
11565           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11566           for (r = regno; r < endregno; r++)
11567             SET_HARD_REG_BIT (newpat_used_regs, r);
11568         }
11569       return;
11570
11571     case SET:
11572       {
11573         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11574            the address.  */
11575         rtx testreg = SET_DEST (x);
11576
11577         while (GET_CODE (testreg) == SUBREG
11578                || GET_CODE (testreg) == ZERO_EXTRACT
11579                || GET_CODE (testreg) == STRICT_LOW_PART)
11580           testreg = XEXP (testreg, 0);
11581
11582         if (MEM_P (testreg))
11583           mark_used_regs_combine (XEXP (testreg, 0));
11584
11585         mark_used_regs_combine (SET_SRC (x));
11586       }
11587       return;
11588
11589     default:
11590       break;
11591     }
11592
11593   /* Recursively scan the operands of this expression.  */
11594
11595   {
11596     const char *fmt = GET_RTX_FORMAT (code);
11597
11598     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11599       {
11600         if (fmt[i] == 'e')
11601           mark_used_regs_combine (XEXP (x, i));
11602         else if (fmt[i] == 'E')
11603           {
11604             int j;
11605
11606             for (j = 0; j < XVECLEN (x, i); j++)
11607               mark_used_regs_combine (XVECEXP (x, i, j));
11608           }
11609       }
11610   }
11611 }
11612 \f
11613 /* Remove register number REGNO from the dead registers list of INSN.
11614
11615    Return the note used to record the death, if there was one.  */
11616
11617 rtx
11618 remove_death (unsigned int regno, rtx insn)
11619 {
11620   rtx note = find_regno_note (insn, REG_DEAD, regno);
11621
11622   if (note)
11623     {
11624       REG_N_DEATHS (regno)--;
11625       remove_note (insn, note);
11626     }
11627
11628   return note;
11629 }
11630
11631 /* For each register (hardware or pseudo) used within expression X, if its
11632    death is in an instruction with cuid between FROM_CUID (inclusive) and
11633    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11634    list headed by PNOTES.
11635
11636    That said, don't move registers killed by maybe_kill_insn.
11637
11638    This is done when X is being merged by combination into TO_INSN.  These
11639    notes will then be distributed as needed.  */
11640
11641 static void
11642 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11643              rtx *pnotes)
11644 {
11645   const char *fmt;
11646   int len, i;
11647   enum rtx_code code = GET_CODE (x);
11648
11649   if (code == REG)
11650     {
11651       unsigned int regno = REGNO (x);
11652       rtx where_dead = reg_stat[regno].last_death;
11653       rtx before_dead, after_dead;
11654
11655       /* Don't move the register if it gets killed in between from and to.  */
11656       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11657           && ! reg_referenced_p (x, maybe_kill_insn))
11658         return;
11659
11660       /* WHERE_DEAD could be a USE insn made by combine, so first we
11661          make sure that we have insns with valid INSN_CUID values.  */
11662       before_dead = where_dead;
11663       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11664         before_dead = PREV_INSN (before_dead);
11665
11666       after_dead = where_dead;
11667       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11668         after_dead = NEXT_INSN (after_dead);
11669
11670       if (before_dead && after_dead
11671           && INSN_CUID (before_dead) >= from_cuid
11672           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11673               || (where_dead != after_dead
11674                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11675         {
11676           rtx note = remove_death (regno, where_dead);
11677
11678           /* It is possible for the call above to return 0.  This can occur
11679              when last_death points to I2 or I1 that we combined with.
11680              In that case make a new note.
11681
11682              We must also check for the case where X is a hard register
11683              and NOTE is a death note for a range of hard registers
11684              including X.  In that case, we must put REG_DEAD notes for
11685              the remaining registers in place of NOTE.  */
11686
11687           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11688               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11689                   > GET_MODE_SIZE (GET_MODE (x))))
11690             {
11691               unsigned int deadregno = REGNO (XEXP (note, 0));
11692               unsigned int deadend
11693                 = (deadregno + hard_regno_nregs[deadregno]
11694                                                [GET_MODE (XEXP (note, 0))]);
11695               unsigned int ourend
11696                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11697               unsigned int i;
11698
11699               for (i = deadregno; i < deadend; i++)
11700                 if (i < regno || i >= ourend)
11701                   REG_NOTES (where_dead)
11702                     = gen_rtx_EXPR_LIST (REG_DEAD,
11703                                          regno_reg_rtx[i],
11704                                          REG_NOTES (where_dead));
11705             }
11706
11707           /* If we didn't find any note, or if we found a REG_DEAD note that
11708              covers only part of the given reg, and we have a multi-reg hard
11709              register, then to be safe we must check for REG_DEAD notes
11710              for each register other than the first.  They could have
11711              their own REG_DEAD notes lying around.  */
11712           else if ((note == 0
11713                     || (note != 0
11714                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11715                             < GET_MODE_SIZE (GET_MODE (x)))))
11716                    && regno < FIRST_PSEUDO_REGISTER
11717                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11718             {
11719               unsigned int ourend
11720                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11721               unsigned int i, offset;
11722               rtx oldnotes = 0;
11723
11724               if (note)
11725                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11726               else
11727                 offset = 1;
11728
11729               for (i = regno + offset; i < ourend; i++)
11730                 move_deaths (regno_reg_rtx[i],
11731                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11732             }
11733
11734           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11735             {
11736               XEXP (note, 1) = *pnotes;
11737               *pnotes = note;
11738             }
11739           else
11740             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11741
11742           REG_N_DEATHS (regno)++;
11743         }
11744
11745       return;
11746     }
11747
11748   else if (GET_CODE (x) == SET)
11749     {
11750       rtx dest = SET_DEST (x);
11751
11752       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11753
11754       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11755          that accesses one word of a multi-word item, some
11756          piece of everything register in the expression is used by
11757          this insn, so remove any old death.  */
11758       /* ??? So why do we test for equality of the sizes?  */
11759
11760       if (GET_CODE (dest) == ZERO_EXTRACT
11761           || GET_CODE (dest) == STRICT_LOW_PART
11762           || (GET_CODE (dest) == SUBREG
11763               && (((GET_MODE_SIZE (GET_MODE (dest))
11764                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11765                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11766                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11767         {
11768           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11769           return;
11770         }
11771
11772       /* If this is some other SUBREG, we know it replaces the entire
11773          value, so use that as the destination.  */
11774       if (GET_CODE (dest) == SUBREG)
11775         dest = SUBREG_REG (dest);
11776
11777       /* If this is a MEM, adjust deaths of anything used in the address.
11778          For a REG (the only other possibility), the entire value is
11779          being replaced so the old value is not used in this insn.  */
11780
11781       if (MEM_P (dest))
11782         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11783                      to_insn, pnotes);
11784       return;
11785     }
11786
11787   else if (GET_CODE (x) == CLOBBER)
11788     return;
11789
11790   len = GET_RTX_LENGTH (code);
11791   fmt = GET_RTX_FORMAT (code);
11792
11793   for (i = 0; i < len; i++)
11794     {
11795       if (fmt[i] == 'E')
11796         {
11797           int j;
11798           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11799             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11800                          to_insn, pnotes);
11801         }
11802       else if (fmt[i] == 'e')
11803         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11804     }
11805 }
11806 \f
11807 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11808    pattern of an insn.  X must be a REG.  */
11809
11810 static int
11811 reg_bitfield_target_p (rtx x, rtx body)
11812 {
11813   int i;
11814
11815   if (GET_CODE (body) == SET)
11816     {
11817       rtx dest = SET_DEST (body);
11818       rtx target;
11819       unsigned int regno, tregno, endregno, endtregno;
11820
11821       if (GET_CODE (dest) == ZERO_EXTRACT)
11822         target = XEXP (dest, 0);
11823       else if (GET_CODE (dest) == STRICT_LOW_PART)
11824         target = SUBREG_REG (XEXP (dest, 0));
11825       else
11826         return 0;
11827
11828       if (GET_CODE (target) == SUBREG)
11829         target = SUBREG_REG (target);
11830
11831       if (!REG_P (target))
11832         return 0;
11833
11834       tregno = REGNO (target), regno = REGNO (x);
11835       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11836         return target == x;
11837
11838       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11839       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11840
11841       return endregno > tregno && regno < endtregno;
11842     }
11843
11844   else if (GET_CODE (body) == PARALLEL)
11845     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11846       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11847         return 1;
11848
11849   return 0;
11850 }
11851 \f
11852 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11853    as appropriate.  I3 and I2 are the insns resulting from the combination
11854    insns including FROM (I2 may be zero).
11855
11856    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11857    not need REG_DEAD notes because they are being substituted for.  This
11858    saves searching in the most common cases.
11859
11860    Each note in the list is either ignored or placed on some insns, depending
11861    on the type of note.  */
11862
11863 static void
11864 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11865                   rtx elim_i1)
11866 {
11867   rtx note, next_note;
11868   rtx tem;
11869
11870   for (note = notes; note; note = next_note)
11871     {
11872       rtx place = 0, place2 = 0;
11873
11874       next_note = XEXP (note, 1);
11875       switch (REG_NOTE_KIND (note))
11876         {
11877         case REG_BR_PROB:
11878         case REG_BR_PRED:
11879           /* Doesn't matter much where we put this, as long as it's somewhere.
11880              It is preferable to keep these notes on branches, which is most
11881              likely to be i3.  */
11882           place = i3;
11883           break;
11884
11885         case REG_VALUE_PROFILE:
11886           /* Just get rid of this note, as it is unused later anyway.  */
11887           break;
11888
11889         case REG_NON_LOCAL_GOTO:
11890           if (JUMP_P (i3))
11891             place = i3;
11892           else
11893             {
11894               gcc_assert (i2 && JUMP_P (i2));
11895               place = i2;
11896             }
11897           break;
11898
11899         case REG_EH_REGION:
11900           /* These notes must remain with the call or trapping instruction.  */
11901           if (CALL_P (i3))
11902             place = i3;
11903           else if (i2 && CALL_P (i2))
11904             place = i2;
11905           else
11906             {
11907               gcc_assert (flag_non_call_exceptions);
11908               if (may_trap_p (i3))
11909                 place = i3;
11910               else if (i2 && may_trap_p (i2))
11911                 place = i2;
11912               /* ??? Otherwise assume we've combined things such that we
11913                  can now prove that the instructions can't trap.  Drop the
11914                  note in this case.  */
11915             }
11916           break;
11917
11918         case REG_NORETURN:
11919         case REG_SETJMP:
11920           /* These notes must remain with the call.  It should not be
11921              possible for both I2 and I3 to be a call.  */
11922           if (CALL_P (i3))
11923             place = i3;
11924           else
11925             {
11926               gcc_assert (i2 && CALL_P (i2));
11927               place = i2;
11928             }
11929           break;
11930
11931         case REG_UNUSED:
11932           /* Any clobbers for i3 may still exist, and so we must process
11933              REG_UNUSED notes from that insn.
11934
11935              Any clobbers from i2 or i1 can only exist if they were added by
11936              recog_for_combine.  In that case, recog_for_combine created the
11937              necessary REG_UNUSED notes.  Trying to keep any original
11938              REG_UNUSED notes from these insns can cause incorrect output
11939              if it is for the same register as the original i3 dest.
11940              In that case, we will notice that the register is set in i3,
11941              and then add a REG_UNUSED note for the destination of i3, which
11942              is wrong.  However, it is possible to have REG_UNUSED notes from
11943              i2 or i1 for register which were both used and clobbered, so
11944              we keep notes from i2 or i1 if they will turn into REG_DEAD
11945              notes.  */
11946
11947           /* If this register is set or clobbered in I3, put the note there
11948              unless there is one already.  */
11949           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11950             {
11951               if (from_insn != i3)
11952                 break;
11953
11954               if (! (REG_P (XEXP (note, 0))
11955                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11956                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11957                 place = i3;
11958             }
11959           /* Otherwise, if this register is used by I3, then this register
11960              now dies here, so we must put a REG_DEAD note here unless there
11961              is one already.  */
11962           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11963                    && ! (REG_P (XEXP (note, 0))
11964                          ? find_regno_note (i3, REG_DEAD,
11965                                             REGNO (XEXP (note, 0)))
11966                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11967             {
11968               PUT_REG_NOTE_KIND (note, REG_DEAD);
11969               place = i3;
11970             }
11971           break;
11972
11973         case REG_EQUAL:
11974         case REG_EQUIV:
11975         case REG_NOALIAS:
11976           /* These notes say something about results of an insn.  We can
11977              only support them if they used to be on I3 in which case they
11978              remain on I3.  Otherwise they are ignored.
11979
11980              If the note refers to an expression that is not a constant, we
11981              must also ignore the note since we cannot tell whether the
11982              equivalence is still true.  It might be possible to do
11983              slightly better than this (we only have a problem if I2DEST
11984              or I1DEST is present in the expression), but it doesn't
11985              seem worth the trouble.  */
11986
11987           if (from_insn == i3
11988               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11989             place = i3;
11990           break;
11991
11992         case REG_INC:
11993         case REG_NO_CONFLICT:
11994           /* These notes say something about how a register is used.  They must
11995              be present on any use of the register in I2 or I3.  */
11996           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11997             place = i3;
11998
11999           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12000             {
12001               if (place)
12002                 place2 = i2;
12003               else
12004                 place = i2;
12005             }
12006           break;
12007
12008         case REG_LABEL:
12009           /* This can show up in several ways -- either directly in the
12010              pattern, or hidden off in the constant pool with (or without?)
12011              a REG_EQUAL note.  */
12012           /* ??? Ignore the without-reg_equal-note problem for now.  */
12013           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12014               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12015                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12016                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12017             place = i3;
12018
12019           if (i2
12020               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12021                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12022                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12023                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12024             {
12025               if (place)
12026                 place2 = i2;
12027               else
12028                 place = i2;
12029             }
12030
12031           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
12032              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
12033           if (place && JUMP_P (place))
12034             {
12035               rtx label = JUMP_LABEL (place);
12036
12037               if (!label)
12038                 JUMP_LABEL (place) = XEXP (note, 0);
12039               else
12040                 {
12041                   gcc_assert (label == XEXP (note, 0));
12042                   if (LABEL_P (label))
12043                     LABEL_NUSES (label)--;
12044                 }
12045               place = 0;
12046             }
12047           if (place2 && JUMP_P (place2))
12048             {
12049               rtx label = JUMP_LABEL (place2);
12050
12051               if (!label)
12052                 JUMP_LABEL (place2) = XEXP (note, 0);
12053               else
12054                 {
12055                   gcc_assert (label == XEXP (note, 0));
12056                   if (LABEL_P (label))
12057                     LABEL_NUSES (label)--;
12058                 }
12059               place2 = 0;
12060             }
12061           break;
12062
12063         case REG_NONNEG:
12064           /* This note says something about the value of a register prior
12065              to the execution of an insn.  It is too much trouble to see
12066              if the note is still correct in all situations.  It is better
12067              to simply delete it.  */
12068           break;
12069
12070         case REG_RETVAL:
12071           /* If the insn previously containing this note still exists,
12072              put it back where it was.  Otherwise move it to the previous
12073              insn.  Adjust the corresponding REG_LIBCALL note.  */
12074           if (!NOTE_P (from_insn))
12075             place = from_insn;
12076           else
12077             {
12078               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12079               place = prev_real_insn (from_insn);
12080               if (tem && place)
12081                 XEXP (tem, 0) = place;
12082               /* If we're deleting the last remaining instruction of a
12083                  libcall sequence, don't add the notes.  */
12084               else if (XEXP (note, 0) == from_insn)
12085                 tem = place = 0;
12086               /* Don't add the dangling REG_RETVAL note.  */
12087               else if (! tem)
12088                 place = 0;
12089             }
12090           break;
12091
12092         case REG_LIBCALL:
12093           /* This is handled similarly to REG_RETVAL.  */
12094           if (!NOTE_P (from_insn))
12095             place = from_insn;
12096           else
12097             {
12098               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12099               place = next_real_insn (from_insn);
12100               if (tem && place)
12101                 XEXP (tem, 0) = place;
12102               /* If we're deleting the last remaining instruction of a
12103                  libcall sequence, don't add the notes.  */
12104               else if (XEXP (note, 0) == from_insn)
12105                 tem = place = 0;
12106               /* Don't add the dangling REG_LIBCALL note.  */
12107               else if (! tem)
12108                 place = 0;
12109             }
12110           break;
12111
12112         case REG_DEAD:
12113           /* If we replaced the right hand side of FROM_INSN with a
12114              REG_EQUAL note, the original use of the dying register
12115              will not have been combined into I3 and I2.  In such cases,
12116              FROM_INSN is guaranteed to be the first of the combined
12117              instructions, so we simply need to search back before
12118              FROM_INSN for the previous use or set of this register,
12119              then alter the notes there appropriately.
12120
12121              If the register is used as an input in I3, it dies there.
12122              Similarly for I2, if it is nonzero and adjacent to I3.
12123
12124              If the register is not used as an input in either I3 or I2
12125              and it is not one of the registers we were supposed to eliminate,
12126              there are two possibilities.  We might have a non-adjacent I2
12127              or we might have somehow eliminated an additional register
12128              from a computation.  For example, we might have had A & B where
12129              we discover that B will always be zero.  In this case we will
12130              eliminate the reference to A.
12131
12132              In both cases, we must search to see if we can find a previous
12133              use of A and put the death note there.  */
12134
12135           if (from_insn
12136               && from_insn == replaced_rhs_insn
12137               && !reg_overlap_mentioned_p (XEXP (note, 0), replaced_rhs_value))
12138             tem = from_insn;
12139           else
12140             {
12141               if (from_insn
12142                   && CALL_P (from_insn)
12143                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12144                 place = from_insn;
12145               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12146                 place = i3;
12147               else if (i2 != 0 && next_nonnote_insn (i2) == i3
12148                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12149                 place = i2;
12150               else if (rtx_equal_p (XEXP (note, 0), elim_i2)
12151                        || rtx_equal_p (XEXP (note, 0), elim_i1))
12152                 break;
12153               tem = i3;
12154             }
12155
12156           if (place == 0)
12157             {
12158               basic_block bb = this_basic_block;
12159
12160               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12161                 {
12162                   if (! INSN_P (tem))
12163                     {
12164                       if (tem == BB_HEAD (bb))
12165                         break;
12166                       continue;
12167                     }
12168
12169                   /* If TEM is a (reaching) definition of the use to which the
12170                      note was attached, see if that is all TEM is doing.  If so,
12171                      delete TEM.  Otherwise, make this into a REG_UNUSED note
12172                      instead.  Don't delete sets to global register vars.  */
12173                   if ((!from_insn
12174                        || INSN_CUID (tem) < INSN_CUID (from_insn))
12175                       && (REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12176                           || !global_regs[REGNO (XEXP (note, 0))])
12177                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12178                     {
12179                       rtx set = single_set (tem);
12180                       rtx inner_dest = 0;
12181 #ifdef HAVE_cc0
12182                       rtx cc0_setter = NULL_RTX;
12183 #endif
12184
12185                       if (set != 0)
12186                         for (inner_dest = SET_DEST (set);
12187                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12188                               || GET_CODE (inner_dest) == SUBREG
12189                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12190                              inner_dest = XEXP (inner_dest, 0))
12191                           ;
12192
12193                       /* Verify that it was the set, and not a clobber that
12194                          modified the register.
12195
12196                          CC0 targets must be careful to maintain setter/user
12197                          pairs.  If we cannot delete the setter due to side
12198                          effects, mark the user with an UNUSED note instead
12199                          of deleting it.  */
12200
12201                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12202                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12203 #ifdef HAVE_cc0
12204                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12205                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12206                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12207 #endif
12208                           )
12209                         {
12210                           /* Move the notes and links of TEM elsewhere.
12211                              This might delete other dead insns recursively.
12212                              First set the pattern to something that won't use
12213                              any register.  */
12214                           rtx old_notes = REG_NOTES (tem);
12215
12216                           PATTERN (tem) = pc_rtx;
12217                           REG_NOTES (tem) = NULL;
12218
12219                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12220                                             NULL_RTX, NULL_RTX);
12221                           distribute_links (LOG_LINKS (tem));
12222
12223                           SET_INSN_DELETED (tem);
12224
12225 #ifdef HAVE_cc0
12226                           /* Delete the setter too.  */
12227                           if (cc0_setter)
12228                             {
12229                               PATTERN (cc0_setter) = pc_rtx;
12230                               old_notes = REG_NOTES (cc0_setter);
12231                               REG_NOTES (cc0_setter) = NULL;
12232
12233                               distribute_notes (old_notes, cc0_setter,
12234                                                 cc0_setter, NULL_RTX,
12235                                                 NULL_RTX, NULL_RTX);
12236                               distribute_links (LOG_LINKS (cc0_setter));
12237
12238                               SET_INSN_DELETED (cc0_setter);
12239                             }
12240 #endif
12241                         }
12242                       else
12243                         {
12244                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12245
12246                           /*  If there isn't already a REG_UNUSED note, put one
12247                               here.  Do not place a REG_DEAD note, even if
12248                               the register is also used here; that would not
12249                               match the algorithm used in lifetime analysis
12250                               and can cause the consistency check in the
12251                               scheduler to fail.  */
12252                           if (! find_regno_note (tem, REG_UNUSED,
12253                                                  REGNO (XEXP (note, 0))))
12254                             place = tem;
12255                           break;
12256                         }
12257                     }
12258                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12259                            || (CALL_P (tem)
12260                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12261                     {
12262                       place = tem;
12263
12264                       /* If we are doing a 3->2 combination, and we have a
12265                          register which formerly died in i3 and was not used
12266                          by i2, which now no longer dies in i3 and is used in
12267                          i2 but does not die in i2, and place is between i2
12268                          and i3, then we may need to move a link from place to
12269                          i2.  */
12270                       if (i2 && INSN_UID (place) <= max_uid_cuid
12271                           && INSN_CUID (place) > INSN_CUID (i2)
12272                           && from_insn
12273                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12274                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12275                         {
12276                           rtx links = LOG_LINKS (place);
12277                           LOG_LINKS (place) = 0;
12278                           distribute_links (links);
12279                         }
12280                       break;
12281                     }
12282
12283                   if (tem == BB_HEAD (bb))
12284                     break;
12285                 }
12286
12287               /* We haven't found an insn for the death note and it
12288                  is still a REG_DEAD note, but we have hit the beginning
12289                  of the block.  If the existing life info says the reg
12290                  was dead, there's nothing left to do.  Otherwise, we'll
12291                  need to do a global life update after combine.  */
12292               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12293                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12294                                       REGNO (XEXP (note, 0))))
12295                 SET_BIT (refresh_blocks, this_basic_block->index);
12296             }
12297
12298           /* If the register is set or already dead at PLACE, we needn't do
12299              anything with this note if it is still a REG_DEAD note.
12300              We check here if it is set at all, not if is it totally replaced,
12301              which is what `dead_or_set_p' checks, so also check for it being
12302              set partially.  */
12303
12304           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12305             {
12306               unsigned int regno = REGNO (XEXP (note, 0));
12307
12308               /* Similarly, if the instruction on which we want to place
12309                  the note is a noop, we'll need do a global live update
12310                  after we remove them in delete_noop_moves.  */
12311               if (noop_move_p (place))
12312                 SET_BIT (refresh_blocks, this_basic_block->index);
12313
12314               if (dead_or_set_p (place, XEXP (note, 0))
12315                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12316                 {
12317                   /* Unless the register previously died in PLACE, clear
12318                      last_death.  [I no longer understand why this is
12319                      being done.] */
12320                   if (reg_stat[regno].last_death != place)
12321                     reg_stat[regno].last_death = 0;
12322                   place = 0;
12323                 }
12324               else
12325                 reg_stat[regno].last_death = place;
12326
12327               /* If this is a death note for a hard reg that is occupying
12328                  multiple registers, ensure that we are still using all
12329                  parts of the object.  If we find a piece of the object
12330                  that is unused, we must arrange for an appropriate REG_DEAD
12331                  note to be added for it.  However, we can't just emit a USE
12332                  and tag the note to it, since the register might actually
12333                  be dead; so we recourse, and the recursive call then finds
12334                  the previous insn that used this register.  */
12335
12336               if (place && regno < FIRST_PSEUDO_REGISTER
12337                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12338                 {
12339                   unsigned int endregno
12340                     = regno + hard_regno_nregs[regno]
12341                                               [GET_MODE (XEXP (note, 0))];
12342                   int all_used = 1;
12343                   unsigned int i;
12344
12345                   for (i = regno; i < endregno; i++)
12346                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12347                          && ! find_regno_fusage (place, USE, i))
12348                         || dead_or_set_regno_p (place, i))
12349                       all_used = 0;
12350
12351                   if (! all_used)
12352                     {
12353                       /* Put only REG_DEAD notes for pieces that are
12354                          not already dead or set.  */
12355
12356                       for (i = regno; i < endregno;
12357                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12358                         {
12359                           rtx piece = regno_reg_rtx[i];
12360                           basic_block bb = this_basic_block;
12361
12362                           if (! dead_or_set_p (place, piece)
12363                               && ! reg_bitfield_target_p (piece,
12364                                                           PATTERN (place)))
12365                             {
12366                               rtx new_note
12367                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12368
12369                               distribute_notes (new_note, place, place,
12370                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12371                             }
12372                           else if (! refers_to_regno_p (i, i + 1,
12373                                                         PATTERN (place), 0)
12374                                    && ! find_regno_fusage (place, USE, i))
12375                             for (tem = PREV_INSN (place); ;
12376                                  tem = PREV_INSN (tem))
12377                               {
12378                                 if (! INSN_P (tem))
12379                                   {
12380                                     if (tem == BB_HEAD (bb))
12381                                       {
12382                                         SET_BIT (refresh_blocks,
12383                                                  this_basic_block->index);
12384                                         break;
12385                                       }
12386                                     continue;
12387                                   }
12388                                 if (dead_or_set_p (tem, piece)
12389                                     || reg_bitfield_target_p (piece,
12390                                                               PATTERN (tem)))
12391                                   {
12392                                     REG_NOTES (tem)
12393                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12394                                                            REG_NOTES (tem));
12395                                     break;
12396                                   }
12397                               }
12398
12399                         }
12400
12401                       place = 0;
12402                     }
12403                 }
12404             }
12405           break;
12406
12407         default:
12408           /* Any other notes should not be present at this point in the
12409              compilation.  */
12410           gcc_unreachable ();
12411         }
12412
12413       if (place)
12414         {
12415           XEXP (note, 1) = REG_NOTES (place);
12416           REG_NOTES (place) = note;
12417         }
12418       else if ((REG_NOTE_KIND (note) == REG_DEAD
12419                 || REG_NOTE_KIND (note) == REG_UNUSED)
12420                && REG_P (XEXP (note, 0)))
12421         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12422
12423       if (place2)
12424         {
12425           if ((REG_NOTE_KIND (note) == REG_DEAD
12426                || REG_NOTE_KIND (note) == REG_UNUSED)
12427               && REG_P (XEXP (note, 0)))
12428             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12429
12430           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12431                                                REG_NOTE_KIND (note),
12432                                                XEXP (note, 0),
12433                                                REG_NOTES (place2));
12434         }
12435     }
12436 }
12437 \f
12438 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12439    I3, I2, and I1 to new locations.  This is also called to add a link
12440    pointing at I3 when I3's destination is changed.  */
12441
12442 static void
12443 distribute_links (rtx links)
12444 {
12445   rtx link, next_link;
12446
12447   for (link = links; link; link = next_link)
12448     {
12449       rtx place = 0;
12450       rtx insn;
12451       rtx set, reg;
12452
12453       next_link = XEXP (link, 1);
12454
12455       /* If the insn that this link points to is a NOTE or isn't a single
12456          set, ignore it.  In the latter case, it isn't clear what we
12457          can do other than ignore the link, since we can't tell which
12458          register it was for.  Such links wouldn't be used by combine
12459          anyway.
12460
12461          It is not possible for the destination of the target of the link to
12462          have been changed by combine.  The only potential of this is if we
12463          replace I3, I2, and I1 by I3 and I2.  But in that case the
12464          destination of I2 also remains unchanged.  */
12465
12466       if (NOTE_P (XEXP (link, 0))
12467           || (set = single_set (XEXP (link, 0))) == 0)
12468         continue;
12469
12470       reg = SET_DEST (set);
12471       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12472              || GET_CODE (reg) == STRICT_LOW_PART)
12473         reg = XEXP (reg, 0);
12474
12475       /* A LOG_LINK is defined as being placed on the first insn that uses
12476          a register and points to the insn that sets the register.  Start
12477          searching at the next insn after the target of the link and stop
12478          when we reach a set of the register or the end of the basic block.
12479
12480          Note that this correctly handles the link that used to point from
12481          I3 to I2.  Also note that not much searching is typically done here
12482          since most links don't point very far away.  */
12483
12484       for (insn = NEXT_INSN (XEXP (link, 0));
12485            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12486                      || BB_HEAD (this_basic_block->next_bb) != insn));
12487            insn = NEXT_INSN (insn))
12488         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12489           {
12490             if (reg_referenced_p (reg, PATTERN (insn)))
12491               place = insn;
12492             break;
12493           }
12494         else if (CALL_P (insn)
12495                  && find_reg_fusage (insn, USE, reg))
12496           {
12497             place = insn;
12498             break;
12499           }
12500         else if (INSN_P (insn) && reg_set_p (reg, insn))
12501           break;
12502
12503       /* If we found a place to put the link, place it there unless there
12504          is already a link to the same insn as LINK at that point.  */
12505
12506       if (place)
12507         {
12508           rtx link2;
12509
12510           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12511             if (XEXP (link2, 0) == XEXP (link, 0))
12512               break;
12513
12514           if (link2 == 0)
12515             {
12516               XEXP (link, 1) = LOG_LINKS (place);
12517               LOG_LINKS (place) = link;
12518
12519               /* Set added_links_insn to the earliest insn we added a
12520                  link to.  */
12521               if (added_links_insn == 0
12522                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12523                 added_links_insn = place;
12524             }
12525         }
12526     }
12527 }
12528 \f
12529 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12530    Check whether the expression pointer to by LOC is a register or
12531    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12532    Otherwise return zero.  */
12533
12534 static int
12535 unmentioned_reg_p_1 (rtx *loc, void *expr)
12536 {
12537   rtx x = *loc;
12538
12539   if (x != NULL_RTX
12540       && (REG_P (x) || MEM_P (x))
12541       && ! reg_mentioned_p (x, (rtx) expr))
12542     return 1;
12543   return 0;
12544 }
12545
12546 /* Check for any register or memory mentioned in EQUIV that is not
12547    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12548    of EXPR where some registers may have been replaced by constants.  */
12549
12550 static bool
12551 unmentioned_reg_p (rtx equiv, rtx expr)
12552 {
12553   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12554 }
12555 \f
12556 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12557
12558 static int
12559 insn_cuid (rtx insn)
12560 {
12561   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12562          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12563     insn = NEXT_INSN (insn);
12564
12565   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12566
12567   return INSN_CUID (insn);
12568 }
12569 \f
12570 void
12571 dump_combine_stats (FILE *file)
12572 {
12573   fprintf
12574     (file,
12575      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12576      combine_attempts, combine_merges, combine_extras, combine_successes);
12577 }
12578
12579 void
12580 dump_combine_total_stats (FILE *file)
12581 {
12582   fprintf
12583     (file,
12584      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12585      total_attempts, total_merges, total_extras, total_successes);
12586 }
12587 \f
12588
12589 static bool
12590 gate_handle_combine (void)
12591 {
12592   return (optimize > 0);
12593 }
12594
12595 /* Try combining insns through substitution.  */
12596 static unsigned int
12597 rest_of_handle_combine (void)
12598 {
12599   int rebuild_jump_labels_after_combine
12600     = combine_instructions (get_insns (), max_reg_num ());
12601
12602   /* Combining insns may have turned an indirect jump into a
12603      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12604      instructions.  */
12605   if (rebuild_jump_labels_after_combine)
12606     {
12607       timevar_push (TV_JUMP);
12608       rebuild_jump_labels (get_insns ());
12609       timevar_pop (TV_JUMP);
12610
12611       delete_dead_jumptables ();
12612       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12613     }
12614   return 0;
12615 }
12616
12617 struct tree_opt_pass pass_combine =
12618 {
12619   "combine",                            /* name */
12620   gate_handle_combine,                  /* gate */
12621   rest_of_handle_combine,               /* execute */
12622   NULL,                                 /* sub */
12623   NULL,                                 /* next */
12624   0,                                    /* static_pass_number */
12625   TV_COMBINE,                           /* tv_id */
12626   0,                                    /* properties_required */
12627   0,                                    /* properties_provided */
12628   0,                                    /* properties_destroyed */
12629   0,                                    /* todo_flags_start */
12630   TODO_dump_func |
12631   TODO_ggc_collect,                     /* todo_flags_finish */
12632   'c'                                   /* letter */
12633 };
12634