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Apply Dimitri Makarov's patch to import attribute short_call and #pragma
[official-gcc.git] / gcc / config / arm / arm.h
blobc20d82bb615bd5b8239e54c012d25a52f9c8d8a5
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #ifndef __ARM_H__
26 #define __ARM_H__
27
28 #define TARGET_CPU_arm2 0x0000
29 #define TARGET_CPU_arm250 0x0000
30 #define TARGET_CPU_arm3 0x0000
31 #define TARGET_CPU_arm6 0x0001
32 #define TARGET_CPU_arm600 0x0001
33 #define TARGET_CPU_arm610 0x0002
34 #define TARGET_CPU_arm7 0x0001
35 #define TARGET_CPU_arm7m 0x0004
36 #define TARGET_CPU_arm7dm 0x0004
37 #define TARGET_CPU_arm7dmi 0x0004
38 #define TARGET_CPU_arm700 0x0001
39 #define TARGET_CPU_arm710 0x0002
40 #define TARGET_CPU_arm7100 0x0002
41 #define TARGET_CPU_arm7500 0x0002
42 #define TARGET_CPU_arm7500fe 0x1001
43 #define TARGET_CPU_arm7tdmi 0x0008
44 #define TARGET_CPU_arm8 0x0010
45 #define TARGET_CPU_arm810 0x0020
46 #define TARGET_CPU_strongarm 0x0040
47 #define TARGET_CPU_strongarm110 0x0040
48 #define TARGET_CPU_strongarm1100 0x0040
49 #define TARGET_CPU_arm9 0x0080
50 #define TARGET_CPU_arm9tdmi 0x0080
51 /* Configure didn't specify. */
52 #define TARGET_CPU_generic 0x8000
53
54 enum arm_cond_code
55 {
56 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
57 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
58 };
59
60 extern enum arm_cond_code arm_current_cc;
61 extern char * arm_condition_codes[];
62
63 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
64
65 extern int arm_target_label;
66 extern int arm_ccfsm_state;
67 extern struct rtx_def * arm_target_insn;
68 extern int lr_save_eliminated;
69 /* This is needed by the tail-calling peepholes */
70 extern int frame_pointer_needed;
71 /* Run-time compilation parameters selecting different hardware subsets. */
72 extern int target_flags;
73 /* The floating point instruction architecture, can be 2 or 3 */
74 extern const char * target_fp_name;
75
76 \f
77 /* Just in case configure has failed to define anything. */
78 #ifndef TARGET_CPU_DEFAULT
79 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
80 #endif
81
82 /* If the configuration file doesn't specify the cpu, the subtarget may
83 override it. If it doesn't, then default to an ARM6. */
84 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
85 #undef TARGET_CPU_DEFAULT
86 #ifdef SUBTARGET_CPU_DEFAULT
87 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
88 #else
89 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
90 #endif
91 #endif
92
93 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
94 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
95 #else
96 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
97 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
98 #else
99 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
100 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
101 #else
102 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9
103 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
104 #else
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
107 #else
108 Unrecognized value in TARGET_CPU_DEFAULT.
109 #endif
110 #endif
111 #endif
112 #endif
113 #endif
114
115 #ifndef CPP_PREDEFINES
116 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
117 #endif
118
119 #define CPP_SPEC "\
120 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
121 %(cpp_endian) %(subtarget_cpp_spec)"
122
123 /* Set the architecture define -- if -march= is set, then it overrides
124 the -mcpu= setting. */
125 #define CPP_CPU_ARCH_SPEC "\
126 %{march=arm2:-D__ARM_ARCH_2__} \
127 %{march=arm250:-D__ARM_ARCH_2__} \
128 %{march=arm3:-D__ARM_ARCH_2__} \
129 %{march=arm6:-D__ARM_ARCH_3__} \
130 %{march=arm600:-D__ARM_ARCH_3__} \
131 %{march=arm610:-D__ARM_ARCH_3__} \
132 %{march=arm7:-D__ARM_ARCH_3__} \
133 %{march=arm700:-D__ARM_ARCH_3__} \
134 %{march=arm710:-D__ARM_ARCH_3__} \
135 %{march=arm720:-D__ARM_ARCH_3__} \
136 %{march=arm7100:-D__ARM_ARCH_3__} \
137 %{march=arm7500:-D__ARM_ARCH_3__} \
138 %{march=arm7500fe:-D__ARM_ARCH_3__} \
139 %{march=arm7m:-D__ARM_ARCH_3M__} \
140 %{march=arm7dm:-D__ARM_ARCH_3M__} \
141 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
142 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
143 %{march=arm8:-D__ARM_ARCH_4__} \
144 %{march=arm810:-D__ARM_ARCH_4__} \
145 %{march=arm9:-D__ARM_ARCH_4T__} \
146 %{march=arm920:-D__ARM_ARCH_4__} \
147 %{march=arm920t:-D__ARM_ARCH_4T__} \
148 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
149 %{march=strongarm:-D__ARM_ARCH_4__} \
150 %{march=strongarm110:-D__ARM_ARCH_4__} \
151 %{march=strongarm1100:-D__ARM_ARCH_4__} \
152 %{march=armv2:-D__ARM_ARCH_2__} \
153 %{march=armv2a:-D__ARM_ARCH_2__} \
154 %{march=armv3:-D__ARM_ARCH_3__} \
155 %{march=armv3m:-D__ARM_ARCH_3M__} \
156 %{march=armv4:-D__ARM_ARCH_4__} \
157 %{march=armv4t:-D__ARM_ARCH_4T__} \
158 %{march=armv5:-D__ARM_ARCH_5__} \
159 %{!march=*: \
160 %{mcpu=arm2:-D__ARM_ARCH_2__} \
161 %{mcpu=arm250:-D__ARM_ARCH_2__} \
162 %{mcpu=arm3:-D__ARM_ARCH_2__} \
163 %{mcpu=arm6:-D__ARM_ARCH_3__} \
164 %{mcpu=arm600:-D__ARM_ARCH_3__} \
165 %{mcpu=arm610:-D__ARM_ARCH_3__} \
166 %{mcpu=arm7:-D__ARM_ARCH_3__} \
167 %{mcpu=arm700:-D__ARM_ARCH_3__} \
168 %{mcpu=arm710:-D__ARM_ARCH_3__} \
169 %{mcpu=arm720:-D__ARM_ARCH_3__} \
170 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
171 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
172 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
173 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
174 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
175 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
176 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
177 %{mcpu=arm8:-D__ARM_ARCH_4__} \
178 %{mcpu=arm810:-D__ARM_ARCH_4__} \
179 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
180 %{mcpu=arm920:-D__ARM_ARCH_4__} \
181 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
182 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
183 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
184 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
185 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
186 %{!mcpu*:%(cpp_cpu_arch_default)}} \
187 "
188
189 /* Define __APCS_26__ if the PC also contains the PSR */
190 #define CPP_APCS_PC_SPEC "\
191 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
192 -D__APCS_32__} \
193 %{mapcs-26:-D__APCS_26__} \
194 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
195 "
196
197 #ifndef CPP_APCS_PC_DEFAULT_SPEC
198 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
199 #endif
200
201 #define CPP_FLOAT_SPEC "\
202 %{msoft-float:\
203 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
204 -D__SOFTFP__} \
205 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
206 "
207
208 /* Default is hard float, which doesn't define anything */
209 #define CPP_FLOAT_DEFAULT_SPEC ""
210
211 #define CPP_ENDIAN_SPEC "\
212 %{mbig-endian: \
213 %{mlittle-endian: \
214 %e-mbig-endian and -mlittle-endian may not be used together} \
215 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
216 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
217 "
218
219 /* Default is little endian, which doesn't define anything. */
220 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__"
221
222 #define CC1_SPEC ""
223
224 /* This macro defines names of additional specifications to put in the specs
225 that can be used in various specifications like CC1_SPEC. Its definition
226 is an initializer with a subgrouping for each command option.
227
228 Each subgrouping contains a string constant, that defines the
229 specification name, and a string constant that used by the GNU CC driver
230 program.
231
232 Do not define this macro if it does not need to do anything. */
233 #define EXTRA_SPECS \
234 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
235 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
236 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
237 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
238 { "cpp_float", CPP_FLOAT_SPEC }, \
239 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
240 { "cpp_endian", CPP_ENDIAN_SPEC }, \
241 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
242 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
243 SUBTARGET_EXTRA_SPECS
244
245 #ifndef SUBTARGET_EXTRA_SPECS
246 #define SUBTARGET_EXTRA_SPECS
247 #endif
248
249 #ifndef SUBTARGET_CPP_SPEC
250 #define SUBTARGET_CPP_SPEC ""
251 #endif
252
253 \f
254 /* Run-time Target Specification. */
255 #ifndef TARGET_VERSION
256 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
257 #endif
258
259 /* Nonzero if the function prologue (and epilogue) should obey
260 the ARM Procedure Call Standard. */
261 #define ARM_FLAG_APCS_FRAME (1 << 0)
262
263 /* Nonzero if the function prologue should output the function name to enable
264 the post mortem debugger to print a backtrace (very useful on RISCOS,
265 unused on RISCiX). Specifying this flag also enables
266 -fno-omit-frame-pointer.
267 XXX Must still be implemented in the prologue. */
268 #define ARM_FLAG_POKE (1 << 1)
269
270 /* Nonzero if floating point instructions are emulated by the FPE, in which
271 case instruction scheduling becomes very uninteresting. */
272 #define ARM_FLAG_FPE (1 << 2)
273
274 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
275 that assume restoration of the condition flags when returning from a
276 branch and link (ie a function). */
277 #define ARM_FLAG_APCS_32 (1 << 3)
278
279 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
280
281 /* Nonzero if stack checking should be performed on entry to each function
282 which allocates temporary variables on the stack. */
283 #define ARM_FLAG_APCS_STACK (1 << 4)
284
285 /* Nonzero if floating point parameters should be passed to functions in
286 floating point registers. */
287 #define ARM_FLAG_APCS_FLOAT (1 << 5)
288
289 /* Nonzero if re-entrant, position independent code should be generated.
290 This is equivalent to -fpic. */
291 #define ARM_FLAG_APCS_REENT (1 << 6)
292
293 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
294 be loaded using either LDRH or LDRB instructions. */
295 #define ARM_FLAG_MMU_TRAPS (1 << 7)
296
297 /* Nonzero if all floating point instructions are missing (and there is no
298 emulator either). Generate function calls for all ops in this case. */
299 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
300
301 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
302 #define ARM_FLAG_BIG_END (1 << 9)
303
304 /* Nonzero if we should compile for Thumb interworking. */
305 #define ARM_FLAG_INTERWORK (1 << 10)
306
307 /* Nonzero if we should have little-endian words even when compiling for
308 big-endian (for backwards compatibility with older versions of GCC). */
309 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
310
311 /* Nonzero if we need to protect the prolog from scheduling */
312 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
313
314 /* Nonzero if a call to abort should be generated if a noreturn
315 function tries to return. */
316 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
317
318 /* Nonzero if function prologues should not load the PIC register. */
319 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
320
321 /* Nonzero if all call instructions should be indirect. */
322 #define ARM_FLAG_LONG_CALLS (1 << 15)
323
324 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
325 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
326 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
327 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
328 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
329 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
330 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
331 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
332 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
333 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
334 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
335 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
336 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
337 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
338 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
339 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
340 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
341
342 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
343 Bit 31 is reserved. See riscix.h. */
344 #ifndef SUBTARGET_SWITCHES
345 #define SUBTARGET_SWITCHES
346 #endif
347
348 #define TARGET_SWITCHES \
349 { \
350 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
351 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
352 "Generate APCS conformant stack frames" }, \
353 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
354 {"poke-function-name", ARM_FLAG_POKE, \
355 "Store function names in object code" }, \
356 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
357 {"fpe", ARM_FLAG_FPE, "" }, \
358 {"apcs-32", ARM_FLAG_APCS_32, \
359 "Use the 32bit version of the APCS" }, \
360 {"apcs-26", -ARM_FLAG_APCS_32, \
361 "Use the 26bit version of the APCS" }, \
362 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
363 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
364 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
365 "Pass FP arguments in FP registers" }, \
366 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
367 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
368 "Generate re-entrant, PIC code" }, \
369 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
370 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
371 "The MMU will trap on unaligned accesses" }, \
372 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
373 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
374 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
375 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
376 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
377 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
378 "Use library calls to perform FP operations" }, \
379 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
380 "Use hardware floating point instructions" }, \
381 {"big-endian", ARM_FLAG_BIG_END, \
382 "Assume target CPU is configured as big endian" }, \
383 {"little-endian", -ARM_FLAG_BIG_END, \
384 "Assume target CPU is configured as little endian" }, \
385 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
386 "Assume big endian bytes, little endian words" }, \
387 {"thumb-interwork", ARM_FLAG_INTERWORK, \
388 "Support calls between THUMB and ARM instructions sets" }, \
389 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
390 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
391 "Generate a call to abort if a noreturn function returns"},\
392 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
393 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
394 "Do not move instructions into a function's prologue" }, \
395 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
396 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
397 "Do not load the PIC register in function prologues" }, \
398 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
399 {"long-calls", ARM_FLAG_LONG_CALLS, \
400 "Generate call insns as indirect calls, if necessary"}, \
401 {"no-long-calls", -ARM_FLAG_LONG_CALLS, ""}, \
402 SUBTARGET_SWITCHES \
403 {"", TARGET_DEFAULT, "" } \
404 }
405
406 #define TARGET_OPTIONS \
407 { \
408 {"cpu=", & arm_select[0].string, \
409 "Specify the name of the target CPU" }, \
410 {"arch=", & arm_select[1].string, \
411 "Specify the name of the target architecture" }, \
412 {"tune=", & arm_select[2].string, "" }, \
413 {"fpe=", & target_fp_name, "" }, \
414 {"fp=", & target_fp_name, \
415 "Specify the version of the floating point emulator" }, \
416 { "structure-size-boundary=", & structure_size_string, \
417 "Specify the minimum bit alignment of structures" }, \
418 { "pic-register=", & arm_pic_register_string, \
419 "Specify the register to be used for PIC addressing" } \
420 }
421
422 struct arm_cpu_select
423 {
424 const char * string;
425 const char * name;
426 const struct processors * processors;
427 };
428
429 /* This is a magic array. If the user specifies a command line switch
430 which matches one of the entries in TARGET_OPTIONS then the corresponding
431 string pointer will be set to the value specified by the user. */
432 extern struct arm_cpu_select arm_select[];
433
434 enum prog_mode_type
435 {
436 prog_mode26,
437 prog_mode32
438 };
439
440 /* Recast the program mode class to be the prog_mode attribute */
441 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
442
443 extern enum prog_mode_type arm_prgmode;
444
445 /* What sort of floating point unit do we have? Hardware or software.
446 If software, is it issue 2 or issue 3? */
447 enum floating_point_type
448 {
449 FP_HARD,
450 FP_SOFT2,
451 FP_SOFT3
452 };
453
454 /* Recast the floating point class to be the floating point attribute. */
455 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
456
457 /* What type of floating point to tune for */
458 extern enum floating_point_type arm_fpu;
459
460 /* What type of floating point instructions are available */
461 extern enum floating_point_type arm_fpu_arch;
462
463 /* Default floating point architecture. Override in sub-target if
464 necessary. */
465 #define FP_DEFAULT FP_SOFT2
466
467 /* Nonzero if the processor has a fast multiply insn, and one that does
468 a 64-bit multiply of two 32-bit values. */
469 extern int arm_fast_multiply;
470
471 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
472 extern int arm_arch4;
473
474 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
475 extern int arm_arch5;
476
477 /* Nonzero if this chip can benefit from load scheduling. */
478 extern int arm_ld_sched;
479
480 /* Nonzero if this chip is a StrongARM. */
481 extern int arm_is_strong;
482
483 /* Nonzero if this chip is a an ARM6 or an ARM7. */
484 extern int arm_is_6_or_7;
485
486 #ifndef TARGET_DEFAULT
487 #define TARGET_DEFAULT 0
488 #endif
489
490 /* The frame pointer register used in gcc has nothing to do with debugging;
491 that is controlled by the APCS-FRAME option. */
492 /* Not fully implemented yet. */
493 /* #define CAN_DEBUG_WITHOUT_FP 1 */
494
495 #define TARGET_MEM_FUNCTIONS 1
496
497 #define OVERRIDE_OPTIONS arm_override_options ()
498
499 /* Nonzero if PIC code requires explicit qualifiers to generate
500 PLT and GOT relocs rather than the assembler doing so implicitly.
501 Subtargets can override these if required. */
502 #ifndef NEED_GOT_RELOC
503 #define NEED_GOT_RELOC 0
504 #endif
505 #ifndef NEED_PLT_RELOC
506 #define NEED_PLT_RELOC 0
507 #endif
508
509 /* Nonzero if we need to refer to the GOT with a PC-relative
510 offset. In other words, generate
511
512 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
513
514 rather than
515
516 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
517
518 The default is true, which matches NetBSD. Subtargets can
519 override this if required. */
520 #ifndef GOT_PCREL
521 #define GOT_PCREL 1
522 #endif
523 \f
524 /* Target machine storage Layout. */
525
526
527 /* Define this macro if it is advisable to hold scalars in registers
528 in a wider mode than that declared by the program. In such cases,
529 the value is constrained to be within the bounds of the declared
530 type, but kept valid in the wider mode. The signedness of the
531 extension may differ from that of the type. */
532
533 /* It is far faster to zero extend chars than to sign extend them */
534
535 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
536 if (GET_MODE_CLASS (MODE) == MODE_INT \
537 && GET_MODE_SIZE (MODE) < 4) \
538 { \
539 if (MODE == QImode) \
540 UNSIGNEDP = 1; \
541 else if (MODE == HImode) \
542 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
543 (MODE) = SImode; \
544 }
545
546 /* Define this macro if the promotion described by `PROMOTE_MODE'
547 should also be done for outgoing function arguments. */
548 /* This is required to ensure that push insns always push a word. */
549 #define PROMOTE_FUNCTION_ARGS
550
551 /* Define for XFmode extended real floating point support.
552 This will automatically cause REAL_ARITHMETIC to be defined. */
553 /* For the ARM:
554 I think I have added all the code to make this work. Unfortunately,
555 early releases of the floating point emulation code on RISCiX used a
556 different format for extended precision numbers. On my RISCiX box there
557 is a bug somewhere which causes the machine to lock up when running enquire
558 with long doubles. There is the additional aspect that Norcroft C
559 treats long doubles as doubles and we ought to remain compatible.
560 Perhaps someone with an FPA coprocessor and not running RISCiX would like
561 to try this someday. */
562 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
563
564 /* Disable XFmode patterns in md file */
565 #define ENABLE_XF_PATTERNS 0
566
567 /* Define if you don't want extended real, but do want to use the
568 software floating point emulator for REAL_ARITHMETIC and
569 decimal <-> binary conversion. */
570 /* See comment above */
571 #define REAL_ARITHMETIC
572
573 /* Define this if most significant bit is lowest numbered
574 in instructions that operate on numbered bit-fields. */
575 #define BITS_BIG_ENDIAN 0
576
577 /* Define this if most significant byte of a word is the lowest numbered.
578 Most ARM processors are run in little endian mode, so that is the default.
579 If you want to have it run-time selectable, change the definition in a
580 cover file to be TARGET_BIG_ENDIAN. */
581 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
582
583 /* Define this if most significant word of a multiword number is the lowest
584 numbered.
585 This is always false, even when in big-endian mode. */
586 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
587
588 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
589 on processor pre-defineds when compiling libgcc2.c. */
590 #if defined(__ARMEB__) && !defined(__ARMWEL__)
591 #define LIBGCC2_WORDS_BIG_ENDIAN 1
592 #else
593 #define LIBGCC2_WORDS_BIG_ENDIAN 0
594 #endif
595
596 /* Define this if most significant word of doubles is the lowest numbered.
597 This is always true, even when in little-endian mode. */
598 #define FLOAT_WORDS_BIG_ENDIAN 1
599
600 /* Number of bits in an addressable storage unit */
601 #define BITS_PER_UNIT 8
602
603 #define BITS_PER_WORD 32
604
605 #define UNITS_PER_WORD 4
606
607 #define POINTER_SIZE 32
608
609 #define PARM_BOUNDARY 32
610
611 #define STACK_BOUNDARY 32
612
613 #define FUNCTION_BOUNDARY 32
614
615 #define EMPTY_FIELD_BOUNDARY 32
616
617 #define BIGGEST_ALIGNMENT 32
618
619 /* Make strings word-aligned so strcpy from constants will be faster. */
620 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
621 (TREE_CODE (EXP) == STRING_CST \
622 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
623
624 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
625 value set in previous versions of this toolchain was 8, which produces more
626 compact structures. The command line option -mstructure_size_boundary=<n>
627 can be used to change this value. For compatability with the ARM SDK
628 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
629 0020D) page 2-20 says "Structures are aligned on word boundaries". */
630 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
631 extern int arm_structure_size_boundary;
632
633 /* This is the value used to initialise arm_structure_size_boundary. If a
634 particular arm target wants to change the default value it should change
635 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
636 for an example of this. */
637 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
638 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
639 #endif
640
641 /* Used when parsing command line option -mstructure_size_boundary. */
642 extern const char * structure_size_string;
643
644 /* Non-zero if move instructions will actually fail to work
645 when given unaligned data. */
646 #define STRICT_ALIGNMENT 1
647
648 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
649
650 \f
651 /* Standard register usage. */
652
653 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
654 (S - saved over call).
655
656 r0 * argument word/integer result
657 r1-r3 argument word
658
659 r4-r8 S register variable
660 r9 S (rfp) register variable (real frame pointer)
661
662 r10 F S (sl) stack limit (used by -mapcs-stack-check)
663 r11 F S (fp) argument pointer
664 r12 (ip) temp workspace
665 r13 F S (sp) lower end of current stack frame
666 r14 (lr) link address/workspace
667 r15 F (pc) program counter
668
669 f0 floating point result
670 f1-f3 floating point scratch
671
672 f4-f7 S floating point variable
673
674 cc This is NOT a real register, but is used internally
675 to represent things that use or set the condition
676 codes.
677 sfp This isn't either. It is used during rtl generation
678 since the offset between the frame pointer and the
679 auto's isn't known until after register allocation.
680 afp Nor this, we only need this because of non-local
681 goto. Without it fp appears to be used and the
682 elimination code won't get rid of sfp. It tracks
683 fp exactly at all times.
684
685 *: See CONDITIONAL_REGISTER_USAGE */
686
687 /* The stack backtrace structure is as follows:
688 fp points to here: | save code pointer | [fp]
689 | return link value | [fp, #-4]
690 | return sp value | [fp, #-8]
691 | return fp value | [fp, #-12]
692 [| saved r10 value |]
693 [| saved r9 value |]
694 [| saved r8 value |]
695 [| saved r7 value |]
696 [| saved r6 value |]
697 [| saved r5 value |]
698 [| saved r4 value |]
699 [| saved r3 value |]
700 [| saved r2 value |]
701 [| saved r1 value |]
702 [| saved r0 value |]
703 [| saved f7 value |] three words
704 [| saved f6 value |] three words
705 [| saved f5 value |] three words
706 [| saved f4 value |] three words
707 r0-r3 are not normally saved in a C function. */
708
709 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
710 #define FIRST_PSEUDO_REGISTER 27
711
712 /* 1 for registers that have pervasive standard uses
713 and are not available for the register allocator. */
714 #define FIXED_REGISTERS \
715 { \
716 0,0,0,0,0,0,0,0, \
717 0,0,0,1,0,1,0,1, \
718 0,0,0,0,0,0,0,0, \
719 1,1,1 \
720 }
721
722 /* 1 for registers not available across function calls.
723 These must include the FIXED_REGISTERS and also any
724 registers that can be used without being saved.
725 The latter must include the registers where values are returned
726 and the register where structure-value addresses are passed.
727 Aside from that, you can include as many other registers as you like.
728 The CC is not preserved over function calls on the ARM 6, so it is
729 easier to assume this for all. SFP is preserved, since FP is. */
730 #define CALL_USED_REGISTERS \
731 { \
732 1,1,1,1,0,0,0,0, \
733 0,0,0,1,1,1,1,1, \
734 1,1,1,1,0,0,0,0, \
735 1,1,1 \
736 }
737
738 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
739 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
740 #endif
741
742 #define CONDITIONAL_REGISTER_USAGE \
743 { \
744 if (TARGET_SOFT_FLOAT) \
745 { \
746 int regno; \
747 for (regno = 16; regno < 24; ++regno) \
748 fixed_regs[regno] = call_used_regs[regno] = 1; \
749 } \
750 if (flag_pic) \
751 { \
752 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
753 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
754 } \
755 else if (TARGET_APCS_STACK) \
756 { \
757 fixed_regs[10] = 1; \
758 call_used_regs[10] = 1; \
759 } \
760 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
761 }
762
763 /* These are a couple of extensions to the formats accecpted
764 by asm_fprintf:
765 %@ prints out ASM_COMMENT_START
766 %r prints out REGISTER_PREFIX reg_names[arg] */
767 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
768 case '@': \
769 fputs (ASM_COMMENT_START, FILE); \
770 break; \
771 \
772 case 'r': \
773 fputs (REGISTER_PREFIX, FILE); \
774 fputs (reg_names [va_arg (ARGS, int)], FILE); \
775 break;
776
777 /* Convert fron bytes to ints. */
778 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
779
780 /* The number of (integer) registers required to hold a quantity of type MODE. */
781 #define NUM_REGS(MODE) \
782 NUM_INTS (GET_MODE_SIZE (MODE))
783
784 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
785 #define NUM_REGS2(MODE, TYPE) \
786 NUM_INTS ((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
787
788 /* The number of (integer) argument register available. */
789 #define NUM_ARG_REGS 4
790
791 /* Return the regiser number of the N'th (integer) argument. */
792 #define ARG_REGISTER(N) (N - 1)
793
794 /* The number of the last argument register. */
795 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
796
797 /* Return number of consecutive hard regs needed starting at reg REGNO
798 to hold something of mode MODE.
799 This is ordinarily the length in words of a value of mode MODE
800 but can be less for certain modes in special long registers.
801
802 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
803 mode. */
804 #define HARD_REGNO_NREGS(REGNO, MODE) \
805 (( REGNO >= 16 \
806 && REGNO != FRAME_POINTER_REGNUM \
807 && REGNO != ARG_POINTER_REGNUM) \
808 ? 1 : NUM_REGS (MODE))
809
810 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
811 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
812 regs holding FP. */
813 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
814 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
815 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
816 || REGNO == ARG_POINTER_REGNUM \
817 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
818
819 /* Value is 1 if it is a good idea to tie two pseudo registers
820 when one has mode MODE1 and one has mode MODE2.
821 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
822 for any hard reg, then this must be 0 for correct output. */
823 #define MODES_TIEABLE_P(MODE1, MODE2) \
824 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
825
826 /* Specify the registers used for certain standard purposes.
827 The values of these macros are register numbers. */
828
829 /* Define this if the program counter is overloaded on a register. */
830 #define PC_REGNUM 15
831
832 /* Register to use for pushing function arguments. */
833 #define STACK_POINTER_REGNUM 13
834 #define SP_REGNUM STACK_POINTER_REGNUM
835
836 /* Base register for access to local variables of the function. */
837 #define FRAME_POINTER_REGNUM 25
838
839 /* Define this to be where the real frame pointer is if it is not possible to
840 work out the offset between the frame pointer and the automatic variables
841 until after register allocation has taken place. FRAME_POINTER_REGNUM
842 should point to a special register that we will make sure is eliminated. */
843 #define HARD_FRAME_POINTER_REGNUM 11
844 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
845
846 /* Register which holds return address from a subroutine call. */
847 #define LR_REGNUM 14
848
849 /* Scratch register - used in all kinds of places, eg trampolines. */
850 #define IP_REGNUM 12
851
852 /* Value should be nonzero if functions must have frame pointers.
853 Zero means the frame pointer need not be set up (and parms may be accessed
854 via the stack pointer) in functions that seem suitable.
855 If we have to have a frame pointer we might as well make use of it.
856 APCS says that the frame pointer does not need to be pushed in leaf
857 functions, or simple tail call functions. */
858 #define FRAME_POINTER_REQUIRED \
859 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
860
861 /* Base register for access to arguments of the function. */
862 #define ARG_POINTER_REGNUM 26
863
864 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
865 as an invisible last argument (possible since varargs don't exist in
866 Pascal), so the following is not true. */
867 #define STATIC_CHAIN_REGNUM 8
868
869 /* Register in which address to store a structure value
870 is passed to a function. */
871 #define STRUCT_VALUE_REGNUM 0
872
873 /* Internal, so that we don't need to refer to a raw number */
874 #define CC_REGNUM 24
875
876 /* The order in which register should be allocated. It is good to use ip
877 since no saving is required (though calls clobber it) and it never contains
878 function parameters. It is quite good to use lr since other calls may
879 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
880 least likely to contain a function parameter; in addition results are
881 returned in r0.
882 */
883 #define REG_ALLOC_ORDER \
884 { \
885 3, 2, 1, 0, 12, 14, 4, 5, \
886 6, 7, 8, 10, 9, 11, 13, 15, \
887 16, 17, 18, 19, 20, 21, 22, 23, \
888 24, 25, 26 \
889 }
890 \f
891 /* Register and constant classes. */
892
893 /* Register classes: all ARM regs or all FPU regs---simple! */
894 enum reg_class
895 {
896 NO_REGS,
897 FPU_REGS,
898 GENERAL_REGS,
899 ALL_REGS,
900 LIM_REG_CLASSES
901 };
902
903 #define N_REG_CLASSES (int) LIM_REG_CLASSES
904
905 /* Give names of register classes as strings for dump file. */
906 #define REG_CLASS_NAMES \
907 { \
908 "NO_REGS", \
909 "FPU_REGS", \
910 "GENERAL_REGS", \
911 "ALL_REGS", \
912 }
913
914 /* Define which registers fit in which classes.
915 This is an initializer for a vector of HARD_REG_SET
916 of length N_REG_CLASSES. */
917 #define REG_CLASS_CONTENTS \
918 { \
919 { 0x0000000 }, /* NO_REGS */ \
920 { 0x0FF0000 }, /* FPU_REGS */ \
921 { 0x200FFFF }, /* GENERAL_REGS */ \
922 { 0x2FFFFFF } /* ALL_REGS */ \
923 }
924
925 /* The same information, inverted:
926 Return the class number of the smallest class containing
927 reg number REGNO. This could be a conditional expression
928 or could index an array. */
929 #define REGNO_REG_CLASS(REGNO) \
930 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
931 || REGNO == ARG_POINTER_REGNUM) \
932 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
933 ? NO_REGS : FPU_REGS)
934
935 /* The class value for index registers, and the one for base regs. */
936 #define INDEX_REG_CLASS GENERAL_REGS
937 #define BASE_REG_CLASS GENERAL_REGS
938
939 /* Get reg_class from a letter such as appears in the machine description.
940 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
941 #define REG_CLASS_FROM_LETTER(C) \
942 ((C)=='f' ? FPU_REGS : NO_REGS)
943
944 /* The letters I, J, K, L and M in a register constraint string
945 can be used to stand for particular ranges of immediate operands.
946 This macro defines what the ranges are.
947 C is the letter, and VALUE is a constant value.
948 Return 1 if VALUE is in the range specified by C.
949 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
950 J: valid indexing constants.
951 K: ~value ok in rhs argument of data operand.
952 L: -value ok in rhs argument of data operand.
953 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
954 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
955 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
956 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
957 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
958 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
959 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
960 || (((VALUE) & ((VALUE) - 1)) == 0)) \
961 : 0)
962
963 /* For the ARM, `Q' means that this is a memory operand that is just
964 an offset from a register.
965 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
966 address. This means that the symbol is in the text segment and can be
967 accessed without using a load. */
968
969 #define EXTRA_CONSTRAINT(OP, C) \
970 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
971 : (C) == 'R' ? (GET_CODE (OP) == MEM \
972 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
973 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
974 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
975 : 0)
976
977 /* Constant letter 'G' for the FPU immediate constants.
978 'H' means the same constant negated. */
979 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
980 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
981 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
982
983 /* Given an rtx X being reloaded into a reg required to be
984 in class CLASS, return the class of reg to actually use.
985 In general this is just CLASS; but on some machines
986 in some cases it is preferable to use a more restrictive class. */
987 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
988
989 /* Return the register class of a scratch register needed to copy IN into
990 or out of a register in CLASS in MODE. If it can be done directly,
991 NO_REGS is returned. */
992 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
993 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
994 ? GENERAL_REGS : NO_REGS)
995
996 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
997 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
998 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
999 && (GET_CODE (X) == MEM \
1000 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1001 && true_regnum (X) == -1))) \
1002 ? GENERAL_REGS : NO_REGS)
1003
1004 /* Try a machine-dependent way of reloading an illegitimate address
1005 operand. If we find one, push the reload and jump to WIN. This
1006 macro is used in only one place: `find_reloads_address' in reload.c.
1007
1008 For the ARM, we wish to handle large displacements off a base
1009 register by splitting the addend across a MOV and the mem insn.
1010 This can cut the number of reloads needed. */
1011 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1012 do \
1013 { \
1014 if (GET_CODE (X) == PLUS \
1015 && GET_CODE (XEXP (X, 0)) == REG \
1016 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1017 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1018 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1019 { \
1020 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1021 HOST_WIDE_INT low, high; \
1022 \
1023 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1024 low = ((val & 0xf) ^ 0x8) - 0x8; \
1025 else if (MODE == SImode \
1026 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1027 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1028 /* Need to be careful, -4096 is not a valid offset */ \
1029 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1030 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1031 /* Need to be careful, -256 is not a valid offset */ \
1032 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1033 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1034 && TARGET_HARD_FLOAT) \
1035 /* Need to be careful, -1024 is not a valid offset */ \
1036 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1037 else \
1038 break; \
1039 \
1040 high = ((((val - low) & 0xffffffffUL) ^ 0x80000000UL) - 0x80000000UL);\
1041 /* Check for overflow or zero */ \
1042 if (low == 0 || high == 0 || (high + low != val)) \
1043 break; \
1044 \
1045 /* Reload the high part into a base reg; leave the low part \
1046 in the mem. */ \
1047 X = gen_rtx_PLUS (GET_MODE (X), \
1048 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1049 GEN_INT (high)), \
1050 GEN_INT (low)); \
1051 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1052 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1053 OPNUM, TYPE); \
1054 goto WIN; \
1055 } \
1056 } \
1057 while (0)
1058
1059 /* Return the maximum number of consecutive registers
1060 needed to represent mode MODE in a register of class CLASS.
1061 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1062 #define CLASS_MAX_NREGS(CLASS, MODE) \
1063 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1064
1065 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1066 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1067 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
1068 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
1069 ? 20 : 2)
1070 \f
1071 /* Stack layout; function entry, exit and calling. */
1072
1073 /* Define this if pushing a word on the stack
1074 makes the stack pointer a smaller address. */
1075 #define STACK_GROWS_DOWNWARD 1
1076
1077 /* Define this if the nominal address of the stack frame
1078 is at the high-address end of the local variables;
1079 that is, each additional local variable allocated
1080 goes at a more negative offset in the frame. */
1081 #define FRAME_GROWS_DOWNWARD 1
1082
1083 /* Offset within stack frame to start allocating local variables at.
1084 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1085 first local allocated. Otherwise, it is the offset to the BEGINNING
1086 of the first local allocated. */
1087 #define STARTING_FRAME_OFFSET 0
1088
1089 /* If we generate an insn to push BYTES bytes,
1090 this says how many the stack pointer really advances by. */
1091 /* The push insns do not do this rounding implicitly. So don't define this. */
1092 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
1093
1094 /* Define this if the maximum size of all the outgoing args is to be
1095 accumulated and pushed during the prologue. The amount can be
1096 found in the variable current_function_outgoing_args_size. */
1097 #define ACCUMULATE_OUTGOING_ARGS 1
1098
1099 /* Offset of first parameter from the argument pointer register value. */
1100 #define FIRST_PARM_OFFSET(FNDECL) 4
1101
1102 /* Value is the number of byte of arguments automatically
1103 popped when returning from a subroutine call.
1104 FUNDECL is the declaration node of the function (as a tree),
1105 FUNTYPE is the data type of the function (as a tree),
1106 or for a library call it is an identifier node for the subroutine name.
1107 SIZE is the number of bytes of arguments passed on the stack.
1108
1109 On the ARM, the caller does not pop any of its arguments that were passed
1110 on the stack. */
1111 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1112
1113 /* Define how to find the value returned by a library function
1114 assuming the value has mode MODE. */
1115 #define LIBCALL_VALUE(MODE) \
1116 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
1117 ? gen_rtx_REG (MODE, 16) \
1118 : gen_rtx_REG (MODE, 0))
1119
1120 /* Define how to find the value returned by a function.
1121 VALTYPE is the data type of the value (as a tree).
1122 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1123 otherwise, FUNC is 0. */
1124 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1125 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1126
1127 /* 1 if N is a possible register number for a function value.
1128 On the ARM, only r0 and f0 can return results. */
1129 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1130 ((REGNO) == 0 || (((REGNO) == 16) && TARGET_HARD_FLOAT))
1131
1132 /* How large values are returned */
1133 /* A C expression which can inhibit the returning of certain function values
1134 in registers, based on the type of value. */
1135 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1136
1137 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1138 values must be in memory. On the ARM, they need only do so if larger
1139 than a word, or if they contain elements offset from zero in the struct. */
1140 #define DEFAULT_PCC_STRUCT_RETURN 0
1141
1142 /* A C type for declaring a variable that is used as the first argument of
1143 `FUNCTION_ARG' and other related values. For some target machines, the
1144 type `int' suffices and can hold the number of bytes of argument so far. */
1145 typedef struct
1146 {
1147 /* This is the number of argument registers scanned so far. */
1148 int nregs;
1149 /* instructions on how to process this call. */
1150 int call_cookie;
1151 }
1152 CUMULATIVE_ARGS;
1153
1154 /* Flags for the call_cookie field of CUMULATIVE_ARGS. */
1155 #define CALL_NORMAL 0 /* No special processing. */
1156 #define CALL_LONG 1 /* Always call indirect. */
1157 #define CALL_SHORT 2 /* Never call indirect. */
1158
1159 /* Define where to put the arguments to a function.
1160 Value is zero to push the argument on the stack,
1161 or a hard register in which to store the argument.
1162
1163 MODE is the argument's machine mode.
1164 TYPE is the data type of the argument (as a tree).
1165 This is null for libcalls where that information may
1166 not be available.
1167 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1168 the preceding args and about the function being called.
1169 NAMED is nonzero if this argument is a named parameter
1170 (otherwise it is an extra parameter matching an ellipsis).
1171
1172 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1173 other arguments are passed on the stack. If (NAMED == 0) (which happens
1174 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1175 passed in the stack (function_prologue will indeed make it pass in the
1176 stack if necessary). */
1177 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1178 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1179
1180 /* For an arg passed partly in registers and partly in memory,
1181 this is the number of registers used.
1182 For args passed entirely in registers or entirely in memory, zero. */
1183 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1184 ( NUM_ARG_REGS > (CUM).nregs \
1185 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1186 ? NUM_ARG_REGS - (CUM).nregs : 0)
1187
1188 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1189 for a call to a function whose data type is FNTYPE.
1190 For a library call, FNTYPE is 0.
1191 On the ARM, the offset starts at 0. */
1192 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1193 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1194
1195 /* Update the data in CUM to advance over an argument
1196 of mode MODE and data type TYPE.
1197 (TYPE is null for libcalls where that information may not be available.) */
1198 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1199 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1200
1201 /* 1 if N is a possible register number for function argument passing.
1202 On the ARM, r0-r3 are used to pass args. */
1203 #define FUNCTION_ARG_REGNO_P(REGNO) \
1204 ((REGNO) >= 0 && (REGNO) <= 3)
1205
1206 /* Perform any actions needed for a function that is receiving a variable
1207 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1208 of the current parameter. PRETEND_SIZE is a variable that should be set to
1209 the amount of stack that must be pushed by the prolog to pretend that our
1210 caller pushed it.
1211
1212 Normally, this macro will push all remaining incoming registers on the
1213 stack and set PRETEND_SIZE to the length of the registers pushed.
1214
1215 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1216 named arg and all anonymous args onto the stack.
1217 XXX I know the prologue shouldn't be pushing registers, but it is faster
1218 that way. */
1219 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1220 { \
1221 extern int current_function_anonymous_args; \
1222 current_function_anonymous_args = 1; \
1223 if ((CUM).nregs < NUM_ARG_REGS) \
1224 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1225 }
1226
1227 /* Generate assembly output for the start of a function. */
1228 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1229 output_func_prologue ((STREAM), (SIZE))
1230
1231 /* If your target environment doesn't prefix user functions with an
1232 underscore, you may wish to re-define this to prevent any conflicts.
1233 e.g. AOF may prefix mcount with an underscore. */
1234 #ifndef ARM_MCOUNT_NAME
1235 #define ARM_MCOUNT_NAME "*mcount"
1236 #endif
1237
1238 /* Call the function profiler with a given profile label. The Acorn
1239 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1240 On the ARM the full profile code will look like:
1241 .data
1242 LP1
1243 .word 0
1244 .text
1245 mov ip, lr
1246 bl mcount
1247 .word LP1
1248
1249 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1250 will output the .text section.
1251
1252 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1253 ``prof'' doesn't seem to mind about this! */
1254 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1255 { \
1256 char temp[20]; \
1257 rtx sym; \
1258 \
1259 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1260 IP_REGNUM, LR_REGNUM); \
1261 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1262 fputc ('\n', STREAM); \
1263 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1264 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1265 ASM_OUTPUT_INT (STREAM, sym); \
1266 }
1267
1268 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1269 the stack pointer does not matter. The value is tested only in
1270 functions that have frame pointers.
1271 No definition is equivalent to always zero.
1272
1273 On the ARM, the function epilogue recovers the stack pointer from the
1274 frame. */
1275 #define EXIT_IGNORE_STACK 1
1276
1277 /* Generate the assembly code for function exit. */
1278 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1279 output_func_epilogue (SIZE)
1280
1281 /* Determine if the epilogue should be output as RTL.
1282 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1283 #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND)
1284
1285 /* Definitions for register eliminations.
1286
1287 This is an array of structures. Each structure initializes one pair
1288 of eliminable registers. The "from" register number is given first,
1289 followed by "to". Eliminations of the same "from" register are listed
1290 in order of preference.
1291
1292 We have two registers that can be eliminated on the ARM. First, the
1293 arg pointer register can often be eliminated in favor of the stack
1294 pointer register. Secondly, the pseudo frame pointer register can always
1295 be eliminated; it is replaced with either the stack or the real frame
1296 pointer. */
1297
1298 #define ELIMINABLE_REGS \
1299 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1300 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
1301 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1302 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
1303
1304 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1305 Frame pointer elimination is automatically handled.
1306
1307 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1308 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1309 pointer, we must eliminate FRAME_POINTER_REGNUM into
1310 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1311 #define CAN_ELIMINATE(FROM, TO) \
1312 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1313
1314 /* Define the offset between two registers, one to be eliminated, and the other
1315 its replacement, at the start of a routine. */
1316 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1317 { \
1318 int volatile_func = arm_volatile_func (); \
1319 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1320 (OFFSET) = 0; \
1321 else if ((FROM) == FRAME_POINTER_REGNUM \
1322 && (TO) == STACK_POINTER_REGNUM) \
1323 (OFFSET) = current_function_outgoing_args_size \
1324 + ((get_frame_size () + 3) & ~3); \
1325 else \
1326 { \
1327 int regno; \
1328 int offset = 12; \
1329 int saved_hard_reg = 0; \
1330 \
1331 if (! volatile_func) \
1332 { \
1333 for (regno = 0; regno <= 10; regno++) \
1334 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1335 saved_hard_reg = 1, offset += 4; \
1336 /* PIC register is a fixed reg, so call_used_regs set. */ \
1337 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1338 saved_hard_reg = 1, offset += 4; \
1339 for (regno = 16; regno <=23; regno++) \
1340 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1341 offset += 12; \
1342 } \
1343 if ((FROM) == FRAME_POINTER_REGNUM) \
1344 (OFFSET) = -offset; \
1345 else \
1346 { \
1347 if (! frame_pointer_needed) \
1348 offset -= 16; \
1349 if (! volatile_func \
1350 && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \
1351 offset += 4; \
1352 offset += current_function_outgoing_args_size; \
1353 (OFFSET) = ((get_frame_size () + 3) & ~3) + offset; \
1354 } \
1355 } \
1356 }
1357
1358 /* Output assembler code for a block containing the constant parts
1359 of a trampoline, leaving space for the variable parts.
1360
1361 On the ARM, (if r8 is the static chain regnum, and remembering that
1362 referencing pc adds an offset of 8) the trampoline looks like:
1363 ldr r8, [pc, #0]
1364 ldr pc, [pc]
1365 .word static chain value
1366 .word function's address
1367 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1368 #define TRAMPOLINE_TEMPLATE(FILE) \
1369 { \
1370 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1371 REGISTER_PREFIX, reg_names[STATIC_CHAIN_REGNUM], \
1372 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1373 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1374 REGISTER_PREFIX, reg_names[PC_REGNUM], \
1375 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1376 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1377 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1378 }
1379
1380 /* Length in units of the trampoline for entering a nested function. */
1381 #define TRAMPOLINE_SIZE 16
1382
1383 /* Alignment required for a trampoline in units. */
1384 #define TRAMPOLINE_ALIGN 4
1385
1386 /* Emit RTL insns to initialize the variable parts of a trampoline.
1387 FNADDR is an RTX for the address of the function's pure code.
1388 CXT is an RTX for the static chain value for the function. */
1389 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1390 { \
1391 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1392 (CXT)); \
1393 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1394 (FNADDR)); \
1395 }
1396
1397 \f
1398 /* Addressing modes, and classification of registers for them. */
1399
1400 #define HAVE_POST_INCREMENT 1
1401 #define HAVE_PRE_INCREMENT 1
1402 #define HAVE_POST_DECREMENT 1
1403 #define HAVE_PRE_DECREMENT 1
1404
1405 /* Macros to check register numbers against specific register classes. */
1406
1407 /* These assume that REGNO is a hard or pseudo reg number.
1408 They give nonzero only if REGNO is a hard reg of the suitable class
1409 or a pseudo reg currently allocated to a suitable hard reg.
1410 Since they use reg_renumber, they are safe only once reg_renumber
1411 has been allocated, which happens in local-alloc.c.
1412
1413 On the ARM, don't allow the pc to be used. */
1414 #define REGNO_OK_FOR_BASE_P(REGNO) \
1415 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1416 || (REGNO) == ARG_POINTER_REGNUM \
1417 || (unsigned) reg_renumber[(REGNO)] < 15 \
1418 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1419 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1420 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1421 REGNO_OK_FOR_BASE_P(REGNO)
1422
1423 /* Maximum number of registers that can appear in a valid memory address.
1424 Shifts in addresses can't be by a register. */
1425
1426 #define MAX_REGS_PER_ADDRESS 2
1427
1428 /* Recognize any constant value that is a valid address. */
1429 /* XXX We can address any constant, eventually... */
1430
1431 #ifdef AOF_ASSEMBLER
1432
1433 #define CONSTANT_ADDRESS_P(X) \
1434 (GET_CODE (X) == SYMBOL_REF \
1435 && CONSTANT_POOL_ADDRESS_P (X))
1436
1437 #else
1438
1439 #define CONSTANT_ADDRESS_P(X) \
1440 (GET_CODE (X) == SYMBOL_REF \
1441 && (CONSTANT_POOL_ADDRESS_P (X) \
1442 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1443
1444 #endif /* AOF_ASSEMBLER */
1445
1446 /* Nonzero if the constant value X is a legitimate general operand.
1447 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1448
1449 On the ARM, allow any integer (invalid ones are removed later by insn
1450 patterns), nice doubles and symbol_refs which refer to the function's
1451 constant pool XXX.
1452
1453 When generating pic allow anything. */
1454 #define LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1455 \f
1456 /* Special characters prefixed to function names
1457 in order to encode attribute like information.
1458 Note, '@' and '*' have already been taken. */
1459 #define SHORT_CALL_FLAG_CHAR '^'
1460 #define LONG_CALL_FLAG_CHAR '#'
1461
1462 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1463 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1464
1465 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1466 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1467
1468 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1469 #define SUBTARGET_NAME_ENCODING_LENGTHS
1470 #endif
1471
1472 /* This is a C fragement for the inside of a switch statement.
1473 Each case label should return the number of characters to
1474 be stripped from the start of a function's name, if that
1475 name starts with the indicated character. */
1476 #define ARM_NAME_ENCODING_LENGTHS \
1477 case SHORT_CALL_FLAG_CHAR: return 1; \
1478 case LONG_CALL_FLAG_CHAR: return 1; \
1479 case '*': return 1; \
1480 SUBTARGET_NAME_ENCODING_LENGTHS
1481
1482 /* This has to be handled by a function because more than part of the
1483 ARM backend uses funciton name prefixes to encode attributes. */
1484 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1485 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1486
1487 /* This is how to output a reference to a user-level label named NAME.
1488 `assemble_name' uses this. */
1489 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1490 fprintf (FILE, "%s%s", USER_LABEL_PREFIX, arm_strip_name_encoding (NAME))
1491
1492 /* If we are referencing a function that is weak then encode a long call
1493 flag in the function name, otherwise if the function is static or
1494 or known to be defined in this file then encode a short call flag.
1495 This macro is used inside the ENCODE_SECTION macro. */
1496 #define ARM_ENCODE_CALL_TYPE(decl) \
1497 if (TREE_CODE (decl) == FUNCTION_DECL) \
1498 { \
1499 if (DECL_WEAK (decl)) \
1500 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1501 else if (! TREE_PUBLIC (decl)) \
1502 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1503 } \
1504
1505 /* Symbols in the text segment can be accessed without indirecting via the
1506 constant pool; it may take an extra binary operation, but this is still
1507 faster than indirecting via memory. Don't do this when not optimizing,
1508 since we won't be calculating al of the offsets necessary to do this
1509 simplification. */
1510 /* This doesn't work with AOF syntax, since the string table may be in
1511 a different AREA. */
1512 #ifndef AOF_ASSEMBLER
1513 #define ENCODE_SECTION_INFO(decl) \
1514 { \
1515 if (optimize > 0 && TREE_CONSTANT (decl) \
1516 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1517 { \
1518 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1519 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1520 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1521 } \
1522 ARM_ENCODE_CALL_TYPE (decl) \
1523 }
1524 #else
1525 #define ENCODE_SECTION_INFO(decl) \
1526 { \
1527 ARM_ENCODE_CALL_TYPE (decl) \
1528 }
1529 #endif
1530
1531 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1532 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1533
1534 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1535 and check its validity for a certain class.
1536 We have two alternate definitions for each of them.
1537 The usual definition accepts all pseudo regs; the other rejects
1538 them unless they have been allocated suitable hard regs.
1539 The symbol REG_OK_STRICT causes the latter definition to be used. */
1540 #ifndef REG_OK_STRICT
1541
1542 /* Nonzero if X is a hard reg that can be used as a base reg
1543 or if it is a pseudo reg. */
1544 #define REG_OK_FOR_BASE_P(X) \
1545 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1546 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1547
1548 /* Nonzero if X is a hard reg that can be used as an index
1549 or if it is a pseudo reg. */
1550 #define REG_OK_FOR_INDEX_P(X) \
1551 REG_OK_FOR_BASE_P(X)
1552
1553 #define REG_OK_FOR_PRE_POST_P(X) \
1554 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1555 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1556
1557 #else
1558
1559 /* Nonzero if X is a hard reg that can be used as a base reg. */
1560 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1561
1562 /* Nonzero if X is a hard reg that can be used as an index. */
1563 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1564
1565 #define REG_OK_FOR_PRE_POST_P(X) \
1566 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1567 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1568 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1569 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1570
1571 #endif
1572 \f
1573 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1574 that is a valid memory address for an instruction.
1575 The MODE argument is the machine mode for the MEM expression
1576 that wants to use this address.
1577
1578 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1579 #define BASE_REGISTER_RTX_P(X) \
1580 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1581
1582 #define INDEX_REGISTER_RTX_P(X) \
1583 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1584
1585 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1586 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1587 only be small constants. */
1588 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1589 do \
1590 { \
1591 HOST_WIDE_INT range; \
1592 enum rtx_code code = GET_CODE (INDEX); \
1593 \
1594 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1595 { \
1596 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1597 && INTVAL (INDEX) > -1024 \
1598 && (INTVAL (INDEX) & 3) == 0) \
1599 goto LABEL; \
1600 } \
1601 else \
1602 { \
1603 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1604 goto LABEL; \
1605 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1606 && (! arm_arch4 || (MODE) != HImode)) \
1607 { \
1608 rtx xiop0 = XEXP (INDEX, 0); \
1609 rtx xiop1 = XEXP (INDEX, 1); \
1610 if (INDEX_REGISTER_RTX_P (xiop0) \
1611 && power_of_two_operand (xiop1, SImode)) \
1612 goto LABEL; \
1613 if (INDEX_REGISTER_RTX_P (xiop1) \
1614 && power_of_two_operand (xiop0, SImode)) \
1615 goto LABEL; \
1616 } \
1617 if (GET_MODE_SIZE (MODE) <= 4 \
1618 && (code == LSHIFTRT || code == ASHIFTRT \
1619 || code == ASHIFT || code == ROTATERT) \
1620 && (! arm_arch4 || (MODE) != HImode)) \
1621 { \
1622 rtx op = XEXP (INDEX, 1); \
1623 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1624 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1625 && INTVAL (op) <= 31) \
1626 goto LABEL; \
1627 } \
1628 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
1629 range = ((MODE) == HImode || (MODE) == QImode) \
1630 ? (arm_arch4 ? 256 : 4095) : 4096; \
1631 if (code == CONST_INT && INTVAL (INDEX) < range \
1632 && INTVAL (INDEX) > -range) \
1633 goto LABEL; \
1634 } \
1635 } \
1636 while (0)
1637
1638 /* Jump to LABEL if X is a valid address RTX. This must also take
1639 REG_OK_STRICT into account when deciding about valid registers, but it uses
1640 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1641 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1642 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1643 refs must be forced though a static cell to ensure addressability. */
1644 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1645 { \
1646 if (BASE_REGISTER_RTX_P (X)) \
1647 goto LABEL; \
1648 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1649 && GET_CODE (XEXP (X, 0)) == REG \
1650 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1651 goto LABEL; \
1652 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1653 && (GET_CODE (X) == LABEL_REF \
1654 || (GET_CODE (X) == CONST \
1655 && GET_CODE (XEXP ((X), 0)) == PLUS \
1656 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1657 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1658 goto LABEL; \
1659 else if ((MODE) == TImode) \
1660 ; \
1661 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1662 { \
1663 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1664 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1665 { \
1666 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1667 if (val == 4 || val == -4 || val == -8) \
1668 goto LABEL; \
1669 } \
1670 } \
1671 else if (GET_CODE (X) == PLUS) \
1672 { \
1673 rtx xop0 = XEXP(X,0); \
1674 rtx xop1 = XEXP(X,1); \
1675 \
1676 if (BASE_REGISTER_RTX_P (xop0)) \
1677 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1678 else if (BASE_REGISTER_RTX_P (xop1)) \
1679 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1680 } \
1681 /* Reload currently can't handle MINUS, so disable this for now */ \
1682 /* else if (GET_CODE (X) == MINUS) \
1683 { \
1684 rtx xop0 = XEXP (X,0); \
1685 rtx xop1 = XEXP (X,1); \
1686 \
1687 if (BASE_REGISTER_RTX_P (xop0)) \
1688 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1689 } */ \
1690 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1691 && GET_CODE (X) == SYMBOL_REF \
1692 && CONSTANT_POOL_ADDRESS_P (X) \
1693 && ! (flag_pic \
1694 && symbol_mentioned_p (get_pool_constant (X)))) \
1695 goto LABEL; \
1696 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1697 && (GET_MODE_SIZE (MODE) <= 4) \
1698 && GET_CODE (XEXP (X, 0)) == REG \
1699 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1700 goto LABEL; \
1701 }
1702 \f
1703 /* Try machine-dependent ways of modifying an illegitimate address
1704 to be legitimate. If we find one, return the new, valid address.
1705 This macro is used in only one place: `memory_address' in explow.c.
1706
1707 OLDX is the address as it was before break_out_memory_refs was called.
1708 In some cases it is useful to look at this to decide what needs to be done.
1709
1710 MODE and WIN are passed so that this macro can use
1711 GO_IF_LEGITIMATE_ADDRESS.
1712
1713 It is always safe for this macro to do nothing. It exists to recognize
1714 opportunities to optimize the output.
1715
1716 On the ARM, try to convert [REG, #BIGCONST]
1717 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1718 where VALIDCONST == 0 in case of TImode. */
1719 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1720 { \
1721 if (GET_CODE (X) == PLUS) \
1722 { \
1723 rtx xop0 = XEXP (X, 0); \
1724 rtx xop1 = XEXP (X, 1); \
1725 \
1726 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1727 xop0 = force_reg (SImode, xop0); \
1728 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1729 xop1 = force_reg (SImode, xop1); \
1730 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1731 { \
1732 HOST_WIDE_INT n, low_n; \
1733 rtx base_reg, val; \
1734 n = INTVAL (xop1); \
1735 \
1736 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1737 { \
1738 low_n = n & 0x0f; \
1739 n &= ~0x0f; \
1740 if (low_n > 4) \
1741 { \
1742 n += 16; \
1743 low_n -= 16; \
1744 } \
1745 } \
1746 else \
1747 { \
1748 low_n = ((MODE) == TImode ? 0 \
1749 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1750 n -= low_n; \
1751 } \
1752 base_reg = gen_reg_rtx (SImode); \
1753 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
1754 GEN_INT (n)), NULL_RTX); \
1755 emit_move_insn (base_reg, val); \
1756 (X) = (low_n == 0 ? base_reg \
1757 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
1758 } \
1759 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1760 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
1761 } \
1762 else if (GET_CODE (X) == MINUS) \
1763 { \
1764 rtx xop0 = XEXP (X, 0); \
1765 rtx xop1 = XEXP (X, 1); \
1766 \
1767 if (CONSTANT_P (xop0)) \
1768 xop0 = force_reg (SImode, xop0); \
1769 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1770 xop1 = force_reg (SImode, xop1); \
1771 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1772 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
1773 } \
1774 if (flag_pic) \
1775 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1776 if (memory_address_p (MODE, X)) \
1777 goto WIN; \
1778 }
1779
1780 /* Go to LABEL if ADDR (a legitimate address expression)
1781 has an effect that depends on the machine mode it is used for. */
1782 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1783 { \
1784 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1785 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1786 goto LABEL; \
1787 }
1788 \f
1789 /* Specify the machine mode that this machine uses
1790 for the index in the tablejump instruction. */
1791 #define CASE_VECTOR_MODE SImode
1792
1793 /* Define as C expression which evaluates to nonzero if the tablejump
1794 instruction expects the table to contain offsets from the address of the
1795 table.
1796 Do not define this if the table should contain absolute addresses. */
1797 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1798
1799 /* Specify the tree operation to be used to convert reals to integers. */
1800 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1801
1802 /* This is the kind of divide that is easiest to do in the general case. */
1803 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1804
1805 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1806 unsigned is probably best, but may break some code. */
1807 #ifndef DEFAULT_SIGNED_CHAR
1808 #define DEFAULT_SIGNED_CHAR 0
1809 #endif
1810
1811 /* Don't cse the address of the function being compiled. */
1812 #define NO_RECURSIVE_FUNCTION_CSE 1
1813
1814 /* Max number of bytes we can move from memory to memory
1815 in one reasonably fast instruction. */
1816 #define MOVE_MAX 4
1817
1818 /* Define if operations between registers always perform the operation
1819 on the full register even if a narrower mode is specified. */
1820 #define WORD_REGISTER_OPERATIONS
1821
1822 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1823 will either zero-extend or sign-extend. The value of this macro should
1824 be the code that says which one of the two operations is implicitly
1825 done, NIL if none. */
1826 #define LOAD_EXTEND_OP(MODE) \
1827 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1828 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1829
1830 /* Define this if zero-extension is slow (more than one real instruction).
1831 On the ARM, it is more than one instruction only if not fetching from
1832 memory. */
1833 /* #define SLOW_ZERO_EXTEND */
1834
1835 /* Nonzero if access to memory by bytes is slow and undesirable. */
1836 #define SLOW_BYTE_ACCESS 0
1837
1838 /* Immediate shift counts are truncated by the output routines (or was it
1839 the assembler?). Shift counts in a register are truncated by ARM. Note
1840 that the native compiler puts too large (> 32) immediate shift counts
1841 into a register and shifts by the register, letting the ARM decide what
1842 to do instead of doing that itself. */
1843 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1844 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1845 On the arm, Y in a register is used modulo 256 for the shift. Only for
1846 rotates is modulo 32 used. */
1847 /* #define SHIFT_COUNT_TRUNCATED 1 */
1848
1849 /* All integers have the same format so truncation is easy. */
1850 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1851
1852 /* Calling from registers is a massive pain. */
1853 #define NO_FUNCTION_CSE 1
1854
1855 /* Chars and shorts should be passed as ints. */
1856 #define PROMOTE_PROTOTYPES 1
1857
1858 /* The machine modes of pointers and functions */
1859 #define Pmode SImode
1860 #define FUNCTION_MODE Pmode
1861
1862 /* The structure type of the machine dependent info field of insns
1863 No uses for this yet. */
1864 /* #define INSN_MACHINE_INFO struct machine_info */
1865
1866 /* The relative costs of various types of constants. Note that cse.c defines
1867 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1868 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1869 case CONST_INT: \
1870 if (const_ok_for_arm (INTVAL (RTX))) \
1871 return (OUTER_CODE) == SET ? 2 : -1; \
1872 else if (OUTER_CODE == AND \
1873 && const_ok_for_arm (~INTVAL (RTX))) \
1874 return -1; \
1875 else if ((OUTER_CODE == COMPARE \
1876 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1877 && const_ok_for_arm (-INTVAL (RTX))) \
1878 return -1; \
1879 else \
1880 return 5; \
1881 case CONST: \
1882 case LABEL_REF: \
1883 case SYMBOL_REF: \
1884 return 6; \
1885 case CONST_DOUBLE: \
1886 if (const_double_rtx_ok_for_fpu (RTX)) \
1887 return (OUTER_CODE) == SET ? 2 : -1; \
1888 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1889 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1890 return -1; \
1891 return(7);
1892
1893 #define ARM_FRAME_RTX(X) \
1894 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1895 || (X) == arg_pointer_rtx)
1896
1897 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
1898 return arm_rtx_costs (X, CODE);
1899
1900 /* Moves to and from memory are quite expensive */
1901 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
1902
1903 /* All address computations that can be done are free, but rtx cost returns
1904 the same for practically all of them. So we weight the different types
1905 of address here in the order (most pref first):
1906 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1907 #define ADDRESS_COST(X) \
1908 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1909 || GET_CODE (X) == SYMBOL_REF) \
1910 ? 0 \
1911 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1912 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1913 ? 10 \
1914 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1915 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1916 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1917 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1918 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1919 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1920 ? 1 : 0)) \
1921 : 4)))))
1922
1923 /* Try to generate sequences that don't involve branches, we can then use
1924 conditional instructions */
1925 #define BRANCH_COST 4
1926
1927 /* A C statement to update the variable COST based on the relationship
1928 between INSN that is dependent on DEP through dependence LINK. */
1929 #define ADJUST_COST(INSN, LINK, DEP, COST) \
1930 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
1931 \f
1932 /* Position Independent Code. */
1933 /* We decide which register to use based on the compilation options and
1934 the assembler in use; this is more general than the APCS restriction of
1935 using sb (r9) all the time. */
1936 extern int arm_pic_register;
1937
1938 /* Used when parsing command line option -mpic-register=. */
1939 extern const char * arm_pic_register_string;
1940
1941 /* The register number of the register used to address a table of static
1942 data addresses in memory. */
1943 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1944
1945 #define FINALIZE_PIC arm_finalize_pic ()
1946
1947 /* We can't directly access anything that contains a symbol,
1948 nor can we indirect via the constant pool. */
1949 #define LEGITIMATE_PIC_OPERAND_P(X) \
1950 ( ! symbol_mentioned_p (X) \
1951 && ! label_mentioned_p (X) \
1952 && (! CONSTANT_POOL_ADDRESS_P (X) \
1953 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
1954 && ! label_mentioned_p (get_pool_constant (X)))))
1955
1956 /* We need to know when we are making a constant pool; this determines
1957 whether data needs to be in the GOT or can be referenced via a GOT
1958 offset. */
1959 extern int making_const_table;
1960 \f
1961 /* If defined, a C expression whose value is nonzero if IDENTIFIER
1962 with arguments ARGS is a valid machine specific attribute for TYPE.
1963 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
1964 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
1965 (arm_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
1966
1967 /* If defined, a C expression whose value is zero if the attributes on
1968 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
1969 two if they are nearly compatible (which causes a warning to be
1970 generated). */
1971 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
1972 (arm_comp_type_attributes (TYPE1, TYPE2))
1973
1974 /* If defined, a C statement that assigns default attributes to newly
1975 defined TYPE. */
1976 #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
1977 arm_set_default_type_attributes (TYPE)
1978
1979 /* Handle pragmas for compatibility with Intel's compilers. */
1980 #define HANDLE_PRAGMA(GET, UNGET, NAME) arm_process_pragma (GET, UNGET, NAME)
1981 \f
1982 /* Condition code information. */
1983 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1984 return the mode to be used for the comparison.
1985 CCFPEmode should be used with floating inequalities,
1986 CCFPmode should be used with floating equalities.
1987 CC_NOOVmode should be used with SImode integer equalities.
1988 CC_Zmode should be used if only the Z flag is set correctly
1989 CCmode should be used otherwise. */
1990
1991 #define EXTRA_CC_MODES \
1992 CC(CC_NOOVmode, "CC_NOOV") \
1993 CC(CC_Zmode, "CC_Z") \
1994 CC(CC_SWPmode, "CC_SWP") \
1995 CC(CCFPmode, "CCFP") \
1996 CC(CCFPEmode, "CCFPE") \
1997 CC(CC_DNEmode, "CC_DNE") \
1998 CC(CC_DEQmode, "CC_DEQ") \
1999 CC(CC_DLEmode, "CC_DLE") \
2000 CC(CC_DLTmode, "CC_DLT") \
2001 CC(CC_DGEmode, "CC_DGE") \
2002 CC(CC_DGTmode, "CC_DGT") \
2003 CC(CC_DLEUmode, "CC_DLEU") \
2004 CC(CC_DLTUmode, "CC_DLTU") \
2005 CC(CC_DGEUmode, "CC_DGEU") \
2006 CC(CC_DGTUmode, "CC_DGTU") \
2007 CC(CC_Cmode, "CC_C")
2008
2009 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
2010
2011 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2012
2013 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2014 do \
2015 { \
2016 if (GET_CODE (OP1) == CONST_INT \
2017 && ! (const_ok_for_arm (INTVAL (OP1)) \
2018 || (const_ok_for_arm (- INTVAL (OP1))))) \
2019 { \
2020 rtx const_op = OP1; \
2021 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2022 OP1 = const_op; \
2023 } \
2024 } \
2025 while (0)
2026
2027 #define STORE_FLAG_VALUE 1
2028
2029 /* Define the information needed to generate branch insns. This is
2030 stored from the compare operation. Note that we can't use "rtx" here
2031 since it hasn't been defined! */
2032
2033 extern struct rtx_def * arm_compare_op0;
2034 extern struct rtx_def * arm_compare_op1;
2035
2036 /* Define the codes that are matched by predicates in arm.c */
2037 #define PREDICATE_CODES \
2038 {"s_register_operand", {SUBREG, REG}}, \
2039 {"f_register_operand", {SUBREG, REG}}, \
2040 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2041 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2042 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2043 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2044 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2045 {"offsettable_memory_operand", {MEM}}, \
2046 {"bad_signed_byte_operand", {MEM}}, \
2047 {"alignable_memory_operand", {MEM}}, \
2048 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2049 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2050 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2051 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2052 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2053 {"load_multiple_operation", {PARALLEL}}, \
2054 {"store_multiple_operation", {PARALLEL}}, \
2055 {"equality_operator", {EQ, NE}}, \
2056 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2057 {"const_shift_operand", {CONST_INT}}, \
2058 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2059 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2060 {"multi_register_push", {PARALLEL}}, \
2061 {"cc_register", {REG}}, \
2062 {"logical_binary_operator", {AND, IOR, XOR}}, \
2063 {"dominant_cc_register", {REG}},
2064
2065 \f
2066
2067 /* Gcc puts the pool in the wrong place for ARM, since we can only
2068 load addresses a limited distance around the pc. We do some
2069 special munging to move the constant pool values to the correct
2070 point in the code. */
2071 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
2072
2073 /* Output an internal label definition. */
2074 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2075 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2076 do \
2077 { \
2078 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2079 \
2080 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2081 && !strcmp (PREFIX, "L")) \
2082 { \
2083 arm_ccfsm_state = 0; \
2084 arm_target_insn = NULL; \
2085 } \
2086 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2087 ASM_OUTPUT_LABEL (STREAM, s); \
2088 } \
2089 while (0)
2090 #endif
2091
2092 /* Output a push or a pop instruction (only used when profiling). */
2093 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2094 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
2095
2096 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2097 asm_fprintf (STREAM,"\tldmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
2098
2099 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2100 do \
2101 { \
2102 if (TARGET_POKE_FUNCTION_NAME) \
2103 arm_poke_function_name (STREAM, NAME); \
2104 } \
2105 while (0)
2106
2107 /* Target characters. */
2108 #define TARGET_BELL 007
2109 #define TARGET_BS 010
2110 #define TARGET_TAB 011
2111 #define TARGET_NEWLINE 012
2112 #define TARGET_VT 013
2113 #define TARGET_FF 014
2114 #define TARGET_CR 015
2115 \f
2116 /* Only perform branch elimination (by making instructions conditional) if
2117 we're optimising. Otherwise it's of no use anyway. */
2118 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2119 if (optimize) \
2120 arm_final_prescan_insn (INSN)
2121
2122 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2123 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
2124
2125 /* Output an operand of an instruction. */
2126 #define PRINT_OPERAND(STREAM, X, CODE) \
2127 arm_print_operand (STREAM, X, CODE)
2128
2129 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2130 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
2131 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffffUL) | \
2132 (((x) & (unsigned HOST_WIDE_INT) 0x80000000UL) \
2133 ? ((~ (HOST_WIDE_INT) 0) \
2134 & ~ (unsigned HOST_WIDE_INT) 0xffffffffUL) \
2135 : 0))))
2136
2137 /* Output the address of an operand. */
2138 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
2139 { \
2140 int is_minus = GET_CODE (X) == MINUS; \
2141 \
2142 if (GET_CODE (X) == REG) \
2143 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2144 else if (GET_CODE (X) == PLUS || is_minus) \
2145 { \
2146 rtx base = XEXP (X, 0); \
2147 rtx index = XEXP (X, 1); \
2148 int base_reg; \
2149 HOST_WIDE_INT offset = 0; \
2150 if (GET_CODE (base) != REG) \
2151 { \
2152 /* Ensure that BASE is a register (one of them must be). */ \
2153 rtx temp = base; \
2154 base = index; \
2155 index = temp; \
2156 } \
2157 base_reg = REGNO (base); \
2158 switch (GET_CODE (index)) \
2159 { \
2160 case CONST_INT: \
2161 offset = INTVAL (index); \
2162 if (is_minus) \
2163 offset = -offset; \
2164 asm_fprintf (STREAM, "[%r, #%d]", base_reg, offset); \
2165 break; \
2166 \
2167 case REG: \
2168 asm_fprintf (STREAM, "[%r, %s%r]", base_reg, \
2169 is_minus ? "-" : "", REGNO (index)); \
2170 break; \
2171 \
2172 case MULT: \
2173 case ASHIFTRT: \
2174 case LSHIFTRT: \
2175 case ASHIFT: \
2176 case ROTATERT: \
2177 { \
2178 asm_fprintf (STREAM, "[%r, %s%r", base_reg, \
2179 is_minus ? "-" : "", REGNO (XEXP (index, 0))); \
2180 arm_print_operand (STREAM, index, 'S'); \
2181 fputs ("]", STREAM); \
2182 break; \
2183 } \
2184 \
2185 default: \
2186 abort(); \
2187 } \
2188 } \
2189 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2190 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2191 { \
2192 extern int output_memory_reference_mode; \
2193 \
2194 if (GET_CODE (XEXP (X, 0)) != REG) \
2195 abort (); \
2196 \
2197 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2198 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2199 REGNO (XEXP (X, 0)), \
2200 GET_CODE (X) == PRE_DEC ? "-" : "", \
2201 GET_MODE_SIZE (output_memory_reference_mode)); \
2202 else \
2203 asm_fprintf (STREAM, "[%r], #%s%d", \
2204 REGNO (XEXP (X, 0)), \
2205 GET_CODE (X) == POST_DEC ? "-" : "", \
2206 GET_MODE_SIZE (output_memory_reference_mode)); \
2207 } \
2208 else output_addr_const (STREAM, X); \
2209 }
2210
2211 /* Handles PIC addr specially */
2212 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
2213 { \
2214 if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \
2215 { \
2216 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2217 fputs (" - (", STREAM); \
2218 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2219 fputs (")", STREAM); \
2220 } \
2221 else output_addr_const (STREAM, X); \
2222 \
2223 /* Mark symbols as position independent. We only do this in the \
2224 .text segment, not in the .data segment. */ \
2225 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2226 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2227 { \
2228 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2229 fprintf (STREAM, "(GOTOFF)"); \
2230 else if (GET_CODE (X) == LABEL_REF) \
2231 fprintf (STREAM, "(GOTOFF)"); \
2232 else \
2233 fprintf (STREAM, "(GOT)"); \
2234 } \
2235 }
2236
2237 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2238 Used for C++ multiple inheritance. */
2239 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2240 do \
2241 { \
2242 int mi_delta = (DELTA); \
2243 char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2244 int shift = 0; \
2245 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2246 ? 1 : 0); \
2247 if (mi_delta < 0) mi_delta = -mi_delta; \
2248 while (mi_delta != 0) \
2249 { \
2250 if (mi_delta & (3 << shift) == 0) \
2251 shift += 2; \
2252 else \
2253 { \
2254 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2255 mi_op, this_regno, this_regno, \
2256 mi_delta & (0xff << shift)); \
2257 mi_delta &= ~(0xff << shift); \
2258 shift += 8; \
2259 } \
2260 } \
2261 fputs ("\tb\t", FILE); \
2262 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2263 if (NEED_PLT_RELOC) \
2264 fputs ("(PLT)", FILE); \
2265 fputc ('\n', FILE); \
2266 } \
2267 while (0)
2268
2269 /* A C expression whose value is RTL representing the value of the return
2270 address for the frame COUNT steps up from the current frame. */
2271
2272 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2273 ((COUNT == 0) \
2274 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \
2275 : NULL_RTX)
2276
2277 /* Used to mask out junk bits from the return address, such as
2278 processor state, interrupt status, condition codes and the like. */
2279 #define MASK_RETURN_ADDR \
2280 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2281 in 26 bit mode, the condition codes must be masked out of the \
2282 return address. This does not apply to ARM6 and later processors \
2283 when running in 32 bit mode. */ \
2284 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
2285
2286 #endif /* __ARM_H__ */
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