gcc/config/aarch64/aarch64.h

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2017 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #ifndef GCC_AARCH64_H
  23 #define GCC_AARCH64_H
  24
  25 /* Target CPU builtins.  */
  26 #define TARGET_CPU_CPP_BUILTINS()       \
  27   aarch64_cpu_cpp_builtins (pfile)
  28
  29 \f
  30
  31 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas ()
  32
  33 /* Target machine storage layout.  */
  34
  35 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  36   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  37       && GET_MODE_SIZE (MODE) < 4)              \
  38     {                                           \
  39       if (MODE == QImode || MODE == HImode)     \
  40         {                                       \
  41           MODE = SImode;                        \
  42         }                                       \
  43     }
  44
  45 /* Bits are always numbered from the LSBit.  */
  46 #define BITS_BIG_ENDIAN 0
  47
  48 /* Big/little-endian flavour.  */
  49 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
  50 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
  51
  52 /* AdvSIMD is supported in the default configuration, unless disabled by
  53    -mgeneral-regs-only or by the +nosimd extension.  */
  54 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)
  55 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)
  56
  57 #define UNITS_PER_WORD          8
  58
  59 #define UNITS_PER_VREG          16
  60
  61 #define PARM_BOUNDARY           64
  62
  63 #define STACK_BOUNDARY          128
  64
  65 #define FUNCTION_BOUNDARY       32
  66
  67 #define EMPTY_FIELD_BOUNDARY    32
  68
  69 #define BIGGEST_ALIGNMENT       128
  70
  71 #define SHORT_TYPE_SIZE         16
  72
  73 #define INT_TYPE_SIZE           32
  74
  75 #define LONG_TYPE_SIZE          (TARGET_ILP32 ? 32 : 64)
  76
  77 #define POINTER_SIZE            (TARGET_ILP32 ? 32 : 64)
  78
  79 #define LONG_LONG_TYPE_SIZE     64
  80
  81 #define FLOAT_TYPE_SIZE         32
  82
  83 #define DOUBLE_TYPE_SIZE        64
  84
  85 #define LONG_DOUBLE_TYPE_SIZE   128
  86
  87 /* The architecture reserves all bits of the address for hardware use,
  88    so the vbit must go into the delta field of pointers to member
  89    functions.  This is the same config as that in the AArch32
  90    port.  */
  91 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
  92
  93 /* Align definitions of arrays, unions and structures so that
  94    initializations and copies can be made more efficient.  This is not
  95    ABI-changing, so it only affects places where we can see the
  96    definition.  Increasing the alignment tends to introduce padding,
  97    so don't do this when optimizing for size/conserving stack space.  */
  98 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN)                      \
  99   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 100     && (TREE_CODE (EXP) == ARRAY_TYPE                                   \
 101         || TREE_CODE (EXP) == UNION_TYPE                                \
 102         || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 103
 104 /* Align global data.  */
 105 #define DATA_ALIGNMENT(EXP, ALIGN)                      \
 106   AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN)
 107
 108 /* Similarly, make sure that objects on the stack are sensibly aligned.  */
 109 #define LOCAL_ALIGNMENT(EXP, ALIGN)                             \
 110   AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN)
 111
 112 #define STRUCTURE_SIZE_BOUNDARY         8
 113
 114 /* Defined by the ABI */
 115 #define WCHAR_TYPE "unsigned int"
 116 #define WCHAR_TYPE_SIZE                 32
 117
 118 /* Using long long breaks -ansi and -std=c90, so these will need to be
 119    made conditional for an LLP64 ABI.  */
 120
 121 #define SIZE_TYPE       "long unsigned int"
 122
 123 #define PTRDIFF_TYPE    "long int"
 124
 125 #define PCC_BITFIELD_TYPE_MATTERS       1
 126
 127 /* Major revision number of the ARM Architecture implemented by the target.  */
 128 extern unsigned aarch64_architecture_version;
 129
 130 /* Instruction tuning/selection flags.  */
 131
 132 /* Bit values used to identify processor capabilities.  */
 133 #define AARCH64_FL_SIMD       (1 << 0)  /* Has SIMD instructions.  */
 134 #define AARCH64_FL_FP         (1 << 1)  /* Has FP.  */
 135 #define AARCH64_FL_CRYPTO     (1 << 2)  /* Has crypto.  */
 136 #define AARCH64_FL_CRC        (1 << 3)  /* Has CRC.  */
 137 /* ARMv8.1-A architecture extensions.  */
 138 #define AARCH64_FL_LSE        (1 << 4)  /* Has Large System Extensions.  */
 139 #define AARCH64_FL_RDMA       (1 << 5)  /* Has Round Double Multiply Add.  */
 140 #define AARCH64_FL_V8_1       (1 << 6)  /* Has ARMv8.1-A extensions.  */
 141 /* ARMv8.2-A architecture extensions.  */
 142 #define AARCH64_FL_V8_2       (1 << 8)  /* Has ARMv8.2-A features.  */
 143 #define AARCH64_FL_F16        (1 << 9)  /* Has ARMv8.2-A FP16 extensions.  */
 144 /* ARMv8.3-A architecture extensions.  */
 145 #define AARCH64_FL_V8_3       (1 << 10)  /* Has ARMv8.3-A features.  */
 146 #define AARCH64_FL_RCPC       (1 << 11)  /* Has support for RCpc model.  */
 147
 148 /* Has FP and SIMD.  */
 149 #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
 150
 151 /* Has FP without SIMD.  */
 152 #define AARCH64_FL_FPQ16      (AARCH64_FL_FP & ~AARCH64_FL_SIMD)
 153
 154 /* Architecture flags that effect instruction selection.  */
 155 #define AARCH64_FL_FOR_ARCH8       (AARCH64_FL_FPSIMD)
 156 #define AARCH64_FL_FOR_ARCH8_1                         \
 157   (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \
 158    | AARCH64_FL_RDMA | AARCH64_FL_V8_1)
 159 #define AARCH64_FL_FOR_ARCH8_2                  \
 160   (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2)
 161 #define AARCH64_FL_FOR_ARCH8_3                  \
 162   (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3)
 163
 164 /* Macros to test ISA flags.  */
 165
 166 #define AARCH64_ISA_CRC            (aarch64_isa_flags & AARCH64_FL_CRC)
 167 #define AARCH64_ISA_CRYPTO         (aarch64_isa_flags & AARCH64_FL_CRYPTO)
 168 #define AARCH64_ISA_FP             (aarch64_isa_flags & AARCH64_FL_FP)
 169 #define AARCH64_ISA_SIMD           (aarch64_isa_flags & AARCH64_FL_SIMD)
 170 #define AARCH64_ISA_LSE            (aarch64_isa_flags & AARCH64_FL_LSE)
 171 #define AARCH64_ISA_RDMA           (aarch64_isa_flags & AARCH64_FL_RDMA)
 172 #define AARCH64_ISA_V8_2           (aarch64_isa_flags & AARCH64_FL_V8_2)
 173 #define AARCH64_ISA_F16            (aarch64_isa_flags & AARCH64_FL_F16)
 174 #define AARCH64_ISA_V8_3           (aarch64_isa_flags & AARCH64_FL_V8_3)
 175
 176 /* Crypto is an optional extension to AdvSIMD.  */
 177 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
 178
 179 /* CRC instructions that can be enabled through +crc arch extension.  */
 180 #define TARGET_CRC32 (AARCH64_ISA_CRC)
 181
 182 /* Atomic instructions that can be enabled through the +lse extension.  */
 183 #define TARGET_LSE (AARCH64_ISA_LSE)
 184
 185 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension.  */
 186 #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16)
 187 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
 188
 189 /* ARMv8.3-A features.  */
 190 #define TARGET_ARMV8_3  (AARCH64_ISA_V8_3)
 191
 192 /* Make sure this is always defined so we don't have to check for ifdefs
 193    but rather use normal ifs.  */
 194 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
 195 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0
 196 #else
 197 #undef TARGET_FIX_ERR_A53_835769_DEFAULT
 198 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1
 199 #endif
 200
 201 /* Apply the workaround for Cortex-A53 erratum 835769.  */
 202 #define TARGET_FIX_ERR_A53_835769       \
 203   ((aarch64_fix_a53_err835769 == 2)     \
 204   ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769)
 205
 206 /* Make sure this is always defined so we don't have to check for ifdefs
 207    but rather use normal ifs.  */
 208 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT
 209 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0
 210 #else
 211 #undef TARGET_FIX_ERR_A53_843419_DEFAULT
 212 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1
 213 #endif
 214
 215 /* Apply the workaround for Cortex-A53 erratum 843419.  */
 216 #define TARGET_FIX_ERR_A53_843419       \
 217   ((aarch64_fix_a53_err843419 == 2)     \
 218   ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
 219
 220 /* ARMv8.1-A Adv.SIMD support.  */
 221 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
 222
 223 /* Standard register usage.  */
 224
 225 /* 31 64-bit general purpose registers R0-R30:
 226    R30          LR (link register)
 227    R29          FP (frame pointer)
 228    R19-R28      Callee-saved registers
 229    R18          The platform register; use as temporary register.
 230    R17          IP1 The second intra-procedure-call temporary register
 231                 (can be used by call veneers and PLT code); otherwise use
 232                 as a temporary register
 233    R16          IP0 The first intra-procedure-call temporary register (can
 234                 be used by call veneers and PLT code); otherwise use as a
 235                 temporary register
 236    R9-R15       Temporary registers
 237    R8           Structure value parameter / temporary register
 238    R0-R7        Parameter/result registers
 239
 240    SP           stack pointer, encoded as X/R31 where permitted.
 241    ZR           zero register, encoded as X/R31 elsewhere
 242
 243    32 x 128-bit floating-point/vector registers
 244    V16-V31      Caller-saved (temporary) registers
 245    V8-V15       Callee-saved registers
 246    V0-V7        Parameter/result registers
 247
 248    The vector register V0 holds scalar B0, H0, S0 and D0 in its least
 249    significant bits.  Unlike AArch32 S1 is not packed into D0,
 250    etc.  */
 251
 252 /* Note that we don't mark X30 as a call-clobbered register.  The idea is
 253    that it's really the call instructions themselves which clobber X30.
 254    We don't care what the called function does with it afterwards.
 255
 256    This approach makes it easier to implement sibcalls.  Unlike normal
 257    calls, sibcalls don't clobber X30, so the register reaches the
 258    called function intact.  EPILOGUE_USES says that X30 is useful
 259    to the called function.  */
 260
 261 #define FIXED_REGISTERS                                 \
 262   {                                                     \
 263     0, 0, 0, 0,   0, 0, 0, 0,   /* R0 - R7 */           \
 264     0, 0, 0, 0,   0, 0, 0, 0,   /* R8 - R15 */          \
 265     0, 0, 0, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 266     0, 0, 0, 0,   0, 1, 0, 1,   /* R24 - R30, SP */     \
 267     0, 0, 0, 0,   0, 0, 0, 0,   /* V0 - V7 */           \
 268     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 269     0, 0, 0, 0,   0, 0, 0, 0,   /* V16 - V23 */         \
 270     0, 0, 0, 0,   0, 0, 0, 0,   /* V24 - V31 */         \
 271     1, 1, 1,                    /* SFP, AP, CC */       \
 272   }
 273
 274 #define CALL_USED_REGISTERS                             \
 275   {                                                     \
 276     1, 1, 1, 1,   1, 1, 1, 1,   /* R0 - R7 */           \
 277     1, 1, 1, 1,   1, 1, 1, 1,   /* R8 - R15 */          \
 278     1, 1, 1, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 279     0, 0, 0, 0,   0, 1, 1, 1,   /* R24 - R30, SP */     \
 280     1, 1, 1, 1,   1, 1, 1, 1,   /* V0 - V7 */           \
 281     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 282     1, 1, 1, 1,   1, 1, 1, 1,   /* V16 - V23 */         \
 283     1, 1, 1, 1,   1, 1, 1, 1,   /* V24 - V31 */         \
 284     1, 1, 1,                    /* SFP, AP, CC */       \
 285   }
 286
 287 #define REGISTER_NAMES                                          \
 288   {                                                             \
 289     "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",      \
 290     "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",     \
 291     "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",     \
 292     "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp",      \
 293     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",      \
 294     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",     \
 295     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",     \
 296     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",     \
 297     "sfp", "ap",  "cc",                                         \
 298   }
 299
 300 /* Generate the register aliases for core register N */
 301 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \
 302                      {"w" # N, R0_REGNUM + (N)}
 303
 304 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \
 305                      {"d" # N, V0_REGNUM + (N)}, \
 306                      {"s" # N, V0_REGNUM + (N)}, \
 307                      {"h" # N, V0_REGNUM + (N)}, \
 308                      {"b" # N, V0_REGNUM + (N)}
 309
 310 /* Provide aliases for all of the ISA defined register name forms.
 311    These aliases are convenient for use in the clobber lists of inline
 312    asm statements.  */
 313
 314 #define ADDITIONAL_REGISTER_NAMES \
 315   { R_ALIASES(0),  R_ALIASES(1),  R_ALIASES(2),  R_ALIASES(3),  \
 316     R_ALIASES(4),  R_ALIASES(5),  R_ALIASES(6),  R_ALIASES(7),  \
 317     R_ALIASES(8),  R_ALIASES(9),  R_ALIASES(10), R_ALIASES(11), \
 318     R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \
 319     R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \
 320     R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \
 321     R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \
 322     R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \
 323     V_ALIASES(0),  V_ALIASES(1),  V_ALIASES(2),  V_ALIASES(3),  \
 324     V_ALIASES(4),  V_ALIASES(5),  V_ALIASES(6),  V_ALIASES(7),  \
 325     V_ALIASES(8),  V_ALIASES(9),  V_ALIASES(10), V_ALIASES(11), \
 326     V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \
 327     V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \
 328     V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \
 329     V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \
 330     V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31)  \
 331   }
 332
 333 /* Say that the epilogue uses the return address register.  Note that
 334    in the case of sibcalls, the values "used by the epilogue" are
 335    considered live at the start of the called function.  */
 336
 337 #define EPILOGUE_USES(REGNO) \
 338   (epilogue_completed && (REGNO) == LR_REGNUM)
 339
 340 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 341    the stack pointer does not matter.  The value is tested only in
 342    functions that have frame pointers.  */
 343 #define EXIT_IGNORE_STACK       1
 344
 345 #define STATIC_CHAIN_REGNUM             R18_REGNUM
 346 #define HARD_FRAME_POINTER_REGNUM       R29_REGNUM
 347 #define FRAME_POINTER_REGNUM            SFP_REGNUM
 348 #define STACK_POINTER_REGNUM            SP_REGNUM
 349 #define ARG_POINTER_REGNUM              AP_REGNUM
 350 #define FIRST_PSEUDO_REGISTER           67
 351
 352 /* The number of (integer) argument register available.  */
 353 #define NUM_ARG_REGS                    8
 354 #define NUM_FP_ARG_REGS                 8
 355
 356 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
 357    four members.  */
 358 #define HA_MAX_NUM_FLDS         4
 359
 360 /* External dwarf register number scheme.  These number are used to
 361    identify registers in dwarf debug information, the values are
 362    defined by the AArch64 ABI.  The numbering scheme is independent of
 363    GCC's internal register numbering scheme.  */
 364
 365 #define AARCH64_DWARF_R0        0
 366
 367 /* The number of R registers, note 31! not 32.  */
 368 #define AARCH64_DWARF_NUMBER_R 31
 369
 370 #define AARCH64_DWARF_SP       31
 371 #define AARCH64_DWARF_V0       64
 372
 373 /* The number of V registers.  */
 374 #define AARCH64_DWARF_NUMBER_V 32
 375
 376 /* For signal frames we need to use an alternative return column.  This
 377    value must not correspond to a hard register and must be out of the
 378    range of DWARF_FRAME_REGNUM().  */
 379 #define DWARF_ALT_FRAME_RETURN_COLUMN   \
 380   (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V)
 381
 382 /* We add 1 extra frame register for use as the
 383    DWARF_ALT_FRAME_RETURN_COLUMN.  */
 384 #define DWARF_FRAME_REGISTERS           (DWARF_ALT_FRAME_RETURN_COLUMN + 1)
 385
 386
 387 #define DBX_REGISTER_NUMBER(REGNO)      aarch64_dbx_register_number (REGNO)
 388 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders
 389    can use DWARF_ALT_FRAME_RETURN_COLUMN defined below.  This is just the same
 390    as the default definition in dwarf2out.c.  */
 391 #undef DWARF_FRAME_REGNUM
 392 #define DWARF_FRAME_REGNUM(REGNO)       DBX_REGISTER_NUMBER (REGNO)
 393
 394 #define DWARF_FRAME_RETURN_COLUMN       DWARF_FRAME_REGNUM (LR_REGNUM)
 395
 396 #define DWARF2_UNWIND_INFO 1
 397
 398 /* Use R0 through R3 to pass exception handling information.  */
 399 #define EH_RETURN_DATA_REGNO(N) \
 400   ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM)
 401
 402 /* Select a format to encode pointers in exception handling data.  */
 403 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
 404   aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL))
 405
 406 /* Output the assembly strings we want to add to a function definition.  */
 407 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)      \
 408   aarch64_declare_function_name (STR, NAME, DECL)
 409
 410 /* For EH returns X4 contains the stack adjustment.  */
 411 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, R4_REGNUM)
 412 #define EH_RETURN_HANDLER_RTX  aarch64_eh_return_handler_rtx ()
 413
 414 /* Don't use __builtin_setjmp until we've defined it.  */
 415 #undef DONT_USE_BUILTIN_SETJMP
 416 #define DONT_USE_BUILTIN_SETJMP 1
 417
 418 /* Register in which the structure value is to be returned.  */
 419 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM
 420
 421 /* Non-zero if REGNO is part of the Core register set.
 422
 423    The rather unusual way of expressing this check is to avoid
 424    warnings when building the compiler when R0_REGNUM is 0 and REGNO
 425    is unsigned.  */
 426 #define GP_REGNUM_P(REGNO)                                              \
 427   (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
 428
 429 #define FP_REGNUM_P(REGNO)                      \
 430   (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
 431
 432 #define FP_LO_REGNUM_P(REGNO)            \
 433   (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
 434
 435 \f
 436 /* Register and constant classes.  */
 437
 438 enum reg_class
 439 {
 440   NO_REGS,
 441   CALLER_SAVE_REGS,
 442   GENERAL_REGS,
 443   STACK_REG,
 444   POINTER_REGS,
 445   FP_LO_REGS,
 446   FP_REGS,
 447   POINTER_AND_FP_REGS,
 448   ALL_REGS,
 449   LIM_REG_CLASSES               /* Last */
 450 };
 451
 452 #define N_REG_CLASSES   ((int) LIM_REG_CLASSES)
 453
 454 #define REG_CLASS_NAMES                         \
 455 {                                               \
 456   "NO_REGS",                                    \
 457   "CALLER_SAVE_REGS",                           \
 458   "GENERAL_REGS",                               \
 459   "STACK_REG",                                  \
 460   "POINTER_REGS",                               \
 461   "FP_LO_REGS",                                 \
 462   "FP_REGS",                                    \
 463   "POINTER_AND_FP_REGS",                        \
 464   "ALL_REGS"                                    \
 465 }
 466
 467 #define REG_CLASS_CONTENTS                                              \
 468 {                                                                       \
 469   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 470   { 0x0007ffff, 0x00000000, 0x00000000 },       /* CALLER_SAVE_REGS */  \
 471   { 0x7fffffff, 0x00000000, 0x00000003 },       /* GENERAL_REGS */      \
 472   { 0x80000000, 0x00000000, 0x00000000 },       /* STACK_REG */         \
 473   { 0xffffffff, 0x00000000, 0x00000003 },       /* POINTER_REGS */      \
 474   { 0x00000000, 0x0000ffff, 0x00000000 },       /* FP_LO_REGS  */       \
 475   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS  */          \
 476   { 0xffffffff, 0xffffffff, 0x00000003 },       /* POINTER_AND_FP_REGS */\
 477   { 0xffffffff, 0xffffffff, 0x00000007 }        /* ALL_REGS */          \
 478 }
 479
 480 #define REGNO_REG_CLASS(REGNO)  aarch64_regno_regclass (REGNO)
 481
 482 #define INDEX_REG_CLASS GENERAL_REGS
 483 #define BASE_REG_CLASS  POINTER_REGS
 484
 485 /* Register pairs used to eliminate unneeded registers that point into
 486    the stack frame.  */
 487 #define ELIMINABLE_REGS                                                 \
 488 {                                                                       \
 489   { ARG_POINTER_REGNUM,         STACK_POINTER_REGNUM            },      \
 490   { ARG_POINTER_REGNUM,         HARD_FRAME_POINTER_REGNUM       },      \
 491   { FRAME_POINTER_REGNUM,       STACK_POINTER_REGNUM            },      \
 492   { FRAME_POINTER_REGNUM,       HARD_FRAME_POINTER_REGNUM       },      \
 493 }
 494
 495 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 496   (OFFSET) = aarch64_initial_elimination_offset (FROM, TO)
 497
 498 /* CPU/ARCH option handling.  */
 499 #include "config/aarch64/aarch64-opts.h"
 500
 501 enum target_cpus
 502 {
 503 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
 504   TARGET_CPU_##INTERNAL_IDENT,
 505 #include "aarch64-cores.def"
 506   TARGET_CPU_generic
 507 };
 508
 509 /* If there is no CPU defined at configure, use generic as default.  */
 510 #ifndef TARGET_CPU_DEFAULT
 511 #define TARGET_CPU_DEFAULT \
 512   (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6))
 513 #endif
 514
 515 /* If inserting NOP before a mult-accumulate insn remember to adjust the
 516    length so that conditional branching code is updated appropriately.  */
 517 #define ADJUST_INSN_LENGTH(insn, length)        \
 518   do                                            \
 519     {                                           \
 520        if (aarch64_madd_needs_nop (insn))       \
 521          length += 4;                           \
 522     } while (0)
 523
 524 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)      \
 525     aarch64_final_prescan_insn (INSN);                  \
 526
 527 /* The processor for which instructions should be scheduled.  */
 528 extern enum aarch64_processor aarch64_tune;
 529
 530 /* RTL generation support.  */
 531 #define INIT_EXPANDERS aarch64_init_expanders ()
 532 \f
 533
 534 /* Stack layout; function entry, exit and calling.  */
 535 #define STACK_GROWS_DOWNWARD    1
 536
 537 #define FRAME_GROWS_DOWNWARD    1
 538
 539 #define STARTING_FRAME_OFFSET   0
 540
 541 #define ACCUMULATE_OUTGOING_ARGS        1
 542
 543 #define FIRST_PARM_OFFSET(FNDECL) 0
 544
 545 /* Fix for VFP */
 546 #define LIBCALL_VALUE(MODE)  \
 547   gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM)
 548
 549 #define DEFAULT_PCC_STRUCT_RETURN 0
 550
 551 #ifdef HOST_WIDE_INT
 552 struct GTY (()) aarch64_frame
 553 {
 554   HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
 555
 556   /* The number of extra stack bytes taken up by register varargs.
 557      This area is allocated by the callee at the very top of the
 558      frame.  This value is rounded up to a multiple of
 559      STACK_BOUNDARY.  */
 560   HOST_WIDE_INT saved_varargs_size;
 561
 562   /* The size of the saved callee-save int/FP registers.  */
 563
 564   HOST_WIDE_INT saved_regs_size;
 565
 566   /* Offset from the base of the frame (incomming SP) to the
 567      top of the locals area.  This value is always a multiple of
 568      STACK_BOUNDARY.  */
 569   HOST_WIDE_INT locals_offset;
 570
 571   /* Offset from the base of the frame (incomming SP) to the
 572      hard_frame_pointer.  This value is always a multiple of
 573      STACK_BOUNDARY.  */
 574   HOST_WIDE_INT hard_fp_offset;
 575
 576   /* The size of the frame.  This value is the offset from base of the
 577    * frame (incomming SP) to the stack_pointer.  This value is always
 578    * a multiple of STACK_BOUNDARY.  */
 579   HOST_WIDE_INT frame_size;
 580
 581   /* The size of the initial stack adjustment before saving callee-saves.  */
 582   HOST_WIDE_INT initial_adjust;
 583
 584   /* The writeback value when pushing callee-save registers.
 585      It is zero when no push is used.  */
 586   HOST_WIDE_INT callee_adjust;
 587
 588   /* The offset from SP to the callee-save registers after initial_adjust.
 589      It may be non-zero if no push is used (ie. callee_adjust == 0).  */
 590   HOST_WIDE_INT callee_offset;
 591
 592   /* The size of the stack adjustment after saving callee-saves.  */
 593   HOST_WIDE_INT final_adjust;
 594
 595   unsigned wb_candidate1;
 596   unsigned wb_candidate2;
 597
 598   bool laid_out;
 599 };
 600
 601 typedef struct GTY (()) machine_function
 602 {
 603   struct aarch64_frame frame;
 604   /* One entry for each hard register.  */
 605   bool reg_is_wrapped_separately[LAST_SAVED_REGNUM];
 606 } machine_function;
 607 #endif
 608
 609 /* Which ABI to use.  */
 610 enum aarch64_abi_type
 611 {
 612   AARCH64_ABI_LP64 = 0,
 613   AARCH64_ABI_ILP32 = 1
 614 };
 615
 616 #ifndef AARCH64_ABI_DEFAULT
 617 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
 618 #endif
 619
 620 #define TARGET_ILP32    (aarch64_abi & AARCH64_ABI_ILP32)
 621
 622 enum arm_pcs
 623 {
 624   ARM_PCS_AAPCS64,              /* Base standard AAPCS for 64 bit.  */
 625   ARM_PCS_UNKNOWN
 626 };
 627
 628
 629
 630
 631 /* We can't use machine_mode inside a generator file because it
 632    hasn't been created yet; we shouldn't be using any code that
 633    needs the real definition though, so this ought to be safe.  */
 634 #ifdef GENERATOR_FILE
 635 #define MACHMODE int
 636 #else
 637 #include "insn-modes.h"
 638 #define MACHMODE machine_mode
 639 #endif
 640
 641 #ifndef USED_FOR_TARGET
 642 /* AAPCS related state tracking.  */
 643 typedef struct
 644 {
 645   enum arm_pcs pcs_variant;
 646   int aapcs_arg_processed;      /* No need to lay out this argument again.  */
 647   int aapcs_ncrn;               /* Next Core register number.  */
 648   int aapcs_nextncrn;           /* Next next core register number.  */
 649   int aapcs_nvrn;               /* Next Vector register number.  */
 650   int aapcs_nextnvrn;           /* Next Next Vector register number.  */
 651   rtx aapcs_reg;                /* Register assigned to this argument.  This
 652                                    is NULL_RTX if this parameter goes on
 653                                    the stack.  */
 654   MACHMODE aapcs_vfp_rmode;
 655   int aapcs_stack_words;        /* If the argument is passed on the stack, this
 656                                    is the number of words needed, after rounding
 657                                    up.  Only meaningful when
 658                                    aapcs_reg == NULL_RTX.  */
 659   int aapcs_stack_size;         /* The total size (in words, per 8 byte) of the
 660                                    stack arg area so far.  */
 661 } CUMULATIVE_ARGS;
 662 #endif
 663
 664 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
 665   (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
 666
 667 #define PAD_VARARGS_DOWN        0
 668
 669 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
 670   aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)
 671
 672 #define FUNCTION_ARG_REGNO_P(REGNO) \
 673   aarch64_function_arg_regno_p(REGNO)
 674 \f
 675
 676 /* ISA Features.  */
 677
 678 /* Addressing modes, etc.  */
 679 #define HAVE_POST_INCREMENT     1
 680 #define HAVE_PRE_INCREMENT      1
 681 #define HAVE_POST_DECREMENT     1
 682 #define HAVE_PRE_DECREMENT      1
 683 #define HAVE_POST_MODIFY_DISP   1
 684 #define HAVE_PRE_MODIFY_DISP    1
 685
 686 #define MAX_REGS_PER_ADDRESS    2
 687
 688 #define CONSTANT_ADDRESS_P(X)           aarch64_constant_address_p(X)
 689
 690 #define REGNO_OK_FOR_BASE_P(REGNO)      \
 691   aarch64_regno_ok_for_base_p (REGNO, true)
 692
 693 #define REGNO_OK_FOR_INDEX_P(REGNO) \
 694   aarch64_regno_ok_for_index_p (REGNO, true)
 695
 696 #define LEGITIMATE_PIC_OPERAND_P(X) \
 697   aarch64_legitimate_pic_operand_p (X)
 698
 699 #define CASE_VECTOR_MODE Pmode
 700
 701 #define DEFAULT_SIGNED_CHAR 0
 702
 703 /* An integer expression for the size in bits of the largest integer machine
 704    mode that should actually be used.  We allow pairs of registers.  */
 705 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
 706
 707 /* Maximum bytes moved by a single instruction (load/store pair).  */
 708 #define MOVE_MAX (UNITS_PER_WORD * 2)
 709
 710 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends.  */
 711 #define AARCH64_CALL_RATIO 8
 712
 713 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure.
 714    move_by_pieces will continually copy the largest safe chunks.  So a
 715    7-byte copy is a 4-byte + 2-byte + byte copy.  This proves inefficient
 716    for both size and speed of copy, so we will instead use the "movmem"
 717    standard name to implement the copy.  This logic does not apply when
 718    targeting -mstrict-align, so keep a sensible default in that case.  */
 719 #define MOVE_RATIO(speed) \
 720   (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
 721
 722 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 723    of the length of a memset call, but use the default otherwise.  */
 724 #define CLEAR_RATIO(speed) \
 725   ((speed) ? 15 : AARCH64_CALL_RATIO)
 726
 727 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when
 728    optimizing for size adjust the ratio to account for the overhead of loading
 729    the constant.  */
 730 #define SET_RATIO(speed) \
 731   ((speed) ? 15 : AARCH64_CALL_RATIO - 2)
 732
 733 /* Disable auto-increment in move_by_pieces et al.  Use of auto-increment is
 734    rarely a good idea in straight-line code since it adds an extra address
 735    dependency between each instruction.  Better to use incrementing offsets.  */
 736 #define USE_LOAD_POST_INCREMENT(MODE)   0
 737 #define USE_LOAD_POST_DECREMENT(MODE)   0
 738 #define USE_LOAD_PRE_INCREMENT(MODE)    0
 739 #define USE_LOAD_PRE_DECREMENT(MODE)    0
 740 #define USE_STORE_POST_INCREMENT(MODE)  0
 741 #define USE_STORE_POST_DECREMENT(MODE)  0
 742 #define USE_STORE_PRE_INCREMENT(MODE)   0
 743 #define USE_STORE_PRE_DECREMENT(MODE)   0
 744
 745 /* WORD_REGISTER_OPERATIONS does not hold for AArch64.
 746    The assigned word_mode is DImode but operations narrower than SImode
 747    behave as 32-bit operations if using the W-form of the registers rather
 748    than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
 749    expects.  */
 750 #define WORD_REGISTER_OPERATIONS 0
 751
 752 /* Define if loading from memory in MODE, an integral mode narrower than
 753    BITS_PER_WORD will either zero-extend or sign-extend.  The value of this
 754    macro should be the code that says which one of the two operations is
 755    implicitly done, or UNKNOWN if none.  */
 756 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 757
 758 /* Define this macro to be non-zero if instructions will fail to work
 759    if given data not on the nominal alignment.  */
 760 #define STRICT_ALIGNMENT                TARGET_STRICT_ALIGN
 761
 762 /* Define this macro to be non-zero if accessing less than a word of
 763    memory is no faster than accessing a word of memory, i.e., if such
 764    accesses require more than one instruction or if there is no
 765    difference in cost.
 766    Although there's no difference in instruction count or cycles,
 767    in AArch64 we don't want to expand to a sub-word to a 64-bit access
 768    if we don't have to, for power-saving reasons.  */
 769 #define SLOW_BYTE_ACCESS                0
 770
 771 #define NO_FUNCTION_CSE 1
 772
 773 /* Specify the machine mode that the hardware addresses have.
 774    After generation of rtl, the compiler makes no further distinction
 775    between pointers and any other objects of this machine mode.  */
 776 #define Pmode           DImode
 777
 778 /* A C expression whose value is zero if pointers that need to be extended
 779    from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
 780    greater then zero if they are zero-extended and less then zero if the
 781    ptr_extend instruction should be used.  */
 782 #define POINTERS_EXTEND_UNSIGNED 1
 783
 784 /* Mode of a function address in a call instruction (for indexing purposes).  */
 785 #define FUNCTION_MODE   Pmode
 786
 787 #define SELECT_CC_MODE(OP, X, Y)        aarch64_select_cc_mode (OP, X, Y)
 788
 789 #define REVERSIBLE_CC_MODE(MODE) 1
 790
 791 #define REVERSE_CONDITION(CODE, MODE)           \
 792   (((MODE) == CCFPmode || (MODE) == CCFPEmode)  \
 793    ? reverse_condition_maybe_unordered (CODE)   \
 794    : reverse_condition (CODE))
 795
 796 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 797   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 798 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 799   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 800
 801 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
 802
 803 #define RETURN_ADDR_RTX aarch64_return_addr
 804
 805 /* 3 insns + padding + 2 pointer-sized entries.  */
 806 #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32)
 807
 808 /* Trampolines contain dwords, so must be dword aligned.  */
 809 #define TRAMPOLINE_ALIGNMENT 64
 810
 811 /* Put trampolines in the text section so that mapping symbols work
 812    correctly.  */
 813 #define TRAMPOLINE_SECTION text_section
 814
 815 /* To start with.  */
 816 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \
 817   (aarch64_branch_cost (SPEED_P, PREDICTABLE_P))
 818 \f
 819
 820 /* Assembly output.  */
 821
 822 /* For now we'll make all jump tables pc-relative.  */
 823 #define CASE_VECTOR_PC_RELATIVE 1
 824
 825 #define CASE_VECTOR_SHORTEN_MODE(min, max, body)        \
 826   ((min < -0x1fff0 || max > 0x1fff0) ? SImode           \
 827    : (min < -0x1f0 || max > 0x1f0) ? HImode             \
 828    : QImode)
 829
 830 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL.  */
 831 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
 832
 833 #define MCOUNT_NAME "_mcount"
 834
 835 #define NO_PROFILE_COUNTERS 1
 836
 837 /* Emit rtl for profiling.  Output assembler code to FILE
 838    to call "_mcount" for profiling a function entry.  */
 839 #define PROFILE_HOOK(LABEL)                                             \
 840   {                                                                     \
 841     rtx fun, lr;                                                        \
 842     lr = get_hard_reg_initial_val (Pmode, LR_REGNUM);                   \
 843     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 844     emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode);           \
 845   }
 846
 847 /* All the work done in PROFILE_HOOK, but still required.  */
 848 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 849
 850 /* For some reason, the Linux headers think they know how to define
 851    these macros.  They don't!!!  */
 852 #undef ASM_APP_ON
 853 #undef ASM_APP_OFF
 854 #define ASM_APP_ON      "\t" ASM_COMMENT_START " Start of user assembly\n"
 855 #define ASM_APP_OFF     "\t" ASM_COMMENT_START " End of user assembly\n"
 856
 857 #define CONSTANT_POOL_BEFORE_FUNCTION 0
 858
 859 /* This definition should be relocated to aarch64-elf-raw.h.  This macro
 860    should be undefined in aarch64-linux.h and a clear_cache pattern
 861    implmented to emit either the call to __aarch64_sync_cache_range()
 862    directly or preferably the appropriate sycall or cache clear
 863    instructions inline.  */
 864 #define CLEAR_INSN_CACHE(beg, end)                              \
 865   extern void  __aarch64_sync_cache_range (void *, void *);     \
 866   __aarch64_sync_cache_range (beg, end)
 867
 868 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
 869
 870 /* Choose appropriate mode for caller saves, so we do the minimum
 871    required size of load/store.  */
 872 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
 873   aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
 874
 875 #undef SWITCHABLE_TARGET
 876 #define SWITCHABLE_TARGET 1
 877
 878 /* Check TLS Descriptors mechanism is selected.  */
 879 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS)
 880
 881 extern enum aarch64_code_model aarch64_cmodel;
 882
 883 /* When using the tiny addressing model conditional and unconditional branches
 884    can span the whole of the available address space (1MB).  */
 885 #define HAS_LONG_COND_BRANCH                            \
 886   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
 887    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
 888
 889 #define HAS_LONG_UNCOND_BRANCH                          \
 890   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
 891    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
 892
 893 #define TARGET_SUPPORTS_WIDE_INT 1
 894
 895 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register.  */
 896 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \
 897   ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
 898    || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \
 899    || (MODE) == DFmode)
 900
 901 /* Modes valid for AdvSIMD Q registers.  */
 902 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
 903   ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
 904    || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \
 905    || (MODE) == V2DFmode)
 906
 907 #define ENDIAN_LANE_N(mode, n)  \
 908   (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
 909
 910 /* Support for a configure-time default CPU, etc.  We currently support
 911    --with-arch and --with-cpu.  Both are ignored if either is specified
 912    explicitly on the command line at run time.  */
 913 #define OPTION_DEFAULT_SPECS                            \
 914   {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" },  \
 915   {"cpu",  "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" },
 916
 917 #define MCPU_TO_MARCH_SPEC \
 918    " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}"
 919
 920 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
 921 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \
 922   { "rewrite_mcpu", aarch64_rewrite_mcpu },
 923
 924 #if defined(__aarch64__)
 925 extern const char *host_detect_local_cpu (int argc, const char **argv);
 926 # define EXTRA_SPEC_FUNCTIONS                                           \
 927   { "local_cpu_detect", host_detect_local_cpu },                        \
 928   MCPU_TO_MARCH_SPEC_FUNCTIONS
 929
 930 # define MCPU_MTUNE_NATIVE_SPECS                                        \
 931    " %{march=native:%<march=native %:local_cpu_detect(arch)}"           \
 932    " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}"              \
 933    " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
 934 #else
 935 # define MCPU_MTUNE_NATIVE_SPECS ""
 936 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS
 937 #endif
 938
 939 #define ASM_CPU_SPEC \
 940    MCPU_TO_MARCH_SPEC
 941
 942 #define EXTRA_SPECS                                             \
 943   { "asm_cpu_spec",             ASM_CPU_SPEC }
 944
 945 #define ASM_OUTPUT_POOL_EPILOGUE  aarch64_asm_output_pool_epilogue
 946
 947 /* This type is the user-visible __fp16, and a pointer to that type.  We
 948    need it in many places in the backend.  Defined in aarch64-builtins.c.  */
 949 extern tree aarch64_fp16_type_node;
 950 extern tree aarch64_fp16_ptr_type_node;
 951
 952 /* The generic unwind code in libgcc does not initialize the frame pointer.
 953    So in order to unwind a function using a frame pointer, the very first
 954    function that is unwound must save the frame pointer.  That way the frame
 955    pointer is restored and its value is now valid - otherwise _Unwind_GetGR
 956    crashes.  Libgcc can now be safely built with -fomit-frame-pointer.  */
 957 #define LIBGCC2_UNWIND_ATTRIBUTE \
 958   __attribute__((optimize ("no-omit-frame-pointer")))
 959
 960 #endif /* GCC_AARCH64_H */