| blob | e89c8156976cecf200cd67c1e938c8156c1240c4 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
71 /* This file should be included last. */
74 /* Defined for convenience. */
75 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
77 /* Classifies an address.
79 ADDRESS_REG_IMM
80 A simple base register plus immediate offset.
82 ADDRESS_REG_WB
83 A base register indexed by immediate offset with writeback.
85 ADDRESS_REG_REG
86 A base register indexed by (optionally scaled) register.
88 ADDRESS_REG_UXTW
89 A base register indexed by (optionally scaled) zero-extended register.
91 ADDRESS_REG_SXTW
92 A base register indexed by (optionally scaled) sign-extended register.
94 ADDRESS_LO_SUM
95 A LO_SUM rtx with a base register and "LO12" symbol relocation.
97 ADDRESS_SYMBOLIC:
98 A constant symbolic address, in pc-relative literal pool. */
101 ADDRESS_REG_IMM,
102 ADDRESS_REG_WB,
103 ADDRESS_REG_REG,
104 ADDRESS_REG_UXTW,
105 ADDRESS_REG_SXTW,
106 ADDRESS_LO_SUM,
107 ADDRESS_SYMBOLIC
108 };
112 rtx base;
113 rtx offset;
116 };
118 struct simd_immediate_info
119 {
120 rtx value;
125 };
127 /* The current code model. */
130 #ifdef HAVE_AS_TLS
131 #undef TARGET_HAVE_TLS
132 #define TARGET_HAVE_TLS 1
133 #endif
137 const_tree,
145 vec_perm_indices);
148 const_tree type,
151 static machine_mode
154 /* Major revision number of the ARM Architecture implemented by the target. */
157 /* The processor for which instructions should be scheduled. */
160 /* Mask to specify which instruction scheduling options should be used. */
163 /* Global flag for PC relative loads. */
166 /* Support for command line parsing of boolean flags in the tuning
167 structures. */
168 struct aarch64_flag_desc
169 {
172 };
174 #define AARCH64_FUSION_PAIR(name, internal_name) \
175 { name, AARCH64_FUSE_##internal_name },
177 {
182 };
184 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
185 { name, AARCH64_EXTRA_TUNE_##internal_name },
187 {
192 };
194 /* Tuning parameters. */
197 {
198 {
203 },
210 };
213 {
214 {
219 },
226 };
229 {
230 {
235 },
242 };
245 {
246 {
251 },
258 };
261 {
263 /* Avoid the use of slow int<->fp moves for spilling by setting
264 their cost higher than memmov_cost. */
268 };
271 {
273 /* Avoid the use of slow int<->fp moves for spilling by setting
274 their cost higher than memmov_cost. */
278 };
281 {
283 /* Avoid the use of slow int<->fp moves for spilling by setting
284 their cost higher than memmov_cost. */
288 };
291 {
293 /* Avoid the use of slow int<->fp moves for spilling by setting
294 their cost higher than memmov_cost (actual, 4 and 9). */
298 };
301 {
306 };
309 {
311 /* Avoid the use of slow int<->fp moves for spilling by setting
312 their cost higher than memmov_cost. */
316 };
319 {
321 /* Avoid the use of int<->fp moves for spilling. */
325 };
328 {
330 /* Avoid the use of int<->fp moves for spilling. */
334 };
336 /* Generic costs for vector insn classes. */
338 {
354 };
356 /* ThunderX costs for vector insn classes. */
358 {
374 };
376 /* Generic costs for vector insn classes. */
378 {
394 };
397 {
413 };
415 /* Generic costs for vector insn classes. */
417 {
433 };
435 /* Costs for vector insn classes for Vulcan. */
437 {
453 };
455 /* Generic costs for branch instructions. */
457 {
460 };
462 /* Generic approximation modes. */
464 {
467 AARCH64_APPROX_NONE /* recip_sqrt */
468 };
470 /* Approximation modes for Exynos M1. */
472 {
475 AARCH64_APPROX_ALL /* recip_sqrt */
476 };
478 /* Approximation modes for X-Gene 1. */
480 {
483 AARCH64_APPROX_ALL /* recip_sqrt */
484 };
486 /* Generic prefetch settings (which disable prefetch). */
488 {
494 };
497 {
503 };
506 {
512 };
515 {
521 };
524 {
530 };
533 {
539 };
542 {
563 &generic_prefetch_tune
564 };
567 {
589 &generic_prefetch_tune
590 };
593 {
615 &generic_prefetch_tune
616 };
619 {
641 &generic_prefetch_tune
642 };
645 {
667 &generic_prefetch_tune
668 };
671 {
693 &generic_prefetch_tune
694 };
699 {
720 &exynosm1_prefetch_tune
721 };
724 {
745 &thunderxt88_prefetch_tune
746 };
749 {
769 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
771 &thunderx_prefetch_tune
772 };
775 {
796 &generic_prefetch_tune
797 };
800 {
822 &qdf24xx_prefetch_tune
823 };
826 {
848 &thunderx2t99_prefetch_tune
849 };
851 /* Support for fine-grained override of the tuning structures. */
852 struct aarch64_tuning_override_function
853 {
856 };
861 static const struct aarch64_tuning_override_function
862 aarch64_tuning_override_functions[] =
863 {
867 };
869 /* A processor implementing AArch64. */
870 struct processor
871 {
879 };
881 /* Architectures implementing AArch64. */
883 {
884 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
885 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
888 };
890 /* Processor cores implementing AArch64. */
892 {
893 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
894 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
895 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
896 FLAGS, &COSTS##_tunings},
901 };
904 /* Target specification. These are populated by the -march, -mtune, -mcpu
905 handling code or by target attributes. */
910 /* The current tuning set. */
913 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
915 /* An ISA extension in the co-processor and main instruction set space. */
916 struct aarch64_option_extension
917 {
921 };
924 {
928 }
929 aarch64_cc;
931 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
933 /* The condition codes of the processor, and the inverse function. */
935 {
938 };
940 /* Generate code to enable conditional branches in functions over 1 MiB. */
944 {
961 }
963 void
965 {
969 else
971 }
973 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
974 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
975 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
976 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
977 cost (in this case the best class is the lowest cost one). Using ALL_REGS
978 irrespectively of its cost results in bad allocations with many redundant
979 int<->FP moves which are expensive on various cores.
980 To avoid this we don't allow ALL_REGS as the allocno class, but force a
981 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
982 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
983 Otherwise set the allocno class depending on the mode.
984 The result of this is that it is no longer inefficient to have a higher
985 memory move cost than the register move cost.
986 */
988 static reg_class_t
990 reg_class_t best_class)
991 {
992 machine_mode mode;
1002 }
1004 static unsigned int
1006 {
1010 }
1012 static int
1014 machine_mode mode)
1015 {
1023 }
1025 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1026 unsigned
1028 {
1036 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1037 equivalent DWARF register. */
1039 }
1041 /* Return TRUE if MODE is any of the large INT modes. */
1042 static bool
1044 {
1046 }
1048 /* Return TRUE if MODE is any of the vector modes. */
1049 static bool
1051 {
1054 }
1056 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1057 static bool
1060 {
1068 }
1070 /* Implement TARGET_HARD_REGNO_NREGS. */
1072 static unsigned int
1074 {
1076 {
1082 }
1084 }
1086 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1088 static bool
1090 {
1095 /* The purpose of comparing with ptr_mode is to support the
1096 global register variable associated with the stack pointer
1097 register via the syntax of asm ("wsp") in ILP32. */
1107 {
1110 else
1112 }
1115 }
1117 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1118 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1119 clobbers the top 64 bits when restoring the bottom 64 bits. */
1121 static bool
1123 {
1125 }
1127 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1128 machine_mode
1130 machine_mode mode)
1131 {
1132 /* Handle modes that fit within single registers. */
1134 {
1137 else
1139 }
1140 /* Fall back to generic for multi-reg and very large modes. */
1141 else
1143 }
1145 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
1146 that strcpy from constants will be faster. */
1148 static HOST_WIDE_INT
1150 {
1154 }
1156 /* Return true if calls to DECL should be treated as
1157 long-calls (ie called via a register). */
1158 static bool
1160 {
1162 }
1164 /* Return true if calls to symbol-ref SYM should be treated as
1165 long-calls (ie called via a register). */
1166 bool
1168 {
1170 }
1172 /* Return true if calls to symbol-ref SYM should not go through
1173 plt stubs. */
1175 bool
1177 {
1181 && decl
1182 && (!flag_plt
1188 }
1190 /* Return true if the offsets to a zero/sign-extract operation
1191 represent an expression that matches an extend operation. The
1192 operands represent the paramters from
1194 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1195 bool
1197 rtx extract_imm)
1198 {
1215 }
1217 /* Emit an insn that's a simple single-set. Both the operands must be
1218 known to be valid. */
1221 {
1223 }
1225 /* X and Y are two things to compare using CODE. Emit the compare insn and
1226 return the rtx for register 0 in the proper mode. */
1227 rtx
1229 {
1235 }
1237 /* Build the SYMBOL_REF for __tls_get_addr. */
1241 rtx
1243 {
1247 }
1249 /* Return the TLS model to use for ADDR. */
1251 static enum tls_model
1253 {
1258 {
1262 }
1267 }
1269 /* We'll allow lo_sum's in addresses in our legitimate addresses
1270 so that combine would take care of combining addresses where
1271 necessary, but for generation purposes, we'll generate the address
1272 as :
1273 RTL Absolute
1274 tmp = hi (symbol_ref); adrp x1, foo
1275 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1276 nop
1278 PIC TLS
1279 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1280 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1281 bl __tls_get_addr
1282 nop
1284 Load TLS symbol, depending on TLS mechanism and TLS access model.
1286 Global Dynamic - Traditional TLS:
1287 adrp tmp, :tlsgd:imm
1288 add dest, tmp, #:tlsgd_lo12:imm
1289 bl __tls_get_addr
1291 Global Dynamic - TLS Descriptors:
1292 adrp dest, :tlsdesc:imm
1293 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1294 add dest, dest, #:tlsdesc_lo12:imm
1295 blr tmp
1296 mrs tp, tpidr_el0
1297 add dest, dest, tp
1299 Initial Exec:
1300 mrs tp, tpidr_el0
1301 adrp tmp, :gottprel:imm
1302 ldr dest, [tmp, #:gottprel_lo12:imm]
1303 add dest, dest, tp
1305 Local Exec:
1306 mrs tp, tpidr_el0
1307 add t0, tp, #:tprel_hi12:imm, lsl #12
1308 add t0, t0, #:tprel_lo12_nc:imm
1309 */
1311 static void
1314 {
1316 {
1318 {
1319 /* In ILP32, the mode of dest can be either SImode or DImode. */
1331 }
1338 {
1341 rtx insn;
1342 rtx mem;
1344 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1345 here before rtl expand. Tree IVOPT will generate rtl pattern to
1346 decide rtx costs, in which case pic_offset_table_rtx is not
1347 initialized. For that case no need to generate the first adrp
1348 instruction as the final cost for global variable access is
1349 one instruction. */
1351 {
1352 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1353 using the page base as GOT base, the first page may be wasted,
1354 in the worst scenario, there is only 28K space for GOT).
1356 The generate instruction sequence for accessing global variable
1357 is:
1359 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1361 Only one instruction needed. But we must initialize
1362 pic_offset_table_rtx properly. We generate initialize insn for
1363 every global access, and allow CSE to remove all redundant.
1365 The final instruction sequences will look like the following
1366 for multiply global variables access.
1368 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1370 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1371 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1372 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1373 ... */
1382 }
1385 {
1388 else
1392 }
1393 else
1394 {
1399 }
1401 /* The operand is expected to be MEM. Whenever the related insn
1402 pattern changed, above code which calculate mem should be
1403 updated. */
1409 }
1412 {
1413 /* In ILP32, the mode of dest can be either SImode or DImode,
1414 while the got entry is always of SImode size. The mode of
1415 dest depends on how dest is used: if dest is assigned to a
1416 pointer (e.g. in the memory), it has SImode; it may have
1417 DImode if dest is dereferenced to access the memeory.
1418 This is why we have to handle three different ldr_got_small
1419 patterns here (two patterns for ILP32). */
1421 rtx insn;
1422 rtx mem;
1431 {
1434 else
1438 }
1439 else
1440 {
1445 }
1452 }
1455 {
1463 else
1471 }
1474 {
1477 rtx tp;
1481 /* In ILP32, the got entry is always of SImode size. Unlike
1482 small GOT, the dest is fixed at reg 0. */
1485 else
1495 }
1498 {
1499 /* In ILP32, the mode of dest can be either SImode or DImode,
1500 while the got entry is always of SImode size. The mode of
1501 dest depends on how dest is used: if dest is assigned to a
1502 pointer (e.g. in the memory), it has SImode; it may have
1503 DImode if dest is dereferenced to access the memeory.
1504 This is why we have to handle three different tlsie_small
1505 patterns here (two patterns for ILP32). */
1511 {
1514 else
1515 {
1518 }
1519 }
1520 else
1521 {
1524 }
1529 }
1535 {
1543 {
1566 }
1570 }
1577 {
1582 {
1585 else
1586 {
1589 }
1590 }
1591 else
1592 {
1595 }
1599 }
1603 }
1604 }
1606 /* Emit a move from SRC to DEST. Assume that the move expanders can
1607 handle all moves if !can_create_pseudo_p (). The distinction is
1608 important because, unlike emit_move_insn, the move expanders know
1609 how to force Pmode objects into the constant pool even when the
1610 constant pool address is not itself legitimate. */
1611 static rtx
1613 {
1617 }
1619 /* Split a 128-bit move operation into two 64-bit move operations,
1620 taking care to handle partial overlap of register to register
1621 copies. Special cases are needed when moving between GP regs and
1622 FP regs. SRC can be a register, constant or memory; DST a register
1623 or memory. If either operand is memory it must not have any side
1624 effects. */
1625 void
1627 {
1638 {
1642 /* Handle FP <-> GP regs. */
1644 {
1649 {
1652 }
1653 else
1654 {
1657 }
1659 }
1661 {
1666 {
1669 }
1670 else
1671 {
1674 }
1676 }
1677 }
1684 /* At most one pairing may overlap. */
1686 {
1689 }
1690 else
1691 {
1694 }
1695 }
1697 bool
1699 {
1702 }
1704 /* Split a complex SIMD combine. */
1706 void
1708 {
1720 {
1744 }
1748 }
1750 /* Split a complex SIMD move. */
1752 void
1754 {
1761 {
1767 {
1791 }
1795 }
1796 }
1798 bool
1801 {
1805 }
1808 static rtx
1810 {
1813 else
1814 {
1817 }
1818 }
1821 static rtx
1823 HOST_WIDE_INT offset)
1824 {
1826 {
1827 rtx high;
1828 /* Load the full offset into a register. This
1829 might be improvable in the future. */
1835 }
1837 }
1839 static int
1841 scalar_int_mode mode)
1842 {
1851 {
1855 }
1857 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
1858 (with XXXX non-zero). In that case check to see if the move can be done in
1859 a smaller mode. */
1864 {
1868 /* Check if we have to emit a second instruction by checking to see
1869 if any of the upper 32 bits of the original DI mode value is set. */
1880 }
1883 {
1885 {
1890 else
1893 }
1895 }
1897 /* Remaining cases are all for DImode. */
1906 {
1907 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1908 For a 64-bit bitmask try whether changing 16 bits to all ones or
1909 zeroes creates a valid bitmask. To check any repeated bitmask,
1910 try using 16 bits from the other 32-bit half of val. */
1913 {
1924 }
1926 {
1928 {
1932 }
1934 }
1935 }
1937 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1938 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1939 otherwise skip zero bits. */
1951 {
1957 num_insns ++;
1958 }
1961 }
1964 void
1966 {
1971 /* Check on what type of symbol it is. */
1972 scalar_int_mode int_mode;
1977 {
1981 /* If we have (const (plus symbol offset)), separate out the offset
1982 before we start classifying the symbol. */
1987 {
1991 {
1998 }
2003 /* If we aren't generating PC relative literals, then
2004 we need to expand the literal pool access carefully.
2005 This is something that needs to be done in a number
2006 of places, so could well live as a separate function. */
2008 {
2015 }
2032 {
2039 }
2040 /* FALLTHRU */
2053 }
2054 }
2057 {
2060 else
2061 {
2065 }
2068 }
2072 }
2074 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
2075 temporary value if necessary. FRAME_RELATED_P should be true if
2076 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
2077 to the generated instructions. If SCRATCHREG is known to hold
2078 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
2079 immediate again.
2081 Since this function may be used to adjust the stack pointer, we must
2082 ensure that it cannot cause transient stack deallocation (for example
2083 by first incrementing SP and then decrementing when adjusting by a
2084 large immediate). */
2086 static void
2090 {
2098 /* Single instruction adjustment. */
2100 {
2104 }
2106 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2107 Only do this if mdelta is not a 16-bit move as adjusting using a move
2108 is better. */
2110 {
2119 }
2121 /* Emit a move immediate if required and an addition/subtraction. */
2128 {
2132 }
2133 }
2137 HOST_WIDE_INT delta)
2138 {
2140 }
2144 {
2147 }
2151 {
2154 }
2156 static bool
2158 tree exp ATTRIBUTE_UNUSED)
2159 {
2160 /* Currently, always true. */
2162 }
2164 /* Implement TARGET_PASS_BY_REFERENCE. */
2166 static bool
2168 machine_mode mode,
2169 const_tree type,
2171 {
2172 HOST_WIDE_INT size;
2173 machine_mode dummymode;
2176 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2180 /* Aggregates are passed by reference based on their size. */
2182 {
2184 }
2186 /* Variable sized arguments are always returned by reference. */
2190 /* Can this be a candidate to be passed in fp/simd register(s)? */
2193 NULL))
2196 /* Arguments which are variable sized or larger than 2 registers are
2197 passed by reference unless they are a homogenous floating point
2198 aggregate. */
2200 }
2202 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2203 static bool
2205 {
2206 machine_mode dummy_mode;
2209 /* Never happens in little-endian mode. */
2213 /* Only composite types smaller than or equal to 16 bytes can
2214 be potentially returned in registers. */
2220 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2221 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2222 is always passed/returned in the least significant bits of fp/simd
2223 register(s). */
2229 }
2231 /* Implement TARGET_FUNCTION_VALUE.
2232 Define how to find the value returned by a function. */
2234 static rtx
2237 {
2238 machine_mode mode;
2241 machine_mode ag_mode;
2248 {
2252 {
2255 }
2256 }
2260 {
2262 {
2265 }
2266 else
2267 {
2269 rtx par;
2273 {
2278 }
2280 }
2281 }
2282 else
2284 }
2286 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2287 Return true if REGNO is the number of a hard register in which the values
2288 of called function may come back. */
2290 static bool
2292 {
2293 /* Maximum of 16 bytes can be returned in the general registers. Examples
2294 of 16-byte return values are: 128-bit integers and 16-byte small
2295 structures (excluding homogeneous floating-point aggregates). */
2299 /* Up to four fp/simd registers can return a function value, e.g. a
2300 homogeneous floating-point aggregate having four members. */
2305 }
2307 /* Implement TARGET_RETURN_IN_MEMORY.
2309 If the type T of the result of a function is such that
2310 void func (T arg)
2311 would require that arg be passed as a value in a register (or set of
2312 registers) according to the parameter passing rules, then the result
2313 is returned in the same registers as would be used for such an
2314 argument. */
2316 static bool
2318 {
2319 HOST_WIDE_INT size;
2320 machine_mode ag_mode;
2326 /* Simple scalar types always returned in registers. */
2330 type,
2333 NULL))
2336 /* Types larger than 2 registers returned in memory. */
2339 }
2341 static bool
2344 {
2347 type,
2349 nregs,
2350 NULL);
2351 }
2353 /* Given MODE and TYPE of a function argument, return the alignment in
2354 bits. The idea is to suppress any stronger alignment requested by
2355 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2356 This is a helper function for local use only. */
2358 static unsigned int
2360 {
2381 }
2383 /* Layout a function argument according to the AAPCS64 rules. The rule
2384 numbers refer to the rule numbers in the AAPCS64. */
2386 static void
2388 const_tree type,
2390 {
2394 HOST_WIDE_INT size;
2396 /* We need to do this once per argument. */
2402 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2403 size
2405 UNITS_PER_WORD);
2409 mode,
2410 type,
2413 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2414 The following code thus handles passing by SIMD/FP registers first. */
2418 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2419 and homogenous short-vector aggregates (HVA). */
2421 {
2426 {
2429 {
2432 }
2433 else
2434 {
2435 rtx par;
2439 {
2442 tmp = gen_rtx_EXPR_LIST
2446 }
2448 }
2450 }
2451 else
2452 {
2453 /* C.3 NSRN is set to 8. */
2456 }
2457 }
2462 /* C6 - C9. though the sign and zero extension semantics are
2463 handled elsewhere. This is the case where the argument fits
2464 entirely general registers. */
2466 {
2470 /* C.8 if the argument has an alignment of 16 then the NGRN is
2471 rounded up to the next even number. */
2474 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
2475 comparison is there because for > 16 * BITS_PER_UNIT
2476 alignment nregs should be > 2 and therefore it should be
2477 passed by reference rather than value. */
2479 {
2482 }
2484 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2485 A reg is still generated for it, but the caller should be smart
2486 enough not to use it. */
2489 else
2490 {
2491 rtx par;
2496 {
2501 }
2503 }
2507 }
2509 /* C.11 */
2512 /* The argument is passed on stack; record the needed number of words for
2513 this argument and align the total size if necessary. */
2514 on_stack:
2521 }
2523 /* Implement TARGET_FUNCTION_ARG. */
2525 static rtx
2528 {
2537 }
2539 void
2541 const_tree fntype ATTRIBUTE_UNUSED,
2542 rtx libname ATTRIBUTE_UNUSED,
2543 const_tree fndecl ATTRIBUTE_UNUSED,
2545 {
2559 {
2566 }
2568 }
2570 static void
2572 machine_mode mode,
2573 const_tree type,
2575 {
2578 {
2588 }
2589 }
2591 bool
2593 {
2596 }
2598 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2599 PARM_BOUNDARY bits of alignment, but will be given anything up
2600 to STACK_BOUNDARY bits if the type requires it. This makes sure
2601 that both before and after the layout of each argument, the Next
2602 Stacked Argument Address (NSAA) will have a minimum alignment of
2603 8 bytes. */
2605 static unsigned int
2607 {
2610 }
2612 /* Implement TARGET_FUNCTION_ARG_PADDING.
2614 Small aggregate types are placed in the lowest memory address.
2616 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2618 static pad_direction
2620 {
2621 /* On little-endian targets, the least significant byte of every stack
2622 argument is passed at the lowest byte address of the stack slot. */
2626 /* Otherwise, integral, floating-point and pointer types are padded downward:
2627 the least significant byte of a stack argument is passed at the highest
2628 byte address of the stack slot. */
2635 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2637 }
2639 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2641 It specifies padding for the last (may also be the only)
2642 element of a block move between registers and memory. If
2643 assuming the block is in the memory, padding upward means that
2644 the last element is padded after its highest significant byte,
2645 while in downward padding, the last element is padded at the
2646 its least significant byte side.
2648 Small aggregates and small complex types are always padded
2649 upwards.
2651 We don't need to worry about homogeneous floating-point or
2652 short-vector aggregates; their move is not affected by the
2653 padding direction determined here. Regardless of endianness,
2654 each element of such an aggregate is put in the least
2655 significant bits of a fp/simd register.
2657 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2658 register has useful data, and return the opposite if the most
2659 significant byte does. */
2661 bool
2664 {
2666 /* Small composite types are always padded upward. */
2668 {
2673 }
2675 /* Otherwise, use the default padding. */
2677 }
2679 static scalar_int_mode
2681 {
2683 }
2685 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2687 /* We use the 12-bit shifted immediate arithmetic instructions so values
2688 must be multiple of (1 << 12), i.e. 4096. */
2689 #define ARITH_FACTOR 4096
2691 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2692 #error Cannot use simple address calculation for stack probing
2693 #endif
2695 /* The pair of scratch registers used for stack probing. */
2696 #define PROBE_STACK_FIRST_REG 9
2697 #define PROBE_STACK_SECOND_REG 10
2699 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2700 inclusive. These are offsets from the current stack pointer. */
2702 static void
2704 {
2707 /* See the same assertion on PROBE_INTERVAL above. */
2710 /* See if we have a constant small number of probes to generate. If so,
2711 that's the easy case. */
2713 {
2720 }
2722 /* The run-time loop is made up of 8 insns in the generic case while the
2723 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2725 {
2730 stack_pointer_rtx,
2734 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2735 it exceeds SIZE. If only two probes are needed, this will not
2736 generate any code. Then probe at FIRST + SIZE. */
2738 {
2742 }
2746 {
2751 }
2752 else
2754 }
2756 /* Otherwise, do the same as above, but in a loop. Note that we must be
2757 extra careful with variables wrapping around because we might be at
2758 the very top (or the very bottom) of the address space and we have
2759 to be able to handle this case properly; in particular, we use an
2760 equality test for the loop condition. */
2761 else
2762 {
2765 /* Step 1: round SIZE to the previous multiple of the interval. */
2770 /* Step 2: compute initial and final value of the loop counter. */
2772 /* TEST_ADDR = SP + FIRST. */
2776 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2779 {
2783 }
2784 else
2785 {
2788 }
2790 /* Step 3: the loop
2792 do
2793 {
2794 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2795 probe at TEST_ADDR
2796 }
2797 while (TEST_ADDR != LAST_ADDR)
2799 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2800 until it is equal to ROUNDED_SIZE. */
2805 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2806 that SIZE is equal to ROUNDED_SIZE. */
2809 {
2813 {
2818 }
2819 else
2821 }
2822 }
2824 /* Make sure nothing is scheduled before we are done. */
2826 }
2828 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2829 absolute addresses. */
2833 {
2840 /* Loop. */
2843 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2848 /* Probe at TEST_ADDR. */
2851 /* Test if TEST_ADDR == LAST_ADDR. */
2855 /* Branch. */
2861 }
2863 static bool
2865 {
2866 /* In aarch64_override_options_after_change
2867 flag_omit_leaf_frame_pointer turns off the frame pointer by
2868 default. Turn it back on now if we've not got a leaf
2869 function. */
2874 /* Force a frame pointer for EH returns so the return address is at FP+8. */
2879 }
2881 /* Mark the registers that need to be saved by the callee and calculate
2882 the size of the callee-saved registers area and frame record (both FP
2883 and LR may be omitted). */
2884 static void
2886 {
2893 #define SLOT_NOT_REQUIRED (-2)
2894 #define SLOT_REQUIRED (-1)
2899 /* First mark all the registers that really need to be saved... */
2906 /* ... that includes the eh data registers (if needed)... */
2912 /* ... and any callee saved register that dataflow says is live. */
2922 {
2925 }
2928 {
2929 /* FP and LR are placed in the linkage record. */
2935 }
2937 /* Now assign stack slots for them. */
2940 {
2947 }
2955 {
2956 /* If there is an alignment gap between integer and fp callee-saves,
2957 allocate the last fp register to it if possible. */
2959 {
2962 }
2971 }
2977 HOST_WIDE_INT varargs_and_saved_regs_size
3004 {
3005 /* Simple, small frame with no outgoing arguments:
3006 stp reg1, reg2, [sp, -frame_size]!
3007 stp reg3, reg4, [sp, 16] */
3009 }
3014 {
3015 /* Frame with small outgoing arguments:
3016 sub sp, sp, frame_size
3017 stp reg1, reg2, [sp, outgoing_args_size]
3018 stp reg3, reg4, [sp, outgoing_args_size + 16] */
3022 }
3024 {
3025 /* Frame with large outgoing arguments but a small local area:
3026 stp reg1, reg2, [sp, -hard_fp_offset]!
3027 stp reg3, reg4, [sp, 16]
3028 sub sp, sp, outgoing_args_size */
3032 }
3035 {
3036 /* Frame with large local area and outgoing arguments (this pushes the
3037 callee-saves first, followed by the locals and outgoing area):
3038 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
3039 stp reg3, reg4, [sp, 16]
3040 sub sp, sp, frame_size - varargs_and_saved_regs_size */
3046 }
3047 else
3048 {
3049 /* Frame with large local area and outgoing arguments using frame pointer:
3050 sub sp, sp, hard_fp_offset
3051 stp x29, x30, [sp, 0]
3052 add x29, sp, 0
3053 stp reg3, reg4, [sp, 16]
3054 sub sp, sp, outgoing_args_size */
3058 }
3061 }
3063 /* Return true if the register REGNO is saved on entry to
3064 the current function. */
3066 static bool
3068 {
3070 }
3072 /* Return the next register up from REGNO up to LIMIT for the callee
3073 to save. */
3075 static unsigned
3077 {
3079 regno ++;
3081 }
3083 /* Push the register number REGNO of mode MODE to the stack with write-back
3084 adjusting the stack by ADJUSTMENT. */
3086 static void
3088 HOST_WIDE_INT adjustment)
3089 {
3100 }
3102 /* Generate and return an instruction to store the pair of registers
3103 REG and REG2 of mode MODE to location BASE with write-back adjusting
3104 the stack location BASE by ADJUSTMENT. */
3106 static rtx
3108 HOST_WIDE_INT adjustment)
3109 {
3111 {
3122 }
3123 }
3125 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3126 stack pointer by ADJUSTMENT. */
3128 static void
3130 {
3145 }
3147 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3148 adjusting it by ADJUSTMENT afterwards. */
3150 static rtx
3152 HOST_WIDE_INT adjustment)
3153 {
3155 {
3164 }
3165 }
3167 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3168 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3169 into CFI_OPS. */
3171 static void
3174 {
3181 {
3185 }
3186 else
3187 {
3192 }
3193 }
3195 /* Generate and return a store pair instruction of mode MODE to store
3196 register REG1 to MEM1 and register REG2 to MEM2. */
3198 static rtx
3200 rtx reg2)
3201 {
3203 {
3212 }
3213 }
3215 /* Generate and regurn a load pair isntruction of mode MODE to load register
3216 REG1 from MEM1 and register REG2 from MEM2. */
3218 static rtx
3220 rtx mem2)
3221 {
3223 {
3232 }
3233 }
3235 /* Return TRUE if return address signing should be enabled for the current
3236 function, otherwise return FALSE. */
3238 bool
3240 {
3241 /* This function should only be called after frame laid out. */
3244 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3245 if it's LR is pushed onto stack. */
3249 }
3251 /* Emit code to save the callee-saved registers from register number START
3252 to LIMIT to the stack at the location starting at offset START_OFFSET,
3253 skipping any write-back candidates if SKIP_WB is true. */
3255 static void
3258 {
3266 {
3268 HOST_WIDE_INT offset;
3281 offset));
3290 {
3292 rtx mem2;
3296 offset));
3298 reg2));
3300 /* The first part of a frame-related parallel insn is
3301 always assumed to be relevant to the frame
3302 calculations; subsequent parts, are only
3303 frame-related if explicitly marked. */
3306 }
3307 else
3311 }
3312 }
3314 /* Emit code to restore the callee registers of mode MODE from register
3315 number START up to and including LIMIT. Restore from the stack offset
3316 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3317 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3319 static void
3323 {
3327 HOST_WIDE_INT offset;
3332 {
3353 {
3355 rtx mem2;
3363 }
3364 else
3367 }
3368 }
3372 HOST_WIDE_INT offset)
3373 {
3375 }
3379 {
3383 }
3385 bool
3387 {
3391 }
3393 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3395 static sbitmap
3397 {
3403 /* The registers we need saved to the frame. */
3406 {
3411 /* Check that we can access the stack slot of the register with one
3412 direct load with no adjustments needed. */
3415 }
3417 /* Don't mess with the hard frame pointer. */
3423 /* If aarch64_layout_frame has chosen registers to store/restore with
3424 writeback don't interfere with them to avoid having to output explicit
3425 stack adjustment instructions. */
3435 }
3437 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3439 static sbitmap
3441 {
3449 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3458 }
3460 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3461 Nothing to do for aarch64. */
3463 static void
3465 {
3466 }
3468 /* Return the next set bit in BMP from START onwards. Return the total number
3469 of bits in BMP if no set bit is found at or after START. */
3471 static unsigned int
3473 {
3484 }
3486 /* Do the work for aarch64_emit_prologue_components and
3487 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3488 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3489 for these components or the epilogue sequence. That is, it determines
3490 whether we should emit stores or loads and what kind of CFA notes to attach
3491 to the insns. Otherwise the logic for the two sequences is very
3492 similar. */
3494 static void
3496 {
3498 ? HARD_FRAME_POINTER_REGNUM
3506 {
3507 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3508 so DFmode for the vector registers is enough. */
3520 /* No more registers to handle after REGNO.
3521 Emit a single save/restore and exit. */
3523 {
3528 else
3531 }
3534 /* The next register is not of the same class or its offset is not
3535 mergeable with the current one into a pair. */
3540 {
3545 else
3550 }
3552 /* REGNO2 can be saved/restored in a pair with REGNO. */
3564 else
3569 {
3572 }
3573 else
3574 {
3577 }
3580 }
3581 }
3583 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3585 static void
3587 {
3589 }
3591 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3593 static void
3595 {
3597 }
3599 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3601 static void
3603 {
3607 }
3609 /* AArch64 stack frames generated by this compiler look like:
3611 +-------------------------------+
3612 | |
3613 | incoming stack arguments |
3614 | |
3615 +-------------------------------+
3616 | | <-- incoming stack pointer (aligned)
3617 | callee-allocated save area |
3618 | for register varargs |
3619 | |
3620 +-------------------------------+
3621 | local variables | <-- frame_pointer_rtx
3622 | |
3623 +-------------------------------+
3624 | padding0 | \
3625 +-------------------------------+ |
3626 | callee-saved registers | | frame.saved_regs_size
3627 +-------------------------------+ |
3628 | LR' | |
3629 +-------------------------------+ |
3630 | FP' | / <- hard_frame_pointer_rtx (aligned)
3631 +-------------------------------+
3632 | dynamic allocation |
3633 +-------------------------------+
3634 | padding |
3635 +-------------------------------+
3636 | outgoing stack arguments | <-- arg_pointer
3637 | |
3638 +-------------------------------+
3639 | | <-- stack_pointer_rtx (aligned)
3641 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3642 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3643 unchanged. */
3645 /* Generate the prologue instructions for entry into a function.
3646 Establish the stack frame by decreasing the stack pointer with a
3647 properly calculated size and, if necessary, create a frame record
3648 filled with the values of LR and previous frame pointer. The
3649 current FP is also set up if it is in use. */
3651 void
3653 {
3665 /* Sign return address for functions. */
3667 {
3671 }
3677 {
3679 {
3683 (frame_size
3685 }
3688 }
3696 {
3701 stack_pointer_rtx,
3705 }
3712 }
3714 /* Return TRUE if we can use a simple_return insn.
3716 This function checks whether the callee saved stack is empty, which
3717 means no restore actions are need. The pro_and_epilogue will use
3718 this to check whether shrink-wrapping opt is feasible. */
3720 bool
3722 {
3732 }
3734 /* Generate the epilogue instructions for returning from a function.
3735 This is almost exactly the reverse of the prolog sequence, except
3736 that we need to insert barriers to avoid scheduling loads that read
3737 from a deallocated stack, and we optimize the unwind records by
3738 emitting them all together if possible. */
3739 void
3741 {
3753 /* We need to add memory barrier to prevent read from deallocated stack. */
3757 /* Emit a barrier to prevent loads from a deallocated stack. */
3760 {
3763 }
3765 /* Restore the stack pointer from the frame pointer if it may not
3766 be the same as the stack pointer. */
3768 {
3770 hard_frame_pointer_rtx,
3772 /* If writeback is used when restoring callee-saves, the CFA
3773 is restored on the instruction doing the writeback. */
3775 }
3776 else
3791 {
3792 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3798 }
3803 {
3804 /* Emit delayed restores and reset the CFA to be SP. */
3809 }
3811 /* We prefer to emit the combined return/authenticate instruction RETAA,
3812 however there are three cases in which we must instead emit an explicit
3813 authentication instruction.
3815 1) Sibcalls don't return in a normal way, so if we're about to call one
3816 we must authenticate.
3818 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3819 generating code for !TARGET_ARMV8_3 we can't use it and must
3820 explicitly authenticate.
3822 3) On an eh_return path we make extra stack adjustments to update the
3823 canonical frame address to be the exception handler's CFA. We want
3824 to authenticate using the CFA of the function which calls eh_return.
3825 */
3828 {
3832 }
3834 /* Stack adjustment for exception handler. */
3836 {
3837 /* We need to unwind the stack by the offset computed by
3838 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3839 to be SP; letting the CFA move during this adjustment
3840 is just as correct as retaining the CFA from the body
3841 of the function. Therefore, do nothing special. */
3843 }
3848 }
3850 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3851 normally or return to a previous frame after unwinding.
3853 An EH return uses a single shared return sequence. The epilogue is
3854 exactly like a normal epilogue except that it has an extra input
3855 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3856 that must be applied after the frame has been destroyed. An extra label
3857 is inserted before the epilogue which initializes this register to zero,
3858 and this is the entry point for a normal return.
3860 An actual EH return updates the return address, initializes the stack
3861 adjustment and jumps directly into the epilogue (bypassing the zeroing
3862 of the adjustment). Since the return address is typically saved on the
3863 stack when a function makes a call, the saved LR must be updated outside
3864 the epilogue.
3866 This poses problems as the store is generated well before the epilogue,
3867 so the offset of LR is not known yet. Also optimizations will remove the
3868 store as it appears dead, even after the epilogue is generated (as the
3869 base or offset for loading LR is different in many cases).
3871 To avoid these problems this implementation forces the frame pointer
3872 in eh_return functions so that the location of LR is fixed and known early.
3873 It also marks the store volatile, so no optimization is permitted to
3874 remove the store. */
3875 rtx
3877 {
3881 /* Mark the store volatile, so no optimization is permitted to remove it. */
3884 }
3886 /* Output code to add DELTA to the first argument, and then jump
3887 to FUNCTION. Used for C++ multiple inheritance. */
3888 static void
3890 HOST_WIDE_INT delta,
3891 HOST_WIDE_INT vcall_offset,
3892 tree function)
3893 {
3894 /* The this pointer is always in x0. Note that this differs from
3895 Arm where the this pointer maybe bumped to r1 if r0 is required
3896 to return a pointer to an aggregate. On AArch64 a result value
3897 pointer will be in x8. */
3907 else
3908 {
3917 {
3921 else
3923 }
3927 else
3934 else
3935 {
3937 Pmode);
3939 }
3943 else
3949 }
3951 /* Generate a tail call to the target function. */
3953 {
3956 }
3968 /* Stop pretending to be a post-reload pass. */
3970 }
3972 static bool
3974 {
3979 {
3983 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3984 TLS offsets, not real symbol references. */
3987 }
3989 }
3992 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3993 a left shift of 0 or 12 bits. */
3994 bool
3996 {
3999 );
4000 }
4003 /* Return true if val is an immediate that can be loaded into a
4004 register by a MOVZ instruction. */
4005 static bool
4007 {
4009 {
4013 }
4014 else
4015 {
4016 /* Ignore sign extension. */
4018 }
4021 }
4023 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
4026 {
4032 };
4035 /* Return true if val is a valid bitmask immediate. */
4037 bool
4039 {
4043 /* Check for a single sequence of one bits and return quickly if so.
4044 The special cases of all ones and all zeroes returns false. */
4051 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
4055 /* Invert if the immediate doesn't start with a zero bit - this means we
4056 only need to search for sequences of one bits. */
4060 /* Find the first set bit and set tmp to val with the first sequence of one
4061 bits removed. Return success if there is a single sequence of ones. */
4068 /* Find the next set bit and compute the difference in bit position. */
4073 /* Check the bit position difference is a power of 2, and that the first
4074 sequence of one bits fits within 'bits' bits. */
4078 /* Check the sequence of one bits is repeated 64/bits times. */
4080 }
4082 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4083 Assumed precondition: VAL_IN Is not zero. */
4085 unsigned HOST_WIDE_INT
4087 {
4094 }
4096 /* Create constant where bits outside of lowest bit set to highest bit set
4097 are set to 1. */
4099 unsigned HOST_WIDE_INT
4101 {
4103 }
4105 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4107 bool
4109 {
4110 scalar_int_mode int_mode;
4123 }
4125 /* Return true if val is an immediate that can be loaded into a
4126 register in a single instruction. */
4127 bool
4129 {
4130 scalar_int_mode int_mode;
4137 }
4139 static bool
4141 {
4149 {
4153 else
4154 /* Avoid generating a 64-bit relocation in ILP32; leave
4155 to aarch64_expand_mov_immediate to handle it properly. */
4157 }
4160 }
4162 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4163 The expansion for a table switch is quite expensive due to the number
4164 of instructions, the table lookup and hard to predict indirect jump.
4165 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4166 set, otherwise use tables for > 16 cases as a tradeoff between size and
4167 performance. When optimizing for size, use the default setting. */
4169 static unsigned int
4171 {
4172 /* Use the specified limit for the number of cases before using jump
4173 tables at higher optimization levels. */
4177 else
4179 }
4181 /* Return true if register REGNO is a valid index register.
4182 STRICT_P is true if REG_OK_STRICT is in effect. */
4184 bool
4186 {
4188 {
4196 }
4198 }
4200 /* Return true if register REGNO is a valid base register for mode MODE.
4201 STRICT_P is true if REG_OK_STRICT is in effect. */
4203 bool
4205 {
4207 {
4215 }
4217 /* The fake registers will be eliminated to either the stack or
4218 hard frame pointer, both of which are usually valid base registers.
4219 Reload deals with the cases where the eliminated form isn't valid. */
4224 }
4226 /* Return true if X is a valid base register for mode MODE.
4227 STRICT_P is true if REG_OK_STRICT is in effect. */
4229 static bool
4231 {
4238 }
4240 /* Return true if address offset is a valid index. If it is, fill in INFO
4241 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4243 static bool
4246 {
4248 rtx index;
4251 /* (reg:P) */
4254 {
4258 }
4259 /* (sign_extend:DI (reg:SI)) */
4264 {
4269 }
4270 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4277 {
4282 }
4283 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4290 {
4295 }
4296 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4303 {
4311 }
4312 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4313 (const_int 0xffffffff<<shift)) */
4320 {
4326 }
4327 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4334 {
4342 }
4343 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4344 (const_int 0xffffffff<<shift)) */
4351 {
4357 }
4358 /* (mult:P (reg:P) (const_int scale)) */
4363 {
4367 }
4368 /* (ashift:P (reg:P) (const_int shift)) */
4373 {
4377 }
4378 else
4391 {
4396 }
4399 }
4401 /* Return true if MODE is one of the modes for which we
4402 support LDP/STP operations. */
4404 static bool
4406 {
4411 }
4413 /* Return true if REGNO is a virtual pointer register, or an eliminable
4414 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4415 include stack_pointer or hard_frame_pointer. */
4416 static bool
4418 {
4423 }
4425 /* Return true if X is a valid address for machine mode MODE. If it is,
4426 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4427 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4429 static bool
4433 {
4437 /* On BE, we use load/store pair for all large int mode load/stores.
4438 TI/TFmode may also use a load/store pair. */
4442 || (BYTES_BIG_ENDIAN
4446 !load_store_pair_p
4450 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4451 REG addressing. */
4457 {
4473 {
4479 }
4484 {
4491 /* TImode and TFmode values are allowed in both pairs of X
4492 registers and individual Q registers. The available
4493 address modes are:
4494 X,X: 7-bit signed scaled offset
4495 Q: 9-bit signed offset
4496 We conservatively require an offset representable in either mode.
4497 When performing the check for pairs of X registers i.e. LDP/STP
4498 pass down DImode since that is the natural size of the LDP/STP
4499 instruction memory accesses. */
4505 /* A 7bit offset check because OImode will emit a ldp/stp
4506 instruction (only big endian will get here).
4507 For ldp/stp instructions, the offset is scaled for the size of a
4508 single element of the pair. */
4512 /* Three 9/12 bit offsets checks because CImode will emit three
4513 ldr/str instructions (only big endian will get here). */
4520 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4521 instructions (only big endian will get here). */
4530 else
4533 }
4536 {
4537 /* Look for base + (scaled/extended) index register. */
4540 {
4543 }
4546 {
4549 }
4550 }
4571 {
4572 HOST_WIDE_INT offset;
4576 /* TImode and TFmode values are allowed in both pairs of X
4577 registers and individual Q registers. The available
4578 address modes are:
4579 X,X: 7-bit signed scaled offset
4580 Q: 9-bit signed offset
4581 We conservatively require an offset representable in either mode.
4582 */
4590 else
4592 }
4598 /* load literal: pc-relative constant pool entry. Only supported
4599 for SI mode or larger. */
4603 {
4611 }
4620 {
4625 {
4626 /* The symbol and offset must be aligned to the access size. */
4633 {
4637 }
4643 else
4652 }
4653 }
4658 }
4659 }
4661 /* Return true if the address X is valid for a PRFM instruction.
4662 STRICT_P is true if we should do strict checking with
4663 aarch64_classify_address. */
4665 bool
4667 {
4670 /* PRFM accepts the same addresses as DImode... */
4675 /* ... except writeback forms. */
4677 }
4679 bool
4681 {
4682 rtx offset;
4686 }
4688 /* Classify the base of symbolic expression X. */
4690 enum aarch64_symbol_type
4692 {
4693 rtx offset;
4697 }
4700 /* Return TRUE if X is a legitimate address for accessing memory in
4701 mode MODE. */
4702 static bool
4704 {
4708 }
4710 /* Return TRUE if X is a legitimate address for accessing memory in
4711 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4712 pair operation. */
4713 bool
4716 {
4720 }
4722 /* Split an out-of-range address displacement into a base and offset.
4723 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4724 to increase opportunities for sharing the base address of different sizes.
4725 For unaligned accesses and TI/TF mode use the signed 9-bit range. */
4726 static bool
4728 {
4739 }
4741 /* Return the binary representation of floating point constant VALUE in INTVAL.
4742 If the value cannot be converted, return false without setting INTVAL.
4743 The conversion is done in the given MODE. */
4744 bool
4746 {
4748 /* We make a general exception for 0. */
4750 {
4753 }
4759 /* Only support up to DF mode. */
4771 {
4775 }
4776 else
4781 }
4783 /* Return TRUE if rtx X is an immediate constant that can be moved using a
4784 single MOV(+MOVK) followed by an FMOV. */
4785 bool
4787 {
4792 /* Determine whether it's cheaper to write float constants as
4793 mov/movk pairs over ldr/adrp pairs. */
4799 {
4801 ? SImode
4806 }
4809 }
4811 /* Return TRUE if rtx X is immediate constant 0.0 */
4812 bool
4814 {
4821 }
4823 /* Return TRUE if rtx X is immediate constant that fits in a single
4824 MOVI immediate operation. */
4825 bool
4827 {
4831 machine_mode vmode;
4832 scalar_int_mode imode;
4837 {
4841 /* We make a general exception for 0. */
4846 }
4850 else
4853 /* use a 64 bit mode for everything except for DI/DF mode, where we use
4854 a 128 bit vector mode. */
4861 }
4864 /* Return the fixed registers used for condition codes. */
4866 static bool
4868 {
4872 }
4874 /* This function is used by the call expanders of the machine description.
4875 RESULT is the register in which the result is returned. It's NULL for
4876 "call" and "sibcall".
4877 MEM is the location of the function call.
4878 SIBCALL indicates whether this function call is normal call or sibling call.
4879 It will generate different pattern accordingly. */
4881 void
4883 {
4885 rtvec vec;
4886 machine_mode mode;
4893 /* Decide if we should generate indirect calls by loading the
4894 address of the callee into a register before performing
4895 the branch-and-link. */
4909 else
4916 }
4918 /* Emit call insn with PAT and do aarch64-specific handling. */
4920 void
4922 {
4928 }
4930 machine_mode
4932 {
4933 /* All floating point compares return CCFP if it is an equality
4934 comparison, and CCFPE otherwise. */
4936 {
4938 {
4959 }
4960 }
4962 /* Equality comparisons of short modes against zero can be performed
4963 using the TST instruction with the appropriate bitmask. */
4969 /* Similarly, comparisons of zero_extends from shorter modes can
4970 be performed using an ANDS with an immediate mask. */
4986 /* A compare with a shifted operand. Because of canonicalization,
4987 the comparison will have to be swapped when we emit the assembly
4988 code. */
4996 /* Similarly for a negated operand, but we can only do this for
4997 equalities. */
5004 /* A test for unsigned overflow. */
5011 /* For everything else, return CCmode. */
5013 }
5015 static int
5018 int
5020 {
5027 }
5029 static int
5031 {
5033 {
5037 {
5051 }
5056 {
5068 }
5073 {
5085 }
5090 {
5096 }
5101 {
5105 }
5110 {
5114 }
5119 }
5122 }
5124 bool
5126 HOST_WIDE_INT minval,
5127 HOST_WIDE_INT maxval)
5128 {
5129 HOST_WIDE_INT firstval;
5146 }
5148 bool
5150 {
5152 }
5155 /* N Z C V. */
5156 #define AARCH64_CC_V 1
5157 #define AARCH64_CC_C (1 << 1)
5158 #define AARCH64_CC_Z (1 << 2)
5159 #define AARCH64_CC_N (1 << 3)
5161 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
5163 {
5180 };
5182 /* Print operand X to file F in a target specific manner according to CODE.
5183 The acceptable formatting commands given by CODE are:
5184 'c': An integer or symbol address without a preceding #
5185 sign.
5186 'e': Print the sign/zero-extend size as a character 8->b,
5187 16->h, 32->w.
5188 'p': Prints N such that 2^N == X (X must be power of 2 and
5189 const int).
5190 'P': Print the number of non-zero bits in X (a const_int).
5191 'H': Print the higher numbered register of a pair (TImode)
5192 of regs.
5193 'm': Print a condition (eq, ne, etc).
5194 'M': Same as 'm', but invert condition.
5195 'b/h/s/d/q': Print a scalar FP/SIMD register name.
5196 'S/T/U/V': Print a FP/SIMD register name for a register list.
5197 The register printed is the FP/SIMD register name
5198 of X + 0/1/2/3 for S/T/U/V.
5199 'R': Print a scalar FP/SIMD register name + 1.
5200 'X': Print bottom 16 bits of integer constant in hex.
5201 'w/x': Print a general register name or the zero register
5202 (32-bit or 64-bit).
5203 '0': Print a normal operand, if it's a general register,
5204 then we assume DImode.
5205 'k': Print NZCV for conditional compare instructions.
5206 'A': Output address constant representing the first
5207 argument of X, specifying a relocation offset
5208 if appropriate.
5209 'L': Output constant address specified by X
5210 with a relocation offset if appropriate.
5211 'G': Prints address of X, specifying a PC relative
5212 relocation mode if appropriate. */
5214 static void
5216 {
5218 {
5221 {
5233 {
5236 }
5237 /* Fall through. */
5241 }
5245 {
5250 {
5253 }
5256 {
5269 }
5270 }
5274 {
5278 {
5281 }
5284 }
5289 {
5292 }
5299 {
5302 }
5309 {
5311 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5313 {
5317 }
5320 {
5323 }
5330 }
5339 {
5340 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5342 }
5351 {
5352 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5354 }
5360 {
5361 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5363 }
5369 {
5372 }
5380 {
5383 }
5386 {
5389 }
5392 {
5395 }
5397 /* Fall through */
5401 {
5404 }
5407 {
5414 /* Check all memory references are Pmode - even with ILP32. */
5430 {
5433 HOST_WIDE_INT_MIN,
5434 HOST_WIDE_INT_MAX));
5436 }
5438 {
5440 }
5441 else
5446 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5447 be getting CONST_DOUBLEs holding integers. */
5450 {
5453 }
5455 {
5456 #define buf_size 20
5464 #undef buf_size
5465 }
5471 }
5479 {
5506 }
5512 {
5547 }
5553 {
5559 }
5564 {
5565 HOST_WIDE_INT cond_code;
5568 {
5571 }
5576 }
5582 }
5583 }
5585 static void
5587 {
5592 {
5596 else
5605 else
5614 else
5623 else
5630 {
5657 }
5668 }
5671 }
5673 bool
5675 {
5682 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5683 referencing instruction, but they are constant offsets, not
5684 symbols. */
5690 {
5692 {
5698 }
5701 }
5704 }
5706 /* Implement REGNO_REG_CLASS. */
5708 enum reg_class
5710 {
5725 }
5727 static rtx
5729 {
5730 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5731 where mask is selected by alignment and size of the offset.
5732 We try to pick as large a range for the offset as possible to
5733 maximize the chance of a CSE. However, for aligned addresses
5734 we limit the range to 4k so that structures with different sized
5735 elements are likely to use the same base. We need to be careful
5736 not to split a CONST for some forms of address expression, otherwise
5737 it will generate sub-optimal code. */
5740 {
5746 {
5750 /* Force any scaling into a temp for CSE. */
5754 /* Let the pointer register be in op0. */
5758 /* If the pointer is virtual or frame related, then we know that
5759 virtual register instantiation or register elimination is going
5760 to apply a second constant. We want the two constants folded
5761 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5763 {
5767 }
5769 /* Otherwise, in order to encourage CSE (and thence loop strength
5770 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5774 }
5776 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5777 HOST_WIDE_INT base_offset;
5780 /* For offsets aren't a multiple of the access size, the limit is
5781 -256...255. */
5783 {
5786 /* BLKmode typically uses LDP of X-registers. */
5789 }
5790 /* Small negative offsets are supported. */
5795 /* Use 12-bit offset by access size. */
5796 else
5800 {
5804 }
5805 }
5808 }
5810 /* Return the reload icode required for a constant pool in mode. */
5811 static enum insn_code
5813 {
5815 {
5851 }
5854 }
5855 static reg_class_t
5857 reg_class_t rclass,
5858 machine_mode mode,
5860 {
5862 /* If we have to disable direct literal pool loads and stores because the
5863 function is too big, then we need a scratch register. */
5868 {
5871 }
5873 /* Without the TARGET_SIMD instructions we cannot move a Q register
5874 to a Q register directly. We need a scratch. */
5878 {
5884 }
5886 /* A TFmode or TImode memory access should be handled via an FP_REGS
5887 because AArch64 has richer addressing modes for LDR/STR instructions
5888 than LDP/STP instructions. */
5897 }
5899 static bool
5901 {
5902 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5903 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5906 {
5918 }
5919 else
5920 {
5921 /* If we decided that we didn't need a leaf frame pointer but then used
5922 LR in the function, then we'll want a frame pointer after all, so
5923 prevent this elimination to ensure a frame pointer is used. */
5925 && flag_omit_leaf_frame_pointer
5928 }
5931 }
5933 HOST_WIDE_INT
5935 {
5939 {
5946 }
5949 {
5953 }
5956 }
5958 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5959 previous frame. */
5961 rtx
5963 {
5967 }
5970 static void
5972 {
5974 {
5977 }
5978 else
5979 {
5982 }
5987 }
5989 static void
5991 {
5995 /* Don't need to copy the trailing D-words, we fill those in below. */
6007 /* XXX We should really define a "clear_cache" pattern and use
6008 gen_clear_cache(). */
6013 ptr_mode);
6014 }
6016 static unsigned char
6018 {
6020 {
6028 return
6040 }
6042 }
6044 static reg_class_t
6046 {
6051 {
6057 }
6059 /* Register eliminiation can result in a request for
6060 SP+constant->FP_REGS. We cannot support such operations which
6061 use SP as source and an FP_REG as destination, so reject out
6062 right now. */
6064 {
6067 /* Look through a possible SUBREG introduced by ILP32. */
6073 POINTER_REGS));
6075 }
6078 }
6080 void
6082 {
6084 }
6086 static void
6088 {
6091 else
6092 {
6094 /* While priority is known to be in range [0, 65535], so 18 bytes
6095 would be enough, the compiler might not know that. To avoid
6096 -Wformat-truncation false positive, use a larger size. */
6103 }
6104 }
6106 static void
6108 {
6111 else
6112 {
6114 /* While priority is known to be in range [0, 65535], so 18 bytes
6115 would be enough, the compiler might not know that. To avoid
6116 -Wformat-truncation false positive, use a larger size. */
6123 }
6124 }
6128 {
6134 {
6135 {
6138 },
6139 {
6142 },
6143 {
6146 },
6147 /* We assume that DImode is only generated when not optimizing and
6148 that we don't really need 64-bit address offsets. That would
6149 imply an object file with 8GB of code in a single function! */
6150 {
6153 }
6154 };
6163 /* Need to implement table size reduction, by chaning the code below. */
6173 }
6176 /* Return size in bits of an arithmetic operand which is shifted/scaled and
6177 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
6178 operator. */
6180 int
6182 {
6184 {
6187 {
6191 }
6192 }
6194 }
6196 /* Constant pools are per function only when PC relative
6197 literal loads are true or we are in the large memory
6198 model. */
6202 {
6205 }
6207 static bool
6209 {
6210 /* Fixme:: In an ideal world this would work similar
6211 to the logic in aarch64_select_rtx_section but this
6212 breaks bootstrap in gcc go. For now we workaround
6213 this by returning false here. */
6215 }
6217 /* Select appropriate section for constants depending
6218 on where we place literal pools. */
6222 rtx x,
6224 {
6229 }
6231 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
6232 void
6234 HOST_WIDE_INT offset)
6235 {
6236 /* When using per-function literal pools, we must ensure that any code
6237 section is aligned to the minimal instruction length, lest we get
6238 errors from the assembler re "unaligned instructions". */
6241 }
6243 /* Costs. */
6245 /* Helper function for rtx cost calculation. Strip a shift expression
6246 from X. Returns the inner operand if successful, or the original
6247 expression on failure. */
6248 static rtx
6250 {
6253 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
6254 we can convert both to ROR during final output. */
6269 }
6271 /* Helper function for rtx cost calculation. Strip an extend
6272 expression from X. Returns the inner operand if successful, or the
6273 original expression on failure. We deal with a number of possible
6274 canonicalization variations here. If STRIP_SHIFT is true, then
6275 we can strip off a shift also. */
6276 static rtx
6278 {
6279 scalar_int_mode mode;
6285 /* Zero and sign extraction of a widened value. */
6293 /* It can also be represented (for zero-extend) as an AND with an
6294 immediate. */
6303 /* Now handle extended register, as this may also have an optional
6304 left shift by 1..4. */
6319 }
6321 /* Return true iff CODE is a shift supported in combination
6322 with arithmetic instructions. */
6324 static bool
6326 {
6328 }
6331 /* Return true iff X is a cheap shift without a sign extend. */
6333 static bool
6335 {
6361 }
6363 /* Helper function for rtx cost calculation. Calculate the cost of
6364 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6365 Return the calculated cost of the expression, recursing manually in to
6366 operands where needed. */
6368 static int
6370 {
6386 /* Integer multiply/fma. */
6388 {
6389 /* The multiply will be canonicalized as a shift, cost it as such. */
6393 {
6397 {
6399 {
6400 /* If the shift is considered cheap,
6401 then don't add any cost. */
6403 ;
6405 /* ARITH + shift-by-register. */
6408 /* ARITH + extended register. We don't have a cost field
6409 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6411 else
6412 /* ARITH + shift-by-immediate. */
6414 }
6415 else
6416 /* LSL (immediate). */
6419 }
6420 /* Strip extends as we will have costed them in the case above. */
6427 }
6429 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6430 compound and let the below cases handle it. After all, MNEG is a
6431 special-case alias of MSUB. */
6433 {
6436 }
6438 /* Integer multiplies or FMAs have zero/sign extending variants. */
6443 {
6448 {
6450 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6452 else
6453 /* MUL/SMULL/UMULL. */
6455 }
6458 }
6460 /* This is either an integer multiply or a MADD. In both cases
6461 we want to recurse and cost the operands. */
6466 {
6468 /* MADD/MSUB. */
6470 else
6471 /* MUL. */
6473 }
6476 }
6477 else
6478 {
6480 {
6481 /* Floating-point FMA/FMUL can also support negations of the
6482 operands, unless the rounding mode is upward or downward in
6483 which case FNMUL is different than FMUL with operand negation. */
6487 {
6492 }
6495 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6497 else
6498 /* FMUL/FNMUL. */
6500 }
6505 }
6506 }
6508 static int
6510 machine_mode mode,
6511 addr_space_t as ATTRIBUTE_UNUSED,
6513 {
6521 {
6523 {
6524 /* This is a CONST or SYMBOL ref which will be split
6525 in a different way depending on the code model in use.
6526 Cost it through the generic infrastructure. */
6528 /* Divide through by the cost of one instruction to
6529 bring it to the same units as the address costs. */
6531 /* The cost is then the cost of preparing the address,
6532 followed by an immediate (possibly 0) offset. */
6534 }
6535 else
6536 {
6537 /* This is most likely a jump table from a case
6538 statement. */
6540 }
6541 }
6544 {
6556 else
6575 }
6579 {
6580 /* For the sake of calculating the cost of the shifted register
6581 component, we can treat same sized modes in the same way. */
6583 {
6596 /* We can't tell, or this is a 128-bit vector. */
6600 }
6601 }
6604 }
6606 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6607 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6608 to be taken. */
6610 int
6612 {
6613 /* When optimizing for speed, use the cost of unpredictable branches. */
6619 else
6621 }
6623 /* Return true if the RTX X in mode MODE is a zero or sign extract
6624 usable in an ADD or SUB (extended register) instruction. */
6625 static bool
6627 {
6628 /* Catch add with a sign extract.
6629 This is add_<optab><mode>_multp2. */
6632 {
6643 op1))
6644 {
6646 }
6647 }
6648 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6649 No shift. */
6655 }
6657 static bool
6659 {
6661 {
6673 }
6674 }
6676 /* Return true iff X is an rtx that will match an extr instruction
6677 i.e. as described in the *extr<mode>5_insn family of patterns.
6678 OP0 and OP1 will be set to the operands of the shifts involved
6679 on success and will be NULL_RTX otherwise. */
6681 static bool
6683 {
6685 scalar_int_mode mode;
6700 {
6701 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6713 {
6717 }
6718 }
6721 }
6723 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6724 storing it in *COST. Result is true if the total cost of the operation
6725 has now been calculated. */
6726 static bool
6728 {
6729 rtx inner;
6730 rtx comparator;
6734 {
6738 }
6739 else
6740 {
6744 }
6747 {
6748 /* Conditional branch. */
6751 else
6752 {
6754 {
6756 {
6757 /* TBZ/TBNZ/CBZ/CBNZ. */
6759 /* TBZ/TBNZ. */
6762 else
6763 /* CBZ/CBNZ. */
6767 }
6768 }
6770 {
6771 /* TBZ/TBNZ. */
6774 }
6775 }
6776 }
6778 {
6779 /* CCMP. */
6781 {
6782 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6786 {
6793 else
6795 }
6797 }
6799 /* It's a conditional operation based on the status flags,
6800 so it must be some flavor of CSEL. */
6802 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6808 {
6809 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6812 }
6817 }
6819 /* We don't know what this is, cost all operands. */
6821 }
6823 /* Check whether X is a bitfield operation of the form shift + extend that
6824 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6825 operand to which the bitfield operation is applied. Otherwise return
6826 NULL_RTX. */
6828 static rtx
6830 {
6844 {
6862 }
6865 }
6867 /* Return true if the mask and a shift amount from an RTX of the form
6868 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6869 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6871 bool
6873 rtx shft_amnt)
6874 {
6879 }
6881 /* Calculate the cost of calculating X, storing it in *COST. Result
6882 is true if the total cost of the operation has now been calculated. */
6883 static bool
6886 {
6891 scalar_int_mode int_mode;
6893 /* By default, assume that everything has equivalent cost to the
6894 cheapest instruction. Any additional costs are applied as a delta
6895 above this default. */
6899 {
6901 /* The cost depends entirely on the operands to SET. */
6907 {
6910 {
6924 }
6933 /* Fall through. */
6935 /* The cost is one per vector-register copied. */
6937 {
6941 }
6942 /* const0_rtx is in general free, but we will use an
6943 instruction to set a register to 0. */
6945 {
6946 /* The cost is 1 per register copied. */
6950 }
6951 else
6952 /* Cost is just the cost of the RHS of the set. */
6958 /* Bit-field insertion. Strip any redundant widening of
6959 the RHS to meet the width of the target. */
6970 {
6971 /* MOV immediate is assumed to always be cheap. */
6973 }
6974 else
6975 {
6976 /* BFM. */
6980 }
6985 /* We can't make sense of this, assume default cost. */
6988 }
6992 /* If an instruction can incorporate a constant within the
6993 instruction, the instruction's expression avoids calling
6994 rtx_cost() on the constant. If rtx_cost() is called on a
6995 constant, then it is usually because the constant must be
6996 moved into a register by one or more instructions.
6998 The exception is constant 0, which can be expressed
6999 as XZR/WZR and is therefore free. The exception to this is
7000 if we have (set (reg) (const0_rtx)) in which case we must cost
7001 the move. However, we can catch that when we cost the SET, so
7002 we don't need to consider that here. */
7005 else
7006 {
7007 /* To an approximation, building any other constant is
7008 proportionally expensive to the number of instructions
7009 required to build that constant. This is true whether we
7010 are compiling for SPEED or otherwise. */
7015 }
7020 /* First determine number of instructions to do the move
7021 as an integer constant. */
7025 {
7031 ? SImode
7037 }
7040 {
7041 /* mov[df,sf]_aarch64. */
7043 /* FMOV (scalar immediate). */
7046 {
7047 /* This will be a load from memory. */
7050 else
7052 }
7053 else
7054 /* Otherwise this is +0.0. We get this using MOVI d0, #0
7055 or MOV v0.s[0], wzr - neither of which are modeled by the
7056 cost tables. Just use the default cost. */
7057 {
7058 }
7059 }
7065 {
7066 /* For loads we want the base cost of a load, plus an
7067 approximation for the additional cost of the addressing
7068 mode. */
7082 }
7090 {
7092 {
7093 /* FNEG. */
7095 }
7097 }
7100 {
7103 {
7104 /* CSETM. */
7107 }
7109 /* Cost this as SUB wzr, X. */
7113 }
7116 {
7117 /* Support (neg(fma...)) as a single instruction only if
7118 sign of zeros is unimportant. This matches the decision
7119 making in aarch64.md. */
7121 {
7122 /* FNMADD. */
7125 }
7127 {
7128 /* FNMUL. */
7131 }
7133 /* FNEG. */
7136 }
7143 {
7146 else
7148 }
7158 {
7162 }
7165 {
7166 /* TODO: A write to the CC flags possibly costs extra, this
7167 needs encoding in the cost tables. */
7170 /* ANDS. */
7172 {
7175 }
7178 {
7179 /* ADDS (and CMN alias). */
7182 }
7185 {
7186 /* SUBS. */
7189 }
7194 {
7195 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
7196 Handle it here directly rather than going to cost_logic
7197 since we know the immediate generated for the TST is valid
7198 so we can avoid creating an intermediate rtx for it only
7199 for costing purposes. */
7206 }
7209 {
7210 /* CMN. */
7217 }
7219 /* CMP.
7221 Compare can freely swap the order of operands, and
7222 canonicalization puts the more complex operation first.
7223 But the integer MINUS logic expects the shift/extend
7224 operation in op1. */
7227 {
7230 }
7232 }
7235 {
7236 /* FCMP. */
7241 {
7243 /* FCMP supports constant 0.0 for no extra cost. */
7245 }
7247 }
7250 {
7251 /* Vector compare. */
7256 {
7257 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
7258 cost. */
7260 }
7262 }
7266 {
7270 cost_minus:
7273 /* Detect valid immediates. */
7279 {
7281 /* SUB(S) (immediate). */
7284 }
7286 /* Look for SUB (extended register). */
7289 {
7297 }
7301 /* Cost this as an FMA-alike operation. */
7305 {
7308 speed);
7310 }
7315 {
7317 {
7318 /* Vector SUB. */
7320 }
7322 {
7323 /* SUB(S). */
7325 }
7327 {
7328 /* FSUB. */
7330 }
7331 }
7333 }
7336 {
7337 rtx new_op0;
7342 cost_plus:
7345 {
7346 /* CSINC. */
7350 }
7355 {
7359 /* ADD (immediate). */
7362 }
7366 /* Look for ADD (extended register). */
7369 {
7377 }
7379 /* Strip any extend, leave shifts behind as we will
7380 cost them through mult_cost. */
7385 {
7387 speed);
7389 }
7394 {
7396 {
7397 /* Vector ADD. */
7399 }
7401 {
7402 /* ADD. */
7404 }
7406 {
7407 /* FADD. */
7409 }
7410 }
7412 }
7418 {
7421 else
7423 }
7428 {
7432 {
7435 else
7437 }
7439 }
7442 {
7449 }
7450 /* Fall through. */
7453 cost_logic:
7458 {
7462 }
7470 {
7471 /* This is a UBFM/SBFM. */
7476 }
7479 {
7481 {
7482 /* We have a mask + shift version of a UBFIZ
7483 i.e. the *andim_ashift<mode>_bfiz pattern. */
7487 {
7494 }
7496 {
7497 /* We possibly get the immediate for free, this is not
7498 modelled. */
7505 }
7506 }
7507 else
7508 {
7511 /* Handle ORN, EON, or BIC. */
7517 /* If we had a shift on op0 then this is a logical-shift-
7518 by-register/immediate operation. Otherwise, this is just
7519 a logical operation. */
7521 {
7523 {
7524 /* Shift by immediate. */
7527 else
7529 }
7530 else
7532 }
7534 /* In both cases we want to cost both operands. */
7541 }
7542 }
7550 {
7551 /* Vector NOT. */
7554 }
7556 /* MVN-shifted-reg. */
7558 {
7565 }
7566 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7567 Handle the second form here taking care that 'a' in the above can
7568 be a shift. */
7570 {
7579 {
7582 else
7584 }
7587 }
7588 /* MVN. */
7597 /* If a value is written in SI mode, then zero extended to DI
7598 mode, the operation will in general be free as a write to
7599 a 'w' register implicitly zeroes the upper bits of an 'x'
7600 register. However, if this is
7602 (set (reg) (zero_extend (reg)))
7604 we must cost the explicit register move. */
7608 {
7611 /* If OP_COST is non-zero, then the cost of the zero extend
7612 is effectively the cost of the inner operation. Otherwise
7613 we have a MOV instruction and we take the cost from the MOV
7614 itself. This is true independently of whether we are
7615 optimizing for space or time. */
7620 }
7622 {
7623 /* All loads can zero extend to any size for free. */
7626 }
7630 {
7635 }
7638 {
7640 {
7641 /* UMOV. */
7643 }
7644 else
7645 {
7646 /* We generate an AND instead of UXTB/UXTH. */
7648 }
7649 }
7654 {
7655 /* LDRSH. */
7657 {
7664 }
7666 }
7670 {
7675 }
7678 {
7681 else
7683 }
7691 {
7693 {
7695 {
7696 /* Vector shift (immediate). */
7698 }
7699 else
7700 {
7701 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7702 aliases. */
7704 }
7705 }
7707 /* We can incorporate zero/sign extend for free. */
7714 }
7715 else
7716 {
7718 {
7720 /* Vector shift (register). */
7722 }
7723 else
7724 {
7726 /* LSLV. */
7732 {
7734 /* We already demanded XEXP (op1, 0) to be REG_P, so
7735 don't recurse into it. */
7737 }
7738 }
7740 }
7750 {
7751 /* ASR (immediate) and friends. */
7753 {
7756 else
7758 }
7762 }
7763 else
7764 {
7766 {
7768 /* Vector shift (register). */
7770 }
7771 else
7772 {
7774 /* ASR (register) and friends. */
7780 {
7782 /* We already demanded XEXP (op1, 0) to be REG_P, so
7783 don't recurse into it. */
7785 }
7786 }
7788 }
7794 {
7795 /* LDR. */
7798 }
7801 {
7802 /* ADRP, followed by ADD. */
7806 }
7809 {
7810 /* ADR. */
7813 }
7816 {
7817 /* One extra load instruction, after accessing the GOT. */
7821 }
7826 /* ADRP/ADD (immediate). */
7833 /* UBFX/SBFX. */
7835 {
7838 else
7840 }
7842 /* We can trust that the immediates used will be correct (there
7843 are no by-register forms), so we need only cost op0. */
7849 /* aarch64_rtx_mult_cost always handles recursion to its
7850 operands. */
7854 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7855 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7856 an unconditional negate. This case should only ever be reached through
7857 the set_smod_pow2_cheap check in expmed.c. */
7861 {
7862 /* We expand to 4 instructions. Reset the baseline. */
7870 }
7872 /* Fall-through. */
7875 {
7876 /* Slighly prefer UMOD over SMOD. */
7883 }
7890 {
7894 /* There is no integer SQRT, so only DIV and UDIV can get
7895 here. */
7897 /* Slighly prefer UDIV over SDIV. */
7899 else
7901 }
7927 {
7930 else
7932 }
7934 /* FMSUB, FNMADD, and FNMSUB are free. */
7941 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7942 and the by-element operand as operand 0. */
7946 /* Catch vector-by-element operations. The by-element operand can
7947 either be (vec_duplicate (vec_select (x))) or just
7948 (vec_select (x)), depending on whether we are multiplying by
7949 a vector or a scalar.
7951 Canonicalization is not very good in these cases, FMA4 will put the
7952 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7963 /* If the remaining parameters are not registers,
7964 get the cost to put them into registers. */
7978 {
7980 {
7981 /*Vector truncate. */
7983 }
7984 else
7986 }
7991 {
7993 {
7994 /*Vector conversion. */
7996 }
7997 else
7999 }
8005 /* Strip the rounding part. They will all be implemented
8006 by the fcvt* family of instructions anyway. */
8008 {
8017 }
8020 {
8023 else
8025 }
8027 /* We can combine fmul by a power of 2 followed by a fcvt into a single
8028 fixed-point fcvt. */
8033 {
8037 }
8044 {
8045 /* ABS (vector). */
8048 }
8050 {
8053 /* FABD, which is analogous to FADD. */
8055 {
8062 }
8063 /* Simple FABS is analogous to FNEG. */
8066 }
8067 else
8068 {
8069 /* Integer ABS will either be split to
8070 two arithmetic instructions, or will be an ABS
8071 (scalar), which we don't model. */
8075 }
8081 {
8084 else
8085 {
8086 /* FMAXNM/FMINNM/FMAX/FMIN.
8087 TODO: This may not be accurate for all implementations, but
8088 we do not model this in the cost tables. */
8090 }
8091 }
8095 /* The floating point round to integer frint* instructions. */
8097 {
8102 }
8105 {
8110 }
8115 /* Decompose <su>muldi3_highpart. */
8117 mode == DImode
8118 /* (lshiftrt:TI */
8121 /* (mult:TI */
8123 /* (ANY_EXTEND:TI (reg:DI))
8124 (ANY_EXTEND:TI (reg:DI))) */
8131 /* (const_int 64) */
8134 {
8135 /* UMULH/SMULH. */
8143 }
8145 /* Fall through. */
8148 }
8156 }
8158 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
8159 calculated for X. This cost is stored in *COST. Returns true
8160 if the total cost of X was calculated. */
8161 static bool
8164 {
8169 {
8174 }
8177 }
8179 static int
8182 {
8188 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
8195 /* Moving between GPR and stack cost is the same as GP2GP. */
8200 /* To/From the stack register, we move via the gprs. */
8206 {
8207 /* 128-bit operations on general registers require 2 instructions. */
8215 /* When AdvSIMD instructions are disabled it is not possible to move
8216 a 128-bit value directly between Q registers. This is handled in
8217 secondary reload. A general register is used as a scratch to move
8218 the upper DI value and the lower DI value is moved directly,
8219 hence the cost is the sum of three moves. */
8224 }
8234 }
8236 static int
8238 reg_class_t rclass ATTRIBUTE_UNUSED,
8240 {
8242 }
8244 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
8245 to optimize 1.0/sqrt. */
8247 static bool
8249 {
8251 && flag_unsafe_math_optimizations
8255 }
8257 /* Function to decide when to use the approximate reciprocal square root
8258 builtin. */
8260 static tree
8262 {
8268 }
8272 /* Select reciprocal square root initial estimate insn depending on machine
8273 mode. */
8275 static rsqrte_type
8277 {
8279 {
8286 }
8287 }
8291 /* Select reciprocal square root series step insn depending on machine mode. */
8293 static rsqrts_type
8295 {
8297 {
8304 }
8305 }
8307 /* Emit instruction sequence to compute either the approximate square root
8308 or its approximate reciprocal, depending on the flag RECP, and return
8309 whether the sequence was emitted or not. */
8311 bool
8313 {
8317 {
8320 }
8323 {
8330 || flag_trapping_math
8331 || !flag_unsafe_math_optimizations
8334 }
8335 else
8336 /* Caller assumes we cannot fail. */
8342 /* When calculating the approximate square root, compare the
8343 argument with 0.0 and create a mask. */
8349 /* Estimate the approximate reciprocal square root. */
8353 /* Iterate over the series twice for SF and thrice for DF. */
8356 /* Optionally iterate over the series once less for faster performance
8357 while sacrificing the accuracy. */
8360 iterations--;
8362 /* Iterate over the series to calculate the approximate reciprocal square
8363 root. */
8366 {
8374 }
8377 {
8378 /* Qualify the approximate reciprocal square root when the argument is
8379 0.0 by squashing the intermediary result to 0.0. */
8385 /* Calculate the approximate square root. */
8387 }
8389 /* Finalize the approximation. */
8393 }
8397 /* Select reciprocal initial estimate insn depending on machine mode. */
8399 static recpe_type
8401 {
8403 {
8410 }
8411 }
8415 /* Select reciprocal series step insn depending on machine mode. */
8417 static recps_type
8419 {
8421 {
8428 }
8429 }
8431 /* Emit the instruction sequence to compute the approximation for the division
8432 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8434 bool
8436 {
8447 || flag_trapping_math
8448 || !flag_unsafe_math_optimizations
8453 /* Estimate the approximate reciprocal. */
8457 /* Iterate over the series twice for SF and thrice for DF. */
8460 /* Optionally iterate over the series once less for faster performance,
8461 while sacrificing the accuracy. */
8463 iterations--;
8465 /* Iterate over the series to calculate the approximate reciprocal. */
8468 {
8473 }
8476 {
8477 /* As the approximate reciprocal of DEN is already calculated, only
8478 calculate the approximate division when NUM is not 1.0. */
8481 }
8483 /* Finalize the approximation. */
8486 }
8488 /* Return the number of instructions that can be issued per cycle. */
8489 static int
8491 {
8493 }
8495 static int
8497 {
8501 }
8504 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8505 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8506 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8508 static int
8511 {
8513 }
8516 /* Vectorizer cost model target hooks. */
8518 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8519 static int
8521 tree vectype,
8523 {
8532 {
8581 }
8582 }
8584 /* Implement targetm.vectorize.add_stmt_cost. */
8585 static unsigned
8589 {
8594 {
8599 /* Statements in an inner loop relative to the loop being
8600 vectorized are weighted more heavily. The value here is
8601 arbitrary and could potentially be improved with analysis. */
8607 }
8610 }
8614 /* Parse the TO_PARSE string and put the architecture struct that it
8615 selects into RES and the architectural features into ISA_FLAGS.
8616 Return an aarch64_parse_opt_result describing the parse result.
8617 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8619 static enum aarch64_parse_opt_result
8622 {
8634 else
8641 /* Loop through the list of supported ARCHes to find a match. */
8643 {
8645 {
8649 {
8650 /* TO_PARSE string contains at least one extension. */
8651 enum aarch64_parse_opt_result ext_res
8656 }
8657 /* Extension parsing was successful. Confirm the result
8658 arch and ISA flags. */
8662 }
8663 }
8665 /* ARCH name not found in list. */
8667 }
8669 /* Parse the TO_PARSE string and put the result tuning in RES and the
8670 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8671 describing the parse result. If there is an error parsing, RES and
8672 ISA_FLAGS are left unchanged. */
8674 static enum aarch64_parse_opt_result
8677 {
8689 else
8696 /* Loop through the list of supported CPUs to find a match. */
8698 {
8700 {
8705 {
8706 /* TO_PARSE string contains at least one extension. */
8707 enum aarch64_parse_opt_result ext_res
8712 }
8713 /* Extension parsing was successfull. Confirm the result
8714 cpu and ISA flags. */
8718 }
8719 }
8721 /* CPU name not found in list. */
8723 }
8725 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8726 Return an aarch64_parse_opt_result describing the parse result.
8727 If the parsing fails the RES does not change. */
8729 static enum aarch64_parse_opt_result
8731 {
8737 /* Loop through the list of supported CPUs to find a match. */
8739 {
8741 {
8744 }
8745 }
8747 /* CPU name not found in list. */
8749 }
8751 /* Parse TOKEN, which has length LENGTH to see if it is an option
8752 described in FLAG. If it is, return the index bit for that fusion type.
8753 If not, error (printing OPTION_NAME) and return zero. */
8755 static unsigned int
8760 {
8762 {
8766 }
8770 }
8772 /* Parse OPTION which is a comma-separated list of flags to enable.
8773 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8774 default state we inherit from the CPU tuning structures. OPTION_NAME
8775 gives the top-level option we are parsing in the -moverride string,
8776 for use in error messages. */
8778 static unsigned int
8783 {
8790 {
8793 token_length,
8794 flags,
8795 option_name);
8796 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8797 in the token stream, reset the supported operations. So:
8799 adrp+add.cmp+branch.none.adrp+add
8801 would have the result of turning on only adrp+add fusion. */
8807 }
8809 /* We ended with a comma, print something. */
8811 {
8814 }
8816 /* We still have one more token to parse. */
8819 token_length,
8820 flags,
8821 option_name);
8827 }
8829 /* Support for overriding instruction fusion. */
8831 static void
8834 {
8836 aarch64_fusible_pairs,
8839 }
8841 /* Support for overriding other tuning flags. */
8843 static void
8846 {
8847 tune->extra_tuning_flags
8849 aarch64_tuning_flags,
8852 }
8854 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8855 we understand. If it is, extract the option string and handoff to
8856 the appropriate function. */
8858 void
8862 {
8868 {
8871 }
8873 /* Get the length of the option name. */
8875 /* Skip the '=' to get to the option string. */
8876 option_part++;
8879 {
8881 {
8884 }
8885 }
8889 }
8891 /* A checking mechanism for the implementation of the tls size. */
8893 static void
8895 {
8900 {
8902 /* Both the default and maximum TLS size allowed under tiny is 1M which
8903 needs two instructions to address, so we clamp the size to 24. */
8908 /* The maximum TLS size allowed under small is 4G. */
8913 /* The maximum TLS size allowed under large is 16E.
8914 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8920 }
8923 }
8925 /* Parse STRING looking for options in the format:
8926 string :: option:string
8927 option :: name=substring
8928 name :: {a-z}
8929 substring :: defined by option. */
8931 static void
8934 {
8945 {
8947 /* Make this substring look like a string. */
8951 }
8953 /* One last option to parse. */
8956 }
8959 static void
8961 {
8962 /* The logic here is that if we are disabling all frame pointer generation
8963 then we do not need to disable leaf frame pointer generation as a
8964 separate operation. But if we are *only* disabling leaf frame pointer
8965 generation then we set flag_omit_frame_pointer to true, but in
8966 aarch64_frame_pointer_required we return false only for leaf functions.
8968 PR 70044: We have to be careful about being called multiple times for the
8969 same function. Once we have decided to set flag_omit_frame_pointer just
8970 so that we can omit leaf frame pointers, we must then not interpret a
8971 second call as meaning that all frame pointer generation should be
8972 omitted. We do this by setting flag_omit_frame_pointer to a special,
8973 non-zero value. */
8982 /* If not optimizing for size, set the default
8983 alignment to what the target wants. */
8985 {
8992 }
8994 /* We default to no pc-relative literal loads. */
8998 /* If -mpc-relative-literal-loads is set on the command line, this
8999 implies that the user asked for PC relative literal loads. */
9003 /* In the tiny memory model it makes no sense to disallow PC relative
9004 literal pool loads. */
9009 /* When enabling the lower precision Newton series for the square root, also
9010 enable it for the reciprocal square root, since the latter is an
9011 intermediary step for the former. */
9014 }
9016 /* 'Unpack' up the internal tuning structs and update the options
9017 in OPTS. The caller must have set up selected_tune and selected_arch
9018 as all the other target-specific codegen decisions are
9019 derived from them. */
9021 void
9023 {
9026 /* Make a copy of the tuning parameters attached to the core, which
9027 we may later overwrite. */
9035 /* This target defaults to strict volatile bitfields. */
9044 {
9056 }
9058 /* We don't mind passing in global_options_set here as we don't use
9059 the *options_set structs anyway. */
9061 queue_depth,
9065 /* Set up parameters to be used in prefetching algorithm. Do not
9066 override the defaults unless we are tuning for a core we have
9067 researched values for. */
9089 /* Enable sw prefetching at specified optimization level for
9090 CPUS that have prefetch. Lower optimization level threshold by 1
9091 when profiling is enabled. */
9099 }
9101 /* Print a hint with a suggestion for a core or architecture name that
9102 most closely resembles what the user passed in STR. ARCH is true if
9103 the user is asking for an architecture name. ARCH is false if the user
9104 is asking for a core name. */
9106 static void
9108 {
9119 }
9121 /* Print a hint with a suggestion for a core name that most closely resembles
9122 what the user passed in STR. */
9126 {
9128 }
9130 /* Print a hint with a suggestion for an architecture name that most closely
9131 resembles what the user passed in STR. */
9135 {
9137 }
9139 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
9140 specified in STR and throw errors if appropriate. Put the results if
9141 they are valid in RES and ISA_FLAGS. Return whether the option is
9142 valid. */
9144 static bool
9147 {
9148 enum aarch64_parse_opt_result parse_res
9155 {
9168 }
9171 }
9173 /* Validate a command-line -march option. Parse the arch and extensions
9174 (if any) specified in STR and throw errors if appropriate. Put the
9175 results, if they are valid, in RES and ISA_FLAGS. Return whether the
9176 option is valid. */
9178 static bool
9181 {
9182 enum aarch64_parse_opt_result parse_res
9189 {
9202 }
9205 }
9207 /* Validate a command-line -mtune option. Parse the cpu
9208 specified in STR and throw errors if appropriate. Put the
9209 result, if it is valid, in RES. Return whether the option is
9210 valid. */
9212 static bool
9214 {
9215 enum aarch64_parse_opt_result parse_res
9222 {
9232 }
9234 }
9236 /* Return the CPU corresponding to the enum CPU.
9237 If it doesn't specify a cpu, return the default. */
9241 {
9245 /* The & 0x3f is to extract the bottom 6 bits that encode the
9246 default cpu as selected by the --with-cpu GCC configure option
9247 in config.gcc.
9248 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
9249 flags mechanism should be reworked to make it more sane. */
9251 }
9253 /* Return the architecture corresponding to the enum ARCH.
9254 If it doesn't specify a valid architecture, return the default. */
9258 {
9265 }
9267 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
9268 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
9269 tuning structs. In particular it must set selected_tune and
9270 aarch64_isa_flags that define the available ISA features and tuning
9271 decisions. It must also set selected_arch as this will be used to
9272 output the .arch asm tags for each function. */
9274 static void
9276 {
9289 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
9290 If either of -march or -mtune is given, they override their
9291 respective component of -mcpu. */
9303 /* If the user did not specify a processor, choose the default
9304 one for them. This will be the CPU set during configuration using
9305 --with-cpu, otherwise it is "generic". */
9307 {
9309 {
9313 }
9314 else
9315 {
9316 /* Get default configure-time CPU. */
9319 }
9323 }
9324 /* If both -mcpu and -march are specified check that they are architecturally
9325 compatible, warn if they're not and prefer the -march ISA flags. */
9327 {
9329 {
9333 }
9338 }
9339 else
9340 {
9341 /* -mcpu but no -march. */
9348 }
9350 /* Set the arch as well as we will need it when outputing
9351 the .arch directive in assembly. */
9353 {
9356 }
9361 #ifndef HAVE_AS_MABI_OPTION
9362 /* The compiler may have been configured with 2.23.* binutils, which does
9363 not have support for ILP32. */
9366 #endif
9371 /* Make sure we properly set up the explicit options. */
9382 /* Save these options as the default ones in case we push and pop them later
9383 while processing functions with potential target attributes. */
9384 target_option_default_node = target_option_current_node
9386 }
9388 /* Implement targetm.override_options_after_change. */
9390 static void
9392 {
9394 }
9398 {
9402 }
9404 void
9406 {
9408 }
9410 /* A checking mechanism for the implementation of the various code models. */
9411 static void
9413 {
9415 {
9417 {
9422 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9424 ? AARCH64_CMODEL_SMALL_PIC
9426 #else
9428 #endif
9436 }
9437 }
9438 else
9440 }
9442 /* Implement TARGET_OPTION_SAVE. */
9444 static void
9446 {
9448 }
9450 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9451 using the information saved in PTR. */
9453 static void
9455 {
9463 }
9465 /* Implement TARGET_OPTION_PRINT. */
9467 static void
9469 {
9480 }
9484 void
9486 {
9488 }
9490 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9491 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9492 make sure optab availability predicates are recomputed when necessary. */
9494 void
9496 {
9501 else
9503 }
9505 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9506 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9507 of the function, if such exists. This function may be called multiple
9508 times on a single function so use aarch64_previous_fndecl to avoid
9509 setting up identical state. */
9511 static void
9513 {
9517 tree old_tree = (aarch64_previous_fndecl
9523 /* If current function has no attributes but the previous one did,
9524 use the default node. */
9528 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9529 the default have been handled by aarch64_save_restore_target_globals from
9530 aarch64_pragma_target_parse. */
9536 /* First set the target options. */
9540 }
9542 /* Enum describing the various ways we can handle attributes.
9543 In many cases we can reuse the generic option handling machinery. */
9545 enum aarch64_attr_opt_type
9546 {
9550 aarch64_attr_custom /* Attribute requires a custom handling function. */
9551 };
9553 /* All the information needed to handle a target attribute.
9554 NAME is the name of the attribute.
9555 ATTR_TYPE specifies the type of behavior of the attribute as described
9556 in the definition of enum aarch64_attr_opt_type.
9557 ALLOW_NEG is true if the attribute supports a "no-" form.
9558 HANDLER is the function that takes the attribute string and whether
9559 it is a pragma or attribute and handles the option. It is needed only
9560 when the ATTR_TYPE is aarch64_attr_custom.
9561 OPT_NUM is the enum specifying the option that the attribute modifies.
9562 This is needed for attributes that mirror the behavior of a command-line
9563 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9564 aarch64_attr_enum. */
9566 struct aarch64_attribute_info
9567 {
9573 };
9575 /* Handle the ARCH_STR argument to the arch= target attribute.
9576 PRAGMA_OR_ATTR is used in potential error messages. */
9578 static bool
9580 {
9582 enum aarch64_parse_opt_result parse_res
9586 {
9591 }
9594 {
9608 }
9611 }
9613 /* Handle the argument CPU_STR to the cpu= target attribute.
9614 PRAGMA_OR_ATTR is used in potential error messages. */
9616 static bool
9618 {
9620 enum aarch64_parse_opt_result parse_res
9624 {
9632 }
9635 {
9649 }
9652 }
9654 /* Handle the argument STR to the tune= target attribute.
9655 PRAGMA_OR_ATTR is used in potential error messages. */
9657 static bool
9659 {
9661 enum aarch64_parse_opt_result parse_res
9665 {
9670 }
9673 {
9680 }
9683 }
9685 /* Parse an architecture extensions target attribute string specified in STR.
9686 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9687 if successful. Update aarch64_isa_flags to reflect the ISA features
9688 modified.
9689 PRAGMA_OR_ATTR is used in potential error messages. */
9691 static bool
9693 {
9697 /* We allow "+nothing" in the beginning to clear out all architectural
9698 features if the user wants to handpick specific features. */
9700 {
9703 }
9708 {
9711 }
9714 {
9727 }
9730 }
9732 /* The target attributes that we support. On top of these we also support just
9733 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9734 handled explicitly in aarch64_process_one_target_attr. */
9737 {
9739 OPT_mgeneral_regs_only },
9741 OPT_mfix_cortex_a53_835769 },
9743 OPT_mfix_cortex_a53_843419 },
9747 OPT_momit_leaf_frame_pointer },
9750 OPT_march_ },
9753 OPT_mtune_ },
9755 OPT_msign_return_address_ },
9757 };
9759 /* Parse ARG_STR which contains the definition of one target attribute.
9760 Show appropriate errors if any or return true if the attribute is valid.
9761 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9762 we're processing a target attribute or pragma. */
9764 static bool
9766 {
9772 {
9775 }
9780 /* Skip leading whitespace. */
9782 str_to_check++;
9784 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9785 It is easier to detect and handle it explicitly here rather than going
9786 through the machinery for the rest of the target attributes in this
9787 function. */
9792 {
9795 }
9798 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9799 and point ARG to "foo". */
9801 {
9803 arg++;
9804 }
9808 {
9809 /* If the names don't match up, or the user has given an argument
9810 to an attribute that doesn't accept one, or didn't give an argument
9811 to an attribute that expects one, fail to match. */
9820 {
9824 }
9826 /* If the name matches but the attribute does not allow "no-" versions
9827 then we can't match. */
9829 {
9833 }
9836 {
9837 /* Has a custom handler registered.
9838 For example, cpu=, arch=, tune=. */
9845 /* Either set or unset a boolean option. */
9847 {
9855 }
9856 /* Set or unset a bit in the target_flags. aarch64_handle_option
9857 should know what mask to apply given the option number. */
9859 {
9861 /* We only need to specify the option number.
9862 aarch64_handle_option will know which mask to apply. */
9868 }
9869 /* Use the option setting machinery to set an option to an enum. */
9871 {
9878 {
9881 global_dc);
9882 }
9883 else
9884 {
9887 }
9889 }
9892 }
9893 }
9895 /* If we reached here we either have found an attribute and validated
9896 it or didn't match any. If we matched an attribute but its arguments
9897 were malformed we will have returned false already. */
9899 }
9901 /* Count how many times the character C appears in
9902 NULL-terminated string STR. */
9904 static unsigned int
9906 {
9909 {
9911 res++;
9913 str++;
9914 }
9917 }
9919 /* Parse the tree in ARGS that contains the target attribute information
9920 and update the global target options space. PRAGMA_OR_ATTR is a string
9921 to be used in error messages, specifying whether this is processing
9922 a target attribute or a target pragma. */
9924 bool
9926 {
9928 {
9929 do
9930 {
9933 {
9936 }
9941 }
9944 {
9947 }
9954 {
9957 }
9959 /* Used to catch empty spaces between commas i.e.
9960 attribute ((target ("attr1,,attr2"))). */
9963 /* Handle multiple target attributes separated by ','. */
9968 {
9969 num_attrs++;
9971 {
9974 }
9977 }
9980 {
9984 }
9987 }
9989 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9990 process attribute ((target ("..."))). */
9992 static bool
9994 {
9997 tree old_optimize;
10001 /* If what we're processing is the current pragma string then the
10002 target option node is already stored in target_option_current_node
10003 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
10004 having to re-parse the string. This is especially useful to keep
10005 arm_neon.h compile times down since that header contains a lot
10006 of intrinsics enclosed in pragmas. */
10008 {
10011 }
10017 /* If the function changed the optimization levels as well as setting
10018 target options, start with the optimizations specified. */
10023 /* Save the current target options to restore at the end. */
10026 /* If fndecl already has some target attributes applied to it, unpack
10027 them so that we add this attribute on top of them, rather than
10028 overwriting them. */
10030 {
10036 }
10037 else
10044 /* Set up any additional state. */
10046 {
10048 /* Initialize SIMD builtins if we haven't already.
10049 Set current_target_pragma to NULL for the duration so that
10050 the builtin initialization code doesn't try to tag the functions
10051 being built with the attributes specified by any current pragma, thus
10052 going into an infinite recursion. */
10054 {
10059 }
10061 }
10062 else
10068 {
10073 }
10081 }
10083 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
10084 tri-bool options (yes, no, don't care) and the default value is
10085 DEF, determine whether to reject inlining. */
10087 static bool
10090 {
10091 /* If the callee doesn't care, always allow inlining. */
10095 /* If the caller doesn't care, always allow inlining. */
10099 /* Otherwise, allow inlining if either the callee and caller values
10100 agree, or if the callee is using the default value. */
10102 }
10104 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
10105 to inline CALLEE into CALLER based on target-specific info.
10106 Make sure that the caller and callee have compatible architectural
10107 features. Then go through the other possible target attributes
10108 and see if they can block inlining. Try not to reject always_inline
10109 callees unless they are incompatible architecturally. */
10111 static bool
10113 {
10117 /* If callee has no option attributes, then it is ok to inline. */
10128 /* Callee's ISA flags should be a subset of the caller's. */
10133 /* Allow non-strict aligned functions inlining into strict
10134 aligned ones. */
10144 /* If the architectural features match up and the callee is always_inline
10145 then the other attributes don't matter. */
10157 /* Honour explicit requests to workaround errata. */
10170 /* If the user explicitly specified -momit-leaf-frame-pointer for the
10171 caller and calle and they don't match up, reject inlining. */
10178 /* If the callee has specific tuning overrides, respect them. */
10183 /* If the user specified tuning override strings for the
10184 caller and callee and they don't match up, reject inlining.
10185 We just do a string compare here, we don't analyze the meaning
10186 of the string, as it would be too costly for little gain. */
10194 }
10196 /* Return true if SYMBOL_REF X binds locally. */
10198 static bool
10200 {
10204 }
10206 /* Return true if SYMBOL_REF X is thread local */
10207 static bool
10209 {
10217 }
10219 /* Classify a TLS symbol into one of the TLS kinds. */
10220 enum aarch64_symbol_type
10222 {
10226 {
10233 {
10239 }
10250 else
10259 }
10260 }
10262 /* Return the method that should be used to access SYMBOL_REF or
10263 LABEL_REF X. */
10265 enum aarch64_symbol_type
10267 {
10269 {
10271 {
10286 }
10287 }
10290 {
10295 {
10297 /* When we retrieve symbol + offset address, we have to make sure
10298 the offset does not cause overflow of the final address. But
10299 we have no way of knowing the address of symbol at compile time
10300 so we can't accurately say if the distance between the PC and
10301 symbol + offset is outside the addressible range of +/-1M in the
10302 TINY code model. So we rely on images not being greater than
10303 1M and cap the offset at 1M and anything beyond 1M will have to
10304 be loaded using an alternative mechanism. Furthermore if the
10305 symbol is a weak reference to something that isn't known to
10306 resolve to a symbol in this module, then force to memory. */
10314 /* Same reasoning as the tiny code model, but the offset cap here is
10315 4G. */
10336 /* This is alright even in PIC code as the constant
10337 pool reference is always PC relative and within
10338 the same translation unit. */
10341 else
10346 }
10347 }
10349 /* By default push everything into the constant pool. */
10351 }
10353 bool
10355 {
10357 }
10359 bool
10361 {
10369 }
10371 /* Return true if X holds either a quarter-precision or
10372 floating-point +0.0 constant. */
10373 static bool
10375 {
10379 /* This call determines which constants can be used in mov<mode>
10380 as integer moves instead of constant loads. */
10385 }
10387 static bool
10389 {
10390 /* Do not allow vector struct mode constants. We could support
10391 0 and -1 easily, but they need support in aarch64-simd.md. */
10395 /* For these cases we never want to use a literal load.
10396 As such we have to prevent the compiler from forcing these
10397 to memory. */
10410 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
10411 so spilling them is better than rematerialization. */
10416 }
10418 rtx
10420 {
10426 /* Can return in any reg. */
10429 }
10431 /* On AAPCS systems, this is the "struct __va_list". */
10434 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10435 Return the type to use as __builtin_va_list.
10437 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10439 struct __va_list
10440 {
10441 void *__stack;
10442 void *__gr_top;
10443 void *__vr_top;
10444 int __gr_offs;
10445 int __vr_offs;
10446 }; */
10448 static tree
10450 {
10451 tree va_list_name;
10454 /* Create the type. */
10456 /* Give it the required name. */
10458 TYPE_DECL,
10460 va_list_type);
10465 /* Create the fields. */
10468 ptr_type_node);
10471 ptr_type_node);
10474 ptr_type_node);
10477 integer_type_node);
10480 integer_type_node);
10482 /* Tell tree-stdarg pass about our internal offset fields.
10483 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10484 purpose to identify whether the code is updating va_list internal
10485 offset fields through irregular way. */
10507 /* Compute its layout. */
10511 }
10513 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10514 static void
10516 {
10520 tree t;
10534 {
10537 }
10546 NULL_TREE);
10548 NULL_TREE);
10550 NULL_TREE);
10552 NULL_TREE);
10554 NULL_TREE);
10556 /* Emit code to initialize STACK, which points to the next varargs stack
10557 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10558 by named arguments. STACK is 8-byte aligned. */
10565 /* Emit code to initialize GRTOP, the top of the GR save area.
10566 virtual_incoming_args_rtx should have been 16 byte aligned. */
10571 /* Emit code to initialize VRTOP, the top of the VR save area.
10572 This address is gr_save_area_bytes below GRTOP, rounded
10573 down to the next 16-byte boundary. */
10583 /* Emit code to initialize GROFF, the offset from GRTOP of the
10584 next GPR argument. */
10589 /* Likewise emit code to initialize VROFF, the offset from FTOP
10590 of the next VR argument. */
10594 }
10596 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10598 static tree
10601 {
10602 tree addr;
10608 machine_mode mode;
10635 type,
10639 {
10640 /* TYPE passed in fp/simd registers. */
10652 {
10655 }
10658 {
10660 }
10661 }
10662 else
10663 {
10664 /* TYPE passed in general registers. */
10677 {
10679 }
10680 }
10682 /* Get a local temporary for the field value. */
10685 /* Emit code to branch if off >= 0. */
10691 {
10692 /* Emit: offs = (offs + 15) & -16. */
10698 }
10699 else
10702 /* Update ap.__[g|v]r_offs */
10707 /* String up. */
10711 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10716 /* String up: make sure the assignment happens before the use. */
10720 /* Prepare the trees handling the argument that is passed on the stack;
10721 the top level node will store in ON_STACK. */
10724 {
10725 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10733 }
10734 else
10736 /* Advance ap.__stack */
10744 /* String up roundup and advance. */
10747 /* String up with arg */
10749 /* Big-endianness related address adjustment. */
10752 {
10756 }
10761 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10771 {
10772 /* type ha; // treat as "struct {ftype field[n];}"
10773 ... [computing offs]
10774 for (i = 0; i <nregs; ++i, offs += 16)
10775 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10776 return ha; */
10780 /* Declare a local variable. */
10784 /* Establish the base type. */
10786 {
10805 {
10809 }
10813 }
10815 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10823 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10825 {
10835 }
10839 }
10849 }
10851 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10853 static void
10857 {
10859 CUMULATIVE_ARGS local_cum;
10863 /* The caller has advanced CUM up to, but not beyond, the last named
10864 argument. Advance a local copy of CUM past the last "real" named
10865 argument, to find out how many registers are left over. */
10869 /* Found out how many registers we need to save.
10870 Honor tree-stdvar analysis results. */
10879 {
10882 }
10885 {
10887 {
10890 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10898 }
10900 {
10901 /* We can't use move_block_from_reg, because it will use
10902 the wrong mode, storing D regs only. */
10906 /* Set OFF to the offset from virtual_incoming_args_rtx of
10907 the first vector register. The VR save area lies below
10908 the GR one, and is aligned to 16 bytes. */
10915 {
10923 }
10924 }
10925 }
10927 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10928 any complication of having crtl->args.pretend_args_size changed. */
10933 }
10935 static void
10937 {
10940 {
10942 {
10945 }
10946 }
10947 }
10949 /* Walk down the type tree of TYPE counting consecutive base elements.
10950 If *MODEP is VOIDmode, then set it to the first valid floating point
10951 type. If a non-floating point type is found, or if a floating point
10952 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10953 otherwise return the count in the sub-tree. */
10954 static int
10956 {
10957 machine_mode mode;
10958 HOST_WIDE_INT size;
10961 {
10991 /* Use V2SImode and V4SImode as representatives of all 64-bit
10992 and 128-bit vector types. */
10995 {
11004 }
11009 /* Vector modes are considered to be opaque: two vectors are
11010 equivalent for the purposes of being homogeneous aggregates
11011 if they are the same size. */
11018 {
11022 /* Can't handle incomplete types nor sizes that are not
11023 fixed. */
11030 || !index
11041 /* There must be no padding. */
11046 }
11049 {
11052 tree field;
11054 /* Can't handle incomplete types nor sizes that are not
11055 fixed. */
11061 {
11069 }
11071 /* There must be no padding. */
11076 }
11080 {
11081 /* These aren't very interesting except in a degenerate case. */
11084 tree field;
11086 /* Can't handle incomplete types nor sizes that are not
11087 fixed. */
11093 {
11101 }
11103 /* There must be no padding. */
11108 }
11112 }
11115 }
11117 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
11118 type as described in AAPCS64 \S 4.1.2.
11120 See the comment above aarch64_composite_type_p for the notes on MODE. */
11122 static bool
11124 machine_mode mode)
11125 {
11135 }
11137 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
11138 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
11139 array types. The C99 floating-point complex types are also considered
11140 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
11141 types, which are GCC extensions and out of the scope of AAPCS64, are
11142 treated as composite types here as well.
11144 Note that MODE itself is not sufficient in determining whether a type
11145 is such a composite type or not. This is because
11146 stor-layout.c:compute_record_mode may have already changed the MODE
11147 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
11148 structure with only one field may have its MODE set to the mode of the
11149 field. Also an integer mode whose size matches the size of the
11150 RECORD_TYPE type may be used to substitute the original mode
11151 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
11152 solely relied on. */
11154 static bool
11156 machine_mode mode)
11157 {
11170 }
11172 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
11173 shall be passed or returned in simd/fp register(s) (providing these
11174 parameter passing registers are available).
11176 Upon successful return, *COUNT returns the number of needed registers,
11177 *BASE_MODE returns the mode of the individual register and when IS_HAF
11178 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
11179 floating-point aggregate or a homogeneous short-vector aggregate. */
11181 static bool
11183 const_tree type,
11187 {
11195 {
11198 }
11200 {
11204 }
11206 {
11210 {
11213 }
11214 else
11216 }
11217 else
11222 }
11224 /* Implement TARGET_STRUCT_VALUE_RTX. */
11226 static rtx
11229 {
11231 }
11233 /* Implements target hook vector_mode_supported_p. */
11234 static bool
11236 {
11248 }
11250 /* Return appropriate SIMD container
11251 for MODE within a vector of WIDTH bits. */
11252 static machine_mode
11254 {
11257 {
11260 {
11277 }
11278 else
11280 {
11293 }
11294 }
11296 }
11298 /* Return 128-bit container as the preferred SIMD mode for MODE. */
11299 static machine_mode
11301 {
11303 }
11305 /* Return the bitmask of possible vector sizes for the vectorizer
11306 to iterate over. */
11307 static unsigned int
11309 {
11311 }
11313 /* Implement TARGET_MANGLE_TYPE. */
11317 {
11318 /* The AArch64 ABI documents say that "__va_list" has to be
11319 managled as if it is in the "std" namespace. */
11323 /* Half-precision float. */
11327 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
11328 builtin types. */
11332 /* Use the default mangling. */
11334 }
11336 /* Find the first rtx_insn before insn that will generate an assembly
11337 instruction. */
11341 {
11345 do
11346 {
11348 }
11352 }
11354 static bool
11356 {
11358 /* A number of these may be AArch32 only. */
11363 };
11366 {
11369 }
11372 }
11374 /* Check if there is a register dependency between a load and the insn
11375 for which we hold recog_data. */
11377 static bool
11379 {
11380 rtx load_reg;
11390 {
11396 }
11398 }
11401 /* When working around the Cortex-A53 erratum 835769,
11402 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
11403 instruction and has a preceding memory instruction such that a NOP
11404 should be inserted between them. */
11406 bool
11408 {
11411 rtx body;
11424 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11425 Restore recog state to INSN to avoid state corruption. */
11433 /* If the previous insn is a memory op and there is no dependency between
11434 it and the DImode madd, emit a NOP between them. If body is NULL then we
11435 have a complex memory operation, probably a load/store pair.
11436 Be conservative for now and emit a NOP. */
11443 }
11446 /* Implement FINAL_PRESCAN_INSN. */
11448 void
11450 {
11453 }
11456 /* Return the equivalent letter for size. */
11457 static char
11459 {
11461 {
11467 }
11468 }
11470 /* Return true iff x is a uniform vector of floating-point
11471 constants, and the constant can be represented in
11472 quarter-precision form. Note, as aarch64_float_const_representable
11473 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11474 static bool
11476 {
11477 rtx elt;
11481 }
11483 /* Return true for valid and false for invalid. */
11484 bool
11487 {
11488 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11489 matches = 1; \
11490 for (i = 0; i < idx; i += (STRIDE)) \
11491 if (!(TEST)) \
11492 matches = 0; \
11493 if (matches) \
11494 { \
11495 immtype = (CLASS); \
11496 elsize = (ELSIZE); \
11497 eshift = (SHIFT); \
11498 emvn = (NEG); \
11499 break; \
11500 }
11510 {
11516 {
11518 scalar_float_mode elt_mode
11525 }
11528 }
11530 /* Splat vector constant out into a byte vector. */
11532 {
11533 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11534 it must be laid out in the vector register in reverse order. */
11542 {
11545 }
11547 }
11549 /* Sanity check. */
11552 do
11553 {
11602 }
11609 {
11619 /* Un-invert bytes of recognized vector, if necessary. */
11625 {
11626 /* FIXME: Broken on 32-bit H_W_I hosts. */
11635 }
11636 else
11637 {
11641 /* Construct 'abcdefgh' because the assembler cannot handle
11642 generic constants. */
11647 }
11648 }
11651 #undef CHECK
11652 }
11654 /* Check of immediate shift constants are within range. */
11655 bool
11657 {
11661 else
11663 }
11665 /* Return true if X is a uniform vector where all elements
11666 are either the floating-point constant 0.0 or the
11667 integer constant 0. */
11668 bool
11670 {
11672 }
11675 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11676 operation of width WIDTH at bit position POS. */
11678 rtx
11680 {
11684 unsigned HOST_WIDE_INT mask
11687 }
11689 bool
11691 {
11704 }
11706 /* Return a const_int vector of VAL. */
11707 rtx
11709 {
11720 }
11722 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11724 bool
11726 {
11727 machine_mode vmode;
11732 }
11734 /* Construct and return a PARALLEL RTX vector with elements numbering the
11735 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11736 the vector - from the perspective of the architecture. This does not
11737 line up with GCC's perspective on lane numbers, so we end up with
11738 different masks depending on our target endian-ness. The diagram
11739 below may help. We must draw the distinction when building masks
11740 which select one half of the vector. An instruction selecting
11741 architectural low-lanes for a big-endian target, must be described using
11742 a mask selecting GCC high-lanes.
11744 Big-Endian Little-Endian
11746 GCC 0 1 2 3 3 2 1 0
11747 | x | x | x | x | | x | x | x | x |
11748 Architecture 3 2 1 0 3 2 1 0
11750 Low Mask: { 2, 3 } { 0, 1 }
11751 High Mask: { 0, 1 } { 2, 3 }
11752 */
11754 rtx
11756 {
11762 rtx t1;
11767 else
11775 }
11777 /* Check OP for validity as a PARALLEL RTX vector with elements
11778 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11779 from the perspective of the architecture. See the diagram above
11780 aarch64_simd_vect_par_cnst_half for more details. */
11782 bool
11785 {
11798 {
11805 }
11807 }
11809 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11810 HIGH (exclusive). */
11811 void
11813 const_tree exp)
11814 {
11815 HOST_WIDE_INT lane;
11820 {
11823 else
11825 }
11826 }
11828 /* Return TRUE if OP is a valid vector addressing mode. */
11829 bool
11831 {
11834 }
11836 /* Emit a register copy from operand to operand, taking care not to
11837 early-clobber source registers in the process.
11839 COUNT is the number of components into which the copy needs to be
11840 decomposed. */
11841 void
11844 {
11854 else
11858 }
11860 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11861 one of VSTRUCT modes: OI, CI, or XI. */
11862 int
11864 {
11866 }
11868 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11869 alignment of a vector to 128 bits. */
11870 static HOST_WIDE_INT
11872 {
11875 }
11877 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11878 static bool
11880 {
11884 /* We guarantee alignment for vectors up to 128-bits. */
11889 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11891 }
11893 /* Return true if the vector misalignment factor is supported by the
11894 target. */
11895 static bool
11899 {
11901 {
11902 /* Return if movmisalign pattern is not supported for this mode. */
11906 /* Misalignment factor is unknown at compile time. */
11909 }
11911 is_packed);
11912 }
11914 /* If VALS is a vector constant that can be loaded into a register
11915 using DUP, generate instructions to do so and return an RTX to
11916 assign to the register. Otherwise return NULL_RTX. */
11917 static rtx
11919 {
11922 rtx x;
11927 /* We can load this constant by using DUP and a constant in a
11928 single ARM register. This will be cheaper than a vector
11929 load. */
11932 }
11935 /* Generate code to load VALS, which is a PARALLEL containing only
11936 constants (for vec_init) or CONST_VECTOR, efficiently into a
11937 register. Returns an RTX to copy into the register, or NULL_RTX
11938 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11939 static rtx
11941 {
11943 rtx const_dup;
11952 {
11953 /* A CONST_VECTOR must contain only CONST_INTs and
11954 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11955 Only store valid constants in a CONST_VECTOR. */
11957 {
11960 n_const++;
11961 }
11964 }
11965 else
11970 /* Load using MOVI/MVNI. */
11973 /* Loaded using DUP. */
11976 /* Load from constant pool. We can not take advantage of single-cycle
11977 LD1 because we need a PC-relative addressing mode. */
11979 else
11980 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11981 We can not construct an initializer. */
11983 }
11985 /* Expand a vector initialisation sequence, such that TARGET is
11986 initialised to contain VALS. */
11988 void
11990 {
11993 /* The number of vector elements. */
11995 /* The number of vector elements which are not constant. */
11998 /* The first element of vals. */
12002 /* Count the number of variable elements to initialise. */
12004 {
12008 else
12012 }
12014 /* No variable elements, hand off to aarch64_simd_make_constant which knows
12015 how best to handle this. */
12017 {
12020 {
12023 }
12024 }
12026 /* Splat a single non-constant element if we can. */
12028 {
12032 }
12037 /* If there are only variable elements, try to optimize
12038 the insertion using dup for the most common element
12039 followed by insertions. */
12041 /* The algorithm will fill matches[*][0] with the earliest matching element,
12042 and matches[X][1] with the count of duplicate elements (if X is the
12043 earliest element which has duplicates). */
12046 {
12049 {
12051 {
12053 {
12057 }
12058 }
12059 }
12064 {
12067 }
12069 /* Create a duplicate of the most common element. */
12073 /* Insert the rest. */
12075 {
12081 }
12083 }
12085 /* Initialise a vector which is part-variable. We want to first try
12086 to build those lanes which are constant in the most efficient way we
12087 can. */
12089 {
12092 /* Load constant part of vector. We really don't care what goes into the
12093 parts we will overwrite, but we're more likely to be able to load the
12094 constant efficiently if it has fewer, larger, repeating parts
12095 (see aarch64_simd_valid_immediate). */
12097 {
12103 {
12104 /* Look in the copied vector, as more elements are const. */
12107 {
12110 }
12111 }
12113 }
12115 }
12117 /* Insert the variable lanes directly. */
12119 {
12125 }
12126 }
12128 static unsigned HOST_WIDE_INT
12130 {
12131 return
12132 (!SHIFT_COUNT_TRUNCATED
12135 }
12137 /* Select a format to encode pointers in exception handling data. */
12138 int
12140 {
12143 {
12149 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
12150 for everything. */
12154 /* No assumptions here. 8-byte relocs required. */
12157 }
12159 }
12161 /* The last .arch and .tune assembly strings that we printed. */
12165 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
12166 by the function fndecl. */
12168 void
12170 tree fndecl)
12171 {
12177 else
12188 /* Only update the assembler .arch string if it is distinct from the last
12189 such string we printed. */
12192 {
12195 }
12197 /* Print the cpu name we're tuning for in the comments, might be
12198 useful to readers of the generated asm. Do it only when it changes
12199 from function to function and verbose assembly is requested. */
12204 {
12208 }
12210 /* Don't forget the type directive for ELF. */
12213 }
12215 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
12217 static void
12219 {
12236 }
12238 /* Emit load exclusive. */
12240 static void
12243 {
12247 {
12254 }
12257 }
12259 /* Emit store exclusive. */
12261 static void
12264 {
12268 {
12275 }
12278 }
12280 /* Mark the previous jump instruction as unlikely. */
12282 static void
12284 {
12287 }
12289 /* Expand a compare and swap pattern. */
12291 void
12293 {
12298 gen_cas_fn gen;
12300 {
12301 gen_aarch64_compare_and_swapqi,
12302 gen_aarch64_compare_and_swaphi,
12303 gen_aarch64_compare_and_swapsi,
12304 gen_aarch64_compare_and_swapdi
12305 };
12307 {
12308 gen_aarch64_compare_and_swapqi_lse,
12309 gen_aarch64_compare_and_swaphi_lse,
12310 gen_aarch64_compare_and_swapsi_lse,
12311 gen_aarch64_compare_and_swapdi_lse
12312 };
12325 /* Normally the succ memory model must be stronger than fail, but in the
12326 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
12327 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
12334 {
12337 /* For short modes, we're going to perform the comparison in SImode,
12338 so do the zero-extension now. */
12342 /* Fall through. */
12346 /* Force the value into a register if needed. */
12353 }
12356 {
12363 }
12366 else
12377 }
12379 /* Test whether the target supports using a atomic load-operate instruction.
12380 CODE is the operation and AFTER is TRUE if the data in memory after the
12381 operation should be returned and FALSE if the data before the operation
12382 should be returned. Returns FALSE if the operation isn't supported by the
12383 architecture. */
12385 bool
12387 {
12392 {
12402 }
12403 }
12405 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
12406 sequence implementing an atomic operation. */
12408 static void
12410 {
12417 {
12419 }
12420 }
12422 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
12423 for the data in memory. EXPECTED is the value expected to be in memory.
12424 DESIRED is the value to store to memory. MEM is the memory location. MODEL
12425 is the memory ordering to use. */
12427 void
12430 rtx model)
12431 {
12433 machine_mode mode;
12438 {
12445 }
12447 /* Move the expected value into the CAS destination register. */
12450 /* Emit the CAS. */
12453 /* Compare the expected value with the value loaded by the CAS, to establish
12454 whether the swap was made. */
12456 }
12458 /* Split a compare and swap pattern. */
12460 void
12462 {
12464 machine_mode mode;
12469 rtx model_rtx;
12481 /* When OLDVAL is zero and we want the strong version we can emit a tighter
12482 loop:
12483 .label1:
12484 LD[A]XR rval, [mem]
12485 CBNZ rval, .label2
12486 ST[L]XR scratch, newval, [mem]
12487 CBNZ scratch, .label1
12488 .label2:
12489 CMP rval, 0. */
12494 {
12497 }
12500 /* The initial load can be relaxed for a __sync operation since a final
12501 barrier will be emitted to stop code hoisting. */
12505 else
12509 {
12514 }
12515 else
12516 {
12522 }
12527 {
12532 }
12533 else
12534 {
12538 }
12541 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
12542 to set the condition flags. If this is not used it will be removed by
12543 later passes. */
12545 {
12549 }
12550 /* Emit any final barrier needed for a __sync operation. */
12553 }
12555 /* Emit a BIC instruction. */
12557 static void
12559 {
12564 {
12569 }
12572 }
12574 /* Emit an atomic swap. */
12576 static void
12579 {
12583 {
12590 }
12593 }
12595 /* Operations supported by aarch64_emit_atomic_load_op. */
12597 enum aarch64_atomic_load_op_code
12598 {
12602 AARCH64_LDOP_BIC /* A & ~B */
12603 };
12605 /* Emit an atomic load-operate. */
12607 static void
12611 {
12614 {
12615 gen_aarch64_atomic_loadaddqi,
12616 gen_aarch64_atomic_loadaddhi,
12617 gen_aarch64_atomic_loadaddsi,
12618 gen_aarch64_atomic_loadadddi
12619 };
12621 {
12622 gen_aarch64_atomic_loadeorqi,
12623 gen_aarch64_atomic_loadeorhi,
12624 gen_aarch64_atomic_loadeorsi,
12625 gen_aarch64_atomic_loadeordi
12626 };
12628 {
12629 gen_aarch64_atomic_loadsetqi,
12630 gen_aarch64_atomic_loadsethi,
12631 gen_aarch64_atomic_loadsetsi,
12632 gen_aarch64_atomic_loadsetdi
12633 };
12635 {
12636 gen_aarch64_atomic_loadclrqi,
12637 gen_aarch64_atomic_loadclrhi,
12638 gen_aarch64_atomic_loadclrsi,
12639 gen_aarch64_atomic_loadclrdi
12640 };
12641 aarch64_atomic_load_op_fn gen;
12645 {
12652 }
12655 {
12662 }
12665 }
12667 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12668 location to store the data read from memory. OUT_RESULT is the location to
12669 store the result of the operation. MEM is the memory location to read and
12670 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12671 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12672 be NULL. */
12674 void
12677 {
12681 aarch64_atomic_load_op_code ldop_code;
12682 rtx src;
12683 rtx x;
12691 /* Make sure the value is in a register, putting it into a destination
12692 register if it needs to be manipulated. */
12695 {
12698 }
12699 else
12703 /* Preprocess the data for the operation as necessary. If the operation is
12704 a SET then emit a swap instruction and finish. */
12706 {
12712 /* Negate the value and treat it as a PLUS. */
12713 {
12714 rtx neg_src;
12716 /* Resize the value if necessary. */
12725 }
12726 /* Fall-through. */
12740 {
12741 rtx not_src;
12743 /* Resize the value if necessary. */
12752 }
12757 /* The operation can't be done with atomic instructions. */
12759 }
12763 /* If necessary, calculate the data in memory after the update by redoing the
12764 operation from values in registers. */
12769 {
12773 }
12778 {
12794 }
12799 }
12801 /* Split an atomic operation. */
12803 void
12806 {
12812 rtx x;
12814 /* Split the atomic operation into a sequence. */
12822 else
12826 /* The initial load can be relaxed for a __sync operation since a final
12827 barrier will be emitted to stop code hoisting. */
12831 else
12835 {
12849 {
12852 }
12853 /* Fall through. */
12859 }
12869 /* Emit any final barrier needed for a __sync operation. */
12872 }
12874 static void
12876 {
12877 /* Half-precision float operations. The compiler handles all operations
12878 with NULL libfuncs by converting to SFmode. */
12880 /* Conversions. */
12884 /* Arithmetic. */
12891 /* Comparisons. */
12899 }
12901 /* Target hook for c_mode_for_suffix. */
12902 static machine_mode
12904 {
12909 }
12911 /* We can only represent floating point constants which will fit in
12912 "quarter-precision" values. These values are characterised by
12913 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12914 by:
12916 (-1)^s * (n/16) * 2^r
12918 Where:
12919 's' is the sign bit.
12920 'n' is an integer in the range 16 <= n <= 31.
12921 'r' is an integer in the range -3 <= r <= 4. */
12923 /* Return true iff X can be represented by a quarter-precision
12924 floating point immediate operand X. Note, we cannot represent 0.0. */
12925 bool
12927 {
12928 /* This represents our current view of how many bits
12929 make up the mantissa. */
12939 /* We don't support HFmode constants yet. */
12945 /* We cannot represent infinities, NaNs or +/-zero. We won't
12946 know if we have +zero until we analyse the mantissa, but we
12947 can reject the other invalid values. */
12952 /* Extract exponent. */
12956 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12957 highest (sign) bit, with a fixed binary point at bit point_pos.
12958 m1 holds the low part of the mantissa, m2 the high part.
12959 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12960 bits for the mantissa, this can fail (low bits will be lost). */
12964 /* If the low part of the mantissa has bits set we cannot represent
12965 the value. */
12968 /* We have rejected the lower HOST_WIDE_INT, so update our
12969 understanding of how many bits lie in the mantissa and
12970 look only at the high HOST_WIDE_INT. */
12974 /* We can only represent values with a mantissa of the form 1.xxxx. */
12979 /* Having filtered unrepresentable values, we may now remove all
12980 but the highest 5 bits. */
12983 /* We cannot represent the value 0.0, so reject it. This is handled
12984 elsewhere. */
12988 /* Then, as bit 4 is always set, we can mask it off, leaving
12989 the mantissa in the range [0, 15]. */
12993 /* GCC internally does not use IEEE754-like encoding (where normalized
12994 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12995 Our mantissa values are shifted 4 places to the left relative to
12996 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12997 by 5 places to correct for GCC's representation. */
13001 }
13005 machine_mode mode,
13007 {
13017 /* This will return true to show const_vector is legal for use as either
13018 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
13019 also update INFO to show how the immediate should be generated. */
13028 {
13030 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
13031 move immediate path. */
13034 else
13035 {
13044 else
13048 }
13049 }
13062 else
13066 }
13070 {
13072 /* If a floating point number was passed and we desire to use it in an
13073 integer mode do the conversion to integer. */
13075 {
13080 }
13082 machine_mode vmode;
13083 /* use a 64 bit mode for everything except for DI/DF mode, where we use
13084 a 128 bit vector mode. */
13090 }
13092 /* Split operands into moves from op[1] + op[2] into op[0]. */
13094 void
13096 {
13107 {
13108 /* No-op move. Can't split to nothing; emit something. */
13111 }
13113 /* Preserve register attributes for variable tracking. */
13118 /* Special case of reversed high/low parts. */
13121 {
13125 }
13127 {
13128 /* Try to avoid unnecessary moves if part of the result
13129 is in the right place already. */
13134 }
13135 else
13136 {
13141 }
13142 }
13144 /* vec_perm support. */
13146 #define MAX_VECT_LEN 16
13148 struct expand_vec_perm_d
13149 {
13151 auto_vec_perm_indices perm;
13152 machine_mode vmode;
13155 };
13157 /* Generate a variable permutation. */
13159 static void
13161 {
13172 {
13174 {
13175 /* Expand the argument to a V16QI mode by duplicating it. */
13179 }
13180 else
13181 {
13183 }
13184 }
13185 else
13186 {
13187 rtx pair;
13190 {
13194 }
13195 else
13196 {
13200 }
13201 }
13202 }
13204 void
13206 {
13210 rtx mask;
13212 /* The TBL instruction does not use a modulo index, so we must take care
13213 of that ourselves. */
13218 /* For big-endian, we also need to reverse the index within the vector
13219 (but not which vector). */
13221 {
13222 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
13227 }
13229 }
13231 /* Recognize patterns suitable for the TRN instructions. */
13232 static bool
13234 {
13243 /* Note that these are little-endian tests.
13244 We correct for big-endian later. */
13249 else
13254 {
13259 }
13261 /* Success! */
13268 {
13271 }
13275 {
13277 {
13292 }
13293 }
13294 else
13295 {
13297 {
13312 }
13313 }
13317 }
13319 /* Recognize patterns suitable for the UZP instructions. */
13320 static bool
13322 {
13331 /* Note that these are little-endian tests.
13332 We correct for big-endian later. */
13337 else
13342 {
13346 }
13348 /* Success! */
13355 {
13358 }
13362 {
13364 {
13379 }
13380 }
13381 else
13382 {
13384 {
13399 }
13400 }
13404 }
13406 /* Recognize patterns suitable for the ZIP instructions. */
13407 static bool
13409 {
13418 /* Note that these are little-endian tests.
13419 We correct for big-endian later. */
13422 /* Do Nothing. */
13423 ;
13426 else
13431 {
13438 }
13440 /* Success! */
13447 {
13450 }
13454 {
13456 {
13471 }
13472 }
13473 else
13474 {
13476 {
13491 }
13492 }
13496 }
13498 /* Recognize patterns for the EXT insn. */
13500 static bool
13502 {
13505 rtx offset;
13509 /* Check if the extracted indices are increasing by one. */
13511 {
13514 {
13515 /* We'll pass the same vector in twice, so allow indices to wrap. */
13517 }
13520 }
13523 {
13538 }
13540 /* Success! */
13544 /* The case where (location == 0) is a no-op for both big- and little-endian,
13545 and is removed by the mid-end at optimization levels -O1 and higher. */
13548 {
13549 /* After setup, we want the high elements of the first vector (stored
13550 at the LSB end of the register), and the low elements of the second
13551 vector (stored at the MSB end of the register). So swap. */
13553 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13555 }
13560 }
13562 /* Recognize patterns for the REV insns. */
13564 static bool
13566 {
13575 {
13578 {
13583 }
13587 {
13594 }
13598 {
13611 }
13615 }
13619 {
13620 /* This is guaranteed to be true as the value of diff
13621 is 7, 3, 1 and we should have enough elements in the
13622 queue to generate this. Getting a vector mask with a
13623 value of diff other than these values implies that
13624 something is wrong by the time we get here. */
13628 }
13630 /* Success! */
13636 }
13638 static bool
13640 {
13643 rtx in0;
13646 rtx lane;
13650 {
13653 }
13655 /* The generic preparation in aarch64_expand_vec_perm_const_1
13656 swaps the operand order and the permute indices if it finds
13657 d->perm[0] to be in the second operand. Thus, we can always
13658 use d->op0 and need not do any extra arithmetic to get the
13659 correct lane number. */
13664 {
13679 }
13683 }
13685 static bool
13687 {
13695 /* Generic code will try constant permutation twice. Once with the
13696 original mode and again with the elements lowered to QImode.
13697 So wait and don't do the selector expansion ourselves. */
13702 {
13705 /* If big-endian and two vectors we end up with a weird mixed-endian
13706 mode on NEON. Reverse the index within each word but not the word
13707 itself. */
13710 }
13716 }
13718 static bool
13720 {
13721 /* The pattern matching functions above are written to look for a small
13722 number to begin the sequence (0, 1, N/2). If we begin with an index
13723 from the second operand, we can swap the operands. */
13726 {
13732 }
13735 {
13749 }
13751 }
13753 /* Expand a vec_perm_const pattern. */
13755 bool
13757 {
13772 {
13777 }
13780 {
13789 /* The elements of PERM do not suggest that only the first operand
13790 is used, but both operands are identical. Allow easier matching
13791 of the permutation by folding the permutation into the single
13792 input vector. */
13793 /* Fall Through. */
13805 }
13808 }
13810 static bool
13812 {
13821 /* Calculate whether all elements are in one vector. */
13824 {
13828 }
13830 /* If all elements are from the second vector, reindex as if from the
13831 first vector. */
13836 /* Check whether the mask can be applied to a single vector. */
13849 }
13851 rtx
13853 {
13854 /* We have to reverse each vector because we dont have
13855 a permuted load that can reverse-load according to ABI rules. */
13856 rtx mask;
13870 }
13872 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
13873 true. However due to issues with register allocation it is preferable
13874 to avoid tieing integer scalar and FP scalar modes. Executing integer
13875 operations in general registers is better than treating them as scalar
13876 vector operations. This reduces latency and avoids redundant int<->FP
13877 moves. So tie modes if they are either the same class, or vector modes
13878 with other vector modes, vector structs or any scalar mode. */
13880 static bool
13882 {
13886 /* We specifically want to allow elements of "structure" modes to
13887 be tieable to the structure. This more general condition allows
13888 other rarer situations too. */
13892 /* Also allow any scalar modes with vectors. */
13898 }
13900 /* Return a new RTX holding the result of moving POINTER forward by
13901 AMOUNT bytes. */
13903 static rtx
13905 {
13910 }
13912 /* Return a new RTX holding the result of moving POINTER forward by the
13913 size of the mode it points to. */
13915 static rtx
13917 {
13921 }
13923 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13924 MODE bytes. */
13926 static void
13928 machine_mode mode)
13929 {
13932 /* "Cast" the pointers to the correct mode. */
13935 /* Emit the memcpy. */
13938 /* Move the pointers forward. */
13941 }
13943 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13944 we succeed, otherwise return false. */
13946 bool
13948 {
13952 rtx base;
13955 /* When optimizing for size, give a better estimate of the length of a
13956 memcpy call, but use the default otherwise. */
13959 /* We can't do anything smart if the amount to copy is not constant. */
13965 /* Try to keep the number of instructions low. For cases below 16 bytes we
13966 need to make at most two moves. For cases above 16 bytes it will be one
13967 move for each 16 byte chunk, then at most two additional moves. */
13977 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13978 1-byte chunk. */
13980 {
13982 {
13985 }
13991 }
13993 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13994 4-byte chunk, partially overlapping with the previously copied chunk. */
13996 {
14000 {
14006 }
14008 }
14010 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
14011 them, then (if applicable) an 8-byte chunk. */
14013 {
14015 {
14018 }
14019 else
14020 {
14023 }
14024 }
14026 /* Finish the final bytes of the copy. We can always do this in one
14027 instruction. We either copy the exact amount we need, or partially
14028 overlap with the previous chunk we copied and copy 8-bytes. */
14037 else
14038 {
14040 {
14044 }
14045 else
14046 {
14052 }
14053 }
14056 }
14058 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
14059 SImode stores. Handle the case when the constant has identical
14060 bottom and top halves. This is beneficial when the two stores can be
14061 merged into an STP and we avoid synthesising potentially expensive
14062 immediates twice. Return true if such a split is possible. */
14064 bool
14066 {
14075 unsigned int orig_cost
14077 unsigned int lo_cost
14080 /* We want to transform:
14081 MOV x1, 49370
14082 MOVK x1, 0x140, lsl 16
14083 MOVK x1, 0xc0da, lsl 32
14084 MOVK x1, 0x140, lsl 48
14085 STR x1, [x0]
14086 into:
14087 MOV w1, 49370
14088 MOVK w1, 0x140, lsl 16
14089 STP w1, w1, [x0]
14090 So we want to perform this only when we save two instructions
14091 or more. When optimizing for size, however, accept any code size
14092 savings we can. */
14107 /* Don't emit an explicit store pair as this may not be always profitable.
14108 Let the sched-fusion logic decide whether to merge them. */
14113 }
14115 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
14117 static unsigned HOST_WIDE_INT
14119 {
14121 }
14123 static bool
14128 {
14129 /* STORE_BY_PIECES can be used when copying a constant string, but
14130 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
14131 For now we always fail this and let the move_by_pieces code copy
14132 the string from read-only memory. */
14137 }
14139 static rtx
14142 {
14146 insn_code icode;
14157 {
14185 }
14190 {
14193 }
14202 {
14205 }
14211 }
14213 static rtx
14216 {
14220 insn_code icode;
14232 {
14260 }
14265 {
14268 }
14276 {
14281 }
14292 {
14295 }
14301 }
14303 #undef TARGET_GEN_CCMP_FIRST
14304 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
14306 #undef TARGET_GEN_CCMP_NEXT
14307 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
14309 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
14310 instruction fusion of some sort. */
14312 static bool
14314 {
14316 }
14319 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
14320 should be kept together during scheduling. */
14322 static bool
14324 {
14325 rtx set_dest;
14328 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
14335 {
14336 /* We are trying to match:
14337 prev (mov) == (set (reg r0) (const_int imm16))
14338 curr (movk) == (set (zero_extract (reg r0)
14339 (const_int 16)
14340 (const_int 16))
14341 (const_int imm16_1)) */
14353 {
14355 }
14356 }
14359 {
14361 /* We're trying to match:
14362 prev (adrp) == (set (reg r1)
14363 (high (symbol_ref ("SYM"))))
14364 curr (add) == (set (reg r0)
14365 (lo_sum (reg r1)
14366 (symbol_ref ("SYM"))))
14367 Note that r0 need not necessarily be the same as r1, especially
14368 during pre-regalloc scheduling. */
14372 {
14380 }
14381 }
14384 {
14386 /* We're trying to match:
14387 prev (movk) == (set (zero_extract (reg r0)
14388 (const_int 16)
14389 (const_int 32))
14390 (const_int imm16_1))
14391 curr (movk) == (set (zero_extract (reg r0)
14392 (const_int 16)
14393 (const_int 48))
14394 (const_int imm16_2)) */
14410 }
14412 {
14413 /* We're trying to match:
14414 prev (adrp) == (set (reg r0)
14415 (high (symbol_ref ("SYM"))))
14416 curr (ldr) == (set (reg r1)
14417 (mem (lo_sum (reg r0)
14418 (symbol_ref ("SYM")))))
14419 or
14420 curr (ldr) == (set (reg r1)
14421 (zero_extend (mem
14422 (lo_sum (reg r0)
14423 (symbol_ref ("SYM")))))) */
14426 {
14439 }
14440 }
14448 {
14452 rtx cc_reg_1;
14457 && prev
14459 {
14460 /* FIXME: this misses some which is considered simple arthematic
14461 instructions for ThunderX. Simple shifts are missed here. */
14467 }
14468 }
14471 && curr_set
14474 {
14475 /* We're trying to match:
14476 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
14477 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
14478 (const_int 0))
14479 (label_ref ("SYM"))
14480 (pc)) */
14487 {
14488 /* Fuse ALU operations followed by conditional branch instruction. */
14490 {
14511 }
14512 }
14513 }
14516 }
14518 /* Return true iff the instruction fusion described by OP is enabled. */
14520 bool
14522 {
14524 }
14526 /* If MEM is in the form of [base+offset], extract the two parts
14527 of address and set to BASE and OFFSET, otherwise return false
14528 after clearing BASE and OFFSET. */
14530 bool
14532 {
14533 rtx addr;
14540 {
14544 }
14548 {
14552 }
14558 }
14560 /* Types for scheduling fusion. */
14561 enum sched_fusion_type
14562 {
14564 SCHED_FUSION_LD_SIGN_EXTEND,
14565 SCHED_FUSION_LD_ZERO_EXTEND,
14566 SCHED_FUSION_LD,
14567 SCHED_FUSION_ST,
14568 SCHED_FUSION_NUM
14569 };
14571 /* If INSN is a load or store of address in the form of [base+offset],
14572 extract the two parts and set to BASE and OFFSET. Return scheduling
14573 fusion type this INSN is. */
14575 static enum sched_fusion_type
14577 {
14595 {
14600 }
14602 {
14607 }
14612 {
14615 }
14616 else
14623 }
14625 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14627 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14628 and PRI are only calculated for these instructions. For other instruction,
14629 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14630 type instruction fusion can be added by returning different priorities.
14632 It's important that irrelevant instructions get the largest FUSION_PRI. */
14634 static void
14637 {
14647 {
14651 }
14653 /* Set FUSION_PRI according to fusion type and base register. */
14656 /* Calculate PRI. */
14659 /* INSN with smaller offset goes first. */
14663 else
14668 }
14670 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14671 Adjust priority of sha1h instructions so they are scheduled before
14672 other SHA1 instructions. */
14674 static int
14676 {
14680 {
14685 }
14688 }
14690 /* Given OPERANDS of consecutive load/store, check if we can merge
14691 them into ldp/stp. LOAD is true if they are load instructions.
14692 MODE is the mode of memory operands. */
14694 bool
14696 machine_mode mode)
14697 {
14703 {
14711 }
14712 else
14713 {
14718 }
14720 /* The mems cannot be volatile. */
14724 /* If we have SImode and slow unaligned ldp,
14725 check the alignment to be at least 8 byte. */
14729 && !optimize_size
14733 /* Check if the addresses are in the form of [base+offset]. */
14741 /* Check if the bases are same. */
14748 /* Check if the offsets are consecutive. */
14752 /* Check if the addresses are clobbered by load. */
14754 {
14758 /* In increasing order, the last load can clobber the address. */
14761 }
14765 else
14770 else
14773 /* Check if the registers are of same class. */
14778 }
14780 /* Given OPERANDS of consecutive load/store, check if we can merge
14781 them into ldp/stp by adjusting the offset. LOAD is true if they
14782 are load instructions. MODE is the mode of memory operands.
14784 Given below consecutive stores:
14786 str w1, [xb, 0x100]
14787 str w1, [xb, 0x104]
14788 str w1, [xb, 0x108]
14789 str w1, [xb, 0x10c]
14791 Though the offsets are out of the range supported by stp, we can
14792 still pair them after adjusting the offset, like:
14794 add scratch, xb, 0x100
14795 stp w1, w1, [scratch]
14796 stp w1, w1, [scratch, 0x8]
14798 The peephole patterns detecting this opportunity should guarantee
14799 the scratch register is avaliable. */
14801 bool
14803 scalar_mode mode)
14804 {
14811 {
14824 }
14825 else
14826 {
14835 }
14836 /* Skip if memory operand is by itslef valid for ldp/stp. */
14840 /* The mems cannot be volatile. */
14845 /* Check if the addresses are in the form of [base+offset]. */
14859 /* Check if the bases are same. */
14870 /* Check if the offsets are consecutive. */
14879 /* Check if the addresses are clobbered by load. */
14881 {
14887 /* In increasing order, the last load can clobber the address. */
14890 }
14892 /* If we have SImode and slow unaligned ldp,
14893 check the alignment to be at least 8 byte. */
14897 && !optimize_size
14903 else
14908 else
14913 else
14918 else
14921 /* Check if the registers are of same class. */
14926 }
14928 /* Given OPERANDS of consecutive load/store, this function pairs them
14929 into ldp/stp after adjusting the offset. It depends on the fact
14930 that addresses of load/store instructions are in increasing order.
14931 MODE is the mode of memory operands. CODE is the rtl operator
14932 which should be applied to all memory operands, it's SIGN_EXTEND,
14933 ZERO_EXTEND or UNKNOWN. */
14935 bool
14938 {
14944 {
14949 }
14950 else
14951 {
14957 }
14962 /* Adjust offset thus it can fit in ldp/stp instruction. */
14970 /* Further adjust to make sure all offsets are OK. */
14972 {
14975 }
14977 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14982 {
14985 }
14987 /* Create new memory references. */
14991 /* Check if the adjusted address is OK for ldp/stp. */
15010 {
15015 }
15017 {
15022 }
15025 {
15030 }
15031 else
15032 {
15037 }
15039 /* Emit adjusting instruction. */
15041 /* Emit ldp/stp instructions. */
15049 }
15051 /* Return 1 if pseudo register should be created and used to hold
15052 GOT address for PIC code. */
15054 bool
15056 {
15058 }
15060 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
15062 static int
15064 {
15066 {
15073 }
15076 }
15079 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
15080 return the log2 of that value. Otherwise return -1. */
15082 int
15084 {
15099 }
15101 /* If X is a vector of equal CONST_DOUBLE values and that value is
15102 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
15104 int
15106 {
15122 }
15124 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
15125 to float.
15127 __fp16 always promotes through this hook.
15128 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
15129 through the generic excess precision logic rather than here. */
15131 static tree
15133 {
15139 }
15141 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
15143 static bool
15145 optimization_type opt_type)
15146 {
15148 {
15154 }
15155 }
15157 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
15158 if MODE is HFmode, and punt to the generic implementation otherwise. */
15160 static bool
15162 {
15166 }
15168 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
15169 if MODE is HFmode, and punt to the generic implementation otherwise. */
15171 static bool
15173 {
15177 }
15179 /* Set the value of FLT_EVAL_METHOD.
15180 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
15182 0: evaluate all operations and constants, whose semantic type has at
15183 most the range and precision of type float, to the range and
15184 precision of float; evaluate all other operations and constants to
15185 the range and precision of the semantic type;
15187 N, where _FloatN is a supported interchange floating type
15188 evaluate all operations and constants, whose semantic type has at
15189 most the range and precision of _FloatN type, to the range and
15190 precision of the _FloatN type; evaluate all other operations and
15191 constants to the range and precision of the semantic type;
15193 If we have the ARMv8.2-A extensions then we support _Float16 in native
15194 precision, so we should set this to 16. Otherwise, we support the type,
15195 but want to evaluate expressions in float precision, so set this to
15196 0. */
15198 static enum flt_eval_method
15200 {
15202 {
15205 /* We can calculate either in 16-bit range and precision or
15206 32-bit range and precision. Make that decision based on whether
15207 we have native support for the ARMv8.2-A 16-bit floating-point
15208 instructions or not. */
15210 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
15216 }
15218 }
15220 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
15221 scheduled for speculative execution. Reject the long-running division
15222 and square-root instructions. */
15224 static bool
15226 {
15228 {
15246 }
15247 }
15249 /* Target-specific selftests. */
15251 #if CHECKING_P
15255 /* Selftest for the RTL loader.
15256 Verify that the RTL loader copes with a dump from
15257 print_rtx_function. This is essentially just a test that class
15258 function_reader can handle a real dump, but it also verifies
15259 that lookup_reg_by_dump_name correctly handles hard regs.
15260 The presence of hard reg names in the dump means that the test is
15261 target-specific, hence it is in this file. */
15263 static void
15265 {
15277 /* Verify crtl->return_rtx. */
15281 }
15283 /* Run all target-specific selftests. */
15285 static void
15287 {
15289 }
15295 #undef TARGET_ADDRESS_COST
15296 #define TARGET_ADDRESS_COST aarch64_address_cost
15298 /* This hook will determines whether unnamed bitfields affect the alignment
15299 of the containing structure. The hook returns true if the structure
15300 should inherit the alignment requirements of an unnamed bitfield's
15301 type. */
15302 #undef TARGET_ALIGN_ANON_BITFIELD
15303 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
15305 #undef TARGET_ASM_ALIGNED_DI_OP
15308 #undef TARGET_ASM_ALIGNED_HI_OP
15311 #undef TARGET_ASM_ALIGNED_SI_OP
15314 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
15315 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
15316 hook_bool_const_tree_hwi_hwi_const_tree_true
15318 #undef TARGET_ASM_FILE_START
15319 #define TARGET_ASM_FILE_START aarch64_start_file
15321 #undef TARGET_ASM_OUTPUT_MI_THUNK
15322 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
15324 #undef TARGET_ASM_SELECT_RTX_SECTION
15325 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
15327 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
15328 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
15330 #undef TARGET_BUILD_BUILTIN_VA_LIST
15331 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
15333 #undef TARGET_CALLEE_COPIES
15334 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
15336 #undef TARGET_CAN_ELIMINATE
15337 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
15339 #undef TARGET_CAN_INLINE_P
15340 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
15342 #undef TARGET_CANNOT_FORCE_CONST_MEM
15343 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
15345 #undef TARGET_CASE_VALUES_THRESHOLD
15346 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
15348 #undef TARGET_CONDITIONAL_REGISTER_USAGE
15349 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
15351 /* Only the least significant bit is used for initialization guard
15352 variables. */
15353 #undef TARGET_CXX_GUARD_MASK_BIT
15354 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
15356 #undef TARGET_C_MODE_FOR_SUFFIX
15357 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
15359 #ifdef TARGET_BIG_ENDIAN_DEFAULT
15360 #undef TARGET_DEFAULT_TARGET_FLAGS
15361 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
15362 #endif
15364 #undef TARGET_CLASS_MAX_NREGS
15365 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
15367 #undef TARGET_BUILTIN_DECL
15368 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
15370 #undef TARGET_BUILTIN_RECIPROCAL
15371 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
15373 #undef TARGET_C_EXCESS_PRECISION
15374 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
15376 #undef TARGET_EXPAND_BUILTIN
15377 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
15379 #undef TARGET_EXPAND_BUILTIN_VA_START
15380 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
15382 #undef TARGET_FOLD_BUILTIN
15383 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
15385 #undef TARGET_FUNCTION_ARG
15386 #define TARGET_FUNCTION_ARG aarch64_function_arg
15388 #undef TARGET_FUNCTION_ARG_ADVANCE
15389 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
15391 #undef TARGET_FUNCTION_ARG_BOUNDARY
15392 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
15394 #undef TARGET_FUNCTION_ARG_PADDING
15395 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
15397 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
15398 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
15400 #undef TARGET_FUNCTION_VALUE
15401 #define TARGET_FUNCTION_VALUE aarch64_function_value
15403 #undef TARGET_FUNCTION_VALUE_REGNO_P
15404 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
15406 #undef TARGET_FRAME_POINTER_REQUIRED
15407 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
15409 #undef TARGET_GIMPLE_FOLD_BUILTIN
15410 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
15412 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
15413 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
15415 #undef TARGET_INIT_BUILTINS
15416 #define TARGET_INIT_BUILTINS aarch64_init_builtins
15418 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
15419 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
15420 aarch64_ira_change_pseudo_allocno_class
15422 #undef TARGET_LEGITIMATE_ADDRESS_P
15423 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
15425 #undef TARGET_LEGITIMATE_CONSTANT_P
15426 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
15428 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
15429 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
15430 aarch64_legitimize_address_displacement
15432 #undef TARGET_LIBGCC_CMP_RETURN_MODE
15433 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
15435 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
15436 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
15437 aarch64_libgcc_floating_mode_supported_p
15439 #undef TARGET_MANGLE_TYPE
15440 #define TARGET_MANGLE_TYPE aarch64_mangle_type
15442 #undef TARGET_MEMORY_MOVE_COST
15443 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
15445 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
15446 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
15448 #undef TARGET_MUST_PASS_IN_STACK
15449 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
15451 /* This target hook should return true if accesses to volatile bitfields
15452 should use the narrowest mode possible. It should return false if these
15453 accesses should use the bitfield container type. */
15454 #undef TARGET_NARROW_VOLATILE_BITFIELD
15455 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
15457 #undef TARGET_OPTION_OVERRIDE
15458 #define TARGET_OPTION_OVERRIDE aarch64_override_options
15460 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
15461 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
15462 aarch64_override_options_after_change
15464 #undef TARGET_OPTION_SAVE
15465 #define TARGET_OPTION_SAVE aarch64_option_save
15467 #undef TARGET_OPTION_RESTORE
15468 #define TARGET_OPTION_RESTORE aarch64_option_restore
15470 #undef TARGET_OPTION_PRINT
15471 #define TARGET_OPTION_PRINT aarch64_option_print
15473 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
15474 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
15476 #undef TARGET_SET_CURRENT_FUNCTION
15477 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
15479 #undef TARGET_PASS_BY_REFERENCE
15480 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
15482 #undef TARGET_PREFERRED_RELOAD_CLASS
15483 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
15485 #undef TARGET_SCHED_REASSOCIATION_WIDTH
15486 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
15488 #undef TARGET_PROMOTED_TYPE
15489 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
15491 #undef TARGET_SECONDARY_RELOAD
15492 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
15494 #undef TARGET_SHIFT_TRUNCATION_MASK
15495 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
15497 #undef TARGET_SETUP_INCOMING_VARARGS
15498 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
15500 #undef TARGET_STRUCT_VALUE_RTX
15501 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
15503 #undef TARGET_REGISTER_MOVE_COST
15504 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
15506 #undef TARGET_RETURN_IN_MEMORY
15507 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
15509 #undef TARGET_RETURN_IN_MSB
15510 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
15512 #undef TARGET_RTX_COSTS
15513 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
15515 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15516 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
15518 #undef TARGET_SCHED_ISSUE_RATE
15519 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
15521 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15522 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15523 aarch64_sched_first_cycle_multipass_dfa_lookahead
15525 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
15526 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
15527 aarch64_first_cycle_multipass_dfa_lookahead_guard
15529 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
15530 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
15531 aarch64_get_separate_components
15533 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
15534 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
15535 aarch64_components_for_bb
15537 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
15538 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
15539 aarch64_disqualify_components
15541 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
15542 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
15543 aarch64_emit_prologue_components
15545 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
15546 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
15547 aarch64_emit_epilogue_components
15549 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
15550 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
15551 aarch64_set_handled_components
15553 #undef TARGET_TRAMPOLINE_INIT
15554 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
15556 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15557 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
15559 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15560 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
15562 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
15563 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
15564 aarch64_builtin_support_vector_misalignment
15566 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15567 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15569 #undef TARGET_VECTORIZE_ADD_STMT_COST
15570 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15572 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15573 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15574 aarch64_builtin_vectorization_cost
15576 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15577 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15579 #undef TARGET_VECTORIZE_BUILTINS
15580 #define TARGET_VECTORIZE_BUILTINS
15582 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15583 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15584 aarch64_builtin_vectorized_function
15586 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15587 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15588 aarch64_autovectorize_vector_sizes
15590 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15591 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15592 aarch64_atomic_assign_expand_fenv
15594 /* Section anchor support. */
15596 #undef TARGET_MIN_ANCHOR_OFFSET
15597 #define TARGET_MIN_ANCHOR_OFFSET -256
15599 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15600 byte offset; we can do much more for larger data types, but have no way
15601 to determine the size of the access. We assume accesses are aligned. */
15602 #undef TARGET_MAX_ANCHOR_OFFSET
15603 #define TARGET_MAX_ANCHOR_OFFSET 4095
15605 #undef TARGET_VECTOR_ALIGNMENT
15606 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15608 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15609 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15610 aarch64_simd_vector_alignment_reachable
15612 /* vec_perm support. */
15614 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15615 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15616 aarch64_vectorize_vec_perm_const_ok
15618 #undef TARGET_INIT_LIBFUNCS
15619 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15621 #undef TARGET_FIXED_CONDITION_CODE_REGS
15622 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15624 #undef TARGET_FLAGS_REGNUM
15625 #define TARGET_FLAGS_REGNUM CC_REGNUM
15627 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15628 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15630 #undef TARGET_ASAN_SHADOW_OFFSET
15631 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15633 #undef TARGET_LEGITIMIZE_ADDRESS
15634 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15636 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15637 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15638 aarch64_use_by_pieces_infrastructure_p
15640 #undef TARGET_SCHED_CAN_SPECULATE_INSN
15641 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
15643 #undef TARGET_CAN_USE_DOLOOP_P
15644 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15646 #undef TARGET_SCHED_ADJUST_PRIORITY
15647 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15649 #undef TARGET_SCHED_MACRO_FUSION_P
15650 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15652 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15653 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15655 #undef TARGET_SCHED_FUSION_PRIORITY
15656 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15658 #undef TARGET_UNSPEC_MAY_TRAP_P
15659 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15661 #undef TARGET_USE_PSEUDO_PIC_REG
15662 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15664 #undef TARGET_PRINT_OPERAND
15665 #define TARGET_PRINT_OPERAND aarch64_print_operand
15667 #undef TARGET_PRINT_OPERAND_ADDRESS
15668 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15670 #undef TARGET_OPTAB_SUPPORTED_P
15671 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15673 #undef TARGET_OMIT_STRUCT_RETURN_REG
15674 #define TARGET_OMIT_STRUCT_RETURN_REG true
15676 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15677 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15678 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15680 #undef TARGET_HARD_REGNO_NREGS
15681 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
15682 #undef TARGET_HARD_REGNO_MODE_OK
15683 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
15685 #undef TARGET_MODES_TIEABLE_P
15686 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
15688 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
15689 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
15690 aarch64_hard_regno_call_part_clobbered
15692 #undef TARGET_CONSTANT_ALIGNMENT
15693 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
15695 #if CHECKING_P
15696 #undef TARGET_RUN_TARGET_SELFTESTS
15697 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests