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MIPS32R6 and MIPS64R6 support
[official-gcc.git] / gcc / config / mips / mips.h
blob4da256dab0091f86184c7bb6620727524b4b1f7d
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables. */
166 #define TARGET_GPWORD \
167 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
168
169 /* True if the output must have a writable .eh_frame.
170 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
171 #ifdef HAVE_LD_PERSONALITY_RELAXATION
172 #define TARGET_WRITABLE_EH_FRAME 0
173 #else
174 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
175 #endif
176
177 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
178 #ifdef HAVE_AS_DSPR1_MULT
179 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
180 #else
181 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
182 #endif
183
184 /* The ISA compression flags that are currently in effect. */
185 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
186
187 /* Generate mips16 code */
188 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
189 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
190 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
191 /* Generate mips16e register save/restore sequences. */
192 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
193
194 /* True if we're generating a form of MIPS16 code in which general
195 text loads are allowed. */
196 #define TARGET_MIPS16_TEXT_LOADS \
197 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
198
199 /* True if we're generating a form of MIPS16 code in which PC-relative
200 loads are allowed. */
201 #define TARGET_MIPS16_PCREL_LOADS \
202 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
203
204 /* Generic ISA defines. */
205 #define ISA_MIPS1 (mips_isa == 1)
206 #define ISA_MIPS2 (mips_isa == 2)
207 #define ISA_MIPS3 (mips_isa == 3)
208 #define ISA_MIPS4 (mips_isa == 4)
209 #define ISA_MIPS32 (mips_isa == 32)
210 #define ISA_MIPS32R2 (mips_isa == 33)
211 #define ISA_MIPS32R3 (mips_isa == 34)
212 #define ISA_MIPS32R5 (mips_isa == 36)
213 #define ISA_MIPS32R6 (mips_isa == 37)
214 #define ISA_MIPS64 (mips_isa == 64)
215 #define ISA_MIPS64R2 (mips_isa == 65)
216 #define ISA_MIPS64R3 (mips_isa == 66)
217 #define ISA_MIPS64R5 (mips_isa == 68)
218 #define ISA_MIPS64R6 (mips_isa == 69)
219
220 /* Architecture target defines. */
221 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
222 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
223 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
224 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
225 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
226 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
227 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
228 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
229 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
230 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
231 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
232 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
233 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
234 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
235 || mips_arch == PROCESSOR_OCTEON2 \
236 || mips_arch == PROCESSOR_OCTEON3)
237 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
238 || mips_arch == PROCESSOR_OCTEON3)
239 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
240 || mips_arch == PROCESSOR_SB1A)
241 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
242 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
243
244 /* Scheduling target defines. */
245 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
246 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
247 || mips_tune == PROCESSOR_24KF2_1 \
248 || mips_tune == PROCESSOR_24KF1_1)
249 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
250 || mips_tune == PROCESSOR_74KF2_1 \
251 || mips_tune == PROCESSOR_74KF1_1 \
252 || mips_tune == PROCESSOR_74KF3_2)
253 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
254 || mips_tune == PROCESSOR_LOONGSON_2F)
255 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
256 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
257 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
258 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
259 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
260 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
261 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
262 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
263 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
264 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
265 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
266 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
267 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
268 || mips_tune == PROCESSOR_OCTEON2 \
269 || mips_tune == PROCESSOR_OCTEON3)
270 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
271 || mips_tune == PROCESSOR_SB1A)
272 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
273
274 /* Whether vector modes and intrinsics for ST Microelectronics
275 Loongson-2E/2F processors should be enabled. In o32 pairs of
276 floating-point registers provide 64-bit values. */
277 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
278 && (TARGET_LOONGSON_2EF \
279 || TARGET_LOONGSON_3A))
280
281 /* True if the pre-reload scheduler should try to create chains of
282 multiply-add or multiply-subtract instructions. For example,
283 suppose we have:
284
285 t1 = a * b
286 t2 = t1 + c * d
287 t3 = e * f
288 t4 = t3 - g * h
289
290 t1 will have a higher priority than t2 and t3 will have a higher
291 priority than t4. However, before reload, there is no dependence
292 between t1 and t3, and they can often have similar priorities.
293 The scheduler will then tend to prefer:
294
295 t1 = a * b
296 t3 = e * f
297 t2 = t1 + c * d
298 t4 = t3 - g * h
299
300 which stops us from making full use of macc/madd-style instructions.
301 This sort of situation occurs frequently in Fourier transforms and
302 in unrolled loops.
303
304 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
305 queue so that chained multiply-add and multiply-subtract instructions
306 appear ahead of any other instruction that is likely to clobber lo.
307 In the example above, if t2 and t3 become ready at the same time,
308 the code ensures that t2 is scheduled first.
309
310 Multiply-accumulate instructions are a bigger win for some targets
311 than others, so this macro is defined on an opt-in basis. */
312 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
313 || TUNE_MIPS4120 \
314 || TUNE_MIPS4130 \
315 || TUNE_24K \
316 || TUNE_P5600)
317
318 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
319 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
320
321 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
322 directly accessible, while the command-line options select
323 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
324 in use. */
325 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
326 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
327
328 /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
329 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
330 #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
331
332 /* TARGET_O32_FP64A_ABI represents all the conditions that form the
333 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
334 #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
335 && !TARGET_ODD_SPREG)
336
337 /* False if SC acts as a memory barrier with respect to itself,
338 otherwise a SYNC will be emitted after SC for atomic operations
339 that require ordering between the SC and following loads and
340 stores. It does not tell anything about ordering of loads and
341 stores prior to and following the SC, only about the SC itself and
342 those loads and stores follow it. */
343 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
344
345 /* Define preprocessor macros for the -march and -mtune options.
346 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
347 processor. If INFO's canonical name is "foo", define PREFIX to
348 be "foo", and define an additional macro PREFIX_FOO. */
349 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
350 do \
351 { \
352 char *macro, *p; \
353 \
354 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
355 for (p = macro; *p != 0; p++) \
356 if (*p == '+') \
357 *p = 'P'; \
358 else \
359 *p = TOUPPER (*p); \
360 \
361 builtin_define (macro); \
362 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
363 free (macro); \
364 } \
365 while (0)
366
367 /* Target CPU builtins. */
368 #define TARGET_CPU_CPP_BUILTINS() \
369 do \
370 { \
371 builtin_assert ("machine=mips"); \
372 builtin_assert ("cpu=mips"); \
373 builtin_define ("__mips__"); \
374 builtin_define ("_mips"); \
375 \
376 /* We do this here because __mips is defined below and so we \
377 can't use builtin_define_std. We don't ever want to define \
378 "mips" for VxWorks because some of the VxWorks headers \
379 construct include filenames from a root directory macro, \
380 an architecture macro and a filename, where the architecture \
381 macro expands to 'mips'. If we define 'mips' to 1, the \
382 architecture macro expands to 1 as well. */ \
383 if (!flag_iso && !TARGET_VXWORKS) \
384 builtin_define ("mips"); \
385 \
386 if (TARGET_64BIT) \
387 builtin_define ("__mips64"); \
388 \
389 /* Treat _R3000 and _R4000 like register-size \
390 defines, which is how they've historically \
391 been used. */ \
392 if (TARGET_64BIT) \
393 { \
394 builtin_define_std ("R4000"); \
395 builtin_define ("_R4000"); \
396 } \
397 else \
398 { \
399 builtin_define_std ("R3000"); \
400 builtin_define ("_R3000"); \
401 } \
402 \
403 if (TARGET_FLOAT64) \
404 builtin_define ("__mips_fpr=64"); \
405 else if (TARGET_FLOATXX) \
406 builtin_define ("__mips_fpr=0"); \
407 else \
408 builtin_define ("__mips_fpr=32"); \
409 \
410 if (mips_base_compression_flags & MASK_MIPS16) \
411 builtin_define ("__mips16"); \
412 \
413 if (TARGET_MIPS3D) \
414 builtin_define ("__mips3d"); \
415 \
416 if (TARGET_SMARTMIPS) \
417 builtin_define ("__mips_smartmips"); \
418 \
419 if (mips_base_compression_flags & MASK_MICROMIPS) \
420 builtin_define ("__mips_micromips"); \
421 \
422 if (TARGET_MCU) \
423 builtin_define ("__mips_mcu"); \
424 \
425 if (TARGET_EVA) \
426 builtin_define ("__mips_eva"); \
427 \
428 if (TARGET_DSP) \
429 { \
430 builtin_define ("__mips_dsp"); \
431 if (TARGET_DSPR2) \
432 { \
433 builtin_define ("__mips_dspr2"); \
434 builtin_define ("__mips_dsp_rev=2"); \
435 } \
436 else \
437 builtin_define ("__mips_dsp_rev=1"); \
438 } \
439 \
440 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
441 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
442 \
443 if (ISA_MIPS1) \
444 { \
445 builtin_define ("__mips=1"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
447 } \
448 else if (ISA_MIPS2) \
449 { \
450 builtin_define ("__mips=2"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
452 } \
453 else if (ISA_MIPS3) \
454 { \
455 builtin_define ("__mips=3"); \
456 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
457 } \
458 else if (ISA_MIPS4) \
459 { \
460 builtin_define ("__mips=4"); \
461 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
462 } \
463 else if (mips_isa >= 32 && mips_isa < 64) \
464 { \
465 builtin_define ("__mips=32"); \
466 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
467 } \
468 else if (mips_isa >= 64) \
469 { \
470 builtin_define ("__mips=64"); \
471 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
472 } \
473 if (mips_isa_rev > 0) \
474 builtin_define_with_int_value ("__mips_isa_rev", \
475 mips_isa_rev); \
476 \
477 switch (mips_abi) \
478 { \
479 case ABI_32: \
480 builtin_define ("_ABIO32=1"); \
481 builtin_define ("_MIPS_SIM=_ABIO32"); \
482 break; \
483 \
484 case ABI_N32: \
485 builtin_define ("_ABIN32=2"); \
486 builtin_define ("_MIPS_SIM=_ABIN32"); \
487 break; \
488 \
489 case ABI_64: \
490 builtin_define ("_ABI64=3"); \
491 builtin_define ("_MIPS_SIM=_ABI64"); \
492 break; \
493 \
494 case ABI_O64: \
495 builtin_define ("_ABIO64=4"); \
496 builtin_define ("_MIPS_SIM=_ABIO64"); \
497 break; \
498 } \
499 \
500 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
501 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
502 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
503 builtin_define_with_int_value ("_MIPS_FPSET", \
504 32 / MAX_FPRS_PER_FMT); \
505 builtin_define_with_int_value ("_MIPS_SPFPSET", \
506 TARGET_ODD_SPREG ? 32 : 16); \
507 \
508 /* These defines reflect the ABI in use, not whether the \
509 FPU is directly accessible. */ \
510 if (TARGET_NO_FLOAT) \
511 builtin_define ("__mips_no_float"); \
512 else if (TARGET_HARD_FLOAT_ABI) \
513 builtin_define ("__mips_hard_float"); \
514 else \
515 builtin_define ("__mips_soft_float"); \
516 \
517 if (TARGET_SINGLE_FLOAT) \
518 builtin_define ("__mips_single_float"); \
519 \
520 if (TARGET_PAIRED_SINGLE_FLOAT) \
521 builtin_define ("__mips_paired_single_float"); \
522 \
523 if (mips_abs == MIPS_IEEE_754_2008) \
524 builtin_define ("__mips_abs2008"); \
525 \
526 if (mips_nan == MIPS_IEEE_754_2008) \
527 builtin_define ("__mips_nan2008"); \
528 \
529 if (TARGET_BIG_ENDIAN) \
530 { \
531 builtin_define_std ("MIPSEB"); \
532 builtin_define ("_MIPSEB"); \
533 } \
534 else \
535 { \
536 builtin_define_std ("MIPSEL"); \
537 builtin_define ("_MIPSEL"); \
538 } \
539 \
540 /* Whether calls should go through $25. The separate __PIC__ \
541 macro indicates whether abicalls code might use a GOT. */ \
542 if (TARGET_ABICALLS) \
543 builtin_define ("__mips_abicalls"); \
544 \
545 /* Whether Loongson vector modes are enabled. */ \
546 if (TARGET_LOONGSON_VECTORS) \
547 builtin_define ("__mips_loongson_vector_rev"); \
548 \
549 /* Historical Octeon macro. */ \
550 if (TARGET_OCTEON) \
551 builtin_define ("__OCTEON__"); \
552 \
553 if (TARGET_SYNCI) \
554 builtin_define ("__mips_synci"); \
555 \
556 /* Macros dependent on the C dialect. */ \
557 if (preprocessing_asm_p ()) \
558 { \
559 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
560 builtin_define ("_LANGUAGE_ASSEMBLY"); \
561 } \
562 else if (c_dialect_cxx ()) \
563 { \
564 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
565 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
566 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
567 } \
568 else \
569 { \
570 builtin_define_std ("LANGUAGE_C"); \
571 builtin_define ("_LANGUAGE_C"); \
572 } \
573 if (c_dialect_objc ()) \
574 { \
575 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
576 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
577 /* Bizarre, but retained for backwards compatibility. */ \
578 builtin_define_std ("LANGUAGE_C"); \
579 builtin_define ("_LANGUAGE_C"); \
580 } \
581 \
582 if (mips_abi == ABI_EABI) \
583 builtin_define ("__mips_eabi"); \
584 \
585 if (TARGET_CACHE_BUILTIN) \
586 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
587 } \
588 while (0)
589
590 /* Default target_flags if no switches are specified */
591
592 #ifndef TARGET_DEFAULT
593 #define TARGET_DEFAULT 0
594 #endif
595
596 #ifndef TARGET_CPU_DEFAULT
597 #define TARGET_CPU_DEFAULT 0
598 #endif
599
600 #ifndef TARGET_ENDIAN_DEFAULT
601 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
602 #endif
603
604 #ifdef IN_LIBGCC2
605 #undef TARGET_64BIT
606 /* Make this compile time constant for libgcc2 */
607 #ifdef __mips64
608 #define TARGET_64BIT 1
609 #else
610 #define TARGET_64BIT 0
611 #endif
612 #endif /* IN_LIBGCC2 */
613
614 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
615 when compiled with hardware floating point. This is because MIPS16
616 code cannot save and restore the floating-point registers, which is
617 important if in a mixed MIPS16/non-MIPS16 environment. */
618
619 #ifdef IN_LIBGCC2
620 #if __mips_hard_float
621 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
622 #endif
623 #endif /* IN_LIBGCC2 */
624
625 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
626
627 #ifndef MULTILIB_ENDIAN_DEFAULT
628 #if TARGET_ENDIAN_DEFAULT == 0
629 #define MULTILIB_ENDIAN_DEFAULT "EL"
630 #else
631 #define MULTILIB_ENDIAN_DEFAULT "EB"
632 #endif
633 #endif
634
635 #ifndef MULTILIB_ISA_DEFAULT
636 #if MIPS_ISA_DEFAULT == 1
637 #define MULTILIB_ISA_DEFAULT "mips1"
638 #elif MIPS_ISA_DEFAULT == 2
639 #define MULTILIB_ISA_DEFAULT "mips2"
640 #elif MIPS_ISA_DEFAULT == 3
641 #define MULTILIB_ISA_DEFAULT "mips3"
642 #elif MIPS_ISA_DEFAULT == 4
643 #define MULTILIB_ISA_DEFAULT "mips4"
644 #elif MIPS_ISA_DEFAULT == 32
645 #define MULTILIB_ISA_DEFAULT "mips32"
646 #elif MIPS_ISA_DEFAULT == 33
647 #define MULTILIB_ISA_DEFAULT "mips32r2"
648 #elif MIPS_ISA_DEFAULT == 37
649 #define MULTILIB_ISA_DEFAULT "mips32r6"
650 #elif MIPS_ISA_DEFAULT == 64
651 #define MULTILIB_ISA_DEFAULT "mips64"
652 #elif MIPS_ISA_DEFAULT == 65
653 #define MULTILIB_ISA_DEFAULT "mips64r2"
654 #elif MIPS_ISA_DEFAULT == 69
655 #define MULTILIB_ISA_DEFAULT "mips64r6"
656 #else
657 #define MULTILIB_ISA_DEFAULT "mips1"
658 #endif
659 #endif
660
661 #ifndef MIPS_ABI_DEFAULT
662 #define MIPS_ABI_DEFAULT ABI_32
663 #endif
664
665 /* Use the most portable ABI flag for the ASM specs. */
666
667 #if MIPS_ABI_DEFAULT == ABI_32
668 #define MULTILIB_ABI_DEFAULT "mabi=32"
669 #elif MIPS_ABI_DEFAULT == ABI_O64
670 #define MULTILIB_ABI_DEFAULT "mabi=o64"
671 #elif MIPS_ABI_DEFAULT == ABI_N32
672 #define MULTILIB_ABI_DEFAULT "mabi=n32"
673 #elif MIPS_ABI_DEFAULT == ABI_64
674 #define MULTILIB_ABI_DEFAULT "mabi=64"
675 #elif MIPS_ABI_DEFAULT == ABI_EABI
676 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
677 #endif
678
679 #ifndef MULTILIB_DEFAULTS
680 #define MULTILIB_DEFAULTS \
681 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
682 #endif
683
684 /* We must pass -EL to the linker by default for little endian embedded
685 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
686 linker will default to using big-endian output files. The OUTPUT_FORMAT
687 line must be in the linker script, otherwise -EB/-EL will not work. */
688
689 #ifndef ENDIAN_SPEC
690 #if TARGET_ENDIAN_DEFAULT == 0
691 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
692 #else
693 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
694 #endif
695 #endif
696
697 /* A spec condition that matches all non-mips16 -mips arguments. */
698
699 #define MIPS_ISA_LEVEL_OPTION_SPEC \
700 "mips1|mips2|mips3|mips4|mips32*|mips64*"
701
702 /* A spec condition that matches all non-mips16 architecture arguments. */
703
704 #define MIPS_ARCH_OPTION_SPEC \
705 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
706
707 /* A spec that infers a -mips argument from an -march argument,
708 or injects the default if no architecture is specified. */
709
710 #define MIPS_ISA_LEVEL_SPEC \
711 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
712 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
713 %{march=mips2|march=r6000:-mips2} \
714 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
715 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
716 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
717 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
718 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
719 |march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
720 %{march=mips32r3: -mips32r3} \
721 %{march=mips32r5|march=p5600: -mips32r5} \
722 %{march=mips32r6: -mips32r6} \
723 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
724 |march=xlr: -mips64} \
725 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
726 %{march=mips64r3: -mips64r3} \
727 %{march=mips64r5: -mips64r5} \
728 %{march=mips64r6: -mips64r6} \
729 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
730
731 /* A spec that infers a -mhard-float or -msoft-float setting from an
732 -march argument. Note that soft-float and hard-float code are not
733 link-compatible. */
734
735 #define MIPS_ARCH_FLOAT_SPEC \
736 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
737 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
738 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
739 |march=m14k*|march=octeon|march=xlr: -msoft-float; \
740 march=*: -mhard-float}"
741
742 /* A spec condition that matches 32-bit options. It only works if
743 MIPS_ISA_LEVEL_SPEC has been applied. */
744
745 #define MIPS_32BIT_OPTION_SPEC \
746 "mips1|mips2|mips32*|mgp32"
747
748 /* A spec condition that matches architectures should be targeted with
749 o32 FPXX for compatibility reasons. */
750 #define MIPS_FPXX_OPTION_SPEC \
751 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
752 mips64|mips64r2|mips64r3|mips64r5"
753
754 /* Infer a -msynci setting from a -mips argument, on the assumption that
755 -msynci is desired where possible. */
756 #define MIPS_ISA_SYNCI_SPEC \
757 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
758 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
759
760 #define MIPS_ISA_NAN2008_SPEC \
761 "%{mnan*:;mips32r6|mips64r6:-mnan=2008}"
762
763 #if (MIPS_ABI_DEFAULT == ABI_O64 \
764 || MIPS_ABI_DEFAULT == ABI_N32 \
765 || MIPS_ABI_DEFAULT == ABI_64)
766 #define OPT_ARCH64 "mabi=32|mgp32:;"
767 #define OPT_ARCH32 "mabi=32|mgp32"
768 #else
769 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
770 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
771 #endif
772
773 /* Support for a compile-time default CPU, et cetera. The rules are:
774 --with-arch is ignored if -march is specified or a -mips is specified
775 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
776 --with-tune is ignored if -mtune is specified; likewise
777 --with-tune-32 and --with-tune-64.
778 --with-abi is ignored if -mabi is specified.
779 --with-float is ignored if -mhard-float or -msoft-float are
780 specified.
781 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
782 specified.
783 --with-nan is ignored if -mnan is specified.
784 --with-fp-32 is ignored if -msoft-float, -msingle-float or -mfp are specified.
785 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
786 or -mno-odd-spreg are specified.
787 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
788 specified. */
789 #define OPTION_DEFAULT_SPECS \
790 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
791 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
792 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
793 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
794 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
795 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
796 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
797 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
798 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
799 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
800 {"fp_32", "%{" OPT_ARCH32 \
801 ":%{!msoft-float:%{!msingle-float:%{!mfp*:-mfp%(VALUE)}}}}" }, \
802 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
803 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
804 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
805 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
806 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
807 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
808
809 /* A spec that infers the -mdsp setting from an -march argument. */
810 #define BASE_DRIVER_SELF_SPECS \
811 MIPS_ISA_NAN2008_SPEC, \
812 "%{!mno-dsp: \
813 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k*: -mdsp} \
814 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
815
816 #define DRIVER_SELF_SPECS \
817 MIPS_ISA_LEVEL_SPEC, \
818 BASE_DRIVER_SELF_SPECS
819
820 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
821 && ISA_HAS_COND_TRAP)
822
823 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
824
825 /* True if the ABI can only work with 64-bit integer registers. We
826 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
827 otherwise floating-point registers must also be 64-bit. */
828 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
829
830 /* Likewise for 32-bit regs. */
831 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
832
833 /* True if the file format uses 64-bit symbols. At present, this is
834 only true for n64, which uses 64-bit ELF. */
835 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
836
837 /* True if symbols are 64 bits wide. This is usually determined by
838 the ABI's file format, but it can be overridden by -msym32. Note that
839 overriding the size with -msym32 changes the ABI of relocatable objects,
840 although it doesn't change the ABI of a fully-linked object. */
841 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
842 && Pmode == DImode \
843 && !TARGET_SYM32)
844
845 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
846 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
847 || ISA_MIPS4 \
848 || ISA_MIPS64 \
849 || ISA_MIPS64R2 \
850 || ISA_MIPS64R3 \
851 || ISA_MIPS64R5 \
852 || ISA_MIPS64R6)
853
854 #define ISA_HAS_JR (mips_isa_rev <= 5)
855
856 /* ISA has branch likely instructions (e.g. mips2). */
857 /* Disable branchlikely for tx39 until compare rewrite. They haven't
858 been generated up to this point. */
859 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
860
861 /* ISA has 32 single-precision registers. */
862 #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
863 && !TARGET_LOONGSON_3A) \
864 || TARGET_FLOAT64 \
865 || TARGET_MIPS5900)
866
867 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
868 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
869 || TARGET_MIPS5400 \
870 || TARGET_MIPS5500 \
871 || TARGET_MIPS5900 \
872 || TARGET_MIPS7000 \
873 || TARGET_MIPS9000 \
874 || TARGET_MAD \
875 || (mips_isa_rev >= 1 \
876 && mips_isa_rev <= 5)) \
877 && !TARGET_MIPS16)
878
879 /* ISA has a three-operand multiplication instruction. */
880 #define ISA_HAS_DMUL3 (TARGET_64BIT \
881 && TARGET_OCTEON \
882 && !TARGET_MIPS16)
883
884 /* ISA has HI and LO registers. */
885 #define ISA_HAS_HILO (mips_isa_rev <= 5)
886
887 /* ISA supports instructions DMULT and DMULTU. */
888 #define ISA_HAS_DMULT (TARGET_64BIT \
889 && !TARGET_MIPS5900 \
890 && mips_isa_rev <= 5)
891
892 /* ISA supports instructions MULT and MULTU. */
893 #define ISA_HAS_MULT (mips_isa_rev <= 5)
894
895 /* ISA supports instructions MUL, MULU, MUH, MUHU. */
896 #define ISA_HAS_R6MUL (mips_isa_rev >= 6)
897
898 /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
899 #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
900
901 /* ISA supports instructions DDIV and DDIVU. */
902 #define ISA_HAS_DDIV (TARGET_64BIT \
903 && !TARGET_MIPS5900 \
904 && mips_isa_rev <= 5)
905
906 /* ISA supports instructions DIV and DIVU.
907 This is always true, but the macro is needed for ISA_HAS_<D>DIV
908 in mips.md. */
909 #define ISA_HAS_DIV (mips_isa_rev <= 5)
910
911 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
912 || TARGET_LOONGSON_3A) \
913 && !TARGET_MIPS16)
914
915 /* ISA supports instructions DIV, DIVU, MOD and MODU. */
916 #define ISA_HAS_R6DIV (mips_isa_rev >= 6)
917
918 /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */
919 #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6)
920
921 /* ISA has the floating-point conditional move instructions introduced
922 in mips4. */
923 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
924 || (mips_isa_rev >= 1 \
925 && mips_isa_rev <= 5)) \
926 && !TARGET_MIPS5500 \
927 && !TARGET_MIPS16)
928
929 /* ISA has the integer conditional move instructions introduced in mips4 and
930 ST Loongson 2E/2F. */
931 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
932 || TARGET_MIPS5900 \
933 || TARGET_LOONGSON_2EF)
934
935 /* ISA has LDC1 and SDC1. */
936 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
937 && !TARGET_MIPS5900 \
938 && !TARGET_MIPS16)
939
940 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
941 branch on CC, and move (both FP and non-FP) on CC. */
942 #define ISA_HAS_8CC (ISA_MIPS4 \
943 || (mips_isa_rev >= 1 \
944 && mips_isa_rev <= 5))
945
946 /* ISA has the FP condition code instructions that store the flag in an
947 FP register. */
948 #define ISA_HAS_CCF (mips_isa_rev >= 6)
949
950 #define ISA_HAS_SEL (mips_isa_rev >= 6)
951
952 /* This is a catch all for other mips4 instructions: indexed load, the
953 FP madd and msub instructions, and the FP recip and recip sqrt
954 instructions. Note that this macro should only be used by other
955 ISA_HAS_* macros. */
956 #define ISA_HAS_FP4 ((ISA_MIPS4 \
957 || ISA_MIPS64 \
958 || (mips_isa_rev >= 2 \
959 && mips_isa_rev <= 5)) \
960 && !TARGET_MIPS16)
961
962 /* ISA has floating-point indexed load and store instructions
963 (LWXC1, LDXC1, SWXC1 and SDXC1). */
964 #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
965
966 /* ISA has paired-single instructions. */
967 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS64 \
968 || (mips_isa_rev >= 2 \
969 && mips_isa_rev <= 5))
970
971 /* ISA has conditional trap instructions. */
972 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
973 && !TARGET_MIPS16)
974
975 /* ISA has conditional trap with immediate instructions. */
976 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
977 && mips_isa_rev <= 5 \
978 && !TARGET_MIPS16)
979
980 /* ISA has integer multiply-accumulate instructions, madd and msub. */
981 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \
982 && mips_isa_rev <= 5)
983
984 /* Integer multiply-accumulate instructions should be generated. */
985 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
986
987 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
988 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
989
990 /* ISA has floating-point MADDF and MSUBF instructions 'd = d [+-] a * b'. */
991 #define ISA_HAS_FP_MADDF_MSUBF (mips_isa_rev >= 6)
992
993 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
994 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
995
996 /* ISA has floating-point nmadd and nmsub instructions
997 'd = -((a * b) [+-] c)'. */
998 #define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4
999
1000 /* ISA has floating-point nmadd and nmsub instructions
1001 'c = -((a * b) [+-] c)'. */
1002 #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF
1003
1004 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
1005 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
1006 doubles are stored in pairs of FPRs, so for safety's sake, we apply
1007 this restriction to the MIPS IV ISA too. */
1008 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
1009 (((ISA_HAS_FP4 \
1010 && ((MODE) == SFmode \
1011 || ((TARGET_FLOAT64 \
1012 || mips_isa_rev >= 2) \
1013 && (MODE) == DFmode))) \
1014 || (((MODE) == SFmode \
1015 || (MODE) == DFmode) \
1016 && (mips_isa_rev >= 6)) \
1017 || (TARGET_SB1 \
1018 && (MODE) == V2SFmode)) \
1019 && !TARGET_MIPS16)
1020
1021 #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16)
1022
1023 #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
1024
1025 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1026
1027 /* ISA has count leading zeroes/ones instruction (not implemented). */
1028 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
1029
1030 /* ISA has three operand multiply instructions that put
1031 the high part in an accumulator: mulhi or mulhiu. */
1032 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
1033 || TARGET_MIPS5500 \
1034 || TARGET_SR71K) \
1035 && !TARGET_MIPS16)
1036
1037 /* ISA has three operand multiply instructions that negate the
1038 result and put the result in an accumulator. */
1039 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
1040 || TARGET_MIPS5500 \
1041 || TARGET_SR71K) \
1042 && !TARGET_MIPS16)
1043
1044 /* ISA has three operand multiply instructions that subtract the
1045 result from a 4th operand and put the result in an accumulator. */
1046 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
1047 || TARGET_MIPS5500 \
1048 || TARGET_SR71K) \
1049 && !TARGET_MIPS16)
1050
1051 /* ISA has three operand multiply instructions that add the result
1052 to a 4th operand and put the result in an accumulator. */
1053 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
1054 || TARGET_MIPS4130 \
1055 || TARGET_MIPS5400 \
1056 || TARGET_MIPS5500 \
1057 || TARGET_SR71K) \
1058 && !TARGET_MIPS16)
1059
1060 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
1061 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
1062 || TARGET_MIPS4130) \
1063 && !TARGET_MIPS16)
1064
1065 /* ISA has the "ror" (rotate right) instructions. */
1066 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
1067 || TARGET_MIPS5400 \
1068 || TARGET_MIPS5500 \
1069 || TARGET_SR71K \
1070 || TARGET_SMARTMIPS) \
1071 && !TARGET_MIPS16)
1072
1073 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1074 64-bit targets also provide DSBH and DSHD. */
1075 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1076
1077 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1078 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1079 || TARGET_LOONGSON_2EF \
1080 || TARGET_MIPS5900 \
1081 || mips_isa_rev >= 1) \
1082 && !TARGET_MIPS16)
1083
1084 /* ISA has data prefetch with limited 9-bit displacement. */
1085 #define ISA_HAS_PREFETCH_9BIT (mips_isa_rev >= 6)
1086
1087 /* ISA has data indexed prefetch instructions. This controls use of
1088 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1089 (prefx is a cop1x instruction, so can only be used if FP is
1090 enabled.) */
1091 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
1092
1093 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1094 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1095 also requires TARGET_DOUBLE_FLOAT. */
1096 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1097
1098 /* ISA includes the MIPS32r2 seb and seh instructions. */
1099 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1100
1101 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1102 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1103
1104 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1105 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1106 && mips_isa_rev >= 2)
1107
1108 /* ISA has lwxs instruction (load w/scaled index address. */
1109 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1110 && !TARGET_MIPS16)
1111
1112 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1113 #define ISA_HAS_LBX (TARGET_OCTEON2)
1114 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1115 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1116 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1117 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1118 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1119 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1120 && TARGET_64BIT)
1121
1122 /* The DSP ASE is available. */
1123 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1124
1125 /* Revision 2 of the DSP ASE is available. */
1126 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1127
1128 /* True if the result of a load is not available to the next instruction.
1129 A nop will then be needed between instructions like "lw $4,..."
1130 and "addiu $4,$4,1". */
1131 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1132 && !TARGET_MIPS3900 \
1133 && !TARGET_MIPS5900 \
1134 && !TARGET_MIPS16 \
1135 && !TARGET_MICROMIPS)
1136
1137 /* Likewise mtc1 and mfc1. */
1138 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1139 && !TARGET_MIPS5900 \
1140 && !TARGET_LOONGSON_2EF)
1141
1142 /* Likewise floating-point comparisons. */
1143 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1144 && !TARGET_MIPS5900 \
1145 && !TARGET_LOONGSON_2EF)
1146
1147 /* True if mflo and mfhi can be immediately followed by instructions
1148 which write to the HI and LO registers.
1149
1150 According to MIPS specifications, MIPS ISAs I, II, and III need
1151 (at least) two instructions between the reads of HI/LO and
1152 instructions which write them, and later ISAs do not. Contradicting
1153 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1154 the UM for the NEC Vr5000) document needing the instructions between
1155 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1156 MIPS64 and later ISAs to have the interlocks, plus any specific
1157 earlier-ISA CPUs for which CPU documentation declares that the
1158 instructions are really interlocked. */
1159 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1160 || TARGET_MIPS5500 \
1161 || TARGET_MIPS5900 \
1162 || TARGET_LOONGSON_2EF)
1163
1164 /* ISA includes synci, jr.hb and jalr.hb. */
1165 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1166
1167 /* ISA includes sync. */
1168 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1169 #define GENERATE_SYNC \
1170 (target_flags_explicit & MASK_LLSC \
1171 ? TARGET_LLSC && !TARGET_MIPS16 \
1172 : ISA_HAS_SYNC)
1173
1174 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1175 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1176 instructions. */
1177 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1178 #define GENERATE_LL_SC \
1179 (target_flags_explicit & MASK_LLSC \
1180 ? TARGET_LLSC && !TARGET_MIPS16 \
1181 : ISA_HAS_LL_SC)
1182
1183 #define ISA_HAS_SWAP (TARGET_XLP)
1184 #define ISA_HAS_LDADD (TARGET_XLP)
1185
1186 /* ISA includes the baddu instruction. */
1187 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1188
1189 /* ISA includes the bbit* instructions. */
1190 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1191
1192 /* ISA includes the cins instruction. */
1193 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1194
1195 /* ISA includes the exts instruction. */
1196 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1197
1198 /* ISA includes the seq and sne instructions. */
1199 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1200
1201 /* ISA includes the pop instruction. */
1202 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1203
1204 /* The CACHE instruction is available in non-MIPS16 code. */
1205 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1206
1207 /* The CACHE instruction is available. */
1208 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1209 \f
1210 /* Tell collect what flags to pass to nm. */
1211 #ifndef NM_FLAGS
1212 #define NM_FLAGS "-Bn"
1213 #endif
1214
1215 \f
1216 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1217 the assembler. It may be overridden by subtargets.
1218
1219 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1220 COFF debugging info. */
1221
1222 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1223 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1224 %{g} %{g0} %{g1} %{g2} %{g3} \
1225 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1226 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1227 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1228 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1229 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1230 #endif
1231
1232 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1233 overridden by subtargets. */
1234
1235 #ifndef SUBTARGET_ASM_SPEC
1236 #define SUBTARGET_ASM_SPEC ""
1237 #endif
1238
1239 #undef ASM_SPEC
1240 #define ASM_SPEC "\
1241 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1242 %{mips32*} %{mips64*} \
1243 %{mips16} %{mno-mips16:-no-mips16} \
1244 %{mmicromips} %{mno-micromips} \
1245 %{mips3d} %{mno-mips3d:-no-mips3d} \
1246 %{mdmx} %{mno-mdmx:-no-mdmx} \
1247 %{mdsp} %{mno-dsp} \
1248 %{mdspr2} %{mno-dspr2} \
1249 %{mmcu} %{mno-mcu} \
1250 %{meva} %{mno-eva} \
1251 %{mvirt} %{mno-virt} \
1252 %{mxpa} %{mno-xpa} \
1253 %{msmartmips} %{mno-smartmips} \
1254 %{mmt} %{mno-mt} \
1255 %{mfix-rm7000} %{mno-fix-rm7000} \
1256 %{mfix-vr4120} %{mfix-vr4130} \
1257 %{mfix-24k} \
1258 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1259 %(subtarget_asm_debugging_spec) \
1260 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1261 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1262 %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \
1263 %{modd-spreg} %{mno-odd-spreg} \
1264 %{mshared} %{mno-shared} \
1265 %{msym32} %{mno-sym32} \
1266 %{mtune=*} \
1267 %{mhard-float} %{msoft-float} \
1268 %{msingle-float} %{mdouble-float} \
1269 %(subtarget_asm_spec)"
1270
1271 /* Extra switches sometimes passed to the linker. */
1272
1273 #ifndef LINK_SPEC
1274 #define LINK_SPEC "\
1275 %(endian_spec) \
1276 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1277 %{shared}"
1278 #endif /* LINK_SPEC defined */
1279
1280
1281 /* Specs for the compiler proper */
1282
1283 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1284 overridden by subtargets. */
1285 #ifndef SUBTARGET_CC1_SPEC
1286 #define SUBTARGET_CC1_SPEC ""
1287 #endif
1288
1289 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1290
1291 #undef CC1_SPEC
1292 #define CC1_SPEC "\
1293 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1294 %(subtarget_cc1_spec)"
1295
1296 /* Preprocessor specs. */
1297
1298 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1299 overridden by subtargets. */
1300 #ifndef SUBTARGET_CPP_SPEC
1301 #define SUBTARGET_CPP_SPEC ""
1302 #endif
1303
1304 #define CPP_SPEC "%(subtarget_cpp_spec)"
1305
1306 /* This macro defines names of additional specifications to put in the specs
1307 that can be used in various specifications like CC1_SPEC. Its definition
1308 is an initializer with a subgrouping for each command option.
1309
1310 Each subgrouping contains a string constant, that defines the
1311 specification name, and a string constant that used by the GCC driver
1312 program.
1313
1314 Do not define this macro if it does not need to do anything. */
1315
1316 #define EXTRA_SPECS \
1317 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1318 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1319 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1320 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1321 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1322 { "endian_spec", ENDIAN_SPEC }, \
1323 SUBTARGET_EXTRA_SPECS
1324
1325 #ifndef SUBTARGET_EXTRA_SPECS
1326 #define SUBTARGET_EXTRA_SPECS
1327 #endif
1328 \f
1329 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1330 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1331
1332 #ifndef PREFERRED_DEBUGGING_TYPE
1333 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1334 #endif
1335
1336 /* The size of DWARF addresses should be the same as the size of symbols
1337 in the target file format. They shouldn't depend on things like -msym32,
1338 because many DWARF consumers do not allow the mixture of address sizes
1339 that one would then get from linking -msym32 code with -msym64 code.
1340
1341 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1342 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1343 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1344
1345 /* By default, turn on GDB extensions. */
1346 #define DEFAULT_GDB_EXTENSIONS 1
1347
1348 /* Registers may have a prefix which can be ignored when matching
1349 user asm and register definitions. */
1350 #ifndef REGISTER_PREFIX
1351 #define REGISTER_PREFIX "$"
1352 #endif
1353
1354 /* Local compiler-generated symbols must have a prefix that the assembler
1355 understands. By default, this is $, although some targets (e.g.,
1356 NetBSD-ELF) need to override this. */
1357
1358 #ifndef LOCAL_LABEL_PREFIX
1359 #define LOCAL_LABEL_PREFIX "$"
1360 #endif
1361
1362 /* By default on the mips, external symbols do not have an underscore
1363 prepended, but some targets (e.g., NetBSD) require this. */
1364
1365 #ifndef USER_LABEL_PREFIX
1366 #define USER_LABEL_PREFIX ""
1367 #endif
1368
1369 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1370 since the length can run past this up to a continuation point. */
1371 #undef DBX_CONTIN_LENGTH
1372 #define DBX_CONTIN_LENGTH 1500
1373
1374 /* How to renumber registers for dbx and gdb. */
1375 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1376
1377 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1378 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1379
1380 /* The DWARF 2 CFA column which tracks the return address. */
1381 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1382
1383 /* Before the prologue, RA lives in r31. */
1384 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1385
1386 /* Describe how we implement __builtin_eh_return. */
1387 #define EH_RETURN_DATA_REGNO(N) \
1388 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1389
1390 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1391
1392 #define EH_USES(N) mips_eh_uses (N)
1393
1394 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1395 The default for this in 64-bit mode is 8, which causes problems with
1396 SFmode register saves. */
1397 #define DWARF_CIE_DATA_ALIGNMENT -4
1398
1399 /* Correct the offset of automatic variables and arguments. Note that
1400 the MIPS debug format wants all automatic variables and arguments
1401 to be in terms of the virtual frame pointer (stack pointer before
1402 any adjustment in the function), while the MIPS 3.0 linker wants
1403 the frame pointer to be the stack pointer after the initial
1404 adjustment. */
1405
1406 #define DEBUGGER_AUTO_OFFSET(X) \
1407 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1408 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1409 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1410 \f
1411 /* Target machine storage layout */
1412
1413 #define BITS_BIG_ENDIAN 0
1414 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1415 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1416
1417 #define MAX_BITS_PER_WORD 64
1418
1419 /* Width of a word, in units (bytes). */
1420 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1421 #ifndef IN_LIBGCC2
1422 #define MIN_UNITS_PER_WORD 4
1423 #endif
1424
1425 /* For MIPS, width of a floating point register. */
1426 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1427
1428 /* The number of consecutive floating-point registers needed to store the
1429 largest format supported by the FPU. */
1430 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1431
1432 /* The number of consecutive floating-point registers needed to store the
1433 smallest format supported by the FPU. */
1434 #define MIN_FPRS_PER_FMT \
1435 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT)
1436
1437 /* The largest size of value that can be held in floating-point
1438 registers and moved with a single instruction. */
1439 #define UNITS_PER_HWFPVALUE \
1440 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1441
1442 /* The largest size of value that can be held in floating-point
1443 registers. */
1444 #define UNITS_PER_FPVALUE \
1445 (TARGET_SOFT_FLOAT_ABI ? 0 \
1446 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1447 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1448
1449 /* The number of bytes in a double. */
1450 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1451
1452 /* Set the sizes of the core types. */
1453 #define SHORT_TYPE_SIZE 16
1454 #define INT_TYPE_SIZE 32
1455 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1456 #define LONG_LONG_TYPE_SIZE 64
1457
1458 #define FLOAT_TYPE_SIZE 32
1459 #define DOUBLE_TYPE_SIZE 64
1460 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1461
1462 /* Define the sizes of fixed-point types. */
1463 #define SHORT_FRACT_TYPE_SIZE 8
1464 #define FRACT_TYPE_SIZE 16
1465 #define LONG_FRACT_TYPE_SIZE 32
1466 #define LONG_LONG_FRACT_TYPE_SIZE 64
1467
1468 #define SHORT_ACCUM_TYPE_SIZE 16
1469 #define ACCUM_TYPE_SIZE 32
1470 #define LONG_ACCUM_TYPE_SIZE 64
1471 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1472 doesn't support 128-bit integers for MIPS32 currently. */
1473 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1474
1475 /* long double is not a fixed mode, but the idea is that, if we
1476 support long double, we also want a 128-bit integer type. */
1477 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1478
1479 /* Width in bits of a pointer. */
1480 #ifndef POINTER_SIZE
1481 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1482 #endif
1483
1484 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1485 #define PARM_BOUNDARY BITS_PER_WORD
1486
1487 /* Allocation boundary (in *bits*) for the code of a function. */
1488 #define FUNCTION_BOUNDARY 32
1489
1490 /* Alignment of field after `int : 0' in a structure. */
1491 #define EMPTY_FIELD_BOUNDARY 32
1492
1493 /* Every structure's size must be a multiple of this. */
1494 /* 8 is observed right on a DECstation and on riscos 4.02. */
1495 #define STRUCTURE_SIZE_BOUNDARY 8
1496
1497 /* There is no point aligning anything to a rounder boundary than this. */
1498 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1499
1500 /* All accesses must be aligned. */
1501 #define STRICT_ALIGNMENT 1
1502
1503 /* Define this if you wish to imitate the way many other C compilers
1504 handle alignment of bitfields and the structures that contain
1505 them.
1506
1507 The behavior is that the type written for a bit-field (`int',
1508 `short', or other integer type) imposes an alignment for the
1509 entire structure, as if the structure really did contain an
1510 ordinary field of that type. In addition, the bit-field is placed
1511 within the structure so that it would fit within such a field,
1512 not crossing a boundary for it.
1513
1514 Thus, on most machines, a bit-field whose type is written as `int'
1515 would not cross a four-byte boundary, and would force four-byte
1516 alignment for the whole structure. (The alignment used may not
1517 be four bytes; it is controlled by the other alignment
1518 parameters.)
1519
1520 If the macro is defined, its definition should be a C expression;
1521 a nonzero value for the expression enables this behavior. */
1522
1523 #define PCC_BITFIELD_TYPE_MATTERS 1
1524
1525 /* If defined, a C expression to compute the alignment given to a
1526 constant that is being placed in memory. CONSTANT is the constant
1527 and ALIGN is the alignment that the object would ordinarily have.
1528 The value of this macro is used instead of that alignment to align
1529 the object.
1530
1531 If this macro is not defined, then ALIGN is used.
1532
1533 The typical use of this macro is to increase alignment for string
1534 constants to be word aligned so that `strcpy' calls that copy
1535 constants can be done inline. */
1536
1537 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1538 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1539 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1540
1541 /* If defined, a C expression to compute the alignment for a static
1542 variable. TYPE is the data type, and ALIGN is the alignment that
1543 the object would ordinarily have. The value of this macro is used
1544 instead of that alignment to align the object.
1545
1546 If this macro is not defined, then ALIGN is used.
1547
1548 One use of this macro is to increase alignment of medium-size
1549 data to make it all fit in fewer cache lines. Another is to
1550 cause character arrays to be word-aligned so that `strcpy' calls
1551 that copy constants to character arrays can be done inline. */
1552
1553 #undef DATA_ALIGNMENT
1554 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1555 ((((ALIGN) < BITS_PER_WORD) \
1556 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1557 || TREE_CODE (TYPE) == UNION_TYPE \
1558 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1559
1560 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1561 character arrays to be word-aligned so that `strcpy' calls that copy
1562 constants to character arrays can be done inline, and 'strcmp' can be
1563 optimised to use word loads. */
1564 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1565 DATA_ALIGNMENT (TYPE, ALIGN)
1566
1567 #define PAD_VARARGS_DOWN \
1568 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1569
1570 /* Define if operations between registers always perform the operation
1571 on the full register even if a narrower mode is specified. */
1572 #define WORD_REGISTER_OPERATIONS
1573
1574 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1575 moves. All other references are zero extended. */
1576 #define LOAD_EXTEND_OP(MODE) \
1577 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1578 ? SIGN_EXTEND : ZERO_EXTEND)
1579
1580 /* Define this macro if it is advisable to hold scalars in registers
1581 in a wider mode than that declared by the program. In such cases,
1582 the value is constrained to be within the bounds of the declared
1583 type, but kept valid in the wider mode. The signedness of the
1584 extension may differ from that of the type. */
1585
1586 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1587 if (GET_MODE_CLASS (MODE) == MODE_INT \
1588 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1589 { \
1590 if ((MODE) == SImode) \
1591 (UNSIGNEDP) = 0; \
1592 (MODE) = Pmode; \
1593 }
1594
1595 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1596 Extensions of pointers to word_mode must be signed. */
1597 #define POINTERS_EXTEND_UNSIGNED false
1598
1599 /* Define if loading short immediate values into registers sign extends. */
1600 #define SHORT_IMMEDIATES_SIGN_EXTEND
1601
1602 /* The [d]clz instructions have the natural values at 0. */
1603
1604 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1605 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1606 \f
1607 /* Standard register usage. */
1608
1609 /* Number of hardware registers. We have:
1610
1611 - 32 integer registers
1612 - 32 floating point registers
1613 - 8 condition code registers
1614 - 2 accumulator registers (hi and lo)
1615 - 32 registers each for coprocessors 0, 2 and 3
1616 - 4 fake registers:
1617 - ARG_POINTER_REGNUM
1618 - FRAME_POINTER_REGNUM
1619 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1620 - CPRESTORE_SLOT_REGNUM
1621 - 2 dummy entries that were used at various times in the past.
1622 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1623 - 6 DSP control registers */
1624
1625 #define FIRST_PSEUDO_REGISTER 188
1626
1627 /* By default, fix the kernel registers ($26 and $27), the global
1628 pointer ($28) and the stack pointer ($29). This can change
1629 depending on the command-line options.
1630
1631 Regarding coprocessor registers: without evidence to the contrary,
1632 it's best to assume that each coprocessor register has a unique
1633 use. This can be overridden, in, e.g., mips_option_override or
1634 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1635 inappropriate for a particular target. */
1636
1637 #define FIXED_REGISTERS \
1638 { \
1639 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1640 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1641 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1642 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1643 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1644 /* COP0 registers */ \
1645 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1646 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1647 /* COP2 registers */ \
1648 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1649 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1650 /* COP3 registers */ \
1651 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1652 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1653 /* 6 DSP accumulator registers & 6 control registers */ \
1654 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1655 }
1656
1657
1658 /* Set up this array for o32 by default.
1659
1660 Note that we don't mark $31 as a call-clobbered register. The idea is
1661 that it's really the call instructions themselves which clobber $31.
1662 We don't care what the called function does with it afterwards.
1663
1664 This approach makes it easier to implement sibcalls. Unlike normal
1665 calls, sibcalls don't clobber $31, so the register reaches the
1666 called function in tact. EPILOGUE_USES says that $31 is useful
1667 to the called function. */
1668
1669 #define CALL_USED_REGISTERS \
1670 { \
1671 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1672 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1673 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1674 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1675 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1676 /* COP0 registers */ \
1677 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1678 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1679 /* COP2 registers */ \
1680 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1681 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1682 /* COP3 registers */ \
1683 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1684 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1685 /* 6 DSP accumulator registers & 6 control registers */ \
1686 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1687 }
1688
1689
1690 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1691
1692 #define CALL_REALLY_USED_REGISTERS \
1693 { /* General registers. */ \
1694 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1695 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1696 /* Floating-point registers. */ \
1697 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1698 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1699 /* Others. */ \
1700 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1701 /* COP0 registers */ \
1702 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1703 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1704 /* COP2 registers */ \
1705 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1706 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1707 /* COP3 registers */ \
1708 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1709 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1710 /* 6 DSP accumulator registers & 6 control registers */ \
1711 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1712 }
1713
1714 /* Internal macros to classify a register number as to whether it's a
1715 general purpose register, a floating point register, a
1716 multiply/divide register, or a status register. */
1717
1718 #define GP_REG_FIRST 0
1719 #define GP_REG_LAST 31
1720 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1721 #define GP_DBX_FIRST 0
1722 #define K0_REG_NUM (GP_REG_FIRST + 26)
1723 #define K1_REG_NUM (GP_REG_FIRST + 27)
1724 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1725
1726 #define FP_REG_FIRST 32
1727 #define FP_REG_LAST 63
1728 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1729 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1730
1731 #define MD_REG_FIRST 64
1732 #define MD_REG_LAST 65
1733 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1734 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1735
1736 /* The DWARF 2 CFA column which tracks the return address from a
1737 signal handler context. This means that to maintain backwards
1738 compatibility, no hard register can be assigned this column if it
1739 would need to be handled by the DWARF unwinder. */
1740 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1741
1742 #define ST_REG_FIRST 67
1743 #define ST_REG_LAST 74
1744 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1745
1746
1747 /* FIXME: renumber. */
1748 #define COP0_REG_FIRST 80
1749 #define COP0_REG_LAST 111
1750 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1751
1752 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1753 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1754 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1755
1756 #define COP2_REG_FIRST 112
1757 #define COP2_REG_LAST 143
1758 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1759
1760 #define COP3_REG_FIRST 144
1761 #define COP3_REG_LAST 175
1762 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1763
1764 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1765 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1766 #define ALL_COP_REG_LAST COP3_REG_LAST
1767 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1768
1769 #define DSP_ACC_REG_FIRST 176
1770 #define DSP_ACC_REG_LAST 181
1771 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1772
1773 #define AT_REGNUM (GP_REG_FIRST + 1)
1774 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1775 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1776
1777 /* A few bitfield locations for the coprocessor registers. */
1778 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1779 the cause register for the EIC interrupt mode. */
1780 #define CAUSE_IPL 10
1781 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1782 #define SR_IPL 10
1783 /* Exception Level is at bit 1 of the status register. */
1784 #define SR_EXL 1
1785 /* Interrupt Enable is at bit 0 of the status register. */
1786 #define SR_IE 0
1787
1788 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1789 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1790 should be used instead. */
1791 #define FPSW_REGNUM ST_REG_FIRST
1792
1793 #define GP_REG_P(REGNO) \
1794 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1795 #define M16_REG_P(REGNO) \
1796 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1797 #define M16STORE_REG_P(REGNO) \
1798 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1799 #define FP_REG_P(REGNO) \
1800 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1801 #define MD_REG_P(REGNO) \
1802 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1803 #define ST_REG_P(REGNO) \
1804 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1805 #define COP0_REG_P(REGNO) \
1806 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1807 #define COP2_REG_P(REGNO) \
1808 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1809 #define COP3_REG_P(REGNO) \
1810 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1811 #define ALL_COP_REG_P(REGNO) \
1812 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1813 /* Test if REGNO is one of the 6 new DSP accumulators. */
1814 #define DSP_ACC_REG_P(REGNO) \
1815 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1816 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1817 #define ACC_REG_P(REGNO) \
1818 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1819
1820 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1821
1822 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1823 to initialize the mips16 gp pseudo register. */
1824 #define CONST_GP_P(X) \
1825 (GET_CODE (X) == CONST \
1826 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1827 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1828
1829 /* Return coprocessor number from register number. */
1830
1831 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1832 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1833 : COP3_REG_P (REGNO) ? '3' : '?')
1834
1835
1836 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1837
1838 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1839 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1840
1841 /* Select a register mode required for caller save of hard regno REGNO. */
1842 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1843 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
1844
1845 /* Odd-numbered single-precision registers are not considered callee-saved
1846 for o32 FPXX as they will be clobbered when run on an FR=1 FPU. */
1847 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1848 (TARGET_FLOATXX && hard_regno_nregs[REGNO][MODE] == 1 \
1849 && FP_REG_P (REGNO) && ((REGNO) & 1))
1850
1851 #define MODES_TIEABLE_P mips_modes_tieable_p
1852
1853 /* Register to use for pushing function arguments. */
1854 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1855
1856 /* These two registers don't really exist: they get eliminated to either
1857 the stack or hard frame pointer. */
1858 #define ARG_POINTER_REGNUM 77
1859 #define FRAME_POINTER_REGNUM 78
1860
1861 /* $30 is not available on the mips16, so we use $17 as the frame
1862 pointer. */
1863 #define HARD_FRAME_POINTER_REGNUM \
1864 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1865
1866 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1867 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1868
1869 /* Register in which static-chain is passed to a function. */
1870 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1871
1872 /* Registers used as temporaries in prologue/epilogue code:
1873
1874 - If a MIPS16 PIC function needs access to _gp, it first loads
1875 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1876
1877 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1878 register. The register must not conflict with MIPS16_PIC_TEMP.
1879
1880 - If we aren't generating MIPS16 code, the prologue can also use
1881 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1882
1883 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1884 register.
1885
1886 If we're generating MIPS16 code, these registers must come from the
1887 core set of 8. The prologue registers mustn't conflict with any
1888 incoming arguments, the static chain pointer, or the frame pointer.
1889 The epilogue temporary mustn't conflict with the return registers,
1890 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1891 or the EH data registers.
1892
1893 If we're generating interrupt handlers, we use K0 as a temporary register
1894 in prologue/epilogue code. */
1895
1896 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1897 #define MIPS_PROLOGUE_TEMP_REGNUM \
1898 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1899 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1900 (TARGET_MIPS16 \
1901 ? (gcc_unreachable (), INVALID_REGNUM) \
1902 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1903 #define MIPS_EPILOGUE_TEMP_REGNUM \
1904 (cfun->machine->interrupt_handler_p \
1905 ? K0_REG_NUM \
1906 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1907
1908 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1909 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1910 #define MIPS_PROLOGUE_TEMP2(MODE) \
1911 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1912 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1913
1914 /* Define this macro if it is as good or better to call a constant
1915 function address than to call an address kept in a register. */
1916 #define NO_FUNCTION_CSE 1
1917
1918 /* The ABI-defined global pointer. Sometimes we use a different
1919 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1920 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1921
1922 /* We normally use $28 as the global pointer. However, when generating
1923 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1924 register instead. They can then avoid saving and restoring $28
1925 and perhaps avoid using a frame at all.
1926
1927 When a leaf function uses something other than $28, mips_expand_prologue
1928 will modify pic_offset_table_rtx in place. Take the register number
1929 from there after reload. */
1930 #define PIC_OFFSET_TABLE_REGNUM \
1931 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1932 \f
1933 /* Define the classes of registers for register constraints in the
1934 machine description. Also define ranges of constants.
1935
1936 One of the classes must always be named ALL_REGS and include all hard regs.
1937 If there is more than one class, another class must be named NO_REGS
1938 and contain no registers.
1939
1940 The name GENERAL_REGS must be the name of a class (or an alias for
1941 another name such as ALL_REGS). This is the class of registers
1942 that is allowed by "g" or "r" in a register constraint.
1943 Also, registers outside this class are allocated only when
1944 instructions express preferences for them.
1945
1946 The classes must be numbered in nondecreasing order; that is,
1947 a larger-numbered class must never be contained completely
1948 in a smaller-numbered class.
1949
1950 For any two classes, it is very desirable that there be another
1951 class that represents their union. */
1952
1953 enum reg_class
1954 {
1955 NO_REGS, /* no registers in set */
1956 M16_STORE_REGS, /* microMIPS store registers */
1957 M16_REGS, /* mips16 directly accessible registers */
1958 M16_SP_REGS, /* mips16 + $sp */
1959 T_REG, /* mips16 T register ($24) */
1960 M16_T_REGS, /* mips16 registers plus T register */
1961 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1962 V1_REG, /* Register $v1 ($3) used for TLS access. */
1963 SPILL_REGS, /* All but $sp and call preserved regs are in here */
1964 LEA_REGS, /* Every GPR except $25 */
1965 GR_REGS, /* integer registers */
1966 FP_REGS, /* floating point registers */
1967 MD0_REG, /* first multiply/divide register */
1968 MD1_REG, /* second multiply/divide register */
1969 MD_REGS, /* multiply/divide registers (hi/lo) */
1970 COP0_REGS, /* generic coprocessor classes */
1971 COP2_REGS,
1972 COP3_REGS,
1973 ST_REGS, /* status registers (fp status) */
1974 DSP_ACC_REGS, /* DSP accumulator registers */
1975 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1976 FRAME_REGS, /* $arg and $frame */
1977 GR_AND_MD0_REGS, /* union classes */
1978 GR_AND_MD1_REGS,
1979 GR_AND_MD_REGS,
1980 GR_AND_ACC_REGS,
1981 ALL_REGS, /* all registers */
1982 LIM_REG_CLASSES /* max value + 1 */
1983 };
1984
1985 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1986
1987 #define GENERAL_REGS GR_REGS
1988
1989 /* An initializer containing the names of the register classes as C
1990 string constants. These names are used in writing some of the
1991 debugging dumps. */
1992
1993 #define REG_CLASS_NAMES \
1994 { \
1995 "NO_REGS", \
1996 "M16_STORE_REGS", \
1997 "M16_REGS", \
1998 "M16_SP_REGS", \
1999 "T_REG", \
2000 "M16_T_REGS", \
2001 "PIC_FN_ADDR_REG", \
2002 "V1_REG", \
2003 "SPILL_REGS", \
2004 "LEA_REGS", \
2005 "GR_REGS", \
2006 "FP_REGS", \
2007 "MD0_REG", \
2008 "MD1_REG", \
2009 "MD_REGS", \
2010 /* coprocessor registers */ \
2011 "COP0_REGS", \
2012 "COP2_REGS", \
2013 "COP3_REGS", \
2014 "ST_REGS", \
2015 "DSP_ACC_REGS", \
2016 "ACC_REGS", \
2017 "FRAME_REGS", \
2018 "GR_AND_MD0_REGS", \
2019 "GR_AND_MD1_REGS", \
2020 "GR_AND_MD_REGS", \
2021 "GR_AND_ACC_REGS", \
2022 "ALL_REGS" \
2023 }
2024
2025 /* An initializer containing the contents of the register classes,
2026 as integers which are bit masks. The Nth integer specifies the
2027 contents of class N. The way the integer MASK is interpreted is
2028 that register R is in the class if `MASK & (1 << R)' is 1.
2029
2030 When the machine has more than 32 registers, an integer does not
2031 suffice. Then the integers are replaced by sub-initializers,
2032 braced groupings containing several integers. Each
2033 sub-initializer must be suitable as an initializer for the type
2034 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2035
2036 #define REG_CLASS_CONTENTS \
2037 { \
2038 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
2039 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
2040 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
2041 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
2042 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
2043 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
2044 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
2045 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
2046 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
2047 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
2048 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
2049 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
2050 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
2051 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
2052 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
2053 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
2054 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
2055 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
2056 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
2057 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
2058 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
2059 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
2060 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
2061 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
2062 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
2063 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
2064 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
2065 }
2066
2067
2068 /* A C expression whose value is a register class containing hard
2069 register REGNO. In general there is more that one such class;
2070 choose a class which is "minimal", meaning that no smaller class
2071 also contains the register. */
2072
2073 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2074
2075 /* A macro whose definition is the name of the class to which a
2076 valid base register must belong. A base register is one used in
2077 an address which is the register value plus a displacement. */
2078
2079 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
2080
2081 /* A macro whose definition is the name of the class to which a
2082 valid index register must belong. An index register is one used
2083 in an address where its value is either multiplied by a scale
2084 factor or added to another register (as well as added to a
2085 displacement). */
2086
2087 #define INDEX_REG_CLASS NO_REGS
2088
2089 /* We generally want to put call-clobbered registers ahead of
2090 call-saved ones. (IRA expects this.) */
2091
2092 #define REG_ALLOC_ORDER \
2093 { /* Accumulator registers. When GPRs and accumulators have equal \
2094 cost, we generally prefer to use accumulators. For example, \
2095 a division of multiplication result is better allocated to LO, \
2096 so that we put the MFLO at the point of use instead of at the \
2097 point of definition. It's also needed if we're to take advantage \
2098 of the extra accumulators available with -mdspr2. In some cases, \
2099 it can also help to reduce register pressure. */ \
2100 64, 65,176,177,178,179,180,181, \
2101 /* Call-clobbered GPRs. */ \
2102 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2103 24, 25, 31, \
2104 /* The global pointer. This is call-clobbered for o32 and o64 \
2105 abicalls, call-saved for n32 and n64 abicalls, and a program \
2106 invariant otherwise. Putting it between the call-clobbered \
2107 and call-saved registers should cope with all eventualities. */ \
2108 28, \
2109 /* Call-saved GPRs. */ \
2110 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2111 /* GPRs that can never be exposed to the register allocator. */ \
2112 0, 26, 27, 29, \
2113 /* Call-clobbered FPRs. */ \
2114 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2115 48, 49, 50, 51, \
2116 /* FPRs that are usually call-saved. The odd ones are actually \
2117 call-clobbered for n32, but listing them ahead of the even \
2118 registers might encourage the register allocator to fragment \
2119 the available FPR pairs. We need paired FPRs to store long \
2120 doubles, so it isn't clear that using a different order \
2121 for n32 would be a win. */ \
2122 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2123 /* None of the remaining classes have defined call-saved \
2124 registers. */ \
2125 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2126 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2127 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2128 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2129 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2130 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2131 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2132 182,183,184,185,186,187 \
2133 }
2134
2135 /* True if VALUE is an unsigned 6-bit number. */
2136
2137 #define UIMM6_OPERAND(VALUE) \
2138 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2139
2140 /* True if VALUE is a signed 10-bit number. */
2141
2142 #define IMM10_OPERAND(VALUE) \
2143 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2144
2145 /* True if VALUE is a signed 16-bit number. */
2146
2147 #define SMALL_OPERAND(VALUE) \
2148 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2149
2150 /* True if VALUE is an unsigned 16-bit number. */
2151
2152 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2153 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2154
2155 /* True if VALUE can be loaded into a register using LUI. */
2156
2157 #define LUI_OPERAND(VALUE) \
2158 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2159 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2160
2161 /* Return a value X with the low 16 bits clear, and such that
2162 VALUE - X is a signed 16-bit value. */
2163
2164 #define CONST_HIGH_PART(VALUE) \
2165 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2166
2167 #define CONST_LOW_PART(VALUE) \
2168 ((VALUE) - CONST_HIGH_PART (VALUE))
2169
2170 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2171 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2172 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2173 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2174 #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
2175
2176 /* The HI and LO registers can only be reloaded via the general
2177 registers. Condition code registers can only be loaded to the
2178 general registers, and from the floating point registers. */
2179
2180 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2181 mips_secondary_reload_class (CLASS, MODE, X, true)
2182 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2183 mips_secondary_reload_class (CLASS, MODE, X, false)
2184
2185 /* When targeting the o32 FPXX ABI, all moves with a length of doubleword
2186 or greater must be performed by FR-mode-aware instructions.
2187 This can be achieved using MFHC1/MTHC1 when these instructions are
2188 available but otherwise moves must go via memory.
2189 For the o32 FP64A ABI, all odd-numbered moves with a length of
2190 doubleword or greater are required to use memory. Using MTC1/MFC1
2191 to access the lower-half of these registers would require a forbidden
2192 single-precision access. We require all double-word moves to use
2193 memory because adding even and odd floating-point registers classes
2194 would have a significant impact on the backend. */
2195 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2196 mips_secondary_memory_needed ((CLASS1), (CLASS2), (MODE))
2197
2198 /* Return the maximum number of consecutive registers
2199 needed to represent mode MODE in a register of class CLASS. */
2200
2201 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2202
2203 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2204 mips_cannot_change_mode_class (FROM, TO, CLASS)
2205 \f
2206 /* Stack layout; function entry, exit and calling. */
2207
2208 #define STACK_GROWS_DOWNWARD
2209
2210 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2211
2212 /* Size of the area allocated in the frame to save the GP. */
2213
2214 #define MIPS_GP_SAVE_AREA_SIZE \
2215 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2216
2217 /* The offset of the first local variable from the frame pointer. See
2218 mips_compute_frame_info for details about the frame layout. */
2219
2220 #define STARTING_FRAME_OFFSET \
2221 (FRAME_GROWS_DOWNWARD \
2222 ? 0 \
2223 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2224
2225 #define RETURN_ADDR_RTX mips_return_addr
2226
2227 /* Mask off the MIPS16 ISA bit in unwind addresses.
2228
2229 The reason for this is a little subtle. When unwinding a call,
2230 we are given the call's return address, which on most targets
2231 is the address of the following instruction. However, what we
2232 actually want to find is the EH region for the call itself.
2233 The target-independent unwind code therefore searches for "RA - 1".
2234
2235 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2236 RA - 1 is therefore the real (even-valued) start of the return
2237 instruction. EH region labels are usually odd-valued MIPS16 symbols
2238 too, so a search for an even address within a MIPS16 region would
2239 usually work.
2240
2241 However, there is an exception. If the end of an EH region is also
2242 the end of a function, the end label is allowed to be even. This is
2243 necessary because a following non-MIPS16 function may also need EH
2244 information for its first instruction.
2245
2246 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2247 non-ISA-encoded address. This probably isn't ideal, but it is
2248 the traditional (legacy) behavior. It is therefore only safe
2249 to search MIPS EH regions for an _odd-valued_ address.
2250
2251 Masking off the ISA bit means that the target-independent code
2252 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2253 #define MASK_RETURN_ADDR GEN_INT (-2)
2254
2255
2256 /* Similarly, don't use the least-significant bit to tell pointers to
2257 code from vtable index. */
2258
2259 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2260
2261 /* The eliminations to $17 are only used for mips16 code. See the
2262 definition of HARD_FRAME_POINTER_REGNUM. */
2263
2264 #define ELIMINABLE_REGS \
2265 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2266 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2267 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2268 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2269 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2270 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2271
2272 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2273 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2274
2275 /* Allocate stack space for arguments at the beginning of each function. */
2276 #define ACCUMULATE_OUTGOING_ARGS 1
2277
2278 /* The argument pointer always points to the first argument. */
2279 #define FIRST_PARM_OFFSET(FNDECL) 0
2280
2281 /* o32 and o64 reserve stack space for all argument registers. */
2282 #define REG_PARM_STACK_SPACE(FNDECL) \
2283 (TARGET_OLDABI \
2284 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2285 : 0)
2286
2287 /* Define this if it is the responsibility of the caller to
2288 allocate the area reserved for arguments passed in registers.
2289 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2290 of this macro is to determine whether the space is included in
2291 `crtl->outgoing_args_size'. */
2292 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2293
2294 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2295 \f
2296 /* Symbolic macros for the registers used to return integer and floating
2297 point values. */
2298
2299 #define GP_RETURN (GP_REG_FIRST + 2)
2300 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2301
2302 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2303
2304 /* Symbolic macros for the first/last argument registers. */
2305
2306 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2307 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2308 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2309 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2310
2311 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2312 are used for returning complex double values in soft-float code, so $6 is the
2313 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2314 $gp itself as the temporary. */
2315 #define POST_CALL_TMP_REG \
2316 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2317
2318 /* 1 if N is a possible register number for function argument passing.
2319 We have no FP argument registers when soft-float. Special handling
2320 is required for O32 where only even numbered registers are used for
2321 O32-FPXX and O32-FP64. */
2322
2323 #define FUNCTION_ARG_REGNO_P(N) \
2324 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2325 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2326 && (mips_abi != ABI_32 \
2327 || TARGET_FLOAT32 \
2328 || ((N) % 2 == 0)))) \
2329 && !fixed_regs[N])
2330 \f
2331 /* This structure has to cope with two different argument allocation
2332 schemes. Most MIPS ABIs view the arguments as a structure, of which
2333 the first N words go in registers and the rest go on the stack. If I
2334 < N, the Ith word might go in Ith integer argument register or in a
2335 floating-point register. For these ABIs, we only need to remember
2336 the offset of the current argument into the structure.
2337
2338 The EABI instead allocates the integer and floating-point arguments
2339 separately. The first N words of FP arguments go in FP registers,
2340 the rest go on the stack. Likewise, the first N words of the other
2341 arguments go in integer registers, and the rest go on the stack. We
2342 need to maintain three counts: the number of integer registers used,
2343 the number of floating-point registers used, and the number of words
2344 passed on the stack.
2345
2346 We could keep separate information for the two ABIs (a word count for
2347 the standard ABIs, and three separate counts for the EABI). But it
2348 seems simpler to view the standard ABIs as forms of EABI that do not
2349 allocate floating-point registers.
2350
2351 So for the standard ABIs, the first N words are allocated to integer
2352 registers, and mips_function_arg decides on an argument-by-argument
2353 basis whether that argument should really go in an integer register,
2354 or in a floating-point one. */
2355
2356 typedef struct mips_args {
2357 /* Always true for varargs functions. Otherwise true if at least
2358 one argument has been passed in an integer register. */
2359 int gp_reg_found;
2360
2361 /* The number of arguments seen so far. */
2362 unsigned int arg_number;
2363
2364 /* The number of integer registers used so far. For all ABIs except
2365 EABI, this is the number of words that have been added to the
2366 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2367 unsigned int num_gprs;
2368
2369 /* For EABI, the number of floating-point registers used so far. */
2370 unsigned int num_fprs;
2371
2372 /* The number of words passed on the stack. */
2373 unsigned int stack_words;
2374
2375 /* On the mips16, we need to keep track of which floating point
2376 arguments were passed in general registers, but would have been
2377 passed in the FP regs if this were a 32-bit function, so that we
2378 can move them to the FP regs if we wind up calling a 32-bit
2379 function. We record this information in fp_code, encoded in base
2380 four. A zero digit means no floating point argument, a one digit
2381 means an SFmode argument, and a two digit means a DFmode argument,
2382 and a three digit is not used. The low order digit is the first
2383 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2384 an SFmode argument. ??? A more sophisticated approach will be
2385 needed if MIPS_ABI != ABI_32. */
2386 int fp_code;
2387
2388 /* True if the function has a prototype. */
2389 int prototype;
2390 } CUMULATIVE_ARGS;
2391
2392 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2393 for a call to a function whose data type is FNTYPE.
2394 For a library call, FNTYPE is 0. */
2395
2396 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2397 mips_init_cumulative_args (&CUM, FNTYPE)
2398
2399 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2400 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2401
2402 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2403 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2404
2405 /* True if using EABI and varargs can be passed in floating-point
2406 registers. Under these conditions, we need a more complex form
2407 of va_list, which tracks GPR, FPR and stack arguments separately. */
2408 #define EABI_FLOAT_VARARGS_P \
2409 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2410
2411 \f
2412 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2413
2414 /* Treat LOC as a byte offset from the stack pointer and round it up
2415 to the next fully-aligned offset. */
2416 #define MIPS_STACK_ALIGN(LOC) \
2417 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2418
2419 \f
2420 /* Output assembler code to FILE to increment profiler label # LABELNO
2421 for profiling a function entry. */
2422
2423 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2424
2425 /* The profiler preserves all interesting registers, including $31. */
2426 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2427
2428 /* No mips port has ever used the profiler counter word, so don't emit it
2429 or the label for it. */
2430
2431 #define NO_PROFILE_COUNTERS 1
2432
2433 /* Define this macro if the code for function profiling should come
2434 before the function prologue. Normally, the profiling code comes
2435 after. */
2436
2437 /* #define PROFILE_BEFORE_PROLOGUE */
2438
2439 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2440 the stack pointer does not matter. The value is tested only in
2441 functions that have frame pointers.
2442 No definition is equivalent to always zero. */
2443
2444 #define EXIT_IGNORE_STACK 1
2445
2446 \f
2447 /* Trampolines are a block of code followed by two pointers. */
2448
2449 #define TRAMPOLINE_SIZE \
2450 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2451
2452 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2453 pointers from a single LUI base. */
2454
2455 #define TRAMPOLINE_ALIGNMENT 64
2456
2457 /* mips_trampoline_init calls this library function to flush
2458 program and data caches. */
2459
2460 #ifndef CACHE_FLUSH_FUNC
2461 #define CACHE_FLUSH_FUNC "_flush_cache"
2462 #endif
2463
2464 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2465 /* Flush both caches. We need to flush the data cache in case \
2466 the system has a write-back cache. */ \
2467 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2468 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2469 GEN_INT (3), TYPE_MODE (integer_type_node))
2470
2471 \f
2472 /* Addressing modes, and classification of registers for them. */
2473
2474 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2475 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2476 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2477 \f
2478 /* Maximum number of registers that can appear in a valid memory address. */
2479
2480 #define MAX_REGS_PER_ADDRESS 1
2481
2482 /* Check for constness inline but use mips_legitimate_address_p
2483 to check whether a constant really is an address. */
2484
2485 #define CONSTANT_ADDRESS_P(X) \
2486 (CONSTANT_P (X) && memory_address_p (SImode, X))
2487
2488 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2489 'the start of the function that this code is output in'. */
2490
2491 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2492 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2493 asm_fprintf ((FILE), "%U%s", \
2494 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2495 else \
2496 asm_fprintf ((FILE), "%U%s", (NAME))
2497 \f
2498 /* Flag to mark a function decl symbol that requires a long call. */
2499 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2500 #define SYMBOL_REF_LONG_CALL_P(X) \
2501 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2502
2503 /* This flag marks functions that cannot be lazily bound. */
2504 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2505 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2506 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2507
2508 /* True if we're generating a form of MIPS16 code in which jump tables
2509 are stored in the text section and encoded as 16-bit PC-relative
2510 offsets. This is only possible when general text loads are allowed,
2511 since the table access itself will be an "lh" instruction. If the
2512 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2513 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2514
2515 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2516
2517 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2518
2519 /* Only use short offsets if their range will not overflow. */
2520 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2521 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2522 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2523 : SImode)
2524
2525 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2526
2527 /* Define this as 1 if `char' should by default be signed; else as 0. */
2528 #ifndef DEFAULT_SIGNED_CHAR
2529 #define DEFAULT_SIGNED_CHAR 1
2530 #endif
2531
2532 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2533 we generally don't want to use them for copying arbitrary data.
2534 A single N-word move is usually the same cost as N single-word moves. */
2535 #define MOVE_MAX UNITS_PER_WORD
2536 #define MAX_MOVE_MAX 8
2537
2538 /* Define this macro as a C expression which is nonzero if
2539 accessing less than a word of memory (i.e. a `char' or a
2540 `short') is no faster than accessing a word of memory, i.e., if
2541 such access require more than one instruction or if there is no
2542 difference in cost between byte and (aligned) word loads.
2543
2544 On RISC machines, it tends to generate better code to define
2545 this as 1, since it avoids making a QI or HI mode register.
2546
2547 But, generating word accesses for -mips16 is generally bad as shifts
2548 (often extended) would be needed for byte accesses. */
2549 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2550
2551 /* Standard MIPS integer shifts truncate the shift amount to the
2552 width of the shifted operand. However, Loongson vector shifts
2553 do not truncate the shift amount at all. */
2554 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2555
2556 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2557 is done just by pretending it is already truncated. */
2558 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2559 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2560
2561
2562 /* Specify the machine mode that pointers have.
2563 After generation of rtl, the compiler makes no further distinction
2564 between pointers and any other objects of this machine mode. */
2565
2566 #ifndef Pmode
2567 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2568 #endif
2569
2570 /* Give call MEMs SImode since it is the "most permissive" mode
2571 for both 32-bit and 64-bit targets. */
2572
2573 #define FUNCTION_MODE SImode
2574
2575 \f
2576 /* We allocate $fcc registers by hand and can't cope with moves of
2577 CCmode registers to and from pseudos (or memory). */
2578 #define AVOID_CCMODE_COPIES
2579
2580 /* A C expression for the cost of a branch instruction. A value of
2581 1 is the default; other values are interpreted relative to that. */
2582
2583 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2584 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2585
2586 /* The MIPS port has several functions that return an instruction count.
2587 Multiplying the count by this value gives the number of bytes that
2588 the instructions occupy. */
2589 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2590
2591 /* The length of a NOP in bytes. */
2592 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2593
2594 /* If defined, modifies the length assigned to instruction INSN as a
2595 function of the context in which it is used. LENGTH is an lvalue
2596 that contains the initially computed length of the insn and should
2597 be updated with the correct length of the insn. */
2598 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2599 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2600
2601 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2602 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2603 its operands. */
2604 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2605 "%*" OPCODE "%?\t" OPERANDS "%/"
2606
2607 /* Return an asm string that forces INSN to be treated as an absolute
2608 J or JAL instruction instead of an assembler macro. */
2609 #define MIPS_ABSOLUTE_JUMP(INSN) \
2610 (TARGET_ABICALLS_PIC2 \
2611 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2612 : INSN)
2613
2614 /* Return the asm template for a call. INSN is the instruction's mnemonic
2615 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2616 number of the target. SIZE_OPNO is the operand number of the argument size
2617 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2618 -1 and the call is indirect, use the function symbol from the call
2619 attributes to attach a R_MIPS_JALR relocation to the call.
2620
2621 When generating GOT code without explicit relocation operators,
2622 all calls should use assembly macros. Otherwise, all indirect
2623 calls should use "jr" or "jalr"; we will arrange to restore $gp
2624 afterwards if necessary. Finally, we can only generate direct
2625 calls for -mabicalls by temporarily switching to non-PIC mode.
2626
2627 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
2628 instruction is in the delay slot of jal(r). */
2629 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2630 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2631 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2632 : REG_P (OPERANDS[TARGET_OPNO]) \
2633 ? (mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO) \
2634 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2635 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2636 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2637 ? "%*" INSN "r%!\t%" #TARGET_OPNO "%/" \
2638 : "%*" INSN "r\t%" #TARGET_OPNO "%/") \
2639 : TARGET_MICROMIPS && !TARGET_INTERLINK_COMPRESSED \
2640 ? MIPS_ABSOLUTE_JUMP ("%*" INSN "%!\t%" #TARGET_OPNO "%/") \
2641 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) \
2642
2643 /* Similar to MIPS_CALL, but this is for MICROMIPS "j" to generate
2644 "jrc" when nop is in the delay slot of "jr". */
2645
2646 #define MICROMIPS_J(INSN, OPERANDS, OPNO) \
2647 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2648 ? "%*j\t%" #OPNO "%/" \
2649 : REG_P (OPERANDS[OPNO]) \
2650 ? "%*jr%:\t%" #OPNO \
2651 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
2652
2653 \f
2654 /* Control the assembler format that we output. */
2655
2656 /* Output to assembler file text saying following lines
2657 may contain character constants, extra white space, comments, etc. */
2658
2659 #ifndef ASM_APP_ON
2660 #define ASM_APP_ON " #APP\n"
2661 #endif
2662
2663 /* Output to assembler file text saying following lines
2664 no longer contain unusual constructs. */
2665
2666 #ifndef ASM_APP_OFF
2667 #define ASM_APP_OFF " #NO_APP\n"
2668 #endif
2669
2670 #define REGISTER_NAMES \
2671 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2672 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2673 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2674 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2675 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2676 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2677 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2678 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2679 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2680 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2681 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2682 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2683 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2684 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2685 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2686 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2687 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2688 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2689 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2690 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2691 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2692 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2693 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2694 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2695
2696 /* List the "software" names for each register. Also list the numerical
2697 names for $fp and $sp. */
2698
2699 #define ADDITIONAL_REGISTER_NAMES \
2700 { \
2701 { "$29", 29 + GP_REG_FIRST }, \
2702 { "$30", 30 + GP_REG_FIRST }, \
2703 { "at", 1 + GP_REG_FIRST }, \
2704 { "v0", 2 + GP_REG_FIRST }, \
2705 { "v1", 3 + GP_REG_FIRST }, \
2706 { "a0", 4 + GP_REG_FIRST }, \
2707 { "a1", 5 + GP_REG_FIRST }, \
2708 { "a2", 6 + GP_REG_FIRST }, \
2709 { "a3", 7 + GP_REG_FIRST }, \
2710 { "t0", 8 + GP_REG_FIRST }, \
2711 { "t1", 9 + GP_REG_FIRST }, \
2712 { "t2", 10 + GP_REG_FIRST }, \
2713 { "t3", 11 + GP_REG_FIRST }, \
2714 { "t4", 12 + GP_REG_FIRST }, \
2715 { "t5", 13 + GP_REG_FIRST }, \
2716 { "t6", 14 + GP_REG_FIRST }, \
2717 { "t7", 15 + GP_REG_FIRST }, \
2718 { "s0", 16 + GP_REG_FIRST }, \
2719 { "s1", 17 + GP_REG_FIRST }, \
2720 { "s2", 18 + GP_REG_FIRST }, \
2721 { "s3", 19 + GP_REG_FIRST }, \
2722 { "s4", 20 + GP_REG_FIRST }, \
2723 { "s5", 21 + GP_REG_FIRST }, \
2724 { "s6", 22 + GP_REG_FIRST }, \
2725 { "s7", 23 + GP_REG_FIRST }, \
2726 { "t8", 24 + GP_REG_FIRST }, \
2727 { "t9", 25 + GP_REG_FIRST }, \
2728 { "k0", 26 + GP_REG_FIRST }, \
2729 { "k1", 27 + GP_REG_FIRST }, \
2730 { "gp", 28 + GP_REG_FIRST }, \
2731 { "sp", 29 + GP_REG_FIRST }, \
2732 { "fp", 30 + GP_REG_FIRST }, \
2733 { "ra", 31 + GP_REG_FIRST } \
2734 }
2735
2736 #define DBR_OUTPUT_SEQEND(STREAM) \
2737 do \
2738 { \
2739 /* Undo the effect of '%*'. */ \
2740 mips_pop_asm_switch (&mips_nomacro); \
2741 mips_pop_asm_switch (&mips_noreorder); \
2742 /* Emit a blank line after the delay slot for emphasis. */ \
2743 fputs ("\n", STREAM); \
2744 } \
2745 while (0)
2746
2747 /* The MIPS implementation uses some labels for its own purpose. The
2748 following lists what labels are created, and are all formed by the
2749 pattern $L[a-z].*. The machine independent portion of GCC creates
2750 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2751
2752 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2753 $Lb[0-9]+ Begin blocks for MIPS debug support
2754 $Lc[0-9]+ Label for use in s<xx> operation.
2755 $Le[0-9]+ End blocks for MIPS debug support */
2756
2757 #undef ASM_DECLARE_OBJECT_NAME
2758 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2759 mips_declare_object (STREAM, NAME, "", ":\n")
2760
2761 /* Globalizing directive for a label. */
2762 #define GLOBAL_ASM_OP "\t.globl\t"
2763
2764 /* This says how to define a global common symbol. */
2765
2766 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2767
2768 /* This says how to define a local common symbol (i.e., not visible to
2769 linker). */
2770
2771 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2772 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2773 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2774 #endif
2775
2776 /* This says how to output an external. It would be possible not to
2777 output anything and let undefined symbol become external. However
2778 the assembler uses length information on externals to allocate in
2779 data/sdata bss/sbss, thereby saving exec time. */
2780
2781 #undef ASM_OUTPUT_EXTERNAL
2782 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2783 mips_output_external(STREAM,DECL,NAME)
2784
2785 /* This is how to declare a function name. The actual work of
2786 emitting the label is moved to function_prologue, so that we can
2787 get the line number correctly emitted before the .ent directive,
2788 and after any .file directives. Define as empty so that the function
2789 is not declared before the .ent directive elsewhere. */
2790
2791 #undef ASM_DECLARE_FUNCTION_NAME
2792 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2793
2794 /* This is how to store into the string LABEL
2795 the symbol_ref name of an internal numbered label where
2796 PREFIX is the class of label and NUM is the number within the class.
2797 This is suitable for output with `assemble_name'. */
2798
2799 #undef ASM_GENERATE_INTERNAL_LABEL
2800 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2801 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2802
2803 /* Print debug labels as "foo = ." rather than "foo:" because they should
2804 represent a byte pointer rather than an ISA-encoded address. This is
2805 particularly important for code like:
2806
2807 $LFBxxx = .
2808 .cfi_startproc
2809 ...
2810 .section .gcc_except_table,...
2811 ...
2812 .uleb128 foo-$LFBxxx
2813
2814 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2815 likewise a byte pointer rather than an ISA-encoded address.
2816
2817 At the time of writing, this hook is not used for the function end
2818 label:
2819
2820 $LFExxx:
2821 .end foo
2822
2823 But this doesn't matter, because GAS doesn't treat a pre-.end label
2824 as a MIPS16 one anyway. */
2825
2826 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2827 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2828
2829 /* This is how to output an element of a case-vector that is absolute. */
2830
2831 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2832 fprintf (STREAM, "\t%s\t%sL%d\n", \
2833 ptr_mode == DImode ? ".dword" : ".word", \
2834 LOCAL_LABEL_PREFIX, \
2835 VALUE)
2836
2837 /* This is how to output an element of a case-vector. We can make the
2838 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2839 is supported. */
2840
2841 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2842 do { \
2843 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2844 { \
2845 if (GET_MODE (BODY) == HImode) \
2846 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2847 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2848 else \
2849 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2850 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2851 } \
2852 else if (TARGET_GPWORD) \
2853 fprintf (STREAM, "\t%s\t%sL%d\n", \
2854 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2855 LOCAL_LABEL_PREFIX, VALUE); \
2856 else if (TARGET_RTP_PIC) \
2857 { \
2858 /* Make the entry relative to the start of the function. */ \
2859 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2860 fprintf (STREAM, "\t%s\t%sL%d-", \
2861 Pmode == DImode ? ".dword" : ".word", \
2862 LOCAL_LABEL_PREFIX, VALUE); \
2863 assemble_name (STREAM, XSTR (fnsym, 0)); \
2864 fprintf (STREAM, "\n"); \
2865 } \
2866 else \
2867 fprintf (STREAM, "\t%s\t%sL%d\n", \
2868 ptr_mode == DImode ? ".dword" : ".word", \
2869 LOCAL_LABEL_PREFIX, VALUE); \
2870 } while (0)
2871
2872 /* This is how to output an assembler line
2873 that says to advance the location counter
2874 to a multiple of 2**LOG bytes. */
2875
2876 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2877 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2878
2879 /* This is how to output an assembler line to advance the location
2880 counter by SIZE bytes. */
2881
2882 #undef ASM_OUTPUT_SKIP
2883 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2884 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2885
2886 /* This is how to output a string. */
2887 #undef ASM_OUTPUT_ASCII
2888 #define ASM_OUTPUT_ASCII mips_output_ascii
2889
2890 \f
2891 /* Default to -G 8 */
2892 #ifndef MIPS_DEFAULT_GVALUE
2893 #define MIPS_DEFAULT_GVALUE 8
2894 #endif
2895
2896 /* Define the strings to put out for each section in the object file. */
2897 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2898 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2899
2900 #undef READONLY_DATA_SECTION_ASM_OP
2901 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2902 \f
2903 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2904 do \
2905 { \
2906 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2907 TARGET_64BIT ? "daddiu" : "addiu", \
2908 reg_names[STACK_POINTER_REGNUM], \
2909 reg_names[STACK_POINTER_REGNUM], \
2910 TARGET_64BIT ? "sd" : "sw", \
2911 reg_names[REGNO], \
2912 reg_names[STACK_POINTER_REGNUM]); \
2913 } \
2914 while (0)
2915
2916 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2917 do \
2918 { \
2919 mips_push_asm_switch (&mips_noreorder); \
2920 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2921 TARGET_64BIT ? "ld" : "lw", \
2922 reg_names[REGNO], \
2923 reg_names[STACK_POINTER_REGNUM], \
2924 TARGET_64BIT ? "daddu" : "addu", \
2925 reg_names[STACK_POINTER_REGNUM], \
2926 reg_names[STACK_POINTER_REGNUM]); \
2927 mips_pop_asm_switch (&mips_noreorder); \
2928 } \
2929 while (0)
2930
2931 /* How to start an assembler comment.
2932 The leading space is important (the mips native assembler requires it). */
2933 #ifndef ASM_COMMENT_START
2934 #define ASM_COMMENT_START " #"
2935 #endif
2936 \f
2937 #undef SIZE_TYPE
2938 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2939
2940 #undef PTRDIFF_TYPE
2941 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2942
2943 /* The maximum number of bytes that can be copied by one iteration of
2944 a movmemsi loop; see mips_block_move_loop. */
2945 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2946 (UNITS_PER_WORD * 4)
2947
2948 /* The maximum number of bytes that can be copied by a straight-line
2949 implementation of movmemsi; see mips_block_move_straight. We want
2950 to make sure that any loop-based implementation will iterate at
2951 least twice. */
2952 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2953 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2954
2955 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2956 values were determined experimentally by benchmarking with CSiBE.
2957 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2958 for o32 where we have to restore $gp afterwards as well as make an
2959 indirect call), but in practice, bumping this up higher for
2960 TARGET_ABICALLS doesn't make much difference to code size. */
2961
2962 #define MIPS_CALL_RATIO 8
2963
2964 /* Any loop-based implementation of movmemsi will have at least
2965 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2966 moves, so allow individual copies of fewer elements.
2967
2968 When movmemsi is not available, use a value approximating
2969 the length of a memcpy call sequence, so that move_by_pieces
2970 will generate inline code if it is shorter than a function call.
2971 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2972 we'll have to generate a load/store pair for each, halve the
2973 value of MIPS_CALL_RATIO to take that into account. */
2974
2975 #define MOVE_RATIO(speed) \
2976 (HAVE_movmemsi \
2977 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2978 : MIPS_CALL_RATIO / 2)
2979
2980 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2981 of the length of a memset call, but use the default otherwise. */
2982
2983 #define CLEAR_RATIO(speed)\
2984 ((speed) ? 15 : MIPS_CALL_RATIO)
2985
2986 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2987 optimizing for size adjust the ratio to account for the overhead of
2988 loading the constant and replicating it across the word. */
2989
2990 #define SET_RATIO(speed) \
2991 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2992 \f
2993 /* Since the bits of the _init and _fini function is spread across
2994 many object files, each potentially with its own GP, we must assume
2995 we need to load our GP. We don't preserve $gp or $ra, since each
2996 init/fini chunk is supposed to initialize $gp, and crti/crtn
2997 already take care of preserving $ra and, when appropriate, $gp. */
2998 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2999 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3000 asm (SECTION_OP "\n\
3001 .set push\n\
3002 .set nomips16\n\
3003 .set noreorder\n\
3004 bal 1f\n\
3005 nop\n\
3006 1: .cpload $31\n\
3007 .set reorder\n\
3008 jal " USER_LABEL_PREFIX #FUNC "\n\
3009 .set pop\n\
3010 " TEXT_SECTION_ASM_OP);
3011 #elif ((defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3012 || (defined _ABI64 && _MIPS_SIM == _ABI64))
3013 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3014 asm (SECTION_OP "\n\
3015 .set push\n\
3016 .set nomips16\n\
3017 .set noreorder\n\
3018 bal 1f\n\
3019 nop\n\
3020 1: .set reorder\n\
3021 .cpsetup $31, $2, 1b\n\
3022 jal " USER_LABEL_PREFIX #FUNC "\n\
3023 .set pop\n\
3024 " TEXT_SECTION_ASM_OP);
3025 #endif
3026
3027 #ifndef HAVE_AS_TLS
3028 #define HAVE_AS_TLS 0
3029 #endif
3030
3031 #ifndef HAVE_AS_NAN
3032 #define HAVE_AS_NAN 0
3033 #endif
3034
3035 #ifndef USED_FOR_TARGET
3036 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3037 struct mips_asm_switch {
3038 /* The FOO in the description above. */
3039 const char *name;
3040
3041 /* The current block nesting level, or 0 if we aren't in a block. */
3042 int nesting_level;
3043 };
3044
3045 extern const enum reg_class mips_regno_to_class[];
3046 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3047 extern const char *current_function_file; /* filename current function is in */
3048 extern int num_source_filenames; /* current .file # */
3049 extern struct mips_asm_switch mips_noreorder;
3050 extern struct mips_asm_switch mips_nomacro;
3051 extern struct mips_asm_switch mips_noat;
3052 extern int mips_dbx_regno[];
3053 extern int mips_dwarf_regno[];
3054 extern bool mips_split_p[];
3055 extern bool mips_split_hi_p[];
3056 extern bool mips_use_pcrel_pool_p[];
3057 extern const char *mips_lo_relocs[];
3058 extern const char *mips_hi_relocs[];
3059 extern enum processor mips_arch; /* which cpu to codegen for */
3060 extern enum processor mips_tune; /* which cpu to schedule for */
3061 extern int mips_isa; /* architectural level */
3062 extern int mips_isa_rev;
3063 extern const struct mips_cpu_info *mips_arch_info;
3064 extern const struct mips_cpu_info *mips_tune_info;
3065 extern unsigned int mips_base_compression_flags;
3066 extern GTY(()) struct target_globals *mips16_globals;
3067 #endif
3068
3069 /* Enable querying of DFA units. */
3070 #define CPU_UNITS_QUERY 1
3071
3072 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3073 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3074
3075 /* As on most targets, we want the .eh_frame section to be read-only where
3076 possible. And as on most targets, this means two things:
3077
3078 (a) Non-locally-binding pointers must have an indirect encoding,
3079 so that the addresses in the .eh_frame section itself become
3080 locally-binding.
3081
3082 (b) A shared library's .eh_frame section must encode locally-binding
3083 pointers in a relative (relocation-free) form.
3084
3085 However, MIPS has traditionally not allowed directives like:
3086
3087 .long x-.
3088
3089 in cases where "x" is in a different section, or is not defined in the
3090 same assembly file. We are therefore unable to emit the PC-relative
3091 form required by (b) at assembly time.
3092
3093 Fortunately, the linker is able to convert absolute addresses into
3094 PC-relative addresses on our behalf. Unfortunately, only certain
3095 versions of the linker know how to do this for indirect pointers,
3096 and for personality data. We must fall back on using writable
3097 .eh_frame sections for shared libraries if the linker does not
3098 support this feature. */
3099 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3100 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3101
3102 /* For switching between MIPS16 and non-MIPS16 modes. */
3103 #define SWITCHABLE_TARGET 1
3104
3105 /* Several named MIPS patterns depend on Pmode. These patterns have the
3106 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3107 Add the appropriate suffix to generator function NAME and invoke it
3108 with arguments ARGS. */
3109 #define PMODE_INSN(NAME, ARGS) \
3110 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
3111
3112 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
3113 need to change these from /lib and /usr/lib. */
3114 #if MIPS_ABI_DEFAULT == ABI_N32
3115 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3116 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3117 #elif MIPS_ABI_DEFAULT == ABI_64
3118 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3119 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3120 #endif
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