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i386: move alignment defaults to processor_costs.
[official-gcc.git] / gcc / common / config / i386 / i386-common.c
blob3b5312d7250941b05c8eae6fe958d0f526976d30
1 /* IA-32 common hooks.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "diagnostic-core.h"
24 #include "tm.h"
25 #include "memmodel.h"
26 #include "tm_p.h"
27 #include "common/common-target.h"
28 #include "common/common-target-def.h"
29 #include "opts.h"
30 #include "flags.h"
31
32 /* Define a set of ISAs which are available when a given ISA is
33 enabled. MMX and SSE ISAs are handled separately. */
34
35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 #define OPTION_MASK_ISA_3DNOW_SET \
37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 #define OPTION_MASK_ISA_3DNOW_A_SET \
39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40
41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 #define OPTION_MASK_ISA_SSE2_SET \
43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 #define OPTION_MASK_ISA_SSE3_SET \
45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 #define OPTION_MASK_ISA_SSSE3_SET \
47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 #define OPTION_MASK_ISA_SSE4_1_SET \
49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 #define OPTION_MASK_ISA_SSE4_2_SET \
51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 #define OPTION_MASK_ISA_AVX_SET \
53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 | OPTION_MASK_ISA_XSAVE_SET)
55 #define OPTION_MASK_ISA_FMA_SET \
56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 #define OPTION_MASK_ISA_AVX2_SET \
58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 #define OPTION_MASK_ISA_AVX512F_SET \
64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 #define OPTION_MASK_ISA_AVX512CD_SET \
66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 #define OPTION_MASK_ISA_AVX512PF_SET \
68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
69 #define OPTION_MASK_ISA_AVX512ER_SET \
70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
71 #define OPTION_MASK_ISA_AVX512DQ_SET \
72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
73 #define OPTION_MASK_ISA_AVX512BW_SET \
74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
75 #define OPTION_MASK_ISA_AVX512VL_SET \
76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
79 #define OPTION_MASK_ISA_AVX512VBMI_SET \
80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
81 #define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS
82 #define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW
83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
85 #define OPTION_MASK_ISA_AVX512VNNI_SET \
86 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
87 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
88 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
89 #define OPTION_MASK_ISA_AVX512BITALG_SET \
90 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
91 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
92 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
93 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
94 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
95 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
96 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
97 #define OPTION_MASK_ISA_XSAVES_SET \
98 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
99 #define OPTION_MASK_ISA_XSAVEC_SET \
100 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
101 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
102
103 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
104 as -msse4.2. */
105 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
106
107 #define OPTION_MASK_ISA_SSE4A_SET \
108 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
109 #define OPTION_MASK_ISA_FMA4_SET \
110 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
111 | OPTION_MASK_ISA_AVX_SET)
112 #define OPTION_MASK_ISA_XOP_SET \
113 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
114 #define OPTION_MASK_ISA_LWP_SET \
115 OPTION_MASK_ISA_LWP
116
117 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
118 #define OPTION_MASK_ISA_AES_SET \
119 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
120 #define OPTION_MASK_ISA_SHA_SET \
121 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
122 #define OPTION_MASK_ISA_PCLMUL_SET \
123 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
124
125 #define OPTION_MASK_ISA_ABM_SET \
126 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
127
128 #define OPTION_MASK_ISA_PCONFIG_SET OPTION_MASK_ISA_PCONFIG
129 #define OPTION_MASK_ISA_WBNOINVD_SET OPTION_MASK_ISA_WBNOINVD
130 #define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX
131 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
132 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
133 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
134 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
135 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
136 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
137 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
138 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
139 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
140
141 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
142 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
143 #define OPTION_MASK_ISA_F16C_SET \
144 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
145 #define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX
146 #define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO
147 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
148 #define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID
149 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
150 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
151 #define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES
152 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
153 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
154 #define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B
155 #define OPTION_MASK_ISA_WAITPKG_SET OPTION_MASK_ISA_WAITPKG
156 #define OPTION_MASK_ISA_CLDEMOTE_SET OPTION_MASK_ISA_CLDEMOTE
157
158 /* Define a set of ISAs which aren't available when a given ISA is
159 disabled. MMX and SSE ISAs are handled separately. */
160
161 #define OPTION_MASK_ISA_MMX_UNSET \
162 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
163 #define OPTION_MASK_ISA_3DNOW_UNSET \
164 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
165 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
166
167 #define OPTION_MASK_ISA_SSE_UNSET \
168 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
169 #define OPTION_MASK_ISA_SSE2_UNSET \
170 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
171 #define OPTION_MASK_ISA_SSE3_UNSET \
172 (OPTION_MASK_ISA_SSE3 \
173 | OPTION_MASK_ISA_SSSE3_UNSET \
174 | OPTION_MASK_ISA_SSE4A_UNSET )
175 #define OPTION_MASK_ISA_SSSE3_UNSET \
176 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
177 #define OPTION_MASK_ISA_SSE4_1_UNSET \
178 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
179 #define OPTION_MASK_ISA_SSE4_2_UNSET \
180 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
181 #define OPTION_MASK_ISA_AVX_UNSET \
182 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
183 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
184 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET)
185 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
186 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
187 #define OPTION_MASK_ISA_XSAVE_UNSET \
188 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
189 | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET)
190 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
191 #define OPTION_MASK_ISA_AVX2_UNSET \
192 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
193 #define OPTION_MASK_ISA_AVX512F_UNSET \
194 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
195 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
196 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
197 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
198 | OPTION_MASK_ISA_AVX512VNNI_UNSET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
199 | OPTION_MASK_ISA_AVX512BITALG_UNSET)
200 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
201 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
202 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
203 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
204 #define OPTION_MASK_ISA_AVX512BW_UNSET \
205 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
206 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
207 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
208 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
209 #define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS
210 #define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW
211 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
212 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
213 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
214 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
215 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
216 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
217 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
218 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
219 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
220 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
221 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
222 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
223 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
224 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
225 #define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO
226 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
227 #define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID
228 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
229 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
230 #define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES
231 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
232 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
233 #define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B
234 #define OPTION_MASK_ISA_WAITPKG_UNSET OPTION_MASK_ISA_WAITPKG
235 #define OPTION_MASK_ISA_CLDEMOTE_UNSET OPTION_MASK_ISA_CLDEMOTE
236
237 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
238 as -mno-sse4.1. */
239 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
240
241 #define OPTION_MASK_ISA_SSE4A_UNSET \
242 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
243
244 #define OPTION_MASK_ISA_FMA4_UNSET \
245 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
246 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
247 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
248
249 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
250 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
251 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
252 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
253 #define OPTION_MASK_ISA_PCONFIG_UNSET OPTION_MASK_ISA_PCONFIG
254 #define OPTION_MASK_ISA_WBNOINVD_UNSET OPTION_MASK_ISA_WBNOINVD
255 #define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX
256 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
257 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
258 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
259 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
260 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
261 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
262 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
263 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
264 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
265
266 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
267 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
268 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
269
270 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
271 (OPTION_MASK_ISA_MMX_UNSET \
272 | OPTION_MASK_ISA_SSE_UNSET)
273
274 #define OPTION_MASK_ISA2_AVX512F_UNSET \
275 (OPTION_MASK_ISA_AVX5124FMAPS_UNSET | OPTION_MASK_ISA_AVX5124VNNIW_UNSET)
276 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
277 (OPTION_MASK_ISA2_AVX512F_UNSET)
278
279 /* Set 1 << value as value of -malign-FLAG option. */
280
281 static void
282 set_malign_value (const char **flag, unsigned value)
283 {
284 char *r = XNEWVEC (char, 6);
285 sprintf (r, "%d", 1 << value);
286 *flag = r;
287 }
288
289 /* Implement TARGET_HANDLE_OPTION. */
290
291 bool
292 ix86_handle_option (struct gcc_options *opts,
293 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
294 const struct cl_decoded_option *decoded,
295 location_t loc)
296 {
297 size_t code = decoded->opt_index;
298 int value = decoded->value;
299
300 switch (code)
301 {
302 case OPT_mgeneral_regs_only:
303 if (value)
304 {
305 /* Disable MMX, SSE and x87 instructions if only
306 general registers are allowed. */
307 opts->x_ix86_isa_flags
308 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
309 opts->x_ix86_isa_flags2
310 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
311 opts->x_ix86_isa_flags_explicit
312 |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
313 opts->x_ix86_isa_flags2_explicit
314 |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
315
316 opts->x_target_flags &= ~MASK_80387;
317 }
318 else
319 gcc_unreachable ();
320 return true;
321
322 case OPT_mmmx:
323 if (value)
324 {
325 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
326 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
327 }
328 else
329 {
330 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
331 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
332 }
333 return true;
334
335 case OPT_m3dnow:
336 if (value)
337 {
338 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
339 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
340 }
341 else
342 {
343 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
344 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
345 }
346 return true;
347
348 case OPT_m3dnowa:
349 if (value)
350 {
351 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
352 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
353 }
354 else
355 {
356 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
357 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
358 }
359 return true;
360
361 case OPT_msse:
362 if (value)
363 {
364 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
365 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
366 }
367 else
368 {
369 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
370 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
371 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
372 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
373 }
374 return true;
375
376 case OPT_msse2:
377 if (value)
378 {
379 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
380 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
381 }
382 else
383 {
384 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
385 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
386 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
387 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
388 }
389 return true;
390
391 case OPT_msse3:
392 if (value)
393 {
394 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
395 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
396 }
397 else
398 {
399 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
400 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
401 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
402 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
403 }
404 return true;
405
406 case OPT_mssse3:
407 if (value)
408 {
409 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
410 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
411 }
412 else
413 {
414 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
415 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
416 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
417 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
418 }
419 return true;
420
421 case OPT_msse4_1:
422 if (value)
423 {
424 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
425 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
426 }
427 else
428 {
429 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
430 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
431 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
432 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
433 }
434 return true;
435
436 case OPT_msse4_2:
437 if (value)
438 {
439 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
440 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
441 }
442 else
443 {
444 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
445 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
446 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
447 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
448 }
449 return true;
450
451 case OPT_mavx:
452 if (value)
453 {
454 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
455 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
456 }
457 else
458 {
459 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
460 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
461 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
462 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
463 }
464 return true;
465
466 case OPT_mavx2:
467 if (value)
468 {
469 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
470 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
471 }
472 else
473 {
474 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
475 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
476 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
477 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
478 }
479 return true;
480
481 case OPT_mavx512f:
482 if (value)
483 {
484 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
485 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
486 }
487 else
488 {
489 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
490 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
491 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
492 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
493 }
494 return true;
495
496 case OPT_mavx512cd:
497 if (value)
498 {
499 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
500 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
501 }
502 else
503 {
504 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
505 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
506 }
507 return true;
508
509 case OPT_mavx512pf:
510 if (value)
511 {
512 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
513 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
514 }
515 else
516 {
517 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
518 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
519 }
520 return true;
521
522 case OPT_mavx512er:
523 if (value)
524 {
525 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
526 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
527 }
528 else
529 {
530 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
531 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
532 }
533 return true;
534
535 case OPT_mrdpid:
536 if (value)
537 {
538 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID_SET;
539 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_SET;
540 }
541 else
542 {
543 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_RDPID_UNSET;
544 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_UNSET;
545 }
546 return true;
547
548 case OPT_mgfni:
549 if (value)
550 {
551 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
552 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
553 }
554 else
555 {
556 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
557 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
558 }
559 return true;
560
561 case OPT_mshstk:
562 if (value)
563 {
564 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
565 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
566 }
567 else
568 {
569 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
570 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
571 }
572 return true;
573
574 case OPT_mvaes:
575 if (value)
576 {
577 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET;
578 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET;
579 }
580 else
581 {
582 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET;
583 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET;
584 }
585 return true;
586
587 case OPT_mvpclmulqdq:
588 if (value)
589 {
590 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
591 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
592 }
593 else
594 {
595 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
596 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
597 }
598 return true;
599
600 case OPT_mmovdiri:
601 if (value)
602 {
603 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
604 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
605 }
606 else
607 {
608 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
609 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
610 }
611 return true;
612
613 case OPT_mmovdir64b:
614 if (value)
615 {
616 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B_SET;
617 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_SET;
618 }
619 else
620 {
621 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVDIR64B_UNSET;
622 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_UNSET;
623 }
624 return true;
625
626 case OPT_mcldemote:
627 if (value)
628 {
629 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLDEMOTE_SET;
630 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_SET;
631 }
632 else
633 {
634 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLDEMOTE_UNSET;
635 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_UNSET;
636 }
637 return true;
638
639 case OPT_mwaitpkg:
640 if (value)
641 {
642 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WAITPKG_SET;
643 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_SET;
644 }
645 else
646 {
647 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WAITPKG_UNSET;
648 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_UNSET;
649 }
650 return true;
651
652 case OPT_mavx5124fmaps:
653 if (value)
654 {
655 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
656 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
657 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
658 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
659 }
660 else
661 {
662 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
663 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
664 }
665 return true;
666
667 case OPT_mavx5124vnniw:
668 if (value)
669 {
670 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
671 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
672 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
673 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
674 }
675 else
676 {
677 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
678 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
679 }
680 return true;
681
682 case OPT_mavx512vbmi2:
683 if (value)
684 {
685 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
686 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
687 }
688 else
689 {
690 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
691 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
692 }
693 return true;
694
695 case OPT_mavx512vnni:
696 if (value)
697 {
698 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
699 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
700 }
701 else
702 {
703 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
704 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
705 }
706 return true;
707
708 case OPT_mavx512vpopcntdq:
709 if (value)
710 {
711 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
712 opts->x_ix86_isa_flags_explicit
713 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
714 }
715 else
716 {
717 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
718 opts->x_ix86_isa_flags_explicit
719 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
720 }
721 return true;
722
723 case OPT_mavx512bitalg:
724 if (value)
725 {
726 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
727 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
728 }
729 else
730 {
731 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
732 opts->x_ix86_isa_flags_explicit
733 |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
734 }
735 return true;
736
737 case OPT_msgx:
738 if (value)
739 {
740 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET;
741 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET;
742 }
743 else
744 {
745 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET;
746 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET;
747 }
748 return true;
749
750 case OPT_mpconfig:
751 if (value)
752 {
753 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG_SET;
754 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_SET;
755 }
756 else
757 {
758 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PCONFIG_UNSET;
759 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_UNSET;
760 }
761 return true;
762
763 case OPT_mwbnoinvd:
764 if (value)
765 {
766 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD_SET;
767 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_SET;
768 }
769 else
770 {
771 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WBNOINVD_UNSET;
772 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_UNSET;
773 }
774 return true;
775
776 case OPT_mavx512dq:
777 if (value)
778 {
779 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
780 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
781 }
782 else
783 {
784 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
785 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
786 }
787 return true;
788
789 case OPT_mavx512bw:
790 if (value)
791 {
792 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
793 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
794 }
795 else
796 {
797 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
798 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
799 }
800 return true;
801
802 case OPT_mavx512vl:
803 if (value)
804 {
805 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
806 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
807 }
808 else
809 {
810 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
811 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
812 }
813 return true;
814
815 case OPT_mavx512ifma:
816 if (value)
817 {
818 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
819 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
820 }
821 else
822 {
823 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
824 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
825 }
826 return true;
827
828 case OPT_mavx512vbmi:
829 if (value)
830 {
831 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
832 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
833 }
834 else
835 {
836 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
837 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
838 }
839 return true;
840
841 case OPT_mfma:
842 if (value)
843 {
844 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
845 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
846 }
847 else
848 {
849 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
850 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
851 }
852 return true;
853
854 case OPT_mrtm:
855 if (value)
856 {
857 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
858 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
859 }
860 else
861 {
862 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
863 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
864 }
865 return true;
866
867 case OPT_msse4:
868 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
869 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
870 return true;
871
872 case OPT_mno_sse4:
873 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
874 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
875 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
876 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
877 return true;
878
879 case OPT_msse4a:
880 if (value)
881 {
882 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
883 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
884 }
885 else
886 {
887 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
888 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
889 }
890 return true;
891
892 case OPT_mfma4:
893 if (value)
894 {
895 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
896 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
897 }
898 else
899 {
900 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
901 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
902 }
903 return true;
904
905 case OPT_mxop:
906 if (value)
907 {
908 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
909 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
910 }
911 else
912 {
913 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
914 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
915 }
916 return true;
917
918 case OPT_mlwp:
919 if (value)
920 {
921 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
922 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
923 }
924 else
925 {
926 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
927 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
928 }
929 return true;
930
931 case OPT_mabm:
932 if (value)
933 {
934 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
935 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
936 }
937 else
938 {
939 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
940 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
941 }
942 return true;
943
944 case OPT_mbmi:
945 if (value)
946 {
947 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
948 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
949 }
950 else
951 {
952 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
953 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
954 }
955 return true;
956
957 case OPT_mbmi2:
958 if (value)
959 {
960 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
961 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
962 }
963 else
964 {
965 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
966 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
967 }
968 return true;
969
970 case OPT_mlzcnt:
971 if (value)
972 {
973 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
974 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
975 }
976 else
977 {
978 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
979 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
980 }
981 return true;
982
983 case OPT_mtbm:
984 if (value)
985 {
986 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
987 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
988 }
989 else
990 {
991 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
992 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
993 }
994 return true;
995
996 case OPT_mpopcnt:
997 if (value)
998 {
999 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1000 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1001 }
1002 else
1003 {
1004 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1005 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1006 }
1007 return true;
1008
1009 case OPT_msahf:
1010 if (value)
1011 {
1012 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1013 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1014 }
1015 else
1016 {
1017 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1018 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1019 }
1020 return true;
1021
1022 case OPT_mcx16:
1023 if (value)
1024 {
1025 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16_SET;
1026 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_SET;
1027 }
1028 else
1029 {
1030 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CX16_UNSET;
1031 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_UNSET;
1032 }
1033 return true;
1034
1035 case OPT_mmovbe:
1036 if (value)
1037 {
1038 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE_SET;
1039 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_SET;
1040 }
1041 else
1042 {
1043 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVBE_UNSET;
1044 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
1045 }
1046 return true;
1047
1048 case OPT_mcrc32:
1049 if (value)
1050 {
1051 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1052 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1053 }
1054 else
1055 {
1056 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1057 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1058 }
1059 return true;
1060
1061 case OPT_maes:
1062 if (value)
1063 {
1064 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1065 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1066 }
1067 else
1068 {
1069 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1070 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1071 }
1072 return true;
1073
1074 case OPT_msha:
1075 if (value)
1076 {
1077 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1078 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1079 }
1080 else
1081 {
1082 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1083 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1084 }
1085 return true;
1086
1087 case OPT_mpclmul:
1088 if (value)
1089 {
1090 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1091 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1092 }
1093 else
1094 {
1095 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1096 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1097 }
1098 return true;
1099
1100 case OPT_mfsgsbase:
1101 if (value)
1102 {
1103 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1104 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1105 }
1106 else
1107 {
1108 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1109 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1110 }
1111 return true;
1112
1113 case OPT_mrdrnd:
1114 if (value)
1115 {
1116 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1117 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1118 }
1119 else
1120 {
1121 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1122 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1123 }
1124 return true;
1125
1126 case OPT_mf16c:
1127 if (value)
1128 {
1129 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1130 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1131 }
1132 else
1133 {
1134 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1135 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1136 }
1137 return true;
1138
1139 case OPT_mfxsr:
1140 if (value)
1141 {
1142 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1143 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1144 }
1145 else
1146 {
1147 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1148 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1149 }
1150 return true;
1151
1152 case OPT_mxsave:
1153 if (value)
1154 {
1155 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1156 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1157 }
1158 else
1159 {
1160 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1161 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1162 }
1163 return true;
1164
1165 case OPT_mxsaveopt:
1166 if (value)
1167 {
1168 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1169 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1170 }
1171 else
1172 {
1173 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1174 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1175 }
1176 return true;
1177
1178 case OPT_mxsavec:
1179 if (value)
1180 {
1181 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1182 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1183 }
1184 else
1185 {
1186 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1187 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1188 }
1189 return true;
1190
1191 case OPT_mxsaves:
1192 if (value)
1193 {
1194 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1195 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1196 }
1197 else
1198 {
1199 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1200 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1201 }
1202 return true;
1203
1204 case OPT_mrdseed:
1205 if (value)
1206 {
1207 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1208 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1209 }
1210 else
1211 {
1212 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1213 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1214 }
1215 return true;
1216
1217 case OPT_mprfchw:
1218 if (value)
1219 {
1220 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1221 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1222 }
1223 else
1224 {
1225 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1226 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1227 }
1228 return true;
1229
1230 case OPT_madx:
1231 if (value)
1232 {
1233 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1234 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1235 }
1236 else
1237 {
1238 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1239 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1240 }
1241 return true;
1242
1243 case OPT_mprefetchwt1:
1244 if (value)
1245 {
1246 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1247 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1248 }
1249 else
1250 {
1251 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1252 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1253 }
1254 return true;
1255
1256 case OPT_mclflushopt:
1257 if (value)
1258 {
1259 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1260 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1261 }
1262 else
1263 {
1264 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1265 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1266 }
1267 return true;
1268
1269 case OPT_mclwb:
1270 if (value)
1271 {
1272 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1273 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1274 }
1275 else
1276 {
1277 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1278 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1279 }
1280 return true;
1281
1282 case OPT_mmwaitx:
1283 if (value)
1284 {
1285 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX_SET;
1286 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_SET;
1287 }
1288 else
1289 {
1290 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MWAITX_UNSET;
1291 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_UNSET;
1292 }
1293 return true;
1294
1295 case OPT_mclzero:
1296 if (value)
1297 {
1298 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO_SET;
1299 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_SET;
1300 }
1301 else
1302 {
1303 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLZERO_UNSET;
1304 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_UNSET;
1305 }
1306 return true;
1307
1308 case OPT_mpku:
1309 if (value)
1310 {
1311 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1312 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1313 }
1314 else
1315 {
1316 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1317 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1318 }
1319 return true;
1320
1321
1322 case OPT_malign_loops_:
1323 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops");
1324 if (value > MAX_CODE_ALIGN)
1325 error_at (loc, "-malign-loops=%d is not between 0 and %d",
1326 value, MAX_CODE_ALIGN);
1327 else
1328 set_malign_value (&opts->x_str_align_loops, value);
1329 return true;
1330
1331 case OPT_malign_jumps_:
1332 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps");
1333 if (value > MAX_CODE_ALIGN)
1334 error_at (loc, "-malign-jumps=%d is not between 0 and %d",
1335 value, MAX_CODE_ALIGN);
1336 else
1337 set_malign_value (&opts->x_str_align_jumps, value);
1338 return true;
1339
1340 case OPT_malign_functions_:
1341 warning_at (loc, 0,
1342 "-malign-functions is obsolete, use -falign-functions");
1343 if (value > MAX_CODE_ALIGN)
1344 error_at (loc, "-malign-functions=%d is not between 0 and %d",
1345 value, MAX_CODE_ALIGN);
1346 else
1347 set_malign_value (&opts->x_str_align_functions, value);
1348 return true;
1349
1350 case OPT_mbranch_cost_:
1351 if (value > 5)
1352 {
1353 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value);
1354 opts->x_ix86_branch_cost = 5;
1355 }
1356 return true;
1357
1358 default:
1359 return true;
1360 }
1361 }
1362
1363 static const struct default_options ix86_option_optimization_table[] =
1364 {
1365 /* Enable redundant extension instructions removal at -O2 and higher. */
1366 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
1367 /* Enable function splitting at -O2 and higher. */
1368 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
1369 /* The STC algorithm produces the smallest code at -Os, for x86. */
1370 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
1371 REORDER_BLOCKS_ALGORITHM_STC },
1372 /* Turn off -fschedule-insns by default. It tends to make the
1373 problem with not enough registers even worse. */
1374 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
1375
1376 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1377 SUBTARGET_OPTIMIZATION_OPTIONS,
1378 #endif
1379 { OPT_LEVELS_NONE, 0, NULL, 0 }
1380 };
1381
1382 /* Implement TARGET_OPTION_INIT_STRUCT. */
1383
1384 static void
1385 ix86_option_init_struct (struct gcc_options *opts)
1386 {
1387 if (TARGET_MACHO)
1388 /* The Darwin libraries never set errno, so we might as well
1389 avoid calling them when that's the only reason we would. */
1390 opts->x_flag_errno_math = 0;
1391
1392 opts->x_flag_pcc_struct_return = 2;
1393 opts->x_flag_asynchronous_unwind_tables = 2;
1394 }
1395
1396 /* On the x86 -fsplit-stack and -fstack-protector both use the same
1397 field in the TCB, so they can not be used together. */
1398
1399 static bool
1400 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED,
1401 struct gcc_options *opts ATTRIBUTE_UNUSED)
1402 {
1403 bool ret = true;
1404
1405 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
1406 if (report)
1407 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1408 ret = false;
1409 #else
1410 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
1411 {
1412 if (report)
1413 error ("%<-fsplit-stack%> requires "
1414 "assembler support for CFI directives");
1415 ret = false;
1416 }
1417 #endif
1418
1419 return ret;
1420 }
1421
1422 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
1423
1424 static enum unwind_info_type
1425 i386_except_unwind_info (struct gcc_options *opts)
1426 {
1427 /* Honor the --enable-sjlj-exceptions configure switch. */
1428 #ifdef CONFIG_SJLJ_EXCEPTIONS
1429 if (CONFIG_SJLJ_EXCEPTIONS)
1430 return UI_SJLJ;
1431 #endif
1432
1433 /* On windows 64, prefer SEH exceptions over anything else. */
1434 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
1435 return UI_SEH;
1436
1437 if (DWARF2_UNWIND_INFO)
1438 return UI_DWARF2;
1439
1440 return UI_SJLJ;
1441 }
1442
1443 #undef TARGET_EXCEPT_UNWIND_INFO
1444 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
1445
1446 #undef TARGET_DEFAULT_TARGET_FLAGS
1447 #define TARGET_DEFAULT_TARGET_FLAGS \
1448 (TARGET_DEFAULT \
1449 | TARGET_SUBTARGET_DEFAULT \
1450 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1451
1452 #undef TARGET_HANDLE_OPTION
1453 #define TARGET_HANDLE_OPTION ix86_handle_option
1454
1455 #undef TARGET_OPTION_OPTIMIZATION_TABLE
1456 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
1457 #undef TARGET_OPTION_INIT_STRUCT
1458 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
1459
1460 #undef TARGET_SUPPORTS_SPLIT_STACK
1461 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1462
1463 /* This table must be in sync with enum processor_type in i386.h. */
1464 const char *const processor_names[PROCESSOR_max] =
1465 {
1466 "generic",
1467 "i386",
1468 "i486",
1469 "pentium",
1470 "lakemont",
1471 "pentiumpro",
1472 "pentium4",
1473 "nocona",
1474 "core2",
1475 "nehalem",
1476 "sandybridge",
1477 "haswell",
1478 "bonnell",
1479 "silvermont",
1480 "goldmont",
1481 "goldmont-plus",
1482 "tremont",
1483 "knl",
1484 "knm",
1485 "skylake",
1486 "skylake-avx512",
1487 "cannonlake",
1488 "icelake-client",
1489 "icelake-server",
1490 "intel",
1491 "geode",
1492 "k6",
1493 "athlon",
1494 "k8",
1495 "amdfam10",
1496 "bdver1",
1497 "bdver2",
1498 "bdver3",
1499 "bdver4",
1500 "btver1",
1501 "btver2",
1502 "znver1"
1503 };
1504
1505 const pta processor_alias_table[] =
1506 {
1507 {"i386", PROCESSOR_I386, CPU_NONE, 0},
1508 {"i486", PROCESSOR_I486, CPU_NONE, 0},
1509 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
1510 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
1511 {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
1512 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
1513 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
1514 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
1515 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
1516 {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
1517 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1518 PTA_MMX | PTA_SSE | PTA_FXSR},
1519 {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1520 PTA_MMX | PTA_SSE | PTA_FXSR},
1521 {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1522 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1523 {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1524 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1525 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
1526 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
1527 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
1528 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1529 PTA_MMX | PTA_SSE | PTA_FXSR},
1530 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1531 PTA_MMX | PTA_SSE | PTA_FXSR},
1532 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1533 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
1534 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
1535 PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
1536 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
1537 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
1538 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
1539 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1540 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
1541 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1542 | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
1543 {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
1544 {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
1545 {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
1546 {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
1547 {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1548 PTA_SANDYBRIDGE},
1549 {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1550 PTA_SANDYBRIDGE},
1551 {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1552 PTA_IVYBRIDGE},
1553 {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1554 PTA_IVYBRIDGE},
1555 {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
1556 {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
1557 {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
1558 {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
1559 {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
1560 PTA_SKYLAKE_AVX512},
1561 {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
1562 {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
1563 PTA_ICELAKE_CLIENT},
1564 {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
1565 PTA_ICELAKE_SERVER},
1566 {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
1567 {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
1568 {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
1569 {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
1570 {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
1571 {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
1572 {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
1573 {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
1574 {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
1575 {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
1576 {"geode", PROCESSOR_GEODE, CPU_GEODE,
1577 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
1578 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
1579 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
1580 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
1581 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
1582 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
1583 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
1584 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
1585 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
1586 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
1587 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
1588 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
1589 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
1590 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
1591 {"x86-64", PROCESSOR_K8, CPU_K8,
1592 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1593 {"eden-x2", PROCESSOR_K8, CPU_K8,
1594 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1595 {"nano", PROCESSOR_K8, CPU_K8,
1596 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1597 | PTA_SSSE3 | PTA_FXSR},
1598 {"nano-1000", PROCESSOR_K8, CPU_K8,
1599 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1600 | PTA_SSSE3 | PTA_FXSR},
1601 {"nano-2000", PROCESSOR_K8, CPU_K8,
1602 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1603 | PTA_SSSE3 | PTA_FXSR},
1604 {"nano-3000", PROCESSOR_K8, CPU_K8,
1605 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1606 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1607 {"nano-x2", PROCESSOR_K8, CPU_K8,
1608 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1609 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1610 {"eden-x4", PROCESSOR_K8, CPU_K8,
1611 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1612 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1613 {"nano-x4", PROCESSOR_K8, CPU_K8,
1614 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1615 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1616 {"k8", PROCESSOR_K8, CPU_K8,
1617 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1618 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1619 {"k8-sse3", PROCESSOR_K8, CPU_K8,
1620 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1621 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
1622 {"opteron", PROCESSOR_K8, CPU_K8,
1623 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1624 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1625 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
1626 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1627 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
1628 {"athlon64", PROCESSOR_K8, CPU_K8,
1629 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1630 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1631 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
1632 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1633 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
1634 {"athlon-fx", PROCESSOR_K8, CPU_K8,
1635 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1636 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1637 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
1638 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1639 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
1640 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
1641 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1642 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
1643 {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
1644 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1645 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1646 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1647 | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
1648 {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
1649 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1650 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1651 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1652 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
1653 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
1654 {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
1655 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1656 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1657 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1658 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
1659 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
1660 | PTA_XSAVEOPT | PTA_FSGSBASE},
1661 {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
1662 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1663 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1664 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
1665 | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
1666 | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
1667 | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
1668 | PTA_MOVBE | PTA_MWAITX},
1669 {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
1670 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1671 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1672 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
1673 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
1674 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
1675 | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
1676 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
1677 | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
1678 {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
1679 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1680 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
1681 | PTA_FXSR | PTA_XSAVE},
1682 {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
1683 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1684 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
1685 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
1686 | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
1687 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
1688
1689 {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
1690 PTA_64BIT
1691 | PTA_HLE /* flags are only used for -march switch. */ },
1692 };
1693
1694 int const pta_size = ARRAY_SIZE (processor_alias_table);
1695
1696 /* Provide valid option values for -march and -mtune options. */
1697
1698 vec<const char *>
1699 ix86_get_valid_option_values (int option_code,
1700 const char *prefix ATTRIBUTE_UNUSED)
1701 {
1702 vec<const char *> v;
1703 v.create (0);
1704 opt_code opt = (opt_code) option_code;
1705
1706 switch (opt)
1707 {
1708 case OPT_march_:
1709 for (unsigned i = 0; i < pta_size; i++)
1710 v.safe_push (processor_alias_table[i].name);
1711 break;
1712 case OPT_mtune_:
1713 for (unsigned i = 0; i < PROCESSOR_max; i++)
1714 v.safe_push (processor_names[i]);
1715 break;
1716 default:
1717 break;
1718 }
1719
1720 return v;
1721 }
1722
1723 #undef TARGET_GET_VALID_OPTION_VALUES
1724 #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
1725
1726 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
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