| blob | c81a2c645a292032a02a6e7fe67ec2f0323b73ce |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
57 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
58 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
60 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
61 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
62 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
65 /* Vector mapping INSN_UIDs to luids.
66 The luids are like uids but increase monotonically always.
67 We use them to see whether a jump comes from outside a given loop. */
71 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
72 number the insn is contained in. */
76 /* 1 + largest uid of any insn. */
80 /* 1 + luid of last insn. */
84 /* Number of loops detected in current function. Used as index to the
85 next few tables. */
89 /* Bound on pseudo register number before loop optimization.
90 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
93 /* The value to pass to the next call of reg_scan_update. */
96 #define obstack_chunk_alloc xmalloc
97 #define obstack_chunk_free free
98 \f
99 /* During the analysis of a loop, a chain of `struct movable's
100 is made to record all the movable insns found.
101 Then the entire chain can be scanned to decide which to move. */
103 struct movable
104 {
109 of any registers used within the LIBCALL. */
111 that must be moved with this one. */
114 may be adjusted when matching movables
115 that load the same value are found. */
117 including other movables that force this
118 or match this one. */
122 /* If PARTIAL is 1, GLOBAL means something different:
123 that the reg is live outside the range from where it is set
124 to the following label. */
128 In particular, moving it does not make it
129 invariant. */
131 load SRC, rather than copying INSN. */
133 first insn of a consecutive sets group. */
136 that we should avoid changing when clearing
137 the rest of the reg. */
141 };
146 /* Forward declarations. */
160 #if 0
162 #endif
192 rtx *));
273 {
274 rtx r1;
275 rtx r2;
279 {
280 rtx match;
281 rtx replacement;
282 rtx insn;
285 /* Nonzero iff INSN is between START and END, inclusive. */
286 #define INSN_IN_RANGE_P(INSN, START, END) \
287 (INSN_UID (INSN) < max_uid_for_loop \
288 && INSN_LUID (INSN) >= INSN_LUID (START) \
289 && INSN_LUID (INSN) <= INSN_LUID (END))
291 /* Indirect_jump_in_function is computed once per function. */
299 rtx));
300 \f
301 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
302 copy the value of the strength reduced giv to its original register. */
305 /* Cost of using a register, to normalize the benefits of a giv. */
308 void
310 {
316 }
317 \f
318 /* Compute the mapping from uids to luids.
319 LUIDs are numbers assigned to insns, like uids,
320 except that luids increase monotonically through the code.
321 Start at insn START and stop just before END. Assign LUIDs
322 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
323 static int
327 {
329 rtx insn;
332 {
335 /* Don't assign luids to line-number NOTEs, so that the distance in
336 luids between two insns is not affected by -g. */
340 else
341 /* Give a line number note the same luid as preceding insn. */
343 }
345 }
346 \f
347 /* Entry point of this file. Perform loop optimization
348 on the current function. F is the first insn of the function
349 and DUMPFILE is a stream for output of a trace of actions taken
350 (or 0 if none should be output). */
352 void
354 /* f is the first instruction of a chain of insns for one function */
355 rtx f;
358 {
359 rtx insn;
374 /* Count the number of loops. */
378 {
381 max_loop_num++;
382 }
384 /* Don't waste time if no loops. */
390 /* Get size to use for tables indexed by uids.
391 Leave some space for labels allocated by find_and_verify_loops. */
398 /* Allocate storage for array of loops. */
402 /* Find and process each loop.
403 First, find them, and record them in order of their beginnings. */
406 /* Allocate and initialize auxiliary loop information. */
411 /* Now find all register lifetimes. This must be done after
412 find_and_verify_loops, because it might reorder the insns in the
413 function. */
416 /* This must occur after reg_scan so that registers created by gcse
417 will have entries in the register tables.
419 We could have added a call to reg_scan after gcse_main in toplev.c,
420 but moving this call to init_alias_analysis is more efficient. */
423 /* See if we went too far. Note that get_max_uid already returns
424 one more that the maximum uid of all insn. */
427 /* Now reset it to the actual size we need. See above. */
430 /* find_and_verify_loops has already called compute_luids, but it
431 might have rearranged code afterwards, so we need to recompute
432 the luids now. */
435 /* Don't leave gaps in uid_luid for insns that have been
436 deleted. It is possible that the first or last insn
437 using some register has been deleted by cross-jumping.
438 Make sure that uid_luid for that former insn's uid
439 points to the general area where that insn used to be. */
441 {
445 }
450 /* Determine if the function has indirect jump. On some systems
451 this prevents low overhead loop instructions from being used. */
454 /* Now scan the loops, last ones first, since this means inner ones are done
455 before outer ones. */
457 {
462 }
464 /* If there were lexical blocks inside the loop, they have been
465 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
466 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
467 the BLOCKs as well. */
473 /* Clean up. */
478 }
479 \f
480 /* Returns the next insn, in execution order, after INSN. START and
481 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
482 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
483 insn-stream; it is used with loops that are entered near the
484 bottom. */
486 static rtx
489 rtx insn;
490 {
494 {
496 /* Go to the top of the loop, and continue there. */
498 else
499 /* We're done. */
501 }
504 /* We're done. */
508 }
510 /* Optimize one loop described by LOOP. */
512 /* ??? Could also move memory writes out of loops if the destination address
513 is invariant, the source is invariant, the memory write is not volatile,
514 and if we can prove that no read inside the loop can read this address
515 before the write occurs. If there is a read of this address after the
516 write, then we can also mark the memory read as invariant. */
518 static void
522 {
528 rtx p;
529 /* 1 if we are scanning insns that could be executed zero times. */
531 /* 1 if we are scanning insns that might never be executed
532 due to a subroutine call which might exit before they are reached. */
534 /* Jump insn that enters the loop, or 0 if control drops in. */
536 /* Number of insns in the loop. */
540 /* The SET from an insn, if it is the only SET in the insn. */
542 /* Chain describing insns movable in current loop. */
544 /* Ratio of extra register life span we can justify
545 for saving an instruction. More if loop doesn't call subroutines
546 since in that case saving an insn makes more difference
547 and more registers are available. */
549 /* Nonzero if we are scanning instructions in a sub-loop. */
557 /* Determine whether this loop starts with a jump down to a test at
558 the end. This will occur for a small number of loops with a test
559 that is too complex to duplicate in front of the loop.
561 We search for the first insn or label in the loop, skipping NOTEs.
562 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
563 (because we might have a loop executed only once that contains a
564 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
565 (in case we have a degenerate loop).
567 Note that if we mistakenly think that a loop is entered at the top
568 when, in fact, it is entered at the exit test, the only effect will be
569 slightly poorer optimization. Making the opposite error can generate
570 incorrect code. Since very few loops now start with a jump to the
571 exit test, the code here to detect that case is very conservative. */
574 p != loop_end
580 ;
584 /* If loop end is the end of the current function, then emit a
585 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
586 note insn. This is the position we use when sinking insns out of
587 the loop. */
590 else
593 /* Set up variables describing this loop. */
597 /* If loop has a jump before the first label,
598 the true entry is the target of that jump.
599 Start scan from there.
600 But record in LOOP->TOP the place where the end-test jumps
601 back to so we can scan that after the end of the loop. */
603 {
606 /* Loop entry must be unconditional jump (and not a RETURN) */
609 /* Check to see whether the jump actually
610 jumps out of the loop (meaning it's no loop).
611 This case can happen for things like
612 do {..} while (0). If this label was generated previously
613 by loop, we can't tell anything about it and have to reject
614 the loop. */
616 {
619 }
620 }
622 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
623 as required by loop_reg_used_before_p. So skip such loops. (This
624 test may never be true, but it's best to play it safe.)
626 Also, skip loops where we do not start scanning at a label. This
627 test also rejects loops starting with a JUMP_INSN that failed the
628 test above. */
632 {
637 }
639 /* Allocate extra space for REGs that might be created by load_mems.
640 We allocate a little extra slop as well, in the hopes that we
641 won't have to reallocate the regs array. */
646 {
652 }
654 /* Scan through the loop finding insns that are safe to move.
655 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
656 this reg will be considered invariant for subsequent insns.
657 We consider whether subsequent insns use the reg
658 in deciding whether it is worth actually moving.
660 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
661 and therefore it is possible that the insns we are scanning
662 would never be executed. At such times, we must make sure
663 that it is safe to execute the insn once instead of zero times.
664 When MAYBE_NEVER is 0, all insns will be executed at least once
665 so that is not a problem. */
670 {
675 {
682 /* Figure out what to use as a source of this insn. If a REG_EQUIV
683 note is given or if a REG_EQUAL note with a constant operand is
684 specified, use it as the source and mark that we should move
685 this insn by calling emit_move_insn rather that duplicating the
686 insn.
688 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
689 is present. */
693 else
694 {
699 {
701 /* A libcall block can use regs that don't appear in
702 the equivalent expression. To move the libcall,
703 we must move those regs too. */
705 }
706 }
708 /* For parallels, add any possible uses to the depencies, as we can't move
709 the insn without resolving them first. */
711 {
713 {
717 }
718 }
720 /* Don't try to optimize a register that was made
721 by loop-optimization for an inner loop.
722 We don't know its life-span, so we can't compute the benefit. */
724 ;
726 than the one where it is set (meaning that
727 something after this point in the loop might
728 depend on its value before the set). */
730 /* And the set is not guaranteed to be executed once
731 the loop starts, or the value before the set is
732 needed before the set occurs...
734 ??? Note we have quadratic behaviour here, mitigated
735 by the fact that the previous test will often fail for
736 large loops. Rather than re-scanning the entire loop
737 each time for register usage, we should build tables
738 of the register usage and use them here instead. */
739 && (maybe_never
741 /* It is unsafe to move the set.
743 This code used to consider it OK to move a set of a variable
744 which was not created by the user and not used in an exit test.
745 That behavior is incorrect and was removed. */
746 ;
751 || (tem1
752 = consec_sets_invariant_p
755 p)))
756 /* If the insn can cause a trap (such as divide by zero),
757 can't move it unless it's guaranteed to be executed
758 once loop is entered. Even a function call might
759 prevent the trap insn from being reached
760 (since it might exit!) */
763 {
767 /* A potential lossage is where we have a case where two insns
768 can be combined as long as they are both in the loop, but
769 we move one of them outside the loop. For large loops,
770 this can lose. The most common case of this is the address
771 of a function being called.
773 Therefore, if this register is marked as being used exactly
774 once if we are in a loop with calls (a "large loop"), see if
775 we can replace the usage of this register with the source
776 of this SET. If we can, delete this insn.
778 Don't do this if P has a REG_RETVAL note or if we have
779 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
791 && (! SMALL_REGISTER_CLASSES
794 /* This test is not redundant; SET_SRC (set) might be
795 a call-clobbered register and the life of REGNO
796 might span a call. */
802 {
803 /* Replace any usage in a REG_EQUAL note. Must copy the
804 new source, so that we don't get rtx sharing between the
805 SET_SOURCE and REG_NOTES of insn p. */
813 }
831 /* Set M->cond if either loop_invariant_p
832 or consec_sets_invariant_p returned 2
833 (only conditionally invariant). */
842 /* Add M to the end of the chain MOVABLES. */
846 {
847 /* It is possible for the first instruction to have a
848 REG_EQUAL note but a non-invariant SET_SRC, so we must
849 remember the status of the first instruction in case
850 the last instruction doesn't have a REG_EQUAL note. */
853 /* Skip this insn, not checking REG_LIBCALL notes. */
855 /* Skip the consecutive insns, if there are any. */
857 /* Back up to the last insn of the consecutive group. */
860 /* We must now reset m->move_insn, m->is_equiv, and possibly
861 m->set_src to correspond to the effects of all the
862 insns. */
866 else
867 {
871 else
874 }
876 }
877 }
878 /* If this register is always set within a STRICT_LOW_PART
879 or set to zero, then its high bytes are constant.
880 So clear them outside the loop and within the loop
881 just load the low bytes.
882 We must check that the machine has an instruction to do so.
883 Also, if the value loaded into the register
884 depends on the same register, this cannot be done. */
894 {
897 {
911 /* If the insn may not be executed on some cycles,
912 we can't clear the whole reg; clear just high part.
913 Not even if the reg is used only within this loop.
914 Consider this:
915 while (1)
916 while (s != t) {
917 if (foo ()) x = *s;
918 use (x);
919 }
920 Clearing x before the inner loop could clobber a value
921 being saved from the last time around the outer loop.
922 However, if the reg is not used outside this loop
923 and all uses of the register are in the same
924 basic block as the store, there is no problem.
926 If this insn was made by loop, we don't know its
927 INSN_LUID and hence must make a conservative
928 assumption. */
931 || (labels_in_range_p
935 else
943 /* Add M to the end of the chain MOVABLES. */
945 }
946 }
947 }
948 /* Past a call insn, we get to insns which might not be executed
949 because the call might exit. This matters for insns that trap.
950 Constant and pure call insns always return, so they don't count. */
953 /* Past a label or a jump, we get to insns for which we
954 can't count on whether or how many times they will be
955 executed during each iteration. Therefore, we can
956 only move out sets of trivial variables
957 (those not used after the loop). */
958 /* Similar code appears twice in strength_reduce. */
960 /* If we enter the loop in the middle, and scan around to the
961 beginning, don't set maybe_never for that. This must be an
962 unconditional jump, otherwise the code at the top of the
963 loop might never be executed. Unconditional jumps are
964 followed by a barrier then the loop_end. */
970 {
971 /* At the virtual top of a converted loop, insns are again known to
972 be executed: logically, the loop begins here even though the exit
973 code has been duplicated. */
977 loop_depth++;
979 loop_depth--;
980 }
981 }
983 /* If one movable subsumes another, ignore that other. */
987 /* For each movable insn, see if the reg that it loads
988 leads when it dies right into another conditionally movable insn.
989 If so, record that the second insn "forces" the first one,
990 since the second can be moved only if the first is. */
994 /* See if there are multiple movable insns that load the same value.
995 If there are, make all but the first point at the first one
996 through the `match' field, and add the priorities of them
997 all together as the priority of the first. */
1001 /* Now consider each movable insn to decide whether it is worth moving.
1002 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1004 Generally this increases code size, so do not move moveables when
1005 optimizing for code size. */
1010 /* Now candidates that still are negative are those not moved.
1011 Change regs->array[I].set_in_loop to indicate that those are not actually
1012 invariant. */
1017 /* Now that we've moved some things out of the loop, we might be able to
1018 hoist even more memory references. */
1021 /* Recalculate regs->array if load_mems has created new registers. */
1029 ;
1036 {
1038 /* Ensure our label doesn't go away. */
1049 }
1052 /* The movable information is required for strength reduction. */
1058 }
1059 \f
1060 /* Add elements to *OUTPUT to record all the pseudo-regs
1061 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1063 void
1067 {
1075 {
1093 }
1097 {
1101 {
1110 }
1111 }
1112 }
1113 \f
1114 /* Check what regs are referred to in the libcall block ending with INSN,
1115 aside from those mentioned in the equivalent value.
1116 If there are none, return 0.
1117 If there are one or more, return an EXPR_LIST containing all of them. */
1119 rtx
1122 {
1127 /* First, find all the regs used in the libcall block
1128 that are not mentioned as inputs to the result. */
1131 {
1136 }
1139 }
1140 \f
1141 /* Return 1 if all uses of REG
1142 are between INSN and the end of the basic block. */
1144 static int
1147 {
1149 rtx p;
1154 /* Search this basic block for the already recorded last use of the reg. */
1156 {
1158 {
1164 /* Ordinary insn: if this is the last use, we win. */
1170 /* Jump insn: if this is the last use, we win. */
1173 /* Otherwise, it's the end of the basic block, so we lose. */
1178 /* It's the end of the basic block, so we lose. */
1183 }
1184 }
1186 /* The "last use" that was recorded can't be found after the first
1187 use. This can happen when the last use was deleted while
1188 processing an inner loop, this inner loop was then completely
1189 unrolled, and the outer loop is always exited after the inner loop,
1190 so that everything after the first use becomes a single basic block. */
1192 }
1193 \f
1194 /* Compute the benefit of eliminating the insns in the block whose
1195 last insn is LAST. This may be a group of insns used to compute a
1196 value directly or can contain a library call. */
1198 static int
1200 rtx last;
1201 {
1202 rtx insn;
1207 {
1210 routine. */
1214 benefit++;
1215 }
1218 }
1219 \f
1220 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1222 static rtx
1224 rtx insn;
1226 {
1228 {
1229 rtx temp;
1231 /* If first insn of libcall sequence, skip to end. */
1232 /* Do this at start of loop, since INSN is guaranteed to
1233 be an insn here. */
1238 do
1241 }
1244 }
1246 /* Ignore any movable whose insn falls within a libcall
1247 which is part of another movable.
1248 We make use of the fact that the movable for the libcall value
1249 was made later and so appears later on the chain. */
1251 static void
1254 {
1258 {
1259 /* Is this a movable for the value of a libcall? */
1262 {
1263 rtx insn;
1264 /* Check for earlier movables inside that range,
1265 and mark them invalid. We cannot use LUIDs here because
1266 insns created by loop.c for prior loops don't have LUIDs.
1267 Rather than reject all such insns from movables, we just
1268 explicitly check each insn in the libcall (since invariant
1269 libcalls aren't that common). */
1274 }
1275 }
1276 }
1278 /* For each movable insn, see if the reg that it loads
1279 leads when it dies right into another conditionally movable insn.
1280 If so, record that the second insn "forces" the first one,
1281 since the second can be moved only if the first is. */
1283 static void
1286 {
1290 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1292 {
1295 /* ??? Could this be a bug? What if CSE caused the
1296 register of M1 to be used after this insn?
1297 Since CSE does not update regno_last_uid,
1298 this insn M->insn might not be where it dies.
1299 But very likely this doesn't matter; what matters is
1300 that M's reg is computed from M1's reg. */
1305 /* If m->consec, m->set_src isn't valid. */
1309 /* Increase the priority of the moving the first insn
1310 since it permits the second to be moved as well. */
1312 {
1316 }
1317 }
1318 }
1319 \f
1320 /* Find invariant expressions that are equal and can be combined into
1321 one register. */
1323 static void
1327 {
1332 /* Regs that are set more than once are not allowed to match
1333 or be matched. I'm no longer sure why not. */
1334 /* Perhaps testing m->consec_sets would be more appropriate here? */
1339 {
1346 /* We want later insns to match the first one. Don't make the first
1347 one match any later ones. So start this loop at m->next. */
1351 /* A reg used outside the loop mustn't be eliminated. */
1353 /* A reg used for zero-extending mustn't be eliminated. */
1356 ||
1357 (
1358 /* Can combine regs with different modes loaded from the
1359 same constant only if the modes are the same or
1360 if both are integer modes with M wider or the same
1361 width as M1. The check for integer is redundant, but
1362 safe, since the only case of differing destination
1363 modes with equal sources is when both sources are
1364 VOIDmode, i.e., CONST_INT. */
1370 /* See if the source of M1 says it matches M. */
1377 {
1383 }
1384 }
1386 /* Now combine the regs used for zero-extension.
1387 This can be done for those not marked `global'
1388 provided their lives don't overlap. */
1392 {
1395 /* Combine all the registers for extension from mode MODE.
1396 Don't combine any that are used outside this loop. */
1400 {
1407 {
1408 /* First one: don't check for overlap, just record it. */
1411 }
1413 /* Make sure they extend to the same mode.
1414 (Almost always true.) */
1418 /* We already have one: check for overlap with those
1419 already combined together. */
1426 /* No overlap: we can combine this with the others. */
1432 overlap:
1433 ;
1434 }
1435 }
1437 /* Clean up. */
1439 }
1441 /* Returns the number of movable instructions in LOOP that were not
1442 moved outside the loop. */
1444 static int
1447 {
1456 }
1458 \f
1459 /* Return 1 if regs X and Y will become the same if moved. */
1461 static int
1465 {
1482 }
1484 /* Return 1 if X and Y are identical-looking rtx's.
1485 This is the Lisp function EQUAL for rtx arguments.
1487 If two registers are matching movables or a movable register and an
1488 equivalent constant, consider them equal. */
1490 static int
1495 {
1509 /* If we have a register and a constant, they may sometimes be
1510 equal. */
1513 {
1518 }
1521 {
1526 }
1528 /* Otherwise, rtx's of different codes cannot be equal. */
1532 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1533 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1538 /* These three types of rtx's can be compared nonrecursively. */
1547 /* Compare the elements. If any pair of corresponding elements
1548 fail to match, return 0 for the whole things. */
1552 {
1554 {
1566 /* Two vectors must have the same length. */
1570 /* And the corresponding elements must match. */
1589 /* These are just backpointers, so they don't matter. */
1595 /* It is believed that rtx's at this level will never
1596 contain anything but integers and other rtx's,
1597 except for within LABEL_REFs and SYMBOL_REFs. */
1600 }
1601 }
1603 }
1604 \f
1605 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1606 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1607 references is incremented once for each added note. */
1609 static void
1611 rtx x;
1612 rtx insns;
1613 {
1617 rtx insn;
1620 {
1621 /* This code used to ignore labels that referred to dispatch tables to
1622 avoid flow generating (slighly) worse code.
1624 We no longer ignore such label references (see LABEL_REF handling in
1625 mark_jump_label for additional information). */
1628 {
1633 }
1634 }
1638 {
1644 }
1645 }
1646 \f
1647 /* Scan MOVABLES, and move the insns that deserve to be moved.
1648 If two matching movables are combined, replace one reg with the
1649 other throughout. */
1651 static void
1657 {
1662 rtx p;
1665 /* Map of pseudo-register replacements to handle combining
1666 when we move several insns that load the same value
1667 into different pseudo-registers. */
1672 {
1673 /* Describe this movable insn. */
1676 {
1697 }
1699 /* Ignore the insn if it's already done (it matched something else).
1700 Otherwise, see if it is now safe to move. */
1712 {
1714 rtx p;
1717 /* We have an insn that is safe to move.
1718 Compute its desirability. */
1729 /* An insn MUST be moved if we already moved something else
1730 which is safe only if this one is moved too: that is,
1731 if already_moved[REGNO] is nonzero. */
1733 /* An insn is desirable to move if the new lifetime of the
1734 register is no more than THRESHOLD times the old lifetime.
1735 If it's not desirable, it means the loop is so big
1736 that moving won't speed things up much,
1737 and it is liable to make register usage worse. */
1739 /* It is also desirable to move if it can be moved at no
1740 extra cost because something else was already moved. */
1743 || flag_move_all_movables
1748 {
1753 /* Now move the insns that set the reg. */
1756 {
1759 /* Find the end of this chain of matching regs.
1760 Thus, we load each reg in the chain from that one reg.
1761 And that reg is loaded with 0 directly,
1762 since it has ->match == 0. */
1768 /* Mark the moved, invariant reg as being allowed to
1769 share a hard reg with the other matching invariant. */
1773 regs_may_share
1776 regs_may_share));
1784 }
1785 /* If we are to re-generate the item being moved with a
1786 new move insn, first delete what we have and then emit
1787 the move insn before the loop. */
1789 {
1793 {
1794 /* If this is the first insn of a library call sequence,
1795 skip to the end. */
1800 /* If this is the last insn of a libcall sequence, then
1801 delete every insn in the sequence except the last.
1802 The last insn is handled in the normal manner. */
1805 {
1809 }
1814 /* simplify_giv_expr expects that it can walk the insns
1815 at m->insn forwards and see this old sequence we are
1816 tossing here. delete_insn does preserve the next
1817 pointers, but when we skip over a NOTE we must fix
1818 it up. Otherwise that code walks into the non-deleted
1819 insn stream. */
1822 }
1841 /* The more regs we move, the less we like moving them. */
1843 }
1844 else
1845 {
1847 {
1850 /* If first insn of libcall sequence, skip to end. */
1851 /* Do this at start of loop, since p is guaranteed to
1852 be an insn here. */
1857 /* If last insn of libcall sequence, move all
1858 insns except the last before the loop. The last
1859 insn is handled in the normal manner. */
1862 {
1870 {
1871 rtx body;
1872 rtx n;
1873 rtx next;
1880 /* Find the next insn after TEMP,
1881 not counting USE or NOTE insns. */
1889 /* If that is the call, this may be the insn
1890 that loads the function address.
1892 Extract the function address from the insn
1893 that loads it into a register.
1894 If this insn was cse'd, we get incorrect code.
1896 So emit a new move insn that copies the
1897 function address into the register that the
1898 call insn will use. flow.c will delete any
1899 redundant stores that we have created. */
1904 NULL_RTX)))
1905 {
1911 }
1912 /* We have the call insn.
1913 If it uses the register we suspect it might,
1914 load it with the correct address directly. */
1919 gen_move_insn
1923 {
1925 /* Because the USAGE information potentially
1926 contains objects other than hard registers
1927 we need to copy it. */
1931 }
1932 else
1941 }
1944 }
1946 {
1947 /* P sets REG to zero; but we should clear only
1948 the bits that are not covered by the mode
1949 m->savemode. */
1951 rtx sequence;
1952 rtx tem;
1955 tem = expand_simple_binop
1968 }
1970 {
1972 /* Because the USAGE information potentially
1973 contains objects other than hard registers
1974 we need to copy it. */
1978 }
1980 {
1981 rtx seq;
1982 /* The SET_SRC might not be invariant, so we must
1983 use the REG_EQUAL note. */
1998 }
1999 else
2003 {
2007 /* If there is a REG_EQUAL note present whose value
2008 is not loop invariant, then delete it, since it
2009 may cause problems with later optimization passes.
2010 It is possible for cse to create such notes
2011 like this as a result of record_jump_cond. */
2016 }
2025 /* If library call, now fix the REG_NOTES that contain
2026 insn pointers, namely REG_LIBCALL on FIRST
2027 and REG_RETVAL on I1. */
2029 {
2033 }
2039 /* simplify_giv_expr expects that it can walk the insns
2040 at m->insn forwards and see this old sequence we are
2041 tossing here. delete_insn does preserve the next
2042 pointers, but when we skip over a NOTE we must fix
2043 it up. Otherwise that code walks into the non-deleted
2044 insn stream. */
2047 }
2049 /* The more regs we move, the less we like moving them. */
2051 }
2053 /* Any other movable that loads the same register
2054 MUST be moved. */
2057 /* This reg has been moved out of one loop. */
2060 /* The reg set here is now invariant. */
2066 /* Change the length-of-life info for the register
2067 to say it lives at least the full length of this loop.
2068 This will help guide optimizations in outer loops. */
2071 /* This is the old insn before all the moved insns.
2072 We can't use the moved insn because it is out of range
2073 in uid_luid. Only the old insns have luids. */
2078 /* Combine with this moved insn any other matching movables. */
2083 {
2084 rtx temp;
2086 /* Schedule the reg loaded by M1
2087 for replacement so that shares the reg of M.
2088 If the modes differ (only possible in restricted
2089 circumstances, make a SUBREG.
2091 Note this assumes that the target dependent files
2092 treat REG and SUBREG equally, including within
2093 GO_IF_LEGITIMATE_ADDRESS and in all the
2094 predicates since we never verify that replacing the
2095 original register with a SUBREG results in a
2096 recognizable insn. */
2099 else
2104 /* Get rid of the matching insn
2105 and prevent further processing of it. */
2108 /* if library call, delete all insns. */
2110 NULL_RTX)))
2112 else
2115 /* Any other movable that loads the same register
2116 MUST be moved. */
2119 /* The reg merged here is now invariant,
2120 if the reg it matches is invariant. */
2123 }
2124 }
2127 }
2133 }
2138 /* Go through all the instructions in the loop, making
2139 all the register substitutions scheduled in REG_MAP. */
2143 {
2147 }
2149 /* Clean up. */
2152 }
2155 static void
2159 {
2162 else
2165 }
2168 static void
2171 {
2176 {
2179 }
2180 }
2181 \f
2182 #if 0
2183 /* Scan X and replace the address of any MEM in it with ADDR.
2184 REG is the address that MEM should have before the replacement. */
2186 static void
2189 {
2198 {
2210 /* Short cut for very common case. */
2215 /* Short cut for very common case. */
2220 /* If this MEM uses a reg other than the one we expected,
2221 something is wrong. */
2229 }
2233 {
2237 {
2241 }
2242 }
2243 }
2244 #endif
2245 \f
2246 /* Return the number of memory refs to addresses that vary
2247 in the rtx X. */
2249 static int
2252 rtx x;
2253 {
2264 {
2281 }
2286 {
2290 {
2294 }
2295 }
2297 }
2298 \f
2299 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2300 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2301 `unknown_address_altered', `unknown_constant_address_altered', and
2302 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2303 list `store_mems' in LOOP. */
2305 static void
2308 {
2310 rtx insn;
2314 /* The label after END. Jumping here is just like falling off the
2315 end of the loop. We use next_nonnote_insn instead of next_label
2316 as a hedge against the (pathological) case where some actual insn
2317 might end up between the two. */
2339 {
2341 {
2344 }
2345 }
2349 {
2351 {
2353 {
2355 /* Count number of loops contained in this one. */
2357 }
2359 {
2361 }
2362 }
2364 {
2366 {
2369 }
2371 }
2373 {
2393 {
2395 {
2398 }
2399 else
2400 {
2402 }
2404 do
2405 {
2407 {
2409 {
2410 /* Something tricky. */
2413 }
2416 {
2417 /* A jump outside the current loop. */
2420 }
2421 }
2425 }
2427 }
2428 }
2431 }
2433 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2435 anywhere. */
2437 /* We don't want loads for MEMs moved to a location before the
2438 one at which their stack memory becomes allocated. (Note
2439 that this is not a problem for malloc, etc., since those
2440 require actual function calls. */
2441 && ! current_function_calls_alloca
2442 /* There are ways to leave the loop other than falling off the
2443 end. */
2449 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2450 that loop_invariant_p and load_mems can use true_dependence
2451 to determine what is really clobbered. */
2453 {
2456 loop_info->store_mems
2458 }
2460 {
2464 loop_info->store_mems
2466 }
2467 }
2468 \f
2469 /* Scan the function looking for loops. Record the start and end of each loop.
2470 Also mark as invalid loops any loops that contain a setjmp or are branched
2471 to from outside the loop. */
2473 static void
2475 rtx f;
2477 {
2478 rtx insn;
2479 rtx label;
2489 /* If there are jumps to undefined labels,
2490 treat them as jumps out of any/all loops.
2491 This also avoids writing past end of tables when there are no loops. */
2494 /* Find boundaries of loops, mark which loops are contained within
2495 loops, and invalidate loops that have setjmp. */
2500 {
2503 {
2507 num_loops++;
2531 }
2535 {
2536 /* In this case, we must invalidate our current loop and any
2537 enclosing loop. */
2539 {
2545 }
2546 }
2548 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2549 enclosing loop, but this doesn't matter. */
2551 }
2553 /* Any loop containing a label used in an initializer must be invalidated,
2554 because it can be jumped into from anywhere. */
2557 {
2561 }
2563 /* Any loop containing a label used for an exception handler must be
2564 invalidated, because it can be jumped into from anywhere. */
2567 {
2571 }
2573 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2574 loop that it is not contained within, that loop is marked invalid.
2575 If any INSN or CALL_INSN uses a label's address, then the loop containing
2576 that label is marked invalid, because it could be jumped into from
2577 anywhere.
2579 Also look for blocks of code ending in an unconditional branch that
2580 exits the loop. If such a block is surrounded by a conditional
2581 branch around the block, move the block elsewhere (see below) and
2582 invert the jump to point to the code block. This may eliminate a
2583 label in our loop and will simplify processing by both us and a
2584 possible second cse pass. */
2588 {
2592 {
2595 {
2599 }
2600 }
2607 /* See if this is an unconditional branch outside the loop. */
2615 {
2616 rtx p;
2622 /* Go backwards until we reach the start of the loop, a label,
2623 or a JUMP_INSN. */
2630 ;
2632 /* Check for the case where we have a jump to an inner nested
2633 loop, and do not perform the optimization in that case. */
2636 {
2639 {
2644 }
2645 }
2647 /* Make sure that the target of P is within the current loop. */
2653 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2654 we have a block of code to try to move.
2656 We look backward and then forward from the target of INSN
2657 to find a BARRIER at the same loop depth as the target.
2658 If we find such a BARRIER, we make a new label for the start
2659 of the block, invert the jump in P and point it to that label,
2660 and move the block of code to the spot we found. */
2665 /* Just ignore jumps to labels that were never emitted.
2666 These always indicate compilation errors. */
2670 /* If it's not safe to move the sequence, then we
2671 mustn't try. */
2674 {
2675 rtx target
2679 rtx tmp;
2681 /* Search for possible garbage past the conditional jumps
2682 and look for the last barrier. */
2690 /* Don't move things inside a tablejump. */
2703 /* Don't move things inside a tablejump. */
2714 {
2718 /* Ensure our label doesn't go away. */
2721 /* Verify that uid_loop is large enough and that
2722 we can invert P. */
2724 {
2727 /* If no suitable BARRIER was found, create a suitable
2728 one before TARGET. Since TARGET is a fall through
2729 path, we'll need to insert an jump around our block
2730 and add a BARRIER before TARGET.
2732 This creates an extra unconditional jump outside
2733 the loop. However, the benefits of removing rarely
2734 executed instructions from inside the loop usually
2735 outweighs the cost of the extra unconditional jump
2736 outside the loop. */
2738 {
2739 rtx temp;
2746 }
2748 /* Include the BARRIER after INSN and copy the
2749 block after LOC. */
2753 /* All those insns are now in TARGET_LOOP. */
2759 /* The label jumped to by INSN is no longer a loop
2760 exit. Unless INSN does not have a label (e.g.,
2761 it is a RETURN insn), search loop->exit_labels
2762 to find its label_ref, and remove it. Also turn
2763 off LABEL_OUTSIDE_LOOP_P bit. */
2765 {
2767 r;
2770 {
2774 else
2777 }
2783 /* If we didn't find it, then something is
2784 wrong. */
2787 }
2789 /* P is now a jump outside the loop, so it must be put
2790 in loop->exit_labels, and marked as such.
2791 The easiest way to do this is to just call
2792 mark_loop_jump again for P. */
2795 /* If INSN now jumps to the insn after it,
2796 delete INSN. */
2801 }
2803 /* Continue the loop after where the conditional
2804 branch used to jump, since the only branch insn
2805 in the block (if it still remains) is an inter-loop
2806 branch and hence needs no processing. */
2812 /* This loop will be continued with NEXT_INSN (insn). */
2814 }
2815 }
2816 }
2817 }
2818 }
2820 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2821 loops it is contained in, mark the target loop invalid.
2823 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2825 static void
2827 rtx x;
2829 {
2835 {
2847 /* There could be a label reference in here. */
2859 /* This may refer to a LABEL_REF or SYMBOL_REF. */
2871 /* Link together all labels that branch outside the loop. This
2872 is used by final_[bg]iv_value and the loop unrolling code. Also
2873 mark this LABEL_REF so we know that this branch should predict
2874 false. */
2876 /* A check to make sure the label is not in an inner nested loop,
2877 since this does not count as a loop exit. */
2879 {
2884 }
2885 else
2889 {
2898 }
2900 /* If this is inside a loop, but not in the current loop or one enclosed
2901 by it, it invalidates at least one loop. */
2906 /* We must invalidate every nested loop containing the target of this
2907 label, except those that also contain the jump insn. */
2910 {
2911 /* Stop when we reach a loop that also contains the jump insn. */
2916 /* If we get here, we know we need to invalidate a loop. */
2923 }
2927 /* If this is not setting pc, ignore. */
2949 /* Strictly speaking this is not a jump into the loop, only a possible
2950 jump out of the loop. However, we have no way to link the destination
2951 of this jump onto the list of exit labels. To be safe we mark this
2952 loop and any containing loops as invalid. */
2954 {
2956 {
2962 }
2963 }
2965 }
2966 }
2967 \f
2968 /* Return nonzero if there is a label in the range from
2969 insn INSN to and including the insn whose luid is END
2970 INSN must have an assigned luid (i.e., it must not have
2971 been previously created by loop.c). */
2973 static int
2975 rtx insn;
2977 {
2979 {
2983 }
2986 }
2988 /* Record that a memory reference X is being set. */
2990 static void
2992 rtx x;
2993 rtx y ATTRIBUTE_UNUSED;
2995 {
3001 /* Count number of memory writes.
3002 This affects heuristics in strength_reduce. */
3005 /* BLKmode MEM means all memory is clobbered. */
3007 {
3010 else
3014 }
3018 }
3020 /* X is a value modified by an INSN that references a biv inside a loop
3021 exit test (ie, X is somehow related to the value of the biv). If X
3022 is a pseudo that is used more than once, then the biv is (effectively)
3023 used more than once. DATA is a pointer to a loop_regs structure. */
3025 static void
3027 rtx x;
3028 rtx y ATTRIBUTE_UNUSED;
3030 {
3045 /* If we do not have usage information, or if we know the register
3046 is used more than once, note that fact for check_dbra_loop. */
3051 }
3052 \f
3053 /* Return nonzero if the rtx X is invariant over the current loop.
3055 The value is 2 if we refer to something only conditionally invariant.
3057 A memory ref is invariant if it is not volatile and does not conflict
3058 with anything stored in `loop_info->store_mems'. */
3060 int
3063 rtx x;
3064 {
3071 rtx mem_list_entry;
3077 {
3085 /* A LABEL_REF is normally invariant, however, if we are unrolling
3086 loops, and this label is inside the loop, then it isn't invariant.
3087 This is because each unrolled copy of the loop body will have
3088 a copy of this label. If this was invariant, then an insn loading
3089 the address of this label into a register might get moved outside
3090 the loop, and then each loop body would end up using the same label.
3092 We don't know the loop bounds here though, so just fail for all
3093 labels. */
3096 else
3105 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3106 since the reg might be set by initialization within the loop. */
3123 /* Volatile memory references must be rejected. Do this before
3124 checking for read-only items, so that volatile read-only items
3125 will be rejected also. */
3129 /* See if there is any dependence between a store and this load. */
3132 {
3138 }
3140 /* It's not invalidated by a store in memory
3141 but we must still verify the address is invariant. */
3145 /* Don't mess with insns declared volatile. */
3152 }
3156 {
3158 {
3164 }
3166 {
3169 {
3175 }
3177 }
3178 }
3181 }
3182 \f
3183 /* Return nonzero if all the insns in the loop that set REG
3184 are INSN and the immediately following insns,
3185 and if each of those insns sets REG in an invariant way
3186 (not counting uses of REG in them).
3188 The value is 2 if some of these insns are only conditionally invariant.
3190 We assume that INSN itself is the first set of REG
3191 and that its source is invariant. */
3193 static int
3198 {
3202 rtx temp;
3203 /* Number of sets we have to insist on finding after INSN. */
3209 /* If N_SETS hit the limit, we can't rely on its value. */
3216 {
3218 rtx set;
3223 /* If library call, skip to end of it. */
3232 {
3237 {
3238 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3239 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3240 notes are OK. */
3246 }
3247 }
3249 count--;
3251 {
3254 }
3255 }
3258 /* If loop_invariant_p ever returned 2, we return 2. */
3260 }
3262 #if 0
3263 /* I don't think this condition is sufficient to allow INSN
3264 to be moved, so we no longer test it. */
3266 /* Return 1 if all insns in the basic block of INSN and following INSN
3267 that set REG are invariant according to TABLE. */
3269 static int
3273 {
3278 {
3287 {
3290 }
3291 }
3292 }
3294 \f
3295 /* Look at all uses (not sets) of registers in X. For each, if it is
3296 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3297 a different insn, set USAGE[REGNO] to const0_rtx. */
3299 static void
3302 rtx insn;
3303 rtx x;
3304 {
3316 {
3317 /* Don't count SET_DEST if it is a REG; otherwise count things
3318 in SET_DEST because if a register is partially modified, it won't
3319 show up as a potential movable so we don't care how USAGE is set
3320 for it. */
3324 }
3325 else
3327 {
3333 }
3334 }
3335 \f
3336 /* Count and record any set in X which is contained in INSN. Update
3337 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3338 in X. */
3340 static void
3345 {
3347 /* Don't move a reg that has an explicit clobber.
3348 It's not worth the pain to try to do it correctly. */
3352 {
3360 {
3362 /* If this is the first setting of this reg
3363 in current basic block, and it was set before,
3364 it must be set in two basic blocks, so it cannot
3365 be moved out of the loop. */
3369 /* If this is not first setting in current basic block,
3370 see if reg was used in between previous one and this.
3371 If so, neither one can be moved. */
3378 }
3379 }
3380 }
3381 \f
3382 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3383 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3384 contained in insn INSN is used by any insn that precedes INSN in
3385 cyclic order starting from the loop entry point.
3387 We don't want to use INSN_LUID here because if we restrict INSN to those
3388 that have a valid INSN_LUID, it means we cannot move an invariant out
3389 from an inner loop past two loops. */
3391 static int
3395 {
3397 rtx p;
3399 /* Scan forward checking for register usage. If we hit INSN, we
3400 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3402 {
3408 }
3411 }
3412 \f
3413 /* A "basic induction variable" or biv is a pseudo reg that is set
3414 (within this loop) only by incrementing or decrementing it. */
3415 /* A "general induction variable" or giv is a pseudo reg whose
3416 value is a linear function of a biv. */
3418 /* Bivs are recognized by `basic_induction_var';
3419 Givs by `general_induction_var'. */
3421 /* Communication with routines called via `note_stores'. */
3425 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3429 /* ??? Unfinished optimizations, and possible future optimizations,
3430 for the strength reduction code. */
3432 /* ??? The interaction of biv elimination, and recognition of 'constant'
3433 bivs, may cause problems. */
3435 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3436 performance problems.
3438 Perhaps don't eliminate things that can be combined with an addressing
3439 mode. Find all givs that have the same biv, mult_val, and add_val;
3440 then for each giv, check to see if its only use dies in a following
3441 memory address. If so, generate a new memory address and check to see
3442 if it is valid. If it is valid, then store the modified memory address,
3443 otherwise, mark the giv as not done so that it will get its own iv. */
3445 /* ??? Could try to optimize branches when it is known that a biv is always
3446 positive. */
3448 /* ??? When replace a biv in a compare insn, we should replace with closest
3449 giv so that an optimized branch can still be recognized by the combiner,
3450 e.g. the VAX acb insn. */
3452 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3453 was rerun in loop_optimize whenever a register was added or moved.
3454 Also, some of the optimizations could be a little less conservative. */
3455 \f
3456 /* Scan the loop body and call FNCALL for each insn. In the addition to the
3457 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
3458 callback.
3460 NOT_EVERY_ITERATION if current insn is not executed at least once for every
3461 loop iteration except for the last one.
3463 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
3464 loop iteration.
3465 */
3466 void
3469 loop_insn_callback fncall;
3470 {
3471 /* This is 1 if current insn is not executed at least once for every loop
3472 iteration. */
3477 rtx p;
3479 /* If loop_scan_start points to the loop exit test, we have to be wary of
3480 subversive use of gotos inside expression statements. */
3484 /* Scan through loop to find all possible bivs. */
3489 {
3492 /* Past CODE_LABEL, we get to insns that may be executed multiple
3493 times. The only way we can be sure that they can't is if every
3494 jump insn between here and the end of the loop either
3495 returns, exits the loop, is a jump to a location that is still
3496 behind the label, or is a jump to the loop start. */
3499 {
3505 {
3510 {
3513 else
3517 }
3525 {
3528 }
3529 }
3530 }
3532 /* Past a jump, we get to insns for which we can't count
3533 on whether they will be executed during each iteration. */
3534 /* This code appears twice in strength_reduce. There is also similar
3535 code in scan_loop. */
3537 /* If we enter the loop in the middle, and scan around to the
3538 beginning, don't set not_every_iteration for that.
3539 This can be any kind of jump, since we want to know if insns
3540 will be executed if the loop is executed. */
3545 {
3548 /* If this is a jump outside the loop, then it also doesn't
3549 matter. Check to see if the target of this branch is on the
3550 loop->exits_labels list. */
3558 }
3561 {
3562 /* At the virtual top of a converted loop, insns are again known to
3563 be executed each iteration: logically, the loop begins here
3564 even though the exit code has been duplicated.
3566 Insns are also again known to be executed each iteration at
3567 the LOOP_CONT note. */
3573 loop_depth++;
3575 loop_depth--;
3576 }
3578 /* Note if we pass a loop latch. If we do, then we can not clear
3579 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3580 a loop since a jump before the last CODE_LABEL may have started
3581 a new loop iteration.
3583 Note that LOOP_TOP is only set for rotated loops and we need
3584 this check for all loops, so compare against the CODE_LABEL
3585 which immediately follows LOOP_START. */
3590 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3591 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3592 or not an insn is known to be executed each iteration of the
3593 loop, whether or not any iterations are known to occur.
3595 Therefore, if we have just passed a label and have no more labels
3596 between here and the test insn of the loop, and we have not passed
3597 a jump to the top of the loop, then we know these insns will be
3598 executed each iteration. */
3601 && !past_loop_latch
3606 }
3607 }
3608 \f
3609 static void
3612 {
3615 /* Temporary list pointers for traversing ivs->list. */
3622 /* Scan ivs->list to remove all regs that proved not to be bivs.
3623 Make a sanity check against regs->n_times_set. */
3625 {
3627 /* Above happens if register modified by subreg, etc. */
3628 /* Make sure it is not recognized as a basic induction var: */
3630 /* If never incremented, it is invariant that we decided not to
3631 move. So leave it alone. */
3633 {
3644 }
3645 else
3646 {
3651 }
3652 }
3653 }
3656 /* Determine how BIVS are initialised by looking through pre-header
3657 extended basic block. */
3658 static void
3661 {
3663 /* Temporary list pointers for traversing ivs->list. */
3666 rtx p;
3668 /* Find initial value for each biv by searching backwards from loop_start,
3669 halting at first label. Also record any test condition. */
3673 {
3674 rtx test;
3684 /* Record any test of a biv that branches around the loop if no store
3685 between it and the start of loop. We only care about tests with
3686 constants and registers and only certain of those. */
3696 {
3697 /* If an NE test, we have an initial value! */
3699 {
3703 }
3704 else
3706 }
3707 }
3708 }
3711 /* Look at the each biv and see if we can say anything better about its
3712 initial value from any initializing insns set up above. (This is done
3713 in two passes to avoid missing SETs in a PARALLEL.) */
3714 static void
3717 {
3719 /* Temporary list pointers for traversing ivs->list. */
3724 {
3725 rtx src;
3726 rtx note;
3731 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
3732 is a constant, use the value of that. */
3738 else
3751 {
3755 {
3758 }
3759 }
3760 /* If we can't make it a giv,
3761 let biv keep initial value of "itself". */
3764 }
3765 }
3768 /* Search the loop for general induction variables. */
3770 static void
3773 {
3775 }
3778 /* For each giv for which we still don't know whether or not it is
3779 replaceable, check to see if it is replaceable because its final value
3780 can be calculated. */
3782 static void
3785 {
3790 {
3796 }
3797 }
3800 /* Return non-zero if it is possible to eliminate the biv BL provided
3801 all givs are reduced. This is possible if either the reg is not
3802 used outside the loop, or we can compute what its final value will
3803 be. */
3805 static int
3811 {
3812 /* For architectures with a decrement_and_branch_until_zero insn,
3813 don't do this if we put a REG_NONNEG note on the endtest for this
3814 biv. */
3816 #ifdef HAVE_decrement_and_branch_until_zero
3818 {
3823 }
3824 #endif
3826 /* Check that biv is used outside loop or if it has a final value.
3827 Compare against bl->init_insn rather than loop->start. We aren't
3828 concerned with any uses of the biv between init_insn and
3829 loop->start since these won't be affected by the value of the biv
3830 elsewhere in the function, so long as init_insn doesn't use the
3831 biv itself. */
3842 {
3850 }
3852 }
3855 /* Reduce each giv of BL that we have decided to reduce. */
3857 static void
3861 {
3865 {
3868 {
3871 /* If the code for derived givs immediately below has already
3872 allocated a new_reg, we must keep it. */
3876 #ifdef AUTO_INC_DEC
3877 /* If the target has auto-increment addressing modes, and
3878 this is an address giv, then try to put the increment
3879 immediately after its use, so that flow can create an
3880 auto-increment addressing mode. */
3883 /* We don't handle reversed biv's because bl->biv->insn
3884 does not have a valid INSN_LUID. */
3888 {
3889 /* If other giv's have been combined with this one, then
3890 this will work only if all uses of the other giv's occur
3891 before this giv's insn. This is difficult to check.
3893 We simplify this by looking for the common case where
3894 there is one DEST_REG giv, and this giv's insn is the
3895 last use of the dest_reg of that DEST_REG giv. If the
3896 increment occurs after the address giv, then we can
3897 perform the optimization. (Otherwise, the increment
3898 would have to go before other_giv, and we would not be
3899 able to combine it with the address giv to get an
3900 auto-inc address.) */
3902 {
3907 {
3910 else
3912 }
3919 }
3920 /* Check for case where increment is before the address
3921 giv. Do this test in "loop order". */
3930 else
3933 #ifdef HAVE_cc0
3934 {
3935 rtx prev;
3937 /* We can't put an insn immediately after one setting
3938 cc0, or immediately before one using cc0. */
3945 }
3946 #endif
3950 }
3951 #endif
3953 /* For each place where the biv is incremented, add an insn
3954 to increment the new, reduced reg for the giv. */
3956 {
3957 rtx insert_before;
3963 else
3971 /* A multiply is acceptable here
3972 since this is presumed to be seldom executed. */
3976 }
3978 /* Add code at loop start to initialize giv's reduced reg. */
3983 }
3984 }
3985 }
3988 /* Check for givs whose first use is their definition and whose
3989 last use is the definition of another giv. If so, it is likely
3990 dead and should not be used to derive another giv nor to
3991 eliminate a biv. */
3993 static void
3997 {
4001 {
4008 {
4014 }
4015 }
4016 }
4019 static void
4024 {
4028 {
4035 /* Update expression if this was combined, in case other giv was
4036 replaced. */
4041 /* See if this register is known to be a pointer to something. If
4042 so, see if we can find the alignment. First see if there is a
4043 destination register that is a pointer. If so, this shares the
4044 alignment too. Next see if we can deduce anything from the
4045 computational information. If not, and this is a DEST_ADDR
4046 giv, at least we know that it's a pointer, though we don't know
4047 the alignment. */
4055 {
4064 }
4068 {
4076 }
4081 /* Store reduced reg as the address in the memref where we found
4082 this giv. */
4085 {
4087 }
4088 else
4089 {
4090 /* Not replaceable; emit an insn to set the original giv reg from
4091 the reduced giv, same as above. */
4094 }
4096 /* When a loop is reversed, givs which depend on the reversed
4097 biv, and which are live outside the loop, must be set to their
4098 correct final value. This insn is only needed if the giv is
4099 not replaceable. The correct final value is the same as the
4100 value that the giv starts the reversed loop with. */
4110 {
4115 }
4116 }
4117 }
4120 static int
4125 rtx test_reg;
4126 {
4135 /* Reduce benefit if not replaceable, since we will insert a
4136 move-insn to replace the insn that calculates this giv. Don't do
4137 this unless the giv is a user variable, since it will often be
4138 marked non-replaceable because of the duplication of the exit
4139 code outside the loop. In such a case, the copies we insert are
4140 dead and will be deleted. So they don't have a cost. Similar
4141 situations exist. */
4142 /* ??? The new final_[bg]iv_value code does a much better job of
4143 finding replaceable giv's, and hence this code may no longer be
4144 necessary. */
4149 /* Decrease the benefit to count the add-insns that we will insert
4150 to increment the reduced reg for the giv. ??? This can
4151 overestimate the run-time cost of the additional insns, e.g. if
4152 there are multiple basic blocks that increment the biv, but only
4153 one of these blocks is executed during each iteration. There is
4154 no good way to detect cases like this with the current structure
4155 of the loop optimizer. This code is more accurate for
4156 determining code size than run-time benefits. */
4159 /* Decide whether to strength-reduce this giv or to leave the code
4160 unchanged (recompute it from the biv each time it is used). This
4161 decision can be made independently for each giv. */
4163 #ifdef AUTO_INC_DEC
4164 /* Attempt to guess whether autoincrement will handle some of the
4165 new add insns; if so, increase BENEFIT (undo the subtraction of
4166 add_cost that was done above). */
4168 /* Increasing the benefit is risky, since this is only a guess.
4169 Avoid increasing register pressure in cases where there would
4170 be no other benefit from reducing this giv. */
4173 {
4188 }
4189 #endif
4192 }
4195 /* Free IV structures for LOOP. */
4197 static void
4200 {
4207 {
4213 {
4216 }
4218 {
4221 }
4225 }
4226 }
4229 /* Perform strength reduction and induction variable elimination.
4231 Pseudo registers created during this function will be beyond the
4232 last valid index in several tables including
4233 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
4234 problem here, because the added registers cannot be givs outside of
4235 their loop, and hence will never be reconsidered. But scan_loop
4236 must check regnos to make sure they are in bounds. */
4238 static void
4242 {
4246 rtx p;
4247 /* Temporary list pointer for traversing ivs->list. */
4249 /* Ratio of extra register life span we can justify
4250 for saving an instruction. More if loop doesn't call subroutines
4251 since in that case saving an insn makes more difference
4252 and more registers are available. */
4253 /* ??? could set this to last value of threshold in move_movables */
4255 /* Map of pseudo-register replacements. */
4267 /* Find all BIVs in loop. */
4270 /* Exit if there are no bivs. */
4272 {
4273 /* Can still unroll the loop anyways, but indicate that there is no
4274 strength reduction info available. */
4280 }
4282 /* Determine how BIVS are initialised by looking through pre-header
4283 extended basic block. */
4286 /* Look at the each biv and see if we can say anything better about its
4287 initial value from any initializing insns set up above. */
4290 /* Search the loop for general induction variables. */
4293 /* Try to calculate and save the number of loop iterations. This is
4294 set to zero if the actual number can not be calculated. This must
4295 be called after all giv's have been identified, since otherwise it may
4296 fail if the iteration variable is a giv. */
4299 /* Now for each giv for which we still don't know whether or not it is
4300 replaceable, check to see if it is replaceable because its final value
4301 can be calculated. This must be done after loop_iterations is called,
4302 so that final_giv_value will work correctly. */
4305 /* Try to prove that the loop counter variable (if any) is always
4306 nonnegative; if so, record that fact with a REG_NONNEG note
4307 so that "decrement and branch until zero" insn can be used. */
4310 /* Create reg_map to hold substitutions for replaceable giv regs.
4311 Some givs might have been made from biv increments, so look at
4312 ivs->reg_iv_type for a suitable size. */
4316 /* Examine each iv class for feasibility of strength reduction/induction
4317 variable elimination. */
4320 {
4324 /* Test whether it will be possible to eliminate this biv
4325 provided all givs are reduced. */
4328 /* This will be true at the end, if all givs which depend on this
4329 biv have been strength reduced.
4330 We can't (currently) eliminate the biv unless this is so. */
4333 /* Check each extension dependent giv in this class to see if its
4334 root biv is safe from wrapping in the interior mode. */
4337 /* Combine all giv's for this iv_class. */
4341 {
4349 /* If an insn is not to be strength reduced, then set its ignore
4350 flag, and clear bl->all_reduced. */
4352 /* A giv that depends on a reversed biv must be reduced if it is
4353 used after the loop exit, otherwise, it would have the wrong
4354 value after the loop exit. To make it simple, just reduce all
4355 of such giv's whether or not we know they are used after the loop
4356 exit. */
4361 {
4369 }
4370 else
4371 {
4372 /* Check that we can increment the reduced giv without a
4373 multiply insn. If not, reject it. */
4378 {
4386 }
4387 }
4388 }
4390 /* Check for givs whose first use is their definition and whose
4391 last use is the definition of another giv. If so, it is likely
4392 dead and should not be used to derive another giv nor to
4393 eliminate a biv. */
4396 /* Reduce each giv that we decided to reduce. */
4399 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
4400 as not reduced.
4402 For each giv register that can be reduced now: if replaceable,
4403 substitute reduced reg wherever the old giv occurs;
4404 else add new move insn "giv_reg = reduced_reg". */
4407 /* All the givs based on the biv bl have been reduced if they
4408 merit it. */
4410 /* For each giv not marked as maybe dead that has been combined with a
4411 second giv, clear any "maybe dead" mark on that second giv.
4412 v->new_reg will either be or refer to the register of the giv it
4413 combined with.
4415 Doing this clearing avoids problems in biv elimination where
4416 a giv's new_reg is a complex value that can't be put in the
4417 insn but the giv combined with (with a reg as new_reg) is
4418 marked maybe_dead. Since the register will be used in either
4419 case, we'd prefer it be used from the simpler giv. */
4425 /* Try to eliminate the biv, if it is a candidate.
4426 This won't work if ! bl->all_reduced,
4427 since the givs we planned to use might not have been reduced.
4429 We have to be careful that we didn't initially think we could
4430 eliminate this biv because of a giv that we now think may be
4431 dead and shouldn't be used as a biv replacement.
4433 Also, there is the possibility that we may have a giv that looks
4434 like it can be used to eliminate a biv, but the resulting insn
4435 isn't valid. This can happen, for example, on the 88k, where a
4436 JUMP_INSN can compare a register only with zero. Attempts to
4437 replace it with a compare with a constant will fail.
4439 Note that in cases where this call fails, we may have replaced some
4440 of the occurrences of the biv with a giv, but no harm was done in
4441 doing so in the rare cases where it can occur. */
4445 {
4446 /* ?? If we created a new test to bypass the loop entirely,
4447 or otherwise drop straight in, based on this test, then
4448 we might want to rewrite it also. This way some later
4449 pass has more hope of removing the initialization of this
4450 biv entirely. */
4452 /* If final_value != 0, then the biv may be used after loop end
4453 and we must emit an insn to set it just in case.
4455 Reversed bivs already have an insn after the loop setting their
4456 value, so we don't need another one. We can't calculate the
4457 proper final value for such a biv here anyways. */
4465 }
4466 }
4468 /* Go through all the instructions in the loop, making all the
4469 register substitutions scheduled in REG_MAP. */
4474 {
4478 }
4481 {
4482 /* When we completely unroll a loop we will likely not need the increment
4483 of the loop BIV and we will not need the conditional branch at the
4484 end of the loop. */
4487 #ifdef HAVE_cc0
4488 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
4489 need the comparison before the conditional branch at the end of the
4490 loop. */
4492 #endif
4494 /* We'll need one copy for each loop iteration. */
4497 /* A little slop to account for the ability to remove initialization
4498 code, better CSE, and other secondary benefits of completely
4499 unrolling some loops. */
4502 /* Clamp the value. */
4505 }
4507 /* Unroll loops from within strength reduction so that we can use the
4508 induction variable information that strength_reduce has already
4509 collected. Always unroll loops that would be as small or smaller
4510 unrolled than when rolled. */
4516 #ifdef HAVE_doloop_end
4521 /* In case number of iterations is known, drop branch prediction note
4522 in the branch. Do that only in second loop pass, as loop unrolling
4523 may change the number of iterations performed. */
4526 {
4529 PRED_LOOP_ITERATIONS,
4531 }
4539 }
4540 \f
4541 /*Record all basic induction variables calculated in the insn. */
4542 static rtx
4545 rtx p;
4548 {
4550 rtx set;
4551 rtx dest_reg;
4552 rtx inc_val;
4553 rtx mult_val;
4559 {
4564 {
4569 {
4570 /* It is a possible basic induction variable.
4571 Create and initialize an induction structure for it. */
4579 }
4582 }
4583 }
4585 }
4586 \f
4587 /* Record all givs calculated in the insn.
4588 A register is a giv if: it is only set once, it is a function of a
4589 biv and a constant (or invariant), and it is not a biv. */
4590 static rtx
4593 rtx p;
4596 {
4599 rtx set;
4600 /* Look for a general induction variable in a register. */
4605 {
4606 rtx src_reg;
4607 rtx dest_reg;
4608 rtx add_val;
4609 rtx mult_val;
4610 rtx ext_val;
4613 rtx last_consec_insn;
4622 /* Equivalent expression is a giv. */
4627 /* Don't try to handle any regs made by loop optimization.
4628 We have nothing on them in regno_first_uid, etc. */
4630 /* Don't recognize a BASIC_INDUCT_VAR here. */
4632 /* This must be the only place where the register is set. */
4634 /* or all sets must be consecutive and make a giv. */
4639 {
4643 /* If this is a library call, increase benefit. */
4647 /* Skip the consecutive insns, if there are any. */
4655 }
4656 }
4658 #ifndef DONT_REDUCE_ADDR
4659 /* Look for givs which are memory addresses. */
4660 /* This resulted in worse code on a VAX 8600. I wonder if it
4661 still does. */
4664 maybe_multiple);
4665 #endif
4667 /* Update the status of whether giv can derive other givs. This can
4668 change when we pass a label or an insn that updates a biv. */
4673 }
4674 \f
4675 /* Return 1 if X is a valid source for an initial value (or as value being
4676 compared against in an initial test).
4678 X must be either a register or constant and must not be clobbered between
4679 the current insn and the start of the loop.
4681 INSN is the insn containing X. */
4683 static int
4685 rtx x;
4686 rtx insn;
4688 rtx loop_start;
4689 {
4693 /* Only consider pseudos we know about initialized in insns whose luids
4694 we know. */
4699 /* Don't use call-clobbered registers across a call which clobbers it. On
4700 some machines, don't use any hard registers at all. */
4702 && (SMALL_REGISTER_CLASSES
4706 /* Don't use registers that have been clobbered before the start of the
4707 loop. */
4712 }
4713 \f
4714 /* Scan X for memory refs and check each memory address
4715 as a possible giv. INSN is the insn whose pattern X comes from.
4716 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
4717 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
4718 more thanonce in each loop iteration. */
4720 static void
4723 rtx x;
4724 rtx insn;
4726 {
4736 {
4752 {
4753 rtx src_reg;
4754 rtx add_val;
4755 rtx mult_val;
4756 rtx ext_val;
4759 /* This code used to disable creating GIVs with mult_val == 1 and
4760 add_val == 0. However, this leads to lost optimizations when
4761 it comes time to combine a set of related DEST_ADDR GIVs, since
4762 this one would not be seen. */
4767 {
4768 /* Found one; record it. */
4777 }
4778 }
4783 }
4785 /* Recursively scan the subexpressions for other mem refs. */
4791 maybe_multiple);
4795 maybe_multiple);
4796 }
4797 \f
4798 /* Fill in the data about one biv update.
4799 V is the `struct induction' in which we record the biv. (It is
4800 allocated by the caller, with alloca.)
4801 INSN is the insn that sets it.
4802 DEST_REG is the biv's reg.
4804 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
4805 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
4806 being set to INC_VAL.
4808 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
4809 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
4810 can be executed more than once per iteration. If MAYBE_MULTIPLE
4811 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
4812 executed exactly once per iteration. */
4814 static void
4819 rtx insn;
4820 rtx dest_reg;
4821 rtx inc_val;
4822 rtx mult_val;
4826 {
4842 /* Add this to the reg's iv_class, creating a class
4843 if this is the first incrementation of the reg. */
4847 {
4848 /* Create and initialize new iv_class. */
4858 /* Set initial value to the reg itself. */
4861 /* We haven't seen the initializing insn yet */
4871 /* Add this class to ivs->list. */
4875 /* Put it in the array of biv register classes. */
4877 }
4879 /* Update IV_CLASS entry for this biv. */
4888 }
4889 \f
4890 /* Fill in the data about one giv.
4891 V is the `struct induction' in which we record the giv. (It is
4892 allocated by the caller, with alloca.)
4893 INSN is the insn that sets it.
4894 BENEFIT estimates the savings from deleting this insn.
4895 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
4896 into a register or is used as a memory address.
4898 SRC_REG is the biv reg which the giv is computed from.
4899 DEST_REG is the giv's reg (if the giv is stored in a reg).
4900 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
4901 LOCATION points to the place where this giv's value appears in INSN. */
4903 static void
4908 rtx insn;
4909 rtx src_reg;
4910 rtx dest_reg;
4916 {
4921 rtx temp;
4923 /* Attempt to prove constantness of the values. Don't let simplity_rtx
4924 undo the MULT canonicalization that we performed earlier. */
4954 /* The v->always_computable field is used in update_giv_derive, to
4955 determine whether a giv can be used to derive another giv. For a
4956 DEST_REG giv, INSN computes a new value for the giv, so its value
4957 isn't computable if INSN insn't executed every iteration.
4958 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
4959 it does not compute a new value. Hence the value is always computable
4960 regardless of whether INSN is executed each iteration. */
4964 else
4970 {
4973 }
4975 {
4980 /* If the lifetime is zero, it means that this register is
4981 really a dead store. So mark this as a giv that can be
4982 ignored. This will not prevent the biv from being eliminated. */
4988 }
4990 /* Add the giv to the class of givs computed from one biv. */
4994 {
4997 /* Don't count DEST_ADDR. This is supposed to count the number of
4998 insns that calculate givs. */
5002 }
5003 else
5004 /* Fatal error, biv missing for this giv? */
5009 else
5010 {
5011 /* The giv can be replaced outright by the reduced register only if all
5012 of the following conditions are true:
5013 - the insn that sets the giv is always executed on any iteration
5014 on which the giv is used at all
5015 (there are two ways to deduce this:
5016 either the insn is executed on every iteration,
5017 or all uses follow that insn in the same basic block),
5018 - the giv is not used outside the loop
5019 - no assignments to the biv occur during the giv's lifetime. */
5022 /* Previous line always fails if INSN was moved by loop opt. */
5025 && (! not_every_iteration
5027 {
5028 /* Now check that there are no assignments to the biv within the
5029 giv's lifetime. This requires two separate checks. */
5031 /* Check each biv update, and fail if any are between the first
5032 and last use of the giv.
5034 If this loop contains an inner loop that was unrolled, then
5035 the insn modifying the biv may have been emitted by the loop
5036 unrolling code, and hence does not have a valid luid. Just
5037 mark the biv as not replaceable in this case. It is not very
5038 useful as a biv, because it is used in two different loops.
5039 It is very unlikely that we would be able to optimize the giv
5040 using this biv anyways. */
5044 {
5050 {
5054 }
5055 }
5057 /* If there are any backwards branches that go from after the
5058 biv update to before it, then this giv is not replaceable. */
5062 {
5066 }
5067 }
5068 else
5069 {
5070 /* May still be replaceable, we don't have enough info here to
5071 decide. */
5074 }
5075 }
5077 /* Record whether the add_val contains a const_int, for later use by
5078 combine_givs. */
5079 {
5084 ;
5088 {
5090 {
5095 else
5097 }
5100 }
5101 }
5105 }
5107 /* All this does is determine whether a giv can be made replaceable because
5108 its final value can be calculated. This code can not be part of record_giv
5109 above, because final_giv_value requires that the number of loop iterations
5110 be known, and that can not be accurately calculated until after all givs
5111 have been identified. */
5113 static void
5117 {
5124 /* DEST_ADDR givs will never reach here, because they are always marked
5125 replaceable above in record_giv. */
5127 /* The giv can be replaced outright by the reduced register only if all
5128 of the following conditions are true:
5129 - the insn that sets the giv is always executed on any iteration
5130 on which the giv is used at all
5131 (there are two ways to deduce this:
5132 either the insn is executed on every iteration,
5133 or all uses follow that insn in the same basic block),
5134 - its final value can be calculated (this condition is different
5135 than the one above in record_giv)
5136 - it's not used before the it's set
5137 - no assignments to the biv occur during the giv's lifetime. */
5139 #if 0
5140 /* This is only called now when replaceable is known to be false. */
5141 /* Clear replaceable, so that it won't confuse final_giv_value. */
5143 #endif
5147 {
5150 rtx last_giv_use;
5154 /* When trying to determine whether or not a biv increment occurs
5155 during the lifetime of the giv, we can ignore uses of the variable
5156 outside the loop because final_value is true. Hence we can not
5157 use regno_last_uid and regno_first_uid as above in record_giv. */
5159 /* Search the loop to determine whether any assignments to the
5160 biv occur during the giv's lifetime. Start with the insn
5161 that sets the giv, and search around the loop until we come
5162 back to that insn again.
5164 Also fail if there is a jump within the giv's lifetime that jumps
5165 to somewhere outside the lifetime but still within the loop. This
5166 catches spaghetti code where the execution order is not linear, and
5167 hence the above test fails. Here we assume that the giv lifetime
5168 does not extend from one iteration of the loop to the next, so as
5169 to make the test easier. Since the lifetime isn't known yet,
5170 this requires two loops. See also record_giv above. */
5175 {
5178 {
5181 }
5187 {
5188 /* It is possible for the BIV increment to use the GIV if we
5189 have a cycle. Thus we must be sure to check each insn for
5190 both BIV and GIV uses, and we must check for BIV uses
5191 first. */
5198 {
5200 {
5204 }
5206 }
5207 }
5208 }
5210 /* Now that the lifetime of the giv is known, check for branches
5211 from within the lifetime to outside the lifetime if it is still
5212 replaceable. */
5215 {
5218 {
5231 {
5240 }
5241 }
5242 }
5244 /* If it is replaceable, then save the final value. */
5247 }
5252 }
5253 \f
5254 /* Update the status of whether a giv can derive other givs.
5256 We need to do something special if there is or may be an update to the biv
5257 between the time the giv is defined and the time it is used to derive
5258 another giv.
5260 In addition, a giv that is only conditionally set is not allowed to
5261 derive another giv once a label has been passed.
5263 The cases we look at are when a label or an update to a biv is passed. */
5265 static void
5268 rtx p;
5269 {
5273 rtx tem;
5276 /* Search all IV classes, then all bivs, and finally all givs.
5278 There are three cases we are concerned with. First we have the situation
5279 of a giv that is only updated conditionally. In that case, it may not
5280 derive any givs after a label is passed.
5282 The second case is when a biv update occurs, or may occur, after the
5283 definition of a giv. For certain biv updates (see below) that are
5284 known to occur between the giv definition and use, we can adjust the
5285 giv definition. For others, or when the biv update is conditional,
5286 we must prevent the giv from deriving any other givs. There are two
5287 sub-cases within this case.
5289 If this is a label, we are concerned with any biv update that is done
5290 conditionally, since it may be done after the giv is defined followed by
5291 a branch here (actually, we need to pass both a jump and a label, but
5292 this extra tracking doesn't seem worth it).
5294 If this is a jump, we are concerned about any biv update that may be
5295 executed multiple times. We are actually only concerned about
5296 backward jumps, but it is probably not worth performing the test
5297 on the jump again here.
5299 If this is a biv update, we must adjust the giv status to show that a
5300 subsequent biv update was performed. If this adjustment cannot be done,
5301 the giv cannot derive further givs. */
5307 {
5309 {
5310 /* If cant_derive is already true, there is no point in
5311 checking all of these conditions again. */
5315 /* If this giv is conditionally set and we have passed a label,
5316 it cannot derive anything. */
5320 /* Skip givs that have mult_val == 0, since
5321 they are really invariants. Also skip those that are
5322 replaceable, since we know their lifetime doesn't contain
5323 any biv update. */
5327 /* The only way we can allow this giv to derive another
5328 is if this is a biv increment and we can form the product
5329 of biv->add_val and giv->mult_val. In this case, we will
5330 be able to compute a compensation. */
5332 {
5333 rtx ext_val_dummy;
5344 tem = simplify_giv_expr
5351 else
5353 }
5357 }
5358 }
5359 }
5360 \f
5361 /* Check whether an insn is an increment legitimate for a basic induction var.
5362 X is the source of insn P, or a part of it.
5363 MODE is the mode in which X should be interpreted.
5365 DEST_REG is the putative biv, also the destination of the insn.
5366 We accept patterns of these forms:
5367 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
5368 REG = INVARIANT + REG
5370 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
5371 store the additive term into *INC_VAL, and store the place where
5372 we found the additive term into *LOCATION.
5374 If X is an assignment of an invariant into DEST_REG, we set
5375 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
5377 We also want to detect a BIV when it corresponds to a variable
5378 whose mode was promoted via PROMOTED_MODE. In that case, an increment
5379 of the variable may be a PLUS that adds a SUBREG of that variable to
5380 an invariant and then sign- or zero-extends the result of the PLUS
5381 into the variable.
5383 Most GIVs in such cases will be in the promoted mode, since that is the
5384 probably the natural computation mode (and almost certainly the mode
5385 used for addresses) on the machine. So we view the pseudo-reg containing
5386 the variable as the BIV, as if it were simply incremented.
5388 Note that treating the entire pseudo as a BIV will result in making
5389 simple increments to any GIVs based on it. However, if the variable
5390 overflows in its declared mode but not its promoted mode, the result will
5391 be incorrect. This is acceptable if the variable is signed, since
5392 overflows in such cases are undefined, but not if it is unsigned, since
5393 those overflows are defined. So we only check for SIGN_EXTEND and
5394 not ZERO_EXTEND.
5396 If we cannot find a biv, we return 0. */
5398 static int
5401 rtx x;
5403 rtx dest_reg;
5404 rtx p;
5408 {
5416 {
5422 {
5424 }
5429 {
5431 }
5432 else
5445 /* If this is a SUBREG for a promoted variable, check the inner
5446 value. */
5454 /* If this register is assigned in a previous insn, look at its
5455 source, but don't go outside the loop or past a label. */
5457 /* If this sets a register to itself, we would repeat any previous
5458 biv increment if we applied this strategy blindly. */
5464 {
5465 rtx dest;
5466 do
5467 {
5469 }
5498 }
5499 /* Fall through. */
5501 /* Can accept constant setting of biv only when inside inner most loop.
5502 Otherwise, a biv of an inner loop may be incorrectly recognized
5503 as a biv of the outer loop,
5504 causing code to be moved INTO the inner loop. */
5511 /* convert_modes aborts if we try to convert to or from CCmode, so just
5512 exclude that case. It is very unlikely that a condition code value
5513 would be a useful iterator anyways. */
5517 {
5518 /* Possible bug here? Perhaps we don't know the mode of X. */
5522 }
5523 else
5531 /* Similar, since this can be a sign extension. */
5536 ;
5550 location);
5555 }
5556 }
5557 \f
5558 /* A general induction variable (giv) is any quantity that is a linear
5559 function of a basic induction variable,
5560 i.e. giv = biv * mult_val + add_val.
5561 The coefficients can be any loop invariant quantity.
5562 A giv need not be computed directly from the biv;
5563 it can be computed by way of other givs. */
5565 /* Determine whether X computes a giv.
5566 If it does, return a nonzero value
5567 which is the benefit from eliminating the computation of X;
5568 set *SRC_REG to the register of the biv that it is computed from;
5569 set *ADD_VAL and *MULT_VAL to the coefficients,
5570 such that the value of X is biv * mult + add; */
5572 static int
5576 rtx x;
5584 {
5588 /* If this is an invariant, forget it, it isn't a giv. */
5599 {
5602 /* Since this is now an invariant and wasn't before, it must be a giv
5603 with MULT_VAL == 0. It doesn't matter which BIV we associate this
5604 with. */
5611 /* This is equivalent to a BIV. */
5618 /* Either (plus (biv) (invar)) or
5619 (plus (mult (biv) (invar_1)) (invar_2)). */
5621 {
5624 }
5625 else
5626 {
5629 }
5634 /* ADD_VAL is zero. */
5642 }
5644 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
5645 unless they are CONST_INT). */
5653 else
5656 /* Always return true if this is a giv so it will be detected as such,
5657 even if the benefit is zero or negative. This allows elimination
5658 of bivs that might otherwise not be eliminated. */
5660 }
5661 \f
5662 /* Given an expression, X, try to form it as a linear function of a biv.
5663 We will canonicalize it to be of the form
5664 (plus (mult (BIV) (invar_1))
5665 (invar_2))
5666 with possible degeneracies.
5668 The invariant expressions must each be of a form that can be used as a
5669 machine operand. We surround then with a USE rtx (a hack, but localized
5670 and certainly unambiguous!) if not a CONST_INT for simplicity in this
5671 routine; it is the caller's responsibility to strip them.
5673 If no such canonicalization is possible (i.e., two biv's are used or an
5674 expression that is neither invariant nor a biv or giv), this routine
5675 returns 0.
5677 For a non-zero return, the result will have a code of CONST_INT, USE,
5678 REG (for a BIV), PLUS, or MULT. No other codes will occur.
5680 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
5685 static rtx
5688 rtx x;
5691 {
5696 rtx tem;
5698 /* If this is not an integer mode, or if we cannot do arithmetic in this
5699 mode, this can't be a giv. */
5706 {
5713 /* Put constant last, CONST_INT last if both constant. */
5721 /* Handle addition of zero, then addition of an invariant. */
5726 {
5729 /* Adding two invariants must result in an invariant, so enclose
5730 addition operation inside a USE and return it. */
5740 else
5749 /* biv + invar or mult + invar. Return sum. */
5753 /* (a + invar_1) + invar_2. Associate. */
5754 return
5760 arg1)),
5765 }
5767 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
5768 MULT to reduce cases. */
5774 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
5775 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
5776 Recurse to associate the second PLUS. */
5781 return
5789 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
5805 /* Handle "a - b" as "a + b * (-1)". */
5811 constm1_rtx)),
5820 /* Put constant last, CONST_INT last if both constant. */
5825 /* If second argument is not now constant, not giv. */
5829 /* Handle multiply by 0 or 1. */
5837 {
5839 /* biv * invar. Done. */
5843 /* Product of two constants. */
5847 /* invar * invar is a giv, but attempt to simplify it somehow. */
5853 {
5854 /* (invar_0 * invar_1) * invar_2. Associate. */
5861 arg1)),
5863 }
5864 /* Porpagate the MULT expressions to the intermost nodes. */
5866 {
5867 /* (invar_0 + invar_1) * invar_2. Distribute. */
5873 arg1),
5877 arg1)),
5879 }
5883 /* (a * invar_1) * invar_2. Associate. */
5889 arg1)),
5893 /* (a + invar_1) * invar_2. Distribute. */
5898 arg1),
5901 arg1)),
5906 }
5909 /* Shift by constant is multiply by power of two. */
5913 return
5922 /* "-a" is "a * (-1)" */
5928 /* "~a" is "-a - 1". Silly, but easy. */
5932 const1_rtx),
5936 /* Already in proper form for invariant. */
5942 /* Conditionally recognize extensions of simple IVs. After we've
5943 computed loop traversal counts and verified the range of the
5944 source IV, we'll reevaluate this as a GIV. */
5946 {
5949 {
5952 }
5953 }
5957 /* If this is a new register, we can't deal with it. */
5961 /* Check for biv or giv. */
5963 {
5967 {
5970 /* Form expression from giv and add benefit. Ensure this giv
5971 can derive another and subtract any needed adjustment if so. */
5973 /* Increasing the benefit here is risky. The only case in which it
5974 is arguably correct is if this is the only use of V. In other
5975 cases, this will artificially inflate the benefit of the current
5976 giv, and lead to suboptimal code. Thus, it is disabled, since
5977 potentially not reducing an only marginally beneficial giv is
5978 less harmful than reducing many givs that are not really
5979 beneficial. */
5980 {
5984 }
5997 {
6000 }
6001 else
6002 {
6005 }
6007 }
6010 do_default:
6011 /* If it isn't an induction variable, and it is invariant, we
6012 may be able to simplify things further by looking through
6013 the bits we just moved outside the loop. */
6015 {
6021 {
6022 /* Ok, we found a match. Substitute and simplify. */
6024 /* If we match another movable, we must use that, as
6025 this one is going away. */
6030 /* If consec is non-zero, this is a member of a group of
6031 instructions that were moved together. We handle this
6032 case only to the point of seeking to the last insn and
6033 looking for a REG_EQUAL. Fail if we don't find one. */
6035 {
6038 do
6039 {
6041 }
6047 }
6048 else
6049 {
6053 }
6056 {
6057 /* What we are most interested in is pointer
6058 arithmetic on invariants -- only take
6059 patterns we may be able to do something with. */
6065 {
6067 benefit);
6070 }
6075 {
6080 }
6081 }
6083 }
6084 }
6086 }
6088 /* Fall through to general case. */
6090 /* If invariant, return as USE (unless CONST_INT).
6091 Otherwise, not giv. */
6096 {
6105 }
6106 else
6108 }
6109 }
6111 /* This routine folds invariants such that there is only ever one
6112 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6114 static rtx
6117 {
6123 {
6126 }
6129 {
6132 }
6133 else
6134 {
6137 }
6138 }
6140 static rtx
6144 {
6146 {
6150 else
6153 }
6156 else
6159 }
6160 \f
6161 /* Help detect a giv that is calculated by several consecutive insns;
6162 for example,
6163 giv = biv * M
6164 giv = giv + A
6165 The caller has already identified the first insn P as having a giv as dest;
6166 we check that all other insns that set the same register follow
6167 immediately after P, that they alter nothing else,
6168 and that the result of the last is still a giv.
6170 The value is 0 if the reg set in P is not really a giv.
6171 Otherwise, the value is the amount gained by eliminating
6172 all the consecutive insns that compute the value.
6174 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6175 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6177 The coefficients of the ultimate giv value are stored in
6178 *MULT_VAL and *ADD_VAL. */
6180 static int
6185 rtx p;
6186 rtx src_reg;
6187 rtx dest_reg;
6192 {
6198 rtx temp;
6199 rtx set;
6201 /* Indicate that this is a giv so that we can update the value produced in
6202 each insn of the multi-insn sequence.
6204 This induction structure will be used only by the call to
6205 general_induction_var below, so we can allocate it on our stack.
6206 If this is a giv, our caller will replace the induct var entry with
6207 a new induction structure. */
6228 {
6232 /* If libcall, skip to end of call sequence. */
6243 /* Giv created by equivalent expression. */
6249 {
6253 count--;
6257 }
6259 {
6260 /* Allow insns that set something other than this giv to a
6261 constant. Such insns are needed on machines which cannot
6262 include long constants and should not disqualify a giv. */
6271 }
6272 }
6277 }
6278 \f
6279 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6280 represented by G1. If no such expression can be found, or it is clear that
6281 it cannot possibly be a valid address, 0 is returned.
6283 To perform the computation, we note that
6284 G1 = x * v + a and
6285 G2 = y * v + b
6286 where `v' is the biv.
6288 So G2 = (y/b) * G1 + (b - a*y/x).
6290 Note that MULT = y/x.
6292 Update: A and B are now allowed to be additive expressions such that
6293 B contains all variables in A. That is, computing B-A will not require
6294 subtracting variables. */
6296 static rtx
6299 {
6300 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6305 /* If MULT is not 1, we cannot handle A with non-constants, since we
6306 would then be required to subtract multiples of the registers in A.
6307 This is theoretically possible, and may even apply to some Fortran
6308 constructs, but it is a lot of work and we do not attempt it here. */
6313 /* In general these structures are sorted top to bottom (down the PLUS
6314 chain), but not left to right across the PLUS. If B is a higher
6315 order giv than A, we can strip one level and recurse. If A is higher
6316 order, we'll eventually bail out, but won't know that until the end.
6317 If they are the same, we'll strip one level around this loop. */
6320 {
6332 /* We matched: remove one reg completely. */
6335 /* An alternate match. */
6338 /* An alternate match. */
6340 else
6341 {
6342 /* Indicates an extra register in B. Strip one level from B and
6343 recurse, hoping B was the higher order expression. */
6348 }
6349 }
6351 /* Here we are at the last level of A, go through the cases hoping to
6352 get rid of everything but a constant. */
6355 {
6368 }
6370 {
6372 }
6374 {
6379 }
6381 {
6386 else
6388 }
6393 }
6395 rtx
6398 {
6401 /* The value that G1 will be multiplied by must be a constant integer. Also,
6402 the only chance we have of getting a valid address is if b*c/a (see above
6403 for notation) is also an integer. */
6406 {
6411 }
6414 else
6415 {
6416 /* ??? Find out if the one is a multiple of the other? */
6418 }
6422 {
6423 /* Failed. If we've got a multiplication factor between G1 and G2,
6424 scale G1's addend and try again. */
6426 {
6430 {
6431 HOST_WIDE_INT m;
6435 }
6436 else
6437 {
6439 mult);
6440 }
6443 }
6444 }
6448 /* Form simplified final result. */
6453 else
6458 else
6459 {
6462 {
6466 }
6469 }
6470 }
6471 \f
6472 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6473 represented by G1. This indicates that G2 should be combined with G1 and
6474 that G2 can use (either directly or via an address expression) a register
6475 used to represent G1. */
6477 static rtx
6480 {
6483 /* With the introduction of ext dependant givs, we must care for modes.
6484 G2 must not use a wider mode than G1. */
6494 /* If these givs are identical, they can be combined. We use the results
6495 of express_from because the addends are not in a canonical form, so
6496 rtx_equal_p is a weaker test. */
6497 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
6498 combination to be the other way round. */
6501 {
6503 }
6505 /* If G2 can be expressed as a function of G1 and that function is valid
6506 as an address and no more expensive than using a register for G2,
6507 the expression of G2 in terms of G1 can be used. */
6511 /* ??? Looses, especially with -fforce-addr, where *g2->location
6512 will always be a register, and so anything more complicated
6513 gets discarded. */
6514 #if 0
6515 #ifdef ADDRESS_COST
6517 #else
6519 #endif
6520 #endif
6521 )
6522 {
6524 }
6527 }
6528 \f
6529 /* Check each extension dependant giv in this class to see if its
6530 root biv is safe from wrapping in the interior mode, which would
6531 make the giv illegal. */
6533 static void
6537 {
6540 HOST_WIDE_INT start_val;
6546 /* Make sure the iteration data is available. We must have
6547 constants in order to be certain of no overflow. */
6548 /* ??? An unknown iteration count with an increment of +-1
6549 combined with friendly exit tests of against an invariant
6550 value is also ameanable to optimization. Not implemented. */
6556 /* Make sure the host can represent the arithmetic. */
6558 {
6560 HOST_WIDE_INT s_end_val;
6572 /* Check for host arithmatic overflow. */
6574 {
6576 HOST_WIDE_INT s_max;
6583 /* Check zero extension of biv ok. */
6585 /* Check for host arithmatic overflow. */
6586 && (neg_incr
6589 /* Check for target arithmetic overflow. */
6590 && (neg_incr
6593 {
6595 }
6597 /* Check sign extension of biv ok. */
6598 /* ??? While it is true that overflow with signed and pointer
6599 arithmetic is undefined, I fear too many programmers don't
6600 keep this fact in mind -- myself included on occasion.
6601 So leave alone with the signed overflow optimizations. */
6603 /* Check for host arithmatic overflow. */
6604 && (neg_incr
6607 /* Check for target arithmetic overflow. */
6608 && (neg_incr
6611 {
6613 }
6614 }
6615 }
6617 /* Invalidate givs that fail the tests. */
6620 {
6625 {
6634 /* We don't know whether this value is being used as either
6635 signed or unsigned, so to safely truncate we must satisfy
6636 both. The initial check here verifies the BIV itself;
6637 once that is successful we may check its range wrt the
6638 derived GIV. */
6640 {
6644 /* We know from the above that both endpoints are nonnegative,
6645 and that there is no wrapping. Verify that both endpoints
6646 are within the (signed) range of the outer mode. */
6649 }
6654 }
6657 {
6659 {
6663 }
6664 }
6665 else
6666 {
6668 {
6673 else
6674 {
6679 else
6681 }
6686 }
6689 }
6690 }
6691 }
6693 /* Generate a version of VALUE in a mode appropriate for initializing V. */
6695 rtx
6698 rtx value;
6699 {
6705 /* Recall that check_ext_dependant_givs verified that the known bounds
6706 of a biv did not overflow or wrap with respect to the extension for
6707 the giv. Therefore, constants need no additional adjustment. */
6711 /* Otherwise, we must adjust the value to compensate for the
6712 differing modes of the biv and the giv. */
6714 }
6715 \f
6716 struct combine_givs_stats
6717 {
6720 };
6722 static int
6726 {
6733 /* Stabilize the sort. */
6737 }
6739 /* Check all pairs of givs for iv_class BL and see if any can be combined with
6740 any other. If so, point SAME to the giv combined with and set NEW_REG to
6741 be an expression (in terms of the other giv's DEST_REG) equivalent to the
6742 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
6744 static void
6748 {
6749 /* Additional benefit to add for being combined multiple times. */
6757 /* Count givs, because bl->giv_count is incorrect here. */
6761 giv_count++;
6763 giv_array
6774 {
6776 rtx single_use;
6781 /* If a DEST_REG GIV is used only once, do not allow it to combine
6782 with anything, for in doing so we will gain nothing that cannot
6783 be had by simply letting the GIV with which we would have combined
6784 to be reduced on its own. The losage shows up in particular with
6785 DEST_ADDR targets on hosts with reg+reg addressing, though it can
6786 be seen elsewhere as well. */
6793 /* Add an additional weight for zero addends. */
6798 {
6799 rtx this_combine;
6804 {
6807 }
6808 }
6810 }
6812 /* Iterate, combining until we can't. */
6813 restart:
6817 {
6820 {
6826 }
6828 }
6831 {
6837 /* If it has already been combined, skip. */
6842 {
6845 /* If it has already been combined, skip. */
6847 {
6852 /* For destination, we now may replace by mem expression instead
6853 of register. This changes the costs considerably, so add the
6854 compensation. */
6864 /* ??? The new final_[bg]iv_value code does a much better job
6865 of finding replaceable giv's, and hence this code may no
6866 longer be necessary. */
6870 /* To help optimize the next set of combinations, remove
6871 this giv from the benefits of other potential mates. */
6873 {
6877 }
6884 }
6885 }
6887 /* To help optimize the next set of combinations, remove
6888 this giv from the benefits of other potential mates. */
6890 {
6892 {
6896 }
6900 /* We've finished with this giv, and everything it touched.
6901 Restart the combination so that proper weights for the
6902 rest of the givs are properly taken into account. */
6903 /* ??? Ideally we would compact the arrays at this point, so
6904 as to not cover old ground. But sanely compacting
6905 can_combine is tricky. */
6907 }
6908 }
6910 /* Clean up. */
6913 }
6914 \f
6915 /* Generate sequence for REG = B * M + A. */
6917 static rtx
6923 {
6924 rtx seq;
6925 rtx result;
6928 /* Use unsigned arithmetic. */
6936 }
6939 /* Update registers created in insn sequence SEQ. */
6941 static void
6944 rtx seq;
6945 {
6946 /* Update register info for alias analysis. */
6949 {
6952 {
6956 }
6957 }
6958 else
6959 {
6963 }
6964 }
6967 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
6969 void
6976 basic_block before_bb;
6977 rtx before_insn;
6978 {
6979 rtx seq;
6982 {
6985 }
6987 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
6990 /* Increase the lifetime of any invariants moved further in code. */
6997 /* It is possible that the expansion created lots of new registers.
6998 Iterate over the sequence we just created and record them all. */
7000 }
7003 /* Emit insns in loop pre-header to set REG = B * M + A. */
7005 void
7012 {
7013 rtx seq;
7015 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7018 /* Increase the lifetime of any invariants moved further in code.
7019 ???? Is this really necessary? */
7026 /* It is possible that the expansion created lots of new registers.
7027 Iterate over the sequence we just created and record them all. */
7029 }
7032 /* Emit insns after loop to set REG = B * M + A. */
7034 void
7041 {
7042 rtx seq;
7044 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7049 /* It is possible that the expansion created lots of new registers.
7050 Iterate over the sequence we just created and record them all. */
7052 }
7056 /* Similar to gen_add_mult, but compute cost rather than generating
7057 sequence. */
7059 static int
7065 {
7075 {
7080 }
7083 }
7084 \f
7085 /* Test whether A * B can be computed without
7086 an actual multiply insn. Value is 1 if so. */
7088 static int
7090 rtx a;
7091 rtx b;
7092 {
7094 rtx tmp;
7097 /* If only one is constant, make it B. */
7101 /* If first constant, both constant, so don't need multiply. */
7105 /* If second not constant, neither is constant, so would need multiply. */
7109 /* One operand is constant, so might not need multiply insn. Generate the
7110 code for the multiply and see if a call or multiply, or long sequence
7111 of insns is generated. */
7119 {
7124 else
7126 {
7135 {
7138 }
7139 }
7140 }
7150 }
7151 \f
7152 /* Check to see if loop can be terminated by a "decrement and branch until
7153 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7154 Also try reversing an increment loop to a decrement loop
7155 to see if the optimization can be performed.
7156 Value is nonzero if optimization was performed. */
7158 /* This is useful even if the architecture doesn't have such an insn,
7159 because it might change a loops which increments from 0 to n to a loop
7160 which decrements from n to 0. A loop that decrements to zero is usually
7161 faster than one that increments from zero. */
7163 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7164 such as approx_final_value, biv_total_increment, loop_iterations, and
7165 final_[bg]iv_value. */
7167 static int
7171 {
7176 rtx reg;
7177 rtx jump_label;
7178 rtx final_value;
7179 rtx start_value;
7180 rtx new_add_val;
7181 rtx comparison;
7182 rtx before_comparison;
7183 rtx p;
7184 rtx jump;
7185 rtx first_compare;
7190 /* If last insn is a conditional branch, and the insn before tests a
7191 register value, try to optimize it. Otherwise, we can't do anything. */
7200 /* Try to compute whether the compare/branch at the loop end is one or
7201 two instructions. */
7207 else
7210 {
7211 /* If more than one condition is present to control the loop, then
7212 do not proceed, as this function does not know how to rewrite
7213 loop tests with more than one condition.
7215 Look backwards from the first insn in the last comparison
7216 sequence and see if we've got another comparison sequence. */
7218 rtx jump1;
7222 }
7224 /* Check all of the bivs to see if the compare uses one of them.
7225 Skip biv's set more than once because we can't guarantee that
7226 it will be zero on the last iteration. Also skip if the biv is
7227 used between its update and the test insn. */
7230 {
7235 first_compare))
7237 }
7242 /* Look for the case where the basic induction variable is always
7243 nonnegative, and equals zero on the last iteration.
7244 In this case, add a reg_note REG_NONNEG, which allows the
7245 m68k DBRA instruction to be used. */
7253 {
7254 /* Initial value must be greater than 0,
7255 init_val % -dec_value == 0 to ensure that it equals zero on
7256 the last iteration */
7262 {
7263 /* register always nonnegative, add REG_NOTE to branch */
7271 }
7273 /* If the decrement is 1 and the value was tested as >= 0 before
7274 the loop, then we can safely optimize. */
7276 {
7289 {
7297 }
7298 }
7299 }
7302 {
7303 /* Try to change inc to dec, so can apply above optimization. */
7304 /* Can do this if:
7305 all registers modified are induction variables or invariant,
7306 all memory references have non-overlapping addresses
7307 (obviously true if only one write)
7308 allow 2 insns for the compare/jump at the end of the loop. */
7309 /* Also, we must avoid any instructions which use both the reversed
7310 biv and another biv. Such instructions will fail if the loop is
7311 reversed. We meet this condition by requiring that either
7312 no_use_except_counting is true, or else that there is only
7313 one biv. */
7315 /* 1 if the iteration var is used only to count iterations. */
7317 /* 1 if the loop has no memory store, or it has a single memory store
7318 which is reversible. */
7322 {
7326 /* If there are no givs for this biv, and the only exit is the
7327 fall through at the end of the loop, then
7328 see if perhaps there are no uses except to count. */
7332 {
7337 /* An insn that sets the biv is okay. */
7338 ;
7342 {
7343 /* If either of these insns uses the biv and sets a pseudo
7344 that has more than one usage, then the biv has uses
7345 other than counting since it's used to derive a value
7346 that is used more than one time. */
7348 regs);
7350 {
7353 }
7354 }
7356 {
7359 }
7360 }
7362 /* A biv has uses besides counting if it is used to set another biv. */
7365 {
7368 }
7369 }
7372 /* No need to worry about MEMs. */
7373 ;
7375 {
7380 /* If the loop has a single store, and the destination address is
7381 invariant, then we can't reverse the loop, because this address
7382 might then have the wrong value at loop exit.
7383 This would work if the source was invariant also, however, in that
7384 case, the insn should have been moved out of the loop. */
7387 {
7390 /* If we could prove that each of the memory locations
7391 written to was different, then we could reverse the
7392 store -- but we don't presently have any way of
7393 knowing that. */
7396 /* If the store depends on a register that is set after the
7397 store, it depends on the initial value, and is thus not
7398 reversible. */
7400 {
7407 }
7408 }
7409 }
7410 else
7413 /* This code only acts for innermost loops. Also it simplifies
7414 the memory address check by only reversing loops with
7415 zero or one memory access.
7416 Two memory accesses could involve parts of the same array,
7417 and that can't be reversed.
7418 If the biv is used only for counting, than we don't need to worry
7419 about all these things. */
7424 && reversible_mem_store
7429 {
7430 rtx tem;
7432 /* Loop can be reversed. */
7436 /* Now check other conditions:
7438 The increment must be a constant, as must the initial value,
7439 and the comparison code must be LT.
7441 This test can probably be improved since +/- 1 in the constant
7442 can be obtained by changing LT to LE and vice versa; this is
7443 confusing. */
7446 /* for constants, LE gets turned into LT */
7450 {
7461 comparison_const_width
7463 else
7464 comparison_const_width
7468 comparison_sign_mask
7471 /* If the comparison value is not a loop invariant, then we
7472 can not reverse this loop.
7474 ??? If the insns which initialize the comparison value as
7475 a whole compute an invariant result, then we could move
7476 them out of the loop and proceed with loop reversal. */
7484 /* Normalize the initial value if it is an integer and
7485 has no other use except as a counter. This will allow
7486 a few more loops to be reversed. */
7490 {
7492 /* The code below requires comparison_val to be a multiple
7493 of add_val in order to do the loop reversal, so
7494 round up comparison_val to a multiple of add_val.
7495 Since comparison_value is constant, we know that the
7496 current comparison code is LT. */
7498 comparison_val
7500 /* We postpone overflow checks for COMPARISON_VAL here;
7501 even if there is an overflow, we might still be able to
7502 reverse the loop, if converting the loop exit test to
7503 NE is possible. */
7505 }
7507 /* First check if we can do a vanilla loop reversal. */
7509 /* If we have a decrement_and_branch_on_count,
7510 prefer the NE test, since this will allow that
7511 instruction to be generated. Note that we must
7512 use a vanilla loop reversal if the biv is used to
7513 calculate a giv or has a non-counting use. */
7514 #if ! defined (HAVE_decrement_and_branch_until_zero) \
7515 && defined (HAVE_decrement_and_branch_on_count)
7519 #endif
7521 /* Now do postponed overflow checks on COMPARISON_VAL. */
7524 {
7525 /* Register will always be nonnegative, with value
7526 0 on last iteration */
7530 }
7534 {
7537 }
7538 else
7544 /* If the initial value is not zero, or if the comparison
7545 value is not an exact multiple of the increment, then we
7546 can not reverse this loop. */
7549 {
7552 }
7553 else
7554 {
7557 }
7561 /* Reset these in case we normalized the initial value
7562 and comparison value above. */
7565 {
7567 final_value
7569 }
7572 /* Save some info needed to produce the new insns. */
7577 /* Set start_value; if this is not a CONST_INT, we need
7578 to generate a SUB.
7579 Initialize biv to start_value before loop start.
7580 The old initializing insn will be deleted as a
7581 dead store by flow.c. */
7584 {
7587 }
7589 {
7597 start_value
7603 }
7605 {
7608 initial_value);
7612 start_value
7615 }
7616 else
7617 /* We could handle the other cases too, but it'll be
7618 better to have a testcase first. */
7621 /* We may not have a single insn which can increment a reg, so
7622 create a sequence to hold all the insns from expand_inc. */
7631 /* Update biv info to reflect its new status. */
7636 /* Update loop info. */
7645 /* Inc LABEL_NUSES so that delete_insn will
7646 not delete the label. */
7649 /* Emit an insn after the end of the loop to set the biv's
7650 proper exit value if it is used anywhere outside the loop. */
7656 /* Delete compare/branch at end of loop. */
7661 /* Add new compare/branch insn at end of loop. */
7673 ;
7679 {
7681 {
7682 /* Increment of LABEL_NUSES done above. */
7683 /* Register is now always nonnegative,
7684 so add REG_NONNEG note to the branch. */
7687 }
7689 }
7691 /* No insn may reference both the reversed and another biv or it
7692 will fail (see comment near the top of the loop reversal
7693 code).
7694 Earlier on, we have verified that the biv has no use except
7695 counting, or it is the only biv in this function.
7696 However, the code that computes no_use_except_counting does
7697 not verify reg notes. It's possible to have an insn that
7698 references another biv, and has a REG_EQUAL note with an
7699 expression based on the reversed biv. To avoid this case,
7700 remove all REG_EQUAL notes based on the reversed biv
7701 here. */
7704 {
7707 /* If this is a set of a GIV based on the reversed biv, any
7708 REG_EQUAL notes should still be correct. */
7715 {
7720 else
7722 }
7723 }
7725 /* Mark that this biv has been reversed. Each giv which depends
7726 on this biv, and which is also live past the end of the loop
7727 will have to be fixed up. */
7732 {
7736 else
7738 }
7741 }
7742 }
7743 }
7746 }
7747 \f
7748 /* Verify whether the biv BL appears to be eliminable,
7749 based on the insns in the loop that refer to it.
7751 If ELIMINATE_P is non-zero, actually do the elimination.
7753 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
7754 determine whether invariant insns should be placed inside or at the
7755 start of the loop. */
7757 static int
7763 {
7766 rtx p;
7768 /* Scan all insns in the loop, stopping if we find one that uses the
7769 biv in a way that we cannot eliminate. */
7772 {
7777 /* If this is a libcall that sets a giv, skip ahead to its end. */
7779 {
7783 {
7788 {
7795 }
7796 }
7797 }
7802 {
7808 }
7809 }
7812 {
7817 }
7820 }
7821 \f
7822 /* INSN and REFERENCE are instructions in the same insn chain.
7823 Return non-zero if INSN is first. */
7825 int
7828 {
7832 {
7833 /* Start with test for not first so that INSN == REFERENCE yields not
7834 first. */
7840 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
7841 previous insn, hence the <= comparison below does not work if
7842 P is a note. */
7853 }
7854 }
7856 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
7857 the offset that we have to take into account due to auto-increment /
7858 div derivation is zero. */
7859 static int
7862 rtx insn;
7863 {
7864 /* If the giv V had the auto-inc address optimization applied
7865 to it, and INSN occurs between the giv insn and the biv
7866 insn, then we'd have to adjust the value used here.
7867 This is rare, so we don't bother to make this possible. */
7876 }
7878 /* If BL appears in X (part of the pattern of INSN), see if we can
7879 eliminate its use. If so, return 1. If not, return 0.
7881 If BIV does not appear in X, return 1.
7883 If ELIMINATE_P is non-zero, actually do the elimination.
7884 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
7885 Depending on how many items have been moved out of the loop, it
7886 will either be before INSN (when WHERE_INSN is non-zero) or at the
7887 start of the loop (when WHERE_INSN is zero). */
7889 static int
7895 basic_block where_bb;
7896 rtx where_insn;
7897 {
7903 #ifdef HAVE_cc0
7905 #endif
7911 {
7913 /* If we haven't already been able to do something with this BIV,
7914 we can't eliminate it. */
7920 /* If this sets the BIV, it is not a problem. */
7924 /* If this is an insn that defines a giv, it is also ok because
7925 it will go away when the giv is reduced. */
7930 #ifdef HAVE_cc0
7932 {
7933 /* Can replace with any giv that was reduced and
7934 that has (MULT_VAL != 0) and (ADD_VAL == 0).
7935 Require a constant for MULT_VAL, so we know it's nonzero.
7936 ??? We disable this optimization to avoid potential
7937 overflows. */
7945 {
7952 /* If the giv has the opposite direction of change,
7953 then reverse the comparison. */
7957 else
7960 /* We can probably test that giv's reduced reg. */
7963 }
7965 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
7966 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
7967 Require a constant for MULT_VAL, so we know it's nonzero.
7968 ??? Do this only if ADD_VAL is a pointer to avoid a potential
7969 overflow problem. */
7981 {
7988 /* If the giv has the opposite direction of change,
7989 then reverse the comparison. */
7993 else
7997 /* Replace biv with the giv's reduced register. */
8002 /* Insn doesn't support that constant or invariant. Copy it
8003 into a register (it will be a loop invariant.) */
8010 /* Substitute the new register for its invariant value in
8011 the compare expression. */
8015 }
8016 }
8017 #endif
8024 /* See if either argument is the biv. */
8029 else
8033 {
8034 /* First try to replace with any giv that has constant positive
8035 mult_val and constant add_val. We might be able to support
8036 negative mult_val, but it seems complex to do it in general. */
8048 {
8055 /* Replace biv with the giv's reduced reg. */
8058 /* If all constants are actually constant integers and
8059 the derived constant can be directly placed in the COMPARE,
8060 do so. */
8064 {
8069 }
8070 else
8071 {
8072 /* Otherwise, load it into a register. */
8078 }
8081 }
8083 /* Look for giv with positive constant mult_val and nonconst add_val.
8084 Insert insns to calculate new compare value.
8085 ??? Turn this off due to possible overflow. */
8093 {
8094 rtx tem;
8104 /* Replace biv with giv's reduced register. */
8108 /* Compute value to compare against. */
8112 /* Use it in this insn. */
8116 }
8117 }
8119 {
8121 {
8122 /* Look for giv with constant positive mult_val and nonconst
8123 add_val. Insert insns to compute new compare value.
8124 ??? Turn this off due to possible overflow. */
8131 {
8132 rtx tem;
8142 /* Replace biv with giv's reduced register. */
8146 /* Compute value to compare against. */
8153 }
8154 }
8156 /* This code has problems. Basically, you can't know when
8157 seeing if we will eliminate BL, whether a particular giv
8158 of ARG will be reduced. If it isn't going to be reduced,
8159 we can't eliminate BL. We can try forcing it to be reduced,
8160 but that can generate poor code.
8162 The problem is that the benefit of reducing TV, below should
8163 be increased if BL can actually be eliminated, but this means
8164 we might have to do a topological sort of the order in which
8165 we try to process biv. It doesn't seem worthwhile to do
8166 this sort of thing now. */
8168 #if 0
8169 /* Otherwise the reg compared with had better be a biv. */
8174 /* Look for a pair of givs, one for each biv,
8175 with identical coefficients. */
8177 {
8189 {
8196 /* Replace biv with its giv's reduced reg. */
8198 /* Replace other operand with the other giv's
8199 reduced reg. */
8202 }
8203 }
8204 #endif
8205 }
8207 /* If we get here, the biv can't be eliminated. */
8211 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8212 biv is used in it, since it will be replaced. */
8220 }
8222 /* See if any subexpression fails elimination. */
8225 {
8227 {
8240 }
8241 }
8244 }
8245 \f
8246 /* Return nonzero if the last use of REG
8247 is in an insn following INSN in the same basic block. */
8249 static int
8251 rtx reg;
8252 rtx insn;
8253 {
8254 rtx n;
8258 {
8261 }
8263 }
8264 \f
8265 /* Called via `note_stores' to record the initial value of a biv. Here we
8266 just record the location of the set and process it later. */
8268 static void
8270 rtx dest;
8271 rtx set;
8273 {
8284 /* If this is the first set found, record it. */
8286 {
8289 }
8290 }
8291 \f
8292 /* If any of the registers in X are "old" and currently have a last use earlier
8293 than INSN, update them to have a last use of INSN. Their actual last use
8294 will be the previous insn but it will not have a valid uid_luid so we can't
8295 use it. X must be a source expression only. */
8297 static void
8299 rtx x;
8300 rtx insn;
8301 {
8302 /* Check for the case where INSN does not have a valid luid. In this case,
8303 there is no need to modify the regno_last_uid, as this can only happen
8304 when code is inserted after the loop_end to set a pseudo's final value,
8305 and hence this insn will never be the last use of x.
8306 ???? This comment is not correct. See for example loop_givs_reduce.
8307 This may insert an insn before another new insn. */
8311 {
8313 }
8314 else
8315 {
8319 {
8325 }
8326 }
8327 }
8328 \f
8329 /* Given an insn INSN and condition COND, return the condition in a
8330 canonical form to simplify testing by callers. Specifically:
8332 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8333 (2) Both operands will be machine operands; (cc0) will have been replaced.
8334 (3) If an operand is a constant, it will be the second operand.
8335 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8336 for GE, GEU, and LEU.
8338 If the condition cannot be understood, or is an inequality floating-point
8339 comparison which needs to be reversed, 0 will be returned.
8341 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
8343 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8344 insn used in locating the condition was found. If a replacement test
8345 of the condition is desired, it should be placed in front of that
8346 insn and we will be sure that the inputs are still valid.
8348 If WANT_REG is non-zero, we wish the condition to be relative to that
8349 register, if possible. Therefore, do not canonicalize the condition
8350 further. */
8352 rtx
8354 rtx insn;
8355 rtx cond;
8358 rtx want_reg;
8359 {
8362 rtx set;
8363 rtx tem;
8381 /* If we are comparing a register with zero, see if the register is set
8382 in the previous insn to a COMPARE or a comparison operation. Perform
8383 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
8384 in cse.c */
8389 {
8390 /* Set non-zero when we find something of interest. */
8393 #ifdef HAVE_cc0
8394 /* If comparison with cc0, import actual comparison from compare
8395 insn. */
8397 {
8408 }
8409 #endif
8411 /* If this is a COMPARE, pick up the two things being compared. */
8413 {
8417 }
8421 /* Go back to the previous insn. Stop if it is not an INSN. We also
8422 stop if it isn't a single set or if it has a REG_INC note because
8423 we don't want to bother dealing with it. */
8437 /* If this is setting OP0, get what it sets it to if it looks
8438 relevant. */
8440 {
8443 /* ??? We may not combine comparisons done in a CCmode with
8444 comparisons not done in a CCmode. This is to aid targets
8445 like Alpha that have an IEEE compliant EQ instruction, and
8446 a non-IEEE compliant BEQ instruction. The use of CCmode is
8447 actually artificial, simply to prevent the combination, but
8448 should not affect other platforms.
8450 However, we must allow VOIDmode comparisons to match either
8451 CCmode or non-CCmode comparison, because some ports have
8452 modeless comparisons inside branch patterns.
8454 ??? This mode check should perhaps look more like the mode check
8455 in simplify_comparison in combine. */
8463 && (STORE_FLAG_VALUE
8466 #ifdef FLOAT_STORE_FLAG_VALUE
8469 && (REAL_VALUE_NEGATIVE
8471 #endif
8472 ))
8483 && (STORE_FLAG_VALUE
8486 #ifdef FLOAT_STORE_FLAG_VALUE
8489 && (REAL_VALUE_NEGATIVE
8491 #endif
8492 ))
8498 {
8501 }
8502 else
8504 }
8507 /* If this sets OP0, but not directly, we have to give up. */
8511 {
8515 {
8520 }
8525 }
8526 }
8528 /* If constant is first, put it last. */
8532 /* If OP0 is the result of a comparison, we weren't able to find what
8533 was really being compared, so fail. */
8537 /* Canonicalize any ordered comparison with integers involving equality
8538 if we can do computations in the relevant mode and we do not
8539 overflow. */
8544 {
8547 unsigned HOST_WIDE_INT max_val
8551 {
8557 /* When cross-compiling, const_val might be sign-extended from
8558 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
8578 }
8579 }
8581 #ifdef HAVE_cc0
8582 /* Never return CC0; return zero instead. */
8585 #endif
8588 }
8590 /* Given a jump insn JUMP, return the condition that will cause it to branch
8591 to its JUMP_LABEL. If the condition cannot be understood, or is an
8592 inequality floating-point comparison which needs to be reversed, 0 will
8593 be returned.
8595 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8596 insn used in locating the condition was found. If a replacement test
8597 of the condition is desired, it should be placed in front of that
8598 insn and we will be sure that the inputs are still valid. */
8600 rtx
8602 rtx jump;
8604 {
8605 rtx cond;
8607 rtx set;
8609 /* If this is not a standard conditional jump, we can't parse it. */
8617 /* If this branches to JUMP_LABEL when the condition is false, reverse
8618 the condition. */
8619 reverse
8624 }
8626 /* Similar to above routine, except that we also put an invariant last
8627 unless both operands are invariants. */
8629 rtx
8632 rtx x;
8633 {
8643 }
8645 /* Scan the function and determine whether it has indirect (computed) jumps.
8647 This is taken mostly from flow.c; similar code exists elsewhere
8648 in the compiler. It may be useful to put this into rtlanal.c. */
8649 static int
8651 rtx start;
8652 {
8653 rtx insn;
8660 }
8662 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
8663 documentation for LOOP_MEMS for the definition of `appropriate'.
8664 This function is called from prescan_loop via for_each_rtx. */
8666 static int
8670 {
8679 {
8684 /* We're not interested in MEMs that are only clobbered. */
8688 /* We're not interested in the MEM associated with a
8689 CONST_DOUBLE, so there's no need to traverse into this. */
8693 /* We're not interested in any MEMs that only appear in notes. */
8697 /* This is not a MEM. */
8699 }
8701 /* See if we've already seen this MEM. */
8704 {
8706 /* The modes of the two memory accesses are different. If
8707 this happens, something tricky is going on, and we just
8708 don't optimize accesses to this MEM. */
8712 }
8714 /* Resize the array, if necessary. */
8716 {
8719 else
8725 }
8727 /* Actually insert the MEM. */
8729 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
8730 because we can't put it in a register. We still store it in the
8731 table, though, so that if we see the same address later, but in a
8732 non-BLK mode, we'll not think we can optimize it at that point. */
8738 }
8741 /* Allocate REGS->ARRAY or reallocate it if it is too small.
8743 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
8744 register that is modified by an insn between FROM and TO. If the
8745 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
8746 more, stop incrementing it, to avoid overflow.
8748 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
8749 register I is used, if it is only used once. Otherwise, it is set
8750 to 0 (for no uses) or const0_rtx for more than one use. This
8751 parameter may be zero, in which case this processing is not done.
8753 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
8754 optimize register I. */
8756 static void
8760 {
8763 /* last_set[n] is nonzero iff reg n has been set in the current
8764 basic block. In that case, it is the insn that last set reg n. */
8766 rtx insn;
8772 /* Grow the regs array if not allocated or too small. */
8774 {
8780 /* Zero the new elements. */
8783 }
8785 /* Clear previously scanned fields but do not clear n_times_set. */
8787 {
8791 }
8795 /* Scan the loop, recording register usage. */
8798 {
8800 {
8801 /* Record registers that have exactly one use. */
8804 /* Include uses in REG_EQUAL notes. */
8812 {
8816 last_set);
8817 }
8818 }
8822 }
8825 {
8828 }
8830 #ifdef AVOID_CCMODE_COPIES
8831 /* Don't try to move insns which set CC registers if we should not
8832 create CCmode register copies. */
8836 #endif
8838 /* Set regs->array[I].n_times_set for the new registers. */
8843 }
8845 /* Returns the number of real INSNs in the LOOP. */
8847 static int
8850 {
8852 rtx insn;
8860 }
8862 /* Move MEMs into registers for the duration of the loop. */
8864 static void
8867 {
8874 rtx end_label;
8875 /* Nonzero if the next instruction may never be executed. */
8882 /* We cannot use next_label here because it skips over normal insns. */
8887 /* Check to see if it's possible that some instructions in the loop are
8888 never executed. Also check if there is a goto out of the loop other
8889 than right after the end of the loop. */
8893 {
8897 /* If we enter the loop in the middle, and scan
8898 around to the beginning, don't set maybe_never
8899 for that. This must be an unconditional jump,
8900 otherwise the code at the top of the loop might
8901 never be executed. Unconditional jumps are
8902 followed a by barrier then loop end. */
8907 {
8908 /* If this is a jump outside of the loop but not right
8909 after the end of the loop, we would have to emit new fixup
8910 sequences for each such label. */
8912 JUMP_INSN is executed, we must be conservative. */
8921 /* Something complicated. */
8923 else
8924 /* If there are any more instructions in the loop, they
8925 might not be reached. */
8927 }
8930 }
8932 /* Find start of the extended basic block that enters the loop. */
8936 ;
8941 /* Build table of mems that get set to constant values before the
8942 loop. */
8946 /* Actually move the MEMs. */
8948 {
8949 regset_head load_copies;
8950 regset_head store_copies;
8952 rtx reg;
8954 rtx mem_list_entry;
8958 /* There's no telling whether or not MEM is modified. */
8961 /* Go through the MEMs written to in the loop to see if this
8962 one is aliased by one of them. */
8965 {
8970 {
8971 /* MEM is indeed aliased by this store. */
8974 }
8976 }
8982 /* If this MEM is written to, we must be sure that there
8983 are no reads from another MEM that aliases this one. */
8985 {
8989 {
8993 VOIDmode,
8995 rtx_varies_p))
8996 {
8997 /* It's not safe to hoist loop_info->mems[i] out of
8998 the loop because writes to it might not be
8999 seen by reads from loop_info->mems[j]. */
9002 }
9003 }
9004 }
9007 /* We can't access the MEM outside the loop; it might
9008 cause a trap that wouldn't have happened otherwise. */
9012 /* We thought we were going to lift this MEM out of the
9013 loop, but later discovered that we could not. */
9019 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9020 order to keep scan_loop from moving stores to this MEM
9021 out of the loop just because this REG is neither a
9022 user-variable nor used in the loop test. */
9027 /* Now, replace all references to the MEM with the
9028 corresponding pseudos. */
9033 {
9035 {
9036 rtx set;
9040 /* See if this copies the mem into a register that isn't
9041 modified afterwards. We'll try to do copy propagation
9042 a little further on. */
9044 /* @@@ This test is _way_ too conservative. */
9045 && ! maybe_never
9053 /* See if this copies the mem from a register that isn't
9054 modified afterwards. We'll try to remove the
9055 redundant copy later on by doing a little register
9056 renaming and copy propagation. This will help
9057 to untangle things for the BIV detection code. */
9059 && ! maybe_never
9067 /* Replace the memory reference with the shadow register. */
9070 }
9075 }
9078 /* We couldn't replace all occurrences of the MEM. */
9080 else
9081 {
9082 /* Load the memory immediately before LOOP->START, which is
9083 the NOTE_LOOP_BEG. */
9085 rtx set;
9091 {
9095 {
9099 /* Extending hard register lifetimes causes crash
9100 on SRC targets. Doing so on non-SRC is
9101 probably also not good idea, since we most
9102 probably have pseudoregister equivalence as
9103 well. */
9106 }
9107 /* Use the constant equivalence if that is cheap enough. */
9113 {
9116 }
9118 /* If best_equiv is nonzero, we know that MEM is set to a
9119 constant or register before the loop. We will use this
9120 knowledge to initialize the shadow register with that
9121 constant or reg rather than by loading from MEM. */
9124 }
9129 {
9132 {
9135 }
9136 }
9144 {
9146 {
9149 }
9151 /* Store the memory immediately after END, which is
9152 the NOTE_LOOP_END. */
9155 }
9158 {
9163 }
9165 /* Attempt a bit of copy propagation. This helps untangle the
9166 data flow, and enables {basic,general}_induction_var to find
9167 more bivs/givs. */
9168 EXECUTE_IF_SET_IN_REG_SET
9170 {
9172 });
9175 EXECUTE_IF_SET_IN_REG_SET
9177 {
9179 });
9181 }
9182 }
9185 {
9186 /* Now, we need to replace all references to the previous exit
9187 label with the new one. */
9188 rtx_pair rr;
9193 {
9196 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9197 field. This is not handled by for_each_rtx because it doesn't
9198 handle unprinted ('0') fields. We need to update JUMP_LABEL
9199 because the immediately following unroll pass will use it.
9200 replace_label would not work anyways, because that only handles
9201 LABEL_REFs. */
9204 }
9205 }
9208 }
9210 /* For communication between note_reg_stored and its caller. */
9211 struct note_reg_stored_arg
9212 {
9214 rtx reg;
9215 };
9217 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9218 is equal to ARG. */
9219 static void
9223 {
9227 }
9229 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9230 There must be exactly one insn that sets this pseudo; it will be
9231 deleted if all replacements succeed and we can prove that the register
9232 is not used after the loop. */
9234 static void
9237 rtx replacement;
9239 {
9240 /* This is the reg that we are copying from. */
9243 rtx insn;
9244 /* These help keep track of whether we replaced all uses of the reg. */
9251 {
9252 rtx set;
9254 /* Only substitute within one extended basic block from the initializing
9255 insn. */
9262 /* Is this the initializing insn? */
9267 {
9274 }
9276 /* Only substitute after seeing the initializing insn. */
9278 {
9285 /* Stop replacing when REPLACEMENT is modified. */
9290 {
9293 /* It is possible that we've turned previously valid REG_EQUAL to
9294 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
9295 REPLACEMENT is modified, we get different meaning. */
9299 }
9300 }
9301 }
9305 {
9309 {
9310 rtx first;
9311 rtx retval_note;
9313 /* Assume we're just deleting INIT_INSN. */
9315 /* Look for REG_RETVAL note. If we're deleting the end of
9316 the libcall sequence, the whole sequence can go. */
9318 /* If we found a REG_RETVAL note, find the first instruction
9319 in the sequence. */
9323 /* Delete the instructions. */
9325 }
9328 }
9329 }
9331 /* Replace all the instructions from FIRST up to and including LAST
9332 with NOTE_INSN_DELETED notes. */
9334 static void
9336 rtx first;
9337 rtx last;
9338 {
9340 {
9346 /* If this was the LAST instructions we're supposed to delete,
9347 we're done. */
9352 }
9353 }
9355 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
9356 loop LOOP if the order of the sets of these registers can be
9357 swapped. There must be exactly one insn within the loop that sets
9358 this pseudo followed immediately by a move insn that sets
9359 REPLACEMENT with REGNO. */
9360 static void
9363 rtx replacement;
9365 {
9366 rtx insn;
9375 {
9376 /* Search for the insn that copies REGNO to NEW_REGNO? */
9384 }
9387 {
9388 rtx prev_insn;
9389 rtx prev_set;
9391 /* Some DEF-USE info would come in handy here to make this
9392 function more general. For now, just check the previous insn
9393 which is the most likely candidate for setting REGNO. */
9401 {
9402 /* We have:
9403 (set (reg regno) (expr))
9404 (set (reg new_regno) (reg regno))
9406 so try converting this to:
9407 (set (reg new_regno) (expr))
9408 (set (reg regno) (reg new_regno))
9410 The former construct is often generated when a global
9411 variable used for an induction variable is shadowed by a
9412 register (NEW_REGNO). The latter construct improves the
9413 chances of GIV replacement and BIV elimination. */
9423 {
9430 /* Update first use of REGNO. */
9434 /* Now perform copy propagation to hopefully
9435 remove all uses of REGNO within the loop. */
9437 }
9438 }
9439 }
9440 }
9442 /* Replace MEM with its associated pseudo register. This function is
9443 called from load_mems via for_each_rtx. DATA is actually a pointer
9444 to a structure describing the instruction currently being scanned
9445 and the MEM we are currently replacing. */
9447 static int
9451 {
9459 {
9464 /* We're not interested in the MEM associated with a
9465 CONST_DOUBLE, so there's no need to traverse into one. */
9469 /* This is not a MEM. */
9471 }
9474 /* This is not the MEM we are currently replacing. */
9477 /* Actually replace the MEM. */
9481 }
9483 static void
9485 rtx insn;
9486 rtx mem;
9487 rtx reg;
9488 {
9489 loop_replace_args args;
9496 }
9498 /* Replace one register with another. Called through for_each_rtx; PX points
9499 to the rtx being scanned. DATA is actually a pointer to
9500 a structure of arguments. */
9502 static int
9506 {
9517 }
9519 static void
9521 rtx insn;
9522 rtx reg;
9523 rtx replacement;
9524 {
9525 loop_replace_args args;
9532 }
9534 /* Replace occurrences of the old exit label for the loop with the new
9535 one. DATA is an rtx_pair containing the old and new labels,
9536 respectively. */
9538 static int
9542 {
9561 }
9562 \f
9563 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
9564 (ignored in the interim). */
9566 static rtx
9569 basic_block where_bb ATTRIBUTE_UNUSED;
9570 rtx where_insn;
9571 rtx pattern;
9572 {
9574 }
9577 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
9578 in basic block WHERE_BB (ignored in the interim) within the loop
9579 otherwise hoist PATTERN into the loop pre-header. */
9581 rtx
9584 basic_block where_bb ATTRIBUTE_UNUSED;
9585 rtx where_insn;
9586 rtx pattern;
9587 {
9591 }
9594 /* Emit call insn for PATTERN before WHERE_INSN in basic block
9595 WHERE_BB (ignored in the interim) within the loop. */
9597 static rtx
9600 basic_block where_bb ATTRIBUTE_UNUSED;
9601 rtx where_insn;
9602 rtx pattern;
9603 {
9605 }
9608 /* Hoist insn for PATTERN into the loop pre-header. */
9610 rtx
9613 rtx pattern;
9614 {
9616 }
9619 /* Hoist call insn for PATTERN into the loop pre-header. */
9621 static rtx
9624 rtx pattern;
9625 {
9627 }
9630 /* Sink insn for PATTERN after the loop end. */
9632 rtx
9635 rtx pattern;
9636 {
9638 }
9641 /* If the loop has multiple exits, emit insn for PATTERN before the
9642 loop to ensure that it will always be executed no matter how the
9643 loop exits. Otherwise, emit the insn for PATTERN after the loop,
9644 since this is slightly more efficient. */
9646 static rtx
9649 rtx pattern;
9650 {
9653 else
9655 }
9656 \f
9657 static void
9662 {
9670 iv_num++;
9675 {
9678 }
9679 }
9682 static void
9687 {
9689 rtx incr;
9700 {
9703 }
9705 {
9708 }
9712 {
9716 }
9719 {
9723 }
9725 /* List the increments. */
9727 {
9731 }
9733 /* List the givs. */
9735 {
9740 else
9743 }
9744 }
9747 static void
9752 {
9763 {
9767 }
9770 }
9773 static void
9778 {
9785 else
9801 {
9803 {
9815 }
9816 }
9827 {
9831 }
9834 }
9837 void
9840 {
9842 }
9845 void
9848 {
9850 }
9853 void
9856 {
9858 }
9861 void
9864 {
9866 }
9869 #define LOOP_BLOCK_NUM_1(INSN) \
9870 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
9872 /* The notes do not have an assigned block, so look at the next insn. */
9873 #define LOOP_BLOCK_NUM(INSN) \
9874 ((INSN) ? (GET_CODE (INSN) == NOTE \
9875 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
9876 : LOOP_BLOCK_NUM_1 (INSN)) \
9877 : -1)
9879 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
9881 static void
9886 {
9887 rtx label;
9892 /* Print diagnostics to compare our concept of a loop with
9893 what the loop notes say. */
9908 {
9928 {
9931 {
9934 }
9935 }
9938 /* This can happen when a marked loop appears as two nested loops,
9939 say from while (a || b) {}. The inner loop won't match
9940 the loop markers but the outer one will. */
9943 }
9944 }
9946 /* Call this function from the debugger to dump LOOP. */
9948 void
9951 {
9953 }
9955 /* Call this function from the debugger to dump LOOPS. */
9957 void
9960 {
9962 }