| blob | 48cc73deb9e830178cf2c915e0ff74b6fa4763af |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 (FIRST_SPE_HIGH_REGNO 117)
60 (LAST_SPE_HIGH_REGNO 148)
61 ])
63 ;;
64 ;; UNSPEC usage
65 ;;
67 (define_c_enum "unspec"
68 [UNSPEC_FRSP ; frsp for POWER machines
69 UNSPEC_PROBE_STACK ; probe stack memory reference
70 UNSPEC_TOCPTR ; address of a word pointing to the TOC
71 UNSPEC_TOC ; address of the TOC (more-or-less)
72 UNSPEC_MOVSI_GOT
73 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
74 UNSPEC_FCTIWZ
75 UNSPEC_FRIM
76 UNSPEC_FRIN
77 UNSPEC_FRIP
78 UNSPEC_FRIZ
79 UNSPEC_LD_MPIC ; load_macho_picbase
80 UNSPEC_RELD_MPIC ; re-load_macho_picbase
81 UNSPEC_MPIC_CORRECT ; macho_correct_pic
82 UNSPEC_TLSGD
83 UNSPEC_TLSLD
84 UNSPEC_MOVESI_FROM_CR
85 UNSPEC_MOVESI_TO_CR
86 UNSPEC_TLSDTPREL
87 UNSPEC_TLSDTPRELHA
88 UNSPEC_TLSDTPRELLO
89 UNSPEC_TLSGOTDTPREL
90 UNSPEC_TLSTPREL
91 UNSPEC_TLSTPRELHA
92 UNSPEC_TLSTPRELLO
93 UNSPEC_TLSGOTTPREL
94 UNSPEC_TLSTLS
95 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
96 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
97 UNSPEC_STFIWX
98 UNSPEC_POPCNTB
99 UNSPEC_FRES
100 UNSPEC_SP_SET
101 UNSPEC_SP_TEST
102 UNSPEC_SYNC
103 UNSPEC_LWSYNC
104 UNSPEC_SYNC_OP
105 UNSPEC_ATOMIC
106 UNSPEC_CMPXCHG
107 UNSPEC_XCHG
108 UNSPEC_AND
109 UNSPEC_DLMZB
110 UNSPEC_DLMZB_CR
111 UNSPEC_DLMZB_STRLEN
112 UNSPEC_RSQRT
113 UNSPEC_TOCREL
114 UNSPEC_MACHOPIC_OFFSET
115 UNSPEC_BPERM
116 UNSPEC_COPYSIGN
117 UNSPEC_PARITY
118 UNSPEC_FCTIW
119 UNSPEC_FCTID
120 UNSPEC_LFIWAX
121 UNSPEC_LFIWZX
122 UNSPEC_FCTIWUZ
123 UNSPEC_GRP_END_NOP
124 UNSPEC_P8V_FMRGOW
125 UNSPEC_P8V_MTVSRWZ
126 UNSPEC_P8V_RELOAD_FROM_GPR
127 UNSPEC_P8V_MTVSRD
128 UNSPEC_P8V_XXPERMDI
129 UNSPEC_P8V_RELOAD_FROM_VSX
130 UNSPEC_ADDG6S
131 UNSPEC_CDTBCD
132 UNSPEC_CBCDTD
133 UNSPEC_DIVE
134 UNSPEC_DIVEO
135 UNSPEC_DIVEU
136 UNSPEC_DIVEUO
137 UNSPEC_UNPACK_128BIT
138 UNSPEC_PACK_128BIT
139 UNSPEC_LSQ
140 UNSPEC_FUSION_GPR
141 ])
143 ;;
144 ;; UNSPEC_VOLATILE usage
145 ;;
147 (define_c_enum "unspecv"
148 [UNSPECV_BLOCK
149 UNSPECV_LL ; load-locked
150 UNSPECV_SC ; store-conditional
151 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
152 UNSPECV_EH_RR ; eh_reg_restore
153 UNSPECV_ISYNC ; isync instruction
154 UNSPECV_MFTB ; move from time base
155 UNSPECV_NLGR ; non-local goto receiver
156 UNSPECV_MFFS ; Move from FPSCR
157 UNSPECV_MTFSF ; Move to FPSCR Fields
158 ])
160 \f
161 ;; Define an insn type attribute. This is used in function unit delay
162 ;; computations.
163 (define_attr "type"
164 "integer,two,three,
165 add,logical,shift,insert,
166 mul,halfmul,div,
167 exts,cntlz,popcnt,isel,
168 load,store,fpload,fpstore,vecload,vecstore,
169 cmp,
170 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
171 compare,
172 cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
173 fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
174 brinc,
175 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
176 vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
177 htm"
178 (const_string "integer"))
180 ;; What data size does this instruction work on?
181 ;; This is used for insert, mul.
182 (define_attr "size" "8,16,32,64" (const_string "32"))
184 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
185 ;; This is used for add, logical, shift, exts, mul.
186 (define_attr "dot" "no,yes" (const_string "no"))
188 ;; Does this instruction sign-extend its result?
189 ;; This is used for load insns.
190 (define_attr "sign_extend" "no,yes" (const_string "no"))
192 ;; Does this instruction use indexed (that is, reg+reg) addressing?
193 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
194 ;; it is automatically set based on that. If a load or store instruction
195 ;; has fewer than two operands it needs to set this attribute manually
196 ;; or the compiler will crash.
197 (define_attr "indexed" "no,yes"
198 (if_then_else (ior (match_operand 0 "indexed_address_mem")
199 (match_operand 1 "indexed_address_mem"))
200 (const_string "yes")
201 (const_string "no")))
203 ;; Does this instruction use update addressing?
204 ;; This is used for load and store insns. See the comments for "indexed".
205 (define_attr "update" "no,yes"
206 (if_then_else (ior (match_operand 0 "update_address_mem")
207 (match_operand 1 "update_address_mem"))
208 (const_string "yes")
209 (const_string "no")))
211 ;; Is this instruction using operands[2] as shift amount, and can that be a
212 ;; register?
213 ;; This is used for shift insns.
214 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
216 ;; Is this instruction using a shift amount from a register?
217 ;; This is used for shift insns.
218 (define_attr "var_shift" "no,yes"
219 (if_then_else (and (eq_attr "type" "shift")
220 (eq_attr "maybe_var_shift" "yes"))
221 (if_then_else (match_operand 2 "gpc_reg_operand")
222 (const_string "yes")
223 (const_string "no"))
224 (const_string "no")))
226 ;; Define floating point instruction sub-types for use with Xfpu.md
227 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
229 ;; Length (in bytes).
230 ; '(pc)' in the following doesn't include the instruction itself; it is
231 ; calculated as if the instruction had zero size.
232 (define_attr "length" ""
233 (if_then_else (eq_attr "type" "branch")
234 (if_then_else (and (ge (minus (match_dup 0) (pc))
235 (const_int -32768))
236 (lt (minus (match_dup 0) (pc))
237 (const_int 32764)))
238 (const_int 4)
239 (const_int 8))
240 (const_int 4)))
242 ;; Processor type -- this attribute must exactly match the processor_type
243 ;; enumeration in rs6000-opts.h.
244 (define_attr "cpu"
245 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
246 ppc750,ppc7400,ppc7450,
247 ppc403,ppc405,ppc440,ppc476,
248 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
249 power4,power5,power6,power7,power8,
250 rs64a,mpccore,cell,ppca2,titan"
251 (const (symbol_ref "rs6000_cpu_attr")))
254 ;; If this instruction is microcoded on the CELL processor
255 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
256 (define_attr "cell_micro" "not,conditional,always"
257 (if_then_else (ior (eq_attr "type" "compare")
258 (and (eq_attr "type" "shift,exts,mul")
259 (eq_attr "dot" "yes"))
260 (and (eq_attr "type" "load")
261 (eq_attr "sign_extend" "yes"))
262 (and (eq_attr "type" "shift")
263 (eq_attr "var_shift" "yes")))
264 (const_string "always")
265 (const_string "not")))
267 (automata_option "ndfa")
269 (include "rs64.md")
270 (include "mpc.md")
271 (include "40x.md")
272 (include "440.md")
273 (include "476.md")
274 (include "601.md")
275 (include "603.md")
276 (include "6xx.md")
277 (include "7xx.md")
278 (include "7450.md")
279 (include "8540.md")
280 (include "e300c2c3.md")
281 (include "e500mc.md")
282 (include "e500mc64.md")
283 (include "e5500.md")
284 (include "e6500.md")
285 (include "power4.md")
286 (include "power5.md")
287 (include "power6.md")
288 (include "power7.md")
289 (include "power8.md")
290 (include "cell.md")
291 (include "xfpu.md")
292 (include "a2.md")
293 (include "titan.md")
295 (include "predicates.md")
296 (include "constraints.md")
298 (include "darwin.md")
300 \f
301 ;; Mode iterators
303 ; This mode iterator allows :GPR to be used to indicate the allowable size
304 ; of whole values in GPRs.
305 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
307 ; Any supported integer mode.
308 (define_mode_iterator INT [QI HI SI DI TI PTI])
310 ; Any supported integer mode that fits in one register.
311 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
313 ; Everything we can extend QImode to.
314 (define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")])
316 ; Everything we can extend HImode to.
317 (define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")])
319 ; Everything we can extend SImode to.
320 (define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")])
322 ; QImode or HImode for small atomic ops
323 (define_mode_iterator QHI [QI HI])
325 ; HImode or SImode for sign extended fusion ops
326 (define_mode_iterator HSI [HI SI])
328 ; SImode or DImode, even if DImode doesn't fit in GPRs.
329 (define_mode_iterator SDI [SI DI])
331 ; The size of a pointer. Also, the size of the value that a record-condition
332 ; (one with a '.') will compare; and the size used for arithmetic carries.
333 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
335 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
336 ; PTImode is GPR only)
337 (define_mode_iterator TI2 [TI PTI])
339 ; Any hardware-supported floating-point mode
340 (define_mode_iterator FP [
341 (SF "TARGET_HARD_FLOAT
342 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
343 (DF "TARGET_HARD_FLOAT
344 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
345 (TF "!TARGET_IEEEQUAD
346 && TARGET_HARD_FLOAT
347 && (TARGET_FPRS || TARGET_E500_DOUBLE)
348 && TARGET_LONG_DOUBLE_128")
349 (DD "TARGET_DFP")
350 (TD "TARGET_DFP")])
352 ; Any fma capable floating-point mode.
353 (define_mode_iterator FMA_F [
354 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
355 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
356 || VECTOR_UNIT_VSX_P (DFmode)")
357 (V2SF "TARGET_PAIRED_FLOAT")
358 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
359 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
360 ])
362 ; Floating point move iterators to combine binary and decimal moves
363 (define_mode_iterator FMOVE32 [SF SD])
364 (define_mode_iterator FMOVE64 [DF DD])
365 (define_mode_iterator FMOVE64X [DI DF DD])
366 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
367 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
369 ; Iterators for 128 bit types for direct move
370 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
371 (V16QI "")
372 (V8HI "")
373 (V4SI "")
374 (V4SF "")
375 (V2DI "")
376 (V2DF "")
377 (V1TI "")])
379 ; Whether a floating point move is ok, don't allow SD without hardware FP
380 (define_mode_attr fmove_ok [(SF "")
381 (DF "")
382 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
383 (DD "")])
385 ; Convert REAL_VALUE to the appropriate bits
386 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
387 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
388 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
389 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
391 ; Definitions for load to 32-bit fpr register
392 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
393 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
394 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
395 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
397 ; Definitions for store from 32-bit fpr register
398 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
399 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
400 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
401 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
403 ; Definitions for 32-bit fpr direct move
404 (define_mode_attr f32_dm [(SF "wn") (SD "wh")])
406 ; These modes do not fit in integer registers in 32-bit mode.
407 ; but on e500v2, the gpr are 64 bit registers
408 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
410 ; Iterator for reciprocal estimate instructions
411 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
413 ; Iterator for just SF/DF
414 (define_mode_iterator SFDF [SF DF])
416 ; SF/DF suffix for traditional floating instructions
417 (define_mode_attr Ftrad [(SF "s") (DF "")])
419 ; SF/DF suffix for VSX instructions
420 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
422 ; SF/DF constraint for arithmetic on traditional floating point registers
423 (define_mode_attr Ff [(SF "f") (DF "d")])
425 ; SF/DF constraint for arithmetic on VSX registers
426 (define_mode_attr Fv [(SF "wy") (DF "ws")])
428 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
429 (define_mode_attr Fs [(SF "s") (DF "d")])
431 ; FRE/FRES support
432 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
433 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
435 ; Conditional returns.
436 (define_code_iterator any_return [return simple_return])
437 (define_code_attr return_pred [(return "direct_return ()")
438 (simple_return "1")])
439 (define_code_attr return_str [(return "") (simple_return "simple_")])
441 ; Signed/unsigned variants of ops.
442 (define_code_iterator any_extend [sign_extend zero_extend])
443 (define_code_attr u [(sign_extend "") (zero_extend "u")])
444 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
446 ; Various instructions that come in SI and DI forms.
447 ; A generic w/d attribute, for things like cmpw/cmpd.
448 (define_mode_attr wd [(QI "b")
449 (HI "h")
450 (SI "w")
451 (DI "d")
452 (V16QI "b")
453 (V8HI "h")
454 (V4SI "w")
455 (V2DI "d")])
457 ;; How many bits in this mode?
458 (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
460 ; DImode bits
461 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
463 ;; ISEL/ISEL64 target selection
464 (define_mode_attr sel [(SI "") (DI "64")])
466 ;; Bitmask for shift instructions
467 (define_mode_attr hH [(SI "h") (DI "H")])
469 ;; A mode twice the size of the given mode
470 (define_mode_attr dmode [(SI "di") (DI "ti")])
471 (define_mode_attr DMODE [(SI "DI") (DI "TI")])
473 ;; Suffix for reload patterns
474 (define_mode_attr ptrsize [(SI "32bit")
475 (DI "64bit")])
477 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
478 (DI "TARGET_64BIT")])
480 (define_mode_attr mptrsize [(SI "si")
481 (DI "di")])
483 (define_mode_attr ptrload [(SI "lwz")
484 (DI "ld")])
486 (define_mode_attr ptrm [(SI "m")
487 (DI "Y")])
489 (define_mode_attr rreg [(SF "f")
490 (DF "ws")
491 (TF "f")
492 (TD "f")
493 (V4SF "wf")
494 (V2DF "wd")])
496 (define_mode_attr rreg2 [(SF "f")
497 (DF "d")])
499 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
500 (DF "TARGET_FCFID")])
502 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
503 (DF "TARGET_E500_DOUBLE")])
505 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
506 (DF "TARGET_DOUBLE_FLOAT")])
508 ;; Mode iterator for logical operations on 128-bit types
509 (define_mode_iterator BOOL_128 [TI
510 PTI
511 (V16QI "TARGET_ALTIVEC")
512 (V8HI "TARGET_ALTIVEC")
513 (V4SI "TARGET_ALTIVEC")
514 (V4SF "TARGET_ALTIVEC")
515 (V2DI "TARGET_ALTIVEC")
516 (V2DF "TARGET_ALTIVEC")
517 (V1TI "TARGET_ALTIVEC")])
519 ;; For the GPRs we use 3 constraints for register outputs, two that are the
520 ;; same as the output register, and a third where the output register is an
521 ;; early clobber, so we don't have to deal with register overlaps. For the
522 ;; vector types, we prefer to use the vector registers. For TI mode, allow
523 ;; either.
525 ;; Mode attribute for boolean operation register constraints for output
526 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
527 (PTI "&r,r,r")
528 (V16QI "wa,v,&?r,?r,?r")
529 (V8HI "wa,v,&?r,?r,?r")
530 (V4SI "wa,v,&?r,?r,?r")
531 (V4SF "wa,v,&?r,?r,?r")
532 (V2DI "wa,v,&?r,?r,?r")
533 (V2DF "wa,v,&?r,?r,?r")
534 (V1TI "wa,v,&?r,?r,?r")])
536 ;; Mode attribute for boolean operation register constraints for operand1
537 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
538 (PTI "r,0,r")
539 (V16QI "wa,v,r,0,r")
540 (V8HI "wa,v,r,0,r")
541 (V4SI "wa,v,r,0,r")
542 (V4SF "wa,v,r,0,r")
543 (V2DI "wa,v,r,0,r")
544 (V2DF "wa,v,r,0,r")
545 (V1TI "wa,v,r,0,r")])
547 ;; Mode attribute for boolean operation register constraints for operand2
548 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
549 (PTI "r,r,0")
550 (V16QI "wa,v,r,r,0")
551 (V8HI "wa,v,r,r,0")
552 (V4SI "wa,v,r,r,0")
553 (V4SF "wa,v,r,r,0")
554 (V2DI "wa,v,r,r,0")
555 (V2DF "wa,v,r,r,0")
556 (V1TI "wa,v,r,r,0")])
558 ;; Mode attribute for boolean operation register constraints for operand1
559 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
560 ;; is used for operand1 or operand2
561 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
562 (PTI "r,0,0")
563 (V16QI "wa,v,r,0,0")
564 (V8HI "wa,v,r,0,0")
565 (V4SI "wa,v,r,0,0")
566 (V4SF "wa,v,r,0,0")
567 (V2DI "wa,v,r,0,0")
568 (V2DF "wa,v,r,0,0")
569 (V1TI "wa,v,r,0,0")])
570 \f
571 ;; Start with fixed-point load and store insns. Here we put only the more
572 ;; complex forms. Basic data transfer is done later.
574 (define_insn "zero_extendqi<mode>2"
575 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
576 (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
577 ""
578 "@
579 lbz%U1%X1 %0,%1
580 rlwinm %0,%1,0,0xff"
581 [(set_attr "type" "load,shift")])
583 (define_insn_and_split "*zero_extendqi<mode>2_dot"
584 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
585 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
586 (const_int 0)))
587 (clobber (match_scratch:EXTQI 0 "=r,r"))]
588 "rs6000_gen_cell_microcode"
589 "@
590 andi. %0,%1,0xff
591 #"
592 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
593 [(set (match_dup 0)
594 (zero_extend:EXTQI (match_dup 1)))
595 (set (match_dup 2)
596 (compare:CC (match_dup 0)
597 (const_int 0)))]
598 ""
599 [(set_attr "type" "logical")
600 (set_attr "dot" "yes")
601 (set_attr "length" "4,8")])
603 (define_insn_and_split "*zero_extendqi<mode>2_dot2"
604 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
605 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
606 (const_int 0)))
607 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
608 (zero_extend:EXTQI (match_dup 1)))]
609 "rs6000_gen_cell_microcode"
610 "@
611 andi. %0,%1,0xff
612 #"
613 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
614 [(set (match_dup 0)
615 (zero_extend:EXTQI (match_dup 1)))
616 (set (match_dup 2)
617 (compare:CC (match_dup 0)
618 (const_int 0)))]
619 ""
620 [(set_attr "type" "logical")
621 (set_attr "dot" "yes")
622 (set_attr "length" "4,8")])
625 (define_insn "zero_extendhi<mode>2"
626 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
627 (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
628 ""
629 "@
630 lhz%U1%X1 %0,%1
631 rlwinm %0,%1,0,0xffff"
632 [(set_attr "type" "load,shift")])
634 (define_insn_and_split "*zero_extendhi<mode>2_dot"
635 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
636 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
637 (const_int 0)))
638 (clobber (match_scratch:EXTHI 0 "=r,r"))]
639 "rs6000_gen_cell_microcode"
640 "@
641 andi. %0,%1,0xffff
642 #"
643 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
644 [(set (match_dup 0)
645 (zero_extend:EXTHI (match_dup 1)))
646 (set (match_dup 2)
647 (compare:CC (match_dup 0)
648 (const_int 0)))]
649 ""
650 [(set_attr "type" "logical")
651 (set_attr "dot" "yes")
652 (set_attr "length" "4,8")])
654 (define_insn_and_split "*zero_extendhi<mode>2_dot2"
655 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
656 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
657 (const_int 0)))
658 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
659 (zero_extend:EXTHI (match_dup 1)))]
660 "rs6000_gen_cell_microcode"
661 "@
662 andi. %0,%1,0xffff
663 #"
664 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
665 [(set (match_dup 0)
666 (zero_extend:EXTHI (match_dup 1)))
667 (set (match_dup 2)
668 (compare:CC (match_dup 0)
669 (const_int 0)))]
670 ""
671 [(set_attr "type" "logical")
672 (set_attr "dot" "yes")
673 (set_attr "length" "4,8")])
676 (define_insn "zero_extendsi<mode>2"
677 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
678 (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
679 ""
680 "@
681 lwz%U1%X1 %0,%1
682 rldicl %0,%1,0,32
683 mtvsrwz %x0,%1
684 lfiwzx %0,%y1
685 lxsiwzx %x0,%y1"
686 [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
688 (define_insn_and_split "*zero_extendsi<mode>2_dot"
689 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
690 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
691 (const_int 0)))
692 (clobber (match_scratch:EXTSI 0 "=r,r"))]
693 "rs6000_gen_cell_microcode"
694 "@
695 rldicl. %0,%1,0,32
696 #"
697 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
698 [(set (match_dup 0)
699 (zero_extend:DI (match_dup 1)))
700 (set (match_dup 2)
701 (compare:CC (match_dup 0)
702 (const_int 0)))]
703 ""
704 [(set_attr "type" "shift")
705 (set_attr "dot" "yes")
706 (set_attr "length" "4,8")])
708 (define_insn_and_split "*zero_extendsi<mode>2_dot2"
709 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
710 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
711 (const_int 0)))
712 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
713 (zero_extend:EXTSI (match_dup 1)))]
714 "rs6000_gen_cell_microcode"
715 "@
716 rldicl. %0,%1,0,32
717 #"
718 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
719 [(set (match_dup 0)
720 (zero_extend:EXTSI (match_dup 1)))
721 (set (match_dup 2)
722 (compare:CC (match_dup 0)
723 (const_int 0)))]
724 ""
725 [(set_attr "type" "shift")
726 (set_attr "dot" "yes")
727 (set_attr "length" "4,8")])
730 (define_insn "extendqi<mode>2"
731 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
732 (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
733 ""
734 "extsb %0,%1"
735 [(set_attr "type" "exts")])
737 (define_insn_and_split "*extendqi<mode>2_dot"
738 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
739 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
740 (const_int 0)))
741 (clobber (match_scratch:EXTQI 0 "=r,r"))]
742 "rs6000_gen_cell_microcode"
743 "@
744 extsb. %0,%1
745 #"
746 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
747 [(set (match_dup 0)
748 (sign_extend:EXTQI (match_dup 1)))
749 (set (match_dup 2)
750 (compare:CC (match_dup 0)
751 (const_int 0)))]
752 ""
753 [(set_attr "type" "exts")
754 (set_attr "dot" "yes")
755 (set_attr "length" "4,8")])
757 (define_insn_and_split "*extendqi<mode>2_dot2"
758 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
759 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
760 (const_int 0)))
761 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
762 (sign_extend:EXTQI (match_dup 1)))]
763 "rs6000_gen_cell_microcode"
764 "@
765 extsb. %0,%1
766 #"
767 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
768 [(set (match_dup 0)
769 (sign_extend:EXTQI (match_dup 1)))
770 (set (match_dup 2)
771 (compare:CC (match_dup 0)
772 (const_int 0)))]
773 ""
774 [(set_attr "type" "exts")
775 (set_attr "dot" "yes")
776 (set_attr "length" "4,8")])
779 (define_expand "extendhi<mode>2"
780 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "")
781 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "")))]
782 ""
783 "")
785 (define_insn "*extendhi<mode>2"
786 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
787 (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
788 "rs6000_gen_cell_microcode"
789 "@
790 lha%U1%X1 %0,%1
791 extsh %0,%1"
792 [(set_attr "type" "load,exts")
793 (set_attr "sign_extend" "yes")])
795 (define_insn "*extendhi<mode>2_noload"
796 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
797 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
798 "!rs6000_gen_cell_microcode"
799 "extsh %0,%1"
800 [(set_attr "type" "exts")])
802 (define_insn_and_split "*extendhi<mode>2_dot"
803 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
804 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
805 (const_int 0)))
806 (clobber (match_scratch:EXTHI 0 "=r,r"))]
807 "rs6000_gen_cell_microcode"
808 "@
809 extsh. %0,%1
810 #"
811 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
812 [(set (match_dup 0)
813 (sign_extend:EXTHI (match_dup 1)))
814 (set (match_dup 2)
815 (compare:CC (match_dup 0)
816 (const_int 0)))]
817 ""
818 [(set_attr "type" "exts")
819 (set_attr "dot" "yes")
820 (set_attr "length" "4,8")])
822 (define_insn_and_split "*extendhi<mode>2_dot2"
823 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
824 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
825 (const_int 0)))
826 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
827 (sign_extend:EXTHI (match_dup 1)))]
828 "rs6000_gen_cell_microcode"
829 "@
830 extsh. %0,%1
831 #"
832 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
833 [(set (match_dup 0)
834 (sign_extend:EXTHI (match_dup 1)))
835 (set (match_dup 2)
836 (compare:CC (match_dup 0)
837 (const_int 0)))]
838 ""
839 [(set_attr "type" "exts")
840 (set_attr "dot" "yes")
841 (set_attr "length" "4,8")])
844 (define_insn "extendsi<mode>2"
845 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
846 (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
847 ""
848 "@
849 lwa%U1%X1 %0,%1
850 extsw %0,%1
851 mtvsrwa %x0,%1
852 lfiwax %0,%y1
853 lxsiwax %x0,%y1"
854 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
855 (set_attr "sign_extend" "yes")])
857 (define_insn_and_split "*extendsi<mode>2_dot"
858 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
859 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
860 (const_int 0)))
861 (clobber (match_scratch:EXTSI 0 "=r,r"))]
862 "rs6000_gen_cell_microcode"
863 "@
864 extsw. %0,%1
865 #"
866 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
867 [(set (match_dup 0)
868 (sign_extend:EXTSI (match_dup 1)))
869 (set (match_dup 2)
870 (compare:CC (match_dup 0)
871 (const_int 0)))]
872 ""
873 [(set_attr "type" "exts")
874 (set_attr "dot" "yes")
875 (set_attr "length" "4,8")])
877 (define_insn_and_split "*extendsi<mode>2_dot2"
878 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
879 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
880 (const_int 0)))
881 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
882 (sign_extend:EXTSI (match_dup 1)))]
883 "rs6000_gen_cell_microcode"
884 "@
885 extsw. %0,%1
886 #"
887 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
888 [(set (match_dup 0)
889 (sign_extend:EXTSI (match_dup 1)))
890 (set (match_dup 2)
891 (compare:CC (match_dup 0)
892 (const_int 0)))]
893 ""
894 [(set_attr "type" "exts")
895 (set_attr "dot" "yes")
896 (set_attr "length" "4,8")])
897 \f
898 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
900 (define_insn "*macchwc"
901 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
902 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
903 (match_operand:SI 2 "gpc_reg_operand" "r")
904 (const_int 16))
905 (sign_extend:SI
906 (match_operand:HI 1 "gpc_reg_operand" "r")))
907 (match_operand:SI 4 "gpc_reg_operand" "0"))
908 (const_int 0)))
909 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
910 (plus:SI (mult:SI (ashiftrt:SI
911 (match_dup 2)
912 (const_int 16))
913 (sign_extend:SI
914 (match_dup 1)))
915 (match_dup 4)))]
916 "TARGET_MULHW"
917 "macchw. %0,%1,%2"
918 [(set_attr "type" "halfmul")])
920 (define_insn "*macchw"
921 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
922 (plus:SI (mult:SI (ashiftrt:SI
923 (match_operand:SI 2 "gpc_reg_operand" "r")
924 (const_int 16))
925 (sign_extend:SI
926 (match_operand:HI 1 "gpc_reg_operand" "r")))
927 (match_operand:SI 3 "gpc_reg_operand" "0")))]
928 "TARGET_MULHW"
929 "macchw %0,%1,%2"
930 [(set_attr "type" "halfmul")])
932 (define_insn "*macchwuc"
933 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
934 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
935 (match_operand:SI 2 "gpc_reg_operand" "r")
936 (const_int 16))
937 (zero_extend:SI
938 (match_operand:HI 1 "gpc_reg_operand" "r")))
939 (match_operand:SI 4 "gpc_reg_operand" "0"))
940 (const_int 0)))
941 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
942 (plus:SI (mult:SI (lshiftrt:SI
943 (match_dup 2)
944 (const_int 16))
945 (zero_extend:SI
946 (match_dup 1)))
947 (match_dup 4)))]
948 "TARGET_MULHW"
949 "macchwu. %0,%1,%2"
950 [(set_attr "type" "halfmul")])
952 (define_insn "*macchwu"
953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
954 (plus:SI (mult:SI (lshiftrt:SI
955 (match_operand:SI 2 "gpc_reg_operand" "r")
956 (const_int 16))
957 (zero_extend:SI
958 (match_operand:HI 1 "gpc_reg_operand" "r")))
959 (match_operand:SI 3 "gpc_reg_operand" "0")))]
960 "TARGET_MULHW"
961 "macchwu %0,%1,%2"
962 [(set_attr "type" "halfmul")])
964 (define_insn "*machhwc"
965 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
966 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
967 (match_operand:SI 1 "gpc_reg_operand" "%r")
968 (const_int 16))
969 (ashiftrt:SI
970 (match_operand:SI 2 "gpc_reg_operand" "r")
971 (const_int 16)))
972 (match_operand:SI 4 "gpc_reg_operand" "0"))
973 (const_int 0)))
974 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
975 (plus:SI (mult:SI (ashiftrt:SI
976 (match_dup 1)
977 (const_int 16))
978 (ashiftrt:SI
979 (match_dup 2)
980 (const_int 16)))
981 (match_dup 4)))]
982 "TARGET_MULHW"
983 "machhw. %0,%1,%2"
984 [(set_attr "type" "halfmul")])
986 (define_insn "*machhw"
987 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
988 (plus:SI (mult:SI (ashiftrt:SI
989 (match_operand:SI 1 "gpc_reg_operand" "%r")
990 (const_int 16))
991 (ashiftrt:SI
992 (match_operand:SI 2 "gpc_reg_operand" "r")
993 (const_int 16)))
994 (match_operand:SI 3 "gpc_reg_operand" "0")))]
995 "TARGET_MULHW"
996 "machhw %0,%1,%2"
997 [(set_attr "type" "halfmul")])
999 (define_insn "*machhwuc"
1000 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1001 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1002 (match_operand:SI 1 "gpc_reg_operand" "%r")
1003 (const_int 16))
1004 (lshiftrt:SI
1005 (match_operand:SI 2 "gpc_reg_operand" "r")
1006 (const_int 16)))
1007 (match_operand:SI 4 "gpc_reg_operand" "0"))
1008 (const_int 0)))
1009 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1010 (plus:SI (mult:SI (lshiftrt:SI
1011 (match_dup 1)
1012 (const_int 16))
1013 (lshiftrt:SI
1014 (match_dup 2)
1015 (const_int 16)))
1016 (match_dup 4)))]
1017 "TARGET_MULHW"
1018 "machhwu. %0,%1,%2"
1019 [(set_attr "type" "halfmul")])
1021 (define_insn "*machhwu"
1022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1023 (plus:SI (mult:SI (lshiftrt:SI
1024 (match_operand:SI 1 "gpc_reg_operand" "%r")
1025 (const_int 16))
1026 (lshiftrt:SI
1027 (match_operand:SI 2 "gpc_reg_operand" "r")
1028 (const_int 16)))
1029 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1030 "TARGET_MULHW"
1031 "machhwu %0,%1,%2"
1032 [(set_attr "type" "halfmul")])
1034 (define_insn "*maclhwc"
1035 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1036 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1037 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1038 (sign_extend:SI
1039 (match_operand:HI 2 "gpc_reg_operand" "r")))
1040 (match_operand:SI 4 "gpc_reg_operand" "0"))
1041 (const_int 0)))
1042 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1043 (plus:SI (mult:SI (sign_extend:SI
1044 (match_dup 1))
1045 (sign_extend:SI
1046 (match_dup 2)))
1047 (match_dup 4)))]
1048 "TARGET_MULHW"
1049 "maclhw. %0,%1,%2"
1050 [(set_attr "type" "halfmul")])
1052 (define_insn "*maclhw"
1053 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1054 (plus:SI (mult:SI (sign_extend:SI
1055 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1056 (sign_extend:SI
1057 (match_operand:HI 2 "gpc_reg_operand" "r")))
1058 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1059 "TARGET_MULHW"
1060 "maclhw %0,%1,%2"
1061 [(set_attr "type" "halfmul")])
1063 (define_insn "*maclhwuc"
1064 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1065 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1066 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1067 (zero_extend:SI
1068 (match_operand:HI 2 "gpc_reg_operand" "r")))
1069 (match_operand:SI 4 "gpc_reg_operand" "0"))
1070 (const_int 0)))
1071 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1072 (plus:SI (mult:SI (zero_extend:SI
1073 (match_dup 1))
1074 (zero_extend:SI
1075 (match_dup 2)))
1076 (match_dup 4)))]
1077 "TARGET_MULHW"
1078 "maclhwu. %0,%1,%2"
1079 [(set_attr "type" "halfmul")])
1081 (define_insn "*maclhwu"
1082 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1083 (plus:SI (mult:SI (zero_extend:SI
1084 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1085 (zero_extend:SI
1086 (match_operand:HI 2 "gpc_reg_operand" "r")))
1087 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1088 "TARGET_MULHW"
1089 "maclhwu %0,%1,%2"
1090 [(set_attr "type" "halfmul")])
1092 (define_insn "*nmacchwc"
1093 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1094 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1095 (mult:SI (ashiftrt:SI
1096 (match_operand:SI 2 "gpc_reg_operand" "r")
1097 (const_int 16))
1098 (sign_extend:SI
1099 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1100 (const_int 0)))
1101 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1102 (minus:SI (match_dup 4)
1103 (mult:SI (ashiftrt:SI
1104 (match_dup 2)
1105 (const_int 16))
1106 (sign_extend:SI
1107 (match_dup 1)))))]
1108 "TARGET_MULHW"
1109 "nmacchw. %0,%1,%2"
1110 [(set_attr "type" "halfmul")])
1112 (define_insn "*nmacchw"
1113 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1114 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1115 (mult:SI (ashiftrt:SI
1116 (match_operand:SI 2 "gpc_reg_operand" "r")
1117 (const_int 16))
1118 (sign_extend:SI
1119 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1120 "TARGET_MULHW"
1121 "nmacchw %0,%1,%2"
1122 [(set_attr "type" "halfmul")])
1124 (define_insn "*nmachhwc"
1125 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1126 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1127 (mult:SI (ashiftrt:SI
1128 (match_operand:SI 1 "gpc_reg_operand" "%r")
1129 (const_int 16))
1130 (ashiftrt:SI
1131 (match_operand:SI 2 "gpc_reg_operand" "r")
1132 (const_int 16))))
1133 (const_int 0)))
1134 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1135 (minus:SI (match_dup 4)
1136 (mult:SI (ashiftrt:SI
1137 (match_dup 1)
1138 (const_int 16))
1139 (ashiftrt:SI
1140 (match_dup 2)
1141 (const_int 16)))))]
1142 "TARGET_MULHW"
1143 "nmachhw. %0,%1,%2"
1144 [(set_attr "type" "halfmul")])
1146 (define_insn "*nmachhw"
1147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1148 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1149 (mult:SI (ashiftrt:SI
1150 (match_operand:SI 1 "gpc_reg_operand" "%r")
1151 (const_int 16))
1152 (ashiftrt:SI
1153 (match_operand:SI 2 "gpc_reg_operand" "r")
1154 (const_int 16)))))]
1155 "TARGET_MULHW"
1156 "nmachhw %0,%1,%2"
1157 [(set_attr "type" "halfmul")])
1159 (define_insn "*nmaclhwc"
1160 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1161 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1162 (mult:SI (sign_extend:SI
1163 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1164 (sign_extend:SI
1165 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1166 (const_int 0)))
1167 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1168 (minus:SI (match_dup 4)
1169 (mult:SI (sign_extend:SI
1170 (match_dup 1))
1171 (sign_extend:SI
1172 (match_dup 2)))))]
1173 "TARGET_MULHW"
1174 "nmaclhw. %0,%1,%2"
1175 [(set_attr "type" "halfmul")])
1177 (define_insn "*nmaclhw"
1178 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1179 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1180 (mult:SI (sign_extend:SI
1181 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1182 (sign_extend:SI
1183 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1184 "TARGET_MULHW"
1185 "nmaclhw %0,%1,%2"
1186 [(set_attr "type" "halfmul")])
1188 (define_insn "*mulchwc"
1189 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1190 (compare:CC (mult:SI (ashiftrt:SI
1191 (match_operand:SI 2 "gpc_reg_operand" "r")
1192 (const_int 16))
1193 (sign_extend:SI
1194 (match_operand:HI 1 "gpc_reg_operand" "r")))
1195 (const_int 0)))
1196 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1197 (mult:SI (ashiftrt:SI
1198 (match_dup 2)
1199 (const_int 16))
1200 (sign_extend:SI
1201 (match_dup 1))))]
1202 "TARGET_MULHW"
1203 "mulchw. %0,%1,%2"
1204 [(set_attr "type" "halfmul")])
1206 (define_insn "*mulchw"
1207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1208 (mult:SI (ashiftrt:SI
1209 (match_operand:SI 2 "gpc_reg_operand" "r")
1210 (const_int 16))
1211 (sign_extend:SI
1212 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1213 "TARGET_MULHW"
1214 "mulchw %0,%1,%2"
1215 [(set_attr "type" "halfmul")])
1217 (define_insn "*mulchwuc"
1218 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1219 (compare:CC (mult:SI (lshiftrt:SI
1220 (match_operand:SI 2 "gpc_reg_operand" "r")
1221 (const_int 16))
1222 (zero_extend:SI
1223 (match_operand:HI 1 "gpc_reg_operand" "r")))
1224 (const_int 0)))
1225 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1226 (mult:SI (lshiftrt:SI
1227 (match_dup 2)
1228 (const_int 16))
1229 (zero_extend:SI
1230 (match_dup 1))))]
1231 "TARGET_MULHW"
1232 "mulchwu. %0,%1,%2"
1233 [(set_attr "type" "halfmul")])
1235 (define_insn "*mulchwu"
1236 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1237 (mult:SI (lshiftrt:SI
1238 (match_operand:SI 2 "gpc_reg_operand" "r")
1239 (const_int 16))
1240 (zero_extend:SI
1241 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1242 "TARGET_MULHW"
1243 "mulchwu %0,%1,%2"
1244 [(set_attr "type" "halfmul")])
1246 (define_insn "*mulhhwc"
1247 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1248 (compare:CC (mult:SI (ashiftrt:SI
1249 (match_operand:SI 1 "gpc_reg_operand" "%r")
1250 (const_int 16))
1251 (ashiftrt:SI
1252 (match_operand:SI 2 "gpc_reg_operand" "r")
1253 (const_int 16)))
1254 (const_int 0)))
1255 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1256 (mult:SI (ashiftrt:SI
1257 (match_dup 1)
1258 (const_int 16))
1259 (ashiftrt:SI
1260 (match_dup 2)
1261 (const_int 16))))]
1262 "TARGET_MULHW"
1263 "mulhhw. %0,%1,%2"
1264 [(set_attr "type" "halfmul")])
1266 (define_insn "*mulhhw"
1267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1268 (mult:SI (ashiftrt:SI
1269 (match_operand:SI 1 "gpc_reg_operand" "%r")
1270 (const_int 16))
1271 (ashiftrt:SI
1272 (match_operand:SI 2 "gpc_reg_operand" "r")
1273 (const_int 16))))]
1274 "TARGET_MULHW"
1275 "mulhhw %0,%1,%2"
1276 [(set_attr "type" "halfmul")])
1278 (define_insn "*mulhhwuc"
1279 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1280 (compare:CC (mult:SI (lshiftrt:SI
1281 (match_operand:SI 1 "gpc_reg_operand" "%r")
1282 (const_int 16))
1283 (lshiftrt:SI
1284 (match_operand:SI 2 "gpc_reg_operand" "r")
1285 (const_int 16)))
1286 (const_int 0)))
1287 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1288 (mult:SI (lshiftrt:SI
1289 (match_dup 1)
1290 (const_int 16))
1291 (lshiftrt:SI
1292 (match_dup 2)
1293 (const_int 16))))]
1294 "TARGET_MULHW"
1295 "mulhhwu. %0,%1,%2"
1296 [(set_attr "type" "halfmul")])
1298 (define_insn "*mulhhwu"
1299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1300 (mult:SI (lshiftrt:SI
1301 (match_operand:SI 1 "gpc_reg_operand" "%r")
1302 (const_int 16))
1303 (lshiftrt:SI
1304 (match_operand:SI 2 "gpc_reg_operand" "r")
1305 (const_int 16))))]
1306 "TARGET_MULHW"
1307 "mulhhwu %0,%1,%2"
1308 [(set_attr "type" "halfmul")])
1310 (define_insn "*mullhwc"
1311 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1312 (compare:CC (mult:SI (sign_extend:SI
1313 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1314 (sign_extend:SI
1315 (match_operand:HI 2 "gpc_reg_operand" "r")))
1316 (const_int 0)))
1317 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1318 (mult:SI (sign_extend:SI
1319 (match_dup 1))
1320 (sign_extend:SI
1321 (match_dup 2))))]
1322 "TARGET_MULHW"
1323 "mullhw. %0,%1,%2"
1324 [(set_attr "type" "halfmul")])
1326 (define_insn "*mullhw"
1327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1328 (mult:SI (sign_extend:SI
1329 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1330 (sign_extend:SI
1331 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1332 "TARGET_MULHW"
1333 "mullhw %0,%1,%2"
1334 [(set_attr "type" "halfmul")])
1336 (define_insn "*mullhwuc"
1337 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1338 (compare:CC (mult:SI (zero_extend:SI
1339 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1340 (zero_extend:SI
1341 (match_operand:HI 2 "gpc_reg_operand" "r")))
1342 (const_int 0)))
1343 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1344 (mult:SI (zero_extend:SI
1345 (match_dup 1))
1346 (zero_extend:SI
1347 (match_dup 2))))]
1348 "TARGET_MULHW"
1349 "mullhwu. %0,%1,%2"
1350 [(set_attr "type" "halfmul")])
1352 (define_insn "*mullhwu"
1353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1354 (mult:SI (zero_extend:SI
1355 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1356 (zero_extend:SI
1357 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1358 "TARGET_MULHW"
1359 "mullhwu %0,%1,%2"
1360 [(set_attr "type" "halfmul")])
1361 \f
1362 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1363 (define_insn "dlmzb"
1364 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1365 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1366 (match_operand:SI 2 "gpc_reg_operand" "r")]
1367 UNSPEC_DLMZB_CR))
1368 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1369 (unspec:SI [(match_dup 1)
1370 (match_dup 2)]
1371 UNSPEC_DLMZB))]
1372 "TARGET_DLMZB"
1373 "dlmzb. %0,%1,%2")
1375 (define_expand "strlensi"
1376 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1377 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1378 (match_operand:QI 2 "const_int_operand" "")
1379 (match_operand 3 "const_int_operand" "")]
1380 UNSPEC_DLMZB_STRLEN))
1381 (clobber (match_scratch:CC 4 "=x"))]
1382 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1383 {
1384 rtx result = operands[0];
1385 rtx src = operands[1];
1386 rtx search_char = operands[2];
1387 rtx align = operands[3];
1388 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1389 rtx loop_label, end_label, mem, cr0, cond;
1390 if (search_char != const0_rtx
1391 || GET_CODE (align) != CONST_INT
1392 || INTVAL (align) < 8)
1393 FAIL;
1394 word1 = gen_reg_rtx (SImode);
1395 word2 = gen_reg_rtx (SImode);
1396 scratch_dlmzb = gen_reg_rtx (SImode);
1397 scratch_string = gen_reg_rtx (Pmode);
1398 loop_label = gen_label_rtx ();
1399 end_label = gen_label_rtx ();
1400 addr = force_reg (Pmode, XEXP (src, 0));
1401 emit_move_insn (scratch_string, addr);
1402 emit_label (loop_label);
1403 mem = change_address (src, SImode, scratch_string);
1404 emit_move_insn (word1, mem);
1405 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1406 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1407 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1408 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1409 emit_jump_insn (gen_rtx_SET (VOIDmode,
1410 pc_rtx,
1411 gen_rtx_IF_THEN_ELSE (VOIDmode,
1412 cond,
1413 gen_rtx_LABEL_REF
1414 (VOIDmode,
1415 end_label),
1416 pc_rtx)));
1417 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1418 emit_jump_insn (gen_rtx_SET (VOIDmode,
1419 pc_rtx,
1420 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1421 emit_barrier ();
1422 emit_label (end_label);
1423 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1424 emit_insn (gen_subsi3 (result, scratch_string, addr));
1425 emit_insn (gen_subsi3 (result, result, const1_rtx));
1426 DONE;
1427 })
1428 \f
1429 ;; Fixed-point arithmetic insns.
1431 (define_expand "add<mode>3"
1432 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1433 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1434 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1435 ""
1436 {
1437 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1438 {
1439 if (non_short_cint_operand (operands[2], DImode))
1440 FAIL;
1441 }
1442 else if (GET_CODE (operands[2]) == CONST_INT
1443 && ! add_operand (operands[2], <MODE>mode))
1444 {
1445 rtx tmp = ((!can_create_pseudo_p ()
1446 || rtx_equal_p (operands[0], operands[1]))
1447 ? operands[0] : gen_reg_rtx (<MODE>mode));
1449 HOST_WIDE_INT val = INTVAL (operands[2]);
1450 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1451 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1453 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1454 FAIL;
1456 /* The ordering here is important for the prolog expander.
1457 When space is allocated from the stack, adding 'low' first may
1458 produce a temporary deallocation (which would be bad). */
1459 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1460 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1461 DONE;
1462 }
1463 })
1465 ;; Discourage ai/addic because of carry but provide it in an alternative
1466 ;; allowing register zero as source.
1467 (define_insn "*add<mode>3_internal1"
1468 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1469 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1470 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1471 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1472 "@
1473 add %0,%1,%2
1474 addi %0,%1,%2
1475 addic %0,%1,%2
1476 addis %0,%1,%v2"
1477 [(set_attr "type" "add")])
1479 (define_insn "addsi3_high"
1480 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1481 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1482 (high:SI (match_operand 2 "" ""))))]
1483 "TARGET_MACHO && !TARGET_64BIT"
1484 "addis %0,%1,ha16(%2)"
1485 [(set_attr "type" "add")])
1487 (define_insn "*add<mode>3_internal2"
1488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1489 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1490 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1491 (const_int 0)))
1492 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1493 ""
1494 "@
1495 add. %3,%1,%2
1496 addic. %3,%1,%2
1497 #
1498 #"
1499 [(set_attr "type" "add,compare,compare,compare")
1500 (set_attr "dot" "yes")
1501 (set_attr "length" "4,4,8,8")])
1503 (define_split
1504 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1505 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1506 (match_operand:GPR 2 "reg_or_short_operand" ""))
1507 (const_int 0)))
1508 (clobber (match_scratch:GPR 3 ""))]
1509 "reload_completed"
1510 [(set (match_dup 3)
1511 (plus:GPR (match_dup 1)
1512 (match_dup 2)))
1513 (set (match_dup 0)
1514 (compare:CC (match_dup 3)
1515 (const_int 0)))]
1516 "")
1518 (define_insn "*add<mode>3_internal3"
1519 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1520 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1521 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1522 (const_int 0)))
1523 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1524 (plus:P (match_dup 1)
1525 (match_dup 2)))]
1526 ""
1527 "@
1528 add. %0,%1,%2
1529 addic. %0,%1,%2
1530 #
1531 #"
1532 [(set_attr "type" "add,compare,compare,compare")
1533 (set_attr "dot" "yes")
1534 (set_attr "length" "4,4,8,8")])
1536 (define_split
1537 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1538 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1539 (match_operand:P 2 "reg_or_short_operand" ""))
1540 (const_int 0)))
1541 (set (match_operand:P 0 "gpc_reg_operand" "")
1542 (plus:P (match_dup 1) (match_dup 2)))]
1543 "reload_completed"
1544 [(set (match_dup 0)
1545 (plus:P (match_dup 1)
1546 (match_dup 2)))
1547 (set (match_dup 3)
1548 (compare:CC (match_dup 0)
1549 (const_int 0)))]
1550 "")
1552 ;; Split an add that we can't do in one insn into two insns, each of which
1553 ;; does one 16-bit part. This is used by combine. Note that the low-order
1554 ;; add should be last in case the result gets used in an address.
1556 (define_split
1557 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1558 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1559 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1560 ""
1561 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1562 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1563 {
1564 HOST_WIDE_INT val = INTVAL (operands[2]);
1565 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1566 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1568 operands[4] = GEN_INT (low);
1569 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1570 operands[3] = GEN_INT (rest);
1571 else if (can_create_pseudo_p ())
1572 {
1573 operands[3] = gen_reg_rtx (DImode);
1574 emit_move_insn (operands[3], operands[2]);
1575 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1576 DONE;
1577 }
1578 else
1579 FAIL;
1580 })
1582 (define_expand "one_cmpl<mode>2"
1583 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1584 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1585 ""
1586 {
1587 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1588 {
1589 rs6000_split_logical (operands, NOT, false, false, false);
1590 DONE;
1591 }
1592 })
1594 (define_insn "*one_cmpl<mode>2"
1595 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1596 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1597 ""
1598 "not %0,%1")
1600 (define_insn_and_split "*one_cmpl<mode>2_dot"
1601 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1602 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1603 (const_int 0)))
1604 (clobber (match_scratch:GPR 0 "=r,r"))]
1605 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1606 "@
1607 not. %0,%1
1608 #"
1609 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1610 [(set (match_dup 0)
1611 (not:GPR (match_dup 1)))
1612 (set (match_dup 2)
1613 (compare:CC (match_dup 0)
1614 (const_int 0)))]
1615 ""
1616 [(set_attr "type" "logical")
1617 (set_attr "dot" "yes")
1618 (set_attr "length" "4,8")])
1620 (define_insn_and_split "*one_cmpl<mode>2_dot2"
1621 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1622 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1623 (const_int 0)))
1624 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1625 (not:GPR (match_dup 1)))]
1626 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1627 "@
1628 not. %0,%1
1629 #"
1630 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1631 [(set (match_dup 0)
1632 (not:GPR (match_dup 1)))
1633 (set (match_dup 2)
1634 (compare:CC (match_dup 0)
1635 (const_int 0)))]
1636 ""
1637 [(set_attr "type" "logical")
1638 (set_attr "dot" "yes")
1639 (set_attr "length" "4,8")])
1642 (define_insn ""
1643 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1644 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1645 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1646 ""
1647 "@
1648 subf %0,%2,%1
1649 subfic %0,%2,%1"
1650 [(set_attr "type" "add")])
1652 (define_insn ""
1653 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1654 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1655 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1656 (const_int 0)))
1657 (clobber (match_scratch:P 3 "=r,r"))]
1658 ""
1659 "@
1660 subf. %3,%2,%1
1661 #"
1662 [(set_attr "type" "add")
1663 (set_attr "dot" "yes")
1664 (set_attr "length" "4,8")])
1666 (define_split
1667 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1668 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1669 (match_operand:P 2 "gpc_reg_operand" ""))
1670 (const_int 0)))
1671 (clobber (match_scratch:P 3 ""))]
1672 "reload_completed"
1673 [(set (match_dup 3)
1674 (minus:P (match_dup 1)
1675 (match_dup 2)))
1676 (set (match_dup 0)
1677 (compare:CC (match_dup 3)
1678 (const_int 0)))]
1679 "")
1681 (define_insn ""
1682 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1683 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1684 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1685 (const_int 0)))
1686 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1687 (minus:P (match_dup 1)
1688 (match_dup 2)))]
1689 ""
1690 "@
1691 subf. %0,%2,%1
1692 #"
1693 [(set_attr "type" "add")
1694 (set_attr "dot" "yes")
1695 (set_attr "length" "4,8")])
1697 (define_split
1698 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1699 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1700 (match_operand:P 2 "gpc_reg_operand" ""))
1701 (const_int 0)))
1702 (set (match_operand:P 0 "gpc_reg_operand" "")
1703 (minus:P (match_dup 1)
1704 (match_dup 2)))]
1705 "reload_completed"
1706 [(set (match_dup 0)
1707 (minus:P (match_dup 1)
1708 (match_dup 2)))
1709 (set (match_dup 3)
1710 (compare:CC (match_dup 0)
1711 (const_int 0)))]
1712 "")
1714 (define_expand "sub<mode>3"
1715 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1716 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1717 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1718 ""
1719 "
1720 {
1721 if (GET_CODE (operands[2]) == CONST_INT)
1722 {
1723 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1724 negate_rtx (<MODE>mode, operands[2])));
1725 DONE;
1726 }
1727 }")
1730 (define_expand "neg<mode>2"
1731 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1732 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1733 ""
1734 "")
1736 (define_insn "*neg<mode>2"
1737 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1738 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1739 ""
1740 "neg %0,%1"
1741 [(set_attr "type" "add")])
1743 (define_insn_and_split "*neg<mode>2_dot"
1744 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1745 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1746 (const_int 0)))
1747 (clobber (match_scratch:GPR 0 "=r,r"))]
1748 "<MODE>mode == Pmode"
1749 "@
1750 neg. %0,%1
1751 #"
1752 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1753 [(set (match_dup 0)
1754 (neg:GPR (match_dup 1)))
1755 (set (match_dup 2)
1756 (compare:CC (match_dup 0)
1757 (const_int 0)))]
1758 ""
1759 [(set_attr "type" "add")
1760 (set_attr "dot" "yes")
1761 (set_attr "length" "4,8")])
1763 (define_insn_and_split "*neg<mode>2_dot2"
1764 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1765 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1766 (const_int 0)))
1767 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1768 (neg:GPR (match_dup 1)))]
1769 "<MODE>mode == Pmode"
1770 "@
1771 neg. %0,%1
1772 #"
1773 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1774 [(set (match_dup 0)
1775 (neg:GPR (match_dup 1)))
1776 (set (match_dup 2)
1777 (compare:CC (match_dup 0)
1778 (const_int 0)))]
1779 ""
1780 [(set_attr "type" "add")
1781 (set_attr "dot" "yes")
1782 (set_attr "length" "4,8")])
1785 (define_insn "clz<mode>2"
1786 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1787 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1788 ""
1789 "cntlz<wd> %0,%1"
1790 [(set_attr "type" "cntlz")])
1792 (define_expand "ctz<mode>2"
1793 [(set (match_dup 2)
1794 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1795 (set (match_dup 3)
1796 (and:GPR (match_dup 1)
1797 (match_dup 2)))
1798 (set (match_dup 4)
1799 (clz:GPR (match_dup 3)))
1800 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1801 (minus:GPR (match_dup 5)
1802 (match_dup 4)))]
1803 ""
1804 {
1805 operands[2] = gen_reg_rtx (<MODE>mode);
1806 operands[3] = gen_reg_rtx (<MODE>mode);
1807 operands[4] = gen_reg_rtx (<MODE>mode);
1808 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1809 })
1811 (define_expand "ffs<mode>2"
1812 [(set (match_dup 2)
1813 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1814 (set (match_dup 3)
1815 (and:GPR (match_dup 1)
1816 (match_dup 2)))
1817 (set (match_dup 4)
1818 (clz:GPR (match_dup 3)))
1819 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1820 (minus:GPR (match_dup 5)
1821 (match_dup 4)))]
1822 ""
1823 {
1824 operands[2] = gen_reg_rtx (<MODE>mode);
1825 operands[3] = gen_reg_rtx (<MODE>mode);
1826 operands[4] = gen_reg_rtx (<MODE>mode);
1827 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1828 })
1830 (define_insn "popcntb<mode>2"
1831 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1832 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1833 UNSPEC_POPCNTB))]
1834 "TARGET_POPCNTB"
1835 "popcntb %0,%1"
1836 [(set_attr "length" "4")
1837 (set_attr "type" "popcnt")])
1839 (define_insn "popcntd<mode>2"
1840 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1841 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1842 "TARGET_POPCNTD"
1843 "popcnt<wd> %0,%1"
1844 [(set_attr "length" "4")
1845 (set_attr "type" "popcnt")])
1847 (define_expand "popcount<mode>2"
1848 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1849 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1850 "TARGET_POPCNTB || TARGET_POPCNTD"
1851 {
1852 rs6000_emit_popcount (operands[0], operands[1]);
1853 DONE;
1854 })
1856 (define_insn "parity<mode>2_cmpb"
1857 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1858 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
1859 "TARGET_CMPB && TARGET_POPCNTB"
1860 "prty<wd> %0,%1"
1861 [(set_attr "length" "4")
1862 (set_attr "type" "popcnt")])
1864 (define_expand "parity<mode>2"
1865 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1866 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1867 "TARGET_POPCNTB"
1868 {
1869 rs6000_emit_parity (operands[0], operands[1]);
1870 DONE;
1871 })
1873 ;; Since the hardware zeros the upper part of the register, save generating the
1874 ;; AND immediate if we are converting to unsigned
1875 (define_insn "*bswaphi2_extenddi"
1876 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1877 (zero_extend:DI
1878 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1879 "TARGET_POWERPC64"
1880 "lhbrx %0,%y1"
1881 [(set_attr "length" "4")
1882 (set_attr "type" "load")])
1884 (define_insn "*bswaphi2_extendsi"
1885 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1886 (zero_extend:SI
1887 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1888 ""
1889 "lhbrx %0,%y1"
1890 [(set_attr "length" "4")
1891 (set_attr "type" "load")])
1893 (define_expand "bswaphi2"
1894 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1895 (bswap:HI
1896 (match_operand:HI 1 "reg_or_mem_operand" "")))
1897 (clobber (match_scratch:SI 2 ""))])]
1898 ""
1899 {
1900 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1901 operands[1] = force_reg (HImode, operands[1]);
1902 })
1904 (define_insn "bswaphi2_internal"
1905 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
1906 (bswap:HI
1907 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
1908 (clobber (match_scratch:SI 2 "=X,X,&r"))]
1909 ""
1910 "@
1911 lhbrx %0,%y1
1912 sthbrx %1,%y0
1913 #"
1914 [(set_attr "length" "4,4,12")
1915 (set_attr "type" "load,store,*")])
1917 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
1918 ;; correct for -mlittle as well as -mbig.
1919 (define_split
1920 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1921 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
1922 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
1923 "reload_completed"
1924 [(set (match_dup 3)
1925 (zero_extract:SI (match_dup 4)
1926 (const_int 8)
1927 (const_int 16)))
1928 (set (match_dup 2)
1929 (and:SI (ashift:SI (match_dup 4)
1930 (const_int 8))
1931 (const_int 65280))) ;; 0xff00
1932 (set (match_dup 3)
1933 (ior:SI (match_dup 3)
1934 (match_dup 2)))]
1935 "
1936 {
1937 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
1938 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
1939 }")
1941 (define_insn "*bswapsi2_extenddi"
1942 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1943 (zero_extend:DI
1944 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
1945 "TARGET_POWERPC64"
1946 "lwbrx %0,%y1"
1947 [(set_attr "length" "4")
1948 (set_attr "type" "load")])
1950 (define_expand "bswapsi2"
1951 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
1952 (bswap:SI
1953 (match_operand:SI 1 "reg_or_mem_operand" "")))]
1954 ""
1955 {
1956 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1957 operands[1] = force_reg (SImode, operands[1]);
1958 })
1960 (define_insn "*bswapsi2_internal"
1961 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
1962 (bswap:SI
1963 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
1964 ""
1965 "@
1966 lwbrx %0,%y1
1967 stwbrx %1,%y0
1968 #"
1969 [(set_attr "length" "4,4,12")
1970 (set_attr "type" "load,store,*")])
1972 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
1973 ;; zero_extract insns do not change for -mlittle.
1974 (define_split
1975 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1976 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1977 "reload_completed"
1978 [(set (match_dup 0)
1979 (rotate:SI (match_dup 1) (const_int 8)))
1980 (set (zero_extract:SI (match_dup 0)
1981 (const_int 8)
1982 (const_int 0))
1983 (match_dup 1))
1984 (set (zero_extract:SI (match_dup 0)
1985 (const_int 8)
1986 (const_int 16))
1987 (rotate:SI (match_dup 1)
1988 (const_int 16)))]
1989 "")
1991 (define_expand "bswapdi2"
1992 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
1993 (bswap:DI
1994 (match_operand:DI 1 "reg_or_mem_operand" "")))
1995 (clobber (match_scratch:DI 2 ""))
1996 (clobber (match_scratch:DI 3 ""))
1997 (clobber (match_scratch:DI 4 ""))])]
1998 ""
1999 {
2000 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2001 operands[1] = force_reg (DImode, operands[1]);
2003 if (!TARGET_POWERPC64)
2004 {
2005 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2006 that uses 64-bit registers needs the same scratch registers as 64-bit
2007 mode. */
2008 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2009 DONE;
2010 }
2011 })
2013 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2014 (define_insn "*bswapdi2_ldbrx"
2015 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2016 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2017 (clobber (match_scratch:DI 2 "=X,X,&r"))
2018 (clobber (match_scratch:DI 3 "=X,X,&r"))
2019 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2020 "TARGET_POWERPC64 && TARGET_LDBRX
2021 && (REG_P (operands[0]) || REG_P (operands[1]))"
2022 "@
2023 ldbrx %0,%y1
2024 stdbrx %1,%y0
2025 #"
2026 [(set_attr "length" "4,4,36")
2027 (set_attr "type" "load,store,*")])
2029 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2030 (define_insn "*bswapdi2_64bit"
2031 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2032 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2033 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2034 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2035 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2036 "TARGET_POWERPC64 && !TARGET_LDBRX
2037 && (REG_P (operands[0]) || REG_P (operands[1]))
2038 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2039 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2040 "#"
2041 [(set_attr "length" "16,12,36")])
2043 (define_split
2044 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2045 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2046 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2047 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2048 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2049 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2050 [(const_int 0)]
2051 "
2052 {
2053 rtx dest = operands[0];
2054 rtx src = operands[1];
2055 rtx op2 = operands[2];
2056 rtx op3 = operands[3];
2057 rtx op4 = operands[4];
2058 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2059 BYTES_BIG_ENDIAN ? 4 : 0);
2060 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2061 BYTES_BIG_ENDIAN ? 4 : 0);
2062 rtx addr1;
2063 rtx addr2;
2064 rtx word_high;
2065 rtx word_low;
2067 addr1 = XEXP (src, 0);
2068 if (GET_CODE (addr1) == PLUS)
2069 {
2070 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2071 if (TARGET_AVOID_XFORM)
2072 {
2073 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2074 addr2 = op2;
2075 }
2076 else
2077 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2078 }
2079 else if (TARGET_AVOID_XFORM)
2080 {
2081 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2082 addr2 = op2;
2083 }
2084 else
2085 {
2086 emit_move_insn (op2, GEN_INT (4));
2087 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2088 }
2090 if (BYTES_BIG_ENDIAN)
2091 {
2092 word_high = change_address (src, SImode, addr1);
2093 word_low = change_address (src, SImode, addr2);
2094 }
2095 else
2096 {
2097 word_high = change_address (src, SImode, addr2);
2098 word_low = change_address (src, SImode, addr1);
2099 }
2101 emit_insn (gen_bswapsi2 (op3_32, word_low));
2102 emit_insn (gen_bswapsi2 (op4_32, word_high));
2103 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2104 emit_insn (gen_iordi3 (dest, dest, op4));
2105 DONE;
2106 }")
2108 (define_split
2109 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2110 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2111 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2112 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2113 (clobber (match_operand:DI 4 "" ""))]
2114 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2115 [(const_int 0)]
2116 "
2117 {
2118 rtx dest = operands[0];
2119 rtx src = operands[1];
2120 rtx op2 = operands[2];
2121 rtx op3 = operands[3];
2122 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2123 BYTES_BIG_ENDIAN ? 4 : 0);
2124 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2125 BYTES_BIG_ENDIAN ? 4 : 0);
2126 rtx addr1;
2127 rtx addr2;
2128 rtx word_high;
2129 rtx word_low;
2131 addr1 = XEXP (dest, 0);
2132 if (GET_CODE (addr1) == PLUS)
2133 {
2134 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2135 if (TARGET_AVOID_XFORM)
2136 {
2137 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2138 addr2 = op2;
2139 }
2140 else
2141 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2142 }
2143 else if (TARGET_AVOID_XFORM)
2144 {
2145 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2146 addr2 = op2;
2147 }
2148 else
2149 {
2150 emit_move_insn (op2, GEN_INT (4));
2151 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2152 }
2154 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2155 if (BYTES_BIG_ENDIAN)
2156 {
2157 word_high = change_address (dest, SImode, addr1);
2158 word_low = change_address (dest, SImode, addr2);
2159 }
2160 else
2161 {
2162 word_high = change_address (dest, SImode, addr2);
2163 word_low = change_address (dest, SImode, addr1);
2164 }
2165 emit_insn (gen_bswapsi2 (word_high, src_si));
2166 emit_insn (gen_bswapsi2 (word_low, op3_si));
2167 DONE;
2168 }")
2170 (define_split
2171 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2172 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2173 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2174 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2175 (clobber (match_operand:DI 4 "" ""))]
2176 "TARGET_POWERPC64 && reload_completed"
2177 [(const_int 0)]
2178 "
2179 {
2180 rtx dest = operands[0];
2181 rtx src = operands[1];
2182 rtx op2 = operands[2];
2183 rtx op3 = operands[3];
2184 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2185 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2186 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2187 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2188 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2190 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2191 emit_insn (gen_bswapsi2 (dest_si, src_si));
2192 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2193 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2194 emit_insn (gen_iordi3 (dest, dest, op3));
2195 DONE;
2196 }")
2198 (define_insn "bswapdi2_32bit"
2199 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2200 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2201 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2202 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2203 "#"
2204 [(set_attr "length" "16,12,36")])
2206 (define_split
2207 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2208 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2209 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2210 "!TARGET_POWERPC64 && reload_completed"
2211 [(const_int 0)]
2212 "
2213 {
2214 rtx dest = operands[0];
2215 rtx src = operands[1];
2216 rtx op2 = operands[2];
2217 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2218 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2219 rtx addr1;
2220 rtx addr2;
2221 rtx word1;
2222 rtx word2;
2224 addr1 = XEXP (src, 0);
2225 if (GET_CODE (addr1) == PLUS)
2226 {
2227 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2228 if (TARGET_AVOID_XFORM)
2229 {
2230 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2231 addr2 = op2;
2232 }
2233 else
2234 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2235 }
2236 else if (TARGET_AVOID_XFORM)
2237 {
2238 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2239 addr2 = op2;
2240 }
2241 else
2242 {
2243 emit_move_insn (op2, GEN_INT (4));
2244 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2245 }
2247 word1 = change_address (src, SImode, addr1);
2248 word2 = change_address (src, SImode, addr2);
2250 emit_insn (gen_bswapsi2 (dest2, word1));
2251 emit_insn (gen_bswapsi2 (dest1, word2));
2252 DONE;
2253 }")
2255 (define_split
2256 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2257 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2258 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2259 "!TARGET_POWERPC64 && reload_completed"
2260 [(const_int 0)]
2261 "
2262 {
2263 rtx dest = operands[0];
2264 rtx src = operands[1];
2265 rtx op2 = operands[2];
2266 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2267 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2268 rtx addr1;
2269 rtx addr2;
2270 rtx word1;
2271 rtx word2;
2273 addr1 = XEXP (dest, 0);
2274 if (GET_CODE (addr1) == PLUS)
2275 {
2276 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2277 if (TARGET_AVOID_XFORM)
2278 {
2279 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2280 addr2 = op2;
2281 }
2282 else
2283 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2284 }
2285 else if (TARGET_AVOID_XFORM)
2286 {
2287 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2288 addr2 = op2;
2289 }
2290 else
2291 {
2292 emit_move_insn (op2, GEN_INT (4));
2293 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2294 }
2296 word1 = change_address (dest, SImode, addr1);
2297 word2 = change_address (dest, SImode, addr2);
2299 emit_insn (gen_bswapsi2 (word2, src1));
2300 emit_insn (gen_bswapsi2 (word1, src2));
2301 DONE;
2302 }")
2304 (define_split
2305 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2306 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2307 (clobber (match_operand:SI 2 "" ""))]
2308 "!TARGET_POWERPC64 && reload_completed"
2309 [(const_int 0)]
2310 "
2311 {
2312 rtx dest = operands[0];
2313 rtx src = operands[1];
2314 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2315 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2316 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2317 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2319 emit_insn (gen_bswapsi2 (dest1, src2));
2320 emit_insn (gen_bswapsi2 (dest2, src1));
2321 DONE;
2322 }")
2325 (define_insn "mul<mode>3"
2326 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2327 (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2328 (match_operand:GPR 2 "reg_or_short_operand" "r,I")))]
2329 ""
2330 "@
2331 mull<wd> %0,%1,%2
2332 mulli %0,%1,%2"
2333 [(set_attr "type" "mul")
2334 (set (attr "size")
2335 (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
2336 (const_string "8")
2337 (match_operand:GPR 2 "short_cint_operand" "")
2338 (const_string "16")]
2339 (const_string "<bits>")))])
2341 (define_insn_and_split "*mul<mode>3_dot"
2342 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2343 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2344 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2345 (const_int 0)))
2346 (clobber (match_scratch:GPR 0 "=r,r"))]
2347 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2348 "@
2349 mull<wd>. %0,%1,%2
2350 #"
2351 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2352 [(set (match_dup 0)
2353 (mult:GPR (match_dup 1)
2354 (match_dup 2)))
2355 (set (match_dup 3)
2356 (compare:CC (match_dup 0)
2357 (const_int 0)))]
2358 ""
2359 [(set_attr "type" "mul")
2360 (set_attr "size" "<bits>")
2361 (set_attr "dot" "yes")
2362 (set_attr "length" "4,8")])
2364 (define_insn_and_split "*mul<mode>3_dot2"
2365 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2366 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2367 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2368 (const_int 0)))
2369 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2370 (mult:GPR (match_dup 1)
2371 (match_dup 2)))]
2372 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2373 "@
2374 mull<wd>. %0,%1,%2
2375 #"
2376 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2377 [(set (match_dup 0)
2378 (mult:GPR (match_dup 1)
2379 (match_dup 2)))
2380 (set (match_dup 3)
2381 (compare:CC (match_dup 0)
2382 (const_int 0)))]
2383 ""
2384 [(set_attr "type" "mul")
2385 (set_attr "size" "<bits>")
2386 (set_attr "dot" "yes")
2387 (set_attr "length" "4,8")])
2390 (define_expand "<su>mul<mode>3_highpart"
2391 [(set (match_operand:GPR 0 "gpc_reg_operand")
2392 (subreg:GPR
2393 (mult:<DMODE> (any_extend:<DMODE>
2394 (match_operand:GPR 1 "gpc_reg_operand"))
2395 (any_extend:<DMODE>
2396 (match_operand:GPR 2 "gpc_reg_operand")))
2397 0))]
2398 ""
2399 {
2400 if (<MODE>mode == SImode && TARGET_POWERPC64)
2401 {
2402 emit_insn (gen_<su>mulsi3_highpart_64 (operands[0], operands[1],
2403 operands[2]));
2404 DONE;
2405 }
2407 if (!WORDS_BIG_ENDIAN)
2408 {
2409 emit_insn (gen_<su>mul<mode>3_highpart_le (operands[0], operands[1],
2410 operands[2]));
2411 DONE;
2412 }
2413 })
2415 (define_insn "*<su>mul<mode>3_highpart"
2416 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2417 (subreg:GPR
2418 (mult:<DMODE> (any_extend:<DMODE>
2419 (match_operand:GPR 1 "gpc_reg_operand" "r"))
2420 (any_extend:<DMODE>
2421 (match_operand:GPR 2 "gpc_reg_operand" "r")))
2422 0))]
2423 "WORDS_BIG_ENDIAN && !(<MODE>mode == SImode && TARGET_POWERPC64)"
2424 "mulh<wd><u> %0,%1,%2"
2425 [(set_attr "type" "mul")
2426 (set_attr "size" "<bits>")])
2428 (define_insn "<su>mulsi3_highpart_le"
2429 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2430 (subreg:SI
2431 (mult:DI (any_extend:DI
2432 (match_operand:SI 1 "gpc_reg_operand" "r"))
2433 (any_extend:DI
2434 (match_operand:SI 2 "gpc_reg_operand" "r")))
2435 4))]
2436 "!WORDS_BIG_ENDIAN && !TARGET_POWERPC64"
2437 "mulhw<u> %0,%1,%2"
2438 [(set_attr "type" "mul")])
2440 (define_insn "<su>muldi3_highpart_le"
2441 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2442 (subreg:DI
2443 (mult:TI (any_extend:TI
2444 (match_operand:DI 1 "gpc_reg_operand" "r"))
2445 (any_extend:TI
2446 (match_operand:DI 2 "gpc_reg_operand" "r")))
2447 8))]
2448 "!WORDS_BIG_ENDIAN && TARGET_POWERPC64"
2449 "mulhd<u> %0,%1,%2"
2450 [(set_attr "type" "mul")
2451 (set_attr "size" "64")])
2453 (define_insn "<su>mulsi3_highpart_64"
2454 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2455 (truncate:SI
2456 (lshiftrt:DI
2457 (mult:DI (any_extend:DI
2458 (match_operand:SI 1 "gpc_reg_operand" "r"))
2459 (any_extend:DI
2460 (match_operand:SI 2 "gpc_reg_operand" "r")))
2461 (const_int 32))))]
2462 "TARGET_POWERPC64"
2463 "mulhw<u> %0,%1,%2"
2464 [(set_attr "type" "mul")])
2466 (define_expand "<u>mul<mode><dmode>3"
2467 [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
2468 (mult:<DMODE> (any_extend:<DMODE>
2469 (match_operand:GPR 1 "gpc_reg_operand"))
2470 (any_extend:<DMODE>
2471 (match_operand:GPR 2 "gpc_reg_operand"))))]
2472 "!(<MODE>mode == SImode && TARGET_POWERPC64)"
2473 {
2474 rtx l = gen_reg_rtx (<MODE>mode);
2475 rtx h = gen_reg_rtx (<MODE>mode);
2476 emit_insn (gen_mul<mode>3 (l, operands[1], operands[2]));
2477 emit_insn (gen_<su>mul<mode>3_highpart (h, operands[1], operands[2]));
2478 emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
2479 emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
2480 DONE;
2481 })
2484 (define_insn "udiv<mode>3"
2485 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2486 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2487 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2488 ""
2489 "div<wd>u %0,%1,%2"
2490 [(set_attr "type" "div")
2491 (set_attr "size" "<bits>")])
2494 ;; For powers of two we can do srai/aze for divide and then adjust for
2495 ;; modulus. If it isn't a power of two, force operands into register and do
2496 ;; a normal divide.
2497 (define_expand "div<mode>3"
2498 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2499 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2500 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2501 ""
2502 {
2503 if (GET_CODE (operands[2]) != CONST_INT
2504 || INTVAL (operands[2]) <= 0
2505 || exact_log2 (INTVAL (operands[2])) < 0)
2506 operands[2] = force_reg (<MODE>mode, operands[2]);
2507 })
2509 (define_insn "*div<mode>3"
2510 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2511 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2512 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2513 ""
2514 "div<wd> %0,%1,%2"
2515 [(set_attr "type" "div")
2516 (set_attr "size" "<bits>")])
2518 (define_expand "mod<mode>3"
2519 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2520 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2521 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2522 ""
2523 "
2524 {
2525 int i;
2526 rtx temp1;
2527 rtx temp2;
2529 if (GET_CODE (operands[2]) != CONST_INT
2530 || INTVAL (operands[2]) <= 0
2531 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2532 FAIL;
2534 temp1 = gen_reg_rtx (<MODE>mode);
2535 temp2 = gen_reg_rtx (<MODE>mode);
2537 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2538 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2539 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2540 DONE;
2541 }")
2543 (define_insn ""
2544 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2545 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2546 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2547 ""
2548 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2549 [(set_attr "type" "two")
2550 (set_attr "length" "8")])
2552 (define_insn ""
2553 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2554 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2555 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2556 (const_int 0)))
2557 (clobber (match_scratch:P 3 "=r,r"))]
2558 ""
2559 "@
2560 sra<wd>i %3,%1,%p2\;addze. %3,%3
2561 #"
2562 [(set_attr "type" "compare")
2563 (set_attr "length" "8,12")
2564 (set_attr "cell_micro" "not")])
2566 (define_split
2567 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2568 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2569 (match_operand:GPR 2 "exact_log2_cint_operand"
2570 ""))
2571 (const_int 0)))
2572 (clobber (match_scratch:GPR 3 ""))]
2573 "reload_completed"
2574 [(set (match_dup 3)
2575 (div:<MODE> (match_dup 1) (match_dup 2)))
2576 (set (match_dup 0)
2577 (compare:CC (match_dup 3)
2578 (const_int 0)))]
2579 "")
2581 (define_insn ""
2582 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2583 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2584 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2585 (const_int 0)))
2586 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2587 (div:P (match_dup 1) (match_dup 2)))]
2588 ""
2589 "@
2590 sra<wd>i %0,%1,%p2\;addze. %0,%0
2591 #"
2592 [(set_attr "type" "compare")
2593 (set_attr "length" "8,12")
2594 (set_attr "cell_micro" "not")])
2596 (define_split
2597 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2598 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2599 (match_operand:GPR 2 "exact_log2_cint_operand"
2600 ""))
2601 (const_int 0)))
2602 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2603 (div:GPR (match_dup 1) (match_dup 2)))]
2604 "reload_completed"
2605 [(set (match_dup 0)
2606 (div:<MODE> (match_dup 1) (match_dup 2)))
2607 (set (match_dup 3)
2608 (compare:CC (match_dup 0)
2609 (const_int 0)))]
2610 "")
2611 \f
2612 ;; Logical instructions
2613 ;; The logical instructions are mostly combined by using match_operator,
2614 ;; but the plain AND insns are somewhat different because there is no
2615 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2616 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2618 (define_expand "and<mode>3"
2619 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2620 (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2621 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2622 ""
2623 {
2624 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2625 {
2626 rs6000_split_logical (operands, AND, false, false, false);
2627 DONE;
2628 }
2630 if (logical_const_operand (operands[2], <MODE>mode)
2631 && !any_mask_operand (operands[2], <MODE>mode))
2632 {
2633 emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
2634 DONE;
2635 }
2637 if ((<MODE>mode == DImode && !and64_2_operand (operands[2], <MODE>mode))
2638 || (<MODE>mode != DImode && !and_operand (operands[2], <MODE>mode)))
2639 operands[2] = force_reg (<MODE>mode, operands[2]);
2640 })
2643 (define_insn "*and<mode>3"
2644 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2645 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2646 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2647 ""
2648 "and %0,%1,%2"
2649 [(set_attr "type" "logical")])
2651 (define_insn_and_split "*and<mode>3_dot"
2652 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2653 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2654 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2655 (const_int 0)))
2656 (clobber (match_scratch:GPR 0 "=r,r"))]
2657 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2658 "@
2659 and. %0,%1,%2
2660 #"
2661 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2662 [(set (match_dup 0)
2663 (and:GPR (match_dup 1)
2664 (match_dup 2)))
2665 (set (match_dup 3)
2666 (compare:CC (match_dup 0)
2667 (const_int 0)))]
2668 ""
2669 [(set_attr "type" "logical")
2670 (set_attr "dot" "yes")
2671 (set_attr "length" "4,8")])
2673 (define_insn_and_split "*and<mode>3_dot2"
2674 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2675 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2676 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2677 (const_int 0)))
2678 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2679 (and:GPR (match_dup 1)
2680 (match_dup 2)))]
2681 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2682 "@
2683 and. %0,%1,%2
2684 #"
2685 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2686 [(set (match_dup 0)
2687 (and:GPR (match_dup 1)
2688 (match_dup 2)))
2689 (set (match_dup 3)
2690 (compare:CC (match_dup 0)
2691 (const_int 0)))]
2692 ""
2693 [(set_attr "type" "logical")
2694 (set_attr "dot" "yes")
2695 (set_attr "length" "4,8")])
2698 (define_insn "and<mode>3_imm"
2699 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2700 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
2701 (match_operand:GPR 2 "logical_const_operand" "n")))
2702 (clobber (match_scratch:CC 3 "=x"))]
2703 "rs6000_gen_cell_microcode
2704 && !any_mask_operand (operands[2], <MODE>mode)"
2705 "andi%e2. %0,%1,%u2"
2706 [(set_attr "type" "logical")
2707 (set_attr "dot" "yes")])
2709 (define_insn_and_split "*and<mode>3_imm_dot"
2710 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2711 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2712 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2713 (const_int 0)))
2714 (clobber (match_scratch:GPR 0 "=r,r"))
2715 (clobber (match_scratch:CC 4 "=X,x"))]
2716 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2717 && rs6000_gen_cell_microcode
2718 && !any_mask_operand (operands[2], <MODE>mode)"
2719 "@
2720 andi%e2. %0,%1,%u2
2721 #"
2722 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2723 [(parallel [(set (match_dup 0)
2724 (and:GPR (match_dup 1)
2725 (match_dup 2)))
2726 (clobber (match_dup 4))])
2727 (set (match_dup 3)
2728 (compare:CC (match_dup 0)
2729 (const_int 0)))]
2730 ""
2731 [(set_attr "type" "logical")
2732 (set_attr "dot" "yes")
2733 (set_attr "length" "4,8")])
2735 (define_insn_and_split "*and<mode>3_imm_dot2"
2736 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2737 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2738 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2739 (const_int 0)))
2740 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2741 (and:GPR (match_dup 1)
2742 (match_dup 2)))
2743 (clobber (match_scratch:CC 4 "=X,x"))]
2744 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2745 && rs6000_gen_cell_microcode
2746 && !any_mask_operand (operands[2], <MODE>mode)"
2747 "@
2748 andi%e2. %0,%1,%u2
2749 #"
2750 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2751 [(parallel [(set (match_dup 0)
2752 (and:GPR (match_dup 1)
2753 (match_dup 2)))
2754 (clobber (match_dup 4))])
2755 (set (match_dup 3)
2756 (compare:CC (match_dup 0)
2757 (const_int 0)))]
2758 ""
2759 [(set_attr "type" "logical")
2760 (set_attr "dot" "yes")
2761 (set_attr "length" "4,8")])
2763 (define_insn_and_split "*and<mode>3_imm_mask_dot"
2764 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2765 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2766 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2767 (const_int 0)))
2768 (clobber (match_scratch:GPR 0 "=r,r"))]
2769 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2770 && rs6000_gen_cell_microcode
2771 && any_mask_operand (operands[2], <MODE>mode)"
2772 "@
2773 andi%e2. %0,%1,%u2
2774 #"
2775 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2776 [(set (match_dup 0)
2777 (and:GPR (match_dup 1)
2778 (match_dup 2)))
2779 (set (match_dup 3)
2780 (compare:CC (match_dup 0)
2781 (const_int 0)))]
2782 ""
2783 [(set_attr "type" "logical")
2784 (set_attr "dot" "yes")
2785 (set_attr "length" "4,8")])
2787 (define_insn_and_split "*and<mode>3_imm_mask_dot2"
2788 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2789 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2790 (match_operand:GPR 2 "logical_const_operand" "n,n"))
2791 (const_int 0)))
2792 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2793 (and:GPR (match_dup 1)
2794 (match_dup 2)))]
2795 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2796 && rs6000_gen_cell_microcode
2797 && any_mask_operand (operands[2], <MODE>mode)"
2798 "@
2799 andi%e2. %0,%1,%u2
2800 #"
2801 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2802 [(set (match_dup 0)
2803 (and:GPR (match_dup 1)
2804 (match_dup 2)))
2805 (set (match_dup 3)
2806 (compare:CC (match_dup 0)
2807 (const_int 0)))]
2808 ""
2809 [(set_attr "type" "logical")
2810 (set_attr "dot" "yes")
2811 (set_attr "length" "4,8")])
2814 (define_insn "*and<mode>3_mask"
2815 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2816 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2817 (match_operand:GPR 2 "any_mask_operand" "S,T")))]
2818 ""
2819 "@
2820 rldic%B2 %0,%1,0,%S2
2821 rlwinm %0,%1,0,%m2,%M2"
2822 [(set_attr "type" "shift")])
2824 (define_insn_and_split "*and<mode>3_mask_dot"
2825 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2826 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2827 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2828 (const_int 0)))
2829 (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
2830 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2831 && rs6000_gen_cell_microcode
2832 && !logical_const_operand (operands[2], <MODE>mode)"
2833 "@
2834 rldic%B2. %0,%1,0,%S2
2835 rlwinm. %0,%1,0,%m2,%M2
2836 #
2837 #"
2838 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2839 [(set (match_dup 0)
2840 (and:GPR (match_dup 1)
2841 (match_dup 2)))
2842 (set (match_dup 3)
2843 (compare:CC (match_dup 0)
2844 (const_int 0)))]
2845 ""
2846 [(set_attr "type" "shift")
2847 (set_attr "dot" "yes")
2848 (set_attr "length" "4,4,8,8")])
2850 (define_insn_and_split "*and<mode>3_mask_dot2"
2851 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
2852 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")
2853 (match_operand:GPR 2 "any_mask_operand" "S,T,S,T"))
2854 (const_int 0)))
2855 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
2856 (and:GPR (match_dup 1)
2857 (match_dup 2)))]
2858 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
2859 && rs6000_gen_cell_microcode
2860 && !logical_const_operand (operands[2], <MODE>mode)"
2861 "@
2862 rldic%B2. %0,%1,0,%S2
2863 rlwinm. %0,%1,0,%m2,%M2
2864 #
2865 #"
2866 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2867 [(set (match_dup 0)
2868 (and:GPR (match_dup 1)
2869 (match_dup 2)))
2870 (set (match_dup 3)
2871 (compare:CC (match_dup 0)
2872 (const_int 0)))]
2873 ""
2874 [(set_attr "type" "shift")
2875 (set_attr "dot" "yes")
2876 (set_attr "length" "4,4,8,8")])
2880 (define_insn "andsi3_internal0_nomc"
2881 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2882 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2883 (match_operand:SI 2 "and_operand" "?r,T")))]
2884 "!rs6000_gen_cell_microcode"
2885 "@
2886 and %0,%1,%2
2887 rlwinm %0,%1,0,%m2,%M2"
2888 [(set_attr "type" "logical,shift")])
2891 ;; Handle the PowerPC64 rlwinm corner case
2893 (define_insn_and_split "*andsi3_internal6"
2894 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2895 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2896 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2897 "TARGET_POWERPC64"
2898 "#"
2899 "TARGET_POWERPC64"
2900 [(set (match_dup 0)
2901 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2902 (match_dup 4)))
2903 (set (match_dup 0)
2904 (rotate:SI (match_dup 0) (match_dup 5)))]
2905 "
2906 {
2907 int mb = extract_MB (operands[2]);
2908 int me = extract_ME (operands[2]);
2909 operands[3] = GEN_INT (me + 1);
2910 operands[5] = GEN_INT (32 - (me + 1));
2911 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2912 }"
2913 [(set_attr "length" "8")])
2916 (define_expand "ior<mode>3"
2917 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2918 (ior:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2919 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2920 ""
2921 {
2922 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2923 {
2924 rs6000_split_logical (operands, IOR, false, false, false);
2925 DONE;
2926 }
2928 if (non_logical_cint_operand (operands[2], <MODE>mode))
2929 {
2930 rtx tmp = ((!can_create_pseudo_p ()
2931 || rtx_equal_p (operands[0], operands[1]))
2932 ? operands[0] : gen_reg_rtx (<MODE>mode));
2933 HOST_WIDE_INT value = INTVAL (operands[2]);
2935 emit_insn (gen_ior<mode>3 (tmp, operands[1],
2936 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2938 emit_insn (gen_ior<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2939 DONE;
2940 }
2942 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
2943 operands[2] = force_reg (<MODE>mode, operands[2]);
2944 })
2946 (define_expand "xor<mode>3"
2947 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2948 (xor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
2949 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
2950 ""
2951 {
2952 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2953 {
2954 rs6000_split_logical (operands, XOR, false, false, false);
2955 DONE;
2956 }
2958 if (non_logical_cint_operand (operands[2], <MODE>mode))
2959 {
2960 rtx tmp = ((!can_create_pseudo_p ()
2961 || rtx_equal_p (operands[0], operands[1]))
2962 ? operands[0] : gen_reg_rtx (<MODE>mode));
2963 HOST_WIDE_INT value = INTVAL (operands[2]);
2965 emit_insn (gen_xor<mode>3 (tmp, operands[1],
2966 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2968 emit_insn (gen_xor<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2969 DONE;
2970 }
2972 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
2973 operands[2] = force_reg (<MODE>mode, operands[2]);
2974 })
2976 (define_insn "*bool<mode>3"
2977 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2978 (match_operator:GPR 3 "boolean_or_operator"
2979 [(match_operand:GPR 1 "gpc_reg_operand" "r")
2980 (match_operand:GPR 2 "gpc_reg_operand" "r")]))]
2981 ""
2982 "%q3 %0,%1,%2"
2983 [(set_attr "type" "logical")])
2985 (define_insn "*bool<mode>3_imm"
2986 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2987 (match_operator:GPR 3 "boolean_or_operator"
2988 [(match_operand:GPR 1 "gpc_reg_operand" "%r")
2989 (match_operand:GPR 2 "logical_const_operand" "n")]))]
2990 ""
2991 "%q3i%e2 %0,%1,%u2"
2992 [(set_attr "type" "logical")])
2994 (define_insn_and_split "*bool<mode>3_dot"
2995 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2996 (compare:CC (match_operator:GPR 3 "boolean_or_operator"
2997 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
2998 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
2999 (const_int 0)))
3000 (clobber (match_scratch:GPR 0 "=r,r"))]
3001 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3002 "@
3003 %q3. %0,%1,%2
3004 #"
3005 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3006 [(set (match_dup 0)
3007 (match_dup 3))
3008 (set (match_dup 4)
3009 (compare:CC (match_dup 0)
3010 (const_int 0)))]
3011 ""
3012 [(set_attr "type" "logical")
3013 (set_attr "dot" "yes")
3014 (set_attr "length" "4,8")])
3016 (define_insn_and_split "*bool<mode>3_dot2"
3017 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3018 (compare:CC (match_operator:GPR 3 "boolean_or_operator"
3019 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
3020 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
3021 (const_int 0)))
3022 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3023 (match_dup 3))]
3024 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3025 "@
3026 %q3. %0,%1,%2
3027 #"
3028 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3029 [(set (match_dup 0)
3030 (match_dup 3))
3031 (set (match_dup 4)
3032 (compare:CC (match_dup 0)
3033 (const_int 0)))]
3034 ""
3035 [(set_attr "type" "logical")
3036 (set_attr "dot" "yes")
3037 (set_attr "length" "4,8")])
3039 ;; Split a logical operation that we can't do in one insn into two insns,
3040 ;; each of which does one 16-bit part. This is used by combine.
3042 (define_split
3043 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3044 (match_operator:GPR 3 "boolean_or_operator"
3045 [(match_operand:GPR 1 "gpc_reg_operand" "")
3046 (match_operand:GPR 2 "non_logical_cint_operand" "")]))]
3047 ""
3048 [(set (match_dup 0) (match_dup 4))
3049 (set (match_dup 0) (match_dup 5))]
3050 {
3051 rtx i;
3052 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3053 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
3054 operands[1], i);
3055 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3056 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
3057 operands[0], i);
3058 })
3061 (define_insn "*boolc<mode>3"
3062 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3063 (match_operator:GPR 3 "boolean_operator"
3064 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))
3065 (match_operand:GPR 1 "gpc_reg_operand" "r")]))]
3066 ""
3067 "%q3 %0,%1,%2"
3068 [(set_attr "type" "logical")])
3070 (define_insn_and_split "*boolc<mode>3_dot"
3071 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3072 (compare:CC (match_operator:GPR 3 "boolean_operator"
3073 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3074 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3075 (const_int 0)))
3076 (clobber (match_scratch:GPR 0 "=r,r"))]
3077 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3078 "@
3079 %q3. %0,%1,%2
3080 #"
3081 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3082 [(set (match_dup 0)
3083 (match_dup 3))
3084 (set (match_dup 4)
3085 (compare:CC (match_dup 0)
3086 (const_int 0)))]
3087 ""
3088 [(set_attr "type" "logical")
3089 (set_attr "dot" "yes")
3090 (set_attr "length" "4,8")])
3092 (define_insn_and_split "*boolc<mode>3_dot2"
3093 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3094 (compare:CC (match_operator:GPR 3 "boolean_operator"
3095 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3096 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3097 (const_int 0)))
3098 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3099 (match_dup 3))]
3100 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3101 "@
3102 %q3. %0,%1,%2
3103 #"
3104 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3105 [(set (match_dup 0)
3106 (match_dup 3))
3107 (set (match_dup 4)
3108 (compare:CC (match_dup 0)
3109 (const_int 0)))]
3110 ""
3111 [(set_attr "type" "logical")
3112 (set_attr "dot" "yes")
3113 (set_attr "length" "4,8")])
3116 (define_insn "*boolcc<mode>3"
3117 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3118 (match_operator:GPR 3 "boolean_operator"
3119 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
3120 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))]
3121 ""
3122 "%q3 %0,%1,%2"
3123 [(set_attr "type" "logical")])
3125 (define_insn_and_split "*boolcc<mode>3_dot"
3126 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3127 (compare:CC (match_operator:GPR 3 "boolean_operator"
3128 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3129 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3130 (const_int 0)))
3131 (clobber (match_scratch:GPR 0 "=r,r"))]
3132 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3133 "@
3134 %q3. %0,%1,%2
3135 #"
3136 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3137 [(set (match_dup 0)
3138 (match_dup 3))
3139 (set (match_dup 4)
3140 (compare:CC (match_dup 0)
3141 (const_int 0)))]
3142 ""
3143 [(set_attr "type" "logical")
3144 (set_attr "dot" "yes")
3145 (set_attr "length" "4,8")])
3147 (define_insn_and_split "*boolcc<mode>3_dot2"
3148 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3149 (compare:CC (match_operator:GPR 3 "boolean_operator"
3150 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3151 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3152 (const_int 0)))
3153 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3154 (match_dup 3))]
3155 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3156 "@
3157 %q3. %0,%1,%2
3158 #"
3159 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3160 [(set (match_dup 0)
3161 (match_dup 3))
3162 (set (match_dup 4)
3163 (compare:CC (match_dup 0)
3164 (const_int 0)))]
3165 ""
3166 [(set_attr "type" "logical")
3167 (set_attr "dot" "yes")
3168 (set_attr "length" "4,8")])
3171 ;; TODO: Should have dots of this as well.
3172 (define_insn "*eqv<mode>3"
3173 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3174 (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3175 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
3176 ""
3177 "eqv %0,%1,%2"
3178 [(set_attr "type" "logical")])
3179 \f
3180 ;; Rotate and shift insns, in all their variants. These support shifts,
3181 ;; field inserts and extracts, and various combinations thereof.
3182 (define_expand "insv"
3183 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3184 (match_operand:SI 1 "const_int_operand" "")
3185 (match_operand:SI 2 "const_int_operand" ""))
3186 (match_operand 3 "gpc_reg_operand" ""))]
3187 ""
3188 "
3189 {
3190 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3191 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3192 compiler if the address of the structure is taken later. Likewise, do
3193 not handle invalid E500 subregs. */
3194 if (GET_CODE (operands[0]) == SUBREG
3195 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3196 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3197 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3198 FAIL;
3200 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3201 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3202 operands[3]));
3203 else
3204 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3205 operands[3]));
3206 DONE;
3207 }")
3209 (define_insn "insvsi_internal"
3210 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3211 (match_operand:SI 1 "const_int_operand" "i")
3212 (match_operand:SI 2 "const_int_operand" "i"))
3213 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3214 ""
3215 "*
3216 {
3217 int start = INTVAL (operands[2]) & 31;
3218 int size = INTVAL (operands[1]) & 31;
3220 operands[4] = GEN_INT (32 - start - size);
3221 operands[1] = GEN_INT (start + size - 1);
3222 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3223 }"
3224 [(set_attr "type" "insert")])
3226 (define_insn "*insvsi_internal1"
3227 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3228 (match_operand:SI 1 "const_int_operand" "i")
3229 (match_operand:SI 2 "const_int_operand" "i"))
3230 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3231 (match_operand:SI 4 "const_int_operand" "i")))]
3232 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3233 "*
3234 {
3235 int shift = INTVAL (operands[4]) & 31;
3236 int start = INTVAL (operands[2]) & 31;
3237 int size = INTVAL (operands[1]) & 31;
3239 operands[4] = GEN_INT (shift - start - size);
3240 operands[1] = GEN_INT (start + size - 1);
3241 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3242 }"
3243 [(set_attr "type" "insert")])
3245 (define_insn "*insvsi_internal2"
3246 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3247 (match_operand:SI 1 "const_int_operand" "i")
3248 (match_operand:SI 2 "const_int_operand" "i"))
3249 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3250 (match_operand:SI 4 "const_int_operand" "i")))]
3251 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3252 "*
3253 {
3254 int shift = INTVAL (operands[4]) & 31;
3255 int start = INTVAL (operands[2]) & 31;
3256 int size = INTVAL (operands[1]) & 31;
3258 operands[4] = GEN_INT (32 - shift - start - size);
3259 operands[1] = GEN_INT (start + size - 1);
3260 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3261 }"
3262 [(set_attr "type" "insert")])
3264 (define_insn "*insvsi_internal3"
3265 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3266 (match_operand:SI 1 "const_int_operand" "i")
3267 (match_operand:SI 2 "const_int_operand" "i"))
3268 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3269 (match_operand:SI 4 "const_int_operand" "i")))]
3270 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3271 "*
3272 {
3273 int shift = INTVAL (operands[4]) & 31;
3274 int start = INTVAL (operands[2]) & 31;
3275 int size = INTVAL (operands[1]) & 31;
3277 operands[4] = GEN_INT (32 - shift - start - size);
3278 operands[1] = GEN_INT (start + size - 1);
3279 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3280 }"
3281 [(set_attr "type" "insert")])
3283 (define_insn "*insvsi_internal4"
3284 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3285 (match_operand:SI 1 "const_int_operand" "i")
3286 (match_operand:SI 2 "const_int_operand" "i"))
3287 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3288 (match_operand:SI 4 "const_int_operand" "i")
3289 (match_operand:SI 5 "const_int_operand" "i")))]
3290 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3291 "*
3292 {
3293 int extract_start = INTVAL (operands[5]) & 31;
3294 int extract_size = INTVAL (operands[4]) & 31;
3295 int insert_start = INTVAL (operands[2]) & 31;
3296 int insert_size = INTVAL (operands[1]) & 31;
3298 /* Align extract field with insert field */
3299 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3300 operands[1] = GEN_INT (insert_start + insert_size - 1);
3301 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3302 }"
3303 [(set_attr "type" "insert")])
3305 ;; combine patterns for rlwimi
3306 (define_insn "*insvsi_internal5"
3307 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3308 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3309 (match_operand:SI 1 "mask_operand" "i"))
3310 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3311 (match_operand:SI 2 "const_int_operand" "i"))
3312 (match_operand:SI 5 "mask_operand" "i"))))]
3313 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3314 "*
3315 {
3316 int me = extract_ME(operands[5]);
3317 int mb = extract_MB(operands[5]);
3318 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3319 operands[2] = GEN_INT(mb);
3320 operands[1] = GEN_INT(me);
3321 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3322 }"
3323 [(set_attr "type" "insert")])
3325 (define_insn "*insvsi_internal6"
3326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3327 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3328 (match_operand:SI 2 "const_int_operand" "i"))
3329 (match_operand:SI 5 "mask_operand" "i"))
3330 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3331 (match_operand:SI 1 "mask_operand" "i"))))]
3332 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3333 "*
3334 {
3335 int me = extract_ME(operands[5]);
3336 int mb = extract_MB(operands[5]);
3337 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3338 operands[2] = GEN_INT(mb);
3339 operands[1] = GEN_INT(me);
3340 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3341 }"
3342 [(set_attr "type" "insert")])
3344 (define_insn "insvdi_internal"
3345 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3346 (match_operand:SI 1 "const_int_operand" "i")
3347 (match_operand:SI 2 "const_int_operand" "i"))
3348 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3349 "TARGET_POWERPC64"
3350 "*
3351 {
3352 int start = INTVAL (operands[2]) & 63;
3353 int size = INTVAL (operands[1]) & 63;
3355 operands[1] = GEN_INT (64 - start - size);
3356 return \"rldimi %0,%3,%H1,%H2\";
3357 }"
3358 [(set_attr "type" "insert")
3359 (set_attr "size" "64")])
3361 (define_insn "*insvdi_internal2"
3362 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3363 (match_operand:SI 1 "const_int_operand" "i")
3364 (match_operand:SI 2 "const_int_operand" "i"))
3365 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3366 (match_operand:SI 4 "const_int_operand" "i")))]
3367 "TARGET_POWERPC64
3368 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3369 "*
3370 {
3371 int shift = INTVAL (operands[4]) & 63;
3372 int start = (INTVAL (operands[2]) & 63) - 32;
3373 int size = INTVAL (operands[1]) & 63;
3375 operands[4] = GEN_INT (64 - shift - start - size);
3376 operands[2] = GEN_INT (start);
3377 operands[1] = GEN_INT (start + size - 1);
3378 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3379 }")
3381 (define_insn "*insvdi_internal3"
3382 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3383 (match_operand:SI 1 "const_int_operand" "i")
3384 (match_operand:SI 2 "const_int_operand" "i"))
3385 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3386 (match_operand:SI 4 "const_int_operand" "i")))]
3387 "TARGET_POWERPC64
3388 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3389 "*
3390 {
3391 int shift = INTVAL (operands[4]) & 63;
3392 int start = (INTVAL (operands[2]) & 63) - 32;
3393 int size = INTVAL (operands[1]) & 63;
3395 operands[4] = GEN_INT (64 - shift - start - size);
3396 operands[2] = GEN_INT (start);
3397 operands[1] = GEN_INT (start + size - 1);
3398 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3399 }")
3401 (define_expand "extzv"
3402 [(set (match_operand 0 "gpc_reg_operand" "")
3403 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3404 (match_operand:SI 2 "const_int_operand" "")
3405 (match_operand:SI 3 "const_int_operand" "")))]
3406 ""
3407 "
3408 {
3409 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3410 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3411 compiler if the address of the structure is taken later. */
3412 if (GET_CODE (operands[0]) == SUBREG
3413 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3414 FAIL;
3416 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3417 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3418 operands[3]));
3419 else
3420 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3421 operands[3]));
3422 DONE;
3423 }")
3425 (define_insn "extzvsi_internal"
3426 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3427 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3428 (match_operand:SI 2 "const_int_operand" "i")
3429 (match_operand:SI 3 "const_int_operand" "i")))]
3430 ""
3431 "*
3432 {
3433 int start = INTVAL (operands[3]) & 31;
3434 int size = INTVAL (operands[2]) & 31;
3436 if (start + size >= 32)
3437 operands[3] = const0_rtx;
3438 else
3439 operands[3] = GEN_INT (start + size);
3440 return \"rlwinm %0,%1,%3,%s2,31\";
3441 }"
3442 [(set_attr "type" "shift")])
3444 (define_insn "*extzvsi_internal1"
3445 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3446 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3447 (match_operand:SI 2 "const_int_operand" "i,i")
3448 (match_operand:SI 3 "const_int_operand" "i,i"))
3449 (const_int 0)))
3450 (clobber (match_scratch:SI 4 "=r,r"))]
3451 ""
3452 "*
3453 {
3454 int start = INTVAL (operands[3]) & 31;
3455 int size = INTVAL (operands[2]) & 31;
3457 /* Force split for non-cc0 compare. */
3458 if (which_alternative == 1)
3459 return \"#\";
3461 /* If the bit-field being tested fits in the upper or lower half of a
3462 word, it is possible to use andiu. or andil. to test it. This is
3463 useful because the condition register set-use delay is smaller for
3464 andi[ul]. than for rlinm. This doesn't work when the starting bit
3465 position is 0 because the LT and GT bits may be set wrong. */
3467 if ((start > 0 && start + size <= 16) || start >= 16)
3468 {
3469 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3470 - (1 << (16 - (start & 15) - size))));
3471 if (start < 16)
3472 return \"andis. %4,%1,%3\";
3473 else
3474 return \"andi. %4,%1,%3\";
3475 }
3477 if (start + size >= 32)
3478 operands[3] = const0_rtx;
3479 else
3480 operands[3] = GEN_INT (start + size);
3481 return \"rlwinm. %4,%1,%3,%s2,31\";
3482 }"
3483 [(set_attr "type" "shift")
3484 (set_attr "dot" "yes")
3485 (set_attr "length" "4,8")])
3487 (define_split
3488 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3489 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3490 (match_operand:SI 2 "const_int_operand" "")
3491 (match_operand:SI 3 "const_int_operand" ""))
3492 (const_int 0)))
3493 (clobber (match_scratch:SI 4 ""))]
3494 "reload_completed"
3495 [(set (match_dup 4)
3496 (zero_extract:SI (match_dup 1) (match_dup 2)
3497 (match_dup 3)))
3498 (set (match_dup 0)
3499 (compare:CC (match_dup 4)
3500 (const_int 0)))]
3501 "")
3503 (define_insn "*extzvsi_internal2"
3504 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3505 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3506 (match_operand:SI 2 "const_int_operand" "i,i")
3507 (match_operand:SI 3 "const_int_operand" "i,i"))
3508 (const_int 0)))
3509 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3510 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3511 ""
3512 "*
3513 {
3514 int start = INTVAL (operands[3]) & 31;
3515 int size = INTVAL (operands[2]) & 31;
3517 /* Force split for non-cc0 compare. */
3518 if (which_alternative == 1)
3519 return \"#\";
3521 /* Since we are using the output value, we can't ignore any need for
3522 a shift. The bit-field must end at the LSB. */
3523 if (start >= 16 && start + size == 32)
3524 {
3525 operands[3] = GEN_INT ((1 << size) - 1);
3526 return \"andi. %0,%1,%3\";
3527 }
3529 if (start + size >= 32)
3530 operands[3] = const0_rtx;
3531 else
3532 operands[3] = GEN_INT (start + size);
3533 return \"rlwinm. %0,%1,%3,%s2,31\";
3534 }"
3535 [(set_attr "type" "shift")
3536 (set_attr "dot" "yes")
3537 (set_attr "length" "4,8")])
3539 (define_split
3540 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3541 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3542 (match_operand:SI 2 "const_int_operand" "")
3543 (match_operand:SI 3 "const_int_operand" ""))
3544 (const_int 0)))
3545 (set (match_operand:SI 0 "gpc_reg_operand" "")
3546 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3547 "reload_completed"
3548 [(set (match_dup 0)
3549 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3550 (set (match_dup 4)
3551 (compare:CC (match_dup 0)
3552 (const_int 0)))]
3553 "")
3555 (define_insn "extzvdi_internal"
3556 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3557 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3558 (match_operand:SI 2 "const_int_operand" "i")
3559 (match_operand:SI 3 "const_int_operand" "i")))]
3560 "TARGET_POWERPC64"
3561 "*
3562 {
3563 int start = INTVAL (operands[3]) & 63;
3564 int size = INTVAL (operands[2]) & 63;
3566 if (start + size >= 64)
3567 operands[3] = const0_rtx;
3568 else
3569 operands[3] = GEN_INT (start + size);
3570 operands[2] = GEN_INT (64 - size);
3571 return \"rldicl %0,%1,%3,%2\";
3572 }"
3573 [(set_attr "type" "shift")])
3575 (define_insn "*extzvdi_internal1"
3576 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3577 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3578 (match_operand:SI 2 "const_int_operand" "i")
3579 (match_operand:SI 3 "const_int_operand" "i"))
3580 (const_int 0)))
3581 (clobber (match_scratch:DI 4 "=r"))]
3582 "TARGET_64BIT && rs6000_gen_cell_microcode"
3583 "*
3584 {
3585 int start = INTVAL (operands[3]) & 63;
3586 int size = INTVAL (operands[2]) & 63;
3588 if (start + size >= 64)
3589 operands[3] = const0_rtx;
3590 else
3591 operands[3] = GEN_INT (start + size);
3592 operands[2] = GEN_INT (64 - size);
3593 return \"rldicl. %4,%1,%3,%2\";
3594 }"
3595 [(set_attr "type" "shift")
3596 (set_attr "dot" "yes")])
3598 (define_insn "*extzvdi_internal2"
3599 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3600 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3601 (match_operand:SI 2 "const_int_operand" "i")
3602 (match_operand:SI 3 "const_int_operand" "i"))
3603 (const_int 0)))
3604 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3605 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3606 "TARGET_64BIT && rs6000_gen_cell_microcode"
3607 "*
3608 {
3609 int start = INTVAL (operands[3]) & 63;
3610 int size = INTVAL (operands[2]) & 63;
3612 if (start + size >= 64)
3613 operands[3] = const0_rtx;
3614 else
3615 operands[3] = GEN_INT (start + size);
3616 operands[2] = GEN_INT (64 - size);
3617 return \"rldicl. %0,%1,%3,%2\";
3618 }"
3619 [(set_attr "type" "shift")
3620 (set_attr "dot" "yes")])
3623 (define_insn "rotl<mode>3"
3624 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3625 (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3626 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3627 ""
3628 "rotl<wd>%I2 %0,%1,%<hH>2"
3629 [(set_attr "type" "shift")
3630 (set_attr "maybe_var_shift" "yes")])
3632 (define_insn "*rotlsi3_64"
3633 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3634 (zero_extend:DI
3635 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3636 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3637 "TARGET_POWERPC64"
3638 "rotlw%I2 %0,%1,%h2"
3639 [(set_attr "type" "shift")
3640 (set_attr "maybe_var_shift" "yes")])
3642 (define_insn_and_split "*rotl<mode>3_dot"
3643 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3644 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3645 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3646 (const_int 0)))
3647 (clobber (match_scratch:GPR 0 "=r,r"))]
3648 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3649 "@
3650 rotl<wd>%I2. %0,%1,%<hH>2
3651 #"
3652 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3653 [(set (match_dup 0)
3654 (rotate:GPR (match_dup 1)
3655 (match_dup 2)))
3656 (set (match_dup 3)
3657 (compare:CC (match_dup 0)
3658 (const_int 0)))]
3659 ""
3660 [(set_attr "type" "shift")
3661 (set_attr "maybe_var_shift" "yes")
3662 (set_attr "dot" "yes")
3663 (set_attr "length" "4,8")])
3665 (define_insn_and_split "*rotl<mode>3_dot2"
3666 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3667 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3668 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3669 (const_int 0)))
3670 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3671 (rotate:GPR (match_dup 1)
3672 (match_dup 2)))]
3673 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3674 "@
3675 rotl<wd>%I2. %0,%1,%<hH>2
3676 #"
3677 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3678 [(set (match_dup 0)
3679 (rotate:GPR (match_dup 1)
3680 (match_dup 2)))
3681 (set (match_dup 3)
3682 (compare:CC (match_dup 0)
3683 (const_int 0)))]
3684 ""
3685 [(set_attr "type" "shift")
3686 (set_attr "maybe_var_shift" "yes")
3687 (set_attr "dot" "yes")
3688 (set_attr "length" "4,8")])
3691 (define_insn "*rotlsi3_internal4"
3692 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3693 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3694 (match_operand:SI 2 "reg_or_cint_operand" "rn"))
3695 (match_operand:SI 3 "mask_operand" "n")))]
3696 ""
3697 "rlw%I2nm %0,%1,%h2,%m3,%M3"
3698 [(set_attr "type" "shift")
3699 (set_attr "maybe_var_shift" "yes")])
3701 (define_insn "*rotlsi3_internal5"
3702 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3703 (compare:CC (and:SI
3704 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3705 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3706 (match_operand:SI 3 "mask_operand" "n,n"))
3707 (const_int 0)))
3708 (clobber (match_scratch:SI 4 "=r,r"))]
3709 ""
3710 "@
3711 rlw%I2nm. %4,%1,%h2,%m3,%M3
3712 #"
3713 [(set_attr "type" "shift")
3714 (set_attr "maybe_var_shift" "yes")
3715 (set_attr "dot" "yes")
3716 (set_attr "length" "4,8")])
3718 (define_split
3719 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3720 (compare:CC (and:SI
3721 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3722 (match_operand:SI 2 "reg_or_cint_operand" ""))
3723 (match_operand:SI 3 "mask_operand" ""))
3724 (const_int 0)))
3725 (clobber (match_scratch:SI 4 ""))]
3726 "reload_completed"
3727 [(set (match_dup 4)
3728 (and:SI (rotate:SI (match_dup 1)
3729 (match_dup 2))
3730 (match_dup 3)))
3731 (set (match_dup 0)
3732 (compare:CC (match_dup 4)
3733 (const_int 0)))]
3734 "")
3736 (define_insn "*rotlsi3_internal6"
3737 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3738 (compare:CC (and:SI
3739 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3740 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3741 (match_operand:SI 3 "mask_operand" "n,n"))
3742 (const_int 0)))
3743 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3744 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3745 ""
3746 "@
3747 rlw%I2nm. %0,%1,%h2,%m3,%M3
3748 #"
3749 [(set_attr "type" "shift")
3750 (set_attr "maybe_var_shift" "yes")
3751 (set_attr "dot" "yes")
3752 (set_attr "length" "4,8")])
3754 (define_split
3755 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3756 (compare:CC (and:SI
3757 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3758 (match_operand:SI 2 "reg_or_cint_operand" ""))
3759 (match_operand:SI 3 "mask_operand" ""))
3760 (const_int 0)))
3761 (set (match_operand:SI 0 "gpc_reg_operand" "")
3762 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3763 "reload_completed"
3764 [(set (match_dup 0)
3765 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3766 (set (match_dup 4)
3767 (compare:CC (match_dup 0)
3768 (const_int 0)))]
3769 "")
3771 (define_insn "*rotlsi3_internal7le"
3772 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3773 (zero_extend:SI
3774 (subreg:QI
3775 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3776 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3777 "!BYTES_BIG_ENDIAN"
3778 "rlw%I2nm %0,%1,%h2,0xff"
3779 [(set (attr "cell_micro")
3780 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3781 (const_string "not")
3782 (const_string "always")))
3783 (set_attr "type" "shift")])
3785 (define_insn "*rotlsi3_internal7be"
3786 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3787 (zero_extend:SI
3788 (subreg:QI
3789 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3790 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3791 "BYTES_BIG_ENDIAN"
3792 "rlw%I2nm %0,%1,%h2,0xff"
3793 [(set (attr "cell_micro")
3794 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3795 (const_string "not")
3796 (const_string "always")))
3797 (set_attr "type" "shift")])
3799 (define_insn "*rotlsi3_internal8le"
3800 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3801 (compare:CC (zero_extend:SI
3802 (subreg:QI
3803 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3804 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3805 (const_int 0)))
3806 (clobber (match_scratch:SI 3 "=r,r"))]
3807 "!BYTES_BIG_ENDIAN"
3808 "@
3809 rlw%I2nm. %3,%1,%h2,0xff
3810 #"
3811 [(set_attr "type" "shift")
3812 (set_attr "maybe_var_shift" "yes")
3813 (set_attr "dot" "yes")
3814 (set_attr "length" "4,8")])
3816 (define_insn "*rotlsi3_internal8be"
3817 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3818 (compare:CC (zero_extend:SI
3819 (subreg:QI
3820 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3821 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3822 (const_int 0)))
3823 (clobber (match_scratch:SI 3 "=r,r"))]
3824 "BYTES_BIG_ENDIAN"
3825 "@
3826 rlw%I2nm. %3,%1,%h2,0xff
3827 #"
3828 [(set_attr "type" "shift")
3829 (set_attr "maybe_var_shift" "yes")
3830 (set_attr "dot" "yes")
3831 (set_attr "length" "4,8")])
3833 (define_split
3834 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3835 (compare:CC (zero_extend:SI
3836 (subreg:QI
3837 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3838 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3839 (const_int 0)))
3840 (clobber (match_scratch:SI 3 ""))]
3841 "!BYTES_BIG_ENDIAN && reload_completed"
3842 [(set (match_dup 3)
3843 (zero_extend:SI (subreg:QI
3844 (rotate:SI (match_dup 1)
3845 (match_dup 2)) 0)))
3846 (set (match_dup 0)
3847 (compare:CC (match_dup 3)
3848 (const_int 0)))]
3849 "")
3851 (define_split
3852 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3853 (compare:CC (zero_extend:SI
3854 (subreg:QI
3855 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3856 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3857 (const_int 0)))
3858 (clobber (match_scratch:SI 3 ""))]
3859 "BYTES_BIG_ENDIAN && reload_completed"
3860 [(set (match_dup 3)
3861 (zero_extend:SI (subreg:QI
3862 (rotate:SI (match_dup 1)
3863 (match_dup 2)) 3)))
3864 (set (match_dup 0)
3865 (compare:CC (match_dup 3)
3866 (const_int 0)))]
3867 "")
3869 (define_insn "*rotlsi3_internal9le"
3870 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3871 (compare:CC (zero_extend:SI
3872 (subreg:QI
3873 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3874 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3875 (const_int 0)))
3876 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3877 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3878 "!BYTES_BIG_ENDIAN"
3879 "@
3880 rlw%I2nm. %0,%1,%h2,0xff
3881 #"
3882 [(set_attr "type" "shift")
3883 (set_attr "maybe_var_shift" "yes")
3884 (set_attr "dot" "yes")
3885 (set_attr "length" "4,8")])
3887 (define_insn "*rotlsi3_internal9be"
3888 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3889 (compare:CC (zero_extend:SI
3890 (subreg:QI
3891 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3892 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
3893 (const_int 0)))
3894 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3895 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3896 "BYTES_BIG_ENDIAN"
3897 "@
3898 rlw%I2nm. %0,%1,%h2,0xff
3899 #"
3900 [(set_attr "type" "shift")
3901 (set_attr "maybe_var_shift" "yes")
3902 (set_attr "dot" "yes")
3903 (set_attr "length" "4,8")])
3905 (define_split
3906 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3907 (compare:CC (zero_extend:SI
3908 (subreg:QI
3909 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3910 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3911 (const_int 0)))
3912 (set (match_operand:SI 0 "gpc_reg_operand" "")
3913 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3914 "!BYTES_BIG_ENDIAN && reload_completed"
3915 [(set (match_dup 0)
3916 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3917 (set (match_dup 3)
3918 (compare:CC (match_dup 0)
3919 (const_int 0)))]
3920 "")
3922 (define_split
3923 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3924 (compare:CC (zero_extend:SI
3925 (subreg:QI
3926 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3927 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
3928 (const_int 0)))
3929 (set (match_operand:SI 0 "gpc_reg_operand" "")
3930 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
3931 "BYTES_BIG_ENDIAN && reload_completed"
3932 [(set (match_dup 0)
3933 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
3934 (set (match_dup 3)
3935 (compare:CC (match_dup 0)
3936 (const_int 0)))]
3937 "")
3939 (define_insn "*rotlsi3_internal10le"
3940 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3941 (zero_extend:SI
3942 (subreg:HI
3943 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3944 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))]
3945 "!BYTES_BIG_ENDIAN"
3946 "rlw%I2nm %0,%1,%h2,0xffff"
3947 [(set_attr "type" "shift")
3948 (set_attr "maybe_var_shift" "yes")])
3950 (define_insn "*rotlsi3_internal10be"
3951 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3952 (zero_extend:SI
3953 (subreg:HI
3954 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3955 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))]
3956 "BYTES_BIG_ENDIAN"
3957 "rlw%I2nm %0,%1,%h2,0xffff"
3958 [(set_attr "type" "shift")
3959 (set_attr "maybe_var_shift" "yes")])
3961 (define_insn "*rotlsi3_internal11le"
3962 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3963 (compare:CC (zero_extend:SI
3964 (subreg:HI
3965 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3966 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
3967 (const_int 0)))
3968 (clobber (match_scratch:SI 3 "=r,r"))]
3969 "!BYTES_BIG_ENDIAN"
3970 "@
3971 rlw%I2nm. %3,%1,%h2,0xffff
3972 #"
3973 [(set_attr "type" "shift")
3974 (set_attr "maybe_var_shift" "yes")
3975 (set_attr "dot" "yes")
3976 (set_attr "length" "4,8")])
3978 (define_insn "*rotlsi3_internal11be"
3979 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3980 (compare:CC (zero_extend:SI
3981 (subreg:HI
3982 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3983 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
3984 (const_int 0)))
3985 (clobber (match_scratch:SI 3 "=r,r"))]
3986 "BYTES_BIG_ENDIAN"
3987 "@
3988 rlw%I2nm. %3,%1,%h2,0xffff
3989 #"
3990 [(set_attr "type" "shift")
3991 (set_attr "maybe_var_shift" "yes")
3992 (set_attr "dot" "yes")
3993 (set_attr "length" "4,8")])
3995 (define_split
3996 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3997 (compare:CC (zero_extend:SI
3998 (subreg:HI
3999 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4000 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4001 (const_int 0)))
4002 (clobber (match_scratch:SI 3 ""))]
4003 "!BYTES_BIG_ENDIAN && reload_completed"
4004 [(set (match_dup 3)
4005 (zero_extend:SI (subreg:HI
4006 (rotate:SI (match_dup 1)
4007 (match_dup 2)) 0)))
4008 (set (match_dup 0)
4009 (compare:CC (match_dup 3)
4010 (const_int 0)))]
4011 "")
4013 (define_split
4014 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4015 (compare:CC (zero_extend:SI
4016 (subreg:HI
4017 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4018 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4019 (const_int 0)))
4020 (clobber (match_scratch:SI 3 ""))]
4021 "BYTES_BIG_ENDIAN && reload_completed"
4022 [(set (match_dup 3)
4023 (zero_extend:SI (subreg:HI
4024 (rotate:SI (match_dup 1)
4025 (match_dup 2)) 2)))
4026 (set (match_dup 0)
4027 (compare:CC (match_dup 3)
4028 (const_int 0)))]
4029 "")
4031 (define_insn "*rotlsi3_internal12le"
4032 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4033 (compare:CC (zero_extend:SI
4034 (subreg:HI
4035 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4036 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4037 (const_int 0)))
4038 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4039 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4040 "!BYTES_BIG_ENDIAN"
4041 "@
4042 rlw%I2nm. %0,%1,%h2,0xffff
4043 #"
4044 [(set_attr "type" "shift")
4045 (set_attr "maybe_var_shift" "yes")
4046 (set_attr "dot" "yes")
4047 (set_attr "length" "4,8")])
4049 (define_insn "*rotlsi3_internal12be"
4050 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4051 (compare:CC (zero_extend:SI
4052 (subreg:HI
4053 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4054 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
4055 (const_int 0)))
4056 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4057 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4058 "BYTES_BIG_ENDIAN"
4059 "@
4060 rlw%I2nm. %0,%1,%h2,0xffff
4061 #"
4062 [(set_attr "type" "shift")
4063 (set_attr "maybe_var_shift" "yes")
4064 (set_attr "dot" "yes")
4065 (set_attr "length" "4,8")])
4067 (define_split
4068 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4069 (compare:CC (zero_extend:SI
4070 (subreg:HI
4071 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4072 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4073 (const_int 0)))
4074 (set (match_operand:SI 0 "gpc_reg_operand" "")
4075 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4076 "!BYTES_BIG_ENDIAN && reload_completed"
4077 [(set (match_dup 0)
4078 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4079 (set (match_dup 3)
4080 (compare:CC (match_dup 0)
4081 (const_int 0)))]
4082 "")
4084 (define_split
4085 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4086 (compare:CC (zero_extend:SI
4087 (subreg:HI
4088 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4089 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4090 (const_int 0)))
4091 (set (match_operand:SI 0 "gpc_reg_operand" "")
4092 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4093 "BYTES_BIG_ENDIAN && reload_completed"
4094 [(set (match_dup 0)
4095 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4096 (set (match_dup 3)
4097 (compare:CC (match_dup 0)
4098 (const_int 0)))]
4099 "")
4102 (define_insn "ashl<mode>3"
4103 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4104 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4105 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4106 ""
4107 "sl<wd>%I2 %0,%1,%<hH>2"
4108 [(set_attr "type" "shift")
4109 (set_attr "maybe_var_shift" "yes")])
4111 (define_insn "*ashlsi3_64"
4112 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4113 (zero_extend:DI
4114 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4115 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4116 "TARGET_POWERPC64"
4117 "slw%I2 %0,%1,%h2"
4118 [(set_attr "type" "shift")
4119 (set_attr "maybe_var_shift" "yes")])
4121 (define_insn_and_split "*ashl<mode>3_dot"
4122 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4123 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4124 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4125 (const_int 0)))
4126 (clobber (match_scratch:GPR 0 "=r,r"))]
4127 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4128 "@
4129 sl<wd>%I2. %0,%1,%<hH>2
4130 #"
4131 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4132 [(set (match_dup 0)
4133 (ashift:GPR (match_dup 1)
4134 (match_dup 2)))
4135 (set (match_dup 3)
4136 (compare:CC (match_dup 0)
4137 (const_int 0)))]
4138 ""
4139 [(set_attr "type" "shift")
4140 (set_attr "maybe_var_shift" "yes")
4141 (set_attr "dot" "yes")
4142 (set_attr "length" "4,8")])
4144 (define_insn_and_split "*ashl<mode>3_dot2"
4145 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4146 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4147 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4148 (const_int 0)))
4149 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4150 (ashift:GPR (match_dup 1)
4151 (match_dup 2)))]
4152 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4153 "@
4154 sl<wd>%I2. %0,%1,%<hH>2
4155 #"
4156 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4157 [(set (match_dup 0)
4158 (ashift:GPR (match_dup 1)
4159 (match_dup 2)))
4160 (set (match_dup 3)
4161 (compare:CC (match_dup 0)
4162 (const_int 0)))]
4163 ""
4164 [(set_attr "type" "shift")
4165 (set_attr "maybe_var_shift" "yes")
4166 (set_attr "dot" "yes")
4167 (set_attr "length" "4,8")])
4170 (define_insn "rlwinm"
4171 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4172 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4173 (match_operand:SI 2 "const_int_operand" "i"))
4174 (match_operand:SI 3 "mask_operand" "n")))]
4175 "includes_lshift_p (operands[2], operands[3])"
4176 "rlwinm %0,%1,%h2,%m3,%M3"
4177 [(set_attr "type" "shift")])
4179 (define_insn ""
4180 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4181 (compare:CC
4182 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4183 (match_operand:SI 2 "const_int_operand" "i,i"))
4184 (match_operand:SI 3 "mask_operand" "n,n"))
4185 (const_int 0)))
4186 (clobber (match_scratch:SI 4 "=r,r"))]
4187 "includes_lshift_p (operands[2], operands[3])"
4188 "@
4189 rlwinm. %4,%1,%h2,%m3,%M3
4190 #"
4191 [(set_attr "type" "shift")
4192 (set_attr "dot" "yes")
4193 (set_attr "length" "4,8")])
4195 (define_split
4196 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4197 (compare:CC
4198 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4199 (match_operand:SI 2 "const_int_operand" ""))
4200 (match_operand:SI 3 "mask_operand" ""))
4201 (const_int 0)))
4202 (clobber (match_scratch:SI 4 ""))]
4203 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4204 [(set (match_dup 4)
4205 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4206 (match_dup 3)))
4207 (set (match_dup 0)
4208 (compare:CC (match_dup 4)
4209 (const_int 0)))]
4210 "")
4212 (define_insn ""
4213 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4214 (compare:CC
4215 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4216 (match_operand:SI 2 "const_int_operand" "i,i"))
4217 (match_operand:SI 3 "mask_operand" "n,n"))
4218 (const_int 0)))
4219 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4220 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4221 "includes_lshift_p (operands[2], operands[3])"
4222 "@
4223 rlwinm. %0,%1,%h2,%m3,%M3
4224 #"
4225 [(set_attr "type" "shift")
4226 (set_attr "dot" "yes")
4227 (set_attr "length" "4,8")])
4229 (define_split
4230 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4231 (compare:CC
4232 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4233 (match_operand:SI 2 "const_int_operand" ""))
4234 (match_operand:SI 3 "mask_operand" ""))
4235 (const_int 0)))
4236 (set (match_operand:SI 0 "gpc_reg_operand" "")
4237 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4238 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4239 [(set (match_dup 0)
4240 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4241 (set (match_dup 4)
4242 (compare:CC (match_dup 0)
4243 (const_int 0)))]
4244 "")
4247 (define_insn "lshr<mode>3"
4248 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4249 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4250 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4251 ""
4252 "sr<wd>%I2 %0,%1,%<hH>2"
4253 [(set_attr "type" "shift")
4254 (set_attr "maybe_var_shift" "yes")])
4256 (define_insn "*lshrsi3_64"
4257 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4258 (zero_extend:DI
4259 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4260 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4261 "TARGET_POWERPC64"
4262 "srw%I2 %0,%1,%h2"
4263 [(set_attr "type" "shift")
4264 (set_attr "maybe_var_shift" "yes")])
4266 (define_insn_and_split "*lshr<mode>3_dot"
4267 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4268 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4269 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4270 (const_int 0)))
4271 (clobber (match_scratch:GPR 0 "=r,r"))]
4272 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4273 "@
4274 sr<wd>%I2. %0,%1,%<hH>2
4275 #"
4276 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4277 [(set (match_dup 0)
4278 (lshiftrt:GPR (match_dup 1)
4279 (match_dup 2)))
4280 (set (match_dup 3)
4281 (compare:CC (match_dup 0)
4282 (const_int 0)))]
4283 ""
4284 [(set_attr "type" "shift")
4285 (set_attr "maybe_var_shift" "yes")
4286 (set_attr "dot" "yes")
4287 (set_attr "length" "4,8")])
4289 (define_insn_and_split "*lshr<mode>3_dot2"
4290 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4291 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4292 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4293 (const_int 0)))
4294 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4295 (lshiftrt:GPR (match_dup 1)
4296 (match_dup 2)))]
4297 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4298 "@
4299 sr<wd>%I2. %0,%1,%<hH>2
4300 #"
4301 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4302 [(set (match_dup 0)
4303 (lshiftrt:GPR (match_dup 1)
4304 (match_dup 2)))
4305 (set (match_dup 3)
4306 (compare:CC (match_dup 0)
4307 (const_int 0)))]
4308 ""
4309 [(set_attr "type" "shift")
4310 (set_attr "maybe_var_shift" "yes")
4311 (set_attr "dot" "yes")
4312 (set_attr "length" "4,8")])
4315 (define_insn ""
4316 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4317 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4318 (match_operand:SI 2 "const_int_operand" "i"))
4319 (match_operand:SI 3 "mask_operand" "n")))]
4320 "includes_rshift_p (operands[2], operands[3])"
4321 "rlwinm %0,%1,%s2,%m3,%M3"
4322 [(set_attr "type" "shift")])
4324 (define_insn ""
4325 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4326 (compare:CC
4327 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4328 (match_operand:SI 2 "const_int_operand" "i,i"))
4329 (match_operand:SI 3 "mask_operand" "n,n"))
4330 (const_int 0)))
4331 (clobber (match_scratch:SI 4 "=r,r"))]
4332 "includes_rshift_p (operands[2], operands[3])"
4333 "@
4334 rlwinm. %4,%1,%s2,%m3,%M3
4335 #"
4336 [(set_attr "type" "shift")
4337 (set_attr "dot" "yes")
4338 (set_attr "length" "4,8")])
4340 (define_split
4341 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4342 (compare:CC
4343 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4344 (match_operand:SI 2 "const_int_operand" ""))
4345 (match_operand:SI 3 "mask_operand" ""))
4346 (const_int 0)))
4347 (clobber (match_scratch:SI 4 ""))]
4348 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4349 [(set (match_dup 4)
4350 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4351 (match_dup 3)))
4352 (set (match_dup 0)
4353 (compare:CC (match_dup 4)
4354 (const_int 0)))]
4355 "")
4357 (define_insn ""
4358 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4359 (compare:CC
4360 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4361 (match_operand:SI 2 "const_int_operand" "i,i"))
4362 (match_operand:SI 3 "mask_operand" "n,n"))
4363 (const_int 0)))
4364 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4365 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4366 "includes_rshift_p (operands[2], operands[3])"
4367 "@
4368 rlwinm. %0,%1,%s2,%m3,%M3
4369 #"
4370 [(set_attr "type" "shift")
4371 (set_attr "dot" "yes")
4372 (set_attr "length" "4,8")])
4374 (define_split
4375 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4376 (compare:CC
4377 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4378 (match_operand:SI 2 "const_int_operand" ""))
4379 (match_operand:SI 3 "mask_operand" ""))
4380 (const_int 0)))
4381 (set (match_operand:SI 0 "gpc_reg_operand" "")
4382 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4383 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4384 [(set (match_dup 0)
4385 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4386 (set (match_dup 4)
4387 (compare:CC (match_dup 0)
4388 (const_int 0)))]
4389 "")
4391 (define_insn "*lshiftrt_internal1le"
4392 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4393 (zero_extend:SI
4394 (subreg:QI
4395 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4396 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4397 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4398 "rlwinm %0,%1,%s2,0xff"
4399 [(set_attr "type" "shift")])
4401 (define_insn "*lshiftrt_internal1be"
4402 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4403 (zero_extend:SI
4404 (subreg:QI
4405 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4406 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4407 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4408 "rlwinm %0,%1,%s2,0xff"
4409 [(set_attr "type" "shift")])
4411 (define_insn "*lshiftrt_internal2le"
4412 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4413 (compare:CC
4414 (zero_extend:SI
4415 (subreg:QI
4416 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4417 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4418 (const_int 0)))
4419 (clobber (match_scratch:SI 3 "=r,r"))]
4420 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4421 "@
4422 rlwinm. %3,%1,%s2,0xff
4423 #"
4424 [(set_attr "type" "shift")
4425 (set_attr "dot" "yes")
4426 (set_attr "length" "4,8")])
4428 (define_insn "*lshiftrt_internal2be"
4429 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4430 (compare:CC
4431 (zero_extend:SI
4432 (subreg:QI
4433 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4434 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4435 (const_int 0)))
4436 (clobber (match_scratch:SI 3 "=r,r"))]
4437 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4438 "@
4439 rlwinm. %3,%1,%s2,0xff
4440 #"
4441 [(set_attr "type" "shift")
4442 (set_attr "dot" "yes")
4443 (set_attr "length" "4,8")])
4445 (define_split
4446 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4447 (compare:CC
4448 (zero_extend:SI
4449 (subreg:QI
4450 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4451 (match_operand:SI 2 "const_int_operand" "")) 0))
4452 (const_int 0)))
4453 (clobber (match_scratch:SI 3 ""))]
4454 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4455 [(set (match_dup 3)
4456 (zero_extend:SI (subreg:QI
4457 (lshiftrt:SI (match_dup 1)
4458 (match_dup 2)) 0)))
4459 (set (match_dup 0)
4460 (compare:CC (match_dup 3)
4461 (const_int 0)))]
4462 "")
4464 (define_split
4465 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4466 (compare:CC
4467 (zero_extend:SI
4468 (subreg:QI
4469 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4470 (match_operand:SI 2 "const_int_operand" "")) 3))
4471 (const_int 0)))
4472 (clobber (match_scratch:SI 3 ""))]
4473 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4474 [(set (match_dup 3)
4475 (zero_extend:SI (subreg:QI
4476 (lshiftrt:SI (match_dup 1)
4477 (match_dup 2)) 3)))
4478 (set (match_dup 0)
4479 (compare:CC (match_dup 3)
4480 (const_int 0)))]
4481 "")
4483 (define_insn "*lshiftrt_internal3le"
4484 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4485 (compare:CC
4486 (zero_extend:SI
4487 (subreg:QI
4488 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4489 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4490 (const_int 0)))
4491 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4492 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4493 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4494 "@
4495 rlwinm. %0,%1,%s2,0xff
4496 #"
4497 [(set_attr "type" "shift")
4498 (set_attr "dot" "yes")
4499 (set_attr "length" "4,8")])
4501 (define_insn "*lshiftrt_internal3be"
4502 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4503 (compare:CC
4504 (zero_extend:SI
4505 (subreg:QI
4506 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4507 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4508 (const_int 0)))
4509 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4510 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4511 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4512 "@
4513 rlwinm. %0,%1,%s2,0xff
4514 #"
4515 [(set_attr "type" "shift")
4516 (set_attr "dot" "yes")
4517 (set_attr "length" "4,8")])
4519 (define_split
4520 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4521 (compare:CC
4522 (zero_extend:SI
4523 (subreg:QI
4524 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4525 (match_operand:SI 2 "const_int_operand" "")) 0))
4526 (const_int 0)))
4527 (set (match_operand:SI 0 "gpc_reg_operand" "")
4528 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4529 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4530 [(set (match_dup 0)
4531 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4532 (set (match_dup 3)
4533 (compare:CC (match_dup 0)
4534 (const_int 0)))]
4535 "")
4537 (define_split
4538 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4539 (compare:CC
4540 (zero_extend:SI
4541 (subreg:QI
4542 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4543 (match_operand:SI 2 "const_int_operand" "")) 3))
4544 (const_int 0)))
4545 (set (match_operand:SI 0 "gpc_reg_operand" "")
4546 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4547 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4548 [(set (match_dup 0)
4549 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4550 (set (match_dup 3)
4551 (compare:CC (match_dup 0)
4552 (const_int 0)))]
4553 "")
4555 (define_insn "*lshiftrt_internal4le"
4556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4557 (zero_extend:SI
4558 (subreg:HI
4559 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4560 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4561 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4562 "rlwinm %0,%1,%s2,0xffff"
4563 [(set_attr "type" "shift")])
4565 (define_insn "*lshiftrt_internal4be"
4566 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4567 (zero_extend:SI
4568 (subreg:HI
4569 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4570 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4571 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4572 "rlwinm %0,%1,%s2,0xffff"
4573 [(set_attr "type" "shift")])
4575 (define_insn "*lshiftrt_internal5le"
4576 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4577 (compare:CC
4578 (zero_extend:SI
4579 (subreg:HI
4580 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4581 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4582 (const_int 0)))
4583 (clobber (match_scratch:SI 3 "=r,r"))]
4584 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4585 "@
4586 rlwinm. %3,%1,%s2,0xffff
4587 #"
4588 [(set_attr "type" "shift")
4589 (set_attr "dot" "yes")
4590 (set_attr "length" "4,8")])
4592 (define_insn "*lshiftrt_internal5be"
4593 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4594 (compare:CC
4595 (zero_extend:SI
4596 (subreg:HI
4597 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4598 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4599 (const_int 0)))
4600 (clobber (match_scratch:SI 3 "=r,r"))]
4601 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4602 "@
4603 rlwinm. %3,%1,%s2,0xffff
4604 #"
4605 [(set_attr "type" "shift")
4606 (set_attr "dot" "yes")
4607 (set_attr "length" "4,8")])
4609 (define_split
4610 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4611 (compare:CC
4612 (zero_extend:SI
4613 (subreg:HI
4614 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4615 (match_operand:SI 2 "const_int_operand" "")) 0))
4616 (const_int 0)))
4617 (clobber (match_scratch:SI 3 ""))]
4618 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4619 [(set (match_dup 3)
4620 (zero_extend:SI (subreg:HI
4621 (lshiftrt:SI (match_dup 1)
4622 (match_dup 2)) 0)))
4623 (set (match_dup 0)
4624 (compare:CC (match_dup 3)
4625 (const_int 0)))]
4626 "")
4628 (define_split
4629 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4630 (compare:CC
4631 (zero_extend:SI
4632 (subreg:HI
4633 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4634 (match_operand:SI 2 "const_int_operand" "")) 2))
4635 (const_int 0)))
4636 (clobber (match_scratch:SI 3 ""))]
4637 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4638 [(set (match_dup 3)
4639 (zero_extend:SI (subreg:HI
4640 (lshiftrt:SI (match_dup 1)
4641 (match_dup 2)) 2)))
4642 (set (match_dup 0)
4643 (compare:CC (match_dup 3)
4644 (const_int 0)))]
4645 "")
4647 (define_insn "*lshiftrt_internal5le"
4648 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4649 (compare:CC
4650 (zero_extend:SI
4651 (subreg:HI
4652 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4653 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4654 (const_int 0)))
4655 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4656 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4657 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4658 "@
4659 rlwinm. %0,%1,%s2,0xffff
4660 #"
4661 [(set_attr "type" "shift")
4662 (set_attr "dot" "yes")
4663 (set_attr "length" "4,8")])
4665 (define_insn "*lshiftrt_internal5be"
4666 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4667 (compare:CC
4668 (zero_extend:SI
4669 (subreg:HI
4670 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4671 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4672 (const_int 0)))
4673 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4674 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4675 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4676 "@
4677 rlwinm. %0,%1,%s2,0xffff
4678 #"
4679 [(set_attr "type" "shift")
4680 (set_attr "dot" "yes")
4681 (set_attr "length" "4,8")])
4683 (define_split
4684 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4685 (compare:CC
4686 (zero_extend:SI
4687 (subreg:HI
4688 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4689 (match_operand:SI 2 "const_int_operand" "")) 0))
4690 (const_int 0)))
4691 (set (match_operand:SI 0 "gpc_reg_operand" "")
4692 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4693 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4694 [(set (match_dup 0)
4695 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4696 (set (match_dup 3)
4697 (compare:CC (match_dup 0)
4698 (const_int 0)))]
4699 "")
4701 (define_split
4702 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4703 (compare:CC
4704 (zero_extend:SI
4705 (subreg:HI
4706 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4707 (match_operand:SI 2 "const_int_operand" "")) 2))
4708 (const_int 0)))
4709 (set (match_operand:SI 0 "gpc_reg_operand" "")
4710 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4711 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4712 [(set (match_dup 0)
4713 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4714 (set (match_dup 3)
4715 (compare:CC (match_dup 0)
4716 (const_int 0)))]
4717 "")
4720 (define_expand "ashr<mode>3"
4721 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4722 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
4723 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4724 ""
4725 {
4726 /* The generic code does not generate optimal code for the low word
4727 (it should be a rlwimi and a rot). Until we have target code to
4728 solve this generically, keep this expander. */
4730 if (<MODE>mode == DImode && !TARGET_POWERPC64)
4731 {
4732 if (CONST_INT_P (operands[2]))
4733 {
4734 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
4735 DONE;
4736 }
4737 else
4738 FAIL;
4739 }
4740 })
4742 (define_insn "*ashr<mode>3"
4743 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4744 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4745 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4746 ""
4747 "sra<wd>%I2 %0,%1,%<hH>2"
4748 [(set_attr "type" "shift")
4749 (set_attr "maybe_var_shift" "yes")])
4751 (define_insn "*ashrsi3_64"
4752 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4753 (sign_extend:DI
4754 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4755 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4756 "TARGET_POWERPC64"
4757 "sraw%I2 %0,%1,%h2"
4758 [(set_attr "type" "shift")
4759 (set_attr "maybe_var_shift" "yes")])
4761 (define_insn_and_split "*ashr<mode>3_dot"
4762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4763 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4764 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4765 (const_int 0)))
4766 (clobber (match_scratch:GPR 0 "=r,r"))]
4767 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4768 "@
4769 sra<wd>%I2. %0,%1,%<hH>2
4770 #"
4771 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4772 [(set (match_dup 0)
4773 (ashiftrt:GPR (match_dup 1)
4774 (match_dup 2)))
4775 (set (match_dup 3)
4776 (compare:CC (match_dup 0)
4777 (const_int 0)))]
4778 ""
4779 [(set_attr "type" "shift")
4780 (set_attr "maybe_var_shift" "yes")
4781 (set_attr "dot" "yes")
4782 (set_attr "length" "4,8")])
4784 (define_insn_and_split "*ashr<mode>3_dot2"
4785 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4786 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4787 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4788 (const_int 0)))
4789 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4790 (ashiftrt:GPR (match_dup 1)
4791 (match_dup 2)))]
4792 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4793 "@
4794 sra<wd>%I2. %0,%1,%<hH>2
4795 #"
4796 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4797 [(set (match_dup 0)
4798 (ashiftrt:GPR (match_dup 1)
4799 (match_dup 2)))
4800 (set (match_dup 3)
4801 (compare:CC (match_dup 0)
4802 (const_int 0)))]
4803 ""
4804 [(set_attr "type" "shift")
4805 (set_attr "maybe_var_shift" "yes")
4806 (set_attr "dot" "yes")
4807 (set_attr "length" "4,8")])
4808 \f
4809 ;; Builtins to replace a division to generate FRE reciprocal estimate
4810 ;; instructions and the necessary fixup instructions
4811 (define_expand "recip<mode>3"
4812 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4813 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4814 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4815 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4816 {
4817 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4818 DONE;
4819 })
4821 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4822 ;; hardware division. This is only done before register allocation and with
4823 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4824 (define_split
4825 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4826 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4827 (match_operand 2 "gpc_reg_operand" "")))]
4828 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4829 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4830 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4831 [(const_int 0)]
4832 {
4833 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4834 DONE;
4835 })
4837 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4838 ;; appropriate fixup.
4839 (define_expand "rsqrt<mode>2"
4840 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4841 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4842 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4843 {
4844 rs6000_emit_swrsqrt (operands[0], operands[1]);
4845 DONE;
4846 })
4847 \f
4848 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
4849 ;; modes here, and also add in conditional vsx/power8-vector support to access
4850 ;; values in the traditional Altivec registers if the appropriate
4851 ;; -mupper-regs-{df,sf} option is enabled.
4853 (define_expand "abs<mode>2"
4854 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4855 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4856 "TARGET_<MODE>_INSN"
4857 "")
4859 (define_insn "*abs<mode>2_fpr"
4860 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4861 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4862 "TARGET_<MODE>_FPR"
4863 "@
4864 fabs %0,%1
4865 xsabsdp %x0,%x1"
4866 [(set_attr "type" "fp")
4867 (set_attr "fp_type" "fp_addsub_<Fs>")])
4869 (define_insn "*nabs<mode>2_fpr"
4870 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4871 (neg:SFDF
4872 (abs:SFDF
4873 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
4874 "TARGET_<MODE>_FPR"
4875 "@
4876 fnabs %0,%1
4877 xsnabsdp %x0,%x1"
4878 [(set_attr "type" "fp")
4879 (set_attr "fp_type" "fp_addsub_<Fs>")])
4881 (define_expand "neg<mode>2"
4882 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4883 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4884 "TARGET_<MODE>_INSN"
4885 "")
4887 (define_insn "*neg<mode>2_fpr"
4888 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4889 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4890 "TARGET_<MODE>_FPR"
4891 "@
4892 fneg %0,%1
4893 xsnegdp %x0,%x1"
4894 [(set_attr "type" "fp")
4895 (set_attr "fp_type" "fp_addsub_<Fs>")])
4897 (define_expand "add<mode>3"
4898 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4899 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4900 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4901 "TARGET_<MODE>_INSN"
4902 "")
4904 (define_insn "*add<mode>3_fpr"
4905 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4906 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4907 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4908 "TARGET_<MODE>_FPR"
4909 "@
4910 fadd<Ftrad> %0,%1,%2
4911 xsadd<Fvsx> %x0,%x1,%x2"
4912 [(set_attr "type" "fp")
4913 (set_attr "fp_type" "fp_addsub_<Fs>")])
4915 (define_expand "sub<mode>3"
4916 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4917 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4918 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4919 "TARGET_<MODE>_INSN"
4920 "")
4922 (define_insn "*sub<mode>3_fpr"
4923 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4924 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4925 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4926 "TARGET_<MODE>_FPR"
4927 "@
4928 fsub<Ftrad> %0,%1,%2
4929 xssub<Fvsx> %x0,%x1,%x2"
4930 [(set_attr "type" "fp")
4931 (set_attr "fp_type" "fp_addsub_<Fs>")])
4933 (define_expand "mul<mode>3"
4934 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4935 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4936 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4937 "TARGET_<MODE>_INSN"
4938 "")
4940 (define_insn "*mul<mode>3_fpr"
4941 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4942 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
4943 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4944 "TARGET_<MODE>_FPR"
4945 "@
4946 fmul<Ftrad> %0,%1,%2
4947 xsmul<Fvsx> %x0,%x1,%x2"
4948 [(set_attr "type" "dmul")
4949 (set_attr "fp_type" "fp_mul_<Fs>")])
4951 (define_expand "div<mode>3"
4952 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4953 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4954 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4955 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
4956 "")
4958 (define_insn "*div<mode>3_fpr"
4959 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4960 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4961 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
4962 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
4963 "@
4964 fdiv<Ftrad> %0,%1,%2
4965 xsdiv<Fvsx> %x0,%x1,%x2"
4966 [(set_attr "type" "<Fs>div")
4967 (set_attr "fp_type" "fp_div_<Fs>")])
4969 (define_insn "sqrt<mode>2"
4970 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4971 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4972 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
4973 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
4974 "@
4975 fsqrt<Ftrad> %0,%1
4976 xssqrt<Fvsx> %x0,%x1"
4977 [(set_attr "type" "<Fs>sqrt")
4978 (set_attr "fp_type" "fp_sqrt_<Fs>")])
4980 ;; Floating point reciprocal approximation
4981 (define_insn "fre<Fs>"
4982 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4983 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4984 UNSPEC_FRES))]
4985 "TARGET_<FFRE>"
4986 "@
4987 fre<Ftrad> %0,%1
4988 xsre<Fvsx> %x0,%x1"
4989 [(set_attr "type" "fp")])
4991 (define_insn "*rsqrt<mode>2"
4992 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4993 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
4994 UNSPEC_RSQRT))]
4995 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4996 "@
4997 frsqrte<Ftrad> %0,%1
4998 xsrsqrte<Fvsx> %x0,%x1"
4999 [(set_attr "type" "fp")])
5001 ;; Floating point comparisons
5002 (define_insn "*cmp<mode>_fpr"
5003 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
5004 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5005 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5006 "TARGET_<MODE>_FPR"
5007 "@
5008 fcmpu %0,%1,%2
5009 xscmpudp %0,%x1,%x2"
5010 [(set_attr "type" "fpcompare")])
5012 ;; Floating point conversions
5013 (define_expand "extendsfdf2"
5014 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5015 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5016 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5017 "")
5019 (define_insn_and_split "*extendsfdf2_fpr"
5020 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
5021 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
5022 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5023 "@
5024 #
5025 fmr %0,%1
5026 lfs%U1%X1 %0,%1
5027 #
5028 xxlor %x0,%x1,%x1
5029 lxsspx %x0,%y1"
5030 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5031 [(const_int 0)]
5032 {
5033 emit_note (NOTE_INSN_DELETED);
5034 DONE;
5035 }
5036 [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
5038 (define_expand "truncdfsf2"
5039 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5040 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5041 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5042 "")
5044 (define_insn "*truncdfsf2_fpr"
5045 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5046 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5047 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5048 "frsp %0,%1"
5049 [(set_attr "type" "fp")])
5051 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
5052 ;; builtins.c and optabs.c that are not correct for IBM long double
5053 ;; when little-endian.
5054 (define_expand "signbittf2"
5055 [(set (match_dup 2)
5056 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5057 (set (match_dup 3)
5058 (subreg:DI (match_dup 2) 0))
5059 (set (match_dup 4)
5060 (match_dup 5))
5061 (set (match_operand:SI 0 "gpc_reg_operand" "")
5062 (match_dup 6))]
5063 "!TARGET_IEEEQUAD
5064 && TARGET_HARD_FLOAT
5065 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5066 && TARGET_LONG_DOUBLE_128"
5067 {
5068 operands[2] = gen_reg_rtx (DFmode);
5069 operands[3] = gen_reg_rtx (DImode);
5070 if (TARGET_POWERPC64)
5071 {
5072 operands[4] = gen_reg_rtx (DImode);
5073 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5074 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5075 WORDS_BIG_ENDIAN ? 4 : 0);
5076 }
5077 else
5078 {
5079 operands[4] = gen_reg_rtx (SImode);
5080 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5081 WORDS_BIG_ENDIAN ? 0 : 4);
5082 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5083 }
5084 })
5086 (define_expand "copysign<mode>3"
5087 [(set (match_dup 3)
5088 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5089 (set (match_dup 4)
5090 (neg:SFDF (abs:SFDF (match_dup 1))))
5091 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5092 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5093 (match_dup 5))
5094 (match_dup 3)
5095 (match_dup 4)))]
5096 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5097 && ((TARGET_PPC_GFXOPT
5098 && !HONOR_NANS (<MODE>mode)
5099 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5100 || TARGET_CMPB
5101 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5102 {
5103 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5104 {
5105 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5106 operands[2]));
5107 DONE;
5108 }
5110 operands[3] = gen_reg_rtx (<MODE>mode);
5111 operands[4] = gen_reg_rtx (<MODE>mode);
5112 operands[5] = CONST0_RTX (<MODE>mode);
5113 })
5115 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5116 ;; compiler from optimizing -0.0
5117 (define_insn "copysign<mode>3_fcpsgn"
5118 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5119 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5120 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5121 UNSPEC_COPYSIGN))]
5122 "TARGET_<MODE>_FPR && TARGET_CMPB"
5123 "@
5124 fcpsgn %0,%2,%1
5125 xscpsgn<Fvsx> %x0,%x2,%x1"
5126 [(set_attr "type" "fp")])
5128 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5129 ;; fsel instruction and some auxiliary computations. Then we just have a
5130 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5131 ;; combine.
5132 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5133 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5134 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5135 ;; define_splits to make them if made by combine. On VSX machines we have the
5136 ;; min/max instructions.
5137 ;;
5138 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5139 ;; to allow either DF/SF to use only traditional registers.
5141 (define_expand "smax<mode>3"
5142 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5143 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5144 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5145 (match_dup 1)
5146 (match_dup 2)))]
5147 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5148 {
5149 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5150 DONE;
5151 })
5153 (define_insn "*smax<mode>3_vsx"
5154 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5155 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5156 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5157 "TARGET_<MODE>_FPR && TARGET_VSX"
5158 "xsmaxdp %x0,%x1,%x2"
5159 [(set_attr "type" "fp")])
5161 (define_expand "smin<mode>3"
5162 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5163 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5164 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5165 (match_dup 2)
5166 (match_dup 1)))]
5167 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5168 {
5169 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5170 DONE;
5171 })
5173 (define_insn "*smin<mode>3_vsx"
5174 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5175 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5176 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5177 "TARGET_<MODE>_FPR && TARGET_VSX"
5178 "xsmindp %x0,%x1,%x2"
5179 [(set_attr "type" "fp")])
5181 (define_split
5182 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5183 (match_operator:SFDF 3 "min_max_operator"
5184 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5185 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5186 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5187 && !TARGET_VSX"
5188 [(const_int 0)]
5189 {
5190 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5191 operands[2]);
5192 DONE;
5193 })
5195 (define_split
5196 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5197 (match_operator:SF 3 "min_max_operator"
5198 [(match_operand:SF 1 "gpc_reg_operand" "")
5199 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5200 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5201 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5202 [(const_int 0)]
5203 "
5204 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5205 operands[1], operands[2]);
5206 DONE;
5207 }")
5209 (define_expand "mov<mode>cc"
5210 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5211 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5212 (match_operand:GPR 2 "gpc_reg_operand" "")
5213 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5214 "TARGET_ISEL<sel>"
5215 "
5216 {
5217 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5218 DONE;
5219 else
5220 FAIL;
5221 }")
5223 ;; We use the BASE_REGS for the isel input operands because, if rA is
5224 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5225 ;; because we may switch the operands and rB may end up being rA.
5226 ;;
5227 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5228 ;; leave out the mode in operand 4 and use one pattern, but reload can
5229 ;; change the mode underneath our feet and then gets confused trying
5230 ;; to reload the value.
5231 (define_insn "isel_signed_<mode>"
5232 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5233 (if_then_else:GPR
5234 (match_operator 1 "scc_comparison_operator"
5235 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5236 (const_int 0)])
5237 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5238 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5239 "TARGET_ISEL<sel>"
5240 "*
5241 { return output_isel (operands); }"
5242 [(set_attr "type" "isel")
5243 (set_attr "length" "4")])
5245 (define_insn "isel_unsigned_<mode>"
5246 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5247 (if_then_else:GPR
5248 (match_operator 1 "scc_comparison_operator"
5249 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5250 (const_int 0)])
5251 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5252 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5253 "TARGET_ISEL<sel>"
5254 "*
5255 { return output_isel (operands); }"
5256 [(set_attr "type" "isel")
5257 (set_attr "length" "4")])
5259 ;; These patterns can be useful for combine; they let combine know that
5260 ;; isel can handle reversed comparisons so long as the operands are
5261 ;; registers.
5263 (define_insn "*isel_reversed_signed_<mode>"
5264 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5265 (if_then_else:GPR
5266 (match_operator 1 "scc_rev_comparison_operator"
5267 [(match_operand:CC 4 "cc_reg_operand" "y")
5268 (const_int 0)])
5269 (match_operand:GPR 2 "gpc_reg_operand" "b")
5270 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5271 "TARGET_ISEL<sel>"
5272 "*
5273 { return output_isel (operands); }"
5274 [(set_attr "type" "isel")
5275 (set_attr "length" "4")])
5277 (define_insn "*isel_reversed_unsigned_<mode>"
5278 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5279 (if_then_else:GPR
5280 (match_operator 1 "scc_rev_comparison_operator"
5281 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5282 (const_int 0)])
5283 (match_operand:GPR 2 "gpc_reg_operand" "b")
5284 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5285 "TARGET_ISEL<sel>"
5286 "*
5287 { return output_isel (operands); }"
5288 [(set_attr "type" "isel")
5289 (set_attr "length" "4")])
5291 (define_expand "movsfcc"
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5293 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5294 (match_operand:SF 2 "gpc_reg_operand" "")
5295 (match_operand:SF 3 "gpc_reg_operand" "")))]
5296 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5297 "
5298 {
5299 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5300 DONE;
5301 else
5302 FAIL;
5303 }")
5305 (define_insn "*fselsfsf4"
5306 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5307 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5308 (match_operand:SF 4 "zero_fp_constant" "F"))
5309 (match_operand:SF 2 "gpc_reg_operand" "f")
5310 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5311 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5312 "fsel %0,%1,%2,%3"
5313 [(set_attr "type" "fp")])
5315 (define_insn "*fseldfsf4"
5316 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5317 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5318 (match_operand:DF 4 "zero_fp_constant" "F"))
5319 (match_operand:SF 2 "gpc_reg_operand" "f")
5320 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5321 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5322 "fsel %0,%1,%2,%3"
5323 [(set_attr "type" "fp")])
5325 ;; The conditional move instructions allow us to perform max and min
5326 ;; operations even when
5328 (define_split
5329 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5330 (match_operator:DF 3 "min_max_operator"
5331 [(match_operand:DF 1 "gpc_reg_operand" "")
5332 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5333 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5334 && !flag_trapping_math"
5335 [(const_int 0)]
5336 "
5337 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5338 operands[1], operands[2]);
5339 DONE;
5340 }")
5342 (define_expand "movdfcc"
5343 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5344 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5345 (match_operand:DF 2 "gpc_reg_operand" "")
5346 (match_operand:DF 3 "gpc_reg_operand" "")))]
5347 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5348 "
5349 {
5350 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5351 DONE;
5352 else
5353 FAIL;
5354 }")
5356 (define_insn "*fseldfdf4"
5357 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5358 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5359 (match_operand:DF 4 "zero_fp_constant" "F"))
5360 (match_operand:DF 2 "gpc_reg_operand" "d")
5361 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5362 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5363 "fsel %0,%1,%2,%3"
5364 [(set_attr "type" "fp")])
5366 (define_insn "*fselsfdf4"
5367 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5368 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5369 (match_operand:SF 4 "zero_fp_constant" "F"))
5370 (match_operand:DF 2 "gpc_reg_operand" "d")
5371 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5372 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5373 "fsel %0,%1,%2,%3"
5374 [(set_attr "type" "fp")])
5375 \f
5376 ;; Conversions to and from floating-point.
5378 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5379 ; don't want to support putting SImode in FPR registers.
5380 (define_insn "lfiwax"
5381 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5382 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5383 UNSPEC_LFIWAX))]
5384 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5385 "@
5386 lfiwax %0,%y1
5387 lxsiwax %x0,%y1
5388 mtvsrwa %x0,%1"
5389 [(set_attr "type" "fpload,fpload,mffgpr")])
5391 ; This split must be run before register allocation because it allocates the
5392 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5393 ; it earlier to allow for the combiner to merge insns together where it might
5394 ; not be needed and also in case the insns are deleted as dead code.
5396 (define_insn_and_split "floatsi<mode>2_lfiwax"
5397 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5398 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5399 (clobber (match_scratch:DI 2 "=d"))]
5400 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5401 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5402 "#"
5403 ""
5404 [(pc)]
5405 "
5406 {
5407 rtx dest = operands[0];
5408 rtx src = operands[1];
5409 rtx tmp;
5411 if (!MEM_P (src) && TARGET_POWERPC64
5412 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5413 tmp = convert_to_mode (DImode, src, false);
5414 else
5415 {
5416 tmp = operands[2];
5417 if (GET_CODE (tmp) == SCRATCH)
5418 tmp = gen_reg_rtx (DImode);
5419 if (MEM_P (src))
5420 {
5421 src = rs6000_address_for_fpconvert (src);
5422 emit_insn (gen_lfiwax (tmp, src));
5423 }
5424 else
5425 {
5426 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5427 emit_move_insn (stack, src);
5428 emit_insn (gen_lfiwax (tmp, stack));
5429 }
5430 }
5431 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5432 DONE;
5433 }"
5434 [(set_attr "length" "12")
5435 (set_attr "type" "fpload")])
5437 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5438 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5439 (float:SFDF
5440 (sign_extend:DI
5441 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5442 (clobber (match_scratch:DI 2 "=0,d"))]
5443 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5444 && <SI_CONVERT_FP>"
5445 "#"
5446 ""
5447 [(pc)]
5448 "
5449 {
5450 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5451 if (GET_CODE (operands[2]) == SCRATCH)
5452 operands[2] = gen_reg_rtx (DImode);
5453 emit_insn (gen_lfiwax (operands[2], operands[1]));
5454 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5455 DONE;
5456 }"
5457 [(set_attr "length" "8")
5458 (set_attr "type" "fpload")])
5460 (define_insn "lfiwzx"
5461 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
5462 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5463 UNSPEC_LFIWZX))]
5464 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5465 "@
5466 lfiwzx %0,%y1
5467 lxsiwzx %x0,%y1
5468 mtvsrwz %x0,%1"
5469 [(set_attr "type" "fpload,fpload,mftgpr")])
5471 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5472 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5473 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5474 (clobber (match_scratch:DI 2 "=d"))]
5475 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5476 && <SI_CONVERT_FP>"
5477 "#"
5478 ""
5479 [(pc)]
5480 "
5481 {
5482 rtx dest = operands[0];
5483 rtx src = operands[1];
5484 rtx tmp;
5486 if (!MEM_P (src) && TARGET_POWERPC64
5487 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5488 tmp = convert_to_mode (DImode, src, true);
5489 else
5490 {
5491 tmp = operands[2];
5492 if (GET_CODE (tmp) == SCRATCH)
5493 tmp = gen_reg_rtx (DImode);
5494 if (MEM_P (src))
5495 {
5496 src = rs6000_address_for_fpconvert (src);
5497 emit_insn (gen_lfiwzx (tmp, src));
5498 }
5499 else
5500 {
5501 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5502 emit_move_insn (stack, src);
5503 emit_insn (gen_lfiwzx (tmp, stack));
5504 }
5505 }
5506 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5507 DONE;
5508 }"
5509 [(set_attr "length" "12")
5510 (set_attr "type" "fpload")])
5512 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5513 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5514 (unsigned_float:SFDF
5515 (zero_extend:DI
5516 (match_operand:SI 1 "indexed_or_indirect_operand" "Z,Z"))))
5517 (clobber (match_scratch:DI 2 "=0,d"))]
5518 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5519 && <SI_CONVERT_FP>"
5520 "#"
5521 ""
5522 [(pc)]
5523 "
5524 {
5525 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5526 if (GET_CODE (operands[2]) == SCRATCH)
5527 operands[2] = gen_reg_rtx (DImode);
5528 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5529 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5530 DONE;
5531 }"
5532 [(set_attr "length" "8")
5533 (set_attr "type" "fpload")])
5535 ; For each of these conversions, there is a define_expand, a define_insn
5536 ; with a '#' template, and a define_split (with C code). The idea is
5537 ; to allow constant folding with the template of the define_insn,
5538 ; then to have the insns split later (between sched1 and final).
5540 (define_expand "floatsidf2"
5541 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5542 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5543 (use (match_dup 2))
5544 (use (match_dup 3))
5545 (clobber (match_dup 4))
5546 (clobber (match_dup 5))
5547 (clobber (match_dup 6))])]
5548 "TARGET_HARD_FLOAT
5549 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5550 "
5551 {
5552 if (TARGET_E500_DOUBLE)
5553 {
5554 if (!REG_P (operands[1]))
5555 operands[1] = force_reg (SImode, operands[1]);
5556 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5557 DONE;
5558 }
5559 else if (TARGET_LFIWAX && TARGET_FCFID)
5560 {
5561 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5562 DONE;
5563 }
5564 else if (TARGET_FCFID)
5565 {
5566 rtx dreg = operands[1];
5567 if (!REG_P (dreg))
5568 dreg = force_reg (SImode, dreg);
5569 dreg = convert_to_mode (DImode, dreg, false);
5570 emit_insn (gen_floatdidf2 (operands[0], dreg));
5571 DONE;
5572 }
5574 if (!REG_P (operands[1]))
5575 operands[1] = force_reg (SImode, operands[1]);
5576 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5577 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5578 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5579 operands[5] = gen_reg_rtx (DFmode);
5580 operands[6] = gen_reg_rtx (SImode);
5581 }")
5583 (define_insn_and_split "*floatsidf2_internal"
5584 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5585 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5586 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5587 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5588 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5589 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5590 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5591 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5592 "#"
5593 ""
5594 [(pc)]
5595 "
5596 {
5597 rtx lowword, highword;
5598 gcc_assert (MEM_P (operands[4]));
5599 highword = adjust_address (operands[4], SImode, 0);
5600 lowword = adjust_address (operands[4], SImode, 4);
5601 if (! WORDS_BIG_ENDIAN)
5602 {
5603 rtx tmp;
5604 tmp = highword; highword = lowword; lowword = tmp;
5605 }
5607 emit_insn (gen_xorsi3 (operands[6], operands[1],
5608 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5609 emit_move_insn (lowword, operands[6]);
5610 emit_move_insn (highword, operands[2]);
5611 emit_move_insn (operands[5], operands[4]);
5612 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5613 DONE;
5614 }"
5615 [(set_attr "length" "24")
5616 (set_attr "type" "fp")])
5618 ;; If we don't have a direct conversion to single precision, don't enable this
5619 ;; conversion for 32-bit without fast math, because we don't have the insn to
5620 ;; generate the fixup swizzle to avoid double rounding problems.
5621 (define_expand "floatunssisf2"
5622 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5623 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5624 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5625 && (!TARGET_FPRS
5626 || (TARGET_FPRS
5627 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5628 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5629 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5630 "
5631 {
5632 if (!TARGET_FPRS)
5633 {
5634 if (!REG_P (operands[1]))
5635 operands[1] = force_reg (SImode, operands[1]);
5636 }
5637 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5638 {
5639 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5640 DONE;
5641 }
5642 else
5643 {
5644 rtx dreg = operands[1];
5645 if (!REG_P (dreg))
5646 dreg = force_reg (SImode, dreg);
5647 dreg = convert_to_mode (DImode, dreg, true);
5648 emit_insn (gen_floatdisf2 (operands[0], dreg));
5649 DONE;
5650 }
5651 }")
5653 (define_expand "floatunssidf2"
5654 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5655 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5656 (use (match_dup 2))
5657 (use (match_dup 3))
5658 (clobber (match_dup 4))
5659 (clobber (match_dup 5))])]
5660 "TARGET_HARD_FLOAT
5661 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5662 "
5663 {
5664 if (TARGET_E500_DOUBLE)
5665 {
5666 if (!REG_P (operands[1]))
5667 operands[1] = force_reg (SImode, operands[1]);
5668 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5669 DONE;
5670 }
5671 else if (TARGET_LFIWZX && TARGET_FCFID)
5672 {
5673 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5674 DONE;
5675 }
5676 else if (TARGET_FCFID)
5677 {
5678 rtx dreg = operands[1];
5679 if (!REG_P (dreg))
5680 dreg = force_reg (SImode, dreg);
5681 dreg = convert_to_mode (DImode, dreg, true);
5682 emit_insn (gen_floatdidf2 (operands[0], dreg));
5683 DONE;
5684 }
5686 if (!REG_P (operands[1]))
5687 operands[1] = force_reg (SImode, operands[1]);
5688 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5689 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5690 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5691 operands[5] = gen_reg_rtx (DFmode);
5692 }")
5694 (define_insn_and_split "*floatunssidf2_internal"
5695 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5696 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5697 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5698 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5699 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5700 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5701 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5702 && !(TARGET_FCFID && TARGET_POWERPC64)"
5703 "#"
5704 ""
5705 [(pc)]
5706 "
5707 {
5708 rtx lowword, highword;
5709 gcc_assert (MEM_P (operands[4]));
5710 highword = adjust_address (operands[4], SImode, 0);
5711 lowword = adjust_address (operands[4], SImode, 4);
5712 if (! WORDS_BIG_ENDIAN)
5713 {
5714 rtx tmp;
5715 tmp = highword; highword = lowword; lowword = tmp;
5716 }
5718 emit_move_insn (lowword, operands[1]);
5719 emit_move_insn (highword, operands[2]);
5720 emit_move_insn (operands[5], operands[4]);
5721 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5722 DONE;
5723 }"
5724 [(set_attr "length" "20")
5725 (set_attr "type" "fp")])
5727 (define_expand "fix_trunc<mode>si2"
5728 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5729 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5730 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5731 "
5732 {
5733 if (!<E500_CONVERT>)
5734 {
5735 rtx tmp, stack;
5737 if (TARGET_STFIWX)
5738 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5739 else
5740 {
5741 tmp = gen_reg_rtx (DImode);
5742 stack = rs6000_allocate_stack_temp (DImode, true, false);
5743 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5744 tmp, stack));
5745 }
5746 DONE;
5747 }
5748 }")
5750 ; Like the convert to float patterns, this insn must be split before
5751 ; register allocation so that it can allocate the memory slot if it
5752 ; needed
5753 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5754 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5755 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5756 (clobber (match_scratch:DI 2 "=d"))]
5757 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5758 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5759 && TARGET_STFIWX && can_create_pseudo_p ()"
5760 "#"
5761 ""
5762 [(pc)]
5763 {
5764 rtx dest = operands[0];
5765 rtx src = operands[1];
5766 rtx tmp = operands[2];
5768 if (GET_CODE (tmp) == SCRATCH)
5769 tmp = gen_reg_rtx (DImode);
5771 emit_insn (gen_fctiwz_<mode> (tmp, src));
5772 if (MEM_P (dest))
5773 {
5774 dest = rs6000_address_for_fpconvert (dest);
5775 emit_insn (gen_stfiwx (dest, tmp));
5776 DONE;
5777 }
5778 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5779 {
5780 dest = gen_lowpart (DImode, dest);
5781 emit_move_insn (dest, tmp);
5782 DONE;
5783 }
5784 else
5785 {
5786 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5787 emit_insn (gen_stfiwx (stack, tmp));
5788 emit_move_insn (dest, stack);
5789 DONE;
5790 }
5791 }
5792 [(set_attr "length" "12")
5793 (set_attr "type" "fp")])
5795 (define_insn_and_split "fix_trunc<mode>si2_internal"
5796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5797 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5798 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5799 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5800 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5801 "#"
5802 ""
5803 [(pc)]
5804 "
5805 {
5806 rtx lowword;
5807 gcc_assert (MEM_P (operands[3]));
5808 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5810 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5811 emit_move_insn (operands[3], operands[2]);
5812 emit_move_insn (operands[0], lowword);
5813 DONE;
5814 }"
5815 [(set_attr "length" "16")
5816 (set_attr "type" "fp")])
5818 (define_expand "fix_trunc<mode>di2"
5819 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5820 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5821 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5822 && TARGET_FCFID"
5823 "")
5825 (define_insn "*fix_trunc<mode>di2_fctidz"
5826 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5827 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5828 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5829 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5830 "fctidz %0,%1"
5831 [(set_attr "type" "fp")])
5833 (define_expand "fixuns_trunc<mode>si2"
5834 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5835 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5836 "TARGET_HARD_FLOAT
5837 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5838 || <E500_CONVERT>)"
5839 "
5840 {
5841 if (!<E500_CONVERT>)
5842 {
5843 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5844 DONE;
5845 }
5846 }")
5848 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5849 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5850 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5851 (clobber (match_scratch:DI 2 "=d"))]
5852 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5853 && TARGET_STFIWX && can_create_pseudo_p ()"
5854 "#"
5855 ""
5856 [(pc)]
5857 {
5858 rtx dest = operands[0];
5859 rtx src = operands[1];
5860 rtx tmp = operands[2];
5862 if (GET_CODE (tmp) == SCRATCH)
5863 tmp = gen_reg_rtx (DImode);
5865 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5866 if (MEM_P (dest))
5867 {
5868 dest = rs6000_address_for_fpconvert (dest);
5869 emit_insn (gen_stfiwx (dest, tmp));
5870 DONE;
5871 }
5872 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5873 {
5874 dest = gen_lowpart (DImode, dest);
5875 emit_move_insn (dest, tmp);
5876 DONE;
5877 }
5878 else
5879 {
5880 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5881 emit_insn (gen_stfiwx (stack, tmp));
5882 emit_move_insn (dest, stack);
5883 DONE;
5884 }
5885 }
5886 [(set_attr "length" "12")
5887 (set_attr "type" "fp")])
5889 (define_expand "fixuns_trunc<mode>di2"
5890 [(set (match_operand:DI 0 "register_operand" "")
5891 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5892 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5893 "")
5895 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5896 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5897 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5898 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5899 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5900 "fctiduz %0,%1"
5901 [(set_attr "type" "fp")])
5903 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5904 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5905 ; because the first makes it clear that operand 0 is not live
5906 ; before the instruction.
5907 (define_insn "fctiwz_<mode>"
5908 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5909 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
5910 UNSPEC_FCTIWZ))]
5911 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5912 "fctiwz %0,%1"
5913 [(set_attr "type" "fp")])
5915 (define_insn "fctiwuz_<mode>"
5916 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5917 (unspec:DI [(unsigned_fix:SI
5918 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
5919 UNSPEC_FCTIWUZ))]
5920 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5921 "fctiwuz %0,%1"
5922 [(set_attr "type" "fp")])
5924 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5925 ;; since the friz instruction does not truncate the value if the floating
5926 ;; point value is < LONG_MIN or > LONG_MAX.
5927 (define_insn "*friz"
5928 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5929 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5930 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5931 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
5932 && !flag_trapping_math && TARGET_FRIZ"
5933 "friz %0,%1"
5934 [(set_attr "type" "fp")])
5936 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5937 ;; load to properly sign extend the value, but at least doing a store, load
5938 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5939 ;; if we have 32-bit memory ops
5940 (define_insn_and_split "*round32<mode>2_fprs"
5941 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5942 (float:SFDF
5943 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5944 (clobber (match_scratch:DI 2 "=d"))
5945 (clobber (match_scratch:DI 3 "=d"))]
5946 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5947 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5948 && can_create_pseudo_p ()"
5949 "#"
5950 ""
5951 [(pc)]
5952 {
5953 rtx dest = operands[0];
5954 rtx src = operands[1];
5955 rtx tmp1 = operands[2];
5956 rtx tmp2 = operands[3];
5957 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5959 if (GET_CODE (tmp1) == SCRATCH)
5960 tmp1 = gen_reg_rtx (DImode);
5961 if (GET_CODE (tmp2) == SCRATCH)
5962 tmp2 = gen_reg_rtx (DImode);
5964 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5965 emit_insn (gen_stfiwx (stack, tmp1));
5966 emit_insn (gen_lfiwax (tmp2, stack));
5967 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5968 DONE;
5969 }
5970 [(set_attr "type" "fpload")
5971 (set_attr "length" "16")])
5973 (define_insn_and_split "*roundu32<mode>2_fprs"
5974 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5975 (unsigned_float:SFDF
5976 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5977 (clobber (match_scratch:DI 2 "=d"))
5978 (clobber (match_scratch:DI 3 "=d"))]
5979 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5980 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
5981 && can_create_pseudo_p ()"
5982 "#"
5983 ""
5984 [(pc)]
5985 {
5986 rtx dest = operands[0];
5987 rtx src = operands[1];
5988 rtx tmp1 = operands[2];
5989 rtx tmp2 = operands[3];
5990 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5992 if (GET_CODE (tmp1) == SCRATCH)
5993 tmp1 = gen_reg_rtx (DImode);
5994 if (GET_CODE (tmp2) == SCRATCH)
5995 tmp2 = gen_reg_rtx (DImode);
5997 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
5998 emit_insn (gen_stfiwx (stack, tmp1));
5999 emit_insn (gen_lfiwzx (tmp2, stack));
6000 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6001 DONE;
6002 }
6003 [(set_attr "type" "fpload")
6004 (set_attr "length" "16")])
6006 ;; No VSX equivalent to fctid
6007 (define_insn "lrint<mode>di2"
6008 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6009 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6010 UNSPEC_FCTID))]
6011 "TARGET_<MODE>_FPR && TARGET_FPRND"
6012 "fctid %0,%1"
6013 [(set_attr "type" "fp")])
6015 (define_insn "btrunc<mode>2"
6016 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6017 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6018 UNSPEC_FRIZ))]
6019 "TARGET_<MODE>_FPR && TARGET_FPRND"
6020 "@
6021 friz %0,%1
6022 xsrdpiz %x0,%x1"
6023 [(set_attr "type" "fp")
6024 (set_attr "fp_type" "fp_addsub_<Fs>")])
6026 (define_insn "ceil<mode>2"
6027 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6028 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6029 UNSPEC_FRIP))]
6030 "TARGET_<MODE>_FPR && TARGET_FPRND"
6031 "@
6032 frip %0,%1
6033 xsrdpip %x0,%x1"
6034 [(set_attr "type" "fp")
6035 (set_attr "fp_type" "fp_addsub_<Fs>")])
6037 (define_insn "floor<mode>2"
6038 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6039 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6040 UNSPEC_FRIM))]
6041 "TARGET_<MODE>_FPR && TARGET_FPRND"
6042 "@
6043 frim %0,%1
6044 xsrdpim %x0,%x1"
6045 [(set_attr "type" "fp")
6046 (set_attr "fp_type" "fp_addsub_<Fs>")])
6048 ;; No VSX equivalent to frin
6049 (define_insn "round<mode>2"
6050 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6051 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6052 UNSPEC_FRIN))]
6053 "TARGET_<MODE>_FPR && TARGET_FPRND"
6054 "frin %0,%1"
6055 [(set_attr "type" "fp")
6056 (set_attr "fp_type" "fp_addsub_<Fs>")])
6058 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6059 (define_insn "stfiwx"
6060 [(set (match_operand:SI 0 "memory_operand" "=Z")
6061 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6062 UNSPEC_STFIWX))]
6063 "TARGET_PPC_GFXOPT"
6064 "stfiwx %1,%y0"
6065 [(set_attr "type" "fpstore")])
6067 ;; If we don't have a direct conversion to single precision, don't enable this
6068 ;; conversion for 32-bit without fast math, because we don't have the insn to
6069 ;; generate the fixup swizzle to avoid double rounding problems.
6070 (define_expand "floatsisf2"
6071 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6072 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6073 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6074 && (!TARGET_FPRS
6075 || (TARGET_FPRS
6076 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6077 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6078 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6079 "
6080 {
6081 if (!TARGET_FPRS)
6082 {
6083 if (!REG_P (operands[1]))
6084 operands[1] = force_reg (SImode, operands[1]);
6085 }
6086 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6087 {
6088 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6089 DONE;
6090 }
6091 else if (TARGET_FCFID && TARGET_LFIWAX)
6092 {
6093 rtx dfreg = gen_reg_rtx (DFmode);
6094 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6095 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6096 DONE;
6097 }
6098 else
6099 {
6100 rtx dreg = operands[1];
6101 if (!REG_P (dreg))
6102 dreg = force_reg (SImode, dreg);
6103 dreg = convert_to_mode (DImode, dreg, false);
6104 emit_insn (gen_floatdisf2 (operands[0], dreg));
6105 DONE;
6106 }
6107 }")
6109 (define_expand "floatdidf2"
6110 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6111 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6112 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6113 "")
6115 (define_insn "*floatdidf2_fpr"
6116 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6117 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6118 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6119 && !VECTOR_UNIT_VSX_P (DFmode)"
6120 "fcfid %0,%1"
6121 [(set_attr "type" "fp")])
6123 ; Allow the combiner to merge source memory operands to the conversion so that
6124 ; the optimizer/register allocator doesn't try to load the value too early in a
6125 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6126 ; hit. We will split after reload to avoid the trip through the GPRs
6128 (define_insn_and_split "*floatdidf2_mem"
6129 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6130 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6131 (clobber (match_scratch:DI 2 "=d"))]
6132 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6133 "#"
6134 "&& reload_completed"
6135 [(set (match_dup 2) (match_dup 1))
6136 (set (match_dup 0) (float:DF (match_dup 2)))]
6137 ""
6138 [(set_attr "length" "8")
6139 (set_attr "type" "fpload")])
6141 (define_expand "floatunsdidf2"
6142 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6143 (unsigned_float:DF
6144 (match_operand:DI 1 "gpc_reg_operand" "")))]
6145 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6146 "")
6148 (define_insn "*floatunsdidf2_fcfidu"
6149 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6150 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6151 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6152 "fcfidu %0,%1"
6153 [(set_attr "type" "fp")
6154 (set_attr "length" "4")])
6156 (define_insn_and_split "*floatunsdidf2_mem"
6157 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6158 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6159 (clobber (match_scratch:DI 2 "=d"))]
6160 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6161 "#"
6162 "&& reload_completed"
6163 [(set (match_dup 2) (match_dup 1))
6164 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6165 ""
6166 [(set_attr "length" "8")
6167 (set_attr "type" "fpload")])
6169 (define_expand "floatdisf2"
6170 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6171 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6172 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6173 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6174 "
6175 {
6176 if (!TARGET_FCFIDS)
6177 {
6178 rtx val = operands[1];
6179 if (!flag_unsafe_math_optimizations)
6180 {
6181 rtx label = gen_label_rtx ();
6182 val = gen_reg_rtx (DImode);
6183 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6184 emit_label (label);
6185 }
6186 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6187 DONE;
6188 }
6189 }")
6191 (define_insn "floatdisf2_fcfids"
6192 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6193 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6194 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6195 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6196 "fcfids %0,%1"
6197 [(set_attr "type" "fp")])
6199 (define_insn_and_split "*floatdisf2_mem"
6200 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6201 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6202 (clobber (match_scratch:DI 2 "=f"))]
6203 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6204 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6205 "#"
6206 "&& reload_completed"
6207 [(pc)]
6208 "
6209 {
6210 emit_move_insn (operands[2], operands[1]);
6211 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6212 DONE;
6213 }"
6214 [(set_attr "length" "8")])
6216 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6217 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6218 ;; from double rounding.
6219 ;; Instead of creating a new cpu type for two FP operations, just use fp
6220 (define_insn_and_split "floatdisf2_internal1"
6221 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6222 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6223 (clobber (match_scratch:DF 2 "=d"))]
6224 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6225 "#"
6226 "&& reload_completed"
6227 [(set (match_dup 2)
6228 (float:DF (match_dup 1)))
6229 (set (match_dup 0)
6230 (float_truncate:SF (match_dup 2)))]
6231 ""
6232 [(set_attr "length" "8")
6233 (set_attr "type" "fp")])
6235 ;; Twiddles bits to avoid double rounding.
6236 ;; Bits that might be truncated when converting to DFmode are replaced
6237 ;; by a bit that won't be lost at that stage, but is below the SFmode
6238 ;; rounding position.
6239 (define_expand "floatdisf2_internal2"
6240 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6241 (const_int 53)))
6242 (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6243 (const_int 2047)))
6244 (set (match_dup 3) (plus:DI (match_dup 3)
6245 (const_int 1)))
6246 (set (match_dup 0) (plus:DI (match_dup 0)
6247 (const_int 2047)))
6248 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6249 (const_int 2)))
6250 (set (match_dup 0) (ior:DI (match_dup 0)
6251 (match_dup 1)))
6252 (set (match_dup 0) (and:DI (match_dup 0)
6253 (const_int -2048)))
6254 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6255 (label_ref (match_operand:DI 2 "" ""))
6256 (pc)))
6257 (set (match_dup 0) (match_dup 1))]
6258 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6259 "
6260 {
6261 operands[3] = gen_reg_rtx (DImode);
6262 operands[4] = gen_reg_rtx (CCUNSmode);
6263 }")
6265 (define_expand "floatunsdisf2"
6266 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6267 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6268 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6269 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6270 "")
6272 (define_insn "floatunsdisf2_fcfidus"
6273 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6274 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6275 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6276 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6277 "fcfidus %0,%1"
6278 [(set_attr "type" "fp")])
6280 (define_insn_and_split "*floatunsdisf2_mem"
6281 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6282 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6283 (clobber (match_scratch:DI 2 "=f"))]
6284 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6285 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6286 "#"
6287 "&& reload_completed"
6288 [(pc)]
6289 "
6290 {
6291 emit_move_insn (operands[2], operands[1]);
6292 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6293 DONE;
6294 }"
6295 [(set_attr "length" "8")
6296 (set_attr "type" "fpload")])
6297 \f
6298 ;; Define the TImode operations that can be done in a small number
6299 ;; of instructions. The & constraints are to prevent the register
6300 ;; allocator from allocating registers that overlap with the inputs
6301 ;; (for example, having an input in 7,8 and an output in 6,7). We
6302 ;; also allow for the output being the same as one of the inputs.
6304 (define_insn "addti3"
6305 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
6306 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
6307 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
6308 "TARGET_64BIT"
6309 {
6310 if (WORDS_BIG_ENDIAN)
6311 return (GET_CODE (operands[2])) != CONST_INT
6312 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6313 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6314 else
6315 return (GET_CODE (operands[2])) != CONST_INT
6316 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6317 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6318 }
6319 [(set_attr "type" "two")
6320 (set_attr "length" "8")])
6322 (define_insn "subti3"
6323 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6324 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
6325 (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6326 "TARGET_64BIT"
6327 {
6328 if (WORDS_BIG_ENDIAN)
6329 return (GET_CODE (operands[1]) != CONST_INT)
6330 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6331 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6332 else
6333 return (GET_CODE (operands[1]) != CONST_INT)
6334 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6335 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6336 }
6337 [(set_attr "type" "two")
6338 (set_attr "length" "8")])
6341 ;; Define the DImode operations that can be done in a small number
6342 ;; of instructions. The & constraints are to prevent the register
6343 ;; allocator from allocating registers that overlap with the inputs
6344 ;; (for example, having an input in 7,8 and an output in 6,7). We
6345 ;; also allow for the output being the same as one of the inputs.
6347 (define_insn "*adddi3_noppc64"
6348 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6349 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6350 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6351 "! TARGET_POWERPC64"
6352 "*
6353 {
6354 if (WORDS_BIG_ENDIAN)
6355 return (GET_CODE (operands[2])) != CONST_INT
6356 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6357 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6358 else
6359 return (GET_CODE (operands[2])) != CONST_INT
6360 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6361 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6362 }"
6363 [(set_attr "type" "two")
6364 (set_attr "length" "8")])
6366 (define_insn "*subdi3_noppc64"
6367 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6368 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6369 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6370 "! TARGET_POWERPC64"
6371 "*
6372 {
6373 if (WORDS_BIG_ENDIAN)
6374 return (GET_CODE (operands[1]) != CONST_INT)
6375 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6376 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6377 else
6378 return (GET_CODE (operands[1]) != CONST_INT)
6379 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6380 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6381 }"
6382 [(set_attr "type" "two")
6383 (set_attr "length" "8")])
6385 (define_insn "*negdi2_noppc64"
6386 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6387 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6388 "! TARGET_POWERPC64"
6389 "*
6390 {
6391 return (WORDS_BIG_ENDIAN)
6392 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6393 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6394 }"
6395 [(set_attr "type" "two")
6396 (set_attr "length" "8")])
6399 ;; Shift by a variable amount is too complex to be worth open-coding. We
6400 ;; just handle shifts by constants.
6401 (define_insn "ashrdi3_no_power"
6402 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6403 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6404 (match_operand:SI 2 "const_int_operand" "M,i")))]
6405 "!TARGET_POWERPC64"
6406 "*
6407 {
6408 switch (which_alternative)
6409 {
6410 default:
6411 gcc_unreachable ();
6412 case 0:
6413 if (WORDS_BIG_ENDIAN)
6414 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6415 else
6416 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6417 case 1:
6418 if (WORDS_BIG_ENDIAN)
6419 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6420 else
6421 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6422 }
6423 }"
6424 [(set_attr "type" "two,three")
6425 (set_attr "length" "8,12")])
6427 (define_insn "*ashrdisi3_noppc64be"
6428 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6429 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6430 (const_int 32)) 4))]
6431 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6432 "*
6433 {
6434 if (REGNO (operands[0]) == REGNO (operands[1]))
6435 return \"\";
6436 else
6437 return \"mr %0,%1\";
6438 }"
6439 [(set_attr "length" "4")])
6441 \f
6442 ;; PowerPC64 DImode operations.
6444 (define_insn "*rotldi3_internal4"
6445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6446 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6447 (match_operand:DI 2 "reg_or_cint_operand" "rn"))
6448 (match_operand:DI 3 "mask64_operand" "n")))]
6449 "TARGET_POWERPC64"
6450 "rld%I2c%B3 %0,%1,%H2,%S3"
6451 [(set_attr "type" "shift")
6452 (set_attr "maybe_var_shift" "yes")])
6454 (define_insn "*rotldi3_internal5"
6455 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6456 (compare:CC (and:DI
6457 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6458 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6459 (match_operand:DI 3 "mask64_operand" "n,n"))
6460 (const_int 0)))
6461 (clobber (match_scratch:DI 4 "=r,r"))]
6462 "TARGET_64BIT"
6463 "@
6464 rld%I2c%B3. %4,%1,%H2,%S3
6465 #"
6466 [(set_attr "type" "shift")
6467 (set_attr "maybe_var_shift" "yes")
6468 (set_attr "dot" "yes")
6469 (set_attr "length" "4,8")])
6471 (define_split
6472 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6473 (compare:CC (and:DI
6474 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6475 (match_operand:DI 2 "reg_or_cint_operand" ""))
6476 (match_operand:DI 3 "mask64_operand" ""))
6477 (const_int 0)))
6478 (clobber (match_scratch:DI 4 ""))]
6479 "TARGET_POWERPC64 && reload_completed"
6480 [(set (match_dup 4)
6481 (and:DI (rotate:DI (match_dup 1)
6482 (match_dup 2))
6483 (match_dup 3)))
6484 (set (match_dup 0)
6485 (compare:CC (match_dup 4)
6486 (const_int 0)))]
6487 "")
6489 (define_insn "*rotldi3_internal6"
6490 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6491 (compare:CC (and:DI
6492 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6493 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6494 (match_operand:DI 3 "mask64_operand" "n,n"))
6495 (const_int 0)))
6496 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6497 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6498 "TARGET_64BIT"
6499 "@
6500 rld%I2c%B3. %0,%1,%H2,%S3
6501 #"
6502 [(set_attr "type" "shift")
6503 (set_attr "maybe_var_shift" "yes")
6504 (set_attr "dot" "yes")
6505 (set_attr "length" "4,8")])
6507 (define_split
6508 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6509 (compare:CC (and:DI
6510 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6511 (match_operand:DI 2 "reg_or_cint_operand" ""))
6512 (match_operand:DI 3 "mask64_operand" ""))
6513 (const_int 0)))
6514 (set (match_operand:DI 0 "gpc_reg_operand" "")
6515 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6516 "TARGET_POWERPC64 && reload_completed"
6517 [(set (match_dup 0)
6518 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6519 (set (match_dup 4)
6520 (compare:CC (match_dup 0)
6521 (const_int 0)))]
6522 "")
6524 (define_insn "*rotldi3_internal7le"
6525 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6526 (zero_extend:DI
6527 (subreg:QI
6528 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6529 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6530 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6531 "rld%I2cl %0,%1,%H2,56"
6532 [(set_attr "type" "shift")
6533 (set_attr "maybe_var_shift" "yes")])
6535 (define_insn "*rotldi3_internal7be"
6536 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6537 (zero_extend:DI
6538 (subreg:QI
6539 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6540 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
6541 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6542 "rld%I2cl %0,%1,%H2,56"
6543 [(set_attr "type" "shift")
6544 (set_attr "maybe_var_shift" "yes")])
6546 (define_insn "*rotldi3_internal8le"
6547 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6548 (compare:CC (zero_extend:DI
6549 (subreg:QI
6550 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6551 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6552 (const_int 0)))
6553 (clobber (match_scratch:DI 3 "=r,r"))]
6554 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6555 "@
6556 rld%I2cl. %3,%1,%H2,56
6557 #"
6558 [(set_attr "type" "shift")
6559 (set_attr "maybe_var_shift" "yes")
6560 (set_attr "dot" "yes")
6561 (set_attr "length" "4,8")])
6563 (define_insn "*rotldi3_internal8be"
6564 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6565 (compare:CC (zero_extend:DI
6566 (subreg:QI
6567 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6568 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6569 (const_int 0)))
6570 (clobber (match_scratch:DI 3 "=r,r"))]
6571 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6572 "@
6573 rld%I2cl. %3,%1,%H2,56
6574 #"
6575 [(set_attr "type" "shift")
6576 (set_attr "maybe_var_shift" "yes")
6577 (set_attr "dot" "yes")
6578 (set_attr "length" "4,8")])
6580 (define_split
6581 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6582 (compare:CC (zero_extend:DI
6583 (subreg:QI
6584 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6585 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6586 (const_int 0)))
6587 (clobber (match_scratch:DI 3 ""))]
6588 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6589 [(set (match_dup 3)
6590 (zero_extend:DI (subreg:QI
6591 (rotate:DI (match_dup 1)
6592 (match_dup 2)) 0)))
6593 (set (match_dup 0)
6594 (compare:CC (match_dup 3)
6595 (const_int 0)))]
6596 "")
6598 (define_split
6599 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6600 (compare:CC (zero_extend:DI
6601 (subreg:QI
6602 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6603 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6604 (const_int 0)))
6605 (clobber (match_scratch:DI 3 ""))]
6606 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6607 [(set (match_dup 3)
6608 (zero_extend:DI (subreg:QI
6609 (rotate:DI (match_dup 1)
6610 (match_dup 2)) 7)))
6611 (set (match_dup 0)
6612 (compare:CC (match_dup 3)
6613 (const_int 0)))]
6614 "")
6616 (define_insn "*rotldi3_internal9le"
6617 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6618 (compare:CC (zero_extend:DI
6619 (subreg:QI
6620 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6621 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6622 (const_int 0)))
6623 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6624 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6625 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6626 "@
6627 rld%I2cl. %0,%1,%H2,56
6628 #"
6629 [(set_attr "type" "shift")
6630 (set_attr "maybe_var_shift" "yes")
6631 (set_attr "dot" "yes")
6632 (set_attr "length" "4,8")])
6634 (define_insn "*rotldi3_internal9be"
6635 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6636 (compare:CC (zero_extend:DI
6637 (subreg:QI
6638 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6639 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
6640 (const_int 0)))
6641 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6642 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6643 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6644 "@
6645 rld%I2cl. %0,%1,%H2,56
6646 #"
6647 [(set_attr "type" "shift")
6648 (set_attr "maybe_var_shift" "yes")
6649 (set_attr "dot" "yes")
6650 (set_attr "length" "4,8")])
6652 (define_split
6653 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6654 (compare:CC (zero_extend:DI
6655 (subreg:QI
6656 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6657 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6658 (const_int 0)))
6659 (set (match_operand:DI 0 "gpc_reg_operand" "")
6660 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6661 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6662 [(set (match_dup 0)
6663 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6664 (set (match_dup 3)
6665 (compare:CC (match_dup 0)
6666 (const_int 0)))]
6667 "")
6669 (define_split
6670 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6671 (compare:CC (zero_extend:DI
6672 (subreg:QI
6673 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6674 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
6675 (const_int 0)))
6676 (set (match_operand:DI 0 "gpc_reg_operand" "")
6677 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
6678 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6679 [(set (match_dup 0)
6680 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
6681 (set (match_dup 3)
6682 (compare:CC (match_dup 0)
6683 (const_int 0)))]
6684 "")
6686 (define_insn "*rotldi3_internal10le"
6687 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6688 (zero_extend:DI
6689 (subreg:HI
6690 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6691 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6692 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6693 "rld%I2cl %0,%1,%H2,48"
6694 [(set_attr "type" "shift")
6695 (set_attr "maybe_var_shift" "yes")])
6697 (define_insn "*rotldi3_internal10be"
6698 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6699 (zero_extend:DI
6700 (subreg:HI
6701 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6702 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
6703 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6704 "rld%I2cl %0,%1,%H2,48"
6705 [(set_attr "type" "shift")
6706 (set_attr "maybe_var_shift" "yes")])
6708 (define_insn "*rotldi3_internal11le"
6709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6710 (compare:CC (zero_extend:DI
6711 (subreg:HI
6712 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6713 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6714 (const_int 0)))
6715 (clobber (match_scratch:DI 3 "=r,r"))]
6716 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6717 "@
6718 rld%I2cl. %3,%1,%H2,48
6719 #"
6720 [(set_attr "type" "shift")
6721 (set_attr "maybe_var_shift" "yes")
6722 (set_attr "dot" "yes")
6723 (set_attr "length" "4,8")])
6725 (define_insn "*rotldi3_internal11be"
6726 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6727 (compare:CC (zero_extend:DI
6728 (subreg:HI
6729 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6730 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6731 (const_int 0)))
6732 (clobber (match_scratch:DI 3 "=r,r"))]
6733 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6734 "@
6735 rld%I2cl. %3,%1,%H2,48
6736 #"
6737 [(set_attr "type" "shift")
6738 (set_attr "maybe_var_shift" "yes")
6739 (set_attr "dot" "yes")
6740 (set_attr "length" "4,8")])
6742 (define_split
6743 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6744 (compare:CC (zero_extend:DI
6745 (subreg:HI
6746 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6747 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6748 (const_int 0)))
6749 (clobber (match_scratch:DI 3 ""))]
6750 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6751 [(set (match_dup 3)
6752 (zero_extend:DI (subreg:HI
6753 (rotate:DI (match_dup 1)
6754 (match_dup 2)) 0)))
6755 (set (match_dup 0)
6756 (compare:CC (match_dup 3)
6757 (const_int 0)))]
6758 "")
6760 (define_split
6761 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6762 (compare:CC (zero_extend:DI
6763 (subreg:HI
6764 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6765 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6766 (const_int 0)))
6767 (clobber (match_scratch:DI 3 ""))]
6768 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6769 [(set (match_dup 3)
6770 (zero_extend:DI (subreg:HI
6771 (rotate:DI (match_dup 1)
6772 (match_dup 2)) 6)))
6773 (set (match_dup 0)
6774 (compare:CC (match_dup 3)
6775 (const_int 0)))]
6776 "")
6778 (define_insn "*rotldi3_internal12le"
6779 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6780 (compare:CC (zero_extend:DI
6781 (subreg:HI
6782 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6783 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6784 (const_int 0)))
6785 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6786 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6787 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6788 "@
6789 rld%I2cl. %0,%1,%H2,48
6790 #"
6791 [(set_attr "type" "shift")
6792 (set_attr "maybe_var_shift" "yes")
6793 (set_attr "dot" "yes")
6794 (set_attr "length" "4,8")])
6796 (define_insn "*rotldi3_internal12be"
6797 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6798 (compare:CC (zero_extend:DI
6799 (subreg:HI
6800 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6801 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
6802 (const_int 0)))
6803 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6804 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6805 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6806 "@
6807 rld%I2cl. %0,%1,%H2,48
6808 #"
6809 [(set_attr "type" "shift")
6810 (set_attr "maybe_var_shift" "yes")
6811 (set_attr "dot" "yes")
6812 (set_attr "length" "4,8")])
6814 (define_split
6815 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6816 (compare:CC (zero_extend:DI
6817 (subreg:HI
6818 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6819 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6820 (const_int 0)))
6821 (set (match_operand:DI 0 "gpc_reg_operand" "")
6822 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6823 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6824 [(set (match_dup 0)
6825 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6826 (set (match_dup 3)
6827 (compare:CC (match_dup 0)
6828 (const_int 0)))]
6829 "")
6831 (define_split
6832 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6833 (compare:CC (zero_extend:DI
6834 (subreg:HI
6835 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6836 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
6837 (const_int 0)))
6838 (set (match_operand:DI 0 "gpc_reg_operand" "")
6839 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
6840 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6841 [(set (match_dup 0)
6842 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
6843 (set (match_dup 3)
6844 (compare:CC (match_dup 0)
6845 (const_int 0)))]
6846 "")
6848 (define_insn "*rotldi3_internal13le"
6849 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6850 (zero_extend:DI
6851 (subreg:SI
6852 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6853 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
6854 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
6855 "rld%I2cl %0,%1,%H2,32"
6856 [(set_attr "type" "shift")
6857 (set_attr "maybe_var_shift" "yes")])
6859 (define_insn "*rotldi3_internal13be"
6860 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6861 (zero_extend:DI
6862 (subreg:SI
6863 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6864 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
6865 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
6866 "rld%I2cl %0,%1,%H2,32"
6867 [(set_attr "type" "shift")
6868 (set_attr "maybe_var_shift" "yes")])
6870 (define_insn "*rotldi3_internal14le"
6871 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6872 (compare:CC (zero_extend:DI
6873 (subreg:SI
6874 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6875 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6876 (const_int 0)))
6877 (clobber (match_scratch:DI 3 "=r,r"))]
6878 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6879 "@
6880 rld%I2cl. %3,%1,%H2,32
6881 #"
6882 [(set_attr "type" "shift")
6883 (set_attr "maybe_var_shift" "yes")
6884 (set_attr "dot" "yes")
6885 (set_attr "length" "4,8")])
6887 (define_insn "*rotldi3_internal14be"
6888 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6889 (compare:CC (zero_extend:DI
6890 (subreg:SI
6891 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6892 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6893 (const_int 0)))
6894 (clobber (match_scratch:DI 3 "=r,r"))]
6895 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6896 "@
6897 rld%I2cl. %3,%1,%H2,32
6898 #"
6899 [(set_attr "type" "shift")
6900 (set_attr "maybe_var_shift" "yes")
6901 (set_attr "dot" "yes")
6902 (set_attr "length" "4,8")])
6904 (define_split
6905 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6906 (compare:CC (zero_extend:DI
6907 (subreg:SI
6908 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6909 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6910 (const_int 0)))
6911 (clobber (match_scratch:DI 3 ""))]
6912 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6913 [(set (match_dup 3)
6914 (zero_extend:DI (subreg:SI
6915 (rotate:DI (match_dup 1)
6916 (match_dup 2)) 0)))
6917 (set (match_dup 0)
6918 (compare:CC (match_dup 3)
6919 (const_int 0)))]
6920 "")
6922 (define_split
6923 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6924 (compare:CC (zero_extend:DI
6925 (subreg:SI
6926 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6927 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6928 (const_int 0)))
6929 (clobber (match_scratch:DI 3 ""))]
6930 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
6931 [(set (match_dup 3)
6932 (zero_extend:DI (subreg:SI
6933 (rotate:DI (match_dup 1)
6934 (match_dup 2)) 4)))
6935 (set (match_dup 0)
6936 (compare:CC (match_dup 3)
6937 (const_int 0)))]
6938 "")
6940 (define_insn "*rotldi3_internal15le"
6941 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6942 (compare:CC (zero_extend:DI
6943 (subreg:SI
6944 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6945 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
6946 (const_int 0)))
6947 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6948 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6949 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
6950 "@
6951 rld%I2cl. %0,%1,%H2,32
6952 #"
6953 [(set_attr "type" "shift")
6954 (set_attr "maybe_var_shift" "yes")
6955 (set_attr "dot" "yes")
6956 (set_attr "length" "4,8")])
6958 (define_insn "*rotldi3_internal15be"
6959 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6960 (compare:CC (zero_extend:DI
6961 (subreg:SI
6962 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6963 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
6964 (const_int 0)))
6965 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6966 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
6967 "TARGET_64BIT && BYTES_BIG_ENDIAN"
6968 "@
6969 rld%I2cl. %0,%1,%H2,32
6970 #"
6971 [(set_attr "type" "shift")
6972 (set_attr "maybe_var_shift" "yes")
6973 (set_attr "dot" "yes")
6974 (set_attr "length" "4,8")])
6976 (define_split
6977 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6978 (compare:CC (zero_extend:DI
6979 (subreg:SI
6980 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6981 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6982 (const_int 0)))
6983 (set (match_operand:DI 0 "gpc_reg_operand" "")
6984 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6985 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
6986 [(set (match_dup 0)
6987 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6988 (set (match_dup 3)
6989 (compare:CC (match_dup 0)
6990 (const_int 0)))]
6991 "")
6993 (define_split
6994 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6995 (compare:CC (zero_extend:DI
6996 (subreg:SI
6997 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6998 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
6999 (const_int 0)))
7000 (set (match_operand:DI 0 "gpc_reg_operand" "")
7001 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7002 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7003 [(set (match_dup 0)
7004 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7005 (set (match_dup 3)
7006 (compare:CC (match_dup 0)
7007 (const_int 0)))]
7008 "")
7010 (define_insn "*ashldi3_internal4"
7011 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7012 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7013 (match_operand:SI 2 "const_int_operand" "i"))
7014 (match_operand:DI 3 "const_int_operand" "n")))]
7015 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7016 "rldic %0,%1,%H2,%W3"
7017 [(set_attr "type" "shift")])
7019 (define_insn "ashldi3_internal5"
7020 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7021 (compare:CC
7022 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7023 (match_operand:SI 2 "const_int_operand" "i,i"))
7024 (match_operand:DI 3 "const_int_operand" "n,n"))
7025 (const_int 0)))
7026 (clobber (match_scratch:DI 4 "=r,r"))]
7027 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7028 "@
7029 rldic. %4,%1,%H2,%W3
7030 #"
7031 [(set_attr "type" "shift")
7032 (set_attr "dot" "yes")
7033 (set_attr "length" "4,8")])
7035 (define_split
7036 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7037 (compare:CC
7038 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7039 (match_operand:SI 2 "const_int_operand" ""))
7040 (match_operand:DI 3 "const_int_operand" ""))
7041 (const_int 0)))
7042 (clobber (match_scratch:DI 4 ""))]
7043 "TARGET_POWERPC64 && reload_completed
7044 && includes_rldic_lshift_p (operands[2], operands[3])"
7045 [(set (match_dup 4)
7046 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7047 (match_dup 3)))
7048 (set (match_dup 0)
7049 (compare:CC (match_dup 4)
7050 (const_int 0)))]
7051 "")
7053 (define_insn "*ashldi3_internal6"
7054 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7055 (compare:CC
7056 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7057 (match_operand:SI 2 "const_int_operand" "i,i"))
7058 (match_operand:DI 3 "const_int_operand" "n,n"))
7059 (const_int 0)))
7060 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7061 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7062 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7063 "@
7064 rldic. %0,%1,%H2,%W3
7065 #"
7066 [(set_attr "type" "shift")
7067 (set_attr "dot" "yes")
7068 (set_attr "length" "4,8")])
7070 (define_split
7071 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7072 (compare:CC
7073 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7074 (match_operand:SI 2 "const_int_operand" ""))
7075 (match_operand:DI 3 "const_int_operand" ""))
7076 (const_int 0)))
7077 (set (match_operand:DI 0 "gpc_reg_operand" "")
7078 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7079 "TARGET_POWERPC64 && reload_completed
7080 && includes_rldic_lshift_p (operands[2], operands[3])"
7081 [(set (match_dup 0)
7082 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7083 (match_dup 3)))
7084 (set (match_dup 4)
7085 (compare:CC (match_dup 0)
7086 (const_int 0)))]
7087 "")
7089 (define_insn "*ashldi3_internal7"
7090 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7091 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7092 (match_operand:SI 2 "const_int_operand" "i"))
7093 (match_operand:DI 3 "mask64_operand" "n")))]
7094 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7095 "rldicr %0,%1,%H2,%S3"
7096 [(set_attr "type" "shift")])
7098 (define_insn "ashldi3_internal8"
7099 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7100 (compare:CC
7101 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7102 (match_operand:SI 2 "const_int_operand" "i,i"))
7103 (match_operand:DI 3 "mask64_operand" "n,n"))
7104 (const_int 0)))
7105 (clobber (match_scratch:DI 4 "=r,r"))]
7106 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7107 "@
7108 rldicr. %4,%1,%H2,%S3
7109 #"
7110 [(set_attr "type" "shift")
7111 (set_attr "dot" "yes")
7112 (set_attr "length" "4,8")])
7114 (define_split
7115 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7116 (compare:CC
7117 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7118 (match_operand:SI 2 "const_int_operand" ""))
7119 (match_operand:DI 3 "mask64_operand" ""))
7120 (const_int 0)))
7121 (clobber (match_scratch:DI 4 ""))]
7122 "TARGET_POWERPC64 && reload_completed
7123 && includes_rldicr_lshift_p (operands[2], operands[3])"
7124 [(set (match_dup 4)
7125 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7126 (match_dup 3)))
7127 (set (match_dup 0)
7128 (compare:CC (match_dup 4)
7129 (const_int 0)))]
7130 "")
7132 (define_insn "*ashldi3_internal9"
7133 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7134 (compare:CC
7135 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7136 (match_operand:SI 2 "const_int_operand" "i,i"))
7137 (match_operand:DI 3 "mask64_operand" "n,n"))
7138 (const_int 0)))
7139 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7140 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7141 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7142 "@
7143 rldicr. %0,%1,%H2,%S3
7144 #"
7145 [(set_attr "type" "shift")
7146 (set_attr "dot" "yes")
7147 (set_attr "length" "4,8")])
7149 (define_split
7150 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7151 (compare:CC
7152 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7153 (match_operand:SI 2 "const_int_operand" ""))
7154 (match_operand:DI 3 "mask64_operand" ""))
7155 (const_int 0)))
7156 (set (match_operand:DI 0 "gpc_reg_operand" "")
7157 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7158 "TARGET_POWERPC64 && reload_completed
7159 && includes_rldicr_lshift_p (operands[2], operands[3])"
7160 [(set (match_dup 0)
7161 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7162 (match_dup 3)))
7163 (set (match_dup 4)
7164 (compare:CC (match_dup 0)
7165 (const_int 0)))]
7166 "")
7169 (define_insn_and_split "*anddi3_2rld"
7170 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7171 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
7172 (match_operand:DI 2 "and_2rld_operand" "n")))]
7173 "TARGET_POWERPC64"
7174 "#"
7175 ""
7176 [(set (match_dup 0)
7177 (and:DI (rotate:DI (match_dup 1)
7178 (match_dup 4))
7179 (match_dup 5)))
7180 (set (match_dup 0)
7181 (and:DI (rotate:DI (match_dup 0)
7182 (match_dup 6))
7183 (match_dup 7)))]
7184 {
7185 build_mask64_2_operands (operands[2], &operands[4]);
7186 }
7187 [(set_attr "length" "8")])
7189 (define_insn_and_split "*anddi3_2rld_dot"
7190 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7191 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7192 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7193 (const_int 0)))
7194 (clobber (match_scratch:DI 0 "=r,r"))]
7195 "TARGET_64BIT && rs6000_gen_cell_microcode"
7196 "@
7197 #
7198 #"
7199 "&& reload_completed"
7200 [(set (match_dup 0)
7201 (and:DI (rotate:DI (match_dup 1)
7202 (match_dup 4))
7203 (match_dup 5)))
7204 (parallel [(set (match_dup 3)
7205 (compare:CC (and:DI (rotate:DI (match_dup 0)
7206 (match_dup 6))
7207 (match_dup 7))
7208 (const_int 0)))
7209 (clobber (match_dup 0))])]
7210 {
7211 build_mask64_2_operands (operands[2], &operands[4]);
7212 }
7213 [(set_attr "type" "compare")
7214 (set_attr "dot" "yes")
7215 (set_attr "length" "8,12")])
7217 (define_insn_and_split "*anddi3_2rld_dot2"
7218 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7219 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7220 (match_operand:DI 2 "and_2rld_operand" "n,n"))
7221 (const_int 0)))
7222 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7223 (and:DI (match_dup 1)
7224 (match_dup 2)))]
7225 "TARGET_64BIT && rs6000_gen_cell_microcode"
7226 "@
7227 #
7228 #"
7229 "&& reload_completed"
7230 [(set (match_dup 0)
7231 (and:DI (rotate:DI (match_dup 1)
7232 (match_dup 4))
7233 (match_dup 5)))
7234 (parallel [(set (match_dup 3)
7235 (compare:CC (and:DI (rotate:DI (match_dup 0)
7236 (match_dup 6))
7237 (match_dup 7))
7238 (const_int 0)))
7239 (set (match_dup 0)
7240 (and:DI (rotate:DI (match_dup 0)
7241 (match_dup 6))
7242 (match_dup 7)))])]
7243 {
7244 build_mask64_2_operands (operands[2], &operands[4]);
7245 }
7246 [(set_attr "type" "compare")
7247 (set_attr "dot" "yes")
7248 (set_attr "length" "8,12")])
7249 \f
7250 ;; 128-bit logical operations expanders
7252 (define_expand "and<mode>3"
7253 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7254 (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7255 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7256 ""
7257 "")
7259 (define_expand "ior<mode>3"
7260 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7261 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7262 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7263 ""
7264 "")
7266 (define_expand "xor<mode>3"
7267 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7268 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7269 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
7270 ""
7271 "")
7273 (define_expand "one_cmpl<mode>2"
7274 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7275 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7276 ""
7277 "")
7279 (define_expand "nor<mode>3"
7280 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7281 (and:BOOL_128
7282 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7283 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7284 ""
7285 "")
7287 (define_expand "andc<mode>3"
7288 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7289 (and:BOOL_128
7290 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7291 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7292 ""
7293 "")
7295 ;; Power8 vector logical instructions.
7296 (define_expand "eqv<mode>3"
7297 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7298 (not:BOOL_128
7299 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
7300 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7301 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7302 "")
7304 ;; Rewrite nand into canonical form
7305 (define_expand "nand<mode>3"
7306 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7307 (ior:BOOL_128
7308 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
7309 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
7310 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7311 "")
7313 ;; The canonical form is to have the negated element first, so we need to
7314 ;; reverse arguments.
7315 (define_expand "orc<mode>3"
7316 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7317 (ior:BOOL_128
7318 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
7319 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
7320 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7321 "")
7323 ;; 128-bit logical operations insns and split operations
7324 (define_insn_and_split "*and<mode>3_internal"
7325 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7326 (and:BOOL_128
7327 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7328 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
7329 ""
7330 {
7331 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7332 return "xxland %x0,%x1,%x2";
7334 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7335 return "vand %0,%1,%2";
7337 return "#";
7338 }
7339 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7340 [(const_int 0)]
7341 {
7342 rs6000_split_logical (operands, AND, false, false, false);
7343 DONE;
7344 }
7345 [(set (attr "type")
7346 (if_then_else
7347 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7348 (const_string "vecsimple")
7349 (const_string "integer")))
7350 (set (attr "length")
7351 (if_then_else
7352 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7353 (const_string "4")
7354 (if_then_else
7355 (match_test "TARGET_POWERPC64")
7356 (const_string "8")
7357 (const_string "16"))))])
7359 ;; 128-bit IOR/XOR
7360 (define_insn_and_split "*bool<mode>3_internal"
7361 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7362 (match_operator:BOOL_128 3 "boolean_or_operator"
7363 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7364 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7365 ""
7366 {
7367 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7368 return "xxl%q3 %x0,%x1,%x2";
7370 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7371 return "v%q3 %0,%1,%2";
7373 return "#";
7374 }
7375 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7376 [(const_int 0)]
7377 {
7378 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
7379 DONE;
7380 }
7381 [(set (attr "type")
7382 (if_then_else
7383 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7384 (const_string "vecsimple")
7385 (const_string "integer")))
7386 (set (attr "length")
7387 (if_then_else
7388 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7389 (const_string "4")
7390 (if_then_else
7391 (match_test "TARGET_POWERPC64")
7392 (const_string "8")
7393 (const_string "16"))))])
7395 ;; 128-bit ANDC/ORC
7396 (define_insn_and_split "*boolc<mode>3_internal1"
7397 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7398 (match_operator:BOOL_128 3 "boolean_operator"
7399 [(not:BOOL_128
7400 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
7401 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7402 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7403 {
7404 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7405 return "xxl%q3 %x0,%x1,%x2";
7407 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7408 return "v%q3 %0,%1,%2";
7410 return "#";
7411 }
7412 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7413 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7414 [(const_int 0)]
7415 {
7416 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7417 DONE;
7418 }
7419 [(set (attr "type")
7420 (if_then_else
7421 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7422 (const_string "vecsimple")
7423 (const_string "integer")))
7424 (set (attr "length")
7425 (if_then_else
7426 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7427 (const_string "4")
7428 (if_then_else
7429 (match_test "TARGET_POWERPC64")
7430 (const_string "8")
7431 (const_string "16"))))])
7433 (define_insn_and_split "*boolc<mode>3_internal2"
7434 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7435 (match_operator:TI2 3 "boolean_operator"
7436 [(not:TI2
7437 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7438 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
7439 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7440 "#"
7441 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7442 [(const_int 0)]
7443 {
7444 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
7445 DONE;
7446 }
7447 [(set_attr "type" "integer")
7448 (set (attr "length")
7449 (if_then_else
7450 (match_test "TARGET_POWERPC64")
7451 (const_string "8")
7452 (const_string "16")))])
7454 ;; 128-bit NAND/NOR
7455 (define_insn_and_split "*boolcc<mode>3_internal1"
7456 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7457 (match_operator:BOOL_128 3 "boolean_operator"
7458 [(not:BOOL_128
7459 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
7460 (not:BOOL_128
7461 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
7462 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
7463 {
7464 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7465 return "xxl%q3 %x0,%x1,%x2";
7467 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7468 return "v%q3 %0,%1,%2";
7470 return "#";
7471 }
7472 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
7473 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7474 [(const_int 0)]
7475 {
7476 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7477 DONE;
7478 }
7479 [(set (attr "type")
7480 (if_then_else
7481 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7482 (const_string "vecsimple")
7483 (const_string "integer")))
7484 (set (attr "length")
7485 (if_then_else
7486 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7487 (const_string "4")
7488 (if_then_else
7489 (match_test "TARGET_POWERPC64")
7490 (const_string "8")
7491 (const_string "16"))))])
7493 (define_insn_and_split "*boolcc<mode>3_internal2"
7494 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7495 (match_operator:TI2 3 "boolean_operator"
7496 [(not:TI2
7497 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
7498 (not:TI2
7499 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
7500 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7501 "#"
7502 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
7503 [(const_int 0)]
7504 {
7505 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
7506 DONE;
7507 }
7508 [(set_attr "type" "integer")
7509 (set (attr "length")
7510 (if_then_else
7511 (match_test "TARGET_POWERPC64")
7512 (const_string "8")
7513 (const_string "16")))])
7516 ;; 128-bit EQV
7517 (define_insn_and_split "*eqv<mode>3_internal1"
7518 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7519 (not:BOOL_128
7520 (xor:BOOL_128
7521 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
7522 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
7523 "TARGET_P8_VECTOR"
7524 {
7525 if (vsx_register_operand (operands[0], <MODE>mode))
7526 return "xxleqv %x0,%x1,%x2";
7528 return "#";
7529 }
7530 "TARGET_P8_VECTOR && reload_completed
7531 && int_reg_operand (operands[0], <MODE>mode)"
7532 [(const_int 0)]
7533 {
7534 rs6000_split_logical (operands, XOR, true, false, false);
7535 DONE;
7536 }
7537 [(set (attr "type")
7538 (if_then_else
7539 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7540 (const_string "vecsimple")
7541 (const_string "integer")))
7542 (set (attr "length")
7543 (if_then_else
7544 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7545 (const_string "4")
7546 (if_then_else
7547 (match_test "TARGET_POWERPC64")
7548 (const_string "8")
7549 (const_string "16"))))])
7551 (define_insn_and_split "*eqv<mode>3_internal2"
7552 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
7553 (not:TI2
7554 (xor:TI2
7555 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
7556 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
7557 "!TARGET_P8_VECTOR"
7558 "#"
7559 "reload_completed && !TARGET_P8_VECTOR"
7560 [(const_int 0)]
7561 {
7562 rs6000_split_logical (operands, XOR, true, false, false);
7563 DONE;
7564 }
7565 [(set_attr "type" "integer")
7566 (set (attr "length")
7567 (if_then_else
7568 (match_test "TARGET_POWERPC64")
7569 (const_string "8")
7570 (const_string "16")))])
7572 ;; 128-bit one's complement
7573 (define_insn_and_split "*one_cmpl<mode>3_internal"
7574 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7575 (not:BOOL_128
7576 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
7577 ""
7578 {
7579 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
7580 return "xxlnor %x0,%x1,%x1";
7582 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
7583 return "vnor %0,%1,%1";
7585 return "#";
7586 }
7587 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
7588 [(const_int 0)]
7589 {
7590 rs6000_split_logical (operands, NOT, false, false, false);
7591 DONE;
7592 }
7593 [(set (attr "type")
7594 (if_then_else
7595 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7596 (const_string "vecsimple")
7597 (const_string "integer")))
7598 (set (attr "length")
7599 (if_then_else
7600 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
7601 (const_string "4")
7602 (if_then_else
7603 (match_test "TARGET_POWERPC64")
7604 (const_string "8")
7605 (const_string "16"))))])
7607 \f
7608 ;; Now define ways of moving data around.
7610 ;; Set up a register with a value from the GOT table
7612 (define_expand "movsi_got"
7613 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7614 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7615 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7616 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7617 "
7618 {
7619 if (GET_CODE (operands[1]) == CONST)
7620 {
7621 rtx offset = const0_rtx;
7622 HOST_WIDE_INT value;
7624 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7625 value = INTVAL (offset);
7626 if (value != 0)
7627 {
7628 rtx tmp = (!can_create_pseudo_p ()
7629 ? operands[0]
7630 : gen_reg_rtx (Pmode));
7631 emit_insn (gen_movsi_got (tmp, operands[1]));
7632 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7633 DONE;
7634 }
7635 }
7637 operands[2] = rs6000_got_register (operands[1]);
7638 }")
7640 (define_insn "*movsi_got_internal"
7641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7642 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7643 (match_operand:SI 2 "gpc_reg_operand" "b")]
7644 UNSPEC_MOVSI_GOT))]
7645 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7646 "lwz %0,%a1@got(%2)"
7647 [(set_attr "type" "load")])
7649 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7650 ;; didn't get allocated to a hard register.
7651 (define_split
7652 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7653 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7654 (match_operand:SI 2 "memory_operand" "")]
7655 UNSPEC_MOVSI_GOT))]
7656 "DEFAULT_ABI == ABI_V4
7657 && flag_pic == 1
7658 && (reload_in_progress || reload_completed)"
7659 [(set (match_dup 0) (match_dup 2))
7660 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7661 UNSPEC_MOVSI_GOT))]
7662 "")
7664 ;; For SI, we special-case integers that can't be loaded in one insn. We
7665 ;; do the load 16-bits at a time. We could do this by loading from memory,
7666 ;; and this is even supposed to be faster, but it is simpler not to get
7667 ;; integers in the TOC.
7668 (define_insn "movsi_low"
7669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7670 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7671 (match_operand 2 "" ""))))]
7672 "TARGET_MACHO && ! TARGET_64BIT"
7673 "lwz %0,lo16(%2)(%1)"
7674 [(set_attr "type" "load")
7675 (set_attr "length" "4")])
7677 (define_insn "*movsi_internal1"
7678 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7679 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7680 "!TARGET_SINGLE_FPU &&
7681 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7682 "@
7683 mr %0,%1
7684 la %0,%a1
7685 lwz%U1%X1 %0,%1
7686 stw%U0%X0 %1,%0
7687 li %0,%1
7688 lis %0,%v1
7689 #
7690 mf%1 %0
7691 mt%0 %1
7692 mt%0 %1
7693 nop"
7694 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7695 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7697 (define_insn "*movsi_internal1_single"
7698 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7699 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7700 "TARGET_SINGLE_FPU &&
7701 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7702 "@
7703 mr %0,%1
7704 la %0,%a1
7705 lwz%U1%X1 %0,%1
7706 stw%U0%X0 %1,%0
7707 li %0,%1
7708 lis %0,%v1
7709 #
7710 mf%1 %0
7711 mt%0 %1
7712 mt%0 %1
7713 nop
7714 stfs%U0%X0 %1,%0
7715 lfs%U1%X1 %0,%1"
7716 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
7717 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7719 ;; Split a load of a large constant into the appropriate two-insn
7720 ;; sequence.
7722 (define_split
7723 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7724 (match_operand:SI 1 "const_int_operand" ""))]
7725 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7726 && (INTVAL (operands[1]) & 0xffff) != 0"
7727 [(set (match_dup 0)
7728 (match_dup 2))
7729 (set (match_dup 0)
7730 (ior:SI (match_dup 0)
7731 (match_dup 3)))]
7732 "
7733 {
7734 if (rs6000_emit_set_const (operands[0], operands[1]))
7735 DONE;
7736 else
7737 FAIL;
7738 }")
7740 (define_insn "*mov<mode>_internal2"
7741 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7742 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7743 (const_int 0)))
7744 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7745 ""
7746 "@
7747 cmp<wd>i %2,%0,0
7748 mr. %0,%1
7749 #"
7750 [(set_attr "type" "cmp,logical,cmp")
7751 (set_attr "dot" "yes")
7752 (set_attr "length" "4,4,8")])
7754 (define_split
7755 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7756 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7757 (const_int 0)))
7758 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7759 "reload_completed"
7760 [(set (match_dup 0) (match_dup 1))
7761 (set (match_dup 2)
7762 (compare:CC (match_dup 0)
7763 (const_int 0)))]
7764 "")
7765 \f
7766 (define_insn "*movhi_internal"
7767 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7768 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7769 "gpc_reg_operand (operands[0], HImode)
7770 || gpc_reg_operand (operands[1], HImode)"
7771 "@
7772 mr %0,%1
7773 lhz%U1%X1 %0,%1
7774 sth%U0%X0 %1,%0
7775 li %0,%w1
7776 mf%1 %0
7777 mt%0 %1
7778 nop"
7779 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7781 (define_expand "mov<mode>"
7782 [(set (match_operand:INT 0 "general_operand" "")
7783 (match_operand:INT 1 "any_operand" ""))]
7784 ""
7785 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7787 (define_insn "*movqi_internal"
7788 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7789 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7790 "gpc_reg_operand (operands[0], QImode)
7791 || gpc_reg_operand (operands[1], QImode)"
7792 "@
7793 mr %0,%1
7794 lbz%U1%X1 %0,%1
7795 stb%U0%X0 %1,%0
7796 li %0,%1
7797 mf%1 %0
7798 mt%0 %1
7799 nop"
7800 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7801 \f
7802 ;; Here is how to move condition codes around. When we store CC data in
7803 ;; an integer register or memory, we store just the high-order 4 bits.
7804 ;; This lets us not shift in the most common case of CR0.
7805 (define_expand "movcc"
7806 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7807 (match_operand:CC 1 "nonimmediate_operand" ""))]
7808 ""
7809 "")
7811 (define_insn "*movcc_internal1"
7812 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7813 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7814 "register_operand (operands[0], CCmode)
7815 || register_operand (operands[1], CCmode)"
7816 "@
7817 mcrf %0,%1
7818 mtcrf 128,%1
7819 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7820 crxor %0,%0,%0
7821 mfcr %0%Q1
7822 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7823 mr %0,%1
7824 li %0,%1
7825 mf%1 %0
7826 mt%0 %1
7827 lwz%U1%X1 %0,%1
7828 stw%U0%X0 %1,%0"
7829 [(set (attr "type")
7830 (cond [(eq_attr "alternative" "0,3")
7831 (const_string "cr_logical")
7832 (eq_attr "alternative" "1,2")
7833 (const_string "mtcr")
7834 (eq_attr "alternative" "6,7")
7835 (const_string "integer")
7836 (eq_attr "alternative" "8")
7837 (const_string "mfjmpr")
7838 (eq_attr "alternative" "9")
7839 (const_string "mtjmpr")
7840 (eq_attr "alternative" "10")
7841 (const_string "load")
7842 (eq_attr "alternative" "11")
7843 (const_string "store")
7844 (match_test "TARGET_MFCRF")
7845 (const_string "mfcrf")
7846 ]
7847 (const_string "mfcr")))
7848 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
7849 \f
7850 ;; For floating-point, we normally deal with the floating-point registers
7851 ;; unless -msoft-float is used. The sole exception is that parameter passing
7852 ;; can produce floating-point values in fixed-point registers. Unless the
7853 ;; value is a simple constant or already in memory, we deal with this by
7854 ;; allocating memory and copying the value explicitly via that memory location.
7856 ;; Move 32-bit binary/decimal floating point
7857 (define_expand "mov<mode>"
7858 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
7859 (match_operand:FMOVE32 1 "any_operand" ""))]
7860 "<fmove_ok>"
7861 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7863 (define_split
7864 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
7865 (match_operand:FMOVE32 1 "const_double_operand" ""))]
7866 "reload_completed
7867 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7868 || (GET_CODE (operands[0]) == SUBREG
7869 && GET_CODE (SUBREG_REG (operands[0])) == REG
7870 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7871 [(set (match_dup 2) (match_dup 3))]
7872 "
7873 {
7874 long l;
7875 REAL_VALUE_TYPE rv;
7877 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7878 <real_value_to_target> (rv, l);
7880 if (! TARGET_POWERPC64)
7881 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
7882 else
7883 operands[2] = gen_lowpart (SImode, operands[0]);
7885 operands[3] = gen_int_mode (l, SImode);
7886 }")
7888 (define_insn "mov<mode>_hardfloat"
7889 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
7890 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
7891 "(gpc_reg_operand (operands[0], <MODE>mode)
7892 || gpc_reg_operand (operands[1], <MODE>mode))
7893 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
7894 "@
7895 mr %0,%1
7896 lwz%U1%X1 %0,%1
7897 stw%U0%X0 %1,%0
7898 fmr %0,%1
7899 xxlor %x0,%x1,%x1
7900 xxlxor %x0,%x0,%x0
7901 <f32_li>
7902 <f32_si>
7903 <f32_lv>
7904 <f32_sv>
7905 mtvsrwz %x0,%1
7906 mfvsrwz %0,%x1
7907 mt%0 %1
7908 mf%1 %0
7909 nop
7910 #
7911 #"
7912 [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
7913 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
7915 (define_insn "*mov<mode>_softfloat"
7916 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
7917 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
7918 "(gpc_reg_operand (operands[0], <MODE>mode)
7919 || gpc_reg_operand (operands[1], <MODE>mode))
7920 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7921 "@
7922 mr %0,%1
7923 mt%0 %1
7924 mf%1 %0
7925 lwz%U1%X1 %0,%1
7926 stw%U0%X0 %1,%0
7927 li %0,%1
7928 lis %0,%v1
7929 #
7930 #
7931 nop"
7932 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
7933 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
7935 \f
7936 ;; Move 64-bit binary/decimal floating point
7937 (define_expand "mov<mode>"
7938 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
7939 (match_operand:FMOVE64 1 "any_operand" ""))]
7940 ""
7941 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7943 (define_split
7944 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7945 (match_operand:FMOVE64 1 "const_int_operand" ""))]
7946 "! TARGET_POWERPC64 && reload_completed
7947 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7948 || (GET_CODE (operands[0]) == SUBREG
7949 && GET_CODE (SUBREG_REG (operands[0])) == REG
7950 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7951 [(set (match_dup 2) (match_dup 4))
7952 (set (match_dup 3) (match_dup 1))]
7953 "
7954 {
7955 int endian = (WORDS_BIG_ENDIAN == 0);
7956 HOST_WIDE_INT value = INTVAL (operands[1]);
7958 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7959 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7960 operands[4] = GEN_INT (value >> 32);
7961 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7962 }")
7964 (define_split
7965 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7966 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7967 "! TARGET_POWERPC64 && reload_completed
7968 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7969 || (GET_CODE (operands[0]) == SUBREG
7970 && GET_CODE (SUBREG_REG (operands[0])) == REG
7971 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7972 [(set (match_dup 2) (match_dup 4))
7973 (set (match_dup 3) (match_dup 5))]
7974 "
7975 {
7976 int endian = (WORDS_BIG_ENDIAN == 0);
7977 long l[2];
7978 REAL_VALUE_TYPE rv;
7980 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7981 <real_value_to_target> (rv, l);
7983 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
7984 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
7985 operands[4] = gen_int_mode (l[endian], SImode);
7986 operands[5] = gen_int_mode (l[1 - endian], SImode);
7987 }")
7989 (define_split
7990 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
7991 (match_operand:FMOVE64 1 "const_double_operand" ""))]
7992 "TARGET_POWERPC64 && reload_completed
7993 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7994 || (GET_CODE (operands[0]) == SUBREG
7995 && GET_CODE (SUBREG_REG (operands[0])) == REG
7996 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7997 [(set (match_dup 2) (match_dup 3))]
7998 "
7999 {
8000 int endian = (WORDS_BIG_ENDIAN == 0);
8001 long l[2];
8002 REAL_VALUE_TYPE rv;
8003 HOST_WIDE_INT val;
8005 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8006 <real_value_to_target> (rv, l);
8008 operands[2] = gen_lowpart (DImode, operands[0]);
8009 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8010 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8011 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8013 operands[3] = gen_int_mode (val, DImode);
8014 }")
8016 ;; Don't have reload use general registers to load a constant. It is
8017 ;; less efficient than loading the constant into an FP register, since
8018 ;; it will probably be used there.
8020 ;; The move constraints are ordered to prefer floating point registers before
8021 ;; general purpose registers to avoid doing a store and a load to get the value
8022 ;; into a floating point register when it is needed for a floating point
8023 ;; operation. Prefer traditional floating point registers over VSX registers,
8024 ;; since the D-form version of the memory instructions does not need a GPR for
8025 ;; reloading.
8027 (define_insn "*mov<mode>_hardfloat32"
8028 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
8029 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
8030 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8031 && (gpc_reg_operand (operands[0], <MODE>mode)
8032 || gpc_reg_operand (operands[1], <MODE>mode))"
8033 "@
8034 stfd%U0%X0 %1,%0
8035 lfd%U1%X1 %0,%1
8036 fmr %0,%1
8037 lxsd%U1x %x0,%y1
8038 stxsd%U0x %x1,%y0
8039 xxlor %x0,%x1,%x1
8040 xxlxor %x0,%x0,%x0
8041 #
8042 #
8043 #
8044 #
8045 #
8046 #"
8047 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
8048 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
8050 (define_insn "*mov<mode>_softfloat32"
8051 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8052 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
8053 "! TARGET_POWERPC64
8054 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8055 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
8056 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
8057 && (gpc_reg_operand (operands[0], <MODE>mode)
8058 || gpc_reg_operand (operands[1], <MODE>mode))"
8059 "#"
8060 [(set_attr "type" "store,load,two,*,*,*")
8061 (set_attr "length" "8,8,8,8,12,16")])
8063 ; ld/std require word-aligned displacements -> 'Y' constraint.
8064 ; List Y->r and r->Y before r->r for reload.
8065 (define_insn "*mov<mode>_hardfloat64"
8066 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wk")
8067 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wk,r"))]
8068 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8069 && (gpc_reg_operand (operands[0], <MODE>mode)
8070 || gpc_reg_operand (operands[1], <MODE>mode))"
8071 "@
8072 stfd%U0%X0 %1,%0
8073 lfd%U1%X1 %0,%1
8074 fmr %0,%1
8075 lxsd%U1x %x0,%y1
8076 stxsd%U0x %x1,%y0
8077 xxlor %x0,%x1,%x1
8078 xxlxor %x0,%x0,%x0
8079 std%U0%X0 %1,%0
8080 ld%U1%X1 %0,%1
8081 mr %0,%1
8082 mt%0 %1
8083 mf%1 %0
8084 nop
8085 #
8086 #
8087 #
8088 mftgpr %0,%1
8089 mffgpr %0,%1
8090 mfvsrd %0,%x1
8091 mtvsrd %x0,%1"
8092 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
8093 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
8095 (define_insn "*mov<mode>_softfloat64"
8096 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8097 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8098 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8099 && (gpc_reg_operand (operands[0], <MODE>mode)
8100 || gpc_reg_operand (operands[1], <MODE>mode))"
8101 "@
8102 std%U0%X0 %1,%0
8103 ld%U1%X1 %0,%1
8104 mr %0,%1
8105 mt%0 %1
8106 mf%1 %0
8107 #
8108 #
8109 #
8110 nop"
8111 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8112 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8113 \f
8114 (define_expand "mov<mode>"
8115 [(set (match_operand:FMOVE128 0 "general_operand" "")
8116 (match_operand:FMOVE128 1 "any_operand" ""))]
8117 ""
8118 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8120 ;; It's important to list Y->r and r->Y before r->r because otherwise
8121 ;; reload, given m->r, will try to pick r->r and reload it, which
8122 ;; doesn't make progress.
8124 ;; We can't split little endian direct moves of TDmode, because the words are
8125 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
8126 ;; problematical. Don't allow direct move for this case.
8128 (define_insn_and_split "*mov<mode>_64bit_dm"
8129 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
8130 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
8131 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8132 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
8133 && (gpc_reg_operand (operands[0], <MODE>mode)
8134 || gpc_reg_operand (operands[1], <MODE>mode))"
8135 "#"
8136 "&& reload_completed"
8137 [(pc)]
8138 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8139 [(set_attr "length" "8,8,8,12,12,8,8,8")])
8141 (define_insn_and_split "*movtd_64bit_nodm"
8142 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8143 (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
8144 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
8145 && (gpc_reg_operand (operands[0], TDmode)
8146 || gpc_reg_operand (operands[1], TDmode))"
8147 "#"
8148 "&& reload_completed"
8149 [(pc)]
8150 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8151 [(set_attr "length" "8,8,8,12,12,8")])
8153 (define_insn_and_split "*mov<mode>_32bit"
8154 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8155 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
8156 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
8157 && (gpc_reg_operand (operands[0], <MODE>mode)
8158 || gpc_reg_operand (operands[1], <MODE>mode))"
8159 "#"
8160 "&& reload_completed"
8161 [(pc)]
8162 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8163 [(set_attr "length" "8,8,8,20,20,16")])
8165 (define_insn_and_split "*mov<mode>_softfloat"
8166 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8167 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
8168 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
8169 && (gpc_reg_operand (operands[0], <MODE>mode)
8170 || gpc_reg_operand (operands[1], <MODE>mode))"
8171 "#"
8172 "&& reload_completed"
8173 [(pc)]
8174 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8175 [(set_attr "length" "20,20,16")])
8177 (define_expand "extenddftf2"
8178 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8179 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8180 "!TARGET_IEEEQUAD
8181 && TARGET_HARD_FLOAT
8182 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8183 && TARGET_LONG_DOUBLE_128"
8184 {
8185 if (TARGET_E500_DOUBLE)
8186 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8187 else
8188 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8189 DONE;
8190 })
8192 (define_expand "extenddftf2_fprs"
8193 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8194 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8195 (use (match_dup 2))])]
8196 "!TARGET_IEEEQUAD
8197 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8198 && TARGET_LONG_DOUBLE_128"
8199 {
8200 operands[2] = CONST0_RTX (DFmode);
8201 /* Generate GOT reference early for SVR4 PIC. */
8202 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8203 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8204 })
8206 (define_insn_and_split "*extenddftf2_internal"
8207 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8208 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8209 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8210 "!TARGET_IEEEQUAD
8211 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8212 && TARGET_LONG_DOUBLE_128"
8213 "#"
8214 "&& reload_completed"
8215 [(pc)]
8216 {
8217 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8218 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8219 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8220 operands[1]);
8221 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8222 operands[2]);
8223 DONE;
8224 })
8226 (define_expand "extendsftf2"
8227 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8228 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8229 "!TARGET_IEEEQUAD
8230 && TARGET_HARD_FLOAT
8231 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8232 && TARGET_LONG_DOUBLE_128"
8233 {
8234 rtx tmp = gen_reg_rtx (DFmode);
8235 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8236 emit_insn (gen_extenddftf2 (operands[0], tmp));
8237 DONE;
8238 })
8240 (define_expand "trunctfdf2"
8241 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8242 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8243 "!TARGET_IEEEQUAD
8244 && TARGET_HARD_FLOAT
8245 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8246 && TARGET_LONG_DOUBLE_128"
8247 "")
8249 (define_insn_and_split "trunctfdf2_internal1"
8250 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8251 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8252 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8253 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8254 "@
8255 #
8256 fmr %0,%1"
8257 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8258 [(const_int 0)]
8259 {
8260 emit_note (NOTE_INSN_DELETED);
8261 DONE;
8262 }
8263 [(set_attr "type" "fp")])
8265 (define_insn "trunctfdf2_internal2"
8266 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8267 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8268 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8269 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8270 && TARGET_LONG_DOUBLE_128"
8271 "fadd %0,%1,%L1"
8272 [(set_attr "type" "fp")
8273 (set_attr "fp_type" "fp_addsub_d")])
8275 (define_expand "trunctfsf2"
8276 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8277 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8278 "!TARGET_IEEEQUAD
8279 && TARGET_HARD_FLOAT
8280 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8281 && TARGET_LONG_DOUBLE_128"
8282 {
8283 if (TARGET_E500_DOUBLE)
8284 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8285 else
8286 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8287 DONE;
8288 })
8290 (define_insn_and_split "trunctfsf2_fprs"
8291 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8292 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8293 (clobber (match_scratch:DF 2 "=d"))]
8294 "!TARGET_IEEEQUAD
8295 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8296 && TARGET_LONG_DOUBLE_128"
8297 "#"
8298 "&& reload_completed"
8299 [(set (match_dup 2)
8300 (float_truncate:DF (match_dup 1)))
8301 (set (match_dup 0)
8302 (float_truncate:SF (match_dup 2)))]
8303 "")
8305 (define_expand "floatsitf2"
8306 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8307 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8308 "!TARGET_IEEEQUAD
8309 && TARGET_HARD_FLOAT
8310 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8311 && TARGET_LONG_DOUBLE_128"
8312 {
8313 rtx tmp = gen_reg_rtx (DFmode);
8314 expand_float (tmp, operands[1], false);
8315 emit_insn (gen_extenddftf2 (operands[0], tmp));
8316 DONE;
8317 })
8319 ; fadd, but rounding towards zero.
8320 ; This is probably not the optimal code sequence.
8321 (define_insn "fix_trunc_helper"
8322 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8323 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8324 UNSPEC_FIX_TRUNC_TF))
8325 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8326 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8327 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8328 [(set_attr "type" "fp")
8329 (set_attr "length" "20")])
8331 (define_expand "fix_trunctfsi2"
8332 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8333 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8334 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8335 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8336 {
8337 if (TARGET_E500_DOUBLE)
8338 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8339 else
8340 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8341 DONE;
8342 })
8344 (define_expand "fix_trunctfsi2_fprs"
8345 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8346 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8347 (clobber (match_dup 2))
8348 (clobber (match_dup 3))
8349 (clobber (match_dup 4))
8350 (clobber (match_dup 5))])]
8351 "!TARGET_IEEEQUAD
8352 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8353 {
8354 operands[2] = gen_reg_rtx (DFmode);
8355 operands[3] = gen_reg_rtx (DFmode);
8356 operands[4] = gen_reg_rtx (DImode);
8357 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8358 })
8360 (define_insn_and_split "*fix_trunctfsi2_internal"
8361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8362 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8363 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8364 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8365 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8366 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8367 "!TARGET_IEEEQUAD
8368 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8369 "#"
8370 ""
8371 [(pc)]
8372 {
8373 rtx lowword;
8374 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8376 gcc_assert (MEM_P (operands[5]));
8377 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8379 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8380 emit_move_insn (operands[5], operands[4]);
8381 emit_move_insn (operands[0], lowword);
8382 DONE;
8383 })
8385 (define_expand "negtf2"
8386 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8387 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8388 "!TARGET_IEEEQUAD
8389 && TARGET_HARD_FLOAT
8390 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8391 && TARGET_LONG_DOUBLE_128"
8392 "")
8394 (define_insn "negtf2_internal"
8395 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8396 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8397 "!TARGET_IEEEQUAD
8398 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8399 "*
8400 {
8401 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8402 return \"fneg %L0,%L1\;fneg %0,%1\";
8403 else
8404 return \"fneg %0,%1\;fneg %L0,%L1\";
8405 }"
8406 [(set_attr "type" "fp")
8407 (set_attr "length" "8")])
8409 (define_expand "abstf2"
8410 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8411 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8412 "!TARGET_IEEEQUAD
8413 && TARGET_HARD_FLOAT
8414 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8415 && TARGET_LONG_DOUBLE_128"
8416 "
8417 {
8418 rtx label = gen_label_rtx ();
8419 if (TARGET_E500_DOUBLE)
8420 {
8421 if (flag_finite_math_only && !flag_trapping_math)
8422 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8423 else
8424 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8425 }
8426 else
8427 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8428 emit_label (label);
8429 DONE;
8430 }")
8432 (define_expand "abstf2_internal"
8433 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8434 (match_operand:TF 1 "gpc_reg_operand" ""))
8435 (set (match_dup 3) (match_dup 5))
8436 (set (match_dup 5) (abs:DF (match_dup 5)))
8437 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8438 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8439 (label_ref (match_operand 2 "" ""))
8440 (pc)))
8441 (set (match_dup 6) (neg:DF (match_dup 6)))]
8442 "!TARGET_IEEEQUAD
8443 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8444 && TARGET_LONG_DOUBLE_128"
8445 "
8446 {
8447 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8448 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8449 operands[3] = gen_reg_rtx (DFmode);
8450 operands[4] = gen_reg_rtx (CCFPmode);
8451 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8452 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8453 }")
8454 \f
8455 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
8456 ;; must have 3 arguments, and scratch register constraint must be a single
8457 ;; constraint.
8459 ;; Reload patterns to support gpr load/store with misaligned mem.
8460 ;; and multiple gpr load/store at offset >= 0xfffc
8461 (define_expand "reload_<mode>_store"
8462 [(parallel [(match_operand 0 "memory_operand" "=m")
8463 (match_operand 1 "gpc_reg_operand" "r")
8464 (match_operand:GPR 2 "register_operand" "=&b")])]
8465 ""
8466 {
8467 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8468 DONE;
8469 })
8471 (define_expand "reload_<mode>_load"
8472 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8473 (match_operand 1 "memory_operand" "m")
8474 (match_operand:GPR 2 "register_operand" "=b")])]
8475 ""
8476 {
8477 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8478 DONE;
8479 })
8481 \f
8482 ;; Power8 merge instructions to allow direct move to/from floating point
8483 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
8484 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
8485 ;; value, since it is allocated in reload and not all of the flow information
8486 ;; is setup for it. We have two patterns to do the two moves between gprs and
8487 ;; fprs. There isn't a dependancy between the two, but we could potentially
8488 ;; schedule other instructions between the two instructions. TFmode is
8489 ;; currently limited to traditional FPR registers. If/when this is changed, we
8490 ;; will need to revist %L to make sure it works with VSX registers, or add an
8491 ;; %x version of %L.
8493 (define_insn "p8_fmrgow_<mode>"
8494 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
8495 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
8496 UNSPEC_P8V_FMRGOW))]
8497 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8498 "fmrgow %0,%1,%L1"
8499 [(set_attr "type" "vecperm")])
8501 (define_insn "p8_mtvsrwz_1"
8502 [(set (match_operand:TF 0 "register_operand" "=d")
8503 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
8504 UNSPEC_P8V_MTVSRWZ))]
8505 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8506 "mtvsrwz %x0,%1"
8507 [(set_attr "type" "mftgpr")])
8509 (define_insn "p8_mtvsrwz_2"
8510 [(set (match_operand:TF 0 "register_operand" "+d")
8511 (unspec:TF [(match_dup 0)
8512 (match_operand:SI 1 "register_operand" "r")]
8513 UNSPEC_P8V_MTVSRWZ))]
8514 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8515 "mtvsrwz %L0,%1"
8516 [(set_attr "type" "mftgpr")])
8518 (define_insn_and_split "reload_fpr_from_gpr<mode>"
8519 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
8520 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
8521 UNSPEC_P8V_RELOAD_FROM_GPR))
8522 (clobber (match_operand:TF 2 "register_operand" "=d"))]
8523 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8524 "#"
8525 "&& reload_completed"
8526 [(const_int 0)]
8527 {
8528 rtx dest = operands[0];
8529 rtx src = operands[1];
8530 rtx tmp = operands[2];
8531 rtx gpr_hi_reg = gen_highpart (SImode, src);
8532 rtx gpr_lo_reg = gen_lowpart (SImode, src);
8534 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
8535 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
8536 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
8537 DONE;
8538 }
8539 [(set_attr "length" "12")
8540 (set_attr "type" "three")])
8542 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
8543 (define_insn "p8_mtvsrd_1"
8544 [(set (match_operand:TF 0 "register_operand" "=ws")
8545 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
8546 UNSPEC_P8V_MTVSRD))]
8547 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8548 "mtvsrd %0,%1"
8549 [(set_attr "type" "mftgpr")])
8551 (define_insn "p8_mtvsrd_2"
8552 [(set (match_operand:TF 0 "register_operand" "+ws")
8553 (unspec:TF [(match_dup 0)
8554 (match_operand:DI 1 "register_operand" "r")]
8555 UNSPEC_P8V_MTVSRD))]
8556 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8557 "mtvsrd %L0,%1"
8558 [(set_attr "type" "mftgpr")])
8560 (define_insn "p8_xxpermdi_<mode>"
8561 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8562 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
8563 UNSPEC_P8V_XXPERMDI))]
8564 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8565 "xxpermdi %x0,%1,%L1,0"
8566 [(set_attr "type" "vecperm")])
8568 (define_insn_and_split "reload_vsx_from_gpr<mode>"
8569 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
8570 (unspec:FMOVE128_GPR
8571 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
8572 UNSPEC_P8V_RELOAD_FROM_GPR))
8573 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
8574 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8575 "#"
8576 "&& reload_completed"
8577 [(const_int 0)]
8578 {
8579 rtx dest = operands[0];
8580 rtx src = operands[1];
8581 rtx tmp = operands[2];
8582 rtx gpr_hi_reg = gen_highpart (DImode, src);
8583 rtx gpr_lo_reg = gen_lowpart (DImode, src);
8585 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
8586 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
8587 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
8588 }
8589 [(set_attr "length" "12")
8590 (set_attr "type" "three")])
8592 (define_split
8593 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
8594 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
8595 "reload_completed
8596 && (int_reg_operand (operands[0], <MODE>mode)
8597 || int_reg_operand (operands[1], <MODE>mode))"
8598 [(pc)]
8599 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8601 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
8602 ;; type is stored internally as double precision in the VSX registers, we have
8603 ;; to convert it from the vector format.
8605 (define_insn_and_split "reload_vsx_from_gprsf"
8606 [(set (match_operand:SF 0 "register_operand" "=wa")
8607 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
8608 UNSPEC_P8V_RELOAD_FROM_GPR))
8609 (clobber (match_operand:DI 2 "register_operand" "=r"))]
8610 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8611 "#"
8612 "&& reload_completed"
8613 [(const_int 0)]
8614 {
8615 rtx op0 = operands[0];
8616 rtx op1 = operands[1];
8617 rtx op2 = operands[2];
8618 /* Also use the destination register to hold the unconverted DImode value.
8619 This is conceptually a separate value from OP0, so we use gen_rtx_REG
8620 rather than simplify_gen_subreg. */
8621 rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
8622 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
8624 /* Move SF value to upper 32-bits for xscvspdpn. */
8625 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
8626 emit_move_insn (op0_di, op2);
8627 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
8628 DONE;
8629 }
8630 [(set_attr "length" "8")
8631 (set_attr "type" "two")])
8633 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
8634 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
8635 ;; and then doing a move of that.
8636 (define_insn "p8_mfvsrd_3_<mode>"
8637 [(set (match_operand:DF 0 "register_operand" "=r")
8638 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8639 UNSPEC_P8V_RELOAD_FROM_VSX))]
8640 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8641 "mfvsrd %0,%x1"
8642 [(set_attr "type" "mftgpr")])
8644 (define_insn_and_split "reload_gpr_from_vsx<mode>"
8645 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
8646 (unspec:FMOVE128_GPR
8647 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
8648 UNSPEC_P8V_RELOAD_FROM_VSX))
8649 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
8650 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8651 "#"
8652 "&& reload_completed"
8653 [(const_int 0)]
8654 {
8655 rtx dest = operands[0];
8656 rtx src = operands[1];
8657 rtx tmp = operands[2];
8658 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
8659 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
8661 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
8662 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
8663 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
8664 }
8665 [(set_attr "length" "12")
8666 (set_attr "type" "three")])
8668 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
8669 ;; type is stored internally as double precision, we have to convert it to the
8670 ;; vector format.
8672 (define_insn_and_split "reload_gpr_from_vsxsf"
8673 [(set (match_operand:SF 0 "register_operand" "=r")
8674 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
8675 UNSPEC_P8V_RELOAD_FROM_VSX))
8676 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
8677 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8678 "#"
8679 "&& reload_completed"
8680 [(const_int 0)]
8681 {
8682 rtx op0 = operands[0];
8683 rtx op1 = operands[1];
8684 rtx op2 = operands[2];
8685 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
8687 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
8688 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
8689 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
8690 DONE;
8691 }
8692 [(set_attr "length" "12")
8693 (set_attr "type" "three")])
8695 (define_insn "p8_mfvsrd_4_disf"
8696 [(set (match_operand:DI 0 "register_operand" "=r")
8697 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
8698 UNSPEC_P8V_RELOAD_FROM_VSX))]
8699 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
8700 "mfvsrd %0,%x1"
8701 [(set_attr "type" "mftgpr")])
8703 \f
8704 ;; Next come the multi-word integer load and store and the load and store
8705 ;; multiple insns.
8707 ;; List r->r after r->Y, otherwise reload will try to reload a
8708 ;; non-offsettable address by using r->r which won't make progress.
8709 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8710 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8711 (define_insn "*movdi_internal32"
8712 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
8713 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
8714 "! TARGET_POWERPC64
8715 && (gpc_reg_operand (operands[0], DImode)
8716 || gpc_reg_operand (operands[1], DImode))"
8717 "@
8718 #
8719 #
8720 #
8721 stfd%U0%X0 %1,%0
8722 lfd%U1%X1 %0,%1
8723 fmr %0,%1
8724 #"
8725 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
8727 (define_split
8728 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8729 (match_operand:DI 1 "const_int_operand" ""))]
8730 "! TARGET_POWERPC64 && reload_completed
8731 && gpr_or_gpr_p (operands[0], operands[1])
8732 && !direct_move_p (operands[0], operands[1])"
8733 [(set (match_dup 2) (match_dup 4))
8734 (set (match_dup 3) (match_dup 1))]
8735 "
8736 {
8737 HOST_WIDE_INT value = INTVAL (operands[1]);
8738 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8739 DImode);
8740 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8741 DImode);
8742 operands[4] = GEN_INT (value >> 32);
8743 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8744 }")
8746 (define_split
8747 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8748 (match_operand:DIFD 1 "input_operand" ""))]
8749 "reload_completed && !TARGET_POWERPC64
8750 && gpr_or_gpr_p (operands[0], operands[1])
8751 && !direct_move_p (operands[0], operands[1])"
8752 [(pc)]
8753 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8755 (define_insn "*movdi_internal64"
8756 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
8757 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
8758 "TARGET_POWERPC64
8759 && (gpc_reg_operand (operands[0], DImode)
8760 || gpc_reg_operand (operands[1], DImode))"
8761 "@
8762 std%U0%X0 %1,%0
8763 ld%U1%X1 %0,%1
8764 mr %0,%1
8765 li %0,%1
8766 lis %0,%v1
8767 #
8768 stfd%U0%X0 %1,%0
8769 lfd%U1%X1 %0,%1
8770 fmr %0,%1
8771 mf%1 %0
8772 mt%0 %1
8773 nop
8774 mftgpr %0,%1
8775 mffgpr %0,%1
8776 mfvsrd %0,%x1
8777 mtvsrd %x0,%1
8778 xxlxor %x0,%x0,%x0"
8779 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple")
8780 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
8782 ;; Generate all one-bits and clear left or right.
8783 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8784 (define_split
8785 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8786 (match_operand:DI 1 "mask64_operand" ""))]
8787 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8788 [(set (match_dup 0) (const_int -1))
8789 (set (match_dup 0)
8790 (and:DI (rotate:DI (match_dup 0)
8791 (const_int 0))
8792 (match_dup 1)))]
8793 "")
8795 ;; Split a load of a large constant into the appropriate five-instruction
8796 ;; sequence. Handle anything in a constant number of insns.
8797 ;; When non-easy constants can go in the TOC, this should use
8798 ;; easy_fp_constant predicate.
8799 (define_split
8800 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8801 (match_operand:DI 1 "const_int_operand" ""))]
8802 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8803 [(set (match_dup 0) (match_dup 2))
8804 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8805 "
8806 {
8807 if (rs6000_emit_set_const (operands[0], operands[1]))
8808 DONE;
8809 else
8810 FAIL;
8811 }")
8813 (define_split
8814 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8815 (match_operand:DI 1 "const_scalar_int_operand" ""))]
8816 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8817 [(set (match_dup 0) (match_dup 2))
8818 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8819 "
8820 {
8821 if (rs6000_emit_set_const (operands[0], operands[1]))
8822 DONE;
8823 else
8824 FAIL;
8825 }")
8826 \f
8827 ;; TImode/PTImode is similar, except that we usually want to compute the
8828 ;; address into a register and use lsi/stsi (the exception is during reload).
8830 (define_insn "*mov<mode>_string"
8831 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8832 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
8833 "! TARGET_POWERPC64
8834 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
8835 && (gpc_reg_operand (operands[0], <MODE>mode)
8836 || gpc_reg_operand (operands[1], <MODE>mode))"
8837 "*
8838 {
8839 switch (which_alternative)
8840 {
8841 default:
8842 gcc_unreachable ();
8843 case 0:
8844 if (TARGET_STRING)
8845 return \"stswi %1,%P0,16\";
8846 case 1:
8847 return \"#\";
8848 case 2:
8849 /* If the address is not used in the output, we can use lsi. Otherwise,
8850 fall through to generating four loads. */
8851 if (TARGET_STRING
8852 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8853 return \"lswi %0,%P1,16\";
8854 /* ... fall through ... */
8855 case 3:
8856 case 4:
8857 case 5:
8858 return \"#\";
8859 }
8860 }"
8861 [(set_attr "type" "store,store,load,load,*,*")
8862 (set_attr "update" "yes")
8863 (set_attr "indexed" "yes")
8864 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8865 (const_string "always")
8866 (const_string "conditional")))])
8868 (define_insn "*mov<mode>_ppc64"
8869 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
8870 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
8871 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
8872 && (gpc_reg_operand (operands[0], <MODE>mode)
8873 || gpc_reg_operand (operands[1], <MODE>mode)))"
8874 {
8875 return rs6000_output_move_128bit (operands);
8876 }
8877 [(set_attr "type" "store,store,load,load,*,*")
8878 (set_attr "length" "8")])
8880 (define_split
8881 [(set (match_operand:TI2 0 "int_reg_operand" "")
8882 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
8883 "TARGET_POWERPC64
8884 && (VECTOR_MEM_NONE_P (<MODE>mode)
8885 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
8886 [(set (match_dup 2) (match_dup 4))
8887 (set (match_dup 3) (match_dup 5))]
8888 "
8889 {
8890 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8891 <MODE>mode);
8892 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8893 <MODE>mode);
8894 if (CONST_WIDE_INT_P (operands[1]))
8895 {
8896 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
8897 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
8898 }
8899 else if (CONST_INT_P (operands[1]))
8900 {
8901 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8902 operands[5] = operands[1];
8903 }
8904 else
8905 FAIL;
8906 }")
8908 (define_split
8909 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
8910 (match_operand:TI2 1 "input_operand" ""))]
8911 "reload_completed
8912 && gpr_or_gpr_p (operands[0], operands[1])
8913 && !direct_move_p (operands[0], operands[1])
8914 && !quad_load_store_p (operands[0], operands[1])"
8915 [(pc)]
8916 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8917 \f
8918 (define_expand "load_multiple"
8919 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8920 (match_operand:SI 1 "" ""))
8921 (use (match_operand:SI 2 "" ""))])]
8922 "TARGET_STRING && !TARGET_POWERPC64"
8923 "
8924 {
8925 int regno;
8926 int count;
8927 rtx op1;
8928 int i;
8930 /* Support only loading a constant number of fixed-point registers from
8931 memory and only bother with this if more than two; the machine
8932 doesn't support more than eight. */
8933 if (GET_CODE (operands[2]) != CONST_INT
8934 || INTVAL (operands[2]) <= 2
8935 || INTVAL (operands[2]) > 8
8936 || GET_CODE (operands[1]) != MEM
8937 || GET_CODE (operands[0]) != REG
8938 || REGNO (operands[0]) >= 32)
8939 FAIL;
8941 count = INTVAL (operands[2]);
8942 regno = REGNO (operands[0]);
8944 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8945 op1 = replace_equiv_address (operands[1],
8946 force_reg (SImode, XEXP (operands[1], 0)));
8948 for (i = 0; i < count; i++)
8949 XVECEXP (operands[3], 0, i)
8950 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8951 adjust_address_nv (op1, SImode, i * 4));
8952 }")
8954 (define_insn "*ldmsi8"
8955 [(match_parallel 0 "load_multiple_operation"
8956 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8957 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8958 (set (match_operand:SI 3 "gpc_reg_operand" "")
8959 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8960 (set (match_operand:SI 4 "gpc_reg_operand" "")
8961 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8962 (set (match_operand:SI 5 "gpc_reg_operand" "")
8963 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8964 (set (match_operand:SI 6 "gpc_reg_operand" "")
8965 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8966 (set (match_operand:SI 7 "gpc_reg_operand" "")
8967 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8968 (set (match_operand:SI 8 "gpc_reg_operand" "")
8969 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8970 (set (match_operand:SI 9 "gpc_reg_operand" "")
8971 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8972 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8973 "*
8974 { return rs6000_output_load_multiple (operands); }"
8975 [(set_attr "type" "load")
8976 (set_attr "update" "yes")
8977 (set_attr "indexed" "yes")
8978 (set_attr "length" "32")])
8980 (define_insn "*ldmsi7"
8981 [(match_parallel 0 "load_multiple_operation"
8982 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8983 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8984 (set (match_operand:SI 3 "gpc_reg_operand" "")
8985 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8986 (set (match_operand:SI 4 "gpc_reg_operand" "")
8987 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8988 (set (match_operand:SI 5 "gpc_reg_operand" "")
8989 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8990 (set (match_operand:SI 6 "gpc_reg_operand" "")
8991 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8992 (set (match_operand:SI 7 "gpc_reg_operand" "")
8993 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8994 (set (match_operand:SI 8 "gpc_reg_operand" "")
8995 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8996 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8997 "*
8998 { return rs6000_output_load_multiple (operands); }"
8999 [(set_attr "type" "load")
9000 (set_attr "update" "yes")
9001 (set_attr "indexed" "yes")
9002 (set_attr "length" "32")])
9004 (define_insn "*ldmsi6"
9005 [(match_parallel 0 "load_multiple_operation"
9006 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9007 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9008 (set (match_operand:SI 3 "gpc_reg_operand" "")
9009 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9010 (set (match_operand:SI 4 "gpc_reg_operand" "")
9011 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9012 (set (match_operand:SI 5 "gpc_reg_operand" "")
9013 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9014 (set (match_operand:SI 6 "gpc_reg_operand" "")
9015 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9016 (set (match_operand:SI 7 "gpc_reg_operand" "")
9017 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9018 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9019 "*
9020 { return rs6000_output_load_multiple (operands); }"
9021 [(set_attr "type" "load")
9022 (set_attr "update" "yes")
9023 (set_attr "indexed" "yes")
9024 (set_attr "length" "32")])
9026 (define_insn "*ldmsi5"
9027 [(match_parallel 0 "load_multiple_operation"
9028 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9029 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9030 (set (match_operand:SI 3 "gpc_reg_operand" "")
9031 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9032 (set (match_operand:SI 4 "gpc_reg_operand" "")
9033 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9034 (set (match_operand:SI 5 "gpc_reg_operand" "")
9035 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9036 (set (match_operand:SI 6 "gpc_reg_operand" "")
9037 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9038 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9039 "*
9040 { return rs6000_output_load_multiple (operands); }"
9041 [(set_attr "type" "load")
9042 (set_attr "update" "yes")
9043 (set_attr "indexed" "yes")
9044 (set_attr "length" "32")])
9046 (define_insn "*ldmsi4"
9047 [(match_parallel 0 "load_multiple_operation"
9048 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9049 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9050 (set (match_operand:SI 3 "gpc_reg_operand" "")
9051 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9052 (set (match_operand:SI 4 "gpc_reg_operand" "")
9053 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9054 (set (match_operand:SI 5 "gpc_reg_operand" "")
9055 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9056 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9057 "*
9058 { return rs6000_output_load_multiple (operands); }"
9059 [(set_attr "type" "load")
9060 (set_attr "update" "yes")
9061 (set_attr "indexed" "yes")
9062 (set_attr "length" "32")])
9064 (define_insn "*ldmsi3"
9065 [(match_parallel 0 "load_multiple_operation"
9066 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9067 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9068 (set (match_operand:SI 3 "gpc_reg_operand" "")
9069 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9070 (set (match_operand:SI 4 "gpc_reg_operand" "")
9071 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9072 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9073 "*
9074 { return rs6000_output_load_multiple (operands); }"
9075 [(set_attr "type" "load")
9076 (set_attr "update" "yes")
9077 (set_attr "indexed" "yes")
9078 (set_attr "length" "32")])
9080 (define_expand "store_multiple"
9081 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9082 (match_operand:SI 1 "" ""))
9083 (clobber (scratch:SI))
9084 (use (match_operand:SI 2 "" ""))])]
9085 "TARGET_STRING && !TARGET_POWERPC64"
9086 "
9087 {
9088 int regno;
9089 int count;
9090 rtx to;
9091 rtx op0;
9092 int i;
9094 /* Support only storing a constant number of fixed-point registers to
9095 memory and only bother with this if more than two; the machine
9096 doesn't support more than eight. */
9097 if (GET_CODE (operands[2]) != CONST_INT
9098 || INTVAL (operands[2]) <= 2
9099 || INTVAL (operands[2]) > 8
9100 || GET_CODE (operands[0]) != MEM
9101 || GET_CODE (operands[1]) != REG
9102 || REGNO (operands[1]) >= 32)
9103 FAIL;
9105 count = INTVAL (operands[2]);
9106 regno = REGNO (operands[1]);
9108 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9109 to = force_reg (SImode, XEXP (operands[0], 0));
9110 op0 = replace_equiv_address (operands[0], to);
9112 XVECEXP (operands[3], 0, 0)
9113 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9114 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9115 gen_rtx_SCRATCH (SImode));
9117 for (i = 1; i < count; i++)
9118 XVECEXP (operands[3], 0, i + 1)
9119 = gen_rtx_SET (VOIDmode,
9120 adjust_address_nv (op0, SImode, i * 4),
9121 gen_rtx_REG (SImode, regno + i));
9122 }")
9124 (define_insn "*stmsi8"
9125 [(match_parallel 0 "store_multiple_operation"
9126 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9127 (match_operand:SI 2 "gpc_reg_operand" "r"))
9128 (clobber (match_scratch:SI 3 "=X"))
9129 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9130 (match_operand:SI 4 "gpc_reg_operand" "r"))
9131 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9132 (match_operand:SI 5 "gpc_reg_operand" "r"))
9133 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9134 (match_operand:SI 6 "gpc_reg_operand" "r"))
9135 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9136 (match_operand:SI 7 "gpc_reg_operand" "r"))
9137 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9138 (match_operand:SI 8 "gpc_reg_operand" "r"))
9139 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9140 (match_operand:SI 9 "gpc_reg_operand" "r"))
9141 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9142 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9143 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9144 "stswi %2,%1,%O0"
9145 [(set_attr "type" "store")
9146 (set_attr "update" "yes")
9147 (set_attr "indexed" "yes")
9148 (set_attr "cell_micro" "always")])
9150 (define_insn "*stmsi7"
9151 [(match_parallel 0 "store_multiple_operation"
9152 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9153 (match_operand:SI 2 "gpc_reg_operand" "r"))
9154 (clobber (match_scratch:SI 3 "=X"))
9155 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9156 (match_operand:SI 4 "gpc_reg_operand" "r"))
9157 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9158 (match_operand:SI 5 "gpc_reg_operand" "r"))
9159 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9160 (match_operand:SI 6 "gpc_reg_operand" "r"))
9161 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9162 (match_operand:SI 7 "gpc_reg_operand" "r"))
9163 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9164 (match_operand:SI 8 "gpc_reg_operand" "r"))
9165 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9166 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9167 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9168 "stswi %2,%1,%O0"
9169 [(set_attr "type" "store")
9170 (set_attr "update" "yes")
9171 (set_attr "indexed" "yes")
9172 (set_attr "cell_micro" "always")])
9174 (define_insn "*stmsi6"
9175 [(match_parallel 0 "store_multiple_operation"
9176 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9177 (match_operand:SI 2 "gpc_reg_operand" "r"))
9178 (clobber (match_scratch:SI 3 "=X"))
9179 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9180 (match_operand:SI 4 "gpc_reg_operand" "r"))
9181 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9182 (match_operand:SI 5 "gpc_reg_operand" "r"))
9183 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9184 (match_operand:SI 6 "gpc_reg_operand" "r"))
9185 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9186 (match_operand:SI 7 "gpc_reg_operand" "r"))
9187 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9188 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9189 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9190 "stswi %2,%1,%O0"
9191 [(set_attr "type" "store")
9192 (set_attr "update" "yes")
9193 (set_attr "indexed" "yes")
9194 (set_attr "cell_micro" "always")])
9196 (define_insn "*stmsi5"
9197 [(match_parallel 0 "store_multiple_operation"
9198 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9199 (match_operand:SI 2 "gpc_reg_operand" "r"))
9200 (clobber (match_scratch:SI 3 "=X"))
9201 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9202 (match_operand:SI 4 "gpc_reg_operand" "r"))
9203 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9204 (match_operand:SI 5 "gpc_reg_operand" "r"))
9205 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9206 (match_operand:SI 6 "gpc_reg_operand" "r"))
9207 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9208 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9209 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9210 "stswi %2,%1,%O0"
9211 [(set_attr "type" "store")
9212 (set_attr "update" "yes")
9213 (set_attr "indexed" "yes")
9214 (set_attr "cell_micro" "always")])
9216 (define_insn "*stmsi4"
9217 [(match_parallel 0 "store_multiple_operation"
9218 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9219 (match_operand:SI 2 "gpc_reg_operand" "r"))
9220 (clobber (match_scratch:SI 3 "=X"))
9221 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9222 (match_operand:SI 4 "gpc_reg_operand" "r"))
9223 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9224 (match_operand:SI 5 "gpc_reg_operand" "r"))
9225 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9226 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9227 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9228 "stswi %2,%1,%O0"
9229 [(set_attr "type" "store")
9230 (set_attr "update" "yes")
9231 (set_attr "indexed" "yes")
9232 (set_attr "cell_micro" "always")])
9234 (define_insn "*stmsi3"
9235 [(match_parallel 0 "store_multiple_operation"
9236 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9237 (match_operand:SI 2 "gpc_reg_operand" "r"))
9238 (clobber (match_scratch:SI 3 "=X"))
9239 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9240 (match_operand:SI 4 "gpc_reg_operand" "r"))
9241 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9242 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9243 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9244 "stswi %2,%1,%O0"
9245 [(set_attr "type" "store")
9246 (set_attr "update" "yes")
9247 (set_attr "indexed" "yes")
9248 (set_attr "cell_micro" "always")])
9249 \f
9250 (define_expand "setmemsi"
9251 [(parallel [(set (match_operand:BLK 0 "" "")
9252 (match_operand 2 "const_int_operand" ""))
9253 (use (match_operand:SI 1 "" ""))
9254 (use (match_operand:SI 3 "" ""))])]
9255 ""
9256 "
9257 {
9258 /* If value to set is not zero, use the library routine. */
9259 if (operands[2] != const0_rtx)
9260 FAIL;
9262 if (expand_block_clear (operands))
9263 DONE;
9264 else
9265 FAIL;
9266 }")
9268 ;; String/block move insn.
9269 ;; Argument 0 is the destination
9270 ;; Argument 1 is the source
9271 ;; Argument 2 is the length
9272 ;; Argument 3 is the alignment
9274 (define_expand "movmemsi"
9275 [(parallel [(set (match_operand:BLK 0 "" "")
9276 (match_operand:BLK 1 "" ""))
9277 (use (match_operand:SI 2 "" ""))
9278 (use (match_operand:SI 3 "" ""))])]
9279 ""
9280 "
9281 {
9282 if (expand_block_move (operands))
9283 DONE;
9284 else
9285 FAIL;
9286 }")
9288 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9289 ;; register allocator doesn't have a clue about allocating 8 word registers.
9290 ;; rD/rS = r5 is preferred, efficient form.
9291 (define_expand "movmemsi_8reg"
9292 [(parallel [(set (match_operand 0 "" "")
9293 (match_operand 1 "" ""))
9294 (use (match_operand 2 "" ""))
9295 (use (match_operand 3 "" ""))
9296 (clobber (reg:SI 5))
9297 (clobber (reg:SI 6))
9298 (clobber (reg:SI 7))
9299 (clobber (reg:SI 8))
9300 (clobber (reg:SI 9))
9301 (clobber (reg:SI 10))
9302 (clobber (reg:SI 11))
9303 (clobber (reg:SI 12))
9304 (clobber (match_scratch:SI 4 ""))])]
9305 "TARGET_STRING"
9306 "")
9308 (define_insn ""
9309 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9310 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9311 (use (match_operand:SI 2 "immediate_operand" "i"))
9312 (use (match_operand:SI 3 "immediate_operand" "i"))
9313 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9314 (clobber (reg:SI 6))
9315 (clobber (reg:SI 7))
9316 (clobber (reg:SI 8))
9317 (clobber (reg:SI 9))
9318 (clobber (reg:SI 10))
9319 (clobber (reg:SI 11))
9320 (clobber (reg:SI 12))
9321 (clobber (match_scratch:SI 5 "=X"))]
9322 "TARGET_STRING
9323 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9324 || INTVAL (operands[2]) == 0)
9325 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9326 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9327 && REGNO (operands[4]) == 5"
9328 "lswi %4,%1,%2\;stswi %4,%0,%2"
9329 [(set_attr "type" "store")
9330 (set_attr "update" "yes")
9331 (set_attr "indexed" "yes")
9332 (set_attr "cell_micro" "always")
9333 (set_attr "length" "8")])
9335 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9336 ;; register allocator doesn't have a clue about allocating 6 word registers.
9337 ;; rD/rS = r5 is preferred, efficient form.
9338 (define_expand "movmemsi_6reg"
9339 [(parallel [(set (match_operand 0 "" "")
9340 (match_operand 1 "" ""))
9341 (use (match_operand 2 "" ""))
9342 (use (match_operand 3 "" ""))
9343 (clobber (reg:SI 5))
9344 (clobber (reg:SI 6))
9345 (clobber (reg:SI 7))
9346 (clobber (reg:SI 8))
9347 (clobber (reg:SI 9))
9348 (clobber (reg:SI 10))
9349 (clobber (match_scratch:SI 4 ""))])]
9350 "TARGET_STRING"
9351 "")
9353 (define_insn ""
9354 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9355 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9356 (use (match_operand:SI 2 "immediate_operand" "i"))
9357 (use (match_operand:SI 3 "immediate_operand" "i"))
9358 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9359 (clobber (reg:SI 6))
9360 (clobber (reg:SI 7))
9361 (clobber (reg:SI 8))
9362 (clobber (reg:SI 9))
9363 (clobber (reg:SI 10))
9364 (clobber (match_scratch:SI 5 "=X"))]
9365 "TARGET_STRING
9366 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9367 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9368 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9369 && REGNO (operands[4]) == 5"
9370 "lswi %4,%1,%2\;stswi %4,%0,%2"
9371 [(set_attr "type" "store")
9372 (set_attr "update" "yes")
9373 (set_attr "indexed" "yes")
9374 (set_attr "cell_micro" "always")
9375 (set_attr "length" "8")])
9377 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9378 ;; problems with TImode.
9379 ;; rD/rS = r5 is preferred, efficient form.
9380 (define_expand "movmemsi_4reg"
9381 [(parallel [(set (match_operand 0 "" "")
9382 (match_operand 1 "" ""))
9383 (use (match_operand 2 "" ""))
9384 (use (match_operand 3 "" ""))
9385 (clobber (reg:SI 5))
9386 (clobber (reg:SI 6))
9387 (clobber (reg:SI 7))
9388 (clobber (reg:SI 8))
9389 (clobber (match_scratch:SI 4 ""))])]
9390 "TARGET_STRING"
9391 "")
9393 (define_insn ""
9394 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9395 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9396 (use (match_operand:SI 2 "immediate_operand" "i"))
9397 (use (match_operand:SI 3 "immediate_operand" "i"))
9398 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9399 (clobber (reg:SI 6))
9400 (clobber (reg:SI 7))
9401 (clobber (reg:SI 8))
9402 (clobber (match_scratch:SI 5 "=X"))]
9403 "TARGET_STRING
9404 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9405 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9406 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9407 && REGNO (operands[4]) == 5"
9408 "lswi %4,%1,%2\;stswi %4,%0,%2"
9409 [(set_attr "type" "store")
9410 (set_attr "update" "yes")
9411 (set_attr "indexed" "yes")
9412 (set_attr "cell_micro" "always")
9413 (set_attr "length" "8")])
9415 ;; Move up to 8 bytes at a time.
9416 (define_expand "movmemsi_2reg"
9417 [(parallel [(set (match_operand 0 "" "")
9418 (match_operand 1 "" ""))
9419 (use (match_operand 2 "" ""))
9420 (use (match_operand 3 "" ""))
9421 (clobber (match_scratch:DI 4 ""))
9422 (clobber (match_scratch:SI 5 ""))])]
9423 "TARGET_STRING && ! TARGET_POWERPC64"
9424 "")
9426 (define_insn ""
9427 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9428 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9429 (use (match_operand:SI 2 "immediate_operand" "i"))
9430 (use (match_operand:SI 3 "immediate_operand" "i"))
9431 (clobber (match_scratch:DI 4 "=&r"))
9432 (clobber (match_scratch:SI 5 "=X"))]
9433 "TARGET_STRING && ! TARGET_POWERPC64
9434 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9435 "lswi %4,%1,%2\;stswi %4,%0,%2"
9436 [(set_attr "type" "store")
9437 (set_attr "update" "yes")
9438 (set_attr "indexed" "yes")
9439 (set_attr "cell_micro" "always")
9440 (set_attr "length" "8")])
9442 ;; Move up to 4 bytes at a time.
9443 (define_expand "movmemsi_1reg"
9444 [(parallel [(set (match_operand 0 "" "")
9445 (match_operand 1 "" ""))
9446 (use (match_operand 2 "" ""))
9447 (use (match_operand 3 "" ""))
9448 (clobber (match_scratch:SI 4 ""))
9449 (clobber (match_scratch:SI 5 ""))])]
9450 "TARGET_STRING"
9451 "")
9453 (define_insn ""
9454 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9455 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9456 (use (match_operand:SI 2 "immediate_operand" "i"))
9457 (use (match_operand:SI 3 "immediate_operand" "i"))
9458 (clobber (match_scratch:SI 4 "=&r"))
9459 (clobber (match_scratch:SI 5 "=X"))]
9460 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9461 "lswi %4,%1,%2\;stswi %4,%0,%2"
9462 [(set_attr "type" "store")
9463 (set_attr "update" "yes")
9464 (set_attr "indexed" "yes")
9465 (set_attr "cell_micro" "always")
9466 (set_attr "length" "8")])
9467 \f
9468 ;; Define insns that do load or store with update. Some of these we can
9469 ;; get by using pre-decrement or pre-increment, but the hardware can also
9470 ;; do cases where the increment is not the size of the object.
9471 ;;
9472 ;; In all these cases, we use operands 0 and 1 for the register being
9473 ;; incremented because those are the operands that local-alloc will
9474 ;; tie and these are the pair most likely to be tieable (and the ones
9475 ;; that will benefit the most).
9477 (define_insn "*movdi_update1"
9478 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9479 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9480 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9481 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9482 (plus:DI (match_dup 1) (match_dup 2)))]
9483 "TARGET_POWERPC64 && TARGET_UPDATE
9484 && (!avoiding_indexed_address_p (DImode)
9485 || !gpc_reg_operand (operands[2], DImode))"
9486 "@
9487 ldux %3,%0,%2
9488 ldu %3,%2(%0)"
9489 [(set_attr "type" "load")
9490 (set_attr "update" "yes")
9491 (set_attr "indexed" "yes,no")])
9493 (define_insn "movdi_<mode>_update"
9494 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9495 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9496 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9497 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9498 (plus:P (match_dup 1) (match_dup 2)))]
9499 "TARGET_POWERPC64 && TARGET_UPDATE
9500 && (!avoiding_indexed_address_p (Pmode)
9501 || !gpc_reg_operand (operands[2], Pmode)
9502 || (REG_P (operands[0])
9503 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9504 "@
9505 stdux %3,%0,%2
9506 stdu %3,%2(%0)"
9507 [(set_attr "type" "store")
9508 (set_attr "update" "yes")
9509 (set_attr "indexed" "yes,no")])
9511 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9512 ;; needed for stack allocation, even if the user passes -mno-update.
9513 (define_insn "movdi_<mode>_update_stack"
9514 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9515 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9516 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9517 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9518 (plus:P (match_dup 1) (match_dup 2)))]
9519 "TARGET_POWERPC64"
9520 "@
9521 stdux %3,%0,%2
9522 stdu %3,%2(%0)"
9523 [(set_attr "type" "store")
9524 (set_attr "update" "yes")
9525 (set_attr "indexed" "yes,no")])
9527 (define_insn "*movsi_update1"
9528 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9529 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9530 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9531 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9532 (plus:SI (match_dup 1) (match_dup 2)))]
9533 "TARGET_UPDATE
9534 && (!avoiding_indexed_address_p (SImode)
9535 || !gpc_reg_operand (operands[2], SImode))"
9536 "@
9537 lwzux %3,%0,%2
9538 lwzu %3,%2(%0)"
9539 [(set_attr "type" "load")
9540 (set_attr "update" "yes")
9541 (set_attr "indexed" "yes,no")])
9543 (define_insn "*movsi_update2"
9544 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9545 (sign_extend:DI
9546 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9547 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9548 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9549 (plus:DI (match_dup 1) (match_dup 2)))]
9550 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9551 && !avoiding_indexed_address_p (DImode)"
9552 "lwaux %3,%0,%2"
9553 [(set_attr "type" "load")
9554 (set_attr "sign_extend" "yes")
9555 (set_attr "update" "yes")
9556 (set_attr "indexed" "yes")])
9558 (define_insn "movsi_update"
9559 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9560 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9561 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9562 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9563 (plus:SI (match_dup 1) (match_dup 2)))]
9564 "TARGET_UPDATE
9565 && (!avoiding_indexed_address_p (SImode)
9566 || !gpc_reg_operand (operands[2], SImode)
9567 || (REG_P (operands[0])
9568 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9569 "@
9570 stwux %3,%0,%2
9571 stwu %3,%2(%0)"
9572 [(set_attr "type" "store")
9573 (set_attr "update" "yes")
9574 (set_attr "indexed" "yes,no")])
9576 ;; This is an unconditional pattern; needed for stack allocation, even
9577 ;; if the user passes -mno-update.
9578 (define_insn "movsi_update_stack"
9579 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9580 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9581 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9582 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9583 (plus:SI (match_dup 1) (match_dup 2)))]
9584 ""
9585 "@
9586 stwux %3,%0,%2
9587 stwu %3,%2(%0)"
9588 [(set_attr "type" "store")
9589 (set_attr "update" "yes")
9590 (set_attr "indexed" "yes,no")])
9592 (define_insn "*movhi_update1"
9593 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9594 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9595 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9596 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9597 (plus:SI (match_dup 1) (match_dup 2)))]
9598 "TARGET_UPDATE
9599 && (!avoiding_indexed_address_p (SImode)
9600 || !gpc_reg_operand (operands[2], SImode))"
9601 "@
9602 lhzux %3,%0,%2
9603 lhzu %3,%2(%0)"
9604 [(set_attr "type" "load")
9605 (set_attr "update" "yes")
9606 (set_attr "indexed" "yes,no")])
9608 (define_insn "*movhi_update2"
9609 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9610 (zero_extend:SI
9611 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9612 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9613 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9614 (plus:SI (match_dup 1) (match_dup 2)))]
9615 "TARGET_UPDATE
9616 && (!avoiding_indexed_address_p (SImode)
9617 || !gpc_reg_operand (operands[2], SImode))"
9618 "@
9619 lhzux %3,%0,%2
9620 lhzu %3,%2(%0)"
9621 [(set_attr "type" "load")
9622 (set_attr "update" "yes")
9623 (set_attr "indexed" "yes,no")])
9625 (define_insn "*movhi_update3"
9626 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9627 (sign_extend:SI
9628 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9629 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9630 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9631 (plus:SI (match_dup 1) (match_dup 2)))]
9632 "TARGET_UPDATE && rs6000_gen_cell_microcode
9633 && (!avoiding_indexed_address_p (SImode)
9634 || !gpc_reg_operand (operands[2], SImode))"
9635 "@
9636 lhaux %3,%0,%2
9637 lhau %3,%2(%0)"
9638 [(set_attr "type" "load")
9639 (set_attr "sign_extend" "yes")
9640 (set_attr "update" "yes")
9641 (set_attr "indexed" "yes,no")])
9643 (define_insn "*movhi_update4"
9644 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9645 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9646 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9647 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9648 (plus:SI (match_dup 1) (match_dup 2)))]
9649 "TARGET_UPDATE
9650 && (!avoiding_indexed_address_p (SImode)
9651 || !gpc_reg_operand (operands[2], SImode))"
9652 "@
9653 sthux %3,%0,%2
9654 sthu %3,%2(%0)"
9655 [(set_attr "type" "store")
9656 (set_attr "update" "yes")
9657 (set_attr "indexed" "yes,no")])
9659 (define_insn "*movqi_update1"
9660 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9661 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9662 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9663 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9664 (plus:SI (match_dup 1) (match_dup 2)))]
9665 "TARGET_UPDATE
9666 && (!avoiding_indexed_address_p (SImode)
9667 || !gpc_reg_operand (operands[2], SImode))"
9668 "@
9669 lbzux %3,%0,%2
9670 lbzu %3,%2(%0)"
9671 [(set_attr "type" "load")
9672 (set_attr "update" "yes")
9673 (set_attr "indexed" "yes,no")])
9675 (define_insn "*movqi_update2"
9676 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9677 (zero_extend:SI
9678 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9679 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9680 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9681 (plus:SI (match_dup 1) (match_dup 2)))]
9682 "TARGET_UPDATE
9683 && (!avoiding_indexed_address_p (SImode)
9684 || !gpc_reg_operand (operands[2], SImode))"
9685 "@
9686 lbzux %3,%0,%2
9687 lbzu %3,%2(%0)"
9688 [(set_attr "type" "load")
9689 (set_attr "update" "yes")
9690 (set_attr "indexed" "yes,no")])
9692 (define_insn "*movqi_update3"
9693 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9694 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9695 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9696 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9697 (plus:SI (match_dup 1) (match_dup 2)))]
9698 "TARGET_UPDATE
9699 && (!avoiding_indexed_address_p (SImode)
9700 || !gpc_reg_operand (operands[2], SImode))"
9701 "@
9702 stbux %3,%0,%2
9703 stbu %3,%2(%0)"
9704 [(set_attr "type" "store")
9705 (set_attr "update" "yes")
9706 (set_attr "indexed" "yes,no")])
9708 (define_insn "*movsf_update1"
9709 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9710 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9711 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9712 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9713 (plus:SI (match_dup 1) (match_dup 2)))]
9714 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9715 && (!avoiding_indexed_address_p (SImode)
9716 || !gpc_reg_operand (operands[2], SImode))"
9717 "@
9718 lfsux %3,%0,%2
9719 lfsu %3,%2(%0)"
9720 [(set_attr "type" "fpload")
9721 (set_attr "update" "yes")
9722 (set_attr "indexed" "yes,no")])
9724 (define_insn "*movsf_update2"
9725 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9726 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9727 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9728 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9729 (plus:SI (match_dup 1) (match_dup 2)))]
9730 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9731 && (!avoiding_indexed_address_p (SImode)
9732 || !gpc_reg_operand (operands[2], SImode))"
9733 "@
9734 stfsux %3,%0,%2
9735 stfsu %3,%2(%0)"
9736 [(set_attr "type" "fpstore")
9737 (set_attr "update" "yes")
9738 (set_attr "indexed" "yes,no")])
9740 (define_insn "*movsf_update3"
9741 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9742 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9743 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9744 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9745 (plus:SI (match_dup 1) (match_dup 2)))]
9746 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9747 && (!avoiding_indexed_address_p (SImode)
9748 || !gpc_reg_operand (operands[2], SImode))"
9749 "@
9750 lwzux %3,%0,%2
9751 lwzu %3,%2(%0)"
9752 [(set_attr "type" "load")
9753 (set_attr "update" "yes")
9754 (set_attr "indexed" "yes,no")])
9756 (define_insn "*movsf_update4"
9757 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9758 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9759 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9760 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9761 (plus:SI (match_dup 1) (match_dup 2)))]
9762 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9763 && (!avoiding_indexed_address_p (SImode)
9764 || !gpc_reg_operand (operands[2], SImode))"
9765 "@
9766 stwux %3,%0,%2
9767 stwu %3,%2(%0)"
9768 [(set_attr "type" "store")
9769 (set_attr "update" "yes")
9770 (set_attr "indexed" "yes,no")])
9772 (define_insn "*movdf_update1"
9773 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9774 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9775 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9776 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9777 (plus:SI (match_dup 1) (match_dup 2)))]
9778 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9779 && (!avoiding_indexed_address_p (SImode)
9780 || !gpc_reg_operand (operands[2], SImode))"
9781 "@
9782 lfdux %3,%0,%2
9783 lfdu %3,%2(%0)"
9784 [(set_attr "type" "fpload")
9785 (set_attr "update" "yes")
9786 (set_attr "indexed" "yes,no")])
9788 (define_insn "*movdf_update2"
9789 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9790 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9791 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9792 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9793 (plus:SI (match_dup 1) (match_dup 2)))]
9794 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9795 && (!avoiding_indexed_address_p (SImode)
9796 || !gpc_reg_operand (operands[2], SImode))"
9797 "@
9798 stfdux %3,%0,%2
9799 stfdu %3,%2(%0)"
9800 [(set_attr "type" "fpstore")
9801 (set_attr "update" "yes")
9802 (set_attr "indexed" "yes,no")])
9805 ;; After inserting conditional returns we can sometimes have
9806 ;; unnecessary register moves. Unfortunately we cannot have a
9807 ;; modeless peephole here, because some single SImode sets have early
9808 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9809 ;; sequences, using get_attr_length here will smash the operands
9810 ;; array. Neither is there an early_cobbler_p predicate.
9811 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9812 (define_peephole2
9813 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9814 (match_operand:DF 1 "any_operand" ""))
9815 (set (match_operand:DF 2 "gpc_reg_operand" "")
9816 (match_dup 0))]
9817 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9818 && peep2_reg_dead_p (2, operands[0])"
9819 [(set (match_dup 2) (match_dup 1))])
9821 (define_peephole2
9822 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9823 (match_operand:SF 1 "any_operand" ""))
9824 (set (match_operand:SF 2 "gpc_reg_operand" "")
9825 (match_dup 0))]
9826 "peep2_reg_dead_p (2, operands[0])"
9827 [(set (match_dup 2) (match_dup 1))])
9829 \f
9830 ;; TLS support.
9832 ;; Mode attributes for different ABIs.
9833 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9834 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9835 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9836 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9838 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9839 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9840 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9841 (match_operand 4 "" "g")))
9842 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9843 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9844 UNSPEC_TLSGD)
9845 (clobber (reg:SI LR_REGNO))]
9846 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9847 {
9848 if (TARGET_CMODEL != CMODEL_SMALL)
9849 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9850 "bl %z3\;nop";
9851 else
9852 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9853 }
9854 "&& TARGET_TLS_MARKERS"
9855 [(set (match_dup 0)
9856 (unspec:TLSmode [(match_dup 1)
9857 (match_dup 2)]
9858 UNSPEC_TLSGD))
9859 (parallel [(set (match_dup 0)
9860 (call (mem:TLSmode (match_dup 3))
9861 (match_dup 4)))
9862 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9863 (clobber (reg:SI LR_REGNO))])]
9864 ""
9865 [(set_attr "type" "two")
9866 (set (attr "length")
9867 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9868 (const_int 16)
9869 (const_int 12)))])
9871 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9872 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9873 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9874 (match_operand 4 "" "g")))
9875 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9876 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9877 UNSPEC_TLSGD)
9878 (clobber (reg:SI LR_REGNO))]
9879 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9880 {
9881 if (flag_pic)
9882 {
9883 if (TARGET_SECURE_PLT && flag_pic == 2)
9884 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9885 else
9886 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9887 }
9888 else
9889 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9890 }
9891 "&& TARGET_TLS_MARKERS"
9892 [(set (match_dup 0)
9893 (unspec:TLSmode [(match_dup 1)
9894 (match_dup 2)]
9895 UNSPEC_TLSGD))
9896 (parallel [(set (match_dup 0)
9897 (call (mem:TLSmode (match_dup 3))
9898 (match_dup 4)))
9899 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9900 (clobber (reg:SI LR_REGNO))])]
9901 ""
9902 [(set_attr "type" "two")
9903 (set_attr "length" "8")])
9905 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9906 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9907 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9908 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9909 UNSPEC_TLSGD))]
9910 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9911 "addi %0,%1,%2@got@tlsgd"
9912 "&& TARGET_CMODEL != CMODEL_SMALL"
9913 [(set (match_dup 3)
9914 (high:TLSmode
9915 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9916 (set (match_dup 0)
9917 (lo_sum:TLSmode (match_dup 3)
9918 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
9919 "
9920 {
9921 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9922 }"
9923 [(set (attr "length")
9924 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9925 (const_int 8)
9926 (const_int 4)))])
9928 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9929 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9930 (high:TLSmode
9931 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9932 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9933 UNSPEC_TLSGD)))]
9934 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9935 "addis %0,%1,%2@got@tlsgd@ha"
9936 [(set_attr "length" "4")])
9938 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9939 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9940 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9941 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
9942 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9943 UNSPEC_TLSGD)))]
9944 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9945 "addi %0,%1,%2@got@tlsgd@l"
9946 [(set_attr "length" "4")])
9948 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9949 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9950 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9951 (match_operand 2 "" "g")))
9952 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9953 UNSPEC_TLSGD)
9954 (clobber (reg:SI LR_REGNO))]
9955 "HAVE_AS_TLS && TARGET_TLS_MARKERS
9956 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9957 "bl %z1(%3@tlsgd)\;nop"
9958 [(set_attr "type" "branch")
9959 (set_attr "length" "8")])
9961 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9962 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9963 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9964 (match_operand 2 "" "g")))
9965 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9966 UNSPEC_TLSGD)
9967 (clobber (reg:SI LR_REGNO))]
9968 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9969 {
9970 if (flag_pic)
9971 {
9972 if (TARGET_SECURE_PLT && flag_pic == 2)
9973 return "bl %z1+32768(%3@tlsgd)@plt";
9974 return "bl %z1(%3@tlsgd)@plt";
9975 }
9976 return "bl %z1(%3@tlsgd)";
9977 }
9978 [(set_attr "type" "branch")
9979 (set_attr "length" "4")])
9981 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
9982 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9983 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9984 (match_operand 3 "" "g")))
9985 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9986 UNSPEC_TLSLD)
9987 (clobber (reg:SI LR_REGNO))]
9988 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9989 {
9990 if (TARGET_CMODEL != CMODEL_SMALL)
9991 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
9992 "bl %z2\;nop";
9993 else
9994 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
9995 }
9996 "&& TARGET_TLS_MARKERS"
9997 [(set (match_dup 0)
9998 (unspec:TLSmode [(match_dup 1)]
9999 UNSPEC_TLSLD))
10000 (parallel [(set (match_dup 0)
10001 (call (mem:TLSmode (match_dup 2))
10002 (match_dup 3)))
10003 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10004 (clobber (reg:SI LR_REGNO))])]
10005 ""
10006 [(set_attr "type" "two")
10007 (set (attr "length")
10008 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10009 (const_int 16)
10010 (const_int 12)))])
10012 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10013 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10014 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10015 (match_operand 3 "" "g")))
10016 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10017 UNSPEC_TLSLD)
10018 (clobber (reg:SI LR_REGNO))]
10019 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10020 {
10021 if (flag_pic)
10022 {
10023 if (TARGET_SECURE_PLT && flag_pic == 2)
10024 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10025 else
10026 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10027 }
10028 else
10029 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10030 }
10031 "&& TARGET_TLS_MARKERS"
10032 [(set (match_dup 0)
10033 (unspec:TLSmode [(match_dup 1)]
10034 UNSPEC_TLSLD))
10035 (parallel [(set (match_dup 0)
10036 (call (mem:TLSmode (match_dup 2))
10037 (match_dup 3)))
10038 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10039 (clobber (reg:SI LR_REGNO))])]
10040 ""
10041 [(set_attr "length" "8")])
10043 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10044 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10045 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10046 UNSPEC_TLSLD))]
10047 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10048 "addi %0,%1,%&@got@tlsld"
10049 "&& TARGET_CMODEL != CMODEL_SMALL"
10050 [(set (match_dup 2)
10051 (high:TLSmode
10052 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10053 (set (match_dup 0)
10054 (lo_sum:TLSmode (match_dup 2)
10055 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
10056 "
10057 {
10058 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10059 }"
10060 [(set (attr "length")
10061 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10062 (const_int 8)
10063 (const_int 4)))])
10065 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10066 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10067 (high:TLSmode
10068 (unspec:TLSmode [(const_int 0)
10069 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10070 UNSPEC_TLSLD)))]
10071 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10072 "addis %0,%1,%&@got@tlsld@ha"
10073 [(set_attr "length" "4")])
10075 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10076 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10077 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10078 (unspec:TLSmode [(const_int 0)
10079 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
10080 UNSPEC_TLSLD)))]
10081 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10082 "addi %0,%1,%&@got@tlsld@l"
10083 [(set_attr "length" "4")])
10085 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10086 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10087 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10088 (match_operand 2 "" "g")))
10089 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10090 (clobber (reg:SI LR_REGNO))]
10091 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10092 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10093 "bl %z1(%&@tlsld)\;nop"
10094 [(set_attr "type" "branch")
10095 (set_attr "length" "8")])
10097 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10098 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10099 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10100 (match_operand 2 "" "g")))
10101 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10102 (clobber (reg:SI LR_REGNO))]
10103 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10104 {
10105 if (flag_pic)
10106 {
10107 if (TARGET_SECURE_PLT && flag_pic == 2)
10108 return "bl %z1+32768(%&@tlsld)@plt";
10109 return "bl %z1(%&@tlsld)@plt";
10110 }
10111 return "bl %z1(%&@tlsld)";
10112 }
10113 [(set_attr "type" "branch")
10114 (set_attr "length" "4")])
10116 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10117 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10118 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10119 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10120 UNSPEC_TLSDTPREL))]
10121 "HAVE_AS_TLS"
10122 "addi %0,%1,%2@dtprel")
10124 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10125 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10126 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10127 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10128 UNSPEC_TLSDTPRELHA))]
10129 "HAVE_AS_TLS"
10130 "addis %0,%1,%2@dtprel@ha")
10132 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10133 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10134 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10135 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10136 UNSPEC_TLSDTPRELLO))]
10137 "HAVE_AS_TLS"
10138 "addi %0,%1,%2@dtprel@l")
10140 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10141 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10142 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10143 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10144 UNSPEC_TLSGOTDTPREL))]
10145 "HAVE_AS_TLS"
10146 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10147 "&& TARGET_CMODEL != CMODEL_SMALL"
10148 [(set (match_dup 3)
10149 (high:TLSmode
10150 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10151 (set (match_dup 0)
10152 (lo_sum:TLSmode (match_dup 3)
10153 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10154 "
10155 {
10156 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10157 }"
10158 [(set (attr "length")
10159 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10160 (const_int 8)
10161 (const_int 4)))])
10163 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10164 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10165 (high:TLSmode
10166 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10167 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10168 UNSPEC_TLSGOTDTPREL)))]
10169 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10170 "addis %0,%1,%2@got@dtprel@ha"
10171 [(set_attr "length" "4")])
10173 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10174 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10175 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10176 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10177 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10178 UNSPEC_TLSGOTDTPREL)))]
10179 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10180 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10181 [(set_attr "length" "4")])
10183 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10184 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10185 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10186 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10187 UNSPEC_TLSTPREL))]
10188 "HAVE_AS_TLS"
10189 "addi %0,%1,%2@tprel")
10191 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10192 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10193 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10194 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10195 UNSPEC_TLSTPRELHA))]
10196 "HAVE_AS_TLS"
10197 "addis %0,%1,%2@tprel@ha")
10199 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10200 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10201 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10202 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10203 UNSPEC_TLSTPRELLO))]
10204 "HAVE_AS_TLS"
10205 "addi %0,%1,%2@tprel@l")
10207 ;; "b" output constraint here and on tls_tls input to support linker tls
10208 ;; optimization. The linker may edit the instructions emitted by a
10209 ;; tls_got_tprel/tls_tls pair to addis,addi.
10210 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10211 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10212 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10213 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10214 UNSPEC_TLSGOTTPREL))]
10215 "HAVE_AS_TLS"
10216 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10217 "&& TARGET_CMODEL != CMODEL_SMALL"
10218 [(set (match_dup 3)
10219 (high:TLSmode
10220 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10221 (set (match_dup 0)
10222 (lo_sum:TLSmode (match_dup 3)
10223 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10224 "
10225 {
10226 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10227 }"
10228 [(set (attr "length")
10229 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10230 (const_int 8)
10231 (const_int 4)))])
10233 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10234 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10235 (high:TLSmode
10236 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10237 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10238 UNSPEC_TLSGOTTPREL)))]
10239 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10240 "addis %0,%1,%2@got@tprel@ha"
10241 [(set_attr "length" "4")])
10243 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10244 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10245 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10246 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10247 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10248 UNSPEC_TLSGOTTPREL)))]
10249 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10250 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
10251 [(set_attr "length" "4")])
10253 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10254 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10255 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10256 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10257 UNSPEC_TLSTLS))]
10258 "TARGET_ELF && HAVE_AS_TLS"
10259 "add %0,%1,%2@tls")
10261 (define_expand "tls_get_tpointer"
10262 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10263 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
10264 "TARGET_XCOFF && HAVE_AS_TLS"
10265 "
10266 {
10267 emit_insn (gen_tls_get_tpointer_internal ());
10268 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
10269 DONE;
10270 }")
10272 (define_insn "tls_get_tpointer_internal"
10273 [(set (reg:SI 3)
10274 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
10275 (clobber (reg:SI LR_REGNO))]
10276 "TARGET_XCOFF && HAVE_AS_TLS"
10277 "bla __get_tpointer")
10279 (define_expand "tls_get_addr<mode>"
10280 [(set (match_operand:P 0 "gpc_reg_operand" "")
10281 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
10282 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
10283 "TARGET_XCOFF && HAVE_AS_TLS"
10284 "
10285 {
10286 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
10287 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
10288 emit_insn (gen_tls_get_addr_internal<mode> ());
10289 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
10290 DONE;
10291 }")
10293 (define_insn "tls_get_addr_internal<mode>"
10294 [(set (reg:P 3)
10295 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
10296 (clobber (reg:P 0))
10297 (clobber (reg:P 4))
10298 (clobber (reg:P 5))
10299 (clobber (reg:P 11))
10300 (clobber (reg:CC CR0_REGNO))
10301 (clobber (reg:P LR_REGNO))]
10302 "TARGET_XCOFF && HAVE_AS_TLS"
10303 "bla __tls_get_addr")
10304 \f
10305 ;; Next come insns related to the calling sequence.
10306 ;;
10307 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10308 ;; We move the back-chain and decrement the stack pointer.
10310 (define_expand "allocate_stack"
10311 [(set (match_operand 0 "gpc_reg_operand" "")
10312 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10313 (set (reg 1)
10314 (minus (reg 1) (match_dup 1)))]
10315 ""
10316 "
10317 { rtx chain = gen_reg_rtx (Pmode);
10318 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10319 rtx neg_op0;
10320 rtx insn, par, set, mem;
10322 emit_move_insn (chain, stack_bot);
10324 /* Check stack bounds if necessary. */
10325 if (crtl->limit_stack)
10326 {
10327 rtx available;
10328 available = expand_binop (Pmode, sub_optab,
10329 stack_pointer_rtx, stack_limit_rtx,
10330 NULL_RTX, 1, OPTAB_WIDEN);
10331 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10332 }
10334 if (GET_CODE (operands[1]) != CONST_INT
10335 || INTVAL (operands[1]) < -32767
10336 || INTVAL (operands[1]) > 32768)
10337 {
10338 neg_op0 = gen_reg_rtx (Pmode);
10339 if (TARGET_32BIT)
10340 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10341 else
10342 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10343 }
10344 else
10345 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10347 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10348 : gen_movdi_di_update_stack))
10349 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10350 chain));
10351 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10352 it now and set the alias set/attributes. The above gen_*_update
10353 calls will generate a PARALLEL with the MEM set being the first
10354 operation. */
10355 par = PATTERN (insn);
10356 gcc_assert (GET_CODE (par) == PARALLEL);
10357 set = XVECEXP (par, 0, 0);
10358 gcc_assert (GET_CODE (set) == SET);
10359 mem = SET_DEST (set);
10360 gcc_assert (MEM_P (mem));
10361 MEM_NOTRAP_P (mem) = 1;
10362 set_mem_alias_set (mem, get_frame_alias_set ());
10364 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10365 DONE;
10366 }")
10368 ;; These patterns say how to save and restore the stack pointer. We need not
10369 ;; save the stack pointer at function level since we are careful to
10370 ;; preserve the backchain. At block level, we have to restore the backchain
10371 ;; when we restore the stack pointer.
10372 ;;
10373 ;; For nonlocal gotos, we must save both the stack pointer and its
10374 ;; backchain and restore both. Note that in the nonlocal case, the
10375 ;; save area is a memory location.
10377 (define_expand "save_stack_function"
10378 [(match_operand 0 "any_operand" "")
10379 (match_operand 1 "any_operand" "")]
10380 ""
10381 "DONE;")
10383 (define_expand "restore_stack_function"
10384 [(match_operand 0 "any_operand" "")
10385 (match_operand 1 "any_operand" "")]
10386 ""
10387 "DONE;")
10389 ;; Adjust stack pointer (op0) to a new value (op1).
10390 ;; First copy old stack backchain to new location, and ensure that the
10391 ;; scheduler won't reorder the sp assignment before the backchain write.
10392 (define_expand "restore_stack_block"
10393 [(set (match_dup 2) (match_dup 3))
10394 (set (match_dup 4) (match_dup 2))
10395 (match_dup 5)
10396 (set (match_operand 0 "register_operand" "")
10397 (match_operand 1 "register_operand" ""))]
10398 ""
10399 "
10400 {
10401 rtvec p;
10403 operands[1] = force_reg (Pmode, operands[1]);
10404 operands[2] = gen_reg_rtx (Pmode);
10405 operands[3] = gen_frame_mem (Pmode, operands[0]);
10406 operands[4] = gen_frame_mem (Pmode, operands[1]);
10407 p = rtvec_alloc (1);
10408 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10409 gen_frame_mem (BLKmode, operands[0]),
10410 const0_rtx);
10411 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10412 }")
10414 (define_expand "save_stack_nonlocal"
10415 [(set (match_dup 3) (match_dup 4))
10416 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10417 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10418 ""
10419 "
10420 {
10421 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10423 /* Copy the backchain to the first word, sp to the second. */
10424 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10425 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10426 operands[3] = gen_reg_rtx (Pmode);
10427 operands[4] = gen_frame_mem (Pmode, operands[1]);
10428 }")
10430 (define_expand "restore_stack_nonlocal"
10431 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10432 (set (match_dup 3) (match_dup 4))
10433 (set (match_dup 5) (match_dup 2))
10434 (match_dup 6)
10435 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10436 ""
10437 "
10438 {
10439 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10440 rtvec p;
10442 /* Restore the backchain from the first word, sp from the second. */
10443 operands[2] = gen_reg_rtx (Pmode);
10444 operands[3] = gen_reg_rtx (Pmode);
10445 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10446 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10447 operands[5] = gen_frame_mem (Pmode, operands[3]);
10448 p = rtvec_alloc (1);
10449 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10450 gen_frame_mem (BLKmode, operands[0]),
10451 const0_rtx);
10452 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10453 }")
10454 \f
10455 ;; TOC register handling.
10457 ;; Code to initialize the TOC register...
10459 (define_insn "load_toc_aix_si"
10460 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10461 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10462 (use (reg:SI 2))])]
10463 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
10464 "*
10465 {
10466 char buf[30];
10467 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10468 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10469 operands[2] = gen_rtx_REG (Pmode, 2);
10470 return \"lwz %0,%1(%2)\";
10471 }"
10472 [(set_attr "type" "load")
10473 (set_attr "update" "no")
10474 (set_attr "indexed" "no")])
10476 (define_insn "load_toc_aix_di"
10477 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10478 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10479 (use (reg:DI 2))])]
10480 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
10481 "*
10482 {
10483 char buf[30];
10484 #ifdef TARGET_RELOCATABLE
10485 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10486 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10487 #else
10488 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10489 #endif
10490 if (TARGET_ELF)
10491 strcat (buf, \"@toc\");
10492 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10493 operands[2] = gen_rtx_REG (Pmode, 2);
10494 return \"ld %0,%1(%2)\";
10495 }"
10496 [(set_attr "type" "load")
10497 (set_attr "update" "no")
10498 (set_attr "indexed" "no")])
10500 (define_insn "load_toc_v4_pic_si"
10501 [(set (reg:SI LR_REGNO)
10502 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10503 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10504 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10505 [(set_attr "type" "branch")
10506 (set_attr "length" "4")])
10508 (define_expand "load_toc_v4_PIC_1"
10509 [(parallel [(set (reg:SI LR_REGNO)
10510 (match_operand:SI 0 "immediate_operand" "s"))
10511 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10512 "TARGET_ELF && DEFAULT_ABI == ABI_V4
10513 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10514 "")
10516 (define_insn "load_toc_v4_PIC_1_normal"
10517 [(set (reg:SI LR_REGNO)
10518 (match_operand:SI 0 "immediate_operand" "s"))
10519 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10520 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10521 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10522 "bcl 20,31,%0\\n%0:"
10523 [(set_attr "type" "branch")
10524 (set_attr "length" "4")])
10526 (define_insn "load_toc_v4_PIC_1_476"
10527 [(set (reg:SI LR_REGNO)
10528 (match_operand:SI 0 "immediate_operand" "s"))
10529 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10530 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
10531 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10532 "*
10533 {
10534 char name[32];
10535 static char templ[32];
10537 get_ppc476_thunk_name (name);
10538 sprintf (templ, \"bl %s\\n%%0:\", name);
10539 return templ;
10540 }"
10541 [(set_attr "type" "branch")
10542 (set_attr "length" "4")])
10544 (define_expand "load_toc_v4_PIC_1b"
10545 [(parallel [(set (reg:SI LR_REGNO)
10546 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10547 (label_ref (match_operand 1 "" ""))]
10548 UNSPEC_TOCPTR))
10549 (match_dup 1)])]
10550 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10551 "")
10553 (define_insn "load_toc_v4_PIC_1b_normal"
10554 [(set (reg:SI LR_REGNO)
10555 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10556 (label_ref (match_operand 1 "" ""))]
10557 UNSPEC_TOCPTR))
10558 (match_dup 1)]
10559 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10560 "bcl 20,31,$+8\;.long %0-$"
10561 [(set_attr "type" "branch")
10562 (set_attr "length" "8")])
10564 (define_insn "load_toc_v4_PIC_1b_476"
10565 [(set (reg:SI LR_REGNO)
10566 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10567 (label_ref (match_operand 1 "" ""))]
10568 UNSPEC_TOCPTR))
10569 (match_dup 1)]
10570 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10571 "*
10572 {
10573 char name[32];
10574 static char templ[32];
10576 get_ppc476_thunk_name (name);
10577 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10578 return templ;
10579 }"
10580 [(set_attr "type" "branch")
10581 (set_attr "length" "16")])
10583 (define_insn "load_toc_v4_PIC_2"
10584 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10585 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10586 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10587 (match_operand:SI 3 "immediate_operand" "s")))))]
10588 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
10589 "lwz %0,%2-%3(%1)"
10590 [(set_attr "type" "load")])
10592 (define_insn "load_toc_v4_PIC_3b"
10593 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10594 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10595 (high:SI
10596 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10597 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10598 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10599 "addis %0,%1,%2-%3@ha")
10601 (define_insn "load_toc_v4_PIC_3c"
10602 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10603 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10604 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10605 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10606 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
10607 "addi %0,%1,%2-%3@l")
10609 ;; If the TOC is shared over a translation unit, as happens with all
10610 ;; the kinds of PIC that we support, we need to restore the TOC
10611 ;; pointer only when jumping over units of translation.
10612 ;; On Darwin, we need to reload the picbase.
10614 (define_expand "builtin_setjmp_receiver"
10615 [(use (label_ref (match_operand 0 "" "")))]
10616 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10617 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10618 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10619 "
10620 {
10621 #if TARGET_MACHO
10622 if (DEFAULT_ABI == ABI_DARWIN)
10623 {
10624 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10625 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10626 rtx tmplabrtx;
10627 char tmplab[20];
10629 crtl->uses_pic_offset_table = 1;
10630 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10631 CODE_LABEL_NUMBER (operands[0]));
10632 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10634 emit_insn (gen_load_macho_picbase (tmplabrtx));
10635 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10636 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10637 }
10638 else
10639 #endif
10640 rs6000_emit_load_toc_table (FALSE);
10641 DONE;
10642 }")
10644 ;; Largetoc support
10645 (define_insn "*largetoc_high"
10646 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10647 (high:DI
10648 (unspec [(match_operand:DI 1 "" "")
10649 (match_operand:DI 2 "gpc_reg_operand" "b")]
10650 UNSPEC_TOCREL)))]
10651 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10652 "addis %0,%2,%1@toc@ha")
10654 (define_insn "*largetoc_high_aix<mode>"
10655 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10656 (high:P
10657 (unspec [(match_operand:P 1 "" "")
10658 (match_operand:P 2 "gpc_reg_operand" "b")]
10659 UNSPEC_TOCREL)))]
10660 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10661 "addis %0,%1@u(%2)")
10663 (define_insn "*largetoc_high_plus"
10664 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10665 (high:DI
10666 (plus:DI
10667 (unspec [(match_operand:DI 1 "" "")
10668 (match_operand:DI 2 "gpc_reg_operand" "b")]
10669 UNSPEC_TOCREL)
10670 (match_operand:DI 3 "add_cint_operand" "n"))))]
10671 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10672 "addis %0,%2,%1+%3@toc@ha")
10674 (define_insn "*largetoc_high_plus_aix<mode>"
10675 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10676 (high:P
10677 (plus:P
10678 (unspec [(match_operand:P 1 "" "")
10679 (match_operand:P 2 "gpc_reg_operand" "b")]
10680 UNSPEC_TOCREL)
10681 (match_operand:P 3 "add_cint_operand" "n"))))]
10682 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10683 "addis %0,%1+%3@u(%2)")
10685 (define_insn "*largetoc_low"
10686 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10687 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
10688 (match_operand:DI 2 "" "")))]
10689 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10690 "@
10691 addi %0,%1,%2@l
10692 addic %0,%1,%2@l")
10694 (define_insn "*largetoc_low_aix<mode>"
10695 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
10696 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
10697 (match_operand:P 2 "" "")))]
10698 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10699 "la %0,%2@l(%1)")
10701 (define_insn_and_split "*tocref<mode>"
10702 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10703 (match_operand:P 1 "small_toc_ref" "R"))]
10704 "TARGET_TOC"
10705 "la %0,%a1"
10706 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10707 [(set (match_dup 0) (high:P (match_dup 1)))
10708 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10710 ;; Elf specific ways of loading addresses for non-PIC code.
10711 ;; The output of this could be r0, but we make a very strong
10712 ;; preference for a base register because it will usually
10713 ;; be needed there.
10714 (define_insn "elf_high"
10715 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10716 (high:SI (match_operand 1 "" "")))]
10717 "TARGET_ELF && ! TARGET_64BIT"
10718 "lis %0,%1@ha")
10720 (define_insn "elf_low"
10721 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10722 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10723 (match_operand 2 "" "")))]
10724 "TARGET_ELF && ! TARGET_64BIT"
10725 "@
10726 la %0,%2@l(%1)
10727 addic %0,%1,%K2")
10728 \f
10729 ;; Call and call_value insns
10730 (define_expand "call"
10731 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10732 (match_operand 1 "" ""))
10733 (use (match_operand 2 "" ""))
10734 (clobber (reg:SI LR_REGNO))])]
10735 ""
10736 "
10737 {
10738 #if TARGET_MACHO
10739 if (MACHOPIC_INDIRECT)
10740 operands[0] = machopic_indirect_call_target (operands[0]);
10741 #endif
10743 gcc_assert (GET_CODE (operands[0]) == MEM);
10744 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10746 operands[0] = XEXP (operands[0], 0);
10748 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10749 {
10750 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
10751 DONE;
10752 }
10754 if (GET_CODE (operands[0]) != SYMBOL_REF
10755 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10756 {
10757 if (INTVAL (operands[2]) & CALL_LONG)
10758 operands[0] = rs6000_longcall_ref (operands[0]);
10760 switch (DEFAULT_ABI)
10761 {
10762 case ABI_V4:
10763 case ABI_DARWIN:
10764 operands[0] = force_reg (Pmode, operands[0]);
10765 break;
10767 default:
10768 gcc_unreachable ();
10769 }
10770 }
10771 }")
10773 (define_expand "call_value"
10774 [(parallel [(set (match_operand 0 "" "")
10775 (call (mem:SI (match_operand 1 "address_operand" ""))
10776 (match_operand 2 "" "")))
10777 (use (match_operand 3 "" ""))
10778 (clobber (reg:SI LR_REGNO))])]
10779 ""
10780 "
10781 {
10782 #if TARGET_MACHO
10783 if (MACHOPIC_INDIRECT)
10784 operands[1] = machopic_indirect_call_target (operands[1]);
10785 #endif
10787 gcc_assert (GET_CODE (operands[1]) == MEM);
10788 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10790 operands[1] = XEXP (operands[1], 0);
10792 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10793 {
10794 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
10795 DONE;
10796 }
10798 if (GET_CODE (operands[1]) != SYMBOL_REF
10799 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10800 {
10801 if (INTVAL (operands[3]) & CALL_LONG)
10802 operands[1] = rs6000_longcall_ref (operands[1]);
10804 switch (DEFAULT_ABI)
10805 {
10806 case ABI_V4:
10807 case ABI_DARWIN:
10808 operands[1] = force_reg (Pmode, operands[1]);
10809 break;
10811 default:
10812 gcc_unreachable ();
10813 }
10814 }
10815 }")
10817 ;; Call to function in current module. No TOC pointer reload needed.
10818 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10819 ;; either the function was not prototyped, or it was prototyped as a
10820 ;; variable argument function. It is > 0 if FP registers were passed
10821 ;; and < 0 if they were not.
10823 (define_insn "*call_local32"
10824 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10825 (match_operand 1 "" "g,g"))
10826 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10827 (clobber (reg:SI LR_REGNO))]
10828 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10829 "*
10830 {
10831 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10832 output_asm_insn (\"crxor 6,6,6\", operands);
10834 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10835 output_asm_insn (\"creqv 6,6,6\", operands);
10837 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10838 }"
10839 [(set_attr "type" "branch")
10840 (set_attr "length" "4,8")])
10842 (define_insn "*call_local64"
10843 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10844 (match_operand 1 "" "g,g"))
10845 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10846 (clobber (reg:SI LR_REGNO))]
10847 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10848 "*
10849 {
10850 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10851 output_asm_insn (\"crxor 6,6,6\", operands);
10853 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10854 output_asm_insn (\"creqv 6,6,6\", operands);
10856 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10857 }"
10858 [(set_attr "type" "branch")
10859 (set_attr "length" "4,8")])
10861 (define_insn "*call_value_local32"
10862 [(set (match_operand 0 "" "")
10863 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10864 (match_operand 2 "" "g,g")))
10865 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10866 (clobber (reg:SI LR_REGNO))]
10867 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10868 "*
10869 {
10870 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10871 output_asm_insn (\"crxor 6,6,6\", operands);
10873 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10874 output_asm_insn (\"creqv 6,6,6\", operands);
10876 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10877 }"
10878 [(set_attr "type" "branch")
10879 (set_attr "length" "4,8")])
10882 (define_insn "*call_value_local64"
10883 [(set (match_operand 0 "" "")
10884 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10885 (match_operand 2 "" "g,g")))
10886 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10887 (clobber (reg:SI LR_REGNO))]
10888 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10889 "*
10890 {
10891 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10892 output_asm_insn (\"crxor 6,6,6\", operands);
10894 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10895 output_asm_insn (\"creqv 6,6,6\", operands);
10897 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10898 }"
10899 [(set_attr "type" "branch")
10900 (set_attr "length" "4,8")])
10903 ;; A function pointer under System V is just a normal pointer
10904 ;; operands[0] is the function pointer
10905 ;; operands[1] is the stack size to clean up
10906 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10907 ;; which indicates how to set cr1
10909 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10910 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10911 (match_operand 1 "" "g,g,g,g"))
10912 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10913 (clobber (reg:SI LR_REGNO))]
10914 "DEFAULT_ABI == ABI_V4
10915 || DEFAULT_ABI == ABI_DARWIN"
10916 {
10917 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10918 output_asm_insn ("crxor 6,6,6", operands);
10920 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10921 output_asm_insn ("creqv 6,6,6", operands);
10923 return "b%T0l";
10924 }
10925 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10926 (set_attr "length" "4,4,8,8")])
10928 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10929 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10930 (match_operand 1 "" "g,g"))
10931 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10932 (clobber (reg:SI LR_REGNO))]
10933 "(DEFAULT_ABI == ABI_DARWIN
10934 || (DEFAULT_ABI == ABI_V4
10935 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10936 {
10937 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10938 output_asm_insn ("crxor 6,6,6", operands);
10940 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10941 output_asm_insn ("creqv 6,6,6", operands);
10943 #if TARGET_MACHO
10944 return output_call(insn, operands, 0, 2);
10945 #else
10946 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10947 {
10948 gcc_assert (!TARGET_SECURE_PLT);
10949 return "bl %z0@plt";
10950 }
10951 else
10952 return "bl %z0";
10953 #endif
10954 }
10955 "DEFAULT_ABI == ABI_V4
10956 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10957 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10958 [(parallel [(call (mem:SI (match_dup 0))
10959 (match_dup 1))
10960 (use (match_dup 2))
10961 (use (match_dup 3))
10962 (clobber (reg:SI LR_REGNO))])]
10963 {
10964 operands[3] = pic_offset_table_rtx;
10965 }
10966 [(set_attr "type" "branch,branch")
10967 (set_attr "length" "4,8")])
10969 (define_insn "*call_nonlocal_sysv_secure<mode>"
10970 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10971 (match_operand 1 "" "g,g"))
10972 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10973 (use (match_operand:SI 3 "register_operand" "r,r"))
10974 (clobber (reg:SI LR_REGNO))]
10975 "(DEFAULT_ABI == ABI_V4
10976 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10977 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
10978 {
10979 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10980 output_asm_insn ("crxor 6,6,6", operands);
10982 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10983 output_asm_insn ("creqv 6,6,6", operands);
10985 if (flag_pic == 2)
10986 /* The magic 32768 offset here and in the other sysv call insns
10987 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10988 See sysv4.h:toc_section. */
10989 return "bl %z0+32768@plt";
10990 else
10991 return "bl %z0@plt";
10992 }
10993 [(set_attr "type" "branch,branch")
10994 (set_attr "length" "4,8")])
10996 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10997 [(set (match_operand 0 "" "")
10998 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10999 (match_operand 2 "" "g,g,g,g")))
11000 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11001 (clobber (reg:SI LR_REGNO))]
11002 "DEFAULT_ABI == ABI_V4
11003 || DEFAULT_ABI == ABI_DARWIN"
11004 {
11005 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11006 output_asm_insn ("crxor 6,6,6", operands);
11008 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11009 output_asm_insn ("creqv 6,6,6", operands);
11011 return "b%T1l";
11012 }
11013 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11014 (set_attr "length" "4,4,8,8")])
11016 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11017 [(set (match_operand 0 "" "")
11018 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11019 (match_operand 2 "" "g,g")))
11020 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11021 (clobber (reg:SI LR_REGNO))]
11022 "(DEFAULT_ABI == ABI_DARWIN
11023 || (DEFAULT_ABI == ABI_V4
11024 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11025 {
11026 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11027 output_asm_insn ("crxor 6,6,6", operands);
11029 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11030 output_asm_insn ("creqv 6,6,6", operands);
11032 #if TARGET_MACHO
11033 return output_call(insn, operands, 1, 3);
11034 #else
11035 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11036 {
11037 gcc_assert (!TARGET_SECURE_PLT);
11038 return "bl %z1@plt";
11039 }
11040 else
11041 return "bl %z1";
11042 #endif
11043 }
11044 "DEFAULT_ABI == ABI_V4
11045 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11046 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11047 [(parallel [(set (match_dup 0)
11048 (call (mem:SI (match_dup 1))
11049 (match_dup 2)))
11050 (use (match_dup 3))
11051 (use (match_dup 4))
11052 (clobber (reg:SI LR_REGNO))])]
11053 {
11054 operands[4] = pic_offset_table_rtx;
11055 }
11056 [(set_attr "type" "branch,branch")
11057 (set_attr "length" "4,8")])
11059 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11060 [(set (match_operand 0 "" "")
11061 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11062 (match_operand 2 "" "g,g")))
11063 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11064 (use (match_operand:SI 4 "register_operand" "r,r"))
11065 (clobber (reg:SI LR_REGNO))]
11066 "(DEFAULT_ABI == ABI_V4
11067 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11068 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11069 {
11070 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11071 output_asm_insn ("crxor 6,6,6", operands);
11073 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11074 output_asm_insn ("creqv 6,6,6", operands);
11076 if (flag_pic == 2)
11077 return "bl %z1+32768@plt";
11078 else
11079 return "bl %z1@plt";
11080 }
11081 [(set_attr "type" "branch,branch")
11082 (set_attr "length" "4,8")])
11085 ;; Call to AIX abi function in the same module.
11087 (define_insn "*call_local_aix<mode>"
11088 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
11089 (match_operand 1 "" "g"))
11090 (clobber (reg:P LR_REGNO))]
11091 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11092 "bl %z0"
11093 [(set_attr "type" "branch")
11094 (set_attr "length" "4")])
11096 (define_insn "*call_value_local_aix<mode>"
11097 [(set (match_operand 0 "" "")
11098 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
11099 (match_operand 2 "" "g")))
11100 (clobber (reg:P LR_REGNO))]
11101 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11102 "bl %z1"
11103 [(set_attr "type" "branch")
11104 (set_attr "length" "4")])
11106 ;; Call to AIX abi function which may be in another module.
11107 ;; Restore the TOC pointer (r2) after the call.
11109 (define_insn "*call_nonlocal_aix<mode>"
11110 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
11111 (match_operand 1 "" "g"))
11112 (clobber (reg:P LR_REGNO))]
11113 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11114 "bl %z0\;nop"
11115 [(set_attr "type" "branch")
11116 (set_attr "length" "8")])
11118 (define_insn "*call_value_nonlocal_aix<mode>"
11119 [(set (match_operand 0 "" "")
11120 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
11121 (match_operand 2 "" "g")))
11122 (clobber (reg:P LR_REGNO))]
11123 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11124 "bl %z1\;nop"
11125 [(set_attr "type" "branch")
11126 (set_attr "length" "8")])
11128 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11129 ;; Operand0 is the addresss of the function to call
11130 ;; Operand2 is the location in the function descriptor to load r2 from
11131 ;; Operand3 is the stack location to hold the current TOC pointer
11133 (define_insn "*call_indirect_aix<mode>"
11134 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11135 (match_operand 1 "" "g,g"))
11136 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11137 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11138 (clobber (reg:P LR_REGNO))]
11139 "DEFAULT_ABI == ABI_AIX"
11140 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11141 [(set_attr "type" "jmpreg")
11142 (set_attr "length" "12")])
11144 (define_insn "*call_value_indirect_aix<mode>"
11145 [(set (match_operand 0 "" "")
11146 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11147 (match_operand 2 "" "g,g")))
11148 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11149 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11150 (clobber (reg:P LR_REGNO))]
11151 "DEFAULT_ABI == ABI_AIX"
11152 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11153 [(set_attr "type" "jmpreg")
11154 (set_attr "length" "12")])
11156 ;; Call to indirect functions with the ELFv2 ABI.
11157 ;; Operand0 is the addresss of the function to call
11158 ;; Operand2 is the stack location to hold the current TOC pointer
11160 (define_insn "*call_indirect_elfv2<mode>"
11161 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11162 (match_operand 1 "" "g,g"))
11163 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11164 (clobber (reg:P LR_REGNO))]
11165 "DEFAULT_ABI == ABI_ELFv2"
11166 "b%T0l\;<ptrload> 2,%2"
11167 [(set_attr "type" "jmpreg")
11168 (set_attr "length" "8")])
11170 (define_insn "*call_value_indirect_elfv2<mode>"
11171 [(set (match_operand 0 "" "")
11172 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11173 (match_operand 2 "" "g,g")))
11174 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11175 (clobber (reg:P LR_REGNO))]
11176 "DEFAULT_ABI == ABI_ELFv2"
11177 "b%T1l\;<ptrload> 2,%3"
11178 [(set_attr "type" "jmpreg")
11179 (set_attr "length" "8")])
11182 ;; Call subroutine returning any type.
11183 (define_expand "untyped_call"
11184 [(parallel [(call (match_operand 0 "" "")
11185 (const_int 0))
11186 (match_operand 1 "" "")
11187 (match_operand 2 "" "")])]
11188 ""
11189 "
11190 {
11191 int i;
11193 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11195 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11196 {
11197 rtx set = XVECEXP (operands[2], 0, i);
11198 emit_move_insn (SET_DEST (set), SET_SRC (set));
11199 }
11201 /* The optimizer does not know that the call sets the function value
11202 registers we stored in the result block. We avoid problems by
11203 claiming that all hard registers are used and clobbered at this
11204 point. */
11205 emit_insn (gen_blockage ());
11207 DONE;
11208 }")
11210 ;; sibling call patterns
11211 (define_expand "sibcall"
11212 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11213 (match_operand 1 "" ""))
11214 (use (match_operand 2 "" ""))
11215 (use (reg:SI LR_REGNO))
11216 (simple_return)])]
11217 ""
11218 "
11219 {
11220 #if TARGET_MACHO
11221 if (MACHOPIC_INDIRECT)
11222 operands[0] = machopic_indirect_call_target (operands[0]);
11223 #endif
11225 gcc_assert (GET_CODE (operands[0]) == MEM);
11226 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11228 operands[0] = XEXP (operands[0], 0);
11230 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11231 {
11232 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11233 DONE;
11234 }
11235 }")
11237 (define_expand "sibcall_value"
11238 [(parallel [(set (match_operand 0 "register_operand" "")
11239 (call (mem:SI (match_operand 1 "address_operand" ""))
11240 (match_operand 2 "" "")))
11241 (use (match_operand 3 "" ""))
11242 (use (reg:SI LR_REGNO))
11243 (simple_return)])]
11244 ""
11245 "
11246 {
11247 #if TARGET_MACHO
11248 if (MACHOPIC_INDIRECT)
11249 operands[1] = machopic_indirect_call_target (operands[1]);
11250 #endif
11252 gcc_assert (GET_CODE (operands[1]) == MEM);
11253 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11255 operands[1] = XEXP (operands[1], 0);
11257 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11258 {
11259 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
11260 DONE;
11261 }
11262 }")
11264 ;; this and similar patterns must be marked as using LR, otherwise
11265 ;; dataflow will try to delete the store into it. This is true
11266 ;; even when the actual reg to jump to is in CTR, when LR was
11267 ;; saved and restored around the PIC-setting BCL.
11268 (define_insn "*sibcall_local32"
11269 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11270 (match_operand 1 "" "g,g"))
11271 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11272 (use (reg:SI LR_REGNO))
11273 (simple_return)]
11274 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11275 "*
11276 {
11277 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11278 output_asm_insn (\"crxor 6,6,6\", operands);
11280 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11281 output_asm_insn (\"creqv 6,6,6\", operands);
11283 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11284 }"
11285 [(set_attr "type" "branch")
11286 (set_attr "length" "4,8")])
11288 (define_insn "*sibcall_local64"
11289 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11290 (match_operand 1 "" "g,g"))
11291 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11292 (use (reg:SI LR_REGNO))
11293 (simple_return)]
11294 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11295 "*
11296 {
11297 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11298 output_asm_insn (\"crxor 6,6,6\", operands);
11300 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11301 output_asm_insn (\"creqv 6,6,6\", operands);
11303 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11304 }"
11305 [(set_attr "type" "branch")
11306 (set_attr "length" "4,8")])
11308 (define_insn "*sibcall_value_local32"
11309 [(set (match_operand 0 "" "")
11310 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11311 (match_operand 2 "" "g,g")))
11312 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11313 (use (reg:SI LR_REGNO))
11314 (simple_return)]
11315 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11316 "*
11317 {
11318 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11319 output_asm_insn (\"crxor 6,6,6\", operands);
11321 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11322 output_asm_insn (\"creqv 6,6,6\", operands);
11324 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11325 }"
11326 [(set_attr "type" "branch")
11327 (set_attr "length" "4,8")])
11329 (define_insn "*sibcall_value_local64"
11330 [(set (match_operand 0 "" "")
11331 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11332 (match_operand 2 "" "g,g")))
11333 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11334 (use (reg:SI LR_REGNO))
11335 (simple_return)]
11336 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11337 "*
11338 {
11339 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11340 output_asm_insn (\"crxor 6,6,6\", operands);
11342 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11343 output_asm_insn (\"creqv 6,6,6\", operands);
11345 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11346 }"
11347 [(set_attr "type" "branch")
11348 (set_attr "length" "4,8")])
11350 (define_insn "*sibcall_nonlocal_sysv<mode>"
11351 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11352 (match_operand 1 "" ""))
11353 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11354 (use (reg:SI LR_REGNO))
11355 (simple_return)]
11356 "(DEFAULT_ABI == ABI_DARWIN
11357 || DEFAULT_ABI == ABI_V4)
11358 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11359 "*
11360 {
11361 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11362 output_asm_insn (\"crxor 6,6,6\", operands);
11364 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11365 output_asm_insn (\"creqv 6,6,6\", operands);
11367 if (which_alternative >= 2)
11368 return \"b%T0\";
11369 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11370 {
11371 gcc_assert (!TARGET_SECURE_PLT);
11372 return \"b %z0@plt\";
11373 }
11374 else
11375 return \"b %z0\";
11376 }"
11377 [(set_attr "type" "branch")
11378 (set_attr "length" "4,8,4,8")])
11380 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11381 [(set (match_operand 0 "" "")
11382 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11383 (match_operand 2 "" "")))
11384 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11385 (use (reg:SI LR_REGNO))
11386 (simple_return)]
11387 "(DEFAULT_ABI == ABI_DARWIN
11388 || DEFAULT_ABI == ABI_V4)
11389 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11390 "*
11391 {
11392 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11393 output_asm_insn (\"crxor 6,6,6\", operands);
11395 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11396 output_asm_insn (\"creqv 6,6,6\", operands);
11398 if (which_alternative >= 2)
11399 return \"b%T1\";
11400 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11401 {
11402 gcc_assert (!TARGET_SECURE_PLT);
11403 return \"b %z1@plt\";
11404 }
11405 else
11406 return \"b %z1\";
11407 }"
11408 [(set_attr "type" "branch")
11409 (set_attr "length" "4,8,4,8")])
11411 ;; AIX ABI sibling call patterns.
11413 (define_insn "*sibcall_aix<mode>"
11414 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11415 (match_operand 1 "" "g,g"))
11416 (simple_return)]
11417 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11418 "@
11419 b %z0
11420 b%T0"
11421 [(set_attr "type" "branch")
11422 (set_attr "length" "4")])
11424 (define_insn "*sibcall_value_aix<mode>"
11425 [(set (match_operand 0 "" "")
11426 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11427 (match_operand 2 "" "g,g")))
11428 (simple_return)]
11429 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11430 "@
11431 b %z1
11432 b%T1"
11433 [(set_attr "type" "branch")
11434 (set_attr "length" "4")])
11436 (define_expand "sibcall_epilogue"
11437 [(use (const_int 0))]
11438 ""
11439 {
11440 if (!TARGET_SCHED_PROLOG)
11441 emit_insn (gen_blockage ());
11442 rs6000_emit_epilogue (TRUE);
11443 DONE;
11444 })
11446 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11447 ;; all of memory. This blocks insns from being moved across this point.
11449 (define_insn "blockage"
11450 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11451 ""
11452 "")
11454 (define_expand "probe_stack"
11455 [(set (match_operand 0 "memory_operand" "=m")
11456 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11457 ""
11458 {
11459 if (TARGET_64BIT)
11460 emit_insn (gen_probe_stack_di (operands[0]));
11461 else
11462 emit_insn (gen_probe_stack_si (operands[0]));
11463 DONE;
11464 })
11466 (define_insn "probe_stack_<mode>"
11467 [(set (match_operand:P 0 "memory_operand" "=m")
11468 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
11469 ""
11470 {
11471 operands[1] = gen_rtx_REG (Pmode, 0);
11472 return "st<wd>%U0%X0 %1,%0";
11473 }
11474 [(set_attr "type" "store")
11475 (set (attr "update")
11476 (if_then_else (match_operand 0 "update_address_mem")
11477 (const_string "yes")
11478 (const_string "no")))
11479 (set (attr "indexed")
11480 (if_then_else (match_operand 0 "indexed_address_mem")
11481 (const_string "yes")
11482 (const_string "no")))
11483 (set_attr "length" "4")])
11485 (define_insn "probe_stack_range<P:mode>"
11486 [(set (match_operand:P 0 "register_operand" "=r")
11487 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11488 (match_operand:P 2 "register_operand" "r")]
11489 UNSPECV_PROBE_STACK_RANGE))]
11490 ""
11491 "* return output_probe_stack_range (operands[0], operands[2]);"
11492 [(set_attr "type" "three")])
11493 \f
11494 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11495 ;; signed & unsigned, and one type of branch.
11496 ;;
11497 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11498 ;; insns, and branches.
11500 (define_expand "cbranch<mode>4"
11501 [(use (match_operator 0 "rs6000_cbranch_operator"
11502 [(match_operand:GPR 1 "gpc_reg_operand" "")
11503 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11504 (use (match_operand 3 ""))]
11505 ""
11506 "
11507 {
11508 /* Take care of the possibility that operands[2] might be negative but
11509 this might be a logical operation. That insn doesn't exist. */
11510 if (GET_CODE (operands[2]) == CONST_INT
11511 && INTVAL (operands[2]) < 0)
11512 {
11513 operands[2] = force_reg (<MODE>mode, operands[2]);
11514 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11515 GET_MODE (operands[0]),
11516 operands[1], operands[2]);
11517 }
11519 rs6000_emit_cbranch (<MODE>mode, operands);
11520 DONE;
11521 }")
11523 (define_expand "cbranch<mode>4"
11524 [(use (match_operator 0 "rs6000_cbranch_operator"
11525 [(match_operand:FP 1 "gpc_reg_operand" "")
11526 (match_operand:FP 2 "gpc_reg_operand" "")]))
11527 (use (match_operand 3 ""))]
11528 ""
11529 "
11530 {
11531 rs6000_emit_cbranch (<MODE>mode, operands);
11532 DONE;
11533 }")
11535 (define_expand "cstore<mode>4"
11536 [(use (match_operator 1 "rs6000_cbranch_operator"
11537 [(match_operand:GPR 2 "gpc_reg_operand" "")
11538 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11539 (clobber (match_operand:SI 0 "register_operand"))]
11540 ""
11541 "
11542 {
11543 /* Take care of the possibility that operands[3] might be negative but
11544 this might be a logical operation. That insn doesn't exist. */
11545 if (GET_CODE (operands[3]) == CONST_INT
11546 && INTVAL (operands[3]) < 0)
11547 {
11548 operands[3] = force_reg (<MODE>mode, operands[3]);
11549 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11550 GET_MODE (operands[1]),
11551 operands[2], operands[3]);
11552 }
11554 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11555 For SEQ, likewise, except that comparisons with zero should be done
11556 with an scc insns. However, due to the order that combine see the
11557 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11558 the cases we don't want to handle or are best handled by portable
11559 code. */
11560 if (GET_CODE (operands[1]) == NE)
11561 FAIL;
11562 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11563 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11564 && operands[3] == const0_rtx)
11565 FAIL;
11566 rs6000_emit_sCOND (<MODE>mode, operands);
11567 DONE;
11568 }")
11570 (define_expand "cstore<mode>4"
11571 [(use (match_operator 1 "rs6000_cbranch_operator"
11572 [(match_operand:FP 2 "gpc_reg_operand" "")
11573 (match_operand:FP 3 "gpc_reg_operand" "")]))
11574 (clobber (match_operand:SI 0 "register_operand"))]
11575 ""
11576 "
11577 {
11578 rs6000_emit_sCOND (<MODE>mode, operands);
11579 DONE;
11580 }")
11583 (define_expand "stack_protect_set"
11584 [(match_operand 0 "memory_operand" "")
11585 (match_operand 1 "memory_operand" "")]
11586 ""
11587 {
11588 #ifdef TARGET_THREAD_SSP_OFFSET
11589 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11590 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11591 operands[1] = gen_rtx_MEM (Pmode, addr);
11592 #endif
11593 if (TARGET_64BIT)
11594 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11595 else
11596 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11597 DONE;
11598 })
11600 (define_insn "stack_protect_setsi"
11601 [(set (match_operand:SI 0 "memory_operand" "=m")
11602 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11603 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11604 "TARGET_32BIT"
11605 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11606 [(set_attr "type" "three")
11607 (set_attr "length" "12")])
11609 (define_insn "stack_protect_setdi"
11610 [(set (match_operand:DI 0 "memory_operand" "=Y")
11611 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11612 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11613 "TARGET_64BIT"
11614 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11615 [(set_attr "type" "three")
11616 (set_attr "length" "12")])
11618 (define_expand "stack_protect_test"
11619 [(match_operand 0 "memory_operand" "")
11620 (match_operand 1 "memory_operand" "")
11621 (match_operand 2 "" "")]
11622 ""
11623 {
11624 rtx test, op0, op1;
11625 #ifdef TARGET_THREAD_SSP_OFFSET
11626 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11627 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11628 operands[1] = gen_rtx_MEM (Pmode, addr);
11629 #endif
11630 op0 = operands[0];
11631 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11632 test = gen_rtx_EQ (VOIDmode, op0, op1);
11633 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11634 DONE;
11635 })
11637 (define_insn "stack_protect_testsi"
11638 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11639 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11640 (match_operand:SI 2 "memory_operand" "m,m")]
11641 UNSPEC_SP_TEST))
11642 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11643 (clobber (match_scratch:SI 3 "=&r,&r"))]
11644 "TARGET_32BIT"
11645 "@
11646 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11647 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11648 [(set_attr "length" "16,20")])
11650 (define_insn "stack_protect_testdi"
11651 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11652 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11653 (match_operand:DI 2 "memory_operand" "Y,Y")]
11654 UNSPEC_SP_TEST))
11655 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11656 (clobber (match_scratch:DI 3 "=&r,&r"))]
11657 "TARGET_64BIT"
11658 "@
11659 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11660 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11661 [(set_attr "length" "16,20")])
11663 \f
11664 ;; Here are the actual compare insns.
11665 (define_insn "*cmp<mode>_internal1"
11666 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11667 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11668 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11669 ""
11670 "cmp<wd>%I2 %0,%1,%2"
11671 [(set_attr "type" "cmp")])
11673 ;; If we are comparing a register for equality with a large constant,
11674 ;; we can do this with an XOR followed by a compare. But this is profitable
11675 ;; only if the large constant is only used for the comparison (and in this
11676 ;; case we already have a register to reuse as scratch).
11677 ;;
11678 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11679 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11681 (define_peephole2
11682 [(set (match_operand:SI 0 "register_operand")
11683 (match_operand:SI 1 "logical_const_operand" ""))
11684 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11685 [(match_dup 0)
11686 (match_operand:SI 2 "logical_const_operand" "")]))
11687 (set (match_operand:CC 4 "cc_reg_operand" "")
11688 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11689 (match_dup 0)))
11690 (set (pc)
11691 (if_then_else (match_operator 6 "equality_operator"
11692 [(match_dup 4) (const_int 0)])
11693 (match_operand 7 "" "")
11694 (match_operand 8 "" "")))]
11695 "peep2_reg_dead_p (3, operands[0])
11696 && peep2_reg_dead_p (4, operands[4])"
11697 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11698 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11699 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11701 {
11702 /* Get the constant we are comparing against, and see what it looks like
11703 when sign-extended from 16 to 32 bits. Then see what constant we could
11704 XOR with SEXTC to get the sign-extended value. */
11705 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11706 SImode,
11707 operands[1], operands[2]);
11708 HOST_WIDE_INT c = INTVAL (cnst);
11709 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11710 HOST_WIDE_INT xorv = c ^ sextc;
11712 operands[9] = GEN_INT (xorv);
11713 operands[10] = GEN_INT (sextc);
11714 })
11716 (define_insn "*cmpsi_internal2"
11717 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11718 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11719 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11720 ""
11721 "cmplw%I2 %0,%1,%b2"
11722 [(set_attr "type" "cmp")])
11724 (define_insn "*cmpdi_internal2"
11725 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11726 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11727 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11728 ""
11729 "cmpld%I2 %0,%1,%b2"
11730 [(set_attr "type" "cmp")])
11732 ;; The following two insns don't exist as single insns, but if we provide
11733 ;; them, we can swap an add and compare, which will enable us to overlap more
11734 ;; of the required delay between a compare and branch. We generate code for
11735 ;; them by splitting.
11737 (define_insn ""
11738 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11739 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11740 (match_operand:SI 2 "short_cint_operand" "i")))
11741 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11742 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11743 ""
11744 "#"
11745 [(set_attr "length" "8")])
11747 (define_insn ""
11748 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11749 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11750 (match_operand:SI 2 "u_short_cint_operand" "i")))
11751 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11752 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11753 ""
11754 "#"
11755 [(set_attr "length" "8")])
11757 (define_split
11758 [(set (match_operand:CC 3 "cc_reg_operand" "")
11759 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11760 (match_operand:SI 2 "short_cint_operand" "")))
11761 (set (match_operand:SI 0 "gpc_reg_operand" "")
11762 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11763 ""
11764 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11765 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11767 (define_split
11768 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11769 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11770 (match_operand:SI 2 "u_short_cint_operand" "")))
11771 (set (match_operand:SI 0 "gpc_reg_operand" "")
11772 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11773 ""
11774 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11775 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11777 ;; Only need to compare second words if first words equal
11778 (define_insn "*cmptf_internal1"
11779 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11780 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11781 (match_operand:TF 2 "gpc_reg_operand" "d")))]
11782 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11783 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11784 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11785 [(set_attr "type" "fpcompare")
11786 (set_attr "length" "12")])
11788 (define_insn_and_split "*cmptf_internal2"
11789 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11790 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11791 (match_operand:TF 2 "gpc_reg_operand" "d")))
11792 (clobber (match_scratch:DF 3 "=d"))
11793 (clobber (match_scratch:DF 4 "=d"))
11794 (clobber (match_scratch:DF 5 "=d"))
11795 (clobber (match_scratch:DF 6 "=d"))
11796 (clobber (match_scratch:DF 7 "=d"))
11797 (clobber (match_scratch:DF 8 "=d"))
11798 (clobber (match_scratch:DF 9 "=d"))
11799 (clobber (match_scratch:DF 10 "=d"))
11800 (clobber (match_scratch:GPR 11 "=b"))]
11801 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11802 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11803 "#"
11804 "&& reload_completed"
11805 [(set (match_dup 3) (match_dup 14))
11806 (set (match_dup 4) (match_dup 15))
11807 (set (match_dup 9) (abs:DF (match_dup 5)))
11808 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11809 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11810 (label_ref (match_dup 12))
11811 (pc)))
11812 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11813 (set (pc) (label_ref (match_dup 13)))
11814 (match_dup 12)
11815 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11816 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11817 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11818 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11819 (match_dup 13)]
11820 {
11821 REAL_VALUE_TYPE rv;
11822 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
11823 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
11825 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11826 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11827 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11828 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11829 operands[12] = gen_label_rtx ();
11830 operands[13] = gen_label_rtx ();
11831 real_inf (&rv);
11832 operands[14] = force_const_mem (DFmode,
11833 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11834 operands[15] = force_const_mem (DFmode,
11835 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11836 DFmode));
11837 if (TARGET_TOC)
11838 {
11839 rtx tocref;
11840 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11841 operands[14] = gen_const_mem (DFmode, tocref);
11842 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11843 operands[15] = gen_const_mem (DFmode, tocref);
11844 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11845 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11846 }
11847 })
11848 \f
11849 ;; Now we have the scc insns. We can do some combinations because of the
11850 ;; way the machine works.
11851 ;;
11852 ;; Note that this is probably faster if we can put an insn between the
11853 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11854 ;; cases the insns below which don't use an intermediate CR field will
11855 ;; be used instead.
11856 (define_insn ""
11857 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11858 (match_operator:SI 1 "scc_comparison_operator"
11859 [(match_operand 2 "cc_reg_operand" "y")
11860 (const_int 0)]))]
11861 ""
11862 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11863 [(set (attr "type")
11864 (cond [(match_test "TARGET_MFCRF")
11865 (const_string "mfcrf")
11866 ]
11867 (const_string "mfcr")))
11868 (set_attr "length" "8")])
11870 ;; Same as above, but get the GT bit.
11871 (define_insn "move_from_CR_gt_bit"
11872 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11873 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11874 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11875 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11876 [(set_attr "type" "mfcr")
11877 (set_attr "length" "8")])
11879 ;; Same as above, but get the OV/ORDERED bit.
11880 (define_insn "move_from_CR_ov_bit"
11881 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11882 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
11883 UNSPEC_MV_CR_OV))]
11884 "TARGET_ISEL"
11885 "mfcr %0\;rlwinm %0,%0,%t1,1"
11886 [(set_attr "type" "mfcr")
11887 (set_attr "length" "8")])
11889 (define_insn ""
11890 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11891 (match_operator:DI 1 "scc_comparison_operator"
11892 [(match_operand 2 "cc_reg_operand" "y")
11893 (const_int 0)]))]
11894 "TARGET_POWERPC64"
11895 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11896 [(set (attr "type")
11897 (cond [(match_test "TARGET_MFCRF")
11898 (const_string "mfcrf")
11899 ]
11900 (const_string "mfcr")))
11901 (set_attr "length" "8")])
11903 (define_insn ""
11904 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11905 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11906 [(match_operand 2 "cc_reg_operand" "y,y")
11907 (const_int 0)])
11908 (const_int 0)))
11909 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11910 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11911 "TARGET_32BIT"
11912 "@
11913 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11914 #"
11915 [(set_attr "type" "shift")
11916 (set_attr "dot" "yes")
11917 (set_attr "length" "8,16")])
11919 (define_split
11920 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11921 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11922 [(match_operand 2 "cc_reg_operand" "")
11923 (const_int 0)])
11924 (const_int 0)))
11925 (set (match_operand:SI 3 "gpc_reg_operand" "")
11926 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11927 "TARGET_32BIT && reload_completed"
11928 [(set (match_dup 3)
11929 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11930 (set (match_dup 0)
11931 (compare:CC (match_dup 3)
11932 (const_int 0)))]
11933 "")
11935 (define_insn ""
11936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11937 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11938 [(match_operand 2 "cc_reg_operand" "y")
11939 (const_int 0)])
11940 (match_operand:SI 3 "const_int_operand" "n")))]
11941 ""
11942 "*
11943 {
11944 int is_bit = ccr_bit (operands[1], 1);
11945 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11946 int count;
11948 if (is_bit >= put_bit)
11949 count = is_bit - put_bit;
11950 else
11951 count = 32 - (put_bit - is_bit);
11953 operands[4] = GEN_INT (count);
11954 operands[5] = GEN_INT (put_bit);
11956 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11957 }"
11958 [(set (attr "type")
11959 (cond [(match_test "TARGET_MFCRF")
11960 (const_string "mfcrf")
11961 ]
11962 (const_string "mfcr")))
11963 (set_attr "length" "8")])
11965 (define_insn ""
11966 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11967 (compare:CC
11968 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11969 [(match_operand 2 "cc_reg_operand" "y,y")
11970 (const_int 0)])
11971 (match_operand:SI 3 "const_int_operand" "n,n"))
11972 (const_int 0)))
11973 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11974 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11975 (match_dup 3)))]
11976 ""
11977 "*
11978 {
11979 int is_bit = ccr_bit (operands[1], 1);
11980 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11981 int count;
11983 /* Force split for non-cc0 compare. */
11984 if (which_alternative == 1)
11985 return \"#\";
11987 if (is_bit >= put_bit)
11988 count = is_bit - put_bit;
11989 else
11990 count = 32 - (put_bit - is_bit);
11992 operands[5] = GEN_INT (count);
11993 operands[6] = GEN_INT (put_bit);
11995 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
11996 }"
11997 [(set_attr "type" "shift")
11998 (set_attr "dot" "yes")
11999 (set_attr "length" "8,16")])
12001 (define_split
12002 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12003 (compare:CC
12004 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12005 [(match_operand 2 "cc_reg_operand" "")
12006 (const_int 0)])
12007 (match_operand:SI 3 "const_int_operand" ""))
12008 (const_int 0)))
12009 (set (match_operand:SI 4 "gpc_reg_operand" "")
12010 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12011 (match_dup 3)))]
12012 "reload_completed"
12013 [(set (match_dup 4)
12014 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12015 (match_dup 3)))
12016 (set (match_dup 0)
12017 (compare:CC (match_dup 4)
12018 (const_int 0)))]
12019 "")
12021 ;; There is a 3 cycle delay between consecutive mfcr instructions
12022 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12024 (define_peephole
12025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12026 (match_operator:SI 1 "scc_comparison_operator"
12027 [(match_operand 2 "cc_reg_operand" "y")
12028 (const_int 0)]))
12029 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12030 (match_operator:SI 4 "scc_comparison_operator"
12031 [(match_operand 5 "cc_reg_operand" "y")
12032 (const_int 0)]))]
12033 "REGNO (operands[2]) != REGNO (operands[5])"
12034 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12035 [(set_attr "type" "mfcr")
12036 (set_attr "length" "12")])
12038 (define_peephole
12039 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12040 (match_operator:DI 1 "scc_comparison_operator"
12041 [(match_operand 2 "cc_reg_operand" "y")
12042 (const_int 0)]))
12043 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12044 (match_operator:DI 4 "scc_comparison_operator"
12045 [(match_operand 5 "cc_reg_operand" "y")
12046 (const_int 0)]))]
12047 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12048 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12049 [(set_attr "type" "mfcr")
12050 (set_attr "length" "12")])
12052 ;; There are some scc insns that can be done directly, without a compare.
12053 ;; These are faster because they don't involve the communications between
12054 ;; the FXU and branch units. In fact, we will be replacing all of the
12055 ;; integer scc insns here or in the portable methods in emit_store_flag.
12056 ;;
12057 ;; Also support (neg (scc ..)) since that construct is used to replace
12058 ;; branches, (plus (scc ..) ..) since that construct is common and
12059 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12060 ;; cases where it is no more expensive than (neg (scc ..)).
12062 ;; Have reload force a constant into a register for the simple insns that
12063 ;; otherwise won't accept constants. We do this because it is faster than
12064 ;; the cmp/mfcr sequence we would otherwise generate.
12066 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12067 (DI "rKJI")])
12069 (define_insn_and_split "*eq<mode>"
12070 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12071 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12072 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12073 ""
12074 "#"
12075 ""
12076 [(set (match_dup 0)
12077 (clz:GPR (match_dup 3)))
12078 (set (match_dup 0)
12079 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12080 {
12081 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12082 {
12083 /* Use output operand as intermediate. */
12084 operands[3] = operands[0];
12086 if (logical_operand (operands[2], <MODE>mode))
12087 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12088 gen_rtx_XOR (<MODE>mode,
12089 operands[1], operands[2])));
12090 else
12091 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12092 gen_rtx_PLUS (<MODE>mode, operands[1],
12093 negate_rtx (<MODE>mode,
12094 operands[2]))));
12095 }
12096 else
12097 operands[3] = operands[1];
12099 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12100 })
12102 (define_insn_and_split "*eq<mode>_compare"
12103 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12104 (compare:CC
12105 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12106 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12107 (const_int 0)))
12108 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12109 (eq:P (match_dup 1) (match_dup 2)))]
12110 "optimize_size"
12111 "#"
12112 "optimize_size"
12113 [(set (match_dup 0)
12114 (clz:P (match_dup 4)))
12115 (parallel [(set (match_dup 3)
12116 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12117 (const_int 0)))
12118 (set (match_dup 0)
12119 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12120 {
12121 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12122 {
12123 /* Use output operand as intermediate. */
12124 operands[4] = operands[0];
12126 if (logical_operand (operands[2], <MODE>mode))
12127 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12128 gen_rtx_XOR (<MODE>mode,
12129 operands[1], operands[2])));
12130 else
12131 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12132 gen_rtx_PLUS (<MODE>mode, operands[1],
12133 negate_rtx (<MODE>mode,
12134 operands[2]))));
12135 }
12136 else
12137 operands[4] = operands[1];
12139 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12140 })
12142 ;; We have insns of the form shown by the first define_insn below. If
12143 ;; there is something inside the comparison operation, we must split it.
12144 (define_split
12145 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12146 (plus:SI (match_operator 1 "comparison_operator"
12147 [(match_operand:SI 2 "" "")
12148 (match_operand:SI 3
12149 "reg_or_cint_operand" "")])
12150 (match_operand:SI 4 "gpc_reg_operand" "")))
12151 (clobber (match_operand:SI 5 "register_operand" ""))]
12152 "! gpc_reg_operand (operands[2], SImode)"
12153 [(set (match_dup 5) (match_dup 2))
12154 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
12155 (match_dup 4)))])
12157 (define_insn "*plus_eqsi"
12158 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12159 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12160 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12161 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12162 "TARGET_32BIT"
12163 "@
12164 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
12165 subfic %0,%1,0\;addze %0,%3
12166 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
12167 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
12168 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
12169 [(set_attr "type" "three,two,three,three,three")
12170 (set_attr "length" "12,8,12,12,12")])
12172 (define_insn "*compare_plus_eqsi"
12173 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12174 (compare:CC
12175 (plus:SI
12176 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12177 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12178 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12179 (const_int 0)))
12180 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12181 "TARGET_32BIT && optimize_size"
12182 "@
12183 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12184 subfic %4,%1,0\;addze. %4,%3
12185 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
12186 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
12187 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12188 #
12189 #
12190 #
12191 #
12192 #"
12193 [(set_attr "type" "compare")
12194 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12196 (define_split
12197 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12198 (compare:CC
12199 (plus:SI
12200 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12201 (match_operand:SI 2 "scc_eq_operand" ""))
12202 (match_operand:SI 3 "gpc_reg_operand" ""))
12203 (const_int 0)))
12204 (clobber (match_scratch:SI 4 ""))]
12205 "TARGET_32BIT && optimize_size && reload_completed"
12206 [(set (match_dup 4)
12207 (plus:SI (eq:SI (match_dup 1)
12208 (match_dup 2))
12209 (match_dup 3)))
12210 (set (match_dup 0)
12211 (compare:CC (match_dup 4)
12212 (const_int 0)))]
12213 "")
12215 (define_insn "*plus_eqsi_compare"
12216 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12217 (compare:CC
12218 (plus:SI
12219 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12220 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12221 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12222 (const_int 0)))
12223 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12224 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12225 "TARGET_32BIT && optimize_size"
12226 "@
12227 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12228 subfic %0,%1,0\;addze. %0,%3
12229 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
12230 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
12231 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12232 #
12233 #
12234 #
12235 #
12236 #"
12237 [(set_attr "type" "compare")
12238 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12240 (define_split
12241 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12242 (compare:CC
12243 (plus:SI
12244 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12245 (match_operand:SI 2 "scc_eq_operand" ""))
12246 (match_operand:SI 3 "gpc_reg_operand" ""))
12247 (const_int 0)))
12248 (set (match_operand:SI 0 "gpc_reg_operand" "")
12249 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12250 "TARGET_32BIT && optimize_size && reload_completed"
12251 [(set (match_dup 0)
12252 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12253 (set (match_dup 4)
12254 (compare:CC (match_dup 0)
12255 (const_int 0)))]
12256 "")
12258 (define_insn "*neg_eq0<mode>"
12259 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12260 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12261 (const_int 0))))]
12262 ""
12263 "addic %0,%1,-1\;subfe %0,%0,%0"
12264 [(set_attr "type" "two")
12265 (set_attr "length" "8")])
12267 (define_insn_and_split "*neg_eq<mode>"
12268 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12269 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12270 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12271 ""
12272 "#"
12273 ""
12274 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12275 {
12276 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12277 {
12278 /* Use output operand as intermediate. */
12279 operands[3] = operands[0];
12281 if (logical_operand (operands[2], <MODE>mode))
12282 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12283 gen_rtx_XOR (<MODE>mode,
12284 operands[1], operands[2])));
12285 else
12286 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12287 gen_rtx_PLUS (<MODE>mode, operands[1],
12288 negate_rtx (<MODE>mode,
12289 operands[2]))));
12290 }
12291 else
12292 operands[3] = operands[1];
12293 })
12295 (define_insn "*ne0_<mode>"
12296 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12297 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12298 (const_int 0)))
12299 (clobber (match_scratch:P 2 "=&r"))]
12300 "!(TARGET_32BIT && TARGET_ISEL)"
12301 "addic %2,%1,-1\;subfe %0,%2,%1"
12302 [(set_attr "type" "two")
12303 (set_attr "length" "8")])
12305 (define_insn "*plus_ne0_<mode>"
12306 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12307 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12308 (const_int 0))
12309 (match_operand:P 2 "gpc_reg_operand" "r")))
12310 (clobber (match_scratch:P 3 "=&r"))]
12311 ""
12312 "addic %3,%1,-1\;addze %0,%2"
12313 [(set_attr "type" "two")
12314 (set_attr "length" "8")])
12316 (define_insn "*compare_plus_ne0_<mode>"
12317 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12318 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12319 (const_int 0))
12320 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12321 (const_int 0)))
12322 (clobber (match_scratch:P 3 "=&r,&r"))
12323 (clobber (match_scratch:P 4 "=X,&r"))]
12324 ""
12325 "@
12326 addic %3,%1,-1\;addze. %3,%2
12327 #"
12328 [(set_attr "type" "compare")
12329 (set_attr "length" "8,12")])
12331 (define_split
12332 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12333 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12334 (const_int 0))
12335 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12336 (clobber (match_scratch:P 3 ""))
12337 (clobber (match_scratch:P 4 ""))]
12338 "reload_completed"
12339 [(parallel [(set (match_dup 3)
12340 (plus:P (ne:P (match_dup 1)
12341 (const_int 0))
12342 (match_dup 2)))
12343 (clobber (match_dup 4))])
12344 (set (match_dup 0)
12345 (compare:CC (match_dup 3)
12346 (const_int 0)))]
12347 "")
12349 ; For combine.
12350 (define_insn "*compare_plus_ne0_<mode>_1"
12351 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12352 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12353 (const_int 0))
12354 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
12355 (clobber (match_scratch:P 3 "=&r,&r"))
12356 (clobber (match_scratch:P 4 "=X,&r"))]
12357 ""
12358 "@
12359 addic %3,%1,-1\;addze. %3,%2
12360 #"
12361 [(set_attr "type" "compare")
12362 (set_attr "length" "8,12")])
12364 (define_split
12365 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
12366 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12367 (const_int 0))
12368 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12369 (clobber (match_scratch:P 3 ""))
12370 (clobber (match_scratch:P 4 ""))]
12371 "reload_completed"
12372 [(parallel [(set (match_dup 3)
12373 (plus:P (ne:P (match_dup 1)
12374 (const_int 0))
12375 (match_dup 2)))
12376 (clobber (match_dup 4))])
12377 (set (match_dup 0)
12378 (compare:CC (match_dup 3)
12379 (const_int 0)))]
12380 "")
12382 (define_insn "*plus_ne0_<mode>_compare"
12383 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12384 (compare:CC
12385 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12386 (const_int 0))
12387 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12388 (const_int 0)))
12389 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12390 (plus:P (ne:P (match_dup 1)
12391 (const_int 0))
12392 (match_dup 2)))
12393 (clobber (match_scratch:P 3 "=&r,&r"))]
12394 ""
12395 "@
12396 addic %3,%1,-1\;addze. %0,%2
12397 #"
12398 [(set_attr "type" "compare")
12399 (set_attr "length" "8,12")])
12401 (define_split
12402 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12403 (compare:CC
12404 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
12405 (const_int 0))
12406 (match_operand:P 2 "gpc_reg_operand" ""))
12407 (const_int 0)))
12408 (set (match_operand:P 0 "gpc_reg_operand" "")
12409 (plus:P (ne:P (match_dup 1)
12410 (const_int 0))
12411 (match_dup 2)))
12412 (clobber (match_scratch:P 3 ""))]
12413 "reload_completed"
12414 [(parallel [(set (match_dup 0)
12415 (plus:P (ne:P (match_dup 1)
12416 (const_int 0))
12417 (match_dup 2)))
12418 (clobber (match_dup 3))])
12419 (set (match_dup 4)
12420 (compare:CC (match_dup 0)
12421 (const_int 0)))]
12422 "")
12424 (define_insn "*leu<mode>"
12425 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12426 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12427 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12428 ""
12429 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12430 [(set_attr "type" "three")
12431 (set_attr "length" "12")])
12433 (define_insn "*leu<mode>_compare"
12434 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12435 (compare:CC
12436 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12437 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12438 (const_int 0)))
12439 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12440 (leu:P (match_dup 1) (match_dup 2)))]
12441 ""
12442 "@
12443 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12444 #"
12445 [(set_attr "type" "compare")
12446 (set_attr "length" "12,16")])
12448 (define_split
12449 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12450 (compare:CC
12451 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12452 (match_operand:P 2 "reg_or_short_operand" ""))
12453 (const_int 0)))
12454 (set (match_operand:P 0 "gpc_reg_operand" "")
12455 (leu:P (match_dup 1) (match_dup 2)))]
12456 "reload_completed"
12457 [(set (match_dup 0)
12458 (leu:P (match_dup 1) (match_dup 2)))
12459 (set (match_dup 3)
12460 (compare:CC (match_dup 0)
12461 (const_int 0)))]
12462 "")
12464 (define_insn "*plus_leu<mode>"
12465 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12466 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12467 (match_operand:P 2 "reg_or_short_operand" "rI"))
12468 (match_operand:P 3 "gpc_reg_operand" "r")))]
12469 ""
12470 "subf%I2c %0,%1,%2\;addze %0,%3"
12471 [(set_attr "type" "two")
12472 (set_attr "length" "8")])
12474 (define_insn ""
12475 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12476 (compare:CC
12477 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12478 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12479 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12480 (const_int 0)))
12481 (clobber (match_scratch:SI 4 "=&r,&r"))]
12482 "TARGET_32BIT"
12483 "@
12484 subf%I2c %4,%1,%2\;addze. %4,%3
12485 #"
12486 [(set_attr "type" "compare")
12487 (set_attr "length" "8,12")])
12489 (define_split
12490 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12491 (compare:CC
12492 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12493 (match_operand:SI 2 "reg_or_short_operand" ""))
12494 (match_operand:SI 3 "gpc_reg_operand" ""))
12495 (const_int 0)))
12496 (clobber (match_scratch:SI 4 ""))]
12497 "TARGET_32BIT && reload_completed"
12498 [(set (match_dup 4)
12499 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12500 (match_dup 3)))
12501 (set (match_dup 0)
12502 (compare:CC (match_dup 4)
12503 (const_int 0)))]
12504 "")
12506 (define_insn ""
12507 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12508 (compare:CC
12509 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12510 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12511 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12512 (const_int 0)))
12513 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12514 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12515 "TARGET_32BIT"
12516 "@
12517 subf%I2c %0,%1,%2\;addze. %0,%3
12518 #"
12519 [(set_attr "type" "compare")
12520 (set_attr "length" "8,12")])
12522 (define_split
12523 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12524 (compare:CC
12525 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12526 (match_operand:SI 2 "reg_or_short_operand" ""))
12527 (match_operand:SI 3 "gpc_reg_operand" ""))
12528 (const_int 0)))
12529 (set (match_operand:SI 0 "gpc_reg_operand" "")
12530 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12531 "TARGET_32BIT && reload_completed"
12532 [(set (match_dup 0)
12533 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12534 (set (match_dup 4)
12535 (compare:CC (match_dup 0)
12536 (const_int 0)))]
12537 "")
12539 (define_insn "*neg_leu<mode>"
12540 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12541 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12542 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12543 ""
12544 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
12545 [(set_attr "type" "three")
12546 (set_attr "length" "12")])
12548 (define_insn "*and_neg_leu<mode>"
12549 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12550 (and:P (neg:P
12551 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12552 (match_operand:P 2 "reg_or_short_operand" "rI")))
12553 (match_operand:P 3 "gpc_reg_operand" "r")))]
12554 ""
12555 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
12556 [(set_attr "type" "three")
12557 (set_attr "length" "12")])
12559 (define_insn ""
12560 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12561 (compare:CC
12562 (and:SI (neg:SI
12563 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12564 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12565 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12566 (const_int 0)))
12567 (clobber (match_scratch:SI 4 "=&r,&r"))]
12568 "TARGET_32BIT"
12569 "@
12570 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
12571 #"
12572 [(set_attr "type" "compare")
12573 (set_attr "length" "12,16")])
12575 (define_split
12576 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12577 (compare:CC
12578 (and:SI (neg:SI
12579 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12580 (match_operand:SI 2 "reg_or_short_operand" "")))
12581 (match_operand:SI 3 "gpc_reg_operand" ""))
12582 (const_int 0)))
12583 (clobber (match_scratch:SI 4 ""))]
12584 "TARGET_32BIT && reload_completed"
12585 [(set (match_dup 4)
12586 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12587 (match_dup 3)))
12588 (set (match_dup 0)
12589 (compare:CC (match_dup 4)
12590 (const_int 0)))]
12591 "")
12593 (define_insn ""
12594 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12595 (compare:CC
12596 (and:SI (neg:SI
12597 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12598 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12599 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12600 (const_int 0)))
12601 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12602 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12603 "TARGET_32BIT"
12604 "@
12605 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
12606 #"
12607 [(set_attr "type" "compare")
12608 (set_attr "length" "12,16")])
12610 (define_split
12611 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12612 (compare:CC
12613 (and:SI (neg:SI
12614 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12615 (match_operand:SI 2 "reg_or_short_operand" "")))
12616 (match_operand:SI 3 "gpc_reg_operand" ""))
12617 (const_int 0)))
12618 (set (match_operand:SI 0 "gpc_reg_operand" "")
12619 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12620 "TARGET_32BIT && reload_completed"
12621 [(set (match_dup 0)
12622 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12623 (match_dup 3)))
12624 (set (match_dup 4)
12625 (compare:CC (match_dup 0)
12626 (const_int 0)))]
12627 "")
12629 (define_insn_and_split "*ltu<mode>"
12630 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12631 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12632 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12633 ""
12634 "#"
12635 ""
12636 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12637 (set (match_dup 0) (neg:P (match_dup 0)))]
12638 "")
12640 (define_insn_and_split "*ltu<mode>_compare"
12641 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12642 (compare:CC
12643 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12644 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12645 (const_int 0)))
12646 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12647 (ltu:P (match_dup 1) (match_dup 2)))]
12648 ""
12649 "#"
12650 ""
12651 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12652 (parallel [(set (match_dup 3)
12653 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12654 (set (match_dup 0) (neg:P (match_dup 0)))])]
12655 "")
12657 (define_insn_and_split "*plus_ltu<mode>"
12658 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12659 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12660 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12661 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12662 ""
12663 "#"
12664 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12665 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12666 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12667 "")
12669 (define_insn_and_split "*plus_ltu<mode>_compare"
12670 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12671 (compare:CC
12672 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12673 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12674 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12675 (const_int 0)))
12676 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12677 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12678 ""
12679 "#"
12680 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12681 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12682 (parallel [(set (match_dup 4)
12683 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12684 (const_int 0)))
12685 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12686 "")
12688 (define_insn "*neg_ltu<mode>"
12689 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12690 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12691 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12692 ""
12693 "@
12694 subfc %0,%2,%1\;subfe %0,%0,%0
12695 addic %0,%1,%n2\;subfe %0,%0,%0"
12696 [(set_attr "type" "two")
12697 (set_attr "length" "8")])
12699 (define_insn "*geu<mode>"
12700 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12701 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12702 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12703 ""
12704 "@
12705 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12706 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12707 [(set_attr "type" "three")
12708 (set_attr "length" "12")])
12710 (define_insn "*geu<mode>_compare"
12711 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12712 (compare:CC
12713 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12714 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12715 (const_int 0)))
12716 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12717 (geu:P (match_dup 1) (match_dup 2)))]
12718 ""
12719 "@
12720 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12721 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12722 #
12723 #"
12724 [(set_attr "type" "compare")
12725 (set_attr "length" "12,12,16,16")])
12727 (define_split
12728 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12729 (compare:CC
12730 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12731 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12732 (const_int 0)))
12733 (set (match_operand:P 0 "gpc_reg_operand" "")
12734 (geu:P (match_dup 1) (match_dup 2)))]
12735 "reload_completed"
12736 [(set (match_dup 0)
12737 (geu:P (match_dup 1) (match_dup 2)))
12738 (set (match_dup 3)
12739 (compare:CC (match_dup 0)
12740 (const_int 0)))]
12741 "")
12743 (define_insn "*plus_geu<mode>"
12744 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12745 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12746 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12747 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12748 ""
12749 "@
12750 subfc %0,%2,%1\;addze %0,%3
12751 addic %0,%1,%n2\;addze %0,%3"
12752 [(set_attr "type" "two")
12753 (set_attr "length" "8")])
12755 (define_insn ""
12756 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12757 (compare:CC
12758 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12759 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12760 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12761 (const_int 0)))
12762 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12763 "TARGET_32BIT"
12764 "@
12765 subfc %4,%2,%1\;addze. %4,%3
12766 addic %4,%1,%n2\;addze. %4,%3
12767 #
12768 #"
12769 [(set_attr "type" "compare")
12770 (set_attr "length" "8,8,12,12")])
12772 (define_split
12773 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12774 (compare:CC
12775 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12776 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12777 (match_operand:SI 3 "gpc_reg_operand" ""))
12778 (const_int 0)))
12779 (clobber (match_scratch:SI 4 ""))]
12780 "TARGET_32BIT && reload_completed"
12781 [(set (match_dup 4)
12782 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12783 (match_dup 3)))
12784 (set (match_dup 0)
12785 (compare:CC (match_dup 4)
12786 (const_int 0)))]
12787 "")
12789 (define_insn ""
12790 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12791 (compare:CC
12792 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12793 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12794 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12795 (const_int 0)))
12796 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12797 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12798 "TARGET_32BIT"
12799 "@
12800 subfc %0,%2,%1\;addze. %0,%3
12801 addic %0,%1,%n2\;addze. %0,%3
12802 #
12803 #"
12804 [(set_attr "type" "compare")
12805 (set_attr "length" "8,8,12,12")])
12807 (define_split
12808 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12809 (compare:CC
12810 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12811 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12812 (match_operand:SI 3 "gpc_reg_operand" ""))
12813 (const_int 0)))
12814 (set (match_operand:SI 0 "gpc_reg_operand" "")
12815 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12816 "TARGET_32BIT && reload_completed"
12817 [(set (match_dup 0)
12818 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12819 (set (match_dup 4)
12820 (compare:CC (match_dup 0)
12821 (const_int 0)))]
12822 "")
12824 (define_insn "*neg_geu<mode>"
12825 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12826 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12827 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12828 ""
12829 "@
12830 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
12831 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
12832 [(set_attr "type" "three")
12833 (set_attr "length" "12")])
12835 (define_insn "*and_neg_geu<mode>"
12836 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12837 (and:P (neg:P
12838 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12839 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12840 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12841 ""
12842 "@
12843 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
12844 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
12845 [(set_attr "type" "three")
12846 (set_attr "length" "12")])
12848 (define_insn ""
12849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12850 (compare:CC
12851 (and:SI (neg:SI
12852 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12853 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12854 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12855 (const_int 0)))
12856 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12857 "TARGET_32BIT"
12858 "@
12859 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
12860 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
12861 #
12862 #"
12863 [(set_attr "type" "compare")
12864 (set_attr "length" "12,12,16,16")])
12866 (define_split
12867 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12868 (compare:CC
12869 (and:SI (neg:SI
12870 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12871 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12872 (match_operand:SI 3 "gpc_reg_operand" ""))
12873 (const_int 0)))
12874 (clobber (match_scratch:SI 4 ""))]
12875 "TARGET_32BIT && reload_completed"
12876 [(set (match_dup 4)
12877 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12878 (match_dup 3)))
12879 (set (match_dup 0)
12880 (compare:CC (match_dup 4)
12881 (const_int 0)))]
12882 "")
12884 (define_insn ""
12885 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12886 (compare:CC
12887 (and:SI (neg:SI
12888 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12889 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12890 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12891 (const_int 0)))
12892 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12893 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12894 "TARGET_32BIT"
12895 "@
12896 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
12897 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
12898 #
12899 #"
12900 [(set_attr "type" "compare")
12901 (set_attr "length" "12,12,16,16")])
12903 (define_split
12904 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12905 (compare:CC
12906 (and:SI (neg:SI
12907 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12908 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12909 (match_operand:SI 3 "gpc_reg_operand" ""))
12910 (const_int 0)))
12911 (set (match_operand:SI 0 "gpc_reg_operand" "")
12912 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12913 "TARGET_32BIT && reload_completed"
12914 [(set (match_dup 0)
12915 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12916 (set (match_dup 4)
12917 (compare:CC (match_dup 0)
12918 (const_int 0)))]
12919 "")
12921 (define_insn "*plus_gt0<mode>"
12922 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12923 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12924 (const_int 0))
12925 (match_operand:P 2 "gpc_reg_operand" "r")))]
12926 ""
12927 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12928 [(set_attr "type" "three")
12929 (set_attr "length" "12")])
12931 (define_insn ""
12932 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12933 (compare:CC
12934 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12935 (const_int 0))
12936 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12937 (const_int 0)))
12938 (clobber (match_scratch:SI 3 "=&r,&r"))]
12939 "TARGET_32BIT"
12940 "@
12941 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12942 #"
12943 [(set_attr "type" "compare")
12944 (set_attr "length" "12,16")])
12946 (define_split
12947 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12948 (compare:CC
12949 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12950 (const_int 0))
12951 (match_operand:SI 2 "gpc_reg_operand" ""))
12952 (const_int 0)))
12953 (clobber (match_scratch:SI 3 ""))]
12954 "TARGET_32BIT && reload_completed"
12955 [(set (match_dup 3)
12956 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12957 (match_dup 2)))
12958 (set (match_dup 0)
12959 (compare:CC (match_dup 3)
12960 (const_int 0)))]
12961 "")
12963 (define_insn ""
12964 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12965 (compare:CC
12966 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12967 (const_int 0))
12968 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12969 (const_int 0)))
12970 (clobber (match_scratch:DI 3 "=&r,&r"))]
12971 "TARGET_64BIT"
12972 "@
12973 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12974 #"
12975 [(set_attr "type" "compare")
12976 (set_attr "length" "12,16")])
12978 (define_split
12979 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12980 (compare:CC
12981 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12982 (const_int 0))
12983 (match_operand:DI 2 "gpc_reg_operand" ""))
12984 (const_int 0)))
12985 (clobber (match_scratch:DI 3 ""))]
12986 "TARGET_64BIT && reload_completed"
12987 [(set (match_dup 3)
12988 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12989 (match_dup 2)))
12990 (set (match_dup 0)
12991 (compare:CC (match_dup 3)
12992 (const_int 0)))]
12993 "")
12995 (define_insn ""
12996 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12997 (compare:CC
12998 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12999 (const_int 0))
13000 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13001 (const_int 0)))
13002 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13003 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13004 "TARGET_32BIT"
13005 "@
13006 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13007 #"
13008 [(set_attr "type" "compare")
13009 (set_attr "length" "12,16")])
13011 (define_split
13012 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13013 (compare:CC
13014 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13015 (const_int 0))
13016 (match_operand:SI 2 "gpc_reg_operand" ""))
13017 (const_int 0)))
13018 (set (match_operand:SI 0 "gpc_reg_operand" "")
13019 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13020 "TARGET_32BIT && reload_completed"
13021 [(set (match_dup 0)
13022 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13023 (set (match_dup 3)
13024 (compare:CC (match_dup 0)
13025 (const_int 0)))]
13026 "")
13028 (define_insn ""
13029 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13030 (compare:CC
13031 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13032 (const_int 0))
13033 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13034 (const_int 0)))
13035 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13036 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13037 "TARGET_64BIT"
13038 "@
13039 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13040 #"
13041 [(set_attr "type" "compare")
13042 (set_attr "length" "12,16")])
13044 (define_split
13045 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13046 (compare:CC
13047 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13048 (const_int 0))
13049 (match_operand:DI 2 "gpc_reg_operand" ""))
13050 (const_int 0)))
13051 (set (match_operand:DI 0 "gpc_reg_operand" "")
13052 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13053 "TARGET_64BIT && reload_completed"
13054 [(set (match_dup 0)
13055 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13056 (set (match_dup 3)
13057 (compare:CC (match_dup 0)
13058 (const_int 0)))]
13059 "")
13061 (define_insn_and_split "*gtu<mode>"
13062 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13063 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13064 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13065 ""
13066 "#"
13067 ""
13068 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13069 (set (match_dup 0) (neg:P (match_dup 0)))]
13070 "")
13072 (define_insn_and_split "*gtu<mode>_compare"
13073 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13074 (compare:CC
13075 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13076 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13077 (const_int 0)))
13078 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13079 (gtu:P (match_dup 1) (match_dup 2)))]
13080 ""
13081 "#"
13082 ""
13083 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13084 (parallel [(set (match_dup 3)
13085 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13086 (set (match_dup 0) (neg:P (match_dup 0)))])]
13087 "")
13089 (define_insn_and_split "*plus_gtu<mode>"
13090 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13091 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13092 (match_operand:P 2 "reg_or_short_operand" "rI"))
13093 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13094 ""
13095 "#"
13096 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13097 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13098 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13099 "")
13101 (define_insn_and_split "*plus_gtu<mode>_compare"
13102 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13103 (compare:CC
13104 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13105 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13106 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13107 (const_int 0)))
13108 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13109 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13110 ""
13111 "#"
13112 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13113 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13114 (parallel [(set (match_dup 4)
13115 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13116 (const_int 0)))
13117 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13118 "")
13120 (define_insn "*neg_gtu<mode>"
13121 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13122 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13123 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13124 ""
13125 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13126 [(set_attr "type" "two")
13127 (set_attr "length" "8")])
13129 \f
13130 ;; Define both directions of branch and return. If we need a reload
13131 ;; register, we'd rather use CR0 since it is much easier to copy a
13132 ;; register CC value to there.
13134 (define_insn ""
13135 [(set (pc)
13136 (if_then_else (match_operator 1 "branch_comparison_operator"
13137 [(match_operand 2
13138 "cc_reg_operand" "y")
13139 (const_int 0)])
13140 (label_ref (match_operand 0 "" ""))
13141 (pc)))]
13142 ""
13143 "*
13144 {
13145 return output_cbranch (operands[1], \"%l0\", 0, insn);
13146 }"
13147 [(set_attr "type" "branch")])
13149 (define_insn ""
13150 [(set (pc)
13151 (if_then_else (match_operator 0 "branch_comparison_operator"
13152 [(match_operand 1
13153 "cc_reg_operand" "y")
13154 (const_int 0)])
13155 (any_return)
13156 (pc)))]
13157 "<return_pred>"
13158 "*
13159 {
13160 return output_cbranch (operands[0], NULL, 0, insn);
13161 }"
13162 [(set_attr "type" "jmpreg")
13163 (set_attr "length" "4")])
13165 (define_insn ""
13166 [(set (pc)
13167 (if_then_else (match_operator 1 "branch_comparison_operator"
13168 [(match_operand 2
13169 "cc_reg_operand" "y")
13170 (const_int 0)])
13171 (pc)
13172 (label_ref (match_operand 0 "" ""))))]
13173 ""
13174 "*
13175 {
13176 return output_cbranch (operands[1], \"%l0\", 1, insn);
13177 }"
13178 [(set_attr "type" "branch")])
13180 (define_insn ""
13181 [(set (pc)
13182 (if_then_else (match_operator 0 "branch_comparison_operator"
13183 [(match_operand 1
13184 "cc_reg_operand" "y")
13185 (const_int 0)])
13186 (pc)
13187 (any_return)))]
13188 "<return_pred>"
13189 "*
13190 {
13191 return output_cbranch (operands[0], NULL, 1, insn);
13192 }"
13193 [(set_attr "type" "jmpreg")
13194 (set_attr "length" "4")])
13196 ;; Logic on condition register values.
13198 ; This pattern matches things like
13199 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13200 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13201 ; (const_int 1)))
13202 ; which are generated by the branch logic.
13203 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13205 (define_insn "*cceq_ior_compare"
13206 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13207 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13208 [(match_operator:SI 2
13209 "branch_positive_comparison_operator"
13210 [(match_operand 3
13211 "cc_reg_operand" "y,y")
13212 (const_int 0)])
13213 (match_operator:SI 4
13214 "branch_positive_comparison_operator"
13215 [(match_operand 5
13216 "cc_reg_operand" "0,y")
13217 (const_int 0)])])
13218 (const_int 1)))]
13219 ""
13220 "cr%q1 %E0,%j2,%j4"
13221 [(set_attr "type" "cr_logical,delayed_cr")])
13223 ; Why is the constant -1 here, but 1 in the previous pattern?
13224 ; Because ~1 has all but the low bit set.
13225 (define_insn ""
13226 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13227 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13228 [(not:SI (match_operator:SI 2
13229 "branch_positive_comparison_operator"
13230 [(match_operand 3
13231 "cc_reg_operand" "y,y")
13232 (const_int 0)]))
13233 (match_operator:SI 4
13234 "branch_positive_comparison_operator"
13235 [(match_operand 5
13236 "cc_reg_operand" "0,y")
13237 (const_int 0)])])
13238 (const_int -1)))]
13239 ""
13240 "cr%q1 %E0,%j2,%j4"
13241 [(set_attr "type" "cr_logical,delayed_cr")])
13243 (define_insn "*cceq_rev_compare"
13244 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13245 (compare:CCEQ (match_operator:SI 1
13246 "branch_positive_comparison_operator"
13247 [(match_operand 2
13248 "cc_reg_operand" "0,y")
13249 (const_int 0)])
13250 (const_int 0)))]
13251 ""
13252 "crnot %E0,%j1"
13253 [(set_attr "type" "cr_logical,delayed_cr")])
13255 ;; If we are comparing the result of two comparisons, this can be done
13256 ;; using creqv or crxor.
13258 (define_insn_and_split ""
13259 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13260 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13261 [(match_operand 2 "cc_reg_operand" "y")
13262 (const_int 0)])
13263 (match_operator 3 "branch_comparison_operator"
13264 [(match_operand 4 "cc_reg_operand" "y")
13265 (const_int 0)])))]
13266 ""
13267 "#"
13268 ""
13269 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13270 (match_dup 5)))]
13271 "
13272 {
13273 int positive_1, positive_2;
13275 positive_1 = branch_positive_comparison_operator (operands[1],
13276 GET_MODE (operands[1]));
13277 positive_2 = branch_positive_comparison_operator (operands[3],
13278 GET_MODE (operands[3]));
13280 if (! positive_1)
13281 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13282 GET_CODE (operands[1])),
13283 SImode,
13284 operands[2], const0_rtx);
13285 else if (GET_MODE (operands[1]) != SImode)
13286 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13287 operands[2], const0_rtx);
13289 if (! positive_2)
13290 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13291 GET_CODE (operands[3])),
13292 SImode,
13293 operands[4], const0_rtx);
13294 else if (GET_MODE (operands[3]) != SImode)
13295 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13296 operands[4], const0_rtx);
13298 if (positive_1 == positive_2)
13299 {
13300 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13301 operands[5] = constm1_rtx;
13302 }
13303 else
13304 {
13305 operands[5] = const1_rtx;
13306 }
13307 }")
13309 ;; Unconditional branch and return.
13311 (define_insn "jump"
13312 [(set (pc)
13313 (label_ref (match_operand 0 "" "")))]
13314 ""
13315 "b %l0"
13316 [(set_attr "type" "branch")])
13318 (define_insn "<return_str>return"
13319 [(any_return)]
13320 "<return_pred>"
13321 "blr"
13322 [(set_attr "type" "jmpreg")])
13324 (define_expand "indirect_jump"
13325 [(set (pc) (match_operand 0 "register_operand" ""))])
13327 (define_insn "*indirect_jump<mode>"
13328 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13329 ""
13330 "@
13331 bctr
13332 blr"
13333 [(set_attr "type" "jmpreg")])
13335 ;; Table jump for switch statements:
13336 (define_expand "tablejump"
13337 [(use (match_operand 0 "" ""))
13338 (use (label_ref (match_operand 1 "" "")))]
13339 ""
13340 "
13341 {
13342 if (TARGET_32BIT)
13343 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13344 else
13345 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13346 DONE;
13347 }")
13349 (define_expand "tablejumpsi"
13350 [(set (match_dup 3)
13351 (plus:SI (match_operand:SI 0 "" "")
13352 (match_dup 2)))
13353 (parallel [(set (pc) (match_dup 3))
13354 (use (label_ref (match_operand 1 "" "")))])]
13355 "TARGET_32BIT"
13356 "
13357 { operands[0] = force_reg (SImode, operands[0]);
13358 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13359 operands[3] = gen_reg_rtx (SImode);
13360 }")
13362 (define_expand "tablejumpdi"
13363 [(set (match_dup 4)
13364 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13365 (set (match_dup 3)
13366 (plus:DI (match_dup 4)
13367 (match_dup 2)))
13368 (parallel [(set (pc) (match_dup 3))
13369 (use (label_ref (match_operand 1 "" "")))])]
13370 "TARGET_64BIT"
13371 "
13372 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13373 operands[3] = gen_reg_rtx (DImode);
13374 operands[4] = gen_reg_rtx (DImode);
13375 }")
13377 (define_insn "*tablejump<mode>_internal1"
13378 [(set (pc)
13379 (match_operand:P 0 "register_operand" "c,*l"))
13380 (use (label_ref (match_operand 1 "" "")))]
13381 ""
13382 "@
13383 bctr
13384 blr"
13385 [(set_attr "type" "jmpreg")])
13387 (define_insn "nop"
13388 [(const_int 0)]
13389 ""
13390 "nop")
13392 (define_insn "group_ending_nop"
13393 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13394 ""
13395 "*
13396 {
13397 if (rs6000_cpu_attr == CPU_POWER6)
13398 return \"ori 1,1,0\";
13399 return \"ori 2,2,0\";
13400 }")
13401 \f
13402 ;; Define the subtract-one-and-jump insns, starting with the template
13403 ;; so loop.c knows what to generate.
13405 (define_expand "doloop_end"
13406 [(use (match_operand 0 "" "")) ; loop pseudo
13407 (use (match_operand 1 "" ""))] ; label
13408 ""
13409 "
13410 {
13411 if (TARGET_64BIT)
13412 {
13413 if (GET_MODE (operands[0]) != DImode)
13414 FAIL;
13415 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
13416 }
13417 else
13418 {
13419 if (GET_MODE (operands[0]) != SImode)
13420 FAIL;
13421 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
13422 }
13423 DONE;
13424 }")
13426 (define_expand "ctr<mode>"
13427 [(parallel [(set (pc)
13428 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13429 (const_int 1))
13430 (label_ref (match_operand 1 "" ""))
13431 (pc)))
13432 (set (match_dup 0)
13433 (plus:P (match_dup 0)
13434 (const_int -1)))
13435 (clobber (match_scratch:CC 2 ""))
13436 (clobber (match_scratch:P 3 ""))])]
13437 ""
13438 "")
13440 ;; We need to be able to do this for any operand, including MEM, or we
13441 ;; will cause reload to blow up since we don't allow output reloads on
13442 ;; JUMP_INSNs.
13443 ;; For the length attribute to be calculated correctly, the
13444 ;; label MUST be operand 0.
13446 (define_insn "*ctr<mode>_internal1"
13447 [(set (pc)
13448 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13449 (const_int 1))
13450 (label_ref (match_operand 0 "" ""))
13451 (pc)))
13452 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13453 (plus:P (match_dup 1)
13454 (const_int -1)))
13455 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13456 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13457 ""
13458 "*
13459 {
13460 if (which_alternative != 0)
13461 return \"#\";
13462 else if (get_attr_length (insn) == 4)
13463 return \"bdnz %l0\";
13464 else
13465 return \"bdz $+8\;b %l0\";
13466 }"
13467 [(set_attr "type" "branch")
13468 (set_attr "length" "*,12,16,16")])
13470 (define_insn "*ctr<mode>_internal2"
13471 [(set (pc)
13472 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13473 (const_int 1))
13474 (pc)
13475 (label_ref (match_operand 0 "" ""))))
13476 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13477 (plus:P (match_dup 1)
13478 (const_int -1)))
13479 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13480 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13481 ""
13482 "*
13483 {
13484 if (which_alternative != 0)
13485 return \"#\";
13486 else if (get_attr_length (insn) == 4)
13487 return \"bdz %l0\";
13488 else
13489 return \"bdnz $+8\;b %l0\";
13490 }"
13491 [(set_attr "type" "branch")
13492 (set_attr "length" "*,12,16,16")])
13494 ;; Similar but use EQ
13496 (define_insn "*ctr<mode>_internal5"
13497 [(set (pc)
13498 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13499 (const_int 1))
13500 (label_ref (match_operand 0 "" ""))
13501 (pc)))
13502 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13503 (plus:P (match_dup 1)
13504 (const_int -1)))
13505 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13506 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13507 ""
13508 "*
13509 {
13510 if (which_alternative != 0)
13511 return \"#\";
13512 else if (get_attr_length (insn) == 4)
13513 return \"bdz %l0\";
13514 else
13515 return \"bdnz $+8\;b %l0\";
13516 }"
13517 [(set_attr "type" "branch")
13518 (set_attr "length" "*,12,16,16")])
13520 (define_insn "*ctr<mode>_internal6"
13521 [(set (pc)
13522 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13523 (const_int 1))
13524 (pc)
13525 (label_ref (match_operand 0 "" ""))))
13526 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13527 (plus:P (match_dup 1)
13528 (const_int -1)))
13529 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13530 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13531 ""
13532 "*
13533 {
13534 if (which_alternative != 0)
13535 return \"#\";
13536 else if (get_attr_length (insn) == 4)
13537 return \"bdnz %l0\";
13538 else
13539 return \"bdz $+8\;b %l0\";
13540 }"
13541 [(set_attr "type" "branch")
13542 (set_attr "length" "*,12,16,16")])
13544 ;; Now the splitters if we could not allocate the CTR register
13546 (define_split
13547 [(set (pc)
13548 (if_then_else (match_operator 2 "comparison_operator"
13549 [(match_operand:P 1 "gpc_reg_operand" "")
13550 (const_int 1)])
13551 (match_operand 5 "" "")
13552 (match_operand 6 "" "")))
13553 (set (match_operand:P 0 "gpc_reg_operand" "")
13554 (plus:P (match_dup 1) (const_int -1)))
13555 (clobber (match_scratch:CC 3 ""))
13556 (clobber (match_scratch:P 4 ""))]
13557 "reload_completed"
13558 [(parallel [(set (match_dup 3)
13559 (compare:CC (plus:P (match_dup 1)
13560 (const_int -1))
13561 (const_int 0)))
13562 (set (match_dup 0)
13563 (plus:P (match_dup 1)
13564 (const_int -1)))])
13565 (set (pc) (if_then_else (match_dup 7)
13566 (match_dup 5)
13567 (match_dup 6)))]
13568 "
13569 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13570 operands[3], const0_rtx); }")
13572 (define_split
13573 [(set (pc)
13574 (if_then_else (match_operator 2 "comparison_operator"
13575 [(match_operand:P 1 "gpc_reg_operand" "")
13576 (const_int 1)])
13577 (match_operand 5 "" "")
13578 (match_operand 6 "" "")))
13579 (set (match_operand:P 0 "nonimmediate_operand" "")
13580 (plus:P (match_dup 1) (const_int -1)))
13581 (clobber (match_scratch:CC 3 ""))
13582 (clobber (match_scratch:P 4 ""))]
13583 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13584 [(parallel [(set (match_dup 3)
13585 (compare:CC (plus:P (match_dup 1)
13586 (const_int -1))
13587 (const_int 0)))
13588 (set (match_dup 4)
13589 (plus:P (match_dup 1)
13590 (const_int -1)))])
13591 (set (match_dup 0)
13592 (match_dup 4))
13593 (set (pc) (if_then_else (match_dup 7)
13594 (match_dup 5)
13595 (match_dup 6)))]
13596 "
13597 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13598 operands[3], const0_rtx); }")
13599 \f
13600 (define_insn "trap"
13601 [(trap_if (const_int 1) (const_int 0))]
13602 ""
13603 "trap"
13604 [(set_attr "type" "trap")])
13606 (define_expand "ctrap<mode>4"
13607 [(trap_if (match_operator 0 "ordered_comparison_operator"
13608 [(match_operand:GPR 1 "register_operand")
13609 (match_operand:GPR 2 "reg_or_short_operand")])
13610 (match_operand 3 "zero_constant" ""))]
13611 ""
13612 "")
13614 (define_insn ""
13615 [(trap_if (match_operator 0 "ordered_comparison_operator"
13616 [(match_operand:GPR 1 "register_operand" "r")
13617 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13618 (const_int 0))]
13619 ""
13620 "t<wd>%V0%I2 %1,%2"
13621 [(set_attr "type" "trap")])
13622 \f
13623 ;; Insns related to generating the function prologue and epilogue.
13625 (define_expand "prologue"
13626 [(use (const_int 0))]
13627 ""
13628 {
13629 rs6000_emit_prologue ();
13630 if (!TARGET_SCHED_PROLOG)
13631 emit_insn (gen_blockage ());
13632 DONE;
13633 })
13635 (define_insn "*movesi_from_cr_one"
13636 [(match_parallel 0 "mfcr_operation"
13637 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13638 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13639 (match_operand 3 "immediate_operand" "n")]
13640 UNSPEC_MOVESI_FROM_CR))])]
13641 "TARGET_MFCRF"
13642 "*
13643 {
13644 int mask = 0;
13645 int i;
13646 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13647 {
13648 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13649 operands[4] = GEN_INT (mask);
13650 output_asm_insn (\"mfcr %1,%4\", operands);
13651 }
13652 return \"\";
13653 }"
13654 [(set_attr "type" "mfcrf")])
13656 (define_insn "movesi_from_cr"
13657 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13658 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13659 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13660 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13661 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13662 UNSPEC_MOVESI_FROM_CR))]
13663 ""
13664 "mfcr %0"
13665 [(set_attr "type" "mfcr")])
13667 (define_insn "*crsave"
13668 [(match_parallel 0 "crsave_operation"
13669 [(set (match_operand:SI 1 "memory_operand" "=m")
13670 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13671 ""
13672 "stw %2,%1"
13673 [(set_attr "type" "store")])
13675 (define_insn "*stmw"
13676 [(match_parallel 0 "stmw_operation"
13677 [(set (match_operand:SI 1 "memory_operand" "=m")
13678 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13679 "TARGET_MULTIPLE"
13680 "stmw %2,%1"
13681 [(set_attr "type" "store")
13682 (set_attr "update" "yes")
13683 (set_attr "indexed" "yes")])
13685 ; The following comment applies to:
13686 ; save_gpregs_*
13687 ; save_fpregs_*
13688 ; restore_gpregs*
13689 ; return_and_restore_gpregs*
13690 ; return_and_restore_fpregs*
13691 ; return_and_restore_fpregs_aix*
13692 ;
13693 ; The out-of-line save / restore functions expects one input argument.
13694 ; Since those are not standard call_insn's, we must avoid using
13695 ; MATCH_OPERAND for that argument. That way the register rename
13696 ; optimization will not try to rename this register.
13697 ; Each pattern is repeated for each possible register number used in
13698 ; various ABIs (r11, r1, and for some functions r12)
13700 (define_insn "*save_gpregs_<mode>_r11"
13701 [(match_parallel 0 "any_parallel_operand"
13702 [(clobber (reg:P 65))
13703 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13704 (use (reg:P 11))
13705 (set (match_operand:P 2 "memory_operand" "=m")
13706 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13707 ""
13708 "bl %1"
13709 [(set_attr "type" "branch")
13710 (set_attr "length" "4")])
13712 (define_insn "*save_gpregs_<mode>_r12"
13713 [(match_parallel 0 "any_parallel_operand"
13714 [(clobber (reg:P 65))
13715 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13716 (use (reg:P 12))
13717 (set (match_operand:P 2 "memory_operand" "=m")
13718 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13719 ""
13720 "bl %1"
13721 [(set_attr "type" "branch")
13722 (set_attr "length" "4")])
13724 (define_insn "*save_gpregs_<mode>_r1"
13725 [(match_parallel 0 "any_parallel_operand"
13726 [(clobber (reg:P 65))
13727 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13728 (use (reg:P 1))
13729 (set (match_operand:P 2 "memory_operand" "=m")
13730 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13731 ""
13732 "bl %1"
13733 [(set_attr "type" "branch")
13734 (set_attr "length" "4")])
13736 (define_insn "*save_fpregs_<mode>_r11"
13737 [(match_parallel 0 "any_parallel_operand"
13738 [(clobber (reg:P 65))
13739 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13740 (use (reg:P 11))
13741 (set (match_operand:DF 2 "memory_operand" "=m")
13742 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13743 ""
13744 "bl %1"
13745 [(set_attr "type" "branch")
13746 (set_attr "length" "4")])
13748 (define_insn "*save_fpregs_<mode>_r12"
13749 [(match_parallel 0 "any_parallel_operand"
13750 [(clobber (reg:P 65))
13751 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13752 (use (reg:P 12))
13753 (set (match_operand:DF 2 "memory_operand" "=m")
13754 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13755 ""
13756 "bl %1"
13757 [(set_attr "type" "branch")
13758 (set_attr "length" "4")])
13760 (define_insn "*save_fpregs_<mode>_r1"
13761 [(match_parallel 0 "any_parallel_operand"
13762 [(clobber (reg:P 65))
13763 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13764 (use (reg:P 1))
13765 (set (match_operand:DF 2 "memory_operand" "=m")
13766 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13767 ""
13768 "bl %1"
13769 [(set_attr "type" "branch")
13770 (set_attr "length" "4")])
13772 ; This is to explain that changes to the stack pointer should
13773 ; not be moved over loads from or stores to stack memory.
13774 (define_insn "stack_tie"
13775 [(match_parallel 0 "tie_operand"
13776 [(set (mem:BLK (reg 1)) (const_int 0))])]
13777 ""
13778 ""
13779 [(set_attr "length" "0")])
13781 (define_expand "epilogue"
13782 [(use (const_int 0))]
13783 ""
13784 {
13785 if (!TARGET_SCHED_PROLOG)
13786 emit_insn (gen_blockage ());
13787 rs6000_emit_epilogue (FALSE);
13788 DONE;
13789 })
13791 ; On some processors, doing the mtcrf one CC register at a time is
13792 ; faster (like on the 604e). On others, doing them all at once is
13793 ; faster; for instance, on the 601 and 750.
13795 (define_expand "movsi_to_cr_one"
13796 [(set (match_operand:CC 0 "cc_reg_operand" "")
13797 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13798 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13799 ""
13800 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13802 (define_insn "*movsi_to_cr"
13803 [(match_parallel 0 "mtcrf_operation"
13804 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13805 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13806 (match_operand 3 "immediate_operand" "n")]
13807 UNSPEC_MOVESI_TO_CR))])]
13808 ""
13809 "*
13810 {
13811 int mask = 0;
13812 int i;
13813 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13814 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13815 operands[4] = GEN_INT (mask);
13816 return \"mtcrf %4,%2\";
13817 }"
13818 [(set_attr "type" "mtcr")])
13820 (define_insn "*mtcrfsi"
13821 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13822 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13823 (match_operand 2 "immediate_operand" "n")]
13824 UNSPEC_MOVESI_TO_CR))]
13825 "GET_CODE (operands[0]) == REG
13826 && CR_REGNO_P (REGNO (operands[0]))
13827 && GET_CODE (operands[2]) == CONST_INT
13828 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13829 "mtcrf %R0,%1"
13830 [(set_attr "type" "mtcr")])
13832 ; The load-multiple instructions have similar properties.
13833 ; Note that "load_multiple" is a name known to the machine-independent
13834 ; code that actually corresponds to the PowerPC load-string.
13836 (define_insn "*lmw"
13837 [(match_parallel 0 "lmw_operation"
13838 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13839 (match_operand:SI 2 "memory_operand" "m"))])]
13840 "TARGET_MULTIPLE"
13841 "lmw %1,%2"
13842 [(set_attr "type" "load")
13843 (set_attr "update" "yes")
13844 (set_attr "indexed" "yes")
13845 (set_attr "cell_micro" "always")])
13847 (define_insn "*return_internal_<mode>"
13848 [(simple_return)
13849 (use (match_operand:P 0 "register_operand" "lc"))]
13850 ""
13851 "b%T0"
13852 [(set_attr "type" "jmpreg")])
13854 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13855 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13857 ; The following comment applies to:
13858 ; save_gpregs_*
13859 ; save_fpregs_*
13860 ; restore_gpregs*
13861 ; return_and_restore_gpregs*
13862 ; return_and_restore_fpregs*
13863 ; return_and_restore_fpregs_aix*
13864 ;
13865 ; The out-of-line save / restore functions expects one input argument.
13866 ; Since those are not standard call_insn's, we must avoid using
13867 ; MATCH_OPERAND for that argument. That way the register rename
13868 ; optimization will not try to rename this register.
13869 ; Each pattern is repeated for each possible register number used in
13870 ; various ABIs (r11, r1, and for some functions r12)
13872 (define_insn "*restore_gpregs_<mode>_r11"
13873 [(match_parallel 0 "any_parallel_operand"
13874 [(clobber (match_operand:P 1 "register_operand" "=l"))
13875 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13876 (use (reg:P 11))
13877 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13878 (match_operand:P 4 "memory_operand" "m"))])]
13879 ""
13880 "bl %2"
13881 [(set_attr "type" "branch")
13882 (set_attr "length" "4")])
13884 (define_insn "*restore_gpregs_<mode>_r12"
13885 [(match_parallel 0 "any_parallel_operand"
13886 [(clobber (match_operand:P 1 "register_operand" "=l"))
13887 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13888 (use (reg:P 12))
13889 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13890 (match_operand:P 4 "memory_operand" "m"))])]
13891 ""
13892 "bl %2"
13893 [(set_attr "type" "branch")
13894 (set_attr "length" "4")])
13896 (define_insn "*restore_gpregs_<mode>_r1"
13897 [(match_parallel 0 "any_parallel_operand"
13898 [(clobber (match_operand:P 1 "register_operand" "=l"))
13899 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13900 (use (reg:P 1))
13901 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13902 (match_operand:P 4 "memory_operand" "m"))])]
13903 ""
13904 "bl %2"
13905 [(set_attr "type" "branch")
13906 (set_attr "length" "4")])
13908 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13909 [(match_parallel 0 "any_parallel_operand"
13910 [(return)
13911 (clobber (match_operand:P 1 "register_operand" "=l"))
13912 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13913 (use (reg:P 11))
13914 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13915 (match_operand:P 4 "memory_operand" "m"))])]
13916 ""
13917 "b %2"
13918 [(set_attr "type" "branch")
13919 (set_attr "length" "4")])
13921 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13922 [(match_parallel 0 "any_parallel_operand"
13923 [(return)
13924 (clobber (match_operand:P 1 "register_operand" "=l"))
13925 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13926 (use (reg:P 12))
13927 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13928 (match_operand:P 4 "memory_operand" "m"))])]
13929 ""
13930 "b %2"
13931 [(set_attr "type" "branch")
13932 (set_attr "length" "4")])
13934 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13935 [(match_parallel 0 "any_parallel_operand"
13936 [(return)
13937 (clobber (match_operand:P 1 "register_operand" "=l"))
13938 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13939 (use (reg:P 1))
13940 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13941 (match_operand:P 4 "memory_operand" "m"))])]
13942 ""
13943 "b %2"
13944 [(set_attr "type" "branch")
13945 (set_attr "length" "4")])
13947 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13948 [(match_parallel 0 "any_parallel_operand"
13949 [(return)
13950 (clobber (match_operand:P 1 "register_operand" "=l"))
13951 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13952 (use (reg:P 11))
13953 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13954 (match_operand:DF 4 "memory_operand" "m"))])]
13955 ""
13956 "b %2"
13957 [(set_attr "type" "branch")
13958 (set_attr "length" "4")])
13960 (define_insn "*return_and_restore_fpregs_<mode>_r12"
13961 [(match_parallel 0 "any_parallel_operand"
13962 [(return)
13963 (clobber (match_operand:P 1 "register_operand" "=l"))
13964 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13965 (use (reg:P 12))
13966 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13967 (match_operand:DF 4 "memory_operand" "m"))])]
13968 ""
13969 "b %2"
13970 [(set_attr "type" "branch")
13971 (set_attr "length" "4")])
13973 (define_insn "*return_and_restore_fpregs_<mode>_r1"
13974 [(match_parallel 0 "any_parallel_operand"
13975 [(return)
13976 (clobber (match_operand:P 1 "register_operand" "=l"))
13977 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13978 (use (reg:P 1))
13979 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13980 (match_operand:DF 4 "memory_operand" "m"))])]
13981 ""
13982 "b %2"
13983 [(set_attr "type" "branch")
13984 (set_attr "length" "4")])
13986 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
13987 [(match_parallel 0 "any_parallel_operand"
13988 [(return)
13989 (use (match_operand:P 1 "register_operand" "l"))
13990 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13991 (use (reg:P 11))
13992 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13993 (match_operand:DF 4 "memory_operand" "m"))])]
13994 ""
13995 "b %2"
13996 [(set_attr "type" "branch")
13997 (set_attr "length" "4")])
13999 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
14000 [(match_parallel 0 "any_parallel_operand"
14001 [(return)
14002 (use (match_operand:P 1 "register_operand" "l"))
14003 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14004 (use (reg:P 1))
14005 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14006 (match_operand:DF 4 "memory_operand" "m"))])]
14007 ""
14008 "b %2"
14009 [(set_attr "type" "branch")
14010 (set_attr "length" "4")])
14012 ; This is used in compiling the unwind routines.
14013 (define_expand "eh_return"
14014 [(use (match_operand 0 "general_operand" ""))]
14015 ""
14016 "
14017 {
14018 if (TARGET_32BIT)
14019 emit_insn (gen_eh_set_lr_si (operands[0]));
14020 else
14021 emit_insn (gen_eh_set_lr_di (operands[0]));
14022 DONE;
14023 }")
14025 ; We can't expand this before we know where the link register is stored.
14026 (define_insn "eh_set_lr_<mode>"
14027 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14028 UNSPECV_EH_RR)
14029 (clobber (match_scratch:P 1 "=&b"))]
14030 ""
14031 "#")
14033 (define_split
14034 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14035 (clobber (match_scratch 1 ""))]
14036 "reload_completed"
14037 [(const_int 0)]
14038 "
14039 {
14040 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14041 DONE;
14042 }")
14044 (define_insn "prefetch"
14045 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14046 (match_operand:SI 1 "const_int_operand" "n")
14047 (match_operand:SI 2 "const_int_operand" "n"))]
14048 ""
14049 "*
14050 {
14051 if (GET_CODE (operands[0]) == REG)
14052 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14053 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14054 }"
14055 [(set_attr "type" "load")])
14056 \f
14057 (define_insn "bpermd_<mode>"
14058 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14059 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14060 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14061 "TARGET_POPCNTD"
14062 "bpermd %0,%1,%2"
14063 [(set_attr "type" "popcnt")])
14065 \f
14066 ;; Builtin fma support. Handle
14067 ;; Note that the conditions for expansion are in the FMA_F iterator.
14069 (define_expand "fma<mode>4"
14070 [(set (match_operand:FMA_F 0 "register_operand" "")
14071 (fma:FMA_F
14072 (match_operand:FMA_F 1 "register_operand" "")
14073 (match_operand:FMA_F 2 "register_operand" "")
14074 (match_operand:FMA_F 3 "register_operand" "")))]
14075 ""
14076 "")
14078 (define_insn "*fma<mode>4_fpr"
14079 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14080 (fma:SFDF
14081 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
14082 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14083 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
14084 "TARGET_<MODE>_FPR"
14085 "@
14086 fmadd<Ftrad> %0,%1,%2,%3
14087 xsmadda<Fvsx> %x0,%x1,%x2
14088 xsmaddm<Fvsx> %x0,%x1,%x3"
14089 [(set_attr "type" "fp")
14090 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14092 ; Altivec only has fma and nfms.
14093 (define_expand "fms<mode>4"
14094 [(set (match_operand:FMA_F 0 "register_operand" "")
14095 (fma:FMA_F
14096 (match_operand:FMA_F 1 "register_operand" "")
14097 (match_operand:FMA_F 2 "register_operand" "")
14098 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14099 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14100 "")
14102 (define_insn "*fms<mode>4_fpr"
14103 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14104 (fma:SFDF
14105 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14106 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14107 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14108 "TARGET_<MODE>_FPR"
14109 "@
14110 fmsub<Ftrad> %0,%1,%2,%3
14111 xsmsuba<Fvsx> %x0,%x1,%x2
14112 xsmsubm<Fvsx> %x0,%x1,%x3"
14113 [(set_attr "type" "fp")
14114 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14116 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14117 (define_expand "fnma<mode>4"
14118 [(set (match_operand:FMA_F 0 "register_operand" "")
14119 (neg:FMA_F
14120 (fma:FMA_F
14121 (match_operand:FMA_F 1 "register_operand" "")
14122 (match_operand:FMA_F 2 "register_operand" "")
14123 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14124 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14125 "")
14127 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14128 (define_expand "fnms<mode>4"
14129 [(set (match_operand:FMA_F 0 "register_operand" "")
14130 (neg:FMA_F
14131 (fma:FMA_F
14132 (match_operand:FMA_F 1 "register_operand" "")
14133 (match_operand:FMA_F 2 "register_operand" "")
14134 (match_operand:FMA_F 3 "register_operand" ""))))]
14135 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14136 "")
14138 ; Not an official optab name, but used from builtins.
14139 (define_expand "nfma<mode>4"
14140 [(set (match_operand:FMA_F 0 "register_operand" "")
14141 (neg:FMA_F
14142 (fma:FMA_F
14143 (match_operand:FMA_F 1 "register_operand" "")
14144 (match_operand:FMA_F 2 "register_operand" "")
14145 (match_operand:FMA_F 3 "register_operand" ""))))]
14146 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14147 "")
14149 (define_insn "*nfma<mode>4_fpr"
14150 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14151 (neg:SFDF
14152 (fma:SFDF
14153 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14154 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14155 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14156 "TARGET_<MODE>_FPR"
14157 "@
14158 fnmadd<Ftrad> %0,%1,%2,%3
14159 xsnmadda<Fvsx> %x0,%x1,%x2
14160 xsnmaddm<Fvsx> %x0,%x1,%x3"
14161 [(set_attr "type" "fp")
14162 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14164 ; Not an official optab name, but used from builtins.
14165 (define_expand "nfms<mode>4"
14166 [(set (match_operand:FMA_F 0 "register_operand" "")
14167 (neg:FMA_F
14168 (fma:FMA_F
14169 (match_operand:FMA_F 1 "register_operand" "")
14170 (match_operand:FMA_F 2 "register_operand" "")
14171 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14172 ""
14173 "")
14175 (define_insn "*nfmssf4_fpr"
14176 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14177 (neg:SFDF
14178 (fma:SFDF
14179 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14180 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14181 (neg:SFDF
14182 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
14183 "TARGET_<MODE>_FPR"
14184 "@
14185 fnmsub<Ftrad> %0,%1,%2,%3
14186 xsnmsuba<Fvsx> %x0,%x1,%x2
14187 xsnmsubm<Fvsx> %x0,%x1,%x3"
14188 [(set_attr "type" "fp")
14189 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14191 \f
14192 (define_expand "rs6000_get_timebase"
14193 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
14194 ""
14195 {
14196 if (TARGET_POWERPC64)
14197 emit_insn (gen_rs6000_mftb_di (operands[0]));
14198 else
14199 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
14200 DONE;
14201 })
14203 (define_insn "rs6000_get_timebase_ppc32"
14204 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
14205 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
14206 (clobber (match_scratch:SI 1 "=r"))
14207 (clobber (match_scratch:CC 2 "=y"))]
14208 "!TARGET_POWERPC64"
14209 {
14210 if (WORDS_BIG_ENDIAN)
14211 if (TARGET_MFCRF)
14212 {
14213 return "mfspr %0,269\;"
14214 "mfspr %L0,268\;"
14215 "mfspr %1,269\;"
14216 "cmpw %2,%0,%1\;"
14217 "bne- %2,$-16";
14218 }
14219 else
14220 {
14221 return "mftbu %0\;"
14222 "mftb %L0\;"
14223 "mftbu %1\;"
14224 "cmpw %2,%0,%1\;"
14225 "bne- %2,$-16";
14226 }
14227 else
14228 if (TARGET_MFCRF)
14229 {
14230 return "mfspr %L0,269\;"
14231 "mfspr %0,268\;"
14232 "mfspr %1,269\;"
14233 "cmpw %2,%L0,%1\;"
14234 "bne- %2,$-16";
14235 }
14236 else
14237 {
14238 return "mftbu %L0\;"
14239 "mftb %0\;"
14240 "mftbu %1\;"
14241 "cmpw %2,%L0,%1\;"
14242 "bne- %2,$-16";
14243 }
14244 }
14245 [(set_attr "length" "20")])
14247 (define_insn "rs6000_mftb_<mode>"
14248 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
14249 (unspec_volatile:GPR [(const_int 0)] UNSPECV_MFTB))]
14250 ""
14251 {
14252 if (TARGET_MFCRF)
14253 return "mfspr %0,268";
14254 else
14255 return "mftb %0";
14256 })
14258 \f
14259 (define_insn "rs6000_mffs"
14260 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
14261 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
14262 "TARGET_HARD_FLOAT && TARGET_FPRS"
14263 "mffs %0")
14265 (define_insn "rs6000_mtfsf"
14266 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
14267 (match_operand:DF 1 "gpc_reg_operand" "d")]
14268 UNSPECV_MTFSF)]
14269 "TARGET_HARD_FLOAT && TARGET_FPRS"
14270 "mtfsf %0,%1")
14272 \f
14273 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
14274 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
14275 ;; register that is being loaded. The fused ops must be physically adjacent.
14277 ;; Find cases where the addis that feeds into a load instruction is either used
14278 ;; once or is the same as the target register, and replace it with the fusion
14279 ;; insn
14281 (define_peephole2
14282 [(set (match_operand:P 0 "base_reg_operand" "")
14283 (match_operand:P 1 "fusion_gpr_addis" ""))
14284 (set (match_operand:INT1 2 "base_reg_operand" "")
14285 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
14286 "TARGET_P8_FUSION
14287 && fusion_gpr_load_p (operands[0], operands[1], operands[2],
14288 operands[3])"
14289 [(const_int 0)]
14290 {
14291 expand_fusion_gpr_load (operands);
14292 DONE;
14293 })
14295 ;; Fusion insn, created by the define_peephole2 above (and eventually by
14296 ;; reload)
14298 (define_insn "fusion_gpr_load_<mode>"
14299 [(set (match_operand:INT1 0 "base_reg_operand" "=&b")
14300 (unspec:INT1 [(match_operand:INT1 1 "fusion_gpr_mem_combo" "")]
14301 UNSPEC_FUSION_GPR))]
14302 "TARGET_P8_FUSION"
14303 {
14304 return emit_fusion_gpr_load (operands[0], operands[1]);
14305 }
14306 [(set_attr "type" "load")
14307 (set_attr "length" "8")])
14309 \f
14310 ;; Miscellaneous ISA 2.06 (power7) instructions
14311 (define_insn "addg6s"
14312 [(set (match_operand:SI 0 "register_operand" "=r")
14313 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
14314 (match_operand:SI 2 "register_operand" "r")]
14315 UNSPEC_ADDG6S))]
14316 "TARGET_POPCNTD"
14317 "addg6s %0,%1,%2"
14318 [(set_attr "type" "integer")
14319 (set_attr "length" "4")])
14321 (define_insn "cdtbcd"
14322 [(set (match_operand:SI 0 "register_operand" "=r")
14323 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14324 UNSPEC_CDTBCD))]
14325 "TARGET_POPCNTD"
14326 "cdtbcd %0,%1"
14327 [(set_attr "type" "integer")
14328 (set_attr "length" "4")])
14330 (define_insn "cbcdtd"
14331 [(set (match_operand:SI 0 "register_operand" "=r")
14332 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
14333 UNSPEC_CBCDTD))]
14334 "TARGET_POPCNTD"
14335 "cbcdtd %0,%1"
14336 [(set_attr "type" "integer")
14337 (set_attr "length" "4")])
14339 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
14340 UNSPEC_DIVEO
14341 UNSPEC_DIVEU
14342 UNSPEC_DIVEUO])
14344 (define_int_attr div_extend [(UNSPEC_DIVE "e")
14345 (UNSPEC_DIVEO "eo")
14346 (UNSPEC_DIVEU "eu")
14347 (UNSPEC_DIVEUO "euo")])
14349 (define_insn "div<div_extend>_<mode>"
14350 [(set (match_operand:GPR 0 "register_operand" "=r")
14351 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
14352 (match_operand:GPR 2 "register_operand" "r")]
14353 UNSPEC_DIV_EXTEND))]
14354 "TARGET_POPCNTD"
14355 "div<wd><div_extend> %0,%1,%2"
14356 [(set_attr "type" "div")
14357 (set_attr "size" "<bits>")])
14359 \f
14360 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
14362 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
14363 (define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
14365 (define_expand "unpack<mode>"
14366 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
14367 (unspec:<FP128_64>
14368 [(match_operand:FMOVE128 1 "register_operand" "")
14369 (match_operand:QI 2 "const_0_to_1_operand" "")]
14370 UNSPEC_UNPACK_128BIT))]
14371 ""
14372 "")
14374 (define_insn_and_split "unpack<mode>_dm"
14375 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
14376 (unspec:<FP128_64>
14377 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
14378 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
14379 UNSPEC_UNPACK_128BIT))]
14380 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
14381 "#"
14382 "&& reload_completed"
14383 [(set (match_dup 0) (match_dup 3))]
14384 {
14385 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14387 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14388 {
14389 emit_note (NOTE_INSN_DELETED);
14390 DONE;
14391 }
14393 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14394 }
14395 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
14396 (set_attr "length" "4")])
14398 (define_insn_and_split "unpack<mode>_nodm"
14399 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
14400 (unspec:<FP128_64>
14401 [(match_operand:FMOVE128 1 "register_operand" "d,d")
14402 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
14403 UNSPEC_UNPACK_128BIT))]
14404 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
14405 "#"
14406 "&& reload_completed"
14407 [(set (match_dup 0) (match_dup 3))]
14408 {
14409 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
14411 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
14412 {
14413 emit_note (NOTE_INSN_DELETED);
14414 DONE;
14415 }
14417 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14418 }
14419 [(set_attr "type" "fp,fpstore")
14420 (set_attr "length" "4")])
14422 (define_insn_and_split "pack<mode>"
14423 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
14424 (unspec:FMOVE128
14425 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
14426 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
14427 UNSPEC_PACK_128BIT))]
14428 ""
14429 "@
14430 fmr %L0,%2
14431 #"
14432 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
14433 [(set (match_dup 3) (match_dup 1))
14434 (set (match_dup 4) (match_dup 2))]
14435 {
14436 unsigned dest_hi = REGNO (operands[0]);
14437 unsigned dest_lo = dest_hi + 1;
14439 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
14440 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
14442 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
14443 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
14444 }
14445 [(set_attr "type" "fp,fp")
14446 (set_attr "length" "4,8")])
14448 (define_insn "unpackv1ti"
14449 [(set (match_operand:DI 0 "register_operand" "=d,d")
14450 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
14451 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
14452 UNSPEC_UNPACK_128BIT))]
14453 "TARGET_VSX"
14454 {
14455 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
14456 return ASM_COMMENT_START " xxpermdi to same register";
14458 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
14459 return "xxpermdi %x0,%x1,%x1,%3";
14460 }
14461 [(set_attr "type" "vecperm")
14462 (set_attr "length" "4")])
14464 (define_insn "packv1ti"
14465 [(set (match_operand:V1TI 0 "register_operand" "=wa")
14466 (unspec:V1TI
14467 [(match_operand:DI 1 "register_operand" "d")
14468 (match_operand:DI 2 "register_operand" "d")]
14469 UNSPEC_PACK_128BIT))]
14470 "TARGET_VSX"
14471 "xxpermdi %x0,%x1,%x2,0"
14472 [(set_attr "type" "vecperm")
14473 (set_attr "length" "4")])
14475 \f
14477 (include "sync.md")
14478 (include "vector.md")
14479 (include "vsx.md")
14480 (include "altivec.md")
14481 (include "spe.md")
14482 (include "dfp.md")
14483 (include "paired.md")
14484 (include "crypto.md")
14485 (include "htm.md")