gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987-2014 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 /* This module is essentially the "combiner" phase of the U. of Arizona
  21    Portable Optimizer, but redone to work on our list-structured
  22    representation for RTL instead of their string representation.
  23
  24    The LOG_LINKS of each insn identify the most recent assignment
  25    to each REG used in the insn.  It is a list of previous insns,
  26    each of which contains a SET for a REG that is used in this insn
  27    and not used or set in between.  LOG_LINKs never cross basic blocks.
  28    They were set up by the preceding pass (lifetime analysis).
  29
  30    We try to combine each pair of insns joined by a logical link.
  31    We also try to combine triplets of insns A, B and C when C has
  32    a link back to B and B has a link back to A.  Likewise for a
  33    small number of quadruplets of insns A, B, C and D for which
  34    there's high likelihood of of success.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "stor-layout.h"
  85 #include "tm_p.h"
  86 #include "flags.h"
  87 #include "regs.h"
  88 #include "hard-reg-set.h"
  89 #include "basic-block.h"
  90 #include "insn-config.h"
  91 #include "function.h"
  92 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  93 #include "expr.h"
  94 #include "insn-attr.h"
  95 #include "recog.h"
  96 #include "diagnostic-core.h"
  97 #include "target.h"
  98 #include "optabs.h"
  99 #include "insn-codes.h"
 100 #include "rtlhooks-def.h"
 101 #include "params.h"
 102 #include "tree-pass.h"
 103 #include "df.h"
 104 #include "valtrack.h"
 105 #include "cgraph.h"
 106 #include "obstack.h"
 107
 108 /* Number of attempts to combine instructions in this function.  */
 109
 110 static int combine_attempts;
 111
 112 /* Number of attempts that got as far as substitution in this function.  */
 113
 114 static int combine_merges;
 115
 116 /* Number of instructions combined with added SETs in this function.  */
 117
 118 static int combine_extras;
 119
 120 /* Number of instructions combined in this function.  */
 121
 122 static int combine_successes;
 123
 124 /* Totals over entire compilation.  */
 125
 126 static int total_attempts, total_merges, total_extras, total_successes;
 127
 128 /* combine_instructions may try to replace the right hand side of the
 129    second instruction with the value of an associated REG_EQUAL note
 130    before throwing it at try_combine.  That is problematic when there
 131    is a REG_DEAD note for a register used in the old right hand side
 132    and can cause distribute_notes to do wrong things.  This is the
 133    second instruction if it has been so modified, null otherwise.  */
 134
 135 static rtx i2mod;
 136
 137 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 138
 139 static rtx i2mod_old_rhs;
 140
 141 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 142
 143 static rtx i2mod_new_rhs;
 144 \f
 145 typedef struct reg_stat_struct {
 146   /* Record last point of death of (hard or pseudo) register n.  */
 147   rtx                           last_death;
 148
 149   /* Record last point of modification of (hard or pseudo) register n.  */
 150   rtx                           last_set;
 151
 152   /* The next group of fields allows the recording of the last value assigned
 153      to (hard or pseudo) register n.  We use this information to see if an
 154      operation being processed is redundant given a prior operation performed
 155      on the register.  For example, an `and' with a constant is redundant if
 156      all the zero bits are already known to be turned off.
 157
 158      We use an approach similar to that used by cse, but change it in the
 159      following ways:
 160
 161      (1) We do not want to reinitialize at each label.
 162      (2) It is useful, but not critical, to know the actual value assigned
 163          to a register.  Often just its form is helpful.
 164
 165      Therefore, we maintain the following fields:
 166
 167      last_set_value             the last value assigned
 168      last_set_label             records the value of label_tick when the
 169                                 register was assigned
 170      last_set_table_tick        records the value of label_tick when a
 171                                 value using the register is assigned
 172      last_set_invalid           set to nonzero when it is not valid
 173                                 to use the value of this register in some
 174                                 register's value
 175
 176      To understand the usage of these tables, it is important to understand
 177      the distinction between the value in last_set_value being valid and
 178      the register being validly contained in some other expression in the
 179      table.
 180
 181      (The next two parameters are out of date).
 182
 183      reg_stat[i].last_set_value is valid if it is nonzero, and either
 184      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 185
 186      Register I may validly appear in any expression returned for the value
 187      of another register if reg_n_sets[i] is 1.  It may also appear in the
 188      value for register J if reg_stat[j].last_set_invalid is zero, or
 189      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 190
 191      If an expression is found in the table containing a register which may
 192      not validly appear in an expression, the register is replaced by
 193      something that won't match, (clobber (const_int 0)).  */
 194
 195   /* Record last value assigned to (hard or pseudo) register n.  */
 196
 197   rtx                           last_set_value;
 198
 199   /* Record the value of label_tick when an expression involving register n
 200      is placed in last_set_value.  */
 201
 202   int                           last_set_table_tick;
 203
 204   /* Record the value of label_tick when the value for register n is placed in
 205      last_set_value.  */
 206
 207   int                           last_set_label;
 208
 209   /* These fields are maintained in parallel with last_set_value and are
 210      used to store the mode in which the register was last set, the bits
 211      that were known to be zero when it was last set, and the number of
 212      sign bits copies it was known to have when it was last set.  */
 213
 214   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 215   char                          last_set_sign_bit_copies;
 216   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 217
 218   /* Set nonzero if references to register n in expressions should not be
 219      used.  last_set_invalid is set nonzero when this register is being
 220      assigned to and last_set_table_tick == label_tick.  */
 221
 222   char                          last_set_invalid;
 223
 224   /* Some registers that are set more than once and used in more than one
 225      basic block are nevertheless always set in similar ways.  For example,
 226      a QImode register may be loaded from memory in two places on a machine
 227      where byte loads zero extend.
 228
 229      We record in the following fields if a register has some leading bits
 230      that are always equal to the sign bit, and what we know about the
 231      nonzero bits of a register, specifically which bits are known to be
 232      zero.
 233
 234      If an entry is zero, it means that we don't know anything special.  */
 235
 236   unsigned char                 sign_bit_copies;
 237
 238   unsigned HOST_WIDE_INT        nonzero_bits;
 239
 240   /* Record the value of the label_tick when the last truncation
 241      happened.  The field truncated_to_mode is only valid if
 242      truncation_label == label_tick.  */
 243
 244   int                           truncation_label;
 245
 246   /* Record the last truncation seen for this register.  If truncation
 247      is not a nop to this mode we might be able to save an explicit
 248      truncation if we know that value already contains a truncated
 249      value.  */
 250
 251   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 252 } reg_stat_type;
 253
 254
 255 static vec<reg_stat_type> reg_stat;
 256
 257 /* Record the luid of the last insn that invalidated memory
 258    (anything that writes memory, and subroutine calls, but not pushes).  */
 259
 260 static int mem_last_set;
 261
 262 /* Record the luid of the last CALL_INSN
 263    so we can tell whether a potential combination crosses any calls.  */
 264
 265 static int last_call_luid;
 266
 267 /* When `subst' is called, this is the insn that is being modified
 268    (by combining in a previous insn).  The PATTERN of this insn
 269    is still the old pattern partially modified and it should not be
 270    looked at, but this may be used to examine the successors of the insn
 271    to judge whether a simplification is valid.  */
 272
 273 static rtx subst_insn;
 274
 275 /* This is the lowest LUID that `subst' is currently dealing with.
 276    get_last_value will not return a value if the register was set at or
 277    after this LUID.  If not for this mechanism, we could get confused if
 278    I2 or I1 in try_combine were an insn that used the old value of a register
 279    to obtain a new value.  In that case, we might erroneously get the
 280    new value of the register when we wanted the old one.  */
 281
 282 static int subst_low_luid;
 283
 284 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 285    must consider all these registers to be always live.  */
 286
 287 static HARD_REG_SET newpat_used_regs;
 288
 289 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 290    insn is the earlier than I2 or I3, combine should rescan starting at
 291    that location.  */
 292
 293 static rtx added_links_insn;
 294
 295 /* Basic block in which we are performing combines.  */
 296 static basic_block this_basic_block;
 297 static bool optimize_this_for_speed_p;
 298
 299 \f
 300 /* Length of the currently allocated uid_insn_cost array.  */
 301
 302 static int max_uid_known;
 303
 304 /* The following array records the insn_rtx_cost for every insn
 305    in the instruction stream.  */
 306
 307 static int *uid_insn_cost;
 308
 309 /* The following array records the LOG_LINKS for every insn in the
 310    instruction stream as struct insn_link pointers.  */
 311
 312 struct insn_link {
 313   rtx insn;
 314   struct insn_link *next;
 315 };
 316
 317 static struct insn_link **uid_log_links;
 318
 319 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 320 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 321
 322 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 323   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 324
 325 /* Links for LOG_LINKS are allocated from this obstack.  */
 326
 327 static struct obstack insn_link_obstack;
 328
 329 /* Allocate a link.  */
 330
 331 static inline struct insn_link *
 332 alloc_insn_link (rtx insn, struct insn_link *next)
 333 {
 334   struct insn_link *l
 335     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 336                                           sizeof (struct insn_link));
 337   l->insn = insn;
 338   l->next = next;
 339   return l;
 340 }
 341
 342 /* Incremented for each basic block.  */
 343
 344 static int label_tick;
 345
 346 /* Reset to label_tick for each extended basic block in scanning order.  */
 347
 348 static int label_tick_ebb_start;
 349
 350 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 351    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 352
 353 static enum machine_mode nonzero_bits_mode;
 354
 355 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 356    be safely used.  It is zero while computing them and after combine has
 357    completed.  This former test prevents propagating values based on
 358    previously set values, which can be incorrect if a variable is modified
 359    in a loop.  */
 360
 361 static int nonzero_sign_valid;
 362
 363 \f
 364 /* Record one modification to rtl structure
 365    to be undone by storing old_contents into *where.  */
 366
 367 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 368
 369 struct undo
 370 {
 371   struct undo *next;
 372   enum undo_kind kind;
 373   union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
 374   union { rtx *r; int *i; struct insn_link **l; } where;
 375 };
 376
 377 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 378    num_undo says how many are currently recorded.
 379
 380    other_insn is nonzero if we have modified some other insn in the process
 381    of working on subst_insn.  It must be verified too.  */
 382
 383 struct undobuf
 384 {
 385   struct undo *undos;
 386   struct undo *frees;
 387   rtx other_insn;
 388 };
 389
 390 static struct undobuf undobuf;
 391
 392 /* Number of times the pseudo being substituted for
 393    was found and replaced.  */
 394
 395 static int n_occurrences;
 396
 397 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 398                                          enum machine_mode,
 399                                          unsigned HOST_WIDE_INT,
 400                                          unsigned HOST_WIDE_INT *);
 401 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 402                                                 enum machine_mode,
 403                                                 unsigned int, unsigned int *);
 404 static void do_SUBST (rtx *, rtx);
 405 static void do_SUBST_INT (int *, int);
 406 static void init_reg_last (void);
 407 static void setup_incoming_promotions (rtx);
 408 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 409 static int cant_combine_insn_p (rtx);
 410 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
 411 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
 412 static int contains_muldiv (rtx);
 413 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
 414 static void undo_all (void);
 415 static void undo_commit (void);
 416 static rtx *find_split_point (rtx *, rtx, bool);
 417 static rtx subst (rtx, rtx, rtx, int, int, int);
 418 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
 419 static rtx simplify_if_then_else (rtx);
 420 static rtx simplify_set (rtx);
 421 static rtx simplify_logical (rtx);
 422 static rtx expand_compound_operation (rtx);
 423 static const_rtx expand_field_assignment (const_rtx);
 424 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 425                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 426 static rtx extract_left_shift (rtx, int);
 427 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 428                               unsigned HOST_WIDE_INT *);
 429 static rtx canon_reg_for_combine (rtx, rtx);
 430 static rtx force_to_mode (rtx, enum machine_mode,
 431                           unsigned HOST_WIDE_INT, int);
 432 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 433 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 434 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 435 static rtx make_field_assignment (rtx);
 436 static rtx apply_distributive_law (rtx);
 437 static rtx distribute_and_simplify_rtx (rtx, int);
 438 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 439                                      unsigned HOST_WIDE_INT);
 440 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 441                                    unsigned HOST_WIDE_INT);
 442 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 443                             HOST_WIDE_INT, enum machine_mode, int *);
 444 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 445 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 446                                  int);
 447 static int recog_for_combine (rtx *, rtx, rtx *);
 448 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 449 static enum rtx_code simplify_compare_const (enum rtx_code, enum machine_mode,
 450                                              rtx, rtx *);
 451 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 452 static void update_table_tick (rtx);
 453 static void record_value_for_reg (rtx, rtx, rtx);
 454 static void check_promoted_subreg (rtx, rtx);
 455 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 456 static void record_dead_and_set_regs (rtx);
 457 static int get_last_value_validate (rtx *, rtx, int, int);
 458 static rtx get_last_value (const_rtx);
 459 static int use_crosses_set_p (const_rtx, int);
 460 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 461 static int reg_dead_at_p (rtx, rtx);
 462 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 463 static int reg_bitfield_target_p (rtx, rtx);
 464 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
 465 static void distribute_links (struct insn_link *);
 466 static void mark_used_regs_combine (rtx);
 467 static void record_promoted_value (rtx, rtx);
 468 static int unmentioned_reg_p_1 (rtx *, void *);
 469 static bool unmentioned_reg_p (rtx, rtx);
 470 static int record_truncated_value (rtx *, void *);
 471 static void record_truncated_values (rtx *, void *);
 472 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 473 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 474 \f
 475
 476 /* It is not safe to use ordinary gen_lowpart in combine.
 477    See comments in gen_lowpart_for_combine.  */
 478 #undef RTL_HOOKS_GEN_LOWPART
 479 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 480
 481 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 482 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 483 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 484
 485 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 486 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 487
 488 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 489 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 490
 491 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 492 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 493
 494 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 495
 496 \f
 497 /* Convenience wrapper for the canonicalize_comparison target hook.
 498    Target hooks cannot use enum rtx_code.  */
 499 static inline void
 500 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
 501                                 bool op0_preserve_value)
 502 {
 503   int code_int = (int)*code;
 504   targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
 505   *code = (enum rtx_code)code_int;
 506 }
 507
 508 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 509    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 510    This is a wrapper around split_insns which ensures that the
 511    reg_stat vector is made larger if the splitter creates a new
 512    register.  */
 513
 514 static rtx
 515 combine_split_insns (rtx pattern, rtx insn)
 516 {
 517   rtx ret;
 518   unsigned int nregs;
 519
 520   ret = split_insns (pattern, insn);
 521   nregs = max_reg_num ();
 522   if (nregs > reg_stat.length ())
 523     reg_stat.safe_grow_cleared (nregs);
 524   return ret;
 525 }
 526
 527 /* This is used by find_single_use to locate an rtx in LOC that
 528    contains exactly one use of DEST, which is typically either a REG
 529    or CC0.  It returns a pointer to the innermost rtx expression
 530    containing DEST.  Appearances of DEST that are being used to
 531    totally replace it are not counted.  */
 532
 533 static rtx *
 534 find_single_use_1 (rtx dest, rtx *loc)
 535 {
 536   rtx x = *loc;
 537   enum rtx_code code = GET_CODE (x);
 538   rtx *result = NULL;
 539   rtx *this_result;
 540   int i;
 541   const char *fmt;
 542
 543   switch (code)
 544     {
 545     case CONST:
 546     case LABEL_REF:
 547     case SYMBOL_REF:
 548     CASE_CONST_ANY:
 549     case CLOBBER:
 550       return 0;
 551
 552     case SET:
 553       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 554          of a REG that occupies all of the REG, the insn uses DEST if
 555          it is mentioned in the destination or the source.  Otherwise, we
 556          need just check the source.  */
 557       if (GET_CODE (SET_DEST (x)) != CC0
 558           && GET_CODE (SET_DEST (x)) != PC
 559           && !REG_P (SET_DEST (x))
 560           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 561                 && REG_P (SUBREG_REG (SET_DEST (x)))
 562                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 563                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 564                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 565                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 566         break;
 567
 568       return find_single_use_1 (dest, &SET_SRC (x));
 569
 570     case MEM:
 571     case SUBREG:
 572       return find_single_use_1 (dest, &XEXP (x, 0));
 573
 574     default:
 575       break;
 576     }
 577
 578   /* If it wasn't one of the common cases above, check each expression and
 579      vector of this code.  Look for a unique usage of DEST.  */
 580
 581   fmt = GET_RTX_FORMAT (code);
 582   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 583     {
 584       if (fmt[i] == 'e')
 585         {
 586           if (dest == XEXP (x, i)
 587               || (REG_P (dest) && REG_P (XEXP (x, i))
 588                   && REGNO (dest) == REGNO (XEXP (x, i))))
 589             this_result = loc;
 590           else
 591             this_result = find_single_use_1 (dest, &XEXP (x, i));
 592
 593           if (result == NULL)
 594             result = this_result;
 595           else if (this_result)
 596             /* Duplicate usage.  */
 597             return NULL;
 598         }
 599       else if (fmt[i] == 'E')
 600         {
 601           int j;
 602
 603           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 604             {
 605               if (XVECEXP (x, i, j) == dest
 606                   || (REG_P (dest)
 607                       && REG_P (XVECEXP (x, i, j))
 608                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 609                 this_result = loc;
 610               else
 611                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 612
 613               if (result == NULL)
 614                 result = this_result;
 615               else if (this_result)
 616                 return NULL;
 617             }
 618         }
 619     }
 620
 621   return result;
 622 }
 623
 624
 625 /* See if DEST, produced in INSN, is used only a single time in the
 626    sequel.  If so, return a pointer to the innermost rtx expression in which
 627    it is used.
 628
 629    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 630
 631    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 632    care about REG_DEAD notes or LOG_LINKS.
 633
 634    Otherwise, we find the single use by finding an insn that has a
 635    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 636    only referenced once in that insn, we know that it must be the first
 637    and last insn referencing DEST.  */
 638
 639 static rtx *
 640 find_single_use (rtx dest, rtx insn, rtx *ploc)
 641 {
 642   basic_block bb;
 643   rtx next;
 644   rtx *result;
 645   struct insn_link *link;
 646
 647 #ifdef HAVE_cc0
 648   if (dest == cc0_rtx)
 649     {
 650       next = NEXT_INSN (insn);
 651       if (next == 0
 652           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 653         return 0;
 654
 655       result = find_single_use_1 (dest, &PATTERN (next));
 656       if (result && ploc)
 657         *ploc = next;
 658       return result;
 659     }
 660 #endif
 661
 662   if (!REG_P (dest))
 663     return 0;
 664
 665   bb = BLOCK_FOR_INSN (insn);
 666   for (next = NEXT_INSN (insn);
 667        next && BLOCK_FOR_INSN (next) == bb;
 668        next = NEXT_INSN (next))
 669     if (INSN_P (next) && dead_or_set_p (next, dest))
 670       {
 671         FOR_EACH_LOG_LINK (link, next)
 672           if (link->insn == insn)
 673             break;
 674
 675         if (link)
 676           {
 677             result = find_single_use_1 (dest, &PATTERN (next));
 678             if (ploc)
 679               *ploc = next;
 680             return result;
 681           }
 682       }
 683
 684   return 0;
 685 }
 686 \f
 687 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 688    insn.  The substitution can be undone by undo_all.  If INTO is already
 689    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 690    also call SUBST, we have to compute it before we put anything into
 691    the undo table.  */
 692
 693 static void
 694 do_SUBST (rtx *into, rtx newval)
 695 {
 696   struct undo *buf;
 697   rtx oldval = *into;
 698
 699   if (oldval == newval)
 700     return;
 701
 702   /* We'd like to catch as many invalid transformations here as
 703      possible.  Unfortunately, there are way too many mode changes
 704      that are perfectly valid, so we'd waste too much effort for
 705      little gain doing the checks here.  Focus on catching invalid
 706      transformations involving integer constants.  */
 707   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 708       && CONST_INT_P (newval))
 709     {
 710       /* Sanity check that we're replacing oldval with a CONST_INT
 711          that is a valid sign-extension for the original mode.  */
 712       gcc_assert (INTVAL (newval)
 713                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 714
 715       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 716          CONST_INT is not valid, because after the replacement, the
 717          original mode would be gone.  Unfortunately, we can't tell
 718          when do_SUBST is called to replace the operand thereof, so we
 719          perform this test on oldval instead, checking whether an
 720          invalid replacement took place before we got here.  */
 721       gcc_assert (!(GET_CODE (oldval) == SUBREG
 722                     && CONST_INT_P (SUBREG_REG (oldval))));
 723       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 724                     && CONST_INT_P (XEXP (oldval, 0))));
 725     }
 726
 727   if (undobuf.frees)
 728     buf = undobuf.frees, undobuf.frees = buf->next;
 729   else
 730     buf = XNEW (struct undo);
 731
 732   buf->kind = UNDO_RTX;
 733   buf->where.r = into;
 734   buf->old_contents.r = oldval;
 735   *into = newval;
 736
 737   buf->next = undobuf.undos, undobuf.undos = buf;
 738 }
 739
 740 #define SUBST(INTO, NEWVAL)     do_SUBST (&(INTO), (NEWVAL))
 741
 742 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 743    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 744    not safe.  */
 745
 746 static void
 747 do_SUBST_INT (int *into, int newval)
 748 {
 749   struct undo *buf;
 750   int oldval = *into;
 751
 752   if (oldval == newval)
 753     return;
 754
 755   if (undobuf.frees)
 756     buf = undobuf.frees, undobuf.frees = buf->next;
 757   else
 758     buf = XNEW (struct undo);
 759
 760   buf->kind = UNDO_INT;
 761   buf->where.i = into;
 762   buf->old_contents.i = oldval;
 763   *into = newval;
 764
 765   buf->next = undobuf.undos, undobuf.undos = buf;
 766 }
 767
 768 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT (&(INTO), (NEWVAL))
 769
 770 /* Similar to SUBST, but just substitute the mode.  This is used when
 771    changing the mode of a pseudo-register, so that any other
 772    references to the entry in the regno_reg_rtx array will change as
 773    well.  */
 774
 775 static void
 776 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 777 {
 778   struct undo *buf;
 779   enum machine_mode oldval = GET_MODE (*into);
 780
 781   if (oldval == newval)
 782     return;
 783
 784   if (undobuf.frees)
 785     buf = undobuf.frees, undobuf.frees = buf->next;
 786   else
 787     buf = XNEW (struct undo);
 788
 789   buf->kind = UNDO_MODE;
 790   buf->where.r = into;
 791   buf->old_contents.m = oldval;
 792   adjust_reg_mode (*into, newval);
 793
 794   buf->next = undobuf.undos, undobuf.undos = buf;
 795 }
 796
 797 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE (&(INTO), (NEWVAL))
 798
 799 #ifndef HAVE_cc0
 800 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 801
 802 static void
 803 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 804 {
 805   struct undo *buf;
 806   struct insn_link * oldval = *into;
 807
 808   if (oldval == newval)
 809     return;
 810
 811   if (undobuf.frees)
 812     buf = undobuf.frees, undobuf.frees = buf->next;
 813   else
 814     buf = XNEW (struct undo);
 815
 816   buf->kind = UNDO_LINKS;
 817   buf->where.l = into;
 818   buf->old_contents.l = oldval;
 819   *into = newval;
 820
 821   buf->next = undobuf.undos, undobuf.undos = buf;
 822 }
 823
 824 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 825 #endif
 826 \f
 827 /* Subroutine of try_combine.  Determine whether the replacement patterns
 828    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 829    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 830    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 831    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 832    of all the instructions can be estimated and the replacements are more
 833    expensive than the original sequence.  */
 834
 835 static bool
 836 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
 837                        rtx newi2pat, rtx newotherpat)
 838 {
 839   int i0_cost, i1_cost, i2_cost, i3_cost;
 840   int new_i2_cost, new_i3_cost;
 841   int old_cost, new_cost;
 842
 843   /* Lookup the original insn_rtx_costs.  */
 844   i2_cost = INSN_COST (i2);
 845   i3_cost = INSN_COST (i3);
 846
 847   if (i1)
 848     {
 849       i1_cost = INSN_COST (i1);
 850       if (i0)
 851         {
 852           i0_cost = INSN_COST (i0);
 853           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 854                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 855         }
 856       else
 857         {
 858           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 859                       ? i1_cost + i2_cost + i3_cost : 0);
 860           i0_cost = 0;
 861         }
 862     }
 863   else
 864     {
 865       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 866       i1_cost = i0_cost = 0;
 867     }
 868
 869   /* Calculate the replacement insn_rtx_costs.  */
 870   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 871   if (newi2pat)
 872     {
 873       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 874       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 875                  ? new_i2_cost + new_i3_cost : 0;
 876     }
 877   else
 878     {
 879       new_cost = new_i3_cost;
 880       new_i2_cost = 0;
 881     }
 882
 883   if (undobuf.other_insn)
 884     {
 885       int old_other_cost, new_other_cost;
 886
 887       old_other_cost = INSN_COST (undobuf.other_insn);
 888       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 889       if (old_other_cost > 0 && new_other_cost > 0)
 890         {
 891           old_cost += old_other_cost;
 892           new_cost += new_other_cost;
 893         }
 894       else
 895         old_cost = 0;
 896     }
 897
 898   /* Disallow this combination if both new_cost and old_cost are greater than
 899      zero, and new_cost is greater than old cost.  */
 900   if (old_cost > 0 && new_cost > old_cost)
 901     {
 902       if (dump_file)
 903         {
 904           if (i0)
 905             {
 906               fprintf (dump_file,
 907                        "rejecting combination of insns %d, %d, %d and %d\n",
 908                        INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
 909                        INSN_UID (i3));
 910               fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
 911                        i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
 912             }
 913           else if (i1)
 914             {
 915               fprintf (dump_file,
 916                        "rejecting combination of insns %d, %d and %d\n",
 917                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 918               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 919                        i1_cost, i2_cost, i3_cost, old_cost);
 920             }
 921           else
 922             {
 923               fprintf (dump_file,
 924                        "rejecting combination of insns %d and %d\n",
 925                        INSN_UID (i2), INSN_UID (i3));
 926               fprintf (dump_file, "original costs %d + %d = %d\n",
 927                        i2_cost, i3_cost, old_cost);
 928             }
 929
 930           if (newi2pat)
 931             {
 932               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 933                        new_i2_cost, new_i3_cost, new_cost);
 934             }
 935           else
 936             fprintf (dump_file, "replacement cost %d\n", new_cost);
 937         }
 938
 939       return false;
 940     }
 941
 942   /* Update the uid_insn_cost array with the replacement costs.  */
 943   INSN_COST (i2) = new_i2_cost;
 944   INSN_COST (i3) = new_i3_cost;
 945   if (i1)
 946     {
 947       INSN_COST (i1) = 0;
 948       if (i0)
 949         INSN_COST (i0) = 0;
 950     }
 951
 952   return true;
 953 }
 954
 955
 956 /* Delete any insns that copy a register to itself.  */
 957
 958 static void
 959 delete_noop_moves (void)
 960 {
 961   rtx insn, next;
 962   basic_block bb;
 963
 964   FOR_EACH_BB_FN (bb, cfun)
 965     {
 966       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 967         {
 968           next = NEXT_INSN (insn);
 969           if (INSN_P (insn) && noop_move_p (insn))
 970             {
 971               if (dump_file)
 972                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 973
 974               delete_insn_and_edges (insn);
 975             }
 976         }
 977     }
 978 }
 979
 980 \f
 981 /* Fill in log links field for all insns.  */
 982
 983 static void
 984 create_log_links (void)
 985 {
 986   basic_block bb;
 987   rtx *next_use, insn;
 988   df_ref def, use;
 989
 990   next_use = XCNEWVEC (rtx, max_reg_num ());
 991
 992   /* Pass through each block from the end, recording the uses of each
 993      register and establishing log links when def is encountered.
 994      Note that we do not clear next_use array in order to save time,
 995      so we have to test whether the use is in the same basic block as def.
 996
 997      There are a few cases below when we do not consider the definition or
 998      usage -- these are taken from original flow.c did. Don't ask me why it is
 999      done this way; I don't know and if it works, I don't want to know.  */
1000
1001   FOR_EACH_BB_FN (bb, cfun)
1002     {
1003       FOR_BB_INSNS_REVERSE (bb, insn)
1004         {
1005           if (!NONDEBUG_INSN_P (insn))
1006             continue;
1007
1008           /* Log links are created only once.  */
1009           gcc_assert (!LOG_LINKS (insn));
1010
1011           FOR_EACH_INSN_DEF (def, insn)
1012             {
1013               int regno = DF_REF_REGNO (def);
1014               rtx use_insn;
1015
1016               if (!next_use[regno])
1017                 continue;
1018
1019               /* Do not consider if it is pre/post modification in MEM.  */
1020               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1021                 continue;
1022
1023               /* Do not make the log link for frame pointer.  */
1024               if ((regno == FRAME_POINTER_REGNUM
1025                    && (! reload_completed || frame_pointer_needed))
1026 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1027                   || (regno == HARD_FRAME_POINTER_REGNUM
1028                       && (! reload_completed || frame_pointer_needed))
1029 #endif
1030 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1031                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1032 #endif
1033                   )
1034                 continue;
1035
1036               use_insn = next_use[regno];
1037               if (BLOCK_FOR_INSN (use_insn) == bb)
1038                 {
1039                   /* flow.c claimed:
1040
1041                      We don't build a LOG_LINK for hard registers contained
1042                      in ASM_OPERANDs.  If these registers get replaced,
1043                      we might wind up changing the semantics of the insn,
1044                      even if reload can make what appear to be valid
1045                      assignments later.  */
1046                   if (regno >= FIRST_PSEUDO_REGISTER
1047                       || asm_noperands (PATTERN (use_insn)) < 0)
1048                     {
1049                       /* Don't add duplicate links between instructions.  */
1050                       struct insn_link *links;
1051                       FOR_EACH_LOG_LINK (links, use_insn)
1052                         if (insn == links->insn)
1053                           break;
1054
1055                       if (!links)
1056                         LOG_LINKS (use_insn)
1057                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1058                     }
1059                 }
1060               next_use[regno] = NULL_RTX;
1061             }
1062
1063           FOR_EACH_INSN_USE (use, insn)
1064             {
1065               int regno = DF_REF_REGNO (use);
1066
1067               /* Do not consider the usage of the stack pointer
1068                  by function call.  */
1069               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1070                 continue;
1071
1072               next_use[regno] = insn;
1073             }
1074         }
1075     }
1076
1077   free (next_use);
1078 }
1079
1080 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1081    true if we found a LOG_LINK that proves that A feeds B.  This only works
1082    if there are no instructions between A and B which could have a link
1083    depending on A, since in that case we would not record a link for B.
1084    We also check the implicit dependency created by a cc0 setter/user
1085    pair.  */
1086
1087 static bool
1088 insn_a_feeds_b (rtx a, rtx b)
1089 {
1090   struct insn_link *links;
1091   FOR_EACH_LOG_LINK (links, b)
1092     if (links->insn == a)
1093       return true;
1094 #ifdef HAVE_cc0
1095   if (sets_cc0_p (a))
1096     return true;
1097 #endif
1098   return false;
1099 }
1100 \f
1101 /* Main entry point for combiner.  F is the first insn of the function.
1102    NREGS is the first unused pseudo-reg number.
1103
1104    Return nonzero if the combiner has turned an indirect jump
1105    instruction into a direct jump.  */
1106 static int
1107 combine_instructions (rtx f, unsigned int nregs)
1108 {
1109   rtx insn, next;
1110 #ifdef HAVE_cc0
1111   rtx prev;
1112 #endif
1113   struct insn_link *links, *nextlinks;
1114   rtx first;
1115   basic_block last_bb;
1116
1117   int new_direct_jump_p = 0;
1118
1119   for (first = f; first && !INSN_P (first); )
1120     first = NEXT_INSN (first);
1121   if (!first)
1122     return 0;
1123
1124   combine_attempts = 0;
1125   combine_merges = 0;
1126   combine_extras = 0;
1127   combine_successes = 0;
1128
1129   rtl_hooks = combine_rtl_hooks;
1130
1131   reg_stat.safe_grow_cleared (nregs);
1132
1133   init_recog_no_volatile ();
1134
1135   /* Allocate array for insn info.  */
1136   max_uid_known = get_max_uid ();
1137   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1138   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1139   gcc_obstack_init (&insn_link_obstack);
1140
1141   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1142
1143   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1144      problems when, for example, we have j <<= 1 in a loop.  */
1145
1146   nonzero_sign_valid = 0;
1147   label_tick = label_tick_ebb_start = 1;
1148
1149   /* Scan all SETs and see if we can deduce anything about what
1150      bits are known to be zero for some registers and how many copies
1151      of the sign bit are known to exist for those registers.
1152
1153      Also set any known values so that we can use it while searching
1154      for what bits are known to be set.  */
1155
1156   setup_incoming_promotions (first);
1157   /* Allow the entry block and the first block to fall into the same EBB.
1158      Conceptually the incoming promotions are assigned to the entry block.  */
1159   last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1160
1161   create_log_links ();
1162   FOR_EACH_BB_FN (this_basic_block, cfun)
1163     {
1164       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1165       last_call_luid = 0;
1166       mem_last_set = -1;
1167
1168       label_tick++;
1169       if (!single_pred_p (this_basic_block)
1170           || single_pred (this_basic_block) != last_bb)
1171         label_tick_ebb_start = label_tick;
1172       last_bb = this_basic_block;
1173
1174       FOR_BB_INSNS (this_basic_block, insn)
1175         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1176           {
1177 #ifdef AUTO_INC_DEC
1178             rtx links;
1179 #endif
1180
1181             subst_low_luid = DF_INSN_LUID (insn);
1182             subst_insn = insn;
1183
1184             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1185                          insn);
1186             record_dead_and_set_regs (insn);
1187
1188 #ifdef AUTO_INC_DEC
1189             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1190               if (REG_NOTE_KIND (links) == REG_INC)
1191                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1192                                                   insn);
1193 #endif
1194
1195             /* Record the current insn_rtx_cost of this instruction.  */
1196             if (NONJUMP_INSN_P (insn))
1197               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1198                                                 optimize_this_for_speed_p);
1199             if (dump_file)
1200               fprintf (dump_file, "insn_cost %d: %d\n",
1201                        INSN_UID (insn), INSN_COST (insn));
1202           }
1203     }
1204
1205   nonzero_sign_valid = 1;
1206
1207   /* Now scan all the insns in forward order.  */
1208   label_tick = label_tick_ebb_start = 1;
1209   init_reg_last ();
1210   setup_incoming_promotions (first);
1211   last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1212
1213   FOR_EACH_BB_FN (this_basic_block, cfun)
1214     {
1215       rtx last_combined_insn = NULL_RTX;
1216       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1217       last_call_luid = 0;
1218       mem_last_set = -1;
1219
1220       label_tick++;
1221       if (!single_pred_p (this_basic_block)
1222           || single_pred (this_basic_block) != last_bb)
1223         label_tick_ebb_start = label_tick;
1224       last_bb = this_basic_block;
1225
1226       rtl_profile_for_bb (this_basic_block);
1227       for (insn = BB_HEAD (this_basic_block);
1228            insn != NEXT_INSN (BB_END (this_basic_block));
1229            insn = next ? next : NEXT_INSN (insn))
1230         {
1231           next = 0;
1232           if (NONDEBUG_INSN_P (insn))
1233             {
1234               while (last_combined_insn
1235                      && INSN_DELETED_P (last_combined_insn))
1236                 last_combined_insn = PREV_INSN (last_combined_insn);
1237               if (last_combined_insn == NULL_RTX
1238                   || BARRIER_P (last_combined_insn)
1239                   || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1240                   || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1241                 last_combined_insn = insn;
1242
1243               /* See if we know about function return values before this
1244                  insn based upon SUBREG flags.  */
1245               check_promoted_subreg (insn, PATTERN (insn));
1246
1247               /* See if we can find hardregs and subreg of pseudos in
1248                  narrower modes.  This could help turning TRUNCATEs
1249                  into SUBREGs.  */
1250               note_uses (&PATTERN (insn), record_truncated_values, NULL);
1251
1252               /* Try this insn with each insn it links back to.  */
1253
1254               FOR_EACH_LOG_LINK (links, insn)
1255                 if ((next = try_combine (insn, links->insn, NULL_RTX,
1256                                          NULL_RTX, &new_direct_jump_p,
1257                                          last_combined_insn)) != 0)
1258                   goto retry;
1259
1260               /* Try each sequence of three linked insns ending with this one.  */
1261
1262               FOR_EACH_LOG_LINK (links, insn)
1263                 {
1264                   rtx link = links->insn;
1265
1266                   /* If the linked insn has been replaced by a note, then there
1267                      is no point in pursuing this chain any further.  */
1268                   if (NOTE_P (link))
1269                     continue;
1270
1271                   FOR_EACH_LOG_LINK (nextlinks, link)
1272                     if ((next = try_combine (insn, link, nextlinks->insn,
1273                                              NULL_RTX, &new_direct_jump_p,
1274                                              last_combined_insn)) != 0)
1275                       goto retry;
1276                 }
1277
1278 #ifdef HAVE_cc0
1279               /* Try to combine a jump insn that uses CC0
1280                  with a preceding insn that sets CC0, and maybe with its
1281                  logical predecessor as well.
1282                  This is how we make decrement-and-branch insns.
1283                  We need this special code because data flow connections
1284                  via CC0 do not get entered in LOG_LINKS.  */
1285
1286               if (JUMP_P (insn)
1287                   && (prev = prev_nonnote_insn (insn)) != 0
1288                   && NONJUMP_INSN_P (prev)
1289                   && sets_cc0_p (PATTERN (prev)))
1290                 {
1291                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1292                                            &new_direct_jump_p,
1293                                            last_combined_insn)) != 0)
1294                     goto retry;
1295
1296                   FOR_EACH_LOG_LINK (nextlinks, prev)
1297                     if ((next = try_combine (insn, prev, nextlinks->insn,
1298                                              NULL_RTX, &new_direct_jump_p,
1299                                              last_combined_insn)) != 0)
1300                       goto retry;
1301                 }
1302
1303               /* Do the same for an insn that explicitly references CC0.  */
1304               if (NONJUMP_INSN_P (insn)
1305                   && (prev = prev_nonnote_insn (insn)) != 0
1306                   && NONJUMP_INSN_P (prev)
1307                   && sets_cc0_p (PATTERN (prev))
1308                   && GET_CODE (PATTERN (insn)) == SET
1309                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1310                 {
1311                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1312                                            &new_direct_jump_p,
1313                                            last_combined_insn)) != 0)
1314                     goto retry;
1315
1316                   FOR_EACH_LOG_LINK (nextlinks, prev)
1317                     if ((next = try_combine (insn, prev, nextlinks->insn,
1318                                              NULL_RTX, &new_direct_jump_p,
1319                                              last_combined_insn)) != 0)
1320                       goto retry;
1321                 }
1322
1323               /* Finally, see if any of the insns that this insn links to
1324                  explicitly references CC0.  If so, try this insn, that insn,
1325                  and its predecessor if it sets CC0.  */
1326               FOR_EACH_LOG_LINK (links, insn)
1327                 if (NONJUMP_INSN_P (links->insn)
1328                     && GET_CODE (PATTERN (links->insn)) == SET
1329                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1330                     && (prev = prev_nonnote_insn (links->insn)) != 0
1331                     && NONJUMP_INSN_P (prev)
1332                     && sets_cc0_p (PATTERN (prev))
1333                     && (next = try_combine (insn, links->insn,
1334                                             prev, NULL_RTX, &new_direct_jump_p,
1335                                             last_combined_insn)) != 0)
1336                   goto retry;
1337 #endif
1338
1339               /* Try combining an insn with two different insns whose results it
1340                  uses.  */
1341               FOR_EACH_LOG_LINK (links, insn)
1342                 for (nextlinks = links->next; nextlinks;
1343                      nextlinks = nextlinks->next)
1344                   if ((next = try_combine (insn, links->insn,
1345                                            nextlinks->insn, NULL_RTX,
1346                                            &new_direct_jump_p,
1347                                            last_combined_insn)) != 0)
1348                     goto retry;
1349
1350               /* Try four-instruction combinations.  */
1351               FOR_EACH_LOG_LINK (links, insn)
1352                 {
1353                   struct insn_link *next1;
1354                   rtx link = links->insn;
1355
1356                   /* If the linked insn has been replaced by a note, then there
1357                      is no point in pursuing this chain any further.  */
1358                   if (NOTE_P (link))
1359                     continue;
1360
1361                   FOR_EACH_LOG_LINK (next1, link)
1362                     {
1363                       rtx link1 = next1->insn;
1364                       if (NOTE_P (link1))
1365                         continue;
1366                       /* I0 -> I1 -> I2 -> I3.  */
1367                       FOR_EACH_LOG_LINK (nextlinks, link1)
1368                         if ((next = try_combine (insn, link, link1,
1369                                                  nextlinks->insn,
1370                                                  &new_direct_jump_p,
1371                                                  last_combined_insn)) != 0)
1372                           goto retry;
1373                       /* I0, I1 -> I2, I2 -> I3.  */
1374                       for (nextlinks = next1->next; nextlinks;
1375                            nextlinks = nextlinks->next)
1376                         if ((next = try_combine (insn, link, link1,
1377                                                  nextlinks->insn,
1378                                                  &new_direct_jump_p,
1379                                                  last_combined_insn)) != 0)
1380                           goto retry;
1381                     }
1382
1383                   for (next1 = links->next; next1; next1 = next1->next)
1384                     {
1385                       rtx link1 = next1->insn;
1386                       if (NOTE_P (link1))
1387                         continue;
1388                       /* I0 -> I2; I1, I2 -> I3.  */
1389                       FOR_EACH_LOG_LINK (nextlinks, link)
1390                         if ((next = try_combine (insn, link, link1,
1391                                                  nextlinks->insn,
1392                                                  &new_direct_jump_p,
1393                                                  last_combined_insn)) != 0)
1394                           goto retry;
1395                       /* I0 -> I1; I1, I2 -> I3.  */
1396                       FOR_EACH_LOG_LINK (nextlinks, link1)
1397                         if ((next = try_combine (insn, link, link1,
1398                                                  nextlinks->insn,
1399                                                  &new_direct_jump_p,
1400                                                  last_combined_insn)) != 0)
1401                           goto retry;
1402                     }
1403                 }
1404
1405               /* Try this insn with each REG_EQUAL note it links back to.  */
1406               FOR_EACH_LOG_LINK (links, insn)
1407                 {
1408                   rtx set, note;
1409                   rtx temp = links->insn;
1410                   if ((set = single_set (temp)) != 0
1411                       && (note = find_reg_equal_equiv_note (temp)) != 0
1412                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1413                       /* Avoid using a register that may already been marked
1414                          dead by an earlier instruction.  */
1415                       && ! unmentioned_reg_p (note, SET_SRC (set))
1416                       && (GET_MODE (note) == VOIDmode
1417                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1418                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1419                     {
1420                       /* Temporarily replace the set's source with the
1421                          contents of the REG_EQUAL note.  The insn will
1422                          be deleted or recognized by try_combine.  */
1423                       rtx orig = SET_SRC (set);
1424                       SET_SRC (set) = note;
1425                       i2mod = temp;
1426                       i2mod_old_rhs = copy_rtx (orig);
1427                       i2mod_new_rhs = copy_rtx (note);
1428                       next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1429                                           &new_direct_jump_p,
1430                                           last_combined_insn);
1431                       i2mod = NULL_RTX;
1432                       if (next)
1433                         goto retry;
1434                       SET_SRC (set) = orig;
1435                     }
1436                 }
1437
1438               if (!NOTE_P (insn))
1439                 record_dead_and_set_regs (insn);
1440
1441             retry:
1442               ;
1443             }
1444         }
1445     }
1446
1447   default_rtl_profile ();
1448   clear_bb_flags ();
1449   new_direct_jump_p |= purge_all_dead_edges ();
1450   delete_noop_moves ();
1451
1452   /* Clean up.  */
1453   obstack_free (&insn_link_obstack, NULL);
1454   free (uid_log_links);
1455   free (uid_insn_cost);
1456   reg_stat.release ();
1457
1458   {
1459     struct undo *undo, *next;
1460     for (undo = undobuf.frees; undo; undo = next)
1461       {
1462         next = undo->next;
1463         free (undo);
1464       }
1465     undobuf.frees = 0;
1466   }
1467
1468   total_attempts += combine_attempts;
1469   total_merges += combine_merges;
1470   total_extras += combine_extras;
1471   total_successes += combine_successes;
1472
1473   nonzero_sign_valid = 0;
1474   rtl_hooks = general_rtl_hooks;
1475
1476   /* Make recognizer allow volatile MEMs again.  */
1477   init_recog ();
1478
1479   return new_direct_jump_p;
1480 }
1481
1482 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1483
1484 static void
1485 init_reg_last (void)
1486 {
1487   unsigned int i;
1488   reg_stat_type *p;
1489
1490   FOR_EACH_VEC_ELT (reg_stat, i, p)
1491     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1492 }
1493 \f
1494 /* Set up any promoted values for incoming argument registers.  */
1495
1496 static void
1497 setup_incoming_promotions (rtx first)
1498 {
1499   tree arg;
1500   bool strictly_local = false;
1501
1502   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1503        arg = DECL_CHAIN (arg))
1504     {
1505       rtx x, reg = DECL_INCOMING_RTL (arg);
1506       int uns1, uns3;
1507       enum machine_mode mode1, mode2, mode3, mode4;
1508
1509       /* Only continue if the incoming argument is in a register.  */
1510       if (!REG_P (reg))
1511         continue;
1512
1513       /* Determine, if possible, whether all call sites of the current
1514          function lie within the current compilation unit.  (This does
1515          take into account the exporting of a function via taking its
1516          address, and so forth.)  */
1517       strictly_local = cgraph_local_info (current_function_decl)->local;
1518
1519       /* The mode and signedness of the argument before any promotions happen
1520          (equal to the mode of the pseudo holding it at that stage).  */
1521       mode1 = TYPE_MODE (TREE_TYPE (arg));
1522       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1523
1524       /* The mode and signedness of the argument after any source language and
1525          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1526       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1527       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1528
1529       /* The mode and signedness of the argument as it is actually passed,
1530          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1531       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1532                                      TREE_TYPE (cfun->decl), 0);
1533
1534       /* The mode of the register in which the argument is being passed.  */
1535       mode4 = GET_MODE (reg);
1536
1537       /* Eliminate sign extensions in the callee when:
1538          (a) A mode promotion has occurred;  */
1539       if (mode1 == mode3)
1540         continue;
1541       /* (b) The mode of the register is the same as the mode of
1542              the argument as it is passed; */
1543       if (mode3 != mode4)
1544         continue;
1545       /* (c) There's no language level extension;  */
1546       if (mode1 == mode2)
1547         ;
1548       /* (c.1) All callers are from the current compilation unit.  If that's
1549          the case we don't have to rely on an ABI, we only have to know
1550          what we're generating right now, and we know that we will do the
1551          mode1 to mode2 promotion with the given sign.  */
1552       else if (!strictly_local)
1553         continue;
1554       /* (c.2) The combination of the two promotions is useful.  This is
1555          true when the signs match, or if the first promotion is unsigned.
1556          In the later case, (sign_extend (zero_extend x)) is the same as
1557          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1558       else if (uns1)
1559         uns3 = true;
1560       else if (uns3)
1561         continue;
1562
1563       /* Record that the value was promoted from mode1 to mode3,
1564          so that any sign extension at the head of the current
1565          function may be eliminated.  */
1566       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1567       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1568       record_value_for_reg (reg, first, x);
1569     }
1570 }
1571
1572 /* Called via note_stores.  If X is a pseudo that is narrower than
1573    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1574
1575    If we are setting only a portion of X and we can't figure out what
1576    portion, assume all bits will be used since we don't know what will
1577    be happening.
1578
1579    Similarly, set how many bits of X are known to be copies of the sign bit
1580    at all locations in the function.  This is the smallest number implied
1581    by any set of X.  */
1582
1583 static void
1584 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1585 {
1586   rtx insn = (rtx) data;
1587   unsigned int num;
1588
1589   if (REG_P (x)
1590       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1591       /* If this register is undefined at the start of the file, we can't
1592          say what its contents were.  */
1593       && ! REGNO_REG_SET_P
1594            (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1595       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1596     {
1597       reg_stat_type *rsp = &reg_stat[REGNO (x)];
1598
1599       if (set == 0 || GET_CODE (set) == CLOBBER)
1600         {
1601           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1602           rsp->sign_bit_copies = 1;
1603           return;
1604         }
1605
1606       /* If this register is being initialized using itself, and the
1607          register is uninitialized in this basic block, and there are
1608          no LOG_LINKS which set the register, then part of the
1609          register is uninitialized.  In that case we can't assume
1610          anything about the number of nonzero bits.
1611
1612          ??? We could do better if we checked this in
1613          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1614          could avoid making assumptions about the insn which initially
1615          sets the register, while still using the information in other
1616          insns.  We would have to be careful to check every insn
1617          involved in the combination.  */
1618
1619       if (insn
1620           && reg_referenced_p (x, PATTERN (insn))
1621           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1622                                REGNO (x)))
1623         {
1624           struct insn_link *link;
1625
1626           FOR_EACH_LOG_LINK (link, insn)
1627             if (dead_or_set_p (link->insn, x))
1628               break;
1629           if (!link)
1630             {
1631               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1632               rsp->sign_bit_copies = 1;
1633               return;
1634             }
1635         }
1636
1637       /* If this is a complex assignment, see if we can convert it into a
1638          simple assignment.  */
1639       set = expand_field_assignment (set);
1640
1641       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1642          set what we know about X.  */
1643
1644       if (SET_DEST (set) == x
1645           || (paradoxical_subreg_p (SET_DEST (set))
1646               && SUBREG_REG (SET_DEST (set)) == x))
1647         {
1648           rtx src = SET_SRC (set);
1649
1650 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1651           /* If X is narrower than a word and SRC is a non-negative
1652              constant that would appear negative in the mode of X,
1653              sign-extend it for use in reg_stat[].nonzero_bits because some
1654              machines (maybe most) will actually do the sign-extension
1655              and this is the conservative approach.
1656
1657              ??? For 2.5, try to tighten up the MD files in this regard
1658              instead of this kludge.  */
1659
1660           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1661               && CONST_INT_P (src)
1662               && INTVAL (src) > 0
1663               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1664             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1665 #endif
1666
1667           /* Don't call nonzero_bits if it cannot change anything.  */
1668           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1669             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1670           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1671           if (rsp->sign_bit_copies == 0
1672               || rsp->sign_bit_copies > num)
1673             rsp->sign_bit_copies = num;
1674         }
1675       else
1676         {
1677           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1678           rsp->sign_bit_copies = 1;
1679         }
1680     }
1681 }
1682 \f
1683 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1684    optionally insns that were previously combined into I3 or that will be
1685    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1686    INSN, SUCC, SUCC2, I3.
1687
1688    Return 0 if the combination is not allowed for any reason.
1689
1690    If the combination is allowed, *PDEST will be set to the single
1691    destination of INSN and *PSRC to the single source, and this function
1692    will return 1.  */
1693
1694 static int
1695 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1696                rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1697                rtx *pdest, rtx *psrc)
1698 {
1699   int i;
1700   const_rtx set = 0;
1701   rtx src, dest;
1702   rtx p;
1703 #ifdef AUTO_INC_DEC
1704   rtx link;
1705 #endif
1706   bool all_adjacent = true;
1707   int (*is_volatile_p) (const_rtx);
1708
1709   if (succ)
1710     {
1711       if (succ2)
1712         {
1713           if (next_active_insn (succ2) != i3)
1714             all_adjacent = false;
1715           if (next_active_insn (succ) != succ2)
1716             all_adjacent = false;
1717         }
1718       else if (next_active_insn (succ) != i3)
1719         all_adjacent = false;
1720       if (next_active_insn (insn) != succ)
1721         all_adjacent = false;
1722     }
1723   else if (next_active_insn (insn) != i3)
1724     all_adjacent = false;
1725
1726   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1727      or a PARALLEL consisting of such a SET and CLOBBERs.
1728
1729      If INSN has CLOBBER parallel parts, ignore them for our processing.
1730      By definition, these happen during the execution of the insn.  When it
1731      is merged with another insn, all bets are off.  If they are, in fact,
1732      needed and aren't also supplied in I3, they may be added by
1733      recog_for_combine.  Otherwise, it won't match.
1734
1735      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1736      note.
1737
1738      Get the source and destination of INSN.  If more than one, can't
1739      combine.  */
1740
1741   if (GET_CODE (PATTERN (insn)) == SET)
1742     set = PATTERN (insn);
1743   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1744            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1745     {
1746       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1747         {
1748           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1749
1750           switch (GET_CODE (elt))
1751             {
1752             /* This is important to combine floating point insns
1753                for the SH4 port.  */
1754             case USE:
1755               /* Combining an isolated USE doesn't make sense.
1756                  We depend here on combinable_i3pat to reject them.  */
1757               /* The code below this loop only verifies that the inputs of
1758                  the SET in INSN do not change.  We call reg_set_between_p
1759                  to verify that the REG in the USE does not change between
1760                  I3 and INSN.
1761                  If the USE in INSN was for a pseudo register, the matching
1762                  insn pattern will likely match any register; combining this
1763                  with any other USE would only be safe if we knew that the
1764                  used registers have identical values, or if there was
1765                  something to tell them apart, e.g. different modes.  For
1766                  now, we forgo such complicated tests and simply disallow
1767                  combining of USES of pseudo registers with any other USE.  */
1768               if (REG_P (XEXP (elt, 0))
1769                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1770                 {
1771                   rtx i3pat = PATTERN (i3);
1772                   int i = XVECLEN (i3pat, 0) - 1;
1773                   unsigned int regno = REGNO (XEXP (elt, 0));
1774
1775                   do
1776                     {
1777                       rtx i3elt = XVECEXP (i3pat, 0, i);
1778
1779                       if (GET_CODE (i3elt) == USE
1780                           && REG_P (XEXP (i3elt, 0))
1781                           && (REGNO (XEXP (i3elt, 0)) == regno
1782                               ? reg_set_between_p (XEXP (elt, 0),
1783                                                    PREV_INSN (insn), i3)
1784                               : regno >= FIRST_PSEUDO_REGISTER))
1785                         return 0;
1786                     }
1787                   while (--i >= 0);
1788                 }
1789               break;
1790
1791               /* We can ignore CLOBBERs.  */
1792             case CLOBBER:
1793               break;
1794
1795             case SET:
1796               /* Ignore SETs whose result isn't used but not those that
1797                  have side-effects.  */
1798               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1799                   && insn_nothrow_p (insn)
1800                   && !side_effects_p (elt))
1801                 break;
1802
1803               /* If we have already found a SET, this is a second one and
1804                  so we cannot combine with this insn.  */
1805               if (set)
1806                 return 0;
1807
1808               set = elt;
1809               break;
1810
1811             default:
1812               /* Anything else means we can't combine.  */
1813               return 0;
1814             }
1815         }
1816
1817       if (set == 0
1818           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1819              so don't do anything with it.  */
1820           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1821         return 0;
1822     }
1823   else
1824     return 0;
1825
1826   if (set == 0)
1827     return 0;
1828
1829   /* The simplification in expand_field_assignment may call back to
1830      get_last_value, so set safe guard here.  */
1831   subst_low_luid = DF_INSN_LUID (insn);
1832
1833   set = expand_field_assignment (set);
1834   src = SET_SRC (set), dest = SET_DEST (set);
1835
1836   /* Don't eliminate a store in the stack pointer.  */
1837   if (dest == stack_pointer_rtx
1838       /* Don't combine with an insn that sets a register to itself if it has
1839          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1840       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1841       /* Can't merge an ASM_OPERANDS.  */
1842       || GET_CODE (src) == ASM_OPERANDS
1843       /* Can't merge a function call.  */
1844       || GET_CODE (src) == CALL
1845       /* Don't eliminate a function call argument.  */
1846       || (CALL_P (i3)
1847           && (find_reg_fusage (i3, USE, dest)
1848               || (REG_P (dest)
1849                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1850                   && global_regs[REGNO (dest)])))
1851       /* Don't substitute into an incremented register.  */
1852       || FIND_REG_INC_NOTE (i3, dest)
1853       || (succ && FIND_REG_INC_NOTE (succ, dest))
1854       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1855       /* Don't substitute into a non-local goto, this confuses CFG.  */
1856       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1857       /* Make sure that DEST is not used after SUCC but before I3.  */
1858       || (!all_adjacent
1859           && ((succ2
1860                && (reg_used_between_p (dest, succ2, i3)
1861                    || reg_used_between_p (dest, succ, succ2)))
1862               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1863       /* Make sure that the value that is to be substituted for the register
1864          does not use any registers whose values alter in between.  However,
1865          If the insns are adjacent, a use can't cross a set even though we
1866          think it might (this can happen for a sequence of insns each setting
1867          the same destination; last_set of that register might point to
1868          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1869          equivalent to the memory so the substitution is valid even if there
1870          are intervening stores.  Also, don't move a volatile asm or
1871          UNSPEC_VOLATILE across any other insns.  */
1872       || (! all_adjacent
1873           && (((!MEM_P (src)
1874                 || ! find_reg_note (insn, REG_EQUIV, src))
1875                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1876               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1877               || GET_CODE (src) == UNSPEC_VOLATILE))
1878       /* Don't combine across a CALL_INSN, because that would possibly
1879          change whether the life span of some REGs crosses calls or not,
1880          and it is a pain to update that information.
1881          Exception: if source is a constant, moving it later can't hurt.
1882          Accept that as a special case.  */
1883       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1884     return 0;
1885
1886   /* DEST must either be a REG or CC0.  */
1887   if (REG_P (dest))
1888     {
1889       /* If register alignment is being enforced for multi-word items in all
1890          cases except for parameters, it is possible to have a register copy
1891          insn referencing a hard register that is not allowed to contain the
1892          mode being copied and which would not be valid as an operand of most
1893          insns.  Eliminate this problem by not combining with such an insn.
1894
1895          Also, on some machines we don't want to extend the life of a hard
1896          register.  */
1897
1898       if (REG_P (src)
1899           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1900                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1901               /* Don't extend the life of a hard register unless it is
1902                  user variable (if we have few registers) or it can't
1903                  fit into the desired register (meaning something special
1904                  is going on).
1905                  Also avoid substituting a return register into I3, because
1906                  reload can't handle a conflict with constraints of other
1907                  inputs.  */
1908               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1909                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1910         return 0;
1911     }
1912   else if (GET_CODE (dest) != CC0)
1913     return 0;
1914
1915
1916   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1917     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1918       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1919         {
1920           /* Don't substitute for a register intended as a clobberable
1921              operand.  */
1922           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1923           if (rtx_equal_p (reg, dest))
1924             return 0;
1925
1926           /* If the clobber represents an earlyclobber operand, we must not
1927              substitute an expression containing the clobbered register.
1928              As we do not analyze the constraint strings here, we have to
1929              make the conservative assumption.  However, if the register is
1930              a fixed hard reg, the clobber cannot represent any operand;
1931              we leave it up to the machine description to either accept or
1932              reject use-and-clobber patterns.  */
1933           if (!REG_P (reg)
1934               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1935               || !fixed_regs[REGNO (reg)])
1936             if (reg_overlap_mentioned_p (reg, src))
1937               return 0;
1938         }
1939
1940   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1941      or not), reject, unless nothing volatile comes between it and I3 */
1942
1943   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1944     {
1945       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1946       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1947         return 0;
1948       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1949         return 0;
1950       /* We'll check insns between INSN and I3 below.  */
1951     }
1952
1953   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1954      to be an explicit register variable, and was chosen for a reason.  */
1955
1956   if (GET_CODE (src) == ASM_OPERANDS
1957       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1958     return 0;
1959
1960   /* If INSN contains volatile references (specifically volatile MEMs),
1961      we cannot combine across any other volatile references.
1962      Even if INSN doesn't contain volatile references, any intervening
1963      volatile insn might affect machine state.  */
1964
1965   is_volatile_p = volatile_refs_p (PATTERN (insn))
1966     ? volatile_refs_p
1967     : volatile_insn_p;
1968
1969   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1970     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1971       return 0;
1972
1973   /* If INSN contains an autoincrement or autodecrement, make sure that
1974      register is not used between there and I3, and not already used in
1975      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1976      Also insist that I3 not be a jump; if it were one
1977      and the incremented register were spilled, we would lose.  */
1978
1979 #ifdef AUTO_INC_DEC
1980   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1981     if (REG_NOTE_KIND (link) == REG_INC
1982         && (JUMP_P (i3)
1983             || reg_used_between_p (XEXP (link, 0), insn, i3)
1984             || (pred != NULL_RTX
1985                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1986             || (pred2 != NULL_RTX
1987                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1988             || (succ != NULL_RTX
1989                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1990             || (succ2 != NULL_RTX
1991                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1992             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1993       return 0;
1994 #endif
1995
1996 #ifdef HAVE_cc0
1997   /* Don't combine an insn that follows a CC0-setting insn.
1998      An insn that uses CC0 must not be separated from the one that sets it.
1999      We do, however, allow I2 to follow a CC0-setting insn if that insn
2000      is passed as I1; in that case it will be deleted also.
2001      We also allow combining in this case if all the insns are adjacent
2002      because that would leave the two CC0 insns adjacent as well.
2003      It would be more logical to test whether CC0 occurs inside I1 or I2,
2004      but that would be much slower, and this ought to be equivalent.  */
2005
2006   p = prev_nonnote_insn (insn);
2007   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2008       && ! all_adjacent)
2009     return 0;
2010 #endif
2011
2012   /* If we get here, we have passed all the tests and the combination is
2013      to be allowed.  */
2014
2015   *pdest = dest;
2016   *psrc = src;
2017
2018   return 1;
2019 }
2020 \f
2021 /* LOC is the location within I3 that contains its pattern or the component
2022    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2023
2024    One problem is if I3 modifies its output, as opposed to replacing it
2025    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2026    doing so would produce an insn that is not equivalent to the original insns.
2027
2028    Consider:
2029
2030          (set (reg:DI 101) (reg:DI 100))
2031          (set (subreg:SI (reg:DI 101) 0) <foo>)
2032
2033    This is NOT equivalent to:
2034
2035          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2036                     (set (reg:DI 101) (reg:DI 100))])
2037
2038    Not only does this modify 100 (in which case it might still be valid
2039    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2040
2041    We can also run into a problem if I2 sets a register that I1
2042    uses and I1 gets directly substituted into I3 (not via I2).  In that
2043    case, we would be getting the wrong value of I2DEST into I3, so we
2044    must reject the combination.  This case occurs when I2 and I1 both
2045    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2046    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2047    of a SET must prevent combination from occurring.  The same situation
2048    can occur for I0, in which case I0_NOT_IN_SRC is set.
2049
2050    Before doing the above check, we first try to expand a field assignment
2051    into a set of logical operations.
2052
2053    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2054    we place a register that is both set and used within I3.  If more than one
2055    such register is detected, we fail.
2056
2057    Return 1 if the combination is valid, zero otherwise.  */
2058
2059 static int
2060 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2061                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2062 {
2063   rtx x = *loc;
2064
2065   if (GET_CODE (x) == SET)
2066     {
2067       rtx set = x ;
2068       rtx dest = SET_DEST (set);
2069       rtx src = SET_SRC (set);
2070       rtx inner_dest = dest;
2071       rtx subdest;
2072
2073       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2074              || GET_CODE (inner_dest) == SUBREG
2075              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2076         inner_dest = XEXP (inner_dest, 0);
2077
2078       /* Check for the case where I3 modifies its output, as discussed
2079          above.  We don't want to prevent pseudos from being combined
2080          into the address of a MEM, so only prevent the combination if
2081          i1 or i2 set the same MEM.  */
2082       if ((inner_dest != dest &&
2083            (!MEM_P (inner_dest)
2084             || rtx_equal_p (i2dest, inner_dest)
2085             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2086             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2087            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2088                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2089                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2090
2091           /* This is the same test done in can_combine_p except we can't test
2092              all_adjacent; we don't have to, since this instruction will stay
2093              in place, thus we are not considering increasing the lifetime of
2094              INNER_DEST.
2095
2096              Also, if this insn sets a function argument, combining it with
2097              something that might need a spill could clobber a previous
2098              function argument; the all_adjacent test in can_combine_p also
2099              checks this; here, we do a more specific test for this case.  */
2100
2101           || (REG_P (inner_dest)
2102               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2103               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2104                                         GET_MODE (inner_dest))))
2105           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2106           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2107         return 0;
2108
2109       /* If DEST is used in I3, it is being killed in this insn, so
2110          record that for later.  We have to consider paradoxical
2111          subregs here, since they kill the whole register, but we
2112          ignore partial subregs, STRICT_LOW_PART, etc.
2113          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2114          STACK_POINTER_REGNUM, since these are always considered to be
2115          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2116       subdest = dest;
2117       if (GET_CODE (subdest) == SUBREG
2118           && (GET_MODE_SIZE (GET_MODE (subdest))
2119               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2120         subdest = SUBREG_REG (subdest);
2121       if (pi3dest_killed
2122           && REG_P (subdest)
2123           && reg_referenced_p (subdest, PATTERN (i3))
2124           && REGNO (subdest) != FRAME_POINTER_REGNUM
2125 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2126           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2127 #endif
2128 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2129           && (REGNO (subdest) != ARG_POINTER_REGNUM
2130               || ! fixed_regs [REGNO (subdest)])
2131 #endif
2132           && REGNO (subdest) != STACK_POINTER_REGNUM)
2133         {
2134           if (*pi3dest_killed)
2135             return 0;
2136
2137           *pi3dest_killed = subdest;
2138         }
2139     }
2140
2141   else if (GET_CODE (x) == PARALLEL)
2142     {
2143       int i;
2144
2145       for (i = 0; i < XVECLEN (x, 0); i++)
2146         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2147                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2148           return 0;
2149     }
2150
2151   return 1;
2152 }
2153 \f
2154 /* Return 1 if X is an arithmetic expression that contains a multiplication
2155    and division.  We don't count multiplications by powers of two here.  */
2156
2157 static int
2158 contains_muldiv (rtx x)
2159 {
2160   switch (GET_CODE (x))
2161     {
2162     case MOD:  case DIV:  case UMOD:  case UDIV:
2163       return 1;
2164
2165     case MULT:
2166       return ! (CONST_INT_P (XEXP (x, 1))
2167                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2168     default:
2169       if (BINARY_P (x))
2170         return contains_muldiv (XEXP (x, 0))
2171             || contains_muldiv (XEXP (x, 1));
2172
2173       if (UNARY_P (x))
2174         return contains_muldiv (XEXP (x, 0));
2175
2176       return 0;
2177     }
2178 }
2179 \f
2180 /* Determine whether INSN can be used in a combination.  Return nonzero if
2181    not.  This is used in try_combine to detect early some cases where we
2182    can't perform combinations.  */
2183
2184 static int
2185 cant_combine_insn_p (rtx insn)
2186 {
2187   rtx set;
2188   rtx src, dest;
2189
2190   /* If this isn't really an insn, we can't do anything.
2191      This can occur when flow deletes an insn that it has merged into an
2192      auto-increment address.  */
2193   if (! INSN_P (insn))
2194     return 1;
2195
2196   /* Never combine loads and stores involving hard regs that are likely
2197      to be spilled.  The register allocator can usually handle such
2198      reg-reg moves by tying.  If we allow the combiner to make
2199      substitutions of likely-spilled regs, reload might die.
2200      As an exception, we allow combinations involving fixed regs; these are
2201      not available to the register allocator so there's no risk involved.  */
2202
2203   set = single_set (insn);
2204   if (! set)
2205     return 0;
2206   src = SET_SRC (set);
2207   dest = SET_DEST (set);
2208   if (GET_CODE (src) == SUBREG)
2209     src = SUBREG_REG (src);
2210   if (GET_CODE (dest) == SUBREG)
2211     dest = SUBREG_REG (dest);
2212   if (REG_P (src) && REG_P (dest)
2213       && ((HARD_REGISTER_P (src)
2214            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2215            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2216           || (HARD_REGISTER_P (dest)
2217               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2218               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2219     return 1;
2220
2221   return 0;
2222 }
2223
2224 struct likely_spilled_retval_info
2225 {
2226   unsigned regno, nregs;
2227   unsigned mask;
2228 };
2229
2230 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2231    hard registers that are known to be written to / clobbered in full.  */
2232 static void
2233 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2234 {
2235   struct likely_spilled_retval_info *const info =
2236     (struct likely_spilled_retval_info *) data;
2237   unsigned regno, nregs;
2238   unsigned new_mask;
2239
2240   if (!REG_P (XEXP (set, 0)))
2241     return;
2242   regno = REGNO (x);
2243   if (regno >= info->regno + info->nregs)
2244     return;
2245   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2246   if (regno + nregs <= info->regno)
2247     return;
2248   new_mask = (2U << (nregs - 1)) - 1;
2249   if (regno < info->regno)
2250     new_mask >>= info->regno - regno;
2251   else
2252     new_mask <<= regno - info->regno;
2253   info->mask &= ~new_mask;
2254 }
2255
2256 /* Return nonzero iff part of the return value is live during INSN, and
2257    it is likely spilled.  This can happen when more than one insn is needed
2258    to copy the return value, e.g. when we consider to combine into the
2259    second copy insn for a complex value.  */
2260
2261 static int
2262 likely_spilled_retval_p (rtx insn)
2263 {
2264   rtx use = BB_END (this_basic_block);
2265   rtx reg, p;
2266   unsigned regno, nregs;
2267   /* We assume here that no machine mode needs more than
2268      32 hard registers when the value overlaps with a register
2269      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2270   unsigned mask;
2271   struct likely_spilled_retval_info info;
2272
2273   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2274     return 0;
2275   reg = XEXP (PATTERN (use), 0);
2276   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2277     return 0;
2278   regno = REGNO (reg);
2279   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2280   if (nregs == 1)
2281     return 0;
2282   mask = (2U << (nregs - 1)) - 1;
2283
2284   /* Disregard parts of the return value that are set later.  */
2285   info.regno = regno;
2286   info.nregs = nregs;
2287   info.mask = mask;
2288   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2289     if (INSN_P (p))
2290       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2291   mask = info.mask;
2292
2293   /* Check if any of the (probably) live return value registers is
2294      likely spilled.  */
2295   nregs --;
2296   do
2297     {
2298       if ((mask & 1 << nregs)
2299           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2300         return 1;
2301     } while (nregs--);
2302   return 0;
2303 }
2304
2305 /* Adjust INSN after we made a change to its destination.
2306
2307    Changing the destination can invalidate notes that say something about
2308    the results of the insn and a LOG_LINK pointing to the insn.  */
2309
2310 static void
2311 adjust_for_new_dest (rtx insn)
2312 {
2313   /* For notes, be conservative and simply remove them.  */
2314   remove_reg_equal_equiv_notes (insn);
2315
2316   /* The new insn will have a destination that was previously the destination
2317      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2318      the next use of that destination.  */
2319   distribute_links (alloc_insn_link (insn, NULL));
2320
2321   df_insn_rescan (insn);
2322 }
2323
2324 /* Return TRUE if combine can reuse reg X in mode MODE.
2325    ADDED_SETS is nonzero if the original set is still required.  */
2326 static bool
2327 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2328 {
2329   unsigned int regno;
2330
2331   if (!REG_P (x))
2332     return false;
2333
2334   regno = REGNO (x);
2335   /* Allow hard registers if the new mode is legal, and occupies no more
2336      registers than the old mode.  */
2337   if (regno < FIRST_PSEUDO_REGISTER)
2338     return (HARD_REGNO_MODE_OK (regno, mode)
2339             && (hard_regno_nregs[regno][GET_MODE (x)]
2340                 >= hard_regno_nregs[regno][mode]));
2341
2342   /* Or a pseudo that is only used once.  */
2343   return (REG_N_SETS (regno) == 1 && !added_sets
2344           && !REG_USERVAR_P (x));
2345 }
2346
2347
2348 /* Check whether X, the destination of a set, refers to part of
2349    the register specified by REG.  */
2350
2351 static bool
2352 reg_subword_p (rtx x, rtx reg)
2353 {
2354   /* Check that reg is an integer mode register.  */
2355   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2356     return false;
2357
2358   if (GET_CODE (x) == STRICT_LOW_PART
2359       || GET_CODE (x) == ZERO_EXTRACT)
2360     x = XEXP (x, 0);
2361
2362   return GET_CODE (x) == SUBREG
2363          && SUBREG_REG (x) == reg
2364          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2365 }
2366
2367 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2368    Note that the INSN should be deleted *after* removing dead edges, so
2369    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2370    but not for a (set (pc) (label_ref FOO)).  */
2371
2372 static void
2373 update_cfg_for_uncondjump (rtx insn)
2374 {
2375   basic_block bb = BLOCK_FOR_INSN (insn);
2376   gcc_assert (BB_END (bb) == insn);
2377
2378   purge_dead_edges (bb);
2379
2380   delete_insn (insn);
2381   if (EDGE_COUNT (bb->succs) == 1)
2382     {
2383       rtx insn;
2384
2385       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2386
2387       /* Remove barriers from the footer if there are any.  */
2388       for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2389         if (BARRIER_P (insn))
2390           {
2391             if (PREV_INSN (insn))
2392               NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2393             else
2394               BB_FOOTER (bb) = NEXT_INSN (insn);
2395             if (NEXT_INSN (insn))
2396               PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2397           }
2398         else if (LABEL_P (insn))
2399           break;
2400     }
2401 }
2402
2403 /* Try to combine the insns I0, I1 and I2 into I3.
2404    Here I0, I1 and I2 appear earlier than I3.
2405    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2406    I3.
2407
2408    If we are combining more than two insns and the resulting insn is not
2409    recognized, try splitting it into two insns.  If that happens, I2 and I3
2410    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2411    Otherwise, I0, I1 and I2 are pseudo-deleted.
2412
2413    Return 0 if the combination does not work.  Then nothing is changed.
2414    If we did the combination, return the insn at which combine should
2415    resume scanning.
2416
2417    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2418    new direct jump instruction.
2419
2420    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2421    been I3 passed to an earlier try_combine within the same basic
2422    block.  */
2423
2424 static rtx
2425 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2426              rtx last_combined_insn)
2427 {
2428   /* New patterns for I3 and I2, respectively.  */
2429   rtx newpat, newi2pat = 0;
2430   rtvec newpat_vec_with_clobbers = 0;
2431   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2432   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2433      dead.  */
2434   int added_sets_0, added_sets_1, added_sets_2;
2435   /* Total number of SETs to put into I3.  */
2436   int total_sets;
2437   /* Nonzero if I2's or I1's body now appears in I3.  */
2438   int i2_is_used = 0, i1_is_used = 0;
2439   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2440   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2441   /* Contains I3 if the destination of I3 is used in its source, which means
2442      that the old life of I3 is being killed.  If that usage is placed into
2443      I2 and not in I3, a REG_DEAD note must be made.  */
2444   rtx i3dest_killed = 0;
2445   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2446   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2447   /* Copy of SET_SRC of I1 and I0, if needed.  */
2448   rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2449   /* Set if I2DEST was reused as a scratch register.  */
2450   bool i2scratch = false;
2451   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2452   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2453   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2454   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2455   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2456   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2457   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2458   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2459   rtx new_i3_notes, new_i2_notes;
2460   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2461   int i3_subst_into_i2 = 0;
2462   /* Notes that I1, I2 or I3 is a MULT operation.  */
2463   int have_mult = 0;
2464   int swap_i2i3 = 0;
2465   int changed_i3_dest = 0;
2466
2467   int maxreg;
2468   rtx temp;
2469   struct insn_link *link;
2470   rtx other_pat = 0;
2471   rtx new_other_notes;
2472   int i;
2473
2474   /* Only try four-insn combinations when there's high likelihood of
2475      success.  Look for simple insns, such as loads of constants or
2476      binary operations involving a constant.  */
2477   if (i0)
2478     {
2479       int i;
2480       int ngood = 0;
2481       int nshift = 0;
2482
2483       if (!flag_expensive_optimizations)
2484         return 0;
2485
2486       for (i = 0; i < 4; i++)
2487         {
2488           rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2489           rtx set = single_set (insn);
2490           rtx src;
2491           if (!set)
2492             continue;
2493           src = SET_SRC (set);
2494           if (CONSTANT_P (src))
2495             {
2496               ngood += 2;
2497               break;
2498             }
2499           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2500             ngood++;
2501           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2502                    || GET_CODE (src) == LSHIFTRT)
2503             nshift++;
2504         }
2505       if (ngood < 2 && nshift < 2)
2506         return 0;
2507     }
2508
2509   /* Exit early if one of the insns involved can't be used for
2510      combinations.  */
2511   if (cant_combine_insn_p (i3)
2512       || cant_combine_insn_p (i2)
2513       || (i1 && cant_combine_insn_p (i1))
2514       || (i0 && cant_combine_insn_p (i0))
2515       || likely_spilled_retval_p (i3))
2516     return 0;
2517
2518   combine_attempts++;
2519   undobuf.other_insn = 0;
2520
2521   /* Reset the hard register usage information.  */
2522   CLEAR_HARD_REG_SET (newpat_used_regs);
2523
2524   if (dump_file && (dump_flags & TDF_DETAILS))
2525     {
2526       if (i0)
2527         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2528                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2529       else if (i1)
2530         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2531                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2532       else
2533         fprintf (dump_file, "\nTrying %d -> %d:\n",
2534                  INSN_UID (i2), INSN_UID (i3));
2535     }
2536
2537   /* If multiple insns feed into one of I2 or I3, they can be in any
2538      order.  To simplify the code below, reorder them in sequence.  */
2539   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2540     temp = i2, i2 = i0, i0 = temp;
2541   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2542     temp = i1, i1 = i0, i0 = temp;
2543   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2544     temp = i1, i1 = i2, i2 = temp;
2545
2546   added_links_insn = 0;
2547
2548   /* First check for one important special case that the code below will
2549      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2550      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2551      we may be able to replace that destination with the destination of I3.
2552      This occurs in the common code where we compute both a quotient and
2553      remainder into a structure, in which case we want to do the computation
2554      directly into the structure to avoid register-register copies.
2555
2556      Note that this case handles both multiple sets in I2 and also cases
2557      where I2 has a number of CLOBBERs inside the PARALLEL.
2558
2559      We make very conservative checks below and only try to handle the
2560      most common cases of this.  For example, we only handle the case
2561      where I2 and I3 are adjacent to avoid making difficult register
2562      usage tests.  */
2563
2564   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2565       && REG_P (SET_SRC (PATTERN (i3)))
2566       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2567       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2568       && GET_CODE (PATTERN (i2)) == PARALLEL
2569       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2570       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2571          below would need to check what is inside (and reg_overlap_mentioned_p
2572          doesn't support those codes anyway).  Don't allow those destinations;
2573          the resulting insn isn't likely to be recognized anyway.  */
2574       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2575       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2576       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2577                                     SET_DEST (PATTERN (i3)))
2578       && next_active_insn (i2) == i3)
2579     {
2580       rtx p2 = PATTERN (i2);
2581
2582       /* Make sure that the destination of I3,
2583          which we are going to substitute into one output of I2,
2584          is not used within another output of I2.  We must avoid making this:
2585          (parallel [(set (mem (reg 69)) ...)
2586                     (set (reg 69) ...)])
2587          which is not well-defined as to order of actions.
2588          (Besides, reload can't handle output reloads for this.)
2589
2590          The problem can also happen if the dest of I3 is a memory ref,
2591          if another dest in I2 is an indirect memory ref.  */
2592       for (i = 0; i < XVECLEN (p2, 0); i++)
2593         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2594              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2595             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2596                                         SET_DEST (XVECEXP (p2, 0, i))))
2597           break;
2598
2599       if (i == XVECLEN (p2, 0))
2600         for (i = 0; i < XVECLEN (p2, 0); i++)
2601           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2602               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2603             {
2604               combine_merges++;
2605
2606               subst_insn = i3;
2607               subst_low_luid = DF_INSN_LUID (i2);
2608
2609               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2610               i2src = SET_SRC (XVECEXP (p2, 0, i));
2611               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2612               i2dest_killed = dead_or_set_p (i2, i2dest);
2613
2614               /* Replace the dest in I2 with our dest and make the resulting
2615                  insn the new pattern for I3.  Then skip to where we validate
2616                  the pattern.  Everything was set up above.  */
2617               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2618               newpat = p2;
2619               i3_subst_into_i2 = 1;
2620               goto validate_replacement;
2621             }
2622     }
2623
2624   /* If I2 is setting a pseudo to a constant and I3 is setting some
2625      sub-part of it to another constant, merge them by making a new
2626      constant.  */
2627   if (i1 == 0
2628       && (temp = single_set (i2)) != 0
2629       && CONST_SCALAR_INT_P (SET_SRC (temp))
2630       && GET_CODE (PATTERN (i3)) == SET
2631       && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2632       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2633     {
2634       rtx dest = SET_DEST (PATTERN (i3));
2635       int offset = -1;
2636       int width = 0;
2637
2638       if (GET_CODE (dest) == ZERO_EXTRACT)
2639         {
2640           if (CONST_INT_P (XEXP (dest, 1))
2641               && CONST_INT_P (XEXP (dest, 2)))
2642             {
2643               width = INTVAL (XEXP (dest, 1));
2644               offset = INTVAL (XEXP (dest, 2));
2645               dest = XEXP (dest, 0);
2646               if (BITS_BIG_ENDIAN)
2647                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2648             }
2649         }
2650       else
2651         {
2652           if (GET_CODE (dest) == STRICT_LOW_PART)
2653             dest = XEXP (dest, 0);
2654           width = GET_MODE_PRECISION (GET_MODE (dest));
2655           offset = 0;
2656         }
2657
2658       if (offset >= 0)
2659         {
2660           /* If this is the low part, we're done.  */
2661           if (subreg_lowpart_p (dest))
2662             ;
2663           /* Handle the case where inner is twice the size of outer.  */
2664           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2665                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2666             offset += GET_MODE_PRECISION (GET_MODE (dest));
2667           /* Otherwise give up for now.  */
2668           else
2669             offset = -1;
2670         }
2671
2672       if (offset >= 0)
2673         {
2674           rtx inner = SET_SRC (PATTERN (i3));
2675           rtx outer = SET_SRC (temp);
2676
2677           wide_int o
2678             = wi::insert (std::make_pair (outer, GET_MODE (SET_DEST (temp))),
2679                           std::make_pair (inner, GET_MODE (dest)),
2680                           offset, width);
2681
2682           combine_merges++;
2683           subst_insn = i3;
2684           subst_low_luid = DF_INSN_LUID (i2);
2685           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2686           i2dest = SET_DEST (temp);
2687           i2dest_killed = dead_or_set_p (i2, i2dest);
2688
2689           /* Replace the source in I2 with the new constant and make the
2690              resulting insn the new pattern for I3.  Then skip to where we
2691              validate the pattern.  Everything was set up above.  */
2692           SUBST (SET_SRC (temp),
2693                  immed_wide_int_const (o, GET_MODE (SET_DEST (temp))));
2694
2695           newpat = PATTERN (i2);
2696
2697           /* The dest of I3 has been replaced with the dest of I2.  */
2698           changed_i3_dest = 1;
2699           goto validate_replacement;
2700         }
2701     }
2702
2703 #ifndef HAVE_cc0
2704   /* If we have no I1 and I2 looks like:
2705         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2706                    (set Y OP)])
2707      make up a dummy I1 that is
2708         (set Y OP)
2709      and change I2 to be
2710         (set (reg:CC X) (compare:CC Y (const_int 0)))
2711
2712      (We can ignore any trailing CLOBBERs.)
2713
2714      This undoes a previous combination and allows us to match a branch-and-
2715      decrement insn.  */
2716
2717   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2718       && XVECLEN (PATTERN (i2), 0) >= 2
2719       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2720       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2721           == MODE_CC)
2722       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2723       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2724       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2725       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2726       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2727                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2728     {
2729       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2730         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2731           break;
2732
2733       if (i == 1)
2734         {
2735           /* We make I1 with the same INSN_UID as I2.  This gives it
2736              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2737              never appear in the insn stream so giving it the same INSN_UID
2738              as I2 will not cause a problem.  */
2739
2740           i1 = gen_rtx_INSN (VOIDmode, NULL_RTX, i2, BLOCK_FOR_INSN (i2),
2741                              XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2742                              -1, NULL_RTX);
2743           INSN_UID (i1) = INSN_UID (i2);
2744
2745           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2746           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2747                  SET_DEST (PATTERN (i1)));
2748           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2749         }
2750     }
2751 #endif
2752
2753   /* Verify that I2 and I1 are valid for combining.  */
2754   if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2755       || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2756                                  &i1dest, &i1src))
2757       || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2758                                  &i0dest, &i0src)))
2759     {
2760       undo_all ();
2761       return 0;
2762     }
2763
2764   /* Record whether I2DEST is used in I2SRC and similarly for the other
2765      cases.  Knowing this will help in register status updating below.  */
2766   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2767   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2768   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2769   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2770   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2771   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2772   i2dest_killed = dead_or_set_p (i2, i2dest);
2773   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2774   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2775
2776   /* For the earlier insns, determine which of the subsequent ones they
2777      feed.  */
2778   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2779   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2780   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2781                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2782                              && reg_overlap_mentioned_p (i0dest, i2src))));
2783
2784   /* Ensure that I3's pattern can be the destination of combines.  */
2785   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2786                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2787                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2788                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2789                           &i3dest_killed))
2790     {
2791       undo_all ();
2792       return 0;
2793     }
2794
2795   /* See if any of the insns is a MULT operation.  Unless one is, we will
2796      reject a combination that is, since it must be slower.  Be conservative
2797      here.  */
2798   if (GET_CODE (i2src) == MULT
2799       || (i1 != 0 && GET_CODE (i1src) == MULT)
2800       || (i0 != 0 && GET_CODE (i0src) == MULT)
2801       || (GET_CODE (PATTERN (i3)) == SET
2802           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2803     have_mult = 1;
2804
2805   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2806      We used to do this EXCEPT in one case: I3 has a post-inc in an
2807      output operand.  However, that exception can give rise to insns like
2808         mov r3,(r3)+
2809      which is a famous insn on the PDP-11 where the value of r3 used as the
2810      source was model-dependent.  Avoid this sort of thing.  */
2811
2812 #if 0
2813   if (!(GET_CODE (PATTERN (i3)) == SET
2814         && REG_P (SET_SRC (PATTERN (i3)))
2815         && MEM_P (SET_DEST (PATTERN (i3)))
2816         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2817             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2818     /* It's not the exception.  */
2819 #endif
2820 #ifdef AUTO_INC_DEC
2821     {
2822       rtx link;
2823       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2824         if (REG_NOTE_KIND (link) == REG_INC
2825             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2826                 || (i1 != 0
2827                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2828           {
2829             undo_all ();
2830             return 0;
2831           }
2832     }
2833 #endif
2834
2835   /* See if the SETs in I1 or I2 need to be kept around in the merged
2836      instruction: whenever the value set there is still needed past I3.
2837      For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2838
2839      For the SET in I1, we have two cases: if I1 and I2 independently feed
2840      into I3, the set in I1 needs to be kept around unless I1DEST dies
2841      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2842      in I1 needs to be kept around unless I1DEST dies or is set in either
2843      I2 or I3.  The same considerations apply to I0.  */
2844
2845   added_sets_2 = !dead_or_set_p (i3, i2dest);
2846
2847   if (i1)
2848     added_sets_1 = !(dead_or_set_p (i3, i1dest)
2849                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2850   else
2851     added_sets_1 = 0;
2852
2853   if (i0)
2854     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
2855                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
2856                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
2857                           && dead_or_set_p (i2, i0dest)));
2858   else
2859     added_sets_0 = 0;
2860
2861   /* We are about to copy insns for the case where they need to be kept
2862      around.  Check that they can be copied in the merged instruction.  */
2863
2864   if (targetm.cannot_copy_insn_p
2865       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2866           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2867           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2868     {
2869       undo_all ();
2870       return 0;
2871     }
2872
2873   /* If the set in I2 needs to be kept around, we must make a copy of
2874      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2875      PATTERN (I2), we are only substituting for the original I1DEST, not into
2876      an already-substituted copy.  This also prevents making self-referential
2877      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2878      I2DEST.  */
2879
2880   if (added_sets_2)
2881     {
2882       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2883         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2884       else
2885         i2pat = copy_rtx (PATTERN (i2));
2886     }
2887
2888   if (added_sets_1)
2889     {
2890       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2891         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2892       else
2893         i1pat = copy_rtx (PATTERN (i1));
2894     }
2895
2896   if (added_sets_0)
2897     {
2898       if (GET_CODE (PATTERN (i0)) == PARALLEL)
2899         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2900       else
2901         i0pat = copy_rtx (PATTERN (i0));
2902     }
2903
2904   combine_merges++;
2905
2906   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2907
2908   maxreg = max_reg_num ();
2909
2910   subst_insn = i3;
2911
2912 #ifndef HAVE_cc0
2913   /* Many machines that don't use CC0 have insns that can both perform an
2914      arithmetic operation and set the condition code.  These operations will
2915      be represented as a PARALLEL with the first element of the vector
2916      being a COMPARE of an arithmetic operation with the constant zero.
2917      The second element of the vector will set some pseudo to the result
2918      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2919      match such a pattern and so will generate an extra insn.   Here we test
2920      for this case, where both the comparison and the operation result are
2921      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2922      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2923
2924   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2925       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2926       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2927       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2928     {
2929       rtx newpat_dest;
2930       rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
2931       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2932       enum machine_mode compare_mode, orig_compare_mode;
2933       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2934
2935       newpat = PATTERN (i3);
2936       newpat_dest = SET_DEST (newpat);
2937       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2938
2939       if (undobuf.other_insn == 0
2940           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2941                                             &cc_use_insn)))
2942         {
2943           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2944           compare_code = simplify_compare_const (compare_code,
2945                                                  GET_MODE (i2dest), op0, &op1);
2946           target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
2947         }
2948
2949       /* Do the rest only if op1 is const0_rtx, which may be the
2950          result of simplification.  */
2951       if (op1 == const0_rtx)
2952         {
2953           /* If a single use of the CC is found, prepare to modify it
2954              when SELECT_CC_MODE returns a new CC-class mode, or when
2955              the above simplify_compare_const() returned a new comparison
2956              operator.  undobuf.other_insn is assigned the CC use insn
2957              when modifying it.  */
2958           if (cc_use_loc)
2959             {
2960 #ifdef SELECT_CC_MODE
2961               enum machine_mode new_mode
2962                 = SELECT_CC_MODE (compare_code, op0, op1);
2963               if (new_mode != orig_compare_mode
2964                   && can_change_dest_mode (SET_DEST (newpat),
2965                                            added_sets_2, new_mode))
2966                 {
2967                   unsigned int regno = REGNO (newpat_dest);
2968                   compare_mode = new_mode;
2969                   if (regno < FIRST_PSEUDO_REGISTER)
2970                     newpat_dest = gen_rtx_REG (compare_mode, regno);
2971                   else
2972                     {
2973                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2974                       newpat_dest = regno_reg_rtx[regno];
2975                     }
2976                 }
2977 #endif
2978               /* Cases for modifying the CC-using comparison.  */
2979               if (compare_code != orig_compare_code
2980                   /* ??? Do we need to verify the zero rtx?  */
2981                   && XEXP (*cc_use_loc, 1) == const0_rtx)
2982                 {
2983                   /* Replace cc_use_loc with entire new RTX.  */
2984                   SUBST (*cc_use_loc,
2985                          gen_rtx_fmt_ee (compare_code, compare_mode,
2986                                          newpat_dest, const0_rtx));
2987                   undobuf.other_insn = cc_use_insn;
2988                 }
2989               else if (compare_mode != orig_compare_mode)
2990                 {
2991                   /* Just replace the CC reg with a new mode.  */
2992                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
2993                   undobuf.other_insn = cc_use_insn;
2994                 }
2995             }
2996
2997           /* Now we modify the current newpat:
2998              First, SET_DEST(newpat) is updated if the CC mode has been
2999              altered. For targets without SELECT_CC_MODE, this should be
3000              optimized away.  */
3001           if (compare_mode != orig_compare_mode)
3002             SUBST (SET_DEST (newpat), newpat_dest);
3003           /* This is always done to propagate i2src into newpat.  */
3004           SUBST (SET_SRC (newpat),
3005                  gen_rtx_COMPARE (compare_mode, op0, op1));
3006           /* Create new version of i2pat if needed; the below PARALLEL
3007              creation needs this to work correctly.  */
3008           if (! rtx_equal_p (i2src, op0))
3009             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3010           i2_is_used = 1;
3011         }
3012     }
3013 #endif
3014
3015   if (i2_is_used == 0)
3016     {
3017       /* It is possible that the source of I2 or I1 may be performing
3018          an unneeded operation, such as a ZERO_EXTEND of something
3019          that is known to have the high part zero.  Handle that case
3020          by letting subst look at the inner insns.
3021
3022          Another way to do this would be to have a function that tries
3023          to simplify a single insn instead of merging two or more
3024          insns.  We don't do this because of the potential of infinite
3025          loops and because of the potential extra memory required.
3026          However, doing it the way we are is a bit of a kludge and
3027          doesn't catch all cases.
3028
3029          But only do this if -fexpensive-optimizations since it slows
3030          things down and doesn't usually win.
3031
3032          This is not done in the COMPARE case above because the
3033          unmodified I2PAT is used in the PARALLEL and so a pattern
3034          with a modified I2SRC would not match.  */
3035
3036       if (flag_expensive_optimizations)
3037         {
3038           /* Pass pc_rtx so no substitutions are done, just
3039              simplifications.  */
3040           if (i1)
3041             {
3042               subst_low_luid = DF_INSN_LUID (i1);
3043               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3044             }
3045
3046           subst_low_luid = DF_INSN_LUID (i2);
3047           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3048         }
3049
3050       n_occurrences = 0;                /* `subst' counts here */
3051       subst_low_luid = DF_INSN_LUID (i2);
3052
3053       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3054          copy of I2SRC each time we substitute it, in order to avoid creating
3055          self-referential RTL when we will be substituting I1SRC for I1DEST
3056          later.  Likewise if I0 feeds into I2, either directly or indirectly
3057          through I1, and I0DEST is in I0SRC.  */
3058       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3059                       (i1_feeds_i2_n && i1dest_in_i1src)
3060                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3061                           && i0dest_in_i0src));
3062       substed_i2 = 1;
3063
3064       /* Record whether I2's body now appears within I3's body.  */
3065       i2_is_used = n_occurrences;
3066     }
3067
3068   /* If we already got a failure, don't try to do more.  Otherwise, try to
3069      substitute I1 if we have it.  */
3070
3071   if (i1 && GET_CODE (newpat) != CLOBBER)
3072     {
3073       /* Check that an autoincrement side-effect on I1 has not been lost.
3074          This happens if I1DEST is mentioned in I2 and dies there, and
3075          has disappeared from the new pattern.  */
3076       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3077            && i1_feeds_i2_n
3078            && dead_or_set_p (i2, i1dest)
3079            && !reg_overlap_mentioned_p (i1dest, newpat))
3080            /* Before we can do this substitution, we must redo the test done
3081               above (see detailed comments there) that ensures I1DEST isn't
3082               mentioned in any SETs in NEWPAT that are field assignments.  */
3083           || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3084                                 0, 0, 0))
3085         {
3086           undo_all ();
3087           return 0;
3088         }
3089
3090       n_occurrences = 0;
3091       subst_low_luid = DF_INSN_LUID (i1);
3092
3093       /* If the following substitution will modify I1SRC, make a copy of it
3094          for the case where it is substituted for I1DEST in I2PAT later.  */
3095       if (added_sets_2 && i1_feeds_i2_n)
3096         i1src_copy = copy_rtx (i1src);
3097
3098       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3099          copy of I1SRC each time we substitute it, in order to avoid creating
3100          self-referential RTL when we will be substituting I0SRC for I0DEST
3101          later.  */
3102       newpat = subst (newpat, i1dest, i1src, 0, 0,
3103                       i0_feeds_i1_n && i0dest_in_i0src);
3104       substed_i1 = 1;
3105
3106       /* Record whether I1's body now appears within I3's body.  */
3107       i1_is_used = n_occurrences;
3108     }
3109
3110   /* Likewise for I0 if we have it.  */
3111
3112   if (i0 && GET_CODE (newpat) != CLOBBER)
3113     {
3114       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3115            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3116                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3117            && !reg_overlap_mentioned_p (i0dest, newpat))
3118           || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3119                                 0, 0, 0))
3120         {
3121           undo_all ();
3122           return 0;
3123         }
3124
3125       /* If the following substitution will modify I0SRC, make a copy of it
3126          for the case where it is substituted for I0DEST in I1PAT later.  */
3127       if (added_sets_1 && i0_feeds_i1_n)
3128         i0src_copy = copy_rtx (i0src);
3129       /* And a copy for I0DEST in I2PAT substitution.  */
3130       if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3131                            || (i0_feeds_i2_n)))
3132         i0src_copy2 = copy_rtx (i0src);
3133
3134       n_occurrences = 0;
3135       subst_low_luid = DF_INSN_LUID (i0);
3136       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3137       substed_i0 = 1;
3138     }
3139
3140   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3141      to count all the ways that I2SRC and I1SRC can be used.  */
3142   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3143        && i2_is_used + added_sets_2 > 1)
3144       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3145           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3146               > 1))
3147       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3148           && (n_occurrences + added_sets_0
3149               + (added_sets_1 && i0_feeds_i1_n)
3150               + (added_sets_2 && i0_feeds_i2_n)
3151               > 1))
3152       /* Fail if we tried to make a new register.  */
3153       || max_reg_num () != maxreg
3154       /* Fail if we couldn't do something and have a CLOBBER.  */
3155       || GET_CODE (newpat) == CLOBBER
3156       /* Fail if this new pattern is a MULT and we didn't have one before
3157          at the outer level.  */
3158       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3159           && ! have_mult))
3160     {
3161       undo_all ();
3162       return 0;
3163     }
3164
3165   /* If the actions of the earlier insns must be kept
3166      in addition to substituting them into the latest one,
3167      we must make a new PARALLEL for the latest insn
3168      to hold additional the SETs.  */
3169
3170   if (added_sets_0 || added_sets_1 || added_sets_2)
3171     {
3172       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3173       combine_extras++;
3174
3175       if (GET_CODE (newpat) == PARALLEL)
3176         {
3177           rtvec old = XVEC (newpat, 0);
3178           total_sets = XVECLEN (newpat, 0) + extra_sets;
3179           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3180           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3181                   sizeof (old->elem[0]) * old->num_elem);
3182         }
3183       else
3184         {
3185           rtx old = newpat;
3186           total_sets = 1 + extra_sets;
3187           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3188           XVECEXP (newpat, 0, 0) = old;
3189         }
3190
3191       if (added_sets_0)
3192         XVECEXP (newpat, 0, --total_sets) = i0pat;
3193
3194       if (added_sets_1)
3195         {
3196           rtx t = i1pat;
3197           if (i0_feeds_i1_n)
3198             t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3199
3200           XVECEXP (newpat, 0, --total_sets) = t;
3201         }
3202       if (added_sets_2)
3203         {
3204           rtx t = i2pat;
3205           if (i1_feeds_i2_n)
3206             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3207                        i0_feeds_i1_n && i0dest_in_i0src);
3208           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3209             t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3210
3211           XVECEXP (newpat, 0, --total_sets) = t;
3212         }
3213     }
3214
3215  validate_replacement:
3216
3217   /* Note which hard regs this insn has as inputs.  */
3218   mark_used_regs_combine (newpat);
3219
3220   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3221      consider splitting this pattern, we might need these clobbers.  */
3222   if (i1 && GET_CODE (newpat) == PARALLEL
3223       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3224     {
3225       int len = XVECLEN (newpat, 0);
3226
3227       newpat_vec_with_clobbers = rtvec_alloc (len);
3228       for (i = 0; i < len; i++)
3229         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3230     }
3231
3232   /* Is the result of combination a valid instruction?  */
3233   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3234
3235   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3236      the second SET's destination is a register that is unused and isn't
3237      marked as an instruction that might trap in an EH region.  In that case,
3238      we just need the first SET.   This can occur when simplifying a divmod
3239      insn.  We *must* test for this case here because the code below that
3240      splits two independent SETs doesn't handle this case correctly when it
3241      updates the register status.
3242
3243      It's pointless doing this if we originally had two sets, one from
3244      i3, and one from i2.  Combining then splitting the parallel results
3245      in the original i2 again plus an invalid insn (which we delete).
3246      The net effect is only to move instructions around, which makes
3247      debug info less accurate.
3248
3249      Also check the case where the first SET's destination is unused.
3250      That would not cause incorrect code, but does cause an unneeded
3251      insn to remain.  */
3252
3253   if (insn_code_number < 0
3254       && !(added_sets_2 && i1 == 0)
3255       && GET_CODE (newpat) == PARALLEL
3256       && XVECLEN (newpat, 0) == 2
3257       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3258       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3259       && asm_noperands (newpat) < 0)
3260     {
3261       rtx set0 = XVECEXP (newpat, 0, 0);
3262       rtx set1 = XVECEXP (newpat, 0, 1);
3263
3264       if (((REG_P (SET_DEST (set1))
3265             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3266            || (GET_CODE (SET_DEST (set1)) == SUBREG
3267                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3268           && insn_nothrow_p (i3)
3269           && !side_effects_p (SET_SRC (set1)))
3270         {
3271           newpat = set0;
3272           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3273         }
3274
3275       else if (((REG_P (SET_DEST (set0))
3276                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3277                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3278                     && find_reg_note (i3, REG_UNUSED,
3279                                       SUBREG_REG (SET_DEST (set0)))))
3280                && insn_nothrow_p (i3)
3281                && !side_effects_p (SET_SRC (set0)))
3282         {
3283           newpat = set1;
3284           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3285
3286           if (insn_code_number >= 0)
3287             changed_i3_dest = 1;
3288         }
3289     }
3290
3291   /* If we were combining three insns and the result is a simple SET
3292      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3293      insns.  There are two ways to do this.  It can be split using a
3294      machine-specific method (like when you have an addition of a large
3295      constant) or by combine in the function find_split_point.  */
3296
3297   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3298       && asm_noperands (newpat) < 0)
3299     {
3300       rtx parallel, m_split, *split;
3301
3302       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3303          use I2DEST as a scratch register will help.  In the latter case,
3304          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3305
3306       m_split = combine_split_insns (newpat, i3);
3307
3308       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3309          inputs of NEWPAT.  */
3310
3311       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3312          possible to try that as a scratch reg.  This would require adding
3313          more code to make it work though.  */
3314
3315       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3316         {
3317           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3318
3319           /* First try to split using the original register as a
3320              scratch register.  */
3321           parallel = gen_rtx_PARALLEL (VOIDmode,
3322                                        gen_rtvec (2, newpat,
3323                                                   gen_rtx_CLOBBER (VOIDmode,
3324                                                                    i2dest)));
3325           m_split = combine_split_insns (parallel, i3);
3326
3327           /* If that didn't work, try changing the mode of I2DEST if
3328              we can.  */
3329           if (m_split == 0
3330               && new_mode != GET_MODE (i2dest)
3331               && new_mode != VOIDmode
3332               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3333             {
3334               enum machine_mode old_mode = GET_MODE (i2dest);
3335               rtx ni2dest;
3336
3337               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3338                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3339               else
3340                 {
3341                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3342                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3343                 }
3344
3345               parallel = (gen_rtx_PARALLEL
3346                           (VOIDmode,
3347                            gen_rtvec (2, newpat,
3348                                       gen_rtx_CLOBBER (VOIDmode,
3349                                                        ni2dest))));
3350               m_split = combine_split_insns (parallel, i3);
3351
3352               if (m_split == 0
3353                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3354                 {
3355                   struct undo *buf;
3356
3357                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3358                   buf = undobuf.undos;
3359                   undobuf.undos = buf->next;
3360                   buf->next = undobuf.frees;
3361                   undobuf.frees = buf;
3362                 }
3363             }
3364
3365           i2scratch = m_split != 0;
3366         }
3367
3368       /* If recog_for_combine has discarded clobbers, try to use them
3369          again for the split.  */
3370       if (m_split == 0 && newpat_vec_with_clobbers)
3371         {
3372           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3373           m_split = combine_split_insns (parallel, i3);
3374         }
3375
3376       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3377         {
3378           m_split = PATTERN (m_split);
3379           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3380           if (insn_code_number >= 0)
3381             newpat = m_split;
3382         }
3383       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3384                && (next_nonnote_nondebug_insn (i2) == i3
3385                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3386         {
3387           rtx i2set, i3set;
3388           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3389           newi2pat = PATTERN (m_split);
3390
3391           i3set = single_set (NEXT_INSN (m_split));
3392           i2set = single_set (m_split);
3393
3394           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3395
3396           /* If I2 or I3 has multiple SETs, we won't know how to track
3397              register status, so don't use these insns.  If I2's destination
3398              is used between I2 and I3, we also can't use these insns.  */
3399
3400           if (i2_code_number >= 0 && i2set && i3set
3401               && (next_nonnote_nondebug_insn (i2) == i3
3402                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3403             insn_code_number = recog_for_combine (&newi3pat, i3,
3404                                                   &new_i3_notes);
3405           if (insn_code_number >= 0)
3406             newpat = newi3pat;
3407
3408           /* It is possible that both insns now set the destination of I3.
3409              If so, we must show an extra use of it.  */
3410
3411           if (insn_code_number >= 0)
3412             {
3413               rtx new_i3_dest = SET_DEST (i3set);
3414               rtx new_i2_dest = SET_DEST (i2set);
3415
3416               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3417                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3418                      || GET_CODE (new_i3_dest) == SUBREG)
3419                 new_i3_dest = XEXP (new_i3_dest, 0);
3420
3421               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3422                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3423                      || GET_CODE (new_i2_dest) == SUBREG)
3424                 new_i2_dest = XEXP (new_i2_dest, 0);
3425
3426               if (REG_P (new_i3_dest)
3427                   && REG_P (new_i2_dest)
3428                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3429                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3430             }
3431         }
3432
3433       /* If we can split it and use I2DEST, go ahead and see if that
3434          helps things be recognized.  Verify that none of the registers
3435          are set between I2 and I3.  */
3436       if (insn_code_number < 0
3437           && (split = find_split_point (&newpat, i3, false)) != 0
3438 #ifdef HAVE_cc0
3439           && REG_P (i2dest)
3440 #endif
3441           /* We need I2DEST in the proper mode.  If it is a hard register
3442              or the only use of a pseudo, we can change its mode.
3443              Make sure we don't change a hard register to have a mode that
3444              isn't valid for it, or change the number of registers.  */
3445           && (GET_MODE (*split) == GET_MODE (i2dest)
3446               || GET_MODE (*split) == VOIDmode
3447               || can_change_dest_mode (i2dest, added_sets_2,
3448                                        GET_MODE (*split)))
3449           && (next_nonnote_nondebug_insn (i2) == i3
3450               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3451           /* We can't overwrite I2DEST if its value is still used by
3452              NEWPAT.  */
3453           && ! reg_referenced_p (i2dest, newpat))
3454         {
3455           rtx newdest = i2dest;
3456           enum rtx_code split_code = GET_CODE (*split);
3457           enum machine_mode split_mode = GET_MODE (*split);
3458           bool subst_done = false;
3459           newi2pat = NULL_RTX;
3460
3461           i2scratch = true;
3462
3463           /* *SPLIT may be part of I2SRC, so make sure we have the
3464              original expression around for later debug processing.
3465              We should not need I2SRC any more in other cases.  */
3466           if (MAY_HAVE_DEBUG_INSNS)
3467             i2src = copy_rtx (i2src);
3468           else
3469             i2src = NULL;
3470
3471           /* Get NEWDEST as a register in the proper mode.  We have already
3472              validated that we can do this.  */
3473           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3474             {
3475               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3476                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3477               else
3478                 {
3479                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3480                   newdest = regno_reg_rtx[REGNO (i2dest)];
3481                 }
3482             }
3483
3484           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3485              an ASHIFT.  This can occur if it was inside a PLUS and hence
3486              appeared to be a memory address.  This is a kludge.  */
3487           if (split_code == MULT
3488               && CONST_INT_P (XEXP (*split, 1))
3489               && INTVAL (XEXP (*split, 1)) > 0
3490               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3491             {
3492               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3493                                              XEXP (*split, 0), GEN_INT (i)));
3494               /* Update split_code because we may not have a multiply
3495                  anymore.  */
3496               split_code = GET_CODE (*split);
3497             }
3498
3499 #ifdef INSN_SCHEDULING
3500           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3501              be written as a ZERO_EXTEND.  */
3502           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3503             {
3504 #ifdef LOAD_EXTEND_OP
3505               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3506                  what it really is.  */
3507               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3508                   == SIGN_EXTEND)
3509                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3510                                                     SUBREG_REG (*split)));
3511               else
3512 #endif
3513                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3514                                                     SUBREG_REG (*split)));
3515             }
3516 #endif
3517
3518           /* Attempt to split binary operators using arithmetic identities.  */
3519           if (BINARY_P (SET_SRC (newpat))
3520               && split_mode == GET_MODE (SET_SRC (newpat))
3521               && ! side_effects_p (SET_SRC (newpat)))
3522             {
3523               rtx setsrc = SET_SRC (newpat);
3524               enum machine_mode mode = GET_MODE (setsrc);
3525               enum rtx_code code = GET_CODE (setsrc);
3526               rtx src_op0 = XEXP (setsrc, 0);
3527               rtx src_op1 = XEXP (setsrc, 1);
3528
3529               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3530               if (rtx_equal_p (src_op0, src_op1))
3531                 {
3532                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3533                   SUBST (XEXP (setsrc, 0), newdest);
3534                   SUBST (XEXP (setsrc, 1), newdest);
3535                   subst_done = true;
3536                 }
3537               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3538               else if ((code == PLUS || code == MULT)
3539                        && GET_CODE (src_op0) == code
3540                        && GET_CODE (XEXP (src_op0, 0)) == code
3541                        && (INTEGRAL_MODE_P (mode)
3542                            || (FLOAT_MODE_P (mode)
3543                                && flag_unsafe_math_optimizations)))
3544                 {
3545                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3546                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3547                   rtx r = XEXP (src_op0, 1);
3548                   rtx s = src_op1;
3549
3550                   /* Split both "((X op Y) op X) op Y" and
3551                      "((X op Y) op Y) op X" as "T op T" where T is
3552                      "X op Y".  */
3553                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3554                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3555                     {
3556                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3557                                               XEXP (src_op0, 0));
3558                       SUBST (XEXP (setsrc, 0), newdest);
3559                       SUBST (XEXP (setsrc, 1), newdest);
3560                       subst_done = true;
3561                     }
3562                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3563                      T is "X op Y".  */
3564                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3565                     {
3566                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3567                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3568                       SUBST (XEXP (setsrc, 0), newdest);
3569                       SUBST (XEXP (setsrc, 1), newdest);
3570                       subst_done = true;
3571                     }
3572                 }
3573             }
3574
3575           if (!subst_done)
3576             {
3577               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3578               SUBST (*split, newdest);
3579             }
3580
3581           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3582
3583           /* recog_for_combine might have added CLOBBERs to newi2pat.
3584              Make sure NEWPAT does not depend on the clobbered regs.  */
3585           if (GET_CODE (newi2pat) == PARALLEL)
3586             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3587               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3588                 {
3589                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3590                   if (reg_overlap_mentioned_p (reg, newpat))
3591                     {
3592                       undo_all ();
3593                       return 0;
3594                     }
3595                 }
3596
3597           /* If the split point was a MULT and we didn't have one before,
3598              don't use one now.  */
3599           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3600             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3601         }
3602     }
3603
3604   /* Check for a case where we loaded from memory in a narrow mode and
3605      then sign extended it, but we need both registers.  In that case,
3606      we have a PARALLEL with both loads from the same memory location.
3607      We can split this into a load from memory followed by a register-register
3608      copy.  This saves at least one insn, more if register allocation can
3609      eliminate the copy.
3610
3611      We cannot do this if the destination of the first assignment is a
3612      condition code register or cc0.  We eliminate this case by making sure
3613      the SET_DEST and SET_SRC have the same mode.
3614
3615      We cannot do this if the destination of the second assignment is
3616      a register that we have already assumed is zero-extended.  Similarly
3617      for a SUBREG of such a register.  */
3618
3619   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3620            && GET_CODE (newpat) == PARALLEL
3621            && XVECLEN (newpat, 0) == 2
3622            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3623            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3624            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3625                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3626            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3627            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3628                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3629            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3630                                    DF_INSN_LUID (i2))
3631            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3632            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3633            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3634                  (REG_P (temp)
3635                   && reg_stat[REGNO (temp)].nonzero_bits != 0
3636                   && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3637                   && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3638                   && (reg_stat[REGNO (temp)].nonzero_bits
3639                       != GET_MODE_MASK (word_mode))))
3640            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3641                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3642                      (REG_P (temp)
3643                       && reg_stat[REGNO (temp)].nonzero_bits != 0
3644                       && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3645                       && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3646                       && (reg_stat[REGNO (temp)].nonzero_bits
3647                           != GET_MODE_MASK (word_mode)))))
3648            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3649                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3650            && ! find_reg_note (i3, REG_UNUSED,
3651                                SET_DEST (XVECEXP (newpat, 0, 0))))
3652     {
3653       rtx ni2dest;
3654
3655       newi2pat = XVECEXP (newpat, 0, 0);
3656       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3657       newpat = XVECEXP (newpat, 0, 1);
3658       SUBST (SET_SRC (newpat),
3659              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3660       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3661
3662       if (i2_code_number >= 0)
3663         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3664
3665       if (insn_code_number >= 0)
3666         swap_i2i3 = 1;
3667     }
3668
3669   /* Similarly, check for a case where we have a PARALLEL of two independent
3670      SETs but we started with three insns.  In this case, we can do the sets
3671      as two separate insns.  This case occurs when some SET allows two
3672      other insns to combine, but the destination of that SET is still live.  */
3673
3674   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3675            && GET_CODE (newpat) == PARALLEL
3676            && XVECLEN (newpat, 0) == 2
3677            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3678            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3679            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3680            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3681            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3682            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3683            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3684                                   XVECEXP (newpat, 0, 0))
3685            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3686                                   XVECEXP (newpat, 0, 1))
3687            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3688                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3689     {
3690       rtx set0 = XVECEXP (newpat, 0, 0);
3691       rtx set1 = XVECEXP (newpat, 0, 1);
3692
3693       /* Normally, it doesn't matter which of the two is done first,
3694          but the one that references cc0 can't be the second, and
3695          one which uses any regs/memory set in between i2 and i3 can't
3696          be first.  The PARALLEL might also have been pre-existing in i3,
3697          so we need to make sure that we won't wrongly hoist a SET to i2
3698          that would conflict with a death note present in there.  */
3699       if (!use_crosses_set_p (SET_SRC (set1), DF_INSN_LUID (i2))
3700           && !(REG_P (SET_DEST (set1))
3701                && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
3702           && !(GET_CODE (SET_DEST (set1)) == SUBREG
3703                && find_reg_note (i2, REG_DEAD,
3704                                  SUBREG_REG (SET_DEST (set1))))
3705 #ifdef HAVE_cc0
3706           && !reg_referenced_p (cc0_rtx, set0)
3707 #endif
3708           /* If I3 is a jump, ensure that set0 is a jump so that
3709              we do not create invalid RTL.  */
3710           && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx)
3711          )
3712         {
3713           newi2pat = set1;
3714           newpat = set0;
3715         }
3716       else if (!use_crosses_set_p (SET_SRC (set0), DF_INSN_LUID (i2))
3717                && !(REG_P (SET_DEST (set0))
3718                     && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
3719                && !(GET_CODE (SET_DEST (set0)) == SUBREG
3720                     && find_reg_note (i2, REG_DEAD,
3721                                       SUBREG_REG (SET_DEST (set0))))
3722 #ifdef HAVE_cc0
3723                && !reg_referenced_p (cc0_rtx, set1)
3724 #endif
3725                /* If I3 is a jump, ensure that set1 is a jump so that
3726                   we do not create invalid RTL.  */
3727                && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx)
3728               )
3729         {
3730           newi2pat = set0;
3731           newpat = set1;
3732         }
3733       else
3734         {
3735           undo_all ();
3736           return 0;
3737         }
3738
3739       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3740
3741       if (i2_code_number >= 0)
3742         {
3743           /* recog_for_combine might have added CLOBBERs to newi2pat.
3744              Make sure NEWPAT does not depend on the clobbered regs.  */
3745           if (GET_CODE (newi2pat) == PARALLEL)
3746             {
3747               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3748                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3749                   {
3750                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3751                     if (reg_overlap_mentioned_p (reg, newpat))
3752                       {
3753                         undo_all ();
3754                         return 0;
3755                       }
3756                   }
3757             }
3758
3759           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3760         }
3761     }
3762
3763   /* If it still isn't recognized, fail and change things back the way they
3764      were.  */
3765   if ((insn_code_number < 0
3766        /* Is the result a reasonable ASM_OPERANDS?  */
3767        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3768     {
3769       undo_all ();
3770       return 0;
3771     }
3772
3773   /* If we had to change another insn, make sure it is valid also.  */
3774   if (undobuf.other_insn)
3775     {
3776       CLEAR_HARD_REG_SET (newpat_used_regs);
3777
3778       other_pat = PATTERN (undobuf.other_insn);
3779       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3780                                              &new_other_notes);
3781
3782       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3783         {
3784           undo_all ();
3785           return 0;
3786         }
3787     }
3788
3789 #ifdef HAVE_cc0
3790   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3791      they are adjacent to each other or not.  */
3792   {
3793     rtx p = prev_nonnote_insn (i3);
3794     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3795         && sets_cc0_p (newi2pat))
3796       {
3797         undo_all ();
3798         return 0;
3799       }
3800   }
3801 #endif
3802
3803   /* Only allow this combination if insn_rtx_costs reports that the
3804      replacement instructions are cheaper than the originals.  */
3805   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3806     {
3807       undo_all ();
3808       return 0;
3809     }
3810
3811   if (MAY_HAVE_DEBUG_INSNS)
3812     {
3813       struct undo *undo;
3814
3815       for (undo = undobuf.undos; undo; undo = undo->next)
3816         if (undo->kind == UNDO_MODE)
3817           {
3818             rtx reg = *undo->where.r;
3819             enum machine_mode new_mode = GET_MODE (reg);
3820             enum machine_mode old_mode = undo->old_contents.m;
3821
3822             /* Temporarily revert mode back.  */
3823             adjust_reg_mode (reg, old_mode);
3824
3825             if (reg == i2dest && i2scratch)
3826               {
3827                 /* If we used i2dest as a scratch register with a
3828                    different mode, substitute it for the original
3829                    i2src while its original mode is temporarily
3830                    restored, and then clear i2scratch so that we don't
3831                    do it again later.  */
3832                 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3833                                      this_basic_block);
3834                 i2scratch = false;
3835                 /* Put back the new mode.  */
3836                 adjust_reg_mode (reg, new_mode);
3837               }
3838             else
3839               {
3840                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3841                 rtx first, last;
3842
3843                 if (reg == i2dest)
3844                   {
3845                     first = i2;
3846                     last = last_combined_insn;
3847                   }
3848                 else
3849                   {
3850                     first = i3;
3851                     last = undobuf.other_insn;
3852                     gcc_assert (last);
3853                     if (DF_INSN_LUID (last)
3854                         < DF_INSN_LUID (last_combined_insn))
3855                       last = last_combined_insn;
3856                   }
3857
3858                 /* We're dealing with a reg that changed mode but not
3859                    meaning, so we want to turn it into a subreg for
3860                    the new mode.  However, because of REG sharing and
3861                    because its mode had already changed, we have to do
3862                    it in two steps.  First, replace any debug uses of
3863                    reg, with its original mode temporarily restored,
3864                    with this copy we have created; then, replace the
3865                    copy with the SUBREG of the original shared reg,
3866                    once again changed to the new mode.  */
3867                 propagate_for_debug (first, last, reg, tempreg,
3868                                      this_basic_block);
3869                 adjust_reg_mode (reg, new_mode);
3870                 propagate_for_debug (first, last, tempreg,
3871                                      lowpart_subreg (old_mode, reg, new_mode),
3872                                      this_basic_block);
3873               }
3874           }
3875     }
3876
3877   /* If we will be able to accept this, we have made a
3878      change to the destination of I3.  This requires us to
3879      do a few adjustments.  */
3880
3881   if (changed_i3_dest)
3882     {
3883       PATTERN (i3) = newpat;
3884       adjust_for_new_dest (i3);
3885     }
3886
3887   /* We now know that we can do this combination.  Merge the insns and
3888      update the status of registers and LOG_LINKS.  */
3889
3890   if (undobuf.other_insn)
3891     {
3892       rtx note, next;
3893
3894       PATTERN (undobuf.other_insn) = other_pat;
3895
3896       /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
3897          ensure that they are still valid.  Then add any non-duplicate
3898          notes added by recog_for_combine.  */
3899       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3900         {
3901           next = XEXP (note, 1);
3902
3903           if ((REG_NOTE_KIND (note) == REG_DEAD
3904                && !reg_referenced_p (XEXP (note, 0),
3905                                      PATTERN (undobuf.other_insn)))
3906               ||(REG_NOTE_KIND (note) == REG_UNUSED
3907                  && !reg_set_p (XEXP (note, 0),
3908                                 PATTERN (undobuf.other_insn))))
3909             remove_note (undobuf.other_insn, note);
3910         }
3911
3912       distribute_notes (new_other_notes, undobuf.other_insn,
3913                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3914                         NULL_RTX);
3915     }
3916
3917   if (swap_i2i3)
3918     {
3919       rtx insn;
3920       struct insn_link *link;
3921       rtx ni2dest;
3922
3923       /* I3 now uses what used to be its destination and which is now
3924          I2's destination.  This requires us to do a few adjustments.  */
3925       PATTERN (i3) = newpat;
3926       adjust_for_new_dest (i3);
3927
3928       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3929          so we still will.
3930
3931          However, some later insn might be using I2's dest and have
3932          a LOG_LINK pointing at I3.  We must remove this link.
3933          The simplest way to remove the link is to point it at I1,
3934          which we know will be a NOTE.  */
3935
3936       /* newi2pat is usually a SET here; however, recog_for_combine might
3937          have added some clobbers.  */
3938       if (GET_CODE (newi2pat) == PARALLEL)
3939         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3940       else
3941         ni2dest = SET_DEST (newi2pat);
3942
3943       for (insn = NEXT_INSN (i3);
3944            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
3945                     || insn != BB_HEAD (this_basic_block->next_bb));
3946            insn = NEXT_INSN (insn))
3947         {
3948           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3949             {
3950               FOR_EACH_LOG_LINK (link, insn)
3951                 if (link->insn == i3)
3952                   link->insn = i1;
3953
3954               break;
3955             }
3956         }
3957     }
3958
3959   {
3960     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3961     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
3962     rtx midnotes = 0;
3963     int from_luid;
3964     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3965        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3966        same as i3dest, in which case newi2pat may be setting i1dest.  */
3967     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3968                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3969                    || !i2dest_killed
3970                    ? 0 : i2dest);
3971     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3972                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3973                    || !i1dest_killed
3974                    ? 0 : i1dest);
3975     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3976                    || (newi2pat && reg_set_p (i0dest, newi2pat))
3977                    || !i0dest_killed
3978                    ? 0 : i0dest);
3979
3980     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3981        clear them.  */
3982     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3983     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3984     if (i1)
3985       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3986     if (i0)
3987       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
3988
3989     /* Ensure that we do not have something that should not be shared but
3990        occurs multiple times in the new insns.  Check this by first
3991        resetting all the `used' flags and then copying anything is shared.  */
3992
3993     reset_used_flags (i3notes);
3994     reset_used_flags (i2notes);
3995     reset_used_flags (i1notes);
3996     reset_used_flags (i0notes);
3997     reset_used_flags (newpat);
3998     reset_used_flags (newi2pat);
3999     if (undobuf.other_insn)
4000       reset_used_flags (PATTERN (undobuf.other_insn));
4001
4002     i3notes = copy_rtx_if_shared (i3notes);
4003     i2notes = copy_rtx_if_shared (i2notes);
4004     i1notes = copy_rtx_if_shared (i1notes);
4005     i0notes = copy_rtx_if_shared (i0notes);
4006     newpat = copy_rtx_if_shared (newpat);
4007     newi2pat = copy_rtx_if_shared (newi2pat);
4008     if (undobuf.other_insn)
4009       reset_used_flags (PATTERN (undobuf.other_insn));
4010
4011     INSN_CODE (i3) = insn_code_number;
4012     PATTERN (i3) = newpat;
4013
4014     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4015       {
4016         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4017
4018         reset_used_flags (call_usage);
4019         call_usage = copy_rtx (call_usage);
4020
4021         if (substed_i2)
4022           {
4023             /* I2SRC must still be meaningful at this point.  Some splitting
4024                operations can invalidate I2SRC, but those operations do not
4025                apply to calls.  */
4026             gcc_assert (i2src);
4027             replace_rtx (call_usage, i2dest, i2src);
4028           }
4029
4030         if (substed_i1)
4031           replace_rtx (call_usage, i1dest, i1src);
4032         if (substed_i0)
4033           replace_rtx (call_usage, i0dest, i0src);
4034
4035         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4036       }
4037
4038     if (undobuf.other_insn)
4039       INSN_CODE (undobuf.other_insn) = other_code_number;
4040
4041     /* We had one special case above where I2 had more than one set and
4042        we replaced a destination of one of those sets with the destination
4043        of I3.  In that case, we have to update LOG_LINKS of insns later
4044        in this basic block.  Note that this (expensive) case is rare.
4045
4046        Also, in this case, we must pretend that all REG_NOTEs for I2
4047        actually came from I3, so that REG_UNUSED notes from I2 will be
4048        properly handled.  */
4049
4050     if (i3_subst_into_i2)
4051       {
4052         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4053           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4054                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4055               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4056               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4057               && ! find_reg_note (i2, REG_UNUSED,
4058                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4059             for (temp = NEXT_INSN (i2);
4060                  temp
4061                  && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4062                           || BB_HEAD (this_basic_block) != temp);
4063                  temp = NEXT_INSN (temp))
4064               if (temp != i3 && INSN_P (temp))
4065                 FOR_EACH_LOG_LINK (link, temp)
4066                   if (link->insn == i2)
4067                     link->insn = i3;
4068
4069         if (i3notes)
4070           {
4071             rtx link = i3notes;
4072             while (XEXP (link, 1))
4073               link = XEXP (link, 1);
4074             XEXP (link, 1) = i2notes;
4075           }
4076         else
4077           i3notes = i2notes;
4078         i2notes = 0;
4079       }
4080
4081     LOG_LINKS (i3) = NULL;
4082     REG_NOTES (i3) = 0;
4083     LOG_LINKS (i2) = NULL;
4084     REG_NOTES (i2) = 0;
4085
4086     if (newi2pat)
4087       {
4088         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4089           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4090                                this_basic_block);
4091         INSN_CODE (i2) = i2_code_number;
4092         PATTERN (i2) = newi2pat;
4093       }
4094     else
4095       {
4096         if (MAY_HAVE_DEBUG_INSNS && i2src)
4097           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4098                                this_basic_block);
4099         SET_INSN_DELETED (i2);
4100       }
4101
4102     if (i1)
4103       {
4104         LOG_LINKS (i1) = NULL;
4105         REG_NOTES (i1) = 0;
4106         if (MAY_HAVE_DEBUG_INSNS)
4107           propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4108                                this_basic_block);
4109         SET_INSN_DELETED (i1);
4110       }
4111
4112     if (i0)
4113       {
4114         LOG_LINKS (i0) = NULL;
4115         REG_NOTES (i0) = 0;
4116         if (MAY_HAVE_DEBUG_INSNS)
4117           propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4118                                this_basic_block);
4119         SET_INSN_DELETED (i0);
4120       }
4121
4122     /* Get death notes for everything that is now used in either I3 or
4123        I2 and used to die in a previous insn.  If we built two new
4124        patterns, move from I1 to I2 then I2 to I3 so that we get the
4125        proper movement on registers that I2 modifies.  */
4126
4127     if (i0)
4128       from_luid = DF_INSN_LUID (i0);
4129     else if (i1)
4130       from_luid = DF_INSN_LUID (i1);
4131     else
4132       from_luid = DF_INSN_LUID (i2);
4133     if (newi2pat)
4134       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4135     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4136
4137     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4138     if (i3notes)
4139       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4140                         elim_i2, elim_i1, elim_i0);
4141     if (i2notes)
4142       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4143                         elim_i2, elim_i1, elim_i0);
4144     if (i1notes)
4145       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4146                         elim_i2, elim_i1, elim_i0);
4147     if (i0notes)
4148       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4149                         elim_i2, elim_i1, elim_i0);
4150     if (midnotes)
4151       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4152                         elim_i2, elim_i1, elim_i0);
4153
4154     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4155        know these are REG_UNUSED and want them to go to the desired insn,
4156        so we always pass it as i3.  */
4157
4158     if (newi2pat && new_i2_notes)
4159       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4160                         NULL_RTX);
4161
4162     if (new_i3_notes)
4163       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4164                         NULL_RTX);
4165
4166     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4167        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4168        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4169        in that case, it might delete I2.  Similarly for I2 and I1.
4170        Show an additional death due to the REG_DEAD note we make here.  If
4171        we discard it in distribute_notes, we will decrement it again.  */
4172
4173     if (i3dest_killed)
4174       {
4175         rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4176         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4177           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, elim_i2,
4178                             elim_i1, elim_i0);
4179         else
4180           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4181                             elim_i2, elim_i1, elim_i0);
4182       }
4183
4184     if (i2dest_in_i2src)
4185       {
4186         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4187         if (newi2pat && reg_set_p (i2dest, newi2pat))
4188           distribute_notes (new_note,  NULL_RTX, i2, NULL_RTX, NULL_RTX,
4189                             NULL_RTX, NULL_RTX);
4190         else
4191           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4192                             NULL_RTX, NULL_RTX, NULL_RTX);
4193       }
4194
4195     if (i1dest_in_i1src)
4196       {
4197         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4198         if (newi2pat && reg_set_p (i1dest, newi2pat))
4199           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4200                             NULL_RTX, NULL_RTX);
4201         else
4202           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4203                             NULL_RTX, NULL_RTX, NULL_RTX);
4204       }
4205
4206     if (i0dest_in_i0src)
4207       {
4208         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4209         if (newi2pat && reg_set_p (i0dest, newi2pat))
4210           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4211                             NULL_RTX, NULL_RTX);
4212         else
4213           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4214                             NULL_RTX, NULL_RTX, NULL_RTX);
4215       }
4216
4217     distribute_links (i3links);
4218     distribute_links (i2links);
4219     distribute_links (i1links);
4220     distribute_links (i0links);
4221
4222     if (REG_P (i2dest))
4223       {
4224         struct insn_link *link;
4225         rtx i2_insn = 0, i2_val = 0, set;
4226
4227         /* The insn that used to set this register doesn't exist, and
4228            this life of the register may not exist either.  See if one of
4229            I3's links points to an insn that sets I2DEST.  If it does,
4230            that is now the last known value for I2DEST. If we don't update
4231            this and I2 set the register to a value that depended on its old
4232            contents, we will get confused.  If this insn is used, thing
4233            will be set correctly in combine_instructions.  */
4234         FOR_EACH_LOG_LINK (link, i3)
4235           if ((set = single_set (link->insn)) != 0
4236               && rtx_equal_p (i2dest, SET_DEST (set)))
4237             i2_insn = link->insn, i2_val = SET_SRC (set);
4238
4239         record_value_for_reg (i2dest, i2_insn, i2_val);
4240
4241         /* If the reg formerly set in I2 died only once and that was in I3,
4242            zero its use count so it won't make `reload' do any work.  */
4243         if (! added_sets_2
4244             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4245             && ! i2dest_in_i2src)
4246           INC_REG_N_SETS (REGNO (i2dest), -1);
4247       }
4248
4249     if (i1 && REG_P (i1dest))
4250       {
4251         struct insn_link *link;
4252         rtx i1_insn = 0, i1_val = 0, set;
4253
4254         FOR_EACH_LOG_LINK (link, i3)
4255           if ((set = single_set (link->insn)) != 0
4256               && rtx_equal_p (i1dest, SET_DEST (set)))
4257             i1_insn = link->insn, i1_val = SET_SRC (set);
4258
4259         record_value_for_reg (i1dest, i1_insn, i1_val);
4260
4261         if (! added_sets_1 && ! i1dest_in_i1src)
4262           INC_REG_N_SETS (REGNO (i1dest), -1);
4263       }
4264
4265     if (i0 && REG_P (i0dest))
4266       {
4267         struct insn_link *link;
4268         rtx i0_insn = 0, i0_val = 0, set;
4269
4270         FOR_EACH_LOG_LINK (link, i3)
4271           if ((set = single_set (link->insn)) != 0
4272               && rtx_equal_p (i0dest, SET_DEST (set)))
4273             i0_insn = link->insn, i0_val = SET_SRC (set);
4274
4275         record_value_for_reg (i0dest, i0_insn, i0_val);
4276
4277         if (! added_sets_0 && ! i0dest_in_i0src)
4278           INC_REG_N_SETS (REGNO (i0dest), -1);
4279       }
4280
4281     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4282        been made to this insn.  The order is important, because newi2pat
4283        can affect nonzero_bits of newpat.  */
4284     if (newi2pat)
4285       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4286     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4287   }
4288
4289   if (undobuf.other_insn != NULL_RTX)
4290     {
4291       if (dump_file)
4292         {
4293           fprintf (dump_file, "modifying other_insn ");
4294           dump_insn_slim (dump_file, undobuf.other_insn);
4295         }
4296       df_insn_rescan (undobuf.other_insn);
4297     }
4298
4299   if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4300     {
4301       if (dump_file)
4302         {
4303           fprintf (dump_file, "modifying insn i0 ");
4304           dump_insn_slim (dump_file, i0);
4305         }
4306       df_insn_rescan (i0);
4307     }
4308
4309   if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4310     {
4311       if (dump_file)
4312         {
4313           fprintf (dump_file, "modifying insn i1 ");
4314           dump_insn_slim (dump_file, i1);
4315         }
4316       df_insn_rescan (i1);
4317     }
4318
4319   if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4320     {
4321       if (dump_file)
4322         {
4323           fprintf (dump_file, "modifying insn i2 ");
4324           dump_insn_slim (dump_file, i2);
4325         }
4326       df_insn_rescan (i2);
4327     }
4328
4329   if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4330     {
4331       if (dump_file)
4332         {
4333           fprintf (dump_file, "modifying insn i3 ");
4334           dump_insn_slim (dump_file, i3);
4335         }
4336       df_insn_rescan (i3);
4337     }
4338
4339   /* Set new_direct_jump_p if a new return or simple jump instruction
4340      has been created.  Adjust the CFG accordingly.  */
4341   if (returnjump_p (i3) || any_uncondjump_p (i3))
4342     {
4343       *new_direct_jump_p = 1;
4344       mark_jump_label (PATTERN (i3), i3, 0);
4345       update_cfg_for_uncondjump (i3);
4346     }
4347
4348   if (undobuf.other_insn != NULL_RTX
4349       && (returnjump_p (undobuf.other_insn)
4350           || any_uncondjump_p (undobuf.other_insn)))
4351     {
4352       *new_direct_jump_p = 1;
4353       update_cfg_for_uncondjump (undobuf.other_insn);
4354     }
4355
4356   /* A noop might also need cleaning up of CFG, if it comes from the
4357      simplification of a jump.  */
4358   if (JUMP_P (i3)
4359       && GET_CODE (newpat) == SET
4360       && SET_SRC (newpat) == pc_rtx
4361       && SET_DEST (newpat) == pc_rtx)
4362     {
4363       *new_direct_jump_p = 1;
4364       update_cfg_for_uncondjump (i3);
4365     }
4366
4367   if (undobuf.other_insn != NULL_RTX
4368       && JUMP_P (undobuf.other_insn)
4369       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4370       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4371       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4372     {
4373       *new_direct_jump_p = 1;
4374       update_cfg_for_uncondjump (undobuf.other_insn);
4375     }
4376
4377   combine_successes++;
4378   undo_commit ();
4379
4380   if (added_links_insn
4381       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4382       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4383     return added_links_insn;
4384   else
4385     return newi2pat ? i2 : i3;
4386 }
4387 \f
4388 /* Undo all the modifications recorded in undobuf.  */
4389
4390 static void
4391 undo_all (void)
4392 {
4393   struct undo *undo, *next;
4394
4395   for (undo = undobuf.undos; undo; undo = next)
4396     {
4397       next = undo->next;
4398       switch (undo->kind)
4399         {
4400         case UNDO_RTX:
4401           *undo->where.r = undo->old_contents.r;
4402           break;
4403         case UNDO_INT:
4404           *undo->where.i = undo->old_contents.i;
4405           break;
4406         case UNDO_MODE:
4407           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4408           break;
4409         case UNDO_LINKS:
4410           *undo->where.l = undo->old_contents.l;
4411           break;
4412         default:
4413           gcc_unreachable ();
4414         }
4415
4416       undo->next = undobuf.frees;
4417       undobuf.frees = undo;
4418     }
4419
4420   undobuf.undos = 0;
4421 }
4422
4423 /* We've committed to accepting the changes we made.  Move all
4424    of the undos to the free list.  */
4425
4426 static void
4427 undo_commit (void)
4428 {
4429   struct undo *undo, *next;
4430
4431   for (undo = undobuf.undos; undo; undo = next)
4432     {
4433       next = undo->next;
4434       undo->next = undobuf.frees;
4435       undobuf.frees = undo;
4436     }
4437   undobuf.undos = 0;
4438 }
4439 \f
4440 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4441    where we have an arithmetic expression and return that point.  LOC will
4442    be inside INSN.
4443
4444    try_combine will call this function to see if an insn can be split into
4445    two insns.  */
4446
4447 static rtx *
4448 find_split_point (rtx *loc, rtx insn, bool set_src)
4449 {
4450   rtx x = *loc;
4451   enum rtx_code code = GET_CODE (x);
4452   rtx *split;
4453   unsigned HOST_WIDE_INT len = 0;
4454   HOST_WIDE_INT pos = 0;
4455   int unsignedp = 0;
4456   rtx inner = NULL_RTX;
4457
4458   /* First special-case some codes.  */
4459   switch (code)
4460     {
4461     case SUBREG:
4462 #ifdef INSN_SCHEDULING
4463       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4464          point.  */
4465       if (MEM_P (SUBREG_REG (x)))
4466         return loc;
4467 #endif
4468       return find_split_point (&SUBREG_REG (x), insn, false);
4469
4470     case MEM:
4471 #ifdef HAVE_lo_sum
4472       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4473          using LO_SUM and HIGH.  */
4474       if (GET_CODE (XEXP (x, 0)) == CONST
4475           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4476         {
4477           enum machine_mode address_mode = get_address_mode (x);
4478
4479           SUBST (XEXP (x, 0),
4480                  gen_rtx_LO_SUM (address_mode,
4481                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4482                                  XEXP (x, 0)));
4483           return &XEXP (XEXP (x, 0), 0);
4484         }
4485 #endif
4486
4487       /* If we have a PLUS whose second operand is a constant and the
4488          address is not valid, perhaps will can split it up using
4489          the machine-specific way to split large constants.  We use
4490          the first pseudo-reg (one of the virtual regs) as a placeholder;
4491          it will not remain in the result.  */
4492       if (GET_CODE (XEXP (x, 0)) == PLUS
4493           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4494           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4495                                             MEM_ADDR_SPACE (x)))
4496         {
4497           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4498           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4499                                                       XEXP (x, 0)),
4500                                          subst_insn);
4501
4502           /* This should have produced two insns, each of which sets our
4503              placeholder.  If the source of the second is a valid address,
4504              we can make put both sources together and make a split point
4505              in the middle.  */
4506
4507           if (seq
4508               && NEXT_INSN (seq) != NULL_RTX
4509               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4510               && NONJUMP_INSN_P (seq)
4511               && GET_CODE (PATTERN (seq)) == SET
4512               && SET_DEST (PATTERN (seq)) == reg
4513               && ! reg_mentioned_p (reg,
4514                                     SET_SRC (PATTERN (seq)))
4515               && NONJUMP_INSN_P (NEXT_INSN (seq))
4516               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4517               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4518               && memory_address_addr_space_p
4519                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4520                     MEM_ADDR_SPACE (x)))
4521             {
4522               rtx src1 = SET_SRC (PATTERN (seq));
4523               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4524
4525               /* Replace the placeholder in SRC2 with SRC1.  If we can
4526                  find where in SRC2 it was placed, that can become our
4527                  split point and we can replace this address with SRC2.
4528                  Just try two obvious places.  */
4529
4530               src2 = replace_rtx (src2, reg, src1);
4531               split = 0;
4532               if (XEXP (src2, 0) == src1)
4533                 split = &XEXP (src2, 0);
4534               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4535                        && XEXP (XEXP (src2, 0), 0) == src1)
4536                 split = &XEXP (XEXP (src2, 0), 0);
4537
4538               if (split)
4539                 {
4540                   SUBST (XEXP (x, 0), src2);
4541                   return split;
4542                 }
4543             }
4544
4545           /* If that didn't work, perhaps the first operand is complex and
4546              needs to be computed separately, so make a split point there.
4547              This will occur on machines that just support REG + CONST
4548              and have a constant moved through some previous computation.  */
4549
4550           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4551                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4552                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4553             return &XEXP (XEXP (x, 0), 0);
4554         }
4555
4556       /* If we have a PLUS whose first operand is complex, try computing it
4557          separately by making a split there.  */
4558       if (GET_CODE (XEXP (x, 0)) == PLUS
4559           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4560                                             MEM_ADDR_SPACE (x))
4561           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4562           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4563                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4564         return &XEXP (XEXP (x, 0), 0);
4565       break;
4566
4567     case SET:
4568 #ifdef HAVE_cc0
4569       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4570          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4571          we need to put the operand into a register.  So split at that
4572          point.  */
4573
4574       if (SET_DEST (x) == cc0_rtx
4575           && GET_CODE (SET_SRC (x)) != COMPARE
4576           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4577           && !OBJECT_P (SET_SRC (x))
4578           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4579                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4580         return &SET_SRC (x);
4581 #endif
4582
4583       /* See if we can split SET_SRC as it stands.  */
4584       split = find_split_point (&SET_SRC (x), insn, true);
4585       if (split && split != &SET_SRC (x))
4586         return split;
4587
4588       /* See if we can split SET_DEST as it stands.  */
4589       split = find_split_point (&SET_DEST (x), insn, false);
4590       if (split && split != &SET_DEST (x))
4591         return split;
4592
4593       /* See if this is a bitfield assignment with everything constant.  If
4594          so, this is an IOR of an AND, so split it into that.  */
4595       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4596           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4597           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4598           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4599           && CONST_INT_P (SET_SRC (x))
4600           && ((INTVAL (XEXP (SET_DEST (x), 1))
4601                + INTVAL (XEXP (SET_DEST (x), 2)))
4602               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4603           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4604         {
4605           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4606           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4607           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4608           rtx dest = XEXP (SET_DEST (x), 0);
4609           enum machine_mode mode = GET_MODE (dest);
4610           unsigned HOST_WIDE_INT mask
4611             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4612           rtx or_mask;
4613
4614           if (BITS_BIG_ENDIAN)
4615             pos = GET_MODE_PRECISION (mode) - len - pos;
4616
4617           or_mask = gen_int_mode (src << pos, mode);
4618           if (src == mask)
4619             SUBST (SET_SRC (x),
4620                    simplify_gen_binary (IOR, mode, dest, or_mask));
4621           else
4622             {
4623               rtx negmask = gen_int_mode (~(mask << pos), mode);
4624               SUBST (SET_SRC (x),
4625                      simplify_gen_binary (IOR, mode,
4626                                           simplify_gen_binary (AND, mode,
4627                                                                dest, negmask),
4628                                           or_mask));
4629             }
4630
4631           SUBST (SET_DEST (x), dest);
4632
4633           split = find_split_point (&SET_SRC (x), insn, true);
4634           if (split && split != &SET_SRC (x))
4635             return split;
4636         }
4637
4638       /* Otherwise, see if this is an operation that we can split into two.
4639          If so, try to split that.  */
4640       code = GET_CODE (SET_SRC (x));
4641
4642       switch (code)
4643         {
4644         case AND:
4645           /* If we are AND'ing with a large constant that is only a single
4646              bit and the result is only being used in a context where we
4647              need to know if it is zero or nonzero, replace it with a bit
4648              extraction.  This will avoid the large constant, which might
4649              have taken more than one insn to make.  If the constant were
4650              not a valid argument to the AND but took only one insn to make,
4651              this is no worse, but if it took more than one insn, it will
4652              be better.  */
4653
4654           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4655               && REG_P (XEXP (SET_SRC (x), 0))
4656               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4657               && REG_P (SET_DEST (x))
4658               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4659               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4660               && XEXP (*split, 0) == SET_DEST (x)
4661               && XEXP (*split, 1) == const0_rtx)
4662             {
4663               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4664                                                 XEXP (SET_SRC (x), 0),
4665                                                 pos, NULL_RTX, 1, 1, 0, 0);
4666               if (extraction != 0)
4667                 {
4668                   SUBST (SET_SRC (x), extraction);
4669                   return find_split_point (loc, insn, false);
4670                 }
4671             }
4672           break;
4673
4674         case NE:
4675           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4676              is known to be on, this can be converted into a NEG of a shift.  */
4677           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4678               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4679               && 1 <= (pos = exact_log2
4680                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4681                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4682             {
4683               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4684
4685               SUBST (SET_SRC (x),
4686                      gen_rtx_NEG (mode,
4687                                   gen_rtx_LSHIFTRT (mode,
4688                                                     XEXP (SET_SRC (x), 0),
4689                                                     GEN_INT (pos))));
4690
4691               split = find_split_point (&SET_SRC (x), insn, true);
4692               if (split && split != &SET_SRC (x))
4693                 return split;
4694             }
4695           break;
4696
4697         case SIGN_EXTEND:
4698           inner = XEXP (SET_SRC (x), 0);
4699
4700           /* We can't optimize if either mode is a partial integer
4701              mode as we don't know how many bits are significant
4702              in those modes.  */
4703           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4704               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4705             break;
4706
4707           pos = 0;
4708           len = GET_MODE_PRECISION (GET_MODE (inner));
4709           unsignedp = 0;
4710           break;
4711
4712         case SIGN_EXTRACT:
4713         case ZERO_EXTRACT:
4714           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4715               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4716             {
4717               inner = XEXP (SET_SRC (x), 0);
4718               len = INTVAL (XEXP (SET_SRC (x), 1));
4719               pos = INTVAL (XEXP (SET_SRC (x), 2));
4720
4721               if (BITS_BIG_ENDIAN)
4722                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4723               unsignedp = (code == ZERO_EXTRACT);
4724             }
4725           break;
4726
4727         default:
4728           break;
4729         }
4730
4731       if (len && pos >= 0
4732           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4733         {
4734           enum machine_mode mode = GET_MODE (SET_SRC (x));
4735
4736           /* For unsigned, we have a choice of a shift followed by an
4737              AND or two shifts.  Use two shifts for field sizes where the
4738              constant might be too large.  We assume here that we can
4739              always at least get 8-bit constants in an AND insn, which is
4740              true for every current RISC.  */
4741
4742           if (unsignedp && len <= 8)
4743             {
4744               unsigned HOST_WIDE_INT mask
4745                 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4746               SUBST (SET_SRC (x),
4747                      gen_rtx_AND (mode,
4748                                   gen_rtx_LSHIFTRT
4749                                   (mode, gen_lowpart (mode, inner),
4750                                    GEN_INT (pos)),
4751                                   gen_int_mode (mask, mode)));
4752
4753               split = find_split_point (&SET_SRC (x), insn, true);
4754               if (split && split != &SET_SRC (x))
4755                 return split;
4756             }
4757           else
4758             {
4759               SUBST (SET_SRC (x),
4760                      gen_rtx_fmt_ee
4761                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4762                       gen_rtx_ASHIFT (mode,
4763                                       gen_lowpart (mode, inner),
4764                                       GEN_INT (GET_MODE_PRECISION (mode)
4765                                                - len - pos)),
4766                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4767
4768               split = find_split_point (&SET_SRC (x), insn, true);
4769               if (split && split != &SET_SRC (x))
4770                 return split;
4771             }
4772         }
4773
4774       /* See if this is a simple operation with a constant as the second
4775          operand.  It might be that this constant is out of range and hence
4776          could be used as a split point.  */
4777       if (BINARY_P (SET_SRC (x))
4778           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4779           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4780               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4781                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4782         return &XEXP (SET_SRC (x), 1);
4783
4784       /* Finally, see if this is a simple operation with its first operand
4785          not in a register.  The operation might require this operand in a
4786          register, so return it as a split point.  We can always do this
4787          because if the first operand were another operation, we would have
4788          already found it as a split point.  */
4789       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4790           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4791         return &XEXP (SET_SRC (x), 0);
4792
4793       return 0;
4794
4795     case AND:
4796     case IOR:
4797       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4798          it is better to write this as (not (ior A B)) so we can split it.
4799          Similarly for IOR.  */
4800       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4801         {
4802           SUBST (*loc,
4803                  gen_rtx_NOT (GET_MODE (x),
4804                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4805                                               GET_MODE (x),
4806                                               XEXP (XEXP (x, 0), 0),
4807                                               XEXP (XEXP (x, 1), 0))));
4808           return find_split_point (loc, insn, set_src);
4809         }
4810
4811       /* Many RISC machines have a large set of logical insns.  If the
4812          second operand is a NOT, put it first so we will try to split the
4813          other operand first.  */
4814       if (GET_CODE (XEXP (x, 1)) == NOT)
4815         {
4816           rtx tem = XEXP (x, 0);
4817           SUBST (XEXP (x, 0), XEXP (x, 1));
4818           SUBST (XEXP (x, 1), tem);
4819         }
4820       break;
4821
4822     case PLUS:
4823     case MINUS:
4824       /* Canonicalization can produce (minus A (mult B C)), where C is a
4825          constant.  It may be better to try splitting (plus (mult B -C) A)
4826          instead if this isn't a multiply by a power of two.  */
4827       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4828           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4829           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4830         {
4831           enum machine_mode mode = GET_MODE (x);
4832           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4833           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4834           SUBST (*loc, gen_rtx_PLUS (mode,
4835                                      gen_rtx_MULT (mode,
4836                                                    XEXP (XEXP (x, 1), 0),
4837                                                    gen_int_mode (other_int,
4838                                                                  mode)),
4839                                      XEXP (x, 0)));
4840           return find_split_point (loc, insn, set_src);
4841         }
4842
4843       /* Split at a multiply-accumulate instruction.  However if this is
4844          the SET_SRC, we likely do not have such an instruction and it's
4845          worthless to try this split.  */
4846       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4847         return loc;
4848
4849     default:
4850       break;
4851     }
4852
4853   /* Otherwise, select our actions depending on our rtx class.  */
4854   switch (GET_RTX_CLASS (code))
4855     {
4856     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4857     case RTX_TERNARY:
4858       split = find_split_point (&XEXP (x, 2), insn, false);
4859       if (split)
4860         return split;
4861       /* ... fall through ...  */
4862     case RTX_BIN_ARITH:
4863     case RTX_COMM_ARITH:
4864     case RTX_COMPARE:
4865     case RTX_COMM_COMPARE:
4866       split = find_split_point (&XEXP (x, 1), insn, false);
4867       if (split)
4868         return split;
4869       /* ... fall through ...  */
4870     case RTX_UNARY:
4871       /* Some machines have (and (shift ...) ...) insns.  If X is not
4872          an AND, but XEXP (X, 0) is, use it as our split point.  */
4873       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4874         return &XEXP (x, 0);
4875
4876       split = find_split_point (&XEXP (x, 0), insn, false);
4877       if (split)
4878         return split;
4879       return loc;
4880
4881     default:
4882       /* Otherwise, we don't have a split point.  */
4883       return 0;
4884     }
4885 }
4886 \f
4887 /* Throughout X, replace FROM with TO, and return the result.
4888    The result is TO if X is FROM;
4889    otherwise the result is X, but its contents may have been modified.
4890    If they were modified, a record was made in undobuf so that
4891    undo_all will (among other things) return X to its original state.
4892
4893    If the number of changes necessary is too much to record to undo,
4894    the excess changes are not made, so the result is invalid.
4895    The changes already made can still be undone.
4896    undobuf.num_undo is incremented for such changes, so by testing that
4897    the caller can tell whether the result is valid.
4898
4899    `n_occurrences' is incremented each time FROM is replaced.
4900
4901    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4902
4903    IN_COND is nonzero if we are at the top level of a condition.
4904
4905    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4906    by copying if `n_occurrences' is nonzero.  */
4907
4908 static rtx
4909 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4910 {
4911   enum rtx_code code = GET_CODE (x);
4912   enum machine_mode op0_mode = VOIDmode;
4913   const char *fmt;
4914   int len, i;
4915   rtx new_rtx;
4916
4917 /* Two expressions are equal if they are identical copies of a shared
4918    RTX or if they are both registers with the same register number
4919    and mode.  */
4920
4921 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4922   ((X) == (Y)                                           \
4923    || (REG_P (X) && REG_P (Y)   \
4924        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4925
4926   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4927     {
4928       n_occurrences++;
4929       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4930     }
4931
4932   /* If X and FROM are the same register but different modes, they
4933      will not have been seen as equal above.  However, the log links code
4934      will make a LOG_LINKS entry for that case.  If we do nothing, we
4935      will try to rerecognize our original insn and, when it succeeds,
4936      we will delete the feeding insn, which is incorrect.
4937
4938      So force this insn not to match in this (rare) case.  */
4939   if (! in_dest && code == REG && REG_P (from)
4940       && reg_overlap_mentioned_p (x, from))
4941     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4942
4943   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4944      of which may contain things that can be combined.  */
4945   if (code != MEM && code != LO_SUM && OBJECT_P (x))
4946     return x;
4947
4948   /* It is possible to have a subexpression appear twice in the insn.
4949      Suppose that FROM is a register that appears within TO.
4950      Then, after that subexpression has been scanned once by `subst',
4951      the second time it is scanned, TO may be found.  If we were
4952      to scan TO here, we would find FROM within it and create a
4953      self-referent rtl structure which is completely wrong.  */
4954   if (COMBINE_RTX_EQUAL_P (x, to))
4955     return to;
4956
4957   /* Parallel asm_operands need special attention because all of the
4958      inputs are shared across the arms.  Furthermore, unsharing the
4959      rtl results in recognition failures.  Failure to handle this case
4960      specially can result in circular rtl.
4961
4962      Solve this by doing a normal pass across the first entry of the
4963      parallel, and only processing the SET_DESTs of the subsequent
4964      entries.  Ug.  */
4965
4966   if (code == PARALLEL
4967       && GET_CODE (XVECEXP (x, 0, 0)) == SET
4968       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4969     {
4970       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
4971
4972       /* If this substitution failed, this whole thing fails.  */
4973       if (GET_CODE (new_rtx) == CLOBBER
4974           && XEXP (new_rtx, 0) == const0_rtx)
4975         return new_rtx;
4976
4977       SUBST (XVECEXP (x, 0, 0), new_rtx);
4978
4979       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4980         {
4981           rtx dest = SET_DEST (XVECEXP (x, 0, i));
4982
4983           if (!REG_P (dest)
4984               && GET_CODE (dest) != CC0
4985               && GET_CODE (dest) != PC)
4986             {
4987               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
4988
4989               /* If this substitution failed, this whole thing fails.  */
4990               if (GET_CODE (new_rtx) == CLOBBER
4991                   && XEXP (new_rtx, 0) == const0_rtx)
4992                 return new_rtx;
4993
4994               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4995             }
4996         }
4997     }
4998   else
4999     {
5000       len = GET_RTX_LENGTH (code);
5001       fmt = GET_RTX_FORMAT (code);
5002
5003       /* We don't need to process a SET_DEST that is a register, CC0,
5004          or PC, so set up to skip this common case.  All other cases
5005          where we want to suppress replacing something inside a
5006          SET_SRC are handled via the IN_DEST operand.  */
5007       if (code == SET
5008           && (REG_P (SET_DEST (x))
5009               || GET_CODE (SET_DEST (x)) == CC0
5010               || GET_CODE (SET_DEST (x)) == PC))
5011         fmt = "ie";
5012
5013       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5014          constant.  */
5015       if (fmt[0] == 'e')
5016         op0_mode = GET_MODE (XEXP (x, 0));
5017
5018       for (i = 0; i < len; i++)
5019         {
5020           if (fmt[i] == 'E')
5021             {
5022               int j;
5023               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5024                 {
5025                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5026                     {
5027                       new_rtx = (unique_copy && n_occurrences
5028                              ? copy_rtx (to) : to);
5029                       n_occurrences++;
5030                     }
5031                   else
5032                     {
5033                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5034                                        unique_copy);
5035
5036                       /* If this substitution failed, this whole thing
5037                          fails.  */
5038                       if (GET_CODE (new_rtx) == CLOBBER
5039                           && XEXP (new_rtx, 0) == const0_rtx)
5040                         return new_rtx;
5041                     }
5042
5043                   SUBST (XVECEXP (x, i, j), new_rtx);
5044                 }
5045             }
5046           else if (fmt[i] == 'e')
5047             {
5048               /* If this is a register being set, ignore it.  */
5049               new_rtx = XEXP (x, i);
5050               if (in_dest
5051                   && i == 0
5052                   && (((code == SUBREG || code == ZERO_EXTRACT)
5053                        && REG_P (new_rtx))
5054                       || code == STRICT_LOW_PART))
5055                 ;
5056
5057               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5058                 {
5059                   /* In general, don't install a subreg involving two
5060                      modes not tieable.  It can worsen register
5061                      allocation, and can even make invalid reload
5062                      insns, since the reg inside may need to be copied
5063                      from in the outside mode, and that may be invalid
5064                      if it is an fp reg copied in integer mode.
5065
5066                      We allow two exceptions to this: It is valid if
5067                      it is inside another SUBREG and the mode of that
5068                      SUBREG and the mode of the inside of TO is
5069                      tieable and it is valid if X is a SET that copies
5070                      FROM to CC0.  */
5071
5072                   if (GET_CODE (to) == SUBREG
5073                       && ! MODES_TIEABLE_P (GET_MODE (to),
5074                                             GET_MODE (SUBREG_REG (to)))
5075                       && ! (code == SUBREG
5076                             && MODES_TIEABLE_P (GET_MODE (x),
5077                                                 GET_MODE (SUBREG_REG (to))))
5078 #ifdef HAVE_cc0
5079                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5080 #endif
5081                       )
5082                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5083
5084 #ifdef CANNOT_CHANGE_MODE_CLASS
5085                   if (code == SUBREG
5086                       && REG_P (to)
5087                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5088                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5089                                                    GET_MODE (to),
5090                                                    GET_MODE (x)))
5091                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5092 #endif
5093
5094                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5095                   n_occurrences++;
5096                 }
5097               else
5098                 /* If we are in a SET_DEST, suppress most cases unless we
5099                    have gone inside a MEM, in which case we want to
5100                    simplify the address.  We assume here that things that
5101                    are actually part of the destination have their inner
5102                    parts in the first expression.  This is true for SUBREG,
5103                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5104                    things aside from REG and MEM that should appear in a
5105                    SET_DEST.  */
5106                 new_rtx = subst (XEXP (x, i), from, to,
5107                              (((in_dest
5108                                 && (code == SUBREG || code == STRICT_LOW_PART
5109                                     || code == ZERO_EXTRACT))
5110                                || code == SET)
5111                               && i == 0),
5112                                  code == IF_THEN_ELSE && i == 0,
5113                                  unique_copy);
5114
5115               /* If we found that we will have to reject this combination,
5116                  indicate that by returning the CLOBBER ourselves, rather than
5117                  an expression containing it.  This will speed things up as
5118                  well as prevent accidents where two CLOBBERs are considered
5119                  to be equal, thus producing an incorrect simplification.  */
5120
5121               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5122                 return new_rtx;
5123
5124               if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5125                 {
5126                   enum machine_mode mode = GET_MODE (x);
5127
5128                   x = simplify_subreg (GET_MODE (x), new_rtx,
5129                                        GET_MODE (SUBREG_REG (x)),
5130                                        SUBREG_BYTE (x));
5131                   if (! x)
5132                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5133                 }
5134               else if (CONST_SCALAR_INT_P (new_rtx)
5135                        && GET_CODE (x) == ZERO_EXTEND)
5136                 {
5137                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5138                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5139                   gcc_assert (x);
5140                 }
5141               else
5142                 SUBST (XEXP (x, i), new_rtx);
5143             }
5144         }
5145     }
5146
5147   /* Check if we are loading something from the constant pool via float
5148      extension; in this case we would undo compress_float_constant
5149      optimization and degenerate constant load to an immediate value.  */
5150   if (GET_CODE (x) == FLOAT_EXTEND
5151       && MEM_P (XEXP (x, 0))
5152       && MEM_READONLY_P (XEXP (x, 0)))
5153     {
5154       rtx tmp = avoid_constant_pool_reference (x);
5155       if (x != tmp)
5156         return x;
5157     }
5158
5159   /* Try to simplify X.  If the simplification changed the code, it is likely
5160      that further simplification will help, so loop, but limit the number
5161      of repetitions that will be performed.  */
5162
5163   for (i = 0; i < 4; i++)
5164     {
5165       /* If X is sufficiently simple, don't bother trying to do anything
5166          with it.  */
5167       if (code != CONST_INT && code != REG && code != CLOBBER)
5168         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5169
5170       if (GET_CODE (x) == code)
5171         break;
5172
5173       code = GET_CODE (x);
5174
5175       /* We no longer know the original mode of operand 0 since we
5176          have changed the form of X)  */
5177       op0_mode = VOIDmode;
5178     }
5179
5180   return x;
5181 }
5182 \f
5183 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5184    outer level; call `subst' to simplify recursively.  Return the new
5185    expression.
5186
5187    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5188    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5189    of a condition.  */
5190
5191 static rtx
5192 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5193                       int in_cond)
5194 {
5195   enum rtx_code code = GET_CODE (x);
5196   enum machine_mode mode = GET_MODE (x);
5197   rtx temp;
5198   int i;
5199
5200   /* If this is a commutative operation, put a constant last and a complex
5201      expression first.  We don't need to do this for comparisons here.  */
5202   if (COMMUTATIVE_ARITH_P (x)
5203       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5204     {
5205       temp = XEXP (x, 0);
5206       SUBST (XEXP (x, 0), XEXP (x, 1));
5207       SUBST (XEXP (x, 1), temp);
5208     }
5209
5210   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5211      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5212      things.  Check for cases where both arms are testing the same
5213      condition.
5214
5215      Don't do anything if all operands are very simple.  */
5216
5217   if ((BINARY_P (x)
5218        && ((!OBJECT_P (XEXP (x, 0))
5219             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5220                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5221            || (!OBJECT_P (XEXP (x, 1))
5222                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5223                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5224       || (UNARY_P (x)
5225           && (!OBJECT_P (XEXP (x, 0))
5226                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5227                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5228     {
5229       rtx cond, true_rtx, false_rtx;
5230
5231       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5232       if (cond != 0
5233           /* If everything is a comparison, what we have is highly unlikely
5234              to be simpler, so don't use it.  */
5235           && ! (COMPARISON_P (x)
5236                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5237         {
5238           rtx cop1 = const0_rtx;
5239           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5240
5241           if (cond_code == NE && COMPARISON_P (cond))
5242             return x;
5243
5244           /* Simplify the alternative arms; this may collapse the true and
5245              false arms to store-flag values.  Be careful to use copy_rtx
5246              here since true_rtx or false_rtx might share RTL with x as a
5247              result of the if_then_else_cond call above.  */
5248           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5249           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5250
5251           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5252              is unlikely to be simpler.  */
5253           if (general_operand (true_rtx, VOIDmode)
5254               && general_operand (false_rtx, VOIDmode))
5255             {
5256               enum rtx_code reversed;
5257
5258               /* Restarting if we generate a store-flag expression will cause
5259                  us to loop.  Just drop through in this case.  */
5260
5261               /* If the result values are STORE_FLAG_VALUE and zero, we can
5262                  just make the comparison operation.  */
5263               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5264                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5265                                              cond, cop1);
5266               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5267                        && ((reversed = reversed_comparison_code_parts
5268                                         (cond_code, cond, cop1, NULL))
5269                            != UNKNOWN))
5270                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5271                                              cond, cop1);
5272
5273               /* Likewise, we can make the negate of a comparison operation
5274                  if the result values are - STORE_FLAG_VALUE and zero.  */
5275               else if (CONST_INT_P (true_rtx)
5276                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5277                        && false_rtx == const0_rtx)
5278                 x = simplify_gen_unary (NEG, mode,
5279                                         simplify_gen_relational (cond_code,
5280                                                                  mode, VOIDmode,
5281                                                                  cond, cop1),
5282                                         mode);
5283               else if (CONST_INT_P (false_rtx)
5284                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5285                        && true_rtx == const0_rtx
5286                        && ((reversed = reversed_comparison_code_parts
5287                                         (cond_code, cond, cop1, NULL))
5288                            != UNKNOWN))
5289                 x = simplify_gen_unary (NEG, mode,
5290                                         simplify_gen_relational (reversed,
5291                                                                  mode, VOIDmode,
5292                                                                  cond, cop1),
5293                                         mode);
5294               else
5295                 return gen_rtx_IF_THEN_ELSE (mode,
5296                                              simplify_gen_relational (cond_code,
5297                                                                       mode,
5298                                                                       VOIDmode,
5299                                                                       cond,
5300                                                                       cop1),
5301                                              true_rtx, false_rtx);
5302
5303               code = GET_CODE (x);
5304               op0_mode = VOIDmode;
5305             }
5306         }
5307     }
5308
5309   /* Try to fold this expression in case we have constants that weren't
5310      present before.  */
5311   temp = 0;
5312   switch (GET_RTX_CLASS (code))
5313     {
5314     case RTX_UNARY:
5315       if (op0_mode == VOIDmode)
5316         op0_mode = GET_MODE (XEXP (x, 0));
5317       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5318       break;
5319     case RTX_COMPARE:
5320     case RTX_COMM_COMPARE:
5321       {
5322         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5323         if (cmp_mode == VOIDmode)
5324           {
5325             cmp_mode = GET_MODE (XEXP (x, 1));
5326             if (cmp_mode == VOIDmode)
5327               cmp_mode = op0_mode;
5328           }
5329         temp = simplify_relational_operation (code, mode, cmp_mode,
5330                                               XEXP (x, 0), XEXP (x, 1));
5331       }
5332       break;
5333     case RTX_COMM_ARITH:
5334     case RTX_BIN_ARITH:
5335       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5336       break;
5337     case RTX_BITFIELD_OPS:
5338     case RTX_TERNARY:
5339       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5340                                          XEXP (x, 1), XEXP (x, 2));
5341       break;
5342     default:
5343       break;
5344     }
5345
5346   if (temp)
5347     {
5348       x = temp;
5349       code = GET_CODE (temp);
5350       op0_mode = VOIDmode;
5351       mode = GET_MODE (temp);
5352     }
5353
5354   /* First see if we can apply the inverse distributive law.  */
5355   if (code == PLUS || code == MINUS
5356       || code == AND || code == IOR || code == XOR)
5357     {
5358       x = apply_distributive_law (x);
5359       code = GET_CODE (x);
5360       op0_mode = VOIDmode;
5361     }
5362
5363   /* If CODE is an associative operation not otherwise handled, see if we
5364      can associate some operands.  This can win if they are constants or
5365      if they are logically related (i.e. (a & b) & a).  */
5366   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5367        || code == AND || code == IOR || code == XOR
5368        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5369       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5370           || (flag_associative_math && FLOAT_MODE_P (mode))))
5371     {
5372       if (GET_CODE (XEXP (x, 0)) == code)
5373         {
5374           rtx other = XEXP (XEXP (x, 0), 0);
5375           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5376           rtx inner_op1 = XEXP (x, 1);
5377           rtx inner;
5378
5379           /* Make sure we pass the constant operand if any as the second
5380              one if this is a commutative operation.  */
5381           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5382             {
5383               rtx tem = inner_op0;
5384               inner_op0 = inner_op1;
5385               inner_op1 = tem;
5386             }
5387           inner = simplify_binary_operation (code == MINUS ? PLUS
5388                                              : code == DIV ? MULT
5389                                              : code,
5390                                              mode, inner_op0, inner_op1);
5391
5392           /* For commutative operations, try the other pair if that one
5393              didn't simplify.  */
5394           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5395             {
5396               other = XEXP (XEXP (x, 0), 1);
5397               inner = simplify_binary_operation (code, mode,
5398                                                  XEXP (XEXP (x, 0), 0),
5399                                                  XEXP (x, 1));
5400             }
5401
5402           if (inner)
5403             return simplify_gen_binary (code, mode, other, inner);
5404         }
5405     }
5406
5407   /* A little bit of algebraic simplification here.  */
5408   switch (code)
5409     {
5410     case MEM:
5411       /* Ensure that our address has any ASHIFTs converted to MULT in case
5412          address-recognizing predicates are called later.  */
5413       temp = make_compound_operation (XEXP (x, 0), MEM);
5414       SUBST (XEXP (x, 0), temp);
5415       break;
5416
5417     case SUBREG:
5418       if (op0_mode == VOIDmode)
5419         op0_mode = GET_MODE (SUBREG_REG (x));
5420
5421       /* See if this can be moved to simplify_subreg.  */
5422       if (CONSTANT_P (SUBREG_REG (x))
5423           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5424              /* Don't call gen_lowpart if the inner mode
5425                 is VOIDmode and we cannot simplify it, as SUBREG without
5426                 inner mode is invalid.  */
5427           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5428               || gen_lowpart_common (mode, SUBREG_REG (x))))
5429         return gen_lowpart (mode, SUBREG_REG (x));
5430
5431       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5432         break;
5433       {
5434         rtx temp;
5435         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5436                                 SUBREG_BYTE (x));
5437         if (temp)
5438           return temp;
5439
5440         /* If op is known to have all lower bits zero, the result is zero.  */
5441         if (!in_dest
5442             && SCALAR_INT_MODE_P (mode)
5443             && SCALAR_INT_MODE_P (op0_mode)
5444             && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode)
5445             && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5446             && HWI_COMPUTABLE_MODE_P (op0_mode)
5447             && (nonzero_bits (SUBREG_REG (x), op0_mode)
5448                 & GET_MODE_MASK (mode)) == 0)
5449           return CONST0_RTX (mode);
5450       }
5451
5452       /* Don't change the mode of the MEM if that would change the meaning
5453          of the address.  */
5454       if (MEM_P (SUBREG_REG (x))
5455           && (MEM_VOLATILE_P (SUBREG_REG (x))
5456               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5457                                            MEM_ADDR_SPACE (SUBREG_REG (x)))))
5458         return gen_rtx_CLOBBER (mode, const0_rtx);
5459
5460       /* Note that we cannot do any narrowing for non-constants since
5461          we might have been counting on using the fact that some bits were
5462          zero.  We now do this in the SET.  */
5463
5464       break;
5465
5466     case NEG:
5467       temp = expand_compound_operation (XEXP (x, 0));
5468
5469       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5470          replaced by (lshiftrt X C).  This will convert
5471          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5472
5473       if (GET_CODE (temp) == ASHIFTRT
5474           && CONST_INT_P (XEXP (temp, 1))
5475           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5476         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5477                                      INTVAL (XEXP (temp, 1)));
5478
5479       /* If X has only a single bit that might be nonzero, say, bit I, convert
5480          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5481          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5482          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5483          or a SUBREG of one since we'd be making the expression more
5484          complex if it was just a register.  */
5485
5486       if (!REG_P (temp)
5487           && ! (GET_CODE (temp) == SUBREG
5488                 && REG_P (SUBREG_REG (temp)))
5489           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5490         {
5491           rtx temp1 = simplify_shift_const
5492             (NULL_RTX, ASHIFTRT, mode,
5493              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5494                                    GET_MODE_PRECISION (mode) - 1 - i),
5495              GET_MODE_PRECISION (mode) - 1 - i);
5496
5497           /* If all we did was surround TEMP with the two shifts, we
5498              haven't improved anything, so don't use it.  Otherwise,
5499              we are better off with TEMP1.  */
5500           if (GET_CODE (temp1) != ASHIFTRT
5501               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5502               || XEXP (XEXP (temp1, 0), 0) != temp)
5503             return temp1;
5504         }
5505       break;
5506
5507     case TRUNCATE:
5508       /* We can't handle truncation to a partial integer mode here
5509          because we don't know the real bitsize of the partial
5510          integer mode.  */
5511       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5512         break;
5513
5514       if (HWI_COMPUTABLE_MODE_P (mode))
5515         SUBST (XEXP (x, 0),
5516                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5517                               GET_MODE_MASK (mode), 0));
5518
5519       /* We can truncate a constant value and return it.  */
5520       if (CONST_INT_P (XEXP (x, 0)))
5521         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5522
5523       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5524          whose value is a comparison can be replaced with a subreg if
5525          STORE_FLAG_VALUE permits.  */
5526       if (HWI_COMPUTABLE_MODE_P (mode)
5527           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5528           && (temp = get_last_value (XEXP (x, 0)))
5529           && COMPARISON_P (temp))
5530         return gen_lowpart (mode, XEXP (x, 0));
5531       break;
5532
5533     case CONST:
5534       /* (const (const X)) can become (const X).  Do it this way rather than
5535          returning the inner CONST since CONST can be shared with a
5536          REG_EQUAL note.  */
5537       if (GET_CODE (XEXP (x, 0)) == CONST)
5538         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5539       break;
5540
5541 #ifdef HAVE_lo_sum
5542     case LO_SUM:
5543       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5544          can add in an offset.  find_split_point will split this address up
5545          again if it doesn't match.  */
5546       if (GET_CODE (XEXP (x, 0)) == HIGH
5547           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5548         return XEXP (x, 1);
5549       break;
5550 #endif
5551
5552     case PLUS:
5553       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5554          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5555          bit-field and can be replaced by either a sign_extend or a
5556          sign_extract.  The `and' may be a zero_extend and the two
5557          <c>, -<c> constants may be reversed.  */
5558       if (GET_CODE (XEXP (x, 0)) == XOR
5559           && CONST_INT_P (XEXP (x, 1))
5560           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5561           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5562           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5563               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5564           && HWI_COMPUTABLE_MODE_P (mode)
5565           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5566                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5567                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5568                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5569               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5570                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5571                       == (unsigned int) i + 1))))
5572         return simplify_shift_const
5573           (NULL_RTX, ASHIFTRT, mode,
5574            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5575                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5576                                  GET_MODE_PRECISION (mode) - (i + 1)),
5577            GET_MODE_PRECISION (mode) - (i + 1));
5578
5579       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5580          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5581          the bitsize of the mode - 1.  This allows simplification of
5582          "a = (b & 8) == 0;"  */
5583       if (XEXP (x, 1) == constm1_rtx
5584           && !REG_P (XEXP (x, 0))
5585           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5586                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5587           && nonzero_bits (XEXP (x, 0), mode) == 1)
5588         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5589            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5590                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5591                                  GET_MODE_PRECISION (mode) - 1),
5592            GET_MODE_PRECISION (mode) - 1);
5593
5594       /* If we are adding two things that have no bits in common, convert
5595          the addition into an IOR.  This will often be further simplified,
5596          for example in cases like ((a & 1) + (a & 2)), which can
5597          become a & 3.  */
5598
5599       if (HWI_COMPUTABLE_MODE_P (mode)
5600           && (nonzero_bits (XEXP (x, 0), mode)
5601               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5602         {
5603           /* Try to simplify the expression further.  */
5604           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5605           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5606
5607           /* If we could, great.  If not, do not go ahead with the IOR
5608              replacement, since PLUS appears in many special purpose
5609              address arithmetic instructions.  */
5610           if (GET_CODE (temp) != CLOBBER
5611               && (GET_CODE (temp) != IOR
5612                   || ((XEXP (temp, 0) != XEXP (x, 0)
5613                        || XEXP (temp, 1) != XEXP (x, 1))
5614                       && (XEXP (temp, 0) != XEXP (x, 1)
5615                           || XEXP (temp, 1) != XEXP (x, 0)))))
5616             return temp;
5617         }
5618       break;
5619
5620     case MINUS:
5621       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5622          (and <foo> (const_int pow2-1))  */
5623       if (GET_CODE (XEXP (x, 1)) == AND
5624           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5625           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5626           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5627         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5628                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5629       break;
5630
5631     case MULT:
5632       /* If we have (mult (plus A B) C), apply the distributive law and then
5633          the inverse distributive law to see if things simplify.  This
5634          occurs mostly in addresses, often when unrolling loops.  */
5635
5636       if (GET_CODE (XEXP (x, 0)) == PLUS)
5637         {
5638           rtx result = distribute_and_simplify_rtx (x, 0);
5639           if (result)
5640             return result;
5641         }
5642
5643       /* Try simplify a*(b/c) as (a*b)/c.  */
5644       if (FLOAT_MODE_P (mode) && flag_associative_math
5645           && GET_CODE (XEXP (x, 0)) == DIV)
5646         {
5647           rtx tem = simplify_binary_operation (MULT, mode,
5648                                                XEXP (XEXP (x, 0), 0),
5649                                                XEXP (x, 1));
5650           if (tem)
5651             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5652         }
5653       break;
5654
5655     case UDIV:
5656       /* If this is a divide by a power of two, treat it as a shift if
5657          its first operand is a shift.  */
5658       if (CONST_INT_P (XEXP (x, 1))
5659           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5660           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5661               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5662               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5663               || GET_CODE (XEXP (x, 0)) == ROTATE
5664               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5665         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5666       break;
5667
5668     case EQ:  case NE:
5669     case GT:  case GTU:  case GE:  case GEU:
5670     case LT:  case LTU:  case LE:  case LEU:
5671     case UNEQ:  case LTGT:
5672     case UNGT:  case UNGE:
5673     case UNLT:  case UNLE:
5674     case UNORDERED: case ORDERED:
5675       /* If the first operand is a condition code, we can't do anything
5676          with it.  */
5677       if (GET_CODE (XEXP (x, 0)) == COMPARE
5678           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5679               && ! CC0_P (XEXP (x, 0))))
5680         {
5681           rtx op0 = XEXP (x, 0);
5682           rtx op1 = XEXP (x, 1);
5683           enum rtx_code new_code;
5684
5685           if (GET_CODE (op0) == COMPARE)
5686             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5687
5688           /* Simplify our comparison, if possible.  */
5689           new_code = simplify_comparison (code, &op0, &op1);
5690
5691           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5692              if only the low-order bit is possibly nonzero in X (such as when
5693              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5694              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5695              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5696              (plus X 1).
5697
5698              Remove any ZERO_EXTRACT we made when thinking this was a
5699              comparison.  It may now be simpler to use, e.g., an AND.  If a
5700              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5701              the call to make_compound_operation in the SET case.
5702
5703              Don't apply these optimizations if the caller would
5704              prefer a comparison rather than a value.
5705              E.g., for the condition in an IF_THEN_ELSE most targets need
5706              an explicit comparison.  */
5707
5708           if (in_cond)
5709             ;
5710
5711           else if (STORE_FLAG_VALUE == 1
5712               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5713               && op1 == const0_rtx
5714               && mode == GET_MODE (op0)
5715               && nonzero_bits (op0, mode) == 1)
5716             return gen_lowpart (mode,
5717                                 expand_compound_operation (op0));
5718
5719           else if (STORE_FLAG_VALUE == 1
5720                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5721                    && op1 == const0_rtx
5722                    && mode == GET_MODE (op0)
5723                    && (num_sign_bit_copies (op0, mode)
5724                        == GET_MODE_PRECISION (mode)))
5725             {
5726               op0 = expand_compound_operation (op0);
5727               return simplify_gen_unary (NEG, mode,
5728                                          gen_lowpart (mode, op0),
5729                                          mode);
5730             }
5731
5732           else if (STORE_FLAG_VALUE == 1
5733                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5734                    && op1 == const0_rtx
5735                    && mode == GET_MODE (op0)
5736                    && nonzero_bits (op0, mode) == 1)
5737             {
5738               op0 = expand_compound_operation (op0);
5739               return simplify_gen_binary (XOR, mode,
5740                                           gen_lowpart (mode, op0),
5741                                           const1_rtx);
5742             }
5743
5744           else if (STORE_FLAG_VALUE == 1
5745                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5746                    && op1 == const0_rtx
5747                    && mode == GET_MODE (op0)
5748                    && (num_sign_bit_copies (op0, mode)
5749                        == GET_MODE_PRECISION (mode)))
5750             {
5751               op0 = expand_compound_operation (op0);
5752               return plus_constant (mode, gen_lowpart (mode, op0), 1);
5753             }
5754
5755           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5756              those above.  */
5757           if (in_cond)
5758             ;
5759
5760           else if (STORE_FLAG_VALUE == -1
5761               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5762               && op1 == const0_rtx
5763               && (num_sign_bit_copies (op0, mode)
5764                   == GET_MODE_PRECISION (mode)))
5765             return gen_lowpart (mode,
5766                                 expand_compound_operation (op0));
5767
5768           else if (STORE_FLAG_VALUE == -1
5769                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5770                    && op1 == const0_rtx
5771                    && mode == GET_MODE (op0)
5772                    && nonzero_bits (op0, mode) == 1)
5773             {
5774               op0 = expand_compound_operation (op0);
5775               return simplify_gen_unary (NEG, mode,
5776                                          gen_lowpart (mode, op0),
5777                                          mode);
5778             }
5779
5780           else if (STORE_FLAG_VALUE == -1
5781                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5782                    && op1 == const0_rtx
5783                    && mode == GET_MODE (op0)
5784                    && (num_sign_bit_copies (op0, mode)
5785                        == GET_MODE_PRECISION (mode)))
5786             {
5787               op0 = expand_compound_operation (op0);
5788               return simplify_gen_unary (NOT, mode,
5789                                          gen_lowpart (mode, op0),
5790                                          mode);
5791             }
5792
5793           /* If X is 0/1, (eq X 0) is X-1.  */
5794           else if (STORE_FLAG_VALUE == -1
5795                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5796                    && op1 == const0_rtx
5797                    && mode == GET_MODE (op0)
5798                    && nonzero_bits (op0, mode) == 1)
5799             {
5800               op0 = expand_compound_operation (op0);
5801               return plus_constant (mode, gen_lowpart (mode, op0), -1);
5802             }
5803
5804           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5805              one bit that might be nonzero, we can convert (ne x 0) to
5806              (ashift x c) where C puts the bit in the sign bit.  Remove any
5807              AND with STORE_FLAG_VALUE when we are done, since we are only
5808              going to test the sign bit.  */
5809           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5810               && HWI_COMPUTABLE_MODE_P (mode)
5811               && val_signbit_p (mode, STORE_FLAG_VALUE)
5812               && op1 == const0_rtx
5813               && mode == GET_MODE (op0)
5814               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5815             {
5816               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5817                                         expand_compound_operation (op0),
5818                                         GET_MODE_PRECISION (mode) - 1 - i);
5819               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5820                 return XEXP (x, 0);
5821               else
5822                 return x;
5823             }
5824
5825           /* If the code changed, return a whole new comparison.
5826              We also need to avoid using SUBST in cases where
5827              simplify_comparison has widened a comparison with a CONST_INT,
5828              since in that case the wider CONST_INT may fail the sanity
5829              checks in do_SUBST.  */
5830           if (new_code != code
5831               || (CONST_INT_P (op1)
5832                   && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
5833                   && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
5834             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5835
5836           /* Otherwise, keep this operation, but maybe change its operands.
5837              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5838           SUBST (XEXP (x, 0), op0);
5839           SUBST (XEXP (x, 1), op1);
5840         }
5841       break;
5842
5843     case IF_THEN_ELSE:
5844       return simplify_if_then_else (x);
5845
5846     case ZERO_EXTRACT:
5847     case SIGN_EXTRACT:
5848     case ZERO_EXTEND:
5849     case SIGN_EXTEND:
5850       /* If we are processing SET_DEST, we are done.  */
5851       if (in_dest)
5852         return x;
5853
5854       return expand_compound_operation (x);
5855
5856     case SET:
5857       return simplify_set (x);
5858
5859     case AND:
5860     case IOR:
5861       return simplify_logical (x);
5862
5863     case ASHIFT:
5864     case LSHIFTRT:
5865     case ASHIFTRT:
5866     case ROTATE:
5867     case ROTATERT:
5868       /* If this is a shift by a constant amount, simplify it.  */
5869       if (CONST_INT_P (XEXP (x, 1)))
5870         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5871                                      INTVAL (XEXP (x, 1)));
5872
5873       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5874         SUBST (XEXP (x, 1),
5875                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5876                               ((unsigned HOST_WIDE_INT) 1
5877                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5878                               - 1,
5879                               0));
5880       break;
5881
5882     default:
5883       break;
5884     }
5885
5886   return x;
5887 }
5888 \f
5889 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5890
5891 static rtx
5892 simplify_if_then_else (rtx x)
5893 {
5894   enum machine_mode mode = GET_MODE (x);
5895   rtx cond = XEXP (x, 0);
5896   rtx true_rtx = XEXP (x, 1);
5897   rtx false_rtx = XEXP (x, 2);
5898   enum rtx_code true_code = GET_CODE (cond);
5899   int comparison_p = COMPARISON_P (cond);
5900   rtx temp;
5901   int i;
5902   enum rtx_code false_code;
5903   rtx reversed;
5904
5905   /* Simplify storing of the truth value.  */
5906   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5907     return simplify_gen_relational (true_code, mode, VOIDmode,
5908                                     XEXP (cond, 0), XEXP (cond, 1));
5909
5910   /* Also when the truth value has to be reversed.  */
5911   if (comparison_p
5912       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5913       && (reversed = reversed_comparison (cond, mode)))
5914     return reversed;
5915
5916   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5917      in it is being compared against certain values.  Get the true and false
5918      comparisons and see if that says anything about the value of each arm.  */
5919
5920   if (comparison_p
5921       && ((false_code = reversed_comparison_code (cond, NULL))
5922           != UNKNOWN)
5923       && REG_P (XEXP (cond, 0)))
5924     {
5925       HOST_WIDE_INT nzb;
5926       rtx from = XEXP (cond, 0);
5927       rtx true_val = XEXP (cond, 1);
5928       rtx false_val = true_val;
5929       int swapped = 0;
5930
5931       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5932
5933       if (false_code == EQ)
5934         {
5935           swapped = 1, true_code = EQ, false_code = NE;
5936           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5937         }
5938
5939       /* If we are comparing against zero and the expression being tested has
5940          only a single bit that might be nonzero, that is its value when it is
5941          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5942
5943       if (true_code == EQ && true_val == const0_rtx
5944           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5945         {
5946           false_code = EQ;
5947           false_val = gen_int_mode (nzb, GET_MODE (from));
5948         }
5949       else if (true_code == EQ && true_val == const0_rtx
5950                && (num_sign_bit_copies (from, GET_MODE (from))
5951                    == GET_MODE_PRECISION (GET_MODE (from))))
5952         {
5953           false_code = EQ;
5954           false_val = constm1_rtx;
5955         }
5956
5957       /* Now simplify an arm if we know the value of the register in the
5958          branch and it is used in the arm.  Be careful due to the potential
5959          of locally-shared RTL.  */
5960
5961       if (reg_mentioned_p (from, true_rtx))
5962         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5963                                       from, true_val),
5964                           pc_rtx, pc_rtx, 0, 0, 0);
5965       if (reg_mentioned_p (from, false_rtx))
5966         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5967                                    from, false_val),
5968                            pc_rtx, pc_rtx, 0, 0, 0);
5969
5970       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5971       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5972
5973       true_rtx = XEXP (x, 1);
5974       false_rtx = XEXP (x, 2);
5975       true_code = GET_CODE (cond);
5976     }
5977
5978   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5979      reversed, do so to avoid needing two sets of patterns for
5980      subtract-and-branch insns.  Similarly if we have a constant in the true
5981      arm, the false arm is the same as the first operand of the comparison, or
5982      the false arm is more complicated than the true arm.  */
5983
5984   if (comparison_p
5985       && reversed_comparison_code (cond, NULL) != UNKNOWN
5986       && (true_rtx == pc_rtx
5987           || (CONSTANT_P (true_rtx)
5988               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5989           || true_rtx == const0_rtx
5990           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5991           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5992               && !OBJECT_P (false_rtx))
5993           || reg_mentioned_p (true_rtx, false_rtx)
5994           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5995     {
5996       true_code = reversed_comparison_code (cond, NULL);
5997       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5998       SUBST (XEXP (x, 1), false_rtx);
5999       SUBST (XEXP (x, 2), true_rtx);
6000
6001       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6002       cond = XEXP (x, 0);
6003
6004       /* It is possible that the conditional has been simplified out.  */
6005       true_code = GET_CODE (cond);
6006       comparison_p = COMPARISON_P (cond);
6007     }
6008
6009   /* If the two arms are identical, we don't need the comparison.  */
6010
6011   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6012     return true_rtx;
6013
6014   /* Convert a == b ? b : a to "a".  */
6015   if (true_code == EQ && ! side_effects_p (cond)
6016       && !HONOR_NANS (mode)
6017       && rtx_equal_p (XEXP (cond, 0), false_rtx)
6018       && rtx_equal_p (XEXP (cond, 1), true_rtx))
6019     return false_rtx;
6020   else if (true_code == NE && ! side_effects_p (cond)
6021            && !HONOR_NANS (mode)
6022            && rtx_equal_p (XEXP (cond, 0), true_rtx)
6023            && rtx_equal_p (XEXP (cond, 1), false_rtx))
6024     return true_rtx;
6025
6026   /* Look for cases where we have (abs x) or (neg (abs X)).  */
6027
6028   if (GET_MODE_CLASS (mode) == MODE_INT
6029       && comparison_p
6030       && XEXP (cond, 1) == const0_rtx
6031       && GET_CODE (false_rtx) == NEG
6032       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6033       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6034       && ! side_effects_p (true_rtx))
6035     switch (true_code)
6036       {
6037       case GT:
6038       case GE:
6039         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6040       case LT:
6041       case LE:
6042         return
6043           simplify_gen_unary (NEG, mode,
6044                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6045                               mode);
6046       default:
6047         break;
6048       }
6049
6050   /* Look for MIN or MAX.  */
6051
6052   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6053       && comparison_p
6054       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6055       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6056       && ! side_effects_p (cond))
6057     switch (true_code)
6058       {
6059       case GE:
6060       case GT:
6061         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6062       case LE:
6063       case LT:
6064         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6065       case GEU:
6066       case GTU:
6067         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6068       case LEU:
6069       case LTU:
6070         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6071       default:
6072         break;
6073       }
6074
6075   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6076      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6077      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6078      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6079      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6080      neither 1 or -1, but it isn't worth checking for.  */
6081
6082   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6083       && comparison_p
6084       && GET_MODE_CLASS (mode) == MODE_INT
6085       && ! side_effects_p (x))
6086     {
6087       rtx t = make_compound_operation (true_rtx, SET);
6088       rtx f = make_compound_operation (false_rtx, SET);
6089       rtx cond_op0 = XEXP (cond, 0);
6090       rtx cond_op1 = XEXP (cond, 1);
6091       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6092       enum machine_mode m = mode;
6093       rtx z = 0, c1 = NULL_RTX;
6094
6095       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6096            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6097            || GET_CODE (t) == ASHIFT
6098            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6099           && rtx_equal_p (XEXP (t, 0), f))
6100         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6101
6102       /* If an identity-zero op is commutative, check whether there
6103          would be a match if we swapped the operands.  */
6104       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6105                 || GET_CODE (t) == XOR)
6106                && rtx_equal_p (XEXP (t, 1), f))
6107         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6108       else if (GET_CODE (t) == SIGN_EXTEND
6109                && (GET_CODE (XEXP (t, 0)) == PLUS
6110                    || GET_CODE (XEXP (t, 0)) == MINUS
6111                    || GET_CODE (XEXP (t, 0)) == IOR
6112                    || GET_CODE (XEXP (t, 0)) == XOR
6113                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6114                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6115                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6116                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6117                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6118                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6119                && (num_sign_bit_copies (f, GET_MODE (f))
6120                    > (unsigned int)
6121                      (GET_MODE_PRECISION (mode)
6122                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6123         {
6124           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6125           extend_op = SIGN_EXTEND;
6126           m = GET_MODE (XEXP (t, 0));
6127         }
6128       else if (GET_CODE (t) == SIGN_EXTEND
6129                && (GET_CODE (XEXP (t, 0)) == PLUS
6130                    || GET_CODE (XEXP (t, 0)) == IOR
6131                    || GET_CODE (XEXP (t, 0)) == XOR)
6132                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6133                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6134                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6135                && (num_sign_bit_copies (f, GET_MODE (f))
6136                    > (unsigned int)
6137                      (GET_MODE_PRECISION (mode)
6138                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6139         {
6140           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6141           extend_op = SIGN_EXTEND;
6142           m = GET_MODE (XEXP (t, 0));
6143         }
6144       else if (GET_CODE (t) == ZERO_EXTEND
6145                && (GET_CODE (XEXP (t, 0)) == PLUS
6146                    || GET_CODE (XEXP (t, 0)) == MINUS
6147                    || GET_CODE (XEXP (t, 0)) == IOR
6148                    || GET_CODE (XEXP (t, 0)) == XOR
6149                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6150                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6151                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6152                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6153                && HWI_COMPUTABLE_MODE_P (mode)
6154                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6155                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6156                && ((nonzero_bits (f, GET_MODE (f))
6157                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6158                    == 0))
6159         {
6160           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6161           extend_op = ZERO_EXTEND;
6162           m = GET_MODE (XEXP (t, 0));
6163         }
6164       else if (GET_CODE (t) == ZERO_EXTEND
6165                && (GET_CODE (XEXP (t, 0)) == PLUS
6166                    || GET_CODE (XEXP (t, 0)) == IOR
6167                    || GET_CODE (XEXP (t, 0)) == XOR)
6168                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6169                && HWI_COMPUTABLE_MODE_P (mode)
6170                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6171                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6172                && ((nonzero_bits (f, GET_MODE (f))
6173                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6174                    == 0))
6175         {
6176           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6177           extend_op = ZERO_EXTEND;
6178           m = GET_MODE (XEXP (t, 0));
6179         }
6180
6181       if (z)
6182         {
6183           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6184                                                  cond_op0, cond_op1),
6185                         pc_rtx, pc_rtx, 0, 0, 0);
6186           temp = simplify_gen_binary (MULT, m, temp,
6187                                       simplify_gen_binary (MULT, m, c1,
6188                                                            const_true_rtx));
6189           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6190           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6191
6192           if (extend_op != UNKNOWN)
6193             temp = simplify_gen_unary (extend_op, mode, temp, m);
6194
6195           return temp;
6196         }
6197     }
6198
6199   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6200      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6201      negation of a single bit, we can convert this operation to a shift.  We
6202      can actually do this more generally, but it doesn't seem worth it.  */
6203
6204   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6205       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6206       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6207            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6208           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6209                == GET_MODE_PRECISION (mode))
6210               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6211     return
6212       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6213                             gen_lowpart (mode, XEXP (cond, 0)), i);
6214
6215   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6216   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6217       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6218       && GET_MODE (XEXP (cond, 0)) == mode
6219       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6220           == nonzero_bits (XEXP (cond, 0), mode)
6221       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6222     return XEXP (cond, 0);
6223
6224   return x;
6225 }
6226 \f
6227 /* Simplify X, a SET expression.  Return the new expression.  */
6228
6229 static rtx
6230 simplify_set (rtx x)
6231 {
6232   rtx src = SET_SRC (x);
6233   rtx dest = SET_DEST (x);
6234   enum machine_mode mode
6235     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6236   rtx other_insn;
6237   rtx *cc_use;
6238
6239   /* (set (pc) (return)) gets written as (return).  */
6240   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6241     return src;
6242
6243   /* Now that we know for sure which bits of SRC we are using, see if we can
6244      simplify the expression for the object knowing that we only need the
6245      low-order bits.  */
6246
6247   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6248     {
6249       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6250       SUBST (SET_SRC (x), src);
6251     }
6252
6253   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6254      the comparison result and try to simplify it unless we already have used
6255      undobuf.other_insn.  */
6256   if ((GET_MODE_CLASS (mode) == MODE_CC
6257        || GET_CODE (src) == COMPARE
6258        || CC0_P (dest))
6259       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6260       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6261       && COMPARISON_P (*cc_use)
6262       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6263     {
6264       enum rtx_code old_code = GET_CODE (*cc_use);
6265       enum rtx_code new_code;
6266       rtx op0, op1, tmp;
6267       int other_changed = 0;
6268       rtx inner_compare = NULL_RTX;
6269       enum machine_mode compare_mode = GET_MODE (dest);
6270
6271       if (GET_CODE (src) == COMPARE)
6272         {
6273           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6274           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6275             {
6276               inner_compare = op0;
6277               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6278             }
6279         }
6280       else
6281         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6282
6283       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6284                                            op0, op1);
6285       if (!tmp)
6286         new_code = old_code;
6287       else if (!CONSTANT_P (tmp))
6288         {
6289           new_code = GET_CODE (tmp);
6290           op0 = XEXP (tmp, 0);
6291           op1 = XEXP (tmp, 1);
6292         }
6293       else
6294         {
6295           rtx pat = PATTERN (other_insn);
6296           undobuf.other_insn = other_insn;
6297           SUBST (*cc_use, tmp);
6298
6299           /* Attempt to simplify CC user.  */
6300           if (GET_CODE (pat) == SET)
6301             {
6302               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6303               if (new_rtx != NULL_RTX)
6304                 SUBST (SET_SRC (pat), new_rtx);
6305             }
6306
6307           /* Convert X into a no-op move.  */
6308           SUBST (SET_DEST (x), pc_rtx);
6309           SUBST (SET_SRC (x), pc_rtx);
6310           return x;
6311         }
6312
6313       /* Simplify our comparison, if possible.  */
6314       new_code = simplify_comparison (new_code, &op0, &op1);
6315
6316 #ifdef SELECT_CC_MODE
6317       /* If this machine has CC modes other than CCmode, check to see if we
6318          need to use a different CC mode here.  */
6319       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6320         compare_mode = GET_MODE (op0);
6321       else if (inner_compare
6322                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6323                && new_code == old_code
6324                && op0 == XEXP (inner_compare, 0)
6325                && op1 == XEXP (inner_compare, 1))
6326         compare_mode = GET_MODE (inner_compare);
6327       else
6328         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6329
6330 #ifndef HAVE_cc0
6331       /* If the mode changed, we have to change SET_DEST, the mode in the
6332          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6333          a hard register, just build new versions with the proper mode.  If it
6334          is a pseudo, we lose unless it is only time we set the pseudo, in
6335          which case we can safely change its mode.  */
6336       if (compare_mode != GET_MODE (dest))
6337         {
6338           if (can_change_dest_mode (dest, 0, compare_mode))
6339             {
6340               unsigned int regno = REGNO (dest);
6341               rtx new_dest;
6342
6343               if (regno < FIRST_PSEUDO_REGISTER)
6344                 new_dest = gen_rtx_REG (compare_mode, regno);
6345               else
6346                 {
6347                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6348                   new_dest = regno_reg_rtx[regno];
6349                 }
6350
6351               SUBST (SET_DEST (x), new_dest);
6352               SUBST (XEXP (*cc_use, 0), new_dest);
6353               other_changed = 1;
6354
6355               dest = new_dest;
6356             }
6357         }
6358 #endif  /* cc0 */
6359 #endif  /* SELECT_CC_MODE */
6360
6361       /* If the code changed, we have to build a new comparison in
6362          undobuf.other_insn.  */
6363       if (new_code != old_code)
6364         {
6365           int other_changed_previously = other_changed;
6366           unsigned HOST_WIDE_INT mask;
6367           rtx old_cc_use = *cc_use;
6368
6369           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6370                                           dest, const0_rtx));
6371           other_changed = 1;
6372
6373           /* If the only change we made was to change an EQ into an NE or
6374              vice versa, OP0 has only one bit that might be nonzero, and OP1
6375              is zero, check if changing the user of the condition code will
6376              produce a valid insn.  If it won't, we can keep the original code
6377              in that insn by surrounding our operation with an XOR.  */
6378
6379           if (((old_code == NE && new_code == EQ)
6380                || (old_code == EQ && new_code == NE))
6381               && ! other_changed_previously && op1 == const0_rtx
6382               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6383               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6384             {
6385               rtx pat = PATTERN (other_insn), note = 0;
6386
6387               if ((recog_for_combine (&pat, other_insn, &note) < 0
6388                    && ! check_asm_operands (pat)))
6389                 {
6390                   *cc_use = old_cc_use;
6391                   other_changed = 0;
6392
6393                   op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6394                                              gen_int_mode (mask,
6395                                                            GET_MODE (op0)));
6396                 }
6397             }
6398         }
6399
6400       if (other_changed)
6401         undobuf.other_insn = other_insn;
6402
6403       /* Otherwise, if we didn't previously have a COMPARE in the
6404          correct mode, we need one.  */
6405       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6406         {
6407           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6408           src = SET_SRC (x);
6409         }
6410       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6411         {
6412           SUBST (SET_SRC (x), op0);
6413           src = SET_SRC (x);
6414         }
6415       /* Otherwise, update the COMPARE if needed.  */
6416       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6417         {
6418           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6419           src = SET_SRC (x);
6420         }
6421     }
6422   else
6423     {
6424       /* Get SET_SRC in a form where we have placed back any
6425          compound expressions.  Then do the checks below.  */
6426       src = make_compound_operation (src, SET);
6427       SUBST (SET_SRC (x), src);
6428     }
6429
6430   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6431      and X being a REG or (subreg (reg)), we may be able to convert this to
6432      (set (subreg:m2 x) (op)).
6433
6434      We can always do this if M1 is narrower than M2 because that means that
6435      we only care about the low bits of the result.
6436
6437      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6438      perform a narrower operation than requested since the high-order bits will
6439      be undefined.  On machine where it is defined, this transformation is safe
6440      as long as M1 and M2 have the same number of words.  */
6441
6442   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6443       && !OBJECT_P (SUBREG_REG (src))
6444       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6445            / UNITS_PER_WORD)
6446           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6447                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6448 #ifndef WORD_REGISTER_OPERATIONS
6449       && (GET_MODE_SIZE (GET_MODE (src))
6450         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6451 #endif
6452 #ifdef CANNOT_CHANGE_MODE_CLASS
6453       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6454             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6455                                          GET_MODE (SUBREG_REG (src)),
6456                                          GET_MODE (src)))
6457 #endif
6458       && (REG_P (dest)
6459           || (GET_CODE (dest) == SUBREG
6460               && REG_P (SUBREG_REG (dest)))))
6461     {
6462       SUBST (SET_DEST (x),
6463              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6464                                       dest));
6465       SUBST (SET_SRC (x), SUBREG_REG (src));
6466
6467       src = SET_SRC (x), dest = SET_DEST (x);
6468     }
6469
6470 #ifdef HAVE_cc0
6471   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6472      in SRC.  */
6473   if (dest == cc0_rtx
6474       && GET_CODE (src) == SUBREG
6475       && subreg_lowpart_p (src)
6476       && (GET_MODE_PRECISION (GET_MODE (src))
6477           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6478     {
6479       rtx inner = SUBREG_REG (src);
6480       enum machine_mode inner_mode = GET_MODE (inner);
6481
6482       /* Here we make sure that we don't have a sign bit on.  */
6483       if (val_signbit_known_clear_p (GET_MODE (src),
6484                                      nonzero_bits (inner, inner_mode)))
6485         {
6486           SUBST (SET_SRC (x), inner);
6487           src = SET_SRC (x);
6488         }
6489     }
6490 #endif
6491
6492 #ifdef LOAD_EXTEND_OP
6493   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6494      would require a paradoxical subreg.  Replace the subreg with a
6495      zero_extend to avoid the reload that would otherwise be required.  */
6496
6497   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6498       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6499       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6500       && SUBREG_BYTE (src) == 0
6501       && paradoxical_subreg_p (src)
6502       && MEM_P (SUBREG_REG (src)))
6503     {
6504       SUBST (SET_SRC (x),
6505              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6506                             GET_MODE (src), SUBREG_REG (src)));
6507
6508       src = SET_SRC (x);
6509     }
6510 #endif
6511
6512   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6513      are comparing an item known to be 0 or -1 against 0, use a logical
6514      operation instead. Check for one of the arms being an IOR of the other
6515      arm with some value.  We compute three terms to be IOR'ed together.  In
6516      practice, at most two will be nonzero.  Then we do the IOR's.  */
6517
6518   if (GET_CODE (dest) != PC
6519       && GET_CODE (src) == IF_THEN_ELSE
6520       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6521       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6522       && XEXP (XEXP (src, 0), 1) == const0_rtx
6523       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6524 #ifdef HAVE_conditional_move
6525       && ! can_conditionally_move_p (GET_MODE (src))
6526 #endif
6527       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6528                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6529           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6530       && ! side_effects_p (src))
6531     {
6532       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6533                       ? XEXP (src, 1) : XEXP (src, 2));
6534       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6535                    ? XEXP (src, 2) : XEXP (src, 1));
6536       rtx term1 = const0_rtx, term2, term3;
6537
6538       if (GET_CODE (true_rtx) == IOR
6539           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6540         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6541       else if (GET_CODE (true_rtx) == IOR
6542                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6543         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6544       else if (GET_CODE (false_rtx) == IOR
6545                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6546         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6547       else if (GET_CODE (false_rtx) == IOR
6548                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6549         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6550
6551       term2 = simplify_gen_binary (AND, GET_MODE (src),
6552                                    XEXP (XEXP (src, 0), 0), true_rtx);
6553       term3 = simplify_gen_binary (AND, GET_MODE (src),
6554                                    simplify_gen_unary (NOT, GET_MODE (src),
6555                                                        XEXP (XEXP (src, 0), 0),
6556                                                        GET_MODE (src)),
6557                                    false_rtx);
6558
6559       SUBST (SET_SRC (x),
6560              simplify_gen_binary (IOR, GET_MODE (src),
6561                                   simplify_gen_binary (IOR, GET_MODE (src),
6562                                                        term1, term2),
6563                                   term3));
6564
6565       src = SET_SRC (x);
6566     }
6567
6568   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6569      whole thing fail.  */
6570   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6571     return src;
6572   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6573     return dest;
6574   else
6575     /* Convert this into a field assignment operation, if possible.  */
6576     return make_field_assignment (x);
6577 }
6578 \f
6579 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6580    result.  */
6581
6582 static rtx
6583 simplify_logical (rtx x)
6584 {
6585   enum machine_mode mode = GET_MODE (x);
6586   rtx op0 = XEXP (x, 0);
6587   rtx op1 = XEXP (x, 1);
6588
6589   switch (GET_CODE (x))
6590     {
6591     case AND:
6592       /* We can call simplify_and_const_int only if we don't lose
6593          any (sign) bits when converting INTVAL (op1) to
6594          "unsigned HOST_WIDE_INT".  */
6595       if (CONST_INT_P (op1)
6596           && (HWI_COMPUTABLE_MODE_P (mode)
6597               || INTVAL (op1) > 0))
6598         {
6599           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6600           if (GET_CODE (x) != AND)
6601             return x;
6602
6603           op0 = XEXP (x, 0);
6604           op1 = XEXP (x, 1);
6605         }
6606
6607       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6608          apply the distributive law and then the inverse distributive
6609          law to see if things simplify.  */
6610       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6611         {
6612           rtx result = distribute_and_simplify_rtx (x, 0);
6613           if (result)
6614             return result;
6615         }
6616       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6617         {
6618           rtx result = distribute_and_simplify_rtx (x, 1);
6619           if (result)
6620             return result;
6621         }
6622       break;
6623
6624     case IOR:
6625       /* If we have (ior (and A B) C), apply the distributive law and then
6626          the inverse distributive law to see if things simplify.  */
6627
6628       if (GET_CODE (op0) == AND)
6629         {
6630           rtx result = distribute_and_simplify_rtx (x, 0);
6631           if (result)
6632             return result;
6633         }
6634
6635       if (GET_CODE (op1) == AND)
6636         {
6637           rtx result = distribute_and_simplify_rtx (x, 1);
6638           if (result)
6639             return result;
6640         }
6641       break;
6642
6643     default:
6644       gcc_unreachable ();
6645     }
6646
6647   return x;
6648 }
6649 \f
6650 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6651    operations" because they can be replaced with two more basic operations.
6652    ZERO_EXTEND is also considered "compound" because it can be replaced with
6653    an AND operation, which is simpler, though only one operation.
6654
6655    The function expand_compound_operation is called with an rtx expression
6656    and will convert it to the appropriate shifts and AND operations,
6657    simplifying at each stage.
6658
6659    The function make_compound_operation is called to convert an expression
6660    consisting of shifts and ANDs into the equivalent compound expression.
6661    It is the inverse of this function, loosely speaking.  */
6662
6663 static rtx
6664 expand_compound_operation (rtx x)
6665 {
6666   unsigned HOST_WIDE_INT pos = 0, len;
6667   int unsignedp = 0;
6668   unsigned int modewidth;
6669   rtx tem;
6670
6671   switch (GET_CODE (x))
6672     {
6673     case ZERO_EXTEND:
6674       unsignedp = 1;
6675     case SIGN_EXTEND:
6676       /* We can't necessarily use a const_int for a multiword mode;
6677          it depends on implicitly extending the value.
6678          Since we don't know the right way to extend it,
6679          we can't tell whether the implicit way is right.
6680
6681          Even for a mode that is no wider than a const_int,
6682          we can't win, because we need to sign extend one of its bits through
6683          the rest of it, and we don't know which bit.  */
6684       if (CONST_INT_P (XEXP (x, 0)))
6685         return x;
6686
6687       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6688          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6689          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6690          reloaded. If not for that, MEM's would very rarely be safe.
6691
6692          Reject MODEs bigger than a word, because we might not be able
6693          to reference a two-register group starting with an arbitrary register
6694          (and currently gen_lowpart might crash for a SUBREG).  */
6695
6696       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6697         return x;
6698
6699       /* Reject MODEs that aren't scalar integers because turning vector
6700          or complex modes into shifts causes problems.  */
6701
6702       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6703         return x;
6704
6705       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6706       /* If the inner object has VOIDmode (the only way this can happen
6707          is if it is an ASM_OPERANDS), we can't do anything since we don't
6708          know how much masking to do.  */
6709       if (len == 0)
6710         return x;
6711
6712       break;
6713
6714     case ZERO_EXTRACT:
6715       unsignedp = 1;
6716
6717       /* ... fall through ...  */
6718
6719     case SIGN_EXTRACT:
6720       /* If the operand is a CLOBBER, just return it.  */
6721       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6722         return XEXP (x, 0);
6723
6724       if (!CONST_INT_P (XEXP (x, 1))
6725           || !CONST_INT_P (XEXP (x, 2))
6726           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6727         return x;
6728
6729       /* Reject MODEs that aren't scalar integers because turning vector
6730          or complex modes into shifts causes problems.  */
6731
6732       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6733         return x;
6734
6735       len = INTVAL (XEXP (x, 1));
6736       pos = INTVAL (XEXP (x, 2));
6737
6738       /* This should stay within the object being extracted, fail otherwise.  */
6739       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6740         return x;
6741
6742       if (BITS_BIG_ENDIAN)
6743         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6744
6745       break;
6746
6747     default:
6748       return x;
6749     }
6750   /* Convert sign extension to zero extension, if we know that the high
6751      bit is not set, as this is easier to optimize.  It will be converted
6752      back to cheaper alternative in make_extraction.  */
6753   if (GET_CODE (x) == SIGN_EXTEND
6754       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6755           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6756                 & ~(((unsigned HOST_WIDE_INT)
6757                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6758                      >> 1))
6759                == 0)))
6760     {
6761       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6762       rtx temp2 = expand_compound_operation (temp);
6763
6764       /* Make sure this is a profitable operation.  */
6765       if (set_src_cost (x, optimize_this_for_speed_p)
6766           > set_src_cost (temp2, optimize_this_for_speed_p))
6767        return temp2;
6768       else if (set_src_cost (x, optimize_this_for_speed_p)
6769                > set_src_cost (temp, optimize_this_for_speed_p))
6770        return temp;
6771       else
6772        return x;
6773     }
6774
6775   /* We can optimize some special cases of ZERO_EXTEND.  */
6776   if (GET_CODE (x) == ZERO_EXTEND)
6777     {
6778       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6779          know that the last value didn't have any inappropriate bits
6780          set.  */
6781       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6782           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6783           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6784           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6785               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6786         return XEXP (XEXP (x, 0), 0);
6787
6788       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6789       if (GET_CODE (XEXP (x, 0)) == SUBREG
6790           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6791           && subreg_lowpart_p (XEXP (x, 0))
6792           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6793           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6794               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6795         return SUBREG_REG (XEXP (x, 0));
6796
6797       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6798          is a comparison and STORE_FLAG_VALUE permits.  This is like
6799          the first case, but it works even when GET_MODE (x) is larger
6800          than HOST_WIDE_INT.  */
6801       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6802           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6803           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6804           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6805               <= HOST_BITS_PER_WIDE_INT)
6806           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6807         return XEXP (XEXP (x, 0), 0);
6808
6809       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6810       if (GET_CODE (XEXP (x, 0)) == SUBREG
6811           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6812           && subreg_lowpart_p (XEXP (x, 0))
6813           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6814           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6815               <= HOST_BITS_PER_WIDE_INT)
6816           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6817         return SUBREG_REG (XEXP (x, 0));
6818
6819     }
6820
6821   /* If we reach here, we want to return a pair of shifts.  The inner
6822      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6823      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6824      logical depending on the value of UNSIGNEDP.
6825
6826      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6827      converted into an AND of a shift.
6828
6829      We must check for the case where the left shift would have a negative
6830      count.  This can happen in a case like (x >> 31) & 255 on machines
6831      that can't shift by a constant.  On those machines, we would first
6832      combine the shift with the AND to produce a variable-position
6833      extraction.  Then the constant of 31 would be substituted in
6834      to produce such a position.  */
6835
6836   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6837   if (modewidth >= pos + len)
6838     {
6839       enum machine_mode mode = GET_MODE (x);
6840       tem = gen_lowpart (mode, XEXP (x, 0));
6841       if (!tem || GET_CODE (tem) == CLOBBER)
6842         return x;
6843       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6844                                   tem, modewidth - pos - len);
6845       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6846                                   mode, tem, modewidth - len);
6847     }
6848   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6849     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6850                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6851                                                         GET_MODE (x),
6852                                                         XEXP (x, 0), pos),
6853                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6854   else
6855     /* Any other cases we can't handle.  */
6856     return x;
6857
6858   /* If we couldn't do this for some reason, return the original
6859      expression.  */
6860   if (GET_CODE (tem) == CLOBBER)
6861     return x;
6862
6863   return tem;
6864 }
6865 \f
6866 /* X is a SET which contains an assignment of one object into
6867    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6868    or certain SUBREGS). If possible, convert it into a series of
6869    logical operations.
6870
6871    We half-heartedly support variable positions, but do not at all
6872    support variable lengths.  */
6873
6874 static const_rtx
6875 expand_field_assignment (const_rtx x)
6876 {
6877   rtx inner;
6878   rtx pos;                      /* Always counts from low bit.  */
6879   int len;
6880   rtx mask, cleared, masked;
6881   enum machine_mode compute_mode;
6882
6883   /* Loop until we find something we can't simplify.  */
6884   while (1)
6885     {
6886       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6887           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6888         {
6889           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6890           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6891           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6892         }
6893       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6894                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6895         {
6896           inner = XEXP (SET_DEST (x), 0);
6897           len = INTVAL (XEXP (SET_DEST (x), 1));
6898           pos = XEXP (SET_DEST (x), 2);
6899
6900           /* A constant position should stay within the width of INNER.  */
6901           if (CONST_INT_P (pos)
6902               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6903             break;
6904
6905           if (BITS_BIG_ENDIAN)
6906             {
6907               if (CONST_INT_P (pos))
6908                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6909                                - INTVAL (pos));
6910               else if (GET_CODE (pos) == MINUS
6911                        && CONST_INT_P (XEXP (pos, 1))
6912                        && (INTVAL (XEXP (pos, 1))
6913                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6914                 /* If position is ADJUST - X, new position is X.  */
6915                 pos = XEXP (pos, 0);
6916               else
6917                 {
6918                   HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner));
6919                   pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6920                                              gen_int_mode (prec - len,
6921                                                            GET_MODE (pos)),
6922                                              pos);
6923                 }
6924             }
6925         }
6926
6927       /* A SUBREG between two modes that occupy the same numbers of words
6928          can be done by moving the SUBREG to the source.  */
6929       else if (GET_CODE (SET_DEST (x)) == SUBREG
6930                /* We need SUBREGs to compute nonzero_bits properly.  */
6931                && nonzero_sign_valid
6932                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6933                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6934                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6935                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6936         {
6937           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6938                            gen_lowpart
6939                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6940                             SET_SRC (x)));
6941           continue;
6942         }
6943       else
6944         break;
6945
6946       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6947         inner = SUBREG_REG (inner);
6948
6949       compute_mode = GET_MODE (inner);
6950
6951       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
6952       if (! SCALAR_INT_MODE_P (compute_mode))
6953         {
6954           enum machine_mode imode;
6955
6956           /* Don't do anything for vector or complex integral types.  */
6957           if (! FLOAT_MODE_P (compute_mode))
6958             break;
6959
6960           /* Try to find an integral mode to pun with.  */
6961           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6962           if (imode == BLKmode)
6963             break;
6964
6965           compute_mode = imode;
6966           inner = gen_lowpart (imode, inner);
6967         }
6968
6969       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
6970       if (len >= HOST_BITS_PER_WIDE_INT)
6971         break;
6972
6973       /* Now compute the equivalent expression.  Make a copy of INNER
6974          for the SET_DEST in case it is a MEM into which we will substitute;
6975          we don't want shared RTL in that case.  */
6976       mask = gen_int_mode (((unsigned HOST_WIDE_INT) 1 << len) - 1,
6977                            compute_mode);
6978       cleared = simplify_gen_binary (AND, compute_mode,
6979                                      simplify_gen_unary (NOT, compute_mode,
6980                                        simplify_gen_binary (ASHIFT,
6981                                                             compute_mode,
6982                                                             mask, pos),
6983                                        compute_mode),
6984                                      inner);
6985       masked = simplify_gen_binary (ASHIFT, compute_mode,
6986                                     simplify_gen_binary (
6987                                       AND, compute_mode,
6988                                       gen_lowpart (compute_mode, SET_SRC (x)),
6989                                       mask),
6990                                     pos);
6991
6992       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6993                        simplify_gen_binary (IOR, compute_mode,
6994                                             cleared, masked));
6995     }
6996
6997   return x;
6998 }
6999 \f
7000 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
7001    it is an RTX that represents the (variable) starting position; otherwise,
7002    POS is the (constant) starting bit position.  Both are counted from the LSB.
7003
7004    UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7005
7006    IN_DEST is nonzero if this is a reference in the destination of a SET.
7007    This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
7008    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7009    be used.
7010
7011    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
7012    ZERO_EXTRACT should be built even for bits starting at bit 0.
7013
7014    MODE is the desired mode of the result (if IN_DEST == 0).
7015
7016    The result is an RTX for the extraction or NULL_RTX if the target
7017    can't handle it.  */
7018
7019 static rtx
7020 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7021                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7022                  int in_dest, int in_compare)
7023 {
7024   /* This mode describes the size of the storage area
7025      to fetch the overall value from.  Within that, we
7026      ignore the POS lowest bits, etc.  */
7027   enum machine_mode is_mode = GET_MODE (inner);
7028   enum machine_mode inner_mode;
7029   enum machine_mode wanted_inner_mode;
7030   enum machine_mode wanted_inner_reg_mode = word_mode;
7031   enum machine_mode pos_mode = word_mode;
7032   enum machine_mode extraction_mode = word_mode;
7033   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7034   rtx new_rtx = 0;
7035   rtx orig_pos_rtx = pos_rtx;
7036   HOST_WIDE_INT orig_pos;
7037
7038   if (pos_rtx && CONST_INT_P (pos_rtx))
7039     pos = INTVAL (pos_rtx), pos_rtx = 0;
7040
7041   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7042     {
7043       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7044          consider just the QI as the memory to extract from.
7045          The subreg adds or removes high bits; its mode is
7046          irrelevant to the meaning of this extraction,
7047          since POS and LEN count from the lsb.  */
7048       if (MEM_P (SUBREG_REG (inner)))
7049         is_mode = GET_MODE (SUBREG_REG (inner));
7050       inner = SUBREG_REG (inner);
7051     }
7052   else if (GET_CODE (inner) == ASHIFT
7053            && CONST_INT_P (XEXP (inner, 1))
7054            && pos_rtx == 0 && pos == 0
7055            && len > UINTVAL (XEXP (inner, 1)))
7056     {
7057       /* We're extracting the least significant bits of an rtx
7058          (ashift X (const_int C)), where LEN > C.  Extract the
7059          least significant (LEN - C) bits of X, giving an rtx
7060          whose mode is MODE, then shift it left C times.  */
7061       new_rtx = make_extraction (mode, XEXP (inner, 0),
7062                              0, 0, len - INTVAL (XEXP (inner, 1)),
7063                              unsignedp, in_dest, in_compare);
7064       if (new_rtx != 0)
7065         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7066     }
7067   else if (GET_CODE (inner) == TRUNCATE)
7068     inner = XEXP (inner, 0);
7069
7070   inner_mode = GET_MODE (inner);
7071
7072   /* See if this can be done without an extraction.  We never can if the
7073      width of the field is not the same as that of some integer mode. For
7074      registers, we can only avoid the extraction if the position is at the
7075      low-order bit and this is either not in the destination or we have the
7076      appropriate STRICT_LOW_PART operation available.
7077
7078      For MEM, we can avoid an extract if the field starts on an appropriate
7079      boundary and we can change the mode of the memory reference.  */
7080
7081   if (tmode != BLKmode
7082       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7083            && !MEM_P (inner)
7084            && (inner_mode == tmode
7085                || !REG_P (inner)
7086                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7087                || reg_truncated_to_mode (tmode, inner))
7088            && (! in_dest
7089                || (REG_P (inner)
7090                    && have_insn_for (STRICT_LOW_PART, tmode))))
7091           || (MEM_P (inner) && pos_rtx == 0
7092               && (pos
7093                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7094                      : BITS_PER_UNIT)) == 0
7095               /* We can't do this if we are widening INNER_MODE (it
7096                  may not be aligned, for one thing).  */
7097               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7098               && (inner_mode == tmode
7099                   || (! mode_dependent_address_p (XEXP (inner, 0),
7100                                                   MEM_ADDR_SPACE (inner))
7101                       && ! MEM_VOLATILE_P (inner))))))
7102     {
7103       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7104          field.  If the original and current mode are the same, we need not
7105          adjust the offset.  Otherwise, we do if bytes big endian.
7106
7107          If INNER is not a MEM, get a piece consisting of just the field
7108          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7109
7110       if (MEM_P (inner))
7111         {
7112           HOST_WIDE_INT offset;
7113
7114           /* POS counts from lsb, but make OFFSET count in memory order.  */
7115           if (BYTES_BIG_ENDIAN)
7116             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7117           else
7118             offset = pos / BITS_PER_UNIT;
7119
7120           new_rtx = adjust_address_nv (inner, tmode, offset);
7121         }
7122       else if (REG_P (inner))
7123         {
7124           if (tmode != inner_mode)
7125             {
7126               /* We can't call gen_lowpart in a DEST since we
7127                  always want a SUBREG (see below) and it would sometimes
7128                  return a new hard register.  */
7129               if (pos || in_dest)
7130                 {
7131                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7132
7133                   if (WORDS_BIG_ENDIAN
7134                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7135                     final_word = ((GET_MODE_SIZE (inner_mode)
7136                                    - GET_MODE_SIZE (tmode))
7137                                   / UNITS_PER_WORD) - final_word;
7138
7139                   final_word *= UNITS_PER_WORD;
7140                   if (BYTES_BIG_ENDIAN &&
7141                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7142                     final_word += (GET_MODE_SIZE (inner_mode)
7143                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7144
7145                   /* Avoid creating invalid subregs, for example when
7146                      simplifying (x>>32)&255.  */
7147                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7148                     return NULL_RTX;
7149
7150                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7151                 }
7152               else
7153                 new_rtx = gen_lowpart (tmode, inner);
7154             }
7155           else
7156             new_rtx = inner;
7157         }
7158       else
7159         new_rtx = force_to_mode (inner, tmode,
7160                              len >= HOST_BITS_PER_WIDE_INT
7161                              ? ~(unsigned HOST_WIDE_INT) 0
7162                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7163                              0);
7164
7165       /* If this extraction is going into the destination of a SET,
7166          make a STRICT_LOW_PART unless we made a MEM.  */
7167
7168       if (in_dest)
7169         return (MEM_P (new_rtx) ? new_rtx
7170                 : (GET_CODE (new_rtx) != SUBREG
7171                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7172                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7173
7174       if (mode == tmode)
7175         return new_rtx;
7176
7177       if (CONST_SCALAR_INT_P (new_rtx))
7178         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7179                                          mode, new_rtx, tmode);
7180
7181       /* If we know that no extraneous bits are set, and that the high
7182          bit is not set, convert the extraction to the cheaper of
7183          sign and zero extension, that are equivalent in these cases.  */
7184       if (flag_expensive_optimizations
7185           && (HWI_COMPUTABLE_MODE_P (tmode)
7186               && ((nonzero_bits (new_rtx, tmode)
7187                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7188                   == 0)))
7189         {
7190           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7191           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7192
7193           /* Prefer ZERO_EXTENSION, since it gives more information to
7194              backends.  */
7195           if (set_src_cost (temp, optimize_this_for_speed_p)
7196               <= set_src_cost (temp1, optimize_this_for_speed_p))
7197             return temp;
7198           return temp1;
7199         }
7200
7201       /* Otherwise, sign- or zero-extend unless we already are in the
7202          proper mode.  */
7203
7204       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7205                              mode, new_rtx));
7206     }
7207
7208   /* Unless this is a COMPARE or we have a funny memory reference,
7209      don't do anything with zero-extending field extracts starting at
7210      the low-order bit since they are simple AND operations.  */
7211   if (pos_rtx == 0 && pos == 0 && ! in_dest
7212       && ! in_compare && unsignedp)
7213     return 0;
7214
7215   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7216      if the position is not a constant and the length is not 1.  In all
7217      other cases, we would only be going outside our object in cases when
7218      an original shift would have been undefined.  */
7219   if (MEM_P (inner)
7220       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7221           || (pos_rtx != 0 && len != 1)))
7222     return 0;
7223
7224   enum extraction_pattern pattern = (in_dest ? EP_insv
7225                                      : unsignedp ? EP_extzv : EP_extv);
7226
7227   /* If INNER is not from memory, we want it to have the mode of a register
7228      extraction pattern's structure operand, or word_mode if there is no
7229      such pattern.  The same applies to extraction_mode and pos_mode
7230      and their respective operands.
7231
7232      For memory, assume that the desired extraction_mode and pos_mode
7233      are the same as for a register operation, since at present we don't
7234      have named patterns for aligned memory structures.  */
7235   struct extraction_insn insn;
7236   if (get_best_reg_extraction_insn (&insn, pattern,
7237                                     GET_MODE_BITSIZE (inner_mode), mode))
7238     {
7239       wanted_inner_reg_mode = insn.struct_mode;
7240       pos_mode = insn.pos_mode;
7241       extraction_mode = insn.field_mode;
7242     }
7243
7244   /* Never narrow an object, since that might not be safe.  */
7245
7246   if (mode != VOIDmode
7247       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7248     extraction_mode = mode;
7249
7250   if (!MEM_P (inner))
7251     wanted_inner_mode = wanted_inner_reg_mode;
7252   else
7253     {
7254       /* Be careful not to go beyond the extracted object and maintain the
7255          natural alignment of the memory.  */
7256       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7257       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7258              > GET_MODE_BITSIZE (wanted_inner_mode))
7259         {
7260           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7261           gcc_assert (wanted_inner_mode != VOIDmode);
7262         }
7263     }
7264
7265   orig_pos = pos;
7266
7267   if (BITS_BIG_ENDIAN)
7268     {
7269       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7270          BITS_BIG_ENDIAN style.  If position is constant, compute new
7271          position.  Otherwise, build subtraction.
7272          Note that POS is relative to the mode of the original argument.
7273          If it's a MEM we need to recompute POS relative to that.
7274          However, if we're extracting from (or inserting into) a register,
7275          we want to recompute POS relative to wanted_inner_mode.  */
7276       int width = (MEM_P (inner)
7277                    ? GET_MODE_BITSIZE (is_mode)
7278                    : GET_MODE_BITSIZE (wanted_inner_mode));
7279
7280       if (pos_rtx == 0)
7281         pos = width - len - pos;
7282       else
7283         pos_rtx
7284           = gen_rtx_MINUS (GET_MODE (pos_rtx),
7285                            gen_int_mode (width - len, GET_MODE (pos_rtx)),
7286                            pos_rtx);
7287       /* POS may be less than 0 now, but we check for that below.
7288          Note that it can only be less than 0 if !MEM_P (inner).  */
7289     }
7290
7291   /* If INNER has a wider mode, and this is a constant extraction, try to
7292      make it smaller and adjust the byte to point to the byte containing
7293      the value.  */
7294   if (wanted_inner_mode != VOIDmode
7295       && inner_mode != wanted_inner_mode
7296       && ! pos_rtx
7297       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7298       && MEM_P (inner)
7299       && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7300       && ! MEM_VOLATILE_P (inner))
7301     {
7302       int offset = 0;
7303
7304       /* The computations below will be correct if the machine is big
7305          endian in both bits and bytes or little endian in bits and bytes.
7306          If it is mixed, we must adjust.  */
7307
7308       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7309          adjust OFFSET to compensate.  */
7310       if (BYTES_BIG_ENDIAN
7311           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7312         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7313
7314       /* We can now move to the desired byte.  */
7315       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7316                 * GET_MODE_SIZE (wanted_inner_mode);
7317       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7318
7319       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7320           && is_mode != wanted_inner_mode)
7321         offset = (GET_MODE_SIZE (is_mode)
7322                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7323
7324       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7325     }
7326
7327   /* If INNER is not memory, get it into the proper mode.  If we are changing
7328      its mode, POS must be a constant and smaller than the size of the new
7329      mode.  */
7330   else if (!MEM_P (inner))
7331     {
7332       /* On the LHS, don't create paradoxical subregs implicitely truncating
7333          the register unless TRULY_NOOP_TRUNCATION.  */
7334       if (in_dest
7335           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7336                                              wanted_inner_mode))
7337         return NULL_RTX;
7338
7339       if (GET_MODE (inner) != wanted_inner_mode
7340           && (pos_rtx != 0
7341               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7342         return NULL_RTX;
7343
7344       if (orig_pos < 0)
7345         return NULL_RTX;
7346
7347       inner = force_to_mode (inner, wanted_inner_mode,
7348                              pos_rtx
7349                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7350                              ? ~(unsigned HOST_WIDE_INT) 0
7351                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7352                                 << orig_pos),
7353                              0);
7354     }
7355
7356   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7357      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7358   if (pos_rtx != 0
7359       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7360     {
7361       rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7362                                      GET_MODE (pos_rtx));
7363
7364       /* If we know that no extraneous bits are set, and that the high
7365          bit is not set, convert extraction to cheaper one - either
7366          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7367          cases.  */
7368       if (flag_expensive_optimizations
7369           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7370               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7371                    & ~(((unsigned HOST_WIDE_INT)
7372                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7373                        >> 1))
7374                   == 0)))
7375         {
7376           rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7377                                           GET_MODE (pos_rtx));
7378
7379           /* Prefer ZERO_EXTENSION, since it gives more information to
7380              backends.  */
7381           if (set_src_cost (temp1, optimize_this_for_speed_p)
7382               < set_src_cost (temp, optimize_this_for_speed_p))
7383             temp = temp1;
7384         }
7385       pos_rtx = temp;
7386     }
7387
7388   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7389      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7390      be a CONST_INT.  */
7391   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7392     pos_rtx = orig_pos_rtx;
7393
7394   else if (pos_rtx == 0)
7395     pos_rtx = GEN_INT (pos);
7396
7397   /* Make the required operation.  See if we can use existing rtx.  */
7398   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7399                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7400   if (! in_dest)
7401     new_rtx = gen_lowpart (mode, new_rtx);
7402
7403   return new_rtx;
7404 }
7405 \f
7406 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7407    with any other operations in X.  Return X without that shift if so.  */
7408
7409 static rtx
7410 extract_left_shift (rtx x, int count)
7411 {
7412   enum rtx_code code = GET_CODE (x);
7413   enum machine_mode mode = GET_MODE (x);
7414   rtx tem;
7415
7416   switch (code)
7417     {
7418     case ASHIFT:
7419       /* This is the shift itself.  If it is wide enough, we will return
7420          either the value being shifted if the shift count is equal to
7421          COUNT or a shift for the difference.  */
7422       if (CONST_INT_P (XEXP (x, 1))
7423           && INTVAL (XEXP (x, 1)) >= count)
7424         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7425                                      INTVAL (XEXP (x, 1)) - count);
7426       break;
7427
7428     case NEG:  case NOT:
7429       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7430         return simplify_gen_unary (code, mode, tem, mode);
7431
7432       break;
7433
7434     case PLUS:  case IOR:  case XOR:  case AND:
7435       /* If we can safely shift this constant and we find the inner shift,
7436          make a new operation.  */
7437       if (CONST_INT_P (XEXP (x, 1))
7438           && (UINTVAL (XEXP (x, 1))
7439               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7440           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7441         {
7442           HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
7443           return simplify_gen_binary (code, mode, tem,
7444                                       gen_int_mode (val, mode));
7445         }
7446       break;
7447
7448     default:
7449       break;
7450     }
7451
7452   return 0;
7453 }
7454 \f
7455 /* Look at the expression rooted at X.  Look for expressions
7456    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7457    Form these expressions.
7458
7459    Return the new rtx, usually just X.
7460
7461    Also, for machines like the VAX that don't have logical shift insns,
7462    try to convert logical to arithmetic shift operations in cases where
7463    they are equivalent.  This undoes the canonicalizations to logical
7464    shifts done elsewhere.
7465
7466    We try, as much as possible, to re-use rtl expressions to save memory.
7467
7468    IN_CODE says what kind of expression we are processing.  Normally, it is
7469    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7470    being kludges), it is MEM.  When processing the arguments of a comparison
7471    or a COMPARE against zero, it is COMPARE.  */
7472
7473 rtx
7474 make_compound_operation (rtx x, enum rtx_code in_code)
7475 {
7476   enum rtx_code code = GET_CODE (x);
7477   enum machine_mode mode = GET_MODE (x);
7478   int mode_width = GET_MODE_PRECISION (mode);
7479   rtx rhs, lhs;
7480   enum rtx_code next_code;
7481   int i, j;
7482   rtx new_rtx = 0;
7483   rtx tem;
7484   const char *fmt;
7485
7486   /* Select the code to be used in recursive calls.  Once we are inside an
7487      address, we stay there.  If we have a comparison, set to COMPARE,
7488      but once inside, go back to our default of SET.  */
7489
7490   next_code = (code == MEM ? MEM
7491                : ((code == PLUS || code == MINUS)
7492                   && SCALAR_INT_MODE_P (mode)) ? MEM
7493                : ((code == COMPARE || COMPARISON_P (x))
7494                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7495                : in_code == COMPARE ? SET : in_code);
7496
7497   /* Process depending on the code of this operation.  If NEW is set
7498      nonzero, it will be returned.  */
7499
7500   switch (code)
7501     {
7502     case ASHIFT:
7503       /* Convert shifts by constants into multiplications if inside
7504          an address.  */
7505       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7506           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7507           && INTVAL (XEXP (x, 1)) >= 0
7508           && SCALAR_INT_MODE_P (mode))
7509         {
7510           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7511           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7512
7513           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7514           if (GET_CODE (new_rtx) == NEG)
7515             {
7516               new_rtx = XEXP (new_rtx, 0);
7517               multval = -multval;
7518             }
7519           multval = trunc_int_for_mode (multval, mode);
7520           new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
7521         }
7522       break;
7523
7524     case PLUS:
7525       lhs = XEXP (x, 0);
7526       rhs = XEXP (x, 1);
7527       lhs = make_compound_operation (lhs, next_code);
7528       rhs = make_compound_operation (rhs, next_code);
7529       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7530           && SCALAR_INT_MODE_P (mode))
7531         {
7532           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7533                                      XEXP (lhs, 1));
7534           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7535         }
7536       else if (GET_CODE (lhs) == MULT
7537                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7538         {
7539           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7540                                      simplify_gen_unary (NEG, mode,
7541                                                          XEXP (lhs, 1),
7542                                                          mode));
7543           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7544         }
7545       else
7546         {
7547           SUBST (XEXP (x, 0), lhs);
7548           SUBST (XEXP (x, 1), rhs);
7549           goto maybe_swap;
7550         }
7551       x = gen_lowpart (mode, new_rtx);
7552       goto maybe_swap;
7553
7554     case MINUS:
7555       lhs = XEXP (x, 0);
7556       rhs = XEXP (x, 1);
7557       lhs = make_compound_operation (lhs, next_code);
7558       rhs = make_compound_operation (rhs, next_code);
7559       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7560           && SCALAR_INT_MODE_P (mode))
7561         {
7562           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7563                                      XEXP (rhs, 1));
7564           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7565         }
7566       else if (GET_CODE (rhs) == MULT
7567                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7568         {
7569           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7570                                      simplify_gen_unary (NEG, mode,
7571                                                          XEXP (rhs, 1),
7572                                                          mode));
7573           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7574         }
7575       else
7576         {
7577           SUBST (XEXP (x, 0), lhs);
7578           SUBST (XEXP (x, 1), rhs);
7579           return x;
7580         }
7581       return gen_lowpart (mode, new_rtx);
7582
7583     case AND:
7584       /* If the second operand is not a constant, we can't do anything
7585          with it.  */
7586       if (!CONST_INT_P (XEXP (x, 1)))
7587         break;
7588
7589       /* If the constant is a power of two minus one and the first operand
7590          is a logical right shift, make an extraction.  */
7591       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7592           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7593         {
7594           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7595           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7596                                  0, in_code == COMPARE);
7597         }
7598
7599       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7600       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7601                && subreg_lowpart_p (XEXP (x, 0))
7602                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7603                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7604         {
7605           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7606                                          next_code);
7607           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7608                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7609                                  0, in_code == COMPARE);
7610         }
7611       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7612       else if ((GET_CODE (XEXP (x, 0)) == XOR
7613                 || GET_CODE (XEXP (x, 0)) == IOR)
7614                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7615                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7616                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7617         {
7618           /* Apply the distributive law, and then try to make extractions.  */
7619           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7620                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7621                                              XEXP (x, 1)),
7622                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7623                                              XEXP (x, 1)));
7624           new_rtx = make_compound_operation (new_rtx, in_code);
7625         }
7626
7627       /* If we are have (and (rotate X C) M) and C is larger than the number
7628          of bits in M, this is an extraction.  */
7629
7630       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7631                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7632                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7633                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7634         {
7635           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7636           new_rtx = make_extraction (mode, new_rtx,
7637                                  (GET_MODE_PRECISION (mode)
7638                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7639                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7640         }
7641
7642       /* On machines without logical shifts, if the operand of the AND is
7643          a logical shift and our mask turns off all the propagated sign
7644          bits, we can replace the logical shift with an arithmetic shift.  */
7645       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7646                && !have_insn_for (LSHIFTRT, mode)
7647                && have_insn_for (ASHIFTRT, mode)
7648                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7649                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7650                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7651                && mode_width <= HOST_BITS_PER_WIDE_INT)
7652         {
7653           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7654
7655           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7656           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7657             SUBST (XEXP (x, 0),
7658                    gen_rtx_ASHIFTRT (mode,
7659                                      make_compound_operation
7660                                      (XEXP (XEXP (x, 0), 0), next_code),
7661                                      XEXP (XEXP (x, 0), 1)));
7662         }
7663
7664       /* If the constant is one less than a power of two, this might be
7665          representable by an extraction even if no shift is present.
7666          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7667          we are in a COMPARE.  */
7668       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7669         new_rtx = make_extraction (mode,
7670                                make_compound_operation (XEXP (x, 0),
7671                                                         next_code),
7672                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7673
7674       /* If we are in a comparison and this is an AND with a power of two,
7675          convert this into the appropriate bit extract.  */
7676       else if (in_code == COMPARE
7677                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7678         new_rtx = make_extraction (mode,
7679                                make_compound_operation (XEXP (x, 0),
7680                                                         next_code),
7681                                i, NULL_RTX, 1, 1, 0, 1);
7682
7683       break;
7684
7685     case LSHIFTRT:
7686       /* If the sign bit is known to be zero, replace this with an
7687          arithmetic shift.  */
7688       if (have_insn_for (ASHIFTRT, mode)
7689           && ! have_insn_for (LSHIFTRT, mode)
7690           && mode_width <= HOST_BITS_PER_WIDE_INT
7691           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7692         {
7693           new_rtx = gen_rtx_ASHIFTRT (mode,
7694                                   make_compound_operation (XEXP (x, 0),
7695                                                            next_code),
7696                                   XEXP (x, 1));
7697           break;
7698         }
7699
7700       /* ... fall through ...  */
7701
7702     case ASHIFTRT:
7703       lhs = XEXP (x, 0);
7704       rhs = XEXP (x, 1);
7705
7706       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7707          this is a SIGN_EXTRACT.  */
7708       if (CONST_INT_P (rhs)
7709           && GET_CODE (lhs) == ASHIFT
7710           && CONST_INT_P (XEXP (lhs, 1))
7711           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7712           && INTVAL (XEXP (lhs, 1)) >= 0
7713           && INTVAL (rhs) < mode_width)
7714         {
7715           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7716           new_rtx = make_extraction (mode, new_rtx,
7717                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7718                                  NULL_RTX, mode_width - INTVAL (rhs),
7719                                  code == LSHIFTRT, 0, in_code == COMPARE);
7720           break;
7721         }
7722
7723       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7724          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7725          also do this for some cases of SIGN_EXTRACT, but it doesn't
7726          seem worth the effort; the case checked for occurs on Alpha.  */
7727
7728       if (!OBJECT_P (lhs)
7729           && ! (GET_CODE (lhs) == SUBREG
7730                 && (OBJECT_P (SUBREG_REG (lhs))))
7731           && CONST_INT_P (rhs)
7732           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7733           && INTVAL (rhs) < mode_width
7734           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7735         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7736                                0, NULL_RTX, mode_width - INTVAL (rhs),
7737                                code == LSHIFTRT, 0, in_code == COMPARE);
7738
7739       break;
7740
7741     case SUBREG:
7742       /* Call ourselves recursively on the inner expression.  If we are
7743          narrowing the object and it has a different RTL code from
7744          what it originally did, do this SUBREG as a force_to_mode.  */
7745       {
7746         rtx inner = SUBREG_REG (x), simplified;
7747         enum rtx_code subreg_code = in_code;
7748
7749         /* If in_code is COMPARE, it isn't always safe to pass it through
7750            to the recursive make_compound_operation call.  */
7751         if (subreg_code == COMPARE
7752             && (!subreg_lowpart_p (x)
7753                 || GET_CODE (inner) == SUBREG
7754                 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7755                    is (const_int 0), rather than
7756                    (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).  */
7757                 || (GET_CODE (inner) == AND
7758                     && CONST_INT_P (XEXP (inner, 1))
7759                     && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7760                     && exact_log2 (UINTVAL (XEXP (inner, 1)))
7761                        >= GET_MODE_BITSIZE (mode))))
7762           subreg_code = SET;
7763
7764         tem = make_compound_operation (inner, subreg_code);
7765
7766         simplified
7767           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7768         if (simplified)
7769           tem = simplified;
7770
7771         if (GET_CODE (tem) != GET_CODE (inner)
7772             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7773             && subreg_lowpart_p (x))
7774           {
7775             rtx newer
7776               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7777
7778             /* If we have something other than a SUBREG, we might have
7779                done an expansion, so rerun ourselves.  */
7780             if (GET_CODE (newer) != SUBREG)
7781               newer = make_compound_operation (newer, in_code);
7782
7783             /* force_to_mode can expand compounds.  If it just re-expanded the
7784                compound, use gen_lowpart to convert to the desired mode.  */
7785             if (rtx_equal_p (newer, x)
7786                 /* Likewise if it re-expanded the compound only partially.
7787                    This happens for SUBREG of ZERO_EXTRACT if they extract
7788                    the same number of bits.  */
7789                 || (GET_CODE (newer) == SUBREG
7790                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7791                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7792                     && GET_CODE (inner) == AND
7793                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7794               return gen_lowpart (GET_MODE (x), tem);
7795
7796             return newer;
7797           }
7798
7799         if (simplified)
7800           return tem;
7801       }
7802       break;
7803
7804     default:
7805       break;
7806     }
7807
7808   if (new_rtx)
7809     {
7810       x = gen_lowpart (mode, new_rtx);
7811       code = GET_CODE (x);
7812     }
7813
7814   /* Now recursively process each operand of this operation.  We need to
7815      handle ZERO_EXTEND specially so that we don't lose track of the
7816      inner mode.  */
7817   if (GET_CODE (x) == ZERO_EXTEND)
7818     {
7819       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7820       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7821                                             new_rtx, GET_MODE (XEXP (x, 0)));
7822       if (tem)
7823         return tem;
7824       SUBST (XEXP (x, 0), new_rtx);
7825       return x;
7826     }
7827
7828   fmt = GET_RTX_FORMAT (code);
7829   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7830     if (fmt[i] == 'e')
7831       {
7832         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7833         SUBST (XEXP (x, i), new_rtx);
7834       }
7835     else if (fmt[i] == 'E')
7836       for (j = 0; j < XVECLEN (x, i); j++)
7837         {
7838           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7839           SUBST (XVECEXP (x, i, j), new_rtx);
7840         }
7841
7842  maybe_swap:
7843   /* If this is a commutative operation, the changes to the operands
7844      may have made it noncanonical.  */
7845   if (COMMUTATIVE_ARITH_P (x)
7846       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7847     {
7848       tem = XEXP (x, 0);
7849       SUBST (XEXP (x, 0), XEXP (x, 1));
7850       SUBST (XEXP (x, 1), tem);
7851     }
7852
7853   return x;
7854 }
7855 \f
7856 /* Given M see if it is a value that would select a field of bits
7857    within an item, but not the entire word.  Return -1 if not.
7858    Otherwise, return the starting position of the field, where 0 is the
7859    low-order bit.
7860
7861    *PLEN is set to the length of the field.  */
7862
7863 static int
7864 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7865 {
7866   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7867   int pos = m ? ctz_hwi (m) : -1;
7868   int len = 0;
7869
7870   if (pos >= 0)
7871     /* Now shift off the low-order zero bits and see if we have a
7872        power of two minus 1.  */
7873     len = exact_log2 ((m >> pos) + 1);
7874
7875   if (len <= 0)
7876     pos = -1;
7877
7878   *plen = len;
7879   return pos;
7880 }
7881 \f
7882 /* If X refers to a register that equals REG in value, replace these
7883    references with REG.  */
7884 static rtx
7885 canon_reg_for_combine (rtx x, rtx reg)
7886 {
7887   rtx op0, op1, op2;
7888   const char *fmt;
7889   int i;
7890   bool copied;
7891
7892   enum rtx_code code = GET_CODE (x);
7893   switch (GET_RTX_CLASS (code))
7894     {
7895     case RTX_UNARY:
7896       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7897       if (op0 != XEXP (x, 0))
7898         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7899                                    GET_MODE (reg));
7900       break;
7901
7902     case RTX_BIN_ARITH:
7903     case RTX_COMM_ARITH:
7904       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7905       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7906       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7907         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7908       break;
7909
7910     case RTX_COMPARE:
7911     case RTX_COMM_COMPARE:
7912       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7913       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7914       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7915         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7916                                         GET_MODE (op0), op0, op1);
7917       break;
7918
7919     case RTX_TERNARY:
7920     case RTX_BITFIELD_OPS:
7921       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7922       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7923       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7924       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7925         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7926                                      GET_MODE (op0), op0, op1, op2);
7927
7928     case RTX_OBJ:
7929       if (REG_P (x))
7930         {
7931           if (rtx_equal_p (get_last_value (reg), x)
7932               || rtx_equal_p (reg, get_last_value (x)))
7933             return reg;
7934           else
7935             break;
7936         }
7937
7938       /* fall through */
7939
7940     default:
7941       fmt = GET_RTX_FORMAT (code);
7942       copied = false;
7943       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7944         if (fmt[i] == 'e')
7945           {
7946             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7947             if (op != XEXP (x, i))
7948               {
7949                 if (!copied)
7950                   {
7951                     copied = true;
7952                     x = copy_rtx (x);
7953                   }
7954                 XEXP (x, i) = op;
7955               }
7956           }
7957         else if (fmt[i] == 'E')
7958           {
7959             int j;
7960             for (j = 0; j < XVECLEN (x, i); j++)
7961               {
7962                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7963                 if (op != XVECEXP (x, i, j))
7964                   {
7965                     if (!copied)
7966                       {
7967                         copied = true;
7968                         x = copy_rtx (x);
7969                       }
7970                     XVECEXP (x, i, j) = op;
7971                   }
7972               }
7973           }
7974
7975       break;
7976     }
7977
7978   return x;
7979 }
7980
7981 /* Return X converted to MODE.  If the value is already truncated to
7982    MODE we can just return a subreg even though in the general case we
7983    would need an explicit truncation.  */
7984
7985 static rtx
7986 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7987 {
7988   if (!CONST_INT_P (x)
7989       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7990       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
7991       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7992     {
7993       /* Bit-cast X into an integer mode.  */
7994       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7995         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7996       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7997                               x, GET_MODE (x));
7998     }
7999
8000   return gen_lowpart (mode, x);
8001 }
8002
8003 /* See if X can be simplified knowing that we will only refer to it in
8004    MODE and will only refer to those bits that are nonzero in MASK.
8005    If other bits are being computed or if masking operations are done
8006    that select a superset of the bits in MASK, they can sometimes be
8007    ignored.
8008
8009    Return a possibly simplified expression, but always convert X to
8010    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
8011
8012    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8013    are all off in X.  This is used when X will be complemented, by either
8014    NOT, NEG, or XOR.  */
8015
8016 static rtx
8017 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8018                int just_select)
8019 {
8020   enum rtx_code code = GET_CODE (x);
8021   int next_select = just_select || code == XOR || code == NOT || code == NEG;
8022   enum machine_mode op_mode;
8023   unsigned HOST_WIDE_INT fuller_mask, nonzero;
8024   rtx op0, op1, temp;
8025
8026   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
8027      code below will do the wrong thing since the mode of such an
8028      expression is VOIDmode.
8029
8030      Also do nothing if X is a CLOBBER; this can happen if X was
8031      the return value from a call to gen_lowpart.  */
8032   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8033     return x;
8034
8035   /* We want to perform the operation in its present mode unless we know
8036      that the operation is valid in MODE, in which case we do the operation
8037      in MODE.  */
8038   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8039               && have_insn_for (code, mode))
8040              ? mode : GET_MODE (x));
8041
8042   /* It is not valid to do a right-shift in a narrower mode
8043      than the one it came in with.  */
8044   if ((code == LSHIFTRT || code == ASHIFTRT)
8045       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8046     op_mode = GET_MODE (x);
8047
8048   /* Truncate MASK to fit OP_MODE.  */
8049   if (op_mode)
8050     mask &= GET_MODE_MASK (op_mode);
8051
8052   /* When we have an arithmetic operation, or a shift whose count we
8053      do not know, we need to assume that all bits up to the highest-order
8054      bit in MASK will be needed.  This is how we form such a mask.  */
8055   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8056     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8057   else
8058     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8059                    - 1);
8060
8061   /* Determine what bits of X are guaranteed to be (non)zero.  */
8062   nonzero = nonzero_bits (x, mode);
8063
8064   /* If none of the bits in X are needed, return a zero.  */
8065   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8066     x = const0_rtx;
8067
8068   /* If X is a CONST_INT, return a new one.  Do this here since the
8069      test below will fail.  */
8070   if (CONST_INT_P (x))
8071     {
8072       if (SCALAR_INT_MODE_P (mode))
8073         return gen_int_mode (INTVAL (x) & mask, mode);
8074       else
8075         {
8076           x = GEN_INT (INTVAL (x) & mask);
8077           return gen_lowpart_common (mode, x);
8078         }
8079     }
8080
8081   /* If X is narrower than MODE and we want all the bits in X's mode, just
8082      get X in the proper mode.  */
8083   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8084       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8085     return gen_lowpart (mode, x);
8086
8087   /* We can ignore the effect of a SUBREG if it narrows the mode or
8088      if the constant masks to zero all the bits the mode doesn't have.  */
8089   if (GET_CODE (x) == SUBREG
8090       && subreg_lowpart_p (x)
8091       && ((GET_MODE_SIZE (GET_MODE (x))
8092            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8093           || (0 == (mask
8094                     & GET_MODE_MASK (GET_MODE (x))
8095                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8096     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8097
8098   /* The arithmetic simplifications here only work for scalar integer modes.  */
8099   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8100     return gen_lowpart_or_truncate (mode, x);
8101
8102   switch (code)
8103     {
8104     case CLOBBER:
8105       /* If X is a (clobber (const_int)), return it since we know we are
8106          generating something that won't match.  */
8107       return x;
8108
8109     case SIGN_EXTEND:
8110     case ZERO_EXTEND:
8111     case ZERO_EXTRACT:
8112     case SIGN_EXTRACT:
8113       x = expand_compound_operation (x);
8114       if (GET_CODE (x) != code)
8115         return force_to_mode (x, mode, mask, next_select);
8116       break;
8117
8118     case TRUNCATE:
8119       /* Similarly for a truncate.  */
8120       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8121
8122     case AND:
8123       /* If this is an AND with a constant, convert it into an AND
8124          whose constant is the AND of that constant with MASK.  If it
8125          remains an AND of MASK, delete it since it is redundant.  */
8126
8127       if (CONST_INT_P (XEXP (x, 1)))
8128         {
8129           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8130                                       mask & INTVAL (XEXP (x, 1)));
8131
8132           /* If X is still an AND, see if it is an AND with a mask that
8133              is just some low-order bits.  If so, and it is MASK, we don't
8134              need it.  */
8135
8136           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8137               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8138                   == mask))
8139             x = XEXP (x, 0);
8140
8141           /* If it remains an AND, try making another AND with the bits
8142              in the mode mask that aren't in MASK turned on.  If the
8143              constant in the AND is wide enough, this might make a
8144              cheaper constant.  */
8145
8146           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8147               && GET_MODE_MASK (GET_MODE (x)) != mask
8148               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8149             {
8150               unsigned HOST_WIDE_INT cval
8151                 = UINTVAL (XEXP (x, 1))
8152                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8153               rtx y;
8154
8155               y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0),
8156                                        gen_int_mode (cval, GET_MODE (x)));
8157               if (set_src_cost (y, optimize_this_for_speed_p)
8158                   < set_src_cost (x, optimize_this_for_speed_p))
8159                 x = y;
8160             }
8161
8162           break;
8163         }
8164
8165       goto binop;
8166
8167     case PLUS:
8168       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8169          low-order bits (as in an alignment operation) and FOO is already
8170          aligned to that boundary, mask C1 to that boundary as well.
8171          This may eliminate that PLUS and, later, the AND.  */
8172
8173       {
8174         unsigned int width = GET_MODE_PRECISION (mode);
8175         unsigned HOST_WIDE_INT smask = mask;
8176
8177         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8178            number, sign extend it.  */
8179
8180         if (width < HOST_BITS_PER_WIDE_INT
8181             && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8182           smask |= HOST_WIDE_INT_M1U << width;
8183
8184         if (CONST_INT_P (XEXP (x, 1))
8185             && exact_log2 (- smask) >= 0
8186             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8187             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8188           return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8189                                                (INTVAL (XEXP (x, 1)) & smask)),
8190                                 mode, smask, next_select);
8191       }
8192
8193       /* ... fall through ...  */
8194
8195     case MULT:
8196       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8197          most significant bit in MASK since carries from those bits will
8198          affect the bits we are interested in.  */
8199       mask = fuller_mask;
8200       goto binop;
8201
8202     case MINUS:
8203       /* If X is (minus C Y) where C's least set bit is larger than any bit
8204          in the mask, then we may replace with (neg Y).  */
8205       if (CONST_INT_P (XEXP (x, 0))
8206           && ((UINTVAL (XEXP (x, 0)) & -UINTVAL (XEXP (x, 0))) > mask))
8207         {
8208           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8209                                   GET_MODE (x));
8210           return force_to_mode (x, mode, mask, next_select);
8211         }
8212
8213       /* Similarly, if C contains every bit in the fuller_mask, then we may
8214          replace with (not Y).  */
8215       if (CONST_INT_P (XEXP (x, 0))
8216           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8217         {
8218           x = simplify_gen_unary (NOT, GET_MODE (x),
8219                                   XEXP (x, 1), GET_MODE (x));
8220           return force_to_mode (x, mode, mask, next_select);
8221         }
8222
8223       mask = fuller_mask;
8224       goto binop;
8225
8226     case IOR:
8227     case XOR:
8228       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8229          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8230          operation which may be a bitfield extraction.  Ensure that the
8231          constant we form is not wider than the mode of X.  */
8232
8233       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8234           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8235           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8236           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8237           && CONST_INT_P (XEXP (x, 1))
8238           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8239                + floor_log2 (INTVAL (XEXP (x, 1))))
8240               < GET_MODE_PRECISION (GET_MODE (x)))
8241           && (UINTVAL (XEXP (x, 1))
8242               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8243         {
8244           temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8245                                << INTVAL (XEXP (XEXP (x, 0), 1)),
8246                                GET_MODE (x));
8247           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8248                                       XEXP (XEXP (x, 0), 0), temp);
8249           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8250                                    XEXP (XEXP (x, 0), 1));
8251           return force_to_mode (x, mode, mask, next_select);
8252         }
8253
8254     binop:
8255       /* For most binary operations, just propagate into the operation and
8256          change the mode if we have an operation of that mode.  */
8257
8258       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8259       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8260
8261       /* If we ended up truncating both operands, truncate the result of the
8262          operation instead.  */
8263       if (GET_CODE (op0) == TRUNCATE
8264           && GET_CODE (op1) == TRUNCATE)
8265         {
8266           op0 = XEXP (op0, 0);
8267           op1 = XEXP (op1, 0);
8268         }
8269
8270       op0 = gen_lowpart_or_truncate (op_mode, op0);
8271       op1 = gen_lowpart_or_truncate (op_mode, op1);
8272
8273       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8274         x = simplify_gen_binary (code, op_mode, op0, op1);
8275       break;
8276
8277     case ASHIFT:
8278       /* For left shifts, do the same, but just for the first operand.
8279          However, we cannot do anything with shifts where we cannot
8280          guarantee that the counts are smaller than the size of the mode
8281          because such a count will have a different meaning in a
8282          wider mode.  */
8283
8284       if (! (CONST_INT_P (XEXP (x, 1))
8285              && INTVAL (XEXP (x, 1)) >= 0
8286              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8287           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8288                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8289                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8290         break;
8291
8292       /* If the shift count is a constant and we can do arithmetic in
8293          the mode of the shift, refine which bits we need.  Otherwise, use the
8294          conservative form of the mask.  */
8295       if (CONST_INT_P (XEXP (x, 1))
8296           && INTVAL (XEXP (x, 1)) >= 0
8297           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8298           && HWI_COMPUTABLE_MODE_P (op_mode))
8299         mask >>= INTVAL (XEXP (x, 1));
8300       else
8301         mask = fuller_mask;
8302
8303       op0 = gen_lowpart_or_truncate (op_mode,
8304                                      force_to_mode (XEXP (x, 0), op_mode,
8305                                                     mask, next_select));
8306
8307       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8308         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8309       break;
8310
8311     case LSHIFTRT:
8312       /* Here we can only do something if the shift count is a constant,
8313          this shift constant is valid for the host, and we can do arithmetic
8314          in OP_MODE.  */
8315
8316       if (CONST_INT_P (XEXP (x, 1))
8317           && INTVAL (XEXP (x, 1)) >= 0
8318           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8319           && HWI_COMPUTABLE_MODE_P (op_mode))
8320         {
8321           rtx inner = XEXP (x, 0);
8322           unsigned HOST_WIDE_INT inner_mask;
8323
8324           /* Select the mask of the bits we need for the shift operand.  */
8325           inner_mask = mask << INTVAL (XEXP (x, 1));
8326
8327           /* We can only change the mode of the shift if we can do arithmetic
8328              in the mode of the shift and INNER_MASK is no wider than the
8329              width of X's mode.  */
8330           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8331             op_mode = GET_MODE (x);
8332
8333           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8334
8335           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8336             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8337         }
8338
8339       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8340          shift and AND produces only copies of the sign bit (C2 is one less
8341          than a power of two), we can do this with just a shift.  */
8342
8343       if (GET_CODE (x) == LSHIFTRT
8344           && CONST_INT_P (XEXP (x, 1))
8345           /* The shift puts one of the sign bit copies in the least significant
8346              bit.  */
8347           && ((INTVAL (XEXP (x, 1))
8348                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8349               >= GET_MODE_PRECISION (GET_MODE (x)))
8350           && exact_log2 (mask + 1) >= 0
8351           /* Number of bits left after the shift must be more than the mask
8352              needs.  */
8353           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8354               <= GET_MODE_PRECISION (GET_MODE (x)))
8355           /* Must be more sign bit copies than the mask needs.  */
8356           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8357               >= exact_log2 (mask + 1)))
8358         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8359                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8360                                           - exact_log2 (mask + 1)));
8361
8362       goto shiftrt;
8363
8364     case ASHIFTRT:
8365       /* If we are just looking for the sign bit, we don't need this shift at
8366          all, even if it has a variable count.  */
8367       if (val_signbit_p (GET_MODE (x), mask))
8368         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8369
8370       /* If this is a shift by a constant, get a mask that contains those bits
8371          that are not copies of the sign bit.  We then have two cases:  If
8372          MASK only includes those bits, this can be a logical shift, which may
8373          allow simplifications.  If MASK is a single-bit field not within
8374          those bits, we are requesting a copy of the sign bit and hence can
8375          shift the sign bit to the appropriate location.  */
8376
8377       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8378           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8379         {
8380           int i;
8381
8382           /* If the considered data is wider than HOST_WIDE_INT, we can't
8383              represent a mask for all its bits in a single scalar.
8384              But we only care about the lower bits, so calculate these.  */
8385
8386           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8387             {
8388               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8389
8390               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8391                  is the number of bits a full-width mask would have set.
8392                  We need only shift if these are fewer than nonzero can
8393                  hold.  If not, we must keep all bits set in nonzero.  */
8394
8395               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8396                   < HOST_BITS_PER_WIDE_INT)
8397                 nonzero >>= INTVAL (XEXP (x, 1))
8398                             + HOST_BITS_PER_WIDE_INT
8399                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8400             }
8401           else
8402             {
8403               nonzero = GET_MODE_MASK (GET_MODE (x));
8404               nonzero >>= INTVAL (XEXP (x, 1));
8405             }
8406
8407           if ((mask & ~nonzero) == 0)
8408             {
8409               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8410                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8411               if (GET_CODE (x) != ASHIFTRT)
8412                 return force_to_mode (x, mode, mask, next_select);
8413             }
8414
8415           else if ((i = exact_log2 (mask)) >= 0)
8416             {
8417               x = simplify_shift_const
8418                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8419                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8420
8421               if (GET_CODE (x) != ASHIFTRT)
8422                 return force_to_mode (x, mode, mask, next_select);
8423             }
8424         }
8425
8426       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8427          even if the shift count isn't a constant.  */
8428       if (mask == 1)
8429         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8430                                  XEXP (x, 0), XEXP (x, 1));
8431
8432     shiftrt:
8433
8434       /* If this is a zero- or sign-extension operation that just affects bits
8435          we don't care about, remove it.  Be sure the call above returned
8436          something that is still a shift.  */
8437
8438       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8439           && CONST_INT_P (XEXP (x, 1))
8440           && INTVAL (XEXP (x, 1)) >= 0
8441           && (INTVAL (XEXP (x, 1))
8442               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8443           && GET_CODE (XEXP (x, 0)) == ASHIFT
8444           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8445         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8446                               next_select);
8447
8448       break;
8449
8450     case ROTATE:
8451     case ROTATERT:
8452       /* If the shift count is constant and we can do computations
8453          in the mode of X, compute where the bits we care about are.
8454          Otherwise, we can't do anything.  Don't change the mode of
8455          the shift or propagate MODE into the shift, though.  */
8456       if (CONST_INT_P (XEXP (x, 1))
8457           && INTVAL (XEXP (x, 1)) >= 0)
8458         {
8459           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8460                                             GET_MODE (x),
8461                                             gen_int_mode (mask, GET_MODE (x)),
8462                                             XEXP (x, 1));
8463           if (temp && CONST_INT_P (temp))
8464             x = simplify_gen_binary (code, GET_MODE (x),
8465                                      force_to_mode (XEXP (x, 0), GET_MODE (x),
8466                                                     INTVAL (temp), next_select),
8467                                      XEXP (x, 1));
8468         }
8469       break;
8470
8471     case NEG:
8472       /* If we just want the low-order bit, the NEG isn't needed since it
8473          won't change the low-order bit.  */
8474       if (mask == 1)
8475         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8476
8477       /* We need any bits less significant than the most significant bit in
8478          MASK since carries from those bits will affect the bits we are
8479          interested in.  */
8480       mask = fuller_mask;
8481       goto unop;
8482
8483     case NOT:
8484       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8485          same as the XOR case above.  Ensure that the constant we form is not
8486          wider than the mode of X.  */
8487
8488       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8489           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8490           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8491           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8492               < GET_MODE_PRECISION (GET_MODE (x)))
8493           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8494         {
8495           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8496                                GET_MODE (x));
8497           temp = simplify_gen_binary (XOR, GET_MODE (x),
8498                                       XEXP (XEXP (x, 0), 0), temp);
8499           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8500                                    temp, XEXP (XEXP (x, 0), 1));
8501
8502           return force_to_mode (x, mode, mask, next_select);
8503         }
8504
8505       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8506          use the full mask inside the NOT.  */
8507       mask = fuller_mask;
8508
8509     unop:
8510       op0 = gen_lowpart_or_truncate (op_mode,
8511                                      force_to_mode (XEXP (x, 0), mode, mask,
8512                                                     next_select));
8513       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8514         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8515       break;
8516
8517     case NE:
8518       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8519          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8520          which is equal to STORE_FLAG_VALUE.  */
8521       if ((mask & ~STORE_FLAG_VALUE) == 0
8522           && XEXP (x, 1) == const0_rtx
8523           && GET_MODE (XEXP (x, 0)) == mode
8524           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8525           && (nonzero_bits (XEXP (x, 0), mode)
8526               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8527         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8528
8529       break;
8530
8531     case IF_THEN_ELSE:
8532       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8533          written in a narrower mode.  We play it safe and do not do so.  */
8534
8535       op0 = gen_lowpart_or_truncate (GET_MODE (x),
8536                                      force_to_mode (XEXP (x, 1), mode,
8537                                                     mask, next_select));
8538       op1 = gen_lowpart_or_truncate (GET_MODE (x),
8539                                      force_to_mode (XEXP (x, 2), mode,
8540                                                     mask, next_select));
8541       if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
8542         x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x),
8543                                   GET_MODE (XEXP (x, 0)), XEXP (x, 0),
8544                                   op0, op1);
8545       break;
8546
8547     default:
8548       break;
8549     }
8550
8551   /* Ensure we return a value of the proper mode.  */
8552   return gen_lowpart_or_truncate (mode, x);
8553 }
8554 \f
8555 /* Return nonzero if X is an expression that has one of two values depending on
8556    whether some other value is zero or nonzero.  In that case, we return the
8557    value that is being tested, *PTRUE is set to the value if the rtx being
8558    returned has a nonzero value, and *PFALSE is set to the other alternative.
8559
8560    If we return zero, we set *PTRUE and *PFALSE to X.  */
8561
8562 static rtx
8563 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8564 {
8565   enum machine_mode mode = GET_MODE (x);
8566   enum rtx_code code = GET_CODE (x);
8567   rtx cond0, cond1, true0, true1, false0, false1;
8568   unsigned HOST_WIDE_INT nz;
8569
8570   /* If we are comparing a value against zero, we are done.  */
8571   if ((code == NE || code == EQ)
8572       && XEXP (x, 1) == const0_rtx)
8573     {
8574       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8575       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8576       return XEXP (x, 0);
8577     }
8578
8579   /* If this is a unary operation whose operand has one of two values, apply
8580      our opcode to compute those values.  */
8581   else if (UNARY_P (x)
8582            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8583     {
8584       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8585       *pfalse = simplify_gen_unary (code, mode, false0,
8586                                     GET_MODE (XEXP (x, 0)));
8587       return cond0;
8588     }
8589
8590   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8591      make can't possibly match and would suppress other optimizations.  */
8592   else if (code == COMPARE)
8593     ;
8594
8595   /* If this is a binary operation, see if either side has only one of two
8596      values.  If either one does or if both do and they are conditional on
8597      the same value, compute the new true and false values.  */
8598   else if (BINARY_P (x))
8599     {
8600       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8601       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8602
8603       if ((cond0 != 0 || cond1 != 0)
8604           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8605         {
8606           /* If if_then_else_cond returned zero, then true/false are the
8607              same rtl.  We must copy one of them to prevent invalid rtl
8608              sharing.  */
8609           if (cond0 == 0)
8610             true0 = copy_rtx (true0);
8611           else if (cond1 == 0)
8612             true1 = copy_rtx (true1);
8613
8614           if (COMPARISON_P (x))
8615             {
8616               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8617                                                 true0, true1);
8618               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8619                                                  false0, false1);
8620              }
8621           else
8622             {
8623               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8624               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8625             }
8626
8627           return cond0 ? cond0 : cond1;
8628         }
8629
8630       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8631          operands is zero when the other is nonzero, and vice-versa,
8632          and STORE_FLAG_VALUE is 1 or -1.  */
8633
8634       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8635           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8636               || code == UMAX)
8637           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8638         {
8639           rtx op0 = XEXP (XEXP (x, 0), 1);
8640           rtx op1 = XEXP (XEXP (x, 1), 1);
8641
8642           cond0 = XEXP (XEXP (x, 0), 0);
8643           cond1 = XEXP (XEXP (x, 1), 0);
8644
8645           if (COMPARISON_P (cond0)
8646               && COMPARISON_P (cond1)
8647               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8648                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8649                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8650                   || ((swap_condition (GET_CODE (cond0))
8651                        == reversed_comparison_code (cond1, NULL))
8652                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8653                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8654               && ! side_effects_p (x))
8655             {
8656               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8657               *pfalse = simplify_gen_binary (MULT, mode,
8658                                              (code == MINUS
8659                                               ? simplify_gen_unary (NEG, mode,
8660                                                                     op1, mode)
8661                                               : op1),
8662                                               const_true_rtx);
8663               return cond0;
8664             }
8665         }
8666
8667       /* Similarly for MULT, AND and UMIN, except that for these the result
8668          is always zero.  */
8669       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8670           && (code == MULT || code == AND || code == UMIN)
8671           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8672         {
8673           cond0 = XEXP (XEXP (x, 0), 0);
8674           cond1 = XEXP (XEXP (x, 1), 0);
8675
8676           if (COMPARISON_P (cond0)
8677               && COMPARISON_P (cond1)
8678               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8679                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8680                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8681                   || ((swap_condition (GET_CODE (cond0))
8682                        == reversed_comparison_code (cond1, NULL))
8683                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8684                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8685               && ! side_effects_p (x))
8686             {
8687               *ptrue = *pfalse = const0_rtx;
8688               return cond0;
8689             }
8690         }
8691     }
8692
8693   else if (code == IF_THEN_ELSE)
8694     {
8695       /* If we have IF_THEN_ELSE already, extract the condition and
8696          canonicalize it if it is NE or EQ.  */
8697       cond0 = XEXP (x, 0);
8698       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8699       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8700         return XEXP (cond0, 0);
8701       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8702         {
8703           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8704           return XEXP (cond0, 0);
8705         }
8706       else
8707         return cond0;
8708     }
8709
8710   /* If X is a SUBREG, we can narrow both the true and false values
8711      if the inner expression, if there is a condition.  */
8712   else if (code == SUBREG
8713            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8714                                                &true0, &false0)))
8715     {
8716       true0 = simplify_gen_subreg (mode, true0,
8717                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8718       false0 = simplify_gen_subreg (mode, false0,
8719                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8720       if (true0 && false0)
8721         {
8722           *ptrue = true0;
8723           *pfalse = false0;
8724           return cond0;
8725         }
8726     }
8727
8728   /* If X is a constant, this isn't special and will cause confusions
8729      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8730   else if (CONSTANT_P (x)
8731            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8732     ;
8733
8734   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8735      will be least confusing to the rest of the compiler.  */
8736   else if (mode == BImode)
8737     {
8738       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8739       return x;
8740     }
8741
8742   /* If X is known to be either 0 or -1, those are the true and
8743      false values when testing X.  */
8744   else if (x == constm1_rtx || x == const0_rtx
8745            || (mode != VOIDmode
8746                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8747     {
8748       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8749       return x;
8750     }
8751
8752   /* Likewise for 0 or a single bit.  */
8753   else if (HWI_COMPUTABLE_MODE_P (mode)
8754            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8755     {
8756       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8757       return x;
8758     }
8759
8760   /* Otherwise fail; show no condition with true and false values the same.  */
8761   *ptrue = *pfalse = x;
8762   return 0;
8763 }
8764 \f
8765 /* Return the value of expression X given the fact that condition COND
8766    is known to be true when applied to REG as its first operand and VAL
8767    as its second.  X is known to not be shared and so can be modified in
8768    place.
8769
8770    We only handle the simplest cases, and specifically those cases that
8771    arise with IF_THEN_ELSE expressions.  */
8772
8773 static rtx
8774 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8775 {
8776   enum rtx_code code = GET_CODE (x);
8777   rtx temp;
8778   const char *fmt;
8779   int i, j;
8780
8781   if (side_effects_p (x))
8782     return x;
8783
8784   /* If either operand of the condition is a floating point value,
8785      then we have to avoid collapsing an EQ comparison.  */
8786   if (cond == EQ
8787       && rtx_equal_p (x, reg)
8788       && ! FLOAT_MODE_P (GET_MODE (x))
8789       && ! FLOAT_MODE_P (GET_MODE (val)))
8790     return val;
8791
8792   if (cond == UNEQ && rtx_equal_p (x, reg))
8793     return val;
8794
8795   /* If X is (abs REG) and we know something about REG's relationship
8796      with zero, we may be able to simplify this.  */
8797
8798   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8799     switch (cond)
8800       {
8801       case GE:  case GT:  case EQ:
8802         return XEXP (x, 0);
8803       case LT:  case LE:
8804         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8805                                    XEXP (x, 0),
8806                                    GET_MODE (XEXP (x, 0)));
8807       default:
8808         break;
8809       }
8810
8811   /* The only other cases we handle are MIN, MAX, and comparisons if the
8812      operands are the same as REG and VAL.  */
8813
8814   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8815     {
8816       if (rtx_equal_p (XEXP (x, 0), val))
8817         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8818
8819       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8820         {
8821           if (COMPARISON_P (x))
8822             {
8823               if (comparison_dominates_p (cond, code))
8824                 return const_true_rtx;
8825
8826               code = reversed_comparison_code (x, NULL);
8827               if (code != UNKNOWN
8828                   && comparison_dominates_p (cond, code))
8829                 return const0_rtx;
8830               else
8831                 return x;
8832             }
8833           else if (code == SMAX || code == SMIN
8834                    || code == UMIN || code == UMAX)
8835             {
8836               int unsignedp = (code == UMIN || code == UMAX);
8837
8838               /* Do not reverse the condition when it is NE or EQ.
8839                  This is because we cannot conclude anything about
8840                  the value of 'SMAX (x, y)' when x is not equal to y,
8841                  but we can when x equals y.  */
8842               if ((code == SMAX || code == UMAX)
8843                   && ! (cond == EQ || cond == NE))
8844                 cond = reverse_condition (cond);
8845
8846               switch (cond)
8847                 {
8848                 case GE:   case GT:
8849                   return unsignedp ? x : XEXP (x, 1);
8850                 case LE:   case LT:
8851                   return unsignedp ? x : XEXP (x, 0);
8852                 case GEU:  case GTU:
8853                   return unsignedp ? XEXP (x, 1) : x;
8854                 case LEU:  case LTU:
8855                   return unsignedp ? XEXP (x, 0) : x;
8856                 default:
8857                   break;
8858                 }
8859             }
8860         }
8861     }
8862   else if (code == SUBREG)
8863     {
8864       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8865       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8866
8867       if (SUBREG_REG (x) != r)
8868         {
8869           /* We must simplify subreg here, before we lose track of the
8870              original inner_mode.  */
8871           new_rtx = simplify_subreg (GET_MODE (x), r,
8872                                  inner_mode, SUBREG_BYTE (x));
8873           if (new_rtx)
8874             return new_rtx;
8875           else
8876             SUBST (SUBREG_REG (x), r);
8877         }
8878
8879       return x;
8880     }
8881   /* We don't have to handle SIGN_EXTEND here, because even in the
8882      case of replacing something with a modeless CONST_INT, a
8883      CONST_INT is already (supposed to be) a valid sign extension for
8884      its narrower mode, which implies it's already properly
8885      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8886      story is different.  */
8887   else if (code == ZERO_EXTEND)
8888     {
8889       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8890       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8891
8892       if (XEXP (x, 0) != r)
8893         {
8894           /* We must simplify the zero_extend here, before we lose
8895              track of the original inner_mode.  */
8896           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8897                                           r, inner_mode);
8898           if (new_rtx)
8899             return new_rtx;
8900           else
8901             SUBST (XEXP (x, 0), r);
8902         }
8903
8904       return x;
8905     }
8906
8907   fmt = GET_RTX_FORMAT (code);
8908   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8909     {
8910       if (fmt[i] == 'e')
8911         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8912       else if (fmt[i] == 'E')
8913         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8914           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8915                                                 cond, reg, val));
8916     }
8917
8918   return x;
8919 }
8920 \f
8921 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8922    assignment as a field assignment.  */
8923
8924 static int
8925 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8926 {
8927   if (x == y || rtx_equal_p (x, y))
8928     return 1;
8929
8930   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8931     return 0;
8932
8933   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8934      Note that all SUBREGs of MEM are paradoxical; otherwise they
8935      would have been rewritten.  */
8936   if (MEM_P (x) && GET_CODE (y) == SUBREG
8937       && MEM_P (SUBREG_REG (y))
8938       && rtx_equal_p (SUBREG_REG (y),
8939                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8940     return 1;
8941
8942   if (MEM_P (y) && GET_CODE (x) == SUBREG
8943       && MEM_P (SUBREG_REG (x))
8944       && rtx_equal_p (SUBREG_REG (x),
8945                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8946     return 1;
8947
8948   /* We used to see if get_last_value of X and Y were the same but that's
8949      not correct.  In one direction, we'll cause the assignment to have
8950      the wrong destination and in the case, we'll import a register into this
8951      insn that might have already have been dead.   So fail if none of the
8952      above cases are true.  */
8953   return 0;
8954 }
8955 \f
8956 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8957    Return that assignment if so.
8958
8959    We only handle the most common cases.  */
8960
8961 static rtx
8962 make_field_assignment (rtx x)
8963 {
8964   rtx dest = SET_DEST (x);
8965   rtx src = SET_SRC (x);
8966   rtx assign;
8967   rtx rhs, lhs;
8968   HOST_WIDE_INT c1;
8969   HOST_WIDE_INT pos;
8970   unsigned HOST_WIDE_INT len;
8971   rtx other;
8972   enum machine_mode mode;
8973
8974   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8975      a clear of a one-bit field.  We will have changed it to
8976      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
8977      for a SUBREG.  */
8978
8979   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8980       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8981       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8982       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8983     {
8984       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8985                                 1, 1, 1, 0);
8986       if (assign != 0)
8987         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8988       return x;
8989     }
8990
8991   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8992       && subreg_lowpart_p (XEXP (src, 0))
8993       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8994           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8995       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8996       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8997       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8998       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8999     {
9000       assign = make_extraction (VOIDmode, dest, 0,
9001                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9002                                 1, 1, 1, 0);
9003       if (assign != 0)
9004         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9005       return x;
9006     }
9007
9008   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9009      one-bit field.  */
9010   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9011       && XEXP (XEXP (src, 0), 0) == const1_rtx
9012       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9013     {
9014       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9015                                 1, 1, 1, 0);
9016       if (assign != 0)
9017         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9018       return x;
9019     }
9020
9021   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9022      SRC is an AND with all bits of that field set, then we can discard
9023      the AND.  */
9024   if (GET_CODE (dest) == ZERO_EXTRACT
9025       && CONST_INT_P (XEXP (dest, 1))
9026       && GET_CODE (src) == AND
9027       && CONST_INT_P (XEXP (src, 1)))
9028     {
9029       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9030       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9031       unsigned HOST_WIDE_INT ze_mask;
9032
9033       if (width >= HOST_BITS_PER_WIDE_INT)
9034         ze_mask = -1;
9035       else
9036         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9037
9038       /* Complete overlap.  We can remove the source AND.  */
9039       if ((and_mask & ze_mask) == ze_mask)
9040         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9041
9042       /* Partial overlap.  We can reduce the source AND.  */
9043       if ((and_mask & ze_mask) != and_mask)
9044         {
9045           mode = GET_MODE (src);
9046           src = gen_rtx_AND (mode, XEXP (src, 0),
9047                              gen_int_mode (and_mask & ze_mask, mode));
9048           return gen_rtx_SET (VOIDmode, dest, src);
9049         }
9050     }
9051
9052   /* The other case we handle is assignments into a constant-position
9053      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9054      a mask that has all one bits except for a group of zero bits and
9055      OTHER is known to have zeros where C1 has ones, this is such an
9056      assignment.  Compute the position and length from C1.  Shift OTHER
9057      to the appropriate position, force it to the required mode, and
9058      make the extraction.  Check for the AND in both operands.  */
9059
9060   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9061     return x;
9062
9063   rhs = expand_compound_operation (XEXP (src, 0));
9064   lhs = expand_compound_operation (XEXP (src, 1));
9065
9066   if (GET_CODE (rhs) == AND
9067       && CONST_INT_P (XEXP (rhs, 1))
9068       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9069     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9070   else if (GET_CODE (lhs) == AND
9071            && CONST_INT_P (XEXP (lhs, 1))
9072            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9073     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9074   else
9075     return x;
9076
9077   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9078   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9079       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9080       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9081     return x;
9082
9083   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9084   if (assign == 0)
9085     return x;
9086
9087   /* The mode to use for the source is the mode of the assignment, or of
9088      what is inside a possible STRICT_LOW_PART.  */
9089   mode = (GET_CODE (assign) == STRICT_LOW_PART
9090           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9091
9092   /* Shift OTHER right POS places and make it the source, restricting it
9093      to the proper length and mode.  */
9094
9095   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9096                                                      GET_MODE (src),
9097                                                      other, pos),
9098                                dest);
9099   src = force_to_mode (src, mode,
9100                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9101                        ? ~(unsigned HOST_WIDE_INT) 0
9102                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9103                        0);
9104
9105   /* If SRC is masked by an AND that does not make a difference in
9106      the value being stored, strip it.  */
9107   if (GET_CODE (assign) == ZERO_EXTRACT
9108       && CONST_INT_P (XEXP (assign, 1))
9109       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9110       && GET_CODE (src) == AND
9111       && CONST_INT_P (XEXP (src, 1))
9112       && UINTVAL (XEXP (src, 1))
9113          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9114     src = XEXP (src, 0);
9115
9116   return gen_rtx_SET (VOIDmode, assign, src);
9117 }
9118 \f
9119 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9120    if so.  */
9121
9122 static rtx
9123 apply_distributive_law (rtx x)
9124 {
9125   enum rtx_code code = GET_CODE (x);
9126   enum rtx_code inner_code;
9127   rtx lhs, rhs, other;
9128   rtx tem;
9129
9130   /* Distributivity is not true for floating point as it can change the
9131      value.  So we don't do it unless -funsafe-math-optimizations.  */
9132   if (FLOAT_MODE_P (GET_MODE (x))
9133       && ! flag_unsafe_math_optimizations)
9134     return x;
9135
9136   /* The outer operation can only be one of the following:  */
9137   if (code != IOR && code != AND && code != XOR
9138       && code != PLUS && code != MINUS)
9139     return x;
9140
9141   lhs = XEXP (x, 0);
9142   rhs = XEXP (x, 1);
9143
9144   /* If either operand is a primitive we can't do anything, so get out
9145      fast.  */
9146   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9147     return x;
9148
9149   lhs = expand_compound_operation (lhs);
9150   rhs = expand_compound_operation (rhs);
9151   inner_code = GET_CODE (lhs);
9152   if (inner_code != GET_CODE (rhs))
9153     return x;
9154
9155   /* See if the inner and outer operations distribute.  */
9156   switch (inner_code)
9157     {
9158     case LSHIFTRT:
9159     case ASHIFTRT:
9160     case AND:
9161     case IOR:
9162       /* These all distribute except over PLUS.  */
9163       if (code == PLUS || code == MINUS)
9164         return x;
9165       break;
9166
9167     case MULT:
9168       if (code != PLUS && code != MINUS)
9169         return x;
9170       break;
9171
9172     case ASHIFT:
9173       /* This is also a multiply, so it distributes over everything.  */
9174       break;
9175
9176     /* This used to handle SUBREG, but this turned out to be counter-
9177        productive, since (subreg (op ...)) usually is not handled by
9178        insn patterns, and this "optimization" therefore transformed
9179        recognizable patterns into unrecognizable ones.  Therefore the
9180        SUBREG case was removed from here.
9181
9182        It is possible that distributing SUBREG over arithmetic operations
9183        leads to an intermediate result than can then be optimized further,
9184        e.g. by moving the outer SUBREG to the other side of a SET as done
9185        in simplify_set.  This seems to have been the original intent of
9186        handling SUBREGs here.
9187
9188        However, with current GCC this does not appear to actually happen,
9189        at least on major platforms.  If some case is found where removing
9190        the SUBREG case here prevents follow-on optimizations, distributing
9191        SUBREGs ought to be re-added at that place, e.g. in simplify_set.  */
9192
9193     default:
9194       return x;
9195     }
9196
9197   /* Set LHS and RHS to the inner operands (A and B in the example
9198      above) and set OTHER to the common operand (C in the example).
9199      There is only one way to do this unless the inner operation is
9200      commutative.  */
9201   if (COMMUTATIVE_ARITH_P (lhs)
9202       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9203     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9204   else if (COMMUTATIVE_ARITH_P (lhs)
9205            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9206     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9207   else if (COMMUTATIVE_ARITH_P (lhs)
9208            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9209     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9210   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9211     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9212   else
9213     return x;
9214
9215   /* Form the new inner operation, seeing if it simplifies first.  */
9216   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9217
9218   /* There is one exception to the general way of distributing:
9219      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9220   if (code == XOR && inner_code == IOR)
9221     {
9222       inner_code = AND;
9223       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9224     }
9225
9226   /* We may be able to continuing distributing the result, so call
9227      ourselves recursively on the inner operation before forming the
9228      outer operation, which we return.  */
9229   return simplify_gen_binary (inner_code, GET_MODE (x),
9230                               apply_distributive_law (tem), other);
9231 }
9232
9233 /* See if X is of the form (* (+ A B) C), and if so convert to
9234    (+ (* A C) (* B C)) and try to simplify.
9235
9236    Most of the time, this results in no change.  However, if some of
9237    the operands are the same or inverses of each other, simplifications
9238    will result.
9239
9240    For example, (and (ior A B) (not B)) can occur as the result of
9241    expanding a bit field assignment.  When we apply the distributive
9242    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9243    which then simplifies to (and (A (not B))).
9244
9245    Note that no checks happen on the validity of applying the inverse
9246    distributive law.  This is pointless since we can do it in the
9247    few places where this routine is called.
9248
9249    N is the index of the term that is decomposed (the arithmetic operation,
9250    i.e. (+ A B) in the first example above).  !N is the index of the term that
9251    is distributed, i.e. of C in the first example above.  */
9252 static rtx
9253 distribute_and_simplify_rtx (rtx x, int n)
9254 {
9255   enum machine_mode mode;
9256   enum rtx_code outer_code, inner_code;
9257   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9258
9259   /* Distributivity is not true for floating point as it can change the
9260      value.  So we don't do it unless -funsafe-math-optimizations.  */
9261   if (FLOAT_MODE_P (GET_MODE (x))
9262       && ! flag_unsafe_math_optimizations)
9263     return NULL_RTX;
9264
9265   decomposed = XEXP (x, n);
9266   if (!ARITHMETIC_P (decomposed))
9267     return NULL_RTX;
9268
9269   mode = GET_MODE (x);
9270   outer_code = GET_CODE (x);
9271   distributed = XEXP (x, !n);
9272
9273   inner_code = GET_CODE (decomposed);
9274   inner_op0 = XEXP (decomposed, 0);
9275   inner_op1 = XEXP (decomposed, 1);
9276
9277   /* Special case (and (xor B C) (not A)), which is equivalent to
9278      (xor (ior A B) (ior A C))  */
9279   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9280     {
9281       distributed = XEXP (distributed, 0);
9282       outer_code = IOR;
9283     }
9284
9285   if (n == 0)
9286     {
9287       /* Distribute the second term.  */
9288       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9289       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9290     }
9291   else
9292     {
9293       /* Distribute the first term.  */
9294       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9295       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9296     }
9297
9298   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9299                                                      new_op0, new_op1));
9300   if (GET_CODE (tmp) != outer_code
9301       && (set_src_cost (tmp, optimize_this_for_speed_p)
9302           < set_src_cost (x, optimize_this_for_speed_p)))
9303     return tmp;
9304
9305   return NULL_RTX;
9306 }
9307 \f
9308 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9309    in MODE.  Return an equivalent form, if different from (and VAROP
9310    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9311
9312 static rtx
9313 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9314                           unsigned HOST_WIDE_INT constop)
9315 {
9316   unsigned HOST_WIDE_INT nonzero;
9317   unsigned HOST_WIDE_INT orig_constop;
9318   rtx orig_varop;
9319   int i;
9320
9321   orig_varop = varop;
9322   orig_constop = constop;
9323   if (GET_CODE (varop) == CLOBBER)
9324     return NULL_RTX;
9325
9326   /* Simplify VAROP knowing that we will be only looking at some of the
9327      bits in it.
9328
9329      Note by passing in CONSTOP, we guarantee that the bits not set in
9330      CONSTOP are not significant and will never be examined.  We must
9331      ensure that is the case by explicitly masking out those bits
9332      before returning.  */
9333   varop = force_to_mode (varop, mode, constop, 0);
9334
9335   /* If VAROP is a CLOBBER, we will fail so return it.  */
9336   if (GET_CODE (varop) == CLOBBER)
9337     return varop;
9338
9339   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9340      to VAROP and return the new constant.  */
9341   if (CONST_INT_P (varop))
9342     return gen_int_mode (INTVAL (varop) & constop, mode);
9343
9344   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9345      a call to nonzero_bits, here we don't care about bits outside
9346      MODE.  */
9347
9348   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9349
9350   /* Turn off all bits in the constant that are known to already be zero.
9351      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9352      which is tested below.  */
9353
9354   constop &= nonzero;
9355
9356   /* If we don't have any bits left, return zero.  */
9357   if (constop == 0)
9358     return const0_rtx;
9359
9360   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9361      a power of two, we can replace this with an ASHIFT.  */
9362   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9363       && (i = exact_log2 (constop)) >= 0)
9364     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9365
9366   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9367      or XOR, then try to apply the distributive law.  This may eliminate
9368      operations if either branch can be simplified because of the AND.
9369      It may also make some cases more complex, but those cases probably
9370      won't match a pattern either with or without this.  */
9371
9372   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9373     return
9374       gen_lowpart
9375         (mode,
9376          apply_distributive_law
9377          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9378                                simplify_and_const_int (NULL_RTX,
9379                                                        GET_MODE (varop),
9380                                                        XEXP (varop, 0),
9381                                                        constop),
9382                                simplify_and_const_int (NULL_RTX,
9383                                                        GET_MODE (varop),
9384                                                        XEXP (varop, 1),
9385                                                        constop))));
9386
9387   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9388      the AND and see if one of the operands simplifies to zero.  If so, we
9389      may eliminate it.  */
9390
9391   if (GET_CODE (varop) == PLUS
9392       && exact_log2 (constop + 1) >= 0)
9393     {
9394       rtx o0, o1;
9395
9396       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9397       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9398       if (o0 == const0_rtx)
9399         return o1;
9400       if (o1 == const0_rtx)
9401         return o0;
9402     }
9403
9404   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9405   varop = gen_lowpart (mode, varop);
9406   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9407     return NULL_RTX;
9408
9409   /* If we are only masking insignificant bits, return VAROP.  */
9410   if (constop == nonzero)
9411     return varop;
9412
9413   if (varop == orig_varop && constop == orig_constop)
9414     return NULL_RTX;
9415
9416   /* Otherwise, return an AND.  */
9417   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9418 }
9419
9420
9421 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9422    in MODE.
9423
9424    Return an equivalent form, if different from X.  Otherwise, return X.  If
9425    X is zero, we are to always construct the equivalent form.  */
9426
9427 static rtx
9428 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9429                         unsigned HOST_WIDE_INT constop)
9430 {
9431   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9432   if (tem)
9433     return tem;
9434
9435   if (!x)
9436     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9437                              gen_int_mode (constop, mode));
9438   if (GET_MODE (x) != mode)
9439     x = gen_lowpart (mode, x);
9440   return x;
9441 }
9442 \f
9443 /* Given a REG, X, compute which bits in X can be nonzero.
9444    We don't care about bits outside of those defined in MODE.
9445
9446    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9447    a shift, AND, or zero_extract, we can do better.  */
9448
9449 static rtx
9450 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9451                               const_rtx known_x ATTRIBUTE_UNUSED,
9452                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
9453                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9454                               unsigned HOST_WIDE_INT *nonzero)
9455 {
9456   rtx tem;
9457   reg_stat_type *rsp;
9458
9459   /* If X is a register whose nonzero bits value is current, use it.
9460      Otherwise, if X is a register whose value we can find, use that
9461      value.  Otherwise, use the previously-computed global nonzero bits
9462      for this register.  */
9463
9464   rsp = &reg_stat[REGNO (x)];
9465   if (rsp->last_set_value != 0
9466       && (rsp->last_set_mode == mode
9467           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9468               && GET_MODE_CLASS (mode) == MODE_INT))
9469       && ((rsp->last_set_label >= label_tick_ebb_start
9470            && rsp->last_set_label < label_tick)
9471           || (rsp->last_set_label == label_tick
9472               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9473           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9474               && REG_N_SETS (REGNO (x)) == 1
9475               && !REGNO_REG_SET_P
9476                   (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9477                    REGNO (x)))))
9478     {
9479       unsigned HOST_WIDE_INT mask = rsp->last_set_nonzero_bits;
9480
9481       if (GET_MODE_PRECISION (rsp->last_set_mode) < GET_MODE_PRECISION (mode))
9482         /* We don't know anything about the upper bits.  */
9483         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (rsp->last_set_mode);
9484
9485       *nonzero &= mask;
9486       return NULL;
9487     }
9488
9489   tem = get_last_value (x);
9490
9491   if (tem)
9492     {
9493 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9494       /* If X is narrower than MODE and TEM is a non-negative
9495          constant that would appear negative in the mode of X,
9496          sign-extend it for use in reg_nonzero_bits because some
9497          machines (maybe most) will actually do the sign-extension
9498          and this is the conservative approach.
9499
9500          ??? For 2.5, try to tighten up the MD files in this regard
9501          instead of this kludge.  */
9502
9503       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9504           && CONST_INT_P (tem)
9505           && INTVAL (tem) > 0
9506           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9507         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9508 #endif
9509       return tem;
9510     }
9511   else if (nonzero_sign_valid && rsp->nonzero_bits)
9512     {
9513       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9514
9515       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9516         /* We don't know anything about the upper bits.  */
9517         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9518
9519       *nonzero &= mask;
9520     }
9521
9522   return NULL;
9523 }
9524
9525 /* Return the number of bits at the high-order end of X that are known to
9526    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9527    VOIDmode, X will be used in its own mode.  The returned value  will always
9528    be between 1 and the number of bits in MODE.  */
9529
9530 static rtx
9531 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9532                                      const_rtx known_x ATTRIBUTE_UNUSED,
9533                                      enum machine_mode known_mode
9534                                      ATTRIBUTE_UNUSED,
9535                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9536                                      unsigned int *result)
9537 {
9538   rtx tem;
9539   reg_stat_type *rsp;
9540
9541   rsp = &reg_stat[REGNO (x)];
9542   if (rsp->last_set_value != 0
9543       && rsp->last_set_mode == mode
9544       && ((rsp->last_set_label >= label_tick_ebb_start
9545            && rsp->last_set_label < label_tick)
9546           || (rsp->last_set_label == label_tick
9547               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9548           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9549               && REG_N_SETS (REGNO (x)) == 1
9550               && !REGNO_REG_SET_P
9551                   (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9552                    REGNO (x)))))
9553     {
9554       *result = rsp->last_set_sign_bit_copies;
9555       return NULL;
9556     }
9557
9558   tem = get_last_value (x);
9559   if (tem != 0)
9560     return tem;
9561
9562   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9563       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9564     *result = rsp->sign_bit_copies;
9565
9566   return NULL;
9567 }
9568 \f
9569 /* Return the number of "extended" bits there are in X, when interpreted
9570    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9571    unsigned quantities, this is the number of high-order zero bits.
9572    For signed quantities, this is the number of copies of the sign bit
9573    minus 1.  In both case, this function returns the number of "spare"
9574    bits.  For example, if two quantities for which this function returns
9575    at least 1 are added, the addition is known not to overflow.
9576
9577    This function will always return 0 unless called during combine, which
9578    implies that it must be called from a define_split.  */
9579
9580 unsigned int
9581 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9582 {
9583   if (nonzero_sign_valid == 0)
9584     return 0;
9585
9586   return (unsignedp
9587           ? (HWI_COMPUTABLE_MODE_P (mode)
9588              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9589                                - floor_log2 (nonzero_bits (x, mode)))
9590              : 0)
9591           : num_sign_bit_copies (x, mode) - 1);
9592 }
9593
9594 /* This function is called from `simplify_shift_const' to merge two
9595    outer operations.  Specifically, we have already found that we need
9596    to perform operation *POP0 with constant *PCONST0 at the outermost
9597    position.  We would now like to also perform OP1 with constant CONST1
9598    (with *POP0 being done last).
9599
9600    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9601    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9602    complement the innermost operand, otherwise it is unchanged.
9603
9604    MODE is the mode in which the operation will be done.  No bits outside
9605    the width of this mode matter.  It is assumed that the width of this mode
9606    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9607
9608    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9609    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9610    result is simply *PCONST0.
9611
9612    If the resulting operation cannot be expressed as one operation, we
9613    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9614
9615 static int
9616 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9617 {
9618   enum rtx_code op0 = *pop0;
9619   HOST_WIDE_INT const0 = *pconst0;
9620
9621   const0 &= GET_MODE_MASK (mode);
9622   const1 &= GET_MODE_MASK (mode);
9623
9624   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9625   if (op0 == AND)
9626     const1 &= const0;
9627
9628   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9629      if OP0 is SET.  */
9630
9631   if (op1 == UNKNOWN || op0 == SET)
9632     return 1;
9633
9634   else if (op0 == UNKNOWN)
9635     op0 = op1, const0 = const1;
9636
9637   else if (op0 == op1)
9638     {
9639       switch (op0)
9640         {
9641         case AND:
9642           const0 &= const1;
9643           break;
9644         case IOR:
9645           const0 |= const1;
9646           break;
9647         case XOR:
9648           const0 ^= const1;
9649           break;
9650         case PLUS:
9651           const0 += const1;
9652           break;
9653         case NEG:
9654           op0 = UNKNOWN;
9655           break;
9656         default:
9657           break;
9658         }
9659     }
9660
9661   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9662   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9663     return 0;
9664
9665   /* If the two constants aren't the same, we can't do anything.  The
9666      remaining six cases can all be done.  */
9667   else if (const0 != const1)
9668     return 0;
9669
9670   else
9671     switch (op0)
9672       {
9673       case IOR:
9674         if (op1 == AND)
9675           /* (a & b) | b == b */
9676           op0 = SET;
9677         else /* op1 == XOR */
9678           /* (a ^ b) | b == a | b */
9679           {;}
9680         break;
9681
9682       case XOR:
9683         if (op1 == AND)
9684           /* (a & b) ^ b == (~a) & b */
9685           op0 = AND, *pcomp_p = 1;
9686         else /* op1 == IOR */
9687           /* (a | b) ^ b == a & ~b */
9688           op0 = AND, const0 = ~const0;
9689         break;
9690
9691       case AND:
9692         if (op1 == IOR)
9693           /* (a | b) & b == b */
9694         op0 = SET;
9695         else /* op1 == XOR */
9696           /* (a ^ b) & b) == (~a) & b */
9697           *pcomp_p = 1;
9698         break;
9699       default:
9700         break;
9701       }
9702
9703   /* Check for NO-OP cases.  */
9704   const0 &= GET_MODE_MASK (mode);
9705   if (const0 == 0
9706       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9707     op0 = UNKNOWN;
9708   else if (const0 == 0 && op0 == AND)
9709     op0 = SET;
9710   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9711            && op0 == AND)
9712     op0 = UNKNOWN;
9713
9714   *pop0 = op0;
9715
9716   /* ??? Slightly redundant with the above mask, but not entirely.
9717      Moving this above means we'd have to sign-extend the mode mask
9718      for the final test.  */
9719   if (op0 != UNKNOWN && op0 != NEG)
9720     *pconst0 = trunc_int_for_mode (const0, mode);
9721
9722   return 1;
9723 }
9724 \f
9725 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9726    the shift in.  The original shift operation CODE is performed on OP in
9727    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9728    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9729    result of the shift is subject to operation OUTER_CODE with operand
9730    OUTER_CONST.  */
9731
9732 static enum machine_mode
9733 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9734                       enum machine_mode orig_mode, enum machine_mode mode,
9735                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9736 {
9737   if (orig_mode == mode)
9738     return mode;
9739   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9740
9741   /* In general we can't perform in wider mode for right shift and rotate.  */
9742   switch (code)
9743     {
9744     case ASHIFTRT:
9745       /* We can still widen if the bits brought in from the left are identical
9746          to the sign bit of ORIG_MODE.  */
9747       if (num_sign_bit_copies (op, mode)
9748           > (unsigned) (GET_MODE_PRECISION (mode)
9749                         - GET_MODE_PRECISION (orig_mode)))
9750         return mode;
9751       return orig_mode;
9752
9753     case LSHIFTRT:
9754       /* Similarly here but with zero bits.  */
9755       if (HWI_COMPUTABLE_MODE_P (mode)
9756           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9757         return mode;
9758
9759       /* We can also widen if the bits brought in will be masked off.  This
9760          operation is performed in ORIG_MODE.  */
9761       if (outer_code == AND)
9762         {
9763           int care_bits = low_bitmask_len (orig_mode, outer_const);
9764
9765           if (care_bits >= 0
9766               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9767             return mode;
9768         }
9769       /* fall through */
9770
9771     case ROTATE:
9772       return orig_mode;
9773
9774     case ROTATERT:
9775       gcc_unreachable ();
9776
9777     default:
9778       return mode;
9779     }
9780 }
9781
9782 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9783    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9784    if we cannot simplify it.  Otherwise, return a simplified value.
9785
9786    The shift is normally computed in the widest mode we find in VAROP, as
9787    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9788    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9789
9790 static rtx
9791 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9792                         rtx varop, int orig_count)
9793 {
9794   enum rtx_code orig_code = code;
9795   rtx orig_varop = varop;
9796   int count;
9797   enum machine_mode mode = result_mode;
9798   enum machine_mode shift_mode, tmode;
9799   unsigned int mode_words
9800     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9801   /* We form (outer_op (code varop count) (outer_const)).  */
9802   enum rtx_code outer_op = UNKNOWN;
9803   HOST_WIDE_INT outer_const = 0;
9804   int complement_p = 0;
9805   rtx new_rtx, x;
9806
9807   /* Make sure and truncate the "natural" shift on the way in.  We don't
9808      want to do this inside the loop as it makes it more difficult to
9809      combine shifts.  */
9810   if (SHIFT_COUNT_TRUNCATED)
9811     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9812
9813   /* If we were given an invalid count, don't do anything except exactly
9814      what was requested.  */
9815
9816   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9817     return NULL_RTX;
9818
9819   count = orig_count;
9820
9821   /* Unless one of the branches of the `if' in this loop does a `continue',
9822      we will `break' the loop after the `if'.  */
9823
9824   while (count != 0)
9825     {
9826       /* If we have an operand of (clobber (const_int 0)), fail.  */
9827       if (GET_CODE (varop) == CLOBBER)
9828         return NULL_RTX;
9829
9830       /* Convert ROTATERT to ROTATE.  */
9831       if (code == ROTATERT)
9832         {
9833           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9834           code = ROTATE;
9835           if (VECTOR_MODE_P (result_mode))
9836             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9837           else
9838             count = bitsize - count;
9839         }
9840
9841       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9842                                          mode, outer_op, outer_const);
9843
9844       /* Handle cases where the count is greater than the size of the mode
9845          minus 1.  For ASHIFT, use the size minus one as the count (this can
9846          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9847          take the count modulo the size.  For other shifts, the result is
9848          zero.
9849
9850          Since these shifts are being produced by the compiler by combining
9851          multiple operations, each of which are defined, we know what the
9852          result is supposed to be.  */
9853
9854       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9855         {
9856           if (code == ASHIFTRT)
9857             count = GET_MODE_PRECISION (shift_mode) - 1;
9858           else if (code == ROTATE || code == ROTATERT)
9859             count %= GET_MODE_PRECISION (shift_mode);
9860           else
9861             {
9862               /* We can't simply return zero because there may be an
9863                  outer op.  */
9864               varop = const0_rtx;
9865               count = 0;
9866               break;
9867             }
9868         }
9869
9870       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9871          here would cause an infinite loop.  */
9872       if (complement_p)
9873         break;
9874
9875       /* An arithmetic right shift of a quantity known to be -1 or 0
9876          is a no-op.  */
9877       if (code == ASHIFTRT
9878           && (num_sign_bit_copies (varop, shift_mode)
9879               == GET_MODE_PRECISION (shift_mode)))
9880         {
9881           count = 0;
9882           break;
9883         }
9884
9885       /* If we are doing an arithmetic right shift and discarding all but
9886          the sign bit copies, this is equivalent to doing a shift by the
9887          bitsize minus one.  Convert it into that shift because it will often
9888          allow other simplifications.  */
9889
9890       if (code == ASHIFTRT
9891           && (count + num_sign_bit_copies (varop, shift_mode)
9892               >= GET_MODE_PRECISION (shift_mode)))
9893         count = GET_MODE_PRECISION (shift_mode) - 1;
9894
9895       /* We simplify the tests below and elsewhere by converting
9896          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9897          `make_compound_operation' will convert it to an ASHIFTRT for
9898          those machines (such as VAX) that don't have an LSHIFTRT.  */
9899       if (code == ASHIFTRT
9900           && val_signbit_known_clear_p (shift_mode,
9901                                         nonzero_bits (varop, shift_mode)))
9902         code = LSHIFTRT;
9903
9904       if (((code == LSHIFTRT
9905             && HWI_COMPUTABLE_MODE_P (shift_mode)
9906             && !(nonzero_bits (varop, shift_mode) >> count))
9907            || (code == ASHIFT
9908                && HWI_COMPUTABLE_MODE_P (shift_mode)
9909                && !((nonzero_bits (varop, shift_mode) << count)
9910                     & GET_MODE_MASK (shift_mode))))
9911           && !side_effects_p (varop))
9912         varop = const0_rtx;
9913
9914       switch (GET_CODE (varop))
9915         {
9916         case SIGN_EXTEND:
9917         case ZERO_EXTEND:
9918         case SIGN_EXTRACT:
9919         case ZERO_EXTRACT:
9920           new_rtx = expand_compound_operation (varop);
9921           if (new_rtx != varop)
9922             {
9923               varop = new_rtx;
9924               continue;
9925             }
9926           break;
9927
9928         case MEM:
9929           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9930              minus the width of a smaller mode, we can do this with a
9931              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9932           if ((code == ASHIFTRT || code == LSHIFTRT)
9933               && ! mode_dependent_address_p (XEXP (varop, 0),
9934                                              MEM_ADDR_SPACE (varop))
9935               && ! MEM_VOLATILE_P (varop)
9936               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9937                                          MODE_INT, 1)) != BLKmode)
9938             {
9939               new_rtx = adjust_address_nv (varop, tmode,
9940                                        BYTES_BIG_ENDIAN ? 0
9941                                        : count / BITS_PER_UNIT);
9942
9943               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9944                                      : ZERO_EXTEND, mode, new_rtx);
9945               count = 0;
9946               continue;
9947             }
9948           break;
9949
9950         case SUBREG:
9951           /* If VAROP is a SUBREG, strip it as long as the inner operand has
9952              the same number of words as what we've seen so far.  Then store
9953              the widest mode in MODE.  */
9954           if (subreg_lowpart_p (varop)
9955               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9956                   > GET_MODE_SIZE (GET_MODE (varop)))
9957               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9958                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9959                  == mode_words
9960               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9961               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9962             {
9963               varop = SUBREG_REG (varop);
9964               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9965                 mode = GET_MODE (varop);
9966               continue;
9967             }
9968           break;
9969
9970         case MULT:
9971           /* Some machines use MULT instead of ASHIFT because MULT
9972              is cheaper.  But it is still better on those machines to
9973              merge two shifts into one.  */
9974           if (CONST_INT_P (XEXP (varop, 1))
9975               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9976             {
9977               varop
9978                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9979                                        XEXP (varop, 0),
9980                                        GEN_INT (exact_log2 (
9981                                                 UINTVAL (XEXP (varop, 1)))));
9982               continue;
9983             }
9984           break;
9985
9986         case UDIV:
9987           /* Similar, for when divides are cheaper.  */
9988           if (CONST_INT_P (XEXP (varop, 1))
9989               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9990             {
9991               varop
9992                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9993                                        XEXP (varop, 0),
9994                                        GEN_INT (exact_log2 (
9995                                                 UINTVAL (XEXP (varop, 1)))));
9996               continue;
9997             }
9998           break;
9999
10000         case ASHIFTRT:
10001           /* If we are extracting just the sign bit of an arithmetic
10002              right shift, that shift is not needed.  However, the sign
10003              bit of a wider mode may be different from what would be
10004              interpreted as the sign bit in a narrower mode, so, if
10005              the result is narrower, don't discard the shift.  */
10006           if (code == LSHIFTRT
10007               && count == (GET_MODE_BITSIZE (result_mode) - 1)
10008               && (GET_MODE_BITSIZE (result_mode)
10009                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
10010             {
10011               varop = XEXP (varop, 0);
10012               continue;
10013             }
10014
10015           /* ... fall through ...  */
10016
10017         case LSHIFTRT:
10018         case ASHIFT:
10019         case ROTATE:
10020           /* Here we have two nested shifts.  The result is usually the
10021              AND of a new shift with a mask.  We compute the result below.  */
10022           if (CONST_INT_P (XEXP (varop, 1))
10023               && INTVAL (XEXP (varop, 1)) >= 0
10024               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10025               && HWI_COMPUTABLE_MODE_P (result_mode)
10026               && HWI_COMPUTABLE_MODE_P (mode)
10027               && !VECTOR_MODE_P (result_mode))
10028             {
10029               enum rtx_code first_code = GET_CODE (varop);
10030               unsigned int first_count = INTVAL (XEXP (varop, 1));
10031               unsigned HOST_WIDE_INT mask;
10032               rtx mask_rtx;
10033
10034               /* We have one common special case.  We can't do any merging if
10035                  the inner code is an ASHIFTRT of a smaller mode.  However, if
10036                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10037                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10038                  we can convert it to
10039                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10040                  This simplifies certain SIGN_EXTEND operations.  */
10041               if (code == ASHIFT && first_code == ASHIFTRT
10042                   && count == (GET_MODE_PRECISION (result_mode)
10043                                - GET_MODE_PRECISION (GET_MODE (varop))))
10044                 {
10045                   /* C3 has the low-order C1 bits zero.  */
10046
10047                   mask = GET_MODE_MASK (mode)
10048                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10049
10050                   varop = simplify_and_const_int (NULL_RTX, result_mode,
10051                                                   XEXP (varop, 0), mask);
10052                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10053                                                 varop, count);
10054                   count = first_count;
10055                   code = ASHIFTRT;
10056                   continue;
10057                 }
10058
10059               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10060                  than C1 high-order bits equal to the sign bit, we can convert
10061                  this to either an ASHIFT or an ASHIFTRT depending on the
10062                  two counts.
10063
10064                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
10065
10066               if (code == ASHIFTRT && first_code == ASHIFT
10067                   && GET_MODE (varop) == shift_mode
10068                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10069                       > first_count))
10070                 {
10071                   varop = XEXP (varop, 0);
10072                   count -= first_count;
10073                   if (count < 0)
10074                     {
10075                       count = -count;
10076                       code = ASHIFT;
10077                     }
10078
10079                   continue;
10080                 }
10081
10082               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10083                  we can only do this if FIRST_CODE is also ASHIFTRT.
10084
10085                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10086                  ASHIFTRT.
10087
10088                  If the mode of this shift is not the mode of the outer shift,
10089                  we can't do this if either shift is a right shift or ROTATE.
10090
10091                  Finally, we can't do any of these if the mode is too wide
10092                  unless the codes are the same.
10093
10094                  Handle the case where the shift codes are the same
10095                  first.  */
10096
10097               if (code == first_code)
10098                 {
10099                   if (GET_MODE (varop) != result_mode
10100                       && (code == ASHIFTRT || code == LSHIFTRT
10101                           || code == ROTATE))
10102                     break;
10103
10104                   count += first_count;
10105                   varop = XEXP (varop, 0);
10106                   continue;
10107                 }
10108
10109               if (code == ASHIFTRT
10110                   || (code == ROTATE && first_code == ASHIFTRT)
10111                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10112                   || (GET_MODE (varop) != result_mode
10113                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10114                           || first_code == ROTATE
10115                           || code == ROTATE)))
10116                 break;
10117
10118               /* To compute the mask to apply after the shift, shift the
10119                  nonzero bits of the inner shift the same way the
10120                  outer shift will.  */
10121
10122               mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)),
10123                                        result_mode);
10124
10125               mask_rtx
10126                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10127                                                    GEN_INT (count));
10128
10129               /* Give up if we can't compute an outer operation to use.  */
10130               if (mask_rtx == 0
10131                   || !CONST_INT_P (mask_rtx)
10132                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10133                                         INTVAL (mask_rtx),
10134                                         result_mode, &complement_p))
10135                 break;
10136
10137               /* If the shifts are in the same direction, we add the
10138                  counts.  Otherwise, we subtract them.  */
10139               if ((code == ASHIFTRT || code == LSHIFTRT)
10140                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10141                 count += first_count;
10142               else
10143                 count -= first_count;
10144
10145               /* If COUNT is positive, the new shift is usually CODE,
10146                  except for the two exceptions below, in which case it is
10147                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10148                  always be used  */
10149               if (count > 0
10150                   && ((first_code == ROTATE && code == ASHIFT)
10151                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10152                 code = first_code;
10153               else if (count < 0)
10154                 code = first_code, count = -count;
10155
10156               varop = XEXP (varop, 0);
10157               continue;
10158             }
10159
10160           /* If we have (A << B << C) for any shift, we can convert this to
10161              (A << C << B).  This wins if A is a constant.  Only try this if
10162              B is not a constant.  */
10163
10164           else if (GET_CODE (varop) == code
10165                    && CONST_INT_P (XEXP (varop, 0))
10166                    && !CONST_INT_P (XEXP (varop, 1)))
10167             {
10168               rtx new_rtx = simplify_const_binary_operation (code, mode,
10169                                                          XEXP (varop, 0),
10170                                                          GEN_INT (count));
10171               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10172               count = 0;
10173               continue;
10174             }
10175           break;
10176
10177         case NOT:
10178           if (VECTOR_MODE_P (mode))
10179             break;
10180
10181           /* Make this fit the case below.  */
10182           varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10183           continue;
10184
10185         case IOR:
10186         case AND:
10187         case XOR:
10188           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10189              with C the size of VAROP - 1 and the shift is logical if
10190              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10191              we have an (le X 0) operation.   If we have an arithmetic shift
10192              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10193              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10194
10195           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10196               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10197               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10198               && (code == LSHIFTRT || code == ASHIFTRT)
10199               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10200               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10201             {
10202               count = 0;
10203               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10204                                   const0_rtx);
10205
10206               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10207                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10208
10209               continue;
10210             }
10211
10212           /* If we have (shift (logical)), move the logical to the outside
10213              to allow it to possibly combine with another logical and the
10214              shift to combine with another shift.  This also canonicalizes to
10215              what a ZERO_EXTRACT looks like.  Also, some machines have
10216              (and (shift)) insns.  */
10217
10218           if (CONST_INT_P (XEXP (varop, 1))
10219               /* We can't do this if we have (ashiftrt (xor))  and the
10220                  constant has its sign bit set in shift_mode.  */
10221               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10222                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10223                                               shift_mode))
10224               && (new_rtx = simplify_const_binary_operation
10225                   (code, result_mode,
10226                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10227                    GEN_INT (count))) != 0
10228               && CONST_INT_P (new_rtx)
10229               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10230                                   INTVAL (new_rtx), result_mode, &complement_p))
10231             {
10232               varop = XEXP (varop, 0);
10233               continue;
10234             }
10235
10236           /* If we can't do that, try to simplify the shift in each arm of the
10237              logical expression, make a new logical expression, and apply
10238              the inverse distributive law.  This also can't be done
10239              for some (ashiftrt (xor)).  */
10240           if (CONST_INT_P (XEXP (varop, 1))
10241              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10242                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10243                                              shift_mode)))
10244             {
10245               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10246                                               XEXP (varop, 0), count);
10247               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10248                                               XEXP (varop, 1), count);
10249
10250               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10251                                            lhs, rhs);
10252               varop = apply_distributive_law (varop);
10253
10254               count = 0;
10255               continue;
10256             }
10257           break;
10258
10259         case EQ:
10260           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10261              says that the sign bit can be tested, FOO has mode MODE, C is
10262              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10263              that may be nonzero.  */
10264           if (code == LSHIFTRT
10265               && XEXP (varop, 1) == const0_rtx
10266               && GET_MODE (XEXP (varop, 0)) == result_mode
10267               && count == (GET_MODE_PRECISION (result_mode) - 1)
10268               && HWI_COMPUTABLE_MODE_P (result_mode)
10269               && STORE_FLAG_VALUE == -1
10270               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10271               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10272                                   &complement_p))
10273             {
10274               varop = XEXP (varop, 0);
10275               count = 0;
10276               continue;
10277             }
10278           break;
10279
10280         case NEG:
10281           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10282              than the number of bits in the mode is equivalent to A.  */
10283           if (code == LSHIFTRT
10284               && count == (GET_MODE_PRECISION (result_mode) - 1)
10285               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10286             {
10287               varop = XEXP (varop, 0);
10288               count = 0;
10289               continue;
10290             }
10291
10292           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10293              NEG outside to allow shifts to combine.  */
10294           if (code == ASHIFT
10295               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10296                                   &complement_p))
10297             {
10298               varop = XEXP (varop, 0);
10299               continue;
10300             }
10301           break;
10302
10303         case PLUS:
10304           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10305              is one less than the number of bits in the mode is
10306              equivalent to (xor A 1).  */
10307           if (code == LSHIFTRT
10308               && count == (GET_MODE_PRECISION (result_mode) - 1)
10309               && XEXP (varop, 1) == constm1_rtx
10310               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10311               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10312                                   &complement_p))
10313             {
10314               count = 0;
10315               varop = XEXP (varop, 0);
10316               continue;
10317             }
10318
10319           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10320              that might be nonzero in BAR are those being shifted out and those
10321              bits are known zero in FOO, we can replace the PLUS with FOO.
10322              Similarly in the other operand order.  This code occurs when
10323              we are computing the size of a variable-size array.  */
10324
10325           if ((code == ASHIFTRT || code == LSHIFTRT)
10326               && count < HOST_BITS_PER_WIDE_INT
10327               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10328               && (nonzero_bits (XEXP (varop, 1), result_mode)
10329                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10330             {
10331               varop = XEXP (varop, 0);
10332               continue;
10333             }
10334           else if ((code == ASHIFTRT || code == LSHIFTRT)
10335                    && count < HOST_BITS_PER_WIDE_INT
10336                    && HWI_COMPUTABLE_MODE_P (result_mode)
10337                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10338                             >> count)
10339                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10340                             & nonzero_bits (XEXP (varop, 1),
10341                                                  result_mode)))
10342             {
10343               varop = XEXP (varop, 1);
10344               continue;
10345             }
10346
10347           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10348           if (code == ASHIFT
10349               && CONST_INT_P (XEXP (varop, 1))
10350               && (new_rtx = simplify_const_binary_operation
10351                   (ASHIFT, result_mode,
10352                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10353                    GEN_INT (count))) != 0
10354               && CONST_INT_P (new_rtx)
10355               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10356                                   INTVAL (new_rtx), result_mode, &complement_p))
10357             {
10358               varop = XEXP (varop, 0);
10359               continue;
10360             }
10361
10362           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10363              signbit', and attempt to change the PLUS to an XOR and move it to
10364              the outer operation as is done above in the AND/IOR/XOR case
10365              leg for shift(logical). See details in logical handling above
10366              for reasoning in doing so.  */
10367           if (code == LSHIFTRT
10368               && CONST_INT_P (XEXP (varop, 1))
10369               && mode_signbit_p (result_mode, XEXP (varop, 1))
10370               && (new_rtx = simplify_const_binary_operation
10371                   (code, result_mode,
10372                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10373                    GEN_INT (count))) != 0
10374               && CONST_INT_P (new_rtx)
10375               && merge_outer_ops (&outer_op, &outer_const, XOR,
10376                                   INTVAL (new_rtx), result_mode, &complement_p))
10377             {
10378               varop = XEXP (varop, 0);
10379               continue;
10380             }
10381
10382           break;
10383
10384         case MINUS:
10385           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10386              with C the size of VAROP - 1 and the shift is logical if
10387              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10388              we have a (gt X 0) operation.  If the shift is arithmetic with
10389              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10390              we have a (neg (gt X 0)) operation.  */
10391
10392           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10393               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10394               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10395               && (code == LSHIFTRT || code == ASHIFTRT)
10396               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10397               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10398               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10399             {
10400               count = 0;
10401               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10402                                   const0_rtx);
10403
10404               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10405                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10406
10407               continue;
10408             }
10409           break;
10410
10411         case TRUNCATE:
10412           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10413              if the truncate does not affect the value.  */
10414           if (code == LSHIFTRT
10415               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10416               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10417               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10418                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10419                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10420             {
10421               rtx varop_inner = XEXP (varop, 0);
10422
10423               varop_inner
10424                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10425                                     XEXP (varop_inner, 0),
10426                                     GEN_INT
10427                                     (count + INTVAL (XEXP (varop_inner, 1))));
10428               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10429               count = 0;
10430               continue;
10431             }
10432           break;
10433
10434         default:
10435           break;
10436         }
10437
10438       break;
10439     }
10440
10441   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10442                                      outer_op, outer_const);
10443
10444   /* We have now finished analyzing the shift.  The result should be
10445      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10446      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10447      to the result of the shift.  OUTER_CONST is the relevant constant,
10448      but we must turn off all bits turned off in the shift.  */
10449
10450   if (outer_op == UNKNOWN
10451       && orig_code == code && orig_count == count
10452       && varop == orig_varop
10453       && shift_mode == GET_MODE (varop))
10454     return NULL_RTX;
10455
10456   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10457   varop = gen_lowpart (shift_mode, varop);
10458   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10459     return NULL_RTX;
10460
10461   /* If we have an outer operation and we just made a shift, it is
10462      possible that we could have simplified the shift were it not
10463      for the outer operation.  So try to do the simplification
10464      recursively.  */
10465
10466   if (outer_op != UNKNOWN)
10467     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10468   else
10469     x = NULL_RTX;
10470
10471   if (x == NULL_RTX)
10472     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10473
10474   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10475      turn off all the bits that the shift would have turned off.  */
10476   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10477     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10478                                 GET_MODE_MASK (result_mode) >> orig_count);
10479
10480   /* Do the remainder of the processing in RESULT_MODE.  */
10481   x = gen_lowpart_or_truncate (result_mode, x);
10482
10483   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10484      operation.  */
10485   if (complement_p)
10486     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10487
10488   if (outer_op != UNKNOWN)
10489     {
10490       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10491           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10492         outer_const = trunc_int_for_mode (outer_const, result_mode);
10493
10494       if (outer_op == AND)
10495         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10496       else if (outer_op == SET)
10497         {
10498           /* This means that we have determined that the result is
10499              equivalent to a constant.  This should be rare.  */
10500           if (!side_effects_p (x))
10501             x = GEN_INT (outer_const);
10502         }
10503       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10504         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10505       else
10506         x = simplify_gen_binary (outer_op, result_mode, x,
10507                                  GEN_INT (outer_const));
10508     }
10509
10510   return x;
10511 }
10512
10513 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10514    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10515    return X or, if it is NULL, synthesize the expression with
10516    simplify_gen_binary.  Otherwise, return a simplified value.
10517
10518    The shift is normally computed in the widest mode we find in VAROP, as
10519    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10520    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10521
10522 static rtx
10523 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10524                       rtx varop, int count)
10525 {
10526   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10527   if (tem)
10528     return tem;
10529
10530   if (!x)
10531     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10532   if (GET_MODE (x) != result_mode)
10533     x = gen_lowpart (result_mode, x);
10534   return x;
10535 }
10536
10537 \f
10538 /* Like recog, but we receive the address of a pointer to a new pattern.
10539    We try to match the rtx that the pointer points to.
10540    If that fails, we may try to modify or replace the pattern,
10541    storing the replacement into the same pointer object.
10542
10543    Modifications include deletion or addition of CLOBBERs.
10544
10545    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10546    the CLOBBERs are placed.
10547
10548    The value is the final insn code from the pattern ultimately matched,
10549    or -1.  */
10550
10551 static int
10552 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10553 {
10554   rtx pat = *pnewpat;
10555   rtx pat_without_clobbers;
10556   int insn_code_number;
10557   int num_clobbers_to_add = 0;
10558   int i;
10559   rtx notes = NULL_RTX;
10560   rtx old_notes, old_pat;
10561   int old_icode;
10562
10563   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10564      we use to indicate that something didn't match.  If we find such a
10565      thing, force rejection.  */
10566   if (GET_CODE (pat) == PARALLEL)
10567     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10568       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10569           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10570         return -1;
10571
10572   old_pat = PATTERN (insn);
10573   old_notes = REG_NOTES (insn);
10574   PATTERN (insn) = pat;
10575   REG_NOTES (insn) = NULL_RTX;
10576
10577   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10578   if (dump_file && (dump_flags & TDF_DETAILS))
10579     {
10580       if (insn_code_number < 0)
10581         fputs ("Failed to match this instruction:\n", dump_file);
10582       else
10583         fputs ("Successfully matched this instruction:\n", dump_file);
10584       print_rtl_single (dump_file, pat);
10585     }
10586
10587   /* If it isn't, there is the possibility that we previously had an insn
10588      that clobbered some register as a side effect, but the combined
10589      insn doesn't need to do that.  So try once more without the clobbers
10590      unless this represents an ASM insn.  */
10591
10592   if (insn_code_number < 0 && ! check_asm_operands (pat)
10593       && GET_CODE (pat) == PARALLEL)
10594     {
10595       int pos;
10596
10597       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10598         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10599           {
10600             if (i != pos)
10601               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10602             pos++;
10603           }
10604
10605       SUBST_INT (XVECLEN (pat, 0), pos);
10606
10607       if (pos == 1)
10608         pat = XVECEXP (pat, 0, 0);
10609
10610       PATTERN (insn) = pat;
10611       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10612       if (dump_file && (dump_flags & TDF_DETAILS))
10613         {
10614           if (insn_code_number < 0)
10615             fputs ("Failed to match this instruction:\n", dump_file);
10616           else
10617             fputs ("Successfully matched this instruction:\n", dump_file);
10618           print_rtl_single (dump_file, pat);
10619         }
10620     }
10621
10622   pat_without_clobbers = pat;
10623
10624   PATTERN (insn) = old_pat;
10625   REG_NOTES (insn) = old_notes;
10626
10627   /* Recognize all noop sets, these will be killed by followup pass.  */
10628   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10629     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10630
10631   /* If we had any clobbers to add, make a new pattern than contains
10632      them.  Then check to make sure that all of them are dead.  */
10633   if (num_clobbers_to_add)
10634     {
10635       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10636                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10637                                                   ? (XVECLEN (pat, 0)
10638                                                      + num_clobbers_to_add)
10639                                                   : num_clobbers_to_add + 1));
10640
10641       if (GET_CODE (pat) == PARALLEL)
10642         for (i = 0; i < XVECLEN (pat, 0); i++)
10643           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10644       else
10645         XVECEXP (newpat, 0, 0) = pat;
10646
10647       add_clobbers (newpat, insn_code_number);
10648
10649       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10650            i < XVECLEN (newpat, 0); i++)
10651         {
10652           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10653               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10654             return -1;
10655           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10656             {
10657               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10658               notes = alloc_reg_note (REG_UNUSED,
10659                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10660             }
10661         }
10662       pat = newpat;
10663     }
10664
10665   if (insn_code_number >= 0
10666       && insn_code_number != NOOP_MOVE_INSN_CODE)
10667     {
10668       old_pat = PATTERN (insn);
10669       old_notes = REG_NOTES (insn);
10670       old_icode = INSN_CODE (insn);
10671       PATTERN (insn) = pat;
10672       REG_NOTES (insn) = notes;
10673
10674       /* Allow targets to reject combined insn.  */
10675       if (!targetm.legitimate_combined_insn (insn))
10676         {
10677           if (dump_file && (dump_flags & TDF_DETAILS))
10678             fputs ("Instruction not appropriate for target.",
10679                    dump_file);
10680
10681           /* Callers expect recog_for_combine to strip
10682              clobbers from the pattern on failure.  */
10683           pat = pat_without_clobbers;
10684           notes = NULL_RTX;
10685
10686           insn_code_number = -1;
10687         }
10688
10689       PATTERN (insn) = old_pat;
10690       REG_NOTES (insn) = old_notes;
10691       INSN_CODE (insn) = old_icode;
10692     }
10693
10694   *pnewpat = pat;
10695   *pnotes = notes;
10696
10697   return insn_code_number;
10698 }
10699 \f
10700 /* Like gen_lowpart_general but for use by combine.  In combine it
10701    is not possible to create any new pseudoregs.  However, it is
10702    safe to create invalid memory addresses, because combine will
10703    try to recognize them and all they will do is make the combine
10704    attempt fail.
10705
10706    If for some reason this cannot do its job, an rtx
10707    (clobber (const_int 0)) is returned.
10708    An insn containing that will not be recognized.  */
10709
10710 static rtx
10711 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10712 {
10713   enum machine_mode imode = GET_MODE (x);
10714   unsigned int osize = GET_MODE_SIZE (omode);
10715   unsigned int isize = GET_MODE_SIZE (imode);
10716   rtx result;
10717
10718   if (omode == imode)
10719     return x;
10720
10721   /* We can only support MODE being wider than a word if X is a
10722      constant integer or has a mode the same size.  */
10723   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10724       && ! (CONST_SCALAR_INT_P (x) || isize == osize))
10725     goto fail;
10726
10727   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10728      won't know what to do.  So we will strip off the SUBREG here and
10729      process normally.  */
10730   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10731     {
10732       x = SUBREG_REG (x);
10733
10734       /* For use in case we fall down into the address adjustments
10735          further below, we need to adjust the known mode and size of
10736          x; imode and isize, since we just adjusted x.  */
10737       imode = GET_MODE (x);
10738
10739       if (imode == omode)
10740         return x;
10741
10742       isize = GET_MODE_SIZE (imode);
10743     }
10744
10745   result = gen_lowpart_common (omode, x);
10746
10747   if (result)
10748     return result;
10749
10750   if (MEM_P (x))
10751     {
10752       int offset = 0;
10753
10754       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10755          address.  */
10756       if (MEM_VOLATILE_P (x)
10757           || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10758         goto fail;
10759
10760       /* If we want to refer to something bigger than the original memref,
10761          generate a paradoxical subreg instead.  That will force a reload
10762          of the original memref X.  */
10763       if (isize < osize)
10764         return gen_rtx_SUBREG (omode, x, 0);
10765
10766       if (WORDS_BIG_ENDIAN)
10767         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10768
10769       /* Adjust the address so that the address-after-the-data is
10770          unchanged.  */
10771       if (BYTES_BIG_ENDIAN)
10772         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10773
10774       return adjust_address_nv (x, omode, offset);
10775     }
10776
10777   /* If X is a comparison operator, rewrite it in a new mode.  This
10778      probably won't match, but may allow further simplifications.  */
10779   else if (COMPARISON_P (x))
10780     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10781
10782   /* If we couldn't simplify X any other way, just enclose it in a
10783      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10784      include an explicit SUBREG or we may simplify it further in combine.  */
10785   else
10786     {
10787       int offset = 0;
10788       rtx res;
10789
10790       offset = subreg_lowpart_offset (omode, imode);
10791       if (imode == VOIDmode)
10792         {
10793           imode = int_mode_for_mode (omode);
10794           x = gen_lowpart_common (imode, x);
10795           if (x == NULL)
10796             goto fail;
10797         }
10798       res = simplify_gen_subreg (omode, x, imode, offset);
10799       if (res)
10800         return res;
10801     }
10802
10803  fail:
10804   return gen_rtx_CLOBBER (omode, const0_rtx);
10805 }
10806 \f
10807 /* Try to simplify a comparison between OP0 and a constant OP1,
10808    where CODE is the comparison code that will be tested, into a
10809    (CODE OP0 const0_rtx) form.
10810
10811    The result is a possibly different comparison code to use.
10812    *POP1 may be updated.  */
10813
10814 static enum rtx_code
10815 simplify_compare_const (enum rtx_code code, enum machine_mode mode,
10816                         rtx op0, rtx *pop1)
10817 {
10818   unsigned int mode_width = GET_MODE_PRECISION (mode);
10819   HOST_WIDE_INT const_op = INTVAL (*pop1);
10820
10821   /* Get the constant we are comparing against and turn off all bits
10822      not on in our mode.  */
10823   if (mode != VOIDmode)
10824     const_op = trunc_int_for_mode (const_op, mode);
10825
10826   /* If we are comparing against a constant power of two and the value
10827      being compared can only have that single bit nonzero (e.g., it was
10828      `and'ed with that bit), we can replace this with a comparison
10829      with zero.  */
10830   if (const_op
10831       && (code == EQ || code == NE || code == GE || code == GEU
10832           || code == LT || code == LTU)
10833       && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10834       && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0
10835       && (nonzero_bits (op0, mode)
10836           == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode))))
10837     {
10838       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10839       const_op = 0;
10840     }
10841
10842   /* Similarly, if we are comparing a value known to be either -1 or
10843      0 with -1, change it to the opposite comparison against zero.  */
10844   if (const_op == -1
10845       && (code == EQ || code == NE || code == GT || code == LE
10846           || code == GEU || code == LTU)
10847       && num_sign_bit_copies (op0, mode) == mode_width)
10848     {
10849       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10850       const_op = 0;
10851     }
10852
10853   /* Do some canonicalizations based on the comparison code.  We prefer
10854      comparisons against zero and then prefer equality comparisons.
10855      If we can reduce the size of a constant, we will do that too.  */
10856   switch (code)
10857     {
10858     case LT:
10859       /* < C is equivalent to <= (C - 1) */
10860       if (const_op > 0)
10861         {
10862           const_op -= 1;
10863           code = LE;
10864           /* ... fall through to LE case below.  */
10865         }
10866       else
10867         break;
10868
10869     case LE:
10870       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10871       if (const_op < 0)
10872         {
10873           const_op += 1;
10874           code = LT;
10875         }
10876
10877       /* If we are doing a <= 0 comparison on a value known to have
10878          a zero sign bit, we can replace this with == 0.  */
10879       else if (const_op == 0
10880                && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10881                && (nonzero_bits (op0, mode)
10882                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10883                == 0)
10884         code = EQ;
10885       break;
10886
10887     case GE:
10888       /* >= C is equivalent to > (C - 1).  */
10889       if (const_op > 0)
10890         {
10891           const_op -= 1;
10892           code = GT;
10893           /* ... fall through to GT below.  */
10894         }
10895       else
10896         break;
10897
10898     case GT:
10899       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10900       if (const_op < 0)
10901         {
10902           const_op += 1;
10903           code = GE;
10904         }
10905
10906       /* If we are doing a > 0 comparison on a value known to have
10907          a zero sign bit, we can replace this with != 0.  */
10908       else if (const_op == 0
10909                && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10910                && (nonzero_bits (op0, mode)
10911                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10912                == 0)
10913         code = NE;
10914       break;
10915
10916     case LTU:
10917       /* < C is equivalent to <= (C - 1).  */
10918       if (const_op > 0)
10919         {
10920           const_op -= 1;
10921           code = LEU;
10922           /* ... fall through ...  */
10923         }
10924       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10925       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
10926                && (unsigned HOST_WIDE_INT) const_op
10927                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10928         {
10929           const_op = 0;
10930           code = GE;
10931           break;
10932         }
10933       else
10934         break;
10935
10936     case LEU:
10937       /* unsigned <= 0 is equivalent to == 0 */
10938       if (const_op == 0)
10939         code = EQ;
10940       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10941       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
10942                && (unsigned HOST_WIDE_INT) const_op
10943                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10944         {
10945           const_op = 0;
10946           code = GE;
10947         }
10948       break;
10949
10950     case GEU:
10951       /* >= C is equivalent to > (C - 1).  */
10952       if (const_op > 1)
10953         {
10954           const_op -= 1;
10955           code = GTU;
10956           /* ... fall through ...  */
10957         }
10958
10959       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10960       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
10961                && (unsigned HOST_WIDE_INT) const_op
10962                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10963         {
10964           const_op = 0;
10965           code = LT;
10966           break;
10967         }
10968       else
10969         break;
10970
10971     case GTU:
10972       /* unsigned > 0 is equivalent to != 0 */
10973       if (const_op == 0)
10974         code = NE;
10975       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
10976       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
10977                && (unsigned HOST_WIDE_INT) const_op
10978                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10979         {
10980           const_op = 0;
10981           code = LT;
10982         }
10983       break;
10984
10985     default:
10986       break;
10987     }
10988
10989   *pop1 = GEN_INT (const_op);
10990   return code;
10991 }
10992 \f
10993 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10994    comparison code that will be tested.
10995
10996    The result is a possibly different comparison code to use.  *POP0 and
10997    *POP1 may be updated.
10998
10999    It is possible that we might detect that a comparison is either always
11000    true or always false.  However, we do not perform general constant
11001    folding in combine, so this knowledge isn't useful.  Such tautologies
11002    should have been detected earlier.  Hence we ignore all such cases.  */
11003
11004 static enum rtx_code
11005 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11006 {
11007   rtx op0 = *pop0;
11008   rtx op1 = *pop1;
11009   rtx tem, tem1;
11010   int i;
11011   enum machine_mode mode, tmode;
11012
11013   /* Try a few ways of applying the same transformation to both operands.  */
11014   while (1)
11015     {
11016 #ifndef WORD_REGISTER_OPERATIONS
11017       /* The test below this one won't handle SIGN_EXTENDs on these machines,
11018          so check specially.  */
11019       if (code != GTU && code != GEU && code != LTU && code != LEU
11020           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11021           && GET_CODE (XEXP (op0, 0)) == ASHIFT
11022           && GET_CODE (XEXP (op1, 0)) == ASHIFT
11023           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11024           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11025           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11026               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11027           && CONST_INT_P (XEXP (op0, 1))
11028           && XEXP (op0, 1) == XEXP (op1, 1)
11029           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11030           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11031           && (INTVAL (XEXP (op0, 1))
11032               == (GET_MODE_PRECISION (GET_MODE (op0))
11033                   - (GET_MODE_PRECISION
11034                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11035         {
11036           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11037           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11038         }
11039 #endif
11040
11041       /* If both operands are the same constant shift, see if we can ignore the
11042          shift.  We can if the shift is a rotate or if the bits shifted out of
11043          this shift are known to be zero for both inputs and if the type of
11044          comparison is compatible with the shift.  */
11045       if (GET_CODE (op0) == GET_CODE (op1)
11046           && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
11047           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11048               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11049                   && (code != GT && code != LT && code != GE && code != LE))
11050               || (GET_CODE (op0) == ASHIFTRT
11051                   && (code != GTU && code != LTU
11052                       && code != GEU && code != LEU)))
11053           && CONST_INT_P (XEXP (op0, 1))
11054           && INTVAL (XEXP (op0, 1)) >= 0
11055           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11056           && XEXP (op0, 1) == XEXP (op1, 1))
11057         {
11058           enum machine_mode mode = GET_MODE (op0);
11059           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11060           int shift_count = INTVAL (XEXP (op0, 1));
11061
11062           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11063             mask &= (mask >> shift_count) << shift_count;
11064           else if (GET_CODE (op0) == ASHIFT)
11065             mask = (mask & (mask << shift_count)) >> shift_count;
11066
11067           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11068               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11069             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11070           else
11071             break;
11072         }
11073
11074       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11075          SUBREGs are of the same mode, and, in both cases, the AND would
11076          be redundant if the comparison was done in the narrower mode,
11077          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11078          and the operand's possibly nonzero bits are 0xffffff01; in that case
11079          if we only care about QImode, we don't need the AND).  This case
11080          occurs if the output mode of an scc insn is not SImode and
11081          STORE_FLAG_VALUE == 1 (e.g., the 386).
11082
11083          Similarly, check for a case where the AND's are ZERO_EXTEND
11084          operations from some narrower mode even though a SUBREG is not
11085          present.  */
11086
11087       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11088                && CONST_INT_P (XEXP (op0, 1))
11089                && CONST_INT_P (XEXP (op1, 1)))
11090         {
11091           rtx inner_op0 = XEXP (op0, 0);
11092           rtx inner_op1 = XEXP (op1, 0);
11093           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11094           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11095           int changed = 0;
11096
11097           if (paradoxical_subreg_p (inner_op0)
11098               && GET_CODE (inner_op1) == SUBREG
11099               && (GET_MODE (SUBREG_REG (inner_op0))
11100                   == GET_MODE (SUBREG_REG (inner_op1)))
11101               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11102                   <= HOST_BITS_PER_WIDE_INT)
11103               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11104                                              GET_MODE (SUBREG_REG (inner_op0)))))
11105               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11106                                              GET_MODE (SUBREG_REG (inner_op1))))))
11107             {
11108               op0 = SUBREG_REG (inner_op0);
11109               op1 = SUBREG_REG (inner_op1);
11110
11111               /* The resulting comparison is always unsigned since we masked
11112                  off the original sign bit.  */
11113               code = unsigned_condition (code);
11114
11115               changed = 1;
11116             }
11117
11118           else if (c0 == c1)
11119             for (tmode = GET_CLASS_NARROWEST_MODE
11120                  (GET_MODE_CLASS (GET_MODE (op0)));
11121                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11122               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11123                 {
11124                   op0 = gen_lowpart (tmode, inner_op0);
11125                   op1 = gen_lowpart (tmode, inner_op1);
11126                   code = unsigned_condition (code);
11127                   changed = 1;
11128                   break;
11129                 }
11130
11131           if (! changed)
11132             break;
11133         }
11134
11135       /* If both operands are NOT, we can strip off the outer operation
11136          and adjust the comparison code for swapped operands; similarly for
11137          NEG, except that this must be an equality comparison.  */
11138       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11139                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11140                    && (code == EQ || code == NE)))
11141         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11142
11143       else
11144         break;
11145     }
11146
11147   /* If the first operand is a constant, swap the operands and adjust the
11148      comparison code appropriately, but don't do this if the second operand
11149      is already a constant integer.  */
11150   if (swap_commutative_operands_p (op0, op1))
11151     {
11152       tem = op0, op0 = op1, op1 = tem;
11153       code = swap_condition (code);
11154     }
11155
11156   /* We now enter a loop during which we will try to simplify the comparison.
11157      For the most part, we only are concerned with comparisons with zero,
11158      but some things may really be comparisons with zero but not start
11159      out looking that way.  */
11160
11161   while (CONST_INT_P (op1))
11162     {
11163       enum machine_mode mode = GET_MODE (op0);
11164       unsigned int mode_width = GET_MODE_PRECISION (mode);
11165       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11166       int equality_comparison_p;
11167       int sign_bit_comparison_p;
11168       int unsigned_comparison_p;
11169       HOST_WIDE_INT const_op;
11170
11171       /* We only want to handle integral modes.  This catches VOIDmode,
11172          CCmode, and the floating-point modes.  An exception is that we
11173          can handle VOIDmode if OP0 is a COMPARE or a comparison
11174          operation.  */
11175
11176       if (GET_MODE_CLASS (mode) != MODE_INT
11177           && ! (mode == VOIDmode
11178                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11179         break;
11180
11181       /* Try to simplify the compare to constant, possibly changing the
11182          comparison op, and/or changing op1 to zero.  */
11183       code = simplify_compare_const (code, mode, op0, &op1);
11184       const_op = INTVAL (op1);
11185
11186       /* Compute some predicates to simplify code below.  */
11187
11188       equality_comparison_p = (code == EQ || code == NE);
11189       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11190       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11191                                || code == GEU);
11192
11193       /* If this is a sign bit comparison and we can do arithmetic in
11194          MODE, say that we will only be needing the sign bit of OP0.  */
11195       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11196         op0 = force_to_mode (op0, mode,
11197                              (unsigned HOST_WIDE_INT) 1
11198                              << (GET_MODE_PRECISION (mode) - 1),
11199                              0);
11200
11201       /* Now try cases based on the opcode of OP0.  If none of the cases
11202          does a "continue", we exit this loop immediately after the
11203          switch.  */
11204
11205       switch (GET_CODE (op0))
11206         {
11207         case ZERO_EXTRACT:
11208           /* If we are extracting a single bit from a variable position in
11209              a constant that has only a single bit set and are comparing it
11210              with zero, we can convert this into an equality comparison
11211              between the position and the location of the single bit.  */
11212           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11213              have already reduced the shift count modulo the word size.  */
11214           if (!SHIFT_COUNT_TRUNCATED
11215               && CONST_INT_P (XEXP (op0, 0))
11216               && XEXP (op0, 1) == const1_rtx
11217               && equality_comparison_p && const_op == 0
11218               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11219             {
11220               if (BITS_BIG_ENDIAN)
11221                 i = BITS_PER_WORD - 1 - i;
11222
11223               op0 = XEXP (op0, 2);
11224               op1 = GEN_INT (i);
11225               const_op = i;
11226
11227               /* Result is nonzero iff shift count is equal to I.  */
11228               code = reverse_condition (code);
11229               continue;
11230             }
11231
11232           /* ... fall through ...  */
11233
11234         case SIGN_EXTRACT:
11235           tem = expand_compound_operation (op0);
11236           if (tem != op0)
11237             {
11238               op0 = tem;
11239               continue;
11240             }
11241           break;
11242
11243         case NOT:
11244           /* If testing for equality, we can take the NOT of the constant.  */
11245           if (equality_comparison_p
11246               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11247             {
11248               op0 = XEXP (op0, 0);
11249               op1 = tem;
11250               continue;
11251             }
11252
11253           /* If just looking at the sign bit, reverse the sense of the
11254              comparison.  */
11255           if (sign_bit_comparison_p)
11256             {
11257               op0 = XEXP (op0, 0);
11258               code = (code == GE ? LT : GE);
11259               continue;
11260             }
11261           break;
11262
11263         case NEG:
11264           /* If testing for equality, we can take the NEG of the constant.  */
11265           if (equality_comparison_p
11266               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11267             {
11268               op0 = XEXP (op0, 0);
11269               op1 = tem;
11270               continue;
11271             }
11272
11273           /* The remaining cases only apply to comparisons with zero.  */
11274           if (const_op != 0)
11275             break;
11276
11277           /* When X is ABS or is known positive,
11278              (neg X) is < 0 if and only if X != 0.  */
11279
11280           if (sign_bit_comparison_p
11281               && (GET_CODE (XEXP (op0, 0)) == ABS
11282                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11283                       && (nonzero_bits (XEXP (op0, 0), mode)
11284                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11285                          == 0)))
11286             {
11287               op0 = XEXP (op0, 0);
11288               code = (code == LT ? NE : EQ);
11289               continue;
11290             }
11291
11292           /* If we have NEG of something whose two high-order bits are the
11293              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11294           if (num_sign_bit_copies (op0, mode) >= 2)
11295             {
11296               op0 = XEXP (op0, 0);
11297               code = swap_condition (code);
11298               continue;
11299             }
11300           break;
11301
11302         case ROTATE:
11303           /* If we are testing equality and our count is a constant, we
11304              can perform the inverse operation on our RHS.  */
11305           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11306               && (tem = simplify_binary_operation (ROTATERT, mode,
11307                                                    op1, XEXP (op0, 1))) != 0)
11308             {
11309               op0 = XEXP (op0, 0);
11310               op1 = tem;
11311               continue;
11312             }
11313
11314           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11315              a particular bit.  Convert it to an AND of a constant of that
11316              bit.  This will be converted into a ZERO_EXTRACT.  */
11317           if (const_op == 0 && sign_bit_comparison_p
11318               && CONST_INT_P (XEXP (op0, 1))
11319               && mode_width <= HOST_BITS_PER_WIDE_INT)
11320             {
11321               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11322                                             ((unsigned HOST_WIDE_INT) 1
11323                                              << (mode_width - 1
11324                                                  - INTVAL (XEXP (op0, 1)))));
11325               code = (code == LT ? NE : EQ);
11326               continue;
11327             }
11328
11329           /* Fall through.  */
11330
11331         case ABS:
11332           /* ABS is ignorable inside an equality comparison with zero.  */
11333           if (const_op == 0 && equality_comparison_p)
11334             {
11335               op0 = XEXP (op0, 0);
11336               continue;
11337             }
11338           break;
11339
11340         case SIGN_EXTEND:
11341           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11342              (compare FOO CONST) if CONST fits in FOO's mode and we
11343              are either testing inequality or have an unsigned
11344              comparison with ZERO_EXTEND or a signed comparison with
11345              SIGN_EXTEND.  But don't do it if we don't have a compare
11346              insn of the given mode, since we'd have to revert it
11347              later on, and then we wouldn't know whether to sign- or
11348              zero-extend.  */
11349           mode = GET_MODE (XEXP (op0, 0));
11350           if (GET_MODE_CLASS (mode) == MODE_INT
11351               && ! unsigned_comparison_p
11352               && HWI_COMPUTABLE_MODE_P (mode)
11353               && trunc_int_for_mode (const_op, mode) == const_op
11354               && have_insn_for (COMPARE, mode))
11355             {
11356               op0 = XEXP (op0, 0);
11357               continue;
11358             }
11359           break;
11360
11361         case SUBREG:
11362           /* Check for the case where we are comparing A - C1 with C2, that is
11363
11364                (subreg:MODE (plus (A) (-C1))) op (C2)
11365
11366              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11367              comparison in the wider mode.  One of the following two conditions
11368              must be true in order for this to be valid:
11369
11370                1. The mode extension results in the same bit pattern being added
11371                   on both sides and the comparison is equality or unsigned.  As
11372                   C2 has been truncated to fit in MODE, the pattern can only be
11373                   all 0s or all 1s.
11374
11375                2. The mode extension results in the sign bit being copied on
11376                   each side.
11377
11378              The difficulty here is that we have predicates for A but not for
11379              (A - C1) so we need to check that C1 is within proper bounds so
11380              as to perturbate A as little as possible.  */
11381
11382           if (mode_width <= HOST_BITS_PER_WIDE_INT
11383               && subreg_lowpart_p (op0)
11384               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11385               && GET_CODE (SUBREG_REG (op0)) == PLUS
11386               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11387             {
11388               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11389               rtx a = XEXP (SUBREG_REG (op0), 0);
11390               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11391
11392               if ((c1 > 0
11393                    && (unsigned HOST_WIDE_INT) c1
11394                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11395                    && (equality_comparison_p || unsigned_comparison_p)
11396                    /* (A - C1) zero-extends if it is positive and sign-extends
11397                       if it is negative, C2 both zero- and sign-extends.  */
11398                    && ((0 == (nonzero_bits (a, inner_mode)
11399                               & ~GET_MODE_MASK (mode))
11400                         && const_op >= 0)
11401                        /* (A - C1) sign-extends if it is positive and 1-extends
11402                           if it is negative, C2 both sign- and 1-extends.  */
11403                        || (num_sign_bit_copies (a, inner_mode)
11404                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11405                                              - mode_width)
11406                            && const_op < 0)))
11407                   || ((unsigned HOST_WIDE_INT) c1
11408                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11409                       /* (A - C1) always sign-extends, like C2.  */
11410                       && num_sign_bit_copies (a, inner_mode)
11411                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11412                                            - (mode_width - 1))))
11413                 {
11414                   op0 = SUBREG_REG (op0);
11415                   continue;
11416                 }
11417             }
11418
11419           /* If the inner mode is narrower and we are extracting the low part,
11420              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11421           if (subreg_lowpart_p (op0)
11422               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11423             /* Fall through */ ;
11424           else
11425             break;
11426
11427           /* ... fall through ...  */
11428
11429         case ZERO_EXTEND:
11430           mode = GET_MODE (XEXP (op0, 0));
11431           if (GET_MODE_CLASS (mode) == MODE_INT
11432               && (unsigned_comparison_p || equality_comparison_p)
11433               && HWI_COMPUTABLE_MODE_P (mode)
11434               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11435               && const_op >= 0
11436               && have_insn_for (COMPARE, mode))
11437             {
11438               op0 = XEXP (op0, 0);
11439               continue;
11440             }
11441           break;
11442
11443         case PLUS:
11444           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11445              this for equality comparisons due to pathological cases involving
11446              overflows.  */
11447           if (equality_comparison_p
11448               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11449                                                         op1, XEXP (op0, 1))))
11450             {
11451               op0 = XEXP (op0, 0);
11452               op1 = tem;
11453               continue;
11454             }
11455
11456           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11457           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11458               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11459             {
11460               op0 = XEXP (XEXP (op0, 0), 0);
11461               code = (code == LT ? EQ : NE);
11462               continue;
11463             }
11464           break;
11465
11466         case MINUS:
11467           /* We used to optimize signed comparisons against zero, but that
11468              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11469              arrive here as equality comparisons, or (GEU, LTU) are
11470              optimized away.  No need to special-case them.  */
11471
11472           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11473              (eq B (minus A C)), whichever simplifies.  We can only do
11474              this for equality comparisons due to pathological cases involving
11475              overflows.  */
11476           if (equality_comparison_p
11477               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11478                                                         XEXP (op0, 1), op1)))
11479             {
11480               op0 = XEXP (op0, 0);
11481               op1 = tem;
11482               continue;
11483             }
11484
11485           if (equality_comparison_p
11486               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11487                                                         XEXP (op0, 0), op1)))
11488             {
11489               op0 = XEXP (op0, 1);
11490               op1 = tem;
11491               continue;
11492             }
11493
11494           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11495              of bits in X minus 1, is one iff X > 0.  */
11496           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11497               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11498               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11499               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11500             {
11501               op0 = XEXP (op0, 1);
11502               code = (code == GE ? LE : GT);
11503               continue;
11504             }
11505           break;
11506
11507         case XOR:
11508           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11509              if C is zero or B is a constant.  */
11510           if (equality_comparison_p
11511               && 0 != (tem = simplify_binary_operation (XOR, mode,
11512                                                         XEXP (op0, 1), op1)))
11513             {
11514               op0 = XEXP (op0, 0);
11515               op1 = tem;
11516               continue;
11517             }
11518           break;
11519
11520         case EQ:  case NE:
11521         case UNEQ:  case LTGT:
11522         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11523         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11524         case UNORDERED: case ORDERED:
11525           /* We can't do anything if OP0 is a condition code value, rather
11526              than an actual data value.  */
11527           if (const_op != 0
11528               || CC0_P (XEXP (op0, 0))
11529               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11530             break;
11531
11532           /* Get the two operands being compared.  */
11533           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11534             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11535           else
11536             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11537
11538           /* Check for the cases where we simply want the result of the
11539              earlier test or the opposite of that result.  */
11540           if (code == NE || code == EQ
11541               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11542                   && (code == LT || code == GE)))
11543             {
11544               enum rtx_code new_code;
11545               if (code == LT || code == NE)
11546                 new_code = GET_CODE (op0);
11547               else
11548                 new_code = reversed_comparison_code (op0, NULL);
11549
11550               if (new_code != UNKNOWN)
11551                 {
11552                   code = new_code;
11553                   op0 = tem;
11554                   op1 = tem1;
11555                   continue;
11556                 }
11557             }
11558           break;
11559
11560         case IOR:
11561           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11562              iff X <= 0.  */
11563           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11564               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11565               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11566             {
11567               op0 = XEXP (op0, 1);
11568               code = (code == GE ? GT : LE);
11569               continue;
11570             }
11571           break;
11572
11573         case AND:
11574           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11575              will be converted to a ZERO_EXTRACT later.  */
11576           if (const_op == 0 && equality_comparison_p
11577               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11578               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11579             {
11580               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11581                                       XEXP (XEXP (op0, 0), 1));
11582               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11583               continue;
11584             }
11585
11586           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11587              zero and X is a comparison and C1 and C2 describe only bits set
11588              in STORE_FLAG_VALUE, we can compare with X.  */
11589           if (const_op == 0 && equality_comparison_p
11590               && mode_width <= HOST_BITS_PER_WIDE_INT
11591               && CONST_INT_P (XEXP (op0, 1))
11592               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11593               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11594               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11595               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11596             {
11597               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11598                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11599               if ((~STORE_FLAG_VALUE & mask) == 0
11600                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11601                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11602                           && COMPARISON_P (tem))))
11603                 {
11604                   op0 = XEXP (XEXP (op0, 0), 0);
11605                   continue;
11606                 }
11607             }
11608
11609           /* If we are doing an equality comparison of an AND of a bit equal
11610              to the sign bit, replace this with a LT or GE comparison of
11611              the underlying value.  */
11612           if (equality_comparison_p
11613               && const_op == 0
11614               && CONST_INT_P (XEXP (op0, 1))
11615               && mode_width <= HOST_BITS_PER_WIDE_INT
11616               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11617                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11618             {
11619               op0 = XEXP (op0, 0);
11620               code = (code == EQ ? GE : LT);
11621               continue;
11622             }
11623
11624           /* If this AND operation is really a ZERO_EXTEND from a narrower
11625              mode, the constant fits within that mode, and this is either an
11626              equality or unsigned comparison, try to do this comparison in
11627              the narrower mode.
11628
11629              Note that in:
11630
11631              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11632              -> (ne:DI (reg:SI 4) (const_int 0))
11633
11634              unless TRULY_NOOP_TRUNCATION allows it or the register is
11635              known to hold a value of the required mode the
11636              transformation is invalid.  */
11637           if ((equality_comparison_p || unsigned_comparison_p)
11638               && CONST_INT_P (XEXP (op0, 1))
11639               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11640                                    & GET_MODE_MASK (mode))
11641                                   + 1)) >= 0
11642               && const_op >> i == 0
11643               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11644               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11645                   || (REG_P (XEXP (op0, 0))
11646                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11647             {
11648               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11649               continue;
11650             }
11651
11652           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11653              fits in both M1 and M2 and the SUBREG is either paradoxical
11654              or represents the low part, permute the SUBREG and the AND
11655              and try again.  */
11656           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11657             {
11658               unsigned HOST_WIDE_INT c1;
11659               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11660               /* Require an integral mode, to avoid creating something like
11661                  (AND:SF ...).  */
11662               if (SCALAR_INT_MODE_P (tmode)
11663                   /* It is unsafe to commute the AND into the SUBREG if the
11664                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11665                      not defined.  As originally written the upper bits
11666                      have a defined value due to the AND operation.
11667                      However, if we commute the AND inside the SUBREG then
11668                      they no longer have defined values and the meaning of
11669                      the code has been changed.  */
11670                   && (0
11671 #ifdef WORD_REGISTER_OPERATIONS
11672                       || (mode_width > GET_MODE_PRECISION (tmode)
11673                           && mode_width <= BITS_PER_WORD)
11674 #endif
11675                       || (mode_width <= GET_MODE_PRECISION (tmode)
11676                           && subreg_lowpart_p (XEXP (op0, 0))))
11677                   && CONST_INT_P (XEXP (op0, 1))
11678                   && mode_width <= HOST_BITS_PER_WIDE_INT
11679                   && HWI_COMPUTABLE_MODE_P (tmode)
11680                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11681                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11682                   && c1 != mask
11683                   && c1 != GET_MODE_MASK (tmode))
11684                 {
11685                   op0 = simplify_gen_binary (AND, tmode,
11686                                              SUBREG_REG (XEXP (op0, 0)),
11687                                              gen_int_mode (c1, tmode));
11688                   op0 = gen_lowpart (mode, op0);
11689                   continue;
11690                 }
11691             }
11692
11693           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11694           if (const_op == 0 && equality_comparison_p
11695               && XEXP (op0, 1) == const1_rtx
11696               && GET_CODE (XEXP (op0, 0)) == NOT)
11697             {
11698               op0 = simplify_and_const_int (NULL_RTX, mode,
11699                                             XEXP (XEXP (op0, 0), 0), 1);
11700               code = (code == NE ? EQ : NE);
11701               continue;
11702             }
11703
11704           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11705              (eq (and (lshiftrt X) 1) 0).
11706              Also handle the case where (not X) is expressed using xor.  */
11707           if (const_op == 0 && equality_comparison_p
11708               && XEXP (op0, 1) == const1_rtx
11709               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11710             {
11711               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11712               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11713
11714               if (GET_CODE (shift_op) == NOT
11715                   || (GET_CODE (shift_op) == XOR
11716                       && CONST_INT_P (XEXP (shift_op, 1))
11717                       && CONST_INT_P (shift_count)
11718                       && HWI_COMPUTABLE_MODE_P (mode)
11719                       && (UINTVAL (XEXP (shift_op, 1))
11720                           == (unsigned HOST_WIDE_INT) 1
11721                                << INTVAL (shift_count))))
11722                 {
11723                   op0
11724                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11725                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11726                   code = (code == NE ? EQ : NE);
11727                   continue;
11728                 }
11729             }
11730           break;
11731
11732         case ASHIFT:
11733           /* If we have (compare (ashift FOO N) (const_int C)) and
11734              the high order N bits of FOO (N+1 if an inequality comparison)
11735              are known to be zero, we can do this by comparing FOO with C
11736              shifted right N bits so long as the low-order N bits of C are
11737              zero.  */
11738           if (CONST_INT_P (XEXP (op0, 1))
11739               && INTVAL (XEXP (op0, 1)) >= 0
11740               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11741                   < HOST_BITS_PER_WIDE_INT)
11742               && (((unsigned HOST_WIDE_INT) const_op
11743                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11744                       - 1)) == 0)
11745               && mode_width <= HOST_BITS_PER_WIDE_INT
11746               && (nonzero_bits (XEXP (op0, 0), mode)
11747                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11748                                + ! equality_comparison_p))) == 0)
11749             {
11750               /* We must perform a logical shift, not an arithmetic one,
11751                  as we want the top N bits of C to be zero.  */
11752               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11753
11754               temp >>= INTVAL (XEXP (op0, 1));
11755               op1 = gen_int_mode (temp, mode);
11756               op0 = XEXP (op0, 0);
11757               continue;
11758             }
11759
11760           /* If we are doing a sign bit comparison, it means we are testing
11761              a particular bit.  Convert it to the appropriate AND.  */
11762           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11763               && mode_width <= HOST_BITS_PER_WIDE_INT)
11764             {
11765               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11766                                             ((unsigned HOST_WIDE_INT) 1
11767                                              << (mode_width - 1
11768                                                  - INTVAL (XEXP (op0, 1)))));
11769               code = (code == LT ? NE : EQ);
11770               continue;
11771             }
11772
11773           /* If this an equality comparison with zero and we are shifting
11774              the low bit to the sign bit, we can convert this to an AND of the
11775              low-order bit.  */
11776           if (const_op == 0 && equality_comparison_p
11777               && CONST_INT_P (XEXP (op0, 1))
11778               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11779             {
11780               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11781               continue;
11782             }
11783           break;
11784
11785         case ASHIFTRT:
11786           /* If this is an equality comparison with zero, we can do this
11787              as a logical shift, which might be much simpler.  */
11788           if (equality_comparison_p && const_op == 0
11789               && CONST_INT_P (XEXP (op0, 1)))
11790             {
11791               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11792                                           XEXP (op0, 0),
11793                                           INTVAL (XEXP (op0, 1)));
11794               continue;
11795             }
11796
11797           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11798              do the comparison in a narrower mode.  */
11799           if (! unsigned_comparison_p
11800               && CONST_INT_P (XEXP (op0, 1))
11801               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11802               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11803               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11804                                          MODE_INT, 1)) != BLKmode
11805               && (((unsigned HOST_WIDE_INT) const_op
11806                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11807                   <= GET_MODE_MASK (tmode)))
11808             {
11809               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11810               continue;
11811             }
11812
11813           /* Likewise if OP0 is a PLUS of a sign extension with a
11814              constant, which is usually represented with the PLUS
11815              between the shifts.  */
11816           if (! unsigned_comparison_p
11817               && CONST_INT_P (XEXP (op0, 1))
11818               && GET_CODE (XEXP (op0, 0)) == PLUS
11819               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11820               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11821               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11822               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11823                                          MODE_INT, 1)) != BLKmode
11824               && (((unsigned HOST_WIDE_INT) const_op
11825                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11826                   <= GET_MODE_MASK (tmode)))
11827             {
11828               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11829               rtx add_const = XEXP (XEXP (op0, 0), 1);
11830               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11831                                                    add_const, XEXP (op0, 1));
11832
11833               op0 = simplify_gen_binary (PLUS, tmode,
11834                                          gen_lowpart (tmode, inner),
11835                                          new_const);
11836               continue;
11837             }
11838
11839           /* ... fall through ...  */
11840         case LSHIFTRT:
11841           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11842              the low order N bits of FOO are known to be zero, we can do this
11843              by comparing FOO with C shifted left N bits so long as no
11844              overflow occurs.  Even if the low order N bits of FOO aren't known
11845              to be zero, if the comparison is >= or < we can use the same
11846              optimization and for > or <= by setting all the low
11847              order N bits in the comparison constant.  */
11848           if (CONST_INT_P (XEXP (op0, 1))
11849               && INTVAL (XEXP (op0, 1)) > 0
11850               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11851               && mode_width <= HOST_BITS_PER_WIDE_INT
11852               && (((unsigned HOST_WIDE_INT) const_op
11853                    + (GET_CODE (op0) != LSHIFTRT
11854                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11855                          + 1)
11856                       : 0))
11857                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11858             {
11859               unsigned HOST_WIDE_INT low_bits
11860                 = (nonzero_bits (XEXP (op0, 0), mode)
11861                    & (((unsigned HOST_WIDE_INT) 1
11862                        << INTVAL (XEXP (op0, 1))) - 1));
11863               if (low_bits == 0 || !equality_comparison_p)
11864                 {
11865                   /* If the shift was logical, then we must make the condition
11866                      unsigned.  */
11867                   if (GET_CODE (op0) == LSHIFTRT)
11868                     code = unsigned_condition (code);
11869
11870                   const_op <<= INTVAL (XEXP (op0, 1));
11871                   if (low_bits != 0
11872                       && (code == GT || code == GTU
11873                           || code == LE || code == LEU))
11874                     const_op
11875                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11876                   op1 = GEN_INT (const_op);
11877                   op0 = XEXP (op0, 0);
11878                   continue;
11879                 }
11880             }
11881
11882           /* If we are using this shift to extract just the sign bit, we
11883              can replace this with an LT or GE comparison.  */
11884           if (const_op == 0
11885               && (equality_comparison_p || sign_bit_comparison_p)
11886               && CONST_INT_P (XEXP (op0, 1))
11887               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11888             {
11889               op0 = XEXP (op0, 0);
11890               code = (code == NE || code == GT ? LT : GE);
11891               continue;
11892             }
11893           break;
11894
11895         default:
11896           break;
11897         }
11898
11899       break;
11900     }
11901
11902   /* Now make any compound operations involved in this comparison.  Then,
11903      check for an outmost SUBREG on OP0 that is not doing anything or is
11904      paradoxical.  The latter transformation must only be performed when
11905      it is known that the "extra" bits will be the same in op0 and op1 or
11906      that they don't matter.  There are three cases to consider:
11907
11908      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11909      care bits and we can assume they have any convenient value.  So
11910      making the transformation is safe.
11911
11912      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11913      In this case the upper bits of op0 are undefined.  We should not make
11914      the simplification in that case as we do not know the contents of
11915      those bits.
11916
11917      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11918      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11919      also be sure that they are the same as the upper bits of op1.
11920
11921      We can never remove a SUBREG for a non-equality comparison because
11922      the sign bit is in a different place in the underlying object.  */
11923
11924   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11925   op1 = make_compound_operation (op1, SET);
11926
11927   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11928       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11929       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11930       && (code == NE || code == EQ))
11931     {
11932       if (paradoxical_subreg_p (op0))
11933         {
11934           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11935              implemented.  */
11936           if (REG_P (SUBREG_REG (op0)))
11937             {
11938               op0 = SUBREG_REG (op0);
11939               op1 = gen_lowpart (GET_MODE (op0), op1);
11940             }
11941         }
11942       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
11943                 <= HOST_BITS_PER_WIDE_INT)
11944                && (nonzero_bits (SUBREG_REG (op0),
11945                                  GET_MODE (SUBREG_REG (op0)))
11946                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11947         {
11948           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11949
11950           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11951                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11952             op0 = SUBREG_REG (op0), op1 = tem;
11953         }
11954     }
11955
11956   /* We now do the opposite procedure: Some machines don't have compare
11957      insns in all modes.  If OP0's mode is an integer mode smaller than a
11958      word and we can't do a compare in that mode, see if there is a larger
11959      mode for which we can do the compare.  There are a number of cases in
11960      which we can use the wider mode.  */
11961
11962   mode = GET_MODE (op0);
11963   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11964       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11965       && ! have_insn_for (COMPARE, mode))
11966     for (tmode = GET_MODE_WIDER_MODE (mode);
11967          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
11968          tmode = GET_MODE_WIDER_MODE (tmode))
11969       if (have_insn_for (COMPARE, tmode))
11970         {
11971           int zero_extended;
11972
11973           /* If this is a test for negative, we can make an explicit
11974              test of the sign bit.  Test this first so we can use
11975              a paradoxical subreg to extend OP0.  */
11976
11977           if (op1 == const0_rtx && (code == LT || code == GE)
11978               && HWI_COMPUTABLE_MODE_P (mode))
11979             {
11980               unsigned HOST_WIDE_INT sign
11981                 = (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1);
11982               op0 = simplify_gen_binary (AND, tmode,
11983                                          gen_lowpart (tmode, op0),
11984                                          gen_int_mode (sign, mode));
11985               code = (code == LT) ? NE : EQ;
11986               break;
11987             }
11988
11989           /* If the only nonzero bits in OP0 and OP1 are those in the
11990              narrower mode and this is an equality or unsigned comparison,
11991              we can use the wider mode.  Similarly for sign-extended
11992              values, in which case it is true for all comparisons.  */
11993           zero_extended = ((code == EQ || code == NE
11994                             || code == GEU || code == GTU
11995                             || code == LEU || code == LTU)
11996                            && (nonzero_bits (op0, tmode)
11997                                & ~GET_MODE_MASK (mode)) == 0
11998                            && ((CONST_INT_P (op1)
11999                                 || (nonzero_bits (op1, tmode)
12000                                     & ~GET_MODE_MASK (mode)) == 0)));
12001
12002           if (zero_extended
12003               || ((num_sign_bit_copies (op0, tmode)
12004                    > (unsigned int) (GET_MODE_PRECISION (tmode)
12005                                      - GET_MODE_PRECISION (mode)))
12006                   && (num_sign_bit_copies (op1, tmode)
12007                       > (unsigned int) (GET_MODE_PRECISION (tmode)
12008                                         - GET_MODE_PRECISION (mode)))))
12009             {
12010               /* If OP0 is an AND and we don't have an AND in MODE either,
12011                  make a new AND in the proper mode.  */
12012               if (GET_CODE (op0) == AND
12013                   && !have_insn_for (AND, mode))
12014                 op0 = simplify_gen_binary (AND, tmode,
12015                                            gen_lowpart (tmode,
12016                                                         XEXP (op0, 0)),
12017                                            gen_lowpart (tmode,
12018                                                         XEXP (op0, 1)));
12019               else
12020                 {
12021                   if (zero_extended)
12022                     {
12023                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12024                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12025                     }
12026                   else
12027                     {
12028                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12029                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12030                     }
12031                   break;
12032                 }
12033             }
12034         }
12035
12036   /* We may have changed the comparison operands.  Re-canonicalize.  */
12037   if (swap_commutative_operands_p (op0, op1))
12038     {
12039       tem = op0, op0 = op1, op1 = tem;
12040       code = swap_condition (code);
12041     }
12042
12043   /* If this machine only supports a subset of valid comparisons, see if we
12044      can convert an unsupported one into a supported one.  */
12045   target_canonicalize_comparison (&code, &op0, &op1, 0);
12046
12047   *pop0 = op0;
12048   *pop1 = op1;
12049
12050   return code;
12051 }
12052 \f
12053 /* Utility function for record_value_for_reg.  Count number of
12054    rtxs in X.  */
12055 static int
12056 count_rtxs (rtx x)
12057 {
12058   enum rtx_code code = GET_CODE (x);
12059   const char *fmt;
12060   int i, j, ret = 1;
12061
12062   if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
12063       || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
12064     {
12065       rtx x0 = XEXP (x, 0);
12066       rtx x1 = XEXP (x, 1);
12067
12068       if (x0 == x1)
12069         return 1 + 2 * count_rtxs (x0);
12070
12071       if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12072            || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12073           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12074         return 2 + 2 * count_rtxs (x0)
12075                + count_rtxs (x == XEXP (x1, 0)
12076                              ? XEXP (x1, 1) : XEXP (x1, 0));
12077
12078       if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12079            || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12080           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12081         return 2 + 2 * count_rtxs (x1)
12082                + count_rtxs (x == XEXP (x0, 0)
12083                              ? XEXP (x0, 1) : XEXP (x0, 0));
12084     }
12085
12086   fmt = GET_RTX_FORMAT (code);
12087   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12088     if (fmt[i] == 'e')
12089       ret += count_rtxs (XEXP (x, i));
12090     else if (fmt[i] == 'E')
12091       for (j = 0; j < XVECLEN (x, i); j++)
12092         ret += count_rtxs (XVECEXP (x, i, j));
12093
12094   return ret;
12095 }
12096 \f
12097 /* Utility function for following routine.  Called when X is part of a value
12098    being stored into last_set_value.  Sets last_set_table_tick
12099    for each register mentioned.  Similar to mention_regs in cse.c  */
12100
12101 static void
12102 update_table_tick (rtx x)
12103 {
12104   enum rtx_code code = GET_CODE (x);
12105   const char *fmt = GET_RTX_FORMAT (code);
12106   int i, j;
12107
12108   if (code == REG)
12109     {
12110       unsigned int regno = REGNO (x);
12111       unsigned int endregno = END_REGNO (x);
12112       unsigned int r;
12113
12114       for (r = regno; r < endregno; r++)
12115         {
12116           reg_stat_type *rsp = &reg_stat[r];
12117           rsp->last_set_table_tick = label_tick;
12118         }
12119
12120       return;
12121     }
12122
12123   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12124     if (fmt[i] == 'e')
12125       {
12126         /* Check for identical subexpressions.  If x contains
12127            identical subexpression we only have to traverse one of
12128            them.  */
12129         if (i == 0 && ARITHMETIC_P (x))
12130           {
12131             /* Note that at this point x1 has already been
12132                processed.  */
12133             rtx x0 = XEXP (x, 0);
12134             rtx x1 = XEXP (x, 1);
12135
12136             /* If x0 and x1 are identical then there is no need to
12137                process x0.  */
12138             if (x0 == x1)
12139               break;
12140
12141             /* If x0 is identical to a subexpression of x1 then while
12142                processing x1, x0 has already been processed.  Thus we
12143                are done with x.  */
12144             if (ARITHMETIC_P (x1)
12145                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12146               break;
12147
12148             /* If x1 is identical to a subexpression of x0 then we
12149                still have to process the rest of x0.  */
12150             if (ARITHMETIC_P (x0)
12151                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12152               {
12153                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12154                 break;
12155               }
12156           }
12157
12158         update_table_tick (XEXP (x, i));
12159       }
12160     else if (fmt[i] == 'E')
12161       for (j = 0; j < XVECLEN (x, i); j++)
12162         update_table_tick (XVECEXP (x, i, j));
12163 }
12164
12165 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12166    are saying that the register is clobbered and we no longer know its
12167    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12168    only permitted with VALUE also zero and is used to invalidate the
12169    register.  */
12170
12171 static void
12172 record_value_for_reg (rtx reg, rtx insn, rtx value)
12173 {
12174   unsigned int regno = REGNO (reg);
12175   unsigned int endregno = END_REGNO (reg);
12176   unsigned int i;
12177   reg_stat_type *rsp;
12178
12179   /* If VALUE contains REG and we have a previous value for REG, substitute
12180      the previous value.  */
12181   if (value && insn && reg_overlap_mentioned_p (reg, value))
12182     {
12183       rtx tem;
12184
12185       /* Set things up so get_last_value is allowed to see anything set up to
12186          our insn.  */
12187       subst_low_luid = DF_INSN_LUID (insn);
12188       tem = get_last_value (reg);
12189
12190       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12191          it isn't going to be useful and will take a lot of time to process,
12192          so just use the CLOBBER.  */
12193
12194       if (tem)
12195         {
12196           if (ARITHMETIC_P (tem)
12197               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12198               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12199             tem = XEXP (tem, 0);
12200           else if (count_occurrences (value, reg, 1) >= 2)
12201             {
12202               /* If there are two or more occurrences of REG in VALUE,
12203                  prevent the value from growing too much.  */
12204               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12205                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12206             }
12207
12208           value = replace_rtx (copy_rtx (value), reg, tem);
12209         }
12210     }
12211
12212   /* For each register modified, show we don't know its value, that
12213      we don't know about its bitwise content, that its value has been
12214      updated, and that we don't know the location of the death of the
12215      register.  */
12216   for (i = regno; i < endregno; i++)
12217     {
12218       rsp = &reg_stat[i];
12219
12220       if (insn)
12221         rsp->last_set = insn;
12222
12223       rsp->last_set_value = 0;
12224       rsp->last_set_mode = VOIDmode;
12225       rsp->last_set_nonzero_bits = 0;
12226       rsp->last_set_sign_bit_copies = 0;
12227       rsp->last_death = 0;
12228       rsp->truncated_to_mode = VOIDmode;
12229     }
12230
12231   /* Mark registers that are being referenced in this value.  */
12232   if (value)
12233     update_table_tick (value);
12234
12235   /* Now update the status of each register being set.
12236      If someone is using this register in this block, set this register
12237      to invalid since we will get confused between the two lives in this
12238      basic block.  This makes using this register always invalid.  In cse, we
12239      scan the table to invalidate all entries using this register, but this
12240      is too much work for us.  */
12241
12242   for (i = regno; i < endregno; i++)
12243     {
12244       rsp = &reg_stat[i];
12245       rsp->last_set_label = label_tick;
12246       if (!insn
12247           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12248         rsp->last_set_invalid = 1;
12249       else
12250         rsp->last_set_invalid = 0;
12251     }
12252
12253   /* The value being assigned might refer to X (like in "x++;").  In that
12254      case, we must replace it with (clobber (const_int 0)) to prevent
12255      infinite loops.  */
12256   rsp = &reg_stat[regno];
12257   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12258     {
12259       value = copy_rtx (value);
12260       if (!get_last_value_validate (&value, insn, label_tick, 1))
12261         value = 0;
12262     }
12263
12264   /* For the main register being modified, update the value, the mode, the
12265      nonzero bits, and the number of sign bit copies.  */
12266
12267   rsp->last_set_value = value;
12268
12269   if (value)
12270     {
12271       enum machine_mode mode = GET_MODE (reg);
12272       subst_low_luid = DF_INSN_LUID (insn);
12273       rsp->last_set_mode = mode;
12274       if (GET_MODE_CLASS (mode) == MODE_INT
12275           && HWI_COMPUTABLE_MODE_P (mode))
12276         mode = nonzero_bits_mode;
12277       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12278       rsp->last_set_sign_bit_copies
12279         = num_sign_bit_copies (value, GET_MODE (reg));
12280     }
12281 }
12282
12283 /* Called via note_stores from record_dead_and_set_regs to handle one
12284    SET or CLOBBER in an insn.  DATA is the instruction in which the
12285    set is occurring.  */
12286
12287 static void
12288 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12289 {
12290   rtx record_dead_insn = (rtx) data;
12291
12292   if (GET_CODE (dest) == SUBREG)
12293     dest = SUBREG_REG (dest);
12294
12295   if (!record_dead_insn)
12296     {
12297       if (REG_P (dest))
12298         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12299       return;
12300     }
12301
12302   if (REG_P (dest))
12303     {
12304       /* If we are setting the whole register, we know its value.  Otherwise
12305          show that we don't know the value.  We can handle SUBREG in
12306          some cases.  */
12307       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12308         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12309       else if (GET_CODE (setter) == SET
12310                && GET_CODE (SET_DEST (setter)) == SUBREG
12311                && SUBREG_REG (SET_DEST (setter)) == dest
12312                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12313                && subreg_lowpart_p (SET_DEST (setter)))
12314         record_value_for_reg (dest, record_dead_insn,
12315                               gen_lowpart (GET_MODE (dest),
12316                                                        SET_SRC (setter)));
12317       else
12318         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12319     }
12320   else if (MEM_P (dest)
12321            /* Ignore pushes, they clobber nothing.  */
12322            && ! push_operand (dest, GET_MODE (dest)))
12323     mem_last_set = DF_INSN_LUID (record_dead_insn);
12324 }
12325
12326 /* Update the records of when each REG was most recently set or killed
12327    for the things done by INSN.  This is the last thing done in processing
12328    INSN in the combiner loop.
12329
12330    We update reg_stat[], in particular fields last_set, last_set_value,
12331    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12332    last_death, and also the similar information mem_last_set (which insn
12333    most recently modified memory) and last_call_luid (which insn was the
12334    most recent subroutine call).  */
12335
12336 static void
12337 record_dead_and_set_regs (rtx insn)
12338 {
12339   rtx link;
12340   unsigned int i;
12341
12342   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12343     {
12344       if (REG_NOTE_KIND (link) == REG_DEAD
12345           && REG_P (XEXP (link, 0)))
12346         {
12347           unsigned int regno = REGNO (XEXP (link, 0));
12348           unsigned int endregno = END_REGNO (XEXP (link, 0));
12349
12350           for (i = regno; i < endregno; i++)
12351             {
12352               reg_stat_type *rsp;
12353
12354               rsp = &reg_stat[i];
12355               rsp->last_death = insn;
12356             }
12357         }
12358       else if (REG_NOTE_KIND (link) == REG_INC)
12359         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12360     }
12361
12362   if (CALL_P (insn))
12363     {
12364       hard_reg_set_iterator hrsi;
12365       EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12366         {
12367           reg_stat_type *rsp;
12368
12369           rsp = &reg_stat[i];
12370           rsp->last_set_invalid = 1;
12371           rsp->last_set = insn;
12372           rsp->last_set_value = 0;
12373           rsp->last_set_mode = VOIDmode;
12374           rsp->last_set_nonzero_bits = 0;
12375           rsp->last_set_sign_bit_copies = 0;
12376           rsp->last_death = 0;
12377           rsp->truncated_to_mode = VOIDmode;
12378         }
12379
12380       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12381
12382       /* We can't combine into a call pattern.  Remember, though, that
12383          the return value register is set at this LUID.  We could
12384          still replace a register with the return value from the
12385          wrong subroutine call!  */
12386       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12387     }
12388   else
12389     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12390 }
12391
12392 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12393    register present in the SUBREG, so for each such SUBREG go back and
12394    adjust nonzero and sign bit information of the registers that are
12395    known to have some zero/sign bits set.
12396
12397    This is needed because when combine blows the SUBREGs away, the
12398    information on zero/sign bits is lost and further combines can be
12399    missed because of that.  */
12400
12401 static void
12402 record_promoted_value (rtx insn, rtx subreg)
12403 {
12404   struct insn_link *links;
12405   rtx set;
12406   unsigned int regno = REGNO (SUBREG_REG (subreg));
12407   enum machine_mode mode = GET_MODE (subreg);
12408
12409   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12410     return;
12411
12412   for (links = LOG_LINKS (insn); links;)
12413     {
12414       reg_stat_type *rsp;
12415
12416       insn = links->insn;
12417       set = single_set (insn);
12418
12419       if (! set || !REG_P (SET_DEST (set))
12420           || REGNO (SET_DEST (set)) != regno
12421           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12422         {
12423           links = links->next;
12424           continue;
12425         }
12426
12427       rsp = &reg_stat[regno];
12428       if (rsp->last_set == insn)
12429         {
12430           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12431             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12432         }
12433
12434       if (REG_P (SET_SRC (set)))
12435         {
12436           regno = REGNO (SET_SRC (set));
12437           links = LOG_LINKS (insn);
12438         }
12439       else
12440         break;
12441     }
12442 }
12443
12444 /* Check if X, a register, is known to contain a value already
12445    truncated to MODE.  In this case we can use a subreg to refer to
12446    the truncated value even though in the generic case we would need
12447    an explicit truncation.  */
12448
12449 static bool
12450 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12451 {
12452   reg_stat_type *rsp = &reg_stat[REGNO (x)];
12453   enum machine_mode truncated = rsp->truncated_to_mode;
12454
12455   if (truncated == 0
12456       || rsp->truncation_label < label_tick_ebb_start)
12457     return false;
12458   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12459     return true;
12460   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12461     return true;
12462   return false;
12463 }
12464
12465 /* Callback for for_each_rtx.  If *P is a hard reg or a subreg record the mode
12466    that the register is accessed in.  For non-TRULY_NOOP_TRUNCATION targets we
12467    might be able to turn a truncate into a subreg using this information.
12468    Return -1 if traversing *P is complete or 0 otherwise.  */
12469
12470 static int
12471 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12472 {
12473   rtx x = *p;
12474   enum machine_mode truncated_mode;
12475   reg_stat_type *rsp;
12476
12477   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12478     {
12479       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12480       truncated_mode = GET_MODE (x);
12481
12482       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12483         return -1;
12484
12485       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12486         return -1;
12487
12488       x = SUBREG_REG (x);
12489     }
12490   /* ??? For hard-regs we now record everything.  We might be able to
12491      optimize this using last_set_mode.  */
12492   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12493     truncated_mode = GET_MODE (x);
12494   else
12495     return 0;
12496
12497   rsp = &reg_stat[REGNO (x)];
12498   if (rsp->truncated_to_mode == 0
12499       || rsp->truncation_label < label_tick_ebb_start
12500       || (GET_MODE_SIZE (truncated_mode)
12501           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12502     {
12503       rsp->truncated_to_mode = truncated_mode;
12504       rsp->truncation_label = label_tick;
12505     }
12506
12507   return -1;
12508 }
12509
12510 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12511    the modes they are used in.  This can help truning TRUNCATEs into
12512    SUBREGs.  */
12513
12514 static void
12515 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12516 {
12517   for_each_rtx (x, record_truncated_value, NULL);
12518 }
12519
12520 /* Scan X for promoted SUBREGs.  For each one found,
12521    note what it implies to the registers used in it.  */
12522
12523 static void
12524 check_promoted_subreg (rtx insn, rtx x)
12525 {
12526   if (GET_CODE (x) == SUBREG
12527       && SUBREG_PROMOTED_VAR_P (x)
12528       && REG_P (SUBREG_REG (x)))
12529     record_promoted_value (insn, x);
12530   else
12531     {
12532       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12533       int i, j;
12534
12535       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12536         switch (format[i])
12537           {
12538           case 'e':
12539             check_promoted_subreg (insn, XEXP (x, i));
12540             break;
12541           case 'V':
12542           case 'E':
12543             if (XVEC (x, i) != 0)
12544               for (j = 0; j < XVECLEN (x, i); j++)
12545                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12546             break;
12547           }
12548     }
12549 }
12550 \f
12551 /* Verify that all the registers and memory references mentioned in *LOC are
12552    still valid.  *LOC was part of a value set in INSN when label_tick was
12553    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12554    the invalid references with (clobber (const_int 0)) and return 1.  This
12555    replacement is useful because we often can get useful information about
12556    the form of a value (e.g., if it was produced by a shift that always
12557    produces -1 or 0) even though we don't know exactly what registers it
12558    was produced from.  */
12559
12560 static int
12561 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12562 {
12563   rtx x = *loc;
12564   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12565   int len = GET_RTX_LENGTH (GET_CODE (x));
12566   int i, j;
12567
12568   if (REG_P (x))
12569     {
12570       unsigned int regno = REGNO (x);
12571       unsigned int endregno = END_REGNO (x);
12572       unsigned int j;
12573
12574       for (j = regno; j < endregno; j++)
12575         {
12576           reg_stat_type *rsp = &reg_stat[j];
12577           if (rsp->last_set_invalid
12578               /* If this is a pseudo-register that was only set once and not
12579                  live at the beginning of the function, it is always valid.  */
12580               || (! (regno >= FIRST_PSEUDO_REGISTER
12581                      && REG_N_SETS (regno) == 1
12582                      && (!REGNO_REG_SET_P
12583                          (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
12584                           regno)))
12585                   && rsp->last_set_label > tick))
12586           {
12587             if (replace)
12588               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12589             return replace;
12590           }
12591         }
12592
12593       return 1;
12594     }
12595   /* If this is a memory reference, make sure that there were no stores after
12596      it that might have clobbered the value.  We don't have alias info, so we
12597      assume any store invalidates it.  Moreover, we only have local UIDs, so
12598      we also assume that there were stores in the intervening basic blocks.  */
12599   else if (MEM_P (x) && !MEM_READONLY_P (x)
12600            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12601     {
12602       if (replace)
12603         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12604       return replace;
12605     }
12606
12607   for (i = 0; i < len; i++)
12608     {
12609       if (fmt[i] == 'e')
12610         {
12611           /* Check for identical subexpressions.  If x contains
12612              identical subexpression we only have to traverse one of
12613              them.  */
12614           if (i == 1 && ARITHMETIC_P (x))
12615             {
12616               /* Note that at this point x0 has already been checked
12617                  and found valid.  */
12618               rtx x0 = XEXP (x, 0);
12619               rtx x1 = XEXP (x, 1);
12620
12621               /* If x0 and x1 are identical then x is also valid.  */
12622               if (x0 == x1)
12623                 return 1;
12624
12625               /* If x1 is identical to a subexpression of x0 then
12626                  while checking x0, x1 has already been checked.  Thus
12627                  it is valid and so as x.  */
12628               if (ARITHMETIC_P (x0)
12629                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12630                 return 1;
12631
12632               /* If x0 is identical to a subexpression of x1 then x is
12633                  valid iff the rest of x1 is valid.  */
12634               if (ARITHMETIC_P (x1)
12635                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12636                 return
12637                   get_last_value_validate (&XEXP (x1,
12638                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12639                                            insn, tick, replace);
12640             }
12641
12642           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12643                                        replace) == 0)
12644             return 0;
12645         }
12646       else if (fmt[i] == 'E')
12647         for (j = 0; j < XVECLEN (x, i); j++)
12648           if (get_last_value_validate (&XVECEXP (x, i, j),
12649                                        insn, tick, replace) == 0)
12650             return 0;
12651     }
12652
12653   /* If we haven't found a reason for it to be invalid, it is valid.  */
12654   return 1;
12655 }
12656
12657 /* Get the last value assigned to X, if known.  Some registers
12658    in the value may be replaced with (clobber (const_int 0)) if their value
12659    is known longer known reliably.  */
12660
12661 static rtx
12662 get_last_value (const_rtx x)
12663 {
12664   unsigned int regno;
12665   rtx value;
12666   reg_stat_type *rsp;
12667
12668   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12669      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12670      we cannot predict what values the "extra" bits might have.  */
12671   if (GET_CODE (x) == SUBREG
12672       && subreg_lowpart_p (x)
12673       && !paradoxical_subreg_p (x)
12674       && (value = get_last_value (SUBREG_REG (x))) != 0)
12675     return gen_lowpart (GET_MODE (x), value);
12676
12677   if (!REG_P (x))
12678     return 0;
12679
12680   regno = REGNO (x);
12681   rsp = &reg_stat[regno];
12682   value = rsp->last_set_value;
12683
12684   /* If we don't have a value, or if it isn't for this basic block and
12685      it's either a hard register, set more than once, or it's a live
12686      at the beginning of the function, return 0.
12687
12688      Because if it's not live at the beginning of the function then the reg
12689      is always set before being used (is never used without being set).
12690      And, if it's set only once, and it's always set before use, then all
12691      uses must have the same last value, even if it's not from this basic
12692      block.  */
12693
12694   if (value == 0
12695       || (rsp->last_set_label < label_tick_ebb_start
12696           && (regno < FIRST_PSEUDO_REGISTER
12697               || REG_N_SETS (regno) != 1
12698               || REGNO_REG_SET_P
12699                  (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
12700     return 0;
12701
12702   /* If the value was set in a later insn than the ones we are processing,
12703      we can't use it even if the register was only set once.  */
12704   if (rsp->last_set_label == label_tick
12705       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12706     return 0;
12707
12708   /* If the value has all its registers valid, return it.  */
12709   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12710     return value;
12711
12712   /* Otherwise, make a copy and replace any invalid register with
12713      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12714
12715   value = copy_rtx (value);
12716   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12717     return value;
12718
12719   return 0;
12720 }
12721 \f
12722 /* Return nonzero if expression X refers to a REG or to memory
12723    that is set in an instruction more recent than FROM_LUID.  */
12724
12725 static int
12726 use_crosses_set_p (const_rtx x, int from_luid)
12727 {
12728   const char *fmt;
12729   int i;
12730   enum rtx_code code = GET_CODE (x);
12731
12732   if (code == REG)
12733     {
12734       unsigned int regno = REGNO (x);
12735       unsigned endreg = END_REGNO (x);
12736
12737 #ifdef PUSH_ROUNDING
12738       /* Don't allow uses of the stack pointer to be moved,
12739          because we don't know whether the move crosses a push insn.  */
12740       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12741         return 1;
12742 #endif
12743       for (; regno < endreg; regno++)
12744         {
12745           reg_stat_type *rsp = &reg_stat[regno];
12746           if (rsp->last_set
12747               && rsp->last_set_label == label_tick
12748               && DF_INSN_LUID (rsp->last_set) > from_luid)
12749             return 1;
12750         }
12751       return 0;
12752     }
12753
12754   if (code == MEM && mem_last_set > from_luid)
12755     return 1;
12756
12757   fmt = GET_RTX_FORMAT (code);
12758
12759   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12760     {
12761       if (fmt[i] == 'E')
12762         {
12763           int j;
12764           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12765             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12766               return 1;
12767         }
12768       else if (fmt[i] == 'e'
12769                && use_crosses_set_p (XEXP (x, i), from_luid))
12770         return 1;
12771     }
12772   return 0;
12773 }
12774 \f
12775 /* Define three variables used for communication between the following
12776    routines.  */
12777
12778 static unsigned int reg_dead_regno, reg_dead_endregno;
12779 static int reg_dead_flag;
12780
12781 /* Function called via note_stores from reg_dead_at_p.
12782
12783    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12784    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12785
12786 static void
12787 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12788 {
12789   unsigned int regno, endregno;
12790
12791   if (!REG_P (dest))
12792     return;
12793
12794   regno = REGNO (dest);
12795   endregno = END_REGNO (dest);
12796   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12797     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12798 }
12799
12800 /* Return nonzero if REG is known to be dead at INSN.
12801
12802    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12803    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12804    live.  Otherwise, see if it is live or dead at the start of the basic
12805    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12806    must be assumed to be always live.  */
12807
12808 static int
12809 reg_dead_at_p (rtx reg, rtx insn)
12810 {
12811   basic_block block;
12812   unsigned int i;
12813
12814   /* Set variables for reg_dead_at_p_1.  */
12815   reg_dead_regno = REGNO (reg);
12816   reg_dead_endregno = END_REGNO (reg);
12817
12818   reg_dead_flag = 0;
12819
12820   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12821      we allow the machine description to decide whether use-and-clobber
12822      patterns are OK.  */
12823   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12824     {
12825       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12826         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12827           return 0;
12828     }
12829
12830   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12831      beginning of basic block.  */
12832   block = BLOCK_FOR_INSN (insn);
12833   for (;;)
12834     {
12835       if (INSN_P (insn))
12836         {
12837           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12838           if (reg_dead_flag)
12839             return reg_dead_flag == 1 ? 1 : 0;
12840
12841           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12842             return 1;
12843         }
12844
12845       if (insn == BB_HEAD (block))
12846         break;
12847
12848       insn = PREV_INSN (insn);
12849     }
12850
12851   /* Look at live-in sets for the basic block that we were in.  */
12852   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12853     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12854       return 0;
12855
12856   return 1;
12857 }
12858 \f
12859 /* Note hard registers in X that are used.  */
12860
12861 static void
12862 mark_used_regs_combine (rtx x)
12863 {
12864   RTX_CODE code = GET_CODE (x);
12865   unsigned int regno;
12866   int i;
12867
12868   switch (code)
12869     {
12870     case LABEL_REF:
12871     case SYMBOL_REF:
12872     case CONST:
12873     CASE_CONST_ANY:
12874     case PC:
12875     case ADDR_VEC:
12876     case ADDR_DIFF_VEC:
12877     case ASM_INPUT:
12878 #ifdef HAVE_cc0
12879     /* CC0 must die in the insn after it is set, so we don't need to take
12880        special note of it here.  */
12881     case CC0:
12882 #endif
12883       return;
12884
12885     case CLOBBER:
12886       /* If we are clobbering a MEM, mark any hard registers inside the
12887          address as used.  */
12888       if (MEM_P (XEXP (x, 0)))
12889         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12890       return;
12891
12892     case REG:
12893       regno = REGNO (x);
12894       /* A hard reg in a wide mode may really be multiple registers.
12895          If so, mark all of them just like the first.  */
12896       if (regno < FIRST_PSEUDO_REGISTER)
12897         {
12898           /* None of this applies to the stack, frame or arg pointers.  */
12899           if (regno == STACK_POINTER_REGNUM
12900 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12901               || regno == HARD_FRAME_POINTER_REGNUM
12902 #endif
12903 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12904               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12905 #endif
12906               || regno == FRAME_POINTER_REGNUM)
12907             return;
12908
12909           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12910         }
12911       return;
12912
12913     case SET:
12914       {
12915         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12916            the address.  */
12917         rtx testreg = SET_DEST (x);
12918
12919         while (GET_CODE (testreg) == SUBREG
12920                || GET_CODE (testreg) == ZERO_EXTRACT
12921                || GET_CODE (testreg) == STRICT_LOW_PART)
12922           testreg = XEXP (testreg, 0);
12923
12924         if (MEM_P (testreg))
12925           mark_used_regs_combine (XEXP (testreg, 0));
12926
12927         mark_used_regs_combine (SET_SRC (x));
12928       }
12929       return;
12930
12931     default:
12932       break;
12933     }
12934
12935   /* Recursively scan the operands of this expression.  */
12936
12937   {
12938     const char *fmt = GET_RTX_FORMAT (code);
12939
12940     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12941       {
12942         if (fmt[i] == 'e')
12943           mark_used_regs_combine (XEXP (x, i));
12944         else if (fmt[i] == 'E')
12945           {
12946             int j;
12947
12948             for (j = 0; j < XVECLEN (x, i); j++)
12949               mark_used_regs_combine (XVECEXP (x, i, j));
12950           }
12951       }
12952   }
12953 }
12954 \f
12955 /* Remove register number REGNO from the dead registers list of INSN.
12956
12957    Return the note used to record the death, if there was one.  */
12958
12959 rtx
12960 remove_death (unsigned int regno, rtx insn)
12961 {
12962   rtx note = find_regno_note (insn, REG_DEAD, regno);
12963
12964   if (note)
12965     remove_note (insn, note);
12966
12967   return note;
12968 }
12969
12970 /* For each register (hardware or pseudo) used within expression X, if its
12971    death is in an instruction with luid between FROM_LUID (inclusive) and
12972    TO_INSN (exclusive), put a REG_DEAD note for that register in the
12973    list headed by PNOTES.
12974
12975    That said, don't move registers killed by maybe_kill_insn.
12976
12977    This is done when X is being merged by combination into TO_INSN.  These
12978    notes will then be distributed as needed.  */
12979
12980 static void
12981 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12982              rtx *pnotes)
12983 {
12984   const char *fmt;
12985   int len, i;
12986   enum rtx_code code = GET_CODE (x);
12987
12988   if (code == REG)
12989     {
12990       unsigned int regno = REGNO (x);
12991       rtx where_dead = reg_stat[regno].last_death;
12992
12993       /* Don't move the register if it gets killed in between from and to.  */
12994       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12995           && ! reg_referenced_p (x, maybe_kill_insn))
12996         return;
12997
12998       if (where_dead
12999           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13000           && DF_INSN_LUID (where_dead) >= from_luid
13001           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13002         {
13003           rtx note = remove_death (regno, where_dead);
13004
13005           /* It is possible for the call above to return 0.  This can occur
13006              when last_death points to I2 or I1 that we combined with.
13007              In that case make a new note.
13008
13009              We must also check for the case where X is a hard register
13010              and NOTE is a death note for a range of hard registers
13011              including X.  In that case, we must put REG_DEAD notes for
13012              the remaining registers in place of NOTE.  */
13013
13014           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13015               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13016                   > GET_MODE_SIZE (GET_MODE (x))))
13017             {
13018               unsigned int deadregno = REGNO (XEXP (note, 0));
13019               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13020               unsigned int ourend = END_HARD_REGNO (x);
13021               unsigned int i;
13022
13023               for (i = deadregno; i < deadend; i++)
13024                 if (i < regno || i >= ourend)
13025                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13026             }
13027
13028           /* If we didn't find any note, or if we found a REG_DEAD note that
13029              covers only part of the given reg, and we have a multi-reg hard
13030              register, then to be safe we must check for REG_DEAD notes
13031              for each register other than the first.  They could have
13032              their own REG_DEAD notes lying around.  */
13033           else if ((note == 0
13034                     || (note != 0
13035                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13036                             < GET_MODE_SIZE (GET_MODE (x)))))
13037                    && regno < FIRST_PSEUDO_REGISTER
13038                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13039             {
13040               unsigned int ourend = END_HARD_REGNO (x);
13041               unsigned int i, offset;
13042               rtx oldnotes = 0;
13043
13044               if (note)
13045                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13046               else
13047                 offset = 1;
13048
13049               for (i = regno + offset; i < ourend; i++)
13050                 move_deaths (regno_reg_rtx[i],
13051                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
13052             }
13053
13054           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13055             {
13056               XEXP (note, 1) = *pnotes;
13057               *pnotes = note;
13058             }
13059           else
13060             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13061         }
13062
13063       return;
13064     }
13065
13066   else if (GET_CODE (x) == SET)
13067     {
13068       rtx dest = SET_DEST (x);
13069
13070       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13071
13072       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13073          that accesses one word of a multi-word item, some
13074          piece of everything register in the expression is used by
13075          this insn, so remove any old death.  */
13076       /* ??? So why do we test for equality of the sizes?  */
13077
13078       if (GET_CODE (dest) == ZERO_EXTRACT
13079           || GET_CODE (dest) == STRICT_LOW_PART
13080           || (GET_CODE (dest) == SUBREG
13081               && (((GET_MODE_SIZE (GET_MODE (dest))
13082                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13083                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13084                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13085         {
13086           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13087           return;
13088         }
13089
13090       /* If this is some other SUBREG, we know it replaces the entire
13091          value, so use that as the destination.  */
13092       if (GET_CODE (dest) == SUBREG)
13093         dest = SUBREG_REG (dest);
13094
13095       /* If this is a MEM, adjust deaths of anything used in the address.
13096          For a REG (the only other possibility), the entire value is
13097          being replaced so the old value is not used in this insn.  */
13098
13099       if (MEM_P (dest))
13100         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13101                      to_insn, pnotes);
13102       return;
13103     }
13104
13105   else if (GET_CODE (x) == CLOBBER)
13106     return;
13107
13108   len = GET_RTX_LENGTH (code);
13109   fmt = GET_RTX_FORMAT (code);
13110
13111   for (i = 0; i < len; i++)
13112     {
13113       if (fmt[i] == 'E')
13114         {
13115           int j;
13116           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13117             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13118                          to_insn, pnotes);
13119         }
13120       else if (fmt[i] == 'e')
13121         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13122     }
13123 }
13124 \f
13125 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13126    pattern of an insn.  X must be a REG.  */
13127
13128 static int
13129 reg_bitfield_target_p (rtx x, rtx body)
13130 {
13131   int i;
13132
13133   if (GET_CODE (body) == SET)
13134     {
13135       rtx dest = SET_DEST (body);
13136       rtx target;
13137       unsigned int regno, tregno, endregno, endtregno;
13138
13139       if (GET_CODE (dest) == ZERO_EXTRACT)
13140         target = XEXP (dest, 0);
13141       else if (GET_CODE (dest) == STRICT_LOW_PART)
13142         target = SUBREG_REG (XEXP (dest, 0));
13143       else
13144         return 0;
13145
13146       if (GET_CODE (target) == SUBREG)
13147         target = SUBREG_REG (target);
13148
13149       if (!REG_P (target))
13150         return 0;
13151
13152       tregno = REGNO (target), regno = REGNO (x);
13153       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13154         return target == x;
13155
13156       endtregno = end_hard_regno (GET_MODE (target), tregno);
13157       endregno = end_hard_regno (GET_MODE (x), regno);
13158
13159       return endregno > tregno && regno < endtregno;
13160     }
13161
13162   else if (GET_CODE (body) == PARALLEL)
13163     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13164       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13165         return 1;
13166
13167   return 0;
13168 }
13169 \f
13170 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13171    as appropriate.  I3 and I2 are the insns resulting from the combination
13172    insns including FROM (I2 may be zero).
13173
13174    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13175    not need REG_DEAD notes because they are being substituted for.  This
13176    saves searching in the most common cases.
13177
13178    Each note in the list is either ignored or placed on some insns, depending
13179    on the type of note.  */
13180
13181 static void
13182 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13183                   rtx elim_i1, rtx elim_i0)
13184 {
13185   rtx note, next_note;
13186   rtx tem;
13187
13188   for (note = notes; note; note = next_note)
13189     {
13190       rtx place = 0, place2 = 0;
13191
13192       next_note = XEXP (note, 1);
13193       switch (REG_NOTE_KIND (note))
13194         {
13195         case REG_BR_PROB:
13196         case REG_BR_PRED:
13197           /* Doesn't matter much where we put this, as long as it's somewhere.
13198              It is preferable to keep these notes on branches, which is most
13199              likely to be i3.  */
13200           place = i3;
13201           break;
13202
13203         case REG_NON_LOCAL_GOTO:
13204           if (JUMP_P (i3))
13205             place = i3;
13206           else
13207             {
13208               gcc_assert (i2 && JUMP_P (i2));
13209               place = i2;
13210             }
13211           break;
13212
13213         case REG_EH_REGION:
13214           /* These notes must remain with the call or trapping instruction.  */
13215           if (CALL_P (i3))
13216             place = i3;
13217           else if (i2 && CALL_P (i2))
13218             place = i2;
13219           else
13220             {
13221               gcc_assert (cfun->can_throw_non_call_exceptions);
13222               if (may_trap_p (i3))
13223                 place = i3;
13224               else if (i2 && may_trap_p (i2))
13225                 place = i2;
13226               /* ??? Otherwise assume we've combined things such that we
13227                  can now prove that the instructions can't trap.  Drop the
13228                  note in this case.  */
13229             }
13230           break;
13231
13232         case REG_ARGS_SIZE:
13233           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13234              entire adjustment.  Assert i3 contains at least some adjust.  */
13235           if (!noop_move_p (i3))
13236             {
13237               int old_size, args_size = INTVAL (XEXP (note, 0));
13238               /* fixup_args_size_notes looks at REG_NORETURN note,
13239                  so ensure the note is placed there first.  */
13240               if (CALL_P (i3))
13241                 {
13242                   rtx *np;
13243                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13244                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13245                       {
13246                         rtx n = *np;
13247                         *np = XEXP (n, 1);
13248                         XEXP (n, 1) = REG_NOTES (i3);
13249                         REG_NOTES (i3) = n;
13250                         break;
13251                       }
13252                 }
13253               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13254               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13255                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13256               gcc_assert (old_size != args_size
13257                           || (CALL_P (i3)
13258                               && !ACCUMULATE_OUTGOING_ARGS
13259                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13260             }
13261           break;
13262
13263         case REG_NORETURN:
13264         case REG_SETJMP:
13265         case REG_TM:
13266         case REG_CALL_DECL:
13267           /* These notes must remain with the call.  It should not be
13268              possible for both I2 and I3 to be a call.  */
13269           if (CALL_P (i3))
13270             place = i3;
13271           else
13272             {
13273               gcc_assert (i2 && CALL_P (i2));
13274               place = i2;
13275             }
13276           break;
13277
13278         case REG_UNUSED:
13279           /* Any clobbers for i3 may still exist, and so we must process
13280              REG_UNUSED notes from that insn.
13281
13282              Any clobbers from i2 or i1 can only exist if they were added by
13283              recog_for_combine.  In that case, recog_for_combine created the
13284              necessary REG_UNUSED notes.  Trying to keep any original
13285              REG_UNUSED notes from these insns can cause incorrect output
13286              if it is for the same register as the original i3 dest.
13287              In that case, we will notice that the register is set in i3,
13288              and then add a REG_UNUSED note for the destination of i3, which
13289              is wrong.  However, it is possible to have REG_UNUSED notes from
13290              i2 or i1 for register which were both used and clobbered, so
13291              we keep notes from i2 or i1 if they will turn into REG_DEAD
13292              notes.  */
13293
13294           /* If this register is set or clobbered in I3, put the note there
13295              unless there is one already.  */
13296           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13297             {
13298               if (from_insn != i3)
13299                 break;
13300
13301               if (! (REG_P (XEXP (note, 0))
13302                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13303                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13304                 place = i3;
13305             }
13306           /* Otherwise, if this register is used by I3, then this register
13307              now dies here, so we must put a REG_DEAD note here unless there
13308              is one already.  */
13309           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13310                    && ! (REG_P (XEXP (note, 0))
13311                          ? find_regno_note (i3, REG_DEAD,
13312                                             REGNO (XEXP (note, 0)))
13313                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13314             {
13315               PUT_REG_NOTE_KIND (note, REG_DEAD);
13316               place = i3;
13317             }
13318           break;
13319
13320         case REG_EQUAL:
13321         case REG_EQUIV:
13322         case REG_NOALIAS:
13323           /* These notes say something about results of an insn.  We can
13324              only support them if they used to be on I3 in which case they
13325              remain on I3.  Otherwise they are ignored.
13326
13327              If the note refers to an expression that is not a constant, we
13328              must also ignore the note since we cannot tell whether the
13329              equivalence is still true.  It might be possible to do
13330              slightly better than this (we only have a problem if I2DEST
13331              or I1DEST is present in the expression), but it doesn't
13332              seem worth the trouble.  */
13333
13334           if (from_insn == i3
13335               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13336             place = i3;
13337           break;
13338
13339         case REG_INC:
13340           /* These notes say something about how a register is used.  They must
13341              be present on any use of the register in I2 or I3.  */
13342           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13343             place = i3;
13344
13345           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13346             {
13347               if (place)
13348                 place2 = i2;
13349               else
13350                 place = i2;
13351             }
13352           break;
13353
13354         case REG_LABEL_TARGET:
13355         case REG_LABEL_OPERAND:
13356           /* This can show up in several ways -- either directly in the
13357              pattern, or hidden off in the constant pool with (or without?)
13358              a REG_EQUAL note.  */
13359           /* ??? Ignore the without-reg_equal-note problem for now.  */
13360           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13361               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13362                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13363                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13364             place = i3;
13365
13366           if (i2
13367               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13368                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13369                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13370                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13371             {
13372               if (place)
13373                 place2 = i2;
13374               else
13375                 place = i2;
13376             }
13377
13378           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13379              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13380              there.  */
13381           if (place && JUMP_P (place)
13382               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13383               && (JUMP_LABEL (place) == NULL
13384                   || JUMP_LABEL (place) == XEXP (note, 0)))
13385             {
13386               rtx label = JUMP_LABEL (place);
13387
13388               if (!label)
13389                 JUMP_LABEL (place) = XEXP (note, 0);
13390               else if (LABEL_P (label))
13391                 LABEL_NUSES (label)--;
13392             }
13393
13394           if (place2 && JUMP_P (place2)
13395               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13396               && (JUMP_LABEL (place2) == NULL
13397                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13398             {
13399               rtx label = JUMP_LABEL (place2);
13400
13401               if (!label)
13402                 JUMP_LABEL (place2) = XEXP (note, 0);
13403               else if (LABEL_P (label))
13404                 LABEL_NUSES (label)--;
13405               place2 = 0;
13406             }
13407           break;
13408
13409         case REG_NONNEG:
13410           /* This note says something about the value of a register prior
13411              to the execution of an insn.  It is too much trouble to see
13412              if the note is still correct in all situations.  It is better
13413              to simply delete it.  */
13414           break;
13415
13416         case REG_DEAD:
13417           /* If we replaced the right hand side of FROM_INSN with a
13418              REG_EQUAL note, the original use of the dying register
13419              will not have been combined into I3 and I2.  In such cases,
13420              FROM_INSN is guaranteed to be the first of the combined
13421              instructions, so we simply need to search back before
13422              FROM_INSN for the previous use or set of this register,
13423              then alter the notes there appropriately.
13424
13425              If the register is used as an input in I3, it dies there.
13426              Similarly for I2, if it is nonzero and adjacent to I3.
13427
13428              If the register is not used as an input in either I3 or I2
13429              and it is not one of the registers we were supposed to eliminate,
13430              there are two possibilities.  We might have a non-adjacent I2
13431              or we might have somehow eliminated an additional register
13432              from a computation.  For example, we might have had A & B where
13433              we discover that B will always be zero.  In this case we will
13434              eliminate the reference to A.
13435
13436              In both cases, we must search to see if we can find a previous
13437              use of A and put the death note there.  */
13438
13439           if (from_insn
13440               && from_insn == i2mod
13441               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13442             tem = from_insn;
13443           else
13444             {
13445               if (from_insn
13446                   && CALL_P (from_insn)
13447                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13448                 place = from_insn;
13449               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13450                 place = i3;
13451               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13452                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13453                 place = i2;
13454               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13455                         && !(i2mod
13456                              && reg_overlap_mentioned_p (XEXP (note, 0),
13457                                                          i2mod_old_rhs)))
13458                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13459                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13460                 break;
13461               tem = i3;
13462             }
13463
13464           if (place == 0)
13465             {
13466               basic_block bb = this_basic_block;
13467
13468               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13469                 {
13470                   if (!NONDEBUG_INSN_P (tem))
13471                     {
13472                       if (tem == BB_HEAD (bb))
13473                         break;
13474                       continue;
13475                     }
13476
13477                   /* If the register is being set at TEM, see if that is all
13478                      TEM is doing.  If so, delete TEM.  Otherwise, make this
13479                      into a REG_UNUSED note instead. Don't delete sets to
13480                      global register vars.  */
13481                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13482                        || !global_regs[REGNO (XEXP (note, 0))])
13483                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13484                     {
13485                       rtx set = single_set (tem);
13486                       rtx inner_dest = 0;
13487 #ifdef HAVE_cc0
13488                       rtx cc0_setter = NULL_RTX;
13489 #endif
13490
13491                       if (set != 0)
13492                         for (inner_dest = SET_DEST (set);
13493                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13494                               || GET_CODE (inner_dest) == SUBREG
13495                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13496                              inner_dest = XEXP (inner_dest, 0))
13497                           ;
13498
13499                       /* Verify that it was the set, and not a clobber that
13500                          modified the register.
13501
13502                          CC0 targets must be careful to maintain setter/user
13503                          pairs.  If we cannot delete the setter due to side
13504                          effects, mark the user with an UNUSED note instead
13505                          of deleting it.  */
13506
13507                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13508                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13509 #ifdef HAVE_cc0
13510                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13511                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13512                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13513 #endif
13514                           )
13515                         {
13516                           /* Move the notes and links of TEM elsewhere.
13517                              This might delete other dead insns recursively.
13518                              First set the pattern to something that won't use
13519                              any register.  */
13520                           rtx old_notes = REG_NOTES (tem);
13521
13522                           PATTERN (tem) = pc_rtx;
13523                           REG_NOTES (tem) = NULL;
13524
13525                           distribute_notes (old_notes, tem, tem, NULL_RTX,
13526                                             NULL_RTX, NULL_RTX, NULL_RTX);
13527                           distribute_links (LOG_LINKS (tem));
13528
13529                           SET_INSN_DELETED (tem);
13530                           if (tem == i2)
13531                             i2 = NULL_RTX;
13532
13533 #ifdef HAVE_cc0
13534                           /* Delete the setter too.  */
13535                           if (cc0_setter)
13536                             {
13537                               PATTERN (cc0_setter) = pc_rtx;
13538                               old_notes = REG_NOTES (cc0_setter);
13539                               REG_NOTES (cc0_setter) = NULL;
13540
13541                               distribute_notes (old_notes, cc0_setter,
13542                                                 cc0_setter, NULL_RTX,
13543                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13544                               distribute_links (LOG_LINKS (cc0_setter));
13545
13546                               SET_INSN_DELETED (cc0_setter);
13547                               if (cc0_setter == i2)
13548                                 i2 = NULL_RTX;
13549                             }
13550 #endif
13551                         }
13552                       else
13553                         {
13554                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13555
13556                           /*  If there isn't already a REG_UNUSED note, put one
13557                               here.  Do not place a REG_DEAD note, even if
13558                               the register is also used here; that would not
13559                               match the algorithm used in lifetime analysis
13560                               and can cause the consistency check in the
13561                               scheduler to fail.  */
13562                           if (! find_regno_note (tem, REG_UNUSED,
13563                                                  REGNO (XEXP (note, 0))))
13564                             place = tem;
13565                           break;
13566                         }
13567                     }
13568                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13569                            || (CALL_P (tem)
13570                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
13571                     {
13572                       place = tem;
13573
13574                       /* If we are doing a 3->2 combination, and we have a
13575                          register which formerly died in i3 and was not used
13576                          by i2, which now no longer dies in i3 and is used in
13577                          i2 but does not die in i2, and place is between i2
13578                          and i3, then we may need to move a link from place to
13579                          i2.  */
13580                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13581                           && from_insn
13582                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13583                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13584                         {
13585                           struct insn_link *links = LOG_LINKS (place);
13586                           LOG_LINKS (place) = NULL;
13587                           distribute_links (links);
13588                         }
13589                       break;
13590                     }
13591
13592                   if (tem == BB_HEAD (bb))
13593                     break;
13594                 }
13595
13596             }
13597
13598           /* If the register is set or already dead at PLACE, we needn't do
13599              anything with this note if it is still a REG_DEAD note.
13600              We check here if it is set at all, not if is it totally replaced,
13601              which is what `dead_or_set_p' checks, so also check for it being
13602              set partially.  */
13603
13604           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13605             {
13606               unsigned int regno = REGNO (XEXP (note, 0));
13607               reg_stat_type *rsp = &reg_stat[regno];
13608
13609               if (dead_or_set_p (place, XEXP (note, 0))
13610                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13611                 {
13612                   /* Unless the register previously died in PLACE, clear
13613                      last_death.  [I no longer understand why this is
13614                      being done.] */
13615                   if (rsp->last_death != place)
13616                     rsp->last_death = 0;
13617                   place = 0;
13618                 }
13619               else
13620                 rsp->last_death = place;
13621
13622               /* If this is a death note for a hard reg that is occupying
13623                  multiple registers, ensure that we are still using all
13624                  parts of the object.  If we find a piece of the object
13625                  that is unused, we must arrange for an appropriate REG_DEAD
13626                  note to be added for it.  However, we can't just emit a USE
13627                  and tag the note to it, since the register might actually
13628                  be dead; so we recourse, and the recursive call then finds
13629                  the previous insn that used this register.  */
13630
13631               if (place && regno < FIRST_PSEUDO_REGISTER
13632                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13633                 {
13634                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13635                   bool all_used = true;
13636                   unsigned int i;
13637
13638                   for (i = regno; i < endregno; i++)
13639                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13640                          && ! find_regno_fusage (place, USE, i))
13641                         || dead_or_set_regno_p (place, i))
13642                       {
13643                         all_used = false;
13644                         break;
13645                       }
13646
13647                   if (! all_used)
13648                     {
13649                       /* Put only REG_DEAD notes for pieces that are
13650                          not already dead or set.  */
13651
13652                       for (i = regno; i < endregno;
13653                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13654                         {
13655                           rtx piece = regno_reg_rtx[i];
13656                           basic_block bb = this_basic_block;
13657
13658                           if (! dead_or_set_p (place, piece)
13659                               && ! reg_bitfield_target_p (piece,
13660                                                           PATTERN (place)))
13661                             {
13662                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13663                                                              NULL_RTX);
13664
13665                               distribute_notes (new_note, place, place,
13666                                                 NULL_RTX, NULL_RTX, NULL_RTX,
13667                                                 NULL_RTX);
13668                             }
13669                           else if (! refers_to_regno_p (i, i + 1,
13670                                                         PATTERN (place), 0)
13671                                    && ! find_regno_fusage (place, USE, i))
13672                             for (tem = PREV_INSN (place); ;
13673                                  tem = PREV_INSN (tem))
13674                               {
13675                                 if (!NONDEBUG_INSN_P (tem))
13676                                   {
13677                                     if (tem == BB_HEAD (bb))
13678                                       break;
13679                                     continue;
13680                                   }
13681                                 if (dead_or_set_p (tem, piece)
13682                                     || reg_bitfield_target_p (piece,
13683                                                               PATTERN (tem)))
13684                                   {
13685                                     add_reg_note (tem, REG_UNUSED, piece);
13686                                     break;
13687                                   }
13688                               }
13689                         }
13690
13691                       place = 0;
13692                     }
13693                 }
13694             }
13695           break;
13696
13697         default:
13698           /* Any other notes should not be present at this point in the
13699              compilation.  */
13700           gcc_unreachable ();
13701         }
13702
13703       if (place)
13704         {
13705           XEXP (note, 1) = REG_NOTES (place);
13706           REG_NOTES (place) = note;
13707         }
13708
13709       if (place2)
13710         add_shallow_copy_of_reg_note (place2, note);
13711     }
13712 }
13713 \f
13714 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13715    I3, I2, and I1 to new locations.  This is also called to add a link
13716    pointing at I3 when I3's destination is changed.  */
13717
13718 static void
13719 distribute_links (struct insn_link *links)
13720 {
13721   struct insn_link *link, *next_link;
13722
13723   for (link = links; link; link = next_link)
13724     {
13725       rtx place = 0;
13726       rtx insn;
13727       rtx set, reg;
13728
13729       next_link = link->next;
13730
13731       /* If the insn that this link points to is a NOTE or isn't a single
13732          set, ignore it.  In the latter case, it isn't clear what we
13733          can do other than ignore the link, since we can't tell which
13734          register it was for.  Such links wouldn't be used by combine
13735          anyway.
13736
13737          It is not possible for the destination of the target of the link to
13738          have been changed by combine.  The only potential of this is if we
13739          replace I3, I2, and I1 by I3 and I2.  But in that case the
13740          destination of I2 also remains unchanged.  */
13741
13742       if (NOTE_P (link->insn)
13743           || (set = single_set (link->insn)) == 0)
13744         continue;
13745
13746       reg = SET_DEST (set);
13747       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13748              || GET_CODE (reg) == STRICT_LOW_PART)
13749         reg = XEXP (reg, 0);
13750
13751       /* A LOG_LINK is defined as being placed on the first insn that uses
13752          a register and points to the insn that sets the register.  Start
13753          searching at the next insn after the target of the link and stop
13754          when we reach a set of the register or the end of the basic block.
13755
13756          Note that this correctly handles the link that used to point from
13757          I3 to I2.  Also note that not much searching is typically done here
13758          since most links don't point very far away.  */
13759
13760       for (insn = NEXT_INSN (link->insn);
13761            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
13762                      || BB_HEAD (this_basic_block->next_bb) != insn));
13763            insn = NEXT_INSN (insn))
13764         if (DEBUG_INSN_P (insn))
13765           continue;
13766         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13767           {
13768             if (reg_referenced_p (reg, PATTERN (insn)))
13769               place = insn;
13770             break;
13771           }
13772         else if (CALL_P (insn)
13773                  && find_reg_fusage (insn, USE, reg))
13774           {
13775             place = insn;
13776             break;
13777           }
13778         else if (INSN_P (insn) && reg_set_p (reg, insn))
13779           break;
13780
13781       /* If we found a place to put the link, place it there unless there
13782          is already a link to the same insn as LINK at that point.  */
13783
13784       if (place)
13785         {
13786           struct insn_link *link2;
13787
13788           FOR_EACH_LOG_LINK (link2, place)
13789             if (link2->insn == link->insn)
13790               break;
13791
13792           if (link2 == NULL)
13793             {
13794               link->next = LOG_LINKS (place);
13795               LOG_LINKS (place) = link;
13796
13797               /* Set added_links_insn to the earliest insn we added a
13798                  link to.  */
13799               if (added_links_insn == 0
13800                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13801                 added_links_insn = place;
13802             }
13803         }
13804     }
13805 }
13806 \f
13807 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13808    Check whether the expression pointer to by LOC is a register or
13809    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13810    Otherwise return zero.  */
13811
13812 static int
13813 unmentioned_reg_p_1 (rtx *loc, void *expr)
13814 {
13815   rtx x = *loc;
13816
13817   if (x != NULL_RTX
13818       && (REG_P (x) || MEM_P (x))
13819       && ! reg_mentioned_p (x, (rtx) expr))
13820     return 1;
13821   return 0;
13822 }
13823
13824 /* Check for any register or memory mentioned in EQUIV that is not
13825    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13826    of EXPR where some registers may have been replaced by constants.  */
13827
13828 static bool
13829 unmentioned_reg_p (rtx equiv, rtx expr)
13830 {
13831   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13832 }
13833 \f
13834 DEBUG_FUNCTION void
13835 dump_combine_stats (FILE *file)
13836 {
13837   fprintf
13838     (file,
13839      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13840      combine_attempts, combine_merges, combine_extras, combine_successes);
13841 }
13842
13843 void
13844 dump_combine_total_stats (FILE *file)
13845 {
13846   fprintf
13847     (file,
13848      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13849      total_attempts, total_merges, total_extras, total_successes);
13850 }
13851 \f
13852 /* Try combining insns through substitution.  */
13853 static unsigned int
13854 rest_of_handle_combine (void)
13855 {
13856   int rebuild_jump_labels_after_combine;
13857
13858   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13859   df_note_add_problem ();
13860   df_analyze ();
13861
13862   regstat_init_n_sets_and_refs ();
13863
13864   rebuild_jump_labels_after_combine
13865     = combine_instructions (get_insns (), max_reg_num ());
13866
13867   /* Combining insns may have turned an indirect jump into a
13868      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13869      instructions.  */
13870   if (rebuild_jump_labels_after_combine)
13871     {
13872       timevar_push (TV_JUMP);
13873       rebuild_jump_labels (get_insns ());
13874       cleanup_cfg (0);
13875       timevar_pop (TV_JUMP);
13876     }
13877
13878   regstat_free_n_sets_and_refs ();
13879   return 0;
13880 }
13881
13882 namespace {
13883
13884 const pass_data pass_data_combine =
13885 {
13886   RTL_PASS, /* type */
13887   "combine", /* name */
13888   OPTGROUP_NONE, /* optinfo_flags */
13889   true, /* has_execute */
13890   TV_COMBINE, /* tv_id */
13891   PROP_cfglayout, /* properties_required */
13892   0, /* properties_provided */
13893   0, /* properties_destroyed */
13894   0, /* todo_flags_start */
13895   TODO_df_finish, /* todo_flags_finish */
13896 };
13897
13898 class pass_combine : public rtl_opt_pass
13899 {
13900 public:
13901   pass_combine (gcc::context *ctxt)
13902     : rtl_opt_pass (pass_data_combine, ctxt)
13903   {}
13904
13905   /* opt_pass methods: */
13906   virtual bool gate (function *) { return (optimize > 0); }
13907   virtual unsigned int execute (function *)
13908     {
13909       return rest_of_handle_combine ();
13910     }
13911
13912 }; // class pass_combine
13913
13914 } // anon namespace
13915
13916 rtl_opt_pass *
13917 make_pass_combine (gcc::context *ctxt)
13918 {
13919   return new pass_combine (ctxt);
13920 }