?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
* config/i386/i386.h (ENCODE_SECTION_INFO): MODULE_LOCAL_P applies
[official-gcc.git] / gcc / config / i386 / i386.h
blobb83b22fe80610fa9decfef7109c5c7b9a583768e
1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
24
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
27
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
30
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
36
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
38
39 #ifndef HALF_PIC_P
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) (X)
48 #define HALF_PIC_FINISH(STREAM)
49 #endif
50
51 /* Define the specific costs for a given cpu */
52
53 struct processor_costs {
54 const int add; /* cost of an add instruction */
55 const int lea; /* cost of a lea instruction */
56 const int shift_var; /* variable shift costs */
57 const int shift_const; /* constant shift costs */
58 const int mult_init; /* cost of starting a multiply */
59 const int mult_bit; /* cost of multiply per each bit set */
60 const int divide; /* cost of a divide/mod */
61 int movsx; /* The cost of movsx operation. */
62 int movzx; /* The cost of movzx operation. */
63 const int large_insn; /* insns larger than this cost more */
64 const int move_ratio; /* The threshold of number of scalar
65 memory-to-memory move insns. */
66 const int movzbl_load; /* cost of loading using movzbl */
67 const int int_load[3]; /* cost of loading integer registers
68 in QImode, HImode and SImode relative
69 to reg-reg move (2). */
70 const int int_store[3]; /* cost of storing integer register
71 in QImode, HImode and SImode */
72 const int fp_move; /* cost of reg,reg fld/fst */
73 const int fp_load[3]; /* cost of loading FP register
74 in SFmode, DFmode and XFmode */
75 const int fp_store[3]; /* cost of storing FP register
76 in SFmode, DFmode and XFmode */
77 const int mmx_move; /* cost of moving MMX register. */
78 const int mmx_load[2]; /* cost of loading MMX register
79 in SImode and DImode */
80 const int mmx_store[2]; /* cost of storing MMX register
81 in SImode and DImode */
82 const int sse_move; /* cost of moving SSE register. */
83 const int sse_load[3]; /* cost of loading SSE register
84 in SImode, DImode and TImode*/
85 const int sse_store[3]; /* cost of storing SSE register
86 in SImode, DImode and TImode*/
87 const int mmxsse_to_integer; /* cost of moving mmxsse register to
88 integer and vice versa. */
89 const int prefetch_block; /* bytes moved to cache for prefetch. */
90 const int simultaneous_prefetches; /* number of parallel prefetch
91 operations. */
92 };
93
94 extern const struct processor_costs *ix86_cost;
95
96 /* Run-time compilation parameters selecting different hardware subsets. */
97
98 extern int target_flags;
99
100 /* Macros used in the machine description to test the flags. */
101
102 /* configure can arrange to make this 2, to force a 486. */
103
104 #ifndef TARGET_CPU_DEFAULT
105 #define TARGET_CPU_DEFAULT 0
106 #endif
107
108 /* Masks for the -m switches */
109 #define MASK_80387 0x00000001 /* Hardware floating point */
110 #define MASK_RTD 0x00000002 /* Use ret that pops args */
111 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
112 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
113 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
114 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
115 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
116 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
117 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
118 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
119 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
120 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
121 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
122 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
123 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
124 #define MASK_MMX_SET 0x00008000
125 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
126 #define MASK_SSE_SET 0x00020000
127 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
128 #define MASK_SSE2_SET 0x00080000
129 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
130 #define MASK_3DNOW_SET 0x00200000
131 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
132 #define MASK_3DNOW_A_SET 0x00800000
133 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
134 #define MASK_64BIT 0x02000000 /* Produce 64bit code */
135 /* ... overlap with subtarget options starts by 0x04000000. */
136 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
137
138 /* Use the floating point instructions */
139 #define TARGET_80387 (target_flags & MASK_80387)
140
141 /* Compile using ret insn that pops args.
142 This will not work unless you use prototypes at least
143 for all functions that can take varying numbers of args. */
144 #define TARGET_RTD (target_flags & MASK_RTD)
145
146 /* Align doubles to a two word boundary. This breaks compatibility with
147 the published ABI's for structures containing doubles, but produces
148 faster code on the pentium. */
149 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
150
151 /* Use push instructions to save outgoing args. */
152 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
153
154 /* Accumulate stack adjustments to prologue/epilogue. */
155 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
156 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
157
158 /* Put uninitialized locals into bss, not data.
159 Meaningful only on svr3. */
160 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
161
162 /* Use IEEE floating point comparisons. These handle correctly the cases
163 where the result of a comparison is unordered. Normally SIGFPE is
164 generated in such cases, in which case this isn't needed. */
165 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
166
167 /* Functions that return a floating point value may return that value
168 in the 387 FPU or in 386 integer registers. If set, this flag causes
169 the 387 to be used, which is compatible with most calling conventions. */
170 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
171
172 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
173 This mode wastes cache, but avoid misaligned data accesses and simplifies
174 address calculations. */
175 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
176
177 /* Disable generation of FP sin, cos and sqrt operations for 387.
178 This is because FreeBSD lacks these in the math-emulator-code */
179 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
180
181 /* Don't create frame pointers for leaf functions */
182 #define TARGET_OMIT_LEAF_FRAME_POINTER \
183 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
184
185 /* Debug GO_IF_LEGITIMATE_ADDRESS */
186 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
187
188 /* Debug FUNCTION_ARG macros */
189 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
190
191 /* 64bit Sledgehammer mode */
192 #ifdef TARGET_BI_ARCH
193 #define TARGET_64BIT (target_flags & MASK_64BIT)
194 #else
195 #ifdef TARGET_64BIT_DEFAULT
196 #define TARGET_64BIT 1
197 #else
198 #define TARGET_64BIT 0
199 #endif
200 #endif
201
202 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
203 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
204 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
205 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
206 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
207 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
208 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
209
210 #define CPUMASK (1 << ix86_cpu)
211 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
212 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
213 extern const int x86_branch_hints, x86_unroll_strlen;
214 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
215 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
216 extern const int x86_use_cltd, x86_read_modify_write;
217 extern const int x86_read_modify, x86_split_long_moves;
218 extern const int x86_promote_QImode, x86_single_stringop;
219 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
220 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
221 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
222 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
223 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
224 extern const int x86_epilogue_using_move, x86_decompose_lea;
225 extern int x86_prefetch_sse;
226
227 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
228 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
229 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
230 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
231 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
232 /* For sane SSE instruction set generation we need fcomi instruction. It is
233 safe to enable all CMOVE instructions. */
234 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
235 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
236 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
237 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
238 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
239 #define TARGET_MOVX (x86_movx & CPUMASK)
240 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
241 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
242 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
243 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
244 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
245 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
246 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
247 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
248 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
249 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
250 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
251 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
252 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
253 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
254 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
255 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
256 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
257 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
258 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
259 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
260 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
261 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
262 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
263 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
264 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
265
266 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
267
268 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
269 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
270
271 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
272
273 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
274 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
275 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
276 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
277 && (ix86_fpmath & FPMATH_387))
278 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
279 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
280 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
281
282 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
283
284 /* WARNING: Do not mark empty strings for translation, as calling
285 gettext on an empty string does NOT return an empty
286 string. */
287
288
289 #define TARGET_SWITCHES \
290 { { "80387", MASK_80387, N_("Use hardware fp") }, \
291 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
292 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
293 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
294 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
295 { "386", 0, "" /*Deprecated.*/}, \
296 { "486", 0, "" /*Deprecated.*/}, \
297 { "pentium", 0, "" /*Deprecated.*/}, \
298 { "pentiumpro", 0, "" /*Deprecated.*/}, \
299 { "intel-syntax", 0, "" /*Deprecated.*/}, \
300 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
301 { "rtd", MASK_RTD, \
302 N_("Alternate calling convention") }, \
303 { "no-rtd", -MASK_RTD, \
304 N_("Use normal calling convention") }, \
305 { "align-double", MASK_ALIGN_DOUBLE, \
306 N_("Align some doubles on dword boundary") }, \
307 { "no-align-double", -MASK_ALIGN_DOUBLE, \
308 N_("Align doubles on word boundary") }, \
309 { "svr3-shlib", MASK_SVR3_SHLIB, \
310 N_("Uninitialized locals in .bss") }, \
311 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
312 N_("Uninitialized locals in .data") }, \
313 { "ieee-fp", MASK_IEEE_FP, \
314 N_("Use IEEE math for fp comparisons") }, \
315 { "no-ieee-fp", -MASK_IEEE_FP, \
316 N_("Do not use IEEE math for fp comparisons") }, \
317 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
318 N_("Return values of functions in FPU registers") }, \
319 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
320 N_("Do not return values of functions in FPU registers")}, \
321 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
322 N_("Do not generate sin, cos, sqrt for FPU") }, \
323 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
324 N_("Generate sin, cos, sqrt for FPU")}, \
325 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
326 N_("Omit the frame pointer in leaf functions") }, \
327 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
328 { "stack-arg-probe", MASK_STACK_PROBE, \
329 N_("Enable stack probing") }, \
330 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
331 { "windows", 0, 0 /* undocumented */ }, \
332 { "dll", 0, 0 /* undocumented */ }, \
333 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
334 N_("Align destination of the string operations") }, \
335 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
336 N_("Do not align destination of the string operations") }, \
337 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
338 N_("Inline all known string operations") }, \
339 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
340 N_("Do not inline all known string operations") }, \
341 { "push-args", -MASK_NO_PUSH_ARGS, \
342 N_("Use push instructions to save outgoing arguments") }, \
343 { "no-push-args", MASK_NO_PUSH_ARGS, \
344 N_("Do not use push instructions to save outgoing arguments") }, \
345 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
346 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
347 N_("Use push instructions to save outgoing arguments") }, \
348 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
349 N_("Do not use push instructions to save outgoing arguments") }, \
350 { "mmx", MASK_MMX | MASK_MMX_SET, \
351 N_("Support MMX built-in functions") }, \
352 { "no-mmx", -MASK_MMX, \
353 N_("Do not support MMX built-in functions") }, \
354 { "no-mmx", MASK_MMX_SET, "" }, \
355 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
356 N_("Support 3DNow! built-in functions") }, \
357 { "no-3dnow", -MASK_3DNOW, "" }, \
358 { "no-3dnow", MASK_3DNOW_SET, \
359 N_("Do not support 3DNow! built-in functions") }, \
360 { "sse", MASK_SSE | MASK_SSE_SET, \
361 N_("Support MMX and SSE built-in functions and code generation") }, \
362 { "no-sse", -MASK_SSE, "" }, \
363 { "no-sse", MASK_SSE_SET, \
364 N_("Do not support MMX and SSE built-in functions and code generation") },\
365 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
366 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
367 { "no-sse2", -MASK_SSE2, "" }, \
368 { "no-sse2", MASK_SSE2_SET, \
369 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
370 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
371 N_("sizeof(long double) is 16") }, \
372 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
373 N_("sizeof(long double) is 12") }, \
374 { "64", MASK_64BIT, \
375 N_("Generate 64bit x86-64 code") }, \
376 { "32", -MASK_64BIT, \
377 N_("Generate 32bit i386 code") }, \
378 { "red-zone", -MASK_NO_RED_ZONE, \
379 N_("Use red-zone in the x86-64 code") }, \
380 { "no-red-zone", MASK_NO_RED_ZONE, \
381 N_("Do not use red-zone in the x86-64 code") }, \
382 SUBTARGET_SWITCHES \
383 { "", TARGET_DEFAULT, 0 }}
384
385 #ifdef TARGET_64BIT_DEFAULT
386 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
387 #else
388 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
389 #endif
390
391 /* Which processor to schedule for. The cpu attribute defines a list that
392 mirrors this list, so changes to i386.md must be made at the same time. */
393
394 enum processor_type
395 {
396 PROCESSOR_I386, /* 80386 */
397 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
398 PROCESSOR_PENTIUM,
399 PROCESSOR_PENTIUMPRO,
400 PROCESSOR_K6,
401 PROCESSOR_ATHLON,
402 PROCESSOR_PENTIUM4,
403 PROCESSOR_max
404 };
405 enum fpmath_unit
406 {
407 FPMATH_387 = 1,
408 FPMATH_SSE = 2
409 };
410
411 extern enum processor_type ix86_cpu;
412 extern enum fpmath_unit ix86_fpmath;
413
414 extern int ix86_arch;
415
416 /* This macro is similar to `TARGET_SWITCHES' but defines names of
417 command options that have values. Its definition is an
418 initializer with a subgrouping for each command option.
419
420 Each subgrouping contains a string constant, that defines the
421 fixed part of the option name, and the address of a variable. The
422 variable, type `char *', is set to the variable part of the given
423 option if the fixed part matches. The actual option name is made
424 by appending `-m' to the specified name. */
425 #define TARGET_OPTIONS \
426 { { "cpu=", &ix86_cpu_string, \
427 N_("Schedule code for given CPU")}, \
428 { "fpmath=", &ix86_fpmath_string, \
429 N_("Generate floating point mathematics using given instruction set")},\
430 { "arch=", &ix86_arch_string, \
431 N_("Generate code for given CPU")}, \
432 { "regparm=", &ix86_regparm_string, \
433 N_("Number of registers used to pass integer arguments") }, \
434 { "align-loops=", &ix86_align_loops_string, \
435 N_("Loop code aligned to this power of 2") }, \
436 { "align-jumps=", &ix86_align_jumps_string, \
437 N_("Jump targets are aligned to this power of 2") }, \
438 { "align-functions=", &ix86_align_funcs_string, \
439 N_("Function starts are aligned to this power of 2") }, \
440 { "preferred-stack-boundary=", \
441 &ix86_preferred_stack_boundary_string, \
442 N_("Attempt to keep stack aligned to this power of 2") }, \
443 { "branch-cost=", &ix86_branch_cost_string, \
444 N_("Branches are this expensive (1-5, arbitrary units)") }, \
445 { "cmodel=", &ix86_cmodel_string, \
446 N_("Use given x86-64 code model") }, \
447 { "debug-arg", &ix86_debug_arg_string, \
448 "" /* Undocumented. */ }, \
449 { "debug-addr", &ix86_debug_addr_string, \
450 "" /* Undocumented. */ }, \
451 { "asm=", &ix86_asm_string, \
452 N_("Use given assembler dialect") }, \
453 SUBTARGET_OPTIONS \
454 }
455
456 /* Sometimes certain combinations of command options do not make
457 sense on a particular target machine. You can define a macro
458 `OVERRIDE_OPTIONS' to take account of this. This macro, if
459 defined, is executed once just after all the command options have
460 been parsed.
461
462 Don't use this macro to turn on various extra optimizations for
463 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
464
465 #define OVERRIDE_OPTIONS override_options ()
466
467 /* These are meant to be redefined in the host dependent files */
468 #define SUBTARGET_SWITCHES
469 #define SUBTARGET_OPTIONS
470
471 /* Define this to change the optimizations performed by default. */
472 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
473 optimization_options ((LEVEL), (SIZE))
474
475 /* Specs for the compiler proper */
476
477 #ifndef CC1_CPU_SPEC
478 #define CC1_CPU_SPEC "\
479 %{!mcpu*: \
480 %{m386:-mcpu=i386 \
481 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
482 %{m486:-mcpu=i486 \
483 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
484 %{mpentium:-mcpu=pentium \
485 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
486 %{mpentiumpro:-mcpu=pentiumpro \
487 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
488 %{mintel-syntax:-masm=intel \
489 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
490 %{mno-intel-syntax:-masm=att \
491 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
492 #endif
493 \f
494 #define TARGET_CPU_DEFAULT_i386 0
495 #define TARGET_CPU_DEFAULT_i486 1
496 #define TARGET_CPU_DEFAULT_pentium 2
497 #define TARGET_CPU_DEFAULT_pentium_mmx 3
498 #define TARGET_CPU_DEFAULT_pentiumpro 4
499 #define TARGET_CPU_DEFAULT_pentium2 5
500 #define TARGET_CPU_DEFAULT_pentium3 6
501 #define TARGET_CPU_DEFAULT_pentium4 7
502 #define TARGET_CPU_DEFAULT_k6 8
503 #define TARGET_CPU_DEFAULT_k6_2 9
504 #define TARGET_CPU_DEFAULT_k6_3 10
505 #define TARGET_CPU_DEFAULT_athlon 11
506 #define TARGET_CPU_DEFAULT_athlon_sse 12
507
508 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
509 "pentiumpro", "pentium2", "pentium3", \
510 "pentium4", "k6", "k6-2", "k6-3",\
511 "athlon", "athlon-4"}
512 #ifndef CPP_CPU_DEFAULT_SPEC
513 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
514 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
515 #endif
516 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
517 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
518 #endif
519 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
520 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
521 #endif
522 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
523 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
524 #endif
525 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
526 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
527 -D__tune_pentium2__"
528 #endif
529 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
530 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
531 -D__tune_pentium2__ -D__tune_pentium3__"
532 #endif
533 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
534 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
535 #endif
536 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
537 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
538 #endif
539 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
540 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
541 #endif
542 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
543 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
544 #endif
545 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
546 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
547 #endif
548 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
549 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
550 #endif
551 #ifndef CPP_CPU_DEFAULT_SPEC
552 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
553 #endif
554 #endif /* CPP_CPU_DEFAULT_SPEC */
555
556 #ifdef TARGET_BI_ARCH
557 #define NO_BUILTIN_SIZE_TYPE
558 #define NO_BUILTIN_PTRDIFF_TYPE
559 #endif
560
561 #ifdef NO_BUILTIN_SIZE_TYPE
562 #define CPP_CPU32_SIZE_TYPE_SPEC \
563 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
564 #define CPP_CPU64_SIZE_TYPE_SPEC \
565 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int"
566 #else
567 #define CPP_CPU32_SIZE_TYPE_SPEC ""
568 #define CPP_CPU64_SIZE_TYPE_SPEC ""
569 #endif
570
571 #define CPP_CPU32_SPEC \
572 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
573 -D__i386__ %(cpp_cpu32sizet)"
574
575 #define CPP_CPU64_SPEC \
576 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)"
577
578 #define CPP_CPUCOMMON_SPEC "\
579 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
580 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
581 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
582 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
583 %{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
584 -D__pentium__mmx__ \
585 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
586 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
587 -D__pentiumpro -D__pentiumpro__ \
588 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
589 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
590 %{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
591 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
592 %{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
593 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
594 %{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
595 %{!mcpu*:-D__tune_athlon__ }}\
596 %{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
597 -D__athlon_sse__ \
598 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
599 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
600 %{m386|mcpu=i386:-D__tune_i386__ }\
601 %{m486|mcpu=i486:-D__tune_i486__ }\
602 %{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
603 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
604 -D__tune_pentiumpro__ }\
605 %{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
606 %{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
607 -D__tune_athlon__ }\
608 %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
609 -D__tune_athlon_sse__ }\
610 %{mcpu=pentium4:-D__tune_pentium4__ }\
611 %{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
612 -D__SSE__ }\
613 %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
614 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
615 |march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
616 %{march=k6-2|march=k6-3\
617 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
618 |march=athlon-mp: -D__3dNOW__ }\
619 %{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
620 |march=athlon-mp: -D__3dNOW_A__ }\
621 %{march=pentium4: -D__SSE2__ }\
622 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
623
624 #ifndef CPP_CPU_SPEC
625 #ifdef TARGET_BI_ARCH
626 #ifdef TARGET_64BIT_DEFAULT
627 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
628 #else
629 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
630 #endif
631 #else
632 #ifdef TARGET_64BIT_DEFAULT
633 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
634 #else
635 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
636 #endif
637 #endif
638 #endif
639
640 #ifndef CC1_SPEC
641 #define CC1_SPEC "%(cc1_cpu) "
642 #endif
643
644 /* This macro defines names of additional specifications to put in the
645 specs that can be used in various specifications like CC1_SPEC. Its
646 definition is an initializer with a subgrouping for each command option.
647
648 Each subgrouping contains a string constant, that defines the
649 specification name, and a string constant that used by the GNU CC driver
650 program.
651
652 Do not define this macro if it does not need to do anything. */
653
654 #ifndef SUBTARGET_EXTRA_SPECS
655 #define SUBTARGET_EXTRA_SPECS
656 #endif
657
658 #define EXTRA_SPECS \
659 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
660 { "cpp_cpu", CPP_CPU_SPEC }, \
661 { "cpp_cpu32", CPP_CPU32_SPEC }, \
662 { "cpp_cpu64", CPP_CPU64_SPEC }, \
663 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \
664 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \
665 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
666 { "cc1_cpu", CC1_CPU_SPEC }, \
667 SUBTARGET_EXTRA_SPECS
668 \f
669 /* target machine storage layout */
670
671 /* Define for XFmode or TFmode extended real floating point support.
672 This will automatically cause REAL_ARITHMETIC to be defined.
673
674 The XFmode is specified by i386 ABI, while TFmode may be faster
675 due to alignment and simplifications in the address calculations.
676 */
677 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
678 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
679 #ifdef __x86_64__
680 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
681 #else
682 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
683 #endif
684 /* Tell real.c that this is the 80-bit Intel extended float format
685 packaged in a 128-bit or 96bit entity. */
686 #define INTEL_EXTENDED_IEEE_FORMAT 1
687
688
689 #define SHORT_TYPE_SIZE 16
690 #define INT_TYPE_SIZE 32
691 #define FLOAT_TYPE_SIZE 32
692 #define LONG_TYPE_SIZE BITS_PER_WORD
693 #define MAX_WCHAR_TYPE_SIZE 32
694 #define DOUBLE_TYPE_SIZE 64
695 #define LONG_LONG_TYPE_SIZE 64
696
697 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
698 #define MAX_BITS_PER_WORD 64
699 #define MAX_LONG_TYPE_SIZE 64
700 #else
701 #define MAX_BITS_PER_WORD 32
702 #define MAX_LONG_TYPE_SIZE 32
703 #endif
704
705 /* Define if you don't want extended real, but do want to use the
706 software floating point emulator for REAL_ARITHMETIC and
707 decimal <-> binary conversion. */
708 /* #define REAL_ARITHMETIC */
709
710 /* Define this if most significant byte of a word is the lowest numbered. */
711 /* That is true on the 80386. */
712
713 #define BITS_BIG_ENDIAN 0
714
715 /* Define this if most significant byte of a word is the lowest numbered. */
716 /* That is not true on the 80386. */
717 #define BYTES_BIG_ENDIAN 0
718
719 /* Define this if most significant word of a multiword number is the lowest
720 numbered. */
721 /* Not true for 80386 */
722 #define WORDS_BIG_ENDIAN 0
723
724 /* Width in bits of a "word", which is the contents of a machine register.
725 Note that this is not necessarily the width of data type `int';
726 if using 16-bit ints on a 80386, this would still be 32.
727 But on a machine with 16-bit registers, this would be 16. */
728 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
729
730 /* Width of a word, in units (bytes). */
731 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
732 #define MIN_UNITS_PER_WORD 4
733
734 /* Width in bits of a pointer.
735 See also the macro `Pmode' defined below. */
736 #define POINTER_SIZE BITS_PER_WORD
737
738 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
739 #define PARM_BOUNDARY BITS_PER_WORD
740
741 /* Boundary (in *bits*) on which stack pointer should be aligned. */
742 #define STACK_BOUNDARY BITS_PER_WORD
743
744 /* Boundary (in *bits*) on which the stack pointer preferrs to be
745 aligned; the compiler cannot rely on having this alignment. */
746 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
747
748 /* As of July 2001, many runtimes to not align the stack properly when
749 entering main. This causes expand_main_function to forcably align
750 the stack, which results in aligned frames for functions called from
751 main, though it does nothing for the alignment of main itself. */
752 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
753 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
754
755 /* Allocation boundary for the code of a function. */
756 #define FUNCTION_BOUNDARY 16
757
758 /* Alignment of field after `int : 0' in a structure. */
759
760 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
761
762 /* Minimum size in bits of the largest boundary to which any
763 and all fundamental data types supported by the hardware
764 might need to be aligned. No data type wants to be aligned
765 rounder than this.
766
767 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
768 and Pentium Pro XFmode values at 128 bit boundaries. */
769
770 #define BIGGEST_ALIGNMENT 128
771
772 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
773 #define ALIGN_MODE_128(MODE) \
774 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
775 || (MODE) == V4SFmode || (MODE) == V4SImode)
776
777 /* The published ABIs say that doubles should be aligned on word
778 boundaries, so lower the aligment for structure fields unless
779 -malign-double is set. */
780 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
781 constant. Use the smaller value in that context. */
782 #ifndef IN_TARGET_LIBS
783 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
784 #else
785 #define BIGGEST_FIELD_ALIGNMENT 32
786 #endif
787
788 /* If defined, a C expression to compute the alignment given to a
789 constant that is being placed in memory. EXP is the constant
790 and ALIGN is the alignment that the object would ordinarily have.
791 The value of this macro is used instead of that alignment to align
792 the object.
793
794 If this macro is not defined, then ALIGN is used.
795
796 The typical use of this macro is to increase alignment for string
797 constants to be word aligned so that `strcpy' calls that copy
798 constants can be done inline. */
799
800 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
801
802 /* If defined, a C expression to compute the alignment for a static
803 variable. TYPE is the data type, and ALIGN is the alignment that
804 the object would ordinarily have. The value of this macro is used
805 instead of that alignment to align the object.
806
807 If this macro is not defined, then ALIGN is used.
808
809 One use of this macro is to increase alignment of medium-size
810 data to make it all fit in fewer cache lines. Another is to
811 cause character arrays to be word-aligned so that `strcpy' calls
812 that copy constants to character arrays can be done inline. */
813
814 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
815
816 /* If defined, a C expression to compute the alignment for a local
817 variable. TYPE is the data type, and ALIGN is the alignment that
818 the object would ordinarily have. The value of this macro is used
819 instead of that alignment to align the object.
820
821 If this macro is not defined, then ALIGN is used.
822
823 One use of this macro is to increase alignment of medium-size
824 data to make it all fit in fewer cache lines. */
825
826 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
827
828 /* If defined, a C expression that gives the alignment boundary, in
829 bits, of an argument with the specified mode and type. If it is
830 not defined, `PARM_BOUNDARY' is used for all arguments. */
831
832 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
833 ix86_function_arg_boundary ((MODE), (TYPE))
834
835 /* Set this non-zero if move instructions will actually fail to work
836 when given unaligned data. */
837 #define STRICT_ALIGNMENT 0
838
839 /* If bit field type is int, don't let it cross an int,
840 and give entire struct the alignment of an int. */
841 /* Required on the 386 since it doesn't have bitfield insns. */
842 #define PCC_BITFIELD_TYPE_MATTERS 1
843 \f
844 /* Standard register usage. */
845
846 /* This processor has special stack-like registers. See reg-stack.c
847 for details. */
848
849 #define STACK_REGS
850 #define IS_STACK_MODE(MODE) \
851 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
852 || (MODE) == TFmode)
853
854 /* Number of actual hardware registers.
855 The hardware registers are assigned numbers for the compiler
856 from 0 to just below FIRST_PSEUDO_REGISTER.
857 All registers that the compiler knows about must be given numbers,
858 even those that are not normally considered general registers.
859
860 In the 80386 we give the 8 general purpose registers the numbers 0-7.
861 We number the floating point registers 8-15.
862 Note that registers 0-7 can be accessed as a short or int,
863 while only 0-3 may be used with byte `mov' instructions.
864
865 Reg 16 does not correspond to any hardware register, but instead
866 appears in the RTL as an argument pointer prior to reload, and is
867 eliminated during reloading in favor of either the stack or frame
868 pointer. */
869
870 #define FIRST_PSEUDO_REGISTER 53
871
872 /* Number of hardware registers that go into the DWARF-2 unwind info.
873 If not defined, equals FIRST_PSEUDO_REGISTER. */
874
875 #define DWARF_FRAME_REGISTERS 17
876
877 /* 1 for registers that have pervasive standard uses
878 and are not available for the register allocator.
879 On the 80386, the stack pointer is such, as is the arg pointer.
880
881 The value is an mask - bit 1 is set for fixed registers
882 for 32bit target, while 2 is set for fixed registers for 64bit.
883 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
884 */
885 #define FIXED_REGISTERS \
886 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
887 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
888 /*arg,flags,fpsr,dir,frame*/ \
889 3, 3, 3, 3, 3, \
890 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
891 0, 0, 0, 0, 0, 0, 0, 0, \
892 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
893 0, 0, 0, 0, 0, 0, 0, 0, \
894 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
895 1, 1, 1, 1, 1, 1, 1, 1, \
896 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
897 1, 1, 1, 1, 1, 1, 1, 1}
898
899
900 /* 1 for registers not available across function calls.
901 These must include the FIXED_REGISTERS and also any
902 registers that can be used without being saved.
903 The latter must include the registers where values are returned
904 and the register where structure-value addresses are passed.
905 Aside from that, you can include as many other registers as you like.
906
907 The value is an mask - bit 1 is set for call used
908 for 32bit target, while 2 is set for call used for 64bit.
909 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
910 */
911 #define CALL_USED_REGISTERS \
912 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
913 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
914 /*arg,flags,fpsr,dir,frame*/ \
915 3, 3, 3, 3, 3, \
916 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
917 3, 3, 3, 3, 3, 3, 3, 3, \
918 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
919 3, 3, 3, 3, 3, 3, 3, 3, \
920 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
921 3, 3, 3, 3, 1, 1, 1, 1, \
922 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
923 3, 3, 3, 3, 3, 3, 3, 3} \
924
925 /* Order in which to allocate registers. Each register must be
926 listed once, even those in FIXED_REGISTERS. List frame pointer
927 late and fixed registers last. Note that, in general, we prefer
928 registers listed in CALL_USED_REGISTERS, keeping the others
929 available for storage of persistent values.
930
931 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
932 so this is just empty initializer for array. */
933
934 #define REG_ALLOC_ORDER \
935 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
936 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
937 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
938 48, 49, 50, 51, 52 }
939
940 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
941 to be rearranged based on a particular function. When using sse math,
942 we want to allocase SSE before x87 registers and vice vera. */
943
944 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
945
946
947 /* Macro to conditionally modify fixed_regs/call_used_regs. */
948 #define CONDITIONAL_REGISTER_USAGE \
949 do { \
950 int i; \
951 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
952 { \
953 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
954 call_used_regs[i] = (call_used_regs[i] \
955 & (TARGET_64BIT ? 2 : 1)) != 0; \
956 } \
957 if (flag_pic && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
958 { \
959 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
960 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
961 } \
962 if (! TARGET_MMX) \
963 { \
964 int i; \
965 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
966 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
967 fixed_regs[i] = call_used_regs[i] = 1; \
968 } \
969 if (! TARGET_SSE) \
970 { \
971 int i; \
972 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
973 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
974 fixed_regs[i] = call_used_regs[i] = 1; \
975 } \
976 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
977 { \
978 int i; \
979 HARD_REG_SET x; \
980 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
981 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
982 if (TEST_HARD_REG_BIT (x, i)) \
983 fixed_regs[i] = call_used_regs[i] = 1; \
984 } \
985 } while (0)
986
987 /* Return number of consecutive hard regs needed starting at reg REGNO
988 to hold something of mode MODE.
989 This is ordinarily the length in words of a value of mode MODE
990 but can be less for certain modes in special long registers.
991
992 Actually there are no two word move instructions for consecutive
993 registers. And only registers 0-3 may have mov byte instructions
994 applied to them.
995 */
996
997 #define HARD_REGNO_NREGS(REGNO, MODE) \
998 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
999 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1000 : ((MODE) == TFmode \
1001 ? (TARGET_64BIT ? 2 : 3) \
1002 : (MODE) == TCmode \
1003 ? (TARGET_64BIT ? 4 : 6) \
1004 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1005
1006 #define VALID_SSE_REG_MODE(MODE) \
1007 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1008 || (MODE) == SFmode \
1009 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
1010
1011 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1012 ((MODE) == V2SFmode || (MODE) == SFmode)
1013
1014 #define VALID_MMX_REG_MODE(MODE) \
1015 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1016 || (MODE) == V2SImode || (MODE) == SImode)
1017
1018 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1019 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
1020 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
1021 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1022
1023 #define VALID_FP_MODE_P(MODE) \
1024 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
1025 || (!TARGET_64BIT && (MODE) == XFmode) \
1026 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
1027 || (!TARGET_64BIT && (MODE) == XCmode))
1028
1029 #define VALID_INT_MODE_P(MODE) \
1030 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1031 || (MODE) == DImode \
1032 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1033 || (MODE) == CDImode \
1034 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
1035
1036 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1037
1038 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1039 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1040
1041 /* Value is 1 if it is a good idea to tie two pseudo registers
1042 when one has mode MODE1 and one has mode MODE2.
1043 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1044 for any hard reg, then this must be 0 for correct output. */
1045
1046 #define MODES_TIEABLE_P(MODE1, MODE2) \
1047 ((MODE1) == (MODE2) \
1048 || (((MODE1) == HImode || (MODE1) == SImode \
1049 || ((MODE1) == QImode \
1050 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1051 || ((MODE1) == DImode && TARGET_64BIT)) \
1052 && ((MODE2) == HImode || (MODE2) == SImode \
1053 || ((MODE1) == QImode \
1054 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1055 || ((MODE2) == DImode && TARGET_64BIT))))
1056
1057
1058 /* Specify the modes required to caller save a given hard regno.
1059 We do this on i386 to prevent flags from being saved at all.
1060
1061 Kill any attempts to combine saving of modes. */
1062
1063 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1064 (CC_REGNO_P (REGNO) ? VOIDmode \
1065 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1066 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1067 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1068 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1069 : (MODE))
1070 /* Specify the registers used for certain standard purposes.
1071 The values of these macros are register numbers. */
1072
1073 /* on the 386 the pc register is %eip, and is not usable as a general
1074 register. The ordinary mov instructions won't work */
1075 /* #define PC_REGNUM */
1076
1077 /* Register to use for pushing function arguments. */
1078 #define STACK_POINTER_REGNUM 7
1079
1080 /* Base register for access to local variables of the function. */
1081 #define HARD_FRAME_POINTER_REGNUM 6
1082
1083 /* Base register for access to local variables of the function. */
1084 #define FRAME_POINTER_REGNUM 20
1085
1086 /* First floating point reg */
1087 #define FIRST_FLOAT_REG 8
1088
1089 /* First & last stack-like regs */
1090 #define FIRST_STACK_REG FIRST_FLOAT_REG
1091 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1092
1093 #define FLAGS_REG 17
1094 #define FPSR_REG 18
1095 #define DIRFLAG_REG 19
1096
1097 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1098 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1099
1100 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1101 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1102
1103 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1104 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1105
1106 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1107 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1108
1109 /* Value should be nonzero if functions must have frame pointers.
1110 Zero means the frame pointer need not be set up (and parms
1111 may be accessed via the stack pointer) in functions that seem suitable.
1112 This is computed in `reload', in reload1.c. */
1113 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1114
1115 /* Override this in other tm.h files to cope with various OS losage
1116 requiring a frame pointer. */
1117 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1118 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1119 #endif
1120
1121 /* Make sure we can access arbitrary call frames. */
1122 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1123
1124 /* Base register for access to arguments of the function. */
1125 #define ARG_POINTER_REGNUM 16
1126
1127 /* Register in which static-chain is passed to a function.
1128 We do use ECX as static chain register for 32 bit ABI. On the
1129 64bit ABI, ECX is an argument register, so we use R10 instead. */
1130 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1131
1132 /* Register to hold the addressing base for position independent
1133 code access to data items.
1134 We don't use PIC pointer for 64bit mode. Define the regnum to
1135 dummy value to prevent gcc from pessimizing code dealing with EBX.
1136 */
1137 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
1138
1139 /* Register in which address to store a structure value
1140 arrives in the function. On the 386, the prologue
1141 copies this from the stack to register %eax. */
1142 #define STRUCT_VALUE_INCOMING 0
1143
1144 /* Place in which caller passes the structure value address.
1145 0 means push the value on the stack like an argument. */
1146 #define STRUCT_VALUE 0
1147
1148 /* A C expression which can inhibit the returning of certain function
1149 values in registers, based on the type of value. A nonzero value
1150 says to return the function value in memory, just as large
1151 structures are always returned. Here TYPE will be a C expression
1152 of type `tree', representing the data type of the value.
1153
1154 Note that values of mode `BLKmode' must be explicitly handled by
1155 this macro. Also, the option `-fpcc-struct-return' takes effect
1156 regardless of this macro. On most systems, it is possible to
1157 leave the macro undefined; this causes a default definition to be
1158 used, whose value is the constant 1 for `BLKmode' values, and 0
1159 otherwise.
1160
1161 Do not use this macro to indicate that structures and unions
1162 should always be returned in memory. You should instead use
1163 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1164
1165 #define RETURN_IN_MEMORY(TYPE) \
1166 ix86_return_in_memory (TYPE)
1167
1168 \f
1169 /* Define the classes of registers for register constraints in the
1170 machine description. Also define ranges of constants.
1171
1172 One of the classes must always be named ALL_REGS and include all hard regs.
1173 If there is more than one class, another class must be named NO_REGS
1174 and contain no registers.
1175
1176 The name GENERAL_REGS must be the name of a class (or an alias for
1177 another name such as ALL_REGS). This is the class of registers
1178 that is allowed by "g" or "r" in a register constraint.
1179 Also, registers outside this class are allocated only when
1180 instructions express preferences for them.
1181
1182 The classes must be numbered in nondecreasing order; that is,
1183 a larger-numbered class must never be contained completely
1184 in a smaller-numbered class.
1185
1186 For any two classes, it is very desirable that there be another
1187 class that represents their union.
1188
1189 It might seem that class BREG is unnecessary, since no useful 386
1190 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1191 and the "b" register constraint is useful in asms for syscalls.
1192
1193 The flags and fpsr registers are in no class. */
1194
1195 enum reg_class
1196 {
1197 NO_REGS,
1198 AREG, DREG, CREG, BREG, SIREG, DIREG,
1199 AD_REGS, /* %eax/%edx for DImode */
1200 Q_REGS, /* %eax %ebx %ecx %edx */
1201 NON_Q_REGS, /* %esi %edi %ebp %esp */
1202 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1203 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1204 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1205 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1206 FLOAT_REGS,
1207 SSE_REGS,
1208 MMX_REGS,
1209 FP_TOP_SSE_REGS,
1210 FP_SECOND_SSE_REGS,
1211 FLOAT_SSE_REGS,
1212 FLOAT_INT_REGS,
1213 INT_SSE_REGS,
1214 FLOAT_INT_SSE_REGS,
1215 ALL_REGS, LIM_REG_CLASSES
1216 };
1217
1218 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1219
1220 #define INTEGER_CLASS_P(CLASS) \
1221 reg_class_subset_p ((CLASS), GENERAL_REGS)
1222 #define FLOAT_CLASS_P(CLASS) \
1223 reg_class_subset_p ((CLASS), FLOAT_REGS)
1224 #define SSE_CLASS_P(CLASS) \
1225 reg_class_subset_p ((CLASS), SSE_REGS)
1226 #define MMX_CLASS_P(CLASS) \
1227 reg_class_subset_p ((CLASS), MMX_REGS)
1228 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1229 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1230 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1231 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1232 #define MAYBE_SSE_CLASS_P(CLASS) \
1233 reg_classes_intersect_p (SSE_REGS, (CLASS))
1234 #define MAYBE_MMX_CLASS_P(CLASS) \
1235 reg_classes_intersect_p (MMX_REGS, (CLASS))
1236
1237 #define Q_CLASS_P(CLASS) \
1238 reg_class_subset_p ((CLASS), Q_REGS)
1239
1240 /* Give names of register classes as strings for dump file. */
1241
1242 #define REG_CLASS_NAMES \
1243 { "NO_REGS", \
1244 "AREG", "DREG", "CREG", "BREG", \
1245 "SIREG", "DIREG", \
1246 "AD_REGS", \
1247 "Q_REGS", "NON_Q_REGS", \
1248 "INDEX_REGS", \
1249 "LEGACY_REGS", \
1250 "GENERAL_REGS", \
1251 "FP_TOP_REG", "FP_SECOND_REG", \
1252 "FLOAT_REGS", \
1253 "SSE_REGS", \
1254 "MMX_REGS", \
1255 "FP_TOP_SSE_REGS", \
1256 "FP_SECOND_SSE_REGS", \
1257 "FLOAT_SSE_REGS", \
1258 "FLOAT_INT_REGS", \
1259 "INT_SSE_REGS", \
1260 "FLOAT_INT_SSE_REGS", \
1261 "ALL_REGS" }
1262
1263 /* Define which registers fit in which classes.
1264 This is an initializer for a vector of HARD_REG_SET
1265 of length N_REG_CLASSES. */
1266
1267 #define REG_CLASS_CONTENTS \
1268 { { 0x00, 0x0 }, \
1269 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1270 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1271 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1272 { 0x03, 0x0 }, /* AD_REGS */ \
1273 { 0x0f, 0x0 }, /* Q_REGS */ \
1274 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1275 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1276 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1277 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1278 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1279 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1280 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1281 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1282 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1283 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1284 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1285 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1286 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1287 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1288 { 0xffffffff,0x1fffff } \
1289 }
1290
1291 /* The same information, inverted:
1292 Return the class number of the smallest class containing
1293 reg number REGNO. This could be a conditional expression
1294 or could index an array. */
1295
1296 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1297
1298 /* When defined, the compiler allows registers explicitly used in the
1299 rtl to be used as spill registers but prevents the compiler from
1300 extending the lifetime of these registers. */
1301
1302 #define SMALL_REGISTER_CLASSES 1
1303
1304 #define QI_REG_P(X) \
1305 (REG_P (X) && REGNO (X) < 4)
1306
1307 #define GENERAL_REGNO_P(N) \
1308 ((N) < 8 || REX_INT_REGNO_P (N))
1309
1310 #define GENERAL_REG_P(X) \
1311 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1312
1313 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1314
1315 #define NON_QI_REG_P(X) \
1316 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1317
1318 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1319 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1320
1321 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1322 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1323 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1324 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1325
1326 #define SSE_REGNO_P(N) \
1327 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1328 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1329
1330 #define SSE_REGNO(N) \
1331 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1332 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1333
1334 #define SSE_FLOAT_MODE_P(MODE) \
1335 ((TARGET_SSE_MATH && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1336
1337 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1338 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1339
1340 #define STACK_REG_P(XOP) \
1341 (REG_P (XOP) && \
1342 REGNO (XOP) >= FIRST_STACK_REG && \
1343 REGNO (XOP) <= LAST_STACK_REG)
1344
1345 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1346
1347 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1348
1349 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1350 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1351
1352 /* Indicate whether hard register numbered REG_NO should be converted
1353 to SSA form. */
1354 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1355 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1356
1357 /* The class value for index registers, and the one for base regs. */
1358
1359 #define INDEX_REG_CLASS INDEX_REGS
1360 #define BASE_REG_CLASS GENERAL_REGS
1361
1362 /* Get reg_class from a letter such as appears in the machine description. */
1363
1364 #define REG_CLASS_FROM_LETTER(C) \
1365 ((C) == 'r' ? GENERAL_REGS : \
1366 (C) == 'R' ? LEGACY_REGS : \
1367 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1368 (C) == 'Q' ? Q_REGS : \
1369 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1370 ? FLOAT_REGS \
1371 : NO_REGS) : \
1372 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1373 ? FP_TOP_REG \
1374 : NO_REGS) : \
1375 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1376 ? FP_SECOND_REG \
1377 : NO_REGS) : \
1378 (C) == 'a' ? AREG : \
1379 (C) == 'b' ? BREG : \
1380 (C) == 'c' ? CREG : \
1381 (C) == 'd' ? DREG : \
1382 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1383 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1384 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1385 (C) == 'A' ? AD_REGS : \
1386 (C) == 'D' ? DIREG : \
1387 (C) == 'S' ? SIREG : NO_REGS)
1388
1389 /* The letters I, J, K, L and M in a register constraint string
1390 can be used to stand for particular ranges of immediate operands.
1391 This macro defines what the ranges are.
1392 C is the letter, and VALUE is a constant value.
1393 Return 1 if VALUE is in the range specified by C.
1394
1395 I is for non-DImode shifts.
1396 J is for DImode shifts.
1397 K is for signed imm8 operands.
1398 L is for andsi as zero-extending move.
1399 M is for shifts that can be executed by the "lea" opcode.
1400 N is for immedaite operands for out/in instructions (0-255)
1401 */
1402
1403 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1404 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1405 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1406 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1407 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1408 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1409 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1410 : 0)
1411
1412 /* Similar, but for floating constants, and defining letters G and H.
1413 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1414 TARGET_387 isn't set, because the stack register converter may need to
1415 load 0.0 into the function value register. */
1416
1417 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1418 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1419 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1420
1421 /* A C expression that defines the optional machine-dependent
1422 constraint letters that can be used to segregate specific types of
1423 operands, usually memory references, for the target machine. Any
1424 letter that is not elsewhere defined and not matched by
1425 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1426 be defined.
1427
1428 If it is required for a particular target machine, it should
1429 return 1 if VALUE corresponds to the operand type represented by
1430 the constraint letter C. If C is not defined as an extra
1431 constraint, the value returned should be 0 regardless of VALUE. */
1432
1433 #define EXTRA_CONSTRAINT(VALUE, C) \
1434 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1435 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1436 : 0)
1437
1438 /* Place additional restrictions on the register class to use when it
1439 is necessary to be able to hold a value of mode MODE in a reload
1440 register for which class CLASS would ordinarily be used. */
1441
1442 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1443 ((MODE) == QImode && !TARGET_64BIT \
1444 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1445 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1446 ? Q_REGS : (CLASS))
1447
1448 /* Given an rtx X being reloaded into a reg required to be
1449 in class CLASS, return the class of reg to actually use.
1450 In general this is just CLASS; but on some machines
1451 in some cases it is preferable to use a more restrictive class.
1452 On the 80386 series, we prevent floating constants from being
1453 reloaded into floating registers (since no move-insn can do that)
1454 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1455
1456 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1457 QImode must go into class Q_REGS.
1458 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1459 movdf to do mem-to-mem moves through integer regs. */
1460
1461 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1462 ix86_preferred_reload_class ((X), (CLASS))
1463
1464 /* If we are copying between general and FP registers, we need a memory
1465 location. The same is true for SSE and MMX registers. */
1466 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1467 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1468
1469 /* QImode spills from non-QI registers need a scratch. This does not
1470 happen often -- the only example so far requires an uninitialized
1471 pseudo. */
1472
1473 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1474 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1475 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1476 ? Q_REGS : NO_REGS)
1477
1478 /* Return the maximum number of consecutive registers
1479 needed to represent mode MODE in a register of class CLASS. */
1480 /* On the 80386, this is the size of MODE in words,
1481 except in the FP regs, where a single reg is always enough.
1482 The TFmodes are really just 80bit values, so we use only 3 registers
1483 to hold them, instead of 4, as the size would suggest.
1484 */
1485 #define CLASS_MAX_NREGS(CLASS, MODE) \
1486 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1487 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1488 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1489 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1490
1491 /* A C expression whose value is nonzero if pseudos that have been
1492 assigned to registers of class CLASS would likely be spilled
1493 because registers of CLASS are needed for spill registers.
1494
1495 The default value of this macro returns 1 if CLASS has exactly one
1496 register and zero otherwise. On most machines, this default
1497 should be used. Only define this macro to some other expression
1498 if pseudo allocated by `local-alloc.c' end up in memory because
1499 their hard registers were needed for spill registers. If this
1500 macro returns nonzero for those classes, those pseudos will only
1501 be allocated by `global.c', which knows how to reallocate the
1502 pseudo to another register. If there would not be another
1503 register available for reallocation, you should not change the
1504 definition of this macro since the only effect of such a
1505 definition would be to slow down register allocation. */
1506
1507 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1508 (((CLASS) == AREG) \
1509 || ((CLASS) == DREG) \
1510 || ((CLASS) == CREG) \
1511 || ((CLASS) == BREG) \
1512 || ((CLASS) == AD_REGS) \
1513 || ((CLASS) == SIREG) \
1514 || ((CLASS) == DIREG))
1515
1516 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1517 to automatically clobber for all asms.
1518
1519 We do this in the new i386 backend to maintain source compatibility
1520 with the old cc0-based compiler. */
1521
1522 #define MD_ASM_CLOBBERS(CLOBBERS) \
1523 do { \
1524 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1525 (CLOBBERS)); \
1526 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1527 (CLOBBERS)); \
1528 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1529 (CLOBBERS)); \
1530 } while (0)
1531 \f
1532 /* Stack layout; function entry, exit and calling. */
1533
1534 /* Define this if pushing a word on the stack
1535 makes the stack pointer a smaller address. */
1536 #define STACK_GROWS_DOWNWARD
1537
1538 /* Define this if the nominal address of the stack frame
1539 is at the high-address end of the local variables;
1540 that is, each additional local variable allocated
1541 goes at a more negative offset in the frame. */
1542 #define FRAME_GROWS_DOWNWARD
1543
1544 /* Offset within stack frame to start allocating local variables at.
1545 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1546 first local allocated. Otherwise, it is the offset to the BEGINNING
1547 of the first local allocated. */
1548 #define STARTING_FRAME_OFFSET 0
1549
1550 /* If we generate an insn to push BYTES bytes,
1551 this says how many the stack pointer really advances by.
1552 On 386 pushw decrements by exactly 2 no matter what the position was.
1553 On the 386 there is no pushb; we use pushw instead, and this
1554 has the effect of rounding up to 2.
1555
1556 For 64bit ABI we round up to 8 bytes.
1557 */
1558
1559 #define PUSH_ROUNDING(BYTES) \
1560 (TARGET_64BIT \
1561 ? (((BYTES) + 7) & (-8)) \
1562 : (((BYTES) + 1) & (-2)))
1563
1564 /* If defined, the maximum amount of space required for outgoing arguments will
1565 be computed and placed into the variable
1566 `current_function_outgoing_args_size'. No space will be pushed onto the
1567 stack for each call; instead, the function prologue should increase the stack
1568 frame size by this amount. */
1569
1570 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1571
1572 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1573 instructions to pass outgoing arguments. */
1574
1575 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1576
1577 /* Offset of first parameter from the argument pointer register value. */
1578 #define FIRST_PARM_OFFSET(FNDECL) 0
1579
1580 /* Define this macro if functions should assume that stack space has been
1581 allocated for arguments even when their values are passed in registers.
1582
1583 The value of this macro is the size, in bytes, of the area reserved for
1584 arguments passed in registers for the function represented by FNDECL.
1585
1586 This space can be allocated by the caller, or be a part of the
1587 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1588 which. */
1589 #define REG_PARM_STACK_SPACE(FNDECL) 0
1590
1591 /* Define as a C expression that evaluates to nonzero if we do not know how
1592 to pass TYPE solely in registers. The file expr.h defines a
1593 definition that is usually appropriate, refer to expr.h for additional
1594 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1595 computed in the stack and then loaded into a register. */
1596 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1597 ((TYPE) != 0 \
1598 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1599 || TREE_ADDRESSABLE (TYPE) \
1600 || ((MODE) == TImode) \
1601 || ((MODE) == BLKmode \
1602 && ! ((TYPE) != 0 \
1603 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1604 && 0 == (int_size_in_bytes (TYPE) \
1605 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1606 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1607 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1608
1609 /* Value is the number of bytes of arguments automatically
1610 popped when returning from a subroutine call.
1611 FUNDECL is the declaration node of the function (as a tree),
1612 FUNTYPE is the data type of the function (as a tree),
1613 or for a library call it is an identifier node for the subroutine name.
1614 SIZE is the number of bytes of arguments passed on the stack.
1615
1616 On the 80386, the RTD insn may be used to pop them if the number
1617 of args is fixed, but if the number is variable then the caller
1618 must pop them all. RTD can't be used for library calls now
1619 because the library is compiled with the Unix compiler.
1620 Use of RTD is a selectable option, since it is incompatible with
1621 standard Unix calling sequences. If the option is not selected,
1622 the caller must always pop the args.
1623
1624 The attribute stdcall is equivalent to RTD on a per module basis. */
1625
1626 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1627 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1628
1629 /* Define how to find the value returned by a function.
1630 VALTYPE is the data type of the value (as a tree).
1631 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1632 otherwise, FUNC is 0. */
1633 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1634 ix86_function_value (VALTYPE)
1635
1636 #define FUNCTION_VALUE_REGNO_P(N) \
1637 ix86_function_value_regno_p (N)
1638
1639 /* Define how to find the value returned by a library function
1640 assuming the value has mode MODE. */
1641
1642 #define LIBCALL_VALUE(MODE) \
1643 ix86_libcall_value (MODE)
1644
1645 /* Define the size of the result block used for communication between
1646 untyped_call and untyped_return. The block contains a DImode value
1647 followed by the block used by fnsave and frstor. */
1648
1649 #define APPLY_RESULT_SIZE (8+108)
1650
1651 /* 1 if N is a possible register number for function argument passing. */
1652 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1653
1654 /* Define a data type for recording info about an argument list
1655 during the scan of that argument list. This data type should
1656 hold all necessary information about the function itself
1657 and about the args processed so far, enough to enable macros
1658 such as FUNCTION_ARG to determine where the next arg should go. */
1659
1660 typedef struct ix86_args {
1661 int words; /* # words passed so far */
1662 int nregs; /* # registers available for passing */
1663 int regno; /* next available register number */
1664 int sse_words; /* # sse words passed so far */
1665 int sse_nregs; /* # sse registers available for passing */
1666 int sse_regno; /* next available sse register number */
1667 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1668 } CUMULATIVE_ARGS;
1669
1670 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1671 for a call to a function whose data type is FNTYPE.
1672 For a library call, FNTYPE is 0. */
1673
1674 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1675 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
1676
1677 /* Update the data in CUM to advance over an argument
1678 of mode MODE and data type TYPE.
1679 (TYPE is null for libcalls where that information may not be available.) */
1680
1681 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1682 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1683
1684 /* Define where to put the arguments to a function.
1685 Value is zero to push the argument on the stack,
1686 or a hard register in which to store the argument.
1687
1688 MODE is the argument's machine mode.
1689 TYPE is the data type of the argument (as a tree).
1690 This is null for libcalls where that information may
1691 not be available.
1692 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1693 the preceding args and about the function being called.
1694 NAMED is nonzero if this argument is a named parameter
1695 (otherwise it is an extra parameter matching an ellipsis). */
1696
1697 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1698 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1699
1700 /* For an arg passed partly in registers and partly in memory,
1701 this is the number of registers used.
1702 For args passed entirely in registers or entirely in memory, zero. */
1703
1704 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1705
1706 /* If PIC, we cannot make sibling calls to global functions
1707 because the PLT requires %ebx live.
1708 If we are returning floats on the register stack, we cannot make
1709 sibling calls to functions that return floats. (The stack adjust
1710 instruction will wind up after the sibcall jump, and not be executed.) */
1711 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1712 ((DECL) \
1713 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1714 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1715 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1716 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1717
1718 /* Perform any needed actions needed for a function that is receiving a
1719 variable number of arguments.
1720
1721 CUM is as above.
1722
1723 MODE and TYPE are the mode and type of the current parameter.
1724
1725 PRETEND_SIZE is a variable that should be set to the amount of stack
1726 that must be pushed by the prolog to pretend that our caller pushed
1727 it.
1728
1729 Normally, this macro will push all remaining incoming registers on the
1730 stack and set PRETEND_SIZE to the length of the registers pushed. */
1731
1732 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1733 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1734 (NO_RTL))
1735
1736 /* Define the `__builtin_va_list' type for the ABI. */
1737 #define BUILD_VA_LIST_TYPE(VALIST) \
1738 ((VALIST) = ix86_build_va_list ())
1739
1740 /* Implement `va_start' for varargs and stdarg. */
1741 #define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \
1742 ix86_va_start ((STDARG), (VALIST), (NEXTARG))
1743
1744 /* Implement `va_arg'. */
1745 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1746 ix86_va_arg ((VALIST), (TYPE))
1747
1748 /* This macro is invoked at the end of compilation. It is used here to
1749 output code for -fpic that will load the return address into %ebx. */
1750
1751 #undef ASM_FILE_END
1752 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1753
1754 /* Output assembler code to FILE to increment profiler label # LABELNO
1755 for profiling a function entry. */
1756
1757 #define FUNCTION_PROFILER(FILE, LABELNO) \
1758 do { \
1759 if (flag_pic) \
1760 { \
1761 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1762 LPREFIX, (LABELNO)); \
1763 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1764 } \
1765 else \
1766 { \
1767 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1768 fprintf ((FILE), "\tcall\t_mcount\n"); \
1769 } \
1770 } while (0)
1771
1772 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1773 the stack pointer does not matter. The value is tested only in
1774 functions that have frame pointers.
1775 No definition is equivalent to always zero. */
1776 /* Note on the 386 it might be more efficient not to define this since
1777 we have to restore it ourselves from the frame pointer, in order to
1778 use pop */
1779
1780 #define EXIT_IGNORE_STACK 1
1781
1782 /* Output assembler code for a block containing the constant parts
1783 of a trampoline, leaving space for the variable parts. */
1784
1785 /* On the 386, the trampoline contains two instructions:
1786 mov #STATIC,ecx
1787 jmp FUNCTION
1788 The trampoline is generated entirely at runtime. The operand of JMP
1789 is the address of FUNCTION relative to the instruction following the
1790 JMP (which is 5 bytes long). */
1791
1792 /* Length in units of the trampoline for entering a nested function. */
1793
1794 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1795
1796 /* Emit RTL insns to initialize the variable parts of a trampoline.
1797 FNADDR is an RTX for the address of the function's pure code.
1798 CXT is an RTX for the static chain value for the function. */
1799
1800 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1801 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1802 \f
1803 /* Definitions for register eliminations.
1804
1805 This is an array of structures. Each structure initializes one pair
1806 of eliminable registers. The "from" register number is given first,
1807 followed by "to". Eliminations of the same "from" register are listed
1808 in order of preference.
1809
1810 There are two registers that can always be eliminated on the i386.
1811 The frame pointer and the arg pointer can be replaced by either the
1812 hard frame pointer or to the stack pointer, depending upon the
1813 circumstances. The hard frame pointer is not used before reload and
1814 so it is not eligible for elimination. */
1815
1816 #define ELIMINABLE_REGS \
1817 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1818 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1819 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1820 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1821
1822 /* Given FROM and TO register numbers, say whether this elimination is
1823 allowed. Frame pointer elimination is automatically handled.
1824
1825 All other eliminations are valid. */
1826
1827 #define CAN_ELIMINATE(FROM, TO) \
1828 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1829
1830 /* Define the offset between two registers, one to be eliminated, and the other
1831 its replacement, at the start of a routine. */
1832
1833 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1834 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1835 \f
1836 /* Addressing modes, and classification of registers for them. */
1837
1838 /* #define HAVE_POST_INCREMENT 0 */
1839 /* #define HAVE_POST_DECREMENT 0 */
1840
1841 /* #define HAVE_PRE_DECREMENT 0 */
1842 /* #define HAVE_PRE_INCREMENT 0 */
1843
1844 /* Macros to check register numbers against specific register classes. */
1845
1846 /* These assume that REGNO is a hard or pseudo reg number.
1847 They give nonzero only if REGNO is a hard reg of the suitable class
1848 or a pseudo reg currently allocated to a suitable hard reg.
1849 Since they use reg_renumber, they are safe only once reg_renumber
1850 has been allocated, which happens in local-alloc.c. */
1851
1852 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1853 ((REGNO) < STACK_POINTER_REGNUM \
1854 || (REGNO >= FIRST_REX_INT_REG \
1855 && (REGNO) <= LAST_REX_INT_REG) \
1856 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1857 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1858 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1859
1860 #define REGNO_OK_FOR_BASE_P(REGNO) \
1861 ((REGNO) <= STACK_POINTER_REGNUM \
1862 || (REGNO) == ARG_POINTER_REGNUM \
1863 || (REGNO) == FRAME_POINTER_REGNUM \
1864 || (REGNO >= FIRST_REX_INT_REG \
1865 && (REGNO) <= LAST_REX_INT_REG) \
1866 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1867 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1868 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1869
1870 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1871 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1872 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1873 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1874
1875 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1876 and check its validity for a certain class.
1877 We have two alternate definitions for each of them.
1878 The usual definition accepts all pseudo regs; the other rejects
1879 them unless they have been allocated suitable hard regs.
1880 The symbol REG_OK_STRICT causes the latter definition to be used.
1881
1882 Most source files want to accept pseudo regs in the hope that
1883 they will get allocated to the class that the insn wants them to be in.
1884 Source files for reload pass need to be strict.
1885 After reload, it makes no difference, since pseudo regs have
1886 been eliminated by then. */
1887
1888
1889 /* Non strict versions, pseudos are ok */
1890 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1891 (REGNO (X) < STACK_POINTER_REGNUM \
1892 || (REGNO (X) >= FIRST_REX_INT_REG \
1893 && REGNO (X) <= LAST_REX_INT_REG) \
1894 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1895
1896 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1897 (REGNO (X) <= STACK_POINTER_REGNUM \
1898 || REGNO (X) == ARG_POINTER_REGNUM \
1899 || REGNO (X) == FRAME_POINTER_REGNUM \
1900 || (REGNO (X) >= FIRST_REX_INT_REG \
1901 && REGNO (X) <= LAST_REX_INT_REG) \
1902 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1903
1904 /* Strict versions, hard registers only */
1905 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1906 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1907
1908 #ifndef REG_OK_STRICT
1909 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1910 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1911
1912 #else
1913 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1914 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1915 #endif
1916
1917 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1918 that is a valid memory address for an instruction.
1919 The MODE argument is the machine mode for the MEM expression
1920 that wants to use this address.
1921
1922 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1923 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1924
1925 See legitimize_pic_address in i386.c for details as to what
1926 constitutes a legitimate address when -fpic is used. */
1927
1928 #define MAX_REGS_PER_ADDRESS 2
1929
1930 #define CONSTANT_ADDRESS_P(X) \
1931 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1932 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1933 || GET_CODE (X) == CONST_DOUBLE)
1934
1935 /* Nonzero if the constant value X is a legitimate general operand.
1936 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1937
1938 #define LEGITIMATE_CONSTANT_P(X) 1
1939
1940 #ifdef REG_OK_STRICT
1941 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1942 do { \
1943 if (legitimate_address_p ((MODE), (X), 1)) \
1944 goto ADDR; \
1945 } while (0)
1946
1947 #else
1948 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1949 do { \
1950 if (legitimate_address_p ((MODE), (X), 0)) \
1951 goto ADDR; \
1952 } while (0)
1953
1954 #endif
1955
1956 /* If defined, a C expression to determine the base term of address X.
1957 This macro is used in only one place: `find_base_term' in alias.c.
1958
1959 It is always safe for this macro to not be defined. It exists so
1960 that alias analysis can understand machine-dependent addresses.
1961
1962 The typical use of this macro is to handle addresses containing
1963 a label_ref or symbol_ref within an UNSPEC. */
1964
1965 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1966
1967 /* Try machine-dependent ways of modifying an illegitimate address
1968 to be legitimate. If we find one, return the new, valid address.
1969 This macro is used in only one place: `memory_address' in explow.c.
1970
1971 OLDX is the address as it was before break_out_memory_refs was called.
1972 In some cases it is useful to look at this to decide what needs to be done.
1973
1974 MODE and WIN are passed so that this macro can use
1975 GO_IF_LEGITIMATE_ADDRESS.
1976
1977 It is always safe for this macro to do nothing. It exists to recognize
1978 opportunities to optimize the output.
1979
1980 For the 80386, we handle X+REG by loading X into a register R and
1981 using R+REG. R will go in a general reg and indexing will be used.
1982 However, if REG is a broken-out memory address or multiplication,
1983 nothing needs to be done because REG can certainly go in a general reg.
1984
1985 When -fpic is used, special handling is needed for symbolic references.
1986 See comments by legitimize_pic_address in i386.c for details. */
1987
1988 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1989 do { \
1990 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1991 if (memory_address_p ((MODE), (X))) \
1992 goto WIN; \
1993 } while (0)
1994
1995 #define REWRITE_ADDRESS(X) rewrite_address (X)
1996
1997 /* Nonzero if the constant value X is a legitimate general operand
1998 when generating PIC code. It is given that flag_pic is on and
1999 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2000
2001 #define LEGITIMATE_PIC_OPERAND_P(X) \
2002 (! SYMBOLIC_CONST (X) \
2003 || legitimate_pic_address_disp_p (X))
2004
2005 #define SYMBOLIC_CONST(X) \
2006 (GET_CODE (X) == SYMBOL_REF \
2007 || GET_CODE (X) == LABEL_REF \
2008 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2009
2010 /* Go to LABEL if ADDR (a legitimate address expression)
2011 has an effect that depends on the machine mode it is used for.
2012 On the 80386, only postdecrement and postincrement address depend thus
2013 (the amount of decrement or increment being the length of the operand). */
2014 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2015 do { \
2016 if (GET_CODE (ADDR) == POST_INC \
2017 || GET_CODE (ADDR) == POST_DEC) \
2018 goto LABEL; \
2019 } while (0)
2020 \f
2021 /* Codes for all the SSE/MMX builtins. */
2022 enum ix86_builtins
2023 {
2024 IX86_BUILTIN_ADDPS,
2025 IX86_BUILTIN_ADDSS,
2026 IX86_BUILTIN_DIVPS,
2027 IX86_BUILTIN_DIVSS,
2028 IX86_BUILTIN_MULPS,
2029 IX86_BUILTIN_MULSS,
2030 IX86_BUILTIN_SUBPS,
2031 IX86_BUILTIN_SUBSS,
2032
2033 IX86_BUILTIN_CMPEQPS,
2034 IX86_BUILTIN_CMPLTPS,
2035 IX86_BUILTIN_CMPLEPS,
2036 IX86_BUILTIN_CMPGTPS,
2037 IX86_BUILTIN_CMPGEPS,
2038 IX86_BUILTIN_CMPNEQPS,
2039 IX86_BUILTIN_CMPNLTPS,
2040 IX86_BUILTIN_CMPNLEPS,
2041 IX86_BUILTIN_CMPNGTPS,
2042 IX86_BUILTIN_CMPNGEPS,
2043 IX86_BUILTIN_CMPORDPS,
2044 IX86_BUILTIN_CMPUNORDPS,
2045 IX86_BUILTIN_CMPNEPS,
2046 IX86_BUILTIN_CMPEQSS,
2047 IX86_BUILTIN_CMPLTSS,
2048 IX86_BUILTIN_CMPLESS,
2049 IX86_BUILTIN_CMPGTSS,
2050 IX86_BUILTIN_CMPGESS,
2051 IX86_BUILTIN_CMPNEQSS,
2052 IX86_BUILTIN_CMPNLTSS,
2053 IX86_BUILTIN_CMPNLESS,
2054 IX86_BUILTIN_CMPNGTSS,
2055 IX86_BUILTIN_CMPNGESS,
2056 IX86_BUILTIN_CMPORDSS,
2057 IX86_BUILTIN_CMPUNORDSS,
2058 IX86_BUILTIN_CMPNESS,
2059
2060 IX86_BUILTIN_COMIEQSS,
2061 IX86_BUILTIN_COMILTSS,
2062 IX86_BUILTIN_COMILESS,
2063 IX86_BUILTIN_COMIGTSS,
2064 IX86_BUILTIN_COMIGESS,
2065 IX86_BUILTIN_COMINEQSS,
2066 IX86_BUILTIN_UCOMIEQSS,
2067 IX86_BUILTIN_UCOMILTSS,
2068 IX86_BUILTIN_UCOMILESS,
2069 IX86_BUILTIN_UCOMIGTSS,
2070 IX86_BUILTIN_UCOMIGESS,
2071 IX86_BUILTIN_UCOMINEQSS,
2072
2073 IX86_BUILTIN_CVTPI2PS,
2074 IX86_BUILTIN_CVTPS2PI,
2075 IX86_BUILTIN_CVTSI2SS,
2076 IX86_BUILTIN_CVTSS2SI,
2077 IX86_BUILTIN_CVTTPS2PI,
2078 IX86_BUILTIN_CVTTSS2SI,
2079
2080 IX86_BUILTIN_MAXPS,
2081 IX86_BUILTIN_MAXSS,
2082 IX86_BUILTIN_MINPS,
2083 IX86_BUILTIN_MINSS,
2084
2085 IX86_BUILTIN_LOADAPS,
2086 IX86_BUILTIN_LOADUPS,
2087 IX86_BUILTIN_STOREAPS,
2088 IX86_BUILTIN_STOREUPS,
2089 IX86_BUILTIN_LOADSS,
2090 IX86_BUILTIN_STORESS,
2091 IX86_BUILTIN_MOVSS,
2092
2093 IX86_BUILTIN_MOVHLPS,
2094 IX86_BUILTIN_MOVLHPS,
2095 IX86_BUILTIN_LOADHPS,
2096 IX86_BUILTIN_LOADLPS,
2097 IX86_BUILTIN_STOREHPS,
2098 IX86_BUILTIN_STORELPS,
2099
2100 IX86_BUILTIN_MASKMOVQ,
2101 IX86_BUILTIN_MOVMSKPS,
2102 IX86_BUILTIN_PMOVMSKB,
2103
2104 IX86_BUILTIN_MOVNTPS,
2105 IX86_BUILTIN_MOVNTQ,
2106
2107 IX86_BUILTIN_PACKSSWB,
2108 IX86_BUILTIN_PACKSSDW,
2109 IX86_BUILTIN_PACKUSWB,
2110
2111 IX86_BUILTIN_PADDB,
2112 IX86_BUILTIN_PADDW,
2113 IX86_BUILTIN_PADDD,
2114 IX86_BUILTIN_PADDSB,
2115 IX86_BUILTIN_PADDSW,
2116 IX86_BUILTIN_PADDUSB,
2117 IX86_BUILTIN_PADDUSW,
2118 IX86_BUILTIN_PSUBB,
2119 IX86_BUILTIN_PSUBW,
2120 IX86_BUILTIN_PSUBD,
2121 IX86_BUILTIN_PSUBSB,
2122 IX86_BUILTIN_PSUBSW,
2123 IX86_BUILTIN_PSUBUSB,
2124 IX86_BUILTIN_PSUBUSW,
2125
2126 IX86_BUILTIN_PAND,
2127 IX86_BUILTIN_PANDN,
2128 IX86_BUILTIN_POR,
2129 IX86_BUILTIN_PXOR,
2130
2131 IX86_BUILTIN_PAVGB,
2132 IX86_BUILTIN_PAVGW,
2133
2134 IX86_BUILTIN_PCMPEQB,
2135 IX86_BUILTIN_PCMPEQW,
2136 IX86_BUILTIN_PCMPEQD,
2137 IX86_BUILTIN_PCMPGTB,
2138 IX86_BUILTIN_PCMPGTW,
2139 IX86_BUILTIN_PCMPGTD,
2140
2141 IX86_BUILTIN_PEXTRW,
2142 IX86_BUILTIN_PINSRW,
2143
2144 IX86_BUILTIN_PMADDWD,
2145
2146 IX86_BUILTIN_PMAXSW,
2147 IX86_BUILTIN_PMAXUB,
2148 IX86_BUILTIN_PMINSW,
2149 IX86_BUILTIN_PMINUB,
2150
2151 IX86_BUILTIN_PMULHUW,
2152 IX86_BUILTIN_PMULHW,
2153 IX86_BUILTIN_PMULLW,
2154
2155 IX86_BUILTIN_PSADBW,
2156 IX86_BUILTIN_PSHUFW,
2157
2158 IX86_BUILTIN_PSLLW,
2159 IX86_BUILTIN_PSLLD,
2160 IX86_BUILTIN_PSLLQ,
2161 IX86_BUILTIN_PSRAW,
2162 IX86_BUILTIN_PSRAD,
2163 IX86_BUILTIN_PSRLW,
2164 IX86_BUILTIN_PSRLD,
2165 IX86_BUILTIN_PSRLQ,
2166 IX86_BUILTIN_PSLLWI,
2167 IX86_BUILTIN_PSLLDI,
2168 IX86_BUILTIN_PSLLQI,
2169 IX86_BUILTIN_PSRAWI,
2170 IX86_BUILTIN_PSRADI,
2171 IX86_BUILTIN_PSRLWI,
2172 IX86_BUILTIN_PSRLDI,
2173 IX86_BUILTIN_PSRLQI,
2174
2175 IX86_BUILTIN_PUNPCKHBW,
2176 IX86_BUILTIN_PUNPCKHWD,
2177 IX86_BUILTIN_PUNPCKHDQ,
2178 IX86_BUILTIN_PUNPCKLBW,
2179 IX86_BUILTIN_PUNPCKLWD,
2180 IX86_BUILTIN_PUNPCKLDQ,
2181
2182 IX86_BUILTIN_SHUFPS,
2183
2184 IX86_BUILTIN_RCPPS,
2185 IX86_BUILTIN_RCPSS,
2186 IX86_BUILTIN_RSQRTPS,
2187 IX86_BUILTIN_RSQRTSS,
2188 IX86_BUILTIN_SQRTPS,
2189 IX86_BUILTIN_SQRTSS,
2190
2191 IX86_BUILTIN_UNPCKHPS,
2192 IX86_BUILTIN_UNPCKLPS,
2193
2194 IX86_BUILTIN_ANDPS,
2195 IX86_BUILTIN_ANDNPS,
2196 IX86_BUILTIN_ORPS,
2197 IX86_BUILTIN_XORPS,
2198
2199 IX86_BUILTIN_EMMS,
2200 IX86_BUILTIN_LDMXCSR,
2201 IX86_BUILTIN_STMXCSR,
2202 IX86_BUILTIN_SFENCE,
2203
2204 /* 3DNow! Original */
2205 IX86_BUILTIN_FEMMS,
2206 IX86_BUILTIN_PAVGUSB,
2207 IX86_BUILTIN_PF2ID,
2208 IX86_BUILTIN_PFACC,
2209 IX86_BUILTIN_PFADD,
2210 IX86_BUILTIN_PFCMPEQ,
2211 IX86_BUILTIN_PFCMPGE,
2212 IX86_BUILTIN_PFCMPGT,
2213 IX86_BUILTIN_PFMAX,
2214 IX86_BUILTIN_PFMIN,
2215 IX86_BUILTIN_PFMUL,
2216 IX86_BUILTIN_PFRCP,
2217 IX86_BUILTIN_PFRCPIT1,
2218 IX86_BUILTIN_PFRCPIT2,
2219 IX86_BUILTIN_PFRSQIT1,
2220 IX86_BUILTIN_PFRSQRT,
2221 IX86_BUILTIN_PFSUB,
2222 IX86_BUILTIN_PFSUBR,
2223 IX86_BUILTIN_PI2FD,
2224 IX86_BUILTIN_PMULHRW,
2225
2226 /* 3DNow! Athlon Extensions */
2227 IX86_BUILTIN_PF2IW,
2228 IX86_BUILTIN_PFNACC,
2229 IX86_BUILTIN_PFPNACC,
2230 IX86_BUILTIN_PI2FW,
2231 IX86_BUILTIN_PSWAPDSI,
2232 IX86_BUILTIN_PSWAPDSF,
2233
2234 IX86_BUILTIN_SSE_ZERO,
2235 IX86_BUILTIN_MMX_ZERO,
2236
2237 IX86_BUILTIN_MAX
2238 };
2239 \f
2240 /* Define this macro if references to a symbol must be treated
2241 differently depending on something about the variable or
2242 function named by the symbol (such as what section it is in).
2243
2244 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2245 so that we may access it directly in the GOT. */
2246
2247 #define ENCODE_SECTION_INFO(DECL, FIRST) \
2248 do { \
2249 if (flag_pic) \
2250 { \
2251 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2252 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2253 \
2254 if (GET_CODE (rtl) == MEM) \
2255 { \
2256 if (TARGET_DEBUG_ADDR \
2257 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2258 { \
2259 fprintf (stderr, "Encode %s, public = %d\n", \
2260 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2261 TREE_PUBLIC (DECL)); \
2262 } \
2263 \
2264 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2265 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2266 || ! TREE_PUBLIC (DECL) \
2267 || MODULE_LOCAL_P (DECL)); \
2268 } \
2269 } \
2270 } while (0)
2271
2272 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2273 codes once the function is being compiled into assembly code, but
2274 not before. (It is not done before, because in the case of
2275 compiling an inline function, it would lead to multiple PIC
2276 prologues being included in functions which used inline functions
2277 and were compiled to assembly language.) */
2278
2279 #define FINALIZE_PIC \
2280 (current_function_uses_pic_offset_table |= current_function_profile)
2281
2282 \f
2283 /* Max number of args passed in registers. If this is more than 3, we will
2284 have problems with ebx (register #4), since it is a caller save register and
2285 is also used as the pic register in ELF. So for now, don't allow more than
2286 3 registers to be passed in registers. */
2287
2288 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2289
2290 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2291
2292 \f
2293 /* Specify the machine mode that this machine uses
2294 for the index in the tablejump instruction. */
2295 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2296
2297 /* Define as C expression which evaluates to nonzero if the tablejump
2298 instruction expects the table to contain offsets from the address of the
2299 table.
2300 Do not define this if the table should contain absolute addresses. */
2301 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2302
2303 /* Define this as 1 if `char' should by default be signed; else as 0. */
2304 #define DEFAULT_SIGNED_CHAR 1
2305
2306 /* Number of bytes moved into a data cache for a single prefetch operation. */
2307 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2308
2309 /* Number of prefetch operations that can be done in parallel. */
2310 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2311
2312 /* Max number of bytes we can move from memory to memory
2313 in one reasonably fast instruction. */
2314 #define MOVE_MAX 16
2315
2316 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2317 move efficiently, as opposed to MOVE_MAX which is the maximum
2318 number of bytes we can move with a single instruction. */
2319 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2320
2321 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2322 move-instruction pairs, we will do a movstr or libcall instead.
2323 Increasing the value will always make code faster, but eventually
2324 incurs high cost in increased code size.
2325
2326 If you don't define this, a reasonable default is used. */
2327
2328 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2329
2330 /* Define if shifts truncate the shift count
2331 which implies one can omit a sign-extension or zero-extension
2332 of a shift count. */
2333 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2334
2335 /* #define SHIFT_COUNT_TRUNCATED */
2336
2337 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2338 is done just by pretending it is already truncated. */
2339 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2340
2341 /* We assume that the store-condition-codes instructions store 0 for false
2342 and some other value for true. This is the value stored for true. */
2343
2344 #define STORE_FLAG_VALUE 1
2345
2346 /* When a prototype says `char' or `short', really pass an `int'.
2347 (The 386 can't easily push less than an int.) */
2348
2349 #define PROMOTE_PROTOTYPES 1
2350
2351 /* A macro to update M and UNSIGNEDP when an object whose type is
2352 TYPE and which has the specified mode and signedness is to be
2353 stored in a register. This macro is only called when TYPE is a
2354 scalar type.
2355
2356 On i386 it is sometimes useful to promote HImode and QImode
2357 quantities to SImode. The choice depends on target type. */
2358
2359 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2360 do { \
2361 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2362 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2363 (MODE) = SImode; \
2364 } while (0)
2365
2366 /* Specify the machine mode that pointers have.
2367 After generation of rtl, the compiler makes no further distinction
2368 between pointers and any other objects of this machine mode. */
2369 #define Pmode (TARGET_64BIT ? DImode : SImode)
2370
2371 /* A function address in a call instruction
2372 is a byte address (for indexing purposes)
2373 so give the MEM rtx a byte's mode. */
2374 #define FUNCTION_MODE QImode
2375 \f
2376 /* A part of a C `switch' statement that describes the relative costs
2377 of constant RTL expressions. It must contain `case' labels for
2378 expression codes `const_int', `const', `symbol_ref', `label_ref'
2379 and `const_double'. Each case must ultimately reach a `return'
2380 statement to return the relative cost of the use of that kind of
2381 constant value in an expression. The cost may depend on the
2382 precise value of the constant, which is available for examination
2383 in X, and the rtx code of the expression in which it is contained,
2384 found in OUTER_CODE.
2385
2386 CODE is the expression code--redundant, since it can be obtained
2387 with `GET_CODE (X)'. */
2388
2389 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2390 case CONST_INT: \
2391 case CONST: \
2392 case LABEL_REF: \
2393 case SYMBOL_REF: \
2394 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2395 return 3; \
2396 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2397 return 2; \
2398 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2399 \
2400 case CONST_DOUBLE: \
2401 { \
2402 int code; \
2403 if (GET_MODE (RTX) == VOIDmode) \
2404 return 0; \
2405 \
2406 code = standard_80387_constant_p (RTX); \
2407 return code == 1 ? 1 : \
2408 code == 2 ? 2 : \
2409 3; \
2410 }
2411
2412 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2413 #define TOPLEVEL_COSTS_N_INSNS(N) \
2414 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2415
2416 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2417 This can be used, for example, to indicate how costly a multiply
2418 instruction is. In writing this macro, you can use the construct
2419 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2420 instructions. OUTER_CODE is the code of the expression in which X
2421 is contained.
2422
2423 This macro is optional; do not define it if the default cost
2424 assumptions are adequate for the target machine. */
2425
2426 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2427 case ZERO_EXTEND: \
2428 /* The zero extensions is often completely free on x86_64, so make \
2429 it as cheap as possible. */ \
2430 if (TARGET_64BIT && GET_MODE (X) == DImode \
2431 && GET_MODE (XEXP (X, 0)) == SImode) \
2432 { \
2433 total = 1; goto egress_rtx_costs; \
2434 } \
2435 else \
2436 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2437 ix86_cost->add : ix86_cost->movzx); \
2438 break; \
2439 case SIGN_EXTEND: \
2440 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2441 break; \
2442 case ASHIFT: \
2443 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2444 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2445 { \
2446 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2447 if (value == 1) \
2448 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2449 if ((value == 2 || value == 3) \
2450 && !TARGET_DECOMPOSE_LEA \
2451 && ix86_cost->lea <= ix86_cost->shift_const) \
2452 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2453 } \
2454 /* fall through */ \
2455 \
2456 case ROTATE: \
2457 case ASHIFTRT: \
2458 case LSHIFTRT: \
2459 case ROTATERT: \
2460 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2461 { \
2462 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2463 { \
2464 if (INTVAL (XEXP (X, 1)) > 32) \
2465 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2466 else \
2467 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2468 } \
2469 else \
2470 { \
2471 if (GET_CODE (XEXP (X, 1)) == AND) \
2472 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2473 else \
2474 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2475 } \
2476 } \
2477 else \
2478 { \
2479 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2480 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2481 else \
2482 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2483 } \
2484 break; \
2485 \
2486 case MULT: \
2487 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2488 { \
2489 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2490 int nbits = 0; \
2491 \
2492 while (value != 0) \
2493 { \
2494 nbits++; \
2495 value >>= 1; \
2496 } \
2497 \
2498 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2499 + nbits * ix86_cost->mult_bit); \
2500 } \
2501 else /* This is arbitrary */ \
2502 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2503 + 7 * ix86_cost->mult_bit); \
2504 \
2505 case DIV: \
2506 case UDIV: \
2507 case MOD: \
2508 case UMOD: \
2509 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2510 \
2511 case PLUS: \
2512 if (!TARGET_DECOMPOSE_LEA \
2513 && INTEGRAL_MODE_P (GET_MODE (X)) \
2514 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2515 { \
2516 if (GET_CODE (XEXP (X, 0)) == PLUS \
2517 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2518 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2519 && CONSTANT_P (XEXP (X, 1))) \
2520 { \
2521 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2522 if (val == 2 || val == 4 || val == 8) \
2523 { \
2524 return (COSTS_N_INSNS (ix86_cost->lea) \
2525 + rtx_cost (XEXP (XEXP (X, 0), 1), \
2526 (OUTER_CODE)) \
2527 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \
2528 (OUTER_CODE)) \
2529 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2530 } \
2531 } \
2532 else if (GET_CODE (XEXP (X, 0)) == MULT \
2533 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2534 { \
2535 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2536 if (val == 2 || val == 4 || val == 8) \
2537 { \
2538 return (COSTS_N_INSNS (ix86_cost->lea) \
2539 + rtx_cost (XEXP (XEXP (X, 0), 0), \
2540 (OUTER_CODE)) \
2541 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2542 } \
2543 } \
2544 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2545 { \
2546 return (COSTS_N_INSNS (ix86_cost->lea) \
2547 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \
2548 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \
2549 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2550 } \
2551 } \
2552 \
2553 /* fall through */ \
2554 case AND: \
2555 case IOR: \
2556 case XOR: \
2557 case MINUS: \
2558 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2559 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2560 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \
2561 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2562 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \
2563 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2564 \
2565 /* fall through */ \
2566 case NEG: \
2567 case NOT: \
2568 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2569 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2570 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2571 \
2572 egress_rtx_costs: \
2573 break;
2574
2575
2576 /* An expression giving the cost of an addressing mode that contains
2577 ADDRESS. If not defined, the cost is computed from the ADDRESS
2578 expression and the `CONST_COSTS' values.
2579
2580 For most CISC machines, the default cost is a good approximation
2581 of the true cost of the addressing mode. However, on RISC
2582 machines, all instructions normally have the same length and
2583 execution time. Hence all addresses will have equal costs.
2584
2585 In cases where more than one form of an address is known, the form
2586 with the lowest cost will be used. If multiple forms have the
2587 same, lowest, cost, the one that is the most complex will be used.
2588
2589 For example, suppose an address that is equal to the sum of a
2590 register and a constant is used twice in the same basic block.
2591 When this macro is not defined, the address will be computed in a
2592 register and memory references will be indirect through that
2593 register. On machines where the cost of the addressing mode
2594 containing the sum is no higher than that of a simple indirect
2595 reference, this will produce an additional instruction and
2596 possibly require an additional register. Proper specification of
2597 this macro eliminates this overhead for such machines.
2598
2599 Similar use of this macro is made in strength reduction of loops.
2600
2601 ADDRESS need not be valid as an address. In such a case, the cost
2602 is not relevant and can be any value; invalid addresses need not be
2603 assigned a different cost.
2604
2605 On machines where an address involving more than one register is as
2606 cheap as an address computation involving only one register,
2607 defining `ADDRESS_COST' to reflect this can cause two registers to
2608 be live over a region of code where only one would have been if
2609 `ADDRESS_COST' were not defined in that manner. This effect should
2610 be considered in the definition of this macro. Equivalent costs
2611 should probably only be given to addresses with different numbers
2612 of registers on machines with lots of registers.
2613
2614 This macro will normally either not be defined or be defined as a
2615 constant.
2616
2617 For i386, it is better to use a complex address than let gcc copy
2618 the address into a reg and make a new pseudo. But not if the address
2619 requires to two regs - that would mean more pseudos with longer
2620 lifetimes. */
2621
2622 #define ADDRESS_COST(RTX) \
2623 ix86_address_cost (RTX)
2624
2625 /* A C expression for the cost of moving data from a register in class FROM to
2626 one in class TO. The classes are expressed using the enumeration values
2627 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2628 interpreted relative to that.
2629
2630 It is not required that the cost always equal 2 when FROM is the same as TO;
2631 on some machines it is expensive to move between registers if they are not
2632 general registers. */
2633
2634 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2635 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2636
2637 /* A C expression for the cost of moving data of mode M between a
2638 register and memory. A value of 2 is the default; this cost is
2639 relative to those in `REGISTER_MOVE_COST'.
2640
2641 If moving between registers and memory is more expensive than
2642 between two registers, you should define this macro to express the
2643 relative cost. */
2644
2645 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2646 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2647
2648 /* A C expression for the cost of a branch instruction. A value of 1
2649 is the default; other values are interpreted relative to that. */
2650
2651 #define BRANCH_COST ix86_branch_cost
2652
2653 /* Define this macro as a C expression which is nonzero if accessing
2654 less than a word of memory (i.e. a `char' or a `short') is no
2655 faster than accessing a word of memory, i.e., if such access
2656 require more than one instruction or if there is no difference in
2657 cost between byte and (aligned) word loads.
2658
2659 When this macro is not defined, the compiler will access a field by
2660 finding the smallest containing object; when it is defined, a
2661 fullword load will be used if alignment permits. Unless bytes
2662 accesses are faster than word accesses, using word accesses is
2663 preferable since it may eliminate subsequent memory access if
2664 subsequent accesses occur to other fields in the same word of the
2665 structure, but to different bytes. */
2666
2667 #define SLOW_BYTE_ACCESS 0
2668
2669 /* Nonzero if access to memory by shorts is slow and undesirable. */
2670 #define SLOW_SHORT_ACCESS 0
2671
2672 /* Define this macro to be the value 1 if unaligned accesses have a
2673 cost many times greater than aligned accesses, for example if they
2674 are emulated in a trap handler.
2675
2676 When this macro is non-zero, the compiler will act as if
2677 `STRICT_ALIGNMENT' were non-zero when generating code for block
2678 moves. This can cause significantly more instructions to be
2679 produced. Therefore, do not set this macro non-zero if unaligned
2680 accesses only add a cycle or two to the time for a memory access.
2681
2682 If the value of this macro is always zero, it need not be defined. */
2683
2684 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2685
2686 /* Define this macro to inhibit strength reduction of memory
2687 addresses. (On some machines, such strength reduction seems to do
2688 harm rather than good.) */
2689
2690 /* #define DONT_REDUCE_ADDR */
2691
2692 /* Define this macro if it is as good or better to call a constant
2693 function address than to call an address kept in a register.
2694
2695 Desirable on the 386 because a CALL with a constant address is
2696 faster than one with a register address. */
2697
2698 #define NO_FUNCTION_CSE
2699
2700 /* Define this macro if it is as good or better for a function to call
2701 itself with an explicit address than to call an address kept in a
2702 register. */
2703
2704 #define NO_RECURSIVE_FUNCTION_CSE
2705 \f
2706 /* Add any extra modes needed to represent the condition code.
2707
2708 For the i386, we need separate modes when floating-point
2709 equality comparisons are being done.
2710
2711 Add CCNO to indicate comparisons against zero that requires
2712 Overflow flag to be unset. Sign bit test is used instead and
2713 thus can be used to form "a&b>0" type of tests.
2714
2715 Add CCGC to indicate comparisons agains zero that allows
2716 unspecified garbage in the Carry flag. This mode is used
2717 by inc/dec instructions.
2718
2719 Add CCGOC to indicate comparisons agains zero that allows
2720 unspecified garbage in the Carry and Overflow flag. This
2721 mode is used to simulate comparisons of (a-b) and (a+b)
2722 against zero using sub/cmp/add operations.
2723
2724 Add CCZ to indicate that only the Zero flag is valid. */
2725
2726 #define EXTRA_CC_MODES \
2727 CC (CCGCmode, "CCGC") \
2728 CC (CCGOCmode, "CCGOC") \
2729 CC (CCNOmode, "CCNO") \
2730 CC (CCZmode, "CCZ") \
2731 CC (CCFPmode, "CCFP") \
2732 CC (CCFPUmode, "CCFPU")
2733
2734 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2735 return the mode to be used for the comparison.
2736
2737 For floating-point equality comparisons, CCFPEQmode should be used.
2738 VOIDmode should be used in all other cases.
2739
2740 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2741 possible, to allow for more combinations. */
2742
2743 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2744
2745 /* Return non-zero if MODE implies a floating point inequality can be
2746 reversed. */
2747
2748 #define REVERSIBLE_CC_MODE(MODE) 1
2749
2750 /* A C expression whose value is reversed condition code of the CODE for
2751 comparison done in CC_MODE mode. */
2752 #define REVERSE_CONDITION(CODE, MODE) \
2753 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2754 : reverse_condition_maybe_unordered (CODE))
2755
2756 \f
2757 /* Control the assembler format that we output, to the extent
2758 this does not vary between assemblers. */
2759
2760 /* How to refer to registers in assembler output.
2761 This sequence is indexed by compiler's hard-register-number (see above). */
2762
2763 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2764 For non floating point regs, the following are the HImode names.
2765
2766 For float regs, the stack top is sometimes referred to as "%st(0)"
2767 instead of just "%st". PRINT_REG handles this with the "y" code. */
2768
2769 #undef HI_REGISTER_NAMES
2770 #define HI_REGISTER_NAMES \
2771 {"ax","dx","cx","bx","si","di","bp","sp", \
2772 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2773 "flags","fpsr", "dirflag", "frame", \
2774 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2775 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2776 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2777 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2778
2779 #define REGISTER_NAMES HI_REGISTER_NAMES
2780
2781 /* Table of additional register names to use in user input. */
2782
2783 #define ADDITIONAL_REGISTER_NAMES \
2784 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2785 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2786 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2787 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2788 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2789 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2790 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2791 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2792
2793 /* Note we are omitting these since currently I don't know how
2794 to get gcc to use these, since they want the same but different
2795 number as al, and ax.
2796 */
2797
2798 #define QI_REGISTER_NAMES \
2799 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2800
2801 /* These parallel the array above, and can be used to access bits 8:15
2802 of regs 0 through 3. */
2803
2804 #define QI_HIGH_REGISTER_NAMES \
2805 {"ah", "dh", "ch", "bh", }
2806
2807 /* How to renumber registers for dbx and gdb. */
2808
2809 #define DBX_REGISTER_NUMBER(N) \
2810 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2811
2812 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2813 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2814 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2815
2816 /* Before the prologue, RA is at 0(%esp). */
2817 #define INCOMING_RETURN_ADDR_RTX \
2818 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2819
2820 /* After the prologue, RA is at -4(AP) in the current frame. */
2821 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2822 ((COUNT) == 0 \
2823 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2824 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2825
2826 /* PC is dbx register 8; let's use that column for RA. */
2827 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2828
2829 /* Before the prologue, the top of the frame is at 4(%esp). */
2830 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2831
2832 /* Describe how we implement __builtin_eh_return. */
2833 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2834 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2835
2836
2837 /* Select a format to encode pointers in exception handling data. CODE
2838 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2839 true if the symbol may be affected by dynamic relocations.
2840
2841 ??? All x86 object file formats are capable of representing this.
2842 After all, the relocation needed is the same as for the call insn.
2843 Whether or not a particular assembler allows us to enter such, I
2844 guess we'll have to see. */
2845 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2846 (flag_pic \
2847 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2848 : DW_EH_PE_absptr)
2849
2850 /* This is how to output the definition of a user-level label named NAME,
2851 such as the label on a static function or variable NAME. */
2852
2853 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2854 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE)))
2855
2856 /* Store in OUTPUT a string (made with alloca) containing
2857 an assembler-name for a local static variable named NAME.
2858 LABELNO is an integer which is different for each call. */
2859
2860 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2861 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2862 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2863
2864 /* This is how to output an insn to push a register on the stack.
2865 It need not be very fast code. */
2866
2867 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2868 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)])
2869
2870 /* This is how to output an insn to pop a register from the stack.
2871 It need not be very fast code. */
2872
2873 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2874 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)])
2875
2876 /* This is how to output an element of a case-vector that is absolute. */
2877
2878 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2879 ix86_output_addr_vec_elt ((FILE), (VALUE))
2880
2881 /* This is how to output an element of a case-vector that is relative. */
2882
2883 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2884 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2885
2886 /* Under some conditions we need jump tables in the text section, because
2887 the assembler cannot handle label differences between sections. */
2888
2889 #define JUMP_TABLES_IN_TEXT_SECTION \
2890 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2891
2892 /* A C statement that outputs an address constant appropriate to
2893 for DWARF debugging. */
2894
2895 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
2896 i386_dwarf_output_addr_const ((FILE), (X))
2897
2898 /* Either simplify a location expression, or return the original. */
2899
2900 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2901 i386_simplify_dwarf_addr (X)
2902
2903 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2904 and switch back. For x86 we do this only to save a few bytes that
2905 would otherwise be unused in the text section. */
2906 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2907 asm (SECTION_OP "\n\t" \
2908 "call " USER_LABEL_PREFIX #FUNC "\n" \
2909 TEXT_SECTION_ASM_OP);
2910 \f
2911 /* Print operand X (an rtx) in assembler syntax to file FILE.
2912 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2913 Effect of various CODE letters is described in i386.c near
2914 print_operand function. */
2915
2916 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2917 ((CODE) == '*' || (CODE) == '+')
2918
2919 /* Print the name of a register based on its machine mode and number.
2920 If CODE is 'w', pretend the mode is HImode.
2921 If CODE is 'b', pretend the mode is QImode.
2922 If CODE is 'k', pretend the mode is SImode.
2923 If CODE is 'q', pretend the mode is DImode.
2924 If CODE is 'h', pretend the reg is the `high' byte register.
2925 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2926
2927 #define PRINT_REG(X, CODE, FILE) \
2928 print_reg ((X), (CODE), (FILE))
2929
2930 #define PRINT_OPERAND(FILE, X, CODE) \
2931 print_operand ((FILE), (X), (CODE))
2932
2933 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2934 print_operand_address ((FILE), (ADDR))
2935
2936 /* Print the name of a register for based on its machine mode and number.
2937 This macro is used to print debugging output.
2938 This macro is different from PRINT_REG in that it may be used in
2939 programs that are not linked with aux-output.o. */
2940
2941 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2942 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2943 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2944 fprintf ((FILE), "%d ", REGNO (X)); \
2945 if (REGNO (X) == FLAGS_REG) \
2946 { fputs ("flags", (FILE)); break; } \
2947 if (REGNO (X) == DIRFLAG_REG) \
2948 { fputs ("dirflag", (FILE)); break; } \
2949 if (REGNO (X) == FPSR_REG) \
2950 { fputs ("fpsr", (FILE)); break; } \
2951 if (REGNO (X) == ARG_POINTER_REGNUM) \
2952 { fputs ("argp", (FILE)); break; } \
2953 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2954 { fputs ("frame", (FILE)); break; } \
2955 if (STACK_TOP_P (X)) \
2956 { fputs ("st(0)", (FILE)); break; } \
2957 if (FP_REG_P (X)) \
2958 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
2959 if (REX_INT_REG_P (X)) \
2960 { \
2961 switch (GET_MODE_SIZE (GET_MODE (X))) \
2962 { \
2963 default: \
2964 case 8: \
2965 fprintf ((FILE), "r%i", REGNO (X) \
2966 - FIRST_REX_INT_REG + 8); \
2967 break; \
2968 case 4: \
2969 fprintf ((FILE), "r%id", REGNO (X) \
2970 - FIRST_REX_INT_REG + 8); \
2971 break; \
2972 case 2: \
2973 fprintf ((FILE), "r%iw", REGNO (X) \
2974 - FIRST_REX_INT_REG + 8); \
2975 break; \
2976 case 1: \
2977 fprintf ((FILE), "r%ib", REGNO (X) \
2978 - FIRST_REX_INT_REG + 8); \
2979 break; \
2980 } \
2981 break; \
2982 } \
2983 switch (GET_MODE_SIZE (GET_MODE (X))) \
2984 { \
2985 case 8: \
2986 fputs ("r", (FILE)); \
2987 fputs (hi_name[REGNO (X)], (FILE)); \
2988 break; \
2989 default: \
2990 fputs ("e", (FILE)); \
2991 case 2: \
2992 fputs (hi_name[REGNO (X)], (FILE)); \
2993 break; \
2994 case 1: \
2995 fputs (qi_name[REGNO (X)], (FILE)); \
2996 break; \
2997 } \
2998 } while (0)
2999
3000 /* a letter which is not needed by the normal asm syntax, which
3001 we can use for operand syntax in the extended asm */
3002
3003 #define ASM_OPERAND_LETTER '#'
3004 #define RET return ""
3005 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
3006 \f
3007 /* Define the codes that are matched by predicates in i386.c. */
3008
3009 #define PREDICATE_CODES \
3010 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3011 SYMBOL_REF, LABEL_REF, CONST}}, \
3012 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3013 SYMBOL_REF, LABEL_REF, CONST}}, \
3014 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3015 SYMBOL_REF, LABEL_REF, CONST}}, \
3016 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3017 SYMBOL_REF, LABEL_REF, CONST}}, \
3018 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3019 SYMBOL_REF, LABEL_REF, CONST}}, \
3020 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3021 SYMBOL_REF, LABEL_REF, CONST}}, \
3022 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3023 SYMBOL_REF, LABEL_REF}}, \
3024 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3025 {"const_int_1_operand", {CONST_INT}}, \
3026 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3027 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3028 LABEL_REF, SUBREG, REG, MEM}}, \
3029 {"pic_symbolic_operand", {CONST}}, \
3030 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3031 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3032 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3033 {"const1_operand", {CONST_INT}}, \
3034 {"const248_operand", {CONST_INT}}, \
3035 {"incdec_operand", {CONST_INT}}, \
3036 {"mmx_reg_operand", {REG}}, \
3037 {"reg_no_sp_operand", {SUBREG, REG}}, \
3038 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3039 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3040 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3041 {"q_regs_operand", {SUBREG, REG}}, \
3042 {"non_q_regs_operand", {SUBREG, REG}}, \
3043 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3044 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3045 GE, UNGE, LTGT, UNEQ}}, \
3046 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3047 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3048 }}, \
3049 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3050 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3051 UNGE, UNGT, LTGT, UNEQ }}, \
3052 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3053 {"ext_register_operand", {SUBREG, REG}}, \
3054 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3055 {"mult_operator", {MULT}}, \
3056 {"div_operator", {DIV}}, \
3057 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3058 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3059 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3060 LSHIFTRT, ROTATERT}}, \
3061 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3062 {"memory_displacement_operand", {MEM}}, \
3063 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3064 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3065 {"long_memory_operand", {MEM}},
3066
3067 /* A list of predicates that do special things with modes, and so
3068 should not elicit warnings for VOIDmode match_operand. */
3069
3070 #define SPECIAL_MODE_PREDICATES \
3071 "ext_register_operand",
3072 \f
3073 /* CM_32 is used by 32bit ABI
3074 CM_SMALL is small model assuming that all code and data fits in the first
3075 31bits of address space.
3076 CM_KERNEL is model assuming that all code and data fits in the negative
3077 31bits of address space.
3078 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3079 space. Size of data is unlimited.
3080 CM_LARGE is model making no assumptions about size of particular sections.
3081
3082 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3083 tables first in 31bits of address space.
3084 */
3085 enum cmodel {
3086 CM_32,
3087 CM_SMALL,
3088 CM_KERNEL,
3089 CM_MEDIUM,
3090 CM_LARGE,
3091 CM_SMALL_PIC
3092 };
3093
3094 /* Size of the RED_ZONE area. */
3095 #define RED_ZONE_SIZE 128
3096 /* Reserved area of the red zone for temporaries. */
3097 #define RED_ZONE_RESERVE 8
3098 extern const char *ix86_debug_arg_string, *ix86_debug_addr_string;
3099
3100 enum asm_dialect {
3101 ASM_ATT,
3102 ASM_INTEL
3103 };
3104 extern const char *ix86_asm_string;
3105 extern enum asm_dialect ix86_asm_dialect;
3106 /* Value of -mcmodel specified by user. */
3107 extern const char *ix86_cmodel_string;
3108 extern enum cmodel ix86_cmodel;
3109 \f
3110 /* Variables in i386.c */
3111 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3112 extern const char *ix86_arch_string; /* for -march=<xxx> */
3113 extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
3114 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3115 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3116 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3117 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3118 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3119 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3120 extern int ix86_regparm; /* ix86_regparm_string as a number */
3121 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3122 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3123 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */
3124 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3125 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3126 \f
3127 /* To properly truncate FP values into integers, we need to set i387 control
3128 word. We can't emit proper mode switching code before reload, as spills
3129 generated by reload may truncate values incorrectly, but we still can avoid
3130 redundant computation of new control word by the mode switching pass.
3131 The fldcw instructions are still emitted redundantly, but this is probably
3132 not going to be noticeable problem, as most CPUs do have fast path for
3133 the sequence.
3134
3135 The machinery is to emit simple truncation instructions and split them
3136 before reload to instructions having USEs of two memory locations that
3137 are filled by this code to old and new control word.
3138
3139 Post-reload pass may be later used to eliminate the redundant fildcw if
3140 needed. */
3141
3142 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3143
3144 /* Define this macro if the port needs extra instructions inserted
3145 for mode switching in an optimizing compilation. */
3146
3147 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3148
3149 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3150 initializer for an array of integers. Each initializer element N
3151 refers to an entity that needs mode switching, and specifies the
3152 number of different modes that might need to be set for this
3153 entity. The position of the initializer in the initializer -
3154 starting counting at zero - determines the integer that is used to
3155 refer to the mode-switched entity in question. */
3156
3157 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3158
3159 /* ENTITY is an integer specifying a mode-switched entity. If
3160 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3161 return an integer value not larger than the corresponding element
3162 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3163 must be switched into prior to the execution of INSN. */
3164
3165 #define MODE_NEEDED(ENTITY, I) \
3166 (GET_CODE (I) == CALL_INSN \
3167 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3168 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3169 ? FP_CW_UNINITIALIZED \
3170 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3171 ? FP_CW_ANY \
3172 : FP_CW_STORED)
3173
3174 /* This macro specifies the order in which modes for ENTITY are
3175 processed. 0 is the highest priority. */
3176
3177 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3178
3179 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3180 is the set of hard registers live at the point where the insn(s)
3181 are to be inserted. */
3182
3183 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3184 ((MODE) == FP_CW_STORED \
3185 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3186 assign_386_stack_local (HImode, 2)), 0\
3187 : 0)
3188 \f
3189 /* Avoid renaming of stack registers, as doing so in combination with
3190 scheduling just increases amount of live registers at time and in
3191 the turn amount of fxch instructions needed.
3192
3193 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3194
3195 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3196 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
3197
3198 \f
3199 /*
3200 Local variables:
3201 version-control: t
3202 End:
3203 */
Mirror of the offical gcc git repository hosted at gcc.gnu.org