gcc/ChangeLog

   1 2024-01-09  Jeff Law  <jlaw@ventanamicro.com>
   2
   3         * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
   4         no less.
   5
   6 2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>
   7
   8         * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
   9
  10 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
  11
  12         * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
  13         restart_loop.
  14         (vectorizable_live_operation): Likewise.
  15
  16 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
  17
  18         PR tree-optimization/113199
  19         * tree-vect-loop.cc (vectorizable_live_operation_1): Use
  20         BIT_FIELD_REF.
  21
  22 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
  23
  24         PR target/113270
  25         * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
  26         * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
  27         GTY(()) declaration before the definition, drop GTY(()) drom the
  28         definition.
  29
  30 2024-01-09  Richard Biener  <rguenther@suse.de>
  31
  32         PR tree-optimization/113026
  33         * tree-vect-loop-manip.cc (vect_do_peeling): Remove
  34         redundant and wrong niter bound setting.  Move niter
  35         bound adjustment down.
  36
  37 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
  38
  39         PR middle-end/113163
  40         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
  41         Reject non-linear inductions that aren't supported.
  42
  43 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
  44
  45         * config/arc/arc.cc (arc_shift_alg): New enumerated type for
  46         left shift implementation strategies.
  47         (arc_shift_info): Type for each entry of the shift strategy table.
  48         (arc_shift_context_idx): Return a integer value for each code
  49         generation context, used as an index
  50         (arc_ashl_alg): Table indexed by context and shifted bit count.
  51         (arc_split_ashl): Use the arc_ashl_alg table to select SImode
  52         left shift implementation.
  53         (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
  54         provide accurate costs, when optimizing for speed or size.
  55
  56 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
  57
  58         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
  59
  60 2024-01-09  Julian Brown  <julian@codesourcery.com>
  61
  62         * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
  63         processed out before gimplification.
  64         * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
  65         * tree.def (OMP_ARRAY_SECTION): New tree code.
  66
  67 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
  68
  69         PR tree-optimization/113210
  70         * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
  71         value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
  72         INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
  73         minus 1.
  74
  75 2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>
  76
  77         PR rtl-optimization/113140
  78         * reorg.cc (fill_slots_from_thread): If we are to branch after the
  79         last instruction of the function, create an end label.
  80
  81 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
  82             Hongtao Liu  <hongtao.liu@intel.com>
  83
  84         PR target/112992
  85         * config/i386/i386-expand.cc
  86         (ix86_convert_const_wide_int_to_broadcast): Allow call to
  87         ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
  88         (ix86_broadcast_from_constant): Revert recent change; Return a
  89         suitable MEMREF independently of mode/target combinations.
  90         (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
  91         to decide whether expansion is possible/preferrable.  Only try
  92         forcing DImode constants to memory (and trying again) if calling
  93         ix86_expand_vector_init_duplicate fails with an DImode immediate
  94         constant.
  95         (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
  96         V4SImode for suitable immediate constants.
  97         <case E_V4DImode>: Try using V8SImode for suitable constants.
  98         <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
  99         <case E_V2HImode>: Likewise.
 100         <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
 101         <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
 102         <label widen>: Handle CONT_INTs via simplify_binary_operation.
 103         Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
 104         <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
 105         <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
 106         (ix86_expand_vector_init): Move try using a broadcast for all_same
 107         with ix86_expand_vector_init_duplicate before using constant pool.
 108
 109 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
 110
 111         * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
 112
 113 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
 114
 115         * config/arm/arm-cpus.in (cortex-m52): New cpu.
 116         * config/arm/arm-tables.opt: Regenerate.
 117         * config/arm/arm-tune.md: Regenerate.
 118
 119 2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>
 120
 121         * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
 122         (vec_init<mode><lasxhalf>): .. this, and extend to mode.
 123         (@vec_concatz<mode>): New insn pattern.
 124         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
 125         Handle VALS containing two vectors.
 126
 127 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 128
 129         * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
 130         (vundefined): Ditto.
 131
 132 2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>
 133
 134         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
 135                                 Add new function_base for crypto vector.
 136         (class bitmanip): Ditto.
 137         (class b_reverse):Ditto.
 138         (class vwsll):   Ditto.
 139         (class clmul):   Ditto.
 140         (class vg_nhab):  Ditto.
 141         (class crypto_vv):Ditto.
 142         (class crypto_vi):Ditto.
 143         (class vaeskf2_vsm3c):Ditto.
 144         (class vsm3me): Ditto.
 145         (BASE): Add BASE declaration for crypto vector.
 146         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
 147         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
 148                                 Add crypto vector intrinsic definition.
 149         (vbrev): Ditto.
 150         (vclz): Ditto.
 151         (vctz): Ditto.
 152         (vwsll): Ditto.
 153         (vandn): Ditto.
 154         (vbrev8): Ditto.
 155         (vrev8): Ditto.
 156         (vrol): Ditto.
 157         (vror): Ditto.
 158         (vclmul): Ditto.
 159         (vclmulh): Ditto.
 160         (vghsh): Ditto.
 161         (vgmul): Ditto.
 162         (vaesef): Ditto.
 163         (vaesem): Ditto.
 164         (vaesdf): Ditto.
 165         (vaesdm): Ditto.
 166         (vaesz): Ditto.
 167         (vaeskf1): Ditto.
 168         (vaeskf2): Ditto.
 169         (vsha2ms): Ditto.
 170         (vsha2ch): Ditto.
 171         (vsha2cl): Ditto.
 172         (vsm4k): Ditto.
 173         (vsm4r): Ditto.
 174         (vsm3me): Ditto.
 175         (vsm3c): Ditto.
 176         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
 177                                 Add new function_shape for crypto vector.
 178         (struct crypto_vi_def): Ditto.
 179         (struct crypto_vv_no_op_type_def): Ditto.
 180         (SHAPE): Add SHAPE declaration of crypto vector.
 181         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
 182         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
 183                                 Add new data type for crypto vector.
 184         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
 185         (vuint32mf2_t): Ditto.
 186         (vuint32m1_t): Ditto.
 187         (vuint32m2_t): Ditto.
 188         (vuint32m4_t): Ditto.
 189         (vuint32m8_t): Ditto.
 190         (vuint64m1_t): Ditto.
 191         (vuint64m2_t): Ditto.
 192         (vuint64m4_t): Ditto.
 193         (vuint64m8_t): Ditto.
 194         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
 195                                 Add new data struct for crypto vector.
 196         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
 197         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
 198         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
 199
 200 2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>
 201
 202         PR sanitizer/113251
 203         * varasm.cc (assemble_function_label_raw): Do not call
 204         asan_function_start () without the current function.
 205
 206 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
 207
 208         PR target/113225
 209         * btfout.cc (btf_collect_datasec): Skip creating BTF info for
 210         extern and kernel_helper attributed function decls.
 211
 212 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
 213
 214         * btfout.cc (output_btf_strs): Changed.
 215
 216 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
 217
 218         * config/gcn/mkoffload.cc (main): Handle gfx1100
 219         when setting the default XNACK.
 220
 221 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
 222
 223         * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
 224         * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
 225         (ASM_SPEC): Handle gfx1100.
 226         * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
 227         (enum gcn_isa): Add ISA_RDNA3.
 228         (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
 229         * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
 230         * config/gcn/gcn.cc (gcn_option_override,
 231         gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
 232         (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
 233         TARGET_RDNA2 to TARGET_RDNA2_PLUS.
 234         (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
 235         with gfx1100.
 236         * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
 237         (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
 238         __gfx1100__.
 239         * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
 240         * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
 241         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
 242         (isa_has_combined_avgprs, main): Handle gfx1100.
 243         * config/gcn/t-omp-device (isa): Add gfx1100.
 244
 245 2024-01-08  Richard Biener  <rguenther@suse.de>
 246
 247         * doc/invoke.texi (-mmovbe): Clarify.
 248
 249 2024-01-08  Richard Biener  <rguenther@suse.de>
 250
 251         PR tree-optimization/113026
 252         * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
 253         Avoid an epilog in more cases.
 254         * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
 255         epilogues niter upper bounds and estimates.
 256
 257 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
 258
 259         PR tree-optimization/113228
 260         * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
 261
 262 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
 263
 264         PR tree-optimization/113120
 265         * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
 266         large _BitInt zero INTEGER_CST PHI argument.
 267
 268 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
 269
 270         PR tree-optimization/113119
 271         * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
 272         both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
 273         is before REALPART_EXPR.
 274
 275 2024-01-08  Georg-Johann Lay  <avr@gjlay.de>
 276
 277         PR target/112952
 278         * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
 279         range when diagnosing attribute "io" and "io_low" are out of range.
 280         (avr_eval_addr_attrib): Don't ICE on empty address at that place.
 281         (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
 282         in contexts other than static storage.
 283         (avr_asm_output_aligned_decl_common): Move output of decls with
 284         attribute "address", "io", and "io_low" to...
 285         (avr_output_addr_attrib): ...this new function.
 286         (avr_asm_asm_output_aligned_bss): Remove output for decls with
 287         attribute "address", "io", and "io_low".
 288         (avr_encode_section_info): Rectify handling of decls with attribute
 289         "address", "io", and "io_low".
 290
 291 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
 292
 293         * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
 294         (elf_flags): Remove XNACK from the default value.
 295         (main): Set a default XNACK according to the arch.
 296
 297 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
 298
 299         * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
 300         (process_asm): Don't count avgprs.
 301
 302 2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>
 303
 304         * config/i386/i386.opt: Add supported sub-features.
 305         * doc/extend.texi: Add description for target attribute.
 306
 307 2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>
 308
 309         * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
 310
 311 2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
 312             Uros Bizjak  <ubizjak@gmail.com>
 313
 314         PR target/113231
 315         * config/i386/i386-features.cc (compute_convert_gain): Include
 316         the overhead of explicit load and store (movd) instructions when
 317         converting non-store scalar operations with memory destinations.
 318         Various indentation whitespace fixes.
 319
 320 2024-01-07  Tamar Christina  <tamar.christina@arm.com>
 321
 322         * config/arm/neon.md (cbranch<mode>4): New.
 323
 324 2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 325
 326         * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
 327
 328 2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>
 329
 330         * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
 331
 332 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 333
 334         PR target/113248
 335         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
 336         Update the MAX_SEW.
 337
 338 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 339
 340         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
 341         (variable_vectorized_p): Teach loop invariant.
 342         (has_unexpected_spills_p): Ditto.
 343
 344 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 345
 346         * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
 347         * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
 348         * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
 349
 350 2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>
 351
 352         PR target/113104
 353         * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
 354         (aarch64-vect-compare-costs): ...this.
 355         * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
 356         Replace with...
 357         (-param=aarch64-vect-compare-costs=): ...this new param.
 358         * config/aarch64/aarch64.cc (aarch64_override_options_internal):
 359         Don't disable it when vectorizing for Advanced SIMD only.
 360         (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
 361         whenever aarch64_vect_compare_costs is true.
 362
 363 2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>
 364
 365         * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
 366         Modify the method of determining the memory offset of [x]vld/[x]vst.
 367         (lasx_mxst_<lasxfmt_f>): Likewise.
 368         * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
 369         (loongarch_address_insns): Likewise.
 370         * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
 371         (lsx_st_<lsxfmt_f>): Likewise.
 372         * config/loongarch/predicates.md (aq10b_operand): Likewise.
 373         (aq10h_operand): Likewise.
 374         (aq10w_operand): Likewise.
 375         (aq10d_operand): Likewise.
 376
 377 2024-01-05  Alex Coplan  <alex.coplan@arm.com>
 378
 379         PR target/113217
 380         * config/aarch64/aarch64-ldp-fusion.cc
 381         (ldp_bb_info::try_fuse_pair): If the second access can throw,
 382         narrow the move range to exactly that insn.
 383
 384 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
 385
 386         * asan.cc (asan_function_start): Drop switch_to_section ().
 387         (asan_emit_stack_protection): Set .LASANPC alignment.
 388         * config/i386/i386.cc: Use assemble_function_label_raw ()
 389         instead of ASM_OUTPUT_LABEL ().
 390         * config/s390/s390.cc (s390_asm_output_function_label):
 391         Likewise.
 392         * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
 393         * final.cc (final_start_function_1): Drop
 394         asan_function_start ().
 395         * output.h (assemble_function_label_raw): New function.
 396         * varasm.cc (assemble_function_label_raw): Likewise.
 397
 398 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
 399
 400         * config/aarch64/aarch64.cc (aarch64_declare_function_name):
 401         Use ASM_OUTPUT_FUNCTION_LABEL ().
 402         * config/alpha/alpha.cc (alpha_start_function): Likewise.
 403         * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
 404         * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
 405         * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
 406         * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
 407         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
 408         * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
 409         * config/ia64/ia64.cc (ia64_start_function): Likewise.
 410         * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
 411         Likewise.
 412         * config/microblaze/microblaze.cc (microblaze_function_prologue):
 413         Likewise.
 414         * config/mips/mips.cc (mips_start_unique_function): Return the
 415         tree.
 416         (mips_start_function_definition): Use
 417         ASM_OUTPUT_FUNCTION_LABEL ().
 418         (mips_finish_stub): Pass the tree to
 419         mips_start_function_definition ().
 420         (mips16_build_function_stub): Likewise.
 421         (mips16_build_call_stub): Likewise.
 422         (mips_output_function_prologue): Likewise.
 423         * config/pa/pa.cc (pa_output_function_label): Use
 424         ASM_OUTPUT_FUNCTION_LABEL ().
 425         * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
 426         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
 427         Likewise.
 428         (rs6000_xcoff_declare_function_name): Likewise.
 429
 430 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
 431
 432         PR tree-optimization/113201
 433         * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
 434         replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
 435
 436 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
 437
 438         PR tree-optimization/90693
 439         * tree-ssa-math-opts.cc (match_single_bit_test): If
 440         tree_expr_nonzero_p (arg), remember it in the second argument to
 441         IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
 442         arg ^ (arg - 1) > arg - 1.
 443         * internal-fn.cc (expand_POPCOUNT): If second argument to
 444         IFN_POPCOUNT suggests arg is non-zero, try to expand it as
 445         arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
 446
 447 2024-01-05  Kito Cheng  <kito.cheng@sifive.com>
 448
 449         * config/riscv/riscv-v.cc (expand_load_store):
 450         Remove `value`.
 451         (expand_cond_len_op): Ditto.
 452         (expand_gather_scatter): Ditto.
 453         (expand_lanes_load_store): Ditto.
 454         (expand_fold_extract_last): Ditto.
 455
 456 2024-01-05  Pan Li  <pan2.li@intel.com>
 457
 458         Revert:
 459         2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
 460
 461         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
 462                                 Add new function_base for crypto vector.
 463         (class bitmanip): Ditto.
 464         (class b_reverse):Ditto.
 465         (class vwsll):   Ditto.
 466         (class clmul):   Ditto.
 467         (class vg_nhab):  Ditto.
 468         (class crypto_vv):Ditto.
 469         (class crypto_vi):Ditto.
 470         (class vaeskf2_vsm3c):Ditto.
 471         (class vsm3me): Ditto.
 472         (BASE): Add BASE declaration for crypto vector.
 473         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
 474         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
 475                                 Add crypto vector intrinsic definition.
 476         (vbrev): Ditto.
 477         (vclz): Ditto.
 478         (vctz): Ditto.
 479         (vwsll): Ditto.
 480         (vandn): Ditto.
 481         (vbrev8): Ditto.
 482         (vrev8): Ditto.
 483         (vrol): Ditto.
 484         (vror): Ditto.
 485         (vclmul): Ditto.
 486         (vclmulh): Ditto.
 487         (vghsh): Ditto.
 488         (vgmul): Ditto.
 489         (vaesef): Ditto.
 490         (vaesem): Ditto.
 491         (vaesdf): Ditto.
 492         (vaesdm): Ditto.
 493         (vaesz): Ditto.
 494         (vaeskf1): Ditto.
 495         (vaeskf2): Ditto.
 496         (vsha2ms): Ditto.
 497         (vsha2ch): Ditto.
 498         (vsha2cl): Ditto.
 499         (vsm4k): Ditto.
 500         (vsm4r): Ditto.
 501         (vsm3me): Ditto.
 502         (vsm3c): Ditto.
 503         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
 504                                 Add new function_shape for crypto vector.
 505         (struct crypto_vi_def): Ditto.
 506         (struct crypto_vv_no_op_type_def): Ditto.
 507         (SHAPE): Add SHAPE declaration of crypto vector.
 508         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
 509         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
 510                                 Add new data type for crypto vector.
 511         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
 512         (vuint32mf2_t): Ditto.
 513         (vuint32m1_t): Ditto.
 514         (vuint32m2_t): Ditto.
 515         (vuint32m4_t): Ditto.
 516         (vuint32m8_t): Ditto.
 517         (vuint64m1_t): Ditto.
 518         (vuint64m2_t): Ditto.
 519         (vuint64m4_t): Ditto.
 520         (vuint64m8_t): Ditto.
 521         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
 522                                 Add new data struct for crypto vector.
 523         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
 524         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
 525         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
 526
 527 2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
 528
 529         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
 530                                 Add new function_base for crypto vector.
 531         (class bitmanip): Ditto.
 532         (class b_reverse):Ditto.
 533         (class vwsll):   Ditto.
 534         (class clmul):   Ditto.
 535         (class vg_nhab):  Ditto.
 536         (class crypto_vv):Ditto.
 537         (class crypto_vi):Ditto.
 538         (class vaeskf2_vsm3c):Ditto.
 539         (class vsm3me): Ditto.
 540         (BASE): Add BASE declaration for crypto vector.
 541         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
 542         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
 543                                 Add crypto vector intrinsic definition.
 544         (vbrev): Ditto.
 545         (vclz): Ditto.
 546         (vctz): Ditto.
 547         (vwsll): Ditto.
 548         (vandn): Ditto.
 549         (vbrev8): Ditto.
 550         (vrev8): Ditto.
 551         (vrol): Ditto.
 552         (vror): Ditto.
 553         (vclmul): Ditto.
 554         (vclmulh): Ditto.
 555         (vghsh): Ditto.
 556         (vgmul): Ditto.
 557         (vaesef): Ditto.
 558         (vaesem): Ditto.
 559         (vaesdf): Ditto.
 560         (vaesdm): Ditto.
 561         (vaesz): Ditto.
 562         (vaeskf1): Ditto.
 563         (vaeskf2): Ditto.
 564         (vsha2ms): Ditto.
 565         (vsha2ch): Ditto.
 566         (vsha2cl): Ditto.
 567         (vsm4k): Ditto.
 568         (vsm4r): Ditto.
 569         (vsm3me): Ditto.
 570         (vsm3c): Ditto.
 571         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
 572                                 Add new function_shape for crypto vector.
 573         (struct crypto_vi_def): Ditto.
 574         (struct crypto_vv_no_op_type_def): Ditto.
 575         (SHAPE): Add SHAPE declaration of crypto vector.
 576         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
 577         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
 578                                 Add new data type for crypto vector.
 579         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
 580         (vuint32mf2_t): Ditto.
 581         (vuint32m1_t): Ditto.
 582         (vuint32m2_t): Ditto.
 583         (vuint32m4_t): Ditto.
 584         (vuint32m8_t): Ditto.
 585         (vuint64m1_t): Ditto.
 586         (vuint64m2_t): Ditto.
 587         (vuint64m4_t): Ditto.
 588         (vuint64m8_t): Ditto.
 589         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
 590                                 Add new data struct for crypto vector.
 591         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
 592         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
 593         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
 594
 595 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 596
 597         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
 598
 599 2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>
 600
 601         PR tree-optimization/113186
 602         * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
 603         Match `^` with the `==` for 1bit integral types.
 604         * match.pd (maybe_cmp): Allow for bit_xor for 1bit
 605         integral types.
 606
 607 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
 608
 609         * toplev.cc (general_init): Pass lang_mask to urlifier.
 610
 611 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
 612
 613         * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
 614         param.
 615         (diagnostic_context::make_option_url): Update for lang_mask param.
 616         * gcc-urlifier.cc: Include "opts.h" and "options.h".
 617         (gcc_urlifier::gcc_urlifier): Add lang_mask param.
 618         (gcc_urlifier::m_lang_mask): New field.
 619         (doc_urls): Make static.
 620         (gcc_urlifier::get_url_for_quoted_text): Use label_text.
 621         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
 622         Look for an option by name before trying a binary search in
 623         doc_urls.
 624         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
 625         (gcc_urlifier::get_url_suffix_for_option): New.
 626         (make_gcc_urlifier): Add lang_mask param.
 627         (selftest::gcc_urlifier_cc_tests): Update for above changes.
 628         Verify that a URL is found for "-fpack-struct".
 629         * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
 630         * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
 631         * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
 632         to make_gcc_urlifier.
 633         * opts-diagnostic.h (get_option_url): Add lang_mask param.
 634         * opts.cc (get_option_html_page): Remove special-casing for
 635         analyzer and LTO.
 636         (get_option_url_suffix): New.
 637         (get_option_url): Reimplement.
 638         (selftest::test_get_option_html_page): Rename to...
 639         (selftest::test_get_option_url_suffix): ...this and update for
 640         above changes.
 641         (selftest::opts_cc_tests): Update for renaming.
 642         * opts.h: Include "rich-location.h".
 643         (get_option_url_suffix): New decl.
 644
 645 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
 646
 647         * Makefile.in (ALL_OPT_URL_FILES): New.
 648         (GCC_OBJS): Add options-urls.o.
 649         (OBJS): Likewise.
 650         (OBJS-libcommon): Likewise.
 651         (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
 652         inputs to opt-gather.awk.
 653         (options-urls.cc): New Makefile target.
 654         * opt-functions.awk (url_suffix): New function.
 655         (lang_url_suffix): New function.
 656         * options-urls-cc-gen.awk: New file.
 657         * opts.h (get_opt_url_suffix): New decl.
 658
 659 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
 660
 661         * params.opt.urls: New file, autogenerated by
 662         regenerate-opt-urls.py.
 663
 664 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
 665
 666         * common.opt.urls: New file, autogenerated by
 667         regenerate-opt-urls.py.
 668         * config/aarch64/aarch64.opt.urls: Likewise.
 669         * config/alpha/alpha.opt.urls: Likewise.
 670         * config/alpha/elf.opt.urls: Likewise.
 671         * config/arc/arc-tables.opt.urls: Likewise.
 672         * config/arc/arc.opt.urls: Likewise.
 673         * config/arm/arm-tables.opt.urls: Likewise.
 674         * config/arm/arm.opt.urls: Likewise.
 675         * config/arm/vxworks.opt.urls: Likewise.
 676         * config/avr/avr.opt.urls: Likewise.
 677         * config/bpf/bpf.opt.urls: Likewise.
 678         * config/c6x/c6x-tables.opt.urls: Likewise.
 679         * config/c6x/c6x.opt.urls: Likewise.
 680         * config/cris/cris.opt.urls: Likewise.
 681         * config/cris/elf.opt.urls: Likewise.
 682         * config/csky/csky.opt.urls: Likewise.
 683         * config/csky/csky_tables.opt.urls: Likewise.
 684         * config/darwin.opt.urls: Likewise.
 685         * config/dragonfly.opt.urls: Likewise.
 686         * config/epiphany/epiphany.opt.urls: Likewise.
 687         * config/fr30/fr30.opt.urls: Likewise.
 688         * config/freebsd.opt.urls: Likewise.
 689         * config/frv/frv.opt.urls: Likewise.
 690         * config/ft32/ft32.opt.urls: Likewise.
 691         * config/fused-madd.opt.urls: Likewise.
 692         * config/g.opt.urls: Likewise.
 693         * config/gcn/gcn.opt.urls: Likewise.
 694         * config/gnu-user.opt.urls: Likewise.
 695         * config/h8300/h8300.opt.urls: Likewise.
 696         * config/hpux11.opt.urls: Likewise.
 697         * config/i386/cygming.opt.urls: Likewise.
 698         * config/i386/cygwin.opt.urls: Likewise.
 699         * config/i386/djgpp.opt.urls: Likewise.
 700         * config/i386/i386.opt.urls: Likewise.
 701         * config/i386/mingw-w64.opt.urls: Likewise.
 702         * config/i386/mingw.opt.urls: Likewise.
 703         * config/i386/nto.opt.urls: Likewise.
 704         * config/ia64/ia64.opt.urls: Likewise.
 705         * config/ia64/ilp32.opt.urls: Likewise.
 706         * config/ia64/vms.opt.urls: Likewise.
 707         * config/iq2000/iq2000.opt.urls: Likewise.
 708         * config/linux-android.opt.urls: Likewise.
 709         * config/linux.opt.urls: Likewise.
 710         * config/lm32/lm32.opt.urls: Likewise.
 711         * config/loongarch/loongarch.opt.urls: Likewise.
 712         * config/lynx.opt.urls: Likewise.
 713         * config/m32c/m32c.opt.urls: Likewise.
 714         * config/m32r/m32r.opt.urls: Likewise.
 715         * config/m68k/ieee.opt.urls: Likewise.
 716         * config/m68k/m68k-tables.opt.urls: Likewise.
 717         * config/m68k/m68k.opt.urls: Likewise.
 718         * config/m68k/uclinux.opt.urls: Likewise.
 719         * config/mcore/mcore.opt.urls: Likewise.
 720         * config/microblaze/microblaze.opt.urls: Likewise.
 721         * config/mips/mips-tables.opt.urls: Likewise.
 722         * config/mips/mips.opt.urls: Likewise.
 723         * config/mips/sde.opt.urls: Likewise.
 724         * config/mmix/mmix.opt.urls: Likewise.
 725         * config/mn10300/mn10300.opt.urls: Likewise.
 726         * config/moxie/moxie.opt.urls: Likewise.
 727         * config/msp430/msp430.opt.urls: Likewise.
 728         * config/nds32/nds32-elf.opt.urls: Likewise.
 729         * config/nds32/nds32-linux.opt.urls: Likewise.
 730         * config/nds32/nds32.opt.urls: Likewise.
 731         * config/netbsd-elf.opt.urls: Likewise.
 732         * config/netbsd.opt.urls: Likewise.
 733         * config/nios2/elf.opt.urls: Likewise.
 734         * config/nios2/nios2.opt.urls: Likewise.
 735         * config/nvptx/nvptx-gen.opt.urls: Likewise.
 736         * config/nvptx/nvptx.opt.urls: Likewise.
 737         * config/openbsd.opt.urls: Likewise.
 738         * config/or1k/elf.opt.urls: Likewise.
 739         * config/or1k/or1k.opt.urls: Likewise.
 740         * config/pa/pa-hpux.opt.urls: Likewise.
 741         * config/pa/pa-hpux1010.opt.urls: Likewise.
 742         * config/pa/pa-hpux1111.opt.urls: Likewise.
 743         * config/pa/pa-hpux1131.opt.urls: Likewise.
 744         * config/pa/pa.opt.urls: Likewise.
 745         * config/pa/pa64-hpux.opt.urls: Likewise.
 746         * config/pdp11/pdp11.opt.urls: Likewise.
 747         * config/pru/pru.opt.urls: Likewise.
 748         * config/riscv/riscv.opt.urls: Likewise.
 749         * config/rl78/rl78.opt.urls: Likewise.
 750         * config/rpath.opt.urls: Likewise.
 751         * config/rs6000/476.opt.urls: Likewise.
 752         * config/rs6000/aix64.opt.urls: Likewise.
 753         * config/rs6000/darwin.opt.urls: Likewise.
 754         * config/rs6000/linux64.opt.urls: Likewise.
 755         * config/rs6000/rs6000-tables.opt.urls: Likewise.
 756         * config/rs6000/rs6000.opt.urls: Likewise.
 757         * config/rs6000/sysv4.opt.urls: Likewise.
 758         * config/rtems.opt.urls: Likewise.
 759         * config/rx/elf.opt.urls: Likewise.
 760         * config/rx/rx.opt.urls: Likewise.
 761         * config/s390/s390.opt.urls: Likewise.
 762         * config/s390/tpf.opt.urls: Likewise.
 763         * config/sh/sh.opt.urls: Likewise.
 764         * config/sh/superh.opt.urls: Likewise.
 765         * config/sol2.opt.urls: Likewise.
 766         * config/sparc/long-double-switch.opt.urls: Likewise.
 767         * config/sparc/sparc.opt.urls: Likewise.
 768         * config/stormy16/stormy16.opt.urls: Likewise.
 769         * config/v850/v850.opt.urls: Likewise.
 770         * config/vax/elf.opt.urls: Likewise.
 771         * config/vax/vax.opt.urls: Likewise.
 772         * config/visium/visium.opt.urls: Likewise.
 773         * config/vms/vms.opt.urls: Likewise.
 774         * config/vxworks-smp.opt.urls: Likewise.
 775         * config/vxworks.opt.urls: Likewise.
 776         * config/xtensa/elf.opt.urls: Likewise.
 777         * config/xtensa/uclinux.opt.urls: Likewise.
 778         * config/xtensa/xtensa.opt.urls: Likewise.
 779         * config/bfin/bfin.opt.urls: New file.
 780
 781 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
 782
 783         * Makefile.in (OPT_URLS_HTML_DEPS): New.
 784         (regenerate-opt-urls): New target.
 785         (regenerate-opt-urls-unit-test): New target.
 786         * doc/options.texi (Option properties): Add UrlSuffix and
 787         description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
 788         * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
 789         reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
 790         and Makefile.in's OPT_URLS_HTML_DEPS.
 791         (Anatomy of a Target Back End): Add
 792         reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
 793         * regenerate-opt-urls.py: New file.
 794
 795 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
 796
 797         * diagnostic-format-sarif.cc
 798         (sarif_builder::make_logical_location_object): Convert to...
 799         (make_sarif_logical_location_object): ...this.
 800         (sarif_builder::set_any_logical_locs_arr): Update for above
 801         change.
 802         (sarif_builder::make_thread_flow_location_object): Call
 803         maybe_add_sarif_properties on each diagnostic_event.
 804         * diagnostic-format-sarif.h (class logical_location): New forward
 805         decl.
 806         (make_sarif_logical_location_object): New decl.
 807         * diagnostic-path.h (class sarif_object): New forward decl.
 808         (diagnostic_event::maybe_add_sarif_properties): New vfunc.
 809
 810 2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
 811             Patrick Lin  <patrick@andestech.com>
 812             Rufus Chen  <rufus@andestech.com>
 813             Monk Chiang  <monk.chiang@sifive.com>
 814
 815         * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
 816         with Nan-boxing value.
 817         * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
 818
 819 2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
 820             Jeff Law  <jlaw@ventanamicro.com>
 821
 822         PR rtl-optimization/104914
 823         * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
 824         a sign or zero extension is only required if the modified field
 825         overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
 826         targets, don't refer to the temporarily incorrectly extended value
 827         using a SUBREG, but instead generate an explicit TRUNCATE rtx.
 828
 829 2024-01-04  Pan Li  <pan2.li@intel.com>
 830
 831         Revert:
 832         2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 833
 834         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
 835
 836 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 837
 838         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
 839
 840 2024-01-04  Kito Cheng  <kito.cheng@sifive.com>
 841
 842         * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
 843         offset of fcsr.
 844
 845 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 846
 847         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
 848         (compute_nregs_for_mode): Refine LMUL.
 849         (max_number_of_live_regs): Ditto.
 850         (compute_estimated_lmul): Ditto.
 851         (has_unexpected_spills_p): Ditto.
 852
 853 2024-01-04  Li Wei  <liwei@loongson.cn>
 854
 855         * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
 856         Remove useless forward declaration.
 857         (loongarch_is_even_extraction): Remove useless forward declaration.
 858         (loongarch_try_expand_lsx_vshuf_const): Removed.
 859         (loongarch_expand_vec_perm_const_1): Merged.
 860         (loongarch_is_double_duplicate): Removed.
 861         (loongarch_is_center_extraction): Ditto.
 862         (loongarch_is_reversing_permutation): Ditto.
 863         (loongarch_is_di_misalign_extract): Ditto.
 864         (loongarch_is_si_misalign_extract): Ditto.
 865         (loongarch_is_lasx_lowpart_extract): Ditto.
 866         (loongarch_is_op_reverse_perm): Ditto.
 867         (loongarch_is_single_op_perm): Ditto.
 868         (loongarch_is_divisible_perm): Ditto.
 869         (loongarch_is_triple_stride_extract): Ditto.
 870         (loongarch_expand_vec_perm_const_2): Merged.
 871         (loongarch_expand_vec_perm_const): New.
 872         (loongarch_vectorize_vec_perm_const): Adjust.
 873
 874 2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>
 875
 876         * omp-general.cc: Fix comment typos and misplaced/confusing
 877         comments.  Delete redundant include of omp-general.h.
 878
 879 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
 880
 881         PR rtl-optimization/104914
 882         * config/mips/mips.md (insqisi_extended): New patterns.
 883         (inshisi_extended): Ditto.
 884
 885 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
 886
 887         * config/mips/mips.cc (mips_insn_cost): New function.
 888
 889 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
 890
 891         * config/mips/mips.md (perf_ratio): New attribute.
 892
 893 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 894
 895         PR target/113206
 896         PR target/113209
 897         * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
 898         (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
 899         blocks belong to infinite loop.
 900         (pre_vsetvl::emit_vsetvl): Remove fake edges.
 901         * config/riscv/t-riscv: Add a new include file.
 902
 903 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 904
 905         * config/riscv/vector.md: Fix indent.
 906
 907 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
 908
 909         * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
 910         OMP_CLAUSE__SIMDUID_.
 911         * tree.cc (omp_clause_num_ops): Update position of entry for
 912         OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
 913         (omp_clause_code_name): Likewise.
 914
 915 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
 916
 917         * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
 918         printing of FUNC_MAP/IND_FUNC_MAP labels.
 919
 920 2024-01-03  Jakub Jelinek  <jakub@redhat.com>
 921
 922         * gcc.cc (process_command): Update copyright notice dates.
 923         * gcov-dump.cc (print_version): Ditto.
 924         * gcov.cc (print_version): Ditto.
 925         * gcov-tool.cc (print_version): Ditto.
 926         * gengtype.cc (create_file): Ditto.
 927         * doc/cpp.texi: Bump @copying's copyright year.
 928         * doc/cppinternals.texi: Ditto.
 929         * doc/gcc.texi: Ditto.
 930         * doc/gccint.texi: Ditto.
 931         * doc/gcov.texi: Ditto.
 932         * doc/install.texi: Ditto.
 933         * doc/invoke.texi: Ditto.
 934
 935 2024-01-03  Xi Ruoyao  <xry111@xry111.site>
 936
 937         * config/loongarch/simd.md (fmax<mode>3): New define_insn.
 938         (fmin<mode>3): Likewise.
 939         (reduc_fmax_scal_<mode>3): New define_expand.
 940         (reduc_fmin_scal_<mode>3): Likewise.
 941
 942 2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 943
 944         PR target/113112
 945         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
 946         (max_number_of_live_regs): Ditto.
 947         (has_unexpected_spills_p): Ditto.
 948
 949 2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 950             Jin Ma  <jinma@linux.alibaba.com>
 951             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 952             Christoph Müllner  <christoph.muellner@vrull.eu>
 953
 954         * config/riscv/vector.md:
 955         Use vector_length_operand for vsetvl patterns.
 956
 957 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 958
 959         * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
 960         (expand_cond_len_op): Add simplification of dummy len and dummy mask.
 961
 962 2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>
 963
 964         * config/aarch64/aarch64-tuning-flags.def
 965         (AARCH64_EXTRA_TUNING_OPTION): New tuning option
 966         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
 967         * config/aarch64/aarch64.cc
 968         (aarch64_override_options_internal): Set
 969         param_fully_pipelined_fma according to tuning option.
 970         * config/aarch64/tuning_models/ampere1.h: Add
 971         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
 972         * config/aarch64/tuning_models/ampere1a.h: Likewise.
 973         * config/aarch64/tuning_models/ampere1b.h: Likewise.
 974
 975 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
 976
 977         * config/riscv/vector-crypto.md: Modify copyright year.
 978
 979 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 980
 981         * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
 982
 983 2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>
 984
 985         * config.in: Regenerate.
 986         * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
 987         * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
 988         Added TLS Le Relax support.
 989         (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
 990         * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
 991         * configure: Regenerate.
 992         * configure.ac: Check if binutils supports TLS le relax.
 993
 994 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
 995
 996         * config/riscv/iterators.md: Add rotate insn name.
 997         * config/riscv/riscv.md: Add new insns name for crypto vector.
 998         * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
 999         * config/riscv/vector.md: Add the corresponding attr for crypto vector.
1000         * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
1001
1002 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1003
1004         PR target/113112
1005         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
1006         pointer type liveness count.
1007 \f
1008 Copyright (C) 2024 Free Software Foundation, Inc.
1009
1010 Copying and distribution of this file, with or without modification,
1011 are permitted in any medium without royalty provided the copyright
1012 notice and this notice are preserved.