1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
23 ;; ??? Should prepend a * to all pattern names which are not used.
24 ;; This will make the compiler smaller, and rebuilds after changes faster.
26 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
27 ;; sequences. Especially the sequences for arithmetic right shifts.
29 ;; ??? Should check all DImode patterns for consistency and usefulness.
31 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
32 ;; way to generate them.
34 ;; BSR is not generated by the compiler proper, but when relaxing, it
35 ;; generates .uses pseudo-ops that allow linker relaxation to create
36 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
38 ;; Special constraints for SH machine description:
45 ;; Special formats used for outputting SH instructions:
47 ;; %. -- print a .s if insn needs delay slot
48 ;; %@ -- print rte/rts if is/isn't an interrupt function
49 ;; %# -- output a nop if there is nothing to put in the delay slot
50 ;; %O -- print a constant without the #
51 ;; %R -- print the lsw reg of a double
52 ;; %S -- print the msw reg of a double
53 ;; %T -- print next word of a double REG or MEM
55 ;; Special predicates:
57 ;; arith_operand -- operand is valid source for arithmetic op
58 ;; arith_reg_operand -- operand is valid register for arithmetic op
59 ;; general_movdst_operand -- operand is valid move destination
60 ;; general_movsrc_operand -- operand is valid move source
61 ;; logical_operand -- operand is valid source for logical op
63 ;; -------------------------------------------------------------------------
65 ;; -------------------------------------------------------------------------
113 ;; These are used with unspec.
114 (UNSPEC_COMPACT_ARGS 0)
127 (UNSPEC_INIT_TRAMP 13)
140 (UNSPEC_DIV_INV_M0 30)
141 (UNSPEC_DIV_INV_M1 31)
142 (UNSPEC_DIV_INV_M2 32)
143 (UNSPEC_DIV_INV_M3 33)
144 (UNSPEC_DIV_INV20 34)
145 (UNSPEC_DIV_INV_TABLE 37)
153 ;; (unspec [VAL SHIFT] UNSPEC_EXTRACT_S16) computes (short) (VAL >> SHIFT).
154 ;; UNSPEC_EXTRACT_U16 is the unsigned equivalent.
155 (UNSPEC_EXTRACT_S16 43)
156 (UNSPEC_EXTRACT_U16 44)
158 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
161 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
162 (UNSPEC_PCREL_SYMOFF 46)
165 (UNSPEC_BUILTIN_STRLEN 47)
167 ;; These are used with unspec_volatile.
173 (UNSPECV_WINDOW_END 10)
174 (UNSPECV_CONST_END 11)
175 (UNSPECV_EH_RETURN 12)
177 (UNSPECV_SP_SWITCH_B 14)
178 (UNSPECV_SP_SWITCH_E 15)
181 ;; -------------------------------------------------------------------------
183 ;; -------------------------------------------------------------------------
188 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a,sh5"
189 (const (symbol_ref "sh_cpu_attr")))
191 (define_attr "endian" "big,little"
192 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
193 (const_string "little") (const_string "big"))))
195 ;; Indicate if the default fpu mode is single precision.
196 (define_attr "fpu_single" "yes,no"
197 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
198 (const_string "yes") (const_string "no"))))
200 (define_attr "fmovd" "yes,no"
201 (const (if_then_else (symbol_ref "TARGET_FMOVD")
202 (const_string "yes") (const_string "no"))))
204 (define_attr "pipe_model" "sh1,sh4,sh5media"
206 (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
207 (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
208 (const_string "sh1"))))
210 ;; cbranch conditional branch instructions
211 ;; jump unconditional jumps
212 ;; arith ordinary arithmetic
213 ;; arith3 a compound insn that behaves similarly to a sequence of
214 ;; three insns of type arith
215 ;; arith3b like above, but might end with a redirected branch
217 ;; load_si Likewise, SImode variant for general register.
218 ;; fload Likewise, but load to fp register.
220 ;; fstore floating point register to memory
221 ;; move general purpose register to register
222 ;; movi8 8-bit immediate to general purpose register
223 ;; mt_group other sh4 mt instructions
224 ;; fmove register to register, floating point
225 ;; smpy word precision integer multiply
226 ;; dmpy longword or doublelongword precision integer multiply
228 ;; pload load of pr reg, which can't be put into delay slot of rts
229 ;; prset copy register to pr reg, ditto
230 ;; pstore store of pr reg, which can't be put into delay slot of jsr
231 ;; prget copy pr to register, ditto
232 ;; pcload pc relative load of constant value
233 ;; pcfload Likewise, but load to fp register.
234 ;; pcload_si Likewise, SImode variant for general register.
235 ;; rte return from exception
236 ;; sfunc special function call with known used registers
237 ;; call function call
239 ;; fpscr_toggle toggle a bit in the fpscr
240 ;; fdiv floating point divide (or square root)
241 ;; gp_fpul move from general purpose register to fpul
242 ;; fpul_gp move from fpul to general purpose register
243 ;; mac_gp move from mac[lh] to general purpose register
244 ;; gp_mac move from general purpose register to mac[lh]
245 ;; mac_mem move from mac[lh] to memory
246 ;; mem_mac move from memory to mac[lh]
247 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
248 ;; ftrc_s fix_truncsfsi2_i4
249 ;; dfdiv double precision floating point divide (or square root)
250 ;; cwb ic_invalidate_line_i
251 ;; movua SH4a unaligned load
252 ;; fsrra square root reciprocal approximate
253 ;; fsca sine and cosine approximate
254 ;; tls_load load TLS related address
255 ;; arith_media SHmedia arithmetic, logical, and shift instructions
256 ;; cbranch_media SHmedia conditional branch instructions
257 ;; cmp_media SHmedia compare instructions
258 ;; dfdiv_media SHmedia double precision divide and square root
259 ;; dfmul_media SHmedia double precision multiply instruction
260 ;; dfparith_media SHmedia double precision floating point arithmetic
261 ;; dfpconv_media SHmedia double precision floating point conversions
262 ;; dmpy_media SHmedia longword multiply
263 ;; fcmp_media SHmedia floating point compare instructions
264 ;; fdiv_media SHmedia single precision divide and square root
265 ;; fload_media SHmedia floating point register load instructions
266 ;; fmove_media SHmedia floating point register moves (inc. fabs and fneg)
267 ;; fparith_media SHmedia single precision floating point arithmetic
268 ;; fpconv_media SHmedia single precision floating point conversions
269 ;; fstore_media SHmedia floating point register store instructions
270 ;; gettr_media SHmedia gettr instruction
271 ;; invalidate_line_media SHmedia invalidate_line sequence
272 ;; jump_media SHmedia unconditional branch instructions
273 ;; load_media SHmedia general register load instructions
274 ;; pt_media SHmedia pt instruction (expanded by assembler)
275 ;; ptabs_media SHmedia ptabs instruction
276 ;; store_media SHmedia general register store instructions
277 ;; mcmp_media SHmedia multimedia compare, absolute, saturating ops
278 ;; mac_media SHmedia mac-style fixed point operations
279 ;; d2mpy_media SHmedia: two 32-bit integer multiplies
280 ;; atrans_media SHmedia approximate transcendental functions
281 ;; ustore_media SHmedia unaligned stores
282 ;; nil no-op move, will be deleted.
285 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
286 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
287 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
288 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
289 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
290 arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,
291 dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,
292 fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,
293 jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,
294 d2mpy_media,atrans_media,ustore_media,nil,other"
295 (const_string "other"))
297 ;; We define a new attribute namely "insn_class".We use
298 ;; this for the DFA based pipeline description.
300 ;; mt_group SH4 "mt" group instructions.
302 ;; ex_group SH4 "ex" group instructions.
304 ;; ls_group SH4 "ls" group instructions.
306 (define_attr "insn_class"
307 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
308 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
309 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
310 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
311 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
312 (eq_attr "type" "cbranch,jump") (const_string "br_group")
313 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
314 (const_string "fe_group")
315 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
316 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
317 gp_mac,mac_mem,mem_mac") (const_string "co_group")]
318 (const_string "none")))
320 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
321 ;; so these do not belong in an insn group, although they are modeled
322 ;; with their own define_insn_reservations.
324 ;; Indicate what precision must be selected in fpscr for this insn, if any.
325 (define_attr "fp_mode" "single,double,none" (const_string "none"))
327 ;; Indicate if the fpu mode is set by this instruction
328 ;; "unknown" must have the value as "none" in fp_mode, and means
329 ;; that the instruction/abi has left the processor in an unknown
331 ;; "none" means that nothing has changed and no mode is set.
332 ;; This attribute is only used for the Renesas ABI.
333 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
335 ; If a conditional branch destination is within -252..258 bytes away
336 ; from the instruction it can be 2 bytes long. Something in the
337 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
338 ; branches are initially assumed to be 16 bytes long.
339 ; In machine_dependent_reorg, we split all branches that are longer than
342 ;; The maximum range used for SImode constant pool entries is 1018. A final
343 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
344 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
345 ;; instruction around the pool table, 2 bytes of alignment before the table,
346 ;; and 30 bytes of alignment after the table. That gives a maximum total
347 ;; pool size of 1058 bytes.
348 ;; Worst case code/pool content size ratio is 1:2 (using asms).
349 ;; Thus, in the worst case, there is one instruction in front of a maximum
350 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
351 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
352 ;; If we have a forward branch, the initial table will be put after the
353 ;; unconditional branch.
355 ;; ??? We could do much better by keeping track of the actual pcloads within
356 ;; the branch range and in the pcload range in front of the branch range.
358 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
360 (define_attr "short_cbranch_p" "no,yes"
361 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
363 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
365 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
367 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
369 ] (const_string "no")))
371 (define_attr "med_branch_p" "no,yes"
372 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
375 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
377 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
380 ] (const_string "no")))
382 (define_attr "med_cbranch_p" "no,yes"
383 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
386 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
388 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
391 ] (const_string "no")))
393 (define_attr "braf_branch_p" "no,yes"
394 (cond [(match_test "! TARGET_SH2")
396 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
399 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
401 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
404 ] (const_string "no")))
406 (define_attr "braf_cbranch_p" "no,yes"
407 (cond [(match_test "! TARGET_SH2")
409 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
412 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
414 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
417 ] (const_string "no")))
419 ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
420 ;; For wider ranges, we need a combination of a code and a data part.
421 ;; If we can get a scratch register for a long range jump, the code
422 ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
423 ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
424 ;; long; otherwise, it must be 6 bytes long.
426 ;; All other instructions are two bytes long by default.
428 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
429 ;; but getattrtab doesn't understand this.
430 (define_attr "length" ""
431 (cond [(eq_attr "type" "cbranch")
432 (cond [(eq_attr "short_cbranch_p" "yes")
434 (eq_attr "med_cbranch_p" "yes")
436 (eq_attr "braf_cbranch_p" "yes")
438 ;; ??? using pc is not computed transitively.
439 (ne (match_dup 0) (match_dup 0))
441 (match_test "flag_pic")
444 (eq_attr "type" "jump")
445 (cond [(eq_attr "med_branch_p" "yes")
447 (and (match_test "prev_nonnote_insn (insn)")
448 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
450 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
451 (symbol_ref "code_for_indirect_jump_scratch"))))
452 (cond [(eq_attr "braf_branch_p" "yes")
454 (not (match_test "flag_pic"))
456 (match_test "TARGET_SH2")
457 (const_int 10)] (const_int 18))
458 (eq_attr "braf_branch_p" "yes")
460 ;; ??? using pc is not computed transitively.
461 (ne (match_dup 0) (match_dup 0))
463 (match_test "flag_pic")
466 (eq_attr "type" "pt_media")
467 (if_then_else (match_test "TARGET_SHMEDIA64")
468 (const_int 20) (const_int 12))
469 (and (eq_attr "type" "jump_media")
470 (match_test "TARGET_SH5_CUT2_WORKAROUND"))
472 ] (if_then_else (match_test "TARGET_SHMEDIA")
476 ;; DFA descriptions for the pipelines
479 (include "shmedia.md")
482 (include "iterators.md")
483 (include "predicates.md")
484 (include "constraints.md")
486 ;; Definitions for filling delay slots
488 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
490 (define_attr "banked" "yes,no"
491 (cond [(match_test "sh_loads_bankedreg_p (insn)")
492 (const_string "yes")]
493 (const_string "no")))
495 ;; ??? This should be (nil) instead of (const_int 0)
496 (define_attr "hit_stack" "yes,no"
497 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
499 (const_string "yes")))
501 (define_attr "interrupt_function" "no,yes"
502 (const (symbol_ref "current_function_interrupt")))
504 (define_attr "in_delay_slot" "yes,no"
505 (cond [(eq_attr "type" "cbranch") (const_string "no")
506 (eq_attr "type" "pcload,pcload_si") (const_string "no")
507 (eq_attr "type" "fpscr_toggle") (const_string "no")
508 (eq_attr "needs_delay_slot" "yes") (const_string "no")
509 (eq_attr "length" "2") (const_string "yes")
510 ] (const_string "no")))
512 (define_attr "cond_delay_slot" "yes,no"
513 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
514 ] (const_string "no")))
516 (define_attr "is_sfunc" ""
517 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
519 (define_attr "is_mac_media" ""
520 (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))
522 (define_attr "branch_zero" "yes,no"
523 (cond [(eq_attr "type" "!cbranch") (const_string "no")
524 (ne (symbol_ref "(next_active_insn (insn)\
525 == (prev_active_insn\
526 (XEXP (SET_SRC (PATTERN (insn)), 1))))\
527 && get_attr_length (next_active_insn (insn)) == 2")
529 (const_string "yes")]
530 (const_string "no")))
532 ;; SH4 Double-precision computation with double-precision result -
533 ;; the two halves are ready at different times.
534 (define_attr "dfp_comp" "yes,no"
535 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
536 (const_string "no")))
538 ;; Insns for which the latency of a preceding fp insn is decreased by one.
539 (define_attr "late_fp_use" "yes,no" (const_string "no"))
540 ;; And feeding insns for which this relevant.
541 (define_attr "any_fp_comp" "yes,no"
542 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
543 (const_string "yes")]
544 (const_string "no")))
546 (define_attr "any_int_load" "yes,no"
547 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
548 (const_string "yes")]
549 (const_string "no")))
551 (define_attr "highpart" "user, ignore, extend, depend, must_split"
552 (const_string "user"))
555 (eq_attr "needs_delay_slot" "yes")
556 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
558 ;; Since a normal return (rts) implicitly uses the PR register,
559 ;; we can't allow PR register loads in an rts delay slot.
560 ;; On the SH1* and SH2*, the rte instruction reads the return pc from the
561 ;; stack, and thus we can't put a pop instruction in its delay slot.
562 ;; On the SH3* and SH4*, the rte instruction does not use the stack, so a
563 ;; pop instruction can go in the delay slot, unless it references a banked
564 ;; register (the register bank is switched by rte).
566 (eq_attr "type" "return")
567 [(and (eq_attr "in_delay_slot" "yes")
568 (ior (and (eq_attr "interrupt_function" "no")
569 (eq_attr "type" "!pload,prset"))
570 (and (eq_attr "interrupt_function" "yes")
571 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no"))
572 (eq_attr "banked" "no"))))
575 ;; Since a call implicitly uses the PR register, we can't allow
576 ;; a PR register store in a jsr delay slot.
579 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
580 [(and (eq_attr "in_delay_slot" "yes")
581 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
583 ;; Say that we have annulled true branches, since this gives smaller and
584 ;; faster code when branches are predicted as not taken.
586 ;; ??? The non-annulled condition should really be "in_delay_slot",
587 ;; but insns that can be filled in non-annulled get priority over insns
588 ;; that can only be filled in anulled.
591 (and (eq_attr "type" "cbranch")
592 (match_test "TARGET_SH2"))
593 ;; SH2e has a hardware bug that pretty much prohibits the use of
594 ;; annulled delay slots.
595 [(eq_attr "cond_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
596 (not (eq_attr "cpu" "sh2e"))) (nil)])
598 ;; -------------------------------------------------------------------------
599 ;; SImode signed integer comparisons
600 ;; -------------------------------------------------------------------------
602 ;; Various patterns to generate the TST #imm, R0 instruction.
603 ;; Although this adds some pressure on the R0 register, it can potentially
604 ;; result in faster code, even if the operand has to be moved to R0 first.
605 ;; This is because on SH4 TST #imm, R0 and MOV Rm, Rn are both MT group
606 ;; instructions and thus will be executed in parallel. On SH4A TST #imm, R0
607 ;; is an EX group instruction but still can be executed in parallel with the
608 ;; MT group MOV Rm, Rn instruction.
610 ;; Usual TST #imm, R0 patterns for SI, HI and QI
611 ;; This is usually used for bit patterns other than contiguous bits
613 (define_insn "tstsi_t"
615 (eq:SI (and:SI (match_operand:SI 0 "logical_operand" "%z,r")
616 (match_operand:SI 1 "logical_operand" "K08,r"))
620 [(set_attr "type" "mt_group")])
622 (define_insn "tsthi_t"
624 (eq:SI (subreg:SI (and:HI (match_operand:HI 0 "logical_operand" "%z")
625 (match_operand 1 "const_int_operand")) 0)
628 && CONST_OK_FOR_K08 (INTVAL (operands[1]))"
630 [(set_attr "type" "mt_group")])
632 (define_insn "tstqi_t"
634 (eq:SI (subreg:SI (and:QI (match_operand:QI 0 "logical_operand" "%z")
635 (match_operand 1 "const_int_operand")) 0)
638 && (CONST_OK_FOR_K08 (INTVAL (operands[1]))
639 || CONST_OK_FOR_I08 (INTVAL (operands[1])))"
641 operands[1] = GEN_INT (INTVAL (operands[1]) & 255);
644 [(set_attr "type" "mt_group")])
646 ;; Test low QI subreg against zero.
647 ;; This avoids unnecessary zero extension before the test.
648 (define_insn "*tstqi_t_zero"
650 (eq:SI (match_operand:QI 0 "logical_operand" "z") (const_int 0)))]
653 [(set_attr "type" "mt_group")])
655 ;; This pattern might be risky because it also tests the upper bits and not
656 ;; only the subreg. However, it seems that combine will get to this only
657 ;; when testing sign/zero extended values. In this case the extended upper
658 ;; bits do not matter.
659 (define_insn "*tst<mode>_t_zero"
663 (and:SI (match_operand:SI 0 "arith_reg_operand" "%r")
664 (match_operand:SI 1 "arith_reg_operand" "r")) <lowpart_le>)
666 "TARGET_SH1 && TARGET_LITTLE_ENDIAN"
668 [(set_attr "type" "mt_group")])
670 (define_insn "*tst<mode>_t_zero"
674 (and:SI (match_operand:SI 0 "arith_reg_operand" "%r")
675 (match_operand:SI 1 "arith_reg_operand" "r")) <lowpart_be>)
677 "TARGET_SH1 && TARGET_BIG_ENDIAN"
679 [(set_attr "type" "mt_group")])
681 ;; Extract LSB, negate and store in T bit.
682 (define_insn "tstsi_t_and_not"
684 (and:SI (not:SI (match_operand:SI 0 "logical_operand" "z"))
688 [(set_attr "type" "mt_group")])
690 ;; Extract contiguous bits and compare them against zero.
691 (define_insn "tst<mode>_t_zero_extract_eq"
693 (eq:SI (zero_extract:SI (match_operand:QIHISIDI 0 "logical_operand" "z")
694 (match_operand:SI 1 "const_int_operand")
695 (match_operand:SI 2 "const_int_operand"))
698 && CONST_OK_FOR_K08 (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]))"
700 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
703 [(set_attr "type" "mt_group")])
705 ;; This split is required when testing bits in a QI subreg.
710 (zero_extract:SI (match_operand 0 "logical_operand")
711 (match_operand 1 "const_int_operand")
712 (match_operand 2 "const_int_operand"))
713 (match_operand 3 "const_int_operand")
717 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
718 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
719 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 3))
722 if (GET_MODE (operands[0]) == QImode)
723 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
726 ;; Extract single bit, negate and store it in the T bit.
727 ;; Not used for SH4A.
728 (define_insn "tstsi_t_zero_extract_xor"
730 (zero_extract:SI (xor:SI (match_operand:SI 0 "logical_operand" "z")
731 (match_operand:SI 3 "const_int_operand"))
732 (match_operand:SI 1 "const_int_operand")
733 (match_operand:SI 2 "const_int_operand")))]
735 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
736 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
738 [(set_attr "type" "mt_group")])
740 ;; Extract single bit, negate and store it in the T bit.
741 ;; Used for SH4A little endian.
742 (define_insn "tstsi_t_zero_extract_subreg_xor_little"
745 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
746 (match_operand:SI 3 "const_int_operand")) 0)
747 (match_operand:SI 1 "const_int_operand")
748 (match_operand:SI 2 "const_int_operand")))]
749 "TARGET_SH1 && TARGET_LITTLE_ENDIAN
750 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
751 == (INTVAL (operands[3]) & 255)
752 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
754 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
757 [(set_attr "type" "mt_group")])
759 ;; Extract single bit, negate and store it in the T bit.
760 ;; Used for SH4A big endian.
761 (define_insn "tstsi_t_zero_extract_subreg_xor_big"
764 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
765 (match_operand:SI 3 "const_int_operand")) 3)
766 (match_operand:SI 1 "const_int_operand")
767 (match_operand:SI 2 "const_int_operand")))]
768 "TARGET_SH1 && TARGET_BIG_ENDIAN
769 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
770 == (INTVAL (operands[3]) & 255)
771 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
773 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
776 [(set_attr "type" "mt_group")])
778 (define_insn "cmpeqsi_t"
780 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
781 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
787 [(set_attr "type" "mt_group")])
789 ;; FIXME: For some reason, on SH4A and SH2A combine fails to simplify this
790 ;; pattern by itself. What this actually does is:
791 ;; x == 0: (1 >> 0-0) & 1 = 1
792 ;; x != 0: (1 >> 0-x) & 1 = 0
793 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
794 (define_insn_and_split "*cmpeqsi_t"
798 (neg:SI (match_operand:SI 0 "arith_reg_operand" "r")))
803 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))])
805 (define_insn "cmpgtsi_t"
807 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
808 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
813 [(set_attr "type" "mt_group")])
815 (define_insn "cmpgesi_t"
817 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
818 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
823 [(set_attr "type" "mt_group")])
825 ;; FIXME: This is actually wrong. There is no way to literally move a
826 ;; general reg to t reg. Luckily, it seems that this pattern will be only
827 ;; used when the general reg is known be either '0' or '1' during combine.
828 ;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
829 ;; Due to interactions with other patterns, combine fails to pick the latter
830 ;; and invert the dependent logic.
831 (define_insn "*negtstsi"
832 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
835 [(set_attr "type" "mt_group")])
837 ;; Some integer sign comparison patterns can be realized with the div0s insn.
838 ;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31)
839 (define_insn "cmp_div0s_0"
841 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
842 (match_operand:SI 1 "arith_reg_operand" "r"))
846 [(set_attr "type" "arith")])
848 (define_insn "cmp_div0s_1"
850 (lt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
851 (match_operand:SI 1 "arith_reg_operand" "r"))
855 [(set_attr "type" "arith")])
857 (define_insn_and_split "*cmp_div0s_0"
858 [(set (match_operand:SI 0 "arith_reg_dest" "")
859 (lshiftrt:SI (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
860 (match_operand:SI 2 "arith_reg_operand" ""))
862 (clobber (reg:SI T_REG))]
867 (lshiftrt:SI (xor:SI (match_dup 1) (match_dup 2)) (const_int 31)))
868 (set (match_dup 0) (reg:SI T_REG))])
870 (define_insn "*cmp_div0s_0"
872 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
874 (ge:SI (match_operand:SI 1 "arith_reg_operand")
878 [(set_attr "type" "arith")])
880 (define_insn_and_split "*cmp_div0s_1"
881 [(set (match_operand:SI 0 "arith_reg_dest" "")
882 (ge:SI (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
883 (match_operand:SI 2 "arith_reg_operand" ""))
885 (clobber (reg:SI T_REG))]
888 "&& can_create_pseudo_p ()"
890 ;; We have to go through the movnegt expander here which will handle the
891 ;; SH2A vs non-SH2A cases.
893 emit_insn (gen_cmp_div0s_1 (operands[1], operands[2]));
894 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
898 (define_insn_and_split "*cmp_div0s_1"
900 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
901 (match_operand:SI 1 "arith_reg_operand" ""))
905 "&& can_create_pseudo_p ()"
906 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 0) (match_dup 1))
908 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
910 (define_insn_and_split "*cmp_div0s_1"
912 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
914 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
918 "&& can_create_pseudo_p ()"
919 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 0) (match_dup 1))
921 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
923 ;; -------------------------------------------------------------------------
924 ;; SImode compare and branch
925 ;; -------------------------------------------------------------------------
927 (define_expand "cbranchsi4"
929 (if_then_else (match_operator 0 "comparison_operator"
930 [(match_operand:SI 1 "arith_operand" "")
931 (match_operand:SI 2 "arith_operand" "")])
932 (label_ref (match_operand 3 "" ""))
934 (clobber (reg:SI T_REG))]
938 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
939 operands[2], operands[3]));
941 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1);
946 ;; Combine patterns to invert compare and branch operations for which we
947 ;; don't have actual comparison insns. These patterns are used in cases
948 ;; which appear after the initial cbranchsi expansion, which also does
949 ;; some condition inversion.
952 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
953 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
954 (label_ref (match_operand 2))
956 (clobber (reg:SI T_REG))]
958 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1)))
959 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
960 (label_ref (match_dup 2))
963 ;; FIXME: Similar to the *cmpeqsi_t pattern above, for some reason, on SH4A
964 ;; and SH2A combine fails to simplify this pattern by itself.
965 ;; What this actually does is:
966 ;; x == 0: (1 >> 0-0) & 1 = 1
967 ;; x != 0: (1 >> 0-x) & 1 = 0
968 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
972 (eq (and:SI (lshiftrt:SI
974 (neg:SI (match_operand:SI 0 "arith_reg_operand" "")))
977 (label_ref (match_operand 2))
979 (clobber (reg:SI T_REG))]
981 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))
982 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
983 (label_ref (match_dup 2))
986 ;; FIXME: These could probably use code iterators for the compare op.
989 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
990 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
991 (label_ref (match_operand 2))
993 (clobber (reg:SI T_REG))]
995 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1)))
996 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
997 (label_ref (match_dup 2))
1002 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "")
1003 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1004 (label_ref (match_operand 2))
1006 (clobber (reg:SI T_REG))]
1008 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1)))
1009 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1010 (label_ref (match_dup 2))
1015 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "")
1016 (match_operand:SI 1 "arith_reg_operand" ""))
1017 (label_ref (match_operand 2))
1019 (clobber (reg:SI T_REG))]
1021 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1)))
1022 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1023 (label_ref (match_dup 2))
1028 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "")
1029 (match_operand:SI 1 "arith_reg_operand" ""))
1030 (label_ref (match_operand 2))
1032 (clobber (reg:SI T_REG))]
1034 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1)))
1035 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1036 (label_ref (match_dup 2))
1039 ;; Compare and branch combine patterns for div0s comparisons.
1040 (define_insn_and_split "*cbranch_div0s"
1042 (if_then_else (lt (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
1043 (match_operand:SI 1 "arith_reg_operand" ""))
1045 (label_ref (match_operand 2))
1047 (clobber (reg:SI T_REG))]
1051 [(set (reg:SI T_REG)
1052 (lt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 0)))
1054 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1055 (label_ref (match_dup 2))
1058 (define_insn_and_split "*cbranch_div0s"
1060 (if_then_else (ge (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
1061 (match_operand:SI 1 "arith_reg_operand" ""))
1063 (label_ref (match_operand 2))
1065 (clobber (reg:SI T_REG))]
1069 [(set (reg:SI T_REG)
1070 (lt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 0)))
1072 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1073 (label_ref (match_dup 2))
1076 ;; Conditional move combine pattern for div0s comparisons.
1077 ;; This is used when TARGET_PRETEND_CMOVE is in effect.
1078 (define_insn_and_split "*movsicc_div0s"
1079 [(set (match_operand:SI 0 "arith_reg_dest" "")
1080 (if_then_else:SI (ge (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
1081 (match_operand:SI 2 "arith_reg_operand" ""))
1083 (match_operand:SI 3 "arith_reg_operand" "")
1084 (match_operand:SI 4 "general_movsrc_operand" "")))
1085 (clobber (reg:SI T_REG))]
1086 "TARGET_PRETEND_CMOVE"
1089 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 1) (match_dup 2))
1092 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1096 (define_insn_and_split "*movsicc_div0s"
1097 [(set (match_operand:SI 0 "arith_reg_dest")
1098 (if_then_else:SI (eq (lshiftrt:SI
1099 (match_operand:SI 1 "arith_reg_operand")
1102 (match_operand:SI 2 "arith_reg_operand")
1104 (match_operand:SI 3 "arith_reg_operand")
1105 (match_operand:SI 4 "general_movsrc_operand")))
1106 (clobber (reg:SI T_REG))]
1107 "TARGET_PRETEND_CMOVE"
1110 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 1) (match_dup 2))
1113 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1117 ;; -------------------------------------------------------------------------
1118 ;; SImode unsigned integer comparisons
1119 ;; -------------------------------------------------------------------------
1121 ;; Usually comparisons of 'unsigned int >= 0' are optimized away completely.
1122 ;; However, especially when optimizations are off (e.g. -O0) such comparisons
1123 ;; might remain and we have to handle them. If the '>= 0' case wasn't
1124 ;; handled here, something else would just load a '0' into the second operand
1125 ;; and do the comparison. We can do slightly better by just setting the
1127 (define_insn_and_split "cmpgeusi_t"
1128 [(set (reg:SI T_REG)
1129 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1130 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))]
1133 "&& satisfies_constraint_Z (operands[1])"
1134 [(set (reg:SI T_REG) (const_int 1))]
1136 [(set_attr "type" "mt_group")])
1138 (define_insn "cmpgtusi_t"
1139 [(set (reg:SI T_REG)
1140 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1141 (match_operand:SI 1 "arith_reg_operand" "r")))]
1144 [(set_attr "type" "mt_group")])
1146 ;; -------------------------------------------------------------------------
1147 ;; DImode compare and branch
1148 ;; -------------------------------------------------------------------------
1150 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
1151 ;; Therefore, we aim to have a set of three branches that go straight to the
1152 ;; destination, i.e. only one of them is taken at any one time.
1153 ;; This mechanism should also be slightly better for the sh4-200.
1155 (define_expand "cbranchdi4"
1157 (if_then_else (match_operator 0 "comparison_operator"
1158 [(match_operand:DI 1 "arith_operand" "")
1159 (match_operand:DI 2 "arith_operand" "")])
1160 (label_ref (match_operand 3 "" ""))
1162 (clobber (match_dup 4))
1163 (clobber (reg:SI T_REG))]
1164 "TARGET_CBRANCHDI4 || TARGET_SH2 || TARGET_SHMEDIA"
1166 enum rtx_code comparison;
1170 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
1171 operands[2], operands[3]));
1174 else if (!TARGET_CBRANCHDI4)
1176 sh_emit_compare_and_branch (operands, DImode);
1181 if (expand_cbranchdi4 (operands, LAST_AND_UNUSED_RTX_CODE))
1184 comparison = prepare_cbranch_operands (operands, DImode,
1185 LAST_AND_UNUSED_RTX_CODE);
1186 if (comparison != GET_CODE (operands[0]))
1188 = gen_rtx_fmt_ee (comparison, VOIDmode, operands[1], operands[2]);
1189 operands[4] = gen_rtx_SCRATCH (SImode);
1193 (define_insn_and_split "cbranchdi4_i"
1195 (if_then_else (match_operator 0 "comparison_operator"
1196 [(match_operand:DI 1 "arith_operand" "r,r")
1197 (match_operand:DI 2 "arith_operand" "rN,I08")])
1198 (label_ref (match_operand 3 "" ""))
1200 (clobber (match_scratch:SI 4 "=X,&r"))
1201 (clobber (reg:SI T_REG))]
1204 "&& reload_completed"
1207 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
1212 ;; -------------------------------------------------------------------------
1213 ;; DImode signed integer comparisons
1214 ;; -------------------------------------------------------------------------
1217 [(set (reg:SI T_REG)
1218 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
1219 (match_operand:DI 1 "arith_operand" "r"))
1223 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
1226 [(set_attr "length" "6")
1227 (set_attr "type" "arith3b")])
1229 (define_insn "cmpeqdi_t"
1230 [(set (reg:SI T_REG)
1231 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1232 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
1235 static const char* alt[] =
1242 "cmp/eq %S1,%S0" "\n"
1244 " cmp/eq %R1,%R0" "\n"
1247 return alt[which_alternative];
1249 [(set_attr "length" "6")
1250 (set_attr "type" "arith3b")])
1253 [(set (reg:SI T_REG)
1254 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
1255 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
1256 ;; If we applied this split when not optimizing, it would only be
1257 ;; applied during the machine-dependent reorg, when no new basic blocks
1259 "TARGET_SH1 && reload_completed && optimize"
1260 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
1261 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1262 (label_ref (match_dup 6))
1264 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
1267 operands[2] = gen_highpart (SImode, operands[0]);
1268 operands[3] = operands[1] == const0_rtx
1270 : gen_highpart (SImode, operands[1]);
1271 operands[4] = gen_lowpart (SImode, operands[0]);
1272 operands[5] = gen_lowpart (SImode, operands[1]);
1273 operands[6] = gen_label_rtx ();
1276 (define_insn "cmpgtdi_t"
1277 [(set (reg:SI T_REG)
1278 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1279 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1282 static const char* alt[] =
1284 "cmp/eq %S1,%S0" "\n"
1286 " cmp/gt %S1,%S0" "\n"
1287 " cmp/hi %R1,%R0" "\n"
1293 " cmp/hi %S0,%R0" "\n"
1296 return alt[which_alternative];
1298 [(set_attr "length" "8")
1299 (set_attr "type" "arith3")])
1301 (define_insn "cmpgedi_t"
1302 [(set (reg:SI T_REG)
1303 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1304 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1307 static const char* alt[] =
1309 "cmp/eq %S1,%S0" "\n"
1311 " cmp/ge %S1,%S0" "\n"
1312 " cmp/hs %R1,%R0" "\n"
1317 return alt[which_alternative];
1319 [(set_attr "length" "8,2")
1320 (set_attr "type" "arith3,mt_group")])
1322 ;; -------------------------------------------------------------------------
1323 ;; DImode unsigned integer comparisons
1324 ;; -------------------------------------------------------------------------
1326 (define_insn "cmpgeudi_t"
1327 [(set (reg:SI T_REG)
1328 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1329 (match_operand:DI 1 "arith_reg_operand" "r")))]
1332 return "cmp/eq %S1,%S0" "\n"
1334 " cmp/hs %S1,%S0" "\n"
1335 " cmp/hs %R1,%R0" "\n"
1338 [(set_attr "length" "8")
1339 (set_attr "type" "arith3")])
1341 (define_insn "cmpgtudi_t"
1342 [(set (reg:SI T_REG)
1343 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1344 (match_operand:DI 1 "arith_reg_operand" "r")))]
1347 return "cmp/eq %S1,%S0" "\n"
1349 " cmp/hi %S1,%S0" "\n"
1350 " cmp/hi %R1,%R0" "\n"
1353 [(set_attr "length" "8")
1354 (set_attr "type" "arith3")])
1356 (define_insn "cmpeqsi_media"
1357 [(set (match_operand:SI 0 "register_operand" "=r")
1358 (eq:SI (match_operand:SI 1 "logical_operand" "%r")
1359 (match_operand:SI 2 "cmp_operand" "Nr")))]
1362 [(set_attr "type" "cmp_media")])
1364 (define_insn "cmpeqdi_media"
1365 [(set (match_operand:SI 0 "register_operand" "=r")
1366 (eq:SI (match_operand:DI 1 "register_operand" "%r")
1367 (match_operand:DI 2 "cmp_operand" "Nr")))]
1370 [(set_attr "type" "cmp_media")])
1372 (define_insn "cmpgtsi_media"
1373 [(set (match_operand:SI 0 "register_operand" "=r")
1374 (gt:SI (match_operand:SI 1 "cmp_operand" "Nr")
1375 (match_operand:SI 2 "cmp_operand" "rN")))]
1377 "cmpgt %N1, %N2, %0"
1378 [(set_attr "type" "cmp_media")])
1380 (define_insn "cmpgtdi_media"
1381 [(set (match_operand:SI 0 "register_operand" "=r")
1382 (gt:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1383 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1385 "cmpgt %N1, %N2, %0"
1386 [(set_attr "type" "cmp_media")])
1388 (define_insn "cmpgtusi_media"
1389 [(set (match_operand:SI 0 "register_operand" "=r")
1390 (gtu:SI (match_operand:SI 1 "cmp_operand" "Nr")
1391 (match_operand:SI 2 "cmp_operand" "rN")))]
1393 "cmpgtu %N1, %N2, %0"
1394 [(set_attr "type" "cmp_media")])
1396 (define_insn "cmpgtudi_media"
1397 [(set (match_operand:SI 0 "register_operand" "=r")
1398 (gtu:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1399 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1401 "cmpgtu %N1, %N2, %0"
1402 [(set_attr "type" "cmp_media")])
1404 ; This pattern is for combine.
1405 (define_insn "*cmpne0sisi_media"
1406 [(set (match_operand:SI 0 "register_operand" "=r")
1407 (ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
1410 [(set_attr "type" "cmp_media")])
1412 ;; -------------------------------------------------------------------------
1413 ;; Conditional move instructions
1414 ;; -------------------------------------------------------------------------
1416 ;; The insn names may seem reversed, but note that cmveq performs the move
1417 ;; if op1 == 0, and cmvne does it if op1 != 0.
1419 (define_insn "movdicc_false"
1420 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1421 (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
1423 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1424 (match_operand:DI 3 "arith_reg_operand" "0")))]
1427 [(set_attr "type" "arith_media")])
1429 (define_insn "movdicc_true"
1430 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1431 (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
1433 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1434 (match_operand:DI 3 "arith_reg_operand" "0")))]
1437 [(set_attr "type" "arith_media")])
1440 [(set (match_operand:DI 0 "arith_reg_dest" "")
1441 (if_then_else:DI (match_operator 3 "equality_comparison_operator"
1442 [(match_operand:DI 1 "arith_reg_operand" "")
1444 (match_operand:DI 2 "arith_reg_dest" "")
1446 (set (match_dup 2) (match_dup 0))]
1447 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1449 (if_then_else:DI (match_dup 3) (match_dup 0) (match_dup 2)))]
1451 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1452 VOIDmode, operands[1], CONST0_RTX (DImode));
1456 [(set (match_operand:DI 0 "general_movdst_operand" "")
1457 (match_operand:DI 1 "arith_reg_or_0_operand" ""))
1458 (set (match_operand:DI 2 "arith_reg_dest" "")
1459 (if_then_else:DI (match_operator 4 "equality_comparison_operator"
1460 [(match_operand:DI 3 "arith_reg_operand" "")
1464 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1466 (if_then_else:DI (match_dup 4) (match_dup 1) (match_dup 2)))]
1469 (define_expand "movdicc"
1470 [(set (match_operand:DI 0 "register_operand" "")
1471 (if_then_else:DI (match_operand 1 "comparison_operator" "")
1472 (match_operand:DI 2 "register_operand" "")
1473 (match_operand:DI 3 "register_operand" "")))]
1476 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1477 && GET_MODE (XEXP (operands[1], 0)) == DImode
1478 && XEXP (operands[1], 1) == const0_rtx)
1482 if (!can_create_pseudo_p ())
1485 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1486 GET_CODE (operands[1]),
1487 XEXP (operands[1], 0),
1488 XEXP (operands[1], 1));
1494 ;; Add SImode variants for cmveq / cmvne to compensate for not promoting
1495 ;; SImode to DImode.
1496 (define_insn "movsicc_false"
1497 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1498 (if_then_else:SI (eq (match_operand:SI 1 "arith_reg_operand" "r")
1500 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1501 (match_operand:SI 3 "arith_reg_operand" "0")))]
1504 [(set_attr "type" "arith_media")])
1506 (define_insn "movsicc_true"
1507 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1508 (if_then_else:SI (ne (match_operand:SI 1 "arith_reg_operand" "r")
1510 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1511 (match_operand:SI 3 "arith_reg_operand" "0")))]
1514 [(set_attr "type" "arith_media")])
1517 [(set (match_operand:SI 0 "arith_reg_dest" "")
1518 (if_then_else:SI (match_operator 3 "equality_comparison_operator"
1519 [(match_operand:SI 1 "arith_reg_operand" "")
1521 (match_operand:SI 2 "arith_reg_dest" "")
1523 (set (match_dup 2) (match_dup 0))]
1524 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1526 (if_then_else:SI (match_dup 3) (match_dup 0) (match_dup 2)))]
1528 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1529 VOIDmode, operands[1], CONST0_RTX (SImode));
1533 [(set (match_operand:SI 0 "general_movdst_operand" "")
1534 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1535 (set (match_operand:SI 2 "arith_reg_dest" "")
1536 (if_then_else:SI (match_operator 4 "equality_comparison_operator"
1537 [(match_operand:SI 3 "arith_reg_operand" "")
1541 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])
1542 && (!REG_P (operands[1]) || GENERAL_REGISTER_P (REGNO (operands[1])))"
1544 (if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))]
1546 replace_rtx (operands[4], operands[0], operands[1]);
1550 [(set (match_operand 0 "any_register_operand" "")
1551 (match_operand 1 "any_register_operand" ""))
1552 (set (match_operand 2 "any_register_operand" "") (match_operand 3 "" ""))
1553 (set (match_operand 4 "" "") (match_operand 5 "" ""))]
1554 "(HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[2]))
1555 <= HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[0])))
1556 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])
1557 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[0])
1558 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[2])
1559 && ! reg_overlap_mentioned_p (operands[0], operands[3])
1560 && ! reg_overlap_mentioned_p (operands[2], operands[0])
1561 && ! reg_overlap_mentioned_p (operands[0], operands[1])
1562 && (REGNO_REG_CLASS (REGNO (operands[0]))
1563 == REGNO_REG_CLASS (REGNO (operands[2])))
1564 && (REGNO_REG_CLASS (REGNO (operands[1]))
1565 == REGNO_REG_CLASS (REGNO (operands[0])))"
1566 [(set (match_dup 0) (match_dup 3))
1567 (set (match_dup 4) (match_dup 5))]
1569 rtx set1, set2, insn2;
1570 rtx replacements[4];
1572 /* We want to replace occurrences of operands[0] with operands[1] and
1573 operands[2] with operands[0] in operands[4]/operands[5].
1574 Doing just two replace_rtx calls naively would result in the second
1575 replacement undoing all that the first did if operands[1] and operands[2]
1576 are identical, so we must do this simultaneously. */
1577 replacements[0] = operands[0];
1578 replacements[1] = operands[1];
1579 replacements[2] = operands[2];
1580 replacements[3] = operands[0];
1581 if (!replace_n_hard_rtx (operands[5], replacements, 2, 0)
1582 || !replace_n_hard_rtx (operands[4], replacements, 2, 0)
1583 || !replace_n_hard_rtx (operands[2], replacements, 2, 0))
1586 operands[5] = replace_n_hard_rtx (operands[5], replacements, 2, 1);
1587 replace_n_hard_rtx (operands[4], replacements, 2, 1);
1588 operands[2] = replace_n_hard_rtx (operands[2], replacements, 2, 1);
1589 /* The operands array is aliased to recog_data.operand, which gets
1590 clobbered by extract_insn, so finish with it now. */
1591 set1 = gen_rtx_SET (VOIDmode, operands[2], operands[3]);
1592 set2 = gen_rtx_SET (VOIDmode, operands[4], operands[5]);
1593 /* ??? The last insn might be a jump insn, but the generic peephole2 code
1594 always uses emit_insn. */
1595 /* Check that we don't violate matching constraints or earlyclobbers. */
1596 extract_insn (emit_insn (set1));
1597 if (! constrain_operands (1))
1599 insn2 = emit (set2);
1600 if (GET_CODE (insn2) == BARRIER)
1602 extract_insn (insn2);
1603 if (! constrain_operands (1))
1607 tmp = replacements[0];
1608 replacements[0] = replacements[1];
1609 replacements[1] = tmp;
1610 tmp = replacements[2];
1611 replacements[2] = replacements[3];
1612 replacements[3] = tmp;
1613 replace_n_hard_rtx (SET_DEST (set1), replacements, 2, 1);
1614 replace_n_hard_rtx (SET_DEST (set2), replacements, 2, 1);
1615 replace_n_hard_rtx (SET_SRC (set2), replacements, 2, 1);
1621 ;; The register allocator is rather clumsy in handling multi-way conditional
1622 ;; moves, so allow the combiner to make them, and we split them up after
1624 (define_insn_and_split "*movsicc_umin"
1625 [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
1626 (umin:SI (if_then_else:SI
1627 (eq (match_operand:SI 1 "arith_reg_operand" "r")
1629 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1630 (match_operand:SI 3 "register_operand" "0"))
1631 (match_operand:SI 4 "arith_reg_or_0_operand" "r")))
1632 (clobber (match_scratch:SI 5 "=&r"))]
1633 "TARGET_SHMEDIA && !can_create_pseudo_p ()"
1635 "TARGET_SHMEDIA && reload_completed"
1638 emit_insn (gen_movsicc_false (operands[0], operands[1], operands[2],
1640 emit_insn (gen_cmpgtusi_media (operands[5], operands[4], operands[0]));
1641 emit_insn (gen_movsicc_false (operands[0], operands[5], operands[4],
1646 (define_insn "*movsicc_t_false"
1647 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1648 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1649 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1650 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1651 "TARGET_PRETEND_CMOVE
1652 && (arith_reg_operand (operands[1], SImode)
1653 || (immediate_operand (operands[1], SImode)
1654 && satisfies_constraint_I08 (operands[1])))"
1660 [(set_attr "type" "mt_group,arith") ;; poor approximation
1661 (set_attr "length" "4")])
1663 (define_insn "*movsicc_t_true"
1664 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1665 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1666 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1667 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1668 "TARGET_PRETEND_CMOVE
1669 && (arith_reg_operand (operands[1], SImode)
1670 || (immediate_operand (operands[1], SImode)
1671 && satisfies_constraint_I08 (operands[1])))"
1677 [(set_attr "type" "mt_group,arith") ;; poor approximation
1678 (set_attr "length" "4")])
1680 (define_expand "movsicc"
1681 [(set (match_operand:SI 0 "arith_reg_dest" "")
1682 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1683 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1684 (match_operand:SI 3 "arith_reg_operand" "")))]
1685 "TARGET_SHMEDIA || TARGET_PRETEND_CMOVE"
1687 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1688 && GET_MODE (XEXP (operands[1], 0)) == SImode
1690 || (REG_P (XEXP (operands[1], 0))
1691 && REGNO (XEXP (operands[1], 0)) == T_REG))
1692 && XEXP (operands[1], 1) == const0_rtx)
1695 else if (TARGET_PRETEND_CMOVE)
1697 enum rtx_code code = GET_CODE (operands[1]);
1698 enum rtx_code new_code = code;
1699 rtx op0 = XEXP (operands[1], 0);
1700 rtx op1 = XEXP (operands[1], 1);
1702 if (! currently_expanding_to_rtl)
1706 case LT: case LE: case LEU: case LTU:
1707 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1710 new_code = reverse_condition (code);
1712 case EQ: case GT: case GE: case GEU: case GTU:
1717 sh_emit_scc_to_t (new_code, op0, op1);
1718 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1719 gen_rtx_REG (SImode, T_REG), const0_rtx);
1723 if (!can_create_pseudo_p ())
1726 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1727 GET_CODE (operands[1]),
1728 XEXP (operands[1], 0),
1729 XEXP (operands[1], 1));
1735 (define_expand "movqicc"
1736 [(set (match_operand:QI 0 "register_operand" "")
1737 (if_then_else:QI (match_operand 1 "comparison_operator" "")
1738 (match_operand:QI 2 "register_operand" "")
1739 (match_operand:QI 3 "register_operand" "")))]
1742 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
1743 operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
1744 operands[3] = simplify_gen_subreg (SImode, operands[3], QImode, 0);
1745 emit (gen_movsicc (operands[0], operands[1], operands[2], operands[3]));
1749 ;; -------------------------------------------------------------------------
1750 ;; Addition instructions
1751 ;; -------------------------------------------------------------------------
1753 (define_expand "adddi3"
1754 [(set (match_operand:DI 0 "arith_reg_operand")
1755 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1756 (match_operand:DI 2 "arith_operand")))]
1761 operands[2] = force_reg (DImode, operands[2]);
1762 emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
1767 (define_insn "*adddi3_media"
1768 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
1769 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1770 (match_operand:DI 2 "arith_operand" "r,I10")))]
1775 [(set_attr "type" "arith_media")])
1777 (define_insn "*adddisi3_media"
1778 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r,r") 0)
1779 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1780 (match_operand:DI 2 "arith_operand" "r,I10")))]
1785 [(set_attr "type" "arith_media")
1786 (set_attr "highpart" "ignore")])
1788 (define_insn "adddi3z_media"
1789 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1791 (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
1792 (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
1794 "addz.l %1, %N2, %0"
1795 [(set_attr "type" "arith_media")
1796 (set_attr "highpart" "ignore")])
1798 (define_insn_and_split "adddi3_compact"
1799 [(set (match_operand:DI 0 "arith_reg_dest")
1800 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1801 (match_operand:DI 2 "arith_reg_operand")))
1802 (clobber (reg:SI T_REG))]
1805 "&& can_create_pseudo_p ()"
1808 emit_insn (gen_clrt ());
1809 emit_insn (gen_addc (gen_lowpart (SImode, operands[0]),
1810 gen_lowpart (SImode, operands[1]),
1811 gen_lowpart (SImode, operands[2])));
1812 emit_insn (gen_addc (gen_highpart (SImode, operands[0]),
1813 gen_highpart (SImode, operands[1]),
1814 gen_highpart (SImode, operands[2])));
1819 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1820 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1821 (match_operand:SI 2 "arith_reg_operand" "r"))
1824 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1827 [(set_attr "type" "arith")])
1829 ;; A simplified version of the addc insn, where the exact value of the
1830 ;; T bit doesn't matter. This is easier for combine to pick up.
1831 ;; We allow a reg or 0 for one of the operands in order to be able to
1832 ;; do 'reg + T' sequences. Reload will load the constant 0 into the reg
1834 ;; FIXME: The load of constant 0 should be split out before reload, or else
1835 ;; it will be difficult to hoist or combine the constant load.
1836 (define_insn "*addc"
1837 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1838 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1839 (match_operand:SI 2 "arith_reg_or_0_operand" "r"))
1840 (match_operand:SI 3 "t_reg_operand" "")))
1841 (clobber (reg:SI T_REG))]
1844 [(set_attr "type" "arith")])
1846 ;; Split 'reg + reg + 1' into a sett addc sequence, as it can be scheduled
1847 ;; better, if the sett insn can be done early.
1848 (define_insn_and_split "*addc_r_r_1"
1849 [(set (match_operand:SI 0 "arith_reg_dest" "")
1850 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
1851 (match_operand:SI 2 "arith_reg_operand" ""))
1853 (clobber (reg:SI T_REG))]
1857 [(set (reg:SI T_REG) (const_int 1))
1858 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
1860 (clobber (reg:SI T_REG))])])
1862 ;; Left shifts by one are usually done with an add insn to avoid T_REG
1863 ;; clobbers. Thus addc can also be used to do something like '(x << 1) + 1'.
1864 (define_insn_and_split "*addc_2r_1"
1865 [(set (match_operand:SI 0 "arith_reg_dest")
1866 (plus:SI (mult:SI (match_operand:SI 1 "arith_reg_operand")
1869 (clobber (reg:SI T_REG))]
1873 [(set (reg:SI T_REG) (const_int 1))
1874 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
1876 (clobber (reg:SI T_REG))])])
1878 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
1879 ;; matched. Split this up into a simple sub add sequence, as this will save
1880 ;; us one sett insn.
1881 (define_insn_and_split "*minus_plus_one"
1882 [(set (match_operand:SI 0 "arith_reg_dest" "")
1883 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
1884 (match_operand:SI 2 "arith_reg_operand" ""))
1889 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1890 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
1892 ;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
1893 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
1894 ;; operation, as opposed to sequences such as
1898 ;; Even if the constant is not CSE-ed, a sequence such as
1901 ;; can be scheduled much better since the load of the constant can be
1902 ;; done earlier, before any comparison insns that store the result in
1904 (define_insn_and_split "*addc_t_r"
1905 [(set (match_operand:SI 0 "arith_reg_dest")
1906 (plus:SI (match_operand:SI 1 "t_reg_operand")
1907 (match_operand:SI 2 "arith_reg_operand")))
1908 (clobber (reg:SI T_REG))]
1912 [(parallel [(set (match_dup 0)
1913 (plus:SI (plus:SI (match_dup 2) (const_int 0))
1915 (clobber (reg:SI T_REG))])])
1917 (define_insn_and_split "*addc_r_t"
1918 [(set (match_operand:SI 0 "arith_reg_dest")
1919 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1920 (match_operand:SI 2 "t_reg_operand")))
1921 (clobber (reg:SI T_REG))]
1925 [(parallel [(set (match_dup 0)
1926 (plus:SI (plus:SI (match_dup 1) (const_int 0))
1928 (clobber (reg:SI T_REG))])])
1930 ;; Use shlr-addc to do 'reg + (reg & 1)'.
1931 (define_insn_and_split "*addc_r_lsb"
1932 [(set (match_operand:SI 0 "arith_reg_dest")
1933 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1935 (match_operand:SI 2 "arith_reg_operand")))
1936 (clobber (reg:SI T_REG))]
1939 "&& can_create_pseudo_p ()"
1940 [(parallel [(set (match_dup 0) (plus:SI (reg:SI T_REG) (match_dup 2)))
1941 (clobber (reg:SI T_REG))])]
1943 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[1]));
1946 ;; Use shlr-addc to do 'reg + reg + (reg & 1)'.
1947 (define_insn_and_split "*addc_r_r_lsb"
1948 [(set (match_operand:SI 0 "arith_reg_dest")
1949 (plus:SI (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1951 (match_operand:SI 2 "arith_reg_operand"))
1952 (match_operand:SI 3 "arith_reg_operand")))
1953 (clobber (reg:SI T_REG))]
1956 "&& can_create_pseudo_p ()"
1957 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1959 (clobber (reg:SI T_REG))])]
1961 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[1]));
1964 ;; Canonicalize 'reg + (reg & 1) + reg' into 'reg + reg + (reg & 1)'.
1965 (define_insn_and_split "*addc_r_lsb_r"
1966 [(set (match_operand:SI 0 "arith_reg_dest")
1967 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1969 (plus:SI (match_operand:SI 2 "arith_reg_operand")
1970 (match_operand:SI 3 "arith_reg_operand"))))
1971 (clobber (reg:SI T_REG))]
1974 "&& can_create_pseudo_p ()"
1975 [(parallel [(set (match_dup 0)
1976 (plus:SI (plus:SI (and:SI (match_dup 1) (const_int 1))
1979 (clobber (reg:SI T_REG))])])
1981 ;; Canonicalize '2 * reg + (reg & 1)' into 'reg + reg + (reg & 1)'.
1982 (define_insn_and_split "*addc_2r_lsb"
1983 [(set (match_operand:SI 0 "arith_reg_dest")
1984 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1986 (mult:SI (match_operand:SI 2 "arith_reg_operand")
1988 (clobber (reg:SI T_REG))]
1991 "&& can_create_pseudo_p ()"
1992 [(parallel [(set (match_dup 0)
1993 (plus:SI (plus:SI (and:SI (match_dup 1) (const_int 1))
1996 (clobber (reg:SI T_REG))])])
1998 ;; Use shll-addc to do 'reg + ((unsigned int)reg >> 31)'.
1999 (define_insn_and_split "*addc_r_msb"
2000 [(set (match_operand:SI 0 "arith_reg_dest")
2001 (plus:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
2003 (match_operand:SI 2 "arith_reg_operand")))
2004 (clobber (reg:SI T_REG))]
2007 "&& can_create_pseudo_p ()"
2008 [(parallel [(set (match_dup 0) (plus:SI (reg:SI T_REG) (match_dup 2)))
2009 (clobber (reg:SI T_REG))])]
2011 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[1]));
2014 ;; Use shll-addc to do 'reg + reg + ((unsigned int)reg >> 31)'.
2015 (define_insn_and_split "*addc_r_r_msb"
2016 [(set (match_operand:SI 0 "arith_reg_dest")
2017 (plus:SI (plus:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
2019 (match_operand:SI 2 "arith_reg_operand"))
2020 (match_operand:SI 3 "arith_reg_operand")))
2021 (clobber (reg:SI T_REG))]
2024 "&& can_create_pseudo_p ()"
2025 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
2027 (clobber (reg:SI T_REG))])]
2029 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[1]));
2032 ;; Canonicalize '2 * reg + ((unsigned int)reg >> 31)'
2033 ;; into 'reg + reg + (reg & 1)'.
2034 (define_insn_and_split "*addc_2r_msb"
2035 [(set (match_operand:SI 0 "arith_reg_dest")
2036 (plus:SI (mult:SI (match_operand:SI 1 "arith_reg_operand")
2038 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
2040 (clobber (reg:SI T_REG))]
2043 "&& can_create_pseudo_p ()"
2044 [(parallel [(set (match_dup 0)
2045 (plus:SI (plus:SI (lshiftrt:SI (match_dup 2) (const_int 31))
2048 (clobber (reg:SI T_REG))])])
2050 (define_expand "addsi3"
2051 [(set (match_operand:SI 0 "arith_reg_operand" "")
2052 (plus:SI (match_operand:SI 1 "arith_operand" "")
2053 (match_operand:SI 2 "arith_operand" "")))]
2057 operands[1] = force_reg (SImode, operands[1]);
2060 (define_insn "addsi3_media"
2061 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
2062 (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
2063 (match_operand:SI 2 "arith_operand" "r,I10")))]
2068 [(set_attr "type" "arith_media")
2069 (set_attr "highpart" "ignore")])
2071 (define_insn "addsidi3_media"
2072 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
2073 (sign_extend:DI (plus:SI (match_operand:SI 1 "extend_reg_operand"
2075 (match_operand:SI 2 "arith_operand"
2081 [(set_attr "type" "arith_media")
2082 (set_attr "highpart" "ignore")])
2084 (define_insn "*addsi3_compact"
2085 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2086 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
2087 (match_operand:SI 2 "arith_operand" "rI08")))]
2090 [(set_attr "type" "arith")])
2092 ;; -------------------------------------------------------------------------
2093 ;; Subtraction instructions
2094 ;; -------------------------------------------------------------------------
2096 (define_expand "subdi3"
2097 [(set (match_operand:DI 0 "arith_reg_operand" "")
2098 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
2099 (match_operand:DI 2 "arith_reg_operand" "")))]
2104 operands[1] = force_reg (DImode, operands[1]);
2105 emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
2110 (define_insn "*subdi3_media"
2111 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2112 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
2113 (match_operand:DI 2 "arith_reg_operand" "r")))]
2116 [(set_attr "type" "arith_media")])
2118 (define_insn "subdisi3_media"
2119 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
2120 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
2121 (match_operand:DI 2 "arith_reg_operand" "r")))]
2124 [(set_attr "type" "arith_media")
2125 (set_attr "highpart" "ignore")])
2127 (define_insn_and_split "subdi3_compact"
2128 [(set (match_operand:DI 0 "arith_reg_dest")
2129 (minus:DI (match_operand:DI 1 "arith_reg_operand")
2130 (match_operand:DI 2 "arith_reg_operand")))
2131 (clobber (reg:SI T_REG))]
2134 "&& can_create_pseudo_p ()"
2137 emit_insn (gen_clrt ());
2138 emit_insn (gen_subc (gen_lowpart (SImode, operands[0]),
2139 gen_lowpart (SImode, operands[1]),
2140 gen_lowpart (SImode, operands[2])));
2141 emit_insn (gen_subc (gen_highpart (SImode, operands[0]),
2142 gen_highpart (SImode, operands[1]),
2143 gen_highpart (SImode, operands[2])));
2148 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2149 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2150 (match_operand:SI 2 "arith_reg_operand" "r"))
2153 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
2158 [(set_attr "type" "arith")])
2160 ;; A simplified version of the subc insn, where the exact value of the
2161 ;; T bit doesn't matter. This is easier for combine to pick up.
2162 ;; We allow a reg or 0 for one of the operands in order to be able to
2163 ;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
2165 (define_insn "*subc"
2166 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2167 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2168 (match_operand:SI 2 "arith_reg_or_0_operand" "r"))
2169 (match_operand:SI 3 "t_reg_operand" "")))
2170 (clobber (reg:SI T_REG))]
2173 [(set_attr "type" "arith")])
2175 ;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
2176 ;; better, if the sett insn can be done early.
2177 ;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
2178 (define_insn_and_split "*subc"
2179 [(set (match_operand:SI 0 "arith_reg_dest" "")
2180 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
2181 (match_operand:SI 2 "arith_reg_operand" "")))
2182 (clobber (reg:SI T_REG))]
2186 [(set (reg:SI T_REG) (const_int 1))
2187 (parallel [(set (match_dup 0)
2188 (minus:SI (minus:SI (match_dup 2) (match_dup 1))
2190 (clobber (reg:SI T_REG))])])
2192 ;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
2193 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2194 ;; operation, as opposed to sequences such as
2198 ;; Even if the constant is not CSE-ed, a sequence such as
2201 ;; can be scheduled much better since the load of the constant can be
2202 ;; done earlier, before any comparison insns that store the result in
2204 (define_insn_and_split "*subc"
2205 [(set (match_operand:SI 0 "arith_reg_dest" "")
2206 (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
2207 (match_operand:SI 2 "t_reg_operand" "")))
2208 (clobber (reg:SI T_REG))]
2212 [(parallel [(set (match_dup 0)
2213 (minus:SI (minus:SI (match_dup 1) (const_int 0))
2215 (clobber (reg:SI T_REG))])])
2217 (define_insn "*subsi3_internal"
2218 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2219 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2220 (match_operand:SI 2 "arith_reg_operand" "r")))]
2223 [(set_attr "type" "arith")])
2225 (define_insn_and_split "*subsi3_media"
2226 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2227 (minus:SI (match_operand:SI 1 "minuend_operand" "rN")
2228 (match_operand:SI 2 "extend_reg_operand" "r")))]
2230 && (operands[1] != constm1_rtx
2231 || (GET_CODE (operands[2]) != TRUNCATE
2232 && GET_CODE (operands[2]) != SUBREG))"
2234 "operands[1] == constm1_rtx"
2235 [(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))]
2237 [(set_attr "type" "arith_media")
2238 (set_attr "highpart" "ignore")])
2241 [(set (match_operand:SI 0 "arith_reg_dest" "")
2242 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2243 "general_extend_operand"
2245 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
2246 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2247 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2251 [(set (match_operand:SI 0 "arith_reg_dest" "")
2252 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2253 "general_extend_operand"
2255 "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
2256 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2257 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2265 ;; since this will sometimes save one instruction.
2266 ;; Otherwise we might get a sequence like
2270 ;; if the source and dest regs are the same.
2271 (define_expand "subsi3"
2272 [(set (match_operand:SI 0 "arith_reg_operand" "")
2273 (minus:SI (match_operand:SI 1 "arith_operand" "")
2274 (match_operand:SI 2 "arith_reg_operand" "")))]
2277 if (TARGET_SH1 && CONST_INT_P (operands[1]))
2279 emit_insn (gen_negsi2 (operands[0], operands[2]));
2280 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
2285 if (!can_create_pseudo_p ()
2286 && ! arith_reg_or_0_operand (operands[1], SImode))
2288 if (operands[1] != const0_rtx && GET_CODE (operands[1]) != SUBREG)
2289 operands[1] = force_reg (SImode, operands[1]);
2293 ;; -------------------------------------------------------------------------
2294 ;; Division instructions
2295 ;; -------------------------------------------------------------------------
2297 ;; We take advantage of the library routines which don't clobber as many
2298 ;; registers as a normal function call would.
2300 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2301 ;; also has an effect on the register that holds the address of the sfunc.
2302 ;; To make this work, we have an extra dummy insn that shows the use
2303 ;; of this register for reorg.
2305 (define_insn "use_sfunc_addr"
2306 [(set (reg:SI PR_REG)
2307 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
2308 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
2310 [(set_attr "length" "0")])
2312 (define_insn "udivsi3_sh2a"
2313 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2314 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
2315 (match_operand:SI 2 "arith_reg_operand" "z")))]
2318 [(set_attr "type" "arith")
2319 (set_attr "in_delay_slot" "no")])
2321 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
2322 ;; hard register 0. If we used hard register 0, then the next instruction
2323 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
2324 ;; gets allocated to a stack slot that needs its address reloaded, then
2325 ;; there is nothing to prevent reload from using r0 to reload the address.
2326 ;; This reload would clobber the value in r0 we are trying to store.
2327 ;; If we let reload allocate r0, then this problem can never happen.
2328 (define_insn "udivsi3_i1"
2329 [(set (match_operand:SI 0 "register_operand" "=z")
2330 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2331 (clobber (reg:SI T_REG))
2332 (clobber (reg:SI PR_REG))
2333 (clobber (reg:SI R1_REG))
2334 (clobber (reg:SI R4_REG))
2335 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2336 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2338 [(set_attr "type" "sfunc")
2339 (set_attr "needs_delay_slot" "yes")])
2341 ; Since shmedia-nofpu code could be linked against shcompact code, and
2342 ; the udivsi3 libcall has the same name, we must consider all registers
2343 ; clobbered that are in the union of the registers clobbered by the
2344 ; shmedia and the shcompact implementation. Note, if the shcompact
2345 ; implementation actually used shcompact code, we'd need to clobber
2346 ; also r23 and fr23.
2347 (define_insn "udivsi3_i1_media"
2348 [(set (match_operand:SI 0 "register_operand" "=z")
2349 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2350 (clobber (reg:SI T_MEDIA_REG))
2351 (clobber (reg:SI PR_MEDIA_REG))
2352 (clobber (reg:SI R20_REG))
2353 (clobber (reg:SI R21_REG))
2354 (clobber (reg:SI R22_REG))
2355 (clobber (reg:DI TR0_REG))
2356 (clobber (reg:DI TR1_REG))
2357 (clobber (reg:DI TR2_REG))
2358 (use (match_operand 1 "target_reg_operand" "b"))]
2359 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2361 [(set_attr "type" "sfunc")
2362 (set_attr "needs_delay_slot" "yes")])
2364 (define_expand "udivsi3_i4_media"
2366 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
2368 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
2369 (set (match_dup 5) (float:DF (match_dup 3)))
2370 (set (match_dup 6) (float:DF (match_dup 4)))
2371 (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
2372 (set (match_dup 8) (fix:DI (match_dup 7)))
2373 (set (match_operand:SI 0 "register_operand" "")
2374 (truncate:SI (match_dup 8)))]
2375 "TARGET_SHMEDIA_FPU"
2377 operands[3] = gen_reg_rtx (DImode);
2378 operands[4] = gen_reg_rtx (DImode);
2379 operands[5] = gen_reg_rtx (DFmode);
2380 operands[6] = gen_reg_rtx (DFmode);
2381 operands[7] = gen_reg_rtx (DFmode);
2382 operands[8] = gen_reg_rtx (DImode);
2385 (define_insn "udivsi3_i4"
2386 [(set (match_operand:SI 0 "register_operand" "=y")
2387 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2388 (clobber (reg:SI T_REG))
2389 (clobber (reg:SI PR_REG))
2390 (clobber (reg:DF DR0_REG))
2391 (clobber (reg:DF DR2_REG))
2392 (clobber (reg:DF DR4_REG))
2393 (clobber (reg:SI R0_REG))
2394 (clobber (reg:SI R1_REG))
2395 (clobber (reg:SI R4_REG))
2396 (clobber (reg:SI R5_REG))
2397 (use (reg:PSI FPSCR_REG))
2398 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2399 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2401 [(set_attr "type" "sfunc")
2402 (set_attr "fp_mode" "double")
2403 (set_attr "needs_delay_slot" "yes")])
2405 (define_insn "udivsi3_i4_single"
2406 [(set (match_operand:SI 0 "register_operand" "=y")
2407 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2408 (clobber (reg:SI T_REG))
2409 (clobber (reg:SI PR_REG))
2410 (clobber (reg:DF DR0_REG))
2411 (clobber (reg:DF DR2_REG))
2412 (clobber (reg:DF DR4_REG))
2413 (clobber (reg:SI R0_REG))
2414 (clobber (reg:SI R1_REG))
2415 (clobber (reg:SI R4_REG))
2416 (clobber (reg:SI R5_REG))
2417 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2418 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2419 && TARGET_FPU_SINGLE"
2421 [(set_attr "type" "sfunc")
2422 (set_attr "needs_delay_slot" "yes")])
2424 (define_insn "udivsi3_i4_int"
2425 [(set (match_operand:SI 0 "register_operand" "=z")
2426 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2427 (clobber (reg:SI T_REG))
2428 (clobber (reg:SI R1_REG))
2429 (clobber (reg:SI PR_REG))
2430 (clobber (reg:SI MACH_REG))
2431 (clobber (reg:SI MACL_REG))
2432 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2435 [(set_attr "type" "sfunc")
2436 (set_attr "needs_delay_slot" "yes")])
2439 (define_expand "udivsi3"
2440 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
2441 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2442 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2443 (parallel [(set (match_operand:SI 0 "register_operand" "")
2444 (udiv:SI (reg:SI R4_REG)
2446 (clobber (reg:SI T_REG))
2447 (clobber (reg:SI PR_REG))
2448 (clobber (reg:SI R4_REG))
2449 (use (match_dup 3))])]
2454 operands[3] = gen_reg_rtx (Pmode);
2455 /* Emit the move of the address to a pseudo outside of the libcall. */
2456 if (TARGET_DIVIDE_CALL_TABLE)
2458 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
2459 that causes problems when the divide code is supposed to come from a
2460 separate library. Division by zero is undefined, so dividing 1 can be
2461 implemented by comparing with the divisor. */
2462 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
2464 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
2465 emit_insn (gen_cstoresi4 (operands[0], test,
2466 operands[1], operands[2]));
2469 else if (operands[2] == const0_rtx)
2471 emit_move_insn (operands[0], operands[2]);
2474 function_symbol (operands[3], "__udivsi3_i4i", SFUNC_GOT);
2475 last = gen_udivsi3_i4_int (operands[0], operands[3]);
2477 else if (TARGET_DIVIDE_CALL_FP)
2479 function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC);
2480 if (TARGET_FPU_SINGLE)
2481 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2483 last = gen_udivsi3_i4 (operands[0], operands[3]);
2485 else if (TARGET_SHMEDIA_FPU)
2487 operands[1] = force_reg (SImode, operands[1]);
2488 operands[2] = force_reg (SImode, operands[2]);
2489 emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
2492 else if (TARGET_SH2A)
2494 operands[1] = force_reg (SImode, operands[1]);
2495 operands[2] = force_reg (SImode, operands[2]);
2496 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
2499 else if (TARGET_SH5)
2501 function_symbol (operands[3],
2502 TARGET_FPU_ANY ? "__udivsi3_i4" : "__udivsi3",
2506 last = gen_udivsi3_i1_media (operands[0], operands[3]);
2507 else if (TARGET_FPU_ANY)
2508 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2510 last = gen_udivsi3_i1 (operands[0], operands[3]);
2514 function_symbol (operands[3], "__udivsi3", SFUNC_STATIC);
2515 last = gen_udivsi3_i1 (operands[0], operands[3]);
2517 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2518 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2523 (define_insn "divsi3_sh2a"
2524 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2525 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
2526 (match_operand:SI 2 "arith_reg_operand" "z")))]
2529 [(set_attr "type" "arith")
2530 (set_attr "in_delay_slot" "no")])
2532 (define_insn "divsi3_i1"
2533 [(set (match_operand:SI 0 "register_operand" "=z")
2534 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2535 (clobber (reg:SI T_REG))
2536 (clobber (reg:SI PR_REG))
2537 (clobber (reg:SI R1_REG))
2538 (clobber (reg:SI R2_REG))
2539 (clobber (reg:SI R3_REG))
2540 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2541 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2543 [(set_attr "type" "sfunc")
2544 (set_attr "needs_delay_slot" "yes")])
2546 (define_insn "divsi3_i1_media"
2547 [(set (match_operand:SI 0 "register_operand" "=z")
2548 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2549 (clobber (reg:SI T_MEDIA_REG))
2550 (clobber (reg:SI PR_MEDIA_REG))
2551 (clobber (reg:SI R1_REG))
2552 (clobber (reg:SI R20_REG))
2553 (clobber (reg:SI R21_REG))
2554 (clobber (reg:SI TR0_REG))
2555 (use (match_operand 1 "target_reg_operand" "b"))]
2556 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2558 [(set_attr "type" "sfunc")])
2560 (define_insn "divsi3_media_2"
2561 [(set (match_operand:SI 0 "register_operand" "=z")
2562 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2563 (clobber (reg:SI T_MEDIA_REG))
2564 (clobber (reg:SI PR_MEDIA_REG))
2565 (clobber (reg:SI R1_REG))
2566 (clobber (reg:SI R21_REG))
2567 (clobber (reg:SI TR0_REG))
2568 (use (reg:SI R20_REG))
2569 (use (match_operand 1 "target_reg_operand" "b"))]
2570 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2572 [(set_attr "type" "sfunc")])
2574 ;; This pattern acts as a placeholder for -mdiv=inv:call to carry
2575 ;; hard reg clobbers and data dependencies that we need when we want
2576 ;; to rematerialize the division into a call.
2577 (define_insn_and_split "divsi_inv_call"
2578 [(set (match_operand:SI 0 "register_operand" "=r")
2579 (div:SI (match_operand:SI 1 "register_operand" "r")
2580 (match_operand:SI 2 "register_operand" "r")))
2581 (clobber (reg:SI R4_REG))
2582 (clobber (reg:SI R5_REG))
2583 (clobber (reg:SI T_MEDIA_REG))
2584 (clobber (reg:SI PR_MEDIA_REG))
2585 (clobber (reg:SI R1_REG))
2586 (clobber (reg:SI R21_REG))
2587 (clobber (reg:SI TR0_REG))
2588 (clobber (reg:SI R20_REG))
2589 (use (match_operand:SI 3 "register_operand" "r"))]
2592 "&& (reload_in_progress || reload_completed)"
2593 [(set (match_dup 0) (match_dup 3))]
2595 [(set_attr "highpart" "must_split")])
2597 ;; This is the combiner pattern for -mdiv=inv:call .
2598 (define_insn_and_split "*divsi_inv_call_combine"
2599 [(set (match_operand:SI 0 "register_operand" "=z")
2600 (div:SI (match_operand:SI 1 "register_operand" "r")
2601 (match_operand:SI 2 "register_operand" "r")))
2602 (clobber (reg:SI R4_REG))
2603 (clobber (reg:SI R5_REG))
2604 (clobber (reg:SI T_MEDIA_REG))
2605 (clobber (reg:SI PR_MEDIA_REG))
2606 (clobber (reg:SI R1_REG))
2607 (clobber (reg:SI R21_REG))
2608 (clobber (reg:SI TR0_REG))
2609 (clobber (reg:SI R20_REG))
2610 (use (unspec:SI [(match_dup 1)
2611 (match_operand:SI 3 "" "")
2612 (unspec:SI [(match_operand:SI 4 "" "")
2614 (match_operand:DI 5 "" "")]
2616 (match_operand:DI 6 "" "")
2619 UNSPEC_DIV_INV_M3))]
2622 "&& (reload_in_progress || reload_completed)"
2625 const char *name = sh_divsi3_libfunc;
2626 enum sh_function_kind kind = SFUNC_GOT;
2629 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2630 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2631 while (TARGET_DIVIDE_INV_CALL2)
2633 rtx x = operands[3];
2635 if (GET_CODE (x) != UNSPEC || XINT (x, 1) != UNSPEC_DIV_INV_M1)
2637 x = XVECEXP (x, 0, 0);
2638 name = "__sdivsi3_2";
2639 kind = SFUNC_STATIC;
2640 emit_move_insn (gen_rtx_REG (DImode, R20_REG), x);
2643 sym = function_symbol (NULL, name, kind);
2644 emit_insn (gen_divsi3_media_2 (operands[0], sym));
2647 [(set_attr "highpart" "must_split")])
2649 (define_expand "divsi3_i4_media"
2650 [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
2651 (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
2652 (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
2653 (set (match_operand:SI 0 "register_operand" "=r")
2654 (fix:SI (match_dup 5)))]
2655 "TARGET_SHMEDIA_FPU"
2657 operands[3] = gen_reg_rtx (DFmode);
2658 operands[4] = gen_reg_rtx (DFmode);
2659 operands[5] = gen_reg_rtx (DFmode);
2662 (define_insn "divsi3_i4"
2663 [(set (match_operand:SI 0 "register_operand" "=y")
2664 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2665 (clobber (reg:SI PR_REG))
2666 (clobber (reg:DF DR0_REG))
2667 (clobber (reg:DF DR2_REG))
2668 (use (reg:PSI FPSCR_REG))
2669 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2670 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2672 [(set_attr "type" "sfunc")
2673 (set_attr "fp_mode" "double")
2674 (set_attr "needs_delay_slot" "yes")])
2676 (define_insn "divsi3_i4_single"
2677 [(set (match_operand:SI 0 "register_operand" "=y")
2678 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2679 (clobber (reg:SI PR_REG))
2680 (clobber (reg:DF DR0_REG))
2681 (clobber (reg:DF DR2_REG))
2682 (clobber (reg:SI R2_REG))
2683 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2684 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2685 && TARGET_FPU_SINGLE"
2687 [(set_attr "type" "sfunc")
2688 (set_attr "needs_delay_slot" "yes")])
2690 (define_insn "divsi3_i4_int"
2691 [(set (match_operand:SI 0 "register_operand" "=z")
2692 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2693 (clobber (reg:SI T_REG))
2694 (clobber (reg:SI PR_REG))
2695 (clobber (reg:SI R1_REG))
2696 (clobber (reg:SI MACH_REG))
2697 (clobber (reg:SI MACL_REG))
2698 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2701 [(set_attr "type" "sfunc")
2702 (set_attr "needs_delay_slot" "yes")])
2704 (define_expand "divsi3"
2705 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
2706 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2707 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2708 (parallel [(set (match_operand:SI 0 "register_operand" "")
2709 (div:SI (reg:SI R4_REG)
2711 (clobber (reg:SI T_REG))
2712 (clobber (reg:SI PR_REG))
2713 (clobber (reg:SI R1_REG))
2714 (clobber (reg:SI R2_REG))
2715 (clobber (reg:SI R3_REG))
2716 (use (match_dup 3))])]
2721 operands[3] = gen_reg_rtx (Pmode);
2722 /* Emit the move of the address to a pseudo outside of the libcall. */
2723 if (TARGET_DIVIDE_CALL_TABLE)
2725 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2726 last = gen_divsi3_i4_int (operands[0], operands[3]);
2728 else if (TARGET_DIVIDE_CALL_FP)
2730 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2731 if (TARGET_FPU_SINGLE)
2732 last = gen_divsi3_i4_single (operands[0], operands[3]);
2734 last = gen_divsi3_i4 (operands[0], operands[3]);
2736 else if (TARGET_SH2A)
2738 operands[1] = force_reg (SImode, operands[1]);
2739 operands[2] = force_reg (SImode, operands[2]);
2740 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2743 else if (TARGET_DIVIDE_INV)
2745 rtx dividend = operands[1];
2746 rtx divisor = operands[2];
2748 rtx nsb_res = gen_reg_rtx (DImode);
2749 rtx norm64 = gen_reg_rtx (DImode);
2750 rtx tab_ix = gen_reg_rtx (DImode);
2751 rtx norm32 = gen_reg_rtx (SImode);
2752 rtx i92 = force_reg (DImode, GEN_INT (92));
2753 rtx scratch0a = gen_reg_rtx (DImode);
2754 rtx scratch0b = gen_reg_rtx (DImode);
2755 rtx inv0 = gen_reg_rtx (SImode);
2756 rtx scratch1a = gen_reg_rtx (DImode);
2757 rtx scratch1b = gen_reg_rtx (DImode);
2758 rtx shift = gen_reg_rtx (DImode);
2760 rtx inv1 = gen_reg_rtx (SImode);
2761 rtx scratch2a = gen_reg_rtx (DImode);
2762 rtx scratch2b = gen_reg_rtx (SImode);
2763 rtx inv2 = gen_reg_rtx (SImode);
2764 rtx scratch3a = gen_reg_rtx (DImode);
2765 rtx scratch3b = gen_reg_rtx (DImode);
2766 rtx scratch3c = gen_reg_rtx (DImode);
2767 rtx scratch3d = gen_reg_rtx (SImode);
2768 rtx scratch3e = gen_reg_rtx (DImode);
2769 rtx result = gen_reg_rtx (SImode);
2771 if (! arith_reg_or_0_operand (dividend, SImode))
2772 dividend = force_reg (SImode, dividend);
2773 if (! arith_reg_operand (divisor, SImode))
2774 divisor = force_reg (SImode, divisor);
2775 if (flag_pic && Pmode != DImode)
2777 tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
2778 tab_base = gen_datalabel_ref (tab_base);
2779 tab_base = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, tab_base));
2783 tab_base = gen_rtx_SYMBOL_REF (DImode, "__div_table");
2784 tab_base = gen_datalabel_ref (tab_base);
2785 tab_base = force_reg (DImode, tab_base);
2787 if (TARGET_DIVIDE_INV20U)
2788 i2p27 = force_reg (DImode, GEN_INT (-2 << 27));
2790 i2p27 = GEN_INT (0);
2791 if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)
2792 i43 = force_reg (DImode, GEN_INT (43));
2795 emit_insn (gen_nsbdi (nsb_res,
2796 simplify_gen_subreg (DImode, divisor, SImode, 0)));
2797 emit_insn (gen_ashldi3_media (norm64,
2798 gen_rtx_SUBREG (DImode, divisor, 0),
2800 emit_insn (gen_ashrdi3_media (tab_ix, norm64, GEN_INT (58)));
2801 emit_insn (gen_ashrdisi3_media_high (norm32, norm64, GEN_INT (32)));
2802 emit_insn (gen_divsi_inv_m1 (inv1, tab_base, tab_ix, norm32,
2803 inv0, scratch0a, scratch0b,
2804 scratch1a, scratch1b));
2805 emit_insn (gen_subdi3 (shift, i92, nsb_res));
2806 emit_insn (gen_divsi_inv_m2 (inv2, norm32, inv1, i92,
2808 emit_insn (gen_divsi_inv_m3 (result, dividend, inv1, inv2, shift,
2810 scratch3a, scratch3b, scratch3c,
2811 scratch2a, scratch2b, scratch3d, scratch3e));
2812 if (TARGET_DIVIDE_INV_CALL || TARGET_DIVIDE_INV_CALL2)
2813 emit_insn (gen_divsi_inv_call (operands[0], dividend, divisor, result));
2814 else if (TARGET_DIVIDE_INV_FP)
2815 emit_insn (gen_divsi_inv_fp (operands[0], dividend, divisor, result,
2816 gen_reg_rtx (SImode), gen_reg_rtx (SImode),
2817 gen_reg_rtx (DFmode), gen_reg_rtx (DFmode),
2818 gen_reg_rtx (DFmode)));
2820 emit_move_insn (operands[0], result);
2823 else if (TARGET_SHMEDIA_FPU && TARGET_DIVIDE_FP)
2825 operands[1] = force_reg (SImode, operands[1]);
2826 operands[2] = force_reg (SImode, operands[2]);
2827 emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
2830 else if (TARGET_SH5)
2832 if (TARGET_DIVIDE_CALL2)
2834 rtx tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
2835 tab_base = gen_datalabel_ref (tab_base);
2836 emit_move_insn (gen_rtx_REG (Pmode, R20_REG), tab_base);
2838 if (TARGET_FPU_ANY && TARGET_SH1)
2839 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2840 else if (TARGET_DIVIDE_CALL2)
2841 function_symbol (operands[3], "__sdivsi3_2", SFUNC_STATIC);
2843 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2846 last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media)
2847 (operands[0], operands[3]));
2848 else if (TARGET_FPU_ANY)
2849 last = gen_divsi3_i4_single (operands[0], operands[3]);
2851 last = gen_divsi3_i1 (operands[0], operands[3]);
2855 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2856 last = gen_divsi3_i1 (operands[0], operands[3]);
2858 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2859 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2864 ;; operands: scratch, tab_base, tab_ix
2865 ;; These are unspecs because we could generate an indexed addressing mode
2866 ;; even if -m5-32media, where INDEX_REG_CLASS == NO_REGS, and this would
2867 ;; confuse reload. See PR27117.
2868 (define_insn "divsi_inv_qitable"
2869 [(set (match_operand:DI 0 "register_operand" "=r")
2870 (zero_extend:DI (unspec:QI [(match_operand:DI 1 "register_operand" "r")
2871 (match_operand:DI 2 "register_operand" "r")]
2872 UNSPEC_DIV_INV_TABLE)))]
2875 [(set_attr "type" "load_media")
2876 (set_attr "highpart" "user")])
2878 ;; operands: scratch, tab_base, tab_ix
2879 (define_insn "divsi_inv_hitable"
2880 [(set (match_operand:DI 0 "register_operand" "=r")
2881 (sign_extend:DI (unspec:HI [(match_operand:DI 1 "register_operand" "r")
2882 (match_operand:DI 2 "register_operand" "r")]
2883 UNSPEC_DIV_INV_TABLE)))]
2886 [(set_attr "type" "load_media")
2887 (set_attr "highpart" "user")])
2889 ;; operands: inv0, tab_base, tab_ix, norm32
2890 ;; scratch equiv in sdivsi3_2: r19, r21
2891 (define_expand "divsi_inv_m0"
2892 [(set (match_operand:SI 0 "register_operand" "=r")
2893 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2894 (match_operand:DI 2 "register_operand" "r")
2895 (match_operand:SI 3 "register_operand" "r")]
2897 (clobber (match_operand:DI 4 "register_operand" "=r"))
2898 (clobber (match_operand:DI 5 "register_operand" "=r"))]
2905 ldx.ub r20, r21, r19 // u0.8
2907 muls.l r25, r19, r19 // s2.38
2908 ldx.w r20, r21, r21 // s2.14
2909 shari r19, 24, r19 // truncate to s2.14
2910 sub r21, r19, r19 // some 11 bit inverse in s1.14
2913 rtx inv0 = operands[0];
2914 rtx tab_base = operands[1];
2915 rtx tab_ix = operands[2];
2916 rtx norm32 = operands[3];
2917 rtx scratch0 = operands[4];
2918 rtx scratch0_si = gen_lowpart (SImode, scratch0);
2919 rtx scratch1 = operands[5];
2921 emit_insn (gen_divsi_inv_qitable (scratch0, tab_base, tab_ix));
2922 emit_insn (gen_ashldi3_media (scratch1, tab_ix, GEN_INT (1)));
2923 emit_insn (gen_mulsidi3_media (scratch0, norm32, scratch0_si));
2924 emit_insn (gen_divsi_inv_hitable (scratch1, tab_base, scratch1));
2925 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (24)));
2926 emit_insn (gen_subdisi3_media (inv0, scratch1, scratch0));
2930 ;; operands: inv1, tab_base, tab_ix, norm32
2931 (define_insn_and_split "divsi_inv_m1"
2932 [(set (match_operand:SI 0 "register_operand" "=r")
2933 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2934 (match_operand:DI 2 "register_operand" "r")
2935 (match_operand:SI 3 "register_operand" "r")]
2937 (clobber (match_operand:SI 4 "register_operand" "=r"))
2938 (clobber (match_operand:DI 5 "register_operand" "=r"))
2939 (clobber (match_operand:DI 6 "register_operand" "=r"))
2940 (clobber (match_operand:DI 7 "register_operand" "=r"))
2941 (clobber (match_operand:DI 8 "register_operand" "=r"))]
2944 "&& !can_create_pseudo_p ()"
2948 muls.l r19, r19, r18 // u0.28
2949 muls.l r25, r18, r18 // s2.58
2950 shlli r19, 45, r0 // multiply by two and convert to s2.58
2952 shari r18, 28, r18 // some 18 bit inverse in s1.30
2955 rtx inv1 = operands[0];
2956 rtx tab_base = operands[1];
2957 rtx tab_ix = operands[2];
2958 rtx norm32 = operands[3];
2959 rtx inv0 = operands[4];
2960 rtx inv0_di = simplify_gen_subreg (DImode, inv0, SImode, 0);
2961 rtx scratch0a = operands[5];
2962 rtx scratch0b = operands[6];
2963 rtx scratch0 = operands[7];
2964 rtx scratch1 = operands[8];
2965 rtx scratch1_si = gen_lowpart (SImode, scratch1);
2967 emit_insn (gen_divsi_inv_m0 (inv0, tab_base, tab_ix, norm32,
2968 scratch0a, scratch0b));
2969 emit_insn (gen_mulsidi3_media (scratch1, inv0, inv0));
2970 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
2971 emit_insn (gen_ashldi3_media (scratch0, inv0_di, GEN_INT (45)));
2972 emit_insn (gen_subdi3 (scratch1, scratch0, scratch1));
2973 emit_insn (gen_ashrdisi3_media_opaque (inv1, scratch1, GEN_INT (28)));
2977 ;; operands: inv2, norm32, inv1, i92
2978 (define_insn_and_split "divsi_inv_m2"
2979 [(set (match_operand:SI 0 "register_operand" "=r")
2980 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2981 (match_operand:SI 2 "register_operand" "r")
2982 (match_operand:DI 3 "register_operand" "r")]
2984 (clobber (match_operand:DI 4 "register_operand" "=r"))]
2987 "&& !can_create_pseudo_p ()"
2991 muls.l r18, r25, r0 // s2.60
2992 shari r0, 16, r0 // s-16.44
2994 muls.l r0, r18, r19 // s-16.74
2995 shari r19, 30, r19 // s-16.44
2997 rtx inv2 = operands[0];
2998 rtx norm32 = operands[1];
2999 rtx inv1 = operands[2];
3000 rtx i92 = operands[3];
3001 rtx scratch0 = operands[4];
3002 rtx scratch0_si = gen_lowpart (SImode, scratch0);
3004 emit_insn (gen_mulsidi3_media (scratch0, inv1, norm32));
3005 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (16)));
3006 emit_insn (gen_subdi3 (scratch0, i92, scratch0));
3007 emit_insn (gen_mulsidi3_media (scratch0, scratch0_si, inv1));
3008 emit_insn (gen_ashrdisi3_media_opaque (inv2, scratch0, GEN_INT (30)));
3012 (define_insn_and_split "divsi_inv_m3"
3013 [(set (match_operand:SI 0 "register_operand" "=r")
3014 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
3015 (match_operand:SI 2 "register_operand" "r")
3016 (match_operand:SI 3 "register_operand" "r")
3017 (match_operand:DI 4 "register_operand" "r")
3018 (match_operand:DI 5 "arith_reg_or_0_operand" "rN")
3019 (match_operand:DI 6 "arith_reg_or_0_operand" "rN")]
3021 (clobber (match_operand:DI 7 "register_operand" "=r"))
3022 (clobber (match_operand:DI 8 "register_operand" "=r"))
3023 (clobber (match_operand:DI 9 "register_operand" "=r"))
3024 (clobber (match_operand:DI 10 "register_operand" "=r"))
3025 (clobber (match_operand:SI 11 "register_operand" "=r"))
3026 (clobber (match_operand:SI 12 "register_operand" "=r"))
3027 (clobber (match_operand:DI 13 "register_operand" "=r"))]
3030 "&& !can_create_pseudo_p ()"
3034 r0: result r1: shift r4: dividend r18: inv1 r19: inv2
3035 r0: scratch0 r19: scratch1 r21: scratch2
3037 muls.l r18, r4, r25 // s32.30
3038 muls.l r19, r4, r19 // s15.30
3040 shari r19, 14, r19 // s18.-14
3046 rtx result = operands[0];
3047 rtx dividend = operands[1];
3048 rtx inv1 = operands[2];
3049 rtx inv2 = operands[3];
3050 rtx shift = operands[4];
3051 rtx scratch0 = operands[7];
3052 rtx scratch1 = operands[8];
3053 rtx scratch2 = operands[9];
3055 if (satisfies_constraint_N (dividend))
3057 emit_move_insn (result, dividend);
3061 emit_insn (gen_mulsidi3_media (scratch0, inv1, dividend));
3062 emit_insn (gen_mulsidi3_media (scratch1, inv2, dividend));
3063 emit_insn (gen_ashrdi3_media (scratch2, scratch0, GEN_INT (63)));
3064 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (14)));
3065 emit_insn (gen_adddi3 (scratch0, scratch0, scratch1));
3066 emit_insn (gen_ashrdi3_media (scratch0, scratch0, shift));
3067 emit_insn (gen_subdisi3_media (result, scratch0, scratch2));
3071 ;; operands: quotient, dividend, inv1, inv2, shift, i2p27, i43
3072 ;; inv1: tab_base, tab_ix, norm32
3073 ;; inv2: norm32, inv1, i92
3074 (define_insn_and_split "divsi_inv_m1_3"
3075 [(set (match_operand:SI 0 "register_operand" "=r")
3076 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
3077 (unspec:SI [(match_operand:DI 2 "register_operand" "r")
3078 (match_operand:DI 3 "register_operand" "r")
3079 (match_operand:SI 4 "register_operand" "r")]
3081 (unspec:SI [(match_dup 4)
3082 (unspec:SI [(match_dup 2)
3084 (match_dup 4)] UNSPEC_DIV_INV_M1)
3085 (match_operand:SI 5 "" "")]
3087 (match_operand:DI 6 "register_operand" "r")
3088 (match_operand:DI 7 "arith_reg_or_0_operand" "rN")
3089 (match_operand:DI 8 "arith_reg_or_0_operand" "rN")]
3091 (clobber (match_operand:DI 9 "register_operand" "=r"))
3092 (clobber (match_operand:DI 10 "register_operand" "=r"))
3093 (clobber (match_operand:DI 11 "register_operand" "=r"))
3094 (clobber (match_operand:DI 12 "register_operand" "=r"))
3095 (clobber (match_operand:SI 13 "register_operand" "=r"))
3096 (clobber (match_operand:SI 14 "register_operand" "=r"))
3097 (clobber (match_operand:DI 15 "register_operand" "=r"))]
3099 && (TARGET_DIVIDE_INV_MINLAT
3100 || TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
3102 "&& !can_create_pseudo_p ()"
3105 rtx result = operands[0];
3106 rtx dividend = operands[1];
3107 rtx tab_base = operands[2];
3108 rtx tab_ix = operands[3];
3109 rtx norm32 = operands[4];
3110 /* rtx i92 = operands[5]; */
3111 rtx shift = operands[6];
3112 rtx i2p27 = operands[7];
3113 rtx i43 = operands[8];
3114 rtx scratch0 = operands[9];
3115 rtx scratch0_si = gen_lowpart (SImode, scratch0);
3116 rtx scratch1 = operands[10];
3117 rtx scratch1_si = gen_lowpart (SImode, scratch1);
3118 rtx scratch2 = operands[11];
3119 rtx scratch3 = operands[12];
3120 rtx scratch4 = operands[13];
3121 rtx scratch4_di = simplify_gen_subreg (DImode, scratch4, SImode, 0);
3122 rtx scratch5 = operands[14];
3123 rtx scratch5_di = simplify_gen_subreg (DImode, scratch5, SImode, 0);
3124 rtx scratch6 = operands[15];
3126 emit_insn (gen_divsi_inv_m0 (scratch4, tab_base, tab_ix, norm32,
3127 scratch0, scratch1));
3128 /* inv0 == scratch4 */
3129 if (! TARGET_DIVIDE_INV20U)
3131 emit_insn (gen_mulsidi3_media (scratch0, scratch4, scratch4));
3133 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch0_si));
3137 emit_insn (gen_mulsidi3_media (scratch1, scratch4, scratch4));
3138 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
3140 emit_insn (gen_ashldi3_media (scratch2, scratch4_di, GEN_INT (45)));
3141 emit_insn (gen_subdi3 (scratch1, scratch2, scratch1));
3142 emit_insn (gen_ashrdisi3_media_opaque (scratch4, scratch1, GEN_INT (28)));
3143 /* inv1 == scratch4 */
3145 if (TARGET_DIVIDE_INV_MINLAT)
3147 emit_insn (gen_mulsidi3_media (scratch1, scratch4, norm32));
3148 emit_insn (gen_mulsidi3_media (scratch2, dividend, scratch4));
3149 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (16)));
3150 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch4));
3151 emit_insn (gen_ashrdi3_media (scratch3, scratch2, GEN_INT (63)));
3152 emit_insn (gen_ashrsi3_media (scratch5, dividend, GEN_INT (14)));
3153 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (30)));
3154 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch5));
3155 emit_insn (gen_xordi3 (scratch0, scratch3, i2p27));
3156 emit_insn (gen_adddi3 (scratch2, scratch2, scratch0));
3157 emit_insn (gen_subdi3 (scratch2, scratch2, scratch1));
3161 rtx label = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
3162 /* Use separate scratch regs for nsb and sign to allow scheduling. */
3163 emit_insn (gen_nsbdi (scratch6,
3164 simplify_gen_subreg (DImode, dividend, SImode, 0)));
3165 emit_insn (gen_xorsi3 (scratch5, dividend, norm32));
3166 emit_insn (gen_ashrdi3_media (scratch3, scratch5_di, GEN_INT (63)));
3167 emit_insn (gen_divsi_inv20 (scratch2,
3168 norm32, scratch4, dividend,
3169 scratch6, scratch3, i43,
3170 /* scratch0 may be shared with i2p27. */
3171 scratch0, scratch1, scratch5,
3172 label, label, i2p27));
3174 emit_insn (gen_ashrdi3_media (scratch2, scratch2, shift));
3175 emit_insn (gen_subdisi3_media (result, scratch2, scratch3));
3179 (define_insn "divsi_inv20"
3180 [(set (match_operand:DI 0 "register_operand" "=&r")
3181 (unspec:DI [(match_operand:SI 1 "register_operand" "r")
3182 (match_operand:SI 2 "register_operand" "r")
3183 (match_operand:SI 3 "register_operand" "r")
3184 (match_operand:DI 4 "register_operand" "r")
3185 (match_operand:DI 5 "register_operand" "r")
3186 (match_operand:DI 6 "register_operand" "r")
3187 (match_operand:DI 12 "register_operand" "r")
3188 (match_operand 10 "target_operand" "b")
3189 (match_operand 11 "immediate_operand" "i")]
3191 (clobber (match_operand:DI 7 "register_operand" "=&r"))
3192 (clobber (match_operand:DI 8 "register_operand" "=&r"))
3193 (clobber (match_operand:SI 9 "register_operand" "=r"))]
3195 && (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
3197 /* operands: %0 div_result, %1 norm32, %2 inv1, %3 dividend,
3198 %4 dividend_nsb, %5 result_sign, %6 i43, %12 i2p27,
3199 %7 round_scratch, %8 scratch0 (di), %9 scratch1 (si)
3200 %10 label (tr), %11 label (imm)
3202 muls.l inv1, norm32, scratch0 // s2.60
3203 muls.l inv1, dividend, result // s32.30
3204 xor i2p27, result_sign, round_scratch
3205 bge/u dividend_nsb, i43, tr.. (label)
3206 shari scratch0, 16, scratch0 // s-16.44
3207 muls.l sratch0_si, inv1, scratch0 // s-16.74
3208 sub result, round_scratch, result
3209 shari dividend, 14, scratch1 // s19.-14
3210 shari scratch0, 30, scratch0 // s-16.44
3211 muls.l scratch0, scratch1, round_scratch // s15.30
3213 sub result, round_scratch, result */
3215 const bool likely = TARGET_DIVIDE_INV20L;
3218 "muls.l %2, %3, %0" "\n"
3219 " xor %12, %5, %7" "\n"
3220 " bge/l %4, %6, %10" "\n"
3221 " muls.l %2, %1, %8" "\n"
3222 " shari %8, 16, %8" "\n"
3223 " muls.l %8, %2, %8" "\n"
3224 " shari %3, 14, %9" "\n"
3225 " shari %8, 30, %8" "\n"
3226 " muls.l %8, %9, %8" "\n"
3227 " sub %0, %8, %0" "\n"
3228 "%11: add %0, %7, %0";
3231 "muls.l %2, %1, %8" "\n"
3232 " muls.l %2, %3, %0" "\n"
3233 " xor %12, %5, %7" "\n"
3234 " bge/u %4, %6, %10" "\n"
3235 " shari %8, 16, %8" "\n"
3236 " muls.l %8, %2, %8" "\n"
3237 " sub %0, %7, %0" "\n"
3238 " shari %3, 14, %9" "\n"
3239 " shari %8, 30, %8" "\n"
3240 " muls.l %8, %9, %7" "\n"
3241 "%11: sub %0, %7, %0";
3244 (define_insn_and_split "divsi_inv_fp"
3245 [(set (match_operand:SI 0 "general_movdst_operand" "=rf")
3246 (div:SI (match_operand:SI 1 "general_movsrc_operand" "rf")
3247 (match_operand:SI 2 "register_operand" "rf")))
3248 (use (match_operand:SI 3 "general_movsrc_operand" "r"))
3249 (clobber (match_operand:SI 4 "register_operand" "=r"))
3250 (clobber (match_operand:SI 5 "register_operand" "=r"))
3251 (clobber (match_operand:DF 6 "register_operand" "=r"))
3252 (clobber (match_operand:DF 7 "register_operand" "=r"))
3253 (clobber (match_operand:DF 8 "register_operand" "=r"))]
3254 "TARGET_SHMEDIA_FPU"
3256 "&& (reload_in_progress || reload_completed)"
3257 [(set (match_dup 0) (match_dup 3))]
3259 [(set_attr "highpart" "must_split")])
3261 ;; If a matching group of divide-by-inverse instructions is in the same
3262 ;; basic block after gcse & loop optimizations, we want to transform them
3263 ;; to a straight division using floating point for TARGET_DIVIDE_INV_FP.
3264 (define_insn_and_split "*divsi_inv_fp_combine"
3265 [(set (match_operand:SI 0 "register_operand" "=f")
3266 (div:SI (match_operand:SI 1 "register_operand" "f")
3267 (match_operand:SI 2 "register_operand" "f")))
3268 (use (unspec:SI [(match_dup 1)
3269 (match_operand:SI 3 "" "")
3270 (unspec:SI [(match_operand:SI 4 "" "")
3272 (match_operand:DI 5 "" "")] UNSPEC_DIV_INV_M2)
3273 (match_operand:DI 6 "" "")
3275 (const_int 0)] UNSPEC_DIV_INV_M3))
3276 (clobber (match_operand:SI 7 "fp_arith_reg_operand" ""))
3277 (clobber (match_operand:SI 8 "fp_arith_reg_operand" ""))
3278 (clobber (match_operand:DF 9 "fp_arith_reg_operand" ""))
3279 (clobber (match_operand:DF 10 "fp_arith_reg_operand" ""))
3280 (clobber (match_operand:DF 11 "fp_arith_reg_operand" ""))]
3281 "TARGET_SHMEDIA_FPU && TARGET_DIVIDE_INV_FP && !can_create_pseudo_p ()"
3284 [(set (match_dup 9) (float:DF (match_dup 1)))
3285 (set (match_dup 10) (float:DF (match_dup 2)))
3286 (set (match_dup 11) (div:DF (match_dup 9) (match_dup 10)))
3288 (fix:SI (match_dup 11)))
3289 (set (match_dup 0) (match_dup 8))]
3291 if (! fp_arith_reg_operand (operands[1], SImode))
3293 emit_move_insn (operands[7], operands[1]);
3294 operands[1] = operands[7];
3296 if (! fp_arith_reg_operand (operands[2], SImode))
3298 emit_move_insn (operands[8], operands[2]);
3299 operands[2] = operands[8];
3302 [(set_attr "highpart" "must_split")])
3304 ;; -------------------------------------------------------------------------
3305 ;; Multiplication instructions
3306 ;; -------------------------------------------------------------------------
3308 (define_insn "umulhisi3_i"
3309 [(set (reg:SI MACL_REG)
3310 (mult:SI (zero_extend:SI
3311 (match_operand:HI 0 "arith_reg_operand" "r"))
3313 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3316 [(set_attr "type" "smpy")])
3318 (define_insn "mulhisi3_i"
3319 [(set (reg:SI MACL_REG)
3320 (mult:SI (sign_extend:SI
3321 (match_operand:HI 0 "arith_reg_operand" "r"))
3323 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3326 [(set_attr "type" "smpy")])
3328 (define_expand "mulhisi3"
3329 [(set (reg:SI MACL_REG)
3330 (mult:SI (sign_extend:SI
3331 (match_operand:HI 1 "arith_reg_operand" ""))
3333 (match_operand:HI 2 "arith_reg_operand" ""))))
3334 (set (match_operand:SI 0 "arith_reg_operand" "")
3340 macl = gen_rtx_REG (SImode, MACL_REG);
3342 emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
3343 insn = get_insns ();
3345 /* expand_binop can't find a suitable code in umul_widen_optab to
3346 make a REG_EQUAL note from, so make one here.
3347 See also smulsi3_highpart.
3348 ??? Alternatively, we could put this at the calling site of expand_binop,
3349 i.e. expand_expr. */
3350 /* Use emit_libcall_block for loop invariant code motion and to make
3351 a REG_EQUAL note. */
3352 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3357 (define_expand "umulhisi3"
3358 [(set (reg:SI MACL_REG)
3359 (mult:SI (zero_extend:SI
3360 (match_operand:HI 1 "arith_reg_operand" ""))
3362 (match_operand:HI 2 "arith_reg_operand" ""))))
3363 (set (match_operand:SI 0 "arith_reg_operand" "")
3369 macl = gen_rtx_REG (SImode, MACL_REG);
3371 emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
3372 insn = get_insns ();
3374 /* expand_binop can't find a suitable code in umul_widen_optab to
3375 make a REG_EQUAL note from, so make one here.
3376 See also smulsi3_highpart.
3377 ??? Alternatively, we could put this at the calling site of expand_binop,
3378 i.e. expand_expr. */
3379 /* Use emit_libcall_block for loop invariant code motion and to make
3380 a REG_EQUAL note. */
3381 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3386 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
3387 ;; a call to a routine which clobbers known registers.
3389 [(set (match_operand:SI 1 "register_operand" "=z")
3390 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
3391 (clobber (reg:SI MACL_REG))
3392 (clobber (reg:SI T_REG))
3393 (clobber (reg:SI PR_REG))
3394 (clobber (reg:SI R3_REG))
3395 (clobber (reg:SI R2_REG))
3396 (clobber (reg:SI R1_REG))
3397 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
3400 [(set_attr "type" "sfunc")
3401 (set_attr "needs_delay_slot" "yes")])
3403 (define_expand "mulsi3_call"
3404 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
3405 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
3406 (parallel[(set (match_operand:SI 0 "register_operand" "")
3407 (mult:SI (reg:SI R4_REG)
3409 (clobber (reg:SI MACL_REG))
3410 (clobber (reg:SI T_REG))
3411 (clobber (reg:SI PR_REG))
3412 (clobber (reg:SI R3_REG))
3413 (clobber (reg:SI R2_REG))
3414 (clobber (reg:SI R1_REG))
3415 (use (match_operand:SI 3 "register_operand" ""))])]
3419 (define_insn "mul_r"
3420 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3421 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
3422 (match_operand:SI 2 "arith_reg_operand" "z")))]
3425 [(set_attr "type" "dmpy")])
3427 (define_insn "mul_l"
3428 [(set (reg:SI MACL_REG)
3429 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
3430 (match_operand:SI 1 "arith_reg_operand" "r")))]
3433 [(set_attr "type" "dmpy")])
3435 (define_expand "mulsi3"
3436 [(set (reg:SI MACL_REG)
3437 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
3438 (match_operand:SI 2 "arith_reg_operand" "")))
3439 (set (match_operand:SI 0 "arith_reg_operand" "")
3445 /* The address must be set outside the libcall,
3446 since it goes into a pseudo. */
3447 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC);
3448 rtx addr = force_reg (SImode, sym);
3449 rtx insns = gen_mulsi3_call (operands[0], operands[1],
3455 rtx macl = gen_rtx_REG (SImode, MACL_REG);
3457 emit_insn (gen_mul_l (operands[1], operands[2]));
3458 /* consec_sets_giv can only recognize the first insn that sets a
3459 giv as the giv insn. So we must tag this also with a REG_EQUAL
3461 emit_insn (gen_movsi_i ((operands[0]), macl));
3466 (define_insn "mulsidi3_i"
3467 [(set (reg:SI MACH_REG)
3471 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3472 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3474 (set (reg:SI MACL_REG)
3475 (mult:SI (match_dup 0)
3479 [(set_attr "type" "dmpy")])
3481 (define_expand "mulsidi3"
3482 [(set (match_operand:DI 0 "arith_reg_dest" "")
3483 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3484 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3485 "TARGET_SH2 || TARGET_SHMEDIA"
3489 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2]));
3494 (define_insn "mulsidi3_media"
3495 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3496 (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3497 (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3500 [(set_attr "type" "dmpy_media")
3501 (set_attr "highpart" "ignore")])
3503 (define_insn_and_split "mulsidi3_compact"
3504 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3506 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3507 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3508 (clobber (reg:SI MACH_REG))
3509 (clobber (reg:SI MACL_REG))]
3515 rtx low_dst = gen_lowpart (SImode, operands[0]);
3516 rtx high_dst = gen_highpart (SImode, operands[0]);
3518 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
3520 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3521 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3522 /* We need something to tag the possible REG_EQUAL notes on to. */
3523 emit_move_insn (operands[0], operands[0]);
3527 (define_insn "umulsidi3_i"
3528 [(set (reg:SI MACH_REG)
3532 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3533 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3535 (set (reg:SI MACL_REG)
3536 (mult:SI (match_dup 0)
3540 [(set_attr "type" "dmpy")])
3542 (define_expand "umulsidi3"
3543 [(set (match_operand:DI 0 "arith_reg_dest" "")
3544 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3545 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3546 "TARGET_SH2 || TARGET_SHMEDIA"
3550 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2]));
3555 (define_insn "umulsidi3_media"
3556 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3557 (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3558 (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3561 [(set_attr "type" "dmpy_media")
3562 (set_attr "highpart" "ignore")])
3564 (define_insn_and_split "umulsidi3_compact"
3565 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3567 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3568 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3569 (clobber (reg:SI MACH_REG))
3570 (clobber (reg:SI MACL_REG))]
3576 rtx low_dst = gen_lowpart (SImode, operands[0]);
3577 rtx high_dst = gen_highpart (SImode, operands[0]);
3579 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
3581 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3582 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3583 /* We need something to tag the possible REG_EQUAL notes on to. */
3584 emit_move_insn (operands[0], operands[0]);
3588 (define_insn "smulsi3_highpart_i"
3589 [(set (reg:SI MACH_REG)
3593 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3594 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3596 (clobber (reg:SI MACL_REG))]
3599 [(set_attr "type" "dmpy")])
3601 (define_expand "smulsi3_highpart"
3603 [(set (reg:SI MACH_REG)
3607 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3608 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3610 (clobber (reg:SI MACL_REG))])
3611 (set (match_operand:SI 0 "arith_reg_operand" "")
3617 mach = gen_rtx_REG (SImode, MACH_REG);
3619 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
3620 insn = get_insns ();
3622 /* expand_binop can't find a suitable code in mul_highpart_optab to
3623 make a REG_EQUAL note from, so make one here.
3624 See also {,u}mulhisi.
3625 ??? Alternatively, we could put this at the calling site of expand_binop,
3626 i.e. expand_mult_highpart. */
3627 /* Use emit_libcall_block for loop invariant code motion and to make
3628 a REG_EQUAL note. */
3629 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3634 (define_insn "umulsi3_highpart_i"
3635 [(set (reg:SI MACH_REG)
3639 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3640 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3642 (clobber (reg:SI MACL_REG))]
3645 [(set_attr "type" "dmpy")])
3647 (define_expand "umulsi3_highpart"
3649 [(set (reg:SI MACH_REG)
3653 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3654 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3656 (clobber (reg:SI MACL_REG))])
3657 (set (match_operand:SI 0 "arith_reg_operand" "")
3663 mach = gen_rtx_REG (SImode, MACH_REG);
3665 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
3666 insn = get_insns ();
3668 /* Use emit_libcall_block for loop invariant code motion and to make
3669 a REG_EQUAL note. */
3670 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3675 (define_insn_and_split "muldi3"
3676 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3677 (mult:DI (match_operand:DI 1 "arith_reg_operand" "r")
3678 (match_operand:DI 2 "arith_reg_operand" "r")))
3679 (clobber (match_scratch:DI 3 "=&r"))
3680 (clobber (match_scratch:DI 4 "=r"))]
3686 rtx op3_v2si, op2_v2si;
3688 op3_v2si = operands[3];
3689 if (GET_CODE (op3_v2si) == SIGN_EXTEND)
3691 op3_v2si = XEXP (op3_v2si, 0);
3692 op3_v2si = simplify_gen_subreg (DImode, op3_v2si, GET_MODE (op3_v2si), 0);
3694 op3_v2si = simplify_gen_subreg (V2SImode, op3_v2si, DImode, 0);
3695 op2_v2si = operands[2];
3696 if (GET_CODE (op2_v2si) == SIGN_EXTEND)
3698 op2_v2si = XEXP (op2_v2si, 0);
3699 op2_v2si = simplify_gen_subreg (DImode, op2_v2si, GET_MODE (op2_v2si), 0);
3701 op2_v2si = simplify_gen_subreg (V2SImode, op2_v2si, DImode, 0);
3702 emit_insn (gen_rotldi3 (operands[3], operands[1], GEN_INT (32)));
3703 emit_insn (gen_mulv2si3 (op3_v2si, op3_v2si, op2_v2si));
3704 emit_insn (gen_umulsidi3_media (operands[4],
3705 sh_gen_truncate (SImode, operands[1], 0),
3706 sh_gen_truncate (SImode, operands[2], 0)));
3707 emit_insn (gen_anddi3 (operands[0], operands[3], GEN_INT (0xffffffff00000000LL)));
3708 emit_insn (gen_ashldi3_media (operands[3], operands[3], GEN_INT (32)));
3709 emit_insn (gen_adddi3 (operands[0], operands[3], operands[0]));
3710 emit_insn (gen_adddi3 (operands[0], operands[4], operands[0]));
3714 ;; -------------------------------------------------------------------------
3715 ;; Logical operations
3716 ;; -------------------------------------------------------------------------
3718 (define_expand "andsi3"
3719 [(set (match_operand:SI 0 "arith_reg_operand" "")
3720 (and:SI (match_operand:SI 1 "logical_reg_operand" "")
3721 (match_operand:SI 2 "logical_and_operand" "")))]
3724 /* If it is possible to turn the and insn into a zero extension
3725 already, redundant zero extensions will be folded, which results
3727 Ideally the splitter of *andsi_compact would be enough, if redundant
3728 zero extensions were detected after the combine pass, which does not
3729 happen at the moment. */
3732 if (satisfies_constraint_Jmb (operands[2]))
3734 emit_insn (gen_zero_extendqisi2 (operands[0],
3735 gen_lowpart (QImode, operands[1])));
3738 else if (satisfies_constraint_Jmw (operands[2]))
3740 emit_insn (gen_zero_extendhisi2 (operands[0],
3741 gen_lowpart (HImode, operands[1])));
3747 (define_insn_and_split "*andsi_compact"
3748 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
3749 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
3750 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
3758 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
3760 if (satisfies_constraint_Jmb (operands[2]))
3761 operands[1] = gen_lowpart (QImode, operands[1]);
3762 else if (satisfies_constraint_Jmw (operands[2]))
3763 operands[1] = gen_lowpart (HImode, operands[1]);
3767 [(set_attr "type" "arith")])
3769 (define_insn "*andsi3_media"
3770 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3771 (and:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3772 (match_operand:SI 2 "logical_operand" "r,I10")))]
3777 [(set_attr "type" "arith_media")])
3779 (define_insn "*andsi3_bclr"
3780 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3781 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3782 (match_operand:SI 2 "const_int_operand" "Psz")))]
3783 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
3785 [(set_attr "type" "arith")])
3787 (define_insn_and_split "anddi3"
3788 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r")
3789 (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
3790 (match_operand:DI 2 "and_operand" "r,I10,J16")))]
3797 && ! logical_operand (operands[2], DImode)"
3800 if ((unsigned)INTVAL (operands[2]) == (unsigned) 0xffffffff)
3801 emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
3803 emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
3806 [(set_attr "type" "arith_media")])
3808 (define_insn "andcsi3"
3809 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3810 (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
3811 (not:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3814 [(set_attr "type" "arith_media")])
3816 (define_insn "andcdi3"
3817 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3818 (and:DI (match_operand:DI 1 "arith_reg_operand" "r")
3819 (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
3822 [(set_attr "type" "arith_media")])
3824 (define_expand "iorsi3"
3825 [(set (match_operand:SI 0 "arith_reg_operand" "")
3826 (ior:SI (match_operand:SI 1 "logical_reg_operand" "")
3827 (match_operand:SI 2 "logical_operand" "")))]
3831 (define_insn "*iorsi3_compact"
3832 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
3833 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3834 (match_operand:SI 2 "logical_operand" "r,K08")))]
3836 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
3838 [(set_attr "type" "arith")])
3840 (define_insn "*iorsi3_media"
3841 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3842 (ior:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3843 (match_operand:SI 2 "logical_operand" "r,I10")))]
3848 [(set_attr "type" "arith_media")])
3850 (define_insn "*iorsi3_bset"
3851 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3852 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3853 (match_operand:SI 2 "const_int_operand" "Pso")))]
3854 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
3856 [(set_attr "type" "arith")])
3858 (define_insn "iordi3"
3859 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3860 (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3861 (match_operand:DI 2 "logical_operand" "r,I10")))]
3866 [(set_attr "type" "arith_media")])
3868 (define_insn_and_split "*logical_sidi3"
3869 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3870 (sign_extend:DI (match_operator:SI 3 "logical_operator"
3871 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3872 (match_operand:SI 2 "logical_operand" "r,I10")])))]
3875 "&& reload_completed"
3876 [(set (match_dup 0) (match_dup 3))]
3879 = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
3880 simplify_gen_subreg (DImode, operands[1], SImode, 0),
3881 simplify_gen_subreg (DImode, operands[2], SImode, 0));
3884 (define_insn_and_split "*logical_sidisi3"
3885 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3886 (truncate:SI (sign_extend:DI
3887 (match_operator:SI 3 "logical_operator"
3888 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3889 (match_operand:SI 2 "logical_operand" "r,I10")]))))]
3893 [(set (match_dup 0) (match_dup 3))])
3895 (define_insn_and_split "*logical_sidi3_2"
3896 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3897 (sign_extend:DI (truncate:SI (sign_extend:DI
3898 (match_operator:SI 3 "logical_operator"
3899 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3900 (match_operand:SI 2 "logical_operand" "r,I10")])))))]
3904 [(set (match_dup 0) (sign_extend:DI (match_dup 3)))])
3906 (define_expand "xorsi3"
3907 [(set (match_operand:SI 0 "arith_reg_operand" "")
3908 (xor:SI (match_operand:SI 1 "logical_reg_operand" "")
3909 (match_operand:SI 2 "xor_operand" "")))]
3913 (define_insn "*xorsi3_compact"
3914 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
3915 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3916 (match_operand:SI 2 "logical_operand" "K08,r")))]
3919 [(set_attr "type" "arith")])
3921 ;; The *logical_op_t pattern helps combine eliminating sign/zero extensions
3922 ;; of results where one of the inputs is a T bit store. Notice that this
3923 ;; pattern must not match during reload. If reload picks this pattern it
3924 ;; will be impossible to split it afterwards.
3925 (define_insn_and_split "*logical_op_t"
3926 [(set (match_operand:SI 0 "arith_reg_dest")
3927 (match_operator:SI 3 "logical_operator"
3928 [(match_operand:SI 1 "arith_reg_operand")
3929 (match_operand:SI 2 "t_reg_operand")]))]
3930 "TARGET_SH1 && can_create_pseudo_p ()"
3933 [(set (match_dup 4) (reg:SI T_REG))
3934 (set (match_dup 0) (match_dup 3))]
3936 operands[4] = gen_reg_rtx (SImode);
3937 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3938 operands[1], operands[4]);
3941 (define_insn "*xorsi3_media"
3942 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3943 (xor:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3944 (match_operand:SI 2 "xor_operand" "r,I06")))]
3949 [(set_attr "type" "arith_media")])
3951 (define_insn "xordi3"
3952 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3953 (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3954 (match_operand:DI 2 "xor_operand" "r,I06")))]
3959 [(set_attr "type" "arith_media")])
3961 ;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
3962 ;; converts 2 * sign extend -> logical op into logical op -> sign extend
3964 [(set (match_operand:DI 0 "arith_reg_dest" "")
3965 (sign_extend:DI (match_operator 4 "binary_logical_operator"
3966 [(match_operand 1 "any_register_operand" "")
3967 (match_operand 2 "any_register_operand" "")])))]
3969 [(set (match_dup 5) (match_dup 4))
3970 (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
3972 enum machine_mode inmode = GET_MODE (operands[1]);
3975 if (GET_CODE (operands[0]) == SUBREG)
3977 offset = SUBREG_BYTE (operands[0]);
3978 operands[0] = SUBREG_REG (operands[0]);
3980 gcc_assert (REG_P (operands[0]));
3981 if (TARGET_BIG_ENDIAN)
3982 offset += 8 - GET_MODE_SIZE (inmode);
3983 operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
3986 ;; -------------------------------------------------------------------------
3987 ;; Shifts and rotates
3988 ;; -------------------------------------------------------------------------
3990 (define_expand "rotldi3"
3991 [(set (match_operand:DI 0 "arith_reg_dest" "")
3992 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "")
3993 (match_operand:HI 2 "mextr_bit_offset" "")))]
3996 if (! mextr_bit_offset (operands[2], HImode))
4000 (define_insn "rotldi3_mextr"
4001 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4002 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
4003 (match_operand:HI 2 "mextr_bit_offset" "i")))]
4006 static char templ[16];
4007 sprintf (templ, "mextr%d %%1,%%1,%%0",
4008 8 - (int) (INTVAL (operands[2]) >> 3));
4011 [(set_attr "type" "arith_media")])
4013 (define_expand "rotrdi3"
4014 [(set (match_operand:DI 0 "arith_reg_dest" "")
4015 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "")
4016 (match_operand:HI 2 "mextr_bit_offset" "")))]
4019 if (! mextr_bit_offset (operands[2], HImode))
4023 (define_insn "rotrdi3_mextr"
4024 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4025 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
4026 (match_operand:HI 2 "mextr_bit_offset" "i")))]
4029 static char templ[16];
4030 sprintf (templ, "mextr%d %%1,%%1,%%0", (int) INTVAL (operands[2]) >> 3);
4033 [(set_attr "type" "arith_media")])
4036 [(set (match_operand:DI 0 "arith_reg_dest" "")
4037 (ior:DI (zero_extend:DI (mem:QI (match_operand 1
4038 "ua_address_operand" "")))
4039 (ashift:DI (match_operand:DI 2 "arith_reg_operand" "")
4041 (clobber (match_operand:DI 3 "register_operand" ""))]
4043 [(match_dup 4) (match_dup 5)]
4045 operands[4] = ((TARGET_LITTLE_ENDIAN ? gen_ldhi_q : gen_ldlo_q)
4046 (operands[3], operands[1]));
4047 operands[5] = gen_mextr_rl (operands[0], operands[3], operands[2],
4048 GEN_INT (56), GEN_INT (8));
4051 (define_expand "rotrsi3"
4052 [(set (match_operand:SI 0 "arith_reg_dest")
4053 (rotatert:SI (match_operand:SI 1 "arith_reg_operand")
4054 (match_operand:SI 2 "const_int_operand")))]
4057 HOST_WIDE_INT ival = INTVAL (operands[2]);
4060 emit_insn (gen_rotrsi3_1 (operands[0], operands[1]));
4067 (define_insn "rotrsi3_1"
4068 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4069 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
4072 (and:SI (match_dup 1) (const_int 1)))]
4075 [(set_attr "type" "arith")])
4077 ;; A slimplified version of rotr for combine.
4078 (define_insn "*rotrsi3_1"
4079 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4080 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
4082 (clobber (reg:SI T_REG))]
4085 [(set_attr "type" "arith")])
4087 (define_insn "rotlsi3_1"
4088 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4089 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4092 (lshiftrt:SI (match_dup 1) (const_int 31)))]
4095 [(set_attr "type" "arith")])
4097 ;; A simplified version of rotl for combine.
4098 (define_insn "*rotlsi3_1"
4099 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4100 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4102 (clobber (reg:SI T_REG))]
4105 [(set_attr "type" "arith")])
4107 (define_insn "rotlsi3_31"
4108 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4109 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4111 (clobber (reg:SI T_REG))]
4114 [(set_attr "type" "arith")])
4116 (define_insn "rotlsi3_16"
4117 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4118 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
4122 [(set_attr "type" "arith")])
4124 (define_expand "rotlsi3"
4125 [(set (match_operand:SI 0 "arith_reg_dest")
4126 (rotate:SI (match_operand:SI 1 "arith_reg_operand")
4127 (match_operand:SI 2 "const_int_operand")))]
4130 static const char rot_tab[] = {
4131 000, 000, 000, 000, 000, 000, 010, 001,
4132 001, 001, 011, 013, 003, 003, 003, 003,
4133 003, 003, 003, 003, 003, 013, 012, 002,
4134 002, 002, 010, 000, 000, 000, 000, 000,
4137 int count = INTVAL (operands[2]);
4138 int choice = rot_tab[count];
4139 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
4145 emit_move_insn (operands[0], operands[1]);
4146 count -= (count & 16) * 2;
4149 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
4156 parts[0] = gen_reg_rtx (SImode);
4157 parts[1] = gen_reg_rtx (SImode);
4158 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
4159 emit_move_insn (parts[choice-1], operands[1]);
4160 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
4161 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
4162 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
4163 count = (count & ~16) - 8;
4167 for (; count > 0; count--)
4168 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
4169 for (; count < 0; count++)
4170 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
4175 (define_insn "rotlhi3_8"
4176 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4177 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
4181 [(set_attr "type" "arith")])
4183 (define_expand "rotlhi3"
4184 [(set (match_operand:HI 0 "arith_reg_operand")
4185 (rotate:HI (match_operand:HI 1 "arith_reg_operand")
4186 (match_operand:HI 2 "const_int_operand")))]
4189 if (INTVAL (operands[2]) != 8)
4193 ;; The rotcr and rotcl insns are used primarily in DImode shifts by one.
4194 ;; They can also be used to implement things like
4196 ;; int x0 = (y >> 1) | (t << 31); // rotcr
4197 ;; int x1 = (y << 1) | t; // rotcl
4198 (define_insn "rotcr"
4199 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4200 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4202 (ashift:SI (match_operand:SI 2 "t_reg_operand")
4205 (and:SI (match_dup 1) (const_int 1)))]
4208 [(set_attr "type" "arith")])
4210 (define_insn "rotcl"
4211 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4212 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4214 (match_operand:SI 2 "t_reg_operand")))
4216 (lshiftrt:SI (match_dup 1) (const_int 31)))]
4219 [(set_attr "type" "arith")])
4221 ;; Simplified rotcr version for combine, which allows arbitrary shift
4222 ;; amounts for the reg. If the shift amount is '1' rotcr can be used
4223 ;; directly. Otherwise we have to insert a shift in between.
4224 (define_insn_and_split "*rotcr"
4225 [(set (match_operand:SI 0 "arith_reg_dest")
4226 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
4227 (match_operand:SI 2 "const_int_operand"))
4228 (ashift:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
4230 (clobber (reg:SI T_REG))]
4233 "&& can_create_pseudo_p ()"
4236 if (INTVAL (operands[2]) > 1)
4238 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4239 rtx prev_set_t_insn = NULL_RTX;
4240 rtx tmp_t_reg = NULL_RTX;
4242 /* If we're going to emit a shift sequence that clobbers the T_REG,
4243 try to find the previous insn that sets the T_REG and emit the
4244 shift insn before that insn, to remove the T_REG dependency.
4245 If the insn that sets the T_REG cannot be found, store the T_REG
4246 in a temporary reg and restore it after the shift. */
4247 if (sh_lshrsi_clobbers_t_reg_p (shift_count)
4248 && ! sh_dynamicalize_shift_p (shift_count))
4250 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4252 /* Skip the nott insn, which was probably inserted by the splitter
4253 of *rotcr_neg_t. Don't use one of the recog functions
4254 here during insn splitting, since that causes problems in later
4256 if (prev_set_t_insn != NULL_RTX)
4258 rtx pat = PATTERN (prev_set_t_insn);
4259 if (GET_CODE (pat) == SET
4260 && t_reg_operand (XEXP (pat, 0), SImode)
4261 && negt_reg_operand (XEXP (pat, 1), SImode))
4262 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4265 if (! (prev_set_t_insn != NULL_RTX
4266 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4267 && ! reg_referenced_p (get_t_reg_rtx (),
4268 PATTERN (prev_set_t_insn))))
4270 prev_set_t_insn = NULL_RTX;
4271 tmp_t_reg = gen_reg_rtx (SImode);
4272 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4276 rtx shift_result = gen_reg_rtx (SImode);
4277 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count);
4278 operands[1] = shift_result;
4280 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4281 if (prev_set_t_insn != NULL_RTX)
4282 emit_insn_before (shift_insn, prev_set_t_insn);
4284 emit_insn (shift_insn);
4286 /* Restore T_REG if it has been saved before. */
4287 if (tmp_t_reg != NULL_RTX)
4288 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4291 /* For the rotcr insn to work, operands[3] must be in T_REG.
4292 If it is not we can get it there by shifting it right one bit.
4293 In this case T_REG is not an input for this insn, thus we don't have to
4294 pay attention as of where to insert the shlr insn. */
4295 if (! t_reg_operand (operands[3], SImode))
4297 /* We don't care about the shifted result here, only the T_REG. */
4298 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4299 operands[3] = get_t_reg_rtx ();
4302 emit_insn (gen_rotcr (operands[0], operands[1], operands[3]));
4306 ;; If combine tries the same as above but with swapped operands, split
4307 ;; it so that it will try the pattern above.
4309 [(set (match_operand:SI 0 "arith_reg_dest")
4310 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
4312 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4313 (match_operand:SI 3 "const_int_operand"))))]
4314 "TARGET_SH1 && can_create_pseudo_p ()"
4315 [(parallel [(set (match_dup 0)
4316 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4317 (ashift:SI (match_dup 1) (const_int 31))))
4318 (clobber (reg:SI T_REG))])])
4320 ;; Basically the same as the rotcr pattern above, but for rotcl.
4321 ;; FIXME: Fold copy pasted split code for rotcr and rotcl.
4322 (define_insn_and_split "*rotcl"
4323 [(set (match_operand:SI 0 "arith_reg_dest")
4324 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4325 (match_operand:SI 2 "const_int_operand"))
4326 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
4328 (clobber (reg:SI T_REG))]
4331 "&& can_create_pseudo_p ()"
4334 gcc_assert (INTVAL (operands[2]) > 0);
4336 if (INTVAL (operands[2]) > 1)
4338 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4339 rtx prev_set_t_insn = NULL_RTX;
4340 rtx tmp_t_reg = NULL_RTX;
4342 /* If we're going to emit a shift sequence that clobbers the T_REG,
4343 try to find the previous insn that sets the T_REG and emit the
4344 shift insn before that insn, to remove the T_REG dependency.
4345 If the insn that sets the T_REG cannot be found, store the T_REG
4346 in a temporary reg and restore it after the shift. */
4347 if (sh_ashlsi_clobbers_t_reg_p (shift_count)
4348 && ! sh_dynamicalize_shift_p (shift_count))
4350 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4352 /* Skip the nott insn, which was probably inserted by the splitter
4353 of *rotcl_neg_t. Don't use one of the recog functions
4354 here during insn splitting, since that causes problems in later
4356 if (prev_set_t_insn != NULL_RTX)
4358 rtx pat = PATTERN (prev_set_t_insn);
4359 if (GET_CODE (pat) == SET
4360 && t_reg_operand (XEXP (pat, 0), SImode)
4361 && negt_reg_operand (XEXP (pat, 1), SImode))
4362 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4365 if (! (prev_set_t_insn != NULL_RTX
4366 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4367 && ! reg_referenced_p (get_t_reg_rtx (),
4368 PATTERN (prev_set_t_insn))))
4370 prev_set_t_insn = NULL_RTX;
4371 tmp_t_reg = gen_reg_rtx (SImode);
4372 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4376 rtx shift_result = gen_reg_rtx (SImode);
4377 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count);
4378 operands[1] = shift_result;
4380 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4381 if (prev_set_t_insn != NULL_RTX)
4382 emit_insn_before (shift_insn, prev_set_t_insn);
4384 emit_insn (shift_insn);
4386 /* Restore T_REG if it has been saved before. */
4387 if (tmp_t_reg != NULL_RTX)
4388 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4391 /* For the rotcl insn to work, operands[3] must be in T_REG.
4392 If it is not we can get it there by shifting it right one bit.
4393 In this case T_REG is not an input for this insn, thus we don't have to
4394 pay attention as of where to insert the shlr insn. */
4395 if (! t_reg_operand (operands[3], SImode))
4397 /* We don't care about the shifted result here, only the T_REG. */
4398 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4399 operands[3] = get_t_reg_rtx ();
4402 emit_insn (gen_rotcl (operands[0], operands[1], operands[3]));
4406 ;; rotcl combine pattern variations
4407 (define_insn_and_split "*rotcl"
4408 [(set (match_operand:SI 0 "arith_reg_dest")
4409 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4410 (match_operand:SI 2 "const_int_operand"))
4411 (match_operand:SI 3 "t_reg_operand")))
4412 (clobber (reg:SI T_REG))]
4415 "&& can_create_pseudo_p ()"
4416 [(parallel [(set (match_dup 0)
4417 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4418 (and:SI (match_dup 3) (const_int 1))))
4419 (clobber (reg:SI T_REG))])])
4421 (define_insn_and_split "*rotcl"
4422 [(set (match_operand:SI 0 "arith_reg_dest")
4423 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
4425 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4426 (match_operand:SI 3 "const_int_operand"))))
4427 (clobber (reg:SI T_REG))]
4430 "&& can_create_pseudo_p ()"
4431 [(parallel [(set (match_dup 0)
4432 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4433 (and:SI (match_dup 1) (const_int 1))))
4434 (clobber (reg:SI T_REG))])])
4436 (define_insn_and_split "*rotcl"
4437 [(set (match_operand:SI 0 "arith_reg_dest")
4438 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4439 (match_operand:SI 2 "const_int_operand"))
4440 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4442 (clobber (reg:SI T_REG))]
4445 "&& can_create_pseudo_p ()"
4446 [(parallel [(set (match_dup 0)
4447 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4448 (and:SI (reg:SI T_REG) (const_int 1))))
4449 (clobber (reg:SI T_REG))])]
4451 /* We don't care about the result of the left shift, only the T_REG. */
4452 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4455 (define_insn_and_split "*rotcl"
4456 [(set (match_operand:SI 0 "arith_reg_dest")
4457 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4459 (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4460 (match_operand:SI 2 "const_int_operand"))))
4461 (clobber (reg:SI T_REG))]
4464 "&& can_create_pseudo_p ()"
4465 [(parallel [(set (match_dup 0)
4466 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4467 (and:SI (reg:SI T_REG) (const_int 1))))
4468 (clobber (reg:SI T_REG))])]
4470 /* We don't care about the result of the left shift, only the T_REG. */
4471 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4474 ;; rotcr combine bridge pattern which will make combine try out more
4475 ;; complex patterns.
4476 (define_insn_and_split "*rotcr"
4477 [(set (match_operand:SI 0 "arith_reg_dest")
4478 (ashift:SI (match_operand:SI 1 "t_reg_operand") (const_int 31)))]
4482 [(set (match_dup 0) (match_dup 1))
4483 (parallel [(set (match_dup 0)
4484 (ior:SI (lshiftrt:SI (match_dup 0) (const_int 1))
4485 (ashift:SI (match_dup 1) (const_int 31))))
4487 (and:SI (match_dup 0) (const_int 1)))])])
4489 (define_insn_and_split "*rotcr"
4490 [(set (match_operand:SI 0 "arith_reg_dest")
4491 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
4492 (const_int -2147483648)) ;; 0xffffffff80000000
4493 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4495 (clobber (reg:SI T_REG))]
4498 "&& can_create_pseudo_p ()"
4501 rtx tmp = gen_reg_rtx (SImode);
4502 emit_insn (gen_shll (tmp, operands[1]));
4503 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ()));
4507 ;; rotcr combine patterns for rotating in the negated T_REG value.
4508 (define_insn_and_split "*rotcr_neg_t"
4509 [(set (match_operand:SI 0 "arith_reg_dest")
4510 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand")
4511 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4512 (match_operand:SI 3 "const_int_operand"))))
4513 (clobber (reg:SI T_REG))]
4516 "&& can_create_pseudo_p ()"
4517 [(parallel [(set (match_dup 0)
4518 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4519 (ashift:SI (reg:SI T_REG) (const_int 31))))
4520 (clobber (reg:SI T_REG))])]
4522 emit_insn (gen_nott (get_t_reg_rtx ()));
4525 (define_insn_and_split "*rotcr_neg_t"
4526 [(set (match_operand:SI 0 "arith_reg_dest")
4527 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
4528 (match_operand:SI 2 "const_int_operand"))
4529 (match_operand:SI 3 "negt_reg_shl31_operand")))
4530 (clobber (reg:SI T_REG))]
4533 "&& can_create_pseudo_p ()"
4534 [(parallel [(set (match_dup 0)
4535 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4536 (ashift:SI (reg:SI T_REG) (const_int 31))))
4537 (clobber (reg:SI T_REG))])]
4539 emit_insn (gen_nott (get_t_reg_rtx ()));
4542 ;; rotcl combine patterns for rotating in the negated T_REG value.
4543 ;; For some strange reason these have to be specified as splits which combine
4544 ;; will pick up. If they are specified as insn_and_split like the
4545 ;; *rotcr_neg_t patterns above, combine would recognize them successfully
4546 ;; but not emit them on non-SH2A targets.
4548 [(set (match_operand:SI 0 "arith_reg_dest")
4549 (ior:SI (match_operand:SI 1 "negt_reg_operand")
4550 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4551 (match_operand:SI 3 "const_int_operand"))))]
4553 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4554 (parallel [(set (match_dup 0)
4555 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4556 (and:SI (reg:SI T_REG) (const_int 1))))
4557 (clobber (reg:SI T_REG))])])
4560 [(set (match_operand:SI 0 "arith_reg_dest")
4561 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4562 (match_operand:SI 3 "const_int_operand"))
4563 (match_operand:SI 1 "negt_reg_operand")))]
4565 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4566 (parallel [(set (match_dup 0)
4567 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4568 (and:SI (reg:SI T_REG) (const_int 1))))
4569 (clobber (reg:SI T_REG))])])
4571 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4572 ;; SImode shift left
4574 (define_expand "ashlsi3"
4575 [(set (match_operand:SI 0 "arith_reg_operand" "")
4576 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
4577 (match_operand:SI 2 "shift_count_operand" "")))]
4582 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
4584 operands[2] = GEN_INT (-INTVAL (operands[2]));
4585 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
4588 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
4592 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
4593 operands[2] = force_reg (SImode, operands[2]);
4595 /* If the ashlsi3_* insn is going to clobber the T_REG it must be
4597 if (CONST_INT_P (operands[2])
4598 && sh_ashlsi_clobbers_t_reg_p (operands[2])
4599 && ! sh_dynamicalize_shift_p (operands[2]))
4601 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1],
4606 /* Expand a library call for the dynamic shift. */
4607 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
4609 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
4610 rtx funcaddr = gen_reg_rtx (Pmode);
4611 function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC);
4612 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr));
4618 (define_insn "ashlsi3_k"
4619 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4620 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
4621 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))]
4626 [(set_attr "type" "arith")])
4628 (define_insn_and_split "ashlsi3_d"
4629 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4630 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4631 (match_operand:SI 2 "shift_count_operand" "r")))]
4634 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
4635 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4638 if (satisfies_constraint_P27 (operands[2]))
4640 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2]));
4643 else if (! satisfies_constraint_P27 (operands[2]))
4645 /* This must happen before reload, otherwise the constant will be moved
4646 into a register due to the "r" constraint, after which this split
4647 cannot be done anymore.
4648 Unfortunately the move insn will not always be eliminated.
4649 Also, here we must not create a shift sequence that clobbers the
4651 emit_move_insn (operands[0], operands[1]);
4652 gen_shifty_op (ASHIFT, operands);
4658 [(set_attr "type" "dyn_shift")])
4660 ;; If dynamic shifts are not available use a library function.
4661 ;; By specifying the pattern we reduce the number of call clobbered regs.
4662 ;; In order to make combine understand the truncation of the shift amount
4663 ;; operand we have to allow it to use pseudo regs for the shift operands.
4664 (define_insn "ashlsi3_d_call"
4665 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
4666 (ashift:SI (reg:SI R4_REG)
4667 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
4669 (use (match_operand:SI 2 "arith_reg_operand" "r"))
4670 (clobber (reg:SI T_REG))
4671 (clobber (reg:SI PR_REG))]
4672 "TARGET_SH1 && !TARGET_DYNSHIFT"
4674 [(set_attr "type" "sfunc")
4675 (set_attr "needs_delay_slot" "yes")])
4677 (define_insn_and_split "ashlsi3_n"
4678 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4679 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4680 (match_operand:SI 2 "not_p27_shift_count_operand" "")))]
4681 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4683 "&& (reload_completed
4684 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4687 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4689 /* If this pattern was picked and dynamic shifts are supported, switch
4690 to dynamic shift pattern before reload. */
4691 operands[2] = force_reg (SImode, operands[2]);
4692 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
4695 gen_shifty_op (ASHIFT, operands);
4700 (define_insn_and_split "ashlsi3_n_clobbers_t"
4701 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4702 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4703 (match_operand:SI 2 "not_p27_shift_count_operand" "")))
4704 (clobber (reg:SI T_REG))]
4705 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])"
4707 "&& (reload_completed || INTVAL (operands[2]) == 31
4708 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4711 if (INTVAL (operands[2]) == 31)
4713 /* If the shift amount is 31 we split into a different sequence before
4714 reload so that it gets a chance to allocate R0 for the sequence.
4715 If it fails to do so (due to pressure on R0), it will take one insn
4716 more for the and. */
4717 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx));
4718 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
4720 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4722 /* If this pattern was picked and dynamic shifts are supported, switch
4723 to dynamic shift pattern before reload. */
4724 operands[2] = force_reg (SImode, operands[2]);
4725 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
4728 gen_shifty_op (ASHIFT, operands);
4734 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4735 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
4737 (lt:SI (match_dup 1) (const_int 0)))]
4740 [(set_attr "type" "arith")])
4742 (define_insn "*ashlsi_c_void"
4743 [(set (reg:SI T_REG)
4744 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
4745 (clobber (match_scratch:SI 1 "=0"))]
4746 "TARGET_SH1 && cse_not_expected"
4748 [(set_attr "type" "arith")])
4751 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
4753 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
4755 && peep2_reg_dead_p (2, operands[0])
4756 && peep2_reg_dead_p (2, operands[1])"
4759 emit_insn (gen_shll (operands[1], operands[1]));
4763 (define_insn "ashlsi3_media"
4764 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4765 (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
4766 (match_operand:SI 2 "shift_count_operand" "r,n")))]
4771 [(set_attr "type" "arith_media")
4772 (set_attr "highpart" "ignore")])
4774 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4775 ;; HImode shift left
4777 (define_expand "ashlhi3"
4778 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
4779 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
4780 (match_operand:SI 2 "nonmemory_operand" "")))
4781 (clobber (reg:SI T_REG))])]
4784 if (!CONST_INT_P (operands[2]))
4786 /* It may be possible to call gen_ashlhi3 directly with more generic
4787 operands. Make sure operands[1] is a HImode register here. */
4788 if (!arith_reg_operand (operands[1], HImode))
4789 operands[1] = copy_to_mode_reg (HImode, operands[1]);
4792 (define_insn "ashlhi3_k"
4793 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
4794 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
4795 (match_operand:HI 2 "const_int_operand" "M,P27")))]
4796 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
4800 [(set_attr "type" "arith")])
4802 (define_insn_and_split "*ashlhi3_n"
4803 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4804 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
4805 (match_operand:HI 2 "const_int_operand" "n")))
4806 (clobber (reg:SI T_REG))]
4809 "&& reload_completed"
4810 [(use (reg:SI R0_REG))]
4812 gen_shifty_hi_op (ASHIFT, operands);
4816 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4817 ;; DImode shift left
4819 (define_expand "ashldi3"
4820 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4821 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
4822 (match_operand:DI 2 "immediate_operand" "")))
4823 (clobber (reg:SI T_REG))])]
4828 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
4830 operands[2] = GEN_INT (-INTVAL (operands[2]));
4831 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
4834 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
4837 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
4839 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
4842 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
4844 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
4851 ;; Expander for DImode shift left with SImode operations.
4852 (define_expand "ashldi3_std"
4853 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4854 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
4855 (match_operand:DI 2 "const_int_operand" "n")))]
4856 "TARGET_SH1 && INTVAL (operands[2]) < 32"
4858 rtx low_src = gen_lowpart (SImode, operands[1]);
4859 rtx high_src = gen_highpart (SImode, operands[1]);
4860 rtx dst = gen_reg_rtx (DImode);
4861 rtx low_dst = gen_lowpart (SImode, dst);
4862 rtx high_dst = gen_highpart (SImode, dst);
4863 rtx tmp0 = gen_reg_rtx (SImode);
4864 rtx tmp1 = gen_reg_rtx (SImode);
4866 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
4867 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
4868 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
4869 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
4870 emit_move_insn (operands[0], dst);
4874 (define_insn_and_split "ashldi3_k"
4875 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4876 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
4878 (clobber (reg:SI T_REG))]
4881 "&& reload_completed"
4884 rtx high = gen_highpart (SImode, operands[0]);
4885 rtx low = gen_lowpart (SImode, operands[0]);
4886 emit_insn (gen_shll (low, low));
4887 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ()));
4891 (define_insn "ashldi3_media"
4892 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
4893 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
4894 (match_operand:DI 2 "shift_count_operand" "r,n")))]
4899 [(set_attr "type" "arith_media")])
4901 (define_insn "*ashldisi3_media"
4902 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
4903 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
4904 (match_operand:DI 2 "const_int_operand" "n")))]
4905 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
4906 "shlli.l %1, %2, %0"
4907 [(set_attr "type" "arith_media")
4908 (set_attr "highpart" "ignore")])
4910 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4911 ;; SImode arithmetic shift right
4913 ;; We can't do HImode right shifts correctly unless we start out with an
4914 ;; explicit zero / sign extension; doing that would result in worse overall
4915 ;; code, so just let the machine independent code widen the mode.
4916 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
4918 (define_expand "ashrsi3"
4919 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
4920 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
4921 (match_operand:SI 2 "nonmemory_operand" "")))
4922 (clobber (reg:SI T_REG))])]
4927 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
4929 operands[2] = GEN_INT (-INTVAL (operands[2]));
4930 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
4933 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
4936 if (expand_ashiftrt (operands))
4943 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4944 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4947 (and:SI (match_dup 1) (const_int 1)))]
4950 [(set_attr "type" "arith")])
4952 (define_insn "ashrsi3_k"
4953 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4954 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4955 (match_operand:SI 2 "const_int_operand" "M")))
4956 (clobber (reg:SI T_REG))]
4957 "TARGET_SH1 && INTVAL (operands[2]) == 1"
4959 [(set_attr "type" "arith")])
4961 (define_insn_and_split "ashrsi2_16"
4962 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4963 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
4968 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
4969 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
4971 operands[2] = gen_lowpart (HImode, operands[0]);
4974 (define_insn_and_split "ashrsi2_31"
4975 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4976 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4978 (clobber (reg:SI T_REG))]
4984 emit_insn (gen_shll (operands[0], operands[1]));
4985 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
4989 (define_insn "ashrsi3_d"
4990 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4991 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4992 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
4995 [(set_attr "type" "dyn_shift")])
4997 (define_insn "ashrsi3_n"
4998 [(set (reg:SI R4_REG)
4999 (ashiftrt:SI (reg:SI R4_REG)
5000 (match_operand:SI 0 "const_int_operand" "i")))
5001 (clobber (reg:SI T_REG))
5002 (clobber (reg:SI PR_REG))
5003 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
5006 [(set_attr "type" "sfunc")
5007 (set_attr "needs_delay_slot" "yes")])
5009 (define_insn "ashrsi3_media"
5010 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5011 (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
5012 (match_operand:SI 2 "shift_count_operand" "r,n")))]
5017 [(set_attr "type" "arith_media")
5018 (set_attr "highpart" "ignore")])
5020 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5021 ;; DImode arithmetic shift right
5023 (define_expand "ashrdi3"
5024 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5025 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
5026 (match_operand:DI 2 "immediate_operand" "")))
5027 (clobber (reg:SI T_REG))])]
5032 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5034 operands[2] = GEN_INT (-INTVAL (operands[2]));
5035 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
5038 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
5041 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
5045 (define_insn_and_split "ashrdi3_k"
5046 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5047 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
5049 (clobber (reg:SI T_REG))]
5052 "&& reload_completed"
5055 rtx high = gen_highpart (SImode, operands[0]);
5056 rtx low = gen_lowpart (SImode, operands[0]);
5057 emit_insn (gen_shar (high, high));
5058 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
5062 (define_insn "ashrdi3_media"
5063 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
5064 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5065 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5067 && (arith_reg_dest (operands[0], DImode)
5068 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 32))"
5072 [(set_attr "type" "arith_media")])
5074 (define_insn "*ashrdisi3_media"
5075 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5076 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5077 (match_operand:DI 2 "const_int_operand" "n")))]
5078 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5079 "shari.l %1, %2, %0"
5080 [(set_attr "type" "arith_media")
5081 (set_attr "highpart" "ignore")])
5083 (define_insn "ashrdisi3_media_high"
5084 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5086 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5087 (match_operand:DI 2 "const_int_operand" "n"))))]
5088 "TARGET_SHMEDIA && INTVAL (operands[2]) >= 32"
5090 [(set_attr "type" "arith_media")])
5092 (define_insn "ashrdisi3_media_opaque"
5093 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5094 (unspec:SI [(match_operand:DI 1 "arith_reg_operand" "r")
5095 (match_operand:DI 2 "const_int_operand" "n")]
5099 [(set_attr "type" "arith_media")])
5101 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5102 ;; SImode logical shift right
5104 (define_expand "lshrsi3"
5105 [(set (match_operand:SI 0 "arith_reg_dest" "")
5106 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
5107 (match_operand:SI 2 "shift_count_operand" "")))]
5112 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5114 operands[2] = GEN_INT (-INTVAL (operands[2]));
5115 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
5118 emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
5122 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn
5123 here, otherwise the pattern will never match due to the shift amount reg
5126 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
5128 rtx neg_count = force_reg (SImode,
5129 gen_int_mode (- INTVAL (operands[2]), SImode));
5130 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
5134 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2]))
5136 rtx neg_count = gen_reg_rtx (SImode);
5137 emit_insn (gen_negsi2 (neg_count, operands[2]));
5138 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
5142 /* If the lshrsi3_* insn is going to clobber the T_REG it must be
5144 if (CONST_INT_P (operands[2])
5145 && sh_lshrsi_clobbers_t_reg_p (operands[2])
5146 && ! sh_dynamicalize_shift_p (operands[2]))
5148 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1],
5153 /* Expand a library call for the dynamic shift. */
5154 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
5156 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
5157 rtx funcaddr = gen_reg_rtx (Pmode);
5158 function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC);
5159 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr));
5164 (define_insn "lshrsi3_k"
5165 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5166 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5167 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))]
5170 [(set_attr "type" "arith")])
5172 (define_insn_and_split "lshrsi3_d"
5173 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5174 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5175 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))]
5178 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
5179 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5182 if (satisfies_constraint_P27 (operands[2]))
5184 /* This will not be done for a shift amount of 1, because it would
5185 clobber the T_REG. */
5186 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2]));
5189 else if (! satisfies_constraint_P27 (operands[2]))
5191 /* This must happen before reload, otherwise the constant will be moved
5192 into a register due to the "r" constraint, after which this split
5193 cannot be done anymore.
5194 Unfortunately the move insn will not always be eliminated.
5195 Also, here we must not create a shift sequence that clobbers the
5197 emit_move_insn (operands[0], operands[1]);
5198 gen_shifty_op (LSHIFTRT, operands);
5204 [(set_attr "type" "dyn_shift")])
5206 ;; If dynamic shifts are not available use a library function.
5207 ;; By specifying the pattern we reduce the number of call clobbered regs.
5208 ;; In order to make combine understand the truncation of the shift amount
5209 ;; operand we have to allow it to use pseudo regs for the shift operands.
5210 (define_insn "lshrsi3_d_call"
5211 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
5212 (lshiftrt:SI (reg:SI R4_REG)
5213 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
5215 (use (match_operand:SI 2 "arith_reg_operand" "r"))
5216 (clobber (reg:SI T_REG))
5217 (clobber (reg:SI PR_REG))]
5218 "TARGET_SH1 && !TARGET_DYNSHIFT"
5220 [(set_attr "type" "sfunc")
5221 (set_attr "needs_delay_slot" "yes")])
5223 (define_insn_and_split "lshrsi3_n"
5224 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5225 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5226 (match_operand:SI 2 "not_p27_rshift_count_operand")))]
5227 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5229 "&& (reload_completed
5230 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5233 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5235 /* If this pattern was picked and dynamic shifts are supported, switch
5236 to dynamic shift pattern before reload. */
5237 operands[2] = force_reg (SImode,
5238 gen_int_mode (- INTVAL (operands[2]), SImode));
5239 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5242 gen_shifty_op (LSHIFTRT, operands);
5247 ;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of
5248 ;; the shlr pattern.
5249 (define_insn_and_split "lshrsi3_n_clobbers_t"
5250 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5251 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5252 (match_operand:SI 2 "not_p27_rshift_count_operand")))
5253 (clobber (reg:SI T_REG))]
5254 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])"
5256 "&& (reload_completed || INTVAL (operands[2]) == 31
5257 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5260 if (INTVAL (operands[2]) == 31)
5262 emit_insn (gen_shll (operands[0], operands[1]));
5263 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
5265 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5267 /* If this pattern was picked and dynamic shifts are supported, switch
5268 to dynamic shift pattern before reload. */
5269 operands[2] = force_reg (SImode,
5270 gen_int_mode (- INTVAL (operands[2]), SImode));
5271 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5274 gen_shifty_op (LSHIFTRT, operands);
5280 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5281 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5284 (and:SI (match_dup 1) (const_int 1)))]
5287 [(set_attr "type" "arith")])
5289 (define_insn "lshrsi3_media"
5290 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5291 (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
5292 (match_operand:SI 2 "shift_count_operand" "r,n")))]
5297 [(set_attr "type" "arith_media")
5298 (set_attr "highpart" "ignore")])
5300 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5301 ;; DImode logical shift right
5303 (define_expand "lshrdi3"
5304 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5305 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
5306 (match_operand:DI 2 "immediate_operand" "")))
5307 (clobber (reg:SI T_REG))])]
5312 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5314 operands[2] = GEN_INT (-INTVAL (operands[2]));
5315 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
5318 emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
5321 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
5325 (define_insn_and_split "lshrdi3_k"
5326 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5327 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
5329 (clobber (reg:SI T_REG))]
5332 "&& reload_completed"
5335 rtx high = gen_highpart (SImode, operands[0]);
5336 rtx low = gen_lowpart (SImode, operands[0]);
5337 emit_insn (gen_shlr (high, high));
5338 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
5342 (define_insn "lshrdi3_media"
5343 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
5344 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5345 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5347 && (arith_reg_dest (operands[0], DImode)
5348 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 32))"
5352 [(set_attr "type" "arith_media")])
5354 (define_insn "*lshrdisi3_media"
5355 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5356 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5357 (match_operand:DI 2 "const_int_operand" "n")))]
5358 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5359 "shlri.l %1, %2, %0"
5360 [(set_attr "type" "arith_media")
5361 (set_attr "highpart" "ignore")])
5363 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5364 ;; Combined left/right shifts
5367 [(set (match_operand:SI 0 "register_operand" "")
5368 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5369 (match_operand:SI 2 "const_int_operand" ""))
5370 (match_operand:SI 3 "const_int_operand" "")))]
5371 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5372 [(use (reg:SI R0_REG))]
5374 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5380 [(set (match_operand:SI 0 "register_operand" "")
5381 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5382 (match_operand:SI 2 "const_int_operand" ""))
5383 (match_operand:SI 3 "const_int_operand" "")))
5384 (clobber (reg:SI T_REG))]
5385 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5386 [(use (reg:SI R0_REG))]
5388 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5394 [(set (match_operand:SI 0 "register_operand" "=r")
5395 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5396 (match_operand:SI 2 "const_int_operand" "n"))
5397 (match_operand:SI 3 "const_int_operand" "n")))
5398 (clobber (reg:SI T_REG))]
5399 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
5401 [(set (attr "length")
5402 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5404 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5406 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5408 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
5410 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
5412 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
5414 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
5415 (const_string "16")]
5416 (const_string "18")))
5417 (set_attr "type" "arith")])
5420 [(set (match_operand:SI 0 "register_operand" "=z")
5421 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5422 (match_operand:SI 2 "const_int_operand" "n"))
5423 (match_operand:SI 3 "const_int_operand" "n")))
5424 (clobber (reg:SI T_REG))]
5425 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
5427 [(set (attr "length")
5428 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5430 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5432 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5434 (const_string "10")))
5435 (set_attr "type" "arith")])
5437 ;; shift left / and combination with a scratch register: The combine pass
5438 ;; does not accept the individual instructions, even though they are
5439 ;; cheap. But it needs a precise description so that it is usable after
5441 (define_insn "and_shl_scratch"
5442 [(set (match_operand:SI 0 "register_operand" "=r,&r")
5446 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
5447 (match_operand:SI 2 "const_int_operand" "N,n"))
5448 (match_operand:SI 3 "" "0,r"))
5449 (match_operand:SI 4 "const_int_operand" "n,n"))
5450 (match_operand:SI 5 "const_int_operand" "n,n")))
5451 (clobber (reg:SI T_REG))]
5454 [(set (attr "length")
5455 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
5457 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
5459 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
5461 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
5462 (const_string "10")]
5463 (const_string "12")))
5464 (set_attr "type" "arith")])
5467 [(set (match_operand:SI 0 "register_operand" "")
5471 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
5472 (match_operand:SI 2 "const_int_operand" ""))
5473 (match_operand:SI 3 "register_operand" ""))
5474 (match_operand:SI 4 "const_int_operand" ""))
5475 (match_operand:SI 5 "const_int_operand" "")))
5476 (clobber (reg:SI T_REG))]
5478 [(use (reg:SI R0_REG))]
5480 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
5482 if (INTVAL (operands[2]))
5484 gen_shifty_op (LSHIFTRT, operands);
5486 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
5487 operands[2] = operands[4];
5488 gen_shifty_op (ASHIFT, operands);
5489 if (INTVAL (operands[5]))
5491 operands[2] = operands[5];
5492 gen_shifty_op (LSHIFTRT, operands);
5497 ;; signed left/right shift combination.
5499 [(set (match_operand:SI 0 "register_operand" "")
5501 (ashift:SI (match_operand:SI 1 "register_operand" "")
5502 (match_operand:SI 2 "const_int_operand" ""))
5503 (match_operand:SI 3 "const_int_operand" "")
5505 (clobber (reg:SI T_REG))]
5507 [(use (reg:SI R0_REG))]
5509 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1]))
5514 (define_insn "shl_sext_ext"
5515 [(set (match_operand:SI 0 "register_operand" "=r")
5517 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5518 (match_operand:SI 2 "const_int_operand" "n"))
5519 (match_operand:SI 3 "const_int_operand" "n")
5521 (clobber (reg:SI T_REG))]
5522 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
5524 [(set (attr "length")
5525 (cond [(match_test "shl_sext_length (insn)")
5527 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
5529 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5531 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5533 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5535 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5537 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
5539 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
5540 (const_string "16")]
5541 (const_string "18")))
5542 (set_attr "type" "arith")])
5544 (define_insn "shl_sext_sub"
5545 [(set (match_operand:SI 0 "register_operand" "=z")
5547 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5548 (match_operand:SI 2 "const_int_operand" "n"))
5549 (match_operand:SI 3 "const_int_operand" "n")
5551 (clobber (reg:SI T_REG))]
5552 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
5554 [(set (attr "length")
5555 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5557 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5559 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5561 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5562 (const_string "12")]
5563 (const_string "14")))
5564 (set_attr "type" "arith")])
5566 ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
5567 ;; shifts by 16, and allow the xtrct instruction to be generated from C
5569 (define_insn "xtrct_left"
5570 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5571 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5573 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
5577 [(set_attr "type" "arith")])
5579 (define_insn "xtrct_right"
5580 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5581 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5583 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
5587 [(set_attr "type" "arith")])
5589 ;; -------------------------------------------------------------------------
5591 ;; -------------------------------------------------------------------------
5594 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5595 (neg:SI (plus:SI (reg:SI T_REG)
5596 (match_operand:SI 1 "arith_reg_operand" "r"))))
5598 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
5602 [(set_attr "type" "arith")])
5604 ;; A simplified version of the negc insn, where the exact value of the
5605 ;; T bit doesn't matter. This is easier for combine to pick up.
5606 ;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
5607 ;; extra patterns for this case.
5608 (define_insn "*negc"
5609 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5610 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5611 (match_operand:SI 2 "t_reg_operand" "")))
5612 (clobber (reg:SI T_REG))]
5615 [(set_attr "type" "arith")])
5617 (define_insn "*negdi_media"
5618 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5619 (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
5622 [(set_attr "type" "arith_media")])
5624 ;; Don't split into individual negc insns immediately so that neg:DI (abs:DI)
5626 (define_expand "negdi2"
5627 [(parallel [(set (match_operand:DI 0 "arith_reg_dest")
5628 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
5629 (clobber (reg:SI T_REG))])]
5632 (define_insn_and_split "*negdi2"
5633 [(set (match_operand:DI 0 "arith_reg_dest")
5634 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
5635 (clobber (reg:SI T_REG))]
5638 "&& can_create_pseudo_p ()"
5641 emit_insn (gen_clrt ());
5642 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
5643 gen_lowpart (SImode, operands[1])));
5644 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
5645 gen_highpart (SImode, operands[1])));
5649 (define_insn "negsi2"
5650 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5651 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5654 [(set_attr "type" "arith")])
5656 (define_insn_and_split "one_cmplsi2"
5657 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5658 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5661 "&& can_create_pseudo_p ()"
5662 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0)))
5663 (set (match_dup 0) (reg:SI T_REG))]
5666 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following
5669 (set (reg0) (not:SI (reg0) (reg1)))
5670 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31)))
5671 (clobber (reg:SI T_REG))])
5673 ... match and combine the sequence manually in the split pass after the
5674 combine pass. Notice that combine does try the target pattern of this
5675 split, but if the pattern is added it interferes with other patterns, in
5676 particular with the div0s comparisons.
5677 This could also be done with a peephole but doing it here before register
5678 allocation can save one temporary.
5679 When we're here, the not:SI pattern obviously has been matched already
5680 and we only have to see whether the following insn is the left shift. */
5682 rtx i = next_nonnote_insn_bb (curr_insn);
5683 if (i == NULL_RTX || !NONJUMP_INSN_P (i))
5686 rtx p = PATTERN (i);
5687 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2)
5690 rtx p0 = XVECEXP (p, 0, 0);
5691 rtx p1 = XVECEXP (p, 0, 1);
5693 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */
5694 GET_CODE (p0) == SET
5695 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT
5696 && REG_P (XEXP (XEXP (p0, 1), 0))
5697 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0])
5698 && CONST_INT_P (XEXP (XEXP (p0, 1), 1))
5699 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31
5701 /* (clobber (reg:SI T_REG)) */
5702 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0))
5703 && REGNO (XEXP (p1, 0)) == T_REG)
5705 operands[0] = XEXP (p0, 0);
5706 set_insn_deleted (i);
5711 [(set_attr "type" "arith")])
5713 (define_expand "one_cmpldi2"
5714 [(set (match_operand:DI 0 "arith_reg_dest" "")
5715 (xor:DI (match_operand:DI 1 "arith_reg_operand" "")
5717 "TARGET_SHMEDIA" "")
5719 (define_expand "abs<mode>2"
5720 [(parallel [(set (match_operand:SIDI 0 "arith_reg_dest")
5721 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
5722 (clobber (reg:SI T_REG))])]
5725 (define_insn_and_split "*abs<mode>2"
5726 [(set (match_operand:SIDI 0 "arith_reg_dest")
5727 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
5728 (clobber (reg:SI T_REG))]
5731 "&& can_create_pseudo_p ()"
5734 if (<MODE>mode == SImode)
5735 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
5738 rtx high_src = gen_highpart (SImode, operands[1]);
5739 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
5742 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
5747 (define_insn_and_split "*negabs<mode>2"
5748 [(set (match_operand:SIDI 0 "arith_reg_dest")
5749 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))))
5750 (clobber (reg:SI T_REG))]
5753 "&& can_create_pseudo_p ()"
5756 if (<MODE>mode == SImode)
5757 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
5760 rtx high_src = gen_highpart (SImode, operands[1]);
5761 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
5764 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
5769 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
5770 ;; This can be used as some kind of conditional execution, which is useful
5772 ;; Actually the instruction scheduling should decide whether to use a
5773 ;; zero-offset branch or not for any generic case involving a single
5774 ;; instruction on SH4 202.
5775 (define_insn_and_split "negsi_cond"
5776 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5778 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N"))
5779 (match_operand:SI 1 "arith_reg_operand" "0,0")
5780 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
5781 "TARGET_SH1 && TARGET_ZDCBRANCH"
5783 static const char* alt[] =
5793 return alt[which_alternative];
5795 "TARGET_SH1 && ! TARGET_ZDCBRANCH"
5798 rtx skip_neg_label = gen_label_rtx ();
5800 emit_move_insn (operands[0], operands[1]);
5802 emit_jump_insn (INTVAL (operands[3])
5803 ? gen_branch_true (skip_neg_label)
5804 : gen_branch_false (skip_neg_label));
5806 emit_label_after (skip_neg_label,
5807 emit_insn (gen_negsi2 (operands[0], operands[1])));
5810 [(set_attr "type" "arith") ;; poor approximation
5811 (set_attr "length" "4")])
5813 (define_insn_and_split "negdi_cond"
5814 [(set (match_operand:DI 0 "arith_reg_dest")
5816 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand"))
5817 (match_operand:DI 1 "arith_reg_operand")
5818 (neg:DI (match_operand:DI 2 "arith_reg_operand"))))
5819 (clobber (reg:SI T_REG))]
5822 "&& can_create_pseudo_p ()"
5825 rtx skip_neg_label = gen_label_rtx ();
5827 emit_move_insn (operands[0], operands[1]);
5829 emit_jump_insn (INTVAL (operands[3])
5830 ? gen_branch_true (skip_neg_label)
5831 : gen_branch_false (skip_neg_label));
5833 if (!INTVAL (operands[3]))
5834 emit_insn (gen_clrt ());
5836 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
5837 gen_lowpart (SImode, operands[1])));
5838 emit_label_after (skip_neg_label,
5839 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
5840 gen_highpart (SImode, operands[1]))));
5844 (define_expand "bswapsi2"
5845 [(set (match_operand:SI 0 "arith_reg_dest" "")
5846 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
5849 if (! can_create_pseudo_p ())
5853 rtx tmp0 = gen_reg_rtx (SImode);
5854 rtx tmp1 = gen_reg_rtx (SImode);
5856 emit_insn (gen_swapbsi2 (tmp0, operands[1]));
5857 emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
5858 emit_insn (gen_swapbsi2 (operands[0], tmp1));
5863 (define_insn "swapbsi2"
5864 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5865 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
5866 (const_int 4294901760))
5867 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5869 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5870 (const_int 255)))))]
5873 [(set_attr "type" "arith")])
5875 ;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying
5876 ;; partial byte swap expressions such as...
5877 ;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF).
5878 ;; ...which are currently not handled by the tree optimizers.
5879 ;; The combine pass will not initially try to combine the full expression,
5880 ;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8
5881 ;; pattern acts as an intermediate pattern that will eventually lead combine
5882 ;; to the swapbsi2 pattern above.
5883 ;; As a side effect this also improves code that does (x & 0xFF) << 8
5884 ;; or (x << 8) & 0xFF00.
5885 (define_insn_and_split "*swapbisi2_and_shl8"
5886 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5887 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5890 (match_operand:SI 2 "arith_reg_operand" "r")))]
5891 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
5893 "&& can_create_pseudo_p ()"
5896 rtx tmp0 = gen_reg_rtx (SImode);
5897 rtx tmp1 = gen_reg_rtx (SImode);
5899 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1])));
5900 emit_insn (gen_swapbsi2 (tmp1, tmp0));
5901 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2]));
5905 ;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another
5906 ;; intermediate pattern that will help the combine pass arriving at swapbsi2.
5907 (define_insn_and_split "*swapbhisi2"
5908 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5909 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5912 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))]
5913 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
5915 "&& can_create_pseudo_p ()"
5918 rtx tmp = gen_reg_rtx (SImode);
5920 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1])));
5921 emit_insn (gen_swapbsi2 (operands[0], tmp));
5925 ;; In some cases the swapbsi2 pattern might leave a sequence such as...
5929 ;; which can be simplified to...
5932 [(set (match_operand:SI 0 "arith_reg_dest" "")
5933 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
5934 (const_int 4294901760))
5935 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5937 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5939 (set (match_operand:SI 2 "arith_reg_dest" "")
5941 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
5943 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
5944 (const_int 4294901760))
5945 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5947 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5948 (const_int 255)))))])
5950 ;; -------------------------------------------------------------------------
5951 ;; Zero extension instructions
5952 ;; -------------------------------------------------------------------------
5954 (define_insn "zero_extendsidi2"
5955 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5956 (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))]
5958 "addz.l %1, r63, %0"
5959 [(set_attr "type" "arith_media")
5960 (set_attr "highpart" "extend")])
5962 (define_insn "zero_extendhidi2"
5963 [(set (match_operand:DI 0 "register_operand" "=r,r")
5964 (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
5969 [(set_attr "type" "*,load_media")
5970 (set (attr "highpart")
5971 (cond [(match_test "sh_contains_memref_p (insn)")
5972 (const_string "user")]
5973 (const_string "ignore")))])
5976 [(set (match_operand:DI 0 "register_operand" "")
5977 (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
5978 "TARGET_SHMEDIA && reload_completed"
5979 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
5980 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
5982 if (GET_CODE (operands[1]) == TRUNCATE)
5983 operands[1] = XEXP (operands[1], 0);
5986 ;; ??? when a truncated input to a zero_extend is reloaded, reload will
5987 ;; reload the entire truncate expression.
5988 (define_insn_and_split "*loaddi_trunc"
5989 [(set (match_operand 0 "any_register_operand" "=r")
5990 (truncate (match_operand:DI 1 "memory_operand" "m")))]
5991 "TARGET_SHMEDIA && reload_completed"
5993 "TARGET_SHMEDIA && reload_completed"
5994 [(set (match_dup 0) (match_dup 1))]
5996 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
5999 (define_insn "zero_extendqidi2"
6000 [(set (match_operand:DI 0 "register_operand" "=r,r")
6001 (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6006 [(set_attr "type" "arith_media,load_media")
6007 (set (attr "highpart")
6008 (cond [(match_test "sh_contains_memref_p (insn)")
6009 (const_string "user")]
6010 (const_string "ignore")))])
6012 (define_expand "zero_extend<mode>si2"
6013 [(set (match_operand:SI 0 "arith_reg_dest")
6014 (zero_extend:SI (match_operand:QIHI 1 "zero_extend_operand")))])
6016 (define_insn_and_split "*zero_extend<mode>si2_compact"
6017 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6018 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
6021 "&& can_create_pseudo_p ()"
6022 [(set (match_dup 0) (match_dup 2))]
6024 /* Sometimes combine fails to combine a T bit or negated T bit store to a
6025 reg with a following zero extension. In the split pass after combine,
6026 try to figure out how the extended reg was set. If it originated from
6027 the T bit we can replace the zero extension with a reg move, which will
6028 be eliminated. Notice that this also helps the *cbranch_t splitter when
6029 it tries to post-combine tests and conditional branches, as it does not
6030 check for zero extensions. */
6031 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
6032 if (operands[2] == NULL_RTX)
6035 [(set_attr "type" "arith")])
6037 (define_insn "*zero_extendhisi2_media"
6038 [(set (match_operand:SI 0 "register_operand" "=r,r")
6039 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6044 [(set_attr "type" "arith_media,load_media")
6045 (set (attr "highpart")
6046 (cond [(match_test "sh_contains_memref_p (insn)")
6047 (const_string "user")]
6048 (const_string "ignore")))])
6051 [(set (match_operand:SI 0 "register_operand" "")
6052 (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
6053 "TARGET_SHMEDIA && reload_completed"
6054 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
6055 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
6057 rtx op1 = operands[1];
6059 if (GET_CODE (op1) == TRUNCATE)
6060 op1 = XEXP (op1, 0);
6062 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6063 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6066 (define_insn "*zero_extendqisi2_media"
6067 [(set (match_operand:SI 0 "register_operand" "=r,r")
6068 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6073 [(set_attr "type" "arith_media,load_media")
6074 (set (attr "highpart")
6075 (cond [(match_test "sh_contains_memref_p (insn)")
6076 (const_string "user")]
6077 (const_string "ignore")))])
6079 (define_insn "zero_extendqihi2"
6080 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
6081 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
6084 [(set_attr "type" "arith")])
6086 ;; SH2A supports two zero extending load instructions: movu.b and movu.w.
6087 ;; They could also be used for simple memory addresses like @Rn by setting
6088 ;; the displacement value to zero. However, doing so too early results in
6089 ;; missed opportunities for other optimizations such as post-inc or index
6090 ;; addressing loads.
6091 ;; Although the 'zero_extend_movu_operand' predicate does not allow simple
6092 ;; register addresses (an address without a displacement, index, post-inc),
6093 ;; zero-displacement addresses might be generated during reload, wich are
6094 ;; simplified to simple register addresses in turn. Thus, we have to
6095 ;; provide the Sdd and Sra alternatives in the patterns.
6096 (define_insn "*zero_extend<mode>si2_disp_mem"
6097 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
6099 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
6103 movu.<bw> @(0,%t1),%0"
6104 [(set_attr "type" "load")
6105 (set_attr "length" "4")])
6107 ;; Convert the zero extending loads in sequences such as:
6108 ;; movu.b @(1,r5),r0 movu.w @(2,r5),r0
6109 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
6111 ;; back to sign extending loads like:
6112 ;; mov.b @(1,r5),r0 mov.w @(2,r5),r0
6113 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
6115 ;; if the extension type is irrelevant. The sign extending mov.{b|w} insn
6116 ;; is only 2 bytes in size if the displacement is {K04|K05}.
6117 ;; If the displacement is greater it doesn't matter, so we convert anyways.
6119 [(set (match_operand:SI 0 "arith_reg_dest" "")
6120 (zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
6121 (set (match_operand 2 "nonimmediate_operand" "")
6122 (match_operand 3 "arith_reg_operand" ""))]
6124 && REGNO (operands[0]) == REGNO (operands[3])
6125 && peep2_reg_dead_p (2, operands[0])
6126 && GET_MODE_SIZE (GET_MODE (operands[2]))
6127 <= GET_MODE_SIZE (GET_MODE (operands[1]))"
6128 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
6129 (set (match_dup 2) (match_dup 3))])
6131 ;; Fold sequences such as
6135 ;; movu.b @(0,r3),r7
6136 ;; This does not reduce the code size but the number of instructions is
6137 ;; halved, which results in faster code.
6139 [(set (match_operand:SI 0 "arith_reg_dest" "")
6140 (sign_extend:SI (match_operand 1 "simple_mem_operand" "")))
6141 (set (match_operand:SI 2 "arith_reg_dest" "")
6142 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
6144 && GET_MODE (operands[1]) == GET_MODE (operands[3])
6145 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode)
6146 && REGNO (operands[0]) == REGNO (operands[3])
6147 && (REGNO (operands[2]) == REGNO (operands[0])
6148 || peep2_reg_dead_p (2, operands[0]))"
6149 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))]
6152 = replace_equiv_address (operands[1],
6153 gen_rtx_PLUS (SImode, XEXP (operands[1], 0),
6157 ;; -------------------------------------------------------------------------
6158 ;; Sign extension instructions
6159 ;; -------------------------------------------------------------------------
6161 ;; ??? This should be a define expand.
6162 ;; ??? Or perhaps it should be dropped?
6164 ;; convert_move generates good code for SH[1-4].
6165 (define_insn "extendsidi2"
6166 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6167 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,?f")))]
6173 [(set_attr "type" "arith_media,load_media,fpconv_media")
6174 (set (attr "highpart")
6175 (cond [(match_test "sh_contains_memref_p (insn)")
6176 (const_string "user")]
6177 (const_string "extend")))])
6179 (define_insn "extendhidi2"
6180 [(set (match_operand:DI 0 "register_operand" "=r,r")
6181 (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6186 [(set_attr "type" "*,load_media")
6187 (set (attr "highpart")
6188 (cond [(match_test "sh_contains_memref_p (insn)")
6189 (const_string "user")]
6190 (const_string "ignore")))])
6193 [(set (match_operand:DI 0 "register_operand" "")
6194 (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
6195 "TARGET_SHMEDIA && reload_completed"
6196 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
6197 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
6199 if (GET_CODE (operands[1]) == TRUNCATE)
6200 operands[1] = XEXP (operands[1], 0);
6203 (define_insn "extendqidi2"
6204 [(set (match_operand:DI 0 "register_operand" "=r,r")
6205 (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6210 [(set_attr "type" "*,load_media")
6211 (set (attr "highpart")
6212 (cond [(match_test "sh_contains_memref_p (insn)")
6213 (const_string "user")]
6214 (const_string "ignore")))])
6217 [(set (match_operand:DI 0 "register_operand" "")
6218 (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
6219 "TARGET_SHMEDIA && reload_completed"
6220 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
6221 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
6223 if (GET_CODE (operands[1]) == TRUNCATE)
6224 operands[1] = XEXP (operands[1], 0);
6227 (define_expand "extend<mode>si2"
6228 [(set (match_operand:SI 0 "arith_reg_dest")
6229 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
6231 (define_insn "*extendhisi2_media"
6232 [(set (match_operand:SI 0 "register_operand" "=r,r")
6233 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6238 [(set_attr "type" "arith_media,load_media")
6239 (set (attr "highpart")
6240 (cond [(match_test "sh_contains_memref_p (insn)")
6241 (const_string "user")]
6242 (const_string "ignore")))])
6245 [(set (match_operand:SI 0 "register_operand" "")
6246 (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
6247 "TARGET_SHMEDIA && reload_completed"
6248 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
6249 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
6251 rtx op1 = operands[1];
6252 if (GET_CODE (op1) == TRUNCATE)
6253 op1 = XEXP (op1, 0);
6255 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6256 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6259 (define_insn_and_split "*extend<mode>si2_compact_reg"
6260 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6261 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
6264 "&& can_create_pseudo_p ()"
6265 [(set (match_dup 0) (match_dup 2))]
6267 /* Sometimes combine fails to combine a T bit or negated T bit store to a
6268 reg with a following sign extension. In the split pass after combine,
6269 try to figure the extended reg was set. If it originated from the T
6270 bit we can replace the sign extension with a reg move, which will be
6272 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
6273 if (operands[2] == NULL_RTX)
6276 [(set_attr "type" "arith")])
6278 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
6280 (define_insn "*extend<mode>si2_compact_mem_disp"
6281 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
6285 (match_operand:SI 1 "arith_reg_operand" "%r,r")
6286 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
6287 "TARGET_SH1 && ! TARGET_SH2A
6288 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
6290 mov.<bw> @(%O2,%1),%0
6292 [(set_attr "type" "load")])
6294 (define_insn "*extend<mode>si2_compact_mem_disp"
6295 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
6299 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
6300 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
6301 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
6303 mov.<bw> @(%O2,%1),%0
6305 mov.<bw> @(%O2,%1),%0"
6306 [(set_attr "type" "load")
6307 (set_attr "length" "2,2,4")])
6309 ;; The *_snd patterns will take care of other QImode/HImode addressing
6310 ;; modes than displacement addressing. They must be defined _after_ the
6311 ;; displacement addressing patterns. Otherwise the displacement addressing
6312 ;; patterns will not be picked.
6313 (define_insn "*extend<mode>si2_compact_snd"
6314 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6316 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
6319 [(set_attr "type" "load")])
6321 (define_insn "*extendqisi2_media"
6322 [(set (match_operand:SI 0 "register_operand" "=r,r")
6323 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6328 [(set_attr "type" "arith_media,load_media")
6329 (set (attr "highpart")
6330 (cond [(match_test "sh_contains_memref_p (insn)")
6331 (const_string "user")]
6332 (const_string "ignore")))])
6335 [(set (match_operand:SI 0 "register_operand" "")
6336 (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
6337 "TARGET_SHMEDIA && reload_completed"
6338 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
6339 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
6341 rtx op1 = operands[1];
6342 if (GET_CODE (op1) == TRUNCATE)
6343 op1 = XEXP (op1, 0);
6345 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6346 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6349 (define_expand "extendqihi2"
6350 [(set (match_operand:HI 0 "arith_reg_dest" "")
6351 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "")))]
6355 (define_insn "*extendqihi2_compact_reg"
6356 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
6357 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
6360 [(set_attr "type" "arith")])
6362 ;; It would seem useful to combine the truncXi patterns into the movXi
6363 ;; patterns, but unary operators are ignored when matching constraints,
6364 ;; so we need separate patterns.
6365 (define_insn "truncdisi2"
6366 [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f")
6367 (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))]
6376 [(set_attr "type" "arith_media,store_media,fstore_media,fload_media,
6377 fpconv_media,fmove_media")
6378 (set (attr "highpart")
6379 (cond [(match_test "sh_contains_memref_p (insn)")
6380 (const_string "user")]
6381 (const_string "extend")))])
6383 (define_insn "truncdihi2"
6384 [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
6385 (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
6388 static const char* alt[] =
6390 "shlli %1,48,%0" "\n"
6395 return alt[which_alternative];
6397 [(set_attr "type" "arith_media,store_media")
6398 (set_attr "length" "8,4")
6399 (set (attr "highpart")
6400 (cond [(match_test "sh_contains_memref_p (insn)")
6401 (const_string "user")]
6402 (const_string "extend")))])
6404 ; N.B. This should agree with LOAD_EXTEND_OP and movqi.
6405 ; Because we use zero extension, we can't provide signed QImode compares
6406 ; using a simple compare or conditional branch insn.
6407 (define_insn "truncdiqi2"
6408 [(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
6409 (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
6414 [(set_attr "type" "arith_media,store")
6415 (set (attr "highpart")
6416 (cond [(match_test "sh_contains_memref_p (insn)")
6417 (const_string "user")]
6418 (const_string "extend")))])
6420 ;; -------------------------------------------------------------------------
6421 ;; Move instructions
6422 ;; -------------------------------------------------------------------------
6424 ;; define push and pop so it is easy for sh.c
6425 ;; We can't use push and pop on SHcompact because the stack must always
6426 ;; be 8-byte aligned.
6427 (define_expand "push"
6428 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6429 (match_operand:SI 0 "register_operand" "r,l,x"))]
6430 "TARGET_SH1 && ! TARGET_SH5"
6433 (define_expand "pop"
6434 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
6435 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
6436 "TARGET_SH1 && ! TARGET_SH5"
6439 (define_expand "push_e"
6440 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
6441 (match_operand:SF 0 "" ""))
6442 (use (reg:PSI FPSCR_REG))
6443 (clobber (scratch:SI))])]
6444 "TARGET_SH1 && ! TARGET_SH5"
6447 (define_insn "push_fpul"
6448 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
6449 "TARGET_SH2E && ! TARGET_SH5"
6451 [(set_attr "type" "fstore")
6452 (set_attr "late_fp_use" "yes")
6453 (set_attr "hit_stack" "yes")])
6455 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
6457 (define_expand "push_4"
6458 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
6459 (match_operand:DF 0 "" ""))
6460 (use (reg:PSI FPSCR_REG))
6461 (clobber (scratch:SI))])]
6462 "TARGET_SH1 && ! TARGET_SH5"
6465 (define_expand "pop_e"
6466 [(parallel [(set (match_operand:SF 0 "" "")
6467 (mem:SF (post_inc:SI (reg:SI SP_REG))))
6468 (use (reg:PSI FPSCR_REG))
6469 (clobber (scratch:SI))])]
6470 "TARGET_SH1 && ! TARGET_SH5"
6473 (define_insn "pop_fpul"
6474 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
6475 "TARGET_SH2E && ! TARGET_SH5"
6477 [(set_attr "type" "load")
6478 (set_attr "hit_stack" "yes")])
6480 (define_expand "pop_4"
6481 [(parallel [(set (match_operand:DF 0 "" "")
6482 (mem:DF (post_inc:SI (reg:SI SP_REG))))
6483 (use (reg:PSI FPSCR_REG))
6484 (clobber (scratch:SI))])]
6485 "TARGET_SH1 && ! TARGET_SH5"
6488 (define_expand "push_fpscr"
6492 rtx insn = emit_insn (gen_fpu_switch (gen_frame_mem (PSImode,
6493 gen_rtx_PRE_DEC (Pmode,
6494 stack_pointer_rtx)),
6496 add_reg_note (insn, REG_INC, stack_pointer_rtx);
6500 (define_expand "pop_fpscr"
6504 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
6505 gen_frame_mem (PSImode,
6506 gen_rtx_POST_INC (Pmode,
6507 stack_pointer_rtx))));
6508 add_reg_note (insn, REG_INC, stack_pointer_rtx);
6512 ;; The clrt and sett patterns can happen as the result of optimization and
6514 ;; Comparisons might get simplified to a move of zero or 1 into the T reg.
6515 ;; In this case they might not disappear completely, because the T reg is
6516 ;; a fixed hard reg.
6517 ;; When DImode operations that use the T reg as carry/borrow are split into
6518 ;; individual SImode operations, the T reg is usually cleared before the
6519 ;; first SImode insn.
6521 [(set (reg:SI T_REG) (const_int 0))]
6524 [(set_attr "type" "mt_group")])
6527 [(set (reg:SI T_REG) (const_int 1))]
6530 [(set_attr "type" "mt_group")])
6532 ;; Use the combine pass to transform sequences such as
6536 ;; mov.l @(r0,r4),r0
6542 ;; See also PR 39423.
6543 ;; Notice that these patterns have a T_REG clobber, because the shift
6544 ;; sequence that will be split out might clobber the T_REG. Ideally, the
6545 ;; clobber would be added conditionally, depending on the result of
6546 ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
6547 ;; through the ashlsi3 expander in order to get the right shift insn --
6548 ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
6549 ;; FIXME: Combine never tries this kind of patterns for DImode.
6550 (define_insn_and_split "*movsi_index_disp_load"
6551 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6552 (match_operand:SI 1 "mem_index_disp_operand" "m"))
6553 (clobber (reg:SI T_REG))]
6556 "&& can_create_pseudo_p ()"
6557 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6558 (set (match_dup 0) (match_dup 7))]
6560 rtx mem = operands[1];
6561 rtx plus0_rtx = XEXP (mem, 0);
6562 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6563 rtx mult_rtx = XEXP (plus1_rtx, 0);
6565 operands[1] = XEXP (mult_rtx, 0);
6566 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6567 operands[3] = XEXP (plus1_rtx, 1);
6568 operands[4] = XEXP (plus0_rtx, 1);
6569 operands[5] = gen_reg_rtx (SImode);
6570 operands[6] = gen_reg_rtx (SImode);
6572 replace_equiv_address (mem,
6573 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6575 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
6578 (define_insn_and_split "*movhi_index_disp_load"
6579 [(set (match_operand:SI 0 "arith_reg_dest")
6580 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
6581 (clobber (reg:SI T_REG))]
6584 "&& can_create_pseudo_p ()"
6587 rtx mem = operands[1];
6588 rtx plus0_rtx = XEXP (mem, 0);
6589 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6590 rtx mult_rtx = XEXP (plus1_rtx, 0);
6592 rtx op_1 = XEXP (mult_rtx, 0);
6593 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6594 rtx op_3 = XEXP (plus1_rtx, 1);
6595 rtx op_4 = XEXP (plus0_rtx, 1);
6596 rtx op_5 = gen_reg_rtx (SImode);
6597 rtx op_6 = gen_reg_rtx (SImode);
6598 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
6600 emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
6601 emit_insn (gen_addsi3 (op_6, op_5, op_3));
6603 if (<CODE> == SIGN_EXTEND)
6605 emit_insn (gen_extendhisi2 (operands[0], op_7));
6608 else if (<CODE> == ZERO_EXTEND)
6610 /* On SH2A the movu.w insn can be used for zero extending loads. */
6612 emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
6615 emit_insn (gen_extendhisi2 (operands[0], op_7));
6616 emit_insn (gen_zero_extendhisi2 (operands[0],
6617 gen_lowpart (HImode, operands[0])));
6625 (define_insn_and_split "*mov<mode>_index_disp_store"
6626 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
6627 (match_operand:HISI 1 "arith_reg_operand" "r"))
6628 (clobber (reg:SI T_REG))]
6631 "&& can_create_pseudo_p ()"
6632 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6633 (set (match_dup 7) (match_dup 1))]
6635 rtx mem = operands[0];
6636 rtx plus0_rtx = XEXP (mem, 0);
6637 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6638 rtx mult_rtx = XEXP (plus1_rtx, 0);
6640 operands[0] = XEXP (mult_rtx, 0);
6641 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6642 operands[3] = XEXP (plus1_rtx, 1);
6643 operands[4] = XEXP (plus0_rtx, 1);
6644 operands[5] = gen_reg_rtx (SImode);
6645 operands[6] = gen_reg_rtx (SImode);
6647 replace_equiv_address (mem,
6648 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6650 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
6653 ;; t/r must come after r/r, lest reload will try to reload stuff like
6654 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
6655 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
6656 (define_insn "movsi_i"
6657 [(set (match_operand:SI 0 "general_movdst_operand"
6658 "=r,r,r,r,r,r,m,<,<,x,l,x,l,r")
6659 (match_operand:SI 1 "general_movsrc_operand"
6660 "Q,r,I08,mr,x,l,r,x,l,r,r,>,>,i"))]
6664 && (register_operand (operands[0], SImode)
6665 || register_operand (operands[1], SImode))"
6681 [(set_attr "type" "pcload_si,move,movi8,load_si,mac_gp,prget,store,mac_mem,
6682 pstore,gp_mac,prset,mem_mac,pload,pcload_si")
6683 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
6685 ;; t/r must come after r/r, lest reload will try to reload stuff like
6686 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
6687 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
6688 ;; will require a reload.
6689 ;; ??? We can't include f/f because we need the proper FPSCR setting when
6690 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
6691 (define_insn "movsi_ie"
6692 [(set (match_operand:SI 0 "general_movdst_operand"
6693 "=r,r,r,r,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
6694 (match_operand:SI 1 "general_movsrc_operand"
6695 "Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
6696 "(TARGET_SH2E || TARGET_SH2A)
6697 && (register_operand (operands[0], SImode)
6698 || register_operand (operands[1], SImode))"
6723 ! move optimized away"
6724 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
6725 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
6726 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
6727 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
6728 (set_attr_alternative "length"
6735 (match_test "TARGET_SH2A")
6736 (const_int 4) (const_int 2))
6740 (match_test "TARGET_SH2A")
6741 (const_int 4) (const_int 2))
6758 (define_insn "movsi_i_lowpart"
6759 [(set (strict_low_part
6760 (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
6761 (match_operand:SI 1 "general_movsrc_operand" "Q,r,I08,mr,x,l,r,i"))]
6763 && (register_operand (operands[0], SImode)
6764 || register_operand (operands[1], SImode))"
6774 [(set_attr "type" "pcload,move,arith,load,mac_gp,prget,store,pcload")])
6776 (define_insn_and_split "load_ra"
6777 [(set (match_operand:SI 0 "general_movdst_operand" "")
6778 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
6781 "&& ! currently_expanding_to_rtl"
6782 [(set (match_dup 0) (match_dup 1))]
6784 if (TARGET_SHCOMPACT && crtl->saves_all_registers)
6785 operands[1] = gen_frame_mem (SImode, return_address_pointer_rtx);
6788 ;; The '?'s in the following constraints may not reflect the time taken
6789 ;; to perform the move. They are there to discourage the use of floating-
6790 ;; point registers for storing integer values.
6791 (define_insn "*movsi_media"
6792 [(set (match_operand:SI 0 "general_movdst_operand"
6793 "=r,r,r,r,m,f?,m,f?,r,f?,*b,r,b")
6794 (match_operand:SI 1 "general_movsrc_operand"
6795 "r,I16Css,nCpg,m,rZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
6797 && (register_operand (operands[0], SImode)
6798 || sh_register_operand (operands[1], SImode)
6799 || GET_CODE (operands[1]) == TRUNCATE)"
6814 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
6815 fload_media,fstore_media,fload_media,fpconv_media,
6816 fmove_media,ptabs_media,gettr_media,pt_media")
6817 (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")
6818 (set (attr "highpart")
6819 (cond [(match_test "sh_contains_memref_p (insn)")
6820 (const_string "user")]
6821 (const_string "ignore")))])
6823 (define_insn "*movsi_media_nofpu"
6824 [(set (match_operand:SI 0 "general_movdst_operand"
6825 "=r,r,r,r,m,*b,r,*b")
6826 (match_operand:SI 1 "general_movsrc_operand"
6827 "r,I16Css,nCpg,m,rZ,r,*b,Csy"))]
6829 && (register_operand (operands[0], SImode)
6830 || sh_register_operand (operands[1], SImode)
6831 || GET_CODE (operands[1]) == TRUNCATE)"
6841 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
6842 ptabs_media,gettr_media,pt_media")
6843 (set_attr "length" "4,4,8,4,4,4,4,12")
6844 (set (attr "highpart")
6845 (cond [(match_test "sh_contains_memref_p (insn)")
6846 (const_string "user")]
6847 (const_string "ignore")))])
6849 (define_expand "movsi_const"
6850 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
6851 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
6852 (const_int 16)] UNSPEC_EXTRACT_S16)))
6854 (ior:SI (ashift:SI (match_dup 0) (const_int 16))
6855 (const:SI (unspec:SI [(match_dup 1)
6856 (const_int 0)] UNSPEC_EXTRACT_U16))))]
6857 "TARGET_SHMEDIA && reload_completed
6858 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
6860 if (GET_CODE (operands[1]) == LABEL_REF
6861 && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
6862 LABEL_NUSES (XEXP (operands[1], 0)) += 2;
6863 else if (GOTOFF_P (operands[1]))
6865 rtx unspec = XEXP (operands[1], 0);
6867 if (! UNSPEC_GOTOFF_P (unspec))
6869 unspec = XEXP (unspec, 0);
6870 if (! UNSPEC_GOTOFF_P (unspec))
6873 if (GET_CODE (XVECEXP (unspec , 0, 0)) == LABEL_REF
6874 && (GET_CODE (XEXP (XVECEXP (unspec, 0, 0), 0)) == CODE_LABEL))
6875 LABEL_NUSES (XEXP (XVECEXP (unspec, 0, 0), 0)) += 2;
6879 (define_expand "movsi_const_16bit"
6880 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
6881 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
6882 (const_int 0)] UNSPEC_EXTRACT_S16)))]
6883 "TARGET_SHMEDIA && flag_pic && reload_completed
6884 && GET_CODE (operands[1]) == SYMBOL_REF"
6888 [(set (match_operand:SI 0 "arith_reg_dest" "")
6889 (match_operand:SI 1 "immediate_operand" ""))]
6890 "TARGET_SHMEDIA && reload_completed
6891 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
6894 rtx insn = emit_insn (gen_movsi_const (operands[0], operands[1]));
6896 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
6902 [(set (match_operand:SI 0 "register_operand" "")
6903 (match_operand:SI 1 "immediate_operand" ""))]
6904 "TARGET_SHMEDIA && reload_completed
6905 && ((CONST_INT_P (operands[1])
6906 && ! satisfies_constraint_I16 (operands[1]))
6907 || GET_CODE (operands[1]) == CONST_DOUBLE)"
6908 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
6910 (define_expand "movsi"
6911 [(set (match_operand:SI 0 "general_movdst_operand" "")
6912 (match_operand:SI 1 "general_movsrc_operand" ""))]
6915 prepare_move_operands (operands, SImode);
6918 (define_expand "ic_invalidate_line"
6919 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
6920 (match_dup 1)] UNSPEC_ICACHE)
6921 (clobber (scratch:SI))])]
6922 "TARGET_HARD_SH4 || TARGET_SH5"
6926 emit_insn (gen_ic_invalidate_line_media (operands[0]));
6929 else if (TARGET_SHCOMPACT)
6931 operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC);
6932 operands[1] = force_reg (Pmode, operands[1]);
6933 emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
6936 else if (TARGET_SH4A_ARCH || TARGET_SH4_300)
6938 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
6941 operands[0] = force_reg (Pmode, operands[0]);
6942 operands[1] = force_reg (Pmode, GEN_INT (trunc_int_for_mode (0xf0000008,
6946 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
6947 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
6948 ;; the requirement *1*00 for associative address writes. The alignment of
6949 ;; %0 implies that its least significant bit is cleared,
6950 ;; thus we clear the V bit of a matching entry if there is one.
6951 (define_insn "ic_invalidate_line_i"
6952 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
6953 (match_operand:SI 1 "register_operand" "r")]
6955 (clobber (match_scratch:SI 2 "=&r"))]
6958 return "ocbwb @%0" "\n"
6959 " extu.w %0,%2" "\n"
6963 [(set_attr "length" "8")
6964 (set_attr "type" "cwb")])
6966 (define_insn "ic_invalidate_line_sh4a"
6967 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
6969 "TARGET_SH4A_ARCH || TARGET_SH4_300"
6971 return "ocbwb @%0" "\n"
6975 [(set_attr "length" "16") ;; FIXME: Why 16 and not 6? Looks like typo.
6976 (set_attr "type" "cwb")])
6978 ;; ??? could make arg 0 an offsettable memory operand to allow to save
6979 ;; an add in the code that calculates the address.
6980 (define_insn "ic_invalidate_line_media"
6981 [(unspec_volatile [(match_operand 0 "any_register_operand" "r")]
6985 return "ocbwb %0,0" "\n"
6990 [(set_attr "length" "16")
6991 (set_attr "type" "invalidate_line_media")])
6993 (define_insn "ic_invalidate_line_compact"
6994 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
6995 (match_operand:SI 1 "register_operand" "r")]
6997 (clobber (reg:SI PR_REG))]
7000 [(set_attr "type" "sfunc")
7001 (set_attr "needs_delay_slot" "yes")])
7003 (define_expand "initialize_trampoline"
7004 [(match_operand:SI 0 "" "")
7005 (match_operand:SI 1 "" "")
7006 (match_operand:SI 2 "" "")]
7011 tramp = force_reg (Pmode, operands[0]);
7012 sfun = force_reg (Pmode, function_symbol (NULL, "__init_trampoline",
7014 emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
7015 emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
7017 emit_insn (gen_initialize_trampoline_compact (tramp, sfun));
7021 (define_insn "initialize_trampoline_compact"
7022 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
7023 (match_operand:SI 1 "register_operand" "r")
7024 (reg:SI R2_REG) (reg:SI R3_REG)]
7027 (clobber (reg:SI PR_REG))]
7030 [(set_attr "type" "sfunc")
7031 (set_attr "needs_delay_slot" "yes")])
7033 (define_expand "mov<mode>"
7034 [(set (match_operand:QIHI 0 "general_movdst_operand")
7035 (match_operand:QIHI 1 "general_movsrc_operand"))]
7038 if (can_create_pseudo_p () && CONST_INT_P (operands[1])
7039 && REG_P (operands[0]) && REGNO (operands[0]) != R0_REG)
7041 rtx reg = gen_reg_rtx(SImode);
7042 emit_move_insn (reg, operands[1]);
7043 operands[1] = gen_lowpart (<MODE>mode, reg);
7046 prepare_move_operands (operands, <MODE>mode);
7049 ;; Specifying the displacement addressing load / store patterns separately
7050 ;; before the generic movqi / movhi pattern allows controlling the order
7051 ;; in which load / store insns are selected in a more fine grained way.
7052 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
7053 ;; "enabled" attribute as it is done in other targets.
7054 (define_insn "*mov<mode>_store_mem_disp04"
7056 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
7057 (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
7058 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
7059 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
7061 mov.<bw> %2,@(%O1,%0)
7063 [(set_attr "type" "store")])
7065 (define_insn "*mov<mode>_store_mem_disp12"
7067 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
7068 (match_operand:SI 1 "const_int_operand" "<disp12>")))
7069 (match_operand:QIHI 2 "arith_reg_operand" "r"))]
7070 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
7071 "mov.<bw> %2,@(%O1,%0)"
7072 [(set_attr "type" "store")
7073 (set_attr "length" "4")])
7075 (define_insn "*mov<mode>_load_mem_disp04"
7076 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
7078 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
7079 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
7080 "TARGET_SH1 && ! TARGET_SH2A
7081 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
7083 mov.<bw> @(%O2,%1),%0
7085 [(set_attr "type" "load")])
7087 (define_insn "*mov<mode>_load_mem_disp12"
7088 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
7091 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
7092 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
7093 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
7095 mov.<bw> @(%O2,%1),%0
7097 mov.<bw> @(%O2,%1),%0"
7098 [(set_attr "type" "load")
7099 (set_attr "length" "2,2,4")])
7101 ;; The order of the constraint alternatives is important here.
7102 ;; Q/r has to come first, otherwise PC relative loads might wrongly get
7103 ;; placed into delay slots. Since there is no QImode PC relative load, the
7104 ;; Q constraint and general_movsrc_operand will reject it for QImode.
7105 ;; The Snd alternatives should come before Sdd in order to avoid a preference
7106 ;; of using r0 als the register operand for addressing modes other than
7107 ;; displacement addressing.
7108 ;; The Sdd alternatives allow only r0 as register operand, even though on
7109 ;; SH2A any register could be allowed by switching to a 32 bit insn.
7110 ;; Generally sticking to the r0 is preferrable, since it generates smaller
7111 ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
7112 (define_insn "*mov<mode>"
7113 [(set (match_operand:QIHI 0 "general_movdst_operand"
7114 "=r,r,r,Snd,r, Sdd,z, r,l")
7115 (match_operand:QIHI 1 "general_movsrc_operand"
7116 "Q,r,i,r, Snd,z, Sdd,l,r"))]
7118 && (arith_reg_operand (operands[0], <MODE>mode)
7119 || arith_reg_operand (operands[1], <MODE>mode))"
7130 [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset")
7131 (set (attr "length")
7132 (cond [(and (match_operand 0 "displacement_mem_operand")
7133 (not (match_operand 0 "short_displacement_mem_operand")))
7135 (and (match_operand 1 "displacement_mem_operand")
7136 (not (match_operand 1 "short_displacement_mem_operand")))
7140 (define_insn "*movqi_media"
7141 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
7142 (match_operand:QI 1 "general_movsrc_operand" "r,I16Css,m,rZ"))]
7144 && (arith_reg_operand (operands[0], QImode)
7145 || extend_reg_or_0_operand (operands[1], QImode))"
7151 [(set_attr "type" "arith_media,arith_media,load_media,store_media")
7152 (set (attr "highpart")
7153 (cond [(match_test "sh_contains_memref_p (insn)")
7154 (const_string "user")]
7155 (const_string "ignore")))])
7157 (define_expand "reload_inqi"
7158 [(set (match_operand:SI 2 "" "=&r")
7159 (match_operand:QI 1 "inqhi_operand" ""))
7160 (set (match_operand:QI 0 "arith_reg_operand" "=r")
7161 (truncate:QI (match_dup 3)))]
7164 rtx inner = XEXP (operands[1], 0);
7165 int regno = REGNO (inner);
7167 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7168 operands[1] = gen_rtx_REG (SImode, regno);
7169 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7172 (define_insn "*movhi_media"
7173 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
7174 (match_operand:HI 1 "general_movsrc_operand" "r,I16Css,n,m,rZ"))]
7176 && (arith_reg_operand (operands[0], HImode)
7177 || arith_reg_or_0_operand (operands[1], HImode))"
7184 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
7185 (set (attr "highpart")
7186 (cond [(match_test "sh_contains_memref_p (insn)")
7187 (const_string "user")]
7188 (const_string "ignore")))])
7191 [(set (match_operand:HI 0 "register_operand" "")
7192 (match_operand:HI 1 "immediate_operand" ""))]
7193 "TARGET_SHMEDIA && reload_completed
7194 && ! satisfies_constraint_I16 (operands[1])"
7195 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
7197 (define_expand "reload_inhi"
7198 [(set (match_operand:SI 2 "" "=&r")
7199 (match_operand:HI 1 "inqhi_operand" ""))
7200 (set (match_operand:HI 0 "arith_reg_operand" "=r")
7201 (truncate:HI (match_dup 3)))]
7204 rtx inner = XEXP (operands[1], 0);
7205 int regno = REGNO (inner);
7207 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7208 operands[1] = gen_rtx_REG (SImode, regno);
7209 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7212 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
7213 ;; compiled with -m2 -ml -O3 -funroll-loops
7214 (define_insn "*movdi_i"
7215 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
7216 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I08,i,x,r"))]
7218 && (arith_reg_operand (operands[0], DImode)
7219 || arith_reg_operand (operands[1], DImode))"
7221 return output_movedouble (insn, operands, DImode);
7223 [(set_attr "length" "4")
7224 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
7226 ;; If the output is a register and the input is memory or a register, we have
7227 ;; to be careful and see which word needs to be loaded first.
7229 [(set (match_operand:DI 0 "general_movdst_operand" "")
7230 (match_operand:DI 1 "general_movsrc_operand" ""))]
7231 "TARGET_SH1 && reload_completed"
7232 [(set (match_dup 2) (match_dup 3))
7233 (set (match_dup 4) (match_dup 5))]
7237 if ((MEM_P (operands[0])
7238 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
7239 || (MEM_P (operands[1])
7240 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
7243 switch (GET_CODE (operands[0]))
7246 regno = REGNO (operands[0]);
7249 regno = subreg_regno (operands[0]);
7259 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
7261 operands[2] = operand_subword (operands[0], 0, 0, DImode);
7262 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7263 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7264 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7268 operands[2] = operand_subword (operands[0], 1, 0, DImode);
7269 operands[3] = operand_subword (operands[1], 1, 0, DImode);
7270 operands[4] = operand_subword (operands[0], 0, 0, DImode);
7271 operands[5] = operand_subword (operands[1], 0, 0, DImode);
7274 if (operands[2] == 0 || operands[3] == 0
7275 || operands[4] == 0 || operands[5] == 0)
7279 ;; The '?'s in the following constraints may not reflect the time taken
7280 ;; to perform the move. They are there to discourage the use of floating-
7281 ;; point registers for storing integer values.
7282 (define_insn "*movdi_media"
7283 [(set (match_operand:DI 0 "general_movdst_operand"
7284 "=r,r,r,rl,m,f?,m,f?,r,f?,*b,r,*b")
7285 (match_operand:DI 1 "general_movsrc_operand"
7286 "r,I16Css,nCpgF,m,rlZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
7288 && (register_operand (operands[0], DImode)
7289 || sh_register_operand (operands[1], DImode))"
7304 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7305 fload_media,fstore_media,fload_media,dfpconv_media,
7306 fmove_media,ptabs_media,gettr_media,pt_media")
7307 (set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")])
7309 (define_insn "*movdi_media_nofpu"
7310 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,*b");
7311 (match_operand:DI 1 "general_movsrc_operand" "r,I16Css,nCpgF,m,rlZ,r,*b,Csy"))]
7313 && (register_operand (operands[0], DImode)
7314 || sh_register_operand (operands[1], DImode))"
7324 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7325 ptabs_media,gettr_media,pt_media")
7326 (set_attr "length" "4,4,16,4,4,4,4,*")])
7328 (define_insn "*movdi_media_I16"
7329 [(set (match_operand:DI 0 "ext_dest_operand" "=r")
7330 (match_operand:DI 1 "const_int_operand" "I16"))]
7331 "TARGET_SHMEDIA && reload_completed"
7333 [(set_attr "type" "arith_media")
7334 (set_attr "length" "4")])
7337 [(set (match_operand:DI 0 "arith_reg_dest" "")
7338 (match_operand:DI 1 "immediate_operand" ""))]
7339 "TARGET_SHMEDIA && reload_completed
7340 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7341 [(set (match_dup 0) (match_dup 1))]
7345 if (TARGET_SHMEDIA64)
7346 insn = emit_insn (gen_movdi_const (operands[0], operands[1]));
7348 insn = emit_insn (gen_movdi_const_32bit (operands[0], operands[1]));
7350 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
7355 (define_expand "movdi_const"
7356 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7357 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7358 (const_int 48)] UNSPEC_EXTRACT_S16)))
7360 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7361 (const:DI (unspec:DI [(match_dup 1)
7362 (const_int 32)] UNSPEC_EXTRACT_U16))))
7364 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7365 (const:DI (unspec:DI [(match_dup 1)
7366 (const_int 16)] UNSPEC_EXTRACT_U16))))
7368 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7369 (const:DI (unspec:DI [(match_dup 1)
7370 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7371 "TARGET_SHMEDIA64 && reload_completed
7372 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7374 sh_mark_label (operands[1], 4);
7377 (define_expand "movdi_const_32bit"
7378 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7379 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7380 (const_int 16)] UNSPEC_EXTRACT_S16)))
7382 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7383 (const:DI (unspec:DI [(match_dup 1)
7384 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7385 "TARGET_SHMEDIA32 && reload_completed
7386 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7388 sh_mark_label (operands[1], 2);
7391 (define_expand "movdi_const_16bit"
7392 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7393 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7394 (const_int 0)] UNSPEC_EXTRACT_S16)))]
7395 "TARGET_SHMEDIA && flag_pic && reload_completed
7396 && GET_CODE (operands[1]) == SYMBOL_REF"
7400 [(set (match_operand:DI 0 "ext_dest_operand" "")
7401 (match_operand:DI 1 "immediate_operand" ""))]
7402 "TARGET_SHMEDIA && reload_completed
7403 && CONST_INT_P (operands[1])
7404 && ! satisfies_constraint_I16 (operands[1])"
7405 [(set (match_dup 0) (match_dup 2))
7408 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
7409 unsigned HOST_WIDE_INT low = val;
7410 unsigned HOST_WIDE_INT high = val;
7411 unsigned HOST_WIDE_INT sign;
7412 unsigned HOST_WIDE_INT val2 = val ^ (val-1);
7414 /* Zero-extend the 16 least-significant bits. */
7417 /* Arithmetic shift right the word by 16 bits. */
7419 if (GET_CODE (operands[0]) == SUBREG
7420 && GET_MODE (SUBREG_REG (operands[0])) == SImode)
7429 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7435 /* If we can't generate the constant with a two-insn movi / shori
7436 sequence, try some other strategies. */
7437 if (! CONST_OK_FOR_I16 (high))
7439 /* Try constant load / left shift. We know VAL != 0. */
7440 val2 = val ^ (val-1);
7443 int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
7445 if (CONST_OK_FOR_I16 (val >> trailing_zeroes)
7446 || (! CONST_OK_FOR_I16 (high >> 16)
7447 && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16))))
7449 val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
7450 operands[1] = gen_ashldi3_media (operands[0], operands[0],
7451 GEN_INT (trailing_zeroes));
7455 /* Try constant load / right shift. */
7456 val2 = (val >> 15) + 1;
7457 if (val2 == (val2 & -val2))
7459 int shift = 49 - exact_log2 (val2);
7461 val2 = trunc_int_for_mode (val << shift, DImode);
7462 if (CONST_OK_FOR_I16 (val2))
7464 operands[1] = gen_lshrdi3_media (operands[0], operands[0],
7470 val2 = val & 0xffff;
7471 if ((val >> 16 & 0xffff) == val2
7472 && (val >> 32 & 0xffff) == val2
7473 && (val >> 48 & 0xffff) == val2)
7475 val2 = (HOST_WIDE_INT) val >> 48;
7476 operands[1] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
7477 operands[1] = gen_mperm_w0 (operands[1], operands[1]);
7480 /* Try movi / mshflo.l */
7481 val2 = (HOST_WIDE_INT) val >> 32;
7482 if (val2 == ((unsigned HOST_WIDE_INT)
7483 trunc_int_for_mode (val, SImode)))
7485 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7489 /* Try movi / mshflo.l w/ r63. */
7490 val2 = val + ((HOST_WIDE_INT) -1 << 32);
7491 if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
7493 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7499 operands[1] = gen_shori_media (operands[0], operands[0], GEN_INT (low));
7502 operands[2] = GEN_INT (val2);
7506 [(set (match_operand:DI 0 "ext_dest_operand" "")
7507 (match_operand:DI 1 "immediate_operand" ""))]
7508 "TARGET_SHMEDIA && reload_completed
7509 && GET_CODE (operands[1]) == CONST_DOUBLE"
7510 [(set (match_dup 0) (match_dup 2))
7512 (ior:DI (ashift:DI (match_dup 0) (const_int 16)) (match_dup 1)))]
7514 unsigned HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
7515 unsigned HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
7516 unsigned HOST_WIDE_INT val = low;
7517 unsigned HOST_WIDE_INT sign;
7519 /* Zero-extend the 16 least-significant bits. */
7521 operands[1] = GEN_INT (val);
7523 /* Arithmetic shift right the double-word by 16 bits. */
7525 low |= (high & 0xffff) << (HOST_BITS_PER_WIDE_INT - 16);
7528 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7532 /* This will only be true if high is a sign-extension of low, i.e.,
7533 it must be either 0 or (unsigned)-1, and be zero iff the
7534 most-significant bit of low is set. */
7535 if (high + (low >> (HOST_BITS_PER_WIDE_INT - 1)) == 0)
7536 operands[2] = GEN_INT (low);
7538 operands[2] = immed_double_const (low, high, DImode);
7541 (define_insn "shori_media"
7542 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
7543 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0,0")
7545 (match_operand:DI 2 "immediate_operand" "K16Csu,nF")))]
7546 "TARGET_SHMEDIA && (reload_completed || arith_reg_dest (operands[0], DImode))"
7550 [(set_attr "type" "arith_media,*")])
7552 (define_insn "*shori_media_si"
7553 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
7554 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
7556 (match_operand:SI 2 "immediate_operand" "K16Csu")))]
7560 (define_expand "movdi"
7561 [(set (match_operand:DI 0 "general_movdst_operand" "")
7562 (match_operand:DI 1 "general_movsrc_operand" ""))]
7565 prepare_move_operands (operands, DImode);
7568 (define_insn "movdf_media"
7569 [(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
7570 (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
7572 && (register_operand (operands[0], DFmode)
7573 || sh_register_operand (operands[1], DFmode))"
7584 [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,
7585 fload_media,fstore_media,load_media,store_media")])
7587 (define_insn "movdf_media_nofpu"
7588 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7589 (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))]
7591 && (register_operand (operands[0], DFmode)
7592 || sh_register_operand (operands[1], DFmode))"
7598 [(set_attr "type" "arith_media,*,load_media,store_media")])
7601 [(set (match_operand:DF 0 "arith_reg_dest" "")
7602 (match_operand:DF 1 "immediate_operand" ""))]
7603 "TARGET_SHMEDIA && reload_completed"
7604 [(set (match_dup 3) (match_dup 2))]
7606 int endian = WORDS_BIG_ENDIAN ? 1 : 0;
7608 REAL_VALUE_TYPE value;
7610 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
7611 REAL_VALUE_TO_TARGET_DOUBLE (value, values);
7613 if (HOST_BITS_PER_WIDE_INT >= 64)
7614 operands[2] = immed_double_const ((unsigned long) values[endian]
7615 | ((HOST_WIDE_INT) values[1 - endian]
7619 gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
7620 operands[2] = immed_double_const (values[endian], values[1 - endian],
7624 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
7627 ;; FIXME: This should be a define_insn_and_split.
7628 (define_insn "movdf_k"
7629 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7630 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
7632 && (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed
7633 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
7634 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
7635 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
7636 && (arith_reg_operand (operands[0], DFmode)
7637 || arith_reg_operand (operands[1], DFmode))"
7639 return output_movedouble (insn, operands, DFmode);
7641 [(set_attr "length" "4")
7642 (set_attr "type" "move,pcload,load,store")])
7644 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
7645 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
7646 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
7647 ;; the d/m/c/X alternative, which is split later into single-precision
7648 ;; instructions. And when not optimizing, no splits are done before fixing
7649 ;; up pcloads, so we need usable length information for that.
7650 (define_insn "movdf_i4"
7651 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
7652 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
7653 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
7654 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
7655 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7656 && (arith_reg_operand (operands[0], DFmode)
7657 || arith_reg_operand (operands[1], DFmode))"
7659 switch (which_alternative)
7663 return "fmov %1,%0";
7664 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
7665 return "fmov %R1,%R0" "\n"
7668 return "fmov %S1,%S0" "\n"
7672 return "fmov.d %1,%0";
7677 [(set_attr_alternative "length"
7678 [(if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
7680 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7681 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7682 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7684 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
7685 ;; We can't use 4-byte push/pop on SHcompact, so we have to
7686 ;; increment or decrement r15 explicitly.
7688 (match_test "TARGET_SHCOMPACT")
7689 (const_int 10) (const_int 8))
7691 (match_test "TARGET_SHCOMPACT")
7692 (const_int 10) (const_int 8))])
7693 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,fload")
7694 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
7695 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
7696 (const_string "double")
7697 (const_string "none")))])
7699 ;; Moving DFmode between fp/general registers through memory
7700 ;; (the top of the stack) is faster than moving through fpul even for
7701 ;; little endian. Because the type of an instruction is important for its
7702 ;; scheduling, it is beneficial to split these operations, rather than
7703 ;; emitting them in one single chunk, even if this will expose a stack
7704 ;; use that will prevent scheduling of other stack accesses beyond this
7707 [(set (match_operand:DF 0 "register_operand" "")
7708 (match_operand:DF 1 "register_operand" ""))
7709 (use (match_operand:PSI 2 "fpscr_operand" ""))
7710 (clobber (match_scratch:SI 3 "=X"))]
7711 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed
7712 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
7717 if (TARGET_SH5 && true_regnum (operands[1]) < 16)
7719 emit_move_insn (stack_pointer_rtx,
7720 plus_constant (Pmode, stack_pointer_rtx, -8));
7721 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
7724 tos = gen_tmp_stack_mem (DFmode,
7725 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
7726 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
7727 if (! (TARGET_SH5 && true_regnum (operands[1]) < 16))
7728 add_reg_note (insn, REG_INC, stack_pointer_rtx);
7729 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
7730 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
7732 tos = gen_tmp_stack_mem (DFmode,
7733 gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
7734 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
7735 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
7736 emit_move_insn (stack_pointer_rtx,
7737 plus_constant (Pmode, stack_pointer_rtx, 8));
7739 add_reg_note (insn, REG_INC, stack_pointer_rtx);
7743 ;; local-alloc sometimes allocates scratch registers even when not required,
7744 ;; so we must be prepared to handle these.
7746 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
7748 [(set (match_operand:DF 0 "general_movdst_operand" "")
7749 (match_operand:DF 1 "general_movsrc_operand" ""))
7750 (use (match_operand:PSI 2 "fpscr_operand" ""))
7751 (clobber (match_scratch:SI 3 ""))]
7752 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7754 && true_regnum (operands[0]) < 16
7755 && true_regnum (operands[1]) < 16"
7756 [(set (match_dup 0) (match_dup 1))]
7758 /* If this was a reg <-> mem operation with base + index reg addressing,
7759 we have to handle this in a special way. */
7760 rtx mem = operands[0];
7762 if (! memory_operand (mem, DFmode))
7767 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
7768 mem = SUBREG_REG (mem);
7771 rtx addr = XEXP (mem, 0);
7772 if (GET_CODE (addr) == PLUS
7773 && REG_P (XEXP (addr, 0))
7774 && REG_P (XEXP (addr, 1)))
7777 rtx reg0 = gen_rtx_REG (Pmode, 0);
7778 rtx regop = operands[store_p], word0 ,word1;
7780 if (GET_CODE (regop) == SUBREG)
7781 alter_subreg (®op, true);
7782 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
7786 mem = copy_rtx (mem);
7787 PUT_MODE (mem, SImode);
7788 word0 = gen_rtx_SUBREG (SImode, regop, 0);
7789 alter_subreg (&word0, true);
7790 word1 = gen_rtx_SUBREG (SImode, regop, 4);
7791 alter_subreg (&word1, true);
7792 if (store_p || ! refers_to_regno_p (REGNO (word0),
7793 REGNO (word0) + 1, addr, 0))
7796 ? gen_movsi_ie (mem, word0)
7797 : gen_movsi_ie (word0, mem));
7798 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
7799 mem = copy_rtx (mem);
7801 ? gen_movsi_ie (mem, word1)
7802 : gen_movsi_ie (word1, mem));
7803 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
7807 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
7808 emit_insn (gen_movsi_ie (word1, mem));
7809 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
7810 mem = copy_rtx (mem);
7811 emit_insn (gen_movsi_ie (word0, mem));
7818 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
7820 [(set (match_operand:DF 0 "register_operand" "")
7821 (match_operand:DF 1 "memory_operand" ""))
7822 (use (match_operand:PSI 2 "fpscr_operand" ""))
7823 (clobber (reg:SI R0_REG))]
7824 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed"
7825 [(parallel [(set (match_dup 0) (match_dup 1))
7827 (clobber (scratch:SI))])]
7830 (define_expand "reload_indf__frn"
7831 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
7832 (match_operand:DF 1 "immediate_operand" "FQ"))
7833 (use (reg:PSI FPSCR_REG))
7834 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
7838 (define_expand "reload_outdf__RnFRm"
7839 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
7840 (match_operand:DF 1 "register_operand" "af,r"))
7841 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
7845 ;; Simplify no-op moves.
7847 [(set (match_operand:SF 0 "register_operand" "")
7848 (match_operand:SF 1 "register_operand" ""))
7849 (use (match_operand:PSI 2 "fpscr_operand" ""))
7850 (clobber (match_scratch:SI 3 ""))]
7851 "TARGET_SH2E && reload_completed
7852 && true_regnum (operands[0]) == true_regnum (operands[1])"
7853 [(set (match_dup 0) (match_dup 0))]
7856 ;; fmovd substitute post-reload splits
7858 [(set (match_operand:DF 0 "register_operand" "")
7859 (match_operand:DF 1 "register_operand" ""))
7860 (use (match_operand:PSI 2 "fpscr_operand" ""))
7861 (clobber (match_scratch:SI 3 ""))]
7862 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
7863 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
7864 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
7867 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
7868 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
7869 gen_rtx_REG (SFmode, src), operands[2]));
7870 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
7871 gen_rtx_REG (SFmode, src + 1), operands[2]));
7876 [(set (match_operand:DF 0 "register_operand" "")
7877 (mem:DF (match_operand:SI 1 "register_operand" "")))
7878 (use (match_operand:PSI 2 "fpscr_operand" ""))
7879 (clobber (match_scratch:SI 3 ""))]
7880 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7881 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
7882 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
7885 int regno = true_regnum (operands[0]);
7887 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
7889 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
7890 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
7891 regno + SH_REG_MSW_OFFSET),
7892 mem2, operands[2]));
7893 add_reg_note (insn, REG_INC, operands[1]);
7894 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
7895 regno + SH_REG_LSW_OFFSET),
7896 change_address (mem, SFmode, NULL_RTX),
7902 [(set (match_operand:DF 0 "register_operand" "")
7903 (match_operand:DF 1 "memory_operand" ""))
7904 (use (match_operand:PSI 2 "fpscr_operand" ""))
7905 (clobber (match_scratch:SI 3 ""))]
7906 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7907 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
7910 int regno = true_regnum (operands[0]);
7912 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
7913 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
7914 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
7916 operands[1] = copy_rtx (mem2);
7917 addr = XEXP (mem2, 0);
7919 switch (GET_CODE (addr))
7922 /* This is complicated. If the register is an arithmetic register
7923 we can just fall through to the REG+DISP case below. Otherwise
7924 we have to use a combination of POST_INC and REG addressing... */
7925 if (! arith_reg_operand (operands[1], SFmode))
7927 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
7928 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
7929 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7931 emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
7933 /* If we have modified the stack pointer, the value that we have
7934 read with post-increment might be modified by an interrupt,
7935 so write it back. */
7936 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
7937 emit_insn (gen_push_e (reg0));
7939 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
7946 emit_insn (gen_movsf_ie (reg0, operands[1], operands[2]));
7947 operands[1] = copy_rtx (operands[1]);
7948 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
7949 emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
7953 insn = emit_insn (gen_movsf_ie (reg0, operands[1], operands[2]));
7954 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7956 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
7957 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7969 [(set (match_operand:DF 0 "memory_operand" "")
7970 (match_operand:DF 1 "register_operand" ""))
7971 (use (match_operand:PSI 2 "fpscr_operand" ""))
7972 (clobber (match_scratch:SI 3 ""))]
7973 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7974 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
7977 int regno = true_regnum (operands[1]);
7979 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
7980 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
7982 operands[0] = copy_rtx (operands[0]);
7983 PUT_MODE (operands[0], SFmode);
7984 addr = XEXP (operands[0], 0);
7986 switch (GET_CODE (addr))
7989 /* This is complicated. If the register is an arithmetic register
7990 we can just fall through to the REG+DISP case below. Otherwise
7991 we have to use a combination of REG and PRE_DEC addressing... */
7992 if (! arith_reg_operand (operands[0], SFmode))
7994 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
7995 emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
7997 operands[0] = copy_rtx (operands[0]);
7998 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
8000 insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
8001 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8007 /* Since REG+DISP addressing has already been decided upon by gcc
8008 we can rely upon it having chosen an arithmetic register as the
8009 register component of the address. Just emit the lower numbered
8010 register first, to the lower address, then the higher numbered
8011 register to the higher address. */
8012 emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
8014 operands[0] = copy_rtx (operands[0]);
8015 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
8017 emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
8021 /* This is easy. Output the word to go to the higher address
8022 first (ie the word in the higher numbered register) then the
8023 word to go to the lower address. */
8025 insn = emit_insn (gen_movsf_ie (operands[0], reg1, operands[2]));
8026 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8028 insn = emit_insn (gen_movsf_ie (operands[0], reg0, operands[2]));
8029 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8041 ;; If the output is a register and the input is memory or a register, we have
8042 ;; to be careful and see which word needs to be loaded first.
8044 [(set (match_operand:DF 0 "general_movdst_operand" "")
8045 (match_operand:DF 1 "general_movsrc_operand" ""))]
8046 "TARGET_SH1 && reload_completed"
8047 [(set (match_dup 2) (match_dup 3))
8048 (set (match_dup 4) (match_dup 5))]
8052 if ((MEM_P (operands[0])
8053 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
8054 || (MEM_P (operands[1])
8055 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
8058 switch (GET_CODE (operands[0]))
8061 regno = REGNO (operands[0]);
8064 regno = subreg_regno (operands[0]);
8074 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
8076 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
8077 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
8078 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
8079 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
8083 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
8084 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
8085 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
8086 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
8089 if (operands[2] == 0 || operands[3] == 0
8090 || operands[4] == 0 || operands[5] == 0)
8094 (define_expand "movdf"
8095 [(set (match_operand:DF 0 "general_movdst_operand" "")
8096 (match_operand:DF 1 "general_movsrc_operand" ""))]
8099 prepare_move_operands (operands, DFmode);
8102 if (TARGET_SHMEDIA_FPU)
8103 emit_insn (gen_movdf_media (operands[0], operands[1]));
8105 emit_insn (gen_movdf_media_nofpu (operands[0], operands[1]));
8108 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
8110 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
8115 ;;This is incompatible with the way gcc uses subregs.
8116 ;;(define_insn "movv2sf_i"
8117 ;; [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
8118 ;; (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
8119 ;; "TARGET_SHMEDIA_FPU
8120 ;; && (fp_arith_reg_operand (operands[0], V2SFmode)
8121 ;; || fp_arith_reg_operand (operands[1], V2SFmode))"
8125 ;; fst%M0.p %m0, %1"
8126 ;; [(set_attr "type" "*,fload_media,fstore_media")])
8127 (define_insn_and_split "movv2sf_i"
8128 [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
8129 (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
8130 "TARGET_SHMEDIA_FPU"
8132 "TARGET_SHMEDIA_FPU && reload_completed"
8133 [(set (match_dup 0) (match_dup 1))]
8135 operands[0] = simplify_gen_subreg (DFmode, operands[0], V2SFmode, 0);
8136 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2SFmode, 0);
8139 (define_expand "movv2sf"
8140 [(set (match_operand:V2SF 0 "general_movdst_operand" "")
8141 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
8142 "TARGET_SHMEDIA_FPU"
8144 prepare_move_operands (operands, V2SFmode);
8147 (define_expand "addv2sf3"
8148 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8149 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8150 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8151 "TARGET_SHMEDIA_FPU"
8153 sh_expand_binop_v2sf (PLUS, operands[0], operands[1], operands[2]);
8157 (define_expand "subv2sf3"
8158 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8159 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8160 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8161 "TARGET_SHMEDIA_FPU"
8163 sh_expand_binop_v2sf (MINUS, operands[0], operands[1], operands[2]);
8167 (define_expand "mulv2sf3"
8168 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8169 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8170 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8171 "TARGET_SHMEDIA_FPU"
8173 sh_expand_binop_v2sf (MULT, operands[0], operands[1], operands[2]);
8177 (define_expand "divv2sf3"
8178 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8179 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8180 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8181 "TARGET_SHMEDIA_FPU"
8183 sh_expand_binop_v2sf (DIV, operands[0], operands[1], operands[2]);
8187 (define_insn_and_split "*movv4sf_i"
8188 [(set (match_operand:V4SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
8189 (match_operand:V4SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
8190 "TARGET_SHMEDIA_FPU"
8192 "&& reload_completed"
8195 for (int i = 0; i < 4/2; i++)
8199 if (MEM_P (operands[0]))
8200 x = adjust_address (operands[0], V2SFmode,
8201 i * GET_MODE_SIZE (V2SFmode));
8203 x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8);
8205 if (MEM_P (operands[1]))
8206 y = adjust_address (operands[1], V2SFmode,
8207 i * GET_MODE_SIZE (V2SFmode));
8209 y = simplify_gen_subreg (V2SFmode, operands[1], V4SFmode, i * 8);
8211 emit_insn (gen_movv2sf_i (x, y));
8216 [(set_attr "length" "8")])
8218 (define_expand "movv4sf"
8219 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
8220 (match_operand:V4SF 1 "general_operand" ""))]
8221 "TARGET_SHMEDIA_FPU"
8223 prepare_move_operands (operands, V4SFmode);
8226 (define_insn_and_split "*movv16sf_i"
8227 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8228 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8229 "TARGET_SHMEDIA_FPU"
8231 "&& reload_completed"
8234 for (int i = 0; i < 16/2; i++)
8238 if (MEM_P (operands[0]))
8239 x = adjust_address (operands[0], V2SFmode,
8240 i * GET_MODE_SIZE (V2SFmode));
8243 x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 8);
8244 alter_subreg (&x, true);
8247 if (MEM_P (operands[1]))
8248 y = adjust_address (operands[1], V2SFmode,
8249 i * GET_MODE_SIZE (V2SFmode));
8252 y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 8);
8253 alter_subreg (&y, true);
8256 emit_insn (gen_movv2sf_i (x, y));
8261 [(set_attr "length" "32")])
8263 (define_expand "movv16sf"
8264 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8265 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8266 "TARGET_SHMEDIA_FPU"
8268 prepare_move_operands (operands, V16SFmode);
8271 (define_insn "movsf_media"
8272 [(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
8273 (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
8275 && (register_operand (operands[0], SFmode)
8276 || sh_register_operand (operands[1], SFmode))"
8287 [(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")
8288 (set (attr "highpart")
8289 (cond [(match_test "sh_contains_memref_p (insn)")
8290 (const_string "user")]
8291 (const_string "ignore")))])
8293 (define_insn "movsf_media_nofpu"
8294 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
8295 (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))]
8297 && (register_operand (operands[0], SFmode)
8298 || sh_register_operand (operands[1], SFmode))"
8304 [(set_attr "type" "arith_media,*,load_media,store_media")
8305 (set (attr "highpart")
8306 (cond [(match_test "sh_contains_memref_p (insn)")
8307 (const_string "user")]
8308 (const_string "ignore")))])
8311 [(set (match_operand:SF 0 "arith_reg_dest" "")
8312 (match_operand:SF 1 "immediate_operand" ""))]
8313 "TARGET_SHMEDIA && reload_completed
8314 && ! FP_REGISTER_P (true_regnum (operands[0]))"
8315 [(set (match_dup 3) (match_dup 2))]
8318 REAL_VALUE_TYPE value;
8320 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
8321 REAL_VALUE_TO_TARGET_SINGLE (value, values);
8322 operands[2] = GEN_INT (values);
8324 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
8327 (define_insn "movsf_i"
8328 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
8329 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
8332 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
8333 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
8334 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
8335 && (arith_reg_operand (operands[0], SFmode)
8336 || arith_reg_operand (operands[1], SFmode))"
8345 [(set_attr "type" "move,move,pcload,load,store,move,move")])
8347 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
8348 ;; update_flow_info would not know where to put REG_EQUAL notes
8349 ;; when the destination changes mode.
8350 (define_insn "movsf_ie"
8351 [(set (match_operand:SF 0 "general_movdst_operand"
8352 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
8353 (match_operand:SF 1 "general_movsrc_operand"
8354 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
8355 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
8356 (clobber (match_scratch:SI 3 "=X,X,Bsc,Bsc,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
8358 && (arith_reg_operand (operands[0], SFmode) || fpul_operand (operands[0], SFmode)
8359 || arith_reg_operand (operands[1], SFmode) || fpul_operand (operands[1], SFmode)
8360 || arith_reg_operand (operands[3], SImode))"
8380 ! move optimized away"
8381 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
8382 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
8383 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
8384 (set_attr_alternative "length"
8391 (match_test "TARGET_SH2A")
8392 (const_int 4) (const_int 2))
8394 (match_test "TARGET_SH2A")
8395 (const_int 4) (const_int 2))
8398 (match_test "TARGET_SH2A")
8399 (const_int 4) (const_int 2))
8401 (match_test "TARGET_SH2A")
8402 (const_int 4) (const_int 2))
8412 (set_attr_alternative "fp_mode"
8413 [(if_then_else (eq_attr "fmovd" "yes")
8414 (const_string "single") (const_string "none"))
8415 (const_string "none")
8416 (const_string "single")
8417 (const_string "single")
8418 (const_string "none")
8419 (if_then_else (eq_attr "fmovd" "yes")
8420 (const_string "single") (const_string "none"))
8421 (if_then_else (eq_attr "fmovd" "yes")
8422 (const_string "single") (const_string "none"))
8423 (const_string "none")
8424 (const_string "none")
8425 (const_string "none")
8426 (const_string "none")
8427 (const_string "none")
8428 (const_string "none")
8429 (const_string "none")
8430 (const_string "none")
8431 (const_string "none")
8432 (const_string "none")
8433 (const_string "none")
8434 (const_string "none")])])
8437 [(set (match_operand:SF 0 "register_operand" "")
8438 (match_operand:SF 1 "register_operand" ""))
8439 (use (match_operand:PSI 2 "fpscr_operand" ""))
8440 (clobber (reg:SI FPUL_REG))]
8442 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
8444 (clobber (scratch:SI))])
8445 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
8447 (clobber (scratch:SI))])]
8450 (define_expand "movsf"
8451 [(set (match_operand:SF 0 "general_movdst_operand" "")
8452 (match_operand:SF 1 "general_movsrc_operand" ""))]
8455 prepare_move_operands (operands, SFmode);
8458 if (TARGET_SHMEDIA_FPU)
8459 emit_insn (gen_movsf_media (operands[0], operands[1]));
8461 emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
8466 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
8471 (define_insn "mov_nop"
8472 [(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
8475 [(set_attr "length" "0")
8476 (set_attr "type" "nil")])
8478 (define_expand "reload_insf__frn"
8479 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
8480 (match_operand:SF 1 "immediate_operand" "FQ"))
8481 (use (reg:PSI FPSCR_REG))
8482 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8486 (define_expand "reload_insi__i_fpul"
8487 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
8488 (match_operand:SI 1 "immediate_operand" "i"))
8489 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8493 (define_expand "ptabs"
8494 [(set (match_operand 0 "" "=b") (match_operand 1 "" "r"))]
8497 if (!TARGET_PT_FIXED)
8499 rtx eq = operands[1];
8501 /* ??? For canonical RTL we really should remove any CONST from EQ
8502 before wrapping it in the AND, and finally wrap the EQ into a
8503 const if is constant. However, for reload we must expose the
8504 input register or symbolic constant, and we can't have
8505 different insn structures outside of the operands for different
8506 alternatives of the same pattern. */
8507 eq = gen_rtx_EQ (SImode, gen_rtx_AND (Pmode, eq, GEN_INT (3)),
8510 = (gen_rtx_IF_THEN_ELSE
8513 gen_rtx_MEM (PDImode, operands[1]),
8514 gen_rtx_fmt_e (TARGET_SHMEDIA32 ? SIGN_EXTEND : TRUNCATE,
8515 PDImode, operands[1])));
8519 ;; expanded by ptabs expander.
8520 (define_insn "*extendsipdi_media"
8521 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8522 (if_then_else:PDI (eq (and:SI (match_operand:SI 1 "target_operand"
8526 (mem:PDI (match_dup 1))
8527 (sign_extend:PDI (match_dup 1))))]
8528 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8532 [(set_attr "type" "ptabs_media,pt_media")
8533 (set_attr "length" "4,*")])
8535 (define_insn "*truncdipdi_media"
8536 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8537 (if_then_else:PDI (eq (and:DI (match_operand:DI 1 "target_operand"
8541 (mem:PDI (match_dup 1))
8542 (truncate:PDI (match_dup 1))))]
8543 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8547 [(set_attr "type" "ptabs_media,pt_media")
8548 (set_attr "length" "4,*")])
8550 (define_insn "*movsi_y"
8551 [(set (match_operand:SI 0 "register_operand" "=y,y")
8552 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
8553 (clobber (match_scratch:SI 2 "=&z,r"))]
8555 && (reload_in_progress || reload_completed)"
8557 [(set_attr "length" "4")
8558 (set_attr "type" "pcload,move")])
8561 [(set (match_operand:SI 0 "register_operand" "")
8562 (match_operand:SI 1 "immediate_operand" ""))
8563 (clobber (match_operand:SI 2 "register_operand" ""))]
8565 [(set (match_dup 2) (match_dup 1))
8566 (set (match_dup 0) (match_dup 2))]
8569 ;; ------------------------------------------------------------------------
8570 ;; Define the real conditional branch instructions.
8571 ;; ------------------------------------------------------------------------
8573 (define_expand "branch_true"
8574 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
8575 (label_ref (match_operand 0))
8579 (define_expand "branch_false"
8580 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
8581 (label_ref (match_operand 0))
8585 (define_insn_and_split "*cbranch_t"
8586 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
8587 (label_ref (match_operand 0))
8591 return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
8596 /* Try to canonicalize the branch condition if it is not one of:
8597 (ne (reg:SI T_REG) (const_int 0))
8598 (eq (reg:SI T_REG) (const_int 0))
8600 Instead of splitting out a new insn, we modify the current insn's
8601 operands as needed. This preserves things such as REG_DEAD notes. */
8603 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
8604 && REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG
8605 && XEXP (operands[1], 1) == const0_rtx)
8608 int branch_cond = sh_eval_treg_value (operands[1]);
8609 rtx new_cond_rtx = NULL_RTX;
8611 if (branch_cond == 0)
8612 new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx);
8613 else if (branch_cond == 1)
8614 new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx);
8616 if (new_cond_rtx != NULL_RTX)
8617 validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0),
8618 new_cond_rtx, false);
8621 [(set_attr "type" "cbranch")])
8623 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
8624 ;; which destination is too far away.
8625 ;; The const_int_operand is distinct for each branch target; it avoids
8626 ;; unwanted matches with redundant_insn.
8627 (define_insn "block_branch_redirect"
8628 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
8631 [(set_attr "length" "0")])
8633 ;; This one has the additional purpose to record a possible scratch register
8634 ;; for the following branch.
8635 ;; ??? Unfortunately, just setting the scratch register is not good enough,
8636 ;; because the insn then might be deemed dead and deleted. And we can't
8637 ;; make the use in the jump insn explicit because that would disable
8638 ;; delay slot scheduling from the target.
8639 (define_insn "indirect_jump_scratch"
8640 [(set (match_operand:SI 0 "register_operand" "=r")
8641 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
8642 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
8645 [(set_attr "length" "0")])
8647 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
8648 ;; being pulled into the delay slot of a condbranch that has been made to
8649 ;; jump around the unconditional jump because it was out of range.
8650 (define_insn "stuff_delay_slot"
8652 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
8653 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
8656 [(set_attr "length" "0")
8657 (set_attr "cond_delay_slot" "yes")])
8659 ;; Conditional branch insns
8661 (define_expand "cbranchint4_media"
8663 (if_then_else (match_operator 0 "shmedia_cbranch_comparison_operator"
8664 [(match_operand 1 "" "")
8665 (match_operand 2 "" "")])
8666 (match_operand 3 "" "")
8670 enum machine_mode mode = GET_MODE (operands[1]);
8671 if (mode == VOIDmode)
8672 mode = GET_MODE (operands[2]);
8673 if (GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
8675 operands[1] = force_reg (mode, operands[1]);
8676 if (CONSTANT_P (operands[2])
8677 && (! satisfies_constraint_I06 (operands[2])))
8678 operands[2] = force_reg (mode, operands[2]);
8682 if (operands[1] != const0_rtx)
8683 operands[1] = force_reg (mode, operands[1]);
8684 if (operands[2] != const0_rtx)
8685 operands[2] = force_reg (mode, operands[2]);
8687 switch (GET_CODE (operands[0]))
8693 operands[0] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[0])),
8694 VOIDmode, operands[2], operands[1]);
8695 operands[1] = XEXP (operands[0], 0);
8696 operands[2] = XEXP (operands[0], 1);
8699 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
8700 VOIDmode, operands[1], operands[2]);
8703 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
8706 (define_expand "cbranchfp4_media"
8708 (if_then_else (match_operator 0 "sh_float_comparison_operator"
8709 [(match_operand 1 "" "")
8710 (match_operand 2 "" "")])
8711 (match_operand 3 "" "")
8715 rtx tmp = gen_reg_rtx (SImode);
8717 if (GET_CODE (operands[0]) == NE)
8718 cmp = gen_rtx_EQ (SImode, operands[1], operands[2]);
8720 cmp = gen_rtx_fmt_ee (GET_CODE (operands[0]), SImode,
8721 operands[1], operands[2]);
8723 emit_insn (gen_cstore4_media (tmp, cmp, operands[1], operands[2]));
8725 if (GET_CODE (cmp) == GET_CODE (operands[0]))
8726 operands[0] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
8728 operands[0] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
8730 operands[2] = const0_rtx;
8731 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
8734 (define_insn "*beq_media_i"
8736 (if_then_else (match_operator 3 "equality_comparison_operator"
8737 [(match_operand:DI 1 "arith_reg_operand" "r,r")
8738 (match_operand:DI 2 "arith_operand" "r,I06")])
8739 (match_operand 0 "target_operand" "b,b")
8744 b%o3i%' %1, %2, %0%>"
8745 [(set_attr "type" "cbranch_media")])
8747 (define_insn "*beq_media_i32"
8749 (if_then_else (match_operator 3 "equality_comparison_operator"
8750 [(match_operand:SI 1 "arith_reg_operand" "r,r")
8751 (match_operand:SI 2 "arith_operand" "r,I06")])
8752 (match_operand 0 "target_operand" "b,b")
8757 b%o3i%' %1, %2, %0%>"
8758 [(set_attr "type" "cbranch_media")])
8760 (define_insn "*bgt_media_i"
8762 (if_then_else (match_operator 3 "greater_comparison_operator"
8763 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
8764 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
8765 (match_operand 0 "target_operand" "b")
8768 "b%o3%' %N1, %N2, %0%>"
8769 [(set_attr "type" "cbranch_media")])
8771 (define_insn "*bgt_media_i32"
8773 (if_then_else (match_operator 3 "greater_comparison_operator"
8774 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
8775 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
8776 (match_operand 0 "target_operand" "b")
8779 "b%o3%' %N1, %N2, %0%>"
8780 [(set_attr "type" "cbranch_media")])
8782 ;; These are only needed to make invert_jump() happy - otherwise, jump
8783 ;; optimization will be silently disabled.
8784 (define_insn "*blt_media_i"
8786 (if_then_else (match_operator 3 "less_comparison_operator"
8787 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
8788 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
8789 (match_operand 0 "target_operand" "b")
8792 "b%o3%' %N2, %N1, %0%>"
8793 [(set_attr "type" "cbranch_media")])
8795 (define_insn "*blt_media_i32"
8797 (if_then_else (match_operator 3 "less_comparison_operator"
8798 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
8799 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
8800 (match_operand 0 "target_operand" "b")
8803 "b%o3%' %N2, %N1, %0%>"
8804 [(set_attr "type" "cbranch_media")])
8806 ;; combiner splitter for test-and-branch on single bit in register. This
8807 ;; is endian dependent because the non-paradoxical subreg looks different
8812 (match_operator 3 "equality_comparison_operator"
8815 (subreg:DI (match_operand:SI 1 "extend_reg_operand" "") 0)
8817 (match_operand 2 "const_int_operand" "")) 0)
8819 (match_operand 0 "target_operand" "")
8821 (clobber (match_operand:SI 4 "arith_reg_dest" ""))]
8822 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
8823 [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 5)))
8824 (set (pc) (if_then_else (match_dup 6) (match_dup 0) (pc)))]
8826 operands[5] = GEN_INT (31 - INTVAL (operands[2]));
8827 operands[6] = (GET_CODE (operands[3]) == EQ
8828 ? gen_rtx_GE (VOIDmode, operands[4], const0_rtx)
8829 : gen_rtx_GT (VOIDmode, const0_rtx, operands[4]));
8832 ; operand 0 is the loop count pseudo register
8833 ; operand 1 is the label to jump to at the top of the loop
8834 (define_expand "doloop_end"
8835 [(parallel [(set (pc)
8836 (if_then_else (ne:SI (match_operand:SI 0 "" "")
8838 (label_ref (match_operand 1 "" ""))
8841 (plus:SI (match_dup 0) (const_int -1)))
8842 (clobber (reg:SI T_REG))])]
8845 if (GET_MODE (operands[0]) != SImode)
8847 emit_jump_insn (gen_doloop_end_split (operands[0], operands[1], operands[0]));
8851 (define_insn_and_split "doloop_end_split"
8853 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
8855 (label_ref (match_operand 1 "" ""))
8857 (set (match_operand:SI 0 "arith_reg_dest" "=r")
8858 (plus:SI (match_dup 2) (const_int -1)))
8859 (clobber (reg:SI T_REG))]
8863 [(parallel [(set (reg:SI T_REG)
8864 (eq:SI (match_dup 2) (const_int 1)))
8865 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
8866 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
8867 (label_ref (match_dup 1))
8870 [(set_attr "type" "cbranch")])
8872 ;; ------------------------------------------------------------------------
8873 ;; Jump and linkage insns
8874 ;; ------------------------------------------------------------------------
8876 (define_insn "jump_compact"
8878 (label_ref (match_operand 0 "" "")))]
8879 "TARGET_SH1 && !CROSSING_JUMP_P (insn)"
8881 /* The length is 16 if the delay slot is unfilled. */
8882 if (get_attr_length(insn) > 4)
8883 return output_far_jump(insn, operands[0]);
8887 [(set_attr "type" "jump")
8888 (set_attr "needs_delay_slot" "yes")])
8890 ;; ??? It would be much saner to explicitly use the scratch register
8891 ;; in the jump insn, and have indirect_jump_scratch only set it,
8892 ;; but fill_simple_delay_slots would refuse to do delay slot filling
8893 ;; from the target then, as it uses simplejump_p.
8894 ;;(define_insn "jump_compact_far"
8896 ;; (label_ref (match_operand 0 "" "")))
8897 ;; (use (match_operand 1 "register_operand" "r")]
8899 ;; "* return output_far_jump(insn, operands[0], operands[1]);"
8900 ;; [(set_attr "type" "jump")
8901 ;; (set_attr "needs_delay_slot" "yes")])
8903 (define_insn "jump_media"
8905 (match_operand 0 "target_operand" "b"))]
8908 [(set_attr "type" "jump_media")])
8910 (define_expand "jump"
8912 (label_ref (match_operand 0 "" "")))]
8916 emit_jump_insn (gen_jump_compact (operands[0]));
8917 else if (TARGET_SHMEDIA)
8919 if (reload_in_progress || reload_completed)
8921 emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (Pmode, operands[0])));
8926 (define_insn "force_mode_for_call"
8927 [(use (reg:PSI FPSCR_REG))]
8930 [(set_attr "length" "0")
8931 (set (attr "fp_mode")
8932 (if_then_else (eq_attr "fpu_single" "yes")
8933 (const_string "single") (const_string "double")))])
8935 (define_insn "calli"
8936 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
8937 (match_operand 1 "" ""))
8938 (use (reg:PSI FPSCR_REG))
8939 (clobber (reg:SI PR_REG))]
8942 if (TARGET_SH2A && (dbr_sequence_length () == 0))
8947 [(set_attr "type" "call")
8948 (set (attr "fp_mode")
8949 (if_then_else (eq_attr "fpu_single" "yes")
8950 (const_string "single") (const_string "double")))
8951 (set_attr "needs_delay_slot" "yes")
8952 (set_attr "fp_set" "unknown")])
8954 ;; This is TBR relative jump instruction for SH2A architecture.
8955 ;; Its use is enabled by assigning an attribute "function_vector"
8956 ;; and the vector number to a function during its declaration.
8957 (define_insn "calli_tbr_rel"
8958 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
8959 (match_operand 1 "" ""))
8960 (use (reg:PSI FPSCR_REG))
8961 (clobber (reg:SI PR_REG))]
8962 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
8964 unsigned HOST_WIDE_INT vect_num;
8965 vect_num = sh2a_get_function_vector_number (operands[0]);
8966 operands[2] = GEN_INT (vect_num * 4);
8968 return "jsr/n @@(%O2,tbr)";
8970 [(set_attr "type" "call")
8971 (set (attr "fp_mode")
8972 (if_then_else (eq_attr "fpu_single" "yes")
8973 (const_string "single") (const_string "double")))
8974 (set_attr "needs_delay_slot" "no")
8975 (set_attr "fp_set" "unknown")])
8977 ;; This is a pc-rel call, using bsrf, for use with PIC.
8978 (define_insn "calli_pcrel"
8979 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
8980 (match_operand 1 "" ""))
8981 (use (reg:PSI FPSCR_REG))
8982 (use (reg:SI PIC_REG))
8983 (use (match_operand 2 "" ""))
8984 (clobber (reg:SI PR_REG))]
8987 return "bsrf %0" "\n"
8990 [(set_attr "type" "call")
8991 (set (attr "fp_mode")
8992 (if_then_else (eq_attr "fpu_single" "yes")
8993 (const_string "single") (const_string "double")))
8994 (set_attr "needs_delay_slot" "yes")
8995 (set_attr "fp_set" "unknown")])
8997 (define_insn_and_split "call_pcrel"
8998 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
8999 (match_operand 1 "" ""))
9000 (use (reg:PSI FPSCR_REG))
9001 (use (reg:SI PIC_REG))
9002 (clobber (reg:SI PR_REG))
9003 (clobber (match_scratch:SI 2 "=r"))]
9009 rtx lab = PATTERN (gen_call_site ());
9011 if (SYMBOL_REF_LOCAL_P (operands[0]))
9012 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
9014 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
9015 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
9018 [(set_attr "type" "call")
9019 (set (attr "fp_mode")
9020 (if_then_else (eq_attr "fpu_single" "yes")
9021 (const_string "single") (const_string "double")))
9022 (set_attr "needs_delay_slot" "yes")
9023 (set_attr "fp_set" "unknown")])
9025 (define_insn "call_compact"
9026 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9027 (match_operand 1 "" ""))
9028 (match_operand 2 "immediate_operand" "n")
9029 (use (reg:SI R0_REG))
9030 (use (reg:SI R1_REG))
9031 (use (reg:PSI FPSCR_REG))
9032 (clobber (reg:SI PR_REG))]
9033 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9035 [(set_attr "type" "call")
9036 (set (attr "fp_mode")
9037 (if_then_else (eq_attr "fpu_single" "yes")
9038 (const_string "single") (const_string "double")))
9039 (set_attr "needs_delay_slot" "yes")])
9041 (define_insn "call_compact_rettramp"
9042 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9043 (match_operand 1 "" ""))
9044 (match_operand 2 "immediate_operand" "n")
9045 (use (reg:SI R0_REG))
9046 (use (reg:SI R1_REG))
9047 (use (reg:PSI FPSCR_REG))
9048 (clobber (reg:SI R10_REG))
9049 (clobber (reg:SI PR_REG))]
9050 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9052 [(set_attr "type" "call")
9053 (set (attr "fp_mode")
9054 (if_then_else (eq_attr "fpu_single" "yes")
9055 (const_string "single") (const_string "double")))
9056 (set_attr "needs_delay_slot" "yes")])
9058 (define_insn "call_media"
9059 [(call (mem:DI (match_operand 0 "target_reg_operand" "b"))
9060 (match_operand 1 "" ""))
9061 (clobber (reg:DI PR_MEDIA_REG))]
9064 [(set_attr "type" "jump_media")])
9066 (define_insn "call_valuei"
9067 [(set (match_operand 0 "" "=rf")
9068 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9069 (match_operand 2 "" "")))
9070 (use (reg:PSI FPSCR_REG))
9071 (clobber (reg:SI PR_REG))]
9074 if (TARGET_SH2A && (dbr_sequence_length () == 0))
9079 [(set_attr "type" "call")
9080 (set (attr "fp_mode")
9081 (if_then_else (eq_attr "fpu_single" "yes")
9082 (const_string "single") (const_string "double")))
9083 (set_attr "needs_delay_slot" "yes")
9084 (set_attr "fp_set" "unknown")])
9086 ;; This is TBR relative jump instruction for SH2A architecture.
9087 ;; Its use is enabled by assigning an attribute "function_vector"
9088 ;; and the vector number to a function during its declaration.
9089 (define_insn "call_valuei_tbr_rel"
9090 [(set (match_operand 0 "" "=rf")
9091 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9092 (match_operand 2 "" "")))
9093 (use (reg:PSI FPSCR_REG))
9094 (clobber (reg:SI PR_REG))]
9095 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
9097 unsigned HOST_WIDE_INT vect_num;
9098 vect_num = sh2a_get_function_vector_number (operands[1]);
9099 operands[3] = GEN_INT (vect_num * 4);
9101 return "jsr/n @@(%O3,tbr)";
9103 [(set_attr "type" "call")
9104 (set (attr "fp_mode")
9105 (if_then_else (eq_attr "fpu_single" "yes")
9106 (const_string "single") (const_string "double")))
9107 (set_attr "needs_delay_slot" "no")
9108 (set_attr "fp_set" "unknown")])
9110 (define_insn "call_valuei_pcrel"
9111 [(set (match_operand 0 "" "=rf")
9112 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9113 (match_operand 2 "" "")))
9114 (use (reg:PSI FPSCR_REG))
9115 (use (reg:SI PIC_REG))
9116 (use (match_operand 3 "" ""))
9117 (clobber (reg:SI PR_REG))]
9120 return "bsrf %1" "\n"
9123 [(set_attr "type" "call")
9124 (set (attr "fp_mode")
9125 (if_then_else (eq_attr "fpu_single" "yes")
9126 (const_string "single") (const_string "double")))
9127 (set_attr "needs_delay_slot" "yes")
9128 (set_attr "fp_set" "unknown")])
9130 (define_insn_and_split "call_value_pcrel"
9131 [(set (match_operand 0 "" "=rf")
9132 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9133 (match_operand 2 "" "")))
9134 (use (reg:PSI FPSCR_REG))
9135 (use (reg:SI PIC_REG))
9136 (clobber (reg:SI PR_REG))
9137 (clobber (match_scratch:SI 3 "=r"))]
9143 rtx lab = PATTERN (gen_call_site ());
9145 if (SYMBOL_REF_LOCAL_P (operands[1]))
9146 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
9148 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
9149 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
9150 operands[2], copy_rtx (lab)));
9153 [(set_attr "type" "call")
9154 (set (attr "fp_mode")
9155 (if_then_else (eq_attr "fpu_single" "yes")
9156 (const_string "single") (const_string "double")))
9157 (set_attr "needs_delay_slot" "yes")
9158 (set_attr "fp_set" "unknown")])
9160 (define_insn "call_value_compact"
9161 [(set (match_operand 0 "" "=rf")
9162 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9163 (match_operand 2 "" "")))
9164 (match_operand 3 "immediate_operand" "n")
9165 (use (reg:SI R0_REG))
9166 (use (reg:SI R1_REG))
9167 (use (reg:PSI FPSCR_REG))
9168 (clobber (reg:SI PR_REG))]
9169 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9171 [(set_attr "type" "call")
9172 (set (attr "fp_mode")
9173 (if_then_else (eq_attr "fpu_single" "yes")
9174 (const_string "single") (const_string "double")))
9175 (set_attr "needs_delay_slot" "yes")])
9177 (define_insn "call_value_compact_rettramp"
9178 [(set (match_operand 0 "" "=rf")
9179 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9180 (match_operand 2 "" "")))
9181 (match_operand 3 "immediate_operand" "n")
9182 (use (reg:SI R0_REG))
9183 (use (reg:SI R1_REG))
9184 (use (reg:PSI FPSCR_REG))
9185 (clobber (reg:SI R10_REG))
9186 (clobber (reg:SI PR_REG))]
9187 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9189 [(set_attr "type" "call")
9190 (set (attr "fp_mode")
9191 (if_then_else (eq_attr "fpu_single" "yes")
9192 (const_string "single") (const_string "double")))
9193 (set_attr "needs_delay_slot" "yes")])
9195 (define_insn "call_value_media"
9196 [(set (match_operand 0 "" "=rf")
9197 (call (mem:DI (match_operand 1 "target_reg_operand" "b"))
9198 (match_operand 2 "" "")))
9199 (clobber (reg:DI PR_MEDIA_REG))]
9202 [(set_attr "type" "jump_media")])
9204 (define_expand "call"
9205 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9206 (match_operand 1 "" ""))
9207 (match_operand 2 "" "")
9208 (use (reg:PSI FPSCR_REG))
9209 (clobber (reg:SI PR_REG))])]
9214 operands[0] = shmedia_prepare_call_address (operands[0], 0);
9215 emit_call_insn (gen_call_media (operands[0], operands[1]));
9218 else if (TARGET_SHCOMPACT && operands[2] && INTVAL (operands[2]))
9220 rtx cookie_rtx = operands[2];
9221 long cookie = INTVAL (cookie_rtx);
9222 rtx func = XEXP (operands[0], 0);
9227 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9229 rtx reg = gen_reg_rtx (Pmode);
9231 emit_insn (gen_symGOTPLT2reg (reg, func));
9235 func = legitimize_pic_address (func, Pmode, 0);
9238 r0 = gen_rtx_REG (SImode, R0_REG);
9239 r1 = gen_rtx_REG (SImode, R1_REG);
9241 /* Since such a call function may use all call-clobbered
9242 registers, we force a mode switch earlier, so that we don't
9243 run out of registers when adjusting fpscr for the call. */
9244 emit_insn (gen_force_mode_for_call ());
9247 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9248 operands[0] = force_reg (SImode, operands[0]);
9250 emit_move_insn (r0, func);
9251 emit_move_insn (r1, cookie_rtx);
9253 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9254 emit_call_insn (gen_call_compact_rettramp (operands[0], operands[1],
9257 emit_call_insn (gen_call_compact (operands[0], operands[1],
9262 else if (TARGET_SHCOMPACT && flag_pic
9263 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9264 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9266 rtx reg = gen_reg_rtx (Pmode);
9268 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[0], 0)));
9269 XEXP (operands[0], 0) = reg;
9271 if (!flag_pic && TARGET_SH2A
9272 && MEM_P (operands[0])
9273 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9275 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
9277 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
9282 if (flag_pic && TARGET_SH2
9283 && MEM_P (operands[0])
9284 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9286 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
9291 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
9292 operands[1] = operands[2];
9295 emit_call_insn (gen_calli (operands[0], operands[1]));
9299 (define_insn "call_pop_compact"
9300 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9301 (match_operand 1 "" ""))
9302 (match_operand 2 "immediate_operand" "n")
9303 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9304 (match_operand 3 "immediate_operand" "n")))
9305 (use (reg:SI R0_REG))
9306 (use (reg:SI R1_REG))
9307 (use (reg:PSI FPSCR_REG))
9308 (clobber (reg:SI PR_REG))]
9309 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9311 [(set_attr "type" "call")
9312 (set (attr "fp_mode")
9313 (if_then_else (eq_attr "fpu_single" "yes")
9314 (const_string "single") (const_string "double")))
9315 (set_attr "needs_delay_slot" "yes")])
9317 (define_insn "call_pop_compact_rettramp"
9318 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9319 (match_operand 1 "" ""))
9320 (match_operand 2 "immediate_operand" "n")
9321 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9322 (match_operand 3 "immediate_operand" "n")))
9323 (use (reg:SI R0_REG))
9324 (use (reg:SI R1_REG))
9325 (use (reg:PSI FPSCR_REG))
9326 (clobber (reg:SI R10_REG))
9327 (clobber (reg:SI PR_REG))]
9328 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9330 [(set_attr "type" "call")
9331 (set (attr "fp_mode")
9332 (if_then_else (eq_attr "fpu_single" "yes")
9333 (const_string "single") (const_string "double")))
9334 (set_attr "needs_delay_slot" "yes")])
9336 (define_expand "call_pop"
9337 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9338 (match_operand 1 "" ""))
9339 (match_operand 2 "" "")
9340 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9341 (match_operand 3 "" "")))])]
9349 gcc_assert (operands[2] && INTVAL (operands[2]));
9350 cookie_rtx = operands[2];
9351 cookie = INTVAL (cookie_rtx);
9352 func = XEXP (operands[0], 0);
9356 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9358 rtx reg = gen_reg_rtx (Pmode);
9359 emit_insn (gen_symGOTPLT2reg (reg, func));
9363 func = legitimize_pic_address (func, Pmode, 0);
9366 r0 = gen_rtx_REG (SImode, R0_REG);
9367 r1 = gen_rtx_REG (SImode, R1_REG);
9369 /* Since such a call function may use all call-clobbered
9370 registers, we force a mode switch earlier, so that we don't
9371 run out of registers when adjusting fpscr for the call. */
9372 emit_insn (gen_force_mode_for_call ());
9374 operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
9376 operands[0] = force_reg (SImode, operands[0]);
9378 emit_move_insn (r0, func);
9379 emit_move_insn (r1, cookie_rtx);
9381 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9382 emit_call_insn (gen_call_pop_compact_rettramp
9383 (operands[0], operands[1], operands[2], operands[3]));
9385 emit_call_insn (gen_call_pop_compact
9386 (operands[0], operands[1], operands[2], operands[3]));
9391 (define_expand "call_value"
9392 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
9393 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9394 (match_operand 2 "" "")))
9395 (match_operand 3 "" "")
9396 (use (reg:PSI FPSCR_REG))
9397 (clobber (reg:SI PR_REG))])]
9402 operands[1] = shmedia_prepare_call_address (operands[1], 0);
9403 emit_call_insn (gen_call_value_media (operands[0], operands[1],
9407 else if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]))
9409 rtx cookie_rtx = operands[3];
9410 long cookie = INTVAL (cookie_rtx);
9411 rtx func = XEXP (operands[1], 0);
9416 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9418 rtx reg = gen_reg_rtx (Pmode);
9420 emit_insn (gen_symGOTPLT2reg (reg, func));
9424 func = legitimize_pic_address (func, Pmode, 0);
9427 r0 = gen_rtx_REG (SImode, R0_REG);
9428 r1 = gen_rtx_REG (SImode, R1_REG);
9430 /* Since such a call function may use all call-clobbered
9431 registers, we force a mode switch earlier, so that we don't
9432 run out of registers when adjusting fpscr for the call. */
9433 emit_insn (gen_force_mode_for_call ());
9436 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9437 operands[1] = force_reg (SImode, operands[1]);
9439 emit_move_insn (r0, func);
9440 emit_move_insn (r1, cookie_rtx);
9442 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9443 emit_call_insn (gen_call_value_compact_rettramp (operands[0],
9448 emit_call_insn (gen_call_value_compact (operands[0], operands[1],
9449 operands[2], operands[3]));
9453 else if (TARGET_SHCOMPACT && flag_pic
9454 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9455 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9457 rtx reg = gen_reg_rtx (Pmode);
9459 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[1], 0)));
9460 XEXP (operands[1], 0) = reg;
9462 if (!flag_pic && TARGET_SH2A
9463 && MEM_P (operands[1])
9464 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9466 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
9468 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
9469 XEXP (operands[1], 0), operands[2]));
9473 if (flag_pic && TARGET_SH2
9474 && MEM_P (operands[1])
9475 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9477 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
9482 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
9484 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
9488 (define_insn "sibcalli"
9489 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
9490 (match_operand 1 "" ""))
9491 (use (reg:PSI FPSCR_REG))
9495 [(set_attr "needs_delay_slot" "yes")
9496 (set (attr "fp_mode")
9497 (if_then_else (eq_attr "fpu_single" "yes")
9498 (const_string "single") (const_string "double")))
9499 (set_attr "type" "jump_ind")])
9501 (define_insn "sibcalli_pcrel"
9502 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
9503 (match_operand 1 "" ""))
9504 (use (match_operand 2 "" ""))
9505 (use (reg:PSI FPSCR_REG))
9509 return "braf %0" "\n"
9512 [(set_attr "needs_delay_slot" "yes")
9513 (set (attr "fp_mode")
9514 (if_then_else (eq_attr "fpu_single" "yes")
9515 (const_string "single") (const_string "double")))
9516 (set_attr "type" "jump_ind")])
9518 ;; This uses an unspec to describe that the symbol_ref is very close.
9519 (define_insn "sibcalli_thunk"
9520 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
9522 (match_operand 1 "" ""))
9523 (use (reg:PSI FPSCR_REG))
9527 [(set_attr "needs_delay_slot" "yes")
9528 (set (attr "fp_mode")
9529 (if_then_else (eq_attr "fpu_single" "yes")
9530 (const_string "single") (const_string "double")))
9531 (set_attr "type" "jump")
9532 (set_attr "length" "2")])
9534 (define_insn_and_split "sibcall_pcrel"
9535 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
9536 (match_operand 1 "" ""))
9537 (use (reg:PSI FPSCR_REG))
9538 (clobber (match_scratch:SI 2 "=k"))
9545 rtx lab = PATTERN (gen_call_site ());
9548 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
9549 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
9551 SIBLING_CALL_P (call_insn) = 1;
9554 [(set_attr "needs_delay_slot" "yes")
9555 (set (attr "fp_mode")
9556 (if_then_else (eq_attr "fpu_single" "yes")
9557 (const_string "single") (const_string "double")))
9558 (set_attr "type" "jump_ind")])
9560 (define_insn "sibcall_compact"
9561 [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
9562 (match_operand 1 "" ""))
9564 (use (match_operand:SI 2 "register_operand" "z,x"))
9565 (use (reg:SI R1_REG))
9566 (use (reg:PSI FPSCR_REG))
9567 ;; We want to make sure the `x' above will only match MACH_REG
9568 ;; because sibcall_epilogue may clobber MACL_REG.
9569 (clobber (reg:SI MACL_REG))]
9572 static const char* alt[] =
9579 return alt[which_alternative];
9581 [(set_attr "needs_delay_slot" "yes,no")
9582 (set_attr "length" "2,4")
9583 (set (attr "fp_mode") (const_string "single"))
9584 (set_attr "type" "jump_ind")])
9586 (define_insn "sibcall_media"
9587 [(call (mem:DI (match_operand 0 "target_reg_operand" "k"))
9588 (match_operand 1 "" ""))
9589 (use (reg:SI PR_MEDIA_REG))
9593 [(set_attr "type" "jump_media")])
9595 (define_expand "sibcall"
9597 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9598 (match_operand 1 "" ""))
9599 (match_operand 2 "" "")
9600 (use (reg:PSI FPSCR_REG))
9606 operands[0] = shmedia_prepare_call_address (operands[0], 1);
9607 emit_call_insn (gen_sibcall_media (operands[0], operands[1]));
9610 else if (TARGET_SHCOMPACT && operands[2]
9611 && (INTVAL (operands[2]) & ~ CALL_COOKIE_RET_TRAMP (1)))
9613 rtx cookie_rtx = operands[2];
9614 long cookie = INTVAL (cookie_rtx);
9615 rtx func = XEXP (operands[0], 0);
9620 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9622 rtx reg = gen_reg_rtx (Pmode);
9624 emit_insn (gen_symGOT2reg (reg, func));
9628 func = legitimize_pic_address (func, Pmode, 0);
9631 /* FIXME: if we could tell whether all argument registers are
9632 already taken, we could decide whether to force the use of
9633 MACH_REG or to stick to R0_REG. Unfortunately, there's no
9634 simple way to tell. We could use the CALL_COOKIE, but we
9635 can't currently tell a register used for regular argument
9636 passing from one that is unused. If we leave it up to reload
9637 to decide which register to use, it seems to always choose
9638 R0_REG, which leaves no available registers in SIBCALL_REGS
9639 to hold the address of the trampoline. */
9640 mach = gen_rtx_REG (SImode, MACH_REG);
9641 r1 = gen_rtx_REG (SImode, R1_REG);
9643 /* Since such a call function may use all call-clobbered
9644 registers, we force a mode switch earlier, so that we don't
9645 run out of registers when adjusting fpscr for the call. */
9646 emit_insn (gen_force_mode_for_call ());
9649 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9650 operands[0] = force_reg (SImode, operands[0]);
9652 /* We don't need a return trampoline, since the callee will
9653 return directly to the upper caller. */
9654 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9656 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
9657 cookie_rtx = GEN_INT (cookie);
9660 emit_move_insn (mach, func);
9661 emit_move_insn (r1, cookie_rtx);
9663 emit_call_insn (gen_sibcall_compact (operands[0], operands[1], mach));
9666 else if (TARGET_SHCOMPACT && flag_pic
9667 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9668 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9670 rtx reg = gen_reg_rtx (Pmode);
9672 emit_insn (gen_symGOT2reg (reg, XEXP (operands[0], 0)));
9673 XEXP (operands[0], 0) = reg;
9675 if (flag_pic && TARGET_SH2
9676 && MEM_P (operands[0])
9677 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9678 /* The PLT needs the PIC register, but the epilogue would have
9679 to restore it, so we can only use PC-relative PIC calls for
9680 static functions. */
9681 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9683 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
9687 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
9689 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
9693 (define_insn "sibcall_valuei"
9694 [(set (match_operand 0 "" "=rf")
9695 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
9696 (match_operand 2 "" "")))
9697 (use (reg:PSI FPSCR_REG))
9701 [(set_attr "needs_delay_slot" "yes")
9702 (set (attr "fp_mode")
9703 (if_then_else (eq_attr "fpu_single" "yes")
9704 (const_string "single") (const_string "double")))
9705 (set_attr "type" "jump_ind")])
9707 (define_insn "sibcall_valuei_pcrel"
9708 [(set (match_operand 0 "" "=rf")
9709 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
9710 (match_operand 2 "" "")))
9711 (use (match_operand 3 "" ""))
9712 (use (reg:PSI FPSCR_REG))
9716 return "braf %1" "\n"
9719 [(set_attr "needs_delay_slot" "yes")
9720 (set (attr "fp_mode")
9721 (if_then_else (eq_attr "fpu_single" "yes")
9722 (const_string "single") (const_string "double")))
9723 (set_attr "type" "jump_ind")])
9725 (define_insn_and_split "sibcall_value_pcrel"
9726 [(set (match_operand 0 "" "=rf")
9727 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9728 (match_operand 2 "" "")))
9729 (use (reg:PSI FPSCR_REG))
9730 (clobber (match_scratch:SI 3 "=k"))
9737 rtx lab = PATTERN (gen_call_site ());
9740 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
9741 call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
9745 SIBLING_CALL_P (call_insn) = 1;
9748 [(set_attr "needs_delay_slot" "yes")
9749 (set (attr "fp_mode")
9750 (if_then_else (eq_attr "fpu_single" "yes")
9751 (const_string "single") (const_string "double")))
9752 (set_attr "type" "jump_ind")])
9754 (define_insn "sibcall_value_compact"
9755 [(set (match_operand 0 "" "=rf,rf")
9756 (call (mem:SI (match_operand:SI 1 "register_operand" "k,k"))
9757 (match_operand 2 "" "")))
9759 (use (match_operand:SI 3 "register_operand" "z,x"))
9760 (use (reg:SI R1_REG))
9761 (use (reg:PSI FPSCR_REG))
9762 ;; We want to make sure the `x' above will only match MACH_REG
9763 ;; because sibcall_epilogue may clobber MACL_REG.
9764 (clobber (reg:SI MACL_REG))]
9767 static const char* alt[] =
9774 return alt[which_alternative];
9776 [(set_attr "needs_delay_slot" "yes,no")
9777 (set_attr "length" "2,4")
9778 (set (attr "fp_mode") (const_string "single"))
9779 (set_attr "type" "jump_ind")])
9781 (define_insn "sibcall_value_media"
9782 [(set (match_operand 0 "" "=rf")
9783 (call (mem:DI (match_operand 1 "target_reg_operand" "k"))
9784 (match_operand 2 "" "")))
9785 (use (reg:SI PR_MEDIA_REG))
9789 [(set_attr "type" "jump_media")])
9791 (define_expand "sibcall_value"
9793 [(set (match_operand 0 "arith_reg_operand" "")
9794 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9795 (match_operand 2 "" "")))
9796 (match_operand 3 "" "")
9797 (use (reg:PSI FPSCR_REG))
9803 operands[1] = shmedia_prepare_call_address (operands[1], 1);
9804 emit_call_insn (gen_sibcall_value_media (operands[0], operands[1],
9808 else if (TARGET_SHCOMPACT && operands[3]
9809 && (INTVAL (operands[3]) & ~ CALL_COOKIE_RET_TRAMP (1)))
9811 rtx cookie_rtx = operands[3];
9812 long cookie = INTVAL (cookie_rtx);
9813 rtx func = XEXP (operands[1], 0);
9818 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9820 rtx reg = gen_reg_rtx (Pmode);
9822 emit_insn (gen_symGOT2reg (reg, func));
9826 func = legitimize_pic_address (func, Pmode, 0);
9829 /* FIXME: if we could tell whether all argument registers are
9830 already taken, we could decide whether to force the use of
9831 MACH_REG or to stick to R0_REG. Unfortunately, there's no
9832 simple way to tell. We could use the CALL_COOKIE, but we
9833 can't currently tell a register used for regular argument
9834 passing from one that is unused. If we leave it up to reload
9835 to decide which register to use, it seems to always choose
9836 R0_REG, which leaves no available registers in SIBCALL_REGS
9837 to hold the address of the trampoline. */
9838 mach = gen_rtx_REG (SImode, MACH_REG);
9839 r1 = gen_rtx_REG (SImode, R1_REG);
9841 /* Since such a call function may use all call-clobbered
9842 registers, we force a mode switch earlier, so that we don't
9843 run out of registers when adjusting fpscr for the call. */
9844 emit_insn (gen_force_mode_for_call ());
9847 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9848 operands[1] = force_reg (SImode, operands[1]);
9850 /* We don't need a return trampoline, since the callee will
9851 return directly to the upper caller. */
9852 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9854 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
9855 cookie_rtx = GEN_INT (cookie);
9858 emit_move_insn (mach, func);
9859 emit_move_insn (r1, cookie_rtx);
9861 emit_call_insn (gen_sibcall_value_compact (operands[0], operands[1],
9862 operands[2], mach));
9865 else if (TARGET_SHCOMPACT && flag_pic
9866 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9867 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9869 rtx reg = gen_reg_rtx (Pmode);
9871 emit_insn (gen_symGOT2reg (reg, XEXP (operands[1], 0)));
9872 XEXP (operands[1], 0) = reg;
9874 if (flag_pic && TARGET_SH2
9875 && MEM_P (operands[1])
9876 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9877 /* The PLT needs the PIC register, but the epilogue would have
9878 to restore it, so we can only use PC-relative PIC calls for
9879 static functions. */
9880 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9882 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
9883 XEXP (operands[1], 0),
9888 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
9890 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
9894 (define_insn "call_value_pop_compact"
9895 [(set (match_operand 0 "" "=rf")
9896 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9897 (match_operand 2 "" "")))
9898 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9899 (match_operand 4 "immediate_operand" "n")))
9900 (match_operand 3 "immediate_operand" "n")
9901 (use (reg:SI R0_REG))
9902 (use (reg:SI R1_REG))
9903 (use (reg:PSI FPSCR_REG))
9904 (clobber (reg:SI PR_REG))]
9905 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9907 [(set_attr "type" "call")
9908 (set (attr "fp_mode")
9909 (if_then_else (eq_attr "fpu_single" "yes")
9910 (const_string "single") (const_string "double")))
9911 (set_attr "needs_delay_slot" "yes")])
9913 (define_insn "call_value_pop_compact_rettramp"
9914 [(set (match_operand 0 "" "=rf")
9915 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9916 (match_operand 2 "" "")))
9917 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9918 (match_operand 4 "immediate_operand" "n")))
9919 (match_operand 3 "immediate_operand" "n")
9920 (use (reg:SI R0_REG))
9921 (use (reg:SI R1_REG))
9922 (use (reg:PSI FPSCR_REG))
9923 (clobber (reg:SI R10_REG))
9924 (clobber (reg:SI PR_REG))]
9925 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9927 [(set_attr "type" "call")
9928 (set (attr "fp_mode")
9929 (if_then_else (eq_attr "fpu_single" "yes")
9930 (const_string "single") (const_string "double")))
9931 (set_attr "needs_delay_slot" "yes")])
9933 (define_expand "call_value_pop"
9934 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
9935 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9936 (match_operand 2 "" "")))
9937 (match_operand 3 "" "")
9938 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9939 (match_operand 4 "" "")))])]
9947 gcc_assert (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]));
9948 cookie_rtx = operands[3];
9949 cookie = INTVAL (cookie_rtx);
9950 func = XEXP (operands[1], 0);
9954 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9956 rtx reg = gen_reg_rtx (Pmode);
9958 emit_insn (gen_symGOTPLT2reg (reg, func));
9962 func = legitimize_pic_address (func, Pmode, 0);
9965 r0 = gen_rtx_REG (SImode, R0_REG);
9966 r1 = gen_rtx_REG (SImode, R1_REG);
9968 /* Since such a call function may use all call-clobbered
9969 registers, we force a mode switch earlier, so that we don't
9970 run out of registers when adjusting fpscr for the call. */
9971 emit_insn (gen_force_mode_for_call ());
9973 operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
9975 operands[1] = force_reg (SImode, operands[1]);
9977 emit_move_insn (r0, func);
9978 emit_move_insn (r1, cookie_rtx);
9980 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9981 emit_call_insn (gen_call_value_pop_compact_rettramp
9982 (operands[0], operands[1], operands[2],
9983 operands[3], operands[4]));
9985 emit_call_insn (gen_call_value_pop_compact
9986 (operands[0], operands[1], operands[2],
9987 operands[3], operands[4]));
9992 (define_expand "sibcall_epilogue"
9996 sh_expand_epilogue (true);
9997 if (TARGET_SHCOMPACT)
10001 /* If epilogue clobbers r0, preserve it in macl. */
10002 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10003 if ((set = single_set (insn))
10004 && REG_P (SET_DEST (set))
10005 && REGNO (SET_DEST (set)) == R0_REG)
10007 rtx r0 = gen_rtx_REG (SImode, R0_REG);
10008 rtx tmp = gen_rtx_REG (SImode, MACL_REG);
10010 /* We can't tell at this point whether the sibcall is a
10011 sibcall_compact and, if it is, whether it uses r0 or
10012 mach as operand 2, so let the instructions that
10013 preserve r0 be optimized away if r0 turns out to be
10015 emit_insn_before (gen_rtx_SET (SImode, tmp, r0), insn);
10016 emit_move_insn (r0, tmp);
10023 (define_insn "indirect_jump_compact"
10025 (match_operand:SI 0 "arith_reg_operand" "r"))]
10028 [(set_attr "needs_delay_slot" "yes")
10029 (set_attr "type" "jump_ind")])
10031 (define_expand "indirect_jump"
10033 (match_operand 0 "register_operand" ""))]
10036 if (GET_MODE (operands[0]) != Pmode)
10037 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
10040 ;; The use of operand 1 / 2 helps us distinguish case table jumps
10041 ;; which can be present in structured code from indirect jumps which can not
10042 ;; be present in structured code. This allows -fprofile-arcs to work.
10044 ;; For SH1 processors.
10045 (define_insn "casesi_jump_1"
10047 (match_operand:SI 0 "register_operand" "r"))
10048 (use (label_ref (match_operand 1 "" "")))]
10051 [(set_attr "needs_delay_slot" "yes")
10052 (set_attr "type" "jump_ind")])
10054 ;; For all later processors.
10055 (define_insn "casesi_jump_2"
10056 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
10057 (label_ref (match_operand 1 "" ""))))
10058 (use (label_ref (match_operand 2 "" "")))]
10060 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
10062 [(set_attr "needs_delay_slot" "yes")
10063 (set_attr "type" "jump_ind")])
10065 (define_insn "casesi_jump_media"
10066 [(set (pc) (match_operand 0 "target_reg_operand" "b"))
10067 (use (label_ref (match_operand 1 "" "")))]
10070 [(set_attr "type" "jump_media")])
10072 ;; Call subroutine returning any type.
10073 ;; ??? This probably doesn't work.
10074 (define_expand "untyped_call"
10075 [(parallel [(call (match_operand 0 "" "")
10077 (match_operand 1 "" "")
10078 (match_operand 2 "" "")])]
10079 "(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA"
10081 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
10083 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
10085 rtx set = XVECEXP (operands[2], 0, i);
10086 emit_move_insn (SET_DEST (set), SET_SRC (set));
10089 /* The optimizer does not know that the call sets the function value
10090 registers we stored in the result block. We avoid problems by
10091 claiming that all hard registers are used and clobbered at this
10093 emit_insn (gen_blockage ());
10098 ;; ------------------------------------------------------------------------
10100 ;; ------------------------------------------------------------------------
10102 (define_insn "dect"
10103 [(set (reg:SI T_REG)
10104 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
10105 (set (match_operand:SI 0 "arith_reg_dest" "=r")
10106 (plus:SI (match_dup 1) (const_int -1)))]
10109 [(set_attr "type" "arith")])
10116 ;; Load address of a label. This is only generated by the casesi expand,
10117 ;; and by machine_dependent_reorg (fixing up fp moves).
10118 ;; This must use unspec, because this only works for labels that are
10120 (define_insn "mova"
10121 [(set (reg:SI R0_REG)
10122 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
10125 [(set_attr "in_delay_slot" "no")
10126 (set_attr "type" "arith")])
10128 ;; machine_dependent_reorg will make this a `mova'.
10129 (define_insn "mova_const"
10130 [(set (reg:SI R0_REG)
10131 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
10134 [(set_attr "in_delay_slot" "no")
10135 (set_attr "type" "arith")])
10137 (define_expand "GOTaddr2picreg"
10138 [(set (reg:SI R0_REG)
10139 (unspec:SI [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
10141 (set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
10142 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
10145 if (TARGET_VXWORKS_RTP)
10147 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
10148 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
10149 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
10153 operands[0] = gen_rtx_REG (Pmode, PIC_REG);
10154 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
10156 if (TARGET_SHMEDIA)
10158 rtx tr = gen_rtx_REG (Pmode, TR0_REG);
10159 rtx pic = operands[0];
10160 rtx lab = PATTERN (gen_call_site ());
10163 equiv = operands[1];
10164 operands[1] = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[1], lab),
10165 UNSPEC_PCREL_SYMOFF);
10166 operands[1] = gen_rtx_CONST (Pmode, operands[1]);
10168 if (Pmode == SImode)
10170 emit_insn (gen_movsi_const (pic, operands[1]));
10171 emit_insn (gen_ptrel_si (tr, pic, copy_rtx (lab)));
10175 emit_insn (gen_movdi_const (pic, operands[1]));
10176 emit_insn (gen_ptrel_di (tr, pic, copy_rtx (lab)));
10179 insn = emit_move_insn (operands[0], tr);
10181 set_unique_reg_note (insn, REG_EQUAL, equiv);
10187 ;; A helper for GOTaddr2picreg to finish up the initialization of the
10189 (define_expand "vxworks_picreg"
10190 [(set (reg:SI PIC_REG)
10191 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
10192 (set (reg:SI R0_REG)
10193 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
10194 (set (reg:SI PIC_REG)
10195 (mem:SI (reg:SI PIC_REG)))
10196 (set (reg:SI PIC_REG)
10197 (mem:SI (plus:SI (reg:SI PIC_REG)
10198 (reg:SI R0_REG))))]
10199 "TARGET_VXWORKS_RTP")
10201 (define_insn "*ptb"
10202 [(set (match_operand 0 "target_reg_operand" "=b")
10203 (const (unspec [(match_operand 1 "" "Csy")]
10204 UNSPEC_DATALABEL)))]
10205 "TARGET_SHMEDIA && flag_pic
10206 && satisfies_constraint_Csy (operands[1])"
10207 "ptb/u datalabel %1, %0"
10208 [(set_attr "type" "ptabs_media")
10209 (set_attr "length" "*")])
10211 (define_insn "ptrel_si"
10212 [(set (match_operand:SI 0 "target_reg_operand" "=b")
10213 (plus:SI (match_operand:SI 1 "register_operand" "r")
10215 (match_operand:SI 2 "" "")]
10217 "%O2: ptrel/u %1, %0"
10218 [(set_attr "type" "ptabs_media")])
10220 (define_insn "ptrel_di"
10221 [(set (match_operand:DI 0 "target_reg_operand" "=b")
10222 (plus:DI (match_operand:DI 1 "register_operand" "r")
10224 (match_operand:DI 2 "" "")]
10226 "%O2: ptrel/u %1, %0"
10227 [(set_attr "type" "ptabs_media")])
10229 (define_expand "builtin_setjmp_receiver"
10230 [(match_operand 0 "" "")]
10233 emit_insn (gen_GOTaddr2picreg ());
10237 (define_expand "call_site"
10238 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
10241 static HOST_WIDE_INT i = 0;
10242 operands[0] = GEN_INT (i);
10246 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
10247 ;; in symGOT_load expand.
10248 (define_insn_and_split "chk_guard_add"
10249 [(set (match_operand:SI 0 "register_operand" "=&r")
10250 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
10255 "TARGET_SH1 && reload_completed"
10256 [(set (match_dup 0) (reg:SI PIC_REG))
10257 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
10259 [(set_attr "type" "arith")])
10261 (define_expand "sym_label2reg"
10262 [(set (match_operand:SI 0 "" "")
10263 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
10264 (const (plus:SI (match_operand:SI 2 "" "")
10269 (define_expand "symGOT_load"
10270 [(set (match_dup 2) (match_operand 1 "" ""))
10271 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
10272 (set (match_operand 0 "" "") (mem (match_dup 3)))]
10277 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10278 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10280 if (TARGET_SHMEDIA)
10282 rtx reg = operands[2];
10284 if (Pmode == DImode)
10287 emit_insn (gen_movdi_const_32bit (reg, operands[1]));
10289 emit_insn (gen_movdi_const_16bit (reg, operands[1]));
10294 emit_insn (gen_movsi_const (reg, operands[1]));
10296 emit_insn (gen_movsi_const_16bit (reg, operands[1]));
10300 emit_move_insn (operands[2], operands[1]);
10302 /* When stack protector inserts codes after the result is set to
10303 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
10304 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
10305 when rX is a GOT address for the guard symbol. Ugly but doesn't
10306 matter because this is a rare situation. */
10307 if (!TARGET_SHMEDIA
10308 && flag_stack_protect
10309 && GET_CODE (operands[1]) == CONST
10310 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
10311 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
10312 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
10313 "__stack_chk_guard") == 0)
10314 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
10316 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
10317 gen_rtx_REG (Pmode, PIC_REG)));
10319 /* N.B. This is not constant for a GOTPLT relocation. */
10320 mem = gen_rtx_MEM (Pmode, operands[3]);
10321 MEM_NOTRAP_P (mem) = 1;
10322 /* ??? Should we have a special alias set for the GOT? */
10323 emit_move_insn (operands[0], mem);
10328 (define_expand "sym2GOT"
10329 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
10333 (define_expand "symGOT2reg"
10334 [(match_operand 0 "" "") (match_operand 1 "" "")]
10339 gotsym = gen_sym2GOT (operands[1]);
10340 PUT_MODE (gotsym, Pmode);
10341 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
10343 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
10348 (define_expand "symGOTPLT2reg"
10349 [(match_operand 0 "" "") (match_operand 1 "" "")]
10352 rtx pltsym = gen_rtx_CONST (Pmode,
10353 gen_rtx_UNSPEC (Pmode,
10354 gen_rtvec (1, operands[1]),
10356 emit_insn (gen_symGOT_load (operands[0], pltsym));
10360 (define_expand "sym2GOTOFF"
10361 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
10365 (define_expand "symGOTOFF2reg"
10366 [(match_operand 0 "" "") (match_operand 1 "" "")]
10369 rtx gotoffsym, insn;
10370 rtx t = (!can_create_pseudo_p ()
10372 : gen_reg_rtx (GET_MODE (operands[0])));
10374 gotoffsym = gen_sym2GOTOFF (operands[1]);
10375 PUT_MODE (gotoffsym, Pmode);
10376 emit_move_insn (t, gotoffsym);
10377 insn = emit_move_insn (operands[0],
10378 gen_rtx_PLUS (Pmode, t,
10379 gen_rtx_REG (Pmode, PIC_REG)));
10381 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
10386 (define_expand "symPLT_label2reg"
10387 [(set (match_operand:SI 0 "" "")
10390 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
10391 (const:SI (plus:SI (match_operand:SI 2 "" "")
10392 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
10393 ;; Even though the PIC register is not really used by the call
10394 ;; sequence in which this is expanded, the PLT code assumes the PIC
10395 ;; register is set, so we must not skip its initialization. Since
10396 ;; we only use this expand as part of calling sequences, and never
10397 ;; to take the address of a function, this is the best point to
10398 ;; insert the (use). Using the PLT to take the address of a
10399 ;; function would be wrong, not only because the PLT entry could
10400 ;; then be called from a function that doesn't initialize the PIC
10401 ;; register to the proper GOT, but also because pointers to the
10402 ;; same function might not compare equal, should they be set by
10403 ;; different shared libraries.
10404 (use (reg:SI PIC_REG))]
10408 (define_expand "sym2PIC"
10409 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
10413 ;; -------------------------------------------------------------------------
10414 ;; TLS code generation.
10416 ;; FIXME: The multi-insn asm blocks should be converted to use
10417 ;; define_insn_and_split.
10418 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
10419 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
10422 (define_insn "tls_global_dynamic"
10423 [(set (match_operand:SI 0 "register_operand" "=&z")
10424 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10427 (use (reg:PSI FPSCR_REG))
10428 (use (reg:SI PIC_REG))
10429 (clobber (reg:SI PR_REG))
10430 (clobber (scratch:SI))]
10433 return "mov.l 1f,r4" "\n"
10435 " mov.l 2f,r1" "\n"
10442 "1: .long %a1@TLSGD" "\n"
10443 "2: .long __tls_get_addr@PLT" "\n"
10446 [(set_attr "type" "tls_load")
10447 (set_attr "length" "26")])
10449 (define_insn "tls_local_dynamic"
10450 [(set (match_operand:SI 0 "register_operand" "=&z")
10451 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10454 (use (reg:PSI FPSCR_REG))
10455 (use (reg:SI PIC_REG))
10456 (clobber (reg:SI PR_REG))
10457 (clobber (scratch:SI))]
10460 return "mov.l 1f,r4" "\n"
10462 " mov.l 2f,r1" "\n"
10469 "1: .long %a1@TLSLDM" "\n"
10470 "2: .long __tls_get_addr@PLT" "\n"
10473 [(set_attr "type" "tls_load")
10474 (set_attr "length" "26")])
10476 (define_expand "sym2DTPOFF"
10477 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
10481 (define_expand "symDTPOFF2reg"
10482 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
10486 rtx t = (!can_create_pseudo_p ()
10488 : gen_reg_rtx (GET_MODE (operands[0])));
10490 dtpoffsym = gen_sym2DTPOFF (operands[1]);
10491 PUT_MODE (dtpoffsym, Pmode);
10492 emit_move_insn (t, dtpoffsym);
10493 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
10497 (define_expand "sym2GOTTPOFF"
10498 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
10502 (define_insn "tls_initial_exec"
10503 [(set (match_operand:SI 0 "register_operand" "=&r")
10504 (unspec:SI [(match_operand:SI 1 "" "")]
10506 (use (reg:SI GBR_REG))
10507 (use (reg:SI PIC_REG))
10508 (clobber (reg:SI R0_REG))]
10511 return "mov.l 1f,r0" "\n"
10513 " mov.l @(r0,r12),r0" "\n"
10517 "1: .long %a1" "\n"
10520 [(set_attr "type" "tls_load")
10521 (set_attr "length" "16")])
10523 (define_expand "sym2TPOFF"
10524 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
10528 (define_expand "symTPOFF2reg"
10529 [(match_operand 0 "" "") (match_operand 1 "" "")]
10534 tpoffsym = gen_sym2TPOFF (operands[1]);
10535 PUT_MODE (tpoffsym, Pmode);
10536 emit_move_insn (operands[0], tpoffsym);
10540 ;;------------------------------------------------------------------------------
10541 ;; Thread pointer getter and setter.
10543 ;; On SH the thread pointer is kept in the GBR.
10544 ;; These patterns are usually expanded from the respective built-in functions.
10545 (define_expand "get_thread_pointersi"
10546 [(set (match_operand:SI 0 "register_operand") (reg:SI GBR_REG))]
10549 ;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses.
10550 (define_insn "store_gbr"
10551 [(set (match_operand:SI 0 "register_operand" "=r") (reg:SI GBR_REG))]
10554 [(set_attr "type" "tls_load")])
10556 (define_expand "set_thread_pointersi"
10557 [(set (reg:SI GBR_REG)
10558 (unspec_volatile:SI [(match_operand:SI 0 "register_operand")]
10562 (define_insn "load_gbr"
10563 [(set (reg:SI GBR_REG)
10564 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
10568 [(set_attr "type" "move")])
10570 ;;------------------------------------------------------------------------------
10571 ;; Thread pointer relative memory loads and stores.
10573 ;; On SH there are GBR displacement address modes which can be utilized to
10574 ;; access memory behind the thread pointer.
10575 ;; Since we do not allow using GBR for general purpose memory accesses, these
10576 ;; GBR addressing modes are formed by the combine pass.
10577 ;; This could be done with fewer patterns than below by using a mem predicate
10578 ;; for the GBR mem, but then reload would try to reload addresses with a
10579 ;; zero displacement for some strange reason.
10581 (define_insn "*mov<mode>_gbr_load"
10582 [(set (match_operand:QIHISI 0 "register_operand" "=z")
10583 (mem:QIHISI (plus:SI (reg:SI GBR_REG)
10584 (match_operand:QIHISI 1 "gbr_displacement"))))]
10586 "mov.<bwl> @(%O1,gbr),%0"
10587 [(set_attr "type" "load")])
10589 (define_insn "*mov<mode>_gbr_load"
10590 [(set (match_operand:QIHISI 0 "register_operand" "=z")
10591 (mem:QIHISI (reg:SI GBR_REG)))]
10593 "mov.<bwl> @(0,gbr),%0"
10594 [(set_attr "type" "load")])
10596 (define_insn "*mov<mode>_gbr_load"
10597 [(set (match_operand:SI 0 "register_operand" "=z")
10599 (mem:QIHI (plus:SI (reg:SI GBR_REG)
10600 (match_operand:QIHI 1 "gbr_displacement")))))]
10602 "mov.<bw> @(%O1,gbr),%0"
10603 [(set_attr "type" "load")])
10605 (define_insn "*mov<mode>_gbr_load"
10606 [(set (match_operand:SI 0 "register_operand" "=z")
10607 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))]
10609 "mov.<bw> @(0,gbr),%0"
10610 [(set_attr "type" "load")])
10612 (define_insn "*mov<mode>_gbr_store"
10613 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG)
10614 (match_operand:QIHISI 0 "gbr_displacement")))
10615 (match_operand:QIHISI 1 "register_operand" "z"))]
10617 "mov.<bwl> %1,@(%O0,gbr)"
10618 [(set_attr "type" "store")])
10620 (define_insn "*mov<mode>_gbr_store"
10621 [(set (mem:QIHISI (reg:SI GBR_REG))
10622 (match_operand:QIHISI 0 "register_operand" "z"))]
10624 "mov.<bwl> %0,@(0,gbr)"
10625 [(set_attr "type" "store")])
10627 ;; DImode memory accesses have to be split in two SImode accesses.
10628 ;; Split them before reload, so that it gets a better chance to figure out
10629 ;; how to deal with the R0 restriction for the individual SImode accesses.
10630 ;; Do not match this insn during or after reload because it can't be split
10632 (define_insn_and_split "*movdi_gbr_load"
10633 [(set (match_operand:DI 0 "register_operand")
10634 (match_operand:DI 1 "gbr_address_mem"))]
10635 "TARGET_SH1 && can_create_pseudo_p ()"
10638 [(set (match_dup 3) (match_dup 5))
10639 (set (match_dup 4) (match_dup 6))]
10641 /* Swap low/high part load order on little endian, so that the result reg
10642 of the second load can be used better. */
10643 int off = TARGET_LITTLE_ENDIAN ? 1 : 0;
10644 operands[3 + off] = gen_lowpart (SImode, operands[0]);
10645 operands[5 + off] = gen_lowpart (SImode, operands[1]);
10646 operands[4 - off] = gen_highpart (SImode, operands[0]);
10647 operands[6 - off] = gen_highpart (SImode, operands[1]);
10650 (define_insn_and_split "*movdi_gbr_store"
10651 [(set (match_operand:DI 0 "gbr_address_mem")
10652 (match_operand:DI 1 "register_operand"))]
10653 "TARGET_SH1 && can_create_pseudo_p ()"
10656 [(set (match_dup 3) (match_dup 5))
10657 (set (match_dup 4) (match_dup 6))]
10659 /* Swap low/high part store order on big endian, so that stores of function
10660 call results can save a reg copy. */
10661 int off = TARGET_LITTLE_ENDIAN ? 0 : 1;
10662 operands[3 + off] = gen_lowpart (SImode, operands[0]);
10663 operands[5 + off] = gen_lowpart (SImode, operands[1]);
10664 operands[4 - off] = gen_highpart (SImode, operands[0]);
10665 operands[6 - off] = gen_highpart (SImode, operands[1]);
10668 ;; Sometimes memory accesses do not get combined with the store_gbr insn,
10669 ;; in particular when the displacements are in the range of the regular move
10670 ;; insns. Thus, in the first split pass after the combine pass we search
10671 ;; for missed opportunities and try to fix them up ourselves.
10672 ;; If an equivalent GBR address can be determined the load / store is split
10673 ;; into one of the GBR load / store patterns.
10674 ;; All of that must happen before reload (GBR address modes use R0 as the
10675 ;; other operand) and there's no point of doing it if the GBR is not
10676 ;; referenced in a function at all.
10678 [(set (match_operand:QIHISIDI 0 "register_operand")
10679 (match_operand:QIHISIDI 1 "memory_operand"))]
10680 "TARGET_SH1 && !reload_in_progress && !reload_completed
10681 && df_regs_ever_live_p (GBR_REG)"
10682 [(set (match_dup 0) (match_dup 1))]
10684 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10685 if (gbr_mem != NULL_RTX)
10686 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10692 [(set (match_operand:SI 0 "register_operand")
10693 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))]
10694 "TARGET_SH1 && !reload_in_progress && !reload_completed
10695 && df_regs_ever_live_p (GBR_REG)"
10696 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
10698 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10699 if (gbr_mem != NULL_RTX)
10700 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10705 ;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads.
10706 ;; Split those so that a GBR load can be used.
10708 [(set (match_operand:SI 0 "register_operand")
10709 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))]
10710 "TARGET_SH2A && !reload_in_progress && !reload_completed
10711 && df_regs_ever_live_p (GBR_REG)"
10712 [(set (match_dup 2) (match_dup 1))
10713 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
10715 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10716 if (gbr_mem != NULL_RTX)
10718 operands[2] = gen_reg_rtx (GET_MODE (operands[1]));
10719 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10726 [(set (match_operand:QIHISIDI 0 "memory_operand")
10727 (match_operand:QIHISIDI 1 "register_operand"))]
10728 "TARGET_SH1 && !reload_in_progress && !reload_completed
10729 && df_regs_ever_live_p (GBR_REG)"
10730 [(set (match_dup 0) (match_dup 1))]
10732 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]);
10733 if (gbr_mem != NULL_RTX)
10734 operands[0] = replace_equiv_address (operands[0], gbr_mem);
10739 ;;------------------------------------------------------------------------------
10740 ;; case instruction for switch statements.
10742 ;; operand 0 is index
10743 ;; operand 1 is the minimum bound
10744 ;; operand 2 is the maximum bound - minimum bound + 1
10745 ;; operand 3 is CODE_LABEL for the table;
10746 ;; operand 4 is the CODE_LABEL to go to if index out of range.
10747 (define_expand "casesi"
10748 [(match_operand:SI 0 "arith_reg_operand" "")
10749 (match_operand:SI 1 "arith_reg_operand" "")
10750 (match_operand:SI 2 "arith_reg_operand" "")
10751 (match_operand 3 "" "") (match_operand 4 "" "")]
10754 rtx reg = gen_reg_rtx (SImode);
10755 rtx reg2 = gen_reg_rtx (SImode);
10756 if (TARGET_SHMEDIA)
10758 rtx reg = gen_reg_rtx (DImode);
10759 rtx reg2 = gen_reg_rtx (DImode);
10760 rtx reg3 = gen_reg_rtx (Pmode);
10761 rtx reg4 = gen_reg_rtx (Pmode);
10762 rtx reg5 = gen_reg_rtx (Pmode);
10765 operands[0] = convert_modes (DImode, SImode, operands[0], 0);
10766 operands[1] = convert_modes (DImode, SImode, operands[1], 0);
10767 operands[2] = convert_modes (DImode, SImode, operands[2], 1);
10769 test = gen_rtx_GT (VOIDmode, operands[1], operands[0]);
10770 emit_jump_insn (gen_cbranchdi4 (test, operands[1], operands[0],
10772 emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1]));
10773 test = gen_rtx_GTU (VOIDmode, reg, operands[2]);
10774 emit_jump_insn (gen_cbranchdi4 (test, reg, operands[2], operands[4]));
10775 emit_insn (gen_casesi_shift_media (reg2, reg, operands[3]));
10776 emit_move_insn (reg3, gen_datalabel_ref (gen_rtx_LABEL_REF
10777 (Pmode, operands[3])));
10778 /* Messy: can we subreg to clean this up? */
10779 if (Pmode == DImode)
10780 load = gen_casesi_load_media (reg4, reg3, reg2, operands[3]);
10782 load = gen_casesi_load_media (reg4,
10783 gen_rtx_SUBREG (DImode, reg3, 0),
10784 reg2, operands[3]);
10785 PUT_MODE (SET_SRC (load), Pmode);
10787 /* ??? The following add could be eliminated if we used ptrel. */
10788 emit_move_insn (reg5, gen_rtx_PLUS (Pmode, reg3, reg4));
10789 emit_jump_insn (gen_casesi_jump_media (reg5, operands[3]));
10793 operands[1] = copy_to_mode_reg (SImode, operands[1]);
10794 operands[2] = copy_to_mode_reg (SImode, operands[2]);
10795 /* If optimizing, casesi_worker depends on the mode of the instruction
10796 before label it 'uses' - operands[3]. */
10797 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
10799 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
10801 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
10803 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
10804 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
10805 operands[3], but to lab. We will fix this up in
10806 machine_dependent_reorg. */
10811 (define_expand "casesi_0"
10812 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
10813 (set (match_dup 4) (minus:SI (match_dup 4)
10814 (match_operand:SI 1 "arith_operand" "")))
10815 (set (reg:SI T_REG)
10816 (gtu:SI (match_dup 4)
10817 (match_operand:SI 2 "arith_reg_operand" "")))
10819 (if_then_else (ne (reg:SI T_REG)
10821 (label_ref (match_operand 3 "" ""))
10826 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
10827 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
10828 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
10829 (define_insn "casesi_worker_0"
10830 [(set (match_operand:SI 0 "register_operand" "=r,r")
10831 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
10832 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10833 (clobber (match_scratch:SI 3 "=X,1"))
10834 (clobber (match_scratch:SI 4 "=&z,z"))]
10839 [(set (match_operand:SI 0 "register_operand" "")
10840 (unspec:SI [(match_operand:SI 1 "register_operand" "")
10841 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10842 (clobber (match_scratch:SI 3 ""))
10843 (clobber (match_scratch:SI 4 ""))]
10844 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
10845 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
10846 (parallel [(set (match_dup 0)
10847 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
10848 (label_ref (match_dup 2))] UNSPEC_CASESI))
10849 (clobber (match_dup 3))])
10850 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
10852 if (GET_CODE (operands[2]) == CODE_LABEL)
10853 LABEL_NUSES (operands[2])++;
10857 [(set (match_operand:SI 0 "register_operand" "")
10858 (unspec:SI [(match_operand:SI 1 "register_operand" "")
10859 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10860 (clobber (match_scratch:SI 3 ""))
10861 (clobber (match_scratch:SI 4 ""))]
10862 "TARGET_SH2 && reload_completed"
10863 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
10864 (parallel [(set (match_dup 0)
10865 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
10866 (label_ref (match_dup 2))] UNSPEC_CASESI))
10867 (clobber (match_dup 3))])]
10869 if (GET_CODE (operands[2]) == CODE_LABEL)
10870 LABEL_NUSES (operands[2])++;
10873 (define_insn "casesi_worker_1"
10874 [(set (match_operand:SI 0 "register_operand" "=r,r")
10875 (unspec:SI [(reg:SI R0_REG)
10876 (match_operand:SI 1 "register_operand" "0,r")
10877 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10878 (clobber (match_scratch:SI 3 "=X,1"))]
10881 rtx diff_vec = PATTERN (NEXT_INSN (operands[2]));
10883 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10885 switch (GET_MODE (diff_vec))
10888 return "shll2 %1" "\n"
10889 " mov.l @(r0,%1),%0";
10891 return "add %1,%1" "\n"
10892 " mov.w @(r0,%1),%0";
10894 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10895 return "mov.b @(r0,%1),%0" "\n"
10898 return "mov.b @(r0,%1),%0";
10901 gcc_unreachable ();
10904 [(set_attr "length" "4")])
10906 (define_insn "casesi_worker_2"
10907 [(set (match_operand:SI 0 "register_operand" "=r,r")
10908 (unspec:SI [(reg:SI R0_REG)
10909 (match_operand:SI 1 "register_operand" "0,r")
10910 (label_ref (match_operand 2 "" ""))
10911 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
10912 (clobber (match_operand:SI 4 "" "=X,1"))]
10913 "TARGET_SH2 && reload_completed && flag_pic"
10915 rtx diff_vec = PATTERN (NEXT_INSN (operands[2]));
10916 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10918 switch (GET_MODE (diff_vec))
10921 return "shll2 %1" "\n"
10923 " mova %O3,r0" "\n"
10924 " mov.l @(r0,%1),%0";
10926 return "add %1,%1" "\n"
10928 " mova %O3,r0" "\n"
10929 " mov.w @(r0,%1),%0";
10931 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10932 return "add r0,%1" "\n"
10933 " mova %O3,r0" "\n"
10934 " mov.b @(r0,%1),%0" "\n"
10937 return "add r0,%1" "\n"
10938 " mova %O3,r0" "\n"
10939 " mov.b @(r0,%1),%0";
10941 gcc_unreachable ();
10944 [(set_attr "length" "8")])
10946 (define_insn "casesi_shift_media"
10947 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10948 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
10949 (unspec:DI [(label_ref:DI (match_operand 2 "" ""))]
10953 rtx diff_vec = PATTERN (NEXT_INSN (operands[2]));
10955 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10957 switch (GET_MODE (diff_vec))
10960 return "shlli %1, 2, %0";
10962 return "shlli %1, 1, %0";
10964 if (rtx_equal_p (operands[0], operands[1]))
10966 return "add %1, r63, %0";
10968 gcc_unreachable ();
10971 [(set_attr "type" "arith_media")])
10973 (define_insn "casesi_load_media"
10974 [(set (match_operand 0 "any_arith_reg_dest" "=r")
10975 (mem (unspec [(match_operand:DI 1 "arith_reg_operand" "r")
10976 (match_operand:DI 2 "arith_reg_operand" "r")
10977 (label_ref:DI (match_operand 3 "" ""))] UNSPEC_CASESI)))]
10980 rtx diff_vec = PATTERN (NEXT_INSN (operands[3]));
10982 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10984 switch (GET_MODE (diff_vec))
10987 return "ldx.l %1, %2, %0";
10990 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10991 return "ldx.uw %1, %2, %0";
10993 return "ldx.w %1, %2, %0";
10995 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10996 return "ldx.ub %1, %2, %0";
10997 return "ldx.b %1, %2, %0";
10999 gcc_unreachable ();
11002 [(set_attr "type" "load_media")])
11004 (define_expand "simple_return"
11006 "sh_can_use_simple_return_p ()")
11008 (define_expand "return"
11010 "reload_completed && epilogue_completed"
11012 if (TARGET_SHMEDIA)
11014 emit_jump_insn (gen_return_media ());
11018 if (TARGET_SHCOMPACT
11019 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))
11021 emit_jump_insn (gen_shcompact_return_tramp ());
11026 (define_insn "*<code>_i"
11028 "TARGET_SH1 && ! (TARGET_SHCOMPACT
11029 && (crtl->args.info.call_cookie
11030 & CALL_COOKIE_RET_TRAMP (1)))
11031 && reload_completed
11032 && ! sh_cfun_trap_exit_p ()"
11034 if (TARGET_SH2A && (dbr_sequence_length () == 0)
11035 && !current_function_interrupt)
11040 [(set_attr "type" "return")
11041 (set_attr "needs_delay_slot" "yes")])
11043 ;; trapa has no delay slot.
11044 (define_insn "*return_trapa"
11046 "TARGET_SH1 && !TARGET_SHCOMPACT
11047 && reload_completed"
11049 [(set_attr "type" "return")])
11051 (define_expand "shcompact_return_tramp"
11054 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
11056 rtx reg = gen_rtx_REG (Pmode, R0_REG);
11058 function_symbol (reg, "__GCC_shcompact_return_trampoline", SFUNC_STATIC);
11059 emit_jump_insn (gen_shcompact_return_tramp_i ());
11063 (define_insn "shcompact_return_tramp_i"
11064 [(parallel [(return) (use (reg:SI R0_REG))])]
11066 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
11068 [(set_attr "type" "jump_ind")
11069 (set_attr "needs_delay_slot" "yes")])
11071 (define_insn "return_media_i"
11072 [(parallel [(return) (use (match_operand 0 "target_reg_operand" "k"))])]
11073 "TARGET_SHMEDIA && reload_completed"
11075 [(set_attr "type" "jump_media")])
11077 (define_insn "return_media_rte"
11079 "TARGET_SHMEDIA && reload_completed && current_function_interrupt"
11081 [(set_attr "type" "jump_media")])
11083 (define_expand "return_media"
11085 "TARGET_SHMEDIA && reload_completed"
11087 int tr_regno = sh_media_register_for_return ();
11090 if (current_function_interrupt)
11092 emit_jump_insn (gen_return_media_rte ());
11097 rtx r18 = gen_rtx_REG (Pmode, PR_MEDIA_REG);
11099 gcc_assert (call_really_used_regs[TR0_REG] && !fixed_regs[TR0_REG]);
11100 tr_regno = TR0_REG;
11101 tr = gen_rtx_REG (Pmode, tr_regno);
11102 emit_move_insn (tr, r18);
11105 tr = gen_rtx_REG (Pmode, tr_regno);
11107 emit_jump_insn (gen_return_media_i (tr));
11111 (define_insn "shcompact_preserve_incoming_args"
11112 [(set (match_operand:SI 0 "register_operand" "+r")
11113 (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
11116 [(set_attr "length" "0")])
11118 (define_insn "shcompact_incoming_args"
11119 [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
11120 (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
11121 (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
11122 (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
11123 (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
11124 (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
11125 (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
11126 (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
11127 (set (mem:BLK (reg:SI MACL_REG))
11128 (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
11129 (use (reg:SI R0_REG))
11130 (clobber (reg:SI R0_REG))
11131 (clobber (reg:SI MACL_REG))
11132 (clobber (reg:SI MACH_REG))
11133 (clobber (reg:SI PR_REG))]
11136 [(set_attr "needs_delay_slot" "yes")])
11138 (define_insn "shmedia_save_restore_regs_compact"
11139 [(set (reg:SI SP_REG)
11140 (plus:SI (reg:SI SP_REG)
11141 (match_operand:SI 0 "immediate_operand" "i")))
11142 (use (reg:SI R0_REG))
11143 (clobber (reg:SI PR_REG))]
11145 && (INTVAL (operands[0]) == SHMEDIA_REGS_STACK_ADJUST ()
11146 || INTVAL (operands[0]) == - SHMEDIA_REGS_STACK_ADJUST ())"
11148 [(set_attr "needs_delay_slot" "yes")])
11150 (define_expand "prologue"
11154 sh_expand_prologue ();
11158 (define_expand "epilogue"
11162 sh_expand_epilogue (false);
11164 || (TARGET_SHCOMPACT
11165 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))))
11167 emit_jump_insn (gen_return ());
11172 (define_expand "eh_return"
11173 [(use (match_operand 0 "register_operand" ""))]
11176 rtx ra = operands[0];
11178 if (TARGET_SHMEDIA64)
11179 emit_insn (gen_eh_set_ra_di (ra));
11181 emit_insn (gen_eh_set_ra_si (ra));
11186 ;; Clobber the return address on the stack. We can't expand this
11187 ;; until we know where it will be put in the stack frame.
11189 (define_insn "eh_set_ra_si"
11190 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
11192 (clobber (match_scratch:SI 1 "=&r"))]
11193 "! TARGET_SHMEDIA64"
11196 (define_insn "eh_set_ra_di"
11197 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
11199 (clobber (match_scratch:DI 1 "=&r"))]
11204 [(unspec_volatile [(match_operand 0 "register_operand" "")]
11206 (clobber (match_scratch 1 ""))]
11210 sh_set_return_address (operands[0], operands[1]);
11214 (define_insn "blockage"
11215 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
11218 [(set_attr "length" "0")])
11220 ;; Define movml instructions for SH2A target. Currently they are
11221 ;; used to push and pop all banked registers only.
11223 (define_insn "movml_push_banked"
11224 [(set (match_operand:SI 0 "register_operand" "=r")
11225 (plus (match_dup 0) (const_int -32)))
11226 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
11227 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
11228 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
11229 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
11230 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
11231 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
11232 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
11233 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
11234 "TARGET_SH2A && REGNO (operands[0]) == 15"
11236 [(set_attr "in_delay_slot" "no")])
11238 (define_insn "movml_pop_banked"
11239 [(set (match_operand:SI 0 "register_operand" "=r")
11240 (plus (match_dup 0) (const_int 32)))
11241 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
11242 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
11243 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
11244 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
11245 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
11246 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
11247 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
11248 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
11249 "TARGET_SH2A && REGNO (operands[0]) == 15"
11251 [(set_attr "in_delay_slot" "no")])
11253 ;; ------------------------------------------------------------------------
11254 ;; Scc instructions
11255 ;; ------------------------------------------------------------------------
11257 (define_insn "movt"
11258 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11259 (match_operand:SI 1 "t_reg_operand"))]
11262 [(set_attr "type" "arith")])
11264 (define_insn "movrt"
11265 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11266 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11269 [(set_attr "type" "arith")])
11271 (define_expand "cstore4_media"
11272 [(set (match_operand:SI 0 "register_operand" "=r")
11273 (match_operator:SI 1 "sh_float_comparison_operator"
11274 [(match_operand 2 "logical_operand" "")
11275 (match_operand 3 "cmp_operand" "")]))]
11278 enum machine_mode mode = GET_MODE (operands[2]);
11279 enum rtx_code code = GET_CODE (operands[1]);
11281 if (mode == VOIDmode)
11282 mode = GET_MODE (operands[3]);
11283 if (operands[2] == const0_rtx)
11285 if (code == EQ || code == NE)
11286 operands[2] = operands[3], operands[3] = const0_rtx;
11289 operands[2] = force_reg (mode, operands[2]);
11290 if (operands[3] != const0_rtx)
11291 operands[3] = force_reg (mode, operands[3]);
11297 swap = invert = !FLOAT_MODE_P (mode);
11302 swap = FLOAT_MODE_P (mode), invert = !swap;
11307 swap = true, invert = false;
11314 swap = invert = false;
11318 swap = invert = true;
11322 gcc_unreachable ();
11327 rtx tem = operands[2];
11328 operands[2] = operands[3];
11330 code = swap_condition (code);
11335 rtx tem = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
11336 code = reverse_condition (code);
11337 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11338 emit_insn (gen_cstore4_media (tem, operands[1],
11339 operands[2], operands[3]));
11342 operands[3] = const0_rtx;
11345 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11348 (define_expand "cstoresi4"
11349 [(set (match_operand:SI 0 "register_operand" "=r")
11350 (match_operator:SI 1 "comparison_operator"
11351 [(match_operand:SI 2 "cmpsi_operand" "")
11352 (match_operand:SI 3 "arith_operand" "")]))]
11353 "TARGET_SH1 || TARGET_SHMEDIA"
11355 if (TARGET_SHMEDIA)
11357 emit_insn (gen_cstore4_media (operands[0], operands[1],
11358 operands[2], operands[3]));
11362 if (sh_expand_t_scc (operands))
11365 if (! currently_expanding_to_rtl)
11368 sh_emit_compare_and_set (operands, SImode);
11372 (define_expand "cstoredi4"
11373 [(set (match_operand:SI 0 "register_operand" "=r")
11374 (match_operator:SI 1 "comparison_operator"
11375 [(match_operand:DI 2 "arith_operand" "")
11376 (match_operand:DI 3 "arith_operand" "")]))]
11377 "TARGET_SH2 || TARGET_SHMEDIA"
11379 if (TARGET_SHMEDIA)
11381 emit_insn (gen_cstore4_media (operands[0], operands[1],
11382 operands[2], operands[3]));
11386 if (sh_expand_t_scc (operands))
11389 if (! currently_expanding_to_rtl)
11392 sh_emit_compare_and_set (operands, DImode);
11396 ;; Move the complement of the T reg to a reg.
11397 ;; On SH2A the movrt insn can be used.
11398 ;; On anything else than SH2A this has to be done with multiple instructions.
11399 ;; One obvious way would be:
11404 ;; However, this puts pressure on r0 in most cases and thus the following is
11410 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
11411 ;; becomes a one instruction operation. Moreover, care must be taken that
11412 ;; the insn can still be combined with inverted compare and branch code
11413 ;; around it. On the other hand, if a function returns the complement of
11414 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
11415 ;; lead to better code.
11416 (define_expand "movnegt"
11417 [(set (match_operand:SI 0 "arith_reg_dest" "")
11418 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11422 emit_insn (gen_movrt (operands[0], operands[1]));
11425 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
11426 emit_insn (gen_movrt_negc (operands[0], operands[1], val));
11431 (define_insn "movrt_negc"
11432 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11433 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))
11434 (set (reg:SI T_REG) (const_int 1))
11435 (use (match_operand:SI 2 "arith_reg_operand" "r"))]
11438 [(set_attr "type" "arith")])
11440 ;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
11441 ;; pattern can be used by the combine pass. Using a scratch reg for the
11442 ;; -1 constant results in slightly better register allocations compared to
11443 ;; generating a pseudo reg before reload.
11444 (define_insn_and_split "*movrt_negc"
11445 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11446 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))
11447 (clobber (match_scratch:SI 2 "=r"))
11448 (clobber (reg:SI T_REG))]
11449 "TARGET_SH1 && ! TARGET_SH2A"
11451 "&& reload_completed"
11452 [(set (match_dup 2) (const_int -1))
11454 [(set (match_dup 0) (xor:SI (match_dup 1) (const_int 1)))
11455 (set (reg:SI T_REG) (const_int 1))
11456 (use (match_dup 2))])])
11458 ;; Store the negated T bit in a reg using r0 and xor. This one doesn't
11459 ;; clobber the T bit, which is useful when storing the T bit and the
11460 ;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
11461 ;; Usually we don't want this insn to be matched, except for cases where the
11462 ;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
11463 (define_insn_and_split "movrt_xor"
11464 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
11465 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11466 (use (reg:SI T_REG))]
11467 "TARGET_SH1 && !TARGET_SH2A"
11469 "&& reload_completed"
11470 [(set (match_dup 0) (reg:SI T_REG))
11471 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
11473 ;; Store the T bit and the negated T bit in two regs in parallel. There is
11474 ;; no real insn to do that, but specifying this pattern will give combine
11475 ;; some opportunities.
11476 (define_insn_and_split "*movt_movrt"
11477 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
11478 (match_operand:SI 1 "negt_reg_operand"))
11479 (set (match_operand:SI 2 "arith_reg_dest")
11480 (match_operand:SI 3 "t_reg_operand"))])]
11486 rtx i = TARGET_SH2A
11487 ? gen_movrt (operands[0], get_t_reg_rtx ())
11488 : gen_movrt_xor (operands[0], get_t_reg_rtx ());
11491 emit_insn (gen_movt (operands[2], get_t_reg_rtx ()));
11495 (define_insn_and_split "*movt_movrt"
11496 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
11497 (match_operand:SI 1 "t_reg_operand"))
11498 (set (match_operand:SI 2 "arith_reg_dest")
11499 (match_operand:SI 3 "negt_reg_operand"))])]
11503 [(parallel [(set (match_dup 2) (match_dup 3))
11504 (set (match_dup 0) (match_dup 1))])])
11506 ;; Use negc to store the T bit in a MSB of a reg in the following way:
11507 ;; T = 1: 0x80000000 -> reg
11508 ;; T = 0: 0x7FFFFFFF -> reg
11509 ;; This works because 0 - 0x80000000 = 0x80000000.
11511 ;; This insn must not match again after it has been split into the constant
11512 ;; load and negc. This is accomplished by the special negc insn that
11513 ;; has a use on the operand.
11514 (define_insn_and_split "*mov_t_msb_neg"
11515 [(set (match_operand:SI 0 "arith_reg_dest")
11516 (minus:SI (const_int -2147483648) ;; 0x80000000
11517 (match_operand 1 "t_reg_operand")))
11518 (clobber (reg:SI T_REG))]
11521 "&& can_create_pseudo_p ()"
11522 [(set (match_dup 2) (const_int -2147483648))
11523 (parallel [(set (match_dup 0) (minus:SI (neg:SI (match_dup 2))
11525 (clobber (reg:SI T_REG))
11526 (use (match_dup 2))])]
11528 operands[2] = gen_reg_rtx (SImode);
11531 (define_insn "*mov_t_msb_neg_negc"
11532 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11533 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
11534 (match_operand:SI 2 "t_reg_operand")))
11535 (clobber (reg:SI T_REG))
11536 (use (match_dup 1))]
11539 [(set_attr "type" "arith")])
11541 ;; These are essentially the same as above, but with the inverted T bit.
11542 ;; Combine recognizes the split patterns, but does not take them sometimes
11543 ;; if the T_REG clobber is specified. Instead it tries to split out the
11544 ;; T bit negation. Since these splits are supposed to be taken only by
11545 ;; combine, it will see the T_REG clobber of the *mov_t_msb_neg insn, so this
11548 [(set (match_operand:SI 0 "arith_reg_dest")
11549 (plus:SI (match_operand 1 "negt_reg_operand")
11550 (const_int 2147483647)))] ;; 0x7fffffff
11551 "TARGET_SH1 && can_create_pseudo_p ()"
11552 [(parallel [(set (match_dup 0)
11553 (minus:SI (const_int -2147483648) (reg:SI T_REG)))
11554 (clobber (reg:SI T_REG))])])
11557 [(set (match_operand:SI 0 "arith_reg_dest")
11558 (if_then_else:SI (match_operand 1 "t_reg_operand")
11559 (const_int 2147483647) ;; 0x7fffffff
11560 (const_int -2147483648)))] ;; 0x80000000
11561 "TARGET_SH1 && can_create_pseudo_p ()"
11562 [(parallel [(set (match_dup 0)
11563 (minus:SI (const_int -2147483648) (reg:SI T_REG)))
11564 (clobber (reg:SI T_REG))])])
11566 ;; The *negnegt pattern helps the combine pass to figure out how to fold
11567 ;; an explicit double T bit negation.
11568 (define_insn_and_split "*negnegt"
11569 [(set (reg:SI T_REG)
11570 (eq:SI (match_operand 0 "negt_reg_operand" "") (const_int 0)))]
11576 ;; Store T bit as all zeros or ones in a reg.
11577 (define_insn "mov_neg_si_t"
11578 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11579 (neg:SI (match_operand 1 "t_reg_operand" "")))]
11582 [(set_attr "type" "arith")])
11584 ;; Store negated T bit as all zeros or ones in a reg.
11585 ;; Use the following sequence:
11586 ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
11587 ;; not Rn,Rn ! Rn = 0 - Rn
11589 [(set (match_operand:SI 0 "arith_reg_dest" "")
11590 (neg:SI (match_operand 1 "negt_reg_operand" "")))]
11592 [(set (match_dup 0) (neg:SI (reg:SI T_REG)))
11593 (set (match_dup 0) (not:SI (match_dup 0)))])
11595 ;; The *movtt pattern eliminates redundant T bit to T bit moves / tests.
11596 (define_insn_and_split "*movtt"
11597 [(set (reg:SI T_REG)
11598 (eq:SI (match_operand 0 "t_reg_operand" "") (const_int 1)))]
11604 ;; Invert the T bit.
11605 ;; On SH2A we can use the nott insn. On anything else this must be done with
11606 ;; multiple insns like:
11609 ;; This requires an additional pseudo. The SH specific sh_treg_combine RTL
11610 ;; pass will look for this insn. Disallow using it if pseudos can't be
11612 (define_insn_and_split "nott"
11613 [(set (reg:SI T_REG)
11614 (xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))]
11615 "TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())"
11617 gcc_assert (TARGET_SH2A);
11620 "! TARGET_SH2A && can_create_pseudo_p ()"
11621 [(set (match_dup 0) (reg:SI T_REG))
11622 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
11624 operands[0] = gen_reg_rtx (SImode);
11627 ;; Store T bit as MSB in a reg.
11628 ;; T = 0: 0x00000000 -> reg
11629 ;; T = 1: 0x80000000 -> reg
11630 (define_insn_and_split "*movt_msb"
11631 [(set (match_operand:SI 0 "arith_reg_dest")
11632 (mult:SI (match_operand:SI 1 "t_reg_operand")
11633 (const_int -2147483648))) ;; 0xffffffff80000000
11634 (clobber (reg:SI T_REG))]
11638 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))])
11640 ;; Store inverted T bit as MSB in a reg.
11641 ;; T = 0: 0x80000000 -> reg
11642 ;; T = 1: 0x00000000 -> reg
11643 ;; On SH2A we can get away without clobbering the T_REG using the movrt insn.
11644 ;; On non SH2A we resort to the following sequence:
11648 ;; The T bit value will be modified during the sequence, but the rotcr insn
11649 ;; will restore its original value.
11650 (define_insn_and_split "*negt_msb"
11651 [(set (match_operand:SI 0 "arith_reg_dest")
11652 (match_operand:SI 1 "negt_reg_shl31_operand"))]
11655 "&& can_create_pseudo_p ()"
11658 rtx tmp = gen_reg_rtx (SImode);
11662 emit_insn (gen_movrt (tmp, get_t_reg_rtx ()));
11663 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx));
11667 emit_move_insn (tmp, get_t_reg_rtx ());
11668 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx));
11669 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ()));
11674 ;; The *cset_zero patterns convert optimizations such as
11675 ;; "if (test) x = 0;"
11677 ;; "x &= -(test == 0);"
11678 ;; back to conditional branch sequences if zero-displacement branches
11680 ;; FIXME: These patterns can be removed when conditional execution patterns
11681 ;; are implemented, since ifcvt will not perform these optimizations if
11682 ;; conditional execution is supported.
11683 (define_insn "*cset_zero"
11684 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11685 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand")
11687 (match_operand:SI 2 "arith_reg_operand" "0")))]
11688 "TARGET_SH1 && TARGET_ZDCBRANCH"
11690 return "bf 0f" "\n"
11694 [(set_attr "type" "arith") ;; poor approximation
11695 (set_attr "length" "4")])
11697 (define_insn "*cset_zero"
11698 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11699 (if_then_else:SI (match_operand:SI 1 "cbranch_treg_value")
11700 (match_operand:SI 2 "arith_reg_operand" "0")
11702 "TARGET_SH1 && TARGET_ZDCBRANCH"
11704 int tval = sh_eval_treg_value (operands[1]);
11706 return "bt 0f" "\n"
11709 else if (tval == false)
11710 return "bf 0f" "\n"
11714 gcc_unreachable ();
11716 [(set_attr "type" "arith") ;; poor approximation
11717 (set_attr "length" "4")])
11719 (define_expand "cstoresf4"
11720 [(set (match_operand:SI 0 "register_operand" "=r")
11721 (match_operator:SI 1 "sh_float_comparison_operator"
11722 [(match_operand:SF 2 "arith_operand" "")
11723 (match_operand:SF 3 "arith_operand" "")]))]
11724 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
11726 if (TARGET_SHMEDIA)
11728 emit_insn (gen_cstore4_media (operands[0], operands[1],
11729 operands[2], operands[3]));
11733 if (! currently_expanding_to_rtl)
11736 sh_emit_compare_and_set (operands, SFmode);
11740 (define_expand "cstoredf4"
11741 [(set (match_operand:SI 0 "register_operand" "=r")
11742 (match_operator:SI 1 "sh_float_comparison_operator"
11743 [(match_operand:DF 2 "arith_operand" "")
11744 (match_operand:DF 3 "arith_operand" "")]))]
11745 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11747 if (TARGET_SHMEDIA)
11749 emit_insn (gen_cstore4_media (operands[0], operands[1],
11750 operands[2], operands[3]));
11754 if (! currently_expanding_to_rtl)
11757 sh_emit_compare_and_set (operands, DFmode);
11761 ;; -------------------------------------------------------------------------
11762 ;; Instructions to cope with inline literal tables
11763 ;; -------------------------------------------------------------------------
11765 ;; 2 byte integer in line
11766 (define_insn "consttable_2"
11767 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11768 (match_operand 1 "" "")]
11772 if (operands[1] != const0_rtx)
11773 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
11776 [(set_attr "length" "2")
11777 (set_attr "in_delay_slot" "no")])
11779 ;; 4 byte integer in line
11780 (define_insn "consttable_4"
11781 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11782 (match_operand 1 "" "")]
11786 if (operands[1] != const0_rtx)
11788 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
11789 mark_symbol_refs_as_used (operands[0]);
11793 [(set_attr "length" "4")
11794 (set_attr "in_delay_slot" "no")])
11796 ;; 8 byte integer in line
11797 (define_insn "consttable_8"
11798 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11799 (match_operand 1 "" "")]
11803 if (operands[1] != const0_rtx)
11804 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
11807 [(set_attr "length" "8")
11808 (set_attr "in_delay_slot" "no")])
11810 ;; 4 byte floating point
11811 (define_insn "consttable_sf"
11812 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
11813 (match_operand 1 "" "")]
11817 if (operands[1] != const0_rtx)
11820 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
11821 assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
11825 [(set_attr "length" "4")
11826 (set_attr "in_delay_slot" "no")])
11828 ;; 8 byte floating point
11829 (define_insn "consttable_df"
11830 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
11831 (match_operand 1 "" "")]
11835 if (operands[1] != const0_rtx)
11838 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
11839 assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
11843 [(set_attr "length" "8")
11844 (set_attr "in_delay_slot" "no")])
11846 ;; Alignment is needed for some constant tables; it may also be added for
11847 ;; Instructions at the start of loops, or after unconditional branches.
11848 ;; ??? We would get more accurate lengths if we did instruction
11849 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
11850 ;; here is too conservative.
11852 ;; align to a two byte boundary
11853 (define_expand "align_2"
11854 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
11858 ;; Align to a four byte boundary.
11859 ;; align_4 and align_log are instructions for the starts of loops, or
11860 ;; after unconditional branches, which may take up extra room.
11861 (define_expand "align_4"
11862 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
11866 ;; Align to a cache line boundary.
11867 (define_insn "align_log"
11868 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
11871 [(set_attr "length" "0")
11872 (set_attr "in_delay_slot" "no")])
11874 ;; Emitted at the end of the literal table, used to emit the
11875 ;; 32bit branch labels if needed.
11876 (define_insn "consttable_end"
11877 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
11880 return output_jump_label_table ();
11882 [(set_attr "in_delay_slot" "no")])
11884 ;; Emitted at the end of the window in the literal table.
11885 (define_insn "consttable_window_end"
11886 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
11889 [(set_attr "length" "0")
11890 (set_attr "in_delay_slot" "no")])
11892 ;; -------------------------------------------------------------------------
11893 ;; Minimum / maximum operations.
11894 ;; -------------------------------------------------------------------------
11896 ;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin
11897 ;; and smax standard name patterns are defined, they will be used during
11898 ;; initial expansion and combine will then be able to form the actual min-max
11900 ;; The clips.b and clips.w set the SR.CS bit if the value in the register is
11901 ;; clipped, but there is currently no way of making use of this information.
11902 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
11903 (define_expand "<code>si3"
11904 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
11905 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
11906 (match_operand 2 "const_int_operand")))
11907 (clobber (reg:SI T_REG))])]
11910 /* Force the comparison value into a register, because greater-than
11911 comparisons can work only on registers. Combine will be able to pick up
11912 the constant value from the REG_EQUAL note when trying to form a min-max
11914 operands[2] = force_reg (SImode, operands[2]);
11918 ;; smax (smin (...))
11920 ;; smin (smax (...))
11921 (define_insn_and_split "*clips"
11922 [(set (match_operand:SI 0 "arith_reg_dest")
11923 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand")
11924 (match_operand 2 "clips_max_const_int"))
11925 (match_operand 3 "clips_min_const_int")))]
11929 [(set (match_dup 0)
11930 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))])
11932 (define_insn "*clips"
11933 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11934 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0")
11935 (match_operand 2 "clips_min_const_int"))
11936 (match_operand 3 "clips_max_const_int")))]
11939 if (INTVAL (operands[3]) == 127)
11940 return "clips.b %0";
11941 else if (INTVAL (operands[3]) == 32767)
11942 return "clips.w %0";
11944 gcc_unreachable ();
11946 [(set_attr "type" "arith")])
11948 ;; If the expanded smin or smax patterns were not combined, split them into
11949 ;; a compare and branch sequence, because there are no real smin or smax
11951 (define_insn_and_split "*<code>si3"
11952 [(set (match_operand:SI 0 "arith_reg_dest")
11953 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
11954 (match_operand:SI 2 "arith_reg_or_0_or_1_operand")))
11955 (clobber (reg:SI T_REG))]
11956 "TARGET_SH2A && can_create_pseudo_p ()"
11961 rtx skip_label = gen_label_rtx ();
11962 emit_move_insn (operands[0], operands[1]);
11964 rtx cmp_val = operands[2];
11965 if (satisfies_constraint_M (cmp_val))
11966 cmp_val = const0_rtx;
11968 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val));
11969 emit_jump_insn (<CODE> == SMIN
11970 ? gen_branch_false (skip_label)
11971 : gen_branch_true (skip_label));
11973 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2]));
11977 ;; The SH2A clipu.b and clipu.w insns can be used to implement a min function
11978 ;; with a register and a constant.
11979 ;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is
11980 ;; clipped, but there is currently no way of making use of this information.
11981 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
11982 (define_expand "uminsi3"
11983 [(set (match_operand:SI 0 "arith_reg_dest")
11984 (umin:SI (match_operand:SI 1 "arith_reg_operand")
11985 (match_operand 2 "const_int_operand")))]
11988 if (INTVAL (operands[2]) == 1)
11990 emit_insn (gen_clipu_one (operands[0], operands[1]));
11993 else if (! clipu_max_const_int (operands[2], VOIDmode))
11997 (define_insn "*clipu"
11998 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11999 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0")
12000 (match_operand 2 "clipu_max_const_int")))]
12003 if (INTVAL (operands[2]) == 255)
12004 return "clipu.b %0";
12005 else if (INTVAL (operands[2]) == 65535)
12006 return "clipu.w %0";
12008 gcc_unreachable ();
12010 [(set_attr "type" "arith")])
12012 (define_insn_and_split "clipu_one"
12013 [(set (match_operand:SI 0 "arith_reg_dest")
12014 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)))
12015 (clobber (reg:SI T_REG))]
12018 "&& can_create_pseudo_p ()"
12021 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx));
12022 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
12026 ;; -------------------------------------------------------------------------
12028 ;; -------------------------------------------------------------------------
12030 ;; String/block move insn.
12032 (define_expand "movmemsi"
12033 [(parallel [(set (mem:BLK (match_operand:BLK 0))
12034 (mem:BLK (match_operand:BLK 1)))
12035 (use (match_operand:SI 2 "nonmemory_operand"))
12036 (use (match_operand:SI 3 "immediate_operand"))
12037 (clobber (reg:SI PR_REG))
12038 (clobber (reg:SI R4_REG))
12039 (clobber (reg:SI R5_REG))
12040 (clobber (reg:SI R0_REG))])]
12041 "TARGET_SH1 && ! TARGET_SH5"
12043 if (expand_block_move (operands))
12049 (define_insn "block_move_real"
12050 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12051 (mem:BLK (reg:SI R5_REG)))
12052 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12053 (clobber (reg:SI PR_REG))
12054 (clobber (reg:SI R0_REG))])]
12055 "TARGET_SH1 && ! TARGET_HARD_SH4"
12057 [(set_attr "type" "sfunc")
12058 (set_attr "needs_delay_slot" "yes")])
12060 (define_insn "block_lump_real"
12061 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12062 (mem:BLK (reg:SI R5_REG)))
12063 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12064 (use (reg:SI R6_REG))
12065 (clobber (reg:SI PR_REG))
12066 (clobber (reg:SI T_REG))
12067 (clobber (reg:SI R4_REG))
12068 (clobber (reg:SI R5_REG))
12069 (clobber (reg:SI R6_REG))
12070 (clobber (reg:SI R0_REG))])]
12071 "TARGET_SH1 && ! TARGET_HARD_SH4"
12073 [(set_attr "type" "sfunc")
12074 (set_attr "needs_delay_slot" "yes")])
12076 (define_insn "block_move_real_i4"
12077 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12078 (mem:BLK (reg:SI R5_REG)))
12079 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12080 (clobber (reg:SI PR_REG))
12081 (clobber (reg:SI R0_REG))
12082 (clobber (reg:SI R1_REG))
12083 (clobber (reg:SI R2_REG))])]
12086 [(set_attr "type" "sfunc")
12087 (set_attr "needs_delay_slot" "yes")])
12089 (define_insn "block_lump_real_i4"
12090 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12091 (mem:BLK (reg:SI R5_REG)))
12092 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12093 (use (reg:SI R6_REG))
12094 (clobber (reg:SI PR_REG))
12095 (clobber (reg:SI T_REG))
12096 (clobber (reg:SI R4_REG))
12097 (clobber (reg:SI R5_REG))
12098 (clobber (reg:SI R6_REG))
12099 (clobber (reg:SI R0_REG))
12100 (clobber (reg:SI R1_REG))
12101 (clobber (reg:SI R2_REG))
12102 (clobber (reg:SI R3_REG))])]
12105 [(set_attr "type" "sfunc")
12106 (set_attr "needs_delay_slot" "yes")])
12108 ;; byte compare pattern
12110 ;; !((temp & 0xF000) && (temp & 0x0F00) && (temp & 0x00F0) && (temp & 0x000F))
12111 (define_insn "cmpstr_t"
12112 [(set (reg:SI T_REG)
12117 (xor:SI (match_operand:SI 0 "arith_reg_operand" "r")
12118 (match_operand:SI 1 "arith_reg_operand" "r"))
12119 (const_int 8) (const_int 0))
12120 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12121 (const_int 8) (const_int 8)))
12122 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12123 (const_int 8) (const_int 16)))
12124 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12125 (const_int 8) (const_int 24)))
12129 [(set_attr "type" "mt_group")])
12131 (define_expand "cmpstrsi"
12132 [(set (match_operand:SI 0 "register_operand")
12133 (compare:SI (match_operand:BLK 1 "memory_operand")
12134 (match_operand:BLK 2 "memory_operand")))
12135 (use (match_operand 3 "immediate_operand"))]
12136 "TARGET_SH1 && optimize"
12138 if (! optimize_insn_for_size_p () && sh_expand_cmpstr (operands))
12144 (define_expand "cmpstrnsi"
12145 [(set (match_operand:SI 0 "register_operand")
12146 (compare:SI (match_operand:BLK 1 "memory_operand")
12147 (match_operand:BLK 2 "memory_operand")))
12148 (use (match_operand:SI 3 "immediate_operand"))
12149 (use (match_operand:SI 4 "immediate_operand"))]
12150 "TARGET_SH1 && optimize"
12152 if (! optimize_insn_for_size_p () && sh_expand_cmpnstr (operands))
12158 (define_expand "strlensi"
12159 [(set (match_operand:SI 0 "register_operand")
12160 (unspec:SI [(match_operand:BLK 1 "memory_operand")
12161 (match_operand:SI 2 "immediate_operand")
12162 (match_operand:SI 3 "immediate_operand")]
12163 UNSPEC_BUILTIN_STRLEN))]
12164 "TARGET_SH1 && optimize"
12166 if (! optimize_insn_for_size_p () && sh_expand_strlen (operands))
12172 (define_expand "setmemqi"
12173 [(parallel [(set (match_operand:BLK 0 "memory_operand")
12174 (match_operand 2 "const_int_operand"))
12175 (use (match_operand:QI 1 "const_int_operand"))
12176 (use (match_operand:QI 3 "const_int_operand"))])]
12177 "TARGET_SH1 && optimize"
12179 if (optimize_insn_for_size_p ())
12182 sh_expand_setmem (operands);
12187 ;; -------------------------------------------------------------------------
12188 ;; Floating point instructions.
12189 ;; -------------------------------------------------------------------------
12191 ;; ??? All patterns should have a type attribute.
12193 (define_expand "movpsi"
12194 [(set (match_operand:PSI 0 "register_operand" "")
12195 (match_operand:PSI 1 "general_movsrc_operand" ""))]
12196 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12199 ;; The c / m alternative is a fake to guide reload to load directly into
12200 ;; fpscr, since reload doesn't know how to use post-increment.
12201 ;; TARGET_LEGITIMATE_ADDRESS_P guards about bogus addresses before reload,
12202 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
12203 ;; predicate after reload.
12204 ;; The mac_gp type for r/!c might look a bit odd, but it actually schedules
12205 ;; like a mac -> gpr move.
12206 (define_insn "fpu_switch"
12207 [(set (match_operand:PSI 0 "general_movdst_operand" "=c,c,r,c,c,r,m,r,<")
12208 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c,c"))]
12210 && (! reload_completed
12211 || true_regnum (operands[0]) != FPSCR_REG
12212 || !MEM_P (operands[1])
12213 || GET_CODE (XEXP (operands[1], 0)) != PLUS)"
12215 ! precision stays the same
12224 [(set_attr "length" "0,2,2,4,2,2,2,2,2")
12225 (set_attr "type" "nil,mem_fpscr,load,mem_fpscr,gp_fpscr,move,store,
12229 [(set (reg:PSI FPSCR_REG)
12230 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
12231 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && peep2_reg_dead_p (1, operands[0])"
12234 rtx fpscr, mem, new_insn;
12236 fpscr = SET_DEST (PATTERN (curr_insn));
12237 mem = SET_SRC (PATTERN (curr_insn));
12238 mem = replace_equiv_address (mem, gen_rtx_POST_INC (Pmode, operands[0]));
12240 new_insn = emit_insn (gen_fpu_switch (fpscr, mem));
12241 add_reg_note (new_insn, REG_INC, operands[0]);
12246 [(set (reg:PSI FPSCR_REG)
12247 (mem:PSI (match_operand:SI 0 "register_operand" "")))]
12248 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
12249 && (flag_peephole2 ? epilogue_completed : reload_completed)"
12252 rtx fpscr, mem, new_insn;
12254 fpscr = SET_DEST (PATTERN (curr_insn));
12255 mem = SET_SRC (PATTERN (curr_insn));
12256 mem = replace_equiv_address (mem, gen_rtx_POST_INC (Pmode, operands[0]));
12258 new_insn = emit_insn (gen_fpu_switch (fpscr, mem));
12259 add_reg_note (new_insn, REG_INC, operands[0]);
12261 if (!find_regno_note (curr_insn, REG_DEAD, true_regnum (operands[0])))
12262 emit_insn (gen_addsi3 (operands[0], operands[0], GEN_INT (-4)));
12266 ;; ??? This uses the fp unit, but has no type indicating that.
12267 ;; If we did that, this would either give a bogus latency or introduce
12268 ;; a bogus FIFO constraint.
12269 ;; Since this insn is currently only used for prologues/epilogues,
12270 ;; it is probably best to claim no function unit, which matches the
12271 ;; current setting.
12272 (define_insn "toggle_sz"
12273 [(set (reg:PSI FPSCR_REG)
12274 (xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
12275 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12277 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
12279 ;; Toggle FPU precision PR mode.
12281 (define_insn "toggle_pr"
12282 [(set (reg:PSI FPSCR_REG)
12283 (xor:PSI (reg:PSI FPSCR_REG) (const_int 524288)))]
12286 [(set_attr "type" "fpscr_toggle")])
12288 (define_expand "addsf3"
12289 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12290 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand")
12291 (match_operand:SF 2 "fp_arith_reg_operand")))]
12292 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12296 expand_sf_binop (&gen_addsf3_i, operands);
12301 (define_insn "*addsf3_media"
12302 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12303 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12304 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12305 "TARGET_SHMEDIA_FPU"
12306 "fadd.s %1, %2, %0"
12307 [(set_attr "type" "fparith_media")])
12309 (define_insn_and_split "unary_sf_op"
12310 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12315 (parallel [(not:BI (match_operand 3 "const_int_operand" "n"))]))
12316 (match_operator:SF 2 "unary_float_operator"
12317 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12318 (parallel [(match_operand 4
12319 "const_int_operand" "n")]))]))
12320 (parallel [(not:BI (match_dup 3)) (match_dup 3)])))]
12321 "TARGET_SHMEDIA_FPU"
12323 "TARGET_SHMEDIA_FPU && reload_completed"
12324 [(set (match_dup 5) (match_dup 6))]
12326 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12327 rtx op1 = gen_rtx_REG (SFmode,
12328 (true_regnum (operands[1])
12329 + (INTVAL (operands[4]) ^ endian)));
12331 operands[7] = gen_rtx_REG (SFmode,
12332 (true_regnum (operands[0])
12333 + (INTVAL (operands[3]) ^ endian)));
12334 operands[6] = gen_rtx_fmt_e (GET_CODE (operands[2]), SFmode, op1);
12336 [(set_attr "type" "fparith_media")])
12338 (define_insn_and_split "binary_sf_op0"
12339 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12341 (match_operator:SF 3 "binary_float_operator"
12342 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12343 (parallel [(const_int 0)]))
12344 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12345 (parallel [(const_int 0)]))])
12348 (parallel [(const_int 1)]))))]
12349 "TARGET_SHMEDIA_FPU"
12351 "&& reload_completed"
12352 [(set (match_dup 4) (match_dup 5))]
12354 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12355 rtx op1 = gen_rtx_REG (SFmode,
12356 true_regnum (operands[1]) + endian);
12357 rtx op2 = gen_rtx_REG (SFmode,
12358 true_regnum (operands[2]) + endian);
12360 operands[4] = gen_rtx_REG (SFmode,
12361 true_regnum (operands[0]) + endian);
12362 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12364 [(set_attr "type" "fparith_media")])
12366 (define_insn_and_split "binary_sf_op1"
12367 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12371 (parallel [(const_int 0)]))
12372 (match_operator:SF 3 "binary_float_operator"
12373 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12374 (parallel [(const_int 1)]))
12375 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12376 (parallel [(const_int 1)]))])))]
12377 "TARGET_SHMEDIA_FPU"
12379 "&& reload_completed"
12380 [(set (match_dup 4) (match_dup 5))]
12382 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12383 rtx op1 = gen_rtx_REG (SFmode, true_regnum (operands[1]) + (1 ^ endian));
12384 rtx op2 = gen_rtx_REG (SFmode, true_regnum (operands[2]) + (1 ^ endian));
12386 operands[4] = gen_rtx_REG (SFmode, true_regnum (operands[0]) + (1 ^ endian));
12387 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12389 [(set_attr "type" "fparith_media")])
12391 (define_insn "addsf3_i"
12392 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12393 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
12394 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12395 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12398 [(set_attr "type" "fp")
12399 (set_attr "fp_mode" "single")])
12401 (define_expand "subsf3"
12402 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12403 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12404 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12405 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12409 expand_sf_binop (&gen_subsf3_i, operands);
12414 (define_insn "*subsf3_media"
12415 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12416 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12417 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12418 "TARGET_SHMEDIA_FPU"
12419 "fsub.s %1, %2, %0"
12420 [(set_attr "type" "fparith_media")])
12422 (define_insn "subsf3_i"
12423 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12424 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
12425 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12426 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12429 [(set_attr "type" "fp")
12430 (set_attr "fp_mode" "single")])
12432 (define_expand "mulsf3"
12433 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12434 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12435 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12436 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12440 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2],
12441 get_fpscr_rtx ()));
12446 (define_insn "*mulsf3_media"
12447 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12448 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12449 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12450 "TARGET_SHMEDIA_FPU"
12451 "fmul.s %1, %2, %0"
12452 [(set_attr "type" "fparith_media")])
12454 (define_insn "mulsf3_i"
12455 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12456 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
12457 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12458 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12461 [(set_attr "type" "fp")
12462 (set_attr "fp_mode" "single")])
12464 ;; FMA (fused multiply-add) patterns
12465 (define_expand "fmasf4"
12466 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12467 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand")
12468 (match_operand:SF 2 "fp_arith_reg_operand")
12469 (match_operand:SF 3 "fp_arith_reg_operand")))]
12470 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12474 emit_sf_insn (gen_fmasf4_i (operands[0], operands[1], operands[2],
12475 operands[3], get_fpscr_rtx ()));
12480 (define_insn "fmasf4_i"
12481 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12482 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w")
12483 (match_operand:SF 2 "fp_arith_reg_operand" "f")
12484 (match_operand:SF 3 "fp_arith_reg_operand" "0")))
12485 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
12488 [(set_attr "type" "fp")
12489 (set_attr "fp_mode" "single")])
12491 (define_insn "fmasf4_media"
12492 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12493 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12494 (match_operand:SF 2 "fp_arith_reg_operand" "f")
12495 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
12496 "TARGET_SHMEDIA_FPU"
12497 "fmac.s %1, %2, %0"
12498 [(set_attr "type" "fparith_media")])
12500 ;; For some cases such as 'a * b + a' the FMA pattern is not generated by
12501 ;; previous transformations. If FMA is generally allowed, let the combine
12502 ;; pass utilize it.
12503 (define_insn_and_split "*fmasf4"
12504 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12505 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
12506 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
12507 (match_operand:SF 3 "arith_reg_operand" "0")))
12508 (use (match_operand:PSI 4 "fpscr_operand"))]
12509 "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF"
12511 "&& can_create_pseudo_p ()"
12512 [(parallel [(set (match_dup 0)
12513 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3)))
12514 (use (match_dup 4))])]
12516 /* Change 'b * a + a' into 'a * b + a'.
12517 This is better for register allocation. */
12518 if (REGNO (operands[2]) == REGNO (operands[3]))
12520 rtx tmp = operands[1];
12521 operands[1] = operands[2];
12525 [(set_attr "type" "fp")
12526 (set_attr "fp_mode" "single")])
12528 (define_insn "*fmasf4_media"
12529 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12530 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12531 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
12532 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
12533 "TARGET_SHMEDIA_FPU && flag_fp_contract_mode != FP_CONTRACT_OFF"
12534 "fmac.s %1, %2, %0"
12535 [(set_attr "type" "fparith_media")])
12537 (define_expand "divsf3"
12538 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12539 (div:SF (match_operand:SF 1 "fp_arith_reg_operand")
12540 (match_operand:SF 2 "fp_arith_reg_operand")))]
12541 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12545 expand_sf_binop (&gen_divsf3_i, operands);
12550 (define_insn "*divsf3_media"
12551 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12552 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12553 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12554 "TARGET_SHMEDIA_FPU"
12555 "fdiv.s %1, %2, %0"
12556 [(set_attr "type" "fdiv_media")])
12558 (define_insn "divsf3_i"
12559 [(set (match_operand:SF 0 "fp_arith_reg_dest" "=f")
12560 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
12561 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12562 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12565 [(set_attr "type" "fdiv")
12566 (set_attr "fp_mode" "single")])
12568 (define_insn "floatdisf2"
12569 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12570 (float:SF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
12571 "TARGET_SHMEDIA_FPU"
12573 [(set_attr "type" "fpconv_media")])
12575 (define_expand "floatsisf2"
12576 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12577 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
12578 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12580 if (TARGET_SH4 || TARGET_SH2A_SINGLE)
12582 emit_sf_insn (gen_floatsisf2_i4 (operands[0], operands[1],
12583 get_fpscr_rtx ()));
12588 (define_insn "*floatsisf2_media"
12589 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12590 (float:SF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
12591 "TARGET_SHMEDIA_FPU"
12593 [(set_attr "type" "fpconv_media")])
12595 (define_insn "floatsisf2_i4"
12596 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12597 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
12598 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12599 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12601 [(set_attr "type" "fp")
12602 (set_attr "fp_mode" "single")])
12604 (define_insn "*floatsisf2_ie"
12605 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12606 (float:SF (match_operand:SI 1 "fpul_operand" "y")))]
12607 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12609 [(set_attr "type" "fp")])
12611 (define_insn "fix_truncsfdi2"
12612 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
12613 (fix:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12614 "TARGET_SHMEDIA_FPU"
12616 [(set_attr "type" "fpconv_media")])
12618 (define_expand "fix_truncsfsi2"
12619 [(set (match_operand:SI 0 "fpul_operand" "=y")
12620 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12621 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12623 if (TARGET_SH4 || TARGET_SH2A_SINGLE)
12625 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1],
12626 get_fpscr_rtx ()));
12631 (define_insn "*fix_truncsfsi2_media"
12632 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
12633 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12634 "TARGET_SHMEDIA_FPU"
12636 [(set_attr "type" "fpconv_media")])
12638 (define_insn "fix_truncsfsi2_i4"
12639 [(set (match_operand:SI 0 "fpul_operand" "=y")
12640 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12641 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12642 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12644 [(set_attr "type" "ftrc_s")
12645 (set_attr "fp_mode" "single")])
12647 ;; ??? This pattern is used nowhere. fix_truncsfsi2 always expands to
12648 ;; fix_truncsfsi2_i4.
12649 ;; (define_insn "fix_truncsfsi2_i4_2"
12650 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
12651 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
12652 ;; (use (reg:PSI FPSCR_REG))
12653 ;; (clobber (reg:SI FPUL_REG))]
12656 ;; [(set_attr "length" "4")
12657 ;; (set_attr "fp_mode" "single")])
12660 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
12661 ;; (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
12662 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
12663 ;; (clobber (reg:SI FPUL_REG))]
12665 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
12666 ;; (use (match_dup 2))])
12667 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
12669 (define_insn "*fixsfsi"
12670 [(set (match_operand:SI 0 "fpul_operand" "=y")
12671 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12672 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12674 [(set_attr "type" "fp")])
12676 (define_insn "cmpgtsf_t"
12677 [(set (reg:SI T_REG)
12678 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12679 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12680 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12682 [(set_attr "type" "fp_cmp")
12683 (set_attr "fp_mode" "single")])
12685 (define_insn "cmpeqsf_t"
12686 [(set (reg:SI T_REG)
12687 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12688 (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12689 "TARGET_SH2E && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12691 [(set_attr "type" "fp_cmp")
12692 (set_attr "fp_mode" "single")])
12694 (define_insn "ieee_ccmpeqsf_t"
12695 [(set (reg:SI T_REG)
12696 (ior:SI (reg:SI T_REG)
12697 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12698 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
12699 "TARGET_SH2E && TARGET_IEEE && ! (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12701 return output_ieee_ccmpeq (insn, operands);
12703 [(set_attr "length" "4")])
12706 (define_insn "cmpgtsf_t_i4"
12707 [(set (reg:SI T_REG)
12708 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12709 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12710 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12711 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12713 [(set_attr "type" "fp_cmp")
12714 (set_attr "fp_mode" "single")])
12716 (define_insn "cmpeqsf_t_i4"
12717 [(set (reg:SI T_REG)
12718 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12719 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12720 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12721 "(TARGET_SH4 || TARGET_SH2A_SINGLE)"
12723 [(set_attr "type" "fp_cmp")
12724 (set_attr "fp_mode" "single")])
12726 (define_insn "*ieee_ccmpeqsf_t_4"
12727 [(set (reg:SI T_REG)
12728 (ior:SI (reg:SI T_REG)
12729 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12730 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
12731 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12732 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_SINGLE)"
12734 return output_ieee_ccmpeq (insn, operands);
12736 [(set_attr "length" "4")
12737 (set_attr "fp_mode" "single")])
12739 (define_insn "cmpeqsf_media"
12740 [(set (match_operand:SI 0 "register_operand" "=r")
12741 (eq:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12742 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12743 "TARGET_SHMEDIA_FPU"
12744 "fcmpeq.s %1, %2, %0"
12745 [(set_attr "type" "fcmp_media")])
12747 (define_insn "cmpgtsf_media"
12748 [(set (match_operand:SI 0 "register_operand" "=r")
12749 (gt:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12750 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12751 "TARGET_SHMEDIA_FPU"
12752 "fcmpgt.s %1, %2, %0"
12753 [(set_attr "type" "fcmp_media")])
12755 (define_insn "cmpgesf_media"
12756 [(set (match_operand:SI 0 "register_operand" "=r")
12757 (ge:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12758 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12759 "TARGET_SHMEDIA_FPU"
12760 "fcmpge.s %1, %2, %0"
12761 [(set_attr "type" "fcmp_media")])
12763 (define_insn "cmpunsf_media"
12764 [(set (match_operand:SI 0 "register_operand" "=r")
12765 (unordered:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12766 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12767 "TARGET_SHMEDIA_FPU"
12768 "fcmpun.s %1, %2, %0"
12769 [(set_attr "type" "fcmp_media")])
12771 (define_expand "cbranchsf4"
12773 (if_then_else (match_operator 0 "sh_float_comparison_operator"
12774 [(match_operand:SF 1 "arith_operand" "")
12775 (match_operand:SF 2 "arith_operand" "")])
12776 (match_operand 3 "" "")
12778 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12780 if (TARGET_SHMEDIA)
12781 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
12784 sh_emit_compare_and_branch (operands, SFmode);
12788 (define_expand "negsf2"
12789 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12790 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
12791 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12795 expand_sf_unop (&gen_negsf2_i, operands);
12800 (define_insn "*negsf2_media"
12801 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12802 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12803 "TARGET_SHMEDIA_FPU"
12805 [(set_attr "type" "fmove_media")])
12807 (define_insn "negsf2_i"
12808 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12809 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
12810 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12813 [(set_attr "type" "fmove")
12814 (set_attr "fp_mode" "single")])
12816 (define_expand "sqrtsf2"
12817 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12818 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
12819 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
12823 expand_sf_unop (&gen_sqrtsf2_i, operands);
12828 (define_insn "*sqrtsf2_media"
12829 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12830 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12831 "TARGET_SHMEDIA_FPU"
12833 [(set_attr "type" "fdiv_media")])
12835 (define_insn "sqrtsf2_i"
12836 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12837 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
12838 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12841 [(set_attr "type" "fdiv")
12842 (set_attr "fp_mode" "single")])
12844 (define_insn "rsqrtsf2"
12845 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12846 (div:SF (match_operand:SF 1 "immediate_operand" "i")
12847 (sqrt:SF (match_operand:SF 2 "fp_arith_reg_operand" "0"))))
12848 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12849 "TARGET_FPU_ANY && TARGET_FSRRA
12850 && operands[1] == CONST1_RTX (SFmode)"
12852 [(set_attr "type" "fsrra")
12853 (set_attr "fp_mode" "single")])
12855 ;; When the sincos pattern is defined, the builtin functions sin and cos
12856 ;; will be expanded to the sincos pattern and one of the output values will
12858 (define_expand "sincossf3"
12859 [(set (match_operand:SF 0 "nonimmediate_operand")
12860 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA))
12861 (set (match_operand:SF 1 "nonimmediate_operand")
12862 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))]
12863 "TARGET_FPU_ANY && TARGET_FSCA"
12865 rtx scaled = gen_reg_rtx (SFmode);
12866 rtx truncated = gen_reg_rtx (SImode);
12867 rtx fsca = gen_reg_rtx (V2SFmode);
12868 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
12870 emit_sf_insn (gen_mulsf3 (scaled, operands[2], scale_reg));
12871 emit_sf_insn (gen_fix_truncsfsi2 (truncated, scaled));
12872 emit_sf_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf (),
12873 get_fpscr_rtx ()));
12875 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
12876 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0));
12880 (define_insn_and_split "fsca"
12881 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12883 (unspec:SF [(mult:SF
12884 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y"))
12885 (match_operand:SF 2 "fsca_scale_factor" "i"))
12887 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
12889 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12890 "TARGET_FPU_ANY && TARGET_FSCA"
12892 "&& !fpul_operand (operands[1], SImode)"
12895 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it
12896 to a simple reg, otherwise reload will have trouble reloading the
12897 pseudo into fpul. */
12898 rtx x = XEXP (operands[1], 0);
12899 while (x != NULL_RTX && !fpul_operand (x, SImode))
12901 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT);
12905 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode));
12906 emit_insn (gen_fsca (operands[0], x, operands[2], operands[3]));
12909 [(set_attr "type" "fsca")
12910 (set_attr "fp_mode" "single")])
12912 (define_expand "abssf2"
12913 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12914 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
12915 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12919 expand_sf_unop (&gen_abssf2_i, operands);
12924 (define_insn "*abssf2_media"
12925 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12926 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12927 "TARGET_SHMEDIA_FPU"
12929 [(set_attr "type" "fmove_media")])
12931 (define_insn "abssf2_i"
12932 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12933 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
12934 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
12937 [(set_attr "type" "fmove")
12938 (set_attr "fp_mode" "single")])
12940 (define_expand "adddf3"
12941 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12942 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12943 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12944 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12946 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12948 expand_df_binop (&gen_adddf3_i, operands);
12953 (define_insn "*adddf3_media"
12954 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12955 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
12956 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12957 "TARGET_SHMEDIA_FPU"
12958 "fadd.d %1, %2, %0"
12959 [(set_attr "type" "dfparith_media")])
12961 (define_insn "adddf3_i"
12962 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12963 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
12964 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12965 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12966 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12968 [(set_attr "type" "dfp_arith")
12969 (set_attr "fp_mode" "double")])
12971 (define_expand "subdf3"
12972 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12973 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12974 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12975 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12977 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12979 expand_df_binop (&gen_subdf3_i, operands);
12984 (define_insn "*subdf3_media"
12985 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12986 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
12987 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12988 "TARGET_SHMEDIA_FPU"
12989 "fsub.d %1, %2, %0"
12990 [(set_attr "type" "dfparith_media")])
12992 (define_insn "subdf3_i"
12993 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12994 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
12995 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12996 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
12997 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12999 [(set_attr "type" "dfp_arith")
13000 (set_attr "fp_mode" "double")])
13002 (define_expand "muldf3"
13003 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13004 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
13005 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
13006 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13008 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13010 expand_df_binop (&gen_muldf3_i, operands);
13015 (define_insn "*muldf3_media"
13016 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13017 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
13018 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13019 "TARGET_SHMEDIA_FPU"
13020 "fmul.d %1, %2, %0"
13021 [(set_attr "type" "dfmul_media")])
13023 (define_insn "muldf3_i"
13024 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13025 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
13026 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
13027 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
13028 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13030 [(set_attr "type" "dfp_mul")
13031 (set_attr "fp_mode" "double")])
13033 (define_expand "divdf3"
13034 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13035 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
13036 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
13037 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13039 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13041 expand_df_binop (&gen_divdf3_i, operands);
13046 (define_insn "*divdf3_media"
13047 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13048 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
13049 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13050 "TARGET_SHMEDIA_FPU"
13051 "fdiv.d %1, %2, %0"
13052 [(set_attr "type" "dfdiv_media")])
13054 (define_insn "divdf3_i"
13055 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13056 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
13057 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
13058 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
13059 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13061 [(set_attr "type" "dfdiv")
13062 (set_attr "fp_mode" "double")])
13064 (define_insn "floatdidf2"
13065 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13066 (float:DF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
13067 "TARGET_SHMEDIA_FPU"
13069 [(set_attr "type" "dfpconv_media")])
13071 (define_expand "floatsidf2"
13072 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13073 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
13074 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13076 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13078 emit_df_insn (gen_floatsidf2_i (operands[0], operands[1],
13079 get_fpscr_rtx ()));
13084 (define_insn "*floatsidf2_media"
13085 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13086 (float:DF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
13087 "TARGET_SHMEDIA_FPU"
13089 [(set_attr "type" "dfpconv_media")])
13091 (define_insn "floatsidf2_i"
13092 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13093 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
13094 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13095 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13097 [(set_attr "type" "dfp_conv")
13098 (set_attr "fp_mode" "double")])
13100 (define_insn "fix_truncdfdi2"
13101 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
13102 (fix:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13103 "TARGET_SHMEDIA_FPU"
13105 [(set_attr "type" "dfpconv_media")])
13107 (define_expand "fix_truncdfsi2"
13108 [(set (match_operand:SI 0 "fpul_operand" "")
13109 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
13110 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13112 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13114 emit_df_insn (gen_fix_truncdfsi2_i (operands[0], operands[1],
13115 get_fpscr_rtx ()));
13120 (define_insn "*fix_truncdfsi2_media"
13121 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
13122 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13123 "TARGET_SHMEDIA_FPU"
13125 [(set_attr "type" "dfpconv_media")])
13127 (define_insn "fix_truncdfsi2_i"
13128 [(set (match_operand:SI 0 "fpul_operand" "=y")
13129 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13130 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13131 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13133 [(set_attr "type" "dfp_conv")
13134 (set_attr "dfp_comp" "no")
13135 (set_attr "fp_mode" "double")])
13137 ;; ??? This pattern is used nowhere. fix_truncdfsi2 always expands to
13138 ;; fix_truncdfsi2_i.
13139 ;; (define_insn "fix_truncdfsi2_i4"
13140 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
13141 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
13142 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
13143 ;; (clobber (reg:SI FPUL_REG))]
13146 ;; [(set_attr "length" "4")
13147 ;; (set_attr "fp_mode" "double")])
13150 ;; [(set (match_operand:SI 0 "arith_reg_operand" "=r")
13151 ;; (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
13152 ;; (use (match_operand:PSI 2 "fpscr_operand" "c"))
13153 ;; (clobber (reg:SI FPUL_REG))]
13155 ;; [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
13156 ;; (use (match_dup 2))])
13157 ;; (set (match_dup 0) (reg:SI FPUL_REG))])
13159 (define_insn "cmpgtdf_t"
13160 [(set (reg:SI T_REG)
13161 (gt:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13162 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13163 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13164 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13166 [(set_attr "type" "dfp_cmp")
13167 (set_attr "fp_mode" "double")])
13169 (define_insn "cmpeqdf_t"
13170 [(set (reg:SI T_REG)
13171 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13172 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13173 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13174 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13176 [(set_attr "type" "dfp_cmp")
13177 (set_attr "fp_mode" "double")])
13179 (define_insn "*ieee_ccmpeqdf_t"
13180 [(set (reg:SI T_REG)
13181 (ior:SI (reg:SI T_REG)
13182 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13183 (match_operand:DF 1 "fp_arith_reg_operand" "f"))))
13184 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13185 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13187 return output_ieee_ccmpeq (insn, operands);
13189 [(set_attr "length" "4")
13190 (set_attr "fp_mode" "double")])
13192 (define_insn "cmpeqdf_media"
13193 [(set (match_operand:SI 0 "register_operand" "=r")
13194 (eq:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13195 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13196 "TARGET_SHMEDIA_FPU"
13197 "fcmpeq.d %1,%2,%0"
13198 [(set_attr "type" "fcmp_media")])
13200 (define_insn "cmpgtdf_media"
13201 [(set (match_operand:SI 0 "register_operand" "=r")
13202 (gt:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13203 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13204 "TARGET_SHMEDIA_FPU"
13205 "fcmpgt.d %1,%2,%0"
13206 [(set_attr "type" "fcmp_media")])
13208 (define_insn "cmpgedf_media"
13209 [(set (match_operand:SI 0 "register_operand" "=r")
13210 (ge:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13211 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13212 "TARGET_SHMEDIA_FPU"
13213 "fcmpge.d %1,%2,%0"
13214 [(set_attr "type" "fcmp_media")])
13216 (define_insn "cmpundf_media"
13217 [(set (match_operand:SI 0 "register_operand" "=r")
13218 (unordered:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13219 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13220 "TARGET_SHMEDIA_FPU"
13221 "fcmpun.d %1,%2,%0"
13222 [(set_attr "type" "fcmp_media")])
13224 (define_expand "cbranchdf4"
13226 (if_then_else (match_operator 0 "sh_float_comparison_operator"
13227 [(match_operand:DF 1 "arith_operand" "")
13228 (match_operand:DF 2 "arith_operand" "")])
13229 (match_operand 3 "" "")
13231 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13233 if (TARGET_SHMEDIA)
13234 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
13237 sh_emit_compare_and_branch (operands, DFmode);
13241 (define_expand "negdf2"
13242 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13243 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13244 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13246 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13248 expand_df_unop (&gen_negdf2_i, operands);
13253 (define_insn "*negdf2_media"
13254 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13255 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13256 "TARGET_SHMEDIA_FPU"
13258 [(set_attr "type" "fmove_media")])
13260 (define_insn "negdf2_i"
13261 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13262 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13263 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13264 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13266 [(set_attr "type" "fmove")
13267 (set_attr "fp_mode" "double")])
13269 (define_expand "sqrtdf2"
13270 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13271 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13272 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13274 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13276 expand_df_unop (&gen_sqrtdf2_i, operands);
13281 (define_insn "*sqrtdf2_media"
13282 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13283 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13284 "TARGET_SHMEDIA_FPU"
13286 [(set_attr "type" "dfdiv_media")])
13288 (define_insn "sqrtdf2_i"
13289 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13290 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13291 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13292 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13294 [(set_attr "type" "dfdiv")
13295 (set_attr "fp_mode" "double")])
13297 (define_expand "absdf2"
13298 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13299 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13300 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13302 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13304 expand_df_unop (&gen_absdf2_i, operands);
13309 (define_insn "*absdf2_media"
13310 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13311 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13312 "TARGET_SHMEDIA_FPU"
13314 [(set_attr "type" "fmove_media")])
13316 (define_insn "absdf2_i"
13317 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13318 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13319 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13320 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13322 [(set_attr "type" "fmove")
13323 (set_attr "fp_mode" "double")])
13325 (define_expand "extendsfdf2"
13326 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13327 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
13328 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13330 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13332 emit_df_insn (gen_extendsfdf2_i4 (operands[0], operands[1],
13333 get_fpscr_rtx ()));
13338 (define_insn "*extendsfdf2_media"
13339 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13340 (float_extend:DF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13341 "TARGET_SHMEDIA_FPU"
13343 [(set_attr "type" "dfpconv_media")])
13345 (define_insn "extendsfdf2_i4"
13346 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13347 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
13348 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13349 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13351 [(set_attr "type" "fp")
13352 (set_attr "fp_mode" "double")])
13354 (define_expand "truncdfsf2"
13355 [(set (match_operand:SF 0 "fpul_operand" "")
13356 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
13357 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13359 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13361 emit_df_insn (gen_truncdfsf2_i4 (operands[0], operands[1],
13362 get_fpscr_rtx ()));
13367 (define_insn "*truncdfsf2_media"
13368 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13369 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13370 "TARGET_SHMEDIA_FPU"
13372 [(set_attr "type" "dfpconv_media")])
13374 (define_insn "truncdfsf2_i4"
13375 [(set (match_operand:SF 0 "fpul_operand" "=y")
13376 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13377 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
13378 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13380 [(set_attr "type" "fp")
13381 (set_attr "fp_mode" "double")])
13383 ;; -------------------------------------------------------------------------
13384 ;; Bit field extract patterns.
13385 ;; -------------------------------------------------------------------------
13387 ;; These give better code for packed bitfields, because they allow
13388 ;; auto-increment addresses to be generated.
13390 (define_expand "insv"
13391 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
13392 (match_operand:SI 1 "immediate_operand" "")
13393 (match_operand:SI 2 "immediate_operand" ""))
13394 (match_operand:SI 3 "general_operand" ""))]
13395 "TARGET_SH1 && TARGET_BIG_ENDIAN"
13397 rtx addr_target, orig_address, shift_reg, qi_val;
13398 HOST_WIDE_INT bitsize, size, v = 0;
13399 rtx x = operands[3];
13401 if (TARGET_SH2A && TARGET_BITOPS
13402 && (satisfies_constraint_Sbw (operands[0])
13403 || satisfies_constraint_Sbv (operands[0]))
13404 && satisfies_constraint_M (operands[1])
13405 && satisfies_constraint_K03 (operands[2]))
13407 if (satisfies_constraint_N (operands[3]))
13409 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
13412 else if (satisfies_constraint_M (operands[3]))
13414 emit_insn (gen_bset_m2a (operands[0], operands[2]));
13417 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
13418 && satisfies_constraint_M (operands[1]))
13420 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13423 else if (REG_P (operands[3])
13424 && satisfies_constraint_M (operands[1]))
13426 emit_insn (gen_bld_reg (operands[3], const0_rtx));
13427 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13431 /* ??? expmed doesn't care for non-register predicates. */
13432 if (! memory_operand (operands[0], VOIDmode)
13433 || ! immediate_operand (operands[1], VOIDmode)
13434 || ! immediate_operand (operands[2], VOIDmode)
13435 || ! general_operand (x, VOIDmode))
13437 /* If this isn't a 16 / 24 / 32 bit field, or if
13438 it doesn't start on a byte boundary, then fail. */
13439 bitsize = INTVAL (operands[1]);
13440 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
13441 || (INTVAL (operands[2]) % 8) != 0)
13444 size = bitsize / 8;
13445 orig_address = XEXP (operands[0], 0);
13446 shift_reg = gen_reg_rtx (SImode);
13447 if (CONST_INT_P (x))
13450 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
13454 emit_insn (gen_movsi (shift_reg, operands[3]));
13455 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13457 addr_target = copy_addr_to_reg (plus_constant (Pmode,
13458 orig_address, size - 1));
13460 operands[0] = replace_equiv_address (operands[0], addr_target);
13461 emit_insn (gen_movqi (operands[0], qi_val));
13465 if (CONST_INT_P (x))
13467 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
13470 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
13471 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13473 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
13474 emit_insn (gen_movqi (operands[0], qi_val));
13480 (define_insn "movua"
13481 [(set (match_operand:SI 0 "register_operand" "=z")
13482 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
13486 [(set_attr "type" "movua")])
13488 ;; We shouldn't need this, but cse replaces increments with references
13489 ;; to other regs before flow has a chance to create post_inc
13490 ;; addressing modes, and only postreload's cse_move2add brings the
13491 ;; increments back to a usable form.
13493 [(set (match_operand:SI 0 "register_operand" "")
13494 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
13495 (const_int 32) (const_int 0)))
13496 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
13497 "TARGET_SH4A_ARCH && REGNO (operands[0]) != REGNO (operands[1])"
13498 [(set (match_operand:SI 0 "register_operand" "")
13499 (sign_extract:SI (mem:SI (post_inc:SI
13500 (match_operand:SI 1 "register_operand" "")))
13501 (const_int 32) (const_int 0)))]
13504 (define_expand "extv"
13505 [(set (match_operand:SI 0 "register_operand" "")
13506 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13507 (match_operand 2 "const_int_operand" "")
13508 (match_operand 3 "const_int_operand" "")))]
13509 "TARGET_SH4A_ARCH || TARGET_SH2A"
13511 if (TARGET_SH2A && TARGET_BITOPS
13512 && (satisfies_constraint_Sbw (operands[1])
13513 || satisfies_constraint_Sbv (operands[1]))
13514 && satisfies_constraint_M (operands[2])
13515 && satisfies_constraint_K03 (operands[3]))
13517 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
13518 if (REGNO (operands[0]) != T_REG)
13519 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
13522 if (TARGET_SH4A_ARCH
13523 && INTVAL (operands[2]) == 32
13524 && INTVAL (operands[3]) == 0
13525 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
13527 rtx src = adjust_address (operands[1], BLKmode, 0);
13528 set_mem_size (src, 4);
13529 emit_insn (gen_movua (operands[0], src));
13536 (define_expand "extzv"
13537 [(set (match_operand:SI 0 "register_operand" "")
13538 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13539 (match_operand 2 "const_int_operand" "")
13540 (match_operand 3 "const_int_operand" "")))]
13541 "TARGET_SH4A_ARCH || TARGET_SH2A"
13543 if (TARGET_SH2A && TARGET_BITOPS
13544 && (satisfies_constraint_Sbw (operands[1])
13545 || satisfies_constraint_Sbv (operands[1]))
13546 && satisfies_constraint_M (operands[2])
13547 && satisfies_constraint_K03 (operands[3]))
13549 emit_insn (gen_bld_m2a (operands[1], operands[3]));
13550 if (REGNO (operands[0]) != T_REG)
13551 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
13554 if (TARGET_SH4A_ARCH
13555 && INTVAL (operands[2]) == 32
13556 && INTVAL (operands[3]) == 0
13557 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
13559 rtx src = adjust_address (operands[1], BLKmode, 0);
13560 set_mem_size (src, 4);
13561 emit_insn (gen_movua (operands[0], src));
13568 ;; SH2A instructions for bitwise operations.
13569 ;; FIXME: Convert multiple instruction insns to insn_and_split.
13570 ;; FIXME: Use iterators to fold at least and,xor,or insn variations.
13572 ;; Clear a bit in a memory location.
13573 (define_insn "bclr_m2a"
13574 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13576 (not:QI (ashift:QI (const_int 1)
13577 (match_operand:QI 1 "const_int_operand" "K03,K03")))
13579 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13582 bclr.b %1,@(0,%t0)"
13583 [(set_attr "length" "4,4")])
13585 (define_insn "bclrmem_m2a"
13586 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13587 (and:QI (match_dup 0)
13588 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
13589 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
13592 bclr.b %W1,@(0,%t0)"
13593 [(set_attr "length" "4,4")])
13595 ;; Set a bit in a memory location.
13596 (define_insn "bset_m2a"
13597 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13599 (ashift:QI (const_int 1)
13600 (match_operand:QI 1 "const_int_operand" "K03,K03"))
13602 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13605 bset.b %1,@(0,%t0)"
13606 [(set_attr "length" "4,4")])
13608 (define_insn "bsetmem_m2a"
13609 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13610 (ior:QI (match_dup 0)
13611 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
13612 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
13615 bset.b %V1,@(0,%t0)"
13616 [(set_attr "length" "4,4")])
13618 ;;; Transfer the contents of the T bit to a specified bit of memory.
13619 (define_insn "bst_m2a"
13620 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
13621 (if_then_else (eq (reg:SI T_REG) (const_int 0))
13623 (not:QI (ashift:QI (const_int 1)
13624 (match_operand:QI 1 "const_int_operand" "K03,K03")))
13627 (ashift:QI (const_int 1) (match_dup 1))
13629 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13633 [(set_attr "length" "4")])
13635 ;; Store a specified bit of memory in the T bit.
13636 (define_insn "bld_m2a"
13637 [(set (reg:SI T_REG)
13639 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
13641 (match_operand 1 "const_int_operand" "K03,K03")))]
13642 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13646 [(set_attr "length" "4,4")])
13648 ;; Store a specified bit of memory in the T bit.
13649 (define_insn "bldsign_m2a"
13650 [(set (reg:SI T_REG)
13652 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13654 (match_operand 1 "const_int_operand" "K03,K03")))]
13655 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13659 [(set_attr "length" "4,4")])
13661 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
13662 (define_insn "bld_reg"
13663 [(set (reg:SI T_REG)
13664 (zero_extract:SI (match_operand:SI 0 "arith_reg_operand" "r")
13666 (match_operand 1 "const_int_operand" "K03")))]
13667 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
13670 (define_insn "*bld_regqi"
13671 [(set (reg:SI T_REG)
13672 (zero_extract:SI (match_operand:QI 0 "arith_reg_operand" "r")
13674 (match_operand 1 "const_int_operand" "K03")))]
13675 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
13678 ;; Take logical and of a specified bit of memory with the T bit and
13679 ;; store its result in the T bit.
13680 (define_insn "band_m2a"
13681 [(set (reg:SI T_REG)
13682 (and:SI (reg:SI T_REG)
13684 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13686 (match_operand 1 "const_int_operand" "K03,K03"))))]
13687 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13690 band.b %1,@(0,%t0)"
13691 [(set_attr "length" "4,4")])
13693 (define_insn "bandreg_m2a"
13694 [(set (match_operand:SI 0 "register_operand" "=r,r")
13695 (and:SI (zero_extract:SI
13696 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13698 (match_operand 2 "const_int_operand" "K03,K03"))
13699 (match_operand:SI 3 "register_operand" "r,r")))]
13700 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13702 static const char* alt[] =
13704 "band.b %2,%1" "\n"
13707 "band.b %2,@(0,%t1)" "\n"
13710 return alt[which_alternative];
13712 [(set_attr "length" "6,6")])
13714 ;; Take logical or of a specified bit of memory with the T bit and
13715 ;; store its result in the T bit.
13716 (define_insn "bor_m2a"
13717 [(set (reg:SI T_REG)
13718 (ior:SI (reg:SI T_REG)
13720 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13722 (match_operand 1 "const_int_operand" "K03,K03"))))]
13723 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13727 [(set_attr "length" "4,4")])
13729 (define_insn "borreg_m2a"
13730 [(set (match_operand:SI 0 "register_operand" "=r,r")
13731 (ior:SI (zero_extract:SI
13732 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13734 (match_operand 2 "const_int_operand" "K03,K03"))
13735 (match_operand:SI 3 "register_operand" "=r,r")))]
13736 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13738 static const char* alt[] =
13743 "bor.b %2,@(0,%t1)" "\n"
13746 return alt[which_alternative];
13748 [(set_attr "length" "6,6")])
13750 ;; Take exclusive or of a specified bit of memory with the T bit and
13751 ;; store its result in the T bit.
13752 (define_insn "bxor_m2a"
13753 [(set (reg:SI T_REG)
13754 (xor:SI (reg:SI T_REG)
13756 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13758 (match_operand 1 "const_int_operand" "K03,K03"))))]
13759 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13762 bxor.b %1,@(0,%t0)"
13763 [(set_attr "length" "4,4")])
13765 (define_insn "bxorreg_m2a"
13766 [(set (match_operand:SI 0 "register_operand" "=r,r")
13767 (xor:SI (zero_extract:SI
13768 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13770 (match_operand 2 "const_int_operand" "K03,K03"))
13771 (match_operand:SI 3 "register_operand" "=r,r")))]
13772 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13774 static const char* alt[] =
13776 "bxor.b %2,%1" "\n"
13779 "bxor.b %2,@(0,%t1)" "\n"
13782 return alt[which_alternative];
13784 [(set_attr "length" "6,6")])
13786 ;; -------------------------------------------------------------------------
13788 ;; -------------------------------------------------------------------------
13789 ;; This matches cases where the bit in a memory location is set.
13791 [(set (match_operand:SI 0 "register_operand")
13792 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
13794 (ior:SI (match_dup 0)
13795 (match_operand:SI 2 "const_int_operand")))
13797 (match_operand 3 "arith_reg_operand"))]
13798 "TARGET_SH2A && TARGET_BITOPS
13799 && satisfies_constraint_Pso (operands[2])
13800 && REGNO (operands[0]) == REGNO (operands[3])"
13801 [(set (match_dup 1)
13802 (ior:QI (match_dup 1) (match_dup 2)))]
13805 ;; This matches cases where the bit in a memory location is cleared.
13807 [(set (match_operand:SI 0 "register_operand")
13808 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
13810 (and:SI (match_dup 0)
13811 (match_operand:SI 2 "const_int_operand")))
13813 (match_operand 3 "arith_reg_operand"))]
13814 "TARGET_SH2A && TARGET_BITOPS
13815 && satisfies_constraint_Psz (operands[2])
13816 && REGNO (operands[0]) == REGNO (operands[3])"
13817 [(set (match_dup 1)
13818 (and:QI (match_dup 1) (match_dup 2)))]
13821 ;; This matches cases where a stack pointer increment at the start of the
13822 ;; epilogue combines with a stack slot read loading the return value.
13824 [(set (match_operand:SI 0 "arith_reg_operand" "")
13825 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
13826 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
13827 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
13830 ;; See the comment on the dt combiner pattern above.
13832 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
13833 (plus:SI (match_dup 0)
13835 (set (reg:SI T_REG)
13836 (eq:SI (match_dup 0) (const_int 0)))]
13840 ;; The following peepholes fold load sequences for which reload was not
13841 ;; able to generate a displacement addressing move insn.
13842 ;; This can happen when reload has to transform a move insn
13843 ;; without displacement into one with displacement. Or when reload can't
13844 ;; fit a displacement into the insn's constraints. In the latter case, the
13845 ;; load destination reg remains at r0, which reload compensates by inserting
13846 ;; another mov insn.
13850 ;; mov.{b,w} @(r0,r15),r0
13853 ;; mov.{b,w} @(54,r15),r3
13856 [(set (match_operand:SI 0 "arith_reg_dest" "")
13857 (match_operand:SI 1 "const_int_operand" ""))
13858 (set (match_operand:SI 2 "arith_reg_dest" "")
13860 (mem:QI (plus:SI (match_dup 0)
13861 (match_operand:SI 3 "arith_reg_operand" "")))))
13862 (set (match_operand:QI 4 "arith_reg_dest" "")
13863 (match_operand:QI 5 "arith_reg_operand" ""))]
13865 && sh_legitimate_index_p (QImode, operands[1], true, true)
13866 && REGNO (operands[2]) == REGNO (operands[5])
13867 && peep2_reg_dead_p (3, operands[5])"
13868 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
13872 [(set (match_operand:SI 0 "arith_reg_dest" "")
13873 (match_operand:SI 1 "const_int_operand" ""))
13874 (set (match_operand:SI 2 "arith_reg_dest" "")
13876 (mem:HI (plus:SI (match_dup 0)
13877 (match_operand:SI 3 "arith_reg_operand" "")))))
13878 (set (match_operand:HI 4 "arith_reg_dest" "")
13879 (match_operand:HI 5 "arith_reg_operand" ""))]
13881 && sh_legitimate_index_p (HImode, operands[1], true, true)
13882 && REGNO (operands[2]) == REGNO (operands[5])
13883 && peep2_reg_dead_p (3, operands[5])"
13884 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))]
13889 ;; mov.{b,w} @(r0,r15),r1
13891 ;; mov.{b,w} @(54,r15),r1
13894 [(set (match_operand:SI 0 "arith_reg_dest" "")
13895 (match_operand:SI 1 "const_int_operand" ""))
13896 (set (match_operand:SI 2 "arith_reg_dest" "")
13898 (mem:QI (plus:SI (match_dup 0)
13899 (match_operand:SI 3 "arith_reg_operand" "")))))]
13901 && sh_legitimate_index_p (QImode, operands[1], true, true)
13902 && (peep2_reg_dead_p (2, operands[0])
13903 || REGNO (operands[0]) == REGNO (operands[2]))"
13904 [(set (match_dup 2)
13905 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
13909 [(set (match_operand:SI 0 "arith_reg_dest" "")
13910 (match_operand:SI 1 "const_int_operand" ""))
13911 (set (match_operand:SI 2 "arith_reg_dest" "")
13913 (mem:HI (plus:SI (match_dup 0)
13914 (match_operand:SI 3 "arith_reg_operand" "")))))]
13916 && sh_legitimate_index_p (HImode, operands[1], true, true)
13917 && (peep2_reg_dead_p (2, operands[0])
13918 || REGNO (operands[0]) == REGNO (operands[2]))"
13919 [(set (match_dup 2)
13920 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))]
13924 ;; mov.{b,w} @(r0,r15),r0
13927 ;; mov.{b,w} @(r0,r15),r3
13929 ;; This can happen when initially a displacement address is picked, where
13930 ;; the destination reg is fixed to r0, and then the address is transformed
13931 ;; into 'r0 + reg'.
13933 [(set (match_operand:SI 0 "arith_reg_dest" "")
13935 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
13936 (match_operand:SI 2 "arith_reg_operand" "")))))
13937 (set (match_operand:QI 3 "arith_reg_dest" "")
13938 (match_operand:QI 4 "arith_reg_operand" ""))]
13940 && REGNO (operands[0]) == REGNO (operands[4])
13941 && peep2_reg_dead_p (2, operands[0])"
13942 [(set (match_dup 3)
13943 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
13947 [(set (match_operand:SI 0 "arith_reg_dest" "")
13949 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
13950 (match_operand:SI 2 "arith_reg_operand" "")))))
13951 (set (match_operand:HI 3 "arith_reg_dest" "")
13952 (match_operand:HI 4 "arith_reg_operand" ""))]
13954 && REGNO (operands[0]) == REGNO (operands[4])
13955 && peep2_reg_dead_p (2, operands[0])"
13956 [(set (match_dup 3)
13957 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))]
13961 [(set (match_operand:SI 0 "register_operand" "=r")
13962 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13963 (set (mem:SF (match_dup 0))
13964 (match_operand:SF 2 "general_movsrc_operand" ""))]
13965 "TARGET_SH1 && REGNO (operands[0]) == 0
13966 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
13967 || (GET_CODE (operands[2]) == SUBREG
13968 && REGNO (SUBREG_REG (operands[2])) < 16))
13969 && reg_unused_after (operands[0], insn)"
13970 "mov.l %2,@(%0,%1)")
13973 [(set (match_operand:SI 0 "register_operand" "=r")
13974 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13975 (set (match_operand:SF 2 "general_movdst_operand" "")
13977 (mem:SF (match_dup 0)))]
13978 "TARGET_SH1 && REGNO (operands[0]) == 0
13979 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
13980 || (GET_CODE (operands[2]) == SUBREG
13981 && REGNO (SUBREG_REG (operands[2])) < 16))
13982 && reg_unused_after (operands[0], insn)"
13983 "mov.l @(%0,%1),%2")
13986 [(set (match_operand:SI 0 "register_operand" "=r")
13987 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13988 (set (mem:SF (match_dup 0))
13989 (match_operand:SF 2 "general_movsrc_operand" ""))]
13990 "TARGET_SH2E && REGNO (operands[0]) == 0
13991 && ((REG_P (operands[2])
13992 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
13993 || (GET_CODE (operands[2]) == SUBREG
13994 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
13995 && reg_unused_after (operands[0], insn)"
13996 "fmov{.s|} %2,@(%0,%1)")
13999 [(set (match_operand:SI 0 "register_operand" "=r")
14000 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
14001 (set (match_operand:SF 2 "general_movdst_operand" "")
14003 (mem:SF (match_dup 0)))]
14004 "TARGET_SH2E && REGNO (operands[0]) == 0
14005 && ((REG_P (operands[2])
14006 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
14007 || (GET_CODE (operands[2]) == SUBREG
14008 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
14009 && reg_unused_after (operands[0], insn)"
14010 "fmov{.s|} @(%0,%1),%2")
14012 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
14013 (define_insn "sp_switch_1"
14014 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")]
14015 UNSPECV_SP_SWITCH_B))]
14018 return "mov.l r0,@-r15" "\n"
14019 " mov.l %0,r0" "\n"
14020 " mov.l @r0,r0" "\n"
14021 " mov.l r15,@-r0" "\n"
14024 [(set_attr "length" "10")])
14026 ;; Switch back to the original stack for interrupt functions with the
14027 ;; sp_switch attribute.
14028 (define_insn "sp_switch_2"
14029 [(unspec_volatile [(const_int 0)]
14030 UNSPECV_SP_SWITCH_E)]
14033 return "mov.l @r15,r15" "\n"
14036 [(set_attr "length" "4")])
14038 ;; -------------------------------------------------------------------------
14039 ;; Integer vector moves
14040 ;; -------------------------------------------------------------------------
14042 (define_expand "movv8qi"
14043 [(set (match_operand:V8QI 0 "general_movdst_operand" "")
14044 (match_operand:V8QI 1 "general_movsrc_operand" ""))]
14047 prepare_move_operands (operands, V8QImode);
14050 (define_insn "movv8qi_i"
14051 [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
14052 (match_operand:V8QI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14054 && (register_operand (operands[0], V8QImode)
14055 || sh_register_operand (operands[1], V8QImode))"
14062 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14063 (set_attr "length" "4,4,16,4,4")])
14066 [(set (match_operand:V8QI 0 "arith_reg_dest" "")
14067 (subreg:V8QI (const_int 0) 0))]
14069 [(set (match_dup 0)
14070 (const_vector:V8QI [(const_int 0) (const_int 0) (const_int 0)
14071 (const_int 0) (const_int 0) (const_int 0)
14072 (const_int 0) (const_int 0)]))])
14075 [(set (match_operand 0 "arith_reg_dest" "")
14076 (match_operand 1 "sh_rep_vec" ""))]
14077 "TARGET_SHMEDIA && reload_completed
14078 && GET_MODE (operands[0]) == GET_MODE (operands[1])
14079 && sh_vector_mode_supported_p (GET_MODE (operands[0]))
14080 && GET_MODE_SIZE (GET_MODE (operands[0])) == 8
14081 && (XVECEXP (operands[1], 0, 0) != const0_rtx
14082 || XVECEXP (operands[1], 0, 1) != const0_rtx)
14083 && (XVECEXP (operands[1], 0, 0) != constm1_rtx
14084 || XVECEXP (operands[1], 0, 1) != constm1_rtx)"
14085 [(set (match_dup 0) (match_dup 1))
14088 int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (operands[1]));
14089 rtx elt1 = XVECEXP (operands[1], 0, 1);
14092 operands[2] = gen_mshflo_l (operands[0], operands[0], operands[0]);
14096 operands[0] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
14097 operands[2] = gen_mperm_w0 (operands[0], operands[0]);
14099 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
14100 operands[1] = XVECEXP (operands[1], 0, 0);
14103 if (CONST_INT_P (operands[1]) && CONST_INT_P (elt1))
14105 = GEN_INT (TARGET_LITTLE_ENDIAN
14106 ? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8)
14107 : (INTVAL (operands[1]) << 8) + (INTVAL (elt1) & 0xff));
14110 operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0]));
14112 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, operands[1], elt1));
14118 [(set (match_operand 0 "arith_reg_dest" "")
14119 (match_operand 1 "sh_const_vec" ""))]
14120 "TARGET_SHMEDIA && reload_completed
14121 && GET_MODE (operands[0]) == GET_MODE (operands[1])
14122 && sh_vector_mode_supported_p (GET_MODE (operands[0]))"
14123 [(set (match_dup 0) (match_dup 1))]
14125 rtx v = operands[1];
14126 enum machine_mode new_mode
14127 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (v)), MODE_INT, 0);
14129 operands[0] = gen_rtx_REG (new_mode, true_regnum (operands[0]));
14131 = simplify_subreg (new_mode, operands[1], GET_MODE (operands[1]), 0);
14134 (define_expand "movv2hi"
14135 [(set (match_operand:V2HI 0 "general_movdst_operand" "")
14136 (match_operand:V2HI 1 "general_movsrc_operand" ""))]
14139 prepare_move_operands (operands, V2HImode);
14142 (define_insn "movv2hi_i"
14143 [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
14144 (match_operand:V2HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14146 && (register_operand (operands[0], V2HImode)
14147 || sh_register_operand (operands[1], V2HImode))"
14154 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14155 (set_attr "length" "4,4,16,4,4")
14156 (set (attr "highpart")
14157 (cond [(match_test "sh_contains_memref_p (insn)")
14158 (const_string "user")]
14159 (const_string "ignore")))])
14161 (define_expand "movv4hi"
14162 [(set (match_operand:V4HI 0 "general_movdst_operand" "")
14163 (match_operand:V4HI 1 "general_movsrc_operand" ""))]
14166 prepare_move_operands (operands, V4HImode);
14169 (define_insn "movv4hi_i"
14170 [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
14171 (match_operand:V4HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14173 && (register_operand (operands[0], V4HImode)
14174 || sh_register_operand (operands[1], V4HImode))"
14181 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14182 (set_attr "length" "4,4,16,4,4")
14183 (set_attr "highpart" "depend")])
14185 (define_expand "movv2si"
14186 [(set (match_operand:V2SI 0 "general_movdst_operand" "")
14187 (match_operand:V2SI 1 "general_movsrc_operand" ""))]
14190 prepare_move_operands (operands, V2SImode);
14193 (define_insn "movv2si_i"
14194 [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
14195 (match_operand:V2SI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14197 && (register_operand (operands[0], V2SImode)
14198 || sh_register_operand (operands[1], V2SImode))"
14205 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14206 (set_attr "length" "4,4,16,4,4")
14207 (set_attr "highpart" "depend")])
14209 ;; -------------------------------------------------------------------------
14210 ;; Multimedia Intrinsics
14211 ;; -------------------------------------------------------------------------
14213 (define_insn "absv2si2"
14214 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14215 (abs:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")))]
14218 [(set_attr "type" "mcmp_media")
14219 (set_attr "highpart" "depend")])
14221 (define_insn "absv4hi2"
14222 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14223 (abs:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")))]
14226 [(set_attr "type" "mcmp_media")
14227 (set_attr "highpart" "depend")])
14229 (define_insn "addv2si3"
14230 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14231 (plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
14232 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14234 "madd.l %1, %2, %0"
14235 [(set_attr "type" "arith_media")
14236 (set_attr "highpart" "depend")])
14238 (define_insn "addv4hi3"
14239 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14240 (plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
14241 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14243 "madd.w %1, %2, %0"
14244 [(set_attr "type" "arith_media")
14245 (set_attr "highpart" "depend")])
14247 (define_insn_and_split "addv2hi3"
14248 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
14249 (plus:V2HI (match_operand:V2HI 1 "extend_reg_operand" "%r")
14250 (match_operand:V2HI 2 "extend_reg_operand" "r")))]
14256 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
14257 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
14258 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
14259 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
14260 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
14262 emit_insn (gen_addv4hi3 (v4hi_dst, src0, src1));
14263 emit_insn (gen_truncdisi2 (si_dst, di_dst));
14266 [(set_attr "highpart" "must_split")])
14268 (define_insn "ssaddv2si3"
14269 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14270 (ss_plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
14271 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14273 "madds.l %1, %2, %0"
14274 [(set_attr "type" "mcmp_media")
14275 (set_attr "highpart" "depend")])
14277 (define_insn "usaddv8qi3"
14278 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14279 (us_plus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "%r")
14280 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
14282 "madds.ub %1, %2, %0"
14283 [(set_attr "type" "mcmp_media")
14284 (set_attr "highpart" "depend")])
14286 (define_insn "ssaddv4hi3"
14287 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14288 (ss_plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
14289 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14291 "madds.w %1, %2, %0"
14292 [(set_attr "type" "mcmp_media")
14293 (set_attr "highpart" "depend")])
14295 (define_insn "negcmpeqv8qi"
14296 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14298 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
14299 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
14301 "mcmpeq.b %N1, %N2, %0"
14302 [(set_attr "type" "mcmp_media")
14303 (set_attr "highpart" "depend")])
14305 (define_insn "negcmpeqv2si"
14306 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14308 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
14309 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14311 "mcmpeq.l %N1, %N2, %0"
14312 [(set_attr "type" "mcmp_media")
14313 (set_attr "highpart" "depend")])
14315 (define_insn "negcmpeqv4hi"
14316 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14318 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
14319 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14321 "mcmpeq.w %N1, %N2, %0"
14322 [(set_attr "type" "mcmp_media")
14323 (set_attr "highpart" "depend")])
14325 (define_insn "negcmpgtuv8qi"
14326 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14327 (neg:V8QI (gtu:V8QI
14328 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
14329 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
14331 "mcmpgt.ub %N1, %N2, %0"
14332 [(set_attr "type" "mcmp_media")
14333 (set_attr "highpart" "depend")])
14335 (define_insn "negcmpgtv2si"
14336 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14338 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
14339 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14341 "mcmpgt.l %N1, %N2, %0"
14342 [(set_attr "type" "mcmp_media")
14343 (set_attr "highpart" "depend")])
14345 (define_insn "negcmpgtv4hi"
14346 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14348 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
14349 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14351 "mcmpgt.w %N1, %N2, %0"
14352 [(set_attr "type" "mcmp_media")
14353 (set_attr "highpart" "depend")])
14355 (define_insn "mcmv"
14356 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14357 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14358 (match_operand:DI 2 "arith_reg_operand" "r"))
14359 (and:DI (match_operand:DI 3 "arith_reg_operand" "0")
14360 (not:DI (match_dup 2)))))]
14363 [(set_attr "type" "arith_media")
14364 (set_attr "highpart" "depend")])
14366 (define_insn "mcnvs_lw"
14367 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14369 (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
14371 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14373 "mcnvs.lw %N1, %N2, %0"
14374 [(set_attr "type" "mcmp_media")])
14376 (define_insn "mcnvs_wb"
14377 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14379 (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
14381 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14383 "mcnvs.wb %N1, %N2, %0"
14384 [(set_attr "type" "mcmp_media")])
14386 (define_insn "mcnvs_wub"
14387 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14389 (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
14391 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14393 "mcnvs.wub %N1, %N2, %0"
14394 [(set_attr "type" "mcmp_media")])
14396 (define_insn "mextr_rl"
14397 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14398 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14399 (match_operand:HI 3 "mextr_bit_offset" "i"))
14400 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14401 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
14402 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
14404 static char templ[21];
14405 sprintf (templ, "mextr%d %%N1, %%N2, %%0",
14406 (int) INTVAL (operands[3]) >> 3);
14409 [(set_attr "type" "arith_media")])
14411 (define_insn "*mextr_lr"
14412 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14413 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14414 (match_operand:HI 3 "mextr_bit_offset" "i"))
14415 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14416 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
14417 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
14419 static char templ[21];
14420 sprintf (templ, "mextr%d %%N2, %%N1, %%0",
14421 (int) INTVAL (operands[4]) >> 3);
14424 [(set_attr "type" "arith_media")])
14426 ; mextrN can be modelled with vec_select / vec_concat, but the selection
14427 ; vector then varies depending on endianness.
14428 (define_expand "mextr1"
14429 [(match_operand:DI 0 "arith_reg_dest" "")
14430 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14431 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14434 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14435 GEN_INT (1 * 8), GEN_INT (7 * 8)));
14439 (define_expand "mextr2"
14440 [(match_operand:DI 0 "arith_reg_dest" "")
14441 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14442 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14445 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14446 GEN_INT (2 * 8), GEN_INT (6 * 8)));
14450 (define_expand "mextr3"
14451 [(match_operand:DI 0 "arith_reg_dest" "")
14452 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14453 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14456 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14457 GEN_INT (3 * 8), GEN_INT (5 * 8)));
14461 (define_expand "mextr4"
14462 [(match_operand:DI 0 "arith_reg_dest" "")
14463 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14464 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14467 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14468 GEN_INT (4 * 8), GEN_INT (4 * 8)));
14472 (define_expand "mextr5"
14473 [(match_operand:DI 0 "arith_reg_dest" "")
14474 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14475 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14478 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14479 GEN_INT (5 * 8), GEN_INT (3 * 8)));
14483 (define_expand "mextr6"
14484 [(match_operand:DI 0 "arith_reg_dest" "")
14485 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14486 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14489 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14490 GEN_INT (6 * 8), GEN_INT (2 * 8)));
14494 (define_expand "mextr7"
14495 [(match_operand:DI 0 "arith_reg_dest" "")
14496 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14497 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14500 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14501 GEN_INT (7 * 8), GEN_INT (1 * 8)));
14505 (define_expand "mmacfx_wl"
14506 [(match_operand:V2SI 0 "arith_reg_dest" "")
14507 (match_operand:V2HI 1 "extend_reg_operand" "")
14508 (match_operand:V2HI 2 "extend_reg_operand" "")
14509 (match_operand:V2SI 3 "arith_reg_operand" "")]
14512 emit_insn (gen_mmacfx_wl_i (operands[0], operands[3],
14513 operands[1], operands[2]));
14517 ;; This could be highpart ignore if it only had inputs 2 or 3, but input 1
14519 (define_insn "mmacfx_wl_i"
14520 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14522 (match_operand:V2SI 1 "arith_reg_operand" "0")
14527 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
14528 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
14531 "mmacfx.wl %2, %3, %0"
14532 [(set_attr "type" "mac_media")
14533 (set_attr "highpart" "depend")])
14535 (define_expand "mmacnfx_wl"
14536 [(match_operand:V2SI 0 "arith_reg_dest" "")
14537 (match_operand:V2HI 1 "extend_reg_operand" "")
14538 (match_operand:V2HI 2 "extend_reg_operand" "")
14539 (match_operand:V2SI 3 "arith_reg_operand" "")]
14542 emit_insn (gen_mmacnfx_wl_i (operands[0], operands[3],
14543 operands[1], operands[2]));
14547 (define_insn "mmacnfx_wl_i"
14548 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14550 (match_operand:V2SI 1 "arith_reg_operand" "0")
14555 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
14556 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
14559 "mmacnfx.wl %2, %3, %0"
14560 [(set_attr "type" "mac_media")
14561 (set_attr "highpart" "depend")])
14563 (define_insn "mulv2si3"
14564 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14565 (mult:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
14566 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14568 "mmul.l %1, %2, %0"
14569 [(set_attr "type" "d2mpy_media")
14570 (set_attr "highpart" "depend")])
14572 (define_insn "mulv4hi3"
14573 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14574 (mult:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
14575 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14577 "mmul.w %1, %2, %0"
14578 [(set_attr "type" "dmpy_media")
14579 (set_attr "highpart" "depend")])
14581 (define_insn "mmulfx_l"
14582 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14586 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
14587 (sign_extend:V2DI (match_operand:V2SI 2 "arith_reg_operand" "r")))
14590 "mmulfx.l %1, %2, %0"
14591 [(set_attr "type" "d2mpy_media")
14592 (set_attr "highpart" "depend")])
14594 (define_insn "mmulfx_w"
14595 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14599 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14600 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14603 "mmulfx.w %1, %2, %0"
14604 [(set_attr "type" "dmpy_media")
14605 (set_attr "highpart" "depend")])
14607 (define_insn "mmulfxrp_w"
14608 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14613 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14614 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14618 "mmulfxrp.w %1, %2, %0"
14619 [(set_attr "type" "dmpy_media")
14620 (set_attr "highpart" "depend")])
14623 (define_expand "mmulhi_wl"
14624 [(match_operand:V2SI 0 "arith_reg_dest" "")
14625 (match_operand:V4HI 1 "arith_reg_operand" "")
14626 (match_operand:V4HI 2 "arith_reg_operand" "")]
14629 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul23_wl : gen_mmul01_wl)
14630 (operands[0], operands[1], operands[2]));
14634 (define_expand "mmullo_wl"
14635 [(match_operand:V2SI 0 "arith_reg_dest" "")
14636 (match_operand:V4HI 1 "arith_reg_operand" "")
14637 (match_operand:V4HI 2 "arith_reg_operand" "")]
14640 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul01_wl : gen_mmul23_wl)
14641 (operands[0], operands[1], operands[2]));
14645 (define_insn "mmul23_wl"
14646 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14649 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14650 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14651 (parallel [(const_int 2) (const_int 3)])))]
14654 return (TARGET_LITTLE_ENDIAN
14655 ? "mmulhi.wl %1, %2, %0"
14656 : "mmullo.wl %1, %2, %0");
14658 [(set_attr "type" "dmpy_media")
14659 (set (attr "highpart")
14660 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14661 (const_string "user")))])
14663 (define_insn "mmul01_wl"
14664 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14667 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14668 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14669 (parallel [(const_int 0) (const_int 1)])))]
14672 return (TARGET_LITTLE_ENDIAN
14673 ? "mmullo.wl %1, %2, %0"
14674 : "mmulhi.wl %1, %2, %0");
14676 [(set_attr "type" "dmpy_media")
14677 (set (attr "highpart")
14678 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14679 (const_string "user")))])
14682 (define_expand "mmulsum_wq"
14683 [(match_operand:DI 0 "arith_reg_dest" "")
14684 (match_operand:V4HI 1 "arith_reg_operand" "")
14685 (match_operand:V4HI 2 "arith_reg_operand" "")
14686 (match_operand:DI 3 "arith_reg_operand" "")]
14689 emit_insn (gen_mmulsum_wq_i (operands[0], operands[3],
14690 operands[1], operands[2]));
14694 (define_insn "mmulsum_wq_i"
14695 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14696 (plus:DI (match_operand:DI 1 "arith_reg_operand" "0")
14701 (sign_extend:V4DI (match_operand:V4HI 2 "arith_reg_operand" "r"))
14702 (sign_extend:V4DI (match_operand:V4HI 3 "arith_reg_operand" "r")))
14703 (parallel [(const_int 0)]))
14704 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14705 (sign_extend:V4DI (match_dup 3)))
14706 (parallel [(const_int 1)])))
14708 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14709 (sign_extend:V4DI (match_dup 3)))
14710 (parallel [(const_int 2)]))
14711 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14712 (sign_extend:V4DI (match_dup 3)))
14713 (parallel [(const_int 3)]))))))]
14715 "mmulsum.wq %2, %3, %0"
14716 [(set_attr "type" "mac_media")])
14718 (define_expand "mperm_w"
14719 [(match_operand:V4HI 0 "arith_reg_dest" "=r")
14720 (match_operand:V4HI 1 "arith_reg_operand" "r")
14721 (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")]
14724 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mperm_w_little : gen_mperm_w_big)
14725 (operands[0], operands[1], operands[2]));
14729 ; This use of vec_select isn't exactly correct according to rtl.texi
14730 ; (because not constant), but it seems a straightforward extension.
14731 (define_insn "mperm_w_little"
14732 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14734 (match_operand:V4HI 1 "arith_reg_operand" "r")
14736 [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")
14737 (const_int 2) (const_int 0))
14738 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 2))
14739 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 4))
14740 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 6))])))]
14741 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
14742 "mperm.w %1, %N2, %0"
14743 [(set_attr "type" "arith_media")])
14745 (define_insn "mperm_w_big"
14746 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14748 (match_operand:V4HI 1 "arith_reg_operand" "r")
14750 [(zero_extract:QI (not:QI (match_operand:QI 2
14751 "extend_reg_or_0_operand" "rZ"))
14752 (const_int 2) (const_int 0))
14753 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2))
14754 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
14755 (zero_extract:QI (not:QI (match_dup 2))
14756 (const_int 2) (const_int 6))])))]
14757 "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
14758 "mperm.w %1, %N2, %0"
14759 [(set_attr "type" "arith_media")])
14761 (define_insn "mperm_w0"
14762 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14763 (vec_duplicate:V4HI (truncate:HI (match_operand 1
14764 "trunc_hi_operand" "r"))))]
14766 "mperm.w %1, r63, %0"
14767 [(set_attr "type" "arith_media")
14768 (set_attr "highpart" "ignore")])
14770 (define_expand "msad_ubq"
14771 [(match_operand:DI 0 "arith_reg_dest" "")
14772 (match_operand:V8QI 1 "arith_reg_or_0_operand" "")
14773 (match_operand:V8QI 2 "arith_reg_or_0_operand" "")
14774 (match_operand:DI 3 "arith_reg_operand" "")]
14777 emit_insn (gen_msad_ubq_i (operands[0], operands[3],
14778 operands[1], operands[2]));
14782 (define_insn "msad_ubq_i"
14783 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14788 (match_operand:DI 1 "arith_reg_operand" "0")
14789 (abs:DI (vec_select:DI
14792 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14794 (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ")))
14795 (parallel [(const_int 0)]))))
14796 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14797 (zero_extend:V8DI (match_dup 3)))
14798 (parallel [(const_int 1)]))))
14800 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14801 (zero_extend:V8DI (match_dup 3)))
14802 (parallel [(const_int 2)])))
14803 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14804 (zero_extend:V8DI (match_dup 3)))
14805 (parallel [(const_int 3)])))))
14808 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14809 (zero_extend:V8DI (match_dup 3)))
14810 (parallel [(const_int 4)])))
14811 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14812 (zero_extend:V8DI (match_dup 3)))
14813 (parallel [(const_int 5)]))))
14815 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14816 (zero_extend:V8DI (match_dup 3)))
14817 (parallel [(const_int 6)])))
14818 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14819 (zero_extend:V8DI (match_dup 3)))
14820 (parallel [(const_int 7)])))))))]
14822 "msad.ubq %N2, %N3, %0"
14823 [(set_attr "type" "mac_media")])
14825 (define_insn "mshalds_l"
14826 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14829 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
14830 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
14831 (const_int 31)))))]
14833 "mshalds.l %1, %2, %0"
14834 [(set_attr "type" "mcmp_media")
14835 (set_attr "highpart" "depend")])
14837 (define_insn "mshalds_w"
14838 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14841 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14842 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
14843 (const_int 15)))))]
14845 "mshalds.w %1, %2, %0"
14846 [(set_attr "type" "mcmp_media")
14847 (set_attr "highpart" "depend")])
14849 (define_insn "ashrv2si3"
14850 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14851 (ashiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
14852 (match_operand:DI 2 "arith_reg_operand" "r")))]
14854 "mshard.l %1, %2, %0"
14855 [(set_attr "type" "arith_media")
14856 (set_attr "highpart" "depend")])
14858 (define_insn "ashrv4hi3"
14859 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14860 (ashiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
14861 (match_operand:DI 2 "arith_reg_operand" "r")))]
14863 "mshard.w %1, %2, %0"
14864 [(set_attr "type" "arith_media")
14865 (set_attr "highpart" "depend")])
14867 (define_insn "mshards_q"
14868 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
14870 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
14871 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))]
14873 "mshards.q %1, %N2, %0"
14874 [(set_attr "type" "mcmp_media")])
14876 (define_expand "mshfhi_b"
14877 [(match_operand:V8QI 0 "arith_reg_dest" "")
14878 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14879 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
14882 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_b : gen_mshf0_b)
14883 (operands[0], operands[1], operands[2]));
14887 (define_expand "mshflo_b"
14888 [(match_operand:V8QI 0 "arith_reg_dest" "")
14889 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14890 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
14893 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_b : gen_mshf4_b)
14894 (operands[0], operands[1], operands[2]));
14898 (define_insn "mshf4_b"
14900 (match_operand:V8QI 0 "arith_reg_dest" "=r")
14902 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14903 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14904 (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
14905 (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
14908 return (TARGET_LITTLE_ENDIAN
14909 ? "mshfhi.b %N1, %N2, %0"
14910 : "mshflo.b %N1, %N2, %0");
14912 [(set_attr "type" "arith_media")
14913 (set (attr "highpart")
14914 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14915 (const_string "user")))])
14917 (define_insn "mshf0_b"
14919 (match_operand:V8QI 0 "arith_reg_dest" "=r")
14921 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14922 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14923 (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
14924 (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
14927 return (TARGET_LITTLE_ENDIAN
14928 ? "mshflo.b %N1, %N2, %0"
14929 : "mshfhi.b %N1, %N2, %0");
14931 [(set_attr "type" "arith_media")
14932 (set (attr "highpart")
14933 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14934 (const_string "user")))])
14936 (define_expand "mshfhi_l"
14937 [(match_operand:V2SI 0 "arith_reg_dest" "")
14938 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14939 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
14942 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_l : gen_mshf0_l)
14943 (operands[0], operands[1], operands[2]));
14947 (define_expand "mshflo_l"
14948 [(match_operand:V2SI 0 "arith_reg_dest" "")
14949 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14950 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
14953 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_l : gen_mshf4_l)
14954 (operands[0], operands[1], operands[2]));
14958 (define_insn "mshf4_l"
14959 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14961 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14962 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
14963 (parallel [(const_int 1) (const_int 3)])))]
14966 return (TARGET_LITTLE_ENDIAN
14967 ? "mshfhi.l %N1, %N2, %0"
14968 : "mshflo.l %N1, %N2, %0");
14970 [(set_attr "type" "arith_media")
14971 (set (attr "highpart")
14972 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14973 (const_string "user")))])
14975 (define_insn "mshf0_l"
14976 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14978 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14979 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
14980 (parallel [(const_int 0) (const_int 2)])))]
14983 return (TARGET_LITTLE_ENDIAN
14984 ? "mshflo.l %N1, %N2, %0"
14985 : "mshfhi.l %N1, %N2, %0");
14987 [(set_attr "type" "arith_media")
14988 (set (attr "highpart")
14989 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14990 (const_string "user")))])
14992 (define_expand "mshfhi_w"
14993 [(match_operand:V4HI 0 "arith_reg_dest" "")
14994 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14995 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
14998 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_w : gen_mshf0_w)
14999 (operands[0], operands[1], operands[2]));
15003 (define_expand "mshflo_w"
15004 [(match_operand:V4HI 0 "arith_reg_dest" "")
15005 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15006 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
15009 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_w : gen_mshf4_w)
15010 (operands[0], operands[1], operands[2]));
15014 (define_insn "mshf4_w"
15015 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15017 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15018 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
15019 (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
15022 return (TARGET_LITTLE_ENDIAN
15023 ? "mshfhi.w %N1, %N2, %0"
15024 : "mshflo.w %N1, %N2, %0");
15026 [(set_attr "type" "arith_media")
15027 (set (attr "highpart")
15028 (cond [(eq_attr "endian" "big") (const_string "ignore")]
15029 (const_string "user")))])
15031 (define_insn "mshf0_w"
15032 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15034 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15035 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
15036 (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
15039 return (TARGET_LITTLE_ENDIAN
15040 ? "mshflo.w %N1, %N2, %0"
15041 : "mshfhi.w %N1, %N2, %0");
15043 [(set_attr "type" "arith_media")
15044 (set (attr "highpart")
15045 (cond [(eq_attr "endian" "little") (const_string "ignore")]
15046 (const_string "user")))])
15048 (define_insn "mshflo_w_x"
15049 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15051 (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ")
15052 (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ"))
15053 (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
15055 "mshflo.w %N1, %N2, %0"
15056 [(set_attr "type" "arith_media")
15057 (set_attr "highpart" "ignore")])
15059 ;; These are useful to expand ANDs and as combiner patterns.
15060 (define_insn_and_split "mshfhi_l_di"
15061 [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
15062 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
15064 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
15065 (const_int -4294967296))))]
15068 mshfhi.l %N1, %N2, %0
15070 "TARGET_SHMEDIA && reload_completed
15071 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
15072 [(set (match_dup 3) (match_dup 4))
15073 (set (match_dup 5) (match_dup 6))]
15075 operands[3] = gen_lowpart (SImode, operands[0]);
15076 operands[4] = gen_highpart (SImode, operands[1]);
15077 operands[5] = gen_highpart (SImode, operands[0]);
15078 operands[6] = gen_highpart (SImode, operands[2]);
15080 [(set_attr "type" "arith_media")])
15082 (define_insn "*mshfhi_l_di_rev"
15083 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15084 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15085 (const_int -4294967296))
15086 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15089 "mshfhi.l %N2, %N1, %0"
15090 [(set_attr "type" "arith_media")])
15093 [(set (match_operand:DI 0 "arith_reg_dest" "")
15094 (ior:DI (zero_extend:DI (match_operand:SI 1
15095 "extend_reg_or_0_operand" ""))
15096 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "")
15097 (const_int -4294967296))))
15098 (clobber (match_operand:DI 3 "arith_reg_dest" ""))]
15102 emit_insn (gen_ashldi3_media (operands[3],
15103 simplify_gen_subreg (DImode, operands[1],
15106 emit_insn (gen_mshfhi_l_di (operands[0], operands[3], operands[2]));
15110 (define_insn "mshflo_l_di"
15111 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15112 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15113 (const_int 4294967295))
15114 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15118 "mshflo.l %N1, %N2, %0"
15119 [(set_attr "type" "arith_media")
15120 (set_attr "highpart" "ignore")])
15122 (define_insn "*mshflo_l_di_rev"
15123 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15124 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15126 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15127 (const_int 4294967295))))]
15130 "mshflo.l %N2, %N1, %0"
15131 [(set_attr "type" "arith_media")
15132 (set_attr "highpart" "ignore")])
15134 ;; Combiner pattern for trampoline initialization.
15135 (define_insn_and_split "*double_shori"
15136 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15137 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
15139 (match_operand:DI 2 "const_int_operand" "n")))]
15141 && ! (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)"
15143 "rtx_equal_p (operands[0], operands[1])"
15146 HOST_WIDE_INT v = INTVAL (operands[2]);
15148 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v >> 16)));
15149 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v & 65535)));
15152 [(set_attr "highpart" "ignore")])
15154 (define_insn "*mshflo_l_di_x"
15155 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15156 (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
15158 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15161 "mshflo.l %N1, %N2, %0"
15162 [(set_attr "type" "arith_media")
15163 (set_attr "highpart" "ignore")])
15165 (define_insn_and_split "concat_v2sf"
15166 [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
15167 ;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
15168 (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
15169 (match_operand:SF 2 "register_operand" "rZ,f,f")))]
15172 mshflo.l %N1, %N2, %0
15175 "TARGET_SHMEDIA && reload_completed
15176 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
15177 [(set (match_dup 3) (match_dup 1))
15178 (set (match_dup 4) (match_dup 2))]
15180 operands[3] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 0);
15181 operands[4] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 4);
15183 [(set_attr "type" "arith_media")
15184 (set_attr "highpart" "ignore")])
15186 (define_insn "*mshflo_l_di_x_rev"
15187 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15188 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15191 (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
15193 "mshflo.l %N2, %N1, %0"
15194 [(set_attr "type" "arith_media")
15195 (set_attr "highpart" "ignore")])
15197 (define_insn "ashlv2si3"
15198 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15199 (ashift:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
15200 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15202 "mshlld.l %1, %2, %0"
15203 [(set_attr "type" "arith_media")
15204 (set_attr "highpart" "depend")])
15207 [(set (match_operand 0 "any_register_operand" "")
15208 (match_operator 3 "shift_operator"
15209 [(match_operand 1 "any_register_operand" "")
15210 (match_operand 2 "shift_count_reg_operand" "")]))]
15211 "TARGET_SHMEDIA && ! register_operand (operands[2], VOIDmode)"
15212 [(set (match_dup 0) (match_dup 3))]
15214 rtx count = operands[2];
15215 enum machine_mode outer_mode = GET_MODE (operands[2]), inner_mode;
15217 while (GET_CODE (count) == ZERO_EXTEND || GET_CODE (count) == SIGN_EXTEND
15218 || (GET_CODE (count) == SUBREG && SUBREG_BYTE (count) == 0)
15219 || GET_CODE (count) == TRUNCATE)
15220 count = XEXP (count, 0);
15221 inner_mode = GET_MODE (count);
15222 count = simplify_gen_subreg (outer_mode, count, inner_mode,
15223 subreg_lowpart_offset (outer_mode, inner_mode));
15224 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), GET_MODE (operands[3]),
15225 operands[1], count);
15228 (define_insn "ashlv4hi3"
15229 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15230 (ashift:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15231 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15233 "mshlld.w %1, %2, %0"
15234 [(set_attr "type" "arith_media")
15235 (set_attr "highpart" "depend")])
15237 (define_insn "lshrv2si3"
15238 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15239 (lshiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
15240 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15242 "mshlrd.l %1, %2, %0"
15243 [(set_attr "type" "arith_media")
15244 (set_attr "highpart" "depend")])
15246 (define_insn "lshrv4hi3"
15247 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15248 (lshiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15249 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15251 "mshlrd.w %1, %2, %0"
15252 [(set_attr "type" "arith_media")
15253 (set_attr "highpart" "depend")])
15255 (define_insn "subv2si3"
15256 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15257 (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15258 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15260 "msub.l %N1, %2, %0"
15261 [(set_attr "type" "arith_media")
15262 (set_attr "highpart" "depend")])
15264 (define_insn "subv4hi3"
15265 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15266 (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15267 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15269 "msub.w %N1, %2, %0"
15270 [(set_attr "type" "arith_media")
15271 (set_attr "highpart" "depend")])
15273 (define_insn_and_split "subv2hi3"
15274 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
15275 (minus:V2HI (match_operand:V2HI 1 "arith_reg_or_0_operand" "rZ")
15276 (match_operand:V2HI 2 "arith_reg_operand" "r")))]
15282 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
15283 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
15284 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
15285 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
15286 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
15288 emit_insn (gen_subv4hi3 (v4hi_dst, src0, src1));
15289 emit_insn (gen_truncdisi2 (si_dst, di_dst));
15292 [(set_attr "highpart" "must_split")])
15294 (define_insn "sssubv2si3"
15295 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15296 (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15297 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15299 "msubs.l %N1, %2, %0"
15300 [(set_attr "type" "mcmp_media")
15301 (set_attr "highpart" "depend")])
15303 (define_insn "ussubv8qi3"
15304 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15305 (us_minus:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
15306 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
15308 "msubs.ub %N1, %2, %0"
15309 [(set_attr "type" "mcmp_media")
15310 (set_attr "highpart" "depend")])
15312 (define_insn "sssubv4hi3"
15313 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15314 (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15315 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15317 "msubs.w %N1, %2, %0"
15318 [(set_attr "type" "mcmp_media")
15319 (set_attr "highpart" "depend")])
15321 ;; -------------------------------------------------------------------------
15322 ;; Floating Point Intrinsics
15323 ;; -------------------------------------------------------------------------
15325 (define_insn "fcosa_s"
15326 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15327 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
15331 [(set_attr "type" "atrans_media")])
15333 (define_insn "fsina_s"
15334 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15335 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
15339 [(set_attr "type" "atrans_media")])
15341 (define_insn "fipr"
15342 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15343 (plus:SF (plus:SF (vec_select:SF (mult:V4SF (match_operand:V4SF 1
15344 "fp_arith_reg_operand" "f")
15345 (match_operand:V4SF 2
15346 "fp_arith_reg_operand" "f"))
15347 (parallel [(const_int 0)]))
15348 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15349 (parallel [(const_int 1)])))
15350 (plus:SF (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15351 (parallel [(const_int 2)]))
15352 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15353 (parallel [(const_int 3)])))))]
15355 "fipr.s %1, %2, %0"
15356 [(set_attr "type" "fparith_media")])
15358 (define_insn "fsrra_s"
15359 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15360 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "f")]
15364 [(set_attr "type" "atrans_media")])
15366 (define_insn "ftrv"
15367 [(set (match_operand:V4SF 0 "fp_arith_reg_operand" "=f")
15371 (vec_select:V4SF (match_operand:V16SF 1 "fp_arith_reg_operand" "f")
15372 (parallel [(const_int 0) (const_int 5)
15373 (const_int 10) (const_int 15)]))
15374 (match_operand:V4SF 2 "fp_arith_reg_operand" "f"))
15376 (vec_select:V4SF (match_dup 1)
15377 (parallel [(const_int 4) (const_int 9)
15378 (const_int 14) (const_int 3)]))
15379 (vec_select:V4SF (match_dup 2)
15380 (parallel [(const_int 1) (const_int 2)
15381 (const_int 3) (const_int 0)]))))
15384 (vec_select:V4SF (match_dup 1)
15385 (parallel [(const_int 8) (const_int 13)
15386 (const_int 2) (const_int 7)]))
15387 (vec_select:V4SF (match_dup 2)
15388 (parallel [(const_int 2) (const_int 3)
15389 (const_int 0) (const_int 1)])))
15391 (vec_select:V4SF (match_dup 1)
15392 (parallel [(const_int 12) (const_int 1)
15393 (const_int 6) (const_int 11)]))
15394 (vec_select:V4SF (match_dup 2)
15395 (parallel [(const_int 3) (const_int 0)
15396 (const_int 1) (const_int 2)]))))))]
15398 "ftrv.s %1, %2, %0"
15399 [(set_attr "type" "fparith_media")])
15401 (define_insn "ldhi_l"
15402 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15404 (mem:SI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
15407 (plus:SI (and:SI (match_dup 1) (const_int 3)) (const_int 1))
15411 [(set_attr "type" "load_media")])
15413 (define_insn "ldhi_q"
15414 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15416 (mem:DI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
15419 (plus:SI (and:SI (match_dup 1) (const_int 7)) (const_int 1))
15423 [(set_attr "type" "load_media")])
15425 (define_insn_and_split "*ldhi_q_comb0"
15426 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15428 (mem:DI (plus:SI (ior:SI (plus:SI
15429 (match_operand:SI 1 "register_operand" "r")
15430 (match_operand:SI 2 "ua_offset" "I06"))
15433 (plus:SI (and:SI (match_dup 1) (const_int 7))
15436 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
15441 emit_insn (gen_ldhi_q (operands[0],
15442 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15446 (define_insn_and_split "*ldhi_q_comb1"
15447 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15449 (mem:DI (plus:SI (ior:SI (plus:SI
15450 (match_operand:SI 1 "register_operand" "r")
15451 (match_operand:SI 2 "ua_offset" "I06"))
15454 (plus:SI (and:SI (plus:SI (match_dup 1)
15455 (match_operand:SI 3 "ua_offset" "I06"))
15459 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
15460 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
15465 emit_insn (gen_ldhi_q (operands[0],
15466 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15470 (define_insn "ldlo_l"
15471 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15473 (mem:SI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
15475 (minus:SI (const_int 4) (and:SI (match_dup 1) (const_int 3)))
15476 (and:SI (match_dup 1) (const_int 3))))]
15479 [(set_attr "type" "load_media")])
15481 (define_insn "ldlo_q"
15482 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15484 (mem:DI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
15486 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
15487 (and:SI (match_dup 1) (const_int 7))))]
15490 [(set_attr "type" "load_media")])
15492 (define_insn_and_split "*ldlo_q_comb0"
15493 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15495 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
15496 (match_operand:SI 2 "ua_offset" "I06"))
15498 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
15499 (and:SI (match_dup 1) (const_int 7))))]
15500 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
15505 emit_insn (gen_ldlo_q (operands[0],
15506 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15510 (define_insn_and_split "*ldlo_q_comb1"
15511 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15513 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
15514 (match_operand:SI 2 "ua_offset" "I06"))
15516 (minus:SI (const_int 8)
15517 (and:SI (plus:SI (match_dup 1)
15518 (match_operand:SI 3 "ua_offset" "I06"))
15520 (and:SI (plus:SI (match_dup 1) (match_dup 3)) (const_int 7))))]
15521 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
15522 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
15527 emit_insn (gen_ldlo_q (operands[0],
15528 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15532 (define_insn "sthi_l"
15533 [(set (zero_extract:SI
15534 (mem:SI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
15537 (plus:SI (and:SI (match_dup 0) (const_int 3)) (const_int 1))
15539 (match_operand:SI 1 "arith_reg_operand" "r"))]
15542 [(set_attr "type" "ustore_media")])
15544 ;; All unaligned stores are considered to be 'narrow' because they typically
15545 ;; operate on less that a quadword, and when they operate on a full quadword,
15546 ;; the vanilla store high / store low sequence will cause a stall if not
15547 ;; scheduled apart.
15548 (define_insn "sthi_q"
15549 [(set (zero_extract:DI
15550 (mem:DI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
15553 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
15555 (match_operand:DI 1 "arith_reg_operand" "r"))]
15558 [(set_attr "type" "ustore_media")])
15560 (define_insn_and_split "*sthi_q_comb0"
15561 [(set (zero_extract:DI
15562 (mem:DI (plus:SI (ior:SI (plus:SI
15563 (match_operand:SI 0 "register_operand" "r")
15564 (match_operand:SI 1 "ua_offset" "I06"))
15567 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
15569 (match_operand:DI 2 "arith_reg_operand" "r"))]
15570 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
15575 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15580 (define_insn_and_split "*sthi_q_comb1"
15581 [(set (zero_extract:DI
15582 (mem:DI (plus:SI (ior:SI (plus:SI
15583 (match_operand:SI 0 "register_operand" "r")
15584 (match_operand:SI 1 "ua_offset" "I06"))
15587 (plus:SI (and:SI (plus:SI (match_dup 0)
15588 (match_operand:SI 2 "ua_offset" "I06"))
15592 (match_operand:DI 3 "arith_reg_operand" "r"))]
15593 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & -8)
15594 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
15599 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15604 ;; This is highpart user because the address is used as full 64 bit.
15605 (define_insn "stlo_l"
15606 [(set (zero_extract:SI
15607 (mem:SI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
15609 (minus:SI (const_int 4) (and:SI (match_dup 0) (const_int 3)))
15610 (and:SI (match_dup 0) (const_int 3)))
15611 (match_operand:SI 1 "arith_reg_operand" "r"))]
15614 [(set_attr "type" "ustore_media")])
15616 (define_insn "stlo_q"
15617 [(set (zero_extract:DI
15618 (mem:DI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
15620 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
15621 (and:SI (match_dup 0) (const_int 7)))
15622 (match_operand:DI 1 "arith_reg_operand" "r"))]
15625 [(set_attr "type" "ustore_media")])
15627 (define_insn_and_split "*stlo_q_comb0"
15628 [(set (zero_extract:DI
15629 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
15630 (match_operand:SI 1 "ua_offset" "I06"))
15632 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
15633 (and:SI (match_dup 0) (const_int 7)))
15634 (match_operand:DI 2 "arith_reg_operand" "r"))]
15635 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
15640 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15645 (define_insn_and_split "*stlo_q_comb1"
15646 [(set (zero_extract:DI
15647 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
15648 (match_operand:SI 1 "ua_offset" "I06"))
15650 (minus:SI (const_int 8)
15651 (and:SI (plus:SI (match_dup 0)
15652 (match_operand:SI 2 "ua_offset" "I06"))
15654 (and:SI (plus:SI (match_dup 0) (match_dup 2)) (const_int 7)))
15655 (match_operand:DI 3 "arith_reg_operand" "r"))]
15656 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
15661 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15666 (define_insn "ldhi_l64"
15667 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15669 (mem:SI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
15672 (plus:DI (and:DI (match_dup 1) (const_int 3)) (const_int 1))
15676 [(set_attr "type" "load_media")])
15678 (define_insn "ldhi_q64"
15679 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15681 (mem:DI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
15684 (plus:DI (and:DI (match_dup 1) (const_int 7)) (const_int 1))
15688 [(set_attr "type" "load_media")])
15690 (define_insn "ldlo_l64"
15691 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15693 (mem:SI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
15695 (minus:DI (const_int 4) (and:DI (match_dup 1) (const_int 3)))
15696 (and:DI (match_dup 1) (const_int 3))))]
15699 [(set_attr "type" "load_media")])
15701 (define_insn "ldlo_q64"
15702 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15704 (mem:DI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
15706 (minus:DI (const_int 8) (and:DI (match_dup 1) (const_int 7)))
15707 (and:DI (match_dup 1) (const_int 7))))]
15710 [(set_attr "type" "load_media")])
15712 (define_insn "sthi_l64"
15713 [(set (zero_extract:SI
15714 (mem:SI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
15717 (plus:DI (and:DI (match_dup 0) (const_int 3)) (const_int 1))
15719 (match_operand:SI 1 "arith_reg_operand" "r"))]
15722 [(set_attr "type" "ustore_media")])
15724 (define_insn "sthi_q64"
15725 [(set (zero_extract:DI
15726 (mem:DI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
15729 (plus:DI (and:DI (match_dup 0) (const_int 7)) (const_int 1))
15731 (match_operand:DI 1 "arith_reg_operand" "r"))]
15734 [(set_attr "type" "ustore_media")])
15736 (define_insn "stlo_l64"
15737 [(set (zero_extract:SI
15738 (mem:SI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
15740 (minus:DI (const_int 4) (and:DI (match_dup 0) (const_int 3)))
15741 (and:DI (match_dup 0) (const_int 3)))
15742 (match_operand:SI 1 "arith_reg_operand" "r"))]
15745 [(set_attr "type" "ustore_media")])
15747 (define_insn "stlo_q64"
15748 [(set (zero_extract:DI
15749 (mem:DI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
15751 (minus:DI (const_int 8) (and:DI (match_dup 0) (const_int 7)))
15752 (and:DI (match_dup 0) (const_int 7)))
15753 (match_operand:DI 1 "arith_reg_operand" "r"))]
15756 [(set_attr "type" "ustore_media")])
15759 [(set (match_operand:QI 0 "arith_reg_dest" "=r")
15760 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15764 [(set_attr "type" "arith_media")])
15766 (define_insn "nsbsi"
15767 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15769 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15773 [(set_attr "type" "arith_media")])
15775 (define_insn "nsbdi"
15776 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15778 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15782 [(set_attr "type" "arith_media")])
15784 (define_expand "ffsdi2"
15785 [(set (match_operand:DI 0 "arith_reg_dest" "")
15786 (ffs:DI (match_operand:DI 1 "arith_reg_operand" "")))]
15789 rtx scratch = gen_reg_rtx (DImode);
15792 emit_insn (gen_adddi3 (scratch, operands[1], constm1_rtx));
15793 emit_insn (gen_xordi3 (scratch, operands[1], scratch));
15794 emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
15795 emit_insn (gen_nsbdi (scratch, scratch));
15796 emit_insn (gen_adddi3 (scratch, scratch, GEN_INT (-64)));
15797 emit_insn (gen_movdicc_false (scratch, operands[1], const0_rtx, scratch));
15798 last = emit_insn (gen_subdi3 (operands[0], const0_rtx, scratch));
15799 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (DImode, operands[0]));
15804 (define_expand "ffssi2"
15805 [(set (match_operand:SI 0 "arith_reg_dest" "")
15806 (ffs:SI (match_operand:SI 1 "arith_reg_operand" "")))]
15809 rtx scratch = gen_reg_rtx (SImode);
15810 rtx discratch = gen_reg_rtx (DImode);
15813 emit_insn (gen_adddi3 (discratch,
15814 simplify_gen_subreg (DImode, operands[1], SImode, 0),
15816 emit_insn (gen_andcdi3 (discratch,
15817 simplify_gen_subreg (DImode, operands[1], SImode, 0),
15819 emit_insn (gen_nsbsi (scratch, discratch));
15820 last = emit_insn (gen_subsi3 (operands[0],
15821 force_reg (SImode, GEN_INT (63)), scratch));
15822 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (SImode, operands[0]));
15827 (define_insn "byterev"
15828 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15829 (vec_select:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
15830 (parallel [(const_int 7) (const_int 6) (const_int 5)
15831 (const_int 4) (const_int 3) (const_int 2)
15832 (const_int 1) (const_int 0)])))]
15835 [(set_attr "type" "arith_media")])
15837 ;; In user mode, the "pref" instruction will raise a RADDERR exception
15838 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
15839 ;; implementation of __builtin_prefetch for VxWorks RTPs.
15840 (define_expand "prefetch"
15841 [(prefetch (match_operand 0 "address_operand" "")
15842 (match_operand:SI 1 "const_int_operand" "")
15843 (match_operand:SI 2 "const_int_operand" ""))]
15844 "(TARGET_SH2A || TARGET_SH3 || TARGET_SH5)
15845 && (TARGET_SHMEDIA || ! TARGET_VXWORKS_RTP)")
15847 (define_insn "*prefetch"
15848 [(prefetch (match_operand:SI 0 "register_operand" "r")
15849 (match_operand:SI 1 "const_int_operand" "n")
15850 (match_operand:SI 2 "const_int_operand" "n"))]
15851 "(TARGET_SH2A || TARGET_SH3 || TARGET_SHCOMPACT) && ! TARGET_VXWORKS_RTP"
15853 [(set_attr "type" "other")])
15855 (define_insn "*prefetch_media"
15856 [(prefetch (match_operand:QI 0 "address_operand" "p")
15857 (match_operand:SI 1 "const_int_operand" "n")
15858 (match_operand:SI 2 "const_int_operand" "n"))]
15861 operands[0] = gen_rtx_MEM (QImode, operands[0]);
15862 output_asm_insn ("ld%M0.b %m0,r63", operands);
15865 [(set_attr "type" "other")])
15867 (define_insn "alloco_i"
15868 [(set (mem:BLK (match_operand:QI 0 "cache_address_operand" "p"))
15869 (unspec:BLK [(const_int 0)] UNSPEC_ALLOCO))]
15874 if (GET_CODE (operands[0]) == PLUS)
15876 xops[0] = XEXP (operands[0], 0);
15877 xops[1] = XEXP (operands[0], 1);
15881 xops[0] = operands[0];
15882 xops[1] = const0_rtx;
15884 output_asm_insn ("alloco %0, %1", xops);
15887 [(set_attr "type" "other")])
15890 [(set (match_operand 0 "any_register_operand" "")
15891 (match_operand 1 "" ""))]
15892 "TARGET_SHMEDIA && reload_completed"
15893 [(set (match_dup 0) (match_dup 1))]
15897 for_each_rtx (&operands[1], shmedia_cleanup_truncate, &n_changes);
15902 ;; -------------------------------------------------------------------------
15903 ;; Stack Protector Patterns
15904 ;; -------------------------------------------------------------------------
15906 (define_expand "stack_protect_set"
15907 [(set (match_operand 0 "memory_operand" "")
15908 (match_operand 1 "memory_operand" ""))]
15911 if (TARGET_SHMEDIA)
15913 if (TARGET_SHMEDIA64)
15914 emit_insn (gen_stack_protect_set_di_media (operands[0], operands[1]));
15916 emit_insn (gen_stack_protect_set_si_media (operands[0], operands[1]));
15919 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
15924 (define_insn "stack_protect_set_si"
15925 [(set (match_operand:SI 0 "memory_operand" "=m")
15926 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15927 (set (match_scratch:SI 2 "=&r") (const_int 0))]
15930 return "mov.l %1,%2" "\n"
15931 " mov.l %2,%0" "\n"
15934 [(set_attr "type" "other")
15935 (set_attr "length" "6")])
15937 (define_insn "stack_protect_set_si_media"
15938 [(set (match_operand:SI 0 "memory_operand" "=m")
15939 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15940 (set (match_scratch:SI 2 "=&r") (const_int 0))]
15943 return "ld%M1.l %m1,%2" "\n"
15944 " st%M0.l %m0,%2" "\n"
15947 [(set_attr "type" "other")
15948 (set_attr "length" "12")])
15950 (define_insn "stack_protect_set_di_media"
15951 [(set (match_operand:DI 0 "memory_operand" "=m")
15952 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15953 (set (match_scratch:DI 2 "=&r") (const_int 0))]
15956 return "ld%M1.q %m1,%2" "\n"
15957 " st%M0.q %m0,%2" "\n"
15960 [(set_attr "type" "other")
15961 (set_attr "length" "12")])
15963 (define_expand "stack_protect_test"
15964 [(match_operand 0 "memory_operand" "")
15965 (match_operand 1 "memory_operand" "")
15966 (match_operand 2 "" "")]
15969 if (TARGET_SHMEDIA)
15971 rtx tmp = gen_reg_rtx (GET_MODE (operands[0]));
15974 test = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
15975 if (TARGET_SHMEDIA64)
15977 emit_insn (gen_stack_protect_test_di_media (tmp, operands[0],
15979 emit_jump_insn (gen_cbranchdi4 (test, tmp, const0_rtx, operands[2]));
15983 emit_insn (gen_stack_protect_test_si_media (tmp, operands[0],
15985 emit_jump_insn (gen_cbranchsi4 (test, tmp, const0_rtx, operands[2]));
15990 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
15991 emit_jump_insn (gen_branch_true (operands[2]));
15997 (define_insn "stack_protect_test_si"
15998 [(set (reg:SI T_REG)
15999 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
16000 (match_operand:SI 1 "memory_operand" "m")]
16002 (set (match_scratch:SI 2 "=&r") (const_int 0))
16003 (set (match_scratch:SI 3 "=&r") (const_int 0))]
16006 return "mov.l %0,%2" "\n"
16007 " mov.l %1,%3" "\n"
16008 " cmp/eq %2,%3" "\n"
16012 [(set_attr "type" "other")
16013 (set_attr "length" "10")])
16015 (define_insn "stack_protect_test_si_media"
16016 [(set (match_operand:SI 0 "register_operand" "=&r")
16017 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
16018 (match_operand:SI 2 "memory_operand" "m")]
16020 (set (match_scratch:SI 3 "=&r") (const_int 0))]
16023 return "ld%M1.l %m1,%0" "\n"
16024 " ld%M2.l %m2,%3" "\n"
16025 " cmpeq %0,%3,%0" "\n"
16028 [(set_attr "type" "other")
16029 (set_attr "length" "16")])
16031 (define_insn "stack_protect_test_di_media"
16032 [(set (match_operand:DI 0 "register_operand" "=&r")
16033 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
16034 (match_operand:DI 2 "memory_operand" "m")]
16036 (set (match_scratch:DI 3 "=&r") (const_int 0))]
16039 return "ld%M1.q %m1,%0" "\n"
16040 " ld%M2.q %m2,%3" "\n"
16041 " cmpeq %0,%3,%0" "\n"
16044 [(set_attr "type" "other")
16045 (set_attr "length" "16")])
16047 ;; -------------------------------------------------------------------------
16048 ;; Atomic operations
16049 ;; -------------------------------------------------------------------------
16051 (include "sync.md")