| blob | e718a82e40b5884d361a1c58608581fbc3c3cc3e |
1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; any later version.
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
34 ;; adds/subs.
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
48 ;; CONSTANTS
49 ;; ----------------------------------------------------------------------
51 (define_constants
52 [(UNSPEC_INCDEC 0)
53 (UNSPEC_MONITOR 1)])
55 (define_constants
56 [(UNSPEC_MOVMD 100)
57 (UNSPEC_STPCPY 101)])
59 (define_constants
60 [(R0_REG 0)
61 (SC_REG 3)
62 (COUNTER_REG 4)
63 (SOURCE_REG 5)
64 (DESTINATION_REG 6)
65 (HFP_REG 6)
66 (SP_REG 7)
67 (MAC_REG 8)
68 (AP_REG 9)
69 (RAP_REG 10)
70 (FP_REG 11)])
72 ;; ----------------------------------------------------------------------
73 ;; ATTRIBUTES
74 ;; ----------------------------------------------------------------------
76 (define_attr "cpu" "h8300,h8300h"
77 (const (symbol_ref "cpu_type")))
79 (define_attr "type" "branch,arith,bitbranch,call"
80 (const_string "arith"))
82 (define_attr "length_table" "none,addb,addw,addl,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
83 (const_string "none"))
85 ;; The size of instructions in bytes.
87 (define_attr "length" ""
88 (cond [(eq_attr "type" "branch")
89 ;; In a forward delayed branch, (pc) represents the end of the
90 ;; delay sequence, not the end of the branch itself.
91 (if_then_else (and (ge (minus (match_dup 0) (pc))
92 (const_int -126))
93 (le (plus (minus (match_dup 0) (pc))
94 (symbol_ref "DELAY_SLOT_LENGTH (insn)"))
95 (const_int 126)))
96 (const_int 2)
97 (if_then_else (and (eq_attr "cpu" "h8300h")
98 (and (ge (minus (pc) (match_dup 0))
99 (const_int -32000))
100 (le (minus (pc) (match_dup 0))
101 (const_int 32000))))
102 (const_int 4)
103 (const_int 6)))
104 (eq_attr "type" "bitbranch")
105 (if_then_else
106 (and (ge (minus (match_dup 0) (pc))
107 (const_int -126))
108 (le (minus (match_dup 0) (pc))
109 (const_int 126)))
110 (plus
111 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
112 (const_int 2))
113 (if_then_else
114 (and (eq_attr "cpu" "h8300h")
115 (and (ge (minus (pc) (match_dup 0))
116 (const_int -32000))
117 (le (minus (pc) (match_dup 0))
118 (const_int 32000))))
119 (plus
120 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
121 (const_int 4))
122 (plus
123 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
124 (const_int 6))))
125 (eq_attr "length_table" "!none")
126 (symbol_ref "h8300_insn_length_from_table (insn, operands)")]
127 (const_int 200)))
129 ;; Condition code settings.
130 ;;
131 ;; none - insn does not affect cc
132 ;; none_0hit - insn does not affect cc but it does modify operand 0
133 ;; This attribute is used to keep track of when operand 0 changes.
134 ;; See the description of NOTICE_UPDATE_CC for more info.
135 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
136 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
137 ;; compare - compare instruction
138 ;; clobber - value of cc is unknown
140 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
141 (const_string "clobber"))
143 ;; Type of delay slot. NONE means the instruction has no delay slot.
144 ;; JUMP means it is an unconditional jump that (if short enough)
145 ;; could be implemented using bra/s.
146 (define_attr "delay_slot" "none,jump"
147 (const_string "none"))
149 ;; "yes" if the instruction can be put into a delay slot. It's not
150 ;; entirely clear that jsr is not valid in delay slots, but it
151 ;; definitely doesn't have the effect of causing the called function
152 ;; to return to the target of the delayed branch.
153 (define_attr "can_delay" "no,yes"
154 (cond [(eq_attr "type" "branch,bitbranch,call")
155 (const_string "no")
156 (ne (symbol_ref "get_attr_length (insn)") (const_int 2))
157 (const_string "no")]
158 (const_string "yes")))
160 ;; Only allow jumps to have a delay slot if we think they might
161 ;; be short enough. This is just an optimisation: we don't know
162 ;; for certain whether they will be or not.
163 (define_delay (and (eq_attr "delay_slot" "jump")
164 (eq (symbol_ref "get_attr_length (insn)") (const_int 2)))
165 [(eq_attr "can_delay" "yes")
166 (nil)
167 (nil)])
169 ;; Provide the maximum length of an assembly instruction in an asm
170 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
172 (define_asm_attributes
173 [(set (attr "length")
174 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
175 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
176 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
177 (const_int 14)))])
178 \f
179 ;; ----------------------------------------------------------------------
180 ;; MOVE INSTRUCTIONS
181 ;; ----------------------------------------------------------------------
183 ;; movqi
185 (define_insn "*movqi_h8300"
186 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
187 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
188 "TARGET_H8300
189 && (register_operand (operands[0], QImode)
190 || register_operand (operands[1], QImode))"
191 "@
192 sub.b %X0,%X0
193 mov.b %R1,%X0
194 mov.b %X1,%R0
195 mov.b %R1,%X0
196 mov.b %R1,%X0
197 mov.b %X1,%R0"
198 [(set_attr "length" "2,2,2,2,4,4")
199 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
201 (define_insn "*movqi_h8300hs"
202 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
203 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
204 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
205 && (register_operand (operands[0], QImode)
206 || register_operand (operands[1], QImode))"
207 "@
208 sub.b %X0,%X0
209 mov.b %R1,%X0
210 mov.b %X1,%R0
211 mov.b %R1,%X0
212 mov.b %R1,%X0
213 mov.b %X1,%R0"
214 [(set (attr "length")
215 (symbol_ref "compute_mov_length (operands)"))
216 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
218 (define_insn "*movqi_h8sx"
219 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
220 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
221 "TARGET_H8300SX"
222 "@
223 mov.b %X1,%X0
224 mov.b %X1,%X0"
225 [(set_attr "length_table" "mov_imm4,movb")
226 (set_attr "cc" "set_znv")])
228 (define_expand "movqi"
229 [(set (match_operand:QI 0 "general_operand_dst" "")
230 (match_operand:QI 1 "general_operand_src" ""))]
231 ""
232 "
233 {
234 /* One of the ops has to be in a register. */
235 if (!TARGET_H8300SX
236 && !register_operand (operand0, QImode)
237 && !register_operand (operand1, QImode))
238 {
239 operands[1] = copy_to_mode_reg (QImode, operand1);
240 }
241 }")
243 (define_insn "movstrictqi"
244 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
245 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
246 ""
247 "@
248 sub.b %X0,%X0
249 mov.b %X1,%X0"
250 [(set_attr "length" "2,*")
251 (set_attr "length_table" "*,movb")
252 (set_attr "cc" "set_zn,set_znv")])
254 ;; movhi
256 (define_insn "*movhi_h8300"
257 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
258 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
259 "TARGET_H8300
260 && (register_operand (operands[0], HImode)
261 || register_operand (operands[1], HImode))
262 && !(GET_CODE (operands[0]) == MEM
263 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
264 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
265 && GET_CODE (operands[1]) == REG
266 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
267 "@
268 sub.w %T0,%T0
269 mov.w %T1,%T0
270 mov.w %T1,%T0
271 mov.w %T1,%T0
272 mov.w %T1,%T0
273 mov.w %T1,%T0"
274 [(set (attr "length")
275 (symbol_ref "compute_mov_length (operands)"))
276 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
278 (define_insn "*movhi_h8300hs"
279 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
280 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
281 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
282 && (register_operand (operands[0], HImode)
283 || register_operand (operands[1], HImode))"
284 "@
285 sub.w %T0,%T0
286 mov.w %T1,%T0
287 mov.w %T1,%T0
288 mov.w %T1,%T0
289 mov.w %T1,%T0
290 mov.w %T1,%T0"
291 [(set (attr "length")
292 (symbol_ref "compute_mov_length (operands)"))
293 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
295 (define_insn "*movhi_h8sx"
296 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
297 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
298 "TARGET_H8300SX"
299 "@
300 sub.w %T0,%T0
301 mov.w %T1,%T0
302 mov.w %T1,%T0
303 mov.w %T1,%T0
304 mov.w %T1,%T0"
305 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
306 (set_attr "length" "2,2,*,*,*")
307 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
309 (define_expand "movhi"
310 [(set (match_operand:HI 0 "general_operand_dst" "")
311 (match_operand:HI 1 "general_operand_src" ""))]
312 ""
313 "
314 {
315 /* One of the ops has to be in a register. */
316 if (!register_operand (operand1, HImode)
317 && !register_operand (operand0, HImode))
318 {
319 operands[1] = copy_to_mode_reg (HImode, operand1);
320 }
321 }")
323 (define_insn "movstricthi"
324 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
325 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
326 ""
327 "@
328 sub.w %T0,%T0
329 mov.w %T1,%T0
330 mov.w %T1,%T0"
331 [(set_attr "length" "2,2,*")
332 (set_attr "length_table" "*,*,movw")
333 (set_attr "cc" "set_zn,set_znv,set_znv")])
335 ;; movsi
337 (define_expand "movsi"
338 [(set (match_operand:SI 0 "general_operand_dst" "")
339 (match_operand:SI 1 "general_operand_src" ""))]
340 ""
341 "
342 {
343 if (TARGET_H8300)
344 {
345 if (h8300_expand_movsi (operands))
346 DONE;
347 }
348 else if (!TARGET_H8300SX)
349 {
350 /* One of the ops has to be in a register. */
351 if (!register_operand (operand1, SImode)
352 && !register_operand (operand0, SImode))
353 {
354 operands[1] = copy_to_mode_reg (SImode, operand1);
355 }
356 }
357 }")
359 (define_insn "*movsi_h8300"
360 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
361 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
362 "TARGET_H8300
363 && (register_operand (operands[0], SImode)
364 || register_operand (operands[1], SImode))"
365 "*
366 {
367 unsigned int rn = -1;
368 switch (which_alternative)
369 {
370 case 0:
371 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
372 case 1:
373 if (REGNO (operands[0]) < REGNO (operands[1]))
374 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
375 else
376 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
377 case 2:
378 /* Make sure we don't trample the register we index with. */
379 if (GET_CODE (operands[1]) == MEM)
380 {
381 rtx inside = XEXP (operands[1], 0);
382 if (REG_P (inside))
383 {
384 rn = REGNO (inside);
385 }
386 else if (GET_CODE (inside) == PLUS)
387 {
388 rtx lhs = XEXP (inside, 0);
389 rtx rhs = XEXP (inside, 1);
390 if (REG_P (lhs)) rn = REGNO (lhs);
391 if (REG_P (rhs)) rn = REGNO (rhs);
392 }
393 }
394 if (rn == REGNO (operands[0]))
395 {
396 /* Move the second word first. */
397 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
398 }
399 else
400 {
401 if (GET_CODE (operands[1]) == CONST_INT)
402 {
403 /* If either half is zero, use sub.w to clear that
404 half. */
405 if ((INTVAL (operands[1]) & 0xffff) == 0)
406 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
407 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
408 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
409 /* If the upper half and the lower half are the same,
410 copy one half to the other. */
411 if ((INTVAL (operands[1]) & 0xffff)
412 == ((INTVAL (operands[1]) >> 16) & 0xffff))
413 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
414 }
415 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
416 }
417 case 3:
418 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
419 case 4:
420 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
421 case 5:
422 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
423 default:
424 abort ();
425 }
426 }"
427 [(set (attr "length")
428 (symbol_ref "compute_mov_length (operands)"))])
430 (define_insn "*movsi_h8300hs"
431 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
432 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
433 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
434 && (register_operand (operands[0], SImode)
435 || register_operand (operands[1], SImode))
436 && !(GET_CODE (operands[0]) == MEM
437 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
438 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
439 && GET_CODE (operands[1]) == REG
440 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
441 "*
442 {
443 switch (which_alternative)
444 {
445 case 0:
446 return \"sub.l %S0,%S0\";
447 case 7:
448 return \"clrmac\";
449 case 8:
450 return \"clrmac\;ldmac %1,macl\";
451 case 9:
452 return \"stmac macl,%0\";
453 default:
454 if (GET_CODE (operands[1]) == CONST_INT)
455 {
456 int val = INTVAL (operands[1]);
458 /* Look for constants which can be made by adding an 8-bit
459 number to zero in one of the two low bytes. */
460 if (val == (val & 0xff))
461 {
462 operands[1] = GEN_INT ((char) val & 0xff);
463 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
464 }
466 if (val == (val & 0xff00))
467 {
468 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
469 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
470 }
472 /* Look for constants that can be obtained by subs, inc, and
473 dec to 0. */
474 switch (val & 0xffffffff)
475 {
476 case 0xffffffff:
477 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
478 case 0xfffffffe:
479 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
480 case 0xfffffffc:
481 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
483 case 0x0000ffff:
484 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
485 case 0x0000fffe:
486 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
488 case 0xffff0000:
489 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
490 case 0xfffe0000:
491 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
493 case 0x00010000:
494 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
495 case 0x00020000:
496 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
497 }
498 }
499 }
500 return \"mov.l %S1,%S0\";
501 }"
502 [(set (attr "length")
503 (symbol_ref "compute_mov_length (operands)"))
504 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
506 (define_insn "*movsi_h8sx"
507 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
508 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
509 "TARGET_H8300SX"
510 "@
511 sub.l %S0,%S0
512 mov.l %S1,%S0
513 mov.l %S1,%S0
514 mov.l %S1,%S0
515 clrmac
516 clrmac\;ldmac %1,macl
517 stmac macl,%0"
518 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
519 (set_attr "length" "2,2,*,*,2,6,4")
520 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
522 (define_insn "*movsf_h8sx"
523 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
524 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
525 "TARGET_H8300SX"
526 "@
527 sub.l %S0,%S0
528 mov.l %S1,%S0"
529 [(set_attr "length" "2,*")
530 (set_attr "length_table" "*,movl")
531 (set_attr "cc" "set_zn,set_znv")])
533 ;; Implement block moves using movmd. Defining movmemsi allows the full
534 ;; range of constant lengths (up to 0x40000 bytes when using movmd.l).
535 ;; See h8sx_emit_movmd for details.
536 (define_expand "movmemsi"
537 [(use (match_operand:BLK 0 "memory_operand" ""))
538 (use (match_operand:BLK 1 "memory_operand" ""))
539 (use (match_operand:SI 2 "" ""))
540 (use (match_operand:SI 3 "const_int_operand" ""))]
541 "TARGET_H8300SX"
542 {
543 if (h8sx_emit_movmd (operands[0], operands[1], operands[2],
544 INTVAL (operands[3])))
545 DONE;
546 else
547 FAIL;
548 })
550 ;; Expander for generating movmd insns. Operand 0 is the destination
551 ;; memory region, operand 1 is the source, operand 2 is the counter
552 ;; register and operand 3 is the chunk size (1, 2 or 4).
553 (define_expand "movmd"
554 [(parallel
555 [(set (match_operand:BLK 0 "memory_operand" "")
556 (match_operand:BLK 1 "memory_operand" ""))
557 (unspec [(match_operand:HI 2 "register_operand" "")
558 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
559 (clobber (match_dup 4))
560 (clobber (match_dup 5))
561 (set (match_dup 2)
562 (const_int 0))])]
563 "TARGET_H8300SX"
564 {
565 operands[4] = copy_rtx (XEXP (operands[0], 0));
566 operands[5] = copy_rtx (XEXP (operands[1], 0));
567 })
570 ;; This is a difficult instruction to reload since operand 0 must be the
571 ;; frame pointer. See h8300_reg_class_from_letter for an explanation.
572 (define_insn "movmd_internal_normal"
573 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
574 (mem:BLK (match_operand:HI 4 "register_operand" "1,1")))
575 (unspec [(match_operand:HI 5 "register_operand" "2,2")
576 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
577 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
578 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
579 (set (match_operand:HI 2 "register_operand" "=c,c")
580 (const_int 0))]
581 "TARGET_H8300SX && TARGET_NORMAL_MODE"
582 "@
583 movmd%m6
584 #"
585 [(set_attr "length" "2,14")
586 (set_attr "can_delay" "no")
587 (set_attr "cc" "none,clobber")])
589 (define_insn "movmd_internal"
590 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
591 (mem:BLK (match_operand:SI 4 "register_operand" "1,1")))
592 (unspec [(match_operand:HI 5 "register_operand" "2,2")
593 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
594 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
595 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
596 (set (match_operand:HI 2 "register_operand" "=c,c")
597 (const_int 0))]
598 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
599 "@
600 movmd%m6
601 #"
602 [(set_attr "length" "2,14")
603 (set_attr "can_delay" "no")
604 (set_attr "cc" "none,clobber")])
606 ;; Split the above instruction if the destination register isn't er6.
607 ;; We need a sequence like:
608 ;;
609 ;; mov.l er6,@-er7
610 ;; mov.l <dest>,er6
611 ;; movmd.sz
612 ;; mov.l er6,<dest>
613 ;; mov.l @er7+,er6
614 ;;
615 ;; where <dest> is the current destination register (operand 4).
616 ;; The fourth instruction will be deleted if <dest> dies here.
617 (define_split
618 [(set (match_operand:BLK 0 "memory_operand" "")
619 (match_operand:BLK 1 "memory_operand" ""))
620 (unspec [(match_operand:HI 2 "register_operand" "")
621 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
622 (clobber (match_operand:HI 4 "register_operand" ""))
623 (clobber (match_operand:HI 5 "register_operand" ""))
624 (set (match_dup 2)
625 (const_int 0))]
626 "TARGET_H8300SX && TARGET_NORMAL_MODE
627 && reload_completed
628 && REGNO (operands[4]) != DESTINATION_REG"
629 [(const_int 0)]
630 {
631 rtx dest;
633 h8300_swap_into_er6 (XEXP (operands[0], 0));
634 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
635 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
636 h8300_swap_out_of_er6 (operands[4]);
637 DONE;
638 })
640 (define_split
641 [(set (match_operand:BLK 0 "memory_operand" "")
642 (match_operand:BLK 1 "memory_operand" ""))
643 (unspec [(match_operand:HI 2 "register_operand" "")
644 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
645 (clobber (match_operand:SI 4 "register_operand" ""))
646 (clobber (match_operand:SI 5 "register_operand" ""))
647 (set (match_dup 2)
648 (const_int 0))]
649 "TARGET_H8300SX && !TARGET_NORMAL_MODE
650 && reload_completed
651 && REGNO (operands[4]) != DESTINATION_REG"
652 [(const_int 0)]
653 {
654 rtx dest;
656 h8300_swap_into_er6 (XEXP (operands[0], 0));
657 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
658 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
659 h8300_swap_out_of_er6 (operands[4]);
660 DONE;
661 })
663 ;; Expand a call to stpcpy() using movsd. Operand 0 should point to
664 ;; the final character, but movsd leaves it pointing to the character
665 ;; after that.
666 (define_expand "movstr"
667 [(use (match_operand 0 "register_operand" ""))
668 (use (match_operand:BLK 1 "memory_operand" ""))
669 (use (match_operand:BLK 2 "memory_operand" ""))]
670 "TARGET_H8300SX"
671 {
672 operands[1] = replace_equiv_address
673 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
674 operands[2] = replace_equiv_address
675 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0)));
676 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode)));
677 emit_insn (gen_add3_insn (operands[0],
678 XEXP (operands[1], 0),
679 constm1_rtx));
680 DONE;
681 })
683 ;; Expander for generating a movsd instruction. Operand 0 is the
684 ;; destination string, operand 1 is the source string and operand 2
685 ;; is a scratch register.
686 (define_expand "movsd"
687 [(parallel
688 [(set (match_operand:BLK 0 "memory_operand" "")
689 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")]
690 UNSPEC_STPCPY))
691 (clobber (match_dup 3))
692 (clobber (match_dup 4))
693 (clobber (match_operand 2 "register_operand" ""))])]
694 "TARGET_H8300SX"
695 {
696 operands[3] = copy_rtx (XEXP (operands[0], 0));
697 operands[4] = copy_rtx (XEXP (operands[1], 0));
698 })
700 ;; See comments above memcpy_internal().
701 (define_insn "stpcpy_internal_normal"
702 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
703 (unspec:BLK [(mem:BLK (match_operand:HI 4 "register_operand" "1,1"))]
704 UNSPEC_STPCPY))
705 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
706 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
707 (clobber (match_operand:HI 2 "register_operand" "=c,c"))]
708 "TARGET_H8300SX && TARGET_NORMAL_MODE"
709 "@
710 \n1:\tmovsd\t2f\;bra\t1b\n2:
711 #"
712 [(set_attr "length" "6,18")
713 (set_attr "cc" "none,clobber")])
715 (define_insn "stpcpy_internal"
716 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
717 (unspec:BLK [(mem:BLK (match_operand:SI 4 "register_operand" "1,1"))]
718 UNSPEC_STPCPY))
719 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
720 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
721 (clobber (match_operand:SI 2 "register_operand" "=c,c"))]
722 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
723 "@
724 \n1:\tmovsd\t2f\;bra\t1b\n2:
725 #"
726 [(set_attr "length" "6,18")
727 (set_attr "cc" "none,clobber")])
729 ;; Split the above instruction if the destination isn't er6. This works
730 ;; in the same way as the movmd splitter.
731 (define_split
732 [(set (match_operand:BLK 0 "memory_operand" "")
733 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
734 (clobber (match_operand:HI 2 "register_operand" ""))
735 (clobber (match_operand:HI 3 "register_operand" ""))
736 (clobber (match_operand:HI 4 "register_operand" ""))]
737 "TARGET_H8300SX && TARGET_NORMAL_MODE
738 && reload_completed
739 && REGNO (operands[2]) != DESTINATION_REG"
740 [(const_int 0)]
741 {
742 rtx dest;
744 h8300_swap_into_er6 (XEXP (operands[0], 0));
745 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
746 emit_insn (gen_movsd (dest, operands[1], operands[4]));
747 h8300_swap_out_of_er6 (operands[2]);
748 DONE;
749 })
751 (define_split
752 [(set (match_operand:BLK 0 "memory_operand" "")
753 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
754 (clobber (match_operand:SI 2 "register_operand" ""))
755 (clobber (match_operand:SI 3 "register_operand" ""))
756 (clobber (match_operand:SI 4 "register_operand" ""))]
757 "TARGET_H8300SX && !TARGET_NORMAL_MODE
758 && reload_completed
759 && REGNO (operands[2]) != DESTINATION_REG"
760 [(const_int 0)]
761 {
762 rtx dest;
764 h8300_swap_into_er6 (XEXP (operands[0], 0));
765 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
766 emit_insn (gen_movsd (dest, operands[1], operands[4]));
767 h8300_swap_out_of_er6 (operands[2]);
768 DONE;
769 })
771 (include "mova.md")
773 (define_expand "movsf"
774 [(set (match_operand:SF 0 "general_operand_dst" "")
775 (match_operand:SF 1 "general_operand_src" ""))]
776 ""
777 "
778 {
779 if (TARGET_H8300)
780 {
781 if (h8300_expand_movsi (operands))
782 DONE;
783 }
784 else if (!TARGET_H8300SX)
785 {
786 /* One of the ops has to be in a register. */
787 if (!register_operand (operand1, SFmode)
788 && !register_operand (operand0, SFmode))
789 {
790 operands[1] = copy_to_mode_reg (SFmode, operand1);
791 }
792 }
793 }")
795 (define_insn "*movsf_h8300"
796 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
797 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
798 "TARGET_H8300
799 && (register_operand (operands[0], SFmode)
800 || register_operand (operands[1], SFmode))"
801 "*
802 {
803 /* Copy of the movsi stuff. */
804 unsigned int rn = -1;
805 switch (which_alternative)
806 {
807 case 0:
808 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
809 case 1:
810 if (REGNO (operands[0]) < REGNO (operands[1]))
811 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
812 else
813 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
814 case 2:
815 /* Make sure we don't trample the register we index with. */
816 if (GET_CODE (operands[1]) == MEM)
817 {
818 rtx inside = XEXP (operands[1], 0);
819 if (REG_P (inside))
820 {
821 rn = REGNO (inside);
822 }
823 else if (GET_CODE (inside) == PLUS)
824 {
825 rtx lhs = XEXP (inside, 0);
826 rtx rhs = XEXP (inside, 1);
827 if (REG_P (lhs)) rn = REGNO (lhs);
828 if (REG_P (rhs)) rn = REGNO (rhs);
829 }
830 }
831 if (rn == REGNO (operands[0]))
832 /* Move the second word first. */
833 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
834 else
835 /* Move the first word first. */
836 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
838 case 3:
839 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
840 case 4:
841 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
842 case 5:
843 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
844 default:
845 abort ();
846 }
847 }"
848 [(set (attr "length")
849 (symbol_ref "compute_mov_length (operands)"))])
851 (define_insn "*movsf_h8300hs"
852 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
853 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
854 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
855 && (register_operand (operands[0], SFmode)
856 || register_operand (operands[1], SFmode))"
857 "@
858 sub.l %S0,%S0
859 mov.l %S1,%S0
860 mov.l %S1,%S0
861 mov.l %S1,%S0
862 mov.l %S1,%S0
863 mov.l %S1,%S0"
864 [(set (attr "length")
865 (symbol_ref "compute_mov_length (operands)"))
866 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
867 \f
868 ;; ----------------------------------------------------------------------
869 ;; PUSH INSTRUCTIONS
870 ;; ----------------------------------------------------------------------
872 (define_insn "pushqi1_h8300"
873 [(set (reg:HI SP_REG)
874 (plus:HI (reg:HI SP_REG) (const_int -2)))
875 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
876 (match_operand:QI 0 "register_operand" "r"))]
877 "TARGET_H8300
878 && operands[0] != stack_pointer_rtx"
879 "mov.w\\t%T0,@-r7"
880 [(set_attr "length" "2")])
882 (define_insn "pushqi1_h8300hs_advanced"
883 [(set (reg:SI SP_REG)
884 (plus:SI (reg:SI SP_REG) (const_int -4)))
885 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
886 (match_operand:QI 0 "register_operand" "r"))]
887 "(TARGET_H8300H || TARGET_H8300S)
888 && operands[0] != stack_pointer_rtx"
889 "mov.l\\t%S0,@-er7"
890 [(set_attr "length" "4")])
892 (define_insn "pushqi1_h8300hs_normal"
893 [(set (reg:HI SP_REG)
894 (plus:HI (reg:HI SP_REG) (const_int -4)))
895 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
896 (match_operand:QI 0 "register_operand" "r"))]
897 "(TARGET_H8300H || TARGET_H8300S)
898 && operands[0] != stack_pointer_rtx"
899 "mov.l\\t%S0,@-er7"
900 [(set_attr "length" "4")])
902 (define_expand "pushqi1"
903 [(match_operand:QI 0 "register_operand" "")]
904 ""
905 "
906 {
907 if (TARGET_H8300)
908 emit_insn (gen_pushqi1_h8300 (operands[0]));
909 else if (!TARGET_NORMAL_MODE)
910 emit_insn (gen_pushqi1_h8300hs_advanced (operands[0]));
911 else
912 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
913 DONE;
914 }")
916 (define_expand "pushhi1_h8300"
917 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
918 (match_operand:HI 0 "register_operand" ""))]
919 "TARGET_H8300
920 && operands[0] != stack_pointer_rtx"
921 "")
923 (define_insn "pushhi1_h8300hs_advanced"
924 [(set (reg:SI SP_REG)
925 (plus:SI (reg:SI SP_REG) (const_int -4)))
926 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
927 (match_operand:HI 0 "register_operand" "r"))]
928 "(TARGET_H8300H || TARGET_H8300S)
929 && operands[0] != stack_pointer_rtx"
930 "mov.l\\t%S0,@-er7"
931 [(set_attr "length" "4")])
933 (define_insn "pushhi1_h8300hs_normal"
934 [(set (reg:HI SP_REG)
935 (plus:HI (reg:HI SP_REG) (const_int -4)))
936 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
937 (match_operand:HI 0 "register_operand" "r"))]
938 "(TARGET_H8300H || TARGET_H8300S)
939 && operands[0] != stack_pointer_rtx"
940 "mov.l\\t%S0,@-er7"
941 [(set_attr "length" "4")])
943 (define_expand "pushhi1"
944 [(match_operand:HI 0 "register_operand" "")]
945 ""
946 "
947 {
948 if (TARGET_H8300)
949 emit_insn (gen_pushhi1_h8300 (operands[0]));
950 else if (!TARGET_NORMAL_MODE)
951 emit_insn (gen_pushhi1_h8300hs_advanced (operands[0]));
952 else
953 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
954 DONE;
955 }")
956 \f
957 ;; ----------------------------------------------------------------------
958 ;; TEST INSTRUCTIONS
959 ;; ----------------------------------------------------------------------
961 (define_insn ""
962 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
963 (const_int 1)
964 (match_operand 1 "const_int_operand" "n,n")))]
965 "TARGET_H8300"
966 "btst %Z1,%Y0"
967 [(set_attr "length" "2,4")
968 (set_attr "cc" "set_zn,set_zn")])
970 (define_insn ""
971 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
972 (const_int 1)
973 (match_operand 1 "const_int_operand" "n")))]
974 "TARGET_H8300"
975 "btst %Z1,%Y0"
976 [(set_attr "length" "2")
977 (set_attr "cc" "set_zn")])
979 (define_insn_and_split "*tst_extzv_1_n"
980 [(set (cc0)
981 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
982 (const_int 1)
983 (match_operand 1 "const_int_operand" "n,n,n")))
984 (clobber (match_scratch:QI 2 "=X,X,&r"))]
985 "(TARGET_H8300H || TARGET_H8300S)"
986 "@
987 btst\\t%Z1,%Y0
988 btst\\t%Z1,%Y0
989 #"
990 "&& reload_completed
991 && !OK_FOR_U (operands[0])"
992 [(set (match_dup 2)
993 (match_dup 0))
994 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
995 (const_int 1)
996 (match_dup 1)))
997 (clobber (scratch:QI))])]
998 ""
999 [(set_attr "length" "2,8,10")
1000 (set_attr "cc" "set_zn,set_zn,set_zn")])
1002 (define_insn ""
1003 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1004 (const_int 1)
1005 (match_operand 1 "const_int_operand" "n")))]
1006 "(TARGET_H8300H || TARGET_H8300S)
1007 && INTVAL (operands[1]) <= 15"
1008 "btst %Z1,%Y0"
1009 [(set_attr "length" "2")
1010 (set_attr "cc" "set_zn")])
1012 (define_insn_and_split "*tstsi_upper_bit"
1013 [(set (cc0)
1014 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1015 (const_int 1)
1016 (match_operand 1 "const_int_operand" "n")))
1017 (clobber (match_scratch:SI 2 "=&r"))]
1018 "(TARGET_H8300H || TARGET_H8300S)
1019 && INTVAL (operands[1]) >= 16"
1020 "#"
1021 "&& reload_completed"
1022 [(set (match_dup 2)
1023 (ior:SI (and:SI (match_dup 2)
1024 (const_int -65536))
1025 (lshiftrt:SI (match_dup 0)
1026 (const_int 16))))
1027 (set (cc0)
1028 (zero_extract:SI (match_dup 2)
1029 (const_int 1)
1030 (match_dup 3)))]
1031 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
1033 (define_insn "*tstsi_variable_bit"
1034 [(set (cc0)
1035 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1036 (const_int 1)
1037 (and:SI (match_operand:SI 1 "register_operand" "r")
1038 (const_int 7))))]
1039 "TARGET_H8300H || TARGET_H8300S"
1040 "btst %w1,%w0"
1041 [(set_attr "length" "2")
1042 (set_attr "cc" "set_zn")])
1044 (define_insn_and_split "*tstsi_variable_bit_qi"
1045 [(set (cc0)
1046 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
1047 (const_int 1)
1048 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
1049 (const_int 7))))
1050 (clobber (match_scratch:QI 2 "=X,X,&r"))]
1051 "(TARGET_H8300H || TARGET_H8300S)"
1052 "@
1053 btst\\t%w1,%X0
1054 btst\\t%w1,%X0
1055 #"
1056 "&& reload_completed
1057 && !OK_FOR_U (operands[0])"
1058 [(set (match_dup 2)
1059 (match_dup 0))
1060 (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup 2))
1061 (const_int 1)
1062 (and:SI (match_dup 1)
1063 (const_int 7))))
1064 (clobber (scratch:QI))])]
1065 ""
1066 [(set_attr "length" "2,8,10")
1067 (set_attr "cc" "set_zn,set_zn,set_zn")])
1069 (define_insn "tstqi"
1070 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
1071 ""
1072 "mov.b %X0,%X0"
1073 [(set_attr "length" "2")
1074 (set_attr "cc" "set_znv")])
1076 (define_insn "tsthi"
1077 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
1078 ""
1079 "mov.w %T0,%T0"
1080 [(set_attr "length" "2")
1081 (set_attr "cc" "set_znv")])
1083 (define_insn "*tsthi_upper"
1084 [(set (cc0)
1085 (and:HI (match_operand:HI 0 "register_operand" "r")
1086 (const_int -256)))]
1087 ""
1088 "mov.b %t0,%t0"
1089 [(set_attr "length" "2")
1090 (set_attr "cc" "set_znv")])
1092 (define_insn "tstsi"
1093 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
1094 "TARGET_H8300H || TARGET_H8300S"
1095 "mov.l %S0,%S0"
1096 [(set_attr "length" "2")
1097 (set_attr "cc" "set_znv")])
1099 (define_insn "*tstsi_upper"
1100 [(set (cc0)
1101 (and:SI (match_operand:SI 0 "register_operand" "r")
1102 (const_int -65536)))]
1103 ""
1104 "mov.w %e0,%e0"
1105 [(set_attr "length" "2")
1106 (set_attr "cc" "set_znv")])
1108 (define_insn "cmpqi"
1109 [(set (cc0)
1110 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
1111 (match_operand:QI 1 "h8300_src_operand" "rQi")))]
1112 ""
1113 "cmp.b %X1,%X0"
1114 [(set_attr "length_table" "addb")
1115 (set_attr "cc" "compare")])
1117 (define_expand "cmphi"
1118 [(set (cc0)
1119 (compare (match_operand:HI 0 "h8300_dst_operand" "")
1120 (match_operand:HI 1 "h8300_src_operand" "")))]
1121 ""
1122 "
1123 {
1124 /* Force operand1 into a register if we're compiling
1125 for the H8/300. */
1126 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
1127 operands[1] = force_reg (HImode, operands[1]);
1128 }")
1130 (define_insn "*cmphi_h8300_znvc"
1131 [(set (cc0)
1132 (compare (match_operand:HI 0 "register_operand" "r")
1133 (match_operand:HI 1 "register_operand" "r")))]
1134 "TARGET_H8300"
1135 "cmp.w %T1,%T0"
1136 [(set_attr "length" "2")
1137 (set_attr "cc" "compare")])
1139 (define_insn "*cmphi_h8300hs_znvc"
1140 [(set (cc0)
1141 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
1142 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
1143 "TARGET_H8300H || TARGET_H8300S"
1144 "cmp.w %T1,%T0"
1145 [(set_attr "length_table" "short_immediate,addw")
1146 (set_attr "cc" "compare,compare")])
1148 (define_insn "cmpsi"
1149 [(set (cc0)
1150 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
1151 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
1152 "TARGET_H8300H || TARGET_H8300S"
1153 "cmp.l %S1,%S0"
1154 [(set_attr "length" "2,*")
1155 (set_attr "length_table" "*,addl")
1156 (set_attr "cc" "compare,compare")])
1157 \f
1158 ;; ----------------------------------------------------------------------
1159 ;; ADD INSTRUCTIONS
1160 ;; ----------------------------------------------------------------------
1162 (define_expand "addqi3"
1163 [(set (match_operand:QI 0 "register_operand" "")
1164 (plus:QI (match_operand:QI 1 "register_operand" "")
1165 (match_operand:QI 2 "h8300_src_operand" "")))]
1166 ""
1167 "")
1169 (define_insn "*addqi3"
1170 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1171 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0")
1172 (match_operand:QI 2 "h8300_src_operand" "rQi")))]
1173 "h8300_operands_match_p (operands)"
1174 "add.b %X2,%X0"
1175 [(set_attr "length_table" "addb")
1176 (set_attr "cc" "set_zn")])
1178 (define_expand "addhi3"
1179 [(set (match_operand:HI 0 "register_operand" "")
1180 (plus:HI (match_operand:HI 1 "register_operand" "")
1181 (match_operand:HI 2 "h8300_src_operand" "")))]
1182 ""
1183 "")
1185 (define_insn "*addhi3_h8300"
1186 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1187 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1188 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1189 "TARGET_H8300"
1190 "@
1191 adds %2,%T0
1192 subs %G2,%T0
1193 add.b %t2,%t0
1194 add.b %s2,%s0\;addx %t2,%t0
1195 add.w %T2,%T0"
1196 [(set_attr "length" "2,2,2,4,2")
1197 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
1199 ;; This splitter is very important to make the stack adjustment
1200 ;; interrupt-safe. The combination of add.b and addx is unsafe!
1201 ;;
1202 ;; We apply this split after the peephole2 pass so that we won't end
1203 ;; up creating too many adds/subs when a scratch register is
1204 ;; available, which is actually a common case because stack unrolling
1205 ;; tends to happen immediately after a function call.
1207 (define_split
1208 [(set (match_operand:HI 0 "stack_pointer_operand" "")
1209 (plus:HI (match_dup 0)
1210 (match_operand 1 "const_int_gt_2_operand" "")))]
1211 "TARGET_H8300 && flow2_completed"
1212 [(const_int 0)]
1213 "split_adds_subs (HImode, operands); DONE;")
1215 (define_peephole2
1216 [(match_scratch:HI 2 "r")
1217 (set (match_operand:HI 0 "stack_pointer_operand" "")
1218 (plus:HI (match_dup 0)
1219 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
1220 "TARGET_H8300"
1221 [(set (match_dup 2)
1222 (match_dup 1))
1223 (set (match_dup 0)
1224 (plus:HI (match_dup 0)
1225 (match_dup 2)))]
1226 "")
1228 (define_insn "*addhi3_h8300hs"
1229 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1230 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1231 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1232 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
1233 "@
1234 adds %2,%S0
1235 subs %G2,%S0
1236 add.b %t2,%t0
1237 add.w %T2,%T0
1238 add.w %T2,%T0"
1239 [(set_attr "length" "2,2,2,4,2")
1240 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
1242 (define_insn "*addhi3_incdec"
1243 [(set (match_operand:HI 0 "register_operand" "=r,r")
1244 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
1245 (match_operand:HI 2 "incdec_operand" "M,O")]
1246 UNSPEC_INCDEC))]
1247 "TARGET_H8300H || TARGET_H8300S"
1248 "@
1249 inc.w %2,%T0
1250 dec.w %G2,%T0"
1251 [(set_attr "length" "2,2")
1252 (set_attr "cc" "set_zn,set_zn")])
1254 (define_insn "*addhi3_h8sx"
1255 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1256 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1257 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1258 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1259 "@
1260 add.w %T2,%T0
1261 sub.w %G2,%T0
1262 add.b %t2,%t0
1263 add.w %T2,%T0"
1264 [(set_attr "length_table" "short_immediate,short_immediate,*,addw")
1265 (set_attr "length" "*,*,2,*")
1266 (set_attr "cc" "set_zn")])
1268 (define_split
1269 [(set (match_operand:HI 0 "register_operand" "")
1270 (plus:HI (match_dup 0)
1271 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
1272 ""
1273 [(const_int 0)]
1274 "split_adds_subs (HImode, operands); DONE;")
1276 (define_expand "addsi3"
1277 [(set (match_operand:SI 0 "register_operand" "")
1278 (plus:SI (match_operand:SI 1 "register_operand" "")
1279 (match_operand:SI 2 "h8300_src_operand" "")))]
1280 ""
1281 "")
1283 (define_insn "*addsi_h8300"
1284 [(set (match_operand:SI 0 "register_operand" "=r,r")
1285 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1286 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
1287 "TARGET_H8300"
1288 "* return output_plussi (operands);"
1289 [(set (attr "length")
1290 (symbol_ref "compute_plussi_length (operands)"))
1291 (set (attr "cc")
1292 (symbol_ref "compute_plussi_cc (operands)"))])
1294 (define_insn "*addsi_h8300hs"
1295 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1296 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
1297 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
1298 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1299 "* return output_plussi (operands);"
1300 [(set (attr "length")
1301 (symbol_ref "compute_plussi_length (operands)"))
1302 (set (attr "cc")
1303 (symbol_ref "compute_plussi_cc (operands)"))])
1305 (define_insn "*addsi3_incdec"
1306 [(set (match_operand:SI 0 "register_operand" "=r,r")
1307 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
1308 (match_operand:SI 2 "incdec_operand" "M,O")]
1309 UNSPEC_INCDEC))]
1310 "TARGET_H8300H || TARGET_H8300S"
1311 "@
1312 inc.l %2,%S0
1313 dec.l %G2,%S0"
1314 [(set_attr "length" "2,2")
1315 (set_attr "cc" "set_zn,set_zn")])
1317 (define_split
1318 [(set (match_operand:SI 0 "register_operand" "")
1319 (plus:SI (match_dup 0)
1320 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
1321 "TARGET_H8300H || TARGET_H8300S"
1322 [(const_int 0)]
1323 "split_adds_subs (SImode, operands); DONE;")
1325 ;; ----------------------------------------------------------------------
1326 ;; SUBTRACT INSTRUCTIONS
1327 ;; ----------------------------------------------------------------------
1329 (define_expand "subqi3"
1330 [(set (match_operand:QI 0 "register_operand" "")
1331 (minus:QI (match_operand:QI 1 "register_operand" "")
1332 (match_operand:QI 2 "h8300_src_operand" "")))]
1333 ""
1334 "")
1336 (define_insn "*subqi3"
1337 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1338 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
1339 (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
1340 "h8300_operands_match_p (operands)"
1341 "sub.b %X2,%X0"
1342 [(set_attr "length_table" "addb")
1343 (set_attr "cc" "set_zn")])
1345 (define_expand "subhi3"
1346 [(set (match_operand:HI 0 "register_operand" "")
1347 (minus:HI (match_operand:HI 1 "register_operand" "")
1348 (match_operand:HI 2 "h8300_src_operand" "")))]
1349 ""
1350 "")
1352 (define_insn "*subhi3_h8300"
1353 [(set (match_operand:HI 0 "register_operand" "=r,r")
1354 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
1355 (match_operand:HI 2 "h8300_src_operand" "r,n")))]
1356 "TARGET_H8300"
1357 "@
1358 sub.w %T2,%T0
1359 add.b %E2,%s0\;addx %F2,%t0"
1360 [(set_attr "length" "2,4")
1361 (set_attr "cc" "set_zn,clobber")])
1363 (define_insn "*subhi3_h8300hs"
1364 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ,rQ")
1365 (minus:HI (match_operand:HI 1 "h8300_dst_operand" "0,0")
1366 (match_operand:HI 2 "h8300_src_operand" "rQ,i")))]
1367 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1368 "@
1369 sub.w %T2,%T0
1370 sub.w %T2,%T0"
1371 [(set_attr "length_table" "addw")
1372 (set_attr "cc" "set_zn")])
1374 (define_expand "subsi3"
1375 [(set (match_operand:SI 0 "register_operand" "")
1376 (minus:SI (match_operand:SI 1 "register_operand" "")
1377 (match_operand:SI 2 "h8300_src_operand" "")))]
1378 ""
1379 {
1380 if (TARGET_H8300)
1381 operands[2] = force_reg (SImode, operands[2]);
1382 })
1384 (define_insn "*subsi3_h8300"
1385 [(set (match_operand:SI 0 "register_operand" "=r")
1386 (minus:SI (match_operand:SI 1 "register_operand" "0")
1387 (match_operand:SI 2 "register_operand" "r")))]
1388 "TARGET_H8300"
1389 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1390 [(set_attr "length" "6")])
1392 (define_insn "*subsi3_h8300hs"
1393 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1394 (minus:SI (match_operand:SI 1 "h8300_dst_operand" "0,0")
1395 (match_operand:SI 2 "h8300_src_operand" "rQ,i")))]
1396 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1397 "@
1398 sub.l %S2,%S0
1399 sub.l %S2,%S0"
1400 [(set_attr "length_table" "addl")
1401 (set_attr "cc" "set_zn")])
1402 \f
1403 ;; ----------------------------------------------------------------------
1404 ;; MULTIPLY INSTRUCTIONS
1405 ;; ----------------------------------------------------------------------
1407 ;; Note that the H8/300 can only handle umulqihi3.
1409 (define_expand "mulqihi3"
1410 [(set (match_operand:HI 0 "register_operand" "")
1411 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
1412 ;; intentionally-mismatched modes
1413 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1414 "TARGET_H8300H || TARGET_H8300S"
1415 "
1416 {
1417 if (GET_MODE (operands[2]) != VOIDmode)
1418 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
1419 }")
1421 (define_insn "*mulqihi3_const"
1422 [(set (match_operand:HI 0 "register_operand" "=r")
1423 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1424 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1425 "TARGET_H8300SX"
1426 "mulxs.b %X2,%T0"
1427 [(set_attr "length" "4")
1428 (set_attr "cc" "set_zn")])
1430 (define_insn "*mulqihi3"
1431 [(set (match_operand:HI 0 "register_operand" "=r")
1432 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1433 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1434 "TARGET_H8300H || TARGET_H8300S"
1435 "mulxs.b %X2,%T0"
1436 [(set_attr "length" "4")
1437 (set_attr "cc" "set_zn")])
1439 (define_expand "mulhisi3"
1440 [(set (match_operand:SI 0 "register_operand" "")
1441 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
1442 ;; intentionally-mismatched modes
1443 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1444 "TARGET_H8300H || TARGET_H8300S"
1445 "
1446 {
1447 if (GET_MODE (operands[2]) != VOIDmode)
1448 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
1449 }")
1451 (define_insn "*mulhisi3_const"
1452 [(set (match_operand:SI 0 "register_operand" "=r")
1453 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1454 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1455 "TARGET_H8300SX"
1456 "mulxs.w %T2,%S0"
1457 [(set_attr "length" "4")
1458 (set_attr "cc" "set_zn")])
1460 (define_insn "*mulhisi3"
1461 [(set (match_operand:SI 0 "register_operand" "=r")
1462 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1463 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1464 "TARGET_H8300H || TARGET_H8300S"
1465 "mulxs.w %T2,%S0"
1466 [(set_attr "length" "4")
1467 (set_attr "cc" "set_zn")])
1469 (define_expand "umulqihi3"
1470 [(set (match_operand:HI 0 "register_operand" "")
1471 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
1472 ;; intentionally-mismatched modes
1473 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1474 "TARGET_H8300H || TARGET_H8300S"
1475 "
1476 {
1477 if (GET_MODE (operands[2]) != VOIDmode)
1478 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
1479 }")
1481 (define_insn "*umulqihi3_const"
1482 [(set (match_operand:HI 0 "register_operand" "=r")
1483 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1484 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1485 "TARGET_H8300SX"
1486 "mulxu.b %X2,%T0"
1487 [(set_attr "length" "4")
1488 (set_attr "cc" "set_zn")])
1490 (define_insn "*umulqihi3"
1491 [(set (match_operand:HI 0 "register_operand" "=r")
1492 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1493 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1494 ""
1495 "mulxu.b %X2,%T0"
1496 [(set_attr "length" "2")
1497 (set_attr "cc" "none_0hit")])
1499 (define_expand "umulhisi3"
1500 [(set (match_operand:SI 0 "register_operand" "")
1501 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
1502 ;; intentionally-mismatched modes
1503 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1504 "TARGET_H8300H || TARGET_H8300S"
1505 "
1506 {
1507 if (GET_MODE (operands[2]) != VOIDmode)
1508 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
1509 }")
1511 (define_insn "*umulhisi3_const"
1512 [(set (match_operand:SI 0 "register_operand" "=r")
1513 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1514 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1515 "TARGET_H8300SX"
1516 "mulxu.w %T2,%S0"
1517 [(set_attr "length" "4")
1518 (set_attr "cc" "set_zn")])
1520 (define_insn "*umulhisi3"
1521 [(set (match_operand:SI 0 "register_operand" "=r")
1522 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1523 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1524 "TARGET_H8300H || TARGET_H8300S"
1525 "mulxu.w %T2,%S0"
1526 [(set_attr "length" "2")
1527 (set_attr "cc" "none_0hit")])
1529 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
1530 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
1531 ;; on all H8SX variants.
1532 (define_insn "mulhi3"
1533 [(set (match_operand:HI 0 "register_operand" "=r")
1534 (mult:HI (match_operand:HI 1 "register_operand" "%0")
1535 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1536 "TARGET_H8300SX"
1537 "muls.w\\t%T2,%T0"
1538 [(set_attr "length" "2")
1539 (set_attr "cc" "set_zn")])
1541 (define_insn "mulsi3"
1542 [(set (match_operand:SI 0 "register_operand" "=r")
1543 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1544 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1545 "TARGET_H8300SX"
1546 "muls.l\\t%S2,%S0"
1547 [(set_attr "length" "2")
1548 (set_attr "cc" "set_zn")])
1550 (define_insn "smulsi3_highpart"
1551 [(set (match_operand:SI 0 "register_operand" "=r")
1552 (truncate:SI
1553 (lshiftrt:DI
1554 (mult:DI
1555 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1556 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1557 (const_int 32))))]
1558 "TARGET_H8300SXMUL"
1559 "muls/u.l\\t%S2,%S0"
1560 [(set_attr "length" "2")
1561 (set_attr "cc" "set_zn")])
1563 (define_insn "umulsi3_highpart"
1564 [(set (match_operand:SI 0 "register_operand" "=r")
1565 (truncate:SI
1566 (ashiftrt:DI
1567 (mult:DI
1568 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1569 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1570 (const_int 32))))]
1571 "TARGET_H8300SX"
1572 "mulu/u.l\\t%S2,%S0"
1573 [(set_attr "length" "2")
1574 (set_attr "cc" "none_0hit")])
1576 ;; This is a "bridge" instruction. Combine can't cram enough insns
1577 ;; together to crate a MAC instruction directly, but it can create
1578 ;; this instruction, which then allows combine to create the real
1579 ;; MAC insn.
1580 ;;
1581 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1582 ;; insn must generate reasonably correct code. Egad.
1583 (define_insn ""
1584 [(set (match_operand:SI 0 "register_operand" "=a")
1585 (mult:SI
1586 (sign_extend:SI
1587 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1588 (sign_extend:SI
1589 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1590 "TARGET_MAC"
1591 "clrmac\;mac @%2+,@%1+"
1592 [(set_attr "length" "6")
1593 (set_attr "cc" "none_0hit")])
1595 (define_insn ""
1596 [(set (match_operand:SI 0 "register_operand" "=a")
1597 (plus:SI (mult:SI
1598 (sign_extend:SI (mem:HI
1599 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1600 (sign_extend:SI (mem:HI
1601 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1602 (match_operand:SI 3 "register_operand" "0")))]
1603 "TARGET_MAC"
1604 "mac @%2+,@%1+"
1605 [(set_attr "length" "4")
1606 (set_attr "cc" "none_0hit")])
1608 ;; ----------------------------------------------------------------------
1609 ;; DIVIDE/MOD INSTRUCTIONS
1610 ;; ----------------------------------------------------------------------
1612 (define_insn "udivhi3"
1613 [(set (match_operand:HI 0 "register_operand" "=r")
1614 (udiv:HI
1615 (match_operand:HI 1 "register_operand" "0")
1616 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1617 "TARGET_H8300SX"
1618 "divu.w\\t%T2,%T0"
1619 [(set_attr "length" "2")])
1621 (define_insn "divhi3"
1622 [(set (match_operand:HI 0 "register_operand" "=r")
1623 (div:HI
1624 (match_operand:HI 1 "register_operand" "0")
1625 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1626 "TARGET_H8300SX"
1627 "divs.w\\t%T2,%T0"
1628 [(set_attr "length" "2")])
1630 (define_insn "udivsi3"
1631 [(set (match_operand:SI 0 "register_operand" "=r")
1632 (udiv:SI
1633 (match_operand:SI 1 "register_operand" "0")
1634 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1635 "TARGET_H8300SX"
1636 "divu.l\\t%S2,%S0"
1637 [(set_attr "length" "2")])
1639 (define_insn "divsi3"
1640 [(set (match_operand:SI 0 "register_operand" "=r")
1641 (div:SI
1642 (match_operand:SI 1 "register_operand" "0")
1643 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1644 "TARGET_H8300SX"
1645 "divs.l\\t%S2,%S0"
1646 [(set_attr "length" "2")])
1648 (define_insn "udivmodqi4"
1649 [(set (match_operand:QI 0 "register_operand" "=r")
1650 (truncate:QI
1651 (udiv:HI
1652 (match_operand:HI 1 "register_operand" "0")
1653 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1654 (set (match_operand:QI 3 "register_operand" "=r")
1655 (truncate:QI
1656 (umod:HI
1657 (match_dup 1)
1658 (zero_extend:HI (match_dup 2)))))]
1659 ""
1660 "*
1661 {
1662 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1663 return \"divxu.b\\t%X2,%T0\";
1664 else
1665 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1666 }"
1667 [(set_attr "length" "4")])
1669 (define_insn "divmodqi4"
1670 [(set (match_operand:QI 0 "register_operand" "=r")
1671 (truncate:QI
1672 (div:HI
1673 (match_operand:HI 1 "register_operand" "0")
1674 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1675 (set (match_operand:QI 3 "register_operand" "=r")
1676 (truncate:QI
1677 (mod:HI
1678 (match_dup 1)
1679 (sign_extend:HI (match_dup 2)))))]
1680 "TARGET_H8300H || TARGET_H8300S"
1681 "*
1682 {
1683 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1684 return \"divxs.b\\t%X2,%T0\";
1685 else
1686 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1687 }"
1688 [(set_attr "length" "6")])
1690 (define_insn "udivmodhi4"
1691 [(set (match_operand:HI 0 "register_operand" "=r")
1692 (truncate:HI
1693 (udiv:SI
1694 (match_operand:SI 1 "register_operand" "0")
1695 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1696 (set (match_operand:HI 3 "register_operand" "=r")
1697 (truncate:HI
1698 (umod:SI
1699 (match_dup 1)
1700 (zero_extend:SI (match_dup 2)))))]
1701 "TARGET_H8300H || TARGET_H8300S"
1702 "*
1703 {
1704 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1705 return \"divxu.w\\t%T2,%S0\";
1706 else
1707 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1708 }"
1709 [(set_attr "length" "4")])
1711 (define_insn "divmodhi4"
1712 [(set (match_operand:HI 0 "register_operand" "=r")
1713 (truncate:HI
1714 (div:SI
1715 (match_operand:SI 1 "register_operand" "0")
1716 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1717 (set (match_operand:HI 3 "register_operand" "=r")
1718 (truncate:HI
1719 (mod:SI
1720 (match_dup 1)
1721 (sign_extend:SI (match_dup 2)))))]
1722 "TARGET_H8300H || TARGET_H8300S"
1723 "*
1724 {
1725 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1726 return \"divxs.w\\t%T2,%S0\";
1727 else
1728 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1729 }"
1730 [(set_attr "length" "6")])
1731 \f
1732 ;; ----------------------------------------------------------------------
1733 ;; AND INSTRUCTIONS
1734 ;; ----------------------------------------------------------------------
1736 (define_insn "*andqi3_2"
1737 [(set (match_operand:QI 0 "bit_operand" "=rQ,r")
1738 (and:QI (match_operand:QI 1 "bit_operand" "%0,WU")
1739 (match_operand:QI 2 "h8300_src_operand" "rQi,IP1>X")))]
1740 "TARGET_H8300SX"
1741 "@
1742 and %X2,%X0
1743 bfld %2,%1,%R0"
1744 [(set_attr "length" "*,8")
1745 (set_attr "length_table" "logicb,*")
1746 (set_attr "cc" "set_znv,none_0hit")])
1748 (define_insn "andqi3_1"
1749 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1750 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1751 (match_operand:QI 2 "h8300_src_operand" "rn,n")))]
1752 "register_operand (operands[0], QImode)
1753 || single_zero_operand (operands[2], QImode)"
1754 "@
1755 and %X2,%X0
1756 bclr %W2,%R0"
1757 [(set_attr "length" "2,8")
1758 (set_attr "cc" "set_znv,none_0hit")])
1760 (define_expand "andqi3"
1761 [(set (match_operand:QI 0 "register_operand" "")
1762 (and:QI (match_operand:QI 1 "register_operand" "")
1763 (match_operand:QI 2 "h8300_src_operand" "")))]
1764 ""
1765 "")
1767 (define_expand "andhi3"
1768 [(set (match_operand:HI 0 "register_operand" "")
1769 (and:HI (match_operand:HI 1 "register_operand" "")
1770 (match_operand:HI 2 "h8300_src_operand" "")))]
1771 ""
1772 "")
1774 (define_insn "*andorqi3"
1775 [(set (match_operand:QI 0 "register_operand" "=r")
1776 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1777 (match_operand:QI 3 "single_one_operand" "n"))
1778 (match_operand:QI 1 "register_operand" "0")))]
1779 ""
1780 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1781 [(set_attr "length" "6")])
1783 (define_insn "*andorhi3"
1784 [(set (match_operand:HI 0 "register_operand" "=r")
1785 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1786 (match_operand:HI 3 "single_one_operand" "n"))
1787 (match_operand:HI 1 "register_operand" "0")))]
1788 ""
1789 "*
1790 {
1791 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1792 if (INTVAL (operands[3]) > 128)
1793 {
1794 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1795 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1796 }
1797 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1798 }"
1799 [(set_attr "length" "6")])
1801 (define_insn "*andorsi3"
1802 [(set (match_operand:SI 0 "register_operand" "=r")
1803 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1804 (match_operand:SI 3 "single_one_operand" "n"))
1805 (match_operand:SI 1 "register_operand" "0")))]
1806 "(INTVAL (operands[3]) & 0xffff) != 0"
1807 "*
1808 {
1809 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1810 if (INTVAL (operands[3]) > 128)
1811 {
1812 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1813 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1814 }
1815 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1816 }"
1817 [(set_attr "length" "6")])
1819 (define_insn "*andorsi3_shift_8"
1820 [(set (match_operand:SI 0 "register_operand" "=r")
1821 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1822 (const_int 8))
1823 (const_int 65280))
1824 (match_operand:SI 1 "register_operand" "0")))]
1825 ""
1826 "or.b\\t%w2,%x0"
1827 [(set_attr "length" "2")])
1829 (define_expand "andsi3"
1830 [(set (match_operand:SI 0 "register_operand" "")
1831 (and:SI (match_operand:SI 1 "register_operand" "")
1832 (match_operand:SI 2 "h8300_src_operand" "")))]
1833 ""
1834 "")
1836 ;; ----------------------------------------------------------------------
1837 ;; OR INSTRUCTIONS
1838 ;; ----------------------------------------------------------------------
1840 (define_insn "iorqi3_1"
1841 [(set (match_operand:QI 0 "bit_operand" "=rQ,U")
1842 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1843 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
1844 "TARGET_H8300SX || register_operand (operands[0], QImode)
1845 || single_one_operand (operands[2], QImode)"
1846 "@
1847 or\\t%X2,%X0
1848 bset\\t%V2,%R0"
1849 [(set_attr "length" "*,8")
1850 (set_attr "length_table" "logicb,*")
1851 (set_attr "cc" "set_znv,none_0hit")])
1853 (define_expand "iorqi3"
1854 [(set (match_operand:QI 0 "register_operand" "")
1855 (ior:QI (match_operand:QI 1 "register_operand" "")
1856 (match_operand:QI 2 "h8300_src_operand" "")))]
1857 ""
1858 "")
1860 (define_expand "iorhi3"
1861 [(set (match_operand:HI 0 "register_operand" "")
1862 (ior:HI (match_operand:HI 1 "register_operand" "")
1863 (match_operand:HI 2 "h8300_src_operand" "")))]
1864 ""
1865 "")
1867 (define_expand "iorsi3"
1868 [(set (match_operand:SI 0 "register_operand" "")
1869 (ior:SI (match_operand:SI 1 "register_operand" "")
1870 (match_operand:SI 2 "h8300_src_operand" "")))]
1871 ""
1872 "")
1874 ;; ----------------------------------------------------------------------
1875 ;; XOR INSTRUCTIONS
1876 ;; ----------------------------------------------------------------------
1878 (define_insn "xorqi3_1"
1879 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1880 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1881 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
1882 "TARGET_H8300SX || register_operand (operands[0], QImode)
1883 || single_one_operand (operands[2], QImode)"
1884 "@
1885 xor\\t%X2,%X0
1886 bnot\\t%V2,%R0"
1887 [(set_attr "length" "*,8")
1888 (set_attr "length_table" "logicb,*")
1889 (set_attr "cc" "set_znv,none_0hit")])
1891 (define_expand "xorqi3"
1892 [(set (match_operand:QI 0 "register_operand" "")
1893 (xor:QI (match_operand:QI 1 "register_operand" "")
1894 (match_operand:QI 2 "h8300_src_operand" "")))]
1895 ""
1896 "")
1898 (define_expand "xorhi3"
1899 [(set (match_operand:HI 0 "register_operand" "")
1900 (xor:HI (match_operand:HI 1 "register_operand" "")
1901 (match_operand:HI 2 "h8300_src_operand" "")))]
1902 ""
1903 "")
1905 (define_expand "xorsi3"
1906 [(set (match_operand:SI 0 "register_operand" "")
1907 (xor:SI (match_operand:SI 1 "register_operand" "")
1908 (match_operand:SI 2 "h8300_src_operand" "")))]
1909 ""
1910 "")
1912 ;; ----------------------------------------------------------------------
1913 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1914 ;; ----------------------------------------------------------------------
1916 ;; We need a separate pattern here because machines other than the
1917 ;; original H8300 don't have to split the 16-bit operand into a pair
1918 ;; of high/low instructions, so we can accept literal addresses, that
1919 ;; have to be loaded into a register on H8300.
1920 (define_insn "*logicalhi3_sn"
1921 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1922 (match_operator:HI 3 "bit_operator"
1923 [(match_operand:HI 1 "h8300_dst_operand" "%0")
1924 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
1925 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
1926 "* return output_logical_op (HImode, operands);"
1927 [(set (attr "length")
1928 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1929 (set (attr "cc")
1930 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1932 (define_insn "*logicalsi3_sn"
1933 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1934 (match_operator:SI 3 "bit_operator"
1935 [(match_operand:SI 1 "h8300_dst_operand" "%0")
1936 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
1937 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
1938 "* return output_logical_op (SImode, operands);"
1939 [(set (attr "length")
1940 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1941 (set (attr "cc")
1942 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1944 (define_insn "*logicalhi3"
1945 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1946 (match_operator:HI 3 "bit_operator"
1947 [(match_operand:HI 1 "h8300_dst_operand" "%0")
1948 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
1949 "h8300_operands_match_p (operands)"
1950 "* return output_logical_op (HImode, operands);"
1951 [(set (attr "length")
1952 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1953 (set (attr "cc")
1954 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1956 (define_insn "*logicalsi3"
1957 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1958 (match_operator:SI 3 "bit_operator"
1959 [(match_operand:SI 1 "h8300_dst_operand" "%0")
1960 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
1961 "h8300_operands_match_p (operands)"
1962 "* return output_logical_op (SImode, operands);"
1963 [(set (attr "length")
1964 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1965 (set (attr "cc")
1966 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1967 \f
1968 ;; ----------------------------------------------------------------------
1969 ;; NEGATION INSTRUCTIONS
1970 ;; ----------------------------------------------------------------------
1972 (define_expand "negqi2"
1973 [(set (match_operand:QI 0 "register_operand" "")
1974 (neg:QI (match_operand:QI 1 "register_operand" "")))]
1975 ""
1976 "")
1978 (define_insn "*negqi2"
1979 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1980 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
1981 ""
1982 "neg %X0"
1983 [(set_attr "length_table" "unary")
1984 (set_attr "cc" "set_zn")])
1986 (define_expand "neghi2"
1987 [(set (match_operand:HI 0 "register_operand" "")
1988 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1989 ""
1990 "
1991 {
1992 if (TARGET_H8300)
1993 {
1994 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1995 DONE;
1996 }
1997 }")
1999 (define_expand "neghi2_h8300"
2000 [(set (match_dup 2)
2001 (not:HI (match_operand:HI 1 "register_operand" "")))
2002 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
2003 (set (match_operand:HI 0 "register_operand" "")
2004 (match_dup 2))]
2005 ""
2006 "operands[2] = gen_reg_rtx (HImode);")
2008 (define_insn "*neghi2_h8300hs"
2009 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2010 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2011 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2012 "neg.w %T0"
2013 [(set_attr "length_table" "unary")
2014 (set_attr "cc" "set_zn")])
2016 (define_expand "negsi2"
2017 [(set (match_operand:SI 0 "register_operand" "")
2018 (neg:SI (match_operand:SI 1 "register_operand" "")))]
2019 ""
2020 "
2021 {
2022 if (TARGET_H8300)
2023 {
2024 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
2025 DONE;
2026 }
2027 }")
2029 (define_expand "negsi2_h8300"
2030 [(set (match_dup 2)
2031 (not:SI (match_operand:SI 1 "register_operand" "")))
2032 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
2033 (set (match_operand:SI 0 "register_operand" "")
2034 (match_dup 2))]
2035 ""
2036 "operands[2] = gen_reg_rtx (SImode);")
2038 (define_insn "*negsi2_h8300hs"
2039 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2040 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2041 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2042 "neg.l %S0"
2043 [(set_attr "length_table" "unary")
2044 (set_attr "cc" "set_zn")])
2046 (define_expand "negsf2"
2047 [(set (match_operand:SF 0 "register_operand" "")
2048 (neg:SF (match_operand:SF 1 "register_operand" "")))]
2049 ""
2050 "")
2052 (define_insn "*negsf2_h8300"
2053 [(set (match_operand:SF 0 "register_operand" "=r")
2054 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2055 "TARGET_H8300"
2056 "xor.b\\t#128,%z0"
2057 [(set_attr "length" "2")])
2059 (define_insn "*negsf2_h8300hs"
2060 [(set (match_operand:SF 0 "register_operand" "=r")
2061 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2062 "TARGET_H8300H || TARGET_H8300S"
2063 "xor.w\\t#32768,%e0"
2064 [(set_attr "length" "4")])
2065 \f
2066 ;; ----------------------------------------------------------------------
2067 ;; ABSOLUTE VALUE INSTRUCTIONS
2068 ;; ----------------------------------------------------------------------
2070 (define_expand "abssf2"
2071 [(set (match_operand:SF 0 "register_operand" "")
2072 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2073 ""
2074 "")
2076 (define_insn "*abssf2_h8300"
2077 [(set (match_operand:SF 0 "register_operand" "=r")
2078 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2079 "TARGET_H8300"
2080 "and.b\\t#127,%z0"
2081 [(set_attr "length" "2")])
2083 (define_insn "*abssf2_h8300hs"
2084 [(set (match_operand:SF 0 "register_operand" "=r")
2085 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2086 "TARGET_H8300H || TARGET_H8300S"
2087 "and.w\\t#32767,%e0"
2088 [(set_attr "length" "4")])
2089 \f
2090 ;; ----------------------------------------------------------------------
2091 ;; NOT INSTRUCTIONS
2092 ;; ----------------------------------------------------------------------
2094 (define_expand "one_cmplqi2"
2095 [(set (match_operand:QI 0 "register_operand" "")
2096 (not:QI (match_operand:QI 1 "register_operand" "")))]
2097 ""
2098 "")
2100 (define_insn "*one_cmplqi2"
2101 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2102 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2103 ""
2104 "not %X0"
2105 [(set_attr "length_table" "unary")
2106 (set_attr "cc" "set_znv")])
2108 (define_expand "one_cmplhi2"
2109 [(set (match_operand:HI 0 "register_operand" "")
2110 (not:HI (match_operand:HI 1 "register_operand" "")))]
2111 ""
2112 "")
2114 (define_insn "*one_cmplhi2_h8300"
2115 [(set (match_operand:HI 0 "register_operand" "=r")
2116 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2117 "TARGET_H8300"
2118 "not %s0\;not %t0"
2119 [(set_attr "length" "4")])
2121 (define_insn "*one_cmplhi2_h8300hs"
2122 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2123 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2124 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2125 "not.w %T0"
2126 [(set_attr "cc" "set_znv")
2127 (set_attr "length_table" "unary")])
2129 (define_expand "one_cmplsi2"
2130 [(set (match_operand:SI 0 "register_operand" "")
2131 (not:SI (match_operand:SI 1 "register_operand" "")))]
2132 ""
2133 "")
2135 (define_insn "*one_cmplsi2_h8300"
2136 [(set (match_operand:SI 0 "register_operand" "=r")
2137 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2138 "TARGET_H8300"
2139 "not %w0\;not %x0\;not %y0\;not %z0"
2140 [(set_attr "length" "8")])
2142 (define_insn "*one_cmplsi2_h8300hs"
2143 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2144 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2145 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2146 "not.l %S0"
2147 [(set_attr "cc" "set_znv")
2148 (set_attr "length_table" "unary")])
2149 \f
2150 ;; ----------------------------------------------------------------------
2151 ;; JUMP INSTRUCTIONS
2152 ;; ----------------------------------------------------------------------
2154 ;; Conditional jump instructions
2156 (define_expand "ble"
2157 [(match_operand 0 "" "")]
2158 ""
2159 "h8300_expand_branch (LE, operands[0]); DONE;")
2161 (define_expand "bleu"
2162 [(match_operand 0 "" "")]
2163 ""
2164 "h8300_expand_branch (LEU, operands[0]); DONE;")
2166 (define_expand "bge"
2167 [(match_operand 0 "" "")]
2168 ""
2169 "h8300_expand_branch (GE, operands[0]); DONE;")
2171 (define_expand "bgeu"
2172 [(match_operand 0 "" "")]
2173 ""
2174 "h8300_expand_branch (GEU, operands[0]); DONE;")
2176 (define_expand "blt"
2177 [(match_operand 0 "" "")]
2178 ""
2179 "h8300_expand_branch (LT, operands[0]); DONE;")
2181 (define_expand "bltu"
2182 [(match_operand 0 "" "")]
2183 ""
2184 "h8300_expand_branch (LTU, operands[0]); DONE;")
2186 (define_expand "bgt"
2187 [(match_operand 0 "" "")]
2188 ""
2189 "h8300_expand_branch (GT, operands[0]); DONE;")
2191 (define_expand "bgtu"
2192 [(match_operand 0 "" "")]
2193 ""
2194 "h8300_expand_branch (GTU, operands[0]); DONE;")
2196 (define_expand "beq"
2197 [(match_operand 0 "" "")]
2198 ""
2199 "h8300_expand_branch (EQ, operands[0]); DONE;")
2201 (define_expand "bne"
2202 [(match_operand 0 "" "")]
2203 ""
2204 "h8300_expand_branch (NE, operands[0]); DONE;")
2206 (define_insn "branch_true"
2207 [(set (pc)
2208 (if_then_else (match_operator 1 "comparison_operator"
2209 [(cc0) (const_int 0)])
2210 (label_ref (match_operand 0 "" ""))
2211 (pc)))]
2212 ""
2213 "*
2214 {
2215 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2216 && (GET_CODE (operands[1]) == GT
2217 || GET_CODE (operands[1]) == GE
2218 || GET_CODE (operands[1]) == LE
2219 || GET_CODE (operands[1]) == LT))
2220 {
2221 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2222 return 0;
2223 }
2225 if (get_attr_length (insn) == 2)
2226 return \"b%j1 %l0\";
2227 else if (get_attr_length (insn) == 4)
2228 return \"b%j1 %l0:16\";
2229 else
2230 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2231 }"
2232 [(set_attr "type" "branch")
2233 (set_attr "cc" "none")])
2235 (define_insn "branch_false"
2236 [(set (pc)
2237 (if_then_else (match_operator 1 "comparison_operator"
2238 [(cc0) (const_int 0)])
2239 (pc)
2240 (label_ref (match_operand 0 "" ""))))]
2241 ""
2242 "*
2243 {
2244 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2245 && (GET_CODE (operands[1]) == GT
2246 || GET_CODE (operands[1]) == GE
2247 || GET_CODE (operands[1]) == LE
2248 || GET_CODE (operands[1]) == LT))
2249 {
2250 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2251 return 0;
2252 }
2254 if (get_attr_length (insn) == 2)
2255 return \"b%k1 %l0\";
2256 else if (get_attr_length (insn) == 4)
2257 return \"b%k1 %l0:16\";
2258 else
2259 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2260 }"
2261 [(set_attr "type" "branch")
2262 (set_attr "cc" "none")])
2264 (define_insn "*brabc"
2265 [(set (pc)
2266 (if_then_else
2267 (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2268 (const_int 1)
2269 (match_operand:QI 2 "immediate_operand" "n"))
2270 (const_int 0))
2271 (label_ref (match_operand 0 "" ""))
2272 (pc)))]
2273 "TARGET_H8300SX"
2274 "*
2275 {
2276 switch (get_attr_length (insn)
2277 - h8300_insn_length_from_table (insn, operands))
2278 {
2279 case 2:
2280 return \"bra/bc %2,%R1,%l0\";
2282 case 4:
2283 return \"bra/bc %2,%R1,%l0:16\";
2285 default:
2286 return \"bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2287 }
2288 }"
2289 [(set_attr "type" "bitbranch")
2290 (set_attr "length_table" "bitbranch")
2291 (set_attr "cc" "none")])
2293 (define_insn "*brabs"
2294 [(set (pc)
2295 (if_then_else
2296 (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2297 (const_int 1)
2298 (match_operand:QI 2 "immediate_operand" "n"))
2299 (const_int 0))
2300 (label_ref (match_operand 0 "" ""))
2301 (pc)))]
2302 "TARGET_H8300SX"
2303 "*
2304 {
2305 switch (get_attr_length (insn)
2306 - h8300_insn_length_from_table (insn, operands))
2307 {
2308 case 2:
2309 return \"bra/bs %2,%R1,%l0\";
2311 case 4:
2312 return \"bra/bs %2,%R1,%l0:16\";
2314 default:
2315 return \"bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2316 }
2317 }"
2318 [(set_attr "type" "bitbranch")
2319 (set_attr "length_table" "bitbranch")
2320 (set_attr "cc" "none")])
2322 ;; Unconditional and other jump instructions.
2324 (define_insn "jump"
2325 [(set (pc)
2326 (label_ref (match_operand 0 "" "")))]
2327 ""
2328 "*
2329 {
2330 if (final_sequence != 0)
2331 {
2332 if (get_attr_length (insn) == 2)
2333 return \"bra/s %l0\";
2334 else
2335 {
2336 /* The branch isn't short enough to use bra/s. Output the
2337 branch and delay slot in their normal order.
2339 If this is a backward branch, it will now be branching two
2340 bytes further than previously thought. The length-based
2341 test for bra vs. jump is very conservative though, so the
2342 branch will still be within range. */
2343 rtvec vec;
2344 int seen;
2346 vec = XVEC (final_sequence, 0);
2347 final_sequence = 0;
2348 final_scan_insn (RTVEC_ELT (vec, 1), asm_out_file, optimize, 0, 1, & seen);
2349 final_scan_insn (RTVEC_ELT (vec, 0), asm_out_file, optimize, 0, 1, & seen);
2350 INSN_DELETED_P (RTVEC_ELT (vec, 1)) = 1;
2351 return \"\";
2352 }
2353 }
2354 else if (get_attr_length (insn) == 2)
2355 return \"bra %l0\";
2356 else if (get_attr_length (insn) == 4)
2357 return \"bra %l0:16\";
2358 else
2359 return \"jmp @%l0\";
2360 }"
2361 [(set_attr "type" "branch")
2362 (set (attr "delay_slot")
2363 (if_then_else (ne (symbol_ref "TARGET_H8300SX") (const_int 0))
2364 (const_string "jump")
2365 (const_string "none")))
2366 (set_attr "cc" "none")])
2368 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2370 (define_expand "tablejump"
2371 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
2372 (use (label_ref (match_operand 1 "" "")))])]
2373 ""
2374 "")
2376 (define_insn "*tablejump_h8300"
2377 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2378 (use (label_ref (match_operand 1 "" "")))]
2379 "TARGET_H8300"
2380 "jmp @%0"
2381 [(set_attr "cc" "none")
2382 (set_attr "length" "2")])
2384 (define_insn "*tablejump_h8300hs_advanced"
2385 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2386 (use (label_ref (match_operand 1 "" "")))]
2387 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2388 "jmp @%0"
2389 [(set_attr "cc" "none")
2390 (set_attr "length" "2")])
2392 (define_insn "*tablejump_h8300hs_normal"
2393 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2394 (use (label_ref (match_operand 1 "" "")))]
2395 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2396 "jmp @%S0"
2397 [(set_attr "cc" "none")
2398 (set_attr "length" "2")])
2400 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2402 (define_expand "indirect_jump"
2403 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
2404 ""
2405 "")
2407 (define_insn "*indirect_jump_h8300"
2408 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2409 "TARGET_H8300"
2410 "jmp @%0"
2411 [(set_attr "cc" "none")
2412 (set_attr "length" "2")])
2414 (define_insn "*indirect_jump_h8300hs_advanced"
2415 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
2416 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2417 "jmp @%0"
2418 [(set_attr "cc" "none")
2419 (set_attr "length" "2")])
2421 (define_insn "*indirect_jump_h8300hs_normal"
2422 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2423 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2424 "jmp @%S0"
2425 [(set_attr "cc" "none")
2426 (set_attr "length" "2")])
2428 ;; Call subroutine with no return value.
2430 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2432 (define_insn "call"
2433 [(call (match_operand:QI 0 "call_insn_operand" "or")
2434 (match_operand:HI 1 "general_operand" "g"))]
2435 ""
2436 "*
2437 {
2438 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2439 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
2440 return \"jsr\\t@%0:8\";
2441 else
2442 return \"jsr\\t%0\";
2443 }"
2444 [(set_attr "type" "call")
2445 (set (attr "length")
2446 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2447 (const_int 2)
2448 (const_int 4)))])
2450 ;; Call subroutine, returning value in operand 0
2451 ;; (which must be a hard register).
2453 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2455 (define_insn "call_value"
2456 [(set (match_operand 0 "" "=r")
2457 (call (match_operand:QI 1 "call_insn_operand" "or")
2458 (match_operand:HI 2 "general_operand" "g")))]
2459 ""
2460 "*
2461 {
2462 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2463 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
2464 return \"jsr\\t@%1:8\";
2465 else
2466 return \"jsr\\t%1\";
2467 }"
2468 [(set_attr "type" "call")
2469 (set (attr "length")
2470 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2471 (const_int 2)
2472 (const_int 4)))])
2474 (define_insn "nop"
2475 [(const_int 0)]
2476 ""
2477 "nop"
2478 [(set_attr "cc" "none")
2479 (set_attr "length" "2")])
2480 \f
2481 ;; ----------------------------------------------------------------------
2482 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
2483 ;; ----------------------------------------------------------------------
2485 (define_expand "push_h8300"
2486 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
2487 (match_operand:HI 0 "register_operand" ""))]
2488 "TARGET_H8300"
2489 "")
2491 (define_expand "push_h8300hs_advanced"
2492 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2493 (match_operand:SI 0 "register_operand" ""))]
2494 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2495 "")
2497 (define_expand "push_h8300hs_normal"
2498 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
2499 (match_operand:SI 0 "register_operand" ""))]
2500 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2501 "")
2503 (define_expand "pop_h8300"
2504 [(set (match_operand:HI 0 "register_operand" "")
2505 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
2506 "TARGET_H8300"
2507 "")
2509 (define_expand "pop_h8300hs_advanced"
2510 [(set (match_operand:SI 0 "register_operand" "")
2511 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2512 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2513 "")
2515 (define_expand "pop_h8300hs_normal"
2516 [(set (match_operand:SI 0 "register_operand" "")
2517 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
2518 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2519 "")
2521 (define_insn "ldm_h8300sx"
2522 [(match_parallel 0 "h8300_ldm_parallel"
2523 [(set (match_operand:SI 1 "register_operand" "")
2524 (match_operand:SI 2 "memory_operand" ""))])]
2525 "TARGET_H8300S"
2526 {
2527 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2528 XVECLEN (operands[0], 0) - 2));
2529 return "ldm.l\t@er7+,%S1-%S3";
2530 }
2531 [(set_attr "cc" "none")
2532 (set_attr "length" "4")])
2534 (define_insn "stm_h8300sx"
2535 [(match_parallel 0 "h8300_stm_parallel"
2536 [(set (match_operand:SI 1 "memory_operand" "")
2537 (match_operand:SI 2 "register_operand" ""))])]
2538 "TARGET_H8300S"
2539 {
2540 operands[3] = SET_SRC (XVECEXP (operands[0], 0,
2541 XVECLEN (operands[0], 0) - 2));
2542 return "stm.l\t%S2-%S3,@-er7";
2543 }
2544 [(set_attr "cc" "none")
2545 (set_attr "length" "4")])
2547 (define_insn "return_h8sx"
2548 [(match_parallel 0 "h8300_return_parallel"
2549 [(return)
2550 (set (match_operand:SI 1 "register_operand" "")
2551 (match_operand:SI 2 "memory_operand" ""))])]
2552 "TARGET_H8300SX"
2553 {
2554 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2555 XVECLEN (operands[0], 0) - 2));
2556 if (h8300_current_function_interrupt_function_p ())
2557 return "rte/l\t%S1-%S3";
2558 else
2559 return "rts/l\t%S1-%S3";
2560 }
2561 [(set_attr "cc" "none")
2562 (set_attr "can_delay" "no")
2563 (set_attr "length" "2")])
2565 (define_expand "return"
2566 [(return)]
2567 "h8300_can_use_return_insn_p ()"
2568 "")
2570 (define_insn "*return_1"
2571 [(return)]
2572 "reload_completed"
2573 "*
2574 {
2575 if (h8300_current_function_interrupt_function_p ())
2576 return \"rte\";
2577 else
2578 return \"rts\";
2579 }"
2580 [(set_attr "cc" "none")
2581 (set_attr "can_delay" "no")
2582 (set_attr "length" "2")])
2584 (define_expand "prologue"
2585 [(const_int 0)]
2586 ""
2587 "h8300_expand_prologue (); DONE;")
2589 (define_expand "epilogue"
2590 [(return)]
2591 ""
2592 "h8300_expand_epilogue (); DONE;")
2594 (define_insn "monitor_prologue"
2595 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2596 ""
2597 "*
2598 {
2599 if (TARGET_H8300)
2600 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2601 else if (TARGET_H8300H)
2602 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2603 else if (TARGET_H8300S)
2604 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2605 abort ();
2606 }"
2607 [(set_attr "length" "20")])
2608 \f
2609 ;; ----------------------------------------------------------------------
2610 ;; EXTEND INSTRUCTIONS
2611 ;; ----------------------------------------------------------------------
2613 (define_expand "zero_extendqihi2"
2614 [(set (match_operand:HI 0 "register_operand" "")
2615 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2616 ""
2617 "")
2619 (define_insn "*zero_extendqihi2_h8300"
2620 [(set (match_operand:HI 0 "register_operand" "=r,r")
2621 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2622 "TARGET_H8300"
2623 "@
2624 mov.b #0,%t0
2625 #"
2626 [(set_attr "length" "2,10")])
2628 (define_insn "*zero_extendqihi2_h8300hs"
2629 [(set (match_operand:HI 0 "register_operand" "=r,r")
2630 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2631 "TARGET_H8300H || TARGET_H8300S"
2632 "@
2633 extu.w %T0
2634 #"
2635 [(set_attr "length" "2,10")
2636 (set_attr "cc" "set_znv,set_znv")])
2638 ;; Split the zero extension of a general operand (actually a memory
2639 ;; operand) into a load of the operand and the actual zero extension
2640 ;; so that 1) the length will be accurate, and 2) the zero extensions
2641 ;; appearing at the end of basic blocks may be merged.
2643 (define_split
2644 [(set (match_operand:HI 0 "register_operand" "")
2645 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2646 "reload_completed"
2647 [(set (match_dup 2)
2648 (match_dup 1))
2649 (set (match_dup 0)
2650 (zero_extend:HI (match_dup 2)))]
2651 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2653 (define_expand "zero_extendqisi2"
2654 [(set (match_operand:SI 0 "register_operand" "")
2655 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2656 ""
2657 {
2658 if (TARGET_H8300SX)
2659 operands[1] = force_reg (QImode, operands[1]);
2660 })
2662 (define_insn "*zero_extendqisi2_h8300"
2663 [(set (match_operand:SI 0 "register_operand" "=r,r")
2664 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2665 "TARGET_H8300"
2666 "@
2667 mov.b #0,%x0\;sub.w %e0,%e0
2668 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2669 [(set_attr "length" "4,8")])
2671 (define_insn "*zero_extendqisi2_h8300hs"
2672 [(set (match_operand:SI 0 "register_operand" "=r,r")
2673 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2674 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2675 "#")
2677 (define_split
2678 [(set (match_operand:SI 0 "register_operand" "")
2679 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2680 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2681 && reg_overlap_mentioned_p (operands[0], operands[1])
2682 && reload_completed"
2683 [(set (match_dup 2)
2684 (match_dup 1))
2685 (set (match_dup 3)
2686 (zero_extend:HI (match_dup 2)))
2687 (set (match_dup 0)
2688 (zero_extend:SI (match_dup 3)))]
2689 "operands[2] = gen_lowpart (QImode, operands[0]);
2690 operands[3] = gen_lowpart (HImode, operands[0]);")
2692 (define_split
2693 [(set (match_operand:SI 0 "register_operand" "")
2694 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2695 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2696 && !reg_overlap_mentioned_p (operands[0], operands[1])
2697 && reload_completed"
2698 [(set (match_dup 0)
2699 (const_int 0))
2700 (set (strict_low_part (match_dup 2))
2701 (match_dup 1))]
2702 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2704 (define_insn "*zero_extendqisi2_h8sx"
2705 [(set (match_operand:SI 0 "register_operand" "=r")
2706 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2707 "TARGET_H8300SX"
2708 "extu.l\t#2,%0"
2709 [(set_attr "length" "2")
2710 (set_attr "cc" "set_znv")])
2712 (define_expand "zero_extendhisi2"
2713 [(set (match_operand:SI 0 "register_operand" "")
2714 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2715 ""
2716 "")
2718 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2719 (define_insn "*zero_extendhisi2_h8300"
2720 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2721 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2722 "TARGET_H8300"
2723 "@
2724 sub.w %e0,%e0
2725 mov.w %f1,%f0\;sub.w %e0,%e0
2726 mov.w %e1,%f0\;sub.w %e0,%e0"
2727 [(set_attr "length" "2,4,6")])
2729 (define_insn "*zero_extendhisi2_h8300hs"
2730 [(set (match_operand:SI 0 "register_operand" "=r")
2731 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2732 "TARGET_H8300H || TARGET_H8300S"
2733 "extu.l %S0"
2734 [(set_attr "length" "2")
2735 (set_attr "cc" "set_znv")])
2737 (define_expand "extendqihi2"
2738 [(set (match_operand:HI 0 "register_operand" "")
2739 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2740 ""
2741 "")
2743 (define_insn "*extendqihi2_h8300"
2744 [(set (match_operand:HI 0 "register_operand" "=r,r")
2745 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2746 "TARGET_H8300"
2747 "@
2748 bld #7,%s0\;subx %t0,%t0
2749 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2750 [(set_attr "length" "4,8")])
2752 (define_insn "*extendqihi2_h8300hs"
2753 [(set (match_operand:HI 0 "register_operand" "=r")
2754 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2755 "TARGET_H8300H || TARGET_H8300S"
2756 "exts.w %T0"
2757 [(set_attr "length" "2")
2758 (set_attr "cc" "set_znv")])
2760 (define_expand "extendqisi2"
2761 [(set (match_operand:SI 0 "register_operand" "")
2762 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2763 ""
2764 "")
2766 (define_insn "*extendqisi2_h8300"
2767 [(set (match_operand:SI 0 "register_operand" "=r,r")
2768 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2769 "TARGET_H8300"
2770 "@
2771 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2772 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2773 [(set_attr "length" "8,12")])
2775 ;; The following pattern is needed because without the pattern, the
2776 ;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2777 ;; shifts, one ashift and one ashiftrt.
2779 (define_insn_and_split "*extendqisi2_h8300hs"
2780 [(set (match_operand:SI 0 "register_operand" "=r")
2781 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2782 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2783 "#"
2784 "&& reload_completed"
2785 [(set (match_dup 2)
2786 (sign_extend:HI (match_dup 1)))
2787 (set (match_dup 0)
2788 (sign_extend:SI (match_dup 2)))]
2789 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2791 (define_insn "*extendqisi2_h8sx"
2792 [(set (match_operand:SI 0 "register_operand" "=r")
2793 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2794 "TARGET_H8300SX"
2795 "exts.l\t#2,%0"
2796 [(set_attr "length" "2")
2797 (set_attr "cc" "set_znv")])
2799 (define_expand "extendhisi2"
2800 [(set (match_operand:SI 0 "register_operand" "")
2801 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2802 ""
2803 "")
2805 (define_insn "*extendhisi2_h8300"
2806 [(set (match_operand:SI 0 "register_operand" "=r,r")
2807 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2808 "TARGET_H8300"
2809 "@
2810 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2811 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2812 [(set_attr "length" "6,10")])
2814 (define_insn "*extendhisi2_h8300hs"
2815 [(set (match_operand:SI 0 "register_operand" "=r")
2816 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2817 "TARGET_H8300H || TARGET_H8300S"
2818 "exts.l %S0"
2819 [(set_attr "length" "2")
2820 (set_attr "cc" "set_znv")])
2821 \f
2822 ;; ----------------------------------------------------------------------
2823 ;; SHIFTS
2824 ;; ----------------------------------------------------------------------
2825 ;;
2826 ;; We make some attempt to provide real efficient shifting. One example is
2827 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2828 ;; reg and moving 0 into the former reg.
2829 ;;
2830 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2831 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2832 ;; give the optimizer more cracks at the code. However, we wish to do things
2833 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2834 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2835 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2836 ;; to detect cases it can optimize.
2837 ;;
2838 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2839 ;; easier "do it at insn emit time" route.
2841 ;; QI BIT SHIFTS
2843 (define_expand "ashlqi3"
2844 [(set (match_operand:QI 0 "register_operand" "")
2845 (ashift:QI (match_operand:QI 1 "register_operand" "")
2846 (match_operand:QI 2 "nonmemory_operand" "")))]
2847 ""
2848 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;")
2850 (define_expand "ashrqi3"
2851 [(set (match_operand:QI 0 "register_operand" "")
2852 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2853 (match_operand:QI 2 "nonmemory_operand" "")))]
2854 ""
2855 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;")
2857 (define_expand "lshrqi3"
2858 [(set (match_operand:QI 0 "register_operand" "")
2859 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2860 (match_operand:QI 2 "nonmemory_operand" "")))]
2861 ""
2862 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;")
2864 (define_insn ""
2865 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2866 (match_operator:QI 3 "h8sx_unary_shift_operator"
2867 [(match_operand:QI 1 "h8300_dst_operand" "0")
2868 (match_operand:QI 2 "const_int_operand" "")]))]
2869 "h8300_operands_match_p (operands)"
2870 { return output_h8sx_shift (operands, 'b', 'X'); }
2871 [(set_attr "length_table" "unary")
2872 (set_attr "cc" "set_znv")])
2874 (define_insn ""
2875 [(set (match_operand:QI 0 "register_operand" "=r")
2876 (match_operator:QI 3 "h8sx_binary_shift_operator"
2877 [(match_operand:QI 1 "register_operand" "0")
2878 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))]
2879 ""
2880 { return output_h8sx_shift (operands, 'b', 'X'); }
2881 [(set_attr "length" "4")
2882 (set_attr "cc" "set_znv")])
2884 (define_insn "*shiftqi"
2885 [(set (match_operand:QI 0 "register_operand" "=r,r")
2886 (match_operator:QI 3 "nshift_operator"
2887 [ (match_operand:QI 1 "register_operand" "0,0")
2888 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2889 (clobber (match_scratch:QI 4 "=X,&r"))]
2890 ""
2891 "* return output_a_shift (operands);"
2892 [(set (attr "length")
2893 (symbol_ref "compute_a_shift_length (insn, operands)"))
2894 (set (attr "cc")
2895 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2897 ;; HI BIT SHIFTS
2899 (define_expand "ashlhi3"
2900 [(set (match_operand:HI 0 "register_operand" "")
2901 (ashift:HI (match_operand:HI 1 "register_operand" "")
2902 (match_operand:QI 2 "nonmemory_operand" "")))]
2903 ""
2904 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;")
2906 (define_expand "lshrhi3"
2907 [(set (match_operand:HI 0 "register_operand" "")
2908 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
2909 (match_operand:QI 2 "nonmemory_operand" "")))]
2910 ""
2911 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;")
2913 (define_expand "ashrhi3"
2914 [(set (match_operand:HI 0 "register_operand" "")
2915 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2916 (match_operand:QI 2 "nonmemory_operand" "")))]
2917 ""
2918 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;")
2920 (define_insn ""
2921 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2922 (match_operator:HI 3 "h8sx_unary_shift_operator"
2923 [(match_operand:HI 1 "h8300_dst_operand" "0")
2924 (match_operand:QI 2 "const_int_operand" "")]))]
2925 "h8300_operands_match_p (operands)"
2926 { return output_h8sx_shift (operands, 'w', 'T'); }
2927 [(set_attr "length_table" "unary")
2928 (set_attr "cc" "set_znv")])
2930 (define_insn ""
2931 [(set (match_operand:HI 0 "register_operand" "=r")
2932 (match_operator:HI 3 "h8sx_binary_shift_operator"
2933 [(match_operand:HI 1 "register_operand" "0")
2934 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))]
2935 ""
2936 { return output_h8sx_shift (operands, 'w', 'T'); }
2937 [(set_attr "length" "4")
2938 (set_attr "cc" "set_znv")])
2940 (define_insn "*shifthi"
2941 [(set (match_operand:HI 0 "register_operand" "=r,r")
2942 (match_operator:HI 3 "nshift_operator"
2943 [ (match_operand:HI 1 "register_operand" "0,0")
2944 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2945 (clobber (match_scratch:QI 4 "=X,&r"))]
2946 ""
2947 "* return output_a_shift (operands);"
2948 [(set (attr "length")
2949 (symbol_ref "compute_a_shift_length (insn, operands)"))
2950 (set (attr "cc")
2951 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2953 ;; SI BIT SHIFTS
2955 (define_expand "ashlsi3"
2956 [(set (match_operand:SI 0 "register_operand" "")
2957 (ashift:SI (match_operand:SI 1 "register_operand" "")
2958 (match_operand:QI 2 "nonmemory_operand" "")))]
2959 ""
2960 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;")
2962 (define_expand "lshrsi3"
2963 [(set (match_operand:SI 0 "register_operand" "")
2964 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
2965 (match_operand:QI 2 "nonmemory_operand" "")))]
2966 ""
2967 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;")
2969 (define_expand "ashrsi3"
2970 [(set (match_operand:SI 0 "register_operand" "")
2971 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
2972 (match_operand:QI 2 "nonmemory_operand" "")))]
2973 ""
2974 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;")
2976 (define_insn ""
2977 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2978 (match_operator:SI 3 "h8sx_unary_shift_operator"
2979 [(match_operand:SI 1 "h8300_dst_operand" "0")
2980 (match_operand:QI 2 "const_int_operand" "")]))]
2981 "h8300_operands_match_p (operands)"
2982 { return output_h8sx_shift (operands, 'l', 'S'); }
2983 [(set_attr "length_table" "unary")
2984 (set_attr "cc" "set_znv")])
2986 (define_insn ""
2987 [(set (match_operand:SI 0 "register_operand" "=r")
2988 (match_operator:SI 3 "h8sx_binary_shift_operator"
2989 [(match_operand:SI 1 "register_operand" "0")
2990 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
2991 ""
2992 { return output_h8sx_shift (operands, 'l', 'S'); }
2993 [(set_attr "length" "4")
2994 (set_attr "cc" "set_znv")])
2996 (define_insn "*shiftsi"
2997 [(set (match_operand:SI 0 "register_operand" "=r,r")
2998 (match_operator:SI 3 "nshift_operator"
2999 [ (match_operand:SI 1 "register_operand" "0,0")
3000 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
3001 (clobber (match_scratch:QI 4 "=X,&r"))]
3002 ""
3003 "* return output_a_shift (operands);"
3004 [(set (attr "length")
3005 (symbol_ref "compute_a_shift_length (insn, operands)"))
3006 (set (attr "cc")
3007 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3009 ;; Split a variable shift into a loop. If the register containing
3010 ;; the shift count dies, then we just use that register.
3012 (define_split
3013 [(set (match_operand 0 "register_operand" "")
3014 (match_operator 2 "nshift_operator"
3015 [(match_dup 0)
3016 (match_operand:QI 1 "register_operand" "")]))
3017 (clobber (match_operand:QI 3 "register_operand" ""))]
3018 "flow2_completed
3019 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3020 [(set (cc0)
3021 (match_dup 1))
3022 (set (pc)
3023 (if_then_else (le (cc0) (const_int 0))
3024 (label_ref (match_dup 5))
3025 (pc)))
3026 (match_dup 4)
3027 (parallel
3028 [(set (match_dup 0)
3029 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3030 (clobber (scratch:QI))])
3031 (set (match_dup 1)
3032 (plus:QI (match_dup 1) (const_int -1)))
3033 (set (cc0)
3034 (match_dup 1))
3035 (set (pc)
3036 (if_then_else (ne (cc0) (const_int 0))
3037 (label_ref (match_dup 4))
3038 (pc)))
3039 (match_dup 5)]
3040 "operands[4] = gen_label_rtx ();
3041 operands[5] = gen_label_rtx ();")
3043 (define_split
3044 [(set (match_operand 0 "register_operand" "")
3045 (match_operator 2 "nshift_operator"
3046 [(match_dup 0)
3047 (match_operand:QI 1 "register_operand" "")]))
3048 (clobber (match_operand:QI 3 "register_operand" ""))]
3049 "flow2_completed
3050 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3051 [(set (match_dup 3)
3052 (match_dup 1))
3053 (set (cc0)
3054 (match_dup 3))
3055 (set (pc)
3056 (if_then_else (le (cc0) (const_int 0))
3057 (label_ref (match_dup 5))
3058 (pc)))
3059 (match_dup 4)
3060 (parallel
3061 [(set (match_dup 0)
3062 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3063 (clobber (scratch:QI))])
3064 (set (match_dup 3)
3065 (plus:QI (match_dup 3) (const_int -1)))
3066 (set (cc0)
3067 (match_dup 3))
3068 (set (pc)
3069 (if_then_else (ne (cc0) (const_int 0))
3070 (label_ref (match_dup 4))
3071 (pc)))
3072 (match_dup 5)]
3073 "operands[4] = gen_label_rtx ();
3074 operands[5] = gen_label_rtx ();")
3075 \f
3076 ;; ----------------------------------------------------------------------
3077 ;; ROTATIONS
3078 ;; ----------------------------------------------------------------------
3080 (define_expand "rotlqi3"
3081 [(set (match_operand:QI 0 "register_operand" "")
3082 (rotate:QI (match_operand:QI 1 "register_operand" "")
3083 (match_operand:QI 2 "nonmemory_operand" "")))]
3084 ""
3085 "if (expand_a_rotate (operands)) DONE;")
3087 (define_insn "rotlqi3_1"
3088 [(set (match_operand:QI 0 "register_operand" "=r")
3089 (rotate:QI (match_operand:QI 1 "register_operand" "0")
3090 (match_operand:QI 2 "immediate_operand" "")))]
3091 ""
3092 "* return output_a_rotate (ROTATE, operands);"
3093 [(set (attr "length")
3094 (symbol_ref "compute_a_rotate_length (operands)"))])
3096 (define_expand "rotlhi3"
3097 [(set (match_operand:HI 0 "register_operand" "")
3098 (rotate:HI (match_operand:HI 1 "register_operand" "")
3099 (match_operand:QI 2 "nonmemory_operand" "")))]
3100 ""
3101 "if (expand_a_rotate (operands)) DONE;")
3103 (define_insn "rotlhi3_1"
3104 [(set (match_operand:HI 0 "register_operand" "=r")
3105 (rotate:HI (match_operand:HI 1 "register_operand" "0")
3106 (match_operand:QI 2 "immediate_operand" "")))]
3107 ""
3108 "* return output_a_rotate (ROTATE, operands);"
3109 [(set (attr "length")
3110 (symbol_ref "compute_a_rotate_length (operands)"))])
3112 (define_expand "rotlsi3"
3113 [(set (match_operand:SI 0 "register_operand" "")
3114 (rotate:SI (match_operand:SI 1 "register_operand" "")
3115 (match_operand:QI 2 "nonmemory_operand" "")))]
3116 "TARGET_H8300H || TARGET_H8300S"
3117 "if (expand_a_rotate (operands)) DONE;")
3119 (define_insn "rotlsi3_1"
3120 [(set (match_operand:SI 0 "register_operand" "=r")
3121 (rotate:SI (match_operand:SI 1 "register_operand" "0")
3122 (match_operand:QI 2 "immediate_operand" "")))]
3123 "TARGET_H8300H || TARGET_H8300S"
3124 "* return output_a_rotate (ROTATE, operands);"
3125 [(set (attr "length")
3126 (symbol_ref "compute_a_rotate_length (operands)"))])
3127 \f
3128 ;; -----------------------------------------------------------------
3129 ;; BIT FIELDS
3130 ;; -----------------------------------------------------------------
3131 ;; The H8/300 has given 1/8th of its opcode space to bitfield
3132 ;; instructions so let's use them as well as we can.
3134 ;; You'll never believe all these patterns perform one basic action --
3135 ;; load a bit from the source, optionally invert the bit, then store it
3136 ;; in the destination (which is known to be zero).
3137 ;;
3138 ;; Combine obviously need some work to better identify this situation and
3139 ;; canonicalize the form better.
3141 ;;
3142 ;; Normal loads with a 16bit destination.
3143 ;;
3145 (define_insn ""
3146 [(set (match_operand:HI 0 "register_operand" "=&r")
3147 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3148 (const_int 1)
3149 (match_operand:HI 2 "immediate_operand" "n")))]
3150 "TARGET_H8300"
3151 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
3152 [(set_attr "length" "6")])
3154 ;;
3155 ;; Inverted loads with a 16bit destination.
3156 ;;
3158 (define_insn ""
3159 [(set (match_operand:HI 0 "register_operand" "=&r")
3160 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
3161 (match_operand:HI 3 "const_int_operand" "n"))
3162 (const_int 1)
3163 (match_operand:HI 2 "const_int_operand" "n")))]
3164 "TARGET_H8300
3165 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3166 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
3167 [(set_attr "length" "8")])
3169 ;;
3170 ;; Normal loads with a 32bit destination.
3171 ;;
3173 (define_insn "*extzv_1_r_h8300"
3174 [(set (match_operand:SI 0 "register_operand" "=&r")
3175 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
3176 (const_int 1)
3177 (match_operand 2 "const_int_operand" "n")))]
3178 "TARGET_H8300
3179 && INTVAL (operands[2]) < 16"
3180 "* return output_simode_bld (0, operands);"
3181 [(set_attr "length" "8")])
3183 (define_insn "*extzv_1_r_h8300hs"
3184 [(set (match_operand:SI 0 "register_operand" "=r,r")
3185 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3186 (const_int 1)
3187 (match_operand 2 "const_int_operand" "n,n")))]
3188 "(TARGET_H8300H || TARGET_H8300S)
3189 && INTVAL (operands[2]) < 16"
3190 "* return output_simode_bld (0, operands);"
3191 [(set_attr "cc" "set_znv,set_znv")
3192 (set_attr "length" "8,6")])
3194 ;;
3195 ;; Inverted loads with a 32bit destination.
3196 ;;
3198 (define_insn "*extzv_1_r_inv_h8300"
3199 [(set (match_operand:SI 0 "register_operand" "=&r")
3200 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
3201 (match_operand:HI 3 "const_int_operand" "n"))
3202 (const_int 1)
3203 (match_operand 2 "const_int_operand" "n")))]
3204 "TARGET_H8300
3205 && INTVAL (operands[2]) < 16
3206 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3207 "* return output_simode_bld (1, operands);"
3208 [(set_attr "length" "8")])
3210 (define_insn "*extzv_1_r_inv_h8300hs"
3211 [(set (match_operand:SI 0 "register_operand" "=r,r")
3212 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
3213 (match_operand 3 "const_int_operand" "n,n"))
3214 (const_int 1)
3215 (match_operand 2 "const_int_operand" "n,n")))]
3216 "(TARGET_H8300H || TARGET_H8300S)
3217 && INTVAL (operands[2]) < 16
3218 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3219 "* return output_simode_bld (1, operands);"
3220 [(set_attr "cc" "set_znv,set_znv")
3221 (set_attr "length" "8,6")])
3223 (define_expand "insv"
3224 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
3225 (match_operand:HI 1 "general_operand" "")
3226 (match_operand:HI 2 "general_operand" ""))
3227 (match_operand:HI 3 "general_operand" ""))]
3228 "TARGET_H8300 || TARGET_H8300SX"
3229 "
3230 {
3231 if (TARGET_H8300SX)
3232 {
3233 if (GET_CODE (operands[1]) == CONST_INT
3234 && GET_CODE (operands[2]) == CONST_INT
3235 && INTVAL (operands[1]) <= 8
3236 && INTVAL (operands[2]) >= 0
3237 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
3238 && memory_operand (operands[0], GET_MODE (operands[0])))
3239 {
3240 /* If the source operand is zero, it's better to use AND rather
3241 than BFST. Likewise OR if the operand is all ones. */
3242 if (GET_CODE (operands[3]) == CONST_INT)
3243 {
3244 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
3245 if ((INTVAL (operands[3]) & mask) == 0)
3246 FAIL;
3247 if ((INTVAL (operands[3]) & mask) == mask)
3248 FAIL;
3249 }
3250 if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
3251 {
3252 if (no_new_pseudos)
3253 FAIL;
3254 operands[0] =
3255 replace_equiv_address (operands[0],
3256 force_reg (Pmode,
3257 XEXP (operands[0], 0)));
3258 }
3259 operands[3] = gen_lowpart (QImode, operands[3]);
3260 if (! operands[3])
3261 FAIL;
3262 if (! register_operand (operands[3], QImode))
3263 {
3264 if (no_new_pseudos)
3265 FAIL;
3266 operands[3] = force_reg (QImode, operands[3]);
3267 }
3268 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
3269 operands[3], operands[1], operands[2]));
3270 DONE;
3271 }
3273 FAIL;
3274 }
3276 /* We only have single bit bit-field instructions. */
3277 if (INTVAL (operands[1]) != 1)
3278 FAIL;
3280 /* For now, we don't allow memory operands. */
3281 if (GET_CODE (operands[0]) == MEM
3282 || GET_CODE (operands[3]) == MEM)
3283 FAIL;
3284 }")
3286 (define_insn ""
3287 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
3288 (const_int 1)
3289 (match_operand:HI 1 "immediate_operand" "n"))
3290 (match_operand:HI 2 "register_operand" "r"))]
3291 ""
3292 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
3293 [(set_attr "length" "4")])
3295 (define_expand "extzv"
3296 [(set (match_operand:HI 0 "register_operand" "")
3297 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
3298 (match_operand:HI 2 "general_operand" "")
3299 (match_operand:HI 3 "general_operand" "")))]
3300 "TARGET_H8300 || TARGET_H8300SX"
3301 "
3302 {
3303 if (TARGET_H8300SX)
3304 {
3305 if (GET_CODE (operands[2]) == CONST_INT
3306 && GET_CODE (operands[3]) == CONST_INT
3307 && INTVAL (operands[2]) <= 8
3308 && INTVAL (operands[3]) >= 0
3309 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
3310 && memory_operand (operands[1], QImode))
3311 {
3312 rtx temp;
3314 /* Optimize the case where we're extracting into a paradoxical
3315 subreg. It's only necessary to extend to the inner reg. */
3316 if (GET_CODE (operands[0]) == SUBREG
3317 && subreg_lowpart_p (operands[0])
3318 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
3319 < GET_MODE_SIZE (GET_MODE (operands[0])))
3320 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
3321 == MODE_INT))
3322 operands[0] = SUBREG_REG (operands[0]);
3324 if (no_new_pseudos)
3325 temp = gen_lowpart (QImode, operands[0]);
3326 else
3327 temp = gen_reg_rtx (QImode);
3328 if (! temp)
3329 FAIL;
3330 if (! bit_memory_operand (operands[1], QImode))
3331 {
3332 if (no_new_pseudos)
3333 FAIL;
3334 operands[1] =
3335 replace_equiv_address (operands[1],
3336 force_reg (Pmode,
3337 XEXP (operands[1], 0)));
3338 }
3339 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
3340 convert_move (operands[0], temp, 1);
3341 DONE;
3342 }
3343 FAIL;
3344 }
3346 /* We only have single bit bit-field instructions. */
3347 if (INTVAL (operands[2]) != 1)
3348 FAIL;
3350 /* For now, we don't allow memory operands. */
3351 if (GET_CODE (operands[1]) == MEM)
3352 FAIL;
3353 }")
3355 ;; BAND, BOR, and BXOR patterns
3357 (define_insn ""
3358 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3359 (match_operator:HI 4 "bit_operator"
3360 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3361 (const_int 1)
3362 (match_operand:HI 2 "immediate_operand" "n"))
3363 (match_operand:HI 3 "bit_operand" "0")]))]
3364 ""
3365 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
3366 [(set_attr "length" "6")])
3368 (define_insn ""
3369 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3370 (match_operator:HI 5 "bit_operator"
3371 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3372 (const_int 1)
3373 (match_operand:HI 2 "immediate_operand" "n"))
3374 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
3375 (const_int 1)
3376 (match_operand:HI 4 "immediate_operand" "n"))]))]
3377 ""
3378 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
3379 [(set_attr "length" "6")])
3381 (define_insn "bfld"
3382 [(set (match_operand:QI 0 "register_operand" "=r")
3383 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU")
3384 (match_operand:QI 2 "immediate_operand" "n")
3385 (match_operand:QI 3 "immediate_operand" "n")))]
3386 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3387 "*
3388 {
3389 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3390 - (1 << INTVAL (operands[3])));
3391 return \"bfld %2,%1,%R0\";
3392 }"
3393 [(set_attr "cc" "none_0hit")
3394 (set_attr "length_table" "bitfield")])
3396 (define_insn "bfst"
3397 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3398 (match_operand:QI 2 "immediate_operand" "n")
3399 (match_operand:QI 3 "immediate_operand" "n"))
3400 (match_operand:QI 1 "register_operand" "r"))]
3401 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3402 "*
3403 {
3404 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3405 - (1 << INTVAL (operands[3])));
3406 return \"bfst %R1,%2,%0\";
3407 }"
3408 [(set_attr "cc" "none_0hit")
3409 (set_attr "length_table" "bitfield")])
3411 (define_expand "seq"
3412 [(set (match_operand:HI 0 "register_operand" "")
3413 (eq:HI (cc0) (const_int 0)))]
3414 "TARGET_H8300SX"
3415 "")
3417 (define_expand "sne"
3418 [(set (match_operand:HI 0 "register_operand" "")
3419 (ne:HI (cc0) (const_int 0)))]
3420 "TARGET_H8300SX"
3421 "")
3423 (define_insn "*bstzhireg"
3424 [(set (match_operand:HI 0 "register_operand" "=r")
3425 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))]
3426 "TARGET_H8300SX"
3427 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:"
3428 [(set_attr "cc" "clobber")])
3430 (define_insn_and_split "*cmpstz"
3431 [(set (zero_extract:QI
3432 (match_operand:QI 0 "bit_memory_operand" "+WU,+WU")
3433 (const_int 1)
3434 (match_operand:QI 1 "immediate_operand" "n,n"))
3435 (match_operator:QI
3436 2 "eqne_operator"
3437 [(match_operand 3 "h8300_dst_operand" "r,rQ")
3438 (match_operand 4 "h8300_src_operand" "I,rQi")]))]
3439 "TARGET_H8300SX
3440 && (GET_MODE (operands[3]) == GET_MODE (operands[4])
3441 || GET_CODE (operands[4]) == CONST_INT)
3442 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
3443 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
3444 "#"
3445 "reload_completed"
3446 [(set (cc0) (match_dup 5))
3447 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1))
3448 (match_op_dup:QI 2 [(cc0) (const_int 0)]))]
3449 "
3450 {
3451 if (operands[4] == const0_rtx && GET_CODE (operands[3]) == REG)
3452 operands[5] = operands[3];
3453 else
3454 operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);
3455 }"
3456 [(set_attr "cc" "set_znv,compare")])
3458 (define_insn "*bstz"
3459 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3460 (const_int 1)
3461 (match_operand:QI 1 "immediate_operand" "n"))
3462 (eq:QI (cc0) (const_int 0)))]
3463 "TARGET_H8300SX && reload_completed"
3464 "bstz %1,%0"
3465 [(set_attr "cc" "none_0hit")
3466 (set_attr "length_table" "unary")])
3468 (define_insn "*bistz"
3469 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3470 (const_int 1)
3471 (match_operand:QI 1 "immediate_operand" "n"))
3472 (ne:QI (cc0) (const_int 0)))]
3473 "TARGET_H8300SX && reload_completed"
3474 "bistz %1,%0"
3475 [(set_attr "cc" "none_0hit")
3476 (set_attr "length_table" "unary")])
3478 (define_insn_and_split "*cmpcondbset"
3479 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3480 (if_then_else:QI
3481 (match_operator
3482 1 "eqne_operator"
3483 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3484 (match_operand 3 "h8300_src_operand" "I,rQi")])
3485 (ior:QI
3486 (match_operand:QI 4 "bit_memory_operand" "0,0")
3487 (match_operand:QI 5 "single_one_operand" "n,n"))
3488 (match_dup 4)))]
3489 "TARGET_H8300SX"
3490 "#"
3491 "reload_completed"
3492 [(set (cc0) (match_dup 6))
3493 (set (match_dup 0)
3494 (if_then_else:QI
3495 (match_op_dup 1 [(cc0) (const_int 0)])
3496 (ior:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3497 "
3498 {
3499 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3500 operands[6] = operands[2];
3501 else
3502 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3503 }"
3504 [(set_attr "cc" "set_znv,compare")])
3506 (define_insn "*condbset"
3507 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3508 (if_then_else:QI
3509 (match_operator:QI 2 "eqne_operator"
3510 [(cc0) (const_int 0)])
3511 (ior:QI
3512 (match_operand:QI 3 "bit_memory_operand" "0")
3513 (match_operand:QI 1 "single_one_operand" "n"))
3514 (match_dup 3)))]
3515 "TARGET_H8300SX && reload_completed"
3516 "bset/%j2\t%V1,%0"
3517 [(set_attr "cc" "none_0hit")
3518 (set_attr "length_table" "logicb")])
3520 (define_insn_and_split "*cmpcondbclr"
3521 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3522 (if_then_else:QI
3523 (match_operator
3524 1 "eqne_operator"
3525 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3526 (match_operand 3 "h8300_src_operand" "I,rQi")])
3527 (and:QI
3528 (match_operand:QI 4 "bit_memory_operand" "0,0")
3529 (match_operand:QI 5 "single_zero_operand" "n,n"))
3530 (match_dup 4)))]
3531 "TARGET_H8300SX"
3532 "#"
3533 "reload_completed"
3534 [(set (cc0) (match_dup 6))
3535 (set (match_dup 0)
3536 (if_then_else:QI
3537 (match_op_dup 1 [(cc0) (const_int 0)])
3538 (and:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3539 "
3540 {
3541 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3542 operands[6] = operands[2];
3543 else
3544 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3545 }"
3546 [(set_attr "cc" "set_znv,compare")])
3548 (define_insn "*condbclr"
3549 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3550 (if_then_else:QI
3551 (match_operator:QI 2 "eqne_operator"
3552 [(cc0) (const_int 0)])
3553 (and:QI
3554 (match_operand:QI 3 "bit_memory_operand" "0")
3555 (match_operand:QI 1 "single_zero_operand" "n"))
3556 (match_dup 3)))]
3557 "TARGET_H8300SX && reload_completed"
3558 "bclr/%j2\t%W1,%0"
3559 [(set_attr "cc" "none_0hit")
3560 (set_attr "length_table" "logicb")])
3562 (define_insn_and_split "*cmpcondbsetreg"
3563 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3564 (if_then_else:QI
3565 (match_operator
3566 1 "eqne_operator"
3567 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3568 (match_operand 3 "h8300_src_operand" "I,rQi")])
3569 (ior:QI
3570 (match_operand:QI 4 "bit_memory_operand" "0,0")
3571 (ashift:QI (const_int 1)
3572 (match_operand:QI 5 "register_operand" "r,r")))
3573 (match_dup 4)))]
3574 "TARGET_H8300SX"
3575 "#"
3576 "reload_completed"
3577 [(set (cc0) (match_dup 6))
3578 (set (match_dup 0)
3579 (if_then_else:QI
3580 (match_op_dup 1 [(cc0) (const_int 0)])
3581 (ior:QI (match_dup 4)
3582 (ashift:QI (const_int 1)
3583 (match_operand:QI 5 "register_operand" "r,r")))
3584 (match_dup 4)))]
3585 "
3586 {
3587 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3588 operands[6] = operands[2];
3589 else
3590 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3591 }"
3592 [(set_attr "cc" "set_znv,compare")])
3594 (define_insn "*condbsetreg"
3595 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3596 (if_then_else:QI
3597 (match_operator:QI 2 "eqne_operator"
3598 [(cc0) (const_int 0)])
3599 (ior:QI
3600 (match_operand:QI 3 "bit_memory_operand" "0")
3601 (ashift:QI (const_int 1)
3602 (match_operand:QI 1 "register_operand" "r")))
3603 (match_dup 3)))]
3604 "TARGET_H8300SX && reload_completed"
3605 "bset/%j2\t%R1,%0"
3606 [(set_attr "cc" "none_0hit")
3607 (set_attr "length_table" "logicb")])
3609 (define_insn_and_split "*cmpcondbclrreg"
3610 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3611 (if_then_else:QI
3612 (match_operator
3613 1 "eqne_operator"
3614 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3615 (match_operand 3 "h8300_src_operand" "I,rQi")])
3616 (and:QI
3617 (match_operand:QI 4 "bit_memory_operand" "0,0")
3618 (ashift:QI (const_int 1)
3619 (match_operand:QI 5 "register_operand" "r,r")))
3620 (match_dup 4)))]
3621 "TARGET_H8300SX"
3622 "#"
3623 "reload_completed"
3624 [(set (cc0) (match_dup 6))
3625 (set (match_dup 0)
3626 (if_then_else:QI
3627 (match_op_dup 1 [(cc0) (const_int 0)])
3628 (and:QI (match_dup 4)
3629 (ashift:QI (const_int 1)
3630 (match_operand:QI 5 "register_operand" "r,r")))
3631 (match_dup 4)))]
3632 "
3633 {
3634 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3635 operands[6] = operands[2];
3636 else
3637 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3638 }"
3639 [(set_attr "cc" "set_znv,compare")])
3641 (define_insn "*condbclrreg"
3642 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3643 (if_then_else:QI
3644 (match_operator:QI 2 "eqne_operator"
3645 [(cc0) (const_int 0)])
3646 (and:QI
3647 (match_operand:QI 3 "bit_memory_operand" "0")
3648 (ashift:QI (const_int 1)
3649 (match_operand:QI 1 "register_operand" "r")))
3650 (match_dup 3)))]
3651 "TARGET_H8300SX && reload_completed"
3652 "bclr/%j2\t%R1,%0"
3653 [(set_attr "cc" "none_0hit")
3654 (set_attr "length_table" "logicb")])
3656 \f
3657 ;; -----------------------------------------------------------------
3658 ;; COMBINE PATTERNS
3659 ;; -----------------------------------------------------------------
3661 ;; insv:SI
3663 (define_insn "*insv_si_1_n"
3664 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3665 (const_int 1)
3666 (match_operand:SI 1 "const_int_operand" "n"))
3667 (match_operand:SI 2 "register_operand" "r"))]
3668 "(TARGET_H8300H || TARGET_H8300S)
3669 && INTVAL (operands[1]) < 16"
3670 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
3671 [(set_attr "length" "4")])
3673 (define_insn "*insv_si_1_n_lshiftrt"
3674 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3675 (const_int 1)
3676 (match_operand:SI 1 "const_int_operand" "n"))
3677 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3678 (match_operand:SI 3 "const_int_operand" "n")))]
3679 "(TARGET_H8300H || TARGET_H8300S)
3680 && INTVAL (operands[1]) < 16
3681 && INTVAL (operands[3]) < 16"
3682 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
3683 [(set_attr "length" "4")])
3685 (define_insn "*insv_si_1_n_lshiftrt_16"
3686 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3687 (const_int 1)
3688 (match_operand:SI 1 "const_int_operand" "n"))
3689 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3690 (const_int 16)))]
3691 "(TARGET_H8300H || TARGET_H8300S)
3692 && INTVAL (operands[1]) < 16"
3693 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
3694 [(set_attr "length" "6")])
3696 (define_insn "*insv_si_8_8"
3697 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3698 (const_int 8)
3699 (const_int 8))
3700 (match_operand:SI 1 "register_operand" "r"))]
3701 "TARGET_H8300H || TARGET_H8300S"
3702 "mov.b\\t%w1,%x0"
3703 [(set_attr "length" "2")])
3705 (define_insn "*insv_si_8_8_lshiftrt_8"
3706 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3707 (const_int 8)
3708 (const_int 8))
3709 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3710 (const_int 8)))]
3711 "TARGET_H8300H || TARGET_H8300S"
3712 "mov.b\\t%x1,%x0"
3713 [(set_attr "length" "2")])
3715 ;; extzv:SI
3717 (define_insn "*extzv_8_8"
3718 [(set (match_operand:SI 0 "register_operand" "=r,r")
3719 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3720 (const_int 8)
3721 (const_int 8)))]
3722 "TARGET_H8300H || TARGET_H8300S"
3723 "@
3724 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
3725 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
3726 [(set_attr "cc" "set_znv,clobber")
3727 (set_attr "length" "6,4")])
3729 (define_insn "*extzv_8_16"
3730 [(set (match_operand:SI 0 "register_operand" "=r")
3731 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3732 (const_int 8)
3733 (const_int 16)))]
3734 "TARGET_H8300H || TARGET_H8300S"
3735 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3736 [(set_attr "cc" "set_znv")
3737 (set_attr "length" "6")])
3739 (define_insn "*extzv_16_8"
3740 [(set (match_operand:SI 0 "register_operand" "=r")
3741 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3742 (const_int 16)
3743 (const_int 8)))
3744 (clobber (match_scratch:SI 2 "=&r"))]
3745 "TARGET_H8300H"
3746 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3747 [(set_attr "length" "8")
3748 (set_attr "cc" "set_znv")])
3750 ;; Extract the exponent of a float.
3752 (define_insn_and_split "*extzv_8_23"
3753 [(set (match_operand:SI 0 "register_operand" "=r")
3754 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3755 (const_int 8)
3756 (const_int 23)))]
3757 "(TARGET_H8300H || TARGET_H8300S)"
3758 "#"
3759 "&& reload_completed"
3760 [(parallel [(set (match_dup 0)
3761 (ashift:SI (match_dup 0)
3762 (const_int 1)))
3763 (clobber (scratch:QI))])
3764 (parallel [(set (match_dup 0)
3765 (lshiftrt:SI (match_dup 0)
3766 (const_int 24)))
3767 (clobber (scratch:QI))])]
3768 "")
3770 ;; and:SI
3772 ;; ((SImode) HImode) << 15
3774 (define_insn_and_split "*twoshifts_l16_r1"
3775 [(set (match_operand:SI 0 "register_operand" "=r")
3776 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3777 (const_int 15))
3778 (const_int 2147450880)))]
3779 "(TARGET_H8300H || TARGET_H8300S)"
3780 "#"
3781 "&& reload_completed"
3782 [(parallel [(set (match_dup 0)
3783 (ashift:SI (match_dup 0)
3784 (const_int 16)))
3785 (clobber (scratch:QI))])
3786 (parallel [(set (match_dup 0)
3787 (lshiftrt:SI (match_dup 0)
3788 (const_int 1)))
3789 (clobber (scratch:QI))])]
3790 "")
3792 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3794 (define_insn_and_split "*andsi3_ashift_n_lower"
3795 [(set (match_operand:SI 0 "register_operand" "=r,r")
3796 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3797 (match_operand:QI 2 "const_int_operand" "S,n"))
3798 (match_operand:SI 3 "const_int_operand" "n,n")))
3799 (clobber (match_scratch:QI 4 "=X,&r"))]
3800 "(TARGET_H8300H || TARGET_H8300S)
3801 && INTVAL (operands[2]) <= 15
3802 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
3803 "#"
3804 "&& reload_completed"
3805 [(parallel [(set (match_dup 5)
3806 (ashift:HI (match_dup 5)
3807 (match_dup 2)))
3808 (clobber (match_dup 4))])
3809 (set (match_dup 0)
3810 (zero_extend:SI (match_dup 5)))]
3811 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3813 ;; Accept (A >> 30) & 2 and the like.
3815 (define_insn "*andsi3_lshiftrt_n_sb"
3816 [(set (match_operand:SI 0 "register_operand" "=r")
3817 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3818 (match_operand:SI 2 "const_int_operand" "n"))
3819 (match_operand:SI 3 "single_one_operand" "n")))]
3820 "(TARGET_H8300H || TARGET_H8300S)
3821 && exact_log2 (INTVAL (operands[3])) < 16
3822 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3823 "*
3824 {
3825 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3826 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
3827 }"
3828 [(set_attr "length" "8")])
3830 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3831 [(set (match_operand:SI 0 "register_operand" "=r")
3832 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3833 (const_int 9))
3834 (const_int 4194304)))]
3835 "(TARGET_H8300H || TARGET_H8300S)"
3836 "#"
3837 "&& reload_completed"
3838 [(set (match_dup 0)
3839 (and:SI (lshiftrt:SI (match_dup 0)
3840 (const_int 25))
3841 (const_int 64)))
3842 (parallel [(set (match_dup 0)
3843 (ashift:SI (match_dup 0)
3844 (const_int 16)))
3845 (clobber (scratch:QI))])]
3846 "")
3848 ;; plus:SI
3850 (define_insn "*addsi3_upper"
3851 [(set (match_operand:SI 0 "register_operand" "=r")
3852 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3853 (const_int 65536))
3854 (match_operand:SI 2 "register_operand" "0")))]
3855 "TARGET_H8300H || TARGET_H8300S"
3856 "add.w\\t%f1,%e0"
3857 [(set_attr "length" "2")])
3859 (define_insn "*addsi3_lshiftrt_16_zexthi"
3860 [(set (match_operand:SI 0 "register_operand" "=r")
3861 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3862 (const_int 16))
3863 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3864 "TARGET_H8300H || TARGET_H8300S"
3865 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3866 [(set_attr "length" "6")])
3868 (define_insn_and_split "*addsi3_and_r_1"
3869 [(set (match_operand:SI 0 "register_operand" "=r")
3870 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3871 (const_int 1))
3872 (match_operand:SI 2 "register_operand" "0")))]
3873 "(TARGET_H8300H || TARGET_H8300S)"
3874 "#"
3875 "&& reload_completed"
3876 [(set (cc0)
3877 (zero_extract:SI (match_dup 1)
3878 (const_int 1)
3879 (const_int 0)))
3880 (set (pc)
3881 (if_then_else (eq (cc0)
3882 (const_int 0))
3883 (label_ref (match_dup 3))
3884 (pc)))
3885 (set (match_dup 2)
3886 (plus:SI (match_dup 2)
3887 (const_int 1)))
3888 (match_dup 3)]
3889 "operands[3] = gen_label_rtx ();")
3891 (define_insn_and_split "*addsi3_and_not_r_1"
3892 [(set (match_operand:SI 0 "register_operand" "=r")
3893 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3894 (const_int 1))
3895 (match_operand:SI 2 "register_operand" "0")))]
3896 "(TARGET_H8300H || TARGET_H8300S)"
3897 "#"
3898 "&& reload_completed"
3899 [(set (cc0)
3900 (zero_extract:SI (match_dup 1)
3901 (const_int 1)
3902 (const_int 0)))
3903 (set (pc)
3904 (if_then_else (ne (cc0)
3905 (const_int 0))
3906 (label_ref (match_dup 3))
3907 (pc)))
3908 (set (match_dup 2)
3909 (plus:SI (match_dup 2)
3910 (const_int 1)))
3911 (match_dup 3)]
3912 "operands[3] = gen_label_rtx ();")
3914 ;; [ix]or:HI
3916 (define_insn "*ixorhi3_zext"
3917 [(set (match_operand:HI 0 "register_operand" "=r")
3918 (match_operator:HI 1 "iorxor_operator"
3919 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3920 (match_operand:HI 3 "register_operand" "0")]))]
3921 ""
3922 "%c1.b\\t%X2,%s0"
3923 [(set_attr "length" "2")])
3925 ;; [ix]or:SI
3927 (define_insn "*ixorsi3_zext_qi"
3928 [(set (match_operand:SI 0 "register_operand" "=r")
3929 (match_operator:SI 1 "iorxor_operator"
3930 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3931 (match_operand:SI 3 "register_operand" "0")]))]
3932 ""
3933 "%c1.b\\t%X2,%w0"
3934 [(set_attr "length" "2")])
3936 (define_insn "*ixorsi3_zext_hi"
3937 [(set (match_operand:SI 0 "register_operand" "=r")
3938 (match_operator:SI 1 "iorxor_operator"
3939 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3940 (match_operand:SI 3 "register_operand" "0")]))]
3941 "TARGET_H8300H || TARGET_H8300S"
3942 "%c1.w\\t%T2,%f0"
3943 [(set_attr "length" "2")])
3945 (define_insn "*ixorsi3_ashift_16"
3946 [(set (match_operand:SI 0 "register_operand" "=r")
3947 (match_operator:SI 1 "iorxor_operator"
3948 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3949 (const_int 16))
3950 (match_operand:SI 3 "register_operand" "0")]))]
3951 "TARGET_H8300H || TARGET_H8300S"
3952 "%c1.w\\t%f2,%e0"
3953 [(set_attr "length" "2")])
3955 (define_insn "*ixorsi3_lshiftrt_16"
3956 [(set (match_operand:SI 0 "register_operand" "=r")
3957 (match_operator:SI 1 "iorxor_operator"
3958 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3959 (const_int 16))
3960 (match_operand:SI 3 "register_operand" "0")]))]
3961 "TARGET_H8300H || TARGET_H8300S"
3962 "%c1.w\\t%e2,%f0"
3963 [(set_attr "length" "2")])
3965 ;; ior:HI
3967 (define_insn "*iorhi3_ashift_8"
3968 [(set (match_operand:HI 0 "register_operand" "=r")
3969 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3970 (const_int 8))
3971 (match_operand:HI 2 "register_operand" "0")))]
3972 ""
3973 "or.b\\t%s1,%t0"
3974 [(set_attr "length" "2")])
3976 (define_insn "*iorhi3_lshiftrt_8"
3977 [(set (match_operand:HI 0 "register_operand" "=r")
3978 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3979 (const_int 8))
3980 (match_operand:HI 2 "register_operand" "0")))]
3981 ""
3982 "or.b\\t%t1,%s0"
3983 [(set_attr "length" "2")])
3985 (define_insn "*iorhi3_two_qi"
3986 [(set (match_operand:HI 0 "register_operand" "=r")
3987 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3988 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3989 (const_int 8))))]
3990 ""
3991 "mov.b\\t%s2,%t0"
3992 [(set_attr "length" "2")])
3994 (define_insn "*iorhi3_two_qi_mem"
3995 [(set (match_operand:HI 0 "register_operand" "=&r")
3996 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3997 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3998 (const_int 8))))]
3999 ""
4000 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
4001 [(set_attr "length" "16")])
4003 (define_split
4004 [(set (match_operand:HI 0 "register_operand" "")
4005 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
4006 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
4007 (const_int 8))))]
4008 "(TARGET_H8300H || TARGET_H8300S)
4009 && reload_completed
4010 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
4011 [(set (match_dup 0)
4012 (match_dup 3))]
4013 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
4015 ;; ior:SI
4017 (define_insn "*iorsi3_two_hi"
4018 [(set (match_operand:SI 0 "register_operand" "=r")
4019 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
4020 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4021 (const_int 16))))]
4022 "TARGET_H8300H || TARGET_H8300S"
4023 "mov.w\\t%f2,%e0"
4024 [(set_attr "length" "2")])
4026 (define_insn_and_split "*iorsi3_two_qi_zext"
4027 [(set (match_operand:SI 0 "register_operand" "=&r")
4028 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
4030 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4031 (const_int 8))
4032 (const_int 65280))))]
4033 "(TARGET_H8300H || TARGET_H8300S)"
4034 "#"
4035 "&& reload_completed"
4036 [(set (match_dup 3)
4037 (ior:HI (zero_extend:HI (match_dup 1))
4038 (ashift:HI (subreg:HI (match_dup 2) 0)
4039 (const_int 8))))
4040 (set (match_dup 0)
4041 (zero_extend:SI (match_dup 3)))]
4042 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4044 (define_insn "*iorsi3_e2f"
4045 [(set (match_operand:SI 0 "register_operand" "=r")
4046 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4047 (const_int -65536))
4048 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4049 (const_int 16))))]
4050 "TARGET_H8300H || TARGET_H8300S"
4051 "mov.w\\t%e2,%f0"
4052 [(set_attr "length" "2")])
4054 (define_insn_and_split "*iorsi3_two_qi_sext"
4055 [(set (match_operand:SI 0 "register_operand" "=r")
4056 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
4057 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
4058 (const_int 8))))]
4059 "(TARGET_H8300H || TARGET_H8300S)"
4060 "#"
4061 "&& reload_completed"
4062 [(set (match_dup 3)
4063 (ior:HI (zero_extend:HI (match_dup 1))
4064 (ashift:HI (match_dup 4)
4065 (const_int 8))))
4066 (set (match_dup 0)
4067 (sign_extend:SI (match_dup 3)))]
4068 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4069 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4071 (define_insn "*iorsi3_w"
4072 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4073 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
4074 (const_int -256))
4075 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
4076 "TARGET_H8300H || TARGET_H8300S"
4077 "mov.b\\t%X2,%w0"
4078 [(set_attr "length" "2,8")])
4080 (define_insn "*iorsi3_ashift_31"
4081 [(set (match_operand:SI 0 "register_operand" "=&r")
4082 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4083 (const_int 31))
4084 (match_operand:SI 2 "register_operand" "0")))]
4085 "TARGET_H8300H || TARGET_H8300S"
4086 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
4087 [(set_attr "length" "6")
4088 (set_attr "cc" "set_znv")])
4090 (define_insn "*iorsi3_and_ashift"
4091 [(set (match_operand:SI 0 "register_operand" "=r")
4092 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4093 (match_operand:SI 2 "const_int_operand" "n"))
4094 (match_operand:SI 3 "single_one_operand" "n"))
4095 (match_operand:SI 4 "register_operand" "0")))]
4096 "(TARGET_H8300H || TARGET_H8300S)
4097 && (INTVAL (operands[3]) & ~0xffff) == 0"
4098 "*
4099 {
4100 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4101 - INTVAL (operands[2]));
4102 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4103 operands[2] = srcpos;
4104 operands[3] = dstpos;
4105 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4106 }"
4107 [(set_attr "length" "6")])
4109 (define_insn "*iorsi3_and_lshiftrt"
4110 [(set (match_operand:SI 0 "register_operand" "=r")
4111 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4112 (match_operand:SI 2 "const_int_operand" "n"))
4113 (match_operand:SI 3 "single_one_operand" "n"))
4114 (match_operand:SI 4 "register_operand" "0")))]
4115 "(TARGET_H8300H || TARGET_H8300S)
4116 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
4117 "*
4118 {
4119 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4120 + INTVAL (operands[2]));
4121 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4122 operands[2] = srcpos;
4123 operands[3] = dstpos;
4124 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4125 }"
4126 [(set_attr "length" "6")])
4128 (define_insn "*iorsi3_zero_extract"
4129 [(set (match_operand:SI 0 "register_operand" "=r")
4130 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
4131 (const_int 1)
4132 (match_operand:SI 2 "const_int_operand" "n"))
4133 (match_operand:SI 3 "register_operand" "0")))]
4134 "(TARGET_H8300H || TARGET_H8300S)
4135 && INTVAL (operands[2]) < 16"
4136 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
4137 [(set_attr "length" "6")])
4139 (define_insn "*iorsi3_and_lshiftrt_n_sb"
4140 [(set (match_operand:SI 0 "register_operand" "=r")
4141 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4142 (const_int 30))
4143 (const_int 2))
4144 (match_operand:SI 2 "register_operand" "0")))]
4145 "(TARGET_H8300H || TARGET_H8300S)"
4146 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
4147 [(set_attr "length" "8")])
4149 (define_insn "*iorsi3_and_lshiftrt_9_sb"
4150 [(set (match_operand:SI 0 "register_operand" "=r")
4151 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4152 (const_int 9))
4153 (const_int 4194304))
4154 (match_operand:SI 2 "register_operand" "0")))
4155 (clobber (match_scratch:HI 3 "=&r"))]
4156 "(TARGET_H8300H || TARGET_H8300S)"
4157 "*
4158 {
4159 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4160 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4161 else
4162 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4163 }"
4164 [(set_attr "length" "10")])
4166 ;; Used to OR the exponent of a float.
4168 (define_insn "*iorsi3_shift"
4169 [(set (match_operand:SI 0 "register_operand" "=r")
4170 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4171 (const_int 23))
4172 (match_operand:SI 2 "register_operand" "0")))
4173 (clobber (match_scratch:SI 3 "=&r"))]
4174 "TARGET_H8300H || TARGET_H8300S"
4175 "#")
4177 (define_split
4178 [(set (match_operand:SI 0 "register_operand" "")
4179 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4180 (const_int 23))
4181 (match_dup 0)))
4182 (clobber (match_operand:SI 2 "register_operand" ""))]
4183 "(TARGET_H8300H || TARGET_H8300S)
4184 && flow2_completed
4185 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4186 && REGNO (operands[0]) != REGNO (operands[1])"
4187 [(parallel [(set (match_dup 3)
4188 (ashift:HI (match_dup 3)
4189 (const_int 7)))
4190 (clobber (scratch:QI))])
4191 (set (match_dup 0)
4192 (ior:SI (ashift:SI (match_dup 1)
4193 (const_int 16))
4194 (match_dup 0)))]
4195 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4197 (define_split
4198 [(set (match_operand:SI 0 "register_operand" "")
4199 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4200 (const_int 23))
4201 (match_dup 0)))
4202 (clobber (match_operand:SI 2 "register_operand" ""))]
4203 "(TARGET_H8300H || TARGET_H8300S)
4204 && flow2_completed
4205 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4206 && REGNO (operands[0]) != REGNO (operands[1]))"
4207 [(set (match_dup 2)
4208 (match_dup 1))
4209 (parallel [(set (match_dup 3)
4210 (ashift:HI (match_dup 3)
4211 (const_int 7)))
4212 (clobber (scratch:QI))])
4213 (set (match_dup 0)
4214 (ior:SI (ashift:SI (match_dup 2)
4215 (const_int 16))
4216 (match_dup 0)))]
4217 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4219 (define_insn "*iorsi2_and_1_lshiftrt_1"
4220 [(set (match_operand:SI 0 "register_operand" "=r")
4221 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4222 (const_int 1))
4223 (lshiftrt:SI (match_dup 1)
4224 (const_int 1))))]
4225 "TARGET_H8300H || TARGET_H8300S"
4226 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
4227 [(set_attr "length" "6")])
4229 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
4230 [(set (match_operand:SI 0 "register_operand" "=r")
4231 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4232 (const_int 16))
4233 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4234 (const_int 24))))]
4235 "(TARGET_H8300H || TARGET_H8300S)"
4236 "#"
4237 "&& reload_completed"
4238 [(set (match_dup 3)
4239 (ior:HI (ashift:HI (match_dup 4)
4240 (const_int 8))
4241 (match_dup 3)))
4242 (parallel [(set (match_dup 0)
4243 (ashift:SI (match_dup 0)
4244 (const_int 16)))
4245 (clobber (scratch:QI))])]
4246 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4247 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4249 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
4250 [(set (match_operand:SI 0 "register_operand" "=&r")
4251 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
4252 (const_int 16))
4253 (const_int 16711680))
4254 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4255 (const_int 24))))]
4256 "(TARGET_H8300H || TARGET_H8300S)"
4257 "#"
4258 "&& reload_completed"
4259 [(set (match_dup 3)
4260 (ior:HI (zero_extend:HI (match_dup 1))
4261 (ashift:HI (subreg:HI (match_dup 2) 0)
4262 (const_int 8))))
4263 (parallel [(set (match_dup 0)
4264 (ashift:SI (match_dup 0)
4265 (const_int 16)))
4266 (clobber (scratch:QI))])]
4267 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4269 ;; Used to add the exponent of a float.
4271 (define_insn "*addsi3_shift"
4272 [(set (match_operand:SI 0 "register_operand" "=r")
4273 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4274 (const_int 8388608))
4275 (match_operand:SI 2 "register_operand" "0")))
4276 (clobber (match_scratch:SI 3 "=&r"))]
4277 "TARGET_H8300H || TARGET_H8300S"
4278 "#")
4280 (define_split
4281 [(set (match_operand:SI 0 "register_operand" "")
4282 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4283 (const_int 8388608))
4284 (match_dup 0)))
4285 (clobber (match_operand:SI 2 "register_operand" ""))]
4286 "(TARGET_H8300H || TARGET_H8300S)
4287 && flow2_completed
4288 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4289 && REGNO (operands[0]) != REGNO (operands[1])"
4290 [(parallel [(set (match_dup 3)
4291 (ashift:HI (match_dup 3)
4292 (const_int 7)))
4293 (clobber (scratch:QI))])
4294 (set (match_dup 0)
4295 (plus:SI (mult:SI (match_dup 1)
4296 (const_int 65536))
4297 (match_dup 0)))]
4298 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4300 (define_split
4301 [(set (match_operand:SI 0 "register_operand" "")
4302 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4303 (const_int 8388608))
4304 (match_dup 0)))
4305 (clobber (match_operand:SI 2 "register_operand" ""))]
4306 "(TARGET_H8300H || TARGET_H8300S)
4307 && flow2_completed
4308 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4309 && REGNO (operands[0]) != REGNO (operands[1]))"
4310 [(set (match_dup 2)
4311 (match_dup 1))
4312 (parallel [(set (match_dup 3)
4313 (ashift:HI (match_dup 3)
4314 (const_int 7)))
4315 (clobber (scratch:QI))])
4316 (set (match_dup 0)
4317 (plus:SI (mult:SI (match_dup 2)
4318 (const_int 65536))
4319 (match_dup 0)))]
4320 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4322 ;; ashift:SI
4324 (define_insn_and_split "*ashiftsi_sextqi_7"
4325 [(set (match_operand:SI 0 "register_operand" "=r")
4326 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
4327 (const_int 7)))]
4328 "(TARGET_H8300H || TARGET_H8300S)"
4329 "#"
4330 "&& reload_completed"
4331 [(parallel [(set (match_dup 2)
4332 (ashift:HI (match_dup 2)
4333 (const_int 8)))
4334 (clobber (scratch:QI))])
4335 (set (match_dup 0)
4336 (sign_extend:SI (match_dup 2)))
4337 (parallel [(set (match_dup 0)
4338 (ashiftrt:SI (match_dup 0)
4339 (const_int 1)))
4340 (clobber (scratch:QI))])]
4341 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4343 ;; Storing a part of HImode to QImode.
4345 (define_insn ""
4346 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4347 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4348 (const_int 8)) 1))]
4349 ""
4350 "mov.b\\t%t1,%R0"
4351 [(set_attr "cc" "set_znv")
4352 (set_attr "length" "8")])
4354 ;; Storing a part of SImode to QImode.
4356 (define_insn ""
4357 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4358 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4359 (const_int 8)) 3))]
4360 ""
4361 "mov.b\\t%x1,%R0"
4362 [(set_attr "cc" "set_znv")
4363 (set_attr "length" "8")])
4365 (define_insn ""
4366 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4367 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4368 (const_int 16)) 3))
4369 (clobber (match_scratch:SI 2 "=&r"))]
4370 "TARGET_H8300H || TARGET_H8300S"
4371 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
4372 [(set_attr "cc" "set_znv")
4373 (set_attr "length" "10")])
4375 (define_insn ""
4376 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4377 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4378 (const_int 24)) 3))
4379 (clobber (match_scratch:SI 2 "=&r"))]
4380 "TARGET_H8300H || TARGET_H8300S"
4381 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
4382 [(set_attr "cc" "set_znv")
4383 (set_attr "length" "10")])
4385 (define_insn_and_split ""
4386 [(set (pc)
4387 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4388 (const_int 1)
4389 (const_int 7))
4390 (const_int 0))
4391 (label_ref (match_operand 1 "" ""))
4392 (pc)))]
4393 ""
4394 "#"
4395 ""
4396 [(set (cc0)
4397 (match_dup 0))
4398 (set (pc)
4399 (if_then_else (ge (cc0)
4400 (const_int 0))
4401 (label_ref (match_dup 1))
4402 (pc)))]
4403 "")
4405 (define_insn_and_split ""
4406 [(set (pc)
4407 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4408 (const_int 1)
4409 (const_int 7))
4410 (const_int 0))
4411 (label_ref (match_operand 1 "" ""))
4412 (pc)))]
4413 ""
4414 "#"
4415 ""
4416 [(set (cc0)
4417 (match_dup 0))
4418 (set (pc)
4419 (if_then_else (lt (cc0)
4420 (const_int 0))
4421 (label_ref (match_dup 1))
4422 (pc)))]
4423 "")
4424 \f
4425 ;; -----------------------------------------------------------------
4426 ;; PEEPHOLE PATTERNS
4427 ;; -----------------------------------------------------------------
4429 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4431 (define_peephole2
4432 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4433 (lshiftrt:HI (match_dup 0)
4434 (match_operand:HI 1 "const_int_operand" "")))
4435 (clobber (match_operand:HI 2 "" ""))])
4436 (set (match_dup 0)
4437 (and:HI (match_dup 0)
4438 (match_operand:HI 3 "const_int_operand" "")))]
4439 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4440 [(set (match_dup 0)
4441 (and:HI (match_dup 0)
4442 (const_int 255)))
4443 (parallel
4444 [(set (match_dup 0)
4445 (lshiftrt:HI (match_dup 0)
4446 (match_dup 1)))
4447 (clobber (match_dup 2))])]
4448 "")
4450 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4452 (define_peephole2
4453 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4454 (ashift:HI (match_dup 0)
4455 (match_operand:HI 1 "const_int_operand" "")))
4456 (clobber (match_operand:HI 2 "" ""))])
4457 (set (match_dup 0)
4458 (and:HI (match_dup 0)
4459 (match_operand:HI 3 "const_int_operand" "")))]
4460 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4461 [(set (match_dup 0)
4462 (and:HI (match_dup 0)
4463 (const_int 255)))
4464 (parallel
4465 [(set (match_dup 0)
4466 (ashift:HI (match_dup 0)
4467 (match_dup 1)))
4468 (clobber (match_dup 2))])]
4469 "")
4471 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4473 (define_peephole2
4474 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4475 (lshiftrt:SI (match_dup 0)
4476 (match_operand:SI 1 "const_int_operand" "")))
4477 (clobber (match_operand:SI 2 "" ""))])
4478 (set (match_dup 0)
4479 (and:SI (match_dup 0)
4480 (match_operand:SI 3 "const_int_operand" "")))]
4481 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4482 [(set (match_dup 0)
4483 (and:SI (match_dup 0)
4484 (const_int 255)))
4485 (parallel
4486 [(set (match_dup 0)
4487 (lshiftrt:SI (match_dup 0)
4488 (match_dup 1)))
4489 (clobber (match_dup 2))])]
4490 "")
4492 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4494 (define_peephole2
4495 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4496 (ashift:SI (match_dup 0)
4497 (match_operand:SI 1 "const_int_operand" "")))
4498 (clobber (match_operand:SI 2 "" ""))])
4499 (set (match_dup 0)
4500 (and:SI (match_dup 0)
4501 (match_operand:SI 3 "const_int_operand" "")))]
4502 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4503 [(set (match_dup 0)
4504 (and:SI (match_dup 0)
4505 (const_int 255)))
4506 (parallel
4507 [(set (match_dup 0)
4508 (ashift:SI (match_dup 0)
4509 (match_dup 1)))
4510 (clobber (match_dup 2))])]
4511 "")
4513 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
4515 (define_peephole2
4516 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4517 (lshiftrt:SI (match_dup 0)
4518 (match_operand:SI 1 "const_int_operand" "")))
4519 (clobber (match_operand:SI 2 "" ""))])
4520 (set (match_dup 0)
4521 (and:SI (match_dup 0)
4522 (match_operand:SI 3 "const_int_operand" "")))]
4523 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
4524 [(set (match_dup 0)
4525 (and:SI (match_dup 0)
4526 (const_int 65535)))
4527 (parallel
4528 [(set (match_dup 0)
4529 (lshiftrt:SI (match_dup 0)
4530 (match_dup 1)))
4531 (clobber (match_dup 2))])]
4532 "")
4534 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
4536 (define_peephole2
4537 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4538 (ashift:SI (match_dup 0)
4539 (match_operand:SI 1 "const_int_operand" "")))
4540 (clobber (match_operand:SI 2 "" ""))])
4541 (set (match_dup 0)
4542 (and:SI (match_dup 0)
4543 (match_operand:SI 3 "const_int_operand" "")))]
4544 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
4545 [(set (match_dup 0)
4546 (and:SI (match_dup 0)
4547 (const_int 65535)))
4548 (parallel
4549 [(set (match_dup 0)
4550 (ashift:SI (match_dup 0)
4551 (match_dup 1)))
4552 (clobber (match_dup 2))])]
4553 "")
4555 ;; Convert a QImode push into an SImode push so that the
4556 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4558 (define_peephole2
4559 [(parallel [(set (reg:SI SP_REG)
4560 (plus:SI (reg:SI SP_REG) (const_int -4)))
4561 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
4562 (match_operand:QI 0 "register_operand" ""))])]
4563 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4564 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4565 (match_dup 0))]
4566 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4568 (define_peephole2
4569 [(parallel [(set (reg:HI SP_REG)
4570 (plus:HI (reg:HI SP_REG) (const_int -4)))
4571 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
4572 (match_operand:QI 0 "register_operand" ""))])]
4573 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4574 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4575 (match_dup 0))]
4576 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4578 ;; Convert a HImode push into an SImode push so that the
4579 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4581 (define_peephole2
4582 [(parallel [(set (reg:SI SP_REG)
4583 (plus:SI (reg:SI SP_REG) (const_int -4)))
4584 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
4585 (match_operand:HI 0 "register_operand" ""))])]
4586 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4587 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4588 (match_dup 0))]
4589 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4591 (define_peephole2
4592 [(parallel [(set (reg:HI SP_REG)
4593 (plus:HI (reg:HI SP_REG) (const_int -4)))
4594 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
4595 (match_operand:HI 0 "register_operand" ""))])]
4596 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4597 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4598 (match_dup 0))]
4599 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4601 ;; Cram four pushes into stm.l.
4603 (define_peephole2
4604 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4605 (match_operand:SI 0 "register_operand" ""))
4606 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4607 (match_operand:SI 1 "register_operand" ""))
4608 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4609 (match_operand:SI 2 "register_operand" ""))
4610 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4611 (match_operand:SI 3 "register_operand" ""))]
4612 "TARGET_H8300S && !TARGET_NORMAL_MODE
4613 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4614 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4615 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4616 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4617 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4618 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4619 (match_dup 0))
4620 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4621 (match_dup 1))
4622 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4623 (match_dup 2))
4624 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
4625 (match_dup 3))
4626 (set (reg:SI SP_REG)
4627 (plus:SI (reg:SI SP_REG)
4628 (const_int -16)))])]
4629 "")
4631 (define_peephole2
4632 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4633 (match_operand:SI 0 "register_operand" ""))
4634 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4635 (match_operand:SI 1 "register_operand" ""))
4636 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4637 (match_operand:SI 2 "register_operand" ""))
4638 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4639 (match_operand:SI 3 "register_operand" ""))]
4640 "TARGET_H8300S && TARGET_NORMAL_MODE
4641 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4642 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4643 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4644 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4645 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4646 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4647 (match_dup 0))
4648 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4649 (match_dup 1))
4650 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4651 (match_dup 2))
4652 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
4653 (match_dup 3))
4654 (set (reg:HI SP_REG)
4655 (plus:HI (reg:HI SP_REG)
4656 (const_int -16)))])]
4657 "")
4659 ;; Cram three pushes into stm.l.
4661 (define_peephole2
4662 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4663 (match_operand:SI 0 "register_operand" ""))
4664 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4665 (match_operand:SI 1 "register_operand" ""))
4666 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4667 (match_operand:SI 2 "register_operand" ""))]
4668 "TARGET_H8300S && !TARGET_NORMAL_MODE
4669 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4670 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4671 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4672 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4673 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4674 (match_dup 0))
4675 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4676 (match_dup 1))
4677 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4678 (match_dup 2))
4679 (set (reg:SI SP_REG)
4680 (plus:SI (reg:SI SP_REG)
4681 (const_int -12)))])]
4682 "")
4684 (define_peephole2
4685 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4686 (match_operand:SI 0 "register_operand" ""))
4687 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4688 (match_operand:SI 1 "register_operand" ""))
4689 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4690 (match_operand:SI 2 "register_operand" ""))]
4691 "TARGET_H8300S && TARGET_NORMAL_MODE
4692 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4693 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4694 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4695 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4696 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4697 (match_dup 0))
4698 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4699 (match_dup 1))
4700 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4701 (match_dup 2))
4702 (set (reg:HI SP_REG)
4703 (plus:HI (reg:HI SP_REG)
4704 (const_int -12)))])]
4705 "")
4707 ;; Cram two pushes into stm.l.
4709 (define_peephole2
4710 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4711 (match_operand:SI 0 "register_operand" ""))
4712 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4713 (match_operand:SI 1 "register_operand" ""))]
4714 "TARGET_H8300S && !TARGET_NORMAL_MODE
4715 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4716 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4717 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4718 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4719 (match_dup 0))
4720 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4721 (match_dup 1))
4722 (set (reg:SI SP_REG)
4723 (plus:SI (reg:SI SP_REG)
4724 (const_int -8)))])]
4725 "")
4727 (define_peephole2
4728 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4729 (match_operand:SI 0 "register_operand" ""))
4730 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4731 (match_operand:SI 1 "register_operand" ""))]
4732 "TARGET_H8300S && TARGET_NORMAL_MODE
4733 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4734 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4735 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4736 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4737 (match_dup 0))
4738 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4739 (match_dup 1))
4740 (set (reg:HI SP_REG)
4741 (plus:HI (reg:HI SP_REG)
4742 (const_int -8)))])]
4743 "")
4745 ;; Turn
4746 ;;
4747 ;; mov.w #2,r0
4748 ;; add.w r7,r0 (6 bytes)
4749 ;;
4750 ;; into
4751 ;;
4752 ;; mov.w r7,r0
4753 ;; adds #2,r0 (4 bytes)
4755 (define_peephole2
4756 [(set (match_operand:HI 0 "register_operand" "")
4757 (match_operand:HI 1 "const_int_operand" ""))
4758 (set (match_dup 0)
4759 (plus:HI (match_dup 0)
4760 (match_operand:HI 2 "register_operand" "")))]
4761 "REG_P (operands[0]) && REG_P (operands[2])
4762 && REGNO (operands[0]) != REGNO (operands[2])
4763 && (CONST_OK_FOR_J (INTVAL (operands[1]))
4764 || CONST_OK_FOR_L (INTVAL (operands[1]))
4765 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4766 [(set (match_dup 0)
4767 (match_dup 2))
4768 (set (match_dup 0)
4769 (plus:HI (match_dup 0)
4770 (match_dup 1)))]
4771 "")
4773 ;; Turn
4774 ;;
4775 ;; sub.l er0,er0
4776 ;; add.b #4,r0l
4777 ;; add.l er7,er0 (6 bytes)
4778 ;;
4779 ;; into
4780 ;;
4781 ;; mov.l er7,er0
4782 ;; adds #4,er0 (4 bytes)
4784 (define_peephole2
4785 [(set (match_operand:SI 0 "register_operand" "")
4786 (match_operand:SI 1 "const_int_operand" ""))
4787 (set (match_dup 0)
4788 (plus:SI (match_dup 0)
4789 (match_operand:SI 2 "register_operand" "")))]
4790 "(TARGET_H8300H || TARGET_H8300S)
4791 && REG_P (operands[0]) && REG_P (operands[2])
4792 && REGNO (operands[0]) != REGNO (operands[2])
4793 && (CONST_OK_FOR_L (INTVAL (operands[1]))
4794 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4795 [(set (match_dup 0)
4796 (match_dup 2))
4797 (set (match_dup 0)
4798 (plus:SI (match_dup 0)
4799 (match_dup 1)))]
4800 "")
4802 ;; Turn
4803 ;;
4804 ;; mov.l er7,er0
4805 ;; add.l #10,er0 (takes 8 bytes)
4806 ;;
4807 ;; into
4808 ;;
4809 ;; sub.l er0,er0
4810 ;; add.b #10,r0l
4811 ;; add.l er7,er0 (takes 6 bytes)
4813 (define_peephole2
4814 [(set (match_operand:SI 0 "register_operand" "")
4815 (match_operand:SI 1 "register_operand" ""))
4816 (set (match_dup 0)
4817 (plus:SI (match_dup 0)
4818 (match_operand:SI 2 "const_int_operand" "")))]
4819 "(TARGET_H8300H || TARGET_H8300S)
4820 && REG_P (operands[0]) && REG_P (operands[1])
4821 && REGNO (operands[0]) != REGNO (operands[1])
4822 && !CONST_OK_FOR_L (INTVAL (operands[2]))
4823 && !CONST_OK_FOR_N (INTVAL (operands[2]))
4824 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4825 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4826 || INTVAL (operands[2]) == 0xffff
4827 || INTVAL (operands[2]) == 0xfffe)"
4828 [(set (match_dup 0)
4829 (match_dup 2))
4830 (set (match_dup 0)
4831 (plus:SI (match_dup 0)
4832 (match_dup 1)))]
4833 "")
4835 ;; Turn
4836 ;;
4837 ;; subs #1,er4
4838 ;; mov.w r4,r4
4839 ;; bne .L2028
4840 ;;
4841 ;; into
4842 ;;
4843 ;; dec.w #1,r4
4844 ;; bne .L2028
4846 (define_peephole2
4847 [(set (match_operand:HI 0 "register_operand" "")
4848 (plus:HI (match_dup 0)
4849 (match_operand 1 "incdec_operand" "")))
4850 (set (cc0)
4851 (match_dup 0))
4852 (set (pc)
4853 (if_then_else (match_operator 3 "eqne_operator"
4854 [(cc0) (const_int 0)])
4855 (label_ref (match_operand 2 "" ""))
4856 (pc)))]
4857 "TARGET_H8300H || TARGET_H8300S"
4858 [(set (match_operand:HI 0 "register_operand" "")
4859 (unspec:HI [(match_dup 0)
4860 (match_dup 1)]
4861 UNSPEC_INCDEC))
4862 (set (cc0)
4863 (match_dup 0))
4864 (set (pc)
4865 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4866 (label_ref (match_dup 2))
4867 (pc)))]
4868 "")
4870 ;; The SImode version of the previous pattern.
4872 (define_peephole2
4873 [(set (match_operand:SI 0 "register_operand" "")
4874 (plus:SI (match_dup 0)
4875 (match_operand 1 "incdec_operand" "")))
4876 (set (cc0)
4877 (match_dup 0))
4878 (set (pc)
4879 (if_then_else (match_operator 3 "eqne_operator"
4880 [(cc0) (const_int 0)])
4881 (label_ref (match_operand 2 "" ""))
4882 (pc)))]
4883 "TARGET_H8300H || TARGET_H8300S"
4884 [(set (match_operand:SI 0 "register_operand" "")
4885 (unspec:SI [(match_dup 0)
4886 (match_dup 1)]
4887 UNSPEC_INCDEC))
4888 (set (cc0)
4889 (match_dup 0))
4890 (set (pc)
4891 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4892 (label_ref (match_dup 2))
4893 (pc)))]
4894 "")
4896 (define_peephole2
4897 [(parallel [(set (cc0)
4898 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4899 (const_int 1)
4900 (const_int 7)))
4901 (clobber (scratch:QI))])
4902 (set (pc)
4903 (if_then_else (match_operator 1 "eqne_operator"
4904 [(cc0) (const_int 0)])
4905 (label_ref (match_operand 2 "" ""))
4906 (pc)))]
4907 "(TARGET_H8300H || TARGET_H8300S)"
4908 [(set (cc0)
4909 (match_dup 0))
4910 (set (pc)
4911 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4912 (label_ref (match_dup 2))
4913 (pc)))]
4914 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4915 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4916 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4918 ;; The next three peephole2's will try to transform
4919 ;;
4920 ;; mov.b A,r0l (or mov.l A,er0)
4921 ;; and.l #CST,er0
4922 ;;
4923 ;; into
4924 ;;
4925 ;; sub.l er0
4926 ;; mov.b A,r0l
4927 ;; and.b #CST,r0l (if CST is not 255)
4929 (define_peephole2
4930 [(set (match_operand:QI 0 "register_operand" "")
4931 (match_operand:QI 1 "general_operand" ""))
4932 (set (match_operand:SI 2 "register_operand" "")
4933 (and:SI (match_dup 2)
4934 (const_int 255)))]
4935 "(TARGET_H8300H || TARGET_H8300S)
4936 && !reg_overlap_mentioned_p (operands[2], operands[1])
4937 && REGNO (operands[0]) == REGNO (operands[2])"
4938 [(set (match_dup 2)
4939 (const_int 0))
4940 (set (strict_low_part (match_dup 0))
4941 (match_dup 1))]
4942 "")
4944 (define_peephole2
4945 [(set (match_operand:SI 0 "register_operand" "")
4946 (match_operand:SI 1 "general_operand" ""))
4947 (set (match_dup 0)
4948 (and:SI (match_dup 0)
4949 (const_int 255)))]
4950 "(TARGET_H8300H || TARGET_H8300S)
4951 && !reg_overlap_mentioned_p (operands[0], operands[1])
4952 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
4953 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4954 [(set (match_dup 0)
4955 (const_int 0))
4956 (set (strict_low_part (match_dup 2))
4957 (match_dup 3))]
4958 "operands[2] = gen_lowpart (QImode, operands[0]);
4959 operands[3] = gen_lowpart (QImode, operands[1]);")
4961 (define_peephole2
4962 [(set (match_operand 0 "register_operand" "")
4963 (match_operand 1 "general_operand" ""))
4964 (set (match_operand:SI 2 "register_operand" "")
4965 (and:SI (match_dup 2)
4966 (match_operand:SI 3 "const_int_qi_operand" "")))]
4967 "(TARGET_H8300H || TARGET_H8300S)
4968 && (GET_MODE (operands[0]) == QImode
4969 || GET_MODE (operands[0]) == HImode
4970 || GET_MODE (operands[0]) == SImode)
4971 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4972 && REGNO (operands[0]) == REGNO (operands[2])
4973 && !reg_overlap_mentioned_p (operands[2], operands[1])
4974 && !(GET_MODE (operands[1]) != QImode
4975 && GET_CODE (operands[1]) == MEM
4976 && !offsettable_memref_p (operands[1]))
4977 && !(GET_MODE (operands[1]) != QImode
4978 && GET_CODE (operands[1]) == MEM
4979 && MEM_VOLATILE_P (operands[1]))"
4980 [(set (match_dup 2)
4981 (const_int 0))
4982 (set (strict_low_part (match_dup 4))
4983 (match_dup 5))
4984 (set (match_dup 2)
4985 (and:SI (match_dup 2)
4986 (match_dup 6)))]
4987 "operands[4] = gen_lowpart (QImode, operands[0]);
4988 operands[5] = gen_lowpart (QImode, operands[1]);
4989 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
4991 (define_peephole2
4992 [(set (match_operand:SI 0 "register_operand" "")
4993 (match_operand:SI 1 "register_operand" ""))
4994 (set (match_dup 0)
4995 (and:SI (match_dup 0)
4996 (const_int 65280)))]
4997 "(TARGET_H8300H || TARGET_H8300S)
4998 && !reg_overlap_mentioned_p (operands[0], operands[1])"
4999 [(set (match_dup 0)
5000 (const_int 0))
5001 (set (zero_extract:SI (match_dup 0)
5002 (const_int 8)
5003 (const_int 8))
5004 (lshiftrt:SI (match_dup 1)
5005 (const_int 8)))]
5006 "")
5008 ;; If a load of mem:SI is followed by an AND that turns off the upper
5009 ;; half, then we can load mem:HI instead.
5011 (define_peephole2
5012 [(set (match_operand:SI 0 "register_operand" "")
5013 (match_operand:SI 1 "memory_operand" ""))
5014 (set (match_dup 0)
5015 (and:SI (match_dup 0)
5016 (match_operand:SI 2 "const_int_operand" "")))]
5017 "(TARGET_H8300H || TARGET_H8300S)
5018 && !MEM_VOLATILE_P (operands[1])
5019 && offsettable_memref_p (operands[1])
5020 && (INTVAL (operands[2]) & ~0xffff) == 0
5021 && INTVAL (operands[2]) != 255"
5022 [(set (match_dup 3)
5023 (match_dup 4))
5024 (set (match_dup 0)
5025 (and:SI (match_dup 0)
5026 (match_dup 2)))]
5027 "operands[3] = gen_lowpart (HImode, operands[0]);
5028 operands[4] = gen_lowpart (HImode, operands[1]);")
5030 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
5031 ;; the equivalent with shorter sequences. Here is the summary. Cases
5032 ;; are grouped for each define_peephole2.
5033 ;;
5034 ;; reg const_int use insn
5035 ;; --------------------------------------------------------
5036 ;; dead -2 eq/ne inc.l
5037 ;; dead -1 eq/ne inc.l
5038 ;; dead 1 eq/ne dec.l
5039 ;; dead 2 eq/ne dec.l
5040 ;;
5041 ;; dead 1 ge/lt shar.l
5042 ;; dead 3 (H8S) ge/lt shar.l
5043 ;;
5044 ;; dead 1 geu/ltu shar.l
5045 ;; dead 3 (H8S) geu/ltu shar.l
5046 ;;
5047 ;; ---- 255 ge/lt mov.b
5048 ;;
5049 ;; ---- 255 geu/ltu mov.b
5051 ;; Transform
5052 ;;
5053 ;; cmp.w #1,r0
5054 ;; bne .L1
5055 ;;
5056 ;; into
5057 ;;
5058 ;; dec.w #1,r0
5059 ;; bne .L1
5061 (define_peephole2
5062 [(set (cc0)
5063 (compare (match_operand:HI 0 "register_operand" "")
5064 (match_operand:HI 1 "incdec_operand" "")))
5065 (set (pc)
5066 (if_then_else (match_operator 3 "eqne_operator"
5067 [(cc0) (const_int 0)])
5068 (label_ref (match_operand 2 "" ""))
5069 (pc)))]
5070 "(TARGET_H8300H || TARGET_H8300S)
5071 && peep2_reg_dead_p (1, operands[0])"
5072 [(set (match_dup 0)
5073 (unspec:HI [(match_dup 0)
5074 (match_dup 4)]
5075 UNSPEC_INCDEC))
5076 (set (cc0)
5077 (match_dup 0))
5078 (set (pc)
5079 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5080 (label_ref (match_dup 2))
5081 (pc)))]
5082 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5084 ;; Transform
5085 ;;
5086 ;; cmp.w #1,r0
5087 ;; bgt .L1
5088 ;;
5089 ;; into
5090 ;;
5091 ;; shar.w r0
5092 ;; bgt .L1
5094 (define_peephole2
5095 [(set (cc0)
5096 (compare (match_operand:HI 0 "register_operand" "")
5097 (match_operand:HI 1 "const_int_operand" "")))
5098 (set (pc)
5099 (if_then_else (match_operator 2 "gtle_operator"
5100 [(cc0) (const_int 0)])
5101 (label_ref (match_operand 3 "" ""))
5102 (pc)))]
5103 "(TARGET_H8300H || TARGET_H8300S)
5104 && peep2_reg_dead_p (1, operands[0])
5105 && (INTVAL (operands[1]) == 1
5106 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5107 [(parallel [(set (match_dup 0)
5108 (ashiftrt:HI (match_dup 0)
5109 (match_dup 4)))
5110 (clobber (scratch:QI))])
5111 (set (cc0)
5112 (match_dup 0))
5113 (set (pc)
5114 (if_then_else (match_dup 2)
5115 (label_ref (match_dup 3))
5116 (pc)))]
5117 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5119 ;; Transform
5120 ;;
5121 ;; cmp.w #1,r0
5122 ;; bhi .L1
5123 ;;
5124 ;; into
5125 ;;
5126 ;; shar.w r0
5127 ;; bne .L1
5129 (define_peephole2
5130 [(set (cc0)
5131 (compare (match_operand:HI 0 "register_operand" "")
5132 (match_operand:HI 1 "const_int_operand" "")))
5133 (set (pc)
5134 (if_then_else (match_operator 2 "gtuleu_operator"
5135 [(cc0) (const_int 0)])
5136 (label_ref (match_operand 3 "" ""))
5137 (pc)))]
5138 "(TARGET_H8300H || TARGET_H8300S)
5139 && peep2_reg_dead_p (1, operands[0])
5140 && (INTVAL (operands[1]) == 1
5141 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5142 [(parallel [(set (match_dup 0)
5143 (ashiftrt:HI (match_dup 0)
5144 (match_dup 4)))
5145 (clobber (scratch:QI))])
5146 (set (cc0)
5147 (match_dup 0))
5148 (set (pc)
5149 (if_then_else (match_dup 5)
5150 (label_ref (match_dup 3))
5151 (pc)))]
5152 {
5153 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5154 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5155 VOIDmode,
5156 cc0_rtx,
5157 const0_rtx);
5158 })
5160 ;; Transform
5161 ;;
5162 ;; cmp.w #255,r0
5163 ;; bgt .L1
5164 ;;
5165 ;; into
5166 ;;
5167 ;; mov.b r0h,r0h
5168 ;; bgt .L1
5170 (define_peephole2
5171 [(set (cc0)
5172 (compare (match_operand:HI 0 "register_operand" "")
5173 (const_int 255)))
5174 (set (pc)
5175 (if_then_else (match_operator 1 "gtle_operator"
5176 [(cc0) (const_int 0)])
5177 (label_ref (match_operand 2 "" ""))
5178 (pc)))]
5179 "TARGET_H8300H || TARGET_H8300S"
5180 [(set (cc0)
5181 (and:HI (match_dup 0)
5182 (const_int -256)))
5183 (set (pc)
5184 (if_then_else (match_dup 1)
5185 (label_ref (match_dup 2))
5186 (pc)))]
5187 "")
5189 ;; Transform
5190 ;;
5191 ;; cmp.w #255,r0
5192 ;; bhi .L1
5193 ;;
5194 ;; into
5195 ;;
5196 ;; mov.b r0h,r0h
5197 ;; bne .L1
5199 (define_peephole2
5200 [(set (cc0)
5201 (compare (match_operand:HI 0 "register_operand" "")
5202 (const_int 255)))
5203 (set (pc)
5204 (if_then_else (match_operator 1 "gtuleu_operator"
5205 [(cc0) (const_int 0)])
5206 (label_ref (match_operand 2 "" ""))
5207 (pc)))]
5208 "TARGET_H8300H || TARGET_H8300S"
5209 [(set (cc0)
5210 (and:HI (match_dup 0)
5211 (const_int -256)))
5212 (set (pc)
5213 (if_then_else (match_dup 3)
5214 (label_ref (match_dup 2))
5215 (pc)))]
5216 {
5217 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5218 VOIDmode,
5219 cc0_rtx,
5220 const0_rtx);
5221 })
5223 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
5224 ;; the equivalent with shorter sequences. Here is the summary. Cases
5225 ;; are grouped for each define_peephole2.
5226 ;;
5227 ;; reg const_int use insn
5228 ;; --------------------------------------------------------
5229 ;; live -2 eq/ne copy and inc.l
5230 ;; live -1 eq/ne copy and inc.l
5231 ;; live 1 eq/ne copy and dec.l
5232 ;; live 2 eq/ne copy and dec.l
5233 ;;
5234 ;; dead -2 eq/ne inc.l
5235 ;; dead -1 eq/ne inc.l
5236 ;; dead 1 eq/ne dec.l
5237 ;; dead 2 eq/ne dec.l
5238 ;;
5239 ;; dead -131072 eq/ne inc.w and test
5240 ;; dead -65536 eq/ne inc.w and test
5241 ;; dead 65536 eq/ne dec.w and test
5242 ;; dead 131072 eq/ne dec.w and test
5243 ;;
5244 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
5245 ;; dead 0x0000??00 eq/ne xor.b and test
5246 ;; dead 0x0000ffff eq/ne not.w and test
5247 ;;
5248 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
5249 ;; dead 0xffff??ff eq/ne xor.b and not.l
5250 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
5251 ;; dead 0x80000000 eq/ne rotl.l and dec.l
5252 ;;
5253 ;; live 1 ge/lt copy and shar.l
5254 ;; live 3 (H8S) ge/lt copy and shar.l
5255 ;;
5256 ;; live 1 geu/ltu copy and shar.l
5257 ;; live 3 (H8S) geu/ltu copy and shar.l
5258 ;;
5259 ;; dead 1 ge/lt shar.l
5260 ;; dead 3 (H8S) ge/lt shar.l
5261 ;;
5262 ;; dead 1 geu/ltu shar.l
5263 ;; dead 3 (H8S) geu/ltu shar.l
5264 ;;
5265 ;; dead 3 (H8/300H) ge/lt and.b and test
5266 ;; dead 7 ge/lt and.b and test
5267 ;; dead 15 ge/lt and.b and test
5268 ;; dead 31 ge/lt and.b and test
5269 ;; dead 63 ge/lt and.b and test
5270 ;; dead 127 ge/lt and.b and test
5271 ;; dead 255 ge/lt and.b and test
5272 ;;
5273 ;; dead 3 (H8/300H) geu/ltu and.b and test
5274 ;; dead 7 geu/ltu and.b and test
5275 ;; dead 15 geu/ltu and.b and test
5276 ;; dead 31 geu/ltu and.b and test
5277 ;; dead 63 geu/ltu and.b and test
5278 ;; dead 127 geu/ltu and.b and test
5279 ;; dead 255 geu/ltu and.b and test
5280 ;;
5281 ;; ---- 65535 ge/lt mov.w
5282 ;;
5283 ;; ---- 65535 geu/ltu mov.w
5285 ;; Transform
5286 ;;
5287 ;; cmp.l #1,er0
5288 ;; beq .L1
5289 ;;
5290 ;; into
5291 ;;
5292 ;; dec.l #1,er0
5293 ;; beq .L1
5295 (define_peephole2
5296 [(set (cc0)
5297 (compare (match_operand:SI 0 "register_operand" "")
5298 (match_operand:SI 1 "incdec_operand" "")))
5299 (set (pc)
5300 (if_then_else (match_operator 3 "eqne_operator"
5301 [(cc0) (const_int 0)])
5302 (label_ref (match_operand 2 "" ""))
5303 (pc)))]
5304 "(TARGET_H8300H || TARGET_H8300S)
5305 && peep2_reg_dead_p (1, operands[0])"
5306 [(set (match_dup 0)
5307 (unspec:SI [(match_dup 0)
5308 (match_dup 4)]
5309 UNSPEC_INCDEC))
5310 (set (cc0)
5311 (match_dup 0))
5312 (set (pc)
5313 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5314 (label_ref (match_dup 2))
5315 (pc)))]
5316 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5318 ;; Transform
5319 ;;
5320 ;; cmp.l #65536,er0
5321 ;; beq .L1
5322 ;;
5323 ;; into
5324 ;;
5325 ;; dec.l #1,e0
5326 ;; beq .L1
5328 (define_peephole2
5329 [(set (cc0)
5330 (compare (match_operand:SI 0 "register_operand" "")
5331 (match_operand:SI 1 "const_int_operand" "")))
5332 (set (pc)
5333 (if_then_else (match_operator 3 "eqne_operator"
5334 [(cc0) (const_int 0)])
5335 (label_ref (match_operand 2 "" ""))
5336 (pc)))]
5337 "(TARGET_H8300H || TARGET_H8300S)
5338 && peep2_reg_dead_p (1, operands[0])
5339 && (INTVAL (operands[1]) == -131072
5340 || INTVAL (operands[1]) == -65536
5341 || INTVAL (operands[1]) == 65536
5342 || INTVAL (operands[1]) == 131072)"
5343 [(set (match_dup 0)
5344 (plus:SI (match_dup 0)
5345 (match_dup 4)))
5346 (set (cc0)
5347 (match_dup 0))
5348 (set (pc)
5349 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5350 (label_ref (match_dup 2))
5351 (pc)))]
5352 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5354 ;; Transform
5355 ;;
5356 ;; cmp.l #100,er0
5357 ;; beq .L1
5358 ;;
5359 ;; into
5360 ;;
5361 ;; xor.b #100,er0
5362 ;; mov.l er0,er0
5363 ;; beq .L1
5365 (define_peephole2
5366 [(set (cc0)
5367 (compare (match_operand:SI 0 "register_operand" "")
5368 (match_operand:SI 1 "const_int_operand" "")))
5369 (set (pc)
5370 (if_then_else (match_operator 3 "eqne_operator"
5371 [(cc0) (const_int 0)])
5372 (label_ref (match_operand 2 "" ""))
5373 (pc)))]
5374 "(TARGET_H8300H || TARGET_H8300S)
5375 && peep2_reg_dead_p (1, operands[0])
5376 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
5377 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
5378 || INTVAL (operands[1]) == 0x0000ffff)
5379 && INTVAL (operands[1]) != 1
5380 && INTVAL (operands[1]) != 2"
5381 [(set (match_dup 0)
5382 (xor:SI (match_dup 0)
5383 (match_dup 1)))
5384 (set (cc0)
5385 (match_dup 0))
5386 (set (pc)
5387 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5388 (label_ref (match_dup 2))
5389 (pc)))]
5390 "")
5392 ;; Transform
5393 ;;
5394 ;; cmp.l #-100,er0
5395 ;; beq .L1
5396 ;;
5397 ;; into
5398 ;;
5399 ;; xor.b #99,er0
5400 ;; not.l er0
5401 ;; beq .L1
5403 (define_peephole2
5404 [(set (cc0)
5405 (compare (match_operand:SI 0 "register_operand" "")
5406 (match_operand:SI 1 "const_int_operand" "")))
5407 (set (pc)
5408 (if_then_else (match_operator 3 "eqne_operator"
5409 [(cc0) (const_int 0)])
5410 (label_ref (match_operand 2 "" ""))
5411 (pc)))]
5412 "(TARGET_H8300H || TARGET_H8300S)
5413 && peep2_reg_dead_p (1, operands[0])
5414 && ((INTVAL (operands[1]) | 0x00ff) == -1
5415 || (INTVAL (operands[1]) | 0xff00) == -1)
5416 && INTVAL (operands[1]) != -1
5417 && INTVAL (operands[1]) != -2"
5418 [(set (match_dup 0)
5419 (xor:SI (match_dup 0)
5420 (match_dup 4)))
5421 (set (match_dup 0)
5422 (not:SI (match_dup 0)))
5423 (set (cc0)
5424 (match_dup 0))
5425 (set (pc)
5426 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5427 (label_ref (match_dup 2))
5428 (pc)))]
5429 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
5431 ;; Transform
5432 ;;
5433 ;; cmp.l #-2147483648,er0
5434 ;; beq .L1
5435 ;;
5436 ;; into
5437 ;;
5438 ;; rotl.l er0
5439 ;; dec.l #1,er0
5440 ;; beq .L1
5442 (define_peephole2
5443 [(set (cc0)
5444 (compare (match_operand:SI 0 "register_operand" "")
5445 (match_operand:SI 1 "const_int_operand" "")))
5446 (set (pc)
5447 (if_then_else (match_operator 3 "eqne_operator"
5448 [(cc0) (const_int 0)])
5449 (label_ref (match_operand 2 "" ""))
5450 (pc)))]
5451 "(TARGET_H8300H || TARGET_H8300S)
5452 && peep2_reg_dead_p (1, operands[0])
5453 && (INTVAL (operands[1]) == -2147483647 - 1
5454 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
5455 [(set (match_dup 0)
5456 (rotate:SI (match_dup 0)
5457 (match_dup 4)))
5458 (set (match_dup 0)
5459 (unspec:SI [(match_dup 0)
5460 (const_int -1)]
5461 UNSPEC_INCDEC))
5462 (set (cc0)
5463 (match_dup 0))
5464 (set (pc)
5465 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5466 (label_ref (match_dup 2))
5467 (pc)))]
5468 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
5470 ;; Transform
5471 ;;
5472 ;; cmp.l #1,er0
5473 ;; bgt .L1
5474 ;;
5475 ;; into
5476 ;;
5477 ;; mov.l er0,er1
5478 ;; shar.l er1
5479 ;; bgt .L1
5481 ;; We avoid this transformation if we see more than one copy of the
5482 ;; same compare insn immediately before this one.
5484 (define_peephole2
5485 [(match_scratch:SI 4 "r")
5486 (set (cc0)
5487 (compare (match_operand:SI 0 "register_operand" "")
5488 (match_operand:SI 1 "const_int_operand" "")))
5489 (set (pc)
5490 (if_then_else (match_operator 2 "gtle_operator"
5491 [(cc0) (const_int 0)])
5492 (label_ref (match_operand 3 "" ""))
5493 (pc)))]
5494 "(TARGET_H8300H || TARGET_H8300S)
5495 && !peep2_reg_dead_p (1, operands[0])
5496 && (INTVAL (operands[1]) == 1
5497 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5498 && !same_cmp_preceding_p (insn)"
5499 [(set (match_dup 4)
5500 (match_dup 0))
5501 (parallel [(set (match_dup 4)
5502 (ashiftrt:SI (match_dup 4)
5503 (match_dup 5)))
5504 (clobber (scratch:QI))])
5505 (set (cc0)
5506 (match_dup 4))
5507 (set (pc)
5508 (if_then_else (match_dup 2)
5509 (label_ref (match_dup 3))
5510 (pc)))]
5511 "operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5513 ;; Transform
5514 ;;
5515 ;; cmp.l #1,er0
5516 ;; bhi .L1
5517 ;;
5518 ;; into
5519 ;;
5520 ;; mov.l er0,er1
5521 ;; shar.l er1
5522 ;; bne .L1
5524 ;; We avoid this transformation if we see more than one copy of the
5525 ;; same compare insn immediately before this one.
5527 (define_peephole2
5528 [(match_scratch:SI 4 "r")
5529 (set (cc0)
5530 (compare (match_operand:SI 0 "register_operand" "")
5531 (match_operand:SI 1 "const_int_operand" "")))
5532 (set (pc)
5533 (if_then_else (match_operator 2 "gtuleu_operator"
5534 [(cc0) (const_int 0)])
5535 (label_ref (match_operand 3 "" ""))
5536 (pc)))]
5537 "(TARGET_H8300H || TARGET_H8300S)
5538 && !peep2_reg_dead_p (1, operands[0])
5539 && (INTVAL (operands[1]) == 1
5540 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5541 && !same_cmp_preceding_p (insn)"
5542 [(set (match_dup 4)
5543 (match_dup 0))
5544 (parallel [(set (match_dup 4)
5545 (ashiftrt:SI (match_dup 4)
5546 (match_dup 5)))
5547 (clobber (scratch:QI))])
5548 (set (cc0)
5549 (match_dup 4))
5550 (set (pc)
5551 (if_then_else (match_dup 6)
5552 (label_ref (match_dup 3))
5553 (pc)))]
5554 {
5555 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5556 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5557 VOIDmode,
5558 cc0_rtx,
5559 const0_rtx);
5560 })
5562 ;; Transform
5563 ;;
5564 ;; cmp.l #1,er0
5565 ;; bgt .L1
5566 ;;
5567 ;; into
5568 ;;
5569 ;; shar.l er0
5570 ;; bgt .L1
5572 (define_peephole2
5573 [(set (cc0)
5574 (compare (match_operand:SI 0 "register_operand" "")
5575 (match_operand:SI 1 "const_int_operand" "")))
5576 (set (pc)
5577 (if_then_else (match_operator 2 "gtle_operator"
5578 [(cc0) (const_int 0)])
5579 (label_ref (match_operand 3 "" ""))
5580 (pc)))]
5581 "(TARGET_H8300H || TARGET_H8300S)
5582 && peep2_reg_dead_p (1, operands[0])
5583 && (INTVAL (operands[1]) == 1
5584 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5585 [(parallel [(set (match_dup 0)
5586 (ashiftrt:SI (match_dup 0)
5587 (match_dup 4)))
5588 (clobber (scratch:QI))])
5589 (set (cc0)
5590 (match_dup 0))
5591 (set (pc)
5592 (if_then_else (match_dup 2)
5593 (label_ref (match_dup 3))
5594 (pc)))]
5595 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5597 ;; Transform
5598 ;;
5599 ;; cmp.l #1,er0
5600 ;; bhi .L1
5601 ;;
5602 ;; into
5603 ;;
5604 ;; shar.l er0
5605 ;; bne .L1
5607 (define_peephole2
5608 [(set (cc0)
5609 (compare (match_operand:SI 0 "register_operand" "")
5610 (match_operand:SI 1 "const_int_operand" "")))
5611 (set (pc)
5612 (if_then_else (match_operator 2 "gtuleu_operator"
5613 [(cc0) (const_int 0)])
5614 (label_ref (match_operand 3 "" ""))
5615 (pc)))]
5616 "(TARGET_H8300H || TARGET_H8300S)
5617 && peep2_reg_dead_p (1, operands[0])
5618 && (INTVAL (operands[1]) == 1
5619 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5620 [(parallel [(set (match_dup 0)
5621 (ashiftrt:SI (match_dup 0)
5622 (match_dup 4)))
5623 (clobber (scratch:QI))])
5624 (set (cc0)
5625 (match_dup 0))
5626 (set (pc)
5627 (if_then_else (match_dup 5)
5628 (label_ref (match_dup 3))
5629 (pc)))]
5630 {
5631 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5632 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5633 VOIDmode,
5634 cc0_rtx,
5635 const0_rtx);
5636 })
5638 ;; Transform
5639 ;;
5640 ;; cmp.l #15,er0
5641 ;; bgt .L1
5642 ;;
5643 ;; into
5644 ;;
5645 ;; and #240,r0l
5646 ;; mov.l er0,er0
5647 ;; bgt .L1
5649 (define_peephole2
5650 [(set (cc0)
5651 (compare (match_operand:SI 0 "register_operand" "")
5652 (match_operand:SI 1 "const_int_operand" "")))
5653 (set (pc)
5654 (if_then_else (match_operator 2 "gtle_operator"
5655 [(cc0) (const_int 0)])
5656 (label_ref (match_operand 3 "" ""))
5657 (pc)))]
5658 "(TARGET_H8300H || TARGET_H8300S)
5659 && peep2_reg_dead_p (1, operands[0])
5660 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5661 || INTVAL (operands[1]) == 7
5662 || INTVAL (operands[1]) == 15
5663 || INTVAL (operands[1]) == 31
5664 || INTVAL (operands[1]) == 63
5665 || INTVAL (operands[1]) == 127
5666 || INTVAL (operands[1]) == 255)"
5667 [(set (match_dup 0)
5668 (and:SI (match_dup 0)
5669 (match_dup 4)))
5670 (set (cc0)
5671 (match_dup 0))
5672 (set (pc)
5673 (if_then_else (match_dup 2)
5674 (label_ref (match_dup 3))
5675 (pc)))]
5676 "operands[4] = GEN_INT (~INTVAL (operands[1]));")
5678 ;; Transform
5679 ;;
5680 ;; cmp.l #15,er0
5681 ;; bhi .L1
5682 ;;
5683 ;; into
5684 ;;
5685 ;; and #240,r0l
5686 ;; mov.l er0,er0
5687 ;; bne .L1
5689 (define_peephole2
5690 [(set (cc0)
5691 (compare (match_operand:SI 0 "register_operand" "")
5692 (match_operand:SI 1 "const_int_operand" "")))
5693 (set (pc)
5694 (if_then_else (match_operator 2 "gtuleu_operator"
5695 [(cc0) (const_int 0)])
5696 (label_ref (match_operand 3 "" ""))
5697 (pc)))]
5698 "(TARGET_H8300H || TARGET_H8300S)
5699 && peep2_reg_dead_p (1, operands[0])
5700 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5701 || INTVAL (operands[1]) == 7
5702 || INTVAL (operands[1]) == 15
5703 || INTVAL (operands[1]) == 31
5704 || INTVAL (operands[1]) == 63
5705 || INTVAL (operands[1]) == 127
5706 || INTVAL (operands[1]) == 255)"
5707 [(set (match_dup 0)
5708 (and:SI (match_dup 0)
5709 (match_dup 4)))
5710 (set (cc0)
5711 (match_dup 0))
5712 (set (pc)
5713 (if_then_else (match_dup 5)
5714 (label_ref (match_dup 3))
5715 (pc)))]
5716 {
5717 operands[4] = GEN_INT (~INTVAL (operands[1]));
5718 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5719 VOIDmode,
5720 cc0_rtx,
5721 const0_rtx);
5722 })
5724 ;; Transform
5725 ;;
5726 ;; cmp.l #65535,er0
5727 ;; bgt .L1
5728 ;;
5729 ;; into
5730 ;;
5731 ;; mov.l e0,e0
5732 ;; bgt .L1
5734 (define_peephole2
5735 [(set (cc0)
5736 (compare (match_operand:SI 0 "register_operand" "")
5737 (const_int 65535)))
5738 (set (pc)
5739 (if_then_else (match_operator 1 "gtle_operator"
5740 [(cc0) (const_int 0)])
5741 (label_ref (match_operand 2 "" ""))
5742 (pc)))]
5743 "TARGET_H8300H || TARGET_H8300S"
5744 [(set (cc0)
5745 (and:SI (match_dup 0)
5746 (const_int -65536)))
5747 (set (pc)
5748 (if_then_else (match_dup 1)
5749 (label_ref (match_dup 2))
5750 (pc)))]
5751 "")
5753 ;; Transform
5754 ;;
5755 ;; cmp.l #65535,er0
5756 ;; bhi .L1
5757 ;;
5758 ;; into
5759 ;;
5760 ;; mov.l e0,e0
5761 ;; bne .L1
5763 (define_peephole2
5764 [(set (cc0)
5765 (compare (match_operand:SI 0 "register_operand" "")
5766 (const_int 65535)))
5767 (set (pc)
5768 (if_then_else (match_operator 1 "gtuleu_operator"
5769 [(cc0) (const_int 0)])
5770 (label_ref (match_operand 2 "" ""))
5771 (pc)))]
5772 "TARGET_H8300H || TARGET_H8300S"
5773 [(set (cc0)
5774 (and:SI (match_dup 0)
5775 (const_int -65536)))
5776 (set (pc)
5777 (if_then_else (match_dup 3)
5778 (label_ref (match_dup 2))
5779 (pc)))]
5780 {
5781 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5782 VOIDmode,
5783 cc0_rtx,
5784 const0_rtx);
5785 })
5787 ;; Transform
5788 ;;
5789 ;; cmp.l #1,er0
5790 ;; beq .L1
5791 ;;
5792 ;; into
5793 ;;
5794 ;; mov.l er0,er1
5795 ;; dec.l #1,er1
5796 ;; beq .L1
5798 ;; We avoid this transformation if we see more than one copy of the
5799 ;; same compare insn.
5801 (define_peephole2
5802 [(match_scratch:SI 4 "r")
5803 (set (cc0)
5804 (compare (match_operand:SI 0 "register_operand" "")
5805 (match_operand:SI 1 "incdec_operand" "")))
5806 (set (pc)
5807 (if_then_else (match_operator 3 "eqne_operator"
5808 [(cc0) (const_int 0)])
5809 (label_ref (match_operand 2 "" ""))
5810 (pc)))]
5811 "(TARGET_H8300H || TARGET_H8300S)
5812 && !peep2_reg_dead_p (1, operands[0])
5813 && !same_cmp_following_p (insn)"
5814 [(set (match_dup 4)
5815 (match_dup 0))
5816 (set (match_dup 4)
5817 (unspec:SI [(match_dup 4)
5818 (match_dup 5)]
5819 UNSPEC_INCDEC))
5820 (set (cc0)
5821 (match_dup 4))
5822 (set (pc)
5823 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5824 (label_ref (match_dup 2))
5825 (pc)))]
5826 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
5828 ;; Narrow the mode of testing if possible.
5830 (define_peephole2
5831 [(set (match_operand:HI 0 "register_operand" "")
5832 (and:HI (match_dup 0)
5833 (match_operand:HI 1 "const_int_qi_operand" "")))
5834 (set (cc0)
5835 (match_dup 0))
5836 (set (pc)
5837 (if_then_else (match_operator 3 "eqne_operator"
5838 [(cc0) (const_int 0)])
5839 (label_ref (match_operand 2 "" ""))
5840 (pc)))]
5841 "peep2_reg_dead_p (2, operands[0])"
5842 [(set (match_dup 4)
5843 (and:QI (match_dup 4)
5844 (match_dup 5)))
5845 (set (cc0)
5846 (match_dup 4))
5847 (set (pc)
5848 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5849 (label_ref (match_dup 2))
5850 (pc)))]
5851 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5852 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
5854 (define_peephole2
5855 [(set (match_operand:SI 0 "register_operand" "")
5856 (and:SI (match_dup 0)
5857 (match_operand:SI 1 "const_int_qi_operand" "")))
5858 (set (cc0)
5859 (match_dup 0))
5860 (set (pc)
5861 (if_then_else (match_operator 3 "eqne_operator"
5862 [(cc0) (const_int 0)])
5863 (label_ref (match_operand 2 "" ""))
5864 (pc)))]
5865 "peep2_reg_dead_p (2, operands[0])"
5866 [(set (match_dup 4)
5867 (and:QI (match_dup 4)
5868 (match_dup 5)))
5869 (set (cc0)
5870 (match_dup 4))
5871 (set (pc)
5872 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5873 (label_ref (match_dup 2))
5874 (pc)))]
5875 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5876 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
5878 (define_peephole2
5879 [(set (match_operand:SI 0 "register_operand" "")
5880 (and:SI (match_dup 0)
5881 (match_operand:SI 1 "const_int_hi_operand" "")))
5882 (set (cc0)
5883 (match_dup 0))
5884 (set (pc)
5885 (if_then_else (match_operator 3 "eqne_operator"
5886 [(cc0) (const_int 0)])
5887 (label_ref (match_operand 2 "" ""))
5888 (pc)))]
5889 "peep2_reg_dead_p (2, operands[0])"
5890 [(set (match_dup 4)
5891 (and:HI (match_dup 4)
5892 (match_dup 5)))
5893 (set (cc0)
5894 (match_dup 4))
5895 (set (pc)
5896 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5897 (label_ref (match_dup 2))
5898 (pc)))]
5899 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
5900 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
5902 (define_peephole2
5903 [(set (match_operand:SI 0 "register_operand" "")
5904 (and:SI (match_dup 0)
5905 (match_operand:SI 1 "const_int_qi_operand" "")))
5906 (set (match_dup 0)
5907 (xor:SI (match_dup 0)
5908 (match_operand:SI 2 "const_int_qi_operand" "")))
5909 (set (cc0)
5910 (match_dup 0))
5911 (set (pc)
5912 (if_then_else (match_operator 4 "eqne_operator"
5913 [(cc0) (const_int 0)])
5914 (label_ref (match_operand 3 "" ""))
5915 (pc)))]
5916 "peep2_reg_dead_p (3, operands[0])
5917 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
5918 [(set (match_dup 5)
5919 (and:QI (match_dup 5)
5920 (match_dup 6)))
5921 (set (match_dup 5)
5922 (xor:QI (match_dup 5)
5923 (match_dup 7)))
5924 (set (cc0)
5925 (match_dup 5))
5926 (set (pc)
5927 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
5928 (label_ref (match_dup 3))
5929 (pc)))]
5930 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
5931 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
5932 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
5934 ;; These triggers right at the end of allocation of locals in the
5935 ;; prologue (and possibly at other places).
5937 ;; stack adjustment of -4, generate one push
5938 ;;
5939 ;; before : 6 bytes, 10 clocks
5940 ;; after : 4 bytes, 10 clocks
5942 (define_peephole2
5943 [(set (reg:SI SP_REG)
5944 (plus:SI (reg:SI SP_REG)
5945 (const_int -4)))
5946 (set (mem:SI (reg:SI SP_REG))
5947 (match_operand:SI 0 "register_operand" ""))]
5948 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5949 && REGNO (operands[0]) != SP_REG"
5950 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5951 (match_dup 0))]
5952 "")
5954 ;; stack adjustment of -12, generate one push
5955 ;;
5956 ;; before : 10 bytes, 14 clocks
5957 ;; after : 8 bytes, 14 clocks
5959 (define_peephole2
5960 [(set (reg:SI SP_REG)
5961 (plus:SI (reg:SI SP_REG)
5962 (const_int -12)))
5963 (set (mem:SI (reg:SI SP_REG))
5964 (match_operand:SI 0 "register_operand" ""))]
5965 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5966 && REGNO (operands[0]) != SP_REG"
5967 [(set (reg:SI SP_REG)
5968 (plus:SI (reg:SI SP_REG)
5969 (const_int -4)))
5970 (set (reg:SI SP_REG)
5971 (plus:SI (reg:SI SP_REG)
5972 (const_int -4)))
5973 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5974 (match_dup 0))]
5975 "")
5977 ;; Transform
5978 ;;
5979 ;; mov dst,reg
5980 ;; op src,reg
5981 ;; mov reg,dst
5982 ;;
5983 ;; into
5984 ;;
5985 ;; op src,dst
5986 ;;
5987 ;; if "reg" dies at the end of the sequence.
5988 (define_peephole2
5989 [(set (match_operand 0 "register_operand" "")
5990 (match_operand 1 "memory_operand" ""))
5991 (set (match_dup 0)
5992 (match_operator 2 "h8sx_binary_memory_operator"
5993 [(match_dup 0)
5994 (match_operand 3 "h8300_src_operand" "")]))
5995 (set (match_operand 4 "memory_operand" "")
5996 (match_dup 0))]
5997 "0 /* Disabale because it break compiling fp-bit.c. */
5998 && TARGET_H8300SX
5999 && peep2_reg_dead_p (3, operands[0])
6000 && !reg_overlap_mentioned_p (operands[0], operands[3])
6001 && !reg_overlap_mentioned_p (operands[0], operands[4])
6002 && h8sx_mergeable_memrefs_p (operands[4], operands[1])"
6003 [(set (match_dup 4)
6004 (match_dup 5))]
6005 {
6006 operands[5] = shallow_copy_rtx (operands[2]);
6007 XEXP (operands[5], 0) = operands[1];
6008 })
6010 ;; Transform
6011 ;;
6012 ;; mov src,reg
6013 ;; op reg,dst
6014 ;;
6015 ;; into
6016 ;;
6017 ;; op src,dst
6018 ;;
6019 ;; if "reg" dies in the second insn.
6020 (define_peephole2
6021 [(set (match_operand 0 "register_operand" "")
6022 (match_operand 1 "h8300_src_operand" ""))
6023 (set (match_operand 2 "h8300_dst_operand" "")
6024 (match_operator 3 "h8sx_binary_memory_operator"
6025 [(match_operand 4 "h8300_dst_operand" "")
6026 (match_dup 0)]))]
6027 "0 /* Disabale because it break compiling fp-bit.c. */
6028 && TARGET_H8300SX
6029 && peep2_reg_dead_p (2, operands[0])
6030 && !reg_overlap_mentioned_p (operands[0], operands[4])"
6031 [(set (match_dup 2)
6032 (match_dup 5))]
6033 {
6034 operands[5] = shallow_copy_rtx (operands[3]);
6035 XEXP (operands[5], 1) = operands[1];
6036 })
6038 ;; Transform
6039 ;;
6040 ;; mov dst,reg
6041 ;; op reg
6042 ;; mov reg,dst
6043 ;;
6044 ;; into
6045 ;;
6046 ;; op dst
6047 ;;
6048 ;; if "reg" dies at the end of the sequence.
6049 (define_peephole2
6050 [(set (match_operand 0 "register_operand" "")
6051 (match_operand 1 "memory_operand" ""))
6052 (set (match_dup 0)
6053 (match_operator 2 "h8sx_unary_memory_operator"
6054 [(match_dup 0)]))
6055 (set (match_operand 3 "memory_operand" "")
6056 (match_dup 0))]
6057 "TARGET_H8300SX
6058 && peep2_reg_dead_p (3, operands[0])
6059 && !reg_overlap_mentioned_p (operands[0], operands[3])
6060 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
6061 [(set (match_dup 3)
6062 (match_dup 4))]
6063 {
6064 operands[4] = shallow_copy_rtx (operands[2]);
6065 XEXP (operands[4], 0) = operands[1];
6066 })
6068 ;; Transform
6069 ;;
6070 ;; mov src1,reg
6071 ;; cmp reg,src2
6072 ;;
6073 ;; into
6074 ;;
6075 ;; cmp src1,src2
6076 ;;
6077 ;; if "reg" dies in the comparison.
6078 (define_peephole2
6079 [(set (match_operand 0 "register_operand" "")
6080 (match_operand 1 "h8300_dst_operand" ""))
6081 (set (cc0)
6082 (compare (match_dup 0)
6083 (match_operand 2 "h8300_src_operand" "")))]
6084 "TARGET_H8300SX
6085 && peep2_reg_dead_p (2, operands[0])
6086 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6087 [(set (cc0)
6088 (compare (match_dup 1)
6089 (match_dup 2)))])
6091 ;; Likewise for the second operand.
6092 (define_peephole2
6093 [(set (match_operand 0 "register_operand" "")
6094 (match_operand 1 "h8300_src_operand" ""))
6095 (set (cc0)
6096 (compare (match_operand 2 "h8300_dst_operand" "")
6097 (match_dup 0)))]
6098 "TARGET_H8300SX
6099 && peep2_reg_dead_p (2, operands[0])
6100 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6101 [(set (cc0)
6102 (compare (match_dup 2)
6103 (match_dup 1)))])
6105 ;; Combine two moves.
6106 (define_peephole2
6107 [(set (match_operand 0 "register_operand" "")
6108 (match_operand 1 "h8300_src_operand" ""))
6109 (set (match_operand 2 "h8300_dst_operand" "")
6110 (match_dup 0))]
6111 "TARGET_H8300SX
6112 && peep2_reg_dead_p (2, operands[0])
6113 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6114 [(set (match_dup 2)
6115 (match_dup 1))])