?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Introduce sh2a support.
[official-gcc.git] / gcc / config / sh / sh.h
blob276bd1e11012077d546104a387f031a89e73e37e
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
29
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
34
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
43 builtin_define ("__sh1__"); \
44 break; \
45 case PROCESSOR_SH2: \
46 builtin_define ("__sh2__"); \
47 break; \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
50 break; \
51 case PROCESSOR_SH2A: \
52 builtin_define ("__SH2A__"); \
53 builtin_define (TARGET_SH2A_DOUBLE \
54 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
55 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
56 : "__SH2A_NOFPU__"); \
57 break; \
58 case PROCESSOR_SH3: \
59 builtin_define ("__sh3__"); \
60 builtin_define ("__SH3__"); \
61 if (TARGET_HARD_SH4) \
62 builtin_define ("__SH4_NOFPU__"); \
63 break; \
64 case PROCESSOR_SH3E: \
65 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
66 break; \
67 case PROCESSOR_SH4: \
68 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
69 break; \
70 case PROCESSOR_SH4A: \
71 builtin_define ("__SH4A__"); \
72 builtin_define (TARGET_SH4 \
73 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
74 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
75 : "__SH4_NOFPU__"); \
76 break; \
77 case PROCESSOR_SH5: \
78 { \
79 builtin_define_with_value ("__SH5__", \
80 TARGET_SHMEDIA64 ? "64" : "32", 0); \
81 builtin_define_with_value ("__SHMEDIA__", \
82 TARGET_SHMEDIA ? "1" : "0", 0); \
83 if (! TARGET_FPU_DOUBLE) \
84 builtin_define ("__SH4_NOFPU__"); \
85 } \
86 } \
87 if (TARGET_HITACHI) \
88 builtin_define ("__HITACHI__"); \
89 builtin_define (TARGET_LITTLE_ENDIAN \
90 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
91 if (flag_pic) \
92 { \
93 builtin_define ("__pic__"); \
94 builtin_define ("__PIC__"); \
95 } \
96 } while (0)
97
98 /* We can not debug without a frame pointer. */
99 /* #define CAN_DEBUG_WITHOUT_FP */
100
101 #define CONDITIONAL_REGISTER_USAGE do \
102 { \
103 int regno; \
104 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
105 if (! VALID_REGISTER_P (regno)) \
106 fixed_regs[regno] = call_used_regs[regno] = 1; \
107 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
108 if (TARGET_SH5) \
109 call_used_regs[FIRST_GENERAL_REG + 8] \
110 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
111 if (TARGET_SHMEDIA) \
112 { \
113 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
114 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
115 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
116 } \
117 if (flag_pic) \
118 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
119 /* Renesas saves and restores mac registers on call. */ \
120 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
121 { \
122 call_used_regs[MACH_REG] = 0; \
123 call_used_regs[MACL_REG] = 0; \
124 } \
125 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
126 regno <= LAST_FP_REG; regno += 2) \
127 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
128 if (TARGET_SHMEDIA) \
129 { \
130 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
131 if (! fixed_regs[regno] && call_used_regs[regno]) \
132 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
133 } \
134 else \
135 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
136 if (! fixed_regs[regno] && call_used_regs[regno]) \
137 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
138 } while (0)
139 \f
140 /* ??? Need to write documentation for all SH options and add it to the
141 invoke.texi file. */
142
143 /* Run-time compilation parameters selecting different hardware subsets. */
144
145 extern int target_flags;
146 #define ISIZE_BIT (1<<1)
147 #define DALIGN_BIT (1<<6)
148 #define SH1_BIT (1<<8)
149 #define SH2_BIT (1<<9)
150 #define SH3_BIT (1<<10)
151 #define SH_E_BIT (1<<11)
152 #define HARD_SH4_BIT (1<<5)
153 #define FPU_SINGLE_BIT (1<<7)
154 #define SH4_BIT (1<<12)
155 #define SH4A_BIT (1<<3)
156 #define FMOVD_BIT (1<<4)
157 #define SH5_BIT (1<<0)
158 #define SPACE_BIT (1<<13)
159 #define BIGTABLE_BIT (1<<14)
160 #define RELAX_BIT (1<<15)
161 #define USERMODE_BIT (1<<16)
162 #define HITACHI_BIT (1<<22)
163 #define NOMACSAVE_BIT (1<<23)
164 #define PREFERGOT_BIT (1<<24)
165 #define PADSTRUCT_BIT (1<<28)
166 #define LITTLE_ENDIAN_BIT (1<<29)
167 #define IEEE_BIT (1<<30)
168 #define SAVE_ALL_TR_BIT (1<<2)
169 #define HARD_SH2A_BIT (1<<17)
170 #define HARD_SH2A_DOUBLE_BIT (1<<18)
171
172 /* Nonzero if this is an ELF target - compile time only */
173 #define TARGET_ELF 0
174
175 /* Nonzero if we should dump out instruction size info. */
176 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
177
178 /* Nonzero to align doubles on 64 bit boundaries. */
179 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
180
181 /* Nonzero if we should generate code using type 1 insns. */
182 #define TARGET_SH1 (target_flags & SH1_BIT)
183
184 /* Nonzero if we should generate code using type 2 insns. */
185 #define TARGET_SH2 (target_flags & SH2_BIT)
186
187 /* Nonzero if we should generate code using type 2E insns. */
188 #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
189
190 /* Nonzero if we should generate code using type 2A insns. */
191 #define TARGET_SH2A (target_flags & HARD_SH2A_BIT)
192 /* Nonzero if we should generate code using type 2A SF insns. */
193 #define TARGET_SH2A_SINGLE ((target_flags & HARD_SH2A_BIT) && TARGET_SH2E)
194 /* Nonzero if we should generate code using type 2A DF insns. */
195 #define TARGET_SH2A_DOUBLE ((target_flags & HARD_SH2A_DOUBLE_BIT) && TARGET_SH2A)
196
197 /* Nonzero if we should generate code using type 3 insns. */
198 #define TARGET_SH3 (target_flags & SH3_BIT)
199
200 /* Nonzero if we should generate code using type 3E insns. */
201 #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
202
203 /* Nonzero if the cache line size is 32. */
204 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
205
206 /* Nonzero if we schedule for a superscalar implementation. */
207 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
208
209 /* Nonzero if the target has separate instruction and data caches. */
210 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
211
212 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
213 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
214
215 /* Nonzero if the default precision of th FPU is single */
216 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
217
218 /* Nonzero if a double-precision FPU is available. */
219 #define TARGET_FPU_DOUBLE ((target_flags & SH4_BIT) || TARGET_SH2A_DOUBLE)
220
221 /* Nonzero if an FPU is available. */
222 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
223
224 /* Nonzero if we should generate code using type 4 insns. */
225 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
226
227 /* Nonzero if we're generating code for the common subset of
228 instructions present on both SH4a and SH4al-dsp. */
229 #define TARGET_SH4A_ARCH (target_flags & SH4A_BIT)
230
231 /* Nonzero if we're generating code for SH4a, unless the use of the
232 FPU is disabled (which makes it compatible with SH4al-dsp). */
233 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
234
235 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
236 #define TARGET_SH5 (target_flags & SH5_BIT)
237
238 /* Nonzero if we should generate code using the SHcompact instruction
239 set and 32-bit ABI. */
240 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
241
242 /* Nonzero if we should generate code using the SHmedia instruction
243 set and ABI. */
244 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
245
246 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
247 ABI. */
248 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
249 && (target_flags & SH_E_BIT))
250
251 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
252 ABI. */
253 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
254 && ! (target_flags & SH_E_BIT))
255
256 /* Nonzero if we should generate code using SHmedia FPU instructions. */
257 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
258 /* Nonzero if we should generate fmovd. */
259 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
260
261 /* Nonzero if we respect NANs. */
262 #define TARGET_IEEE (target_flags & IEEE_BIT)
263
264 /* Nonzero if we should generate smaller code rather than faster code. */
265 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
266
267 /* Nonzero to use long jump tables. */
268 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
269
270 /* Nonzero to generate pseudo-ops needed by the assembler and linker
271 to do function call relaxing. */
272 #define TARGET_RELAX (target_flags & RELAX_BIT)
273
274 /* Nonzero if using Renesas's calling convention. */
275 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
276
277 /* Nonzero if not saving macl/mach when using -mhitachi */
278 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
279
280 /* Nonzero if padding structures to a multiple of 4 bytes. This is
281 incompatible with Renesas's compiler, and gives unusual structure layouts
282 which confuse programmers.
283 ??? This option is not useful, but is retained in case there are people
284 who are still relying on it. It may be deleted in the future. */
285 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
286
287 /* Nonzero if generating code for a little endian SH. */
288 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
289
290 /* Nonzero if we should do everything in userland. */
291 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
292
293 /* Nonzero if we should prefer @GOT calls when generating PIC. */
294 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
295
296 #define TARGET_SAVE_ALL_TARGET_REGS (target_flags & SAVE_ALL_TR_BIT)
297
298 /* This is not used by the SH2E calling convention */
299 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
300 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
301 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
302
303 #ifndef TARGET_CPU_DEFAULT
304 #define TARGET_CPU_DEFAULT SELECT_SH1
305 #define SUPPORT_SH1
306 #define SUPPORT_SH2E
307 #define SUPPORT_SH4
308 #define SUPPORT_SH4_SINGLE
309 #define SUPPORT_SH2A
310 #define SUPPORT_SH2A_SINGLE
311 #endif
312
313 #define SELECT_SH1 (SH1_BIT)
314 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
315 #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
316 #define SELECT_SH2A (SH_E_BIT | HARD_SH2A_BIT | HARD_SH2A_DOUBLE_BIT | SH2_BIT | SH1_BIT)
317 #define SELECT_SH2A_NOFPU (HARD_SH2A_BIT | SH2_BIT | SH1_BIT)
318 #define SELECT_SH2A_SINGLE_ONLY (SH_E_BIT | HARD_SH2A_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
319 #define SELECT_SH2A_SINGLE (SH_E_BIT | HARD_SH2A_BIT | FPU_SINGLE_BIT \
320 | HARD_SH2A_DOUBLE_BIT | SH2_BIT | SH1_BIT)
321 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
322 #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
323 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
324 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
325 #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
326 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
327 #define SELECT_SH4A_NOFPU (SH4A_BIT | SELECT_SH4_NOFPU)
328 #define SELECT_SH4A_SINGLE_ONLY (SH4A_BIT | SELECT_SH4_SINGLE_ONLY)
329 #define SELECT_SH4A (SH4A_BIT | SELECT_SH4)
330 #define SELECT_SH4A_SINGLE (SH4A_BIT | SELECT_SH4_SINGLE)
331 #define SELECT_SH5_64MEDIA (SH5_BIT | SH4_BIT)
332 #define SELECT_SH5_64MEDIA_NOFPU (SH5_BIT)
333 #define SELECT_SH5_32MEDIA (SH5_BIT | SH4_BIT | SH_E_BIT)
334 #define SELECT_SH5_32MEDIA_NOFPU (SH5_BIT | SH_E_BIT)
335 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
336 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
337
338 /* Disable processor switches for which we have no suitable multilibs. */
339 #ifndef SUPPORT_SH1
340 #define TARGET_SWITCH_SH1
341 #ifndef SUPPORT_SH2
342 #define TARGET_SWITCH_SH2
343 #ifndef SUPPORT_SH3
344 #define TARGET_SWITCH_SH3
345 #ifndef SUPPORT_SH4_NOFPU
346 #define TARGET_SWITCH_SH4_NOFPU
347 #endif
348 #ifndef SUPPORT_SH4A_NOFPU
349 #define TARGET_SWITCH_SH4A_NOFPU
350 #endif
351 #ifndef SUPPORT_SH4AL
352 #define TARGET_SWITCH_SH4AL
353 #endif
354 #ifndef SUPPORT_SH2A_NOFPU
355 #define TARGET_SWITCH_SH2A_NOFPU
356 #endif
357 #endif
358 #endif
359 #endif
360
361 #ifndef SUPPORT_SH2E
362 #define TARGET_SWITCH_SH2E
363 #ifndef SUPPORT_SH3E
364 #define TARGET_SWITCH_SH3E
365 #ifndef SUPPORT_SH4_SINGLE_ONLY
366 #define TARGET_SWITCH_SH4_SINGLE_ONLY
367 #endif
368 #ifndef SUPPORT_SH4A_SINGLE_ONLY
369 #define TARGET_SWITCH_SH4A_SINGLE_ONLY
370 #endif
371 #ifndef SUPPORT_SH2A_SINGLE_ONLY
372 #define TARGET_SWITCH_SH2A_SINGLE_ONLY
373 #endif
374 #endif
375 #endif
376
377 #ifndef SUPPORT_SH4
378 #define TARGET_SWITCH_SH4
379 #ifndef SUPPORT_SH4A
380 #define TARGET_SWITCH_SH4A
381 #endif
382 #endif
383
384 #ifndef SUPPORT_SH4_SINGLE
385 #define TARGET_SWITCH_SH4_SINGLE
386 #ifndef SUPPORT_SH4A_SINGLE
387 #define TARGET_SWITCH_SH4A_SINGLE
388 #endif
389 #endif
390
391 #ifndef SUPPORT_SH2A
392 #define TARGET_SWITCH_SH2A
393 #endif
394
395 #ifndef SUPPORT_SH2A_SINGLE
396 #define TARGET_SWITCH_SH2A_SINGLE
397 #endif
398
399 #ifndef SUPPORT_SH5_64MEDIA
400 #define TARGET_SWITCH_SH5_64MEDIA
401 #endif
402
403 #ifndef SUPPORT_SH5_64MEDIA_NOFPU
404 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU
405 #endif
406
407 #if !defined(SUPPORT_SH5_32MEDIA) && !defined (SUPPORT_SH5_COMPACT)
408 #define TARGET_SWITCHES_SH5_32MEDIA
409 #endif
410
411 #if !defined(SUPPORT_SH5_32MEDIA_NOFPU) && !defined (SUPPORT_SH5_COMPACT_NOFPU)
412 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU
413 #endif
414
415 /* Reset all target-selection flags. */
416 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
417 | HARD_SH2A_BIT | HARD_SH2A_DOUBLE_BIT \
418 | SH4A_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
419
420 #ifndef TARGET_SWITCH_SH1
421 #define TARGET_SWITCH_SH1 \
422 {"1", TARGET_NONE, "" }, \
423 {"1", SELECT_SH1, "Generate SH1 code" },
424 #endif
425 #ifndef TARGET_SWITCH_SH2
426 #define TARGET_SWITCH_SH2 \
427 {"2", TARGET_NONE, "" }, \
428 {"2", SELECT_SH2, "Generate SH2 code" },
429 #endif
430 #ifndef TARGET_SWITCH_SH2E
431 #define TARGET_SWITCH_SH2E \
432 {"2e", TARGET_NONE, "" }, \
433 {"2e", SELECT_SH2E, "Generate SH2e code" },
434 #endif
435 #ifndef TARGET_SWITCH_SH2A
436 #define TARGET_SWITCH_SH2A \
437 {"2a", TARGET_NONE, "" }, \
438 {"2a", SELECT_SH2A, "Generate SH2a code" },
439 #endif
440 #ifndef TARGET_SWITCH_SH2A_SINGLE_ONLY
441 #define TARGET_SWITCH_SH2A_SINGLE_ONLY \
442 {"2a-single-only", TARGET_NONE, "" }, \
443 {"2a-single-only", SELECT_SH2A_SINGLE_ONLY, "Generate only single-precision SH2a code" },
444 #endif
445 #ifndef TARGET_SWITCH_SH2A_SINGLE
446 #define TARGET_SWITCH_SH2A_SINGLE \
447 {"2a-single", TARGET_NONE, "" }, \
448 {"2a-single", SELECT_SH2A_SINGLE, "Generate default single-precision SH2a code" },
449 #endif
450 #ifndef TARGET_SWITCH_SH2A_NOFPU
451 #define TARGET_SWITCH_SH2A_NOFPU \
452 {"2a-nofpu", TARGET_NONE, "" }, \
453 {"2a-nofpu", SELECT_SH2A_NOFPU, "Generate SH2a FPU-less code" },
454 #endif
455 #ifndef TARGET_SWITCH_SH3
456 #define TARGET_SWITCH_SH3 \
457 {"3", TARGET_NONE, "" }, \
458 {"3", SELECT_SH3, "Generate SH3 code" },
459 #endif
460 #ifndef TARGET_SWITCH_SH3E
461 #define TARGET_SWITCH_SH3E \
462 {"3e", TARGET_NONE, "" }, \
463 {"3e", SELECT_SH3E, "Generate SH3e code" },
464 #endif
465 #ifndef TARGET_SWITCH_SH4_SINGLE_ONLY
466 #define TARGET_SWITCH_SH4_SINGLE_ONLY \
467 {"4-single-only", TARGET_NONE, "" }, \
468 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" },
469 #endif
470 #ifndef TARGET_SWITCH_SH4_SINGLE
471 #define TARGET_SWITCH_SH4_SINGLE \
472 {"4-single", TARGET_NONE, "" }, \
473 {"4-single", SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" },
474 #endif
475 #ifndef TARGET_SWITCH_SH4_NOFPU
476 #define TARGET_SWITCH_SH4_NOFPU \
477 {"4-nofpu", TARGET_NONE, "" }, \
478 {"4-nofpu", SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" },
479 #endif
480 #ifndef TARGET_SWITCH_SH4
481 #define TARGET_SWITCH_SH4 \
482 {"4", TARGET_NONE, "" }, \
483 {"4", SELECT_SH4, "Generate SH4 code" },
484 #endif
485 #ifndef TARGET_SWITCH_SH4A
486 #define TARGET_SWITCH_SH4A \
487 {"4a", TARGET_NONE, "" }, \
488 {"4a", SELECT_SH4A, "Generate SH4a code" },
489 #endif
490 #ifndef TARGET_SWITCH_SH4A_SINGLE_ONLY
491 #define TARGET_SWITCH_SH4A_SINGLE_ONLY \
492 {"4a-single-only", TARGET_NONE, "" }, \
493 {"4a-single-only", SELECT_SH4A_SINGLE_ONLY, "Generate only single-precision SH4a code" },
494 #endif
495 #ifndef TARGET_SWITCH_SH4A_SINGLE
496 #define TARGET_SWITCH_SH4A_SINGLE \
497 {"4a-single", TARGET_NONE, "" },\
498 {"4a-single", SELECT_SH4A_SINGLE, "Generate default single-precision SH4a code" },
499 #endif
500 #ifndef TARGET_SWITCH_SH4A_NOFPU
501 #define TARGET_SWITCH_SH4A_NOFPU \
502 {"4a-nofpu", TARGET_NONE, "" },\
503 {"4a-nofpu", SELECT_SH4A_NOFPU, "Generate SH4a FPU-less code" },
504 #endif
505 #ifndef TARGET_SWITCH_SH4AL
506 #define TARGET_SWITCH_SH4AL \
507 {"4al", TARGET_NONE, "" },\
508 {"4al", SELECT_SH4A_NOFPU, "Generate SH4al-dsp code" },
509 #endif
510 #ifndef TARGET_SWITCH_SH5_64MEDIA
511 #define TARGET_SWITCH_SH5_64MEDIA \
512 {"5-64media", TARGET_NONE, "" }, \
513 {"5-64media", SELECT_SH5_64MEDIA, "Generate 64-bit SHmedia code" },
514 #endif
515 #ifndef TARGET_SWITCH_SH5_64MEDIA_NOFPU
516 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU \
517 {"5-64media-nofpu", TARGET_NONE, "" }, \
518 {"5-64media-nofpu", SELECT_SH5_64MEDIA_NOFPU, "Generate 64-bit FPU-less SHmedia code" },
519 #endif
520 #ifndef TARGET_SWITCHES_SH5_32MEDIA
521 #define TARGET_SWITCHES_SH5_32MEDIA \
522 {"5-32media", TARGET_NONE, "" }, \
523 {"5-32media", SELECT_SH5_32MEDIA, "Generate 32-bit SHmedia code" }, \
524 {"5-compact", TARGET_NONE, "" }, \
525 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" },
526 #endif
527 #ifndef TARGET_SWITCHES_SH5_32MEDIA_NOFPU
528 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
529 {"5-32media-nofpu", TARGET_NONE, "" }, \
530 {"5-32media-nofpu", SELECT_SH5_32MEDIA_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
531 {"5-compact-nofpu", TARGET_NONE, "" }, \
532 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" },
533 #endif
534
535 #define TARGET_SWITCHES \
536 { TARGET_SWITCH_SH1 \
537 TARGET_SWITCH_SH2 \
538 TARGET_SWITCH_SH2A_SINGLE_ONLY \
539 TARGET_SWITCH_SH2A_SINGLE \
540 TARGET_SWITCH_SH2A_NOFPU \
541 TARGET_SWITCH_SH2A \
542 TARGET_SWITCH_SH2E \
543 TARGET_SWITCH_SH3 \
544 TARGET_SWITCH_SH3E \
545 TARGET_SWITCH_SH4_SINGLE_ONLY \
546 TARGET_SWITCH_SH4_SINGLE \
547 TARGET_SWITCH_SH4_NOFPU \
548 TARGET_SWITCH_SH4 \
549 TARGET_SWITCH_SH4A_SINGLE_ONLY \
550 TARGET_SWITCH_SH4A_SINGLE \
551 TARGET_SWITCH_SH4A_NOFPU \
552 TARGET_SWITCH_SH4A \
553 TARGET_SWITCH_SH4AL \
554 TARGET_SWITCH_SH5_64MEDIA \
555 TARGET_SWITCH_SH5_64MEDIA_NOFPU \
556 TARGET_SWITCHES_SH5_32MEDIA \
557 TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
558 {"b", -LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
559 {"bigtable", BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
560 {"dalign", DALIGN_BIT, "Aligns doubles at 64-bit boundaries" }, \
561 {"fmovd", FMOVD_BIT, "" }, \
562 {"hitachi", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
563 {"renesas", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
564 {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" }, \
565 {"ieee", IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
566 {"isize", ISIZE_BIT, "" }, \
567 {"l", LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
568 {"no-ieee", -IEEE_BIT, "" }, \
569 {"padstruct", PADSTRUCT_BIT, "" }, \
570 {"prefergot", PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
571 {"relax", RELAX_BIT, "Shorten address references during linking" }, \
572 {"space", SPACE_BIT, "Deprecated. Use -Os instead" }, \
573 {"usermode", USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
574 SUBTARGET_SWITCHES \
575 {"", TARGET_DEFAULT, "" } \
576 }
577
578 /* This are meant to be redefined in the host dependent files */
579 #define SUBTARGET_SWITCHES
580
581 /* This defaults us to big-endian. */
582 #ifndef TARGET_ENDIAN_DEFAULT
583 #define TARGET_ENDIAN_DEFAULT 0
584 #endif
585
586 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
587
588 #ifndef SH_MULTILIB_CPU_DEFAULT
589 #define SH_MULTILIB_CPU_DEFAULT "m1"
590 #endif
591
592 #if TARGET_ENDIAN_DEFAULT
593 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
594 #else
595 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
596 #endif
597
598 #define CPP_SPEC " %(subtarget_cpp_spec) "
599
600 #ifndef SUBTARGET_CPP_SPEC
601 #define SUBTARGET_CPP_SPEC ""
602 #endif
603
604 #ifndef SUBTARGET_EXTRA_SPECS
605 #define SUBTARGET_EXTRA_SPECS
606 #endif
607
608 #define EXTRA_SPECS \
609 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
610 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
611 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
612 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
613 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
614 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
615 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
616 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
617 SUBTARGET_EXTRA_SPECS
618
619 #if TARGET_CPU_DEFAULT & HARD_SH4_BIT
620 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
621 #else
622 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
623 #endif
624
625 #define SH_ASM_SPEC \
626 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
627 %(subtarget_asm_isa_spec) %{m4al:-dsp}"
628
629 #define ASM_SPEC SH_ASM_SPEC
630
631 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
632 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
633 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
634 #else
635 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
636 #endif
637 #endif
638
639 #define SUBTARGET_ASM_ISA_SPEC ""
640
641 #define LINK_EMUL_PREFIX "sh%{ml:l}"
642
643 #if TARGET_CPU_DEFAULT & SH5_BIT
644 #if TARGET_CPU_DEFAULT & SH_E_BIT
645 #define LINK_DEFAULT_CPU_EMUL "32"
646 #if TARGET_CPU_DEFAULT & SH1_BIT
647 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
648 #else
649 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
650 #endif /* SH1_BIT */
651 #else /* !SH_E_BIT */
652 #define LINK_DEFAULT_CPU_EMUL "64"
653 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
654 #endif /* SH_E_BIT */
655 #define ASM_ISA_DEFAULT_SPEC \
656 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
657 #else /* !SH5_BIT */
658 #define LINK_DEFAULT_CPU_EMUL ""
659 #define ASM_ISA_DEFAULT_SPEC ""
660 #endif /* SH5_BIT */
661
662 #define SUBTARGET_LINK_EMUL_SUFFIX ""
663 #define SUBTARGET_LINK_SPEC ""
664
665 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
666 so that we can undo the damage without code replication. */
667 #define LINK_SPEC SH_LINK_SPEC
668
669 #define SH_LINK_SPEC "\
670 -m %(link_emul_prefix)\
671 %{m5-compact*|m5-32media*:32}\
672 %{m5-64media*:64}\
673 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
674 %(subtarget_link_emul_suffix) \
675 %{mrelax:-relax} %(subtarget_link_spec)"
676
677 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
678 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
679 do { \
680 if (LEVEL) \
681 flag_omit_frame_pointer = -1; \
682 if (SIZE) \
683 target_flags |= SPACE_BIT; \
684 if (TARGET_SHMEDIA && LEVEL > 1) \
685 { \
686 flag_branch_target_load_optimize = 1; \
687 if (! (SIZE)) \
688 target_flags |= SAVE_ALL_TR_BIT; \
689 } \
690 } while (0)
691
692 #define ASSEMBLER_DIALECT assembler_dialect
693
694 extern int assembler_dialect;
695
696 #define OVERRIDE_OPTIONS \
697 do { \
698 int regno; \
699 \
700 sh_cpu = CPU_SH1; \
701 assembler_dialect = 0; \
702 if (TARGET_SH2) \
703 sh_cpu = CPU_SH2; \
704 if (TARGET_SH2E) \
705 sh_cpu = CPU_SH2E; \
706 if (TARGET_SH2A) \
707 { \
708 sh_cpu = CPU_SH2A; \
709 if (TARGET_SH2A_DOUBLE) \
710 target_flags |= FMOVD_BIT; \
711 } \
712 if (TARGET_SH3) \
713 sh_cpu = CPU_SH3; \
714 if (TARGET_SH3E) \
715 sh_cpu = CPU_SH3E; \
716 if (TARGET_SH4) \
717 { \
718 assembler_dialect = 1; \
719 sh_cpu = CPU_SH4; \
720 } \
721 if (TARGET_SH4A_ARCH) \
722 { \
723 assembler_dialect = 1; \
724 sh_cpu = CPU_SH4A; \
725 } \
726 if (TARGET_SH5) \
727 { \
728 sh_cpu = CPU_SH5; \
729 target_flags |= DALIGN_BIT; \
730 if (TARGET_FPU_ANY \
731 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
732 target_flags |= FMOVD_BIT; \
733 if (TARGET_SHMEDIA) \
734 { \
735 /* There are no delay slots on SHmedia. */ \
736 flag_delayed_branch = 0; \
737 /* Relaxation isn't yet supported for SHmedia */ \
738 target_flags &= ~RELAX_BIT; \
739 } \
740 /* -fprofile-arcs needs a working libgcov . In unified tree \
741 configurations with newlib, this requires to configure with \
742 --with-newlib --with-headers. But there is no way to check \
743 here we have a working libgcov, so just assume that we have. */\
744 if (profile_flag) \
745 { \
746 warning ("Profiling is not supported on this target."); \
747 profile_flag = profile_arc_flag = 0; \
748 } \
749 } \
750 else \
751 { \
752 /* Only the sh64-elf assembler fully supports .quad properly. */\
753 targetm.asm_out.aligned_op.di = NULL; \
754 targetm.asm_out.unaligned_op.di = NULL; \
755 } \
756 if (TARGET_FMOVD) \
757 reg_class_from_letter['e' - 'a'] = NO_REGS; \
758 \
759 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
760 if (! VALID_REGISTER_P (regno)) \
761 sh_register_names[regno][0] = '\0'; \
762 \
763 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
764 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
765 sh_additional_register_names[regno][0] = '\0'; \
766 \
767 if (flag_omit_frame_pointer < 0) \
768 { \
769 /* The debugging information is sufficient, \
770 but gdb doesn't implement this yet */ \
771 if (0) \
772 flag_omit_frame_pointer \
773 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
774 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
775 else \
776 flag_omit_frame_pointer = 0; \
777 } \
778 \
779 if (flag_pic && ! TARGET_PREFERGOT) \
780 flag_no_function_cse = 1; \
781 \
782 if (SMALL_REGISTER_CLASSES) \
783 { \
784 /* Never run scheduling before reload, since that can \
785 break global alloc, and generates slower code anyway due \
786 to the pressure on R0. */ \
787 /* Enable sched1 for SH4; ready queue will be reordered by \
788 the target hooks when pressure is high. We can not do this for \
789 SH3 and lower as they give spill failures for R0. */ \
790 if (!TARGET_HARD_SH4) \
791 flag_schedule_insns = 0; \
792 } \
793 \
794 if (align_loops == 0) \
795 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
796 if (align_jumps == 0) \
797 align_jumps = 1 << CACHE_LOG; \
798 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
799 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
800 \
801 /* Allocation boundary (in *bytes*) for the code of a function. \
802 SH1: 32 bit alignment is faster, because instructions are always \
803 fetched as a pair from a longword boundary. \
804 SH2 .. SH5 : align to cache line start. */ \
805 if (align_functions == 0) \
806 align_functions \
807 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
808 /* The linker relaxation code breaks when a function contains \
809 alignments that are larger than that at the start of a \
810 compilation unit. */ \
811 if (TARGET_RELAX) \
812 { \
813 int min_align \
814 = align_loops > align_jumps ? align_loops : align_jumps; \
815 \
816 /* Also take possible .long constants / mova tables int account. */\
817 if (min_align < 4) \
818 min_align = 4; \
819 if (align_functions < min_align) \
820 align_functions = min_align; \
821 } \
822 } while (0)
823 \f
824 /* Target machine storage layout. */
825
826 /* Define this if most significant bit is lowest numbered
827 in instructions that operate on numbered bit-fields. */
828
829 #define BITS_BIG_ENDIAN 0
830
831 /* Define this if most significant byte of a word is the lowest numbered. */
832 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
833
834 /* Define this if most significant word of a multiword number is the lowest
835 numbered. */
836 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
837
838 /* Define this to set the endianness to use in libgcc2.c, which can
839 not depend on target_flags. */
840 #if defined(__LITTLE_ENDIAN__)
841 #define LIBGCC2_WORDS_BIG_ENDIAN 0
842 #else
843 #define LIBGCC2_WORDS_BIG_ENDIAN 1
844 #endif
845
846 #define MAX_BITS_PER_WORD 64
847
848 /* Width in bits of an `int'. We want just 32-bits, even if words are
849 longer. */
850 #define INT_TYPE_SIZE 32
851
852 /* Width in bits of a `long'. */
853 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
854
855 /* Width in bits of a `long long'. */
856 #define LONG_LONG_TYPE_SIZE 64
857
858 /* Width in bits of a `long double'. */
859 #define LONG_DOUBLE_TYPE_SIZE 64
860
861 /* Width of a word, in units (bytes). */
862 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
863 #define MIN_UNITS_PER_WORD 4
864
865 /* Scaling factor for Dwarf data offsets for CFI information.
866 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
867 SHmedia; however, since we do partial register saves for the registers
868 visible to SHcompact, and for target registers for SHMEDIA32, we have
869 to allow saves that are only 4-byte aligned. */
870 #define DWARF_CIE_DATA_ALIGNMENT -4
871
872 /* Width in bits of a pointer.
873 See also the macro `Pmode' defined below. */
874 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
875
876 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
877 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
878
879 /* Boundary (in *bits*) on which stack pointer should be aligned. */
880 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
881
882 /* The log (base 2) of the cache line size, in bytes. Processors prior to
883 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
884 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
885 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
886
887 /* ABI given & required minimum allocation boundary (in *bits*) for the
888 code of a function. */
889 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
890
891 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
892 the vbit must go into the delta field of
893 pointers-to-member-functions. */
894 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
895 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
896
897 /* Alignment of field after `int : 0' in a structure. */
898 #define EMPTY_FIELD_BOUNDARY 32
899
900 /* No data type wants to be aligned rounder than this. */
901 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
902
903 /* The best alignment to use in cases where we have a choice. */
904 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
905
906 /* Make strings word-aligned so strcpy from constants will be faster. */
907 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
908 ((TREE_CODE (EXP) == STRING_CST \
909 && (ALIGN) < FASTEST_ALIGNMENT) \
910 ? FASTEST_ALIGNMENT : (ALIGN))
911
912 /* get_mode_alignment assumes complex values are always held in multiple
913 registers, but that is not the case on the SH; CQImode and CHImode are
914 held in a single integer register. SH5 also holds CSImode and SCmode
915 values in integer registers. This is relevant for argument passing on
916 SHcompact as we use a stack temp in order to pass CSImode by reference. */
917 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
918 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
919 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
920 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
921 : (unsigned) ALIGN)
922
923 /* Make arrays of chars word-aligned for the same reasons. */
924 #define DATA_ALIGNMENT(TYPE, ALIGN) \
925 (TREE_CODE (TYPE) == ARRAY_TYPE \
926 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
927 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
928
929 /* Number of bits which any structure or union's size must be a
930 multiple of. Each structure or union's size is rounded up to a
931 multiple of this. */
932 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
933
934 /* Set this nonzero if move instructions will actually fail to work
935 when given unaligned data. */
936 #define STRICT_ALIGNMENT 1
937
938 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
939 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
940 barrier_align (LABEL_AFTER_BARRIER)
941
942 #define LOOP_ALIGN(A_LABEL) \
943 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
944 ? 0 : sh_loop_align (A_LABEL))
945
946 #define LABEL_ALIGN(A_LABEL) \
947 ( \
948 (PREV_INSN (A_LABEL) \
949 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
950 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
951 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
952 /* explicit alignment insn in constant tables. */ \
953 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
954 : 0)
955
956 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
957 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
958
959 /* The base two logarithm of the known minimum alignment of an insn length. */
960 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
961 (GET_CODE (A_INSN) == INSN \
962 ? 1 << TARGET_SHMEDIA \
963 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
964 ? 1 << TARGET_SHMEDIA \
965 : CACHE_LOG)
966 \f
967 /* Standard register usage. */
968
969 /* Register allocation for the Renesas calling convention:
970
971 r0 arg return
972 r1..r3 scratch
973 r4..r7 args in
974 r8..r13 call saved
975 r14 frame pointer/call saved
976 r15 stack pointer
977 ap arg pointer (doesn't really exist, always eliminated)
978 pr subroutine return address
979 t t bit
980 mach multiply/accumulate result, high part
981 macl multiply/accumulate result, low part.
982 fpul fp/int communication register
983 rap return address pointer register
984 fr0 fp arg return
985 fr1..fr3 scratch floating point registers
986 fr4..fr11 fp args in
987 fr12..fr15 call saved floating point registers */
988
989 #define MAX_REGISTER_NAME_LENGTH 5
990 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
991
992 #define SH_REGISTER_NAMES_INITIALIZER \
993 { \
994 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
995 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
996 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
997 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
998 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
999 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
1000 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
1001 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
1002 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1003 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
1004 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
1005 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
1006 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
1007 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
1008 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
1009 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
1010 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
1011 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
1012 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
1013 "rap" \
1014 }
1015
1016 #define REGNAMES_ARR_INDEX_1(index) \
1017 (sh_register_names[index])
1018 #define REGNAMES_ARR_INDEX_2(index) \
1019 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
1020 #define REGNAMES_ARR_INDEX_4(index) \
1021 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
1022 #define REGNAMES_ARR_INDEX_8(index) \
1023 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
1024 #define REGNAMES_ARR_INDEX_16(index) \
1025 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
1026 #define REGNAMES_ARR_INDEX_32(index) \
1027 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
1028 #define REGNAMES_ARR_INDEX_64(index) \
1029 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
1030
1031 #define REGISTER_NAMES \
1032 { \
1033 REGNAMES_ARR_INDEX_64 (0), \
1034 REGNAMES_ARR_INDEX_64 (64), \
1035 REGNAMES_ARR_INDEX_8 (128), \
1036 REGNAMES_ARR_INDEX_8 (136), \
1037 REGNAMES_ARR_INDEX_8 (144), \
1038 REGNAMES_ARR_INDEX_1 (152) \
1039 }
1040
1041 #define ADDREGNAMES_SIZE 32
1042 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
1043 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
1044 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
1045
1046 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
1047 { \
1048 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
1049 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
1050 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
1051 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
1052 }
1053
1054 #define ADDREGNAMES_REGNO(index) \
1055 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
1056 : (-1))
1057
1058 #define ADDREGNAMES_ARR_INDEX_1(index) \
1059 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
1060 #define ADDREGNAMES_ARR_INDEX_2(index) \
1061 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
1062 #define ADDREGNAMES_ARR_INDEX_4(index) \
1063 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
1064 #define ADDREGNAMES_ARR_INDEX_8(index) \
1065 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1066 #define ADDREGNAMES_ARR_INDEX_16(index) \
1067 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1068 #define ADDREGNAMES_ARR_INDEX_32(index) \
1069 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1070
1071 #define ADDITIONAL_REGISTER_NAMES \
1072 { \
1073 ADDREGNAMES_ARR_INDEX_32 (0) \
1074 }
1075
1076 /* Number of actual hardware registers.
1077 The hardware registers are assigned numbers for the compiler
1078 from 0 to just below FIRST_PSEUDO_REGISTER.
1079 All registers that the compiler knows about must be given numbers,
1080 even those that are not normally considered general registers. */
1081
1082 /* There are many other relevant definitions in sh.md's md_constants. */
1083
1084 #define FIRST_GENERAL_REG R0_REG
1085 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1086 #define FIRST_FP_REG DR0_REG
1087 #define LAST_FP_REG (FIRST_FP_REG + \
1088 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1089 #define FIRST_XD_REG XD0_REG
1090 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1091 #define FIRST_TARGET_REG TR0_REG
1092 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1093
1094 #define GENERAL_REGISTER_P(REGNO) \
1095 IN_RANGE ((REGNO), \
1096 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1097 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1098
1099 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1100 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
1101
1102 #define FP_REGISTER_P(REGNO) \
1103 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1104
1105 #define XD_REGISTER_P(REGNO) \
1106 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1107
1108 #define FP_OR_XD_REGISTER_P(REGNO) \
1109 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1110
1111 #define FP_ANY_REGISTER_P(REGNO) \
1112 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1113
1114 #define SPECIAL_REGISTER_P(REGNO) \
1115 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1116 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1117
1118 #define TARGET_REGISTER_P(REGNO) \
1119 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1120
1121 #define SHMEDIA_REGISTER_P(REGNO) \
1122 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1123 || TARGET_REGISTER_P (REGNO))
1124
1125 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1126 that should be fixed. */
1127 #define VALID_REGISTER_P(REGNO) \
1128 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1129 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1130 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1131 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1132
1133 /* The mode that should be generally used to store a register by
1134 itself in the stack, or to load it back. */
1135 #define REGISTER_NATURAL_MODE(REGNO) \
1136 (FP_REGISTER_P (REGNO) ? SFmode \
1137 : XD_REGISTER_P (REGNO) ? DFmode \
1138 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1139 ? DImode \
1140 : SImode)
1141
1142 #define FIRST_PSEUDO_REGISTER 153
1143
1144 /* 1 for registers that have pervasive standard uses
1145 and are not available for the register allocator.
1146
1147 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1148 It is 32 bits wide for SH2. */
1149
1150 #define FIXED_REGISTERS \
1151 { \
1152 /* Regular registers. */ \
1153 0, 0, 0, 0, 0, 0, 0, 0, \
1154 0, 0, 0, 0, 0, 0, 0, 1, \
1155 /* r16 is reserved, r18 is the former pr. */ \
1156 1, 0, 0, 0, 0, 0, 0, 0, \
1157 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1158 /* r26 is a global variable data pointer; r27 is for constants. */ \
1159 1, 1, 1, 1, 0, 0, 0, 0, \
1160 0, 0, 0, 0, 0, 0, 0, 0, \
1161 0, 0, 0, 0, 0, 0, 0, 0, \
1162 0, 0, 0, 0, 0, 0, 0, 0, \
1163 0, 0, 0, 0, 0, 0, 0, 1, \
1164 /* FP registers. */ \
1165 0, 0, 0, 0, 0, 0, 0, 0, \
1166 0, 0, 0, 0, 0, 0, 0, 0, \
1167 0, 0, 0, 0, 0, 0, 0, 0, \
1168 0, 0, 0, 0, 0, 0, 0, 0, \
1169 0, 0, 0, 0, 0, 0, 0, 0, \
1170 0, 0, 0, 0, 0, 0, 0, 0, \
1171 0, 0, 0, 0, 0, 0, 0, 0, \
1172 0, 0, 0, 0, 0, 0, 0, 0, \
1173 /* Branch target registers. */ \
1174 0, 0, 0, 0, 0, 0, 0, 0, \
1175 /* XD registers. */ \
1176 0, 0, 0, 0, 0, 0, 0, 0, \
1177 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1178 1, 1, 1, 1, 1, 1, 0, 1, \
1179 /*"rap" */ \
1180 1, \
1181 }
1182
1183 /* 1 for registers not available across function calls.
1184 These must include the FIXED_REGISTERS and also any
1185 registers that can be used without being saved.
1186 The latter must include the registers where values are returned
1187 and the register where structure-value addresses are passed.
1188 Aside from that, you can include as many other registers as you like. */
1189
1190 #define CALL_USED_REGISTERS \
1191 { \
1192 /* Regular registers. */ \
1193 1, 1, 1, 1, 1, 1, 1, 1, \
1194 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1195 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1196 across SH5 function calls. */ \
1197 0, 0, 0, 0, 0, 0, 0, 1, \
1198 1, 1, 1, 1, 1, 1, 1, 1, \
1199 1, 1, 1, 1, 0, 0, 0, 0, \
1200 0, 0, 0, 0, 1, 1, 1, 1, \
1201 1, 1, 1, 1, 0, 0, 0, 0, \
1202 0, 0, 0, 0, 0, 0, 0, 0, \
1203 0, 0, 0, 0, 1, 1, 1, 1, \
1204 /* FP registers. */ \
1205 1, 1, 1, 1, 1, 1, 1, 1, \
1206 1, 1, 1, 1, 0, 0, 0, 0, \
1207 1, 1, 1, 1, 1, 1, 1, 1, \
1208 1, 1, 1, 1, 1, 1, 1, 1, \
1209 1, 1, 1, 1, 0, 0, 0, 0, \
1210 0, 0, 0, 0, 0, 0, 0, 0, \
1211 0, 0, 0, 0, 0, 0, 0, 0, \
1212 0, 0, 0, 0, 0, 0, 0, 0, \
1213 /* Branch target registers. */ \
1214 1, 1, 1, 1, 1, 0, 0, 0, \
1215 /* XD registers. */ \
1216 1, 1, 1, 1, 1, 1, 0, 0, \
1217 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1218 1, 1, 1, 1, 1, 1, 1, 1, \
1219 /*"rap" */ \
1220 1, \
1221 }
1222
1223 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1224 across SHcompact function calls. We can't tell whether a called
1225 function is SHmedia or SHcompact, so we assume it may be when
1226 compiling SHmedia code with the 32-bit ABI, since that's the only
1227 ABI that can be linked with SHcompact code. */
1228 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1229 (TARGET_SHMEDIA32 \
1230 && GET_MODE_SIZE (MODE) > 4 \
1231 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1232 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1233 || TARGET_REGISTER_P (REGNO) \
1234 || (REGNO) == PR_MEDIA_REG))
1235
1236 /* Return number of consecutive hard regs needed starting at reg REGNO
1237 to hold something of mode MODE.
1238 This is ordinarily the length in words of a value of mode MODE
1239 but can be less for certain modes in special long registers.
1240
1241 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1242
1243 #define HARD_REGNO_NREGS(REGNO, MODE) \
1244 (XD_REGISTER_P (REGNO) \
1245 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1246 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1247 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1248 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1249
1250 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1251 We can allow any mode in any general register. The special registers
1252 only allow SImode. Don't allow any mode in the PR. */
1253
1254 /* We cannot hold DCmode values in the XD registers because alter_reg
1255 handles subregs of them incorrectly. We could work around this by
1256 spacing the XD registers like the DR registers, but this would require
1257 additional memory in every compilation to hold larger register vectors.
1258 We could hold SFmode / SCmode values in XD registers, but that
1259 would require a tertiary reload when reloading from / to memory,
1260 and a secondary reload to reload from / to general regs; that
1261 seems to be a loosing proposition. */
1262 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1263 it won't be ferried through GP registers first. */
1264 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1265 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1266 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1267 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1268 ? 1 \
1269 : (MODE) == V2SFmode \
1270 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1271 || GENERAL_REGISTER_P (REGNO)) \
1272 : (MODE) == V4SFmode \
1273 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1274 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
1275 : (MODE) == V16SFmode \
1276 ? (TARGET_SHMEDIA \
1277 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1278 : (REGNO) == FIRST_XD_REG) \
1279 : FP_REGISTER_P (REGNO) \
1280 ? ((MODE) == SFmode || (MODE) == SImode \
1281 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1282 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1283 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1284 || (MODE) == V2SFmode || (MODE) == TImode))) \
1285 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
1286 : XD_REGISTER_P (REGNO) \
1287 ? (MODE) == DFmode \
1288 : TARGET_REGISTER_P (REGNO) \
1289 ? ((MODE) == DImode || (MODE) == SImode) \
1290 : (REGNO) == PR_REG ? (MODE) == SImode \
1291 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1292 : 1)
1293
1294 /* Value is 1 if MODE is a supported vector mode. */
1295 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1296 ((TARGET_FPU_ANY \
1297 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
1298 || (TARGET_SHMEDIA \
1299 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
1300 || (MODE) == V2SImode)))
1301
1302 /* Value is 1 if it is a good idea to tie two pseudo registers
1303 when one has mode MODE1 and one has mode MODE2.
1304 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1305 for any hard reg, then this must be 0 for correct output.
1306 That's the case for xd registers: we don't hold SFmode values in
1307 them, so we can't tie an SFmode pseudos with one in another
1308 floating-point mode. */
1309
1310 #define MODES_TIEABLE_P(MODE1, MODE2) \
1311 ((MODE1) == (MODE2) \
1312 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1313 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1314 && (GET_MODE_SIZE (MODE2) <= 4)) \
1315 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1316
1317 /* A C expression that is nonzero if hard register NEW_REG can be
1318 considered for use as a rename register for OLD_REG register */
1319
1320 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1321 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1322
1323 /* Specify the registers used for certain standard purposes.
1324 The values of these macros are register numbers. */
1325
1326 /* Define this if the program counter is overloaded on a register. */
1327 /* #define PC_REGNUM 15*/
1328
1329 /* Register to use for pushing function arguments. */
1330 #define STACK_POINTER_REGNUM SP_REG
1331
1332 /* Base register for access to local variables of the function. */
1333 #define FRAME_POINTER_REGNUM FP_REG
1334
1335 /* Fake register that holds the address on the stack of the
1336 current function's return address. */
1337 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1338
1339 /* Register to hold the addressing base for position independent
1340 code access to data items. */
1341 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1342
1343 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1344
1345 /* Value should be nonzero if functions must have frame pointers.
1346 Zero means the frame pointer need not be set up (and parms may be accessed
1347 via the stack pointer) in functions that seem suitable. */
1348
1349 #define FRAME_POINTER_REQUIRED 0
1350
1351 /* Definitions for register eliminations.
1352
1353 We have three registers that can be eliminated on the SH. First, the
1354 frame pointer register can often be eliminated in favor of the stack
1355 pointer register. Secondly, the argument pointer register can always be
1356 eliminated; it is replaced with either the stack or frame pointer.
1357 Third, there is the return address pointer, which can also be replaced
1358 with either the stack or the frame pointer. */
1359
1360 /* This is an array of structures. Each structure initializes one pair
1361 of eliminable registers. The "from" register number is given first,
1362 followed by "to". Eliminations of the same "from" register are listed
1363 in order of preference. */
1364
1365 /* If you add any registers here that are not actually hard registers,
1366 and that have any alternative of elimination that doesn't always
1367 apply, you need to amend calc_live_regs to exclude it, because
1368 reload spills all eliminable registers where it sees an
1369 can_eliminate == 0 entry, thus making them 'live' .
1370 If you add any hard registers that can be eliminated in different
1371 ways, you have to patch reload to spill them only when all alternatives
1372 of elimination fail. */
1373
1374 #define ELIMINABLE_REGS \
1375 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1376 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1377 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1378 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1379 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1380
1381 /* Given FROM and TO register numbers, say whether this elimination
1382 is allowed. */
1383 #define CAN_ELIMINATE(FROM, TO) \
1384 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1385
1386 /* Define the offset between two registers, one to be eliminated, and the other
1387 its replacement, at the start of a routine. */
1388
1389 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1390 OFFSET = initial_elimination_offset ((FROM), (TO))
1391
1392 /* Base register for access to arguments of the function. */
1393 #define ARG_POINTER_REGNUM AP_REG
1394
1395 /* Register in which the static-chain is passed to a function. */
1396 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1397
1398 /* Don't default to pcc-struct-return, because we have already specified
1399 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1400 target hook. */
1401
1402 #define DEFAULT_PCC_STRUCT_RETURN 0
1403
1404 #define SHMEDIA_REGS_STACK_ADJUST() \
1405 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1406 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1407 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1408 : 0)
1409
1410 \f
1411 /* Define the classes of registers for register constraints in the
1412 machine description. Also define ranges of constants.
1413
1414 One of the classes must always be named ALL_REGS and include all hard regs.
1415 If there is more than one class, another class must be named NO_REGS
1416 and contain no registers.
1417
1418 The name GENERAL_REGS must be the name of a class (or an alias for
1419 another name such as ALL_REGS). This is the class of registers
1420 that is allowed by "g" or "r" in a register constraint.
1421 Also, registers outside this class are allocated only when
1422 instructions express preferences for them.
1423
1424 The classes must be numbered in nondecreasing order; that is,
1425 a larger-numbered class must never be contained completely
1426 in a smaller-numbered class.
1427
1428 For any two classes, it is very desirable that there be another
1429 class that represents their union. */
1430
1431 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1432 be used as the destination of some of the arithmetic ops. There are
1433 also some special purpose registers; the T bit register, the
1434 Procedure Return Register and the Multiply Accumulate Registers. */
1435 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1436 reg_class_subunion. We don't want to have an actual union class
1437 of these, because it would only be used when both classes are calculated
1438 to give the same cost, but there is only one FPUL register.
1439 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1440 applying to the actual instruction alternative considered. E.g., the
1441 y/r alternative of movsi_ie is considered to have no more cost that
1442 the r/r alternative, which is patently untrue. */
1443
1444 enum reg_class
1445 {
1446 NO_REGS,
1447 R0_REGS,
1448 PR_REGS,
1449 T_REGS,
1450 MAC_REGS,
1451 FPUL_REGS,
1452 SIBCALL_REGS,
1453 GENERAL_REGS,
1454 FP0_REGS,
1455 FP_REGS,
1456 DF_HI_REGS,
1457 DF_REGS,
1458 FPSCR_REGS,
1459 GENERAL_FP_REGS,
1460 TARGET_REGS,
1461 ALL_REGS,
1462 LIM_REG_CLASSES
1463 };
1464
1465 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1466
1467 /* Give names of register classes as strings for dump file. */
1468 #define REG_CLASS_NAMES \
1469 { \
1470 "NO_REGS", \
1471 "R0_REGS", \
1472 "PR_REGS", \
1473 "T_REGS", \
1474 "MAC_REGS", \
1475 "FPUL_REGS", \
1476 "SIBCALL_REGS", \
1477 "GENERAL_REGS", \
1478 "FP0_REGS", \
1479 "FP_REGS", \
1480 "DF_HI_REGS", \
1481 "DF_REGS", \
1482 "FPSCR_REGS", \
1483 "GENERAL_FP_REGS", \
1484 "TARGET_REGS", \
1485 "ALL_REGS", \
1486 }
1487
1488 /* Define which registers fit in which classes.
1489 This is an initializer for a vector of HARD_REG_SET
1490 of length N_REG_CLASSES. */
1491
1492 #define REG_CLASS_CONTENTS \
1493 { \
1494 /* NO_REGS: */ \
1495 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1496 /* R0_REGS: */ \
1497 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1498 /* PR_REGS: */ \
1499 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1500 /* T_REGS: */ \
1501 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1502 /* MAC_REGS: */ \
1503 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1504 /* FPUL_REGS: */ \
1505 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1506 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1507 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1508 /* GENERAL_REGS: */ \
1509 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1510 /* FP0_REGS: */ \
1511 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1512 /* FP_REGS: */ \
1513 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1514 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1515 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1516 /* DF_REGS: */ \
1517 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1518 /* FPSCR_REGS: */ \
1519 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1520 /* GENERAL_FP_REGS: */ \
1521 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1522 /* TARGET_REGS: */ \
1523 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1524 /* ALL_REGS: */ \
1525 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1526 }
1527
1528 /* The same information, inverted:
1529 Return the class number of the smallest class containing
1530 reg number REGNO. This could be a conditional expression
1531 or could index an array. */
1532
1533 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1534 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1535
1536 /* When defined, the compiler allows registers explicitly used in the
1537 rtl to be used as spill registers but prevents the compiler from
1538 extending the lifetime of these registers. */
1539
1540 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1541
1542 /* The order in which register should be allocated. */
1543 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1544 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1545 spilled or used otherwise, we better have the FP_REGS allocated first. */
1546 #define REG_ALLOC_ORDER \
1547 {/* Caller-saved FPRs */ \
1548 65, 66, 67, 68, 69, 70, 71, 64, \
1549 72, 73, 74, 75, 80, 81, 82, 83, \
1550 84, 85, 86, 87, 88, 89, 90, 91, \
1551 92, 93, 94, 95, 96, 97, 98, 99, \
1552 /* Callee-saved FPRs */ \
1553 76, 77, 78, 79,100,101,102,103, \
1554 104,105,106,107,108,109,110,111, \
1555 112,113,114,115,116,117,118,119, \
1556 120,121,122,123,124,125,126,127, \
1557 136,137,138,139,140,141,142,143, \
1558 /* FPSCR */ 151, \
1559 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1560 1, 2, 3, 7, 6, 5, 4, 0, \
1561 8, 9, 17, 19, 20, 21, 22, 23, \
1562 36, 37, 38, 39, 40, 41, 42, 43, \
1563 60, 61, 62, \
1564 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1565 10, 11, 12, 13, 14, 18, \
1566 /* SH5 callee-saved GPRs */ \
1567 28, 29, 30, 31, 32, 33, 34, 35, \
1568 44, 45, 46, 47, 48, 49, 50, 51, \
1569 52, 53, 54, 55, 56, 57, 58, 59, \
1570 /* FPUL */ 150, \
1571 /* SH5 branch target registers */ \
1572 128,129,130,131,132,133,134,135, \
1573 /* Fixed registers */ \
1574 15, 16, 24, 25, 26, 27, 63,144, \
1575 145,146,147,148,149,152 }
1576
1577 /* The class value for index registers, and the one for base regs. */
1578 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1579 #define BASE_REG_CLASS GENERAL_REGS
1580
1581 /* Get reg_class from a letter such as appears in the machine
1582 description. */
1583 extern enum reg_class reg_class_from_letter[];
1584
1585 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1586 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1587 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1588 \f
1589 /* Overview of uppercase letter constraints:
1590 A: Addresses (constraint len == 3)
1591 Ac4: sh4 cache operations
1592 Ac5: sh5 cache operations
1593 Bxx: miscellaneous constraints
1594 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1595 fldi0 / fldi0 cases
1596 C: Constants other than only CONST_INT (constraint len == 3)
1597 C16: 16 bit constant, literal or symbolic
1598 Csy: label or symbol
1599 Cpg: non-explicit constants that can be directly loaded into a general
1600 purpose register in PIC code. like 's' except we don't allow
1601 PIC_DIRECT_ADDR_P
1602 IJKLMNOP: CONT_INT constants
1603 Ixx: signed xx bit
1604 J16: 0xffffffff00000000 | 0x00000000ffffffff
1605 Kxx: unsigned xx bit
1606 M: 1
1607 N: 0
1608 P27: 1 | 2 | 8 | 16
1609 Q: pc relative load operand
1610 Rxx: reserved for exotic register classes.
1611 S: extra memory (storage) constraints (constraint len == 3)
1612 Sua: unaligned memory operations
1613 W: vector
1614 Z: zero in any mode
1615
1616 unused CONST_INT constraint letters: LO
1617 unused EXTRA_CONSTRAINT letters: D T U Y */
1618
1619 #if 1 /* check that the transition went well. */
1620 #define CONSTRAINT_LEN(C,STR) \
1621 (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
1622 || (C) == 'Y' \
1623 || ((C) == 'I' \
1624 && (((STR)[1] != '0' && (STR)[1] != '1' && (STR)[1] != '2') \
1625 || (STR)[2] < '0' || (STR)[2] > '9')) \
1626 || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
1627 || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
1628 || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
1629 || ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
1630 ? -1 \
1631 : ((C) == 'A' || (C) == 'B' || (C) == 'C' \
1632 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1633 || (C) == 'R' || (C) == 'S') \
1634 ? 3 \
1635 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1636 #else
1637 #define CONSTRAINT_LEN(C,STR) \
1638 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1639 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1640 || (C) == 'R' || (C) == 'S') \
1641 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1642 #endif
1643
1644 /* The letters I, J, K, L and M in a register constraint string
1645 can be used to stand for particular ranges of immediate operands.
1646 This macro defines what the ranges are.
1647 C is the letter, and VALUE is a constant value.
1648 Return 1 if VALUE is in the range specified by C.
1649 I08: arithmetic operand -127..128, as used in add, sub, etc
1650 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1651 P27: shift operand 1,2,8 or 16
1652 K08: logical operand 0..255, as used in and, or, etc.
1653 M: constant 1
1654 N: constant 0
1655 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1656 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1657 */
1658
1659 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1660 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1661 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1662 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1663 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1664 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1665 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1666 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1667 #define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
1668 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \
1669 && TARGET_SH2A)
1670 #define CONST_OK_FOR_I(VALUE, STR) \
1671 ((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
1672 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1673 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1674 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1675 : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
1676 : 0)
1677
1678 #define CONST_OK_FOR_J16(VALUE) \
1679 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1680 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1681 #define CONST_OK_FOR_J(VALUE, STR) \
1682 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1683 : 0)
1684
1685 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1686 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1687 #define CONST_OK_FOR_K(VALUE, STR) \
1688 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1689 : 0)
1690 #define CONST_OK_FOR_P27(VALUE) \
1691 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1692 #define CONST_OK_FOR_P(VALUE, STR) \
1693 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1694 : 0)
1695 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1696 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1697 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1698 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1699 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1700 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1701 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1702 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1703 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1704 : 0)
1705
1706 /* Similar, but for floating constants, and defining letters G and H.
1707 Here VALUE is the CONST_DOUBLE rtx itself. */
1708
1709 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1710 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1711 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1712 : (C) == 'F')
1713
1714 /* Given an rtx X being reloaded into a reg required to be
1715 in class CLASS, return the class of reg to actually use.
1716 In general this is just CLASS; but on some machines
1717 in some cases it is preferable to use a more restrictive class. */
1718
1719 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1720 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1721 && (GET_CODE (X) == CONST_DOUBLE \
1722 || GET_CODE (X) == SYMBOL_REF) \
1723 ? GENERAL_REGS \
1724 : (CLASS)) \
1725
1726 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1727 ((((REGCLASS_HAS_FP_REG (CLASS) \
1728 && (GET_CODE (X) == REG \
1729 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1730 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1731 && TARGET_FMOVD)))) \
1732 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1733 && GET_CODE (X) == REG \
1734 && FP_REGISTER_P (REGNO (X)))) \
1735 && ! TARGET_SHMEDIA \
1736 && ((MODE) == SFmode || (MODE) == SImode)) \
1737 ? FPUL_REGS \
1738 : (((CLASS) == FPUL_REGS \
1739 || (REGCLASS_HAS_FP_REG (CLASS) \
1740 && ! TARGET_SHMEDIA && MODE == SImode)) \
1741 && (GET_CODE (X) == MEM \
1742 || (GET_CODE (X) == REG \
1743 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1744 || REGNO (X) == T_REG \
1745 || system_reg_operand (X, VOIDmode))))) \
1746 ? GENERAL_REGS \
1747 : ((CLASS) == TARGET_REGS \
1748 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1749 ? ((target_operand ((X), (MODE)) \
1750 && ! target_reg_operand ((X), (MODE))) \
1751 ? NO_REGS : GENERAL_REGS) \
1752 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1753 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1754 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1755 ? GENERAL_REGS \
1756 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1757 && TARGET_REGISTER_P (REGNO (X))) \
1758 ? GENERAL_REGS : NO_REGS)
1759
1760 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1761 ((REGCLASS_HAS_FP_REG (CLASS) \
1762 && ! TARGET_SHMEDIA \
1763 && immediate_operand ((X), (MODE)) \
1764 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1765 && (MODE) == SFmode && fldi_ok ())) \
1766 ? R0_REGS \
1767 : (CLASS == FPUL_REGS \
1768 && ((GET_CODE (X) == REG \
1769 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1770 || REGNO (X) == T_REG)) \
1771 || GET_CODE (X) == PLUS)) \
1772 ? GENERAL_REGS \
1773 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1774 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1775 ? GENERAL_REGS \
1776 : R0_REGS) \
1777 : (CLASS == FPSCR_REGS \
1778 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1779 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1780 ? GENERAL_REGS \
1781 : (REGCLASS_HAS_FP_REG (CLASS) \
1782 && TARGET_SHMEDIA \
1783 && immediate_operand ((X), (MODE)) \
1784 && (X) != CONST0_RTX (GET_MODE (X)) \
1785 && GET_MODE (X) != V4SFmode) \
1786 ? GENERAL_REGS \
1787 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1788
1789 /* Return the maximum number of consecutive registers
1790 needed to represent mode MODE in a register of class CLASS.
1791
1792 If TARGET_SHMEDIA, we need two FP registers per word.
1793 Otherwise we will need at most one register per word. */
1794 #define CLASS_MAX_NREGS(CLASS, MODE) \
1795 (TARGET_SHMEDIA \
1796 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1797 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1798 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1799
1800 /* If defined, gives a class of registers that cannot be used as the
1801 operand of a SUBREG that changes the mode of the object illegally. */
1802 /* ??? We need to renumber the internal numbers for the frnn registers
1803 when in little endian in order to allow mode size changes. */
1804
1805 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1806 sh_cannot_change_mode_class (FROM, TO, CLASS)
1807 \f
1808 /* Stack layout; function entry, exit and calling. */
1809
1810 /* Define the number of registers that can hold parameters.
1811 These macros are used only in other macro definitions below. */
1812
1813 #define NPARM_REGS(MODE) \
1814 (TARGET_FPU_ANY && (MODE) == SFmode \
1815 ? (TARGET_SH5 ? 12 : 8) \
1816 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1817 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1818 ? (TARGET_SH5 ? 12 : 8) \
1819 : (TARGET_SH5 ? 8 : 4))
1820
1821 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1822 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1823
1824 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1825 #define FIRST_FP_RET_REG FIRST_FP_REG
1826
1827 /* Define this if pushing a word on the stack
1828 makes the stack pointer a smaller address. */
1829 #define STACK_GROWS_DOWNWARD
1830
1831 /* Define this macro if the addresses of local variable slots are at
1832 negative offsets from the frame pointer.
1833
1834 The SH only has positive indexes, so grow the frame up. */
1835 /* #define FRAME_GROWS_DOWNWARD */
1836
1837 /* Offset from the frame pointer to the first local variable slot to
1838 be allocated. */
1839 #define STARTING_FRAME_OFFSET 0
1840
1841 /* If we generate an insn to push BYTES bytes,
1842 this says how many the stack pointer really advances by. */
1843 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1844 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1845 do correct alignment. */
1846 #if 0
1847 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1848 #endif
1849
1850 /* Offset of first parameter from the argument pointer register value. */
1851 #define FIRST_PARM_OFFSET(FNDECL) 0
1852
1853 /* Value is the number of byte of arguments automatically
1854 popped when returning from a subroutine call.
1855 FUNDECL is the declaration node of the function (as a tree),
1856 FUNTYPE is the data type of the function (as a tree),
1857 or for a library call it is an identifier node for the subroutine name.
1858 SIZE is the number of bytes of arguments passed on the stack.
1859
1860 On the SH, the caller does not pop any of its arguments that were passed
1861 on the stack. */
1862 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1863
1864 /* Value is the number of bytes of arguments automatically popped when
1865 calling a subroutine.
1866 CUM is the accumulated argument list.
1867
1868 On SHcompact, the call trampoline pops arguments off the stack. */
1869 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1870
1871 /* Some subroutine macros specific to this machine. */
1872
1873 #define BASE_RETURN_VALUE_REG(MODE) \
1874 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1875 ? FIRST_FP_RET_REG \
1876 : TARGET_FPU_ANY && (MODE) == SCmode \
1877 ? FIRST_FP_RET_REG \
1878 : (TARGET_FPU_DOUBLE \
1879 && ((MODE) == DFmode || (MODE) == SFmode \
1880 || (MODE) == DCmode || (MODE) == SCmode )) \
1881 ? FIRST_FP_RET_REG \
1882 : FIRST_RET_REG)
1883
1884 #define BASE_ARG_REG(MODE) \
1885 ((TARGET_SH2E && ((MODE) == SFmode)) \
1886 ? FIRST_FP_PARM_REG \
1887 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1888 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1889 ? FIRST_FP_PARM_REG \
1890 : FIRST_PARM_REG)
1891
1892 /* Define how to find the value returned by a function.
1893 VALTYPE is the data type of the value (as a tree).
1894 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1895 otherwise, FUNC is 0.
1896 For the SH, this is like LIBCALL_VALUE, except that we must change the
1897 mode like PROMOTE_MODE does.
1898 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1899 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1900
1901 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1902 gen_rtx_REG ( \
1903 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1904 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1905 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1906 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1907 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1908 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1909 || TREE_CODE (VALTYPE) == REAL_TYPE \
1910 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1911 && sh_promote_prototypes (VALTYPE) \
1912 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1913 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1914
1915 /* Define how to find the value returned by a library function
1916 assuming the value has mode MODE. */
1917 #define LIBCALL_VALUE(MODE) \
1918 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1919
1920 /* 1 if N is a possible register number for a function value. */
1921 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1922 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1923 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1924
1925 /* 1 if N is a possible register number for function argument passing. */
1926 /* ??? There are some callers that pass REGNO as int, and others that pass
1927 it as unsigned. We get warnings unless we do casts everywhere. */
1928 #define FUNCTION_ARG_REGNO_P(REGNO) \
1929 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1930 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1931 || (TARGET_FPU_ANY \
1932 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1933 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1934 + NPARM_REGS (SFmode))))
1935 \f
1936 /* Define a data type for recording info about an argument list
1937 during the scan of that argument list. This data type should
1938 hold all necessary information about the function itself
1939 and about the args processed so far, enough to enable macros
1940 such as FUNCTION_ARG to determine where the next arg should go.
1941
1942 On SH, this is a single integer, which is a number of words
1943 of arguments scanned so far (including the invisible argument,
1944 if any, which holds the structure-value-address).
1945 Thus NARGREGS or more means all following args should go on the stack. */
1946
1947 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1948 struct sh_args {
1949 int arg_count[2];
1950 int force_mem;
1951 /* Nonzero if a prototype is available for the function. */
1952 int prototype_p;
1953 /* The number of an odd floating-point register, that should be used
1954 for the next argument of type float. */
1955 int free_single_fp_reg;
1956 /* Whether we're processing an outgoing function call. */
1957 int outgoing;
1958 /* The number of general-purpose registers that should have been
1959 used to pass partial arguments, that are passed totally on the
1960 stack. On SHcompact, a call trampoline will pop them off the
1961 stack before calling the actual function, and, if the called
1962 function is implemented in SHcompact mode, the incoming arguments
1963 decoder will push such arguments back onto the stack. For
1964 incoming arguments, STACK_REGS also takes into account other
1965 arguments passed by reference, that the decoder will also push
1966 onto the stack. */
1967 int stack_regs;
1968 /* The number of general-purpose registers that should have been
1969 used to pass arguments, if the arguments didn't have to be passed
1970 by reference. */
1971 int byref_regs;
1972 /* Set as by shcompact_byref if the current argument is to be passed
1973 by reference. */
1974 int byref;
1975
1976 /* call_cookie is a bitmask used by call expanders, as well as
1977 function prologue and epilogues, to allow SHcompact to comply
1978 with the SH5 32-bit ABI, that requires 64-bit registers to be
1979 used even though only the lower 32-bit half is visible in
1980 SHcompact mode. The strategy is to call SHmedia trampolines.
1981
1982 The alternatives for each of the argument-passing registers are
1983 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1984 contents from the address in it; (d) add 8 to it, storing the
1985 result in the next register, then (c); (e) copy it from some
1986 floating-point register,
1987
1988 Regarding copies from floating-point registers, r2 may only be
1989 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1990 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1991 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1992 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1993 dr10.
1994
1995 The bit mask is structured as follows:
1996
1997 - 1 bit to tell whether to set up a return trampoline.
1998
1999 - 3 bits to count the number consecutive registers to pop off the
2000 stack.
2001
2002 - 4 bits for each of r9, r8, r7 and r6.
2003
2004 - 3 bits for each of r5, r4, r3 and r2.
2005
2006 - 3 bits set to 0 (the most significant ones)
2007
2008 3 2 1 0
2009 1098 7654 3210 9876 5432 1098 7654 3210
2010 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
2011 2223 3344 4555 6666 7777 8888 9999 SSS-
2012
2013 - If F is set, the register must be copied from an FP register,
2014 whose number is encoded in the remaining bits.
2015
2016 - Else, if L is set, the register must be loaded from the address
2017 contained in it. If the P bit is *not* set, the address of the
2018 following dword should be computed first, and stored in the
2019 following register.
2020
2021 - Else, if P is set, the register alone should be popped off the
2022 stack.
2023
2024 - After all this processing, the number of registers represented
2025 in SSS will be popped off the stack. This is an optimization
2026 for pushing/popping consecutive registers, typically used for
2027 varargs and large arguments partially passed in registers.
2028
2029 - If T is set, a return trampoline will be set up for 64-bit
2030 return values to be split into 2 32-bit registers. */
2031 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
2032 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
2033 #define CALL_COOKIE_STACKSEQ_SHIFT 1
2034 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
2035 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
2036 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
2037 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
2038 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
2039 #define CALL_COOKIE_INT_REG(REG, VAL) \
2040 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
2041 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
2042 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
2043 long call_cookie;
2044
2045 /* This is set to nonzero when the call in question must use the Renesas ABI,
2046 even without the -mrenesas option. */
2047 int renesas_abi;
2048 };
2049
2050 #define CUMULATIVE_ARGS struct sh_args
2051
2052 #define GET_SH_ARG_CLASS(MODE) \
2053 ((TARGET_FPU_ANY && (MODE) == SFmode) \
2054 ? SH_ARG_FLOAT \
2055 /* There's no mention of complex float types in the SH5 ABI, so we
2056 should presumably handle them as aggregate types. */ \
2057 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
2058 ? SH_ARG_INT \
2059 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2060 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
2061 ? SH_ARG_FLOAT : SH_ARG_INT)
2062
2063 #define ROUND_ADVANCE(SIZE) \
2064 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2065
2066 /* Round a register number up to a proper boundary for an arg of mode
2067 MODE.
2068
2069 The SH doesn't care about double alignment, so we only
2070 round doubles to even regs when asked to explicitly. */
2071
2072 #define ROUND_REG(CUM, MODE) \
2073 (((TARGET_ALIGN_DOUBLE \
2074 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
2075 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
2076 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
2077 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
2078 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
2079 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
2080
2081 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2082 for a call to a function whose data type is FNTYPE.
2083 For a library call, FNTYPE is 0.
2084
2085 On SH, the offset always starts at 0: the first parm reg is always
2086 the same reg for a given argument class.
2087
2088 For TARGET_HITACHI, the structure value pointer is passed in memory. */
2089
2090 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
2091 do { \
2092 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
2093 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
2094 (CUM).renesas_abi = sh_attr_renesas_p (FNTYPE) ? 1 : 0; \
2095 (CUM).force_mem \
2096 = ((TARGET_HITACHI || (CUM).renesas_abi) && (FNTYPE) \
2097 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
2098 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
2099 (CUM).arg_count[(int) SH_ARG_INT] \
2100 = (TARGET_SH5 && (FNTYPE) \
2101 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
2102 (CUM).free_single_fp_reg = 0; \
2103 (CUM).outgoing = 1; \
2104 (CUM).stack_regs = 0; \
2105 (CUM).byref_regs = 0; \
2106 (CUM).byref = 0; \
2107 (CUM).call_cookie \
2108 = (CALL_COOKIE_RET_TRAMP \
2109 (TARGET_SHCOMPACT && (FNTYPE) \
2110 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
2111 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
2112 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
2113 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
2114 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
2115 (FNTYPE))) \
2116 == FIRST_RET_REG))); \
2117 } while (0)
2118
2119 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
2120 do { \
2121 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0, 0); \
2122 (CUM).call_cookie \
2123 = (CALL_COOKIE_RET_TRAMP \
2124 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
2125 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
2126 } while (0)
2127
2128 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
2129 do { \
2130 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0, 0); \
2131 (CUM).outgoing = 0; \
2132 } while (0)
2133
2134 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2135 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
2136 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2137 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
2138
2139 /* Return boolean indicating arg of mode MODE will be passed in a reg.
2140 This macro is only used in this file. */
2141
2142 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2143 (((TYPE) == 0 \
2144 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2145 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2146 || ! (AGGREGATE_TYPE_P (TYPE) \
2147 || (!TARGET_FPU_ANY \
2148 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2149 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2150 && ! (CUM).force_mem \
2151 && (TARGET_SH2E \
2152 ? ((MODE) == BLKmode \
2153 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2154 + int_size_in_bytes (TYPE)) \
2155 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2156 : ((ROUND_REG((CUM), (MODE)) \
2157 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2158 <= NPARM_REGS (MODE))) \
2159 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2160
2161 /* By accident we got stuck with passing SCmode on SH4 little endian
2162 in two registers that are nominally successive - which is different from
2163 two single SFmode values, where we take endianness translation into
2164 account. That does not work at all if an odd number of registers is
2165 already in use, so that got fixed, but library functions are still more
2166 likely to use complex numbers without mixing them with SFmode arguments
2167 (which in C would have to be structures), so for the sake of ABI
2168 compatibility the way SCmode values are passed when an even number of
2169 FP registers is in use remains different from a pair of SFmode values for
2170 now.
2171 I.e.:
2172 foo (double); a: fr5,fr4
2173 foo (float a, float b); a: fr5 b: fr4
2174 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2175 this should be the other way round...
2176 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2177 #define FUNCTION_ARG_SCmode_WART 1
2178
2179 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2180 register in SHcompact mode, it must be padded in the most
2181 significant end. This means that passing it by reference wouldn't
2182 pad properly on a big-endian machine. In this particular case, we
2183 pass this argument on the stack, in a way that the call trampoline
2184 will load its value into the appropriate register. */
2185 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2186 ((MODE) == BLKmode \
2187 && TARGET_SHCOMPACT \
2188 && ! TARGET_LITTLE_ENDIAN \
2189 && int_size_in_bytes (TYPE) > 4 \
2190 && int_size_in_bytes (TYPE) < 8)
2191
2192 /* Minimum alignment for an argument to be passed by callee-copy
2193 reference. We need such arguments to be aligned to 8 byte
2194 boundaries, because they'll be loaded using quad loads. */
2195 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2196
2197 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
2198 ((CUM).outgoing \
2199 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
2200 : GET_MODE_ALIGNMENT (MODE)) \
2201 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
2202
2203 /* The SH5 ABI requires floating-point arguments to be passed to
2204 functions without a prototype in both an FP register and a regular
2205 register or the stack. When passing the argument in both FP and
2206 general-purpose registers, list the FP register first. */
2207 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2208 (gen_rtx_PARALLEL \
2209 ((MODE), \
2210 gen_rtvec (2, \
2211 gen_rtx_EXPR_LIST \
2212 (VOIDmode, \
2213 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2214 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2215 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2216 : NULL_RTX), \
2217 const0_rtx), \
2218 gen_rtx_EXPR_LIST \
2219 (VOIDmode, \
2220 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2221 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2222 + (CUM).arg_count[(int) SH_ARG_INT]) \
2223 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2224 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2225 const0_rtx))))
2226
2227 /* The SH5 ABI requires regular registers or stack slots to be
2228 reserved for floating-point arguments. Registers are taken care of
2229 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2230 Unfortunately, there's no way to just reserve a stack slot, so
2231 we'll end up needlessly storing a copy of the argument in the
2232 stack. For incoming arguments, however, the PARALLEL will be
2233 optimized to the register-only form, and the value in the stack
2234 slot won't be used at all. */
2235 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2236 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2237 ? gen_rtx_REG ((MODE), (REG)) \
2238 : gen_rtx_PARALLEL ((MODE), \
2239 gen_rtvec (2, \
2240 gen_rtx_EXPR_LIST \
2241 (VOIDmode, NULL_RTX, \
2242 const0_rtx), \
2243 gen_rtx_EXPR_LIST \
2244 (VOIDmode, gen_rtx_REG ((MODE), \
2245 (REG)), \
2246 const0_rtx))))
2247
2248 /* For an arg passed partly in registers and partly in memory,
2249 this is the number of registers used.
2250 For args passed entirely in registers or entirely in memory, zero.
2251
2252 We sometimes split args. */
2253
2254 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2255 ((! TARGET_SH5 \
2256 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2257 && ! (TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2258 && (ROUND_REG ((CUM), (MODE)) \
2259 + ((MODE) != BLKmode \
2260 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2261 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2262 > NPARM_REGS (MODE))) \
2263 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2264 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2265 && ! TARGET_SHCOMPACT) \
2266 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2267 : 0)
2268
2269 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2270 (TARGET_SH5 \
2271 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2272 || (MODE) == DCmode) \
2273 && ((CUM).arg_count[(int) SH_ARG_INT] \
2274 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2275
2276 /* Perform any needed actions needed for a function that is receiving a
2277 variable number of arguments. */
2278
2279 /* Implement `va_start' for varargs and stdarg. */
2280 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2281 sh_va_start (valist, nextarg)
2282
2283 /* Call the function profiler with a given profile label.
2284 We use two .aligns, so as to make sure that both the .long is aligned
2285 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2286 from the trapa instruction. */
2287
2288 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2289 { \
2290 fprintf((STREAM), "\t.align\t2\n"); \
2291 fprintf((STREAM), "\ttrapa\t#33\n"); \
2292 fprintf((STREAM), "\t.align\t2\n"); \
2293 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2294 }
2295
2296 /* Define this macro if the code for function profiling should come
2297 before the function prologue. Normally, the profiling code comes
2298 after. */
2299
2300 #define PROFILE_BEFORE_PROLOGUE
2301
2302 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2303 the stack pointer does not matter. The value is tested only in
2304 functions that have frame pointers.
2305 No definition is equivalent to always zero. */
2306
2307 #define EXIT_IGNORE_STACK 1
2308
2309 /*
2310 On the SH, the trampoline looks like
2311 2 0002 D202 mov.l l2,r2
2312 1 0000 D301 mov.l l1,r3
2313 3 0004 422B jmp @r2
2314 4 0006 0009 nop
2315 5 0008 00000000 l1: .long area
2316 6 000c 00000000 l2: .long function */
2317
2318 /* Length in units of the trampoline for entering a nested function. */
2319 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2320
2321 /* Alignment required for a trampoline in bits . */
2322 #define TRAMPOLINE_ALIGNMENT \
2323 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2324 : TARGET_SHMEDIA ? 256 : 64)
2325
2326 /* Emit RTL insns to initialize the variable parts of a trampoline.
2327 FNADDR is an RTX for the address of the function's pure code.
2328 CXT is an RTX for the static chain value for the function. */
2329
2330 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2331 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2332
2333 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2334
2335 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2336 { \
2337 if (TARGET_SHMEDIA) \
2338 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2339 gen_reg_rtx (Pmode), 0, \
2340 OPTAB_LIB_WIDEN); \
2341 } while (0)
2342
2343 /* A C expression whose value is RTL representing the value of the return
2344 address for the frame COUNT steps up from the current frame.
2345 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2346 can ignore COUNT. */
2347
2348 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2349 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2350
2351 /* A C expression whose value is RTL representing the location of the
2352 incoming return address at the beginning of any function, before the
2353 prologue. This RTL is either a REG, indicating that the return
2354 value is saved in REG, or a MEM representing a location in
2355 the stack. */
2356 #define INCOMING_RETURN_ADDR_RTX \
2357 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2358 \f
2359 /* Addressing modes, and classification of registers for them. */
2360 #define HAVE_POST_INCREMENT TARGET_SH1
2361 #define HAVE_PRE_DECREMENT TARGET_SH1
2362
2363 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2364 ? 0 : TARGET_SH1)
2365 #define USE_LOAD_PRE_DECREMENT(mode) 0
2366 #define USE_STORE_POST_INCREMENT(mode) 0
2367 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2368 ? 0 : TARGET_SH1)
2369
2370 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2371 < (TARGET_SMALLCODE ? 2 : \
2372 ((ALIGN >= 32) ? 16 : 2)))
2373
2374 /* Macros to check register numbers against specific register classes. */
2375
2376 /* These assume that REGNO is a hard or pseudo reg number.
2377 They give nonzero only if REGNO is a hard reg of the suitable class
2378 or a pseudo reg currently allocated to a suitable hard reg.
2379 Since they use reg_renumber, they are safe only once reg_renumber
2380 has been allocated, which happens in local-alloc.c. */
2381
2382 #define REGNO_OK_FOR_BASE_P(REGNO) \
2383 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2384 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2385 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2386 (TARGET_SHMEDIA \
2387 ? (GENERAL_REGISTER_P (REGNO) \
2388 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2389 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2390
2391 /* Maximum number of registers that can appear in a valid memory
2392 address. */
2393
2394 #define MAX_REGS_PER_ADDRESS 2
2395
2396 /* Recognize any constant value that is a valid address. */
2397
2398 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2399
2400 /* Nonzero if the constant value X is a legitimate general operand. */
2401
2402 #define LEGITIMATE_CONSTANT_P(X) \
2403 (TARGET_SHMEDIA \
2404 ? ((GET_MODE (X) != DFmode \
2405 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2406 || (X) == CONST0_RTX (GET_MODE (X)) \
2407 || ! TARGET_SHMEDIA_FPU \
2408 || TARGET_SHMEDIA64) \
2409 : (GET_CODE (X) != CONST_DOUBLE \
2410 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2411 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2412
2413 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2414 and check its validity for a certain class.
2415 We have two alternate definitions for each of them.
2416 The usual definition accepts all pseudo regs; the other rejects
2417 them unless they have been allocated suitable hard regs.
2418 The symbol REG_OK_STRICT causes the latter definition to be used. */
2419
2420 #ifndef REG_OK_STRICT
2421
2422 /* Nonzero if X is a hard reg that can be used as a base reg
2423 or if it is a pseudo reg. */
2424 #define REG_OK_FOR_BASE_P(X) \
2425 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2426
2427 /* Nonzero if X is a hard reg that can be used as an index
2428 or if it is a pseudo reg. */
2429 #define REG_OK_FOR_INDEX_P(X) \
2430 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2431 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2432
2433 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2434 or if X is a pseudo reg. */
2435 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2436 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2437 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2438
2439 #else
2440
2441 /* Nonzero if X is a hard reg that can be used as a base reg. */
2442 #define REG_OK_FOR_BASE_P(X) \
2443 REGNO_OK_FOR_BASE_P (REGNO (X))
2444
2445 /* Nonzero if X is a hard reg that can be used as an index. */
2446 #define REG_OK_FOR_INDEX_P(X) \
2447 REGNO_OK_FOR_INDEX_P (REGNO (X))
2448
2449 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2450 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2451 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2452
2453 #endif
2454
2455 /* The 'Q' constraint is a pc relative load operand. */
2456 #define EXTRA_CONSTRAINT_Q(OP) \
2457 (GET_CODE (OP) == MEM \
2458 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2459 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2460 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2461 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2462 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2463
2464 /* Extra address constraints. */
2465 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2466
2467 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2468 operand is not SCRATCH (i.e. REG) then R0 is probably being
2469 used, hence mova is being used, hence do not select this pattern */
2470 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2471 #define EXTRA_CONSTRAINT_B(OP, STR) \
2472 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2473 : 0)
2474
2475 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2476 #define EXTRA_CONSTRAINT_C16(OP) \
2477 (GET_CODE (OP) == CONST \
2478 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2479 && GET_MODE (XEXP ((OP), 0)) == DImode \
2480 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2481 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2482 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2483 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2484 && (MOVI_SHORI_BASE_OPERAND_P \
2485 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2486 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2487 1)) == CONST_INT)))
2488
2489 /* Check whether OP is a datalabel unspec. */
2490 #define DATALABEL_REF_NO_CONST_P(OP) \
2491 (GET_CODE (OP) == UNSPEC \
2492 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2493 && XVECLEN ((OP), 0) == 1 \
2494 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2495 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2496
2497 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2498 CONST. */
2499 #define DATALABEL_REF_P(OP) \
2500 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2501 || DATALABEL_REF_NO_CONST_P (OP))
2502
2503 #define GOT_ENTRY_P(OP) \
2504 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2505 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2506
2507 #define GOTPLT_ENTRY_P(OP) \
2508 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2509 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2510
2511 #define UNSPEC_GOTOFF_P(OP) \
2512 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2513
2514 #define GOTOFF_P(OP) \
2515 (GET_CODE (OP) == CONST \
2516 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2517 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2518 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2519 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2520
2521 #define PIC_ADDR_P(OP) \
2522 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2523 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2524
2525 #define PIC_OFFSET_P(OP) \
2526 (PIC_ADDR_P (OP) \
2527 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2528 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2529
2530 #define PIC_DIRECT_ADDR_P(OP) \
2531 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2532
2533 #define NON_PIC_REFERENCE_P(OP) \
2534 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2535 || DATALABEL_REF_P (OP) \
2536 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2537 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2538 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2539 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2540
2541 #define PIC_REFERENCE_P(OP) \
2542 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2543 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2544
2545 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2546 (flag_pic \
2547 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2548 || PIC_OFFSET_P (OP)) \
2549 : NON_PIC_REFERENCE_P (OP))
2550
2551 /* The `Csy' constraint is a label or a symbol. */
2552 #define EXTRA_CONSTRAINT_Csy(OP) \
2553 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2554
2555 /* A zero in any shape or form. */
2556 #define EXTRA_CONSTRAINT_Z(OP) \
2557 ((OP) == CONST0_RTX (GET_MODE (OP)))
2558
2559 /* Any vector constant we can handle. */
2560 #define EXTRA_CONSTRAINT_W(OP) \
2561 (GET_CODE (OP) == CONST_VECTOR \
2562 && (sh_rep_vec ((OP), VOIDmode) \
2563 || (HOST_BITS_PER_WIDE_INT >= 64 \
2564 ? sh_const_vec ((OP), VOIDmode) \
2565 : sh_1el_vec ((OP), VOIDmode))))
2566
2567 /* A non-explicit constant that can be loaded directly into a general purpose
2568 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2569 #define EXTRA_CONSTRAINT_Cpg(OP) \
2570 (CONSTANT_P (OP) \
2571 && GET_CODE (OP) != CONST_INT \
2572 && GET_CODE (OP) != CONST_DOUBLE \
2573 && (!flag_pic \
2574 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2575 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2576 && GET_CODE (OP) != LABEL_REF)))
2577 #define EXTRA_CONSTRAINT_C(OP, STR) \
2578 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2579 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2580 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2581 : 0)
2582
2583 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2584 #define EXTRA_CONSTRAINT_Sr0(OP) \
2585 (memory_operand((OP), GET_MODE (OP)) \
2586 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2587 #define EXTRA_CONSTRAINT_Sua(OP) \
2588 (memory_operand((OP), GET_MODE (OP)) \
2589 && GET_CODE (XEXP (OP, 0)) != PLUS)
2590 #define EXTRA_CONSTRAINT_S(OP, STR) \
2591 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2592 : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
2593 : 0)
2594
2595 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2596 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2597 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2598 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2599 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2600 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2601 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2602 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2603 : 0)
2604 \f
2605 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2606 that is a valid memory address for an instruction.
2607 The MODE argument is the machine mode for the MEM expression
2608 that wants to use this address. */
2609
2610 #define MODE_DISP_OK_4(X,MODE) \
2611 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2612 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2613
2614 #define MODE_DISP_OK_8(X,MODE) \
2615 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2616 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2617
2618 #undef MODE_DISP_OK_4
2619 #define MODE_DISP_OK_4(X,MODE) \
2620 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2621 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2622 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2623 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2624
2625 #undef MODE_DISP_OK_8
2626 #define MODE_DISP_OK_8(X,MODE) \
2627 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2628 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2629 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2630 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2631
2632 #define BASE_REGISTER_RTX_P(X) \
2633 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2634 || (GET_CODE (X) == SUBREG \
2635 && GET_CODE (SUBREG_REG (X)) == REG \
2636 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2637
2638 /* Since this must be r0, which is a single register class, we must check
2639 SUBREGs more carefully, to be sure that we don't accept one that extends
2640 outside the class. */
2641 #define INDEX_REGISTER_RTX_P(X) \
2642 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2643 || (GET_CODE (X) == SUBREG \
2644 && GET_CODE (SUBREG_REG (X)) == REG \
2645 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2646
2647 /* Jump to LABEL if X is a valid address RTX. This must also take
2648 REG_OK_STRICT into account when deciding about valid registers, but it uses
2649 the above macros so we are in luck.
2650
2651 Allow REG
2652 REG+disp
2653 REG+r0
2654 REG++
2655 --REG */
2656
2657 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2658 into the FRx registers. We implement this by setting the maximum offset
2659 to zero when the value is SFmode. This also restricts loading of SFmode
2660 values into the integer registers, but that can't be helped. */
2661
2662 /* The SH allows a displacement in a QI or HI amode, but only when the
2663 other operand is R0. GCC doesn't handle this very well, so we forgo
2664 all of that.
2665
2666 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2667 DI can be any number 0..60. */
2668
2669 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2670 do { \
2671 if (GET_CODE (OP) == CONST_INT) \
2672 { \
2673 if (TARGET_SHMEDIA) \
2674 { \
2675 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2676 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2677 && INTVAL (OP) >= -512 * MODE_SIZE \
2678 && INTVAL (OP) < 512 * MODE_SIZE) \
2679 goto LABEL; \
2680 else \
2681 break; \
2682 } \
2683 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2684 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2685 } \
2686 } while(0)
2687
2688 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2689 { \
2690 if (BASE_REGISTER_RTX_P (X)) \
2691 goto LABEL; \
2692 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2693 && ! TARGET_SHMEDIA \
2694 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2695 goto LABEL; \
2696 else if (GET_CODE (X) == PLUS \
2697 && ((MODE) != PSImode || reload_completed)) \
2698 { \
2699 rtx xop0 = XEXP ((X), 0); \
2700 rtx xop1 = XEXP ((X), 1); \
2701 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2702 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2703 if (GET_MODE_SIZE (MODE) <= 4 \
2704 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2705 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && MODE == DFmode)) \
2706 { \
2707 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2708 goto LABEL; \
2709 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2710 goto LABEL; \
2711 } \
2712 } \
2713 }
2714 \f
2715 /* Try machine-dependent ways of modifying an illegitimate address
2716 to be legitimate. If we find one, return the new, valid address.
2717 This macro is used in only one place: `memory_address' in explow.c.
2718
2719 OLDX is the address as it was before break_out_memory_refs was called.
2720 In some cases it is useful to look at this to decide what needs to be done.
2721
2722 MODE and WIN are passed so that this macro can use
2723 GO_IF_LEGITIMATE_ADDRESS.
2724
2725 It is always safe for this macro to do nothing. It exists to recognize
2726 opportunities to optimize the output.
2727
2728 For the SH, if X is almost suitable for indexing, but the offset is
2729 out of range, convert it into a normal form so that cse has a chance
2730 of reducing the number of address registers used. */
2731
2732 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2733 { \
2734 if (flag_pic) \
2735 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2736 if (GET_CODE (X) == PLUS \
2737 && (GET_MODE_SIZE (MODE) == 4 \
2738 || GET_MODE_SIZE (MODE) == 8) \
2739 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2740 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2741 && ! TARGET_SHMEDIA \
2742 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2743 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2744 { \
2745 rtx index_rtx = XEXP ((X), 1); \
2746 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2747 rtx sum; \
2748 \
2749 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2750 /* On rare occasions, we might get an unaligned pointer \
2751 that is indexed in a way to give an aligned address. \
2752 Therefore, keep the lower two bits in offset_base. */ \
2753 /* Instead of offset_base 128..131 use 124..127, so that \
2754 simple add suffices. */ \
2755 if (offset > 127) \
2756 { \
2757 offset_base = ((offset + 4) & ~60) - 4; \
2758 } \
2759 else \
2760 offset_base = offset & ~60; \
2761 /* Sometimes the normal form does not suit DImode. We \
2762 could avoid that by using smaller ranges, but that \
2763 would give less optimized code when SImode is \
2764 prevalent. */ \
2765 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2766 { \
2767 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2768 GEN_INT (offset_base), NULL_RTX, 0, \
2769 OPTAB_LIB_WIDEN); \
2770 \
2771 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2772 goto WIN; \
2773 } \
2774 } \
2775 }
2776
2777 /* A C compound statement that attempts to replace X, which is an address
2778 that needs reloading, with a valid memory address for an operand of
2779 mode MODE. WIN is a C statement label elsewhere in the code.
2780
2781 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2782 of the address. That will allow inheritance of the address reloads. */
2783
2784 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2785 { \
2786 if (GET_CODE (X) == PLUS \
2787 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2788 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2789 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2790 && ! TARGET_SHMEDIA \
2791 && ! (TARGET_SH4 && (MODE) == DFmode) \
2792 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2793 { \
2794 rtx index_rtx = XEXP (X, 1); \
2795 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2796 rtx sum; \
2797 \
2798 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2799 { \
2800 push_reload (X, NULL_RTX, &X, NULL, \
2801 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2802 (TYPE)); \
2803 goto WIN; \
2804 } \
2805 if (TARGET_SH2E && MODE == SFmode) \
2806 { \
2807 X = copy_rtx (X); \
2808 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2809 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2810 (TYPE)); \
2811 goto WIN; \
2812 } \
2813 /* Instead of offset_base 128..131 use 124..127, so that \
2814 simple add suffices. */ \
2815 if (offset > 127) \
2816 { \
2817 offset_base = ((offset + 4) & ~60) - 4; \
2818 } \
2819 else \
2820 offset_base = offset & ~60; \
2821 /* Sometimes the normal form does not suit DImode. We \
2822 could avoid that by using smaller ranges, but that \
2823 would give less optimized code when SImode is \
2824 prevalent. */ \
2825 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2826 { \
2827 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2828 GEN_INT (offset_base)); \
2829 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2830 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2831 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2832 (TYPE)); \
2833 goto WIN; \
2834 } \
2835 } \
2836 /* We must re-recognize what we created before. */ \
2837 else if (GET_CODE (X) == PLUS \
2838 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2839 && GET_CODE (XEXP (X, 0)) == PLUS \
2840 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2841 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2842 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2843 && ! TARGET_SHMEDIA \
2844 && ! (TARGET_SH2E && MODE == SFmode)) \
2845 { \
2846 /* Because this address is so complex, we know it must have \
2847 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2848 it is already unshared, and needs no further unsharing. */ \
2849 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2850 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2851 goto WIN; \
2852 } \
2853 }
2854
2855 /* Go to LABEL if ADDR (a legitimate address expression)
2856 has an effect that depends on the machine mode it is used for.
2857
2858 ??? Strictly speaking, we should also include all indexed addressing,
2859 because the index scale factor is the length of the operand.
2860 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2861 high if we did that. So we rely on reload to fix things up. */
2862
2863 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2864 { \
2865 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2866 goto LABEL; \
2867 }
2868 \f
2869 /* Specify the machine mode that this machine uses
2870 for the index in the tablejump instruction. */
2871 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2872
2873 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2874 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2875 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2876 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2877 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2878 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2879 : SImode)
2880
2881 /* Define as C expression which evaluates to nonzero if the tablejump
2882 instruction expects the table to contain offsets from the address of the
2883 table.
2884 Do not define this if the table should contain absolute addresses. */
2885 #define CASE_VECTOR_PC_RELATIVE 1
2886
2887 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2888 #define FLOAT_TYPE_SIZE 32
2889
2890 /* Since the SH2e has only `float' support, it is desirable to make all
2891 floating point types equivalent to `float'. */
2892 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2893
2894 /* 'char' is signed by default. */
2895 #define DEFAULT_SIGNED_CHAR 1
2896
2897 /* The type of size_t unsigned int. */
2898 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2899
2900 #undef PTRDIFF_TYPE
2901 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2902
2903 #define WCHAR_TYPE "short unsigned int"
2904 #define WCHAR_TYPE_SIZE 16
2905
2906 #define SH_ELF_WCHAR_TYPE "long int"
2907
2908 /* Max number of bytes we can move from memory to memory
2909 in one reasonably fast instruction. */
2910 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2911
2912 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2913 MOVE_MAX is not a compile-time constant. */
2914 #define MAX_MOVE_MAX 8
2915
2916 /* Max number of bytes we want move_by_pieces to be able to copy
2917 efficiently. */
2918 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2919
2920 /* Define if operations between registers always perform the operation
2921 on the full register even if a narrower mode is specified. */
2922 #define WORD_REGISTER_OPERATIONS
2923
2924 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2925 will either zero-extend or sign-extend. The value of this macro should
2926 be the code that says which one of the two operations is implicitly
2927 done, NIL if none. */
2928 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2929 /* FP registers can load SImode values, but don't implicitly sign-extend
2930 them to DImode. */
2931 #define LOAD_EXTEND_OP(MODE) \
2932 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2933 : (MODE) != SImode ? SIGN_EXTEND : NIL)
2934
2935 /* Define if loading short immediate values into registers sign extends. */
2936 #define SHORT_IMMEDIATES_SIGN_EXTEND
2937
2938 /* Nonzero if access to memory by bytes is no faster than for words. */
2939 #define SLOW_BYTE_ACCESS 1
2940
2941 /* Immediate shift counts are truncated by the output routines (or was it
2942 the assembler?). Shift counts in a register are truncated by SH. Note
2943 that the native compiler puts too large (> 32) immediate shift counts
2944 into a register and shifts by the register, letting the SH decide what
2945 to do instead of doing that itself. */
2946 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2947 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2948 expects - the sign bit is significant - so it appears that we need to
2949 leave this zero for correct SH3 code. */
2950 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2951
2952 /* All integers have the same format so truncation is easy. */
2953 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2954
2955 /* Define this if addresses of constant functions
2956 shouldn't be put through pseudo regs where they can be cse'd.
2957 Desirable on machines where ordinary constants are expensive
2958 but a CALL with constant address is cheap. */
2959 /*#define NO_FUNCTION_CSE 1*/
2960
2961 /* The machine modes of pointers and functions. */
2962 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2963 #define FUNCTION_MODE Pmode
2964
2965 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2966 are actually function calls with some special constraints on arguments
2967 and register usage.
2968
2969 These macros tell reorg that the references to arguments and
2970 register clobbers for insns of type sfunc do not appear to happen
2971 until after the millicode call. This allows reorg to put insns
2972 which set the argument registers into the delay slot of the millicode
2973 call -- thus they act more like traditional CALL_INSNs.
2974
2975 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2976 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2977 in particular. */
2978
2979 #define INSN_SETS_ARE_DELAYED(X) \
2980 ((GET_CODE (X) == INSN \
2981 && GET_CODE (PATTERN (X)) != SEQUENCE \
2982 && GET_CODE (PATTERN (X)) != USE \
2983 && GET_CODE (PATTERN (X)) != CLOBBER \
2984 && get_attr_is_sfunc (X)))
2985
2986 #define INSN_REFERENCES_ARE_DELAYED(X) \
2987 ((GET_CODE (X) == INSN \
2988 && GET_CODE (PATTERN (X)) != SEQUENCE \
2989 && GET_CODE (PATTERN (X)) != USE \
2990 && GET_CODE (PATTERN (X)) != CLOBBER \
2991 && get_attr_is_sfunc (X)))
2992
2993 \f
2994 /* Position Independent Code. */
2995
2996 /* We can't directly access anything that contains a symbol,
2997 nor can we indirect via the constant pool. */
2998 #define LEGITIMATE_PIC_OPERAND_P(X) \
2999 ((! nonpic_symbol_mentioned_p (X) \
3000 && (GET_CODE (X) != SYMBOL_REF \
3001 || ! CONSTANT_POOL_ADDRESS_P (X) \
3002 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
3003 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
3004
3005 #define SYMBOLIC_CONST_P(X) \
3006 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
3007 && nonpic_symbol_mentioned_p (X))
3008 \f
3009 /* Compute extra cost of moving data between one register class
3010 and another. */
3011
3012 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
3013 uses this information. Hence, the general register <-> floating point
3014 register information here is not used for SFmode. */
3015
3016 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
3017 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
3018 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
3019
3020 #define REGCLASS_HAS_FP_REG(CLASS) \
3021 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
3022 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
3023
3024 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
3025 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
3026
3027 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
3028 would be so that people with slow memory systems could generate
3029 different code that does fewer memory accesses. */
3030
3031 /* A C expression for the cost of a branch instruction. A value of 1
3032 is the default; other values are interpreted relative to that.
3033 The SH1 does not have delay slots, hence we get a pipeline stall
3034 at every branch. The SH4 is superscalar, so the single delay slot
3035 is not sufficient to keep both pipelines filled. */
3036 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
3037 \f
3038 /* Assembler output control. */
3039
3040 /* A C string constant describing how to begin a comment in the target
3041 assembler language. The compiler assumes that the comment will end at
3042 the end of the line. */
3043 #define ASM_COMMENT_START "!"
3044
3045 #define ASM_APP_ON ""
3046 #define ASM_APP_OFF ""
3047 #define FILE_ASM_OP "\t.file\n"
3048 #define SET_ASM_OP "\t.set\t"
3049
3050 /* How to change between sections. */
3051
3052 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
3053 #define DATA_SECTION_ASM_OP "\t.data"
3054
3055 #if defined CRT_BEGIN || defined CRT_END
3056 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
3057 # undef TEXT_SECTION_ASM_OP
3058 # if __SHMEDIA__ == 1 && __SH5__ == 32
3059 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
3060 # else
3061 # define TEXT_SECTION_ASM_OP "\t.text"
3062 # endif
3063 #endif
3064
3065
3066 /* If defined, a C expression whose value is a string containing the
3067 assembler operation to identify the following data as
3068 uninitialized global data. If not defined, and neither
3069 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
3070 uninitialized global data will be output in the data section if
3071 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
3072 used. */
3073 #ifndef BSS_SECTION_ASM_OP
3074 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
3075 #endif
3076
3077 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
3078 separate, explicit argument. If you define this macro, it is used
3079 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
3080 handling the required alignment of the variable. The alignment is
3081 specified as the number of bits.
3082
3083 Try to use function `asm_output_aligned_bss' defined in file
3084 `varasm.c' when defining this macro. */
3085 #ifndef ASM_OUTPUT_ALIGNED_BSS
3086 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3087 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
3088 #endif
3089
3090 /* Define this so that jump tables go in same section as the current function,
3091 which could be text or it could be a user defined section. */
3092 #define JUMP_TABLES_IN_TEXT_SECTION 1
3093
3094 #undef DO_GLOBAL_CTORS_BODY
3095 #define DO_GLOBAL_CTORS_BODY \
3096 { \
3097 typedef (*pfunc)(); \
3098 extern pfunc __ctors[]; \
3099 extern pfunc __ctors_end[]; \
3100 pfunc *p; \
3101 for (p = __ctors_end; p > __ctors; ) \
3102 { \
3103 (*--p)(); \
3104 } \
3105 }
3106
3107 #undef DO_GLOBAL_DTORS_BODY
3108 #define DO_GLOBAL_DTORS_BODY \
3109 { \
3110 typedef (*pfunc)(); \
3111 extern pfunc __dtors[]; \
3112 extern pfunc __dtors_end[]; \
3113 pfunc *p; \
3114 for (p = __dtors; p < __dtors_end; p++) \
3115 { \
3116 (*p)(); \
3117 } \
3118 }
3119
3120 #define ASM_OUTPUT_REG_PUSH(file, v) \
3121 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
3122
3123 #define ASM_OUTPUT_REG_POP(file, v) \
3124 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
3125
3126 /* DBX register number for a given compiler register number. */
3127 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3128 to match gdb. */
3129 /* svr4.h undefines this macro, yet we really want to use the same numbers
3130 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
3131 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3132 register exists, so we should return -1 for invalid register numbers. */
3133 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3134
3135 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3136 used to use the encodings 245..260, but that doesn't make sense:
3137 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3138 the FP registers stay the same when switching between compact and media
3139 mode. Hence, we also need to use the same dwarf frame columns.
3140 Likewise, we need to support unwind information for SHmedia registers
3141 even in compact code. */
3142 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3143 (IN_RANGE ((REGNO), \
3144 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3145 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3146 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3147 : ((int) (REGNO) >= FIRST_FP_REG \
3148 && ((int) (REGNO) \
3149 <= (FIRST_FP_REG + \
3150 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3151 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3152 + (TARGET_SH5 ? 77 : 25)) \
3153 : XD_REGISTER_P (REGNO) \
3154 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3155 : TARGET_REGISTER_P (REGNO) \
3156 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3157 : (REGNO) == PR_REG \
3158 ? (TARGET_SH5 ? 18 : 17) \
3159 : (REGNO) == PR_MEDIA_REG \
3160 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3161 : (REGNO) == T_REG \
3162 ? (TARGET_SH5 ? 242 : 18) \
3163 : (REGNO) == GBR_REG \
3164 ? (TARGET_SH5 ? 238 : 19) \
3165 : (REGNO) == MACH_REG \
3166 ? (TARGET_SH5 ? 239 : 20) \
3167 : (REGNO) == MACL_REG \
3168 ? (TARGET_SH5 ? 240 : 21) \
3169 : (REGNO) == FPUL_REG \
3170 ? (TARGET_SH5 ? 244 : 23) \
3171 : (unsigned) -1)
3172
3173 /* This is how to output a reference to a symbol_ref. On SH5,
3174 references to non-code symbols must be preceded by `datalabel'. */
3175 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3176 do \
3177 { \
3178 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3179 fputs ("datalabel ", (FILE)); \
3180 assemble_name ((FILE), XSTR ((SYM), 0)); \
3181 } \
3182 while (0)
3183
3184 /* This is how to output an assembler line
3185 that says to advance the location counter
3186 to a multiple of 2**LOG bytes. */
3187
3188 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3189 if ((LOG) != 0) \
3190 fprintf ((FILE), "\t.align %d\n", (LOG))
3191
3192 /* Globalizing directive for a label. */
3193 #define GLOBAL_ASM_OP "\t.global\t"
3194
3195 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3196
3197 /* Output a relative address table. */
3198
3199 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3200 switch (GET_MODE (BODY)) \
3201 { \
3202 case SImode: \
3203 if (TARGET_SH5) \
3204 { \
3205 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3206 (VALUE), (REL)); \
3207 break; \
3208 } \
3209 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3210 break; \
3211 case HImode: \
3212 if (TARGET_SH5) \
3213 { \
3214 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3215 (VALUE), (REL)); \
3216 break; \
3217 } \
3218 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3219 break; \
3220 case QImode: \
3221 if (TARGET_SH5) \
3222 { \
3223 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3224 (VALUE), (REL)); \
3225 break; \
3226 } \
3227 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3228 break; \
3229 default: \
3230 break; \
3231 }
3232
3233 /* Output an absolute table element. */
3234
3235 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3236 if (! optimize || TARGET_BIGTABLE) \
3237 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3238 else \
3239 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3240
3241 \f
3242 /* A C statement to be executed just prior to the output of
3243 assembler code for INSN, to modify the extracted operands so
3244 they will be output differently.
3245
3246 Here the argument OPVEC is the vector containing the operands
3247 extracted from INSN, and NOPERANDS is the number of elements of
3248 the vector which contain meaningful data for this insn.
3249 The contents of this vector are what will be used to convert the insn
3250 template into assembler code, so you can change the assembler output
3251 by changing the contents of the vector. */
3252
3253 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3254 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3255
3256 /* Print operand X (an rtx) in assembler syntax to file FILE.
3257 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3258 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3259
3260 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3261
3262 /* Print a memory address as an operand to reference that memory location. */
3263
3264 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3265
3266 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3267 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3268 || (CHAR) == '$'|| (CHAR) == '\'')
3269
3270 /* Recognize machine-specific patterns that may appear within
3271 constants. Used for PIC-specific UNSPECs. */
3272 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3273 do \
3274 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3275 { \
3276 switch (XINT ((X), 1)) \
3277 { \
3278 case UNSPEC_DATALABEL: \
3279 fputs ("datalabel ", (STREAM)); \
3280 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3281 break; \
3282 case UNSPEC_PIC: \
3283 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3284 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3285 break; \
3286 case UNSPEC_GOT: \
3287 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3288 fputs ("@GOT", (STREAM)); \
3289 break; \
3290 case UNSPEC_GOTOFF: \
3291 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3292 fputs ("@GOTOFF", (STREAM)); \
3293 break; \
3294 case UNSPEC_PLT: \
3295 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3296 fputs ("@PLT", (STREAM)); \
3297 break; \
3298 case UNSPEC_GOTPLT: \
3299 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3300 fputs ("@GOTPLT", (STREAM)); \
3301 break; \
3302 case UNSPEC_DTPOFF: \
3303 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3304 fputs ("@DTPOFF", (STREAM)); \
3305 break; \
3306 case UNSPEC_GOTTPOFF: \
3307 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3308 fputs ("@GOTTPOFF", (STREAM)); \
3309 break; \
3310 case UNSPEC_TPOFF: \
3311 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3312 fputs ("@TPOFF", (STREAM)); \
3313 break; \
3314 case UNSPEC_CALLER: \
3315 { \
3316 char name[32]; \
3317 /* LPCS stands for Label for PIC Call Site. */ \
3318 ASM_GENERATE_INTERNAL_LABEL \
3319 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3320 assemble_name ((STREAM), name); \
3321 } \
3322 break; \
3323 default: \
3324 goto FAIL; \
3325 } \
3326 break; \
3327 } \
3328 else \
3329 goto FAIL; \
3330 while (0)
3331
3332 \f
3333 extern struct rtx_def *sh_compare_op0;
3334 extern struct rtx_def *sh_compare_op1;
3335
3336 /* Which processor to schedule for. The elements of the enumeration must
3337 match exactly the cpu attribute in the sh.md file. */
3338
3339 enum processor_type {
3340 PROCESSOR_SH1,
3341 PROCESSOR_SH2,
3342 PROCESSOR_SH2E,
3343 PROCESSOR_SH2A,
3344 PROCESSOR_SH3,
3345 PROCESSOR_SH3E,
3346 PROCESSOR_SH4,
3347 PROCESSOR_SH4A,
3348 PROCESSOR_SH5
3349 };
3350
3351 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3352 extern enum processor_type sh_cpu;
3353
3354 extern int optimize; /* needed for gen_casesi. */
3355
3356 enum mdep_reorg_phase_e
3357 {
3358 SH_BEFORE_MDEP_REORG,
3359 SH_INSERT_USES_LABELS,
3360 SH_SHORTEN_BRANCHES0,
3361 SH_FIXUP_PCLOAD,
3362 SH_SHORTEN_BRANCHES1,
3363 SH_AFTER_MDEP_REORG
3364 };
3365
3366 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3367
3368 /* Handle Renesas compiler's pragmas. */
3369 #define REGISTER_TARGET_PRAGMAS() do { \
3370 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3371 c_register_pragma (0, "trapa", sh_pr_trapa); \
3372 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3373 } while (0)
3374
3375 /* Set when processing a function with pragma interrupt turned on. */
3376
3377 extern int pragma_interrupt;
3378
3379 /* Set when processing a function with interrupt attribute. */
3380
3381 extern int current_function_interrupt;
3382
3383 /* Set to an RTX containing the address of the stack to switch to
3384 for interrupt functions. */
3385 extern struct rtx_def *sp_switch;
3386
3387 extern int rtx_equal_function_value_matters;
3388
3389 \f
3390 /* Instructions with unfilled delay slots take up an
3391 extra two bytes for the nop in the delay slot.
3392 sh-dsp parallel processing insns are four bytes long. */
3393
3394 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3395 (LENGTH) += sh_insn_length_adjustment (X);
3396 \f
3397 /* Define the codes that are matched by predicates in sh.c. */
3398 #define PREDICATE_CODES \
3399 {"and_operand", {SUBREG, REG, CONST_INT}}, \
3400 {"any_register_operand", {SUBREG, REG}}, \
3401 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3402 {"arith_reg_dest", {SUBREG, REG}}, \
3403 {"arith_reg_operand", {SUBREG, REG}}, \
3404 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
3405 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
3406 {"binary_logical_operator", {AND, IOR, XOR}}, \
3407 {"cmpsi_operand", {SUBREG, REG, CONST_INT}}, \
3408 {"commutative_float_operator", {PLUS, MULT}}, \
3409 {"equality_comparison_operator", {EQ,NE}}, \
3410 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3411 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
3412 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3413 {"fpscr_operand", {REG}}, \
3414 {"fpul_operand", {REG}}, \
3415 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
3416 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3417 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3418 {"unaligned_load_operand", {MEM}}, \
3419 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
3420 {"int_gpr_dest", {SUBREG, REG}}, \
3421 {"inqhi_operand", {TRUNCATE}}, \
3422 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
3423 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3424 {"mextr_bit_offset", {CONST_INT}}, \
3425 {"noncommutative_float_operator", {MINUS, DIV}}, \
3426 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3427 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \
3428 {"target_reg_operand", {SUBREG, REG}}, \
3429 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
3430 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
3431 {"register_operand", {SUBREG, REG}}, \
3432 {"sh_const_vec", {CONST_VECTOR}}, \
3433 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3434 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3435 {"symbol_ref_operand", {SYMBOL_REF}}, \
3436 {"unary_float_operator", {ABS, NEG, SQRT}}, \
3437
3438 #define SPECIAL_MODE_PREDICATES \
3439 "any_register_operand", \
3440 "int_gpr_dest", \
3441 "trunc_hi_operand", \
3442 /* This line intentionally left blank. */
3443
3444 #define any_register_operand register_operand
3445
3446 /* Define this macro if it is advisable to hold scalars in registers
3447 in a wider mode than that declared by the program. In such cases,
3448 the value is constrained to be within the bounds of the declared
3449 type, but kept valid in the wider mode. The signedness of the
3450 extension may differ from that of the type.
3451
3452 Leaving the unsignedp unchanged gives better code than always setting it
3453 to 0. This is despite the fact that we have only signed char and short
3454 load instructions. */
3455 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3456 if (GET_MODE_CLASS (MODE) == MODE_INT \
3457 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3458 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3459 (MODE) = (TARGET_SH1 ? SImode : DImode);
3460
3461 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3462
3463 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3464 and popping arguments. However, we do have push/pop instructions, and
3465 rather limited offsets (4 bits) in load/store instructions, so it isn't
3466 clear if this would give better code. If implemented, should check for
3467 compatibility problems. */
3468
3469 #define SH_DYNAMIC_SHIFT_COST \
3470 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3471
3472
3473 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3474
3475 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3476
3477 #define ACTUAL_NORMAL_MODE(ENTITY) \
3478 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3479
3480 #define NORMAL_MODE(ENTITY) \
3481 (sh_cfun_interrupt_handler_p () \
3482 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3483 : ACTUAL_NORMAL_MODE (ENTITY))
3484
3485 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3486
3487 #define MODE_EXIT(ENTITY) \
3488 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3489
3490 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3491 && (REGNO) == FPSCR_REG)
3492
3493 #define MODE_NEEDED(ENTITY, INSN) \
3494 (recog_memoized (INSN) >= 0 \
3495 ? get_attr_fp_mode (INSN) \
3496 : FP_MODE_NONE)
3497
3498 #define MODE_AFTER(MODE, INSN) \
3499 (TARGET_HITACHI \
3500 && recog_memoized (INSN) >= 0 \
3501 && get_attr_fp_set (INSN) != FP_SET_NONE \
3502 ? (int) get_attr_fp_set (INSN) \
3503 : (MODE))
3504
3505 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3506 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3507
3508 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3509 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3510
3511 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3512 sh_can_redirect_branch ((INSN), (SEQ))
3513
3514 #define DWARF_FRAME_RETURN_COLUMN \
3515 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3516
3517 #define EH_RETURN_DATA_REGNO(N) \
3518 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3519
3520 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3521 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3522
3523 /* We have to distinguish between code and data, so that we apply
3524 datalabel where and only where appropriate. Use textrel for code. */
3525 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3526 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3527 | ((CODE) ? DW_EH_PE_textrel : flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))
3528
3529 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3530 indirect are handled automatically. */
3531 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3532 do { \
3533 if (((ENCODING) & 0x70) == DW_EH_PE_textrel) \
3534 { \
3535 encoding &= ~DW_EH_PE_textrel; \
3536 encoding |= flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr; \
3537 if (GET_CODE (ADDR) != SYMBOL_REF) \
3538 abort (); \
3539 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3540 if (0) goto DONE; \
3541 } \
3542 } while (0)
3543
3544 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3545 /* SH constant pool breaks the devices in crtstuff.c to control section
3546 in where code resides. We have to write it as asm code. */
3547 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3548 asm (SECTION_OP "\n\
3549 mov.l 1f,r1\n\
3550 mova 2f,r0\n\
3551 braf r1\n\
3552 lds r0,pr\n\
3553 0: .p2align 2\n\
3554 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3555 2:\n" TEXT_SECTION_ASM_OP);
3556 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3557
3558 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3559 (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
3560 ? (current_function_is_leaf \
3561 && ! sh_pr_n_sets () \
3562 && ! (TARGET_SHCOMPACT \
3563 && ((current_function_args_info.call_cookie \
3564 & ~ CALL_COOKIE_RET_TRAMP (1)) \
3565 || current_function_has_nonlocal_label)) \
3566 ? (hard_reg) \
3567 : gen_rtx_MEM (Pmode, return_address_pointer_rtx)) \
3568 : NULL_RTX)
3569
3570 #endif /* ! GCC_SH_H */
Mirror of the offical gcc git repository hosted at gcc.gnu.org