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2008-04-06 Vladimir Makarov <vmakarov@redhat.com>
[official-gcc.git] / gcc / config / sh / sh.h
blob2b004d0722f2ad0ea03c4e6e2b39776b29188589
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #ifndef GCC_SH_H
24 #define GCC_SH_H
25
26 #include "config/vxworks-dummy.h"
27
28 #define TARGET_VERSION \
29 fputs (" (Hitachi SH)", stderr);
30
31 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
32 include it here, because bconfig.h is also included by gencodes.c . */
33 /* ??? No longer true. */
34 extern int code_for_indirect_jump_scratch;
35
36 #define TARGET_CPU_CPP_BUILTINS() \
37 do { \
38 builtin_define ("__sh__"); \
39 builtin_assert ("cpu=sh"); \
40 builtin_assert ("machine=sh"); \
41 switch ((int) sh_cpu) \
42 { \
43 case PROCESSOR_SH1: \
44 builtin_define ("__sh1__"); \
45 break; \
46 case PROCESSOR_SH2: \
47 builtin_define ("__sh2__"); \
48 break; \
49 case PROCESSOR_SH2E: \
50 builtin_define ("__SH2E__"); \
51 break; \
52 case PROCESSOR_SH2A: \
53 builtin_define ("__SH2A__"); \
54 builtin_define (TARGET_SH2A_DOUBLE \
55 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
56 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
57 : "__SH2A_NOFPU__"); \
58 break; \
59 case PROCESSOR_SH3: \
60 builtin_define ("__sh3__"); \
61 builtin_define ("__SH3__"); \
62 if (TARGET_HARD_SH4) \
63 builtin_define ("__SH4_NOFPU__"); \
64 break; \
65 case PROCESSOR_SH3E: \
66 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
67 break; \
68 case PROCESSOR_SH4: \
69 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
70 break; \
71 case PROCESSOR_SH4A: \
72 builtin_define ("__SH4A__"); \
73 builtin_define (TARGET_SH4 \
74 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
75 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
76 : "__SH4_NOFPU__"); \
77 break; \
78 case PROCESSOR_SH5: \
79 { \
80 builtin_define_with_value ("__SH5__", \
81 TARGET_SHMEDIA64 ? "64" : "32", 0); \
82 builtin_define_with_value ("__SHMEDIA__", \
83 TARGET_SHMEDIA ? "1" : "0", 0); \
84 if (! TARGET_FPU_DOUBLE) \
85 builtin_define ("__SH4_NOFPU__"); \
86 } \
87 } \
88 if (TARGET_FPU_ANY) \
89 builtin_define ("__SH_FPU_ANY__"); \
90 if (TARGET_FPU_DOUBLE) \
91 builtin_define ("__SH_FPU_DOUBLE__"); \
92 if (TARGET_HITACHI) \
93 builtin_define ("__HITACHI__"); \
94 builtin_define (TARGET_LITTLE_ENDIAN \
95 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
96 } while (0)
97
98 /* We can not debug without a frame pointer. */
99 /* #define CAN_DEBUG_WITHOUT_FP */
100
101 #define CONDITIONAL_REGISTER_USAGE do \
102 { \
103 int regno; \
104 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
105 if (! VALID_REGISTER_P (regno)) \
106 fixed_regs[regno] = call_used_regs[regno] = 1; \
107 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
108 if (TARGET_SH5) \
109 { \
110 call_used_regs[FIRST_GENERAL_REG + 8] \
111 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
112 call_really_used_regs[FIRST_GENERAL_REG + 8] \
113 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
114 } \
115 if (TARGET_SHMEDIA) \
116 { \
117 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
118 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
119 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
120 } \
121 if (flag_pic) \
122 { \
123 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
125 } \
126 /* Renesas saves and restores mac registers on call. */ \
127 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
128 { \
129 call_really_used_regs[MACH_REG] = 0; \
130 call_really_used_regs[MACL_REG] = 0; \
131 } \
132 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
133 regno <= LAST_FP_REG; regno += 2) \
134 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
135 if (TARGET_SHMEDIA) \
136 { \
137 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
138 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
139 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
140 } \
141 else \
142 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
143 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
144 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
145 } while (0)
146 \f
147 /* Nonzero if this is an ELF target - compile time only */
148 #define TARGET_ELF 0
149
150 /* Nonzero if we should generate code using type 2E insns. */
151 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
152
153 /* Nonzero if we should generate code using type 2A insns. */
154 #define TARGET_SH2A TARGET_HARD_SH2A
155 /* Nonzero if we should generate code using type 2A SF insns. */
156 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
157 /* Nonzero if we should generate code using type 2A DF insns. */
158 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
159
160 /* Nonzero if we should generate code using type 3E insns. */
161 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
162
163 /* Nonzero if the cache line size is 32. */
164 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
165
166 /* Nonzero if we schedule for a superscalar implementation. */
167 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
168
169 /* Nonzero if the target has separate instruction and data caches. */
170 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
171
172 /* Nonzero if a double-precision FPU is available. */
173 #define TARGET_FPU_DOUBLE \
174 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
175
176 /* Nonzero if an FPU is available. */
177 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
178
179 /* Nonzero if we should generate code using type 4 insns. */
180 #undef TARGET_SH4
181 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
182
183 /* Nonzero if we're generating code for the common subset of
184 instructions present on both SH4a and SH4al-dsp. */
185 #define TARGET_SH4A_ARCH TARGET_SH4A
186
187 /* Nonzero if we're generating code for SH4a, unless the use of the
188 FPU is disabled (which makes it compatible with SH4al-dsp). */
189 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
190
191 /* Nonzero if we should generate code using the SHcompact instruction
192 set and 32-bit ABI. */
193 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
194
195 /* Nonzero if we should generate code using the SHmedia instruction
196 set and ABI. */
197 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
198
199 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
200 ABI. */
201 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
202
203 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
204 ABI. */
205 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
206
207 /* Nonzero if we should generate code using SHmedia FPU instructions. */
208 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
209
210 /* This is not used by the SH2E calling convention */
211 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
212 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
213 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
214
215 #ifndef TARGET_CPU_DEFAULT
216 #define TARGET_CPU_DEFAULT SELECT_SH1
217 #define SUPPORT_SH1 1
218 #define SUPPORT_SH2E 1
219 #define SUPPORT_SH4 1
220 #define SUPPORT_SH4_SINGLE 1
221 #define SUPPORT_SH2A 1
222 #define SUPPORT_SH2A_SINGLE 1
223 #endif
224
225 #define TARGET_DIVIDE_INV \
226 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
227 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
228 || sh_div_strategy == SH_DIV_INV_CALL \
229 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
230 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
231 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
232 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
233 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
234 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
235 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
236 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
237 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
238 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
239 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
240 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
241
242 #define SELECT_SH1 (MASK_SH1)
243 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
244 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
245 | MASK_FPU_SINGLE)
246 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
247 | MASK_HARD_SH2A_DOUBLE \
248 | MASK_SH2 | MASK_SH1)
249 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
250 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
251 | MASK_SH1 | MASK_FPU_SINGLE)
252 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
253 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
254 | MASK_SH2 | MASK_SH1)
255 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
256 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
257 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
258 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
259 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
260 | SELECT_SH3)
261 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
262 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
263 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
264 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
265 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
266 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
267 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
268 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
269 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
270 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
271 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
272
273 #if SUPPORT_SH1
274 #define SUPPORT_SH2 1
275 #endif
276 #if SUPPORT_SH2
277 #define SUPPORT_SH3 1
278 #define SUPPORT_SH2A_NOFPU 1
279 #endif
280 #if SUPPORT_SH3
281 #define SUPPORT_SH4_NOFPU 1
282 #endif
283 #if SUPPORT_SH4_NOFPU
284 #define SUPPORT_SH4A_NOFPU 1
285 #define SUPPORT_SH4AL 1
286 #endif
287
288 #if SUPPORT_SH2E
289 #define SUPPORT_SH3E 1
290 #define SUPPORT_SH2A_SINGLE_ONLY 1
291 #endif
292 #if SUPPORT_SH3E
293 #define SUPPORT_SH4_SINGLE_ONLY 1
294 #endif
295 #if SUPPORT_SH4_SINGLE_ONLY
296 #define SUPPORT_SH4A_SINGLE_ONLY 1
297 #endif
298
299 #if SUPPORT_SH4
300 #define SUPPORT_SH4A 1
301 #endif
302
303 #if SUPPORT_SH4_SINGLE
304 #define SUPPORT_SH4A_SINGLE 1
305 #endif
306
307 #if SUPPORT_SH5_COMPAT
308 #define SUPPORT_SH5_32MEDIA 1
309 #endif
310
311 #if SUPPORT_SH5_COMPACT_NOFPU
312 #define SUPPORT_SH5_32MEDIA_NOFPU 1
313 #endif
314
315 #define SUPPORT_ANY_SH5_32MEDIA \
316 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
317 #define SUPPORT_ANY_SH5_64MEDIA \
318 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
319 #define SUPPORT_ANY_SH5 \
320 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
321
322 /* Reset all target-selection flags. */
323 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
324 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
325 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
326
327 /* This defaults us to big-endian. */
328 #ifndef TARGET_ENDIAN_DEFAULT
329 #define TARGET_ENDIAN_DEFAULT 0
330 #endif
331
332 #ifndef TARGET_OPT_DEFAULT
333 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
334 #endif
335
336 #define TARGET_DEFAULT \
337 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
338
339 #ifndef SH_MULTILIB_CPU_DEFAULT
340 #define SH_MULTILIB_CPU_DEFAULT "m1"
341 #endif
342
343 #if TARGET_ENDIAN_DEFAULT
344 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
345 #else
346 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
347 #endif
348
349 #define CPP_SPEC " %(subtarget_cpp_spec) "
350
351 #ifndef SUBTARGET_CPP_SPEC
352 #define SUBTARGET_CPP_SPEC ""
353 #endif
354
355 #ifndef SUBTARGET_EXTRA_SPECS
356 #define SUBTARGET_EXTRA_SPECS
357 #endif
358
359 #define EXTRA_SPECS \
360 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
361 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
362 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
363 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
364 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
365 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
366 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
367 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
368 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
369 SUBTARGET_EXTRA_SPECS
370
371 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
372 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
373 #else
374 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
375 #endif
376
377 #define SH_ASM_SPEC \
378 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
379 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
380 %{m2a:--isa=sh2a} \
381 %{m2a-single:--isa=sh2a} \
382 %{m2a-single-only:--isa=sh2a} \
383 %{m2a-nofpu:--isa=sh2a-nofpu} \
384 %{m5-compact*:--isa=SHcompact} \
385 %{m5-32media*:--isa=SHmedia --abi=32} \
386 %{m5-64media*:--isa=SHmedia --abi=64} \
387 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
388
389 #define ASM_SPEC SH_ASM_SPEC
390
391 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
392 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
393 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
394 #else
395 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
396 #endif
397 #endif
398
399 #if STRICT_NOFPU == 1
400 /* Strict nofpu means that the compiler should tell the assembler
401 to reject FPU instructions. E.g. from ASM inserts. */
402 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
403 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
404 #else
405 /* If there were an -isa option for sh5-nofpu then it would also go here. */
406 #define SUBTARGET_ASM_ISA_SPEC \
407 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
408 #endif
409 #else /* ! STRICT_NOFPU */
410 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
411 #endif
412
413 #ifndef SUBTARGET_ASM_SPEC
414 #define SUBTARGET_ASM_SPEC ""
415 #endif
416
417 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
418 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
419 #else
420 #define LINK_EMUL_PREFIX "sh%{ml:l}"
421 #endif
422
423 #if TARGET_CPU_DEFAULT & MASK_SH5
424 #if TARGET_CPU_DEFAULT & MASK_SH_E
425 #define LINK_DEFAULT_CPU_EMUL "32"
426 #if TARGET_CPU_DEFAULT & MASK_SH1
427 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
428 #else
429 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
430 #endif /* MASK_SH1 */
431 #else /* !MASK_SH_E */
432 #define LINK_DEFAULT_CPU_EMUL "64"
433 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
434 #endif /* MASK_SH_E */
435 #define ASM_ISA_DEFAULT_SPEC \
436 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
437 #else /* !MASK_SH5 */
438 #define LINK_DEFAULT_CPU_EMUL ""
439 #define ASM_ISA_DEFAULT_SPEC ""
440 #endif /* MASK_SH5 */
441
442 #define SUBTARGET_LINK_EMUL_SUFFIX ""
443 #define SUBTARGET_LINK_SPEC ""
444
445 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
446 so that we can undo the damage without code replication. */
447 #define LINK_SPEC SH_LINK_SPEC
448
449 #define SH_LINK_SPEC "\
450 -m %(link_emul_prefix)\
451 %{m5-compact*|m5-32media*:32}\
452 %{m5-64media*:64}\
453 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
454 %(subtarget_link_emul_suffix) \
455 %{mrelax:-relax} %(subtarget_link_spec)"
456
457 #ifndef SH_DIV_STR_FOR_SIZE
458 #define SH_DIV_STR_FOR_SIZE "call"
459 #endif
460
461 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
462 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
463 do { \
464 if (LEVEL) \
465 { \
466 flag_omit_frame_pointer = -1; \
467 if (! SIZE) \
468 sh_div_str = "inv:minlat"; \
469 } \
470 if (SIZE) \
471 { \
472 target_flags |= MASK_SMALLCODE; \
473 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
474 } \
475 else \
476 { \
477 TARGET_CBRANCHDI4 = 1; \
478 TARGET_EXPAND_CBRANCHDI4 = 1; \
479 } \
480 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
481 haven't been parsed yet, hence we'd read only the default. \
482 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
483 it's OK to always set flag_branch_target_load_optimize. */ \
484 if (LEVEL > 1) \
485 { \
486 flag_branch_target_load_optimize = 1; \
487 if (! (SIZE)) \
488 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
489 } \
490 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
491 here, so leave it to OVERRIDE_OPTIONS to set \
492 flag_finite_math_only. We set it to 2 here so we know if the user \
493 explicitly requested this to be on or off. */ \
494 flag_finite_math_only = 2; \
495 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
496 the user explicitly requested this to be on or off. */ \
497 if (flag_schedule_insns > 0) \
498 flag_schedule_insns = 2; \
499 \
500 set_param_value ("simultaneous-prefetches", 2); \
501 } while (0)
502
503 #define ASSEMBLER_DIALECT assembler_dialect
504
505 extern int assembler_dialect;
506
507 enum sh_divide_strategy_e {
508 /* SH5 strategies. */
509 SH_DIV_CALL,
510 SH_DIV_CALL2,
511 SH_DIV_FP, /* We could do this also for SH4. */
512 SH_DIV_INV,
513 SH_DIV_INV_MINLAT,
514 SH_DIV_INV20U,
515 SH_DIV_INV20L,
516 SH_DIV_INV_CALL,
517 SH_DIV_INV_CALL2,
518 SH_DIV_INV_FP,
519 /* SH1 .. SH4 strategies. Because of the small number of registers
520 available, the compiler uses knowledge of the actual set of registers
521 being clobbered by the different functions called. */
522 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
523 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
524 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
525 SH_DIV_INTRINSIC
526 };
527
528 extern enum sh_divide_strategy_e sh_div_strategy;
529
530 #ifndef SH_DIV_STRATEGY_DEFAULT
531 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
532 #endif
533
534 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
535
536 #define OVERRIDE_OPTIONS \
537 do { \
538 int regno; \
539 \
540 SUBTARGET_OVERRIDE_OPTIONS; \
541 if (flag_finite_math_only == 2) \
542 flag_finite_math_only \
543 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
544 if (TARGET_SH2E && !flag_finite_math_only) \
545 target_flags |= MASK_IEEE; \
546 sh_cpu = CPU_SH1; \
547 assembler_dialect = 0; \
548 if (TARGET_SH2) \
549 sh_cpu = CPU_SH2; \
550 if (TARGET_SH2E) \
551 sh_cpu = CPU_SH2E; \
552 if (TARGET_SH2A) \
553 { \
554 sh_cpu = CPU_SH2A; \
555 if (TARGET_SH2A_DOUBLE) \
556 target_flags |= MASK_FMOVD; \
557 } \
558 if (TARGET_SH3) \
559 sh_cpu = CPU_SH3; \
560 if (TARGET_SH3E) \
561 sh_cpu = CPU_SH3E; \
562 if (TARGET_SH4) \
563 { \
564 assembler_dialect = 1; \
565 sh_cpu = CPU_SH4; \
566 } \
567 if (TARGET_SH4A_ARCH) \
568 { \
569 assembler_dialect = 1; \
570 sh_cpu = CPU_SH4A; \
571 } \
572 if (TARGET_SH5) \
573 { \
574 sh_cpu = CPU_SH5; \
575 target_flags |= MASK_ALIGN_DOUBLE; \
576 if (TARGET_SHMEDIA_FPU) \
577 target_flags |= MASK_FMOVD; \
578 if (TARGET_SHMEDIA) \
579 { \
580 /* There are no delay slots on SHmedia. */ \
581 flag_delayed_branch = 0; \
582 /* Relaxation isn't yet supported for SHmedia */ \
583 target_flags &= ~MASK_RELAX; \
584 /* After reload, if conversion does little good but can cause \
585 ICEs: \
586 - find_if_block doesn't do anything for SH because we don't\
587 have conditional execution patterns. (We use conditional\
588 move patterns, which are handled differently, and only \
589 before reload). \
590 - find_cond_trap doesn't do anything for the SH because we \
591 don't have conditional traps. \
592 - find_if_case_1 uses redirect_edge_and_branch_force in \
593 the only path that does an optimization, and this causes \
594 an ICE when branch targets are in registers. \
595 - find_if_case_2 doesn't do anything for the SHmedia after \
596 reload except when it can redirect a tablejump - and \
597 that's rather rare. */ \
598 flag_if_conversion2 = 0; \
599 if (! strcmp (sh_div_str, "call")) \
600 sh_div_strategy = SH_DIV_CALL; \
601 else if (! strcmp (sh_div_str, "call2")) \
602 sh_div_strategy = SH_DIV_CALL2; \
603 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
604 sh_div_strategy = SH_DIV_FP; \
605 else if (! strcmp (sh_div_str, "inv")) \
606 sh_div_strategy = SH_DIV_INV; \
607 else if (! strcmp (sh_div_str, "inv:minlat")) \
608 sh_div_strategy = SH_DIV_INV_MINLAT; \
609 else if (! strcmp (sh_div_str, "inv20u")) \
610 sh_div_strategy = SH_DIV_INV20U; \
611 else if (! strcmp (sh_div_str, "inv20l")) \
612 sh_div_strategy = SH_DIV_INV20L; \
613 else if (! strcmp (sh_div_str, "inv:call2")) \
614 sh_div_strategy = SH_DIV_INV_CALL2; \
615 else if (! strcmp (sh_div_str, "inv:call")) \
616 sh_div_strategy = SH_DIV_INV_CALL; \
617 else if (! strcmp (sh_div_str, "inv:fp")) \
618 { \
619 if (TARGET_FPU_ANY) \
620 sh_div_strategy = SH_DIV_INV_FP; \
621 else \
622 sh_div_strategy = SH_DIV_INV; \
623 } \
624 TARGET_CBRANCHDI4 = 0; \
625 } \
626 } \
627 else \
628 { \
629 /* Only the sh64-elf assembler fully supports .quad properly. */\
630 targetm.asm_out.aligned_op.di = NULL; \
631 targetm.asm_out.unaligned_op.di = NULL; \
632 } \
633 if (TARGET_SH1) \
634 { \
635 if (! strcmp (sh_div_str, "call-div1")) \
636 sh_div_strategy = SH_DIV_CALL_DIV1; \
637 else if (! strcmp (sh_div_str, "call-fp") \
638 && (TARGET_FPU_DOUBLE \
639 || (TARGET_HARD_SH4 && TARGET_SH2E) \
640 || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
641 sh_div_strategy = SH_DIV_CALL_FP; \
642 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2) \
643 sh_div_strategy = SH_DIV_CALL_TABLE; \
644 else \
645 /* Pick one that makes most sense for the target in general. \
646 It is not much good to use different functions depending \
647 on -Os, since then we'll end up with two different functions \
648 when some of the code is compiled for size, and some for \
649 speed. */ \
650 \
651 /* SH4 tends to emphasize speed. */ \
652 if (TARGET_HARD_SH4) \
653 sh_div_strategy = SH_DIV_CALL_TABLE; \
654 /* These have their own way of doing things. */ \
655 else if (TARGET_SH2A) \
656 sh_div_strategy = SH_DIV_INTRINSIC; \
657 /* ??? Should we use the integer SHmedia function instead? */ \
658 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
659 sh_div_strategy = SH_DIV_CALL_FP; \
660 /* SH1 .. SH3 cores often go into small-footprint systems, so \
661 default to the smallest implementation available. */ \
662 else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \
663 sh_div_strategy = SH_DIV_CALL_TABLE; \
664 else \
665 sh_div_strategy = SH_DIV_CALL_DIV1; \
666 } \
667 if (!TARGET_SH1) \
668 TARGET_PRETEND_CMOVE = 0; \
669 if (sh_divsi3_libfunc[0]) \
670 ; /* User supplied - leave it alone. */ \
671 else if (TARGET_DIVIDE_CALL_FP) \
672 sh_divsi3_libfunc = "__sdivsi3_i4"; \
673 else if (TARGET_DIVIDE_CALL_TABLE) \
674 sh_divsi3_libfunc = "__sdivsi3_i4i"; \
675 else if (TARGET_SH5) \
676 sh_divsi3_libfunc = "__sdivsi3_1"; \
677 else \
678 sh_divsi3_libfunc = "__sdivsi3"; \
679 if (sh_branch_cost == -1) \
680 sh_branch_cost \
681 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1; \
682 \
683 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
684 if (! VALID_REGISTER_P (regno)) \
685 sh_register_names[regno][0] = '\0'; \
686 \
687 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
688 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
689 sh_additional_register_names[regno][0] = '\0'; \
690 \
691 if (flag_omit_frame_pointer < 0) \
692 { \
693 /* The debugging information is sufficient, \
694 but gdb doesn't implement this yet */ \
695 if (0) \
696 flag_omit_frame_pointer \
697 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
698 else \
699 flag_omit_frame_pointer = 0; \
700 } \
701 \
702 if ((flag_pic && ! TARGET_PREFERGOT) \
703 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
704 flag_no_function_cse = 1; \
705 \
706 if (SMALL_REGISTER_CLASSES) \
707 { \
708 /* Never run scheduling before reload, since that can \
709 break global alloc, and generates slower code anyway due \
710 to the pressure on R0. */ \
711 /* Enable sched1 for SH4; ready queue will be reordered by \
712 the target hooks when pressure is high. We can not do this for \
713 SH3 and lower as they give spill failures for R0. */ \
714 if (!TARGET_HARD_SH4) \
715 flag_schedule_insns = 0; \
716 /* ??? Current exception handling places basic block boundaries \
717 after call_insns. It causes the high pressure on R0 and gives \
718 spill failures for R0 in reload. See PR 22553 and the thread \
719 on gcc-patches \
720 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
721 else if (flag_exceptions) \
722 { \
723 if (flag_schedule_insns == 1) \
724 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
725 flag_schedule_insns = 0; \
726 } \
727 } \
728 \
729 if (align_loops == 0) \
730 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
731 if (align_jumps == 0) \
732 align_jumps = 1 << CACHE_LOG; \
733 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
734 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
735 \
736 /* Allocation boundary (in *bytes*) for the code of a function. \
737 SH1: 32 bit alignment is faster, because instructions are always \
738 fetched as a pair from a longword boundary. \
739 SH2 .. SH5 : align to cache line start. */ \
740 if (align_functions == 0) \
741 align_functions \
742 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
743 /* The linker relaxation code breaks when a function contains \
744 alignments that are larger than that at the start of a \
745 compilation unit. */ \
746 if (TARGET_RELAX) \
747 { \
748 int min_align \
749 = align_loops > align_jumps ? align_loops : align_jumps; \
750 \
751 /* Also take possible .long constants / mova tables int account. */\
752 if (min_align < 4) \
753 min_align = 4; \
754 if (align_functions < min_align) \
755 align_functions = min_align; \
756 } \
757 } while (0)
758 \f
759 /* Target machine storage layout. */
760
761 /* Define this if most significant bit is lowest numbered
762 in instructions that operate on numbered bit-fields. */
763
764 #define BITS_BIG_ENDIAN 0
765
766 /* Define this if most significant byte of a word is the lowest numbered. */
767 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
768
769 /* Define this if most significant word of a multiword number is the lowest
770 numbered. */
771 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
772
773 /* Define this to set the endianness to use in libgcc2.c, which can
774 not depend on target_flags. */
775 #if defined(__LITTLE_ENDIAN__)
776 #define LIBGCC2_WORDS_BIG_ENDIAN 0
777 #else
778 #define LIBGCC2_WORDS_BIG_ENDIAN 1
779 #endif
780
781 #define MAX_BITS_PER_WORD 64
782
783 /* Width in bits of an `int'. We want just 32-bits, even if words are
784 longer. */
785 #define INT_TYPE_SIZE 32
786
787 /* Width in bits of a `long'. */
788 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
789
790 /* Width in bits of a `long long'. */
791 #define LONG_LONG_TYPE_SIZE 64
792
793 /* Width in bits of a `long double'. */
794 #define LONG_DOUBLE_TYPE_SIZE 64
795
796 /* Width of a word, in units (bytes). */
797 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
798 #define MIN_UNITS_PER_WORD 4
799
800 /* Scaling factor for Dwarf data offsets for CFI information.
801 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
802 SHmedia; however, since we do partial register saves for the registers
803 visible to SHcompact, and for target registers for SHMEDIA32, we have
804 to allow saves that are only 4-byte aligned. */
805 #define DWARF_CIE_DATA_ALIGNMENT -4
806
807 /* Width in bits of a pointer.
808 See also the macro `Pmode' defined below. */
809 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
810
811 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
812 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
813
814 /* Boundary (in *bits*) on which stack pointer should be aligned. */
815 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
816
817 /* The log (base 2) of the cache line size, in bytes. Processors prior to
818 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
819 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
820 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
821
822 /* ABI given & required minimum allocation boundary (in *bits*) for the
823 code of a function. */
824 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
825
826 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
827 the vbit must go into the delta field of
828 pointers-to-member-functions. */
829 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
830 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
831
832 /* Alignment of field after `int : 0' in a structure. */
833 #define EMPTY_FIELD_BOUNDARY 32
834
835 /* No data type wants to be aligned rounder than this. */
836 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
837
838 /* The best alignment to use in cases where we have a choice. */
839 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
840
841 /* Make strings word-aligned so strcpy from constants will be faster. */
842 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
843 ((TREE_CODE (EXP) == STRING_CST \
844 && (ALIGN) < FASTEST_ALIGNMENT) \
845 ? FASTEST_ALIGNMENT : (ALIGN))
846
847 /* get_mode_alignment assumes complex values are always held in multiple
848 registers, but that is not the case on the SH; CQImode and CHImode are
849 held in a single integer register. SH5 also holds CSImode and SCmode
850 values in integer registers. This is relevant for argument passing on
851 SHcompact as we use a stack temp in order to pass CSImode by reference. */
852 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
853 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
854 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
855 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
856 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
857
858 /* Make arrays of chars word-aligned for the same reasons. */
859 #define DATA_ALIGNMENT(TYPE, ALIGN) \
860 (TREE_CODE (TYPE) == ARRAY_TYPE \
861 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
862 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
863
864 /* Number of bits which any structure or union's size must be a
865 multiple of. Each structure or union's size is rounded up to a
866 multiple of this. */
867 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
868
869 /* Set this nonzero if move instructions will actually fail to work
870 when given unaligned data. */
871 #define STRICT_ALIGNMENT 1
872
873 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
874 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
875 barrier_align (LABEL_AFTER_BARRIER)
876
877 #define LOOP_ALIGN(A_LABEL) \
878 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
879 ? 0 : sh_loop_align (A_LABEL))
880
881 #define LABEL_ALIGN(A_LABEL) \
882 ( \
883 (PREV_INSN (A_LABEL) \
884 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
885 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
886 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
887 /* explicit alignment insn in constant tables. */ \
888 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
889 : 0)
890
891 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
892 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
893
894 /* The base two logarithm of the known minimum alignment of an insn length. */
895 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
896 (GET_CODE (A_INSN) == INSN \
897 ? 1 << TARGET_SHMEDIA \
898 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
899 ? 1 << TARGET_SHMEDIA \
900 : CACHE_LOG)
901 \f
902 /* Standard register usage. */
903
904 /* Register allocation for the Renesas calling convention:
905
906 r0 arg return
907 r1..r3 scratch
908 r4..r7 args in
909 r8..r13 call saved
910 r14 frame pointer/call saved
911 r15 stack pointer
912 ap arg pointer (doesn't really exist, always eliminated)
913 pr subroutine return address
914 t t bit
915 mach multiply/accumulate result, high part
916 macl multiply/accumulate result, low part.
917 fpul fp/int communication register
918 rap return address pointer register
919 fr0 fp arg return
920 fr1..fr3 scratch floating point registers
921 fr4..fr11 fp args in
922 fr12..fr15 call saved floating point registers */
923
924 #define MAX_REGISTER_NAME_LENGTH 5
925 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
926
927 #define SH_REGISTER_NAMES_INITIALIZER \
928 { \
929 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
930 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
931 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
932 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
933 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
934 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
935 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
936 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
937 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
938 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
939 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
940 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
941 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
942 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
943 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
944 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
945 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
946 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
947 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
948 "rap", "sfp" \
949 }
950
951 #define REGNAMES_ARR_INDEX_1(index) \
952 (sh_register_names[index])
953 #define REGNAMES_ARR_INDEX_2(index) \
954 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
955 #define REGNAMES_ARR_INDEX_4(index) \
956 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
957 #define REGNAMES_ARR_INDEX_8(index) \
958 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
959 #define REGNAMES_ARR_INDEX_16(index) \
960 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
961 #define REGNAMES_ARR_INDEX_32(index) \
962 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
963 #define REGNAMES_ARR_INDEX_64(index) \
964 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
965
966 #define REGISTER_NAMES \
967 { \
968 REGNAMES_ARR_INDEX_64 (0), \
969 REGNAMES_ARR_INDEX_64 (64), \
970 REGNAMES_ARR_INDEX_8 (128), \
971 REGNAMES_ARR_INDEX_8 (136), \
972 REGNAMES_ARR_INDEX_8 (144), \
973 REGNAMES_ARR_INDEX_2 (152) \
974 }
975
976 #define ADDREGNAMES_SIZE 32
977 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
978 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
979 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
980
981 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
982 { \
983 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
984 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
985 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
986 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
987 }
988
989 #define ADDREGNAMES_REGNO(index) \
990 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
991 : (-1))
992
993 #define ADDREGNAMES_ARR_INDEX_1(index) \
994 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
995 #define ADDREGNAMES_ARR_INDEX_2(index) \
996 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
997 #define ADDREGNAMES_ARR_INDEX_4(index) \
998 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
999 #define ADDREGNAMES_ARR_INDEX_8(index) \
1000 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1001 #define ADDREGNAMES_ARR_INDEX_16(index) \
1002 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1003 #define ADDREGNAMES_ARR_INDEX_32(index) \
1004 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1005
1006 #define ADDITIONAL_REGISTER_NAMES \
1007 { \
1008 ADDREGNAMES_ARR_INDEX_32 (0) \
1009 }
1010
1011 /* Number of actual hardware registers.
1012 The hardware registers are assigned numbers for the compiler
1013 from 0 to just below FIRST_PSEUDO_REGISTER.
1014 All registers that the compiler knows about must be given numbers,
1015 even those that are not normally considered general registers. */
1016
1017 /* There are many other relevant definitions in sh.md's md_constants. */
1018
1019 #define FIRST_GENERAL_REG R0_REG
1020 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1021 #define FIRST_FP_REG DR0_REG
1022 #define LAST_FP_REG (FIRST_FP_REG + \
1023 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1024 #define FIRST_XD_REG XD0_REG
1025 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1026 #define FIRST_TARGET_REG TR0_REG
1027 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1028
1029 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
1030
1031 #define FIRST_BANKED_REG R0_REG
1032 #define LAST_BANKED_REG R7_REG
1033
1034 #define BANKED_REGISTER_P(REGNO) \
1035 IN_RANGE ((REGNO), \
1036 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
1037 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
1038
1039 #define GENERAL_REGISTER_P(REGNO) \
1040 IN_RANGE ((REGNO), \
1041 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1042 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1043
1044 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1045 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
1046 || ((REGNO) == FRAME_POINTER_REGNUM))
1047
1048 #define FP_REGISTER_P(REGNO) \
1049 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1050
1051 #define XD_REGISTER_P(REGNO) \
1052 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1053
1054 #define FP_OR_XD_REGISTER_P(REGNO) \
1055 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1056
1057 #define FP_ANY_REGISTER_P(REGNO) \
1058 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1059
1060 #define SPECIAL_REGISTER_P(REGNO) \
1061 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1062 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1063
1064 #define TARGET_REGISTER_P(REGNO) \
1065 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1066
1067 #define SHMEDIA_REGISTER_P(REGNO) \
1068 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1069 || TARGET_REGISTER_P (REGNO))
1070
1071 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1072 that should be fixed. */
1073 #define VALID_REGISTER_P(REGNO) \
1074 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1075 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1076 || (REGNO) == FRAME_POINTER_REGNUM \
1077 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1078 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1079
1080 /* The mode that should be generally used to store a register by
1081 itself in the stack, or to load it back. */
1082 #define REGISTER_NATURAL_MODE(REGNO) \
1083 (FP_REGISTER_P (REGNO) ? SFmode \
1084 : XD_REGISTER_P (REGNO) ? DFmode \
1085 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1086 ? DImode \
1087 : SImode)
1088
1089 #define FIRST_PSEUDO_REGISTER 154
1090
1091 /* Don't count soft frame pointer. */
1092 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1093
1094 /* 1 for registers that have pervasive standard uses
1095 and are not available for the register allocator.
1096
1097 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1098 It is 32 bits wide for SH2. */
1099
1100 #define FIXED_REGISTERS \
1101 { \
1102 /* Regular registers. */ \
1103 0, 0, 0, 0, 0, 0, 0, 0, \
1104 0, 0, 0, 0, 0, 0, 0, 1, \
1105 /* r16 is reserved, r18 is the former pr. */ \
1106 1, 0, 0, 0, 0, 0, 0, 0, \
1107 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1108 /* r26 is a global variable data pointer; r27 is for constants. */ \
1109 1, 1, 1, 1, 0, 0, 0, 0, \
1110 0, 0, 0, 0, 0, 0, 0, 0, \
1111 0, 0, 0, 0, 0, 0, 0, 0, \
1112 0, 0, 0, 0, 0, 0, 0, 0, \
1113 0, 0, 0, 0, 0, 0, 0, 1, \
1114 /* FP registers. */ \
1115 0, 0, 0, 0, 0, 0, 0, 0, \
1116 0, 0, 0, 0, 0, 0, 0, 0, \
1117 0, 0, 0, 0, 0, 0, 0, 0, \
1118 0, 0, 0, 0, 0, 0, 0, 0, \
1119 0, 0, 0, 0, 0, 0, 0, 0, \
1120 0, 0, 0, 0, 0, 0, 0, 0, \
1121 0, 0, 0, 0, 0, 0, 0, 0, \
1122 0, 0, 0, 0, 0, 0, 0, 0, \
1123 /* Branch target registers. */ \
1124 0, 0, 0, 0, 0, 0, 0, 0, \
1125 /* XD registers. */ \
1126 0, 0, 0, 0, 0, 0, 0, 0, \
1127 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1128 1, 1, 1, 1, 1, 1, 0, 1, \
1129 /*"rap", "sfp" */ \
1130 1, 1, \
1131 }
1132
1133 /* 1 for registers not available across function calls.
1134 These must include the FIXED_REGISTERS and also any
1135 registers that can be used without being saved.
1136 The latter must include the registers where values are returned
1137 and the register where structure-value addresses are passed.
1138 Aside from that, you can include as many other registers as you like. */
1139
1140 #define CALL_USED_REGISTERS \
1141 { \
1142 /* Regular registers. */ \
1143 1, 1, 1, 1, 1, 1, 1, 1, \
1144 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1145 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1146 across SH5 function calls. */ \
1147 0, 0, 0, 0, 0, 0, 0, 1, \
1148 1, 1, 1, 1, 1, 1, 1, 1, \
1149 1, 1, 1, 1, 0, 0, 0, 0, \
1150 0, 0, 0, 0, 1, 1, 1, 1, \
1151 1, 1, 1, 1, 0, 0, 0, 0, \
1152 0, 0, 0, 0, 0, 0, 0, 0, \
1153 0, 0, 0, 0, 1, 1, 1, 1, \
1154 /* FP registers. */ \
1155 1, 1, 1, 1, 1, 1, 1, 1, \
1156 1, 1, 1, 1, 0, 0, 0, 0, \
1157 1, 1, 1, 1, 1, 1, 1, 1, \
1158 1, 1, 1, 1, 1, 1, 1, 1, \
1159 1, 1, 1, 1, 0, 0, 0, 0, \
1160 0, 0, 0, 0, 0, 0, 0, 0, \
1161 0, 0, 0, 0, 0, 0, 0, 0, \
1162 0, 0, 0, 0, 0, 0, 0, 0, \
1163 /* Branch target registers. */ \
1164 1, 1, 1, 1, 1, 0, 0, 0, \
1165 /* XD registers. */ \
1166 1, 1, 1, 1, 1, 1, 0, 0, \
1167 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1168 1, 1, 1, 1, 1, 1, 1, 1, \
1169 /*"rap", "sfp" */ \
1170 1, 1, \
1171 }
1172
1173 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1174 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1175 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1176
1177 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1178 across SHcompact function calls. We can't tell whether a called
1179 function is SHmedia or SHcompact, so we assume it may be when
1180 compiling SHmedia code with the 32-bit ABI, since that's the only
1181 ABI that can be linked with SHcompact code. */
1182 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1183 (TARGET_SHMEDIA32 \
1184 && GET_MODE_SIZE (MODE) > 4 \
1185 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1186 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1187 || TARGET_REGISTER_P (REGNO) \
1188 || (REGNO) == PR_MEDIA_REG))
1189
1190 /* Return number of consecutive hard regs needed starting at reg REGNO
1191 to hold something of mode MODE.
1192 This is ordinarily the length in words of a value of mode MODE
1193 but can be less for certain modes in special long registers.
1194
1195 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1196
1197 #define HARD_REGNO_NREGS(REGNO, MODE) \
1198 (XD_REGISTER_P (REGNO) \
1199 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1200 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1201 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1202 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1203
1204 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1205 We can allow any mode in any general register. The special registers
1206 only allow SImode. Don't allow any mode in the PR. */
1207
1208 /* We cannot hold DCmode values in the XD registers because alter_reg
1209 handles subregs of them incorrectly. We could work around this by
1210 spacing the XD registers like the DR registers, but this would require
1211 additional memory in every compilation to hold larger register vectors.
1212 We could hold SFmode / SCmode values in XD registers, but that
1213 would require a tertiary reload when reloading from / to memory,
1214 and a secondary reload to reload from / to general regs; that
1215 seems to be a loosing proposition. */
1216 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1217 it won't be ferried through GP registers first. */
1218 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1219 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1220 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1221 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1222 ? 1 \
1223 : (MODE) == V2SFmode \
1224 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1225 || GENERAL_REGISTER_P (REGNO)) \
1226 : (MODE) == V4SFmode \
1227 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1228 || GENERAL_REGISTER_P (REGNO)) \
1229 : (MODE) == V16SFmode \
1230 ? (TARGET_SHMEDIA \
1231 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1232 : (REGNO) == FIRST_XD_REG) \
1233 : FP_REGISTER_P (REGNO) \
1234 ? ((MODE) == SFmode || (MODE) == SImode \
1235 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1236 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1237 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1238 || (MODE) == V2SFmode || (MODE) == TImode))) \
1239 && (((REGNO) - FIRST_FP_REG) & 1) == 0) \
1240 || ((TARGET_SH4 || TARGET_SHMEDIA) \
1241 && (MODE) == TImode \
1242 && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
1243 : XD_REGISTER_P (REGNO) \
1244 ? (MODE) == DFmode \
1245 : TARGET_REGISTER_P (REGNO) \
1246 ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
1247 : (REGNO) == PR_REG ? (MODE) == SImode \
1248 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1249 : 1)
1250
1251 /* Value is 1 if it is a good idea to tie two pseudo registers
1252 when one has mode MODE1 and one has mode MODE2.
1253 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1254 for any hard reg, then this must be 0 for correct output.
1255 That's the case for xd registers: we don't hold SFmode values in
1256 them, so we can't tie an SFmode pseudos with one in another
1257 floating-point mode. */
1258
1259 #define MODES_TIEABLE_P(MODE1, MODE2) \
1260 ((MODE1) == (MODE2) \
1261 || (TARGET_SHMEDIA \
1262 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1263 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1264 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1265 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1266 && (GET_MODE_SIZE (MODE2) <= 4)) \
1267 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1268
1269 /* A C expression that is nonzero if hard register NEW_REG can be
1270 considered for use as a rename register for OLD_REG register */
1271
1272 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1273 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1274
1275 /* Specify the registers used for certain standard purposes.
1276 The values of these macros are register numbers. */
1277
1278 /* Define this if the program counter is overloaded on a register. */
1279 /* #define PC_REGNUM 15*/
1280
1281 /* Register to use for pushing function arguments. */
1282 #define STACK_POINTER_REGNUM SP_REG
1283
1284 /* Base register for access to local variables of the function. */
1285 #define HARD_FRAME_POINTER_REGNUM FP_REG
1286
1287 /* Base register for access to local variables of the function. */
1288 #define FRAME_POINTER_REGNUM 153
1289
1290 /* Fake register that holds the address on the stack of the
1291 current function's return address. */
1292 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1293
1294 /* Register to hold the addressing base for position independent
1295 code access to data items. */
1296 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1297
1298 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1299
1300 /* Value should be nonzero if functions must have frame pointers.
1301 Zero means the frame pointer need not be set up (and parms may be accessed
1302 via the stack pointer) in functions that seem suitable. */
1303
1304 #define FRAME_POINTER_REQUIRED 0
1305
1306 /* Definitions for register eliminations.
1307
1308 We have three registers that can be eliminated on the SH. First, the
1309 frame pointer register can often be eliminated in favor of the stack
1310 pointer register. Secondly, the argument pointer register can always be
1311 eliminated; it is replaced with either the stack or frame pointer.
1312 Third, there is the return address pointer, which can also be replaced
1313 with either the stack or the frame pointer. */
1314
1315 /* This is an array of structures. Each structure initializes one pair
1316 of eliminable registers. The "from" register number is given first,
1317 followed by "to". Eliminations of the same "from" register are listed
1318 in order of preference. */
1319
1320 /* If you add any registers here that are not actually hard registers,
1321 and that have any alternative of elimination that doesn't always
1322 apply, you need to amend calc_live_regs to exclude it, because
1323 reload spills all eliminable registers where it sees an
1324 can_eliminate == 0 entry, thus making them 'live' .
1325 If you add any hard registers that can be eliminated in different
1326 ways, you have to patch reload to spill them only when all alternatives
1327 of elimination fail. */
1328
1329 #define ELIMINABLE_REGS \
1330 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1331 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1332 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1333 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1334 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1335 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1336 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1337
1338 /* Given FROM and TO register numbers, say whether this elimination
1339 is allowed. */
1340 #define CAN_ELIMINATE(FROM, TO) \
1341 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1342
1343 /* Define the offset between two registers, one to be eliminated, and the other
1344 its replacement, at the start of a routine. */
1345
1346 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1347 OFFSET = initial_elimination_offset ((FROM), (TO))
1348
1349 /* Base register for access to arguments of the function. */
1350 #define ARG_POINTER_REGNUM AP_REG
1351
1352 /* Register in which the static-chain is passed to a function. */
1353 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1354
1355 /* Don't default to pcc-struct-return, because we have already specified
1356 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1357 target hook. */
1358
1359 #define DEFAULT_PCC_STRUCT_RETURN 0
1360
1361 #define SHMEDIA_REGS_STACK_ADJUST() \
1362 (TARGET_SHCOMPACT && current_function_saves_all_registers \
1363 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1364 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1365 : 0)
1366
1367 \f
1368 /* Define the classes of registers for register constraints in the
1369 machine description. Also define ranges of constants.
1370
1371 One of the classes must always be named ALL_REGS and include all hard regs.
1372 If there is more than one class, another class must be named NO_REGS
1373 and contain no registers.
1374
1375 The name GENERAL_REGS must be the name of a class (or an alias for
1376 another name such as ALL_REGS). This is the class of registers
1377 that is allowed by "g" or "r" in a register constraint.
1378 Also, registers outside this class are allocated only when
1379 instructions express preferences for them.
1380
1381 The classes must be numbered in nondecreasing order; that is,
1382 a larger-numbered class must never be contained completely
1383 in a smaller-numbered class.
1384
1385 For any two classes, it is very desirable that there be another
1386 class that represents their union. */
1387
1388 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1389 be used as the destination of some of the arithmetic ops. There are
1390 also some special purpose registers; the T bit register, the
1391 Procedure Return Register and the Multiply Accumulate Registers. */
1392 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1393 reg_class_subunion. We don't want to have an actual union class
1394 of these, because it would only be used when both classes are calculated
1395 to give the same cost, but there is only one FPUL register.
1396 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1397 applying to the actual instruction alternative considered. E.g., the
1398 y/r alternative of movsi_ie is considered to have no more cost that
1399 the r/r alternative, which is patently untrue. */
1400
1401 enum reg_class
1402 {
1403 NO_REGS,
1404 R0_REGS,
1405 PR_REGS,
1406 T_REGS,
1407 MAC_REGS,
1408 FPUL_REGS,
1409 SIBCALL_REGS,
1410 GENERAL_REGS,
1411 FP0_REGS,
1412 FP_REGS,
1413 DF_HI_REGS,
1414 DF_REGS,
1415 FPSCR_REGS,
1416 GENERAL_FP_REGS,
1417 GENERAL_DF_REGS,
1418 TARGET_REGS,
1419 ALL_REGS,
1420 LIM_REG_CLASSES
1421 };
1422
1423 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1424
1425 /* Give names of register classes as strings for dump file. */
1426 #define REG_CLASS_NAMES \
1427 { \
1428 "NO_REGS", \
1429 "R0_REGS", \
1430 "PR_REGS", \
1431 "T_REGS", \
1432 "MAC_REGS", \
1433 "FPUL_REGS", \
1434 "SIBCALL_REGS", \
1435 "GENERAL_REGS", \
1436 "FP0_REGS", \
1437 "FP_REGS", \
1438 "DF_HI_REGS", \
1439 "DF_REGS", \
1440 "FPSCR_REGS", \
1441 "GENERAL_FP_REGS", \
1442 "GENERAL_DF_REGS", \
1443 "TARGET_REGS", \
1444 "ALL_REGS", \
1445 }
1446
1447 /* Define which registers fit in which classes.
1448 This is an initializer for a vector of HARD_REG_SET
1449 of length N_REG_CLASSES. */
1450
1451 #define REG_CLASS_CONTENTS \
1452 { \
1453 /* NO_REGS: */ \
1454 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1455 /* R0_REGS: */ \
1456 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1457 /* PR_REGS: */ \
1458 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1459 /* T_REGS: */ \
1460 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1461 /* MAC_REGS: */ \
1462 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1463 /* FPUL_REGS: */ \
1464 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1465 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1466 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1467 /* GENERAL_REGS: */ \
1468 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1469 /* FP0_REGS: */ \
1470 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1471 /* FP_REGS: */ \
1472 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1473 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1474 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1475 /* DF_REGS: */ \
1476 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1477 /* FPSCR_REGS: */ \
1478 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1479 /* GENERAL_FP_REGS: */ \
1480 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1481 /* GENERAL_DF_REGS: */ \
1482 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1483 /* TARGET_REGS: */ \
1484 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1485 /* ALL_REGS: */ \
1486 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1487 }
1488
1489 /* The same information, inverted:
1490 Return the class number of the smallest class containing
1491 reg number REGNO. This could be a conditional expression
1492 or could index an array. */
1493
1494 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1495 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1496
1497 /* The following macro defines cover classes for Integrated Register
1498 Allocator. Cover classes is a set of non-intersected register
1499 classes covering all hard registers used for register allocation
1500 purpose. Any move between two registers of a cover class should be
1501 cheaper than load or store of the registers. The macro value is
1502 array of register classes with LIM_REG_CLASSES used as the end
1503 marker. */
1504
1505 #define IRA_COVER_CLASSES \
1506 { \
1507 GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \
1508 LIM_REG_CLASSES \
1509 }
1510
1511 /* When defined, the compiler allows registers explicitly used in the
1512 rtl to be used as spill registers but prevents the compiler from
1513 extending the lifetime of these registers. */
1514
1515 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1516
1517 /* The order in which register should be allocated. */
1518 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1519 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1520 spilled or used otherwise, we better have the FP_REGS allocated first. */
1521 #define REG_ALLOC_ORDER \
1522 {/* Caller-saved FPRs */ \
1523 65, 66, 67, 68, 69, 70, 71, 64, \
1524 72, 73, 74, 75, 80, 81, 82, 83, \
1525 84, 85, 86, 87, 88, 89, 90, 91, \
1526 92, 93, 94, 95, 96, 97, 98, 99, \
1527 /* Callee-saved FPRs */ \
1528 76, 77, 78, 79,100,101,102,103, \
1529 104,105,106,107,108,109,110,111, \
1530 112,113,114,115,116,117,118,119, \
1531 120,121,122,123,124,125,126,127, \
1532 136,137,138,139,140,141,142,143, \
1533 /* FPSCR */ 151, \
1534 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1535 1, 2, 3, 7, 6, 5, 4, 0, \
1536 8, 9, 17, 19, 20, 21, 22, 23, \
1537 36, 37, 38, 39, 40, 41, 42, 43, \
1538 60, 61, 62, \
1539 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1540 10, 11, 12, 13, 14, 18, \
1541 /* SH5 callee-saved GPRs */ \
1542 28, 29, 30, 31, 32, 33, 34, 35, \
1543 44, 45, 46, 47, 48, 49, 50, 51, \
1544 52, 53, 54, 55, 56, 57, 58, 59, \
1545 /* FPUL */ 150, \
1546 /* SH5 branch target registers */ \
1547 128,129,130,131,132,133,134,135, \
1548 /* Fixed registers */ \
1549 15, 16, 24, 25, 26, 27, 63,144, \
1550 145,146,147,148,149,152,153 }
1551
1552 /* The class value for index registers, and the one for base regs. */
1553 #define INDEX_REG_CLASS \
1554 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1555 #define BASE_REG_CLASS GENERAL_REGS
1556 \f
1557 /* Defines for sh.md and constraints.md. */
1558
1559 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1560 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1561 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1562 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1563 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1564 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1565 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1566 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1567
1568 #define CONST_OK_FOR_J16(VALUE) \
1569 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1570 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1571
1572 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1573 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1574
1575 /* Given an rtx X being reloaded into a reg required to be
1576 in class CLASS, return the class of reg to actually use.
1577 In general this is just CLASS; but on some machines
1578 in some cases it is preferable to use a more restrictive class. */
1579
1580 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1581 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1582 && (GET_CODE (X) == CONST_DOUBLE \
1583 || GET_CODE (X) == SYMBOL_REF \
1584 || PIC_DIRECT_ADDR_P (X)) \
1585 ? GENERAL_REGS \
1586 : (CLASS)) \
1587
1588 #if 0
1589 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1590 ((((REGCLASS_HAS_FP_REG (CLASS) \
1591 && (GET_CODE (X) == REG \
1592 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1593 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1594 && TARGET_FMOVD)))) \
1595 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1596 && GET_CODE (X) == REG \
1597 && FP_REGISTER_P (REGNO (X)))) \
1598 && ! TARGET_SHMEDIA \
1599 && ((MODE) == SFmode || (MODE) == SImode)) \
1600 ? FPUL_REGS \
1601 : (((CLASS) == FPUL_REGS \
1602 || (REGCLASS_HAS_FP_REG (CLASS) \
1603 && ! TARGET_SHMEDIA && MODE == SImode)) \
1604 && (GET_CODE (X) == MEM \
1605 || (GET_CODE (X) == REG \
1606 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1607 || REGNO (X) == T_REG \
1608 || system_reg_operand (X, VOIDmode))))) \
1609 ? GENERAL_REGS \
1610 : (((CLASS) == TARGET_REGS \
1611 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1612 && !satisfies_constraint_Csy (X) \
1613 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1614 ? GENERAL_REGS \
1615 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1616 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1617 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1618 ? GENERAL_REGS \
1619 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1620 && TARGET_REGISTER_P (REGNO (X))) \
1621 ? GENERAL_REGS : (ELSE))
1622
1623 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1624 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1625
1626 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1627 ((REGCLASS_HAS_FP_REG (CLASS) \
1628 && ! TARGET_SHMEDIA \
1629 && immediate_operand ((X), (MODE)) \
1630 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1631 && (MODE) == SFmode && fldi_ok ())) \
1632 ? R0_REGS \
1633 : ((CLASS) == FPUL_REGS \
1634 && ((GET_CODE (X) == REG \
1635 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1636 || REGNO (X) == T_REG)) \
1637 || GET_CODE (X) == PLUS)) \
1638 ? GENERAL_REGS \
1639 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1640 ? (satisfies_constraint_I08 (X) \
1641 ? GENERAL_REGS \
1642 : R0_REGS) \
1643 : ((CLASS) == FPSCR_REGS \
1644 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1645 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1646 ? GENERAL_REGS \
1647 : (REGCLASS_HAS_FP_REG (CLASS) \
1648 && TARGET_SHMEDIA \
1649 && immediate_operand ((X), (MODE)) \
1650 && (X) != CONST0_RTX (GET_MODE (X)) \
1651 && GET_MODE (X) != V4SFmode) \
1652 ? GENERAL_REGS \
1653 : (((MODE) == QImode || (MODE) == HImode) \
1654 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1655 ? GENERAL_REGS \
1656 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1657 && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
1658 ? TARGET_REGS \
1659 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1660 #endif
1661
1662 /* Return the maximum number of consecutive registers
1663 needed to represent mode MODE in a register of class CLASS.
1664
1665 If TARGET_SHMEDIA, we need two FP registers per word.
1666 Otherwise we will need at most one register per word. */
1667 #define CLASS_MAX_NREGS(CLASS, MODE) \
1668 (TARGET_SHMEDIA \
1669 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1670 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1671 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1672
1673 /* If defined, gives a class of registers that cannot be used as the
1674 operand of a SUBREG that changes the mode of the object illegally. */
1675 /* ??? We need to renumber the internal numbers for the frnn registers
1676 when in little endian in order to allow mode size changes. */
1677
1678 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1679 sh_cannot_change_mode_class (FROM, TO, CLASS)
1680 \f
1681 /* Stack layout; function entry, exit and calling. */
1682
1683 /* Define the number of registers that can hold parameters.
1684 These macros are used only in other macro definitions below. */
1685
1686 #define NPARM_REGS(MODE) \
1687 (TARGET_FPU_ANY && (MODE) == SFmode \
1688 ? (TARGET_SH5 ? 12 : 8) \
1689 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1690 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1691 ? (TARGET_SH5 ? 12 : 8) \
1692 : (TARGET_SH5 ? 8 : 4))
1693
1694 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1695 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1696
1697 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1698 #define FIRST_FP_RET_REG FIRST_FP_REG
1699
1700 /* Define this if pushing a word on the stack
1701 makes the stack pointer a smaller address. */
1702 #define STACK_GROWS_DOWNWARD
1703
1704 /* Define this macro to nonzero if the addresses of local variable slots
1705 are at negative offsets from the frame pointer. */
1706 #define FRAME_GROWS_DOWNWARD 1
1707
1708 /* Offset from the frame pointer to the first local variable slot to
1709 be allocated. */
1710 #define STARTING_FRAME_OFFSET 0
1711
1712 /* If we generate an insn to push BYTES bytes,
1713 this says how many the stack pointer really advances by. */
1714 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1715 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1716 do correct alignment. */
1717 #if 0
1718 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1719 #endif
1720
1721 /* Offset of first parameter from the argument pointer register value. */
1722 #define FIRST_PARM_OFFSET(FNDECL) 0
1723
1724 /* Value is the number of byte of arguments automatically
1725 popped when returning from a subroutine call.
1726 FUNDECL is the declaration node of the function (as a tree),
1727 FUNTYPE is the data type of the function (as a tree),
1728 or for a library call it is an identifier node for the subroutine name.
1729 SIZE is the number of bytes of arguments passed on the stack.
1730
1731 On the SH, the caller does not pop any of its arguments that were passed
1732 on the stack. */
1733 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1734
1735 /* Value is the number of bytes of arguments automatically popped when
1736 calling a subroutine.
1737 CUM is the accumulated argument list.
1738
1739 On SHcompact, the call trampoline pops arguments off the stack. */
1740 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1741
1742 /* Some subroutine macros specific to this machine. */
1743
1744 #define BASE_RETURN_VALUE_REG(MODE) \
1745 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1746 ? FIRST_FP_RET_REG \
1747 : TARGET_FPU_ANY && (MODE) == SCmode \
1748 ? FIRST_FP_RET_REG \
1749 : (TARGET_FPU_DOUBLE \
1750 && ((MODE) == DFmode || (MODE) == SFmode \
1751 || (MODE) == DCmode || (MODE) == SCmode )) \
1752 ? FIRST_FP_RET_REG \
1753 : FIRST_RET_REG)
1754
1755 #define BASE_ARG_REG(MODE) \
1756 ((TARGET_SH2E && ((MODE) == SFmode)) \
1757 ? FIRST_FP_PARM_REG \
1758 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1759 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1760 ? FIRST_FP_PARM_REG \
1761 : FIRST_PARM_REG)
1762
1763 /* Define how to find the value returned by a function.
1764 VALTYPE is the data type of the value (as a tree).
1765 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1766 otherwise, FUNC is 0.
1767 For the SH, this is like LIBCALL_VALUE, except that we must change the
1768 mode like PROMOTE_MODE does.
1769 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1770 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1771
1772 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1773 gen_rtx_REG ( \
1774 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1775 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1776 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1777 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1778 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1779 || TREE_CODE (VALTYPE) == REAL_TYPE \
1780 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1781 && sh_promote_prototypes (VALTYPE) \
1782 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1783 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1784
1785 /* Define how to find the value returned by a library function
1786 assuming the value has mode MODE. */
1787 #define LIBCALL_VALUE(MODE) \
1788 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1789
1790 /* 1 if N is a possible register number for a function value. */
1791 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1792 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1793 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1794
1795 /* 1 if N is a possible register number for function argument passing. */
1796 /* ??? There are some callers that pass REGNO as int, and others that pass
1797 it as unsigned. We get warnings unless we do casts everywhere. */
1798 #define FUNCTION_ARG_REGNO_P(REGNO) \
1799 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1800 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1801 || (TARGET_FPU_ANY \
1802 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1803 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1804 + NPARM_REGS (SFmode))))
1805 \f
1806 /* Define a data type for recording info about an argument list
1807 during the scan of that argument list. This data type should
1808 hold all necessary information about the function itself
1809 and about the args processed so far, enough to enable macros
1810 such as FUNCTION_ARG to determine where the next arg should go.
1811
1812 On SH, this is a single integer, which is a number of words
1813 of arguments scanned so far (including the invisible argument,
1814 if any, which holds the structure-value-address).
1815 Thus NARGREGS or more means all following args should go on the stack. */
1816
1817 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1818 struct sh_args {
1819 int arg_count[2];
1820 int force_mem;
1821 /* Nonzero if a prototype is available for the function. */
1822 int prototype_p;
1823 /* The number of an odd floating-point register, that should be used
1824 for the next argument of type float. */
1825 int free_single_fp_reg;
1826 /* Whether we're processing an outgoing function call. */
1827 int outgoing;
1828 /* The number of general-purpose registers that should have been
1829 used to pass partial arguments, that are passed totally on the
1830 stack. On SHcompact, a call trampoline will pop them off the
1831 stack before calling the actual function, and, if the called
1832 function is implemented in SHcompact mode, the incoming arguments
1833 decoder will push such arguments back onto the stack. For
1834 incoming arguments, STACK_REGS also takes into account other
1835 arguments passed by reference, that the decoder will also push
1836 onto the stack. */
1837 int stack_regs;
1838 /* The number of general-purpose registers that should have been
1839 used to pass arguments, if the arguments didn't have to be passed
1840 by reference. */
1841 int byref_regs;
1842 /* Set as by shcompact_byref if the current argument is to be passed
1843 by reference. */
1844 int byref;
1845
1846 /* call_cookie is a bitmask used by call expanders, as well as
1847 function prologue and epilogues, to allow SHcompact to comply
1848 with the SH5 32-bit ABI, that requires 64-bit registers to be
1849 used even though only the lower 32-bit half is visible in
1850 SHcompact mode. The strategy is to call SHmedia trampolines.
1851
1852 The alternatives for each of the argument-passing registers are
1853 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1854 contents from the address in it; (d) add 8 to it, storing the
1855 result in the next register, then (c); (e) copy it from some
1856 floating-point register,
1857
1858 Regarding copies from floating-point registers, r2 may only be
1859 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1860 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1861 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1862 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1863 dr10.
1864
1865 The bit mask is structured as follows:
1866
1867 - 1 bit to tell whether to set up a return trampoline.
1868
1869 - 3 bits to count the number consecutive registers to pop off the
1870 stack.
1871
1872 - 4 bits for each of r9, r8, r7 and r6.
1873
1874 - 3 bits for each of r5, r4, r3 and r2.
1875
1876 - 3 bits set to 0 (the most significant ones)
1877
1878 3 2 1 0
1879 1098 7654 3210 9876 5432 1098 7654 3210
1880 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1881 2223 3344 4555 6666 7777 8888 9999 SSS-
1882
1883 - If F is set, the register must be copied from an FP register,
1884 whose number is encoded in the remaining bits.
1885
1886 - Else, if L is set, the register must be loaded from the address
1887 contained in it. If the P bit is *not* set, the address of the
1888 following dword should be computed first, and stored in the
1889 following register.
1890
1891 - Else, if P is set, the register alone should be popped off the
1892 stack.
1893
1894 - After all this processing, the number of registers represented
1895 in SSS will be popped off the stack. This is an optimization
1896 for pushing/popping consecutive registers, typically used for
1897 varargs and large arguments partially passed in registers.
1898
1899 - If T is set, a return trampoline will be set up for 64-bit
1900 return values to be split into 2 32-bit registers. */
1901 long call_cookie;
1902
1903 /* This is set to nonzero when the call in question must use the Renesas ABI,
1904 even without the -mrenesas option. */
1905 int renesas_abi;
1906 };
1907
1908 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1909 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1910 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1911 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1912 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1913 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1914 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1915 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1916 #define CALL_COOKIE_INT_REG(REG, VAL) \
1917 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1918 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1919 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1920
1921 #define CUMULATIVE_ARGS struct sh_args
1922
1923 #define GET_SH_ARG_CLASS(MODE) \
1924 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1925 ? SH_ARG_FLOAT \
1926 /* There's no mention of complex float types in the SH5 ABI, so we
1927 should presumably handle them as aggregate types. */ \
1928 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1929 ? SH_ARG_INT \
1930 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1931 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1932 ? SH_ARG_FLOAT : SH_ARG_INT)
1933
1934 #define ROUND_ADVANCE(SIZE) \
1935 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1936
1937 /* Round a register number up to a proper boundary for an arg of mode
1938 MODE.
1939
1940 The SH doesn't care about double alignment, so we only
1941 round doubles to even regs when asked to explicitly. */
1942
1943 #define ROUND_REG(CUM, MODE) \
1944 (((TARGET_ALIGN_DOUBLE \
1945 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1946 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1947 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1948 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1949 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1950 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1951
1952 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1953 for a call to a function whose data type is FNTYPE.
1954 For a library call, FNTYPE is 0.
1955
1956 On SH, the offset always starts at 0: the first parm reg is always
1957 the same reg for a given argument class.
1958
1959 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1960
1961 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1962 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1963
1964 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1965 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1966
1967 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1968 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1969 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1970 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1971
1972 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1973 This macro is only used in this file. */
1974
1975 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1976 (((TYPE) == 0 \
1977 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1978 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1979 || ! (AGGREGATE_TYPE_P (TYPE) \
1980 || (!TARGET_FPU_ANY \
1981 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1982 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1983 && ! (CUM).force_mem \
1984 && (TARGET_SH2E \
1985 ? ((MODE) == BLKmode \
1986 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1987 + int_size_in_bytes (TYPE)) \
1988 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1989 : ((ROUND_REG((CUM), (MODE)) \
1990 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1991 <= NPARM_REGS (MODE))) \
1992 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1993
1994 /* By accident we got stuck with passing SCmode on SH4 little endian
1995 in two registers that are nominally successive - which is different from
1996 two single SFmode values, where we take endianness translation into
1997 account. That does not work at all if an odd number of registers is
1998 already in use, so that got fixed, but library functions are still more
1999 likely to use complex numbers without mixing them with SFmode arguments
2000 (which in C would have to be structures), so for the sake of ABI
2001 compatibility the way SCmode values are passed when an even number of
2002 FP registers is in use remains different from a pair of SFmode values for
2003 now.
2004 I.e.:
2005 foo (double); a: fr5,fr4
2006 foo (float a, float b); a: fr5 b: fr4
2007 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2008 this should be the other way round...
2009 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2010 #define FUNCTION_ARG_SCmode_WART 1
2011
2012 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2013 register in SHcompact mode, it must be padded in the most
2014 significant end. This means that passing it by reference wouldn't
2015 pad properly on a big-endian machine. In this particular case, we
2016 pass this argument on the stack, in a way that the call trampoline
2017 will load its value into the appropriate register. */
2018 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2019 ((MODE) == BLKmode \
2020 && TARGET_SHCOMPACT \
2021 && ! TARGET_LITTLE_ENDIAN \
2022 && int_size_in_bytes (TYPE) > 4 \
2023 && int_size_in_bytes (TYPE) < 8)
2024
2025 /* Minimum alignment for an argument to be passed by callee-copy
2026 reference. We need such arguments to be aligned to 8 byte
2027 boundaries, because they'll be loaded using quad loads. */
2028 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2029
2030 /* The SH5 ABI requires floating-point arguments to be passed to
2031 functions without a prototype in both an FP register and a regular
2032 register or the stack. When passing the argument in both FP and
2033 general-purpose registers, list the FP register first. */
2034 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2035 (gen_rtx_PARALLEL \
2036 ((MODE), \
2037 gen_rtvec (2, \
2038 gen_rtx_EXPR_LIST \
2039 (VOIDmode, \
2040 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2041 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2042 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2043 : NULL_RTX), \
2044 const0_rtx), \
2045 gen_rtx_EXPR_LIST \
2046 (VOIDmode, \
2047 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2048 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2049 + (CUM).arg_count[(int) SH_ARG_INT]) \
2050 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2051 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2052 const0_rtx))))
2053
2054 /* The SH5 ABI requires regular registers or stack slots to be
2055 reserved for floating-point arguments. Registers are taken care of
2056 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2057 Unfortunately, there's no way to just reserve a stack slot, so
2058 we'll end up needlessly storing a copy of the argument in the
2059 stack. For incoming arguments, however, the PARALLEL will be
2060 optimized to the register-only form, and the value in the stack
2061 slot won't be used at all. */
2062 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2063 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2064 ? gen_rtx_REG ((MODE), (REG)) \
2065 : gen_rtx_PARALLEL ((MODE), \
2066 gen_rtvec (2, \
2067 gen_rtx_EXPR_LIST \
2068 (VOIDmode, NULL_RTX, \
2069 const0_rtx), \
2070 gen_rtx_EXPR_LIST \
2071 (VOIDmode, gen_rtx_REG ((MODE), \
2072 (REG)), \
2073 const0_rtx))))
2074
2075 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2076 (TARGET_SH5 \
2077 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2078 || (MODE) == DCmode) \
2079 && ((CUM).arg_count[(int) SH_ARG_INT] \
2080 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2081 : GET_MODE_SIZE (MODE)) \
2082 + 7) / 8) > NPARM_REGS (SImode))
2083
2084 /* Perform any needed actions needed for a function that is receiving a
2085 variable number of arguments. */
2086
2087 /* Call the function profiler with a given profile label.
2088 We use two .aligns, so as to make sure that both the .long is aligned
2089 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2090 from the trapa instruction. */
2091
2092 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2093 { \
2094 if (TARGET_SHMEDIA) \
2095 { \
2096 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2097 fprintf((STREAM), "\ttrapa\tr0\n"); \
2098 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2099 } \
2100 else \
2101 { \
2102 fprintf((STREAM), "\t.align\t2\n"); \
2103 fprintf((STREAM), "\ttrapa\t#33\n"); \
2104 fprintf((STREAM), "\t.align\t2\n"); \
2105 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2106 } \
2107 }
2108
2109 /* Define this macro if the code for function profiling should come
2110 before the function prologue. Normally, the profiling code comes
2111 after. */
2112
2113 #define PROFILE_BEFORE_PROLOGUE
2114
2115 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2116 the stack pointer does not matter. The value is tested only in
2117 functions that have frame pointers.
2118 No definition is equivalent to always zero. */
2119
2120 #define EXIT_IGNORE_STACK 1
2121
2122 /*
2123 On the SH, the trampoline looks like
2124 2 0002 D202 mov.l l2,r2
2125 1 0000 D301 mov.l l1,r3
2126 3 0004 422B jmp @r2
2127 4 0006 0009 nop
2128 5 0008 00000000 l1: .long area
2129 6 000c 00000000 l2: .long function */
2130
2131 /* Length in units of the trampoline for entering a nested function. */
2132 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2133
2134 /* Alignment required for a trampoline in bits . */
2135 #define TRAMPOLINE_ALIGNMENT \
2136 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2137 : TARGET_SHMEDIA ? 256 : 64)
2138
2139 /* Emit RTL insns to initialize the variable parts of a trampoline.
2140 FNADDR is an RTX for the address of the function's pure code.
2141 CXT is an RTX for the static chain value for the function. */
2142
2143 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2144 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2145
2146 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2147
2148 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2149 { \
2150 if (TARGET_SHMEDIA) \
2151 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2152 gen_reg_rtx (Pmode), 0, \
2153 OPTAB_LIB_WIDEN); \
2154 } while (0)
2155
2156 /* A C expression whose value is RTL representing the value of the return
2157 address for the frame COUNT steps up from the current frame.
2158 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2159 can ignore COUNT. */
2160
2161 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2162 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2163
2164 /* A C expression whose value is RTL representing the location of the
2165 incoming return address at the beginning of any function, before the
2166 prologue. This RTL is either a REG, indicating that the return
2167 value is saved in REG, or a MEM representing a location in
2168 the stack. */
2169 #define INCOMING_RETURN_ADDR_RTX \
2170 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2171 \f
2172 /* Addressing modes, and classification of registers for them. */
2173 #define HAVE_POST_INCREMENT TARGET_SH1
2174 #define HAVE_PRE_DECREMENT TARGET_SH1
2175
2176 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2177 ? 0 : TARGET_SH1)
2178 #define USE_LOAD_PRE_DECREMENT(mode) 0
2179 #define USE_STORE_POST_INCREMENT(mode) 0
2180 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2181 ? 0 : TARGET_SH1)
2182
2183 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2184 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2185 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2186
2187 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2188 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2189 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2190
2191 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
2192
2193 /* Macros to check register numbers against specific register classes. */
2194
2195 /* These assume that REGNO is a hard or pseudo reg number.
2196 They give nonzero only if REGNO is a hard reg of the suitable class
2197 or a pseudo reg currently allocated to a suitable hard reg.
2198 Since they use reg_renumber, they are safe only once reg_renumber
2199 has been allocated, which happens in local-alloc.c. */
2200
2201 #define REGNO_OK_FOR_BASE_P(REGNO) \
2202 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2203 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2204 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2205 (TARGET_SHMEDIA \
2206 ? (GENERAL_REGISTER_P (REGNO) \
2207 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2208 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2209
2210 /* Maximum number of registers that can appear in a valid memory
2211 address. */
2212
2213 #define MAX_REGS_PER_ADDRESS 2
2214
2215 /* Recognize any constant value that is a valid address. */
2216
2217 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2218
2219 /* Nonzero if the constant value X is a legitimate general operand. */
2220 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
2221
2222 #define LEGITIMATE_CONSTANT_P(X) \
2223 (TARGET_SHMEDIA \
2224 ? ((GET_MODE (X) != DFmode \
2225 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2226 || (X) == CONST0_RTX (GET_MODE (X)) \
2227 || ! TARGET_SHMEDIA_FPU \
2228 || TARGET_SHMEDIA64) \
2229 : (GET_CODE (X) != CONST_DOUBLE \
2230 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2231 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
2232
2233 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2234 and check its validity for a certain class.
2235 We have two alternate definitions for each of them.
2236 The usual definition accepts all pseudo regs; the other rejects
2237 them unless they have been allocated suitable hard regs.
2238 The symbol REG_OK_STRICT causes the latter definition to be used. */
2239
2240 #ifndef REG_OK_STRICT
2241
2242 /* Nonzero if X is a hard reg that can be used as a base reg
2243 or if it is a pseudo reg. */
2244 #define REG_OK_FOR_BASE_P(X) \
2245 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2246
2247 /* Nonzero if X is a hard reg that can be used as an index
2248 or if it is a pseudo reg. */
2249 #define REG_OK_FOR_INDEX_P(X) \
2250 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2251 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2252
2253 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2254 or if X is a pseudo reg. */
2255 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2256 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2257 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2258
2259 #else
2260
2261 /* Nonzero if X is a hard reg that can be used as a base reg. */
2262 #define REG_OK_FOR_BASE_P(X) \
2263 REGNO_OK_FOR_BASE_P (REGNO (X))
2264
2265 /* Nonzero if X is a hard reg that can be used as an index. */
2266 #define REG_OK_FOR_INDEX_P(X) \
2267 REGNO_OK_FOR_INDEX_P (REGNO (X))
2268
2269 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2270 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2271 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2272
2273 #endif
2274
2275 /* Macros for extra constraints. */
2276
2277 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
2278 ((GET_CODE ((OP)) == LABEL_REF) \
2279 || (GET_CODE ((OP)) == CONST \
2280 && GET_CODE (XEXP ((OP), 0)) == PLUS \
2281 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2282 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2283
2284 #define IS_LITERAL_OR_SYMBOLIC_S16_P(OP) \
2285 (GET_CODE ((OP)) == SIGN_EXTEND \
2286 && (GET_MODE ((OP)) == DImode \
2287 || GET_MODE ((OP)) == SImode) \
2288 && GET_CODE (XEXP ((OP), 0)) == TRUNCATE \
2289 && GET_MODE (XEXP ((OP), 0)) == HImode \
2290 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP ((OP), 0), 0)) \
2291 || (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == ASHIFTRT \
2292 && (MOVI_SHORI_BASE_OPERAND_P \
2293 (XEXP (XEXP (XEXP ((OP), 0), 0), 0))) \
2294 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2295
2296 #define IS_LITERAL_OR_SYMBOLIC_U16_P(OP) \
2297 (GET_CODE ((OP)) == ZERO_EXTEND \
2298 && (GET_MODE ((OP)) == DImode \
2299 || GET_MODE ((OP)) == SImode) \
2300 && GET_CODE (XEXP ((OP), 0)) == TRUNCATE \
2301 && GET_MODE (XEXP ((OP), 0)) == HImode \
2302 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP ((OP), 0), 0)) \
2303 || (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == ASHIFTRT \
2304 && (MOVI_SHORI_BASE_OPERAND_P \
2305 (XEXP (XEXP (XEXP ((OP), 0), 0), 0))) \
2306 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2307
2308 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
2309 (CONSTANT_P (OP) \
2310 && GET_CODE (OP) != CONST_INT \
2311 && GET_CODE (OP) != CONST_DOUBLE \
2312 && (!flag_pic \
2313 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2314 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2315 && GET_CODE (OP) != LABEL_REF)))
2316
2317 /* Check whether OP is a datalabel unspec. */
2318 #define DATALABEL_REF_NO_CONST_P(OP) \
2319 (GET_CODE (OP) == UNSPEC \
2320 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2321 && XVECLEN ((OP), 0) == 1 \
2322 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2323
2324 #define GOT_ENTRY_P(OP) \
2325 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2326 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2327
2328 #define GOTPLT_ENTRY_P(OP) \
2329 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2330 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2331
2332 #define UNSPEC_GOTOFF_P(OP) \
2333 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2334
2335 #define GOTOFF_P(OP) \
2336 (GET_CODE (OP) == CONST \
2337 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2338 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2339 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2340 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2341
2342 #define PIC_ADDR_P(OP) \
2343 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2344 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2345
2346 #define PIC_OFFSET_P(OP) \
2347 (PIC_ADDR_P (OP) \
2348 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2349 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2350
2351 #define PIC_DIRECT_ADDR_P(OP) \
2352 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2353
2354 #define NON_PIC_REFERENCE_P(OP) \
2355 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2356 || (GET_CODE (OP) == CONST \
2357 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2358 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2359 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2360 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2361 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2362 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2363 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2364 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2365
2366 #define PIC_REFERENCE_P(OP) \
2367 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2368 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2369
2370 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2371 (flag_pic \
2372 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2373 || PIC_OFFSET_P (OP)) \
2374 : NON_PIC_REFERENCE_P (OP))
2375 \f
2376 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2377 that is a valid memory address for an instruction.
2378 The MODE argument is the machine mode for the MEM expression
2379 that wants to use this address. */
2380
2381 #define MODE_DISP_OK_4(X,MODE) \
2382 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2383 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2384
2385 #define MODE_DISP_OK_8(X,MODE) \
2386 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2387 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2388
2389 #undef MODE_DISP_OK_4
2390 #define MODE_DISP_OK_4(X,MODE) \
2391 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2392 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2393 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2394 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2395
2396 #undef MODE_DISP_OK_8
2397 #define MODE_DISP_OK_8(X,MODE) \
2398 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2399 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2400 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2401 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2402
2403 #define BASE_REGISTER_RTX_P(X) \
2404 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2405 || (GET_CODE (X) == SUBREG \
2406 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2407 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2408 && GET_CODE (SUBREG_REG (X)) == REG \
2409 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2410
2411 /* Since this must be r0, which is a single register class, we must check
2412 SUBREGs more carefully, to be sure that we don't accept one that extends
2413 outside the class. */
2414 #define INDEX_REGISTER_RTX_P(X) \
2415 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2416 || (GET_CODE (X) == SUBREG \
2417 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2418 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2419 && GET_CODE (SUBREG_REG (X)) == REG \
2420 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2421
2422 /* Jump to LABEL if X is a valid address RTX. This must also take
2423 REG_OK_STRICT into account when deciding about valid registers, but it uses
2424 the above macros so we are in luck.
2425
2426 Allow REG
2427 REG+disp
2428 REG+r0
2429 REG++
2430 --REG */
2431
2432 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2433 into the FRx registers. We implement this by setting the maximum offset
2434 to zero when the value is SFmode. This also restricts loading of SFmode
2435 values into the integer registers, but that can't be helped. */
2436
2437 /* The SH allows a displacement in a QI or HI amode, but only when the
2438 other operand is R0. GCC doesn't handle this very well, so we forgo
2439 all of that.
2440
2441 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2442 DI can be any number 0..60. */
2443
2444 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2445 do { \
2446 if (GET_CODE (OP) == CONST_INT) \
2447 { \
2448 if (TARGET_SHMEDIA) \
2449 { \
2450 int MODE_SIZE; \
2451 /* Check if this the address of an unaligned load / store. */\
2452 if ((MODE) == VOIDmode) \
2453 { \
2454 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2455 goto LABEL; \
2456 break; \
2457 } \
2458 MODE_SIZE = GET_MODE_SIZE (MODE); \
2459 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2460 && INTVAL (OP) >= -512 * MODE_SIZE \
2461 && INTVAL (OP) < 512 * MODE_SIZE) \
2462 goto LABEL; \
2463 else \
2464 break; \
2465 } \
2466 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2467 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2468 } \
2469 } while(0)
2470
2471 #define ALLOW_INDEXED_ADDRESS \
2472 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2473
2474 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2475 { \
2476 if (BASE_REGISTER_RTX_P (X)) \
2477 goto LABEL; \
2478 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2479 && ! TARGET_SHMEDIA \
2480 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2481 goto LABEL; \
2482 else if (GET_CODE (X) == PLUS \
2483 && ((MODE) != PSImode || reload_completed)) \
2484 { \
2485 rtx xop0 = XEXP ((X), 0); \
2486 rtx xop1 = XEXP ((X), 1); \
2487 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2488 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2489 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2490 || ((xop0 == stack_pointer_rtx \
2491 || xop0 == hard_frame_pointer_rtx) \
2492 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2493 || ((xop1 == stack_pointer_rtx \
2494 || xop1 == hard_frame_pointer_rtx) \
2495 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2496 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2497 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2498 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2499 && TARGET_FMOVD && MODE == DFmode))) \
2500 { \
2501 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2502 goto LABEL; \
2503 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2504 goto LABEL; \
2505 } \
2506 } \
2507 }
2508 \f
2509 /* Try machine-dependent ways of modifying an illegitimate address
2510 to be legitimate. If we find one, return the new, valid address.
2511 This macro is used in only one place: `memory_address' in explow.c.
2512
2513 OLDX is the address as it was before break_out_memory_refs was called.
2514 In some cases it is useful to look at this to decide what needs to be done.
2515
2516 MODE and WIN are passed so that this macro can use
2517 GO_IF_LEGITIMATE_ADDRESS.
2518
2519 It is always safe for this macro to do nothing. It exists to recognize
2520 opportunities to optimize the output.
2521
2522 For the SH, if X is almost suitable for indexing, but the offset is
2523 out of range, convert it into a normal form so that cse has a chance
2524 of reducing the number of address registers used. */
2525
2526 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2527 { \
2528 if (flag_pic) \
2529 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2530 if (GET_CODE (X) == PLUS \
2531 && (GET_MODE_SIZE (MODE) == 4 \
2532 || GET_MODE_SIZE (MODE) == 8) \
2533 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2534 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2535 && ! TARGET_SHMEDIA \
2536 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2537 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2538 { \
2539 rtx index_rtx = XEXP ((X), 1); \
2540 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2541 rtx sum; \
2542 \
2543 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2544 /* On rare occasions, we might get an unaligned pointer \
2545 that is indexed in a way to give an aligned address. \
2546 Therefore, keep the lower two bits in offset_base. */ \
2547 /* Instead of offset_base 128..131 use 124..127, so that \
2548 simple add suffices. */ \
2549 if (offset > 127) \
2550 { \
2551 offset_base = ((offset + 4) & ~60) - 4; \
2552 } \
2553 else \
2554 offset_base = offset & ~60; \
2555 /* Sometimes the normal form does not suit DImode. We \
2556 could avoid that by using smaller ranges, but that \
2557 would give less optimized code when SImode is \
2558 prevalent. */ \
2559 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2560 { \
2561 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2562 GEN_INT (offset_base), NULL_RTX, 0, \
2563 OPTAB_LIB_WIDEN); \
2564 \
2565 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2566 goto WIN; \
2567 } \
2568 } \
2569 }
2570
2571 /* A C compound statement that attempts to replace X, which is an address
2572 that needs reloading, with a valid memory address for an operand of
2573 mode MODE. WIN is a C statement label elsewhere in the code.
2574
2575 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2576 of the address. That will allow inheritance of the address reloads. */
2577
2578 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2579 { \
2580 if (GET_CODE (X) == PLUS \
2581 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2582 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2583 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2584 && ! TARGET_SHMEDIA \
2585 && ! (TARGET_SH4 && (MODE) == DFmode) \
2586 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2587 && (ALLOW_INDEXED_ADDRESS \
2588 || XEXP ((X), 0) == stack_pointer_rtx \
2589 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2590 { \
2591 rtx index_rtx = XEXP (X, 1); \
2592 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2593 rtx sum; \
2594 \
2595 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2596 { \
2597 push_reload (X, NULL_RTX, &X, NULL, \
2598 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2599 (TYPE)); \
2600 goto WIN; \
2601 } \
2602 if (TARGET_SH2E && MODE == SFmode) \
2603 { \
2604 X = copy_rtx (X); \
2605 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2606 R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2607 (TYPE)); \
2608 goto WIN; \
2609 } \
2610 /* Instead of offset_base 128..131 use 124..127, so that \
2611 simple add suffices. */ \
2612 if (offset > 127) \
2613 { \
2614 offset_base = ((offset + 4) & ~60) - 4; \
2615 } \
2616 else \
2617 offset_base = offset & ~60; \
2618 /* Sometimes the normal form does not suit DImode. We \
2619 could avoid that by using smaller ranges, but that \
2620 would give less optimized code when SImode is \
2621 prevalent. */ \
2622 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2623 { \
2624 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2625 GEN_INT (offset_base)); \
2626 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2627 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2628 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2629 (TYPE)); \
2630 goto WIN; \
2631 } \
2632 } \
2633 /* We must re-recognize what we created before. */ \
2634 else if (GET_CODE (X) == PLUS \
2635 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2636 && GET_CODE (XEXP (X, 0)) == PLUS \
2637 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2638 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2639 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2640 && ! TARGET_SHMEDIA \
2641 && ! (TARGET_SH2E && MODE == SFmode)) \
2642 { \
2643 /* Because this address is so complex, we know it must have \
2644 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2645 it is already unshared, and needs no further unsharing. */ \
2646 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2647 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2648 goto WIN; \
2649 } \
2650 }
2651
2652 /* Go to LABEL if ADDR (a legitimate address expression)
2653 has an effect that depends on the machine mode it is used for.
2654
2655 ??? Strictly speaking, we should also include all indexed addressing,
2656 because the index scale factor is the length of the operand.
2657 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2658 high if we did that. So we rely on reload to fix things up.
2659
2660 Auto-increment addressing is now treated in recog.c. */
2661
2662 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2663 \f
2664 /* Specify the machine mode that this machine uses
2665 for the index in the tablejump instruction. */
2666 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2667
2668 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2669 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2670 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2671 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2672 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2673 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2674 : SImode)
2675
2676 /* Define as C expression which evaluates to nonzero if the tablejump
2677 instruction expects the table to contain offsets from the address of the
2678 table.
2679 Do not define this if the table should contain absolute addresses. */
2680 #define CASE_VECTOR_PC_RELATIVE 1
2681
2682 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2683 #define FLOAT_TYPE_SIZE 32
2684
2685 /* Since the SH2e has only `float' support, it is desirable to make all
2686 floating point types equivalent to `float'. */
2687 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2688
2689 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH4_SINGLE_ONLY__)
2690 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2691 #else
2692 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2693 #endif
2694
2695 /* 'char' is signed by default. */
2696 #define DEFAULT_SIGNED_CHAR 1
2697
2698 /* The type of size_t unsigned int. */
2699 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2700
2701 #undef PTRDIFF_TYPE
2702 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2703
2704 #define WCHAR_TYPE "short unsigned int"
2705 #define WCHAR_TYPE_SIZE 16
2706
2707 #define SH_ELF_WCHAR_TYPE "long int"
2708
2709 /* Max number of bytes we can move from memory to memory
2710 in one reasonably fast instruction. */
2711 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2712
2713 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2714 MOVE_MAX is not a compile-time constant. */
2715 #define MAX_MOVE_MAX 8
2716
2717 /* Max number of bytes we want move_by_pieces to be able to copy
2718 efficiently. */
2719 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2720
2721 /* Define if operations between registers always perform the operation
2722 on the full register even if a narrower mode is specified. */
2723 #define WORD_REGISTER_OPERATIONS
2724
2725 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2726 will either zero-extend or sign-extend. The value of this macro should
2727 be the code that says which one of the two operations is implicitly
2728 done, UNKNOWN if none. */
2729 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2730 /* FP registers can load SImode values, but don't implicitly sign-extend
2731 them to DImode. */
2732 #define LOAD_EXTEND_OP(MODE) \
2733 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2734 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2735
2736 /* Define if loading short immediate values into registers sign extends. */
2737 #define SHORT_IMMEDIATES_SIGN_EXTEND
2738
2739 /* Nonzero if access to memory by bytes is no faster than for words. */
2740 #define SLOW_BYTE_ACCESS 1
2741
2742 /* Immediate shift counts are truncated by the output routines (or was it
2743 the assembler?). Shift counts in a register are truncated by SH. Note
2744 that the native compiler puts too large (> 32) immediate shift counts
2745 into a register and shifts by the register, letting the SH decide what
2746 to do instead of doing that itself. */
2747 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2748 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2749 expects - the sign bit is significant - so it appears that we need to
2750 leave this zero for correct SH3 code. */
2751 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2752
2753 /* All integers have the same format so truncation is easy. */
2754 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2755 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2756 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2757
2758 /* Define this if addresses of constant functions
2759 shouldn't be put through pseudo regs where they can be cse'd.
2760 Desirable on machines where ordinary constants are expensive
2761 but a CALL with constant address is cheap. */
2762 /*#define NO_FUNCTION_CSE 1*/
2763
2764 /* The machine modes of pointers and functions. */
2765 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2766 #define FUNCTION_MODE Pmode
2767
2768 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2769 are actually function calls with some special constraints on arguments
2770 and register usage.
2771
2772 These macros tell reorg that the references to arguments and
2773 register clobbers for insns of type sfunc do not appear to happen
2774 until after the millicode call. This allows reorg to put insns
2775 which set the argument registers into the delay slot of the millicode
2776 call -- thus they act more like traditional CALL_INSNs.
2777
2778 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2779 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2780 in particular. */
2781
2782 #define INSN_SETS_ARE_DELAYED(X) \
2783 ((GET_CODE (X) == INSN \
2784 && GET_CODE (PATTERN (X)) != SEQUENCE \
2785 && GET_CODE (PATTERN (X)) != USE \
2786 && GET_CODE (PATTERN (X)) != CLOBBER \
2787 && get_attr_is_sfunc (X)))
2788
2789 #define INSN_REFERENCES_ARE_DELAYED(X) \
2790 ((GET_CODE (X) == INSN \
2791 && GET_CODE (PATTERN (X)) != SEQUENCE \
2792 && GET_CODE (PATTERN (X)) != USE \
2793 && GET_CODE (PATTERN (X)) != CLOBBER \
2794 && get_attr_is_sfunc (X)))
2795
2796 \f
2797 /* Position Independent Code. */
2798
2799 /* We can't directly access anything that contains a symbol,
2800 nor can we indirect via the constant pool. */
2801 #define LEGITIMATE_PIC_OPERAND_P(X) \
2802 ((! nonpic_symbol_mentioned_p (X) \
2803 && (GET_CODE (X) != SYMBOL_REF \
2804 || ! CONSTANT_POOL_ADDRESS_P (X) \
2805 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2806 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2807
2808 #define SYMBOLIC_CONST_P(X) \
2809 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2810 && nonpic_symbol_mentioned_p (X))
2811 \f
2812 /* Compute extra cost of moving data between one register class
2813 and another. */
2814
2815 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2816 uses this information. Hence, the general register <-> floating point
2817 register information here is not used for SFmode. */
2818
2819 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2820 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2821 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2822
2823 #define REGCLASS_HAS_FP_REG(CLASS) \
2824 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2825 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2826
2827 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2828 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2829
2830 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2831 would be so that people with slow memory systems could generate
2832 different code that does fewer memory accesses. */
2833
2834 /* A C expression for the cost of a branch instruction. A value of 1
2835 is the default; other values are interpreted relative to that.
2836 The SH1 does not have delay slots, hence we get a pipeline stall
2837 at every branch. The SH4 is superscalar, so the single delay slot
2838 is not sufficient to keep both pipelines filled. */
2839 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2840 \f
2841 /* Assembler output control. */
2842
2843 /* A C string constant describing how to begin a comment in the target
2844 assembler language. The compiler assumes that the comment will end at
2845 the end of the line. */
2846 #define ASM_COMMENT_START "!"
2847
2848 #define ASM_APP_ON ""
2849 #define ASM_APP_OFF ""
2850 #define FILE_ASM_OP "\t.file\n"
2851 #define SET_ASM_OP "\t.set\t"
2852
2853 /* How to change between sections. */
2854
2855 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2856 #define DATA_SECTION_ASM_OP "\t.data"
2857
2858 #if defined CRT_BEGIN || defined CRT_END
2859 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2860 # undef TEXT_SECTION_ASM_OP
2861 # if __SHMEDIA__ == 1 && __SH5__ == 32
2862 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2863 # else
2864 # define TEXT_SECTION_ASM_OP "\t.text"
2865 # endif
2866 #endif
2867
2868
2869 /* If defined, a C expression whose value is a string containing the
2870 assembler operation to identify the following data as
2871 uninitialized global data. If not defined, and neither
2872 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2873 uninitialized global data will be output in the data section if
2874 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2875 used. */
2876 #ifndef BSS_SECTION_ASM_OP
2877 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2878 #endif
2879
2880 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2881 separate, explicit argument. If you define this macro, it is used
2882 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2883 handling the required alignment of the variable. The alignment is
2884 specified as the number of bits.
2885
2886 Try to use function `asm_output_aligned_bss' defined in file
2887 `varasm.c' when defining this macro. */
2888 #ifndef ASM_OUTPUT_ALIGNED_BSS
2889 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2890 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2891 #endif
2892
2893 /* Define this so that jump tables go in same section as the current function,
2894 which could be text or it could be a user defined section. */
2895 #define JUMP_TABLES_IN_TEXT_SECTION 1
2896
2897 #undef DO_GLOBAL_CTORS_BODY
2898 #define DO_GLOBAL_CTORS_BODY \
2899 { \
2900 typedef void (*pfunc) (void); \
2901 extern pfunc __ctors[]; \
2902 extern pfunc __ctors_end[]; \
2903 pfunc *p; \
2904 for (p = __ctors_end; p > __ctors; ) \
2905 { \
2906 (*--p)(); \
2907 } \
2908 }
2909
2910 #undef DO_GLOBAL_DTORS_BODY
2911 #define DO_GLOBAL_DTORS_BODY \
2912 { \
2913 typedef void (*pfunc) (void); \
2914 extern pfunc __dtors[]; \
2915 extern pfunc __dtors_end[]; \
2916 pfunc *p; \
2917 for (p = __dtors; p < __dtors_end; p++) \
2918 { \
2919 (*p)(); \
2920 } \
2921 }
2922
2923 #define ASM_OUTPUT_REG_PUSH(file, v) \
2924 { \
2925 if (TARGET_SHMEDIA) \
2926 { \
2927 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2928 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2929 } \
2930 else \
2931 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2932 }
2933
2934 #define ASM_OUTPUT_REG_POP(file, v) \
2935 { \
2936 if (TARGET_SHMEDIA) \
2937 { \
2938 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2939 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2940 } \
2941 else \
2942 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2943 }
2944
2945 /* DBX register number for a given compiler register number. */
2946 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2947 to match gdb. */
2948 /* svr4.h undefines this macro, yet we really want to use the same numbers
2949 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2950 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2951 register exists, so we should return -1 for invalid register numbers. */
2952 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2953
2954 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2955 used to use the encodings 245..260, but that doesn't make sense:
2956 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2957 the FP registers stay the same when switching between compact and media
2958 mode. Hence, we also need to use the same dwarf frame columns.
2959 Likewise, we need to support unwind information for SHmedia registers
2960 even in compact code. */
2961 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2962 (IN_RANGE ((REGNO), \
2963 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2964 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2965 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2966 : ((int) (REGNO) >= FIRST_FP_REG \
2967 && ((int) (REGNO) \
2968 <= (FIRST_FP_REG + \
2969 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2970 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2971 + (TARGET_SH5 ? 77 : 25)) \
2972 : XD_REGISTER_P (REGNO) \
2973 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2974 : TARGET_REGISTER_P (REGNO) \
2975 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2976 : (REGNO) == PR_REG \
2977 ? (TARGET_SH5 ? 18 : 17) \
2978 : (REGNO) == PR_MEDIA_REG \
2979 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2980 : (REGNO) == GBR_REG \
2981 ? (TARGET_SH5 ? 238 : 18) \
2982 : (REGNO) == MACH_REG \
2983 ? (TARGET_SH5 ? 239 : 20) \
2984 : (REGNO) == MACL_REG \
2985 ? (TARGET_SH5 ? 240 : 21) \
2986 : (REGNO) == T_REG \
2987 ? (TARGET_SH5 ? 242 : 22) \
2988 : (REGNO) == FPUL_REG \
2989 ? (TARGET_SH5 ? 244 : 23) \
2990 : (REGNO) == FPSCR_REG \
2991 ? (TARGET_SH5 ? 243 : 24) \
2992 : (unsigned) -1)
2993
2994 /* This is how to output a reference to a symbol_ref. On SH5,
2995 references to non-code symbols must be preceded by `datalabel'. */
2996 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2997 do \
2998 { \
2999 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3000 fputs ("datalabel ", (FILE)); \
3001 assemble_name ((FILE), XSTR ((SYM), 0)); \
3002 } \
3003 while (0)
3004
3005 /* This is how to output an assembler line
3006 that says to advance the location counter
3007 to a multiple of 2**LOG bytes. */
3008
3009 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3010 if ((LOG) != 0) \
3011 fprintf ((FILE), "\t.align %d\n", (LOG))
3012
3013 /* Globalizing directive for a label. */
3014 #define GLOBAL_ASM_OP "\t.global\t"
3015
3016 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3017
3018 /* Output a relative address table. */
3019
3020 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3021 switch (GET_MODE (BODY)) \
3022 { \
3023 case SImode: \
3024 if (TARGET_SH5) \
3025 { \
3026 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3027 (VALUE), (REL)); \
3028 break; \
3029 } \
3030 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3031 break; \
3032 case HImode: \
3033 if (TARGET_SH5) \
3034 { \
3035 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3036 (VALUE), (REL)); \
3037 break; \
3038 } \
3039 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3040 break; \
3041 case QImode: \
3042 if (TARGET_SH5) \
3043 { \
3044 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3045 (VALUE), (REL)); \
3046 break; \
3047 } \
3048 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3049 break; \
3050 default: \
3051 break; \
3052 }
3053
3054 /* Output an absolute table element. */
3055
3056 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3057 if (! optimize || TARGET_BIGTABLE) \
3058 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3059 else \
3060 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3061
3062 \f
3063 /* A C statement to be executed just prior to the output of
3064 assembler code for INSN, to modify the extracted operands so
3065 they will be output differently.
3066
3067 Here the argument OPVEC is the vector containing the operands
3068 extracted from INSN, and NOPERANDS is the number of elements of
3069 the vector which contain meaningful data for this insn.
3070 The contents of this vector are what will be used to convert the insn
3071 template into assembler code, so you can change the assembler output
3072 by changing the contents of the vector. */
3073
3074 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3075 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3076
3077 /* Print operand X (an rtx) in assembler syntax to file FILE.
3078 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3079 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3080
3081 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3082
3083 /* Print a memory address as an operand to reference that memory location. */
3084
3085 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3086
3087 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3088 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3089 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
3090
3091 /* Recognize machine-specific patterns that may appear within
3092 constants. Used for PIC-specific UNSPECs. */
3093 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3094 do \
3095 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3096 { \
3097 switch (XINT ((X), 1)) \
3098 { \
3099 case UNSPEC_DATALABEL: \
3100 fputs ("datalabel ", (STREAM)); \
3101 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3102 break; \
3103 case UNSPEC_PIC: \
3104 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3105 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3106 break; \
3107 case UNSPEC_GOT: \
3108 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3109 fputs ("@GOT", (STREAM)); \
3110 break; \
3111 case UNSPEC_GOTOFF: \
3112 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3113 fputs ("@GOTOFF", (STREAM)); \
3114 break; \
3115 case UNSPEC_PLT: \
3116 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3117 fputs ("@PLT", (STREAM)); \
3118 break; \
3119 case UNSPEC_GOTPLT: \
3120 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3121 fputs ("@GOTPLT", (STREAM)); \
3122 break; \
3123 case UNSPEC_DTPOFF: \
3124 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3125 fputs ("@DTPOFF", (STREAM)); \
3126 break; \
3127 case UNSPEC_GOTTPOFF: \
3128 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3129 fputs ("@GOTTPOFF", (STREAM)); \
3130 break; \
3131 case UNSPEC_TPOFF: \
3132 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3133 fputs ("@TPOFF", (STREAM)); \
3134 break; \
3135 case UNSPEC_CALLER: \
3136 { \
3137 char name[32]; \
3138 /* LPCS stands for Label for PIC Call Site. */ \
3139 ASM_GENERATE_INTERNAL_LABEL \
3140 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3141 assemble_name ((STREAM), name); \
3142 } \
3143 break; \
3144 default: \
3145 goto FAIL; \
3146 } \
3147 break; \
3148 } \
3149 else \
3150 goto FAIL; \
3151 while (0)
3152
3153 \f
3154 extern struct rtx_def *sh_compare_op0;
3155 extern struct rtx_def *sh_compare_op1;
3156
3157 /* Which processor to schedule for. The elements of the enumeration must
3158 match exactly the cpu attribute in the sh.md file. */
3159
3160 enum processor_type {
3161 PROCESSOR_SH1,
3162 PROCESSOR_SH2,
3163 PROCESSOR_SH2E,
3164 PROCESSOR_SH2A,
3165 PROCESSOR_SH3,
3166 PROCESSOR_SH3E,
3167 PROCESSOR_SH4,
3168 PROCESSOR_SH4A,
3169 PROCESSOR_SH5
3170 };
3171
3172 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3173 extern enum processor_type sh_cpu;
3174
3175 extern int optimize; /* needed for gen_casesi. */
3176
3177 enum mdep_reorg_phase_e
3178 {
3179 SH_BEFORE_MDEP_REORG,
3180 SH_INSERT_USES_LABELS,
3181 SH_SHORTEN_BRANCHES0,
3182 SH_FIXUP_PCLOAD,
3183 SH_SHORTEN_BRANCHES1,
3184 SH_AFTER_MDEP_REORG
3185 };
3186
3187 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3188
3189 /* Handle Renesas compiler's pragmas. */
3190 #define REGISTER_TARGET_PRAGMAS() do { \
3191 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3192 c_register_pragma (0, "trapa", sh_pr_trapa); \
3193 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3194 } while (0)
3195
3196 extern tree sh_deferred_function_attributes;
3197 extern tree *sh_deferred_function_attributes_tail;
3198
3199 /* Set when processing a function with interrupt attribute. */
3200
3201 extern int current_function_interrupt;
3202
3203 \f
3204 /* Instructions with unfilled delay slots take up an
3205 extra two bytes for the nop in the delay slot.
3206 sh-dsp parallel processing insns are four bytes long. */
3207
3208 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3209 (LENGTH) += sh_insn_length_adjustment (X);
3210 \f
3211 /* Define this macro if it is advisable to hold scalars in registers
3212 in a wider mode than that declared by the program. In such cases,
3213 the value is constrained to be within the bounds of the declared
3214 type, but kept valid in the wider mode. The signedness of the
3215 extension may differ from that of the type.
3216
3217 Leaving the unsignedp unchanged gives better code than always setting it
3218 to 0. This is despite the fact that we have only signed char and short
3219 load instructions. */
3220 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3221 if (GET_MODE_CLASS (MODE) == MODE_INT \
3222 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3223 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3224 (MODE) = (TARGET_SH1 ? SImode \
3225 : TARGET_SHMEDIA32 ? SImode : DImode);
3226
3227 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3228
3229 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3230
3231 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3232 and popping arguments. However, we do have push/pop instructions, and
3233 rather limited offsets (4 bits) in load/store instructions, so it isn't
3234 clear if this would give better code. If implemented, should check for
3235 compatibility problems. */
3236
3237 #define SH_DYNAMIC_SHIFT_COST \
3238 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3239
3240
3241 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3242
3243 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3244
3245 #define ACTUAL_NORMAL_MODE(ENTITY) \
3246 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3247
3248 #define NORMAL_MODE(ENTITY) \
3249 (sh_cfun_interrupt_handler_p () \
3250 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3251 : ACTUAL_NORMAL_MODE (ENTITY))
3252
3253 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3254
3255 #define MODE_EXIT(ENTITY) \
3256 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3257
3258 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3259 && (REGNO) == FPSCR_REG)
3260
3261 #define MODE_NEEDED(ENTITY, INSN) \
3262 (recog_memoized (INSN) >= 0 \
3263 ? get_attr_fp_mode (INSN) \
3264 : FP_MODE_NONE)
3265
3266 #define MODE_AFTER(MODE, INSN) \
3267 (TARGET_HITACHI \
3268 && recog_memoized (INSN) >= 0 \
3269 && get_attr_fp_set (INSN) != FP_SET_NONE \
3270 ? (int) get_attr_fp_set (INSN) \
3271 : (MODE))
3272
3273 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3274 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3275
3276 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3277 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3278
3279 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3280 sh_can_redirect_branch ((INSN), (SEQ))
3281
3282 #define DWARF_FRAME_RETURN_COLUMN \
3283 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3284
3285 #define EH_RETURN_DATA_REGNO(N) \
3286 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3287
3288 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3289 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3290
3291 /* We have to distinguish between code and data, so that we apply
3292 datalabel where and only where appropriate. Use sdataN for data. */
3293 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3294 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3295 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3296 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3297
3298 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3299 indirect are handled automatically. */
3300 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3301 do { \
3302 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3303 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3304 { \
3305 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3306 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3307 if (0) goto DONE; \
3308 } \
3309 } while (0)
3310
3311 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3312 /* SH constant pool breaks the devices in crtstuff.c to control section
3313 in where code resides. We have to write it as asm code. */
3314 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3315 asm (SECTION_OP "\n\
3316 mov.l 1f,r1\n\
3317 mova 2f,r0\n\
3318 braf r1\n\
3319 lds r0,pr\n\
3320 0: .p2align 2\n\
3321 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3322 2:\n" TEXT_SECTION_ASM_OP);
3323 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3324
3325 /* FIXME: middle-end support for highpart optimizations is missing. */
3326 #define high_life_started reload_in_progress
3327
3328 #endif /* ! GCC_SH_H */
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